since electric conduction does not occur directly between the laminated graphene sheets , when a via or a contact plug is connected to an upper or lower surface of a wiring as in a conventional cu wiring , only an uppermost or lowermost graphene sheet is connected to the via or the contact plug . in this case , graphene sheets other than the uppermost or lowermost graphene sheet cannot be used as a current path , in addition to this , when , for example , two vias are connected to the upper and lower surfaces of the wiring , it is not possible to flow current between the two vias . fig1 a is a vertical cross sectional view of a semiconductor device 100 according to a first embodiment . fig1 b is a horizontal cross sectional view of the semiconductor device 100 taken along line a - a of fig1 a . the semiconductor device 100 has an insulating film 10 a formed above a non - illustrated semiconductor substrate , an interlayer insulating film 11 a on the insulating film 10 a , an interlayer insulating film 11 b on the interlayer insulating film 11 a , an insulating film 10 b on the interlayer insulating film 11 b , a lower wiring 12 in the interlayer insulating film 11 a , an upper wiring 13 in the interlayer insulating film 11 b , and a via 14 for electrically connecting the lower wiring 12 to the upper wiring 13 . the lower wiring 12 is composed of a catalyst layer 120 and a gnr ( graphene nano ribbon ) layer 121 thereon . meanwhile , the upper wiring 13 is composed of a catalyst layer 130 and a gnr layer 131 thereon . the catalyst layers 120 and 130 are made of catalyst material which functions as a catalyst for growing graphene composing the gnr layers 121 and 131 . as a catalyst material , for example , co , ni , ru , fe or a compound containing these metals is used . the gnr layers 121 and 131 are composed of one to several tens of gnr sheets which are grown by using the catalyst layers 120 and 130 as a catalyst , and have ballistic conduction properties . in the gnr layers 121 and 131 , the ballistic conduction occurs independently in each gnr sheet and plural current paths are formed in parallel . here , the gnr sheet is a single graphene sheet which is processed so as to have a fine line width . the layer number of the gnr sheets is preferably 10 layers or less so that the gnr layers 121 and 131 have higher conduction properties , and using fewer layers is especially preferable . when the layer number of the gnr sheets is greater than 10 layers , the characteristics of the gnr layers 121 and 131 come close to that of graphite and there is a possibility that the conduction properties deteriorate . it is known that a mean free path of electron in the graphene is about 100 nm - 1 μm , and it is further longer compared with a mean free path of electron in cu ( about 40 nm ) which is a low resistance metal material currently used for various lsi devices . the graphene has quantum conduction properties and is more advantageous for long - distance electric conduction . in a conventional metal wiring , influence of electron scattering effect at an interface between a wiring and an insulating film becomes remarkable as miniaturization of the wiring proceeds , and a resistance increase due to interface electron scattering is not avoidable . in contrast , the resistance increase due to interface scattering is less in the graphene due to the quantum conduction . therefore , it is possible to lower the resistance of the wiring by using a graphene layer for a wiring material . since the lower wiring 12 and the upper wiring 13 have a narrow line width and low electrical resistance , they are suitable for an ultrafine wiring structure . the via 14 is made of , e . g ., metal such as w , cu or al . a barrier metal 15 is made of , e . g ., metal such as ta , ti , ru , mn , co , or nitride containing these metals . in addition , the barrier metal 15 has a function of preventing diffusion of metal contained in the via 14 to the outside . fig2 is a partial enlarged view of a periphery of the gnr layer 121 of fig1 a . in the example shown in fig2 , the gnr layer 121 is composed of four gnr sheets 122 . in addition , although it is not shown in the figures , the gnr layer 131 also has the same structure as the gnr layer 121 . the via 14 and the barrier metal 15 penetrate the gnr layer 131 and the catalyst layer 130 of the upper wiring 13 as well as at least one gnr sheet 122 of the gnr layer 121 of the lower wiring 12 , and are connected to a gnr sheet of the gnr layer 131 and at least two gnr sheets 122 . as shown in fig2 , it is preferable that a carbide layer 150 is formed at an interface between the gnr layer 121 and the barrier metal 15 by a reaction of the gnr layer 121 with the barrier metal 15 , and the laminated gnr sheets 122 of the gnr layer 121 are electrically connected each other via the carbide layer 150 . as a result , it is possible to further reduce the electrical resistance at a connecting portion of the gnr layer 121 with the via 14 ( the barrier metal 15 ). for example , when the barrier metal 15 is made of ti , the carbide layer 150 is made of tic . note that , it is preferable that the same structure is also formed at a connecting portion of the gnr layer 131 with the via 14 ( the barrier metal 15 ). alternatively , as shown in fig2 , the catalyst layer 120 may have a multilayer structure composed of a base layer 120 c , a co - catalyst layer 120 b and a surface layer 120 a . the surface layer 120 a is made of co , ni , ru or fe , etc ., and functions as a catalyst for growing the gnr sheet 122 . the co - catalyst layer 120 b is made of ti , etc ., and functions as a co - catalyst of the surface layer 120 a . alternatively , the co - catalyst layer 120 b may be an ultrathin layer composed of ti fine particle . the base layer 120 c is made of tan , tin , run , wn , ta , ti , ru or w , etc ., and has a function of preventing diffusion of metal contained in the surface layer 120 a . the insulating films 10 a and 10 b are made of insulating material such as sin . meanwhile , the interlayer insulating films 11 a and 11 b are preferably made of low dielectric constant insulating material such as sioc - based insulating material . an example of a method of fabricating the semiconductor device 100 according to the present embodiment will be described hereinafter . fig3 a to 3g are cross sectional views showing processes for fabricating the semiconductor device 100 according to the first embodiment . firstly , as shown in fig3 a , a catalyst film 101 which is a material film of the catalyst layer 120 and a graphene film 102 which is a material film of the gnr layer 121 are formed on the insulating film 10 a the catalyst film 101 is formed by cvd ( chemical vapor deposition ) or pvd ( physical vapor deposition ), etc . a specific example of a method of forming the graphene film 102 will be described below . firstly , plasma treatment is performed for suppressing microparticulation of the catalyst film 101 due to agglomeration thereof . by preventing the microparticulation of the catalyst film 101 and maintaining continuity of the surface thereof , it is possible to promote uniform growth of graphene . although a hydrogen gas or a noble gas is preferable as a discharge gas used for the plasma treatment , a mixture gas containing both of them may be used . the effect is higher at as low treatment temperature as possible , and it is desirable to perform at a room temperature . in addition , it is preferable that the plasma is relatively strong , and the effect is further increased when exposed to high power remote plasma or plasma . next , the catalyst film 101 is carbonized . a hydrocarbon - based gas such as methane or acetylene , or a mixture gas thereof is used as a discharge gas . in addition , a hydrogen gas or a noble gas , etc ., is used for a carrier gas . it is necessary to perform this treatment at a temperature lower than the treatment temperature during the below - described graphene formation as well as at a temperature that a graphite film can be formed , and about 150 - 600 ° c . is preferable . in addition , the treatment time may be short . this treatment is also preferably performed using relatively strong plasma . next , the plasma treatment is performed for improving the quality of a carbonized layer of the catalyst film 101 and for activating the catalyst . it is preferable to use a noble gas for a discharge gas . the treatment temperature may be about intermediate between the treatment temperature for carbonizing the catalyst film 101 and that during the below - described graphene formation . the plasma used for this treatment may be relatively weak , and it is preferable to use remote plasma . at the end , graphene is formed . a hydrocarbon - based gas or a mixture gas thereof is used as a discharge gas . the treatment temperature is about 200 - 1000 ° c ., and about 350 ° c . is especially preferable . in case of below 200 ° c ., a sufficient growth rate is not obtained and graphene growth hardly occurs . under the temperature of 200 ° c . or more , the graphene growth occurs and a uniform graphene film is formed . this treatment temperature is equivalent to or less than that in a typical wiring formation process of a lsi device , and this graphene formation process is excellent in affinity to a semiconductor process . in this treatment , since it is important to remove ions as well as electrons and to supply only radicals on the catalyst film 101 , very weak remote plasma is desirably used . applying voltage to a substrate by providing an electrode on an upper portion of the substrate is also effective in order to further remove ions and electrons . the applied voltage is preferably about 0 to ± 100v . the graphene film 102 is obtained by the above - mentioned multistep treatment . it is possible to form the graphene film 102 by the treatment using the cvd method under the single condition using a hydrocarbon - based gas as a carbon source , however , it is possible to form a low resistance graphene film 102 further excellent in uniformity under the low temperature condition by using the multistep treatment as described above . next , as shown in fig3 b , the catalyst film 101 and the graphene film 102 are patterned by a combination of photolithography and rie ( reactive ion etching ), thereby shaped into the catalyst layer 120 and the gnr layer 121 . as a result , the lower wiring 12 is obtained . note that , it is preferable that a termination process is performed on a side portion of the gnr layer 121 exposed by the patterning after the formation of the gnr layer 121 . here , the termination process means treatment for terminating dangling bond not having bondings at an end portion of the graphene , such as hydrogen sintering , silylation treatment or hydrophobizing treatment by hdms . for example , when the silylation treatment is performed , it is possible to terminate the dangling bond by bonding hydrogen thereto , and when the silylation treatment or the hydrophobizing treatment by hdms is performed , it is possible to terminate the dangling bond by bonding silicon - methyl group , etc ., thereto . when the dangling bond remains without being terminated , electron scattering is likely to occur at an end surface of the graphene and there is a possibility to adversely affect electron conduction properties in the graphene layer . in addition , in a state that the dangling bond remains , unintentional bonding may be formed at a graphene edge , and there is a possibility to adversely affect the electron conduction properties in the graphene in this case as well . next , as shown in fig3 c , the interlayer insulating film 11 a is formed . the interlayer insulating film 11 a is formed by cvd , etc ., so as to cover the lower wiring 12 , and is subsequently planarized by planarization treatment such as cmp ( chemical mechanical polishing ). next , as shown in fig3 d , the upper wiring 13 and the interlayer insulating film 11 b are formed on the interlayer insulating film 11 a . the upper wiring 13 and the interlayer insulating film 11 b are respectively formed by the same methods as used to form the lower wiring 12 and the interlayer insulating film 11 a . next , as shown in fig3 e , a via hole 103 is formed in the interlayer insulating film 11 b , the gnr layer 131 , the catalyst layer 130 , the interlayer insulating film 11 a and the gnr layer 121 by a combination of photolithography and rie , etc . since materials of the catalyst layer 120 and the gnr layer 121 can be selected so that the catalyst layer 120 has a sufficient etching selectivity with respect to the gnr layer 121 , it is possible to form the via hole 103 using a catalyst layer 120 as an etching stopper . a fluorine - based gas , etc ., is used as a gas for etching the interlayer insulating films 11 a and 11 b . meanwhile , an oxygen - based gas , etc ., is used as a gas for etching the gnr layers 121 and 131 . in addition , a cl ( chlorine )- based gas , etc ., is used as a gas for etching the catalyst layer 120 and 130 . next , as shown in fig3 f , a metal film 104 which is a material film of the barrier metal 15 and a metal film 105 which is a material film of the via 14 are formed by cvd , etc ., so as to fill the via hole 103 . next , as shown in fig3 g , the metal films 104 and 105 outside of the via hole 103 are removed by the planarization treatment such as cmp , thereby respectively shaping into the barrier metal 15 and the via 14 . subsequently , the insulating film 10 b is formed on the interlayer insulating film 11 b by cvd , etc . as a result , the semiconductor device 100 shown in fig1 a and 1b is obtained . according to the first embodiment , since the lower wiring 12 and the upper wiring 13 include the gnr layers 121 and 131 , it is possible to reduce the electrical resistance by using the ballistic conductivity of the graphene . in addition , since the via 14 ( the barrier metal 15 ) is directly connected to each of the laminated graphene nanoribbon sheets of the gnr layers 121 and 131 , it is possible to allow each graphene nanoribbon sheet to function as a current path in the wiring without increasing the complexity of the connecting portion of the lower wiring 12 with the via 14 and that of the upper wiring 13 with the via 14 . thus , it is possible to reduce the electrical resistance by accurately connecting the lower wiring 12 to the via 14 and the upper wiring 13 to the via 14 , and to reduce the fabrication steps of the wiring structure . note that , the configurations of the wiring and the wiring connecting member are not limited to those composed of the lower wiring 12 , the upper wiring 13 , the via 14 and the barrier metal 15 shown in the present embodiment . for example , a contact plug connecting a wiring to an element therebelow and a barrier metal on a surface of the contact plug may be used as a wiring connecting member . in this case , structures of a connecting portion of the wiring with the contact plug and the barrier metal are the same as the structures of the connecting portion of the upper wiring 13 with the via 14 and the barrier metal 15 in the present embodiment . the second embodiment is different from the first embodiment in that the wiring has plural laminated gnr layers . note that , the explanation will be omitted or simplified for the same points as the first embodiment . fig4 is a vertical cross sectional view of a semiconductor device 200 according to a second embodiment . the semiconductor device 200 has an insulating film 10 a formed above a non - illustrated semiconductor substrate , an interlayer insulating film 11 a on the insulating film 10 a , an interlayer insulating film 11 b on the interlayer insulating film 11 a , an insulating film 10 b on the interlayer insulating film 11 b , a lower wiring 22 in the interlayer insulating film 11 a , an upper wiring 23 in the interlayer insulating film 11 b , and a via 14 for electrically connecting the lower wiring 22 to the upper wiring 23 . the lower wiring 22 has a structure in which two pairs of catalyst layer and gnr layer , which are composed of catalyst layers 220 a , 220 b and gnr layers 221 a and 221 b , are laminated . alternatively , the lower wiring 22 may have a structure in which three or more pairs of catalyst layer and gnr layer are laminated . the upper wiring 23 has a structure in which two pairs of catalyst layer and gnr layer , which are composed of catalyst layers 230 a , 230 b and gnr layers 231 a and 231 b , are laminated . alternatively , the upper wiring 23 may have a structure in which three or more pairs of catalyst layer and gnr layer are laminated . the catalyst layers 220 a , 220 b , 230 a and 230 b have the same characteristics as the catalyst layers 120 and 130 in the first embodiment , and are formed by the same method . meanwhile , the gnr layers 221 a , 221 b , 231 a and 231 b have the same characteristics as the gnr layers 121 and 131 in the first embodiment , and are formed by the same method . similarly to the gnr layers 121 and 131 in the first embodiment , the gnr layers 221 a , 221 b , 231 a and 231 b are preferably composed of 10 layers or less of gnr sheets . therefore , although improvement in the conduction properties is not expected even if the layer number of the gnr sheets in one gnr layer is increased , it is possible to improve the conduction properties of the wiring by forming laminated plural pairs of catalyst layer and gnr layer , as is in the present embodiment . according to the second embodiment , since the lower wiring 22 has a structure in which two pairs of catalyst layer and gnr layer , which are composed of the catalyst layers 220 a , 220 b and the gnr layers 221 a and 221 b , are laminated , it is possible to further improve the conduction properties of the lower wiring 22 . in addition , since the upper wiring 23 has a structure in which two pairs of catalyst layer and gnr layer , which are composed of the catalyst layers 230 a , 230 b and the gnr layers 231 a and 231 b , are laminated , it is possible to further improve the conduction properties of the upper wiring 23 . the third embodiment is different from the second embodiment in that plural upper wirings are connected to a lower wiring . note that , the explanation will be omitted or simplified for the same points as the second embodiment . fig5 is a vertical cross sectional view of a semiconductor device 300 according to a third embodiment . the semiconductor device 300 has an interlayer insulating film 31 a formed above a non - illustrated semiconductor substrate , an interlayer insulating film 31 b on the interlayer insulating film 31 a , an interlayer insulating film 31 c on the interlayer insulating film 31 b , an interlayer insulating film 31 d on the interlayer insulating film 31 c , an insulating film 10 b on the interlayer insulating film 31 d , a lower wiring 32 in the interlayer insulating film 31 b , upper wirings 33 a and 33 b in the interlayer insulating film 31 d , a via 34 a for electrically connecting the lower wiring 32 to the upper wiring 33 a , a via 34 b for electrically connecting the lower wiring 32 to the upper wiring 33 b , and a via 34 c for electrically connecting the lower wiring 32 to a conductive member therebelow . the lower wiring 32 has the same characteristics as the lower wiring 22 in the second embodiment . meanwhile , the upper wirings 33 a and 33 b have the same characteristics as the upper wiring 23 in the second embodiment . the vias 34 a , 34 b and 34 c are made of the same material as the via 14 in the first embodiment . meanwhile , barrier metals 35 a , 35 b and 35 c are made of the same material as the barrier metal 15 in the first embodiment . the via 34 a and the barrier metal 35 a penetrate gnr layers 331 a , 331 b and catalyst layers 330 a and 330 b of the upper wiring 33 a , and gnr layers 321 a , 321 b and catalyst layer 320 b of the lower wiring 32 . the via 34 b and the barrier metal 35 b penetrate gnr layers 331 c , 331 d and catalyst layers 330 c and 330 c of the upper wiring 33 b , and the gnr layers 321 b of the lower wiring 32 . the via 34 c and the barrier metal 35 c penetrate the gnr layers 321 a , 321 b and the catalyst layers 320 a and 320 b of the lower wiring 32 . when the via 34 a and the barrier metal 35 a as well as the via 34 b and the barrier metal 35 b both penetrate the gnr layers 321 a and 321 b , the presence of the via 34 b disturbs the ballistic conduction between the vias 34 c and 34 a . note that , when the semiconductor device 300 has an ultrafine wiring structure , since the gnr layers 321 a and 321 b made of graphene nanoribbon has a narrow line width , it is difficult to sufficiently reduce a diameter of the via 34 b with respect to the line width of the gnr layers 321 a and 321 b so as not to disturb the ballistic conduction . in the present embodiment , the via 34 a and the barrier metal 35 a are connected to the gnr layer 321 a of the lower wiring 32 but the via 34 b and the barrier metal 35 b are not connected thereto . thus , the ballistic conduction between the vias 34 c and 34 a is not disturbed in the gnr layer 321 a , and it is possible to set the resistance between the vias 34 c and 34 a lower similarly to the resistance between the vias 34 c and 34 b . note that , since the ballistic conduction occurs independently in each gnr sheet in the gnr layers 321 a and 321 b , if the height of the bottom surface of the via 34 a is lower than that of the via 34 b , a path in which the ballistic conduction is not disturbed is formed between the vias 34 c and 34 a . in other words , for example , the height of the bottom surface of the barrier metal 35 b may be between the heights of upper and lower surfaces of the gnr layer 321 a or between the heights of upper and lower surfaces of the gnr layer 321 b . however , since materials of the catalyst layer 320 b and the gnr layer 321 b can be selected so that the catalyst layer 320 b has a sufficient etching selectivity with respect to the gnr layer 321 b , it is easy to form a via hole for the via 34 b and the barrier metal 35 b using the catalyst layer 320 b as an etching stopper in the fabrication process . in this case , as shown in fig5 , the bottom surface of the barrier metal 35 b contacts with the gnr layer 321 b . in addition , even in the case that there is a pair or three or more pairs of catalyst layer and gnr layer which compose the lower wiring 32 , when the height of the bottom surface of the via 34 a is lower than that of the via 34 b , a path in which the ballistic conduction is not disturbed is formed between the vias 34 c and 34 a . in addition , when three or more vias which connect the lower wiring 32 to the upper conductive member are formed , it is possible to form a path in which the ballistic conduction is not disturbed between the via 34 c and each via by arranging the vias in order of lowering height of bottom surface from a position closer to the via 34 c . in addition , when the vias 34 a and 34 b are each connected to the lower conductive member instead of being connected to the upper wirings 33 a and 33 b , it is possible to form a path in which the ballistic conduction is not disturbed between the vias 34 c and 34 a and between the vias 34 c and 34 b by lowering the height of the upper surface of the via 34 b than that of the via 34 a ( by arranging the vias in order of heightening height of upper surface from a position closer to the via 34 c ). note that , also in case that the via 34 a connects the lower wiring 32 to the conductive member thereabove , the condition for forming a path in which the ballistic conduction is not disturbed between the vias 34 c and 34 a and between the vias 34 c and 34 b is the same . in summary , when the lower wiring 32 includes the gnr sheet connected to the vias 34 a , 34 b and 34 c and the gnr sheet connected to only the vias 34 a and 34 c , a path in which the ballistic conduction is not disturbed is formed between the vias 34 c and 34 a and between the vias 34 c and 34 b . the interlayer insulating films 31 a , 31 b , 31 c and 31 d are made of the same material as the interlayer insulating films 11 a and 11 b in the first embodiment . an example of a method of fabricating the semiconductor device 300 according to the present embodiment will be described hereinafter . fig6 a to 6g are cross sectional views showing processes for fabricating the semiconductor device 300 according to the third embodiment . firstly , as shown in fig6 a , the lower wiring 32 and the interlayer insulating film 31 b are formed on the interlayer insulating film 31 a . material films of the catalyst layers 320 a , 320 b and the gnr layers 321 a and 321 b are formed in the same manner as the catalyst film 101 and the graphene film 102 in the first embodiment , and are patterned , thereby forming the lower wiring 32 . the interlayer insulating film 31 b is formed by cvd , etc ., so as to cover the lower wiring 32 , and is subsequently planarized by the planarization treatment such as cmp . next , as shown in fig6 b , a via hole 301 is formed in the interlayer insulating film 31 b , the gnr layer 321 b , the catalyst layer 320 b , the gnr layer 321 a , the catalyst layer 320 a and the interlayer insulating film 31 a by a combination of photolithography and rie , etc . next , as shown in fig6 c , the barrier metal 35 c and the via 34 c are formed in the via hole 301 . the barrier metal 35 c and the via 34 c are formed by the same method as used to form the barrier metal 15 and the via 14 in the first embodiment . next , as shown in fig6 d , the interlayer insulating film 31 c is formed on the interlayer insulating film 31 b by cvd , etc . next , as shown in fig6 e , the upper wirings 33 a , 33 b and the interlayer insulating film 31 d are formed on the interlayer insulating film 31 c . a material film of the catalyst layers 330 a and 330 c , that of the gnr layers 331 a and 331 c , that of the catalyst layers 330 b and 330 d , and that of the gnr layers 331 b and 331 d are laminated and patterned , thereby forming the upper wirings 33 a and 33 b . the interlayer insulating film 31 d is formed by cvd , etc ., so as to cover the upper wirings 33 a and 33 b , and is subsequently planarized by the planarization treatment such as cmp . next , as shown in fig6 f , via holes 302 a and 302 b are formed by a combination of photolithography and rie , etc . the via hole 302 a is formed in the interlayer insulating film 31 d , the upper wiring 33 a , the interlayer insulating films 31 c , 31 b and the gnr layer 3213 , the catalyst layer 320 b and the gnr layer 321 a of the lower wiring 32 by etching using the catalyst layer 320 a as an etching stopper . thus , the catalyst layer 320 a is exposed on the bottom surface of the via hole 302 a . the via hole 302 b is formed in the interlayer insulating film 31 d , the upper wiring 33 b , the interlayer insulating films 31 c , 315 and the gnr layer 321 b of the lower wiring 32 by etching using the catalyst layer 320 b as an etching stopper . thus , the catalyst layer 320 b is exposed on the bottom surface of the via hole 302 b . next , as shown in fig6 g , the barrier metal 35 a and the via 34 a are formed in the via hole 302 a , and the barrier metal 35 b and the via 34 b are formed in the via hole 302 b . a material film of the barrier metals 35 a and 35 b and that of the vias 34 a and 34 b are formed in the via holes 302 a and 302 b , and the material films outside of the via holes 302 a and 302 b are substantially removed by the planarization treatment such as cmp , thereby forming the vias 34 a and 34 b and the barrier metals 35 a and 35 b . subsequently , the insulating film 10 b is formed on the interlayer insulating film 31 d by cvd , etc . as a result , the semiconductor device 300 shown in fig5 is obtained . according to the third embodiment , the lower wiring 32 includes the gnr sheet connected to the vias 34 a , 34 b and 34 c and the gnr sheet connected to only the vias 34 a and 34 c , and it is thereby possible to form a path in which the ballistic conduction is not disturbed between the vias 34 c and 34 a and between the vias 34 c and 34 b . it should be noted that the present invention is not intended to be limited to the above - mentioned first to third embodiments , and the various kinds of changes thereof can be implemented by those skilled in the art without departing from the gist of the invention . in addition , the constituent elements of the above - mentioned embodiments can be arbitrarily combined with each other without departing from the gist of the invention .