as shown in fig4 a preferred embodiment of the invention includes a reference stage 10 and a drive stage 12 . in reference stage 10 , transistors q5 , q1 , q2 and q6 are chained between voltage supplies vcc and vss . it is likely that vss is at zero potential . q5 is a p - channel transistors and q1 , q2 , and q6 are n - channel transistors . q1 and q2 are configured as forward - biased diodes by connecting gates and drains , together forming biasing means 11 , wherein the threshold voltage characteristics of q1 and q2 are exploited to prevent q3 and q4 in the drive stage from being on at the same time , thus reducing standby current . capacitors c1 and c2 couple the gates of q1 and q2 , respectively , to vss , or alternatively to vcc . c1 - c3 are coupled as shown to avoid circuit oscillation in the event no load is provided on vo . in all practicality , since the intent of vo is to be loaded , c1 - c3 are omittable . drive stage 12 consists of transistor chain q3 and q4 between vcc and vss . q3 is an n - channel transistor and q4 is a p - channel transistor . q3 and q4 are driven by nodes v1 and v2 , respectively , connected to reference stage 10 as shown in fig4 . feedback 14 and 14 &# 39 ; is provided directly from output node vo to the gates of q5 and q6 in reference stage 10 . for a basic understanding of the operation of this circuit , assume for sake of illustration that the threshold voltages for both n - channel and p - channel devices are approximately equal at about 1 v . further assume that all transistors are matched . further assume that vss is 0 v . a &# 34 ; correction &# 34 ; is when variations in a load driven by vo forces vo to deviate from its reference level , and the inventive circuit compensates by urging vo back to its correct level . a &# 34 ; response &# 34 ; is when vcc or vss undergo a transition to a new level , and the inventive circuit generates a corresponding new reference level on vo . in steady state , that is , with no recent transitions on vcc , vx stabilizes at a potential close to midway between vcc and vss , because q5 matches q6 and q1 matches q2 . v1 is vx + 1 v and v2 is vx - 1 v . vo stabilizes at a potential close to midway between vcc and vss . q5 and q6 operate in the linear region . for 4 v vcc , node v1 assumes a potential of 3 v , and v2 , 1 v . under these conditions , transistors q3 and q4 are barely off and output node vo is urged to an intermediate potential of about 2 v . if node vo is forced by its load higher than 2 v , say to 2 . 5 v , the difference between vo and v2 becomes 1 . 5 v , which is higher than the threshold voltage of q4 . q4 therefore turns on , pulling vo toward vss , until vo reaches 2 v and q4 turns off . q3 remains off . the correction is made quicker by feedback 14 and 14 &# 39 ; turning down q5 and turning up q6 , allowing q6 to pull biasing means 11 ( hence v1 and v2 ) down , further assisting q4 turn - on and q3 turn - off . similarly , if node vo is forced lower than 2 v , say to 1 . 5 v , the difference between vo and v1 becomes 1 . 5 v , which is higher than the threshold voltage of q3 . q3 turns on , pulling vo toward vcc , until vo reaches 2 v and q3 turns off . q4 remains off . the correction is made quicker by feedback 14 and 14 &# 39 ; turning up q5 and turning down q6 , allowing q5 to pull biasing means 11 ( hence v1 and v2 ) up , further assisting q3 turn - on and q4 turn - off . fig5 illustrates the quick response of vo and vx to vcc transitions , also showing prior art vo1 , vo3 , and vx3 responses for comparison . at time t0 , vcc is steady at 4 v . vo stabilizes at approximately 2 v as described above . at time t1 , vcc undergoes a positive transition , from 4 v to 6 v . the difference between vo and vcc approaches 4 v from 2 v , immediately turning up q5 via feedback 14 , which causes node v1 to rise , and v2 via biasing means 11 . rising node v1 turns on q3 . rising node v2 turns off q4 . vo is quickly pulled up to approximately 3 v at time t2 , and q3 and q4 equilibrate barely off again . note that v1 and v2 overshoot , represented by vx in fig5 for faster response , whereas vx3 ( prior art ) does not . time t3 shows the circuit &# 39 ; s response to a negative transition of vcc , from 6 v to 4 v . the difference between vo and vcc approaches 1 v from 3 v , immediately turning down q5 via feedback 14 , which allows q6 to pull down v2 , and v1 via biasing means 11 . falling node v2 turns on q4 . falling node v1 turns off q3 . vo is quickly pulled down to approximately 4 v at time t4 , and q3 and q4 equilibrate barely off again . this response is a little slower than for the positive transition . had the transition been on vss , the response would have been equivalent . note that v1 and v2 undershoot , represented by vx in fig5 for faster response , whereas vx3 ( prior art ) does not . in reality , n - channel and p - channel thresholds were about 0 . 8 v and 1 . 0 v , respectively . q1 was about 20 microns wide , and q2 - q6 were about 20 , 20 , 20 , 10 , and 10 microns wide , respectively . q5 and q6 were 40 and 45 microns long , respectively . c1 , c2 , and c3 were on the order of 100 ff . full positive response ( t1 to t2 ) was obtained in about 70 μs , and full negative response ( t3 to t4 ) was obtained in about 150 μs , for vcc transitions between 4 v and 6 v . compare this to about 200 μs and over 200 μs , respectively , for the circuit of fig3 . the preferred embodiment has a drive stage 12 standby current on the order of 1 μa when matched to a reference stage 10 which draws on the order of 20 μa . preferably , but not necessarily , q1 is matched to q3 , and q2 to q4 . the ratio of q1 and q2 sizes to q3 and q4 sizes determines how much standby current q3 and q4 use . q2 is shown as an n - channel fet gated by vx . alternatively , q2 can be a p - channel fet gated by v2 , at the price of increased standby current due to typically greater p - channel threshold voltages than n - channel threshold voltages . n - channel q1 and q2 , because of lower n - channel threshold voltages , turn q3 and q4 on less hard , cutting standby power of the inventive circuit by roughly half . biasing means other than q1 and q2 as described may be utilized without escaping the claims below . clearly , other modifications may be made to the inventive circuit without escaping circumscription by the claims below .