in the following description , for the purposes of explanation , numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments . it should be apparent , however , that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement . in other instances , well - known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments . in addition , unless otherwise indicated , all numbers expressing quantities , ratios , and numerical properties of ingredients , reaction conditions , and so forth used in the specification and claims are to be understood as being modified in all instances by the term “ about .” aspects , features , and technical effects will be readily apparent to those skilled in this art from the following detailed description , wherein preferred embodiments are shown and described , simply by way of illustration of the best mode contemplated . the disclosure is capable of other and different embodiments , and its several details are capable of modifications in various obvious respects . accordingly , the drawings and description are to be regarded as illustrative in nature , and not as restrictive . fig2 is a graphic representation of snap - back holding voltage ( vh ) and snap - back holding current ( ih ) of a snap - back esd clamp . once conducting current , the clamp will exhibit “ snap - back ” or negative resistance characteristics due to its structure . during normal operation , the esd device represents a high impedance to the circuit up to the esd device trigger voltage ( vt1 ). during an esd event , the trigger voltage will be exceeded and the esd device will begin to conduct and enter a low impedance state . this point is defined on the curve , shown in fig2 , by the snap - back holding voltage ( vh ) and snap - back holding current ( ih ). to return to a non - conducting state , the current through the device must fall below a snap - back holding current ( ih ) and the voltage must fall below a snap - back holding voltage ( vh ), for the esd device to be immune to static and transient latch - up , its snap - back holding voltage must be within an esd protection window , as illustrated in fig3 . the esd protection window is a voltage range dependent upon the core device breakdown voltage ( vbd ), i . e ., the voltage at which the device trigger voltage ( vt 1 ) causes core failure . vt 1 as can be seen , if the trigger voltage vt 1 exceeds the core breakdown voltage vbd , the snap - back holding voltage vh falls below the supply rail voltage protection window , causing protection failure . static latch - up is an event that occurs when the clamp device becomes conductive due to lower snap - back holding voltage of the clamp device or fluctuation of the supply voltage rail ( vdd ). transient latch - up is an event that occurs when the clamp device becomes conductive as a result of spikes , noise , or a start - up transient on the supply rail . fig4 is a circuit diagram of one embodiment of the esd clamp of the present disclosure . connected in series across supply terminals vdd and vss are capacitor 16 and resistor 14 . one terminal of nmosfet 18 is connected to vdd . the gate of nmosfet 18 is coupled to vss via body resistance 20 . the other terminal of nmosfet 18 is connected to vss via external resistor 20 . operation of the circuit of fig4 is described with reference to fig5 . under normal operating conditions , i . e ., in the absence of an electrostatic event , node n 1 = vdd , node n 2 = 0v , node n 3 = vdd , and node n 4 = 0v . as a result , mnesd 18 will not be conducting . during an electrostatic discharge event , node n 1 = 0v , node n 2 = vdd , node n 3 = 0v , and node n 4 = vdd . mnesd 18 is thus rendered conductive . esd current from vdd will bypass the protected circuit through a first path , shown as a channel , and then bypass through the b channel , parasitic bipolar mode , to vss . with the addition of external resistor 22 , the trigger voltage vt 1 , or snapback trigger voltage , will increase to twice the value it would otherwise obtain . the snapback action can thus be delayed to improve esd performance . fig6 is a modification of the embodiment described with respect to fig4 and 5 . switch 30 is connected between node n 2 , the output of diode 24 , and node n 5 , the junction between mnesd 18 and external resistor 22 . during normal operation , switch 30 will be closed . during an electrostatic discharge event , switch 30 will be open , and the circuit will operate as described above with respect to fig4 and 5 . operation of switch 30 can be implemented , for example , as illustrated in fig7 . as illustrated , switch 30 may comprise a latch having control inputs connected , respectively to nodes n 2 and n 3 . under normal conditions , switch 30 is on . node n 2 = 0v , n 3 = vdd , and n 5 = 0v . as there is no voltage difference across resistor 22 , there will not be body resistance introduced therefrom . under an electrostatic discharge event , switch 30 will be off . node n 2 = vdd , node n 3 = 0v and node n 4 = vdd . mnesd 18 is thus rendered conductive . esd current from vdd will bypass the protected circuit through a first path , shown as a channel , and then bypass through the b channel , parasitic bipolar mode , to vss . with the addition of external resistor 22 , the trigger voltage vt 1 , or snapback trigger voltage , will increase to twice the value it would otherwise obtain . the snapback action can thus be delayed to improve esd performance . in this disclosure there are shown and described only preferred embodiments of the invention and but a few examples of its versatility . it is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein . for example , other circuits can be used in lieu of the latch shown in fig7 to provide the described switch operation . further , the concepts disclosed herein are also applicable for use in pmos circuit arrangements . the embodiments of the present disclosure can achieve several technical effects , such as an efficient esd robust , latch - up free , compact sized whole chip esd protection in high voltage based products such as lcd drivers and power management . embodiments of the present disclosure enjoy utility in various industrial applications as , for example , microprocessors , smart phones , mobile phones , cellular handsets , set - top boxes , dvd recorders and players , automotive navigation , printers and peripherals , networking and telecom equipment , gaming systems , and digital cameras . the present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices , including , for instance , devices that benefits from reliable esd protection schemes that utilize less chip area . in the preceding description , the present disclosure is described with reference to specifically exemplary embodiments thereof . it will , however , be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure , as set forth in the claims . the specification and drawings are , accordingly , to be regarded as illustrative and not as restrictive . it is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein .