the present invention will now be described more fully hereinafter with reference to the accompanying drawings , in which preferred embodiments of the invention are shown . the invention may , however , be embodied in different forms and should not be construed as limited to the embodiments set forth herein . rather , these embodiments are provided so that this disclosure will be thorough and complete , and will fully convey the scope of the invention to those skilled in the art . in the drawings , the thickness of layers and regions are exaggerated for clarity . it will also be understood that when a layer is referred to as being “ on ” another layer or substrate , it can be directly on the other layer or substrate , or intervening layers may also be present . like numbers refer to like elements throughout . a phase - changeable memory device according to some embodiments of the present invention includes a phase - changeable material region with two active contact areas that are disposed on the same plane . that is , the active contact areas exist at opposing sidewalls of a phase - changeable material region . on the same plane as the phase - changeable material layer , conductive patterns are in contact with the phase - changeable material region at the active contact areas . the conductive patterns serve as a current path that supplies predetermined currents to the sidewalls of the phase - changeable material region . the phase - changeable material region is interposed between the symmetrical pair of conductive patterns on the same plane . accordingly , currents in the phase - changeable material region flow in a lateral ( horizontal ) direction . fig3 a is a cross - sectional view of a phase - changeable memory device according to some embodiments of the present invention . fig3 b is a top plan view of the phase - changeable memory device of fig3 a , taken along a line i - i ′. fig3 c is a perspective view of the phase - changeable memory device of fig3 a and 3b . referring to fig3 a through 3c , the phase - changeable memory device includes a pair of conductive patterns 260 a and 260 b and a phase - changeable material pattern 300 a . the pair of conductive patterns 260 a and 260 b are disposed on opposite sides of the phase - changeable material pattern 300 a on the same plane , i . e ., on a lower insulating layer 250 . the pair of conductive patterns 260 a and 260 b are spaced apart from each other by a predetermined length l . the phase - changeable material pattern 300 a is interposed between the conductive patterns 260 a and 260 b , and is in direct contact with sidewalls of the conductive patterns 260 a and 260 b . one conductive pattern ( here , the conductive pattern 260 a ) is electrically connected to a first source / drain region , e . g ., an impurity diffusion region 140 , of a semiconductor substrate 100 . the other conductive pattern 260 b is electrically connected to a metal interconnection 360 ( e . g ., a bit line ). preferably , the conductive pattern 260 a is electrically connected to the impurity diffusion region 140 through a contact plug 240 passing through the lower insulating layer 250 . the other conductive pattern 260 b is electrically connected to the metal interconnection 360 through a contact plug 340 passing through an upper insulating layer 330 that is interposed between the conductive pattern 260 b and the metal interconnection 360 . the upper insulating layer 330 is interposed between the metal interconnection 360 and the conductive pattern 260 a and the phase - changeable material pattern 300 a . in the semiconductor substrate 100 , another source / drain region , e . g ., another impurity diffusion region 160 , is spaced apart from the impurity diffusion region 140 that is electrically connected to one conductive pattern 260 a . a gate electrode 120 is disposed on the semiconductor substrate 100 between the impurity diffusion regions 140 and 160 . the impurity diffusion regions 140 and 160 and the gate electrode 120 form an access transistor ta . the gate electrode 120 acts as a word line . a common drain electrode 200 is disposed in the lower insulating layer 250 so as to be electrically connected to the other impurity diffusion region 160 through a contact plug formed in the lower insulating layer 250 . the conductive patterns 260 a and 260 b are electrically isolated from the gate electrode 120 and the common drain electrode 200 by the upper insulating layer 250 . the conductive pattern 260 a includes a plug contact region , e . g ., a relatively large body portion 260 ac , and a material pattern contact region , e . g ., a relatively small tab portion 260 ai extending from the body portion . the plug contact region 260 ac is in contact with the contact plug 240 . the material pattern contact region 260 ai is in contact with the phase - changeable material pattern 300 a . the conductive pattern 260 b also includes a similar plug contact region 260 bc and a similar material pattern contact region 260 bi . the plug contact region 260 bc is in contact with the contact plug 340 . the material pattern contact region 260 bi is in contact with the phase - changeable material pattern 300 a . the material pattern contact regions 260 ai and 260 bi are extended from a middle portion of sidewalls of the plug contact regions 260 ac and 260 bc toward the phase - changeable material pattern 300 a . it is preferable that the width of the material pattern contact regions 260 ai and 260 bi are made as narrow as possible to the resolution of the photolithography . because the plug contact regions 260 ac and 260 bc are connected to the contact plugs 240 and 340 , the plug contact regions 260 ac and 260 bc are relatively larger than the material pattern contact regions 260 ai and 260 bi . the length l between the pair of conductive patterns ( i . e ., a size of y axis dimension of the phase - changeable material pattern 300 a ) depends on the photolithography resolution . the conductive patterns 260 a and 260 b are in contact with the phase - changeable material pattern 300 a at active contact areas 270 a and 270 b at opposite sidewalls of the phase - changeable material pattern 300 a . it is preferable that the active contact areas 270 a and 270 b be made as small as possible in order to reduce currents required to vary a crystallization state of phase - changeable material pattern 300 a . according to some embodiments of the present invention , the dimensions of the active contact areas 270 a and 270 b is dependent upon a thickness t ( i . e ., a z axis dimension ) of the conductive patterns 260 a and 260 b and a width w of the conductive patterns 260 a and 260 b ( i . e ., the material pattern contact regions 260 ai and 260 bi ). the width w of the conductive patterns 260 a and 260 b may be limited to the photolithography resolution . because the thickness t of the conductive patterns generally is not limited by the photolithography resolution , the thickness t can be lower than the photolithography resolution . furthermore , the phase - changeable memory device includes two active contact areas 270 a and 270 b . therefore , although the same currents ( i . e ., joule heat ) are used , a resistivity variation can be doubled . program and read operations of the phase - changeable memory device will now be described . fig4 is an equivalent circuit of the phase - changeable memory device of fig3 a - 3c . referring to fig3 a - 3c and 4 , the bit line bl ( i . e ., the metal interconnection 360 ) is grounded and a turn on voltage is applied to the word line wl ( i . e ., the gate electrode 120 ). predetermined current flows are applied to the common drain electrode cdl ( 200 in fig3 a - 3 c ). accordingly , a current path is formed between the common drain electrode cdl and the bit line bl . the crystallization state of the active contact areas 270 a and 270 b of the phase - changeable material pattern rc is changed by joule heat ( joule energy ) of the current flow . the amount of current applied to the common drain electrode cdl is adjusted , so that heat ( energy ) applied to the active contact area is determined . thus , phase - changeable materials have a crystalline state or an amorphous state depending on current flow . for example , if a temperature of 650 ° c . is applied during very short time to the active contact areas , the phase - changeable materials of the active contact areas are transformed into the amorphous state . if a temperature of 400 ° c . is applied for a relatively long time to the active contact areas , the phase - changeable materials of the active contact areas are transformed into the crystalline state . alternatively , the program operation can be performed by grounding the common drain electrode cdl , and applying predetermined current flows to the bit line bl . next , the read operation will be explained . the common drain electrode cdl is grounded , and a read voltage is applied to the bit line bl . the bit line bl detects resistivity ( i . e ., currents flowing through the phase - changeable material pattern ) of the phase - changeable material pattern rc . therefore , a logic value can be discriminated . fig5 a through 5g illustrate methods for forming a phase - changeable memory device as shown in fig5 g according to first embodiments of the present invention . referring to fig5 a , after a device isolation process is performed by a conventional method , an access transistor is formed on a semiconductor substrate 100 . the access transistor includes a source region 140 , a drain region 160 and a gate electrode 120 . a lower first oxide layer 190 is formed on the semiconductor substrate 100 having the access transistor . a common drain electrode 200 is formed on the lower first oxide layer 190 and is electrically connected to the drain region 160 of the access transistor . a lower second oxide layer 230 is formed on the common drain electrode 200 and the lower first oxide layer 190 . the lower first oxide layer 190 and the lower second oxide layer 230 form a lower insulating layer 250 . an intermediate conductive pattern 260 ′ is formed on the lower second oxide layer 230 and is electrically connected to the source region 140 of the access transistor . more particularly , the common drain electrode 200 is electrically connected to the drain region 160 by a contact plug 180 . the contact plug 180 penetrates the lower first oxide layer 190 and contacts the drain region 160 . a contact plug process includes forming a contact hole by a photolithographic process and depositing a conductive material in the contact hole . likewise , the intermediate conductive pattern 260 ′ is electrically connected to the source region 140 through contact plug 240 penetrating the lower insulating layer 250 . preferably , the contact plug 240 includes a first contact plug 180 ′, a conductive pad 200 ′, and a second contact plug 220 . the first contact plug 180 ′ is in contact with the source region 140 through the lower first oxide layer 190 . the conductive pad 200 ′ is formed on the lower first oxide layer 190 and is electrically connected to the first contact plug 180 ′. the second contact plug 220 is in contact with the conductive pad 200 ′ through the lower second oxide layer 230 . in this case , when the common drain electrode 200 is formed , the first contact plug 180 ′ and the conductive pad 200 ′ are formed simultaneously . after depositing the lower second oxide layer 230 , a contact hole is formed to expose the contact pad 200 ′, and then conductive material is deposited in the contact hole to form the second contact plug 220 . thereafter , a conductive layer is formed on the second contact plug 220 and the lower second oxide layer 230 . the conductive layer is patterned to form the intermediate conductive pattern 260 ′ that is electrically connected to the second contact plug 220 . the second contact plug 220 is made of sequentially stacked titanium ( ti ), titanium nitride ( tin ), and tungsten ( w ) layers . for example , the ti layer may have a thickness of 50 angstroms , the tin layer may have a thickness of 250 angstroms and the w layer may have a thickness of 2500 angstroms . the intermediate conductive pattern 260 ′ is made of tin with a thickness of 200 angstroms . preferably , the intermediate conductive pattern 260 ′ is formed as thin as possible , because the thickness of the intermediate conductive pattern 260 ′ is an important factor determining dimensions of an active contact area . accordingly the thickness of the intermediate conductive pattern 260 ′ can be made to size smaller than the photolithographic resolution . referring to fig5 b , an upper first oxide layer 280 is formed on the intermediate conductive pattern 260 ′ and the lower insulating layer 250 . for example , the upper first oxide layer 280 may have a thickness of about 5000 angstroms . referring to fig5 c , the upper first oxide layer 280 and the intermediate conductive pattern 260 ′ are etched by a photolithographic etching process . an opening 290 is formed to expose a portion of the lower first oxide layer 230 under a middle portion of the intermediate conductive pattern 260 ′. thus , the intermediate conductive pattern 260 ′ is divided into a pair of conductive patterns 260 a and 260 b , which are spaced apart from each other by the opening 290 . here , one conductive pattern 260 a is electrically connected to the second contact plug 220 , in particular , a bottom surface of the conductive pattern 260 a is in contact with the second contact plug 220 . the opening 290 exposes sidewalls 265 a and 265 b of the conductive patterns 260 a and 260 b . referring to fig5 d , a variable resistivity material layer 300 is formed to cover the patterned upper first oxide layer 280 ′, the exposed lower first oxide layer 230 and the exposed sidewalls 265 a and 265 b of the conductive patterns . the variable resistivity material layer 300 is a material whose crystalline state can be varied depending on temperature . the variable resistivity material layer 300 is made of a phase - changeable material layer , for example , a gst layer . the phase - changeable material layer 300 may have a thickness of about 200 angstroms . the variable resistor material layer 300 is contact with the sidewalls 265 a and 265 b of the conductive patterns 260 a and 260 b to define active contact areas 270 a and 270 b . referring to fig5 e , for electrical isolation between neighboring cells , the phase - changeable material layer 300 is etched by a photolithographic etching process to form the phase - changeable material pattern 300 a ( i . e ., a phase - changeable memory cell ). the phase - changeable material pattern 300 a is formed between the conductive patterns 260 a and 260 b , so that sidewalls thereof are in direct contact with the sidewalls 265 a and 265 b of the conductive patterns 260 a and 260 b at active contact areas 270 a and 270 a . referring to fig5 f , an upper second oxide layer 320 is formed on the surface of the semiconductor substrate where the phase - changeable material pattern 300 a is formed . the upper second oxide layer 320 and the upper first oxide layer 280 form an upper insulating layer 330 . referring to fig5 g , the upper insulating layer 330 is patterned to form a contact hole exposing the conductive pattern 260 b that is not in contact with the second contact plug 220 . next , a conductive material is deposited to form a contact plug 340 . the contact plug 340 may be formed using the same method used in forming the second contact plug 220 . a metal material is deposited on the contact plug 340 and the upper insulating layer 330 to be patterned . thereafter , a bit line 360 is formed . the bit line 360 is a metal interconnection electrically contacting with the contact plug 340 . for example , the bit line 360 may be formed of aluminum . fig6 a - 6e show methods of forming the phase - changeable memory device shown in fig6 e according to second embodiments of the present invention . in the above - described first embodiments , the phase - changeable material pattern 300 a is formed after the conductive patterns 260 a and 260 b are formed . however , in the second embodiments , the phase - changeable material pattern 300 a is formed before the conductive patterns 260 a and 260 b are formed . referring to fig6 a , the access transistor , the common drain electrode 200 , and the contact plug 240 are formed by the same method as the first embodiments . next , the phase - changeable material layer 300 is formed on the lower insulating layer 250 and the second contact plug 220 . the upper first oxide layer 280 is formed on the phase - changeable material layer 300 . referring to fig6 b , the upper first oxide layer 280 and the phase - changeable material layer 300 are successively patterned to form the phase - changeable material pattern 300 a ( i . e ., a phase - changeable memory cell ). the phase - changeable material pattern 300 a is spaced apart from the second contact plug 220 . referring to fig6 c , a conductive layer 260 is formed on the surface of the semiconductor substrate having the phase - changeable material pattern 300 a , i . e ., on the second contact plug 220 , the lower oxide layer 250 , the patterned upper first oxide layer 280 ′, and both sidewalls of the phase - changeable material pattern 300 a . the conductive layer is in contact with the phase - changeable material pattern 300 a to define the active contact areas 270 a and 270 b . referring to fig6 d , the conductive layer 260 is patterned to form a symmetrical pair of conductive patterns 260 a and 260 b . at this time , one conductive pattern 260 a is electrically connected to the second contact plug 220 . that is , a bottom surface of the conductive pattern 260 a is in contact with the second contact plug 220 . referring to fig6 e , in a manner similar to that for the first embodiments , the upper second oxide layer 320 is formed . thereafter , the bit line 360 is formed to be electrically connected to the conductive pattern 260 b through the contact plug 340 . fig7 a through 7e show methods of forming the phase - changeable memory device as shown in fig7 e according to third embodiments of the present invention . in the above - described first embodiments , the conductive patterns 260 a and 260 b are formed after the intermediate conductive pattern 260 ′ is formed . in the third embodiments , the intermediate conductive pattern is not formed . referring to fig7 a , after the access transistor , the common drain electrode 200 , and the second contact plug 220 are formed by the same method as the first embodiments , the conductive layer 260 is formed on the lower second oxide layer 250 and the second contact plug 220 . the upper first oxide layer 280 is formed on the conductive layer 260 . referring to fig7 b , the upper first oxide layer 280 and the conductive layer 260 are patterned to form the spaced apart pair of conductive patterns 260 a and 260 b . the conductive pattern 260 a is electrically connected to the second contact plug 220 . the conductive patterns 260 a and 260 b are spaced apart from each other by the opening 290 , and the sidewalls 265 a and 265 b thereof are exposed . referring to fig7 c , the phase - changeable material layer 300 is formed on the surface of the semiconductor substrate having the conductive patterns 260 a and 260 b . at this time , the phase - changeable material layer 300 is in contact with the sidewalls 265 a and 265 b of the conductive patterns 260 a and 260 b , thus defining the active contact areas 270 a and 270 b . referring to fig7 d , the phase - changeable material layer 300 is patterned to be interposed between the pair of conductive patterns 260 a and 260 b . the phase - changeable material pattern 300 a is formed to be in direct contact with the sidewalls 265 a and 265 b of the conductive patterns 260 a and 260 b . referring to fig7 e , by using the same method as the first embodiments , the upper second oxide layer 320 is formed and the bit line 360 is formed . the bit line 360 is electrically connected to the conductive pattern 260 b through the contact plug 340 . according to some embodiments of the present invention , dimensions of active contact areas for phase - changeable memory materials may be reduced to decrease currents required during a program operation of a phase - changeable memory device . also , two active contact areas may be provided , so that a resistivity variation with respect to the same currents may be doubled as compared with a typical phase - changeable memory device . accordingly , a detection margin for read operations may increase and mis - operation may be reduced . furthermore , because the upper and lower electrodes ( i . e ., conductive patterns ) exist on the same plane , a height of a memory cell region can be decreased . therefore , it is possible to reduce a step difference between the cell region and a peripheral circuit region . in the drawings and specification , there have been disclosed typical preferred embodiments of the invention and , although specific terms are employed , they are used in a generic and descriptive sense only and not for purpose of limitation , the scope of the invention being set forth in the following claims .