the following detailed description , which references and incorporates fig1 - 8 , describes and illustrates specific embodiments of the invention . these embodiments , offered not to limit but only to exemplify and teach the concepts of the invention , are shown and described in sufficient detail to enable those skilled in the art to implement or practice the invention . thus , where appropriate to avoid obscuring the invention , the description may omit certain information known to those of skill in the art . fig1 - 7 show a number of cross - sectional views of a partial integrated - circuits assembly 100 , which taken collectively and sequentially , illustrate a unique exemplary method of making integrated circuits , and more particularly making integrated - circuit wiring in accord with teachings of the present invention . the method , as shown in fig1 , begins with a known integrated - circuit assembly or structure 100 , which can exist within any integrated circuit , a dynamic - random - access memory , for example . assembly 100 includes a substrate 212 . the term “ substrate ,” as used herein , encompasses a semiconductor wafer as well as structures having one or more insulative , conductive , or semiconductive layers and materials . thus , for example , the term embraces silicon - on - insulator , silicon - on - sapphire , and other advanced structures . substrate 212 supports a number of integrated elements 214 , for example transistors 214 a and 214 b . transistors 214 a and 214 b are covered by a mask layer 216 , which , for example , comprises photoresist . in the exemplary embodiment , the transistors are metal - oxide - semiconductor field - effect transistors ( mosfets ); however , in other embodiments , the transistors are other types of field - effect transistors or bipolar junction transistors , or mixed transistor types . still other embodiments use other types of integrated devices . layer 216 includes two exemplary via holes 216 a and 216 b positioned over respective contact regions ( not shown ) of transistors 214 a and 214 b and a trench 216 c connecting the via holes . the exemplary embodiment forms layer 216 from photoresist , through use of spincoating , lithography , and photoresist remover . some embodiments use plasma ashing to pattern the photoresist . also , in the exemplary embodiment , via holes 216 a and 216 b are cylindrical with diameters of about 1000 nanometers and depths of about 500 nanometers . trench 216 c is less than 0 . 50 microns wide and at least one micron deep . the invention , however , is not limited to any particular mask material , formation technique , geometry , or dimensions . fig2 shows that the exemplary method next forms a conductive structure 218 on mask 216 , with one or more portions of the conductive structure contacting one or more exposed portions of the transistors . in the exemplary embodiment , this entails depositing a 20 - 30 - nanometer - thick copper -, silver -, or gold - based seed layer ( not shown separately ) using a chemical - vapor - deposition , ionized - magnetron sputtering technique , or dc magnetron self - sputtering technique , and then electroplating additional copper -, silver -, or gold - based material on the seed layer to a total thickness of , for example , 0 . 5 microns . ( as used herein , a copper -, silver -, or gold - based material includes at least 25 weight - percent of the base material .) an exemplary chemical - vapor - deposition technique follows a procedure such as that described in y . senzaki , “ chemical vapor deposition of copper using a new liquid precursor with improved thermal stability ,” mrs conference proceedings of advanced metallization and interconnect systems for ulsi applications in 1997 , ulsi xiii , p . 451 - 455 , 1998 , which is incorporated herein by reference . this procedure yields copper films at a typical deposition rate of 150 - 170 nanometers per minute at wafer temperatures of 195 - 225 ° c . the resistance of these films is in the range of 2 . 0 micro - ohm - centimeter after annealing at 400 ° c . for five minutes . exemplary ionized sputtering technique and d - c magnetron sputtering techniques follow procedures similar to those outlined in s . m . rossnagel et al ., metal ion deposition from ionized magnetron sputtering discharge ,” j . vac . sci . technology b , 12 ( 1 ), p . 449 - 453 , 1994 . and z . j . radzimski et al , “ directional copper deposition using d - c magnetron self - sputtering ,” j . vac . sci technology b 16 ( 3 ), p . 1102 - 1106 , 1998 . exemplary conditions for the ionized - magnetron sputtering operation are : target power range of 10 - 30 kilowatts for a 200 - 300 millimeter diameter wafer ( or integrated - circuit assembly ), rf coil power at 3 - 5 kilowatts , negative dc bias of 100 - 200 volts , sputtering argon gas pressurized at 1 - 35 millitorrs . ionized - magnetron sputtering , which provides greater acceleration of the metal deposition material than conventional sputtering , forces the sputtered material to more closely conform to the interior profiles of holes and trenches of the targeted surface . notably , the exemplary embodiment omits formation of an adhesion layer to promote adhesion of copper ( or other materials ) to the mask layer . some embodiments use a 20 - 50 nanometer - thick layer of titanium nitride ( tin ) over the transistor contacts as an adhesion layer and a diffusion barrier . however , other embodiments provide an adhesion layer of titanium nitride . after depositing the conductive material , the exemplary method removes excess material , for example , using a chemical - mechanical planarization or polishing procedure . next , as fig3 shows , the exemplary method forms a mask layer 220 over conductive structure 218 . mask layer 220 includes an opening ( via ) 220 a which exposes a portion of conductive structure 218 and a trench 220 b which intersects 20 opening 220 a . exemplary formation of conductive structure follows a procedure similar to that used to form mask layer 216 and occurs with at least a portion of mask layer 216 still in place . fig4 shows that the exemplary method next forms a conductive structure 222 on mask 216 , with portions of structure 222 contacting exposed portions of conductive structure 218 . in the exemplary embodiment , this entails depositing a 20 - 30 - nanometer - thick copper -, silver -, or gold - based seed layer and electroplating additional copper -, silver -, or gold - based material to an exemplary thickness of 0 . 5 microns . excess material is then removed using a chemical - mechanical planarization or polishing procedure . subsequently , one or more higher - level conductive structures can be formed similarly . fig5 shows that after forming conductive structure 222 , the method removes at least a portion of mask structures 216 and 220 , defining one or more spaces or voids 224 around conductive structures 218 and 222 . without the surrounding masks , conductive structures 218 and 222 appears as a two - level airbridge . the exemplary embodiment removes substantially all of the mask structures by ashing them in an oxygen plasma . after removal of the mask structures , the exemplary method forms a diffusion barrier 226 on at least portions of conductive structures 218 and 222 . in the exemplary embodiment , this entails growing or depositing a two - to - six nanometer - thick layer of wsin over substantially all of conductive structures 218 and 222 . exemplary formation of this layer of wsin occurs within a hybrid reaction chamber such as that described in co - filed and co - assigned patent application entitled methods and apparatus for making copper wiring in integrated circuits . this application , attorney docket 303 . 618us1 ( 99 - 0469 ), is incorporated herein by reference . more particularly , exemplary formation of diffusion barrier 226 entails forming a graded composition of tungsten silicide ( wsi x ), with x varying from 2 . 0 to 2 . 5 . this entails heating the assembly to a temperature of 360 ° c . and introducing hydrogen , tungsten hexafluoride , and silane gases into a process chamber enclosing the assembly . the exemplary embodiment introduces the hydrogen and tungsten hexaflouride gases about one - to - three seconds before introducing the silane gas and stops introducing the silane gas about one - to - three seconds before stopping introduction of the hydrogen and tungsten hexaflouride . exemplary flow rates for the silane and tungsten hexaflouride gases are respectively 1000 sccm and 14 sccm . these flow rates result in a composition of wsi 2 . 3 , with a growth rate of approximately 50 nanometers per minute . to complete the diffusion barrier , the exemplary method nitrides the graded composition of wsi x , forming wsi x n y . the exemplary nitridation follows an electron - cyclotron - resonance ( ecr ) plasma nitridation procedure . one version of this procedure is described in a . hirata et al ., wsin diffusion barrier formed by ecr plasma nitridation for copper damascene interconnection , extended abstracts of 1998 international conference on solid state devices and materials , p . 260 - 261 , which is incorporated herein by reference . this entails introducing nitrogen gas and argon gas into the chamber , with the argon gas exciting a plasma . in the exemplary embodiment , the wsi x n y is not a compound - forming barrier , but a stuffed barrier , which prevents diffusion by stuffing nitrogen atoms into diffusion paths , such as interstitial sites , within the tungsten silicide . other embodiments uses diffusion barriers having different compositions and thicknesses , and some entirely omit a diffusion barrier . fig7 and 7 a show that after completion of diffusion barrier 226 , the exemplary method fills at least a portion of the remainder of space 224 ( denoted 224 ′ in fig6 ) with one or more insulative materials . the exemplary embodiment fills substantially all of space 224 ′, which was previously occupied by mask structures 216 and 220 , with a single dielectric material using a single procedure . more particularly , the exemplary embodiment vapor deposits a silicon oxide , such as sio 2 , or low - k ( that is , low - dielectric - constant ) materials , such as xerogels or aerogels . various methods , such as physical - vapor deposition , chemical - vapor deposition , spin - coating , sol - gel procedures , and so forth can be used to apply these dielectrics . fig8 shows one example of the unlimited number of applications for one or more embodiments of the present invention : a generic integrated memory circuit 600 . circuit 600 , which operates according to well - known and understood principles , is generally coupled to a processor ( not shown ) to form a computer system . more precisely , circuit 600 includes a memory array 642 which comprises a number of memory cells 643 a - 643 d , a column address decoder 644 , and a row address decoder 645 , bit lines 646 , word lines 647 , and voltage - sense - amplifier circuit 648 coupled to bit lines 646 . in the exemplary embodiment , each of the memory cells , the address decoders , and the amplifier circuit includes one or more copper -, silver , or gold - based conductors according to the present invention . other embodiments , use conductors of other materials , made in accord with one or more methods of the present invention . in addition , connections between the address decoders , the memory array , the amplifier circuit are implemented using similar interconnects . in furtherance of the art , the inventors have one or more exemplary methods for making integrated - circuit wiring from materials , such as copper -, silver -, and gold - based metals , some of which allow fabrication of wiring with fewer steps and lower electrical resistance than some conventional methods . one exemplary method initially forms a first mask and a first metal structure on the first mask and then forms a second mask and a second metal structure on the second mask , with the first mask and first metal structure still in place . continuing , this exemplary method removes both masks in a single removal procedure , forms a diffusion barrier to both metal structures in a single formation procedure , and fills insulative material in and around both metal structures in a single fill procedure . applying one or more procedures across multiple wiring levels , as in this embodiment , ultimately precludes the necessity of applying these procedures separately to each wiring level and thus promises to simplify fabrication . the embodiments described above are intended only to illustrate and teach one or more ways of practicing or implementing the present invention , not to restrict its breadth or scope . the actual scope of the invention , which embraces all ways of practicing or implementing the invention , is defined only by the following claims and their equivalents .