one or more specific embodiments of the present invention will be described below . it should be appreciated that in the development of any such actual implementation , as in any engineering or design project , numerous implementation - specific decisions must be made to achieve the developer &# 39 ; s specific goals , such as compliance with system - related and business related constraints , which may vary from one implementation to another . moreover , it should be appreciated that such a development effort might be complex and time consuming , but would nevertheless be a routine undertaking of design , fabrication , and manufacture for those of ordinary skill having the benefit of this disclosure . referring now to the drawings wherein like reference numerals correspond to similar elements throughout the several views and , more specifically , referring to fig1 , the present invention will be described in the context of an exemplary rectifier and control system 10 including , among other components , a rectifier controller / processor 12 , a rectifier bridge 16 and a pre - charge circuit 18 . the system 10 receives three phase ac voltages v r , v s and v t on three input supply lines 20 , 22 and 24 , respectively , and converts those ac voltages into a dc voltage / potential across positive and negative dc buses 26 and 28 , respectively . to this end , rectifier bridge 16 includes first , second and third switches or switching devices which , in the illustrated example , include first , second and third silicon controlled rectifiers ( scrs ) 30 , 32 and 34 , respectively , first , second and third diodes 36 , 38 and 40 , respectively , a snubber circuit including a capacitor 84 and a resistor 86 and a dc bus capacitor 82 . the first scr 30 and the first diode 36 are linked series between the positive and negative dc buses 26 and 28 , respectively . in this regard , the anode of diode 36 is linked to negative dc bus 28 , the cathode of scr 30 is linked to positive dc bus 26 and the cathode of diode 36 is linked to the anode of scr 30 at a node 31 . the r - phase supply line 20 is linked to node 31 . similarly , the anode of second diode 38 is linked to negative dc bus 28 , the cathode of second scr 32 is linked to positive dc bus 26 , the cathode of diode 38 is linked to the anode of scr 32 at a node 33 and the s - phase supply line 22 is linked to node 33 . continuing , the anode of the third diode 40 is linked to negative dc bus 28 , the cathode of third scr 34 is linked to positive dc bus 26 , the cathode of diode 40 is linked to the anode of scr 34 at a node 35 and the t - phase supply line 24 is linked at node 35 . referring still to fig1 , capacitor 84 is linked in series with resistor 86 between positive and negative dc buses 26 and 28 . dc bus capacitor 82 is linked between positive and negative dc buses 26 and 28 so as to be in parallel with the series pair including capacitor 84 and resistor 86 . pre - charge circuit 18 includes first and second pre - charge diodes 60 and 62 and first and second pre - charge resistors 64 and 66 , respectively . first pre - charge diode 60 is linked in series with first pre - charge resistor 64 between supply line 24 and positive dc bus 26 where the cathode of diode 60 is linked to positive dc bus 26 . similarly , second pre - charge diode 62 and second pre - charge resistor 66 are linked in series between supply line 22 and positive dc bus 26 with the cathode of diode 62 linked to positive dc bus 26 . referring yet again to fig1 , rectifier controller / processor 12 includes a high frequency pulse generator 70 , an isolation transformer 72 , an scr gate driver 74 and a dc voltage comparator module 14 . as the label implies , high frequency generator 70 generates a high frequency ( e . g ., 20 khz ) pulse signal . to this end , see pulse signal p c in fig3 . the high frequency pulse signal is provided to transformer 72 which isolates generator 70 from driver 74 . comparator module 14 is linked to a voltage sensor 80 that is in turn linked to positive dc bus 26 . sensor 80 generates a feedback dc voltage value v dc which is provided to comparator module 14 . in addition to receiving the feedback dc voltage value v dc , module 14 also receives a dc voltage reference value v r which is input by a system user . the reference value v r is the rated voltage value for the dc bus . comparator module 14 compares the feedback dc voltage v dc to the reference or rated value v r and generates a control signal α on line 48 which is provided to scr gate driver 74 . the control signal a generated by module 14 is low when the feedback dc voltage value v dc is less than the reference voltage value v r . when feedback dc voltage value v dc is equal or greater than reference voltage value v r , control signal α is high . an exemplary control signal α is shown in fig3 . in addition to receiving the high frequency pulse signal p c and the control signals α , gate driver 74 receives the three phase line voltages v r , v s and v t on lines 50 , 52 and 54 , respectively . gate driver 74 uses all of the received signals p c , α , v r , v s and v t to generate first , second and third firing signals r f , s f and t f for controlling scr switching devices 30 , 32 and 34 , respectively . referring still to fig1 and now also to fig2 , scr gate driver 74 includes first , second and third a / d converters 110 , 112 and 114 , respectively , and , first , second and third and gates 100 , 102 and 104 , respectively . the r - phase input voltage signals v r is provided to converter 110 which generates an output signal that is low when the r - phase voltage is negative and that is high when the r - phase voltage is positive . similarly , converters , 112 and 114 receive the s - phase and t - phase input voltages and generate output signals that are high when the associated input voltages are positive and that are low when the associated input voltages are negative . each of the control signal α and the high frequency signal p c is provided to each of and gates 100 , 102 and 104 . in addition , and gate 100 receives the output of first converter 110 , and gate 102 receives the output of second converter 112 and the and gate 104 receives the output of third converter 114 . when all of the inputs to and gate 100 are high or positive , a firing pulse is generated as signal r f on line 42 . similarly , when each of the inputs to and gate 102 are high or positive , a firing pulse is generated as signal s f on line 44 and when all of the input to and gate 104 are positive or high , a firing pulse is generated as signal t f on line 46 . in operation , referring to fig1 , 2 and 3 , when three phase voltages v r , v s , and v t are initially applied to lines 20 , 22 and 24 , dc bus capacitor 82 is initially uncharged and therefore the feedback dc voltage v dc measured by sensor 80 will have a zero value . when the feedback dc voltage v dc is zero , the control signal a has a low value and therefore , referring specifically to fig2 , none of the and gates 100 , 102 or 104 generates firing pulses so that , referring to fig1 , scrs 30 , 32 and 34 act as open circuits . in this case , voltage on supply lines 22 and 24 is supplied through resistors 64 and 66 and diodes 60 and 62 to the positive dc bus 26 which starts to pre - charge the dc bus capacitor 82 . as dc bus capacitor 82 charges , sensor 80 begins to generate a non - zero dc voltage value v dc which , during a pre - charging period , remains below the reference voltage value v r and , during this pre - charging period , the control signal α remains low . in fig3 , this pre - charging period corresponds to the period between times τ 0 and τ 1 where control signal α is low and the resulting r - phase firing signal r f does not include firing pulses . referring still to fig1 - 3 , eventually dc bus capacitor 82 charges to the point where the dc bus potential as reflected in the feedback dc voltage v dc exceeds the rated or reference voltage value v r . when the feedback dc voltage v dc exceeds the rated or reference voltage value v r , module 14 generates a high control signal α ( see time τ 1 in fig3 ). when control signal a goes high , during positive half - cycles of the phase voltages v r , v s and v t , and gates 100 , 102 and 104 generate firing pulses as the firing signals r f , s f and t f , respectively , for their associated phases . thus , for instance , referring to fig3 , for the r - phase , firing signal r f includes exemplary firing pulses 120 whenever the r - phase input voltage v r is high and when the high frequency signals p c is high once control signal a goes high after time τ 1 . as seen in fig3 , once the r - phase input voltage v r goes negative at time τ 2 , the r - phase firing pulses stop . again , at time τ 3 when the r - phase input voltage is positive , the high frequency pulses commence again as signal r f . referring once again to fig1 , once scrs 30 , 32 and 34 begin to fire , because the scrs have very little resistance , the pre - charge circuit 18 is effectively opened ( i . e ., the pre - charge resistors 64 and 66 essentially limit current flow through circuit 18 to a negligible value ). referring now to fig4 , an exemplary method 130 consistent with at least some aspects of the present invention is shown that may be performed by the system of fig1 . at block 132 a rectifier bridge is provided that includes scrs that form the top half of the bridge and diodes that form the bottom half of the bridge . at block 134 , a pre - charge circuit that maybe akin to the circuit 18 shown in fig1 is provided and is used to commence pre - charging of the dc bus capacitor 82 . at block 136 a voltage sensor ( e . g ., see 80 in fig1 ) is used to measure the dc bus voltage and at decision block 138 the feedback dc voltage v dc is compared to the reference voltage v r . where the feedback dc voltage v dc is less than the reference voltage v r , control passes back up to block 134 . where the feedback dc voltage v dc is greater or equal to the reference voltage v r , control passes to block 140 . at block 140 , on a phase - by - phase basis , where one of the phase voltages v r , v s or v t is negative , control passes back up to block 134 . however , on a phase - by - phase basis , where one of the phase voltages is positive , control passes to block 142 where , on a phase - by - phase basis , high frequency firing pulses r f , s f and t f are generated thereby turning on the associated scrs 30 , 32 and 34 , respectively ( see again fig1 ). it should be appreciated that a system has been described for relatively inexpensively pre - charging a dc bus capacitor using a hybrid scr - diode rectifier bridge . it should also be appreciated that the system described does not require any type of phase tracking to determine when during positive half cycles of supply line voltages the scrs should be turned on . instead , because of the high frequency of the pulse signal p c , a firing pulse is effectively provided immediately when a phase voltage goes positive so that the scrs are immediately full on whenever associated line voltages are positive . what has been described above includes examples of the present invention . it is , of course , not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention , but one of ordinary skill in the art may recognize that many further combinations and permutations of the present invention are possible . accordingly , the present invention is intended to embrace all such alterations , modifications , and variations that fall within the spirit and scope of the appended claims for example , while the rectifier is described above as including three scrs , other embodiments could use other types of switching devices . to apprise the public of the scope of this invention , the following claims are made :