according to the preferred embodiment , a novel digital background calibration technique that corrects for the nonlinearity and gain error in the sub - dac ( sdac ), amplifier finite dc gain and reference voltage inaccuracy in a multi - bit / stage pipelined adc is provided . this background calibration technique does not rely on accurate injected calibration voltages that are difficult to be obtained on chip or that would increase the sdac or sadc precision or even split up the capacitor sizes that limit the maximal achievable speed . also a global gain correction ( gcc ) useful for time - interleaved adc ( tiadc ) and techniques to shorten the calibration duration are provided . the general block diagram of a pipelined adc where front - end stages resolve several bits ( e . g 2 . 3 or 3 . 5 ) is shown in fig1 . the output residue v n of stage i is expressed as : where v in and g i are the sdac analog output and the interstage gain respectively . the input of the entire pipelined adc can be obtained by : v in = v dac ⁢ ⁢ 1 + v dac ⁢ ⁢ 2 g 1 + v dac ⁢ ⁢ 3 g 1 ⁢ g 2 + … + v dacp g 1 ⁢ g 2 ⁢ … ⁢ ⁢ g p - 1 + δ ( 2 ) according to eq . ( 2 ) the input signal can be accurately generated when the effective values of v daci and g i are used . capacitor mismatch creates non - linearity in the sdac that limits the precision of v daci . also the capacitor mismatch and the finite opamp gain deviate g i from its ideal value . the mdac circuit of fig2 includes the sdac , the adder and the amplifier illustrated in the schematic expansion of the stage 2 block of fig1 . on φ 1 , the analog voltage from the sample and hold circuit , sha , is loaded onto the capacitors , while on φ 2 , the amplifier feedback through c 1 — is connected , and the digital values from the sub - adc ( sdac ) are loaded on the capacitors to measure the difference between v i and v dac . for a 2 . 5 bit / stage multiplying digital - to - analog converter ( mdac ), as shown in fig2 , the residue voltage can be derived as : v p = g a · g p · ( ⁢ v 1 - v dac ⁢ ⁢ 1 + c t + c p c t · v as ⁢ ⁢ where ( 3 ) c t = c f + c 1 + c 2 + c 3 ( 4 ) g a = 1 / ( 1 + 1 / af ) ( 5 ) and g a is the interstage gain due to the finite opamp gain a that is ideally equal 1 . g c =( c 1 + c 2 + c 3 + c i )/ c f ( 7 ) g c is the interstage gain due to sdac ideally equal 2 2 . v daci =( d 1 · c 1 + d 2 · c 2 + d 3 · c 3 )· v r / c t ( 9 ) g 1 is the interstage gain and v daci is the sdac output . v r is the reference voltage and d 1 are the digital output code of the sadc where d 1 ∈{= 1 , 0 , 1 } and d = σ i = 1 3 d i . fig3 a depicts the residue plot of a realistic 2 . 5 bit / stage given by eq . ( 3 ) compared with an ideal one . nonlinearity of the sdac and the inter - stage gain error , due to the deviation of g 1 from 2 2 , introduce mismatch in the residue jumps in the different boundaries of the digital code d . fig3 a shows the effect of this error on the input - output relationship of the overall pipelined adc when the stage i is considered as the first stage and the remaining stages were ideal . the discontinuities , generally referred to as major - carry jumps in the uncalibrated adc curve shown in fig3 a , cause deleterious missing codes and harmonic distortion that degrade considerably the adc performance . by measuring exactly the value of the jumps g a ·( c i / c f )· v r in the residue and by using the following equation , the residue output becomes linear when it is referred to the input of the stage i despite the gain errors of the sdac and the opamp , and the reference voltage inaccuracy . ideally the gain is equal to 2 n − 1 for n - bit sadc in the stage i . after the correction using eq . ( 10 ) the backend , constituted now from the stage i and the following stage , is linear with a global gain g i = g a · g c . when the stage i is the first stage and after calibrating the adc the calibrated transfer curve is shown in fig4 , where the input - output relationship is linearized and the global gain is equal to the ideal gain multiplied by g 1 / 2 n − 1 . after measuring the errors associated with stage i , stage i − 1 can be calibrated using the linearized backend formed from stage i and its following stages . the final digital output d out is constructed , as shown in fig5 , by starting the correction from the least significant stages to the most significant ones . several calibration methods cause the slope of the overall adc transfer characteristic to depend on the actual residue gains and is therefore not well controlled . fig4 shows that the final gain is multiplied by g i / 2 n − 1 in the case of correction of the first stage . the global gain mismatch is harmful for some applications such as time interleaved adc ( tiadc ) that are inevitable when increasing the speed is desired with high resolution adcs to overcome the technology limits . with gain mismatch between the different channels , inband distortions are created and that degrades considerably performance of time - interleaved adc systems , as for example is known from the article by n . kurosawa , h . kobayashi , k . maruyama , h . sugawara and k . kobayashi , titled “ explicit analysis of channel mismatch effects in time - interleaved adc systems ,” and published in ieee trans . circuits syst . i , vol . 48 , pp . 261 – 271 , march 2001 . in fig6 , the transfer functions of 2 adcs are compared with an ideal one . by succeeding in measuring the global gain g 1 / 2 n − 1 and g 2 / 2 n − 1 for the channels adc 1 and adc 2 , a global gain correction is possible by dividing the final digital output of each adc by 2 n − 1 / g 1 and 2 n − 1 / g 2 respectively ( fig6 ). in the case of calibrating the first stages in adc 1 and adc 2 , the gain g 1 ( i = 1 , 2 ) can be computed using the following equation , this equation indicates that for a global gain correction ( ggc ), a separate measurement for the gain g a from the other products in eq . ( 10 ) needs to be performed . in the background calibration method of the preferred embodiment , the team g a ( c i / c f ) v r is measured for the different values of c i to enable the usage of eq . ( 10 ). a schematic of a modified 2 . 5 - bit mdac according to the preferred embodiment is shown in fig7 . the most significant modification of this mdac from the conventional one is the addition of an extra capacitor c 4 . furthermore , voltage v 1 · p n is sampled onto the feedback capacitor c f when φ 1 is high , where p n is a pseudorandom signal alternating between 0 and 1 . fig3 b illustrates the influence of p n on the mdac response . capacitor c 4 is used instead of c f to sample the input voltage when φ 1 , is high . by doing so , a voltage equal g a · v 1 is injected in the residue output . in background calibration , v in is an unknown , and thus an average of the residue is calculated . with reference to the residue plot of fig3 , it will be appreciated that the residue average across all d i values has a “ dc ” mean value , the latter being increased when p n is 1 by δv = g a ·( v 1 −( c 4 / c f ) v 3 ) and then returning its normal value when p n is 0 . when the averaging is complete for c 4 , and δv is measured , the multiplexers in fig7 are controlled to calibrate the next in the remainder of the capacitors . to not consume much from the offset correctable range of the sadc , v 1 should be a small and stable analog voltage . a voltage could be injected by splitting up the unit capacitor but the voltage v 1 cannot be made arbitrarily small . also , splitting up the capacitors will limit the maximal achievable speed because , in this case , sampling capacitors bigger than the minimal possible size will be used . for this reason , a voltage v 2 − p n is sampled onto the capacitor c 4 in the next phase when φ 2 is high . the voltage v 1 and v 2 do not need to be accurate ( as explained below ). by injecting these voltages , a subtractive imprecise voltage ( siv ) is injected in output residue for the stage under calibration given by : v o = g a · ( g c · v 1 - d 1 · c 1 + d 2 · c 2 + d 3 · c 3 c f · v r + p n · v 1 - p n · c 2 c f · v 2 + ∑ t = 1 n ⁢ c 1 + c f + c p c f · v o ⁢ ⁢ 3 ) = g a · ( v 1 - v 2 · c o c f ) · p n + v o ⁢ ⁢ 1 ( 12 ) where g c =( c 1 + c 2 + c 3 + c 4 )/ c f and v o1 is the remaining term in v n , a simplified example wherein the siv technique is applied to the first stage is shown in fig8 a . by correlating the backend adc digital output d [ v n ] with p n the term δv = g a ·( v 1 −( c 4 / c f ) v 2 ) is extracted . p n1 is used for correlation instead of p n , where p n1 alternates between − 1 and + 1 instead of 0 and 1 in p n . that substitution averages out the mean of the remaining term d [ v n1 ] since p n1 has a mean value of 0 . since d [ v o1 ] and p n1 are uncorrelated and e [ p n ( k )· p n1 ( k )]= ½ , the variance , σ 2 δe , of δe is : σ δ ⁢ ⁢ σ 2 = e ⁡ [ δ ⁢ ⁢ e 2 ] - e ⁡ [ δ ⁢ ⁢ e ] 3 = 1 n 2 ⁢ ∑ t = 1 n ⁢ ( e ⁡ [ d ⁡ [ v n ⁢ ⁢ 1 ⁡ ( k ) ] 2 ] · e ⁡ [ p n ⁢ ⁢ 1 2 ⁡ ( k ) ] ) = 1 n ⁢ σ d ⁡ [ v o ⁢ ⁢ 1 ] 2 ( 15 ) the averager output is not constant in the steady state . instead , it contains a random fluctuation caused by the term involving the variance of d [ v n1 ]. because this term is accumulated , however , it can be made arbitrarily small by increasing the number of samples ( n ) at the input of the averager in fig8 a . in the simplified example of fig8 a , only the first stage is calibrated . it will be appreciated that the modified mdac of fig7 is used to perform calibration for each term related to each capacitor in order to achieve full calibration . in the complete block diagram of fig8 b illustrating the preferred embodiment , two stages 20 a and 20 b are calibrated , and the calibration control system 50 is shown . the pseudorandom generator 54 provides two uncorrelated streams of binary signals , p n1 and p n2 . as in fig8 a , the signals may be converted from a 0 and 1 state used in the fig7 into a − 1 and + 1 state for use in correlation so that the mean correlation has a value of 0 . the imprecise voltages v 1 and v 2 used in mdac 24 a and v 3 and v 4 used in mdac 24 b are provided by a voltage switching matrix 52 . the control unit 50 outputs control signals for the switching matrix 52 and the muxes of the mdac &# 39 ; s 24 to select a capacitor to receive the imprecise voltage selected . the controls signals are also communicated to the successive coefficient measurement unit 46 that analyses the averaged errors δe 1 and δe 2 to determine the correction values associated with each capacitor in the mdac &# 39 ; s . the adc calibration logic 40 uses the correction values from unit 46 along with the random values p n1 and p n2 to process each sample from the adc uncorrected output from the digital error correction unit 30 to provide the desired corrected output samples . global gain correction , that is particularly desirable in the context of a time - interleaved adc , is schematically illustrated as being performed in unit 48 on the output of calibration logic 40 . of course , global gain correction can be performed within logic 40 . the voltages injected into mdac 24 b cause a measurable change in the residual v o2 that is measured by the backend adc 20 c . the residue v o1 is measured by the sub - adc of stage 20 b . measurement of the measurable change caused by the subtractive injection is done using a correlator 44 a , 44 b and averaging unit 42 a , 42 b for the respective stages under calibration to provide the respective averaged errors δe 1 and δe 2 . increasing the number of samples n to achieve calibration means increasing the required calibration time . in the following , two techniques to accelerate the convergence rate at a low overhead are described . in the preferred embodiment , the term g a ( c 4 / c f ) v r is found by injecting subtractive imprecise voltages ( siv ) and performing successive coefficient measurements ( scm ) as explained below . in the first coefficient measurement , v 1 is set equal to ( k − 1 ) v r / k and v 3 equal to v k where k is an even number . in that case , a term g 1 is measured . in the second one v 1 is set to ( k − 1 ) v r / k , v 2 equal to ( k − 2 ) v r / k and coefficient g 1 is obtained . at the k − 1 measurement v 1 is set to v r / k , v 2 to 2 · v n / k , and it gives g r − 1 . finally v 1 is set to v r / k and v 3 to ground and g k is obtained . g 1 = g a ·((( k − 1 )· v r / k )−( c 4 / c f )· v r / k ) g 2 = g a ·((( k − 1 )· v r / k )−( c 4 / c f )·(( k − 2 )· v r / k ))) g 3 = g a ·(( k − 3 )·( v r / k )−( c 4 / c f )·(( k − 2 )·( v r / k ))) g 4 = g a ·(( k − 3 )·( v r / k )−( c 4 / c f )·(( k − 4 )·( v r / k ))) g k − 2 = g a ·(( 3 · v r / k )−( c 4 / c f )·( 2 · v r / k )) g k − 1 = g a ·(( v r / k )−( c 4 / c f )·( 2 · v r / k )) the term g a ( c 4 / c f ) v n is obtained by : g a ( c 4 / c f ) v r =− g 1 + g 2 − g 3 + g 4 − . . . + g k − 2 − g k − 1 + g k ( 17 ) the same procedure is repeated for every capacitors where c 4 will replace the one used in the coefficient measurement procedure . the reference voltages used in sgm do not need to be accurate because there are eliminated from eq . ( 17 ) and a simple string resistance can be used to measure the gain term . the same string resistance used to generate the references of the sadc could be used . if k is chosen to be equal 8 , in every coefficient measurement a voltage around v r / 8 is injected in the second stage . injecting such small voltage means that the non - overload range equal v r / 2 − v r / 8 is left for sadc correction . that non - overload range can correct sadc offset up to =( ¾ ) v r / 8 instead of = v r / 8 in 2 . 5 b / stage without this method . this will alleviate the comparator requirements compared to other calibration methods where a precise voltage of v r / 4 is injected leaving non - overload range of v r / 4 and offset correctable range of ±( ½ ) v r / 8 ( see e . siragusa and i . galton , “ a digitally enhanced 1 . 8v 15 b 50 ms / s cmos pipelined adc ,” isscc dig . tech . papers , pp . 452 – 453 , february 2004 ). moreover the comparator offset correctable range can increase arbitrarily to approach ± v r / 8 by using more reference voltages and by performing more sgm . setting k equal to 8 means 8 calibration cycles are needed to measure every coefficient g a ( c i / c f ) v r . the addition of the 8 coefficients means that the variance in eq . ( 15 ) is now 8 times higher . to obtain the same resolution for the gain as one coefficient measurement , the number of samples in every measurement needs to be 8 · n instead of n . knowing that we need 8 gain measurements so the total number of samples needed is 8 ·( 8 · n ). to shorten the gain calibration to only one cycle of measurement ( e . g . 8 · n ) the calibration voltages are applied in the following manner . in the first sample v 1 is set equal to ( k − 1 ) v r / k and v 2 equal to v n so the injected coefficient is equal to g 1 . in the second sample , we set v 2 and v 3 to obtain g 1 and so on until injecting the voltage that gives the coefficients g 8 . after g 8 , the injected voltages are repeated to obtain g 1 again and so on . in this case the averager output is written as : so to obtain the same resolution as the one coefficient ( e . g . g 1 ) measurement n should be multiplied by 2 3 and only one measurement is sufficient to determine g 4 ( c i / c f ) v r . it will be appreciated that the gain measurement does not need the injection of an accurate analog voltage or an increasing in the sdac linearity or even splitting up the minimal size capacitor that limit the speed . by using the capacitor c 4 instead of c f to sample the input voltage when φ 1 is high in the modified mdac , the interstage gain g a · g c is now constant despite periodically changing of the capacitor under measurement . also this modification avoids the need to measure g a and g a ( c i / c f ) separately as indicated in eq . ( 11 ). in this embodiment , the term given in eq . ( 11 ) is constructed for the modified mdac of fig7 in the digital domain by summing the already measured terms g a ( c i / c f ) related to every capacitor : d ⁡ [ g 1 ] = ⁢ d ⁡ [ ( ( c 1 + c 2 + c 3 + c 4 ) / c f ) · g a ] = ⁢ d ⁡ [ g a · ( c 1 / c f ) ] + d ⁡ [ g a · ( c 2 / c f ) ] + ⁢ d ⁡ [ g a · ( c 3 / c f ) ] + d ⁡ [ g a · ( c 4 / c f ) ] ( 21 ) and then the corrected digital output of the adc is divided by g 1 . in the case of several stages to be corrected , g a given in eq . ( 21 ) will be measured directly multiplied by the new gain of the backend adc ( g back ) where g a = g back ·( 1 /( 1 + 1 / af )). and then , g 1 is constructed by the same equation given in eq . ( 21 ). two techniques that shorten the calibration duration are provided eq . ( 15 ) indicates that the calibration cycles can be shortened by increasing n or by reducing the variance of d [ vol ]. the first technique is applicable when an anti - aliasing filter precedes the adc ( e . g . the adc is not used for under - sampling ) and that only the first stage of the adc needs to be calibrated . in this case , this filter could be made to provide a 0 power at the frequency f s / 2 . in this case , p n could be alternate between + 1 and 0 periodically to modulate the calibration term at f s / 2 as shown in fig1 . that will eliminate the interference between the calibration term and the full - scale spread input signal and that will reduce the number of samples needed . it will be appreciated that the residue or residual voltage d [ vol ] occupies an identified frequency range during normal operation . the injecting of the calibration signal involves alternating between no injecting and injecting of the calibration signal from measurement to measurement at a frequency resulting in the measurable change in d [ vol ] having a frequency outside of the identified frequency range . the measuring of the change uses filtering of the residue d [ vol ] to detect the change at the frequency outside of said frequency range . this gives the value of the change in d [ vol ] without long averaging . since the frequency range of the adc input can occupy any or all of the range of the adc , the frequency range can be detected during operation . it can then be determined whether there is a suitable frequency resulting in the measurable change having a frequency outside of the frequency range of d [ vol ]. if there is such a suitable frequency then a filter is advantageously to obtain the measure of the change more quickly . if not , then the change is measured by obtaining an average of the output residue with the calibration signal injected and an average of the output residue without the calibration signal injected . the change is then a difference between the two averages , and the injecting is done in a random or pseudorandom manner , so that the averages are free of aliasing . when the adc has no empty spectrum to modulate the calibration signal on it , the input signal will be spread all over the bandwidth when multiplied by a pseudo - random p n sequence . knowing that the input signal is preferred to be full - scale to maximize the dynamic range , the input variance can be decreased by subtracting vol from eq . ( 15 ). to calibrate a multibit per stage pipelined adc , the input to be subtracted is the input of the stage under calibration and not necessarily the input signal ( except for the first stage ). usually a multibit per stage pipetined adc has front - end stages resolving several bits ( e . g 2 . 3 or 3 . 5 ) and a backend constituted from 1 . 5 b / stages as shown in fig1 . in this embodiment , the backend adc and the sadc for the stages under calibration are used to predict the variance of vol during the normal operation of the adc . knowing that the accuracy required from the backend adc is relaxed and also knowing that the stages in the backend are configured as 1 . 5 b / stage , this backend can be run at double speed without the need for additional overhead ( see fig1 ). when stage 2 is undergoing calibration in one cycle , the backend adc is connected to the input of stage 2 ( cal = 1 ) to estimate the input signal v res1 . in the next period , the backend adc performs its normal operation for the whole adc . v res1 is sampled at f s while the backend is operating at 2 · f s that means that this voltage is constant during the 2 operations . the value obtained by backend adc during the normal operation of the adc is : v res2 = g 2 ·( v res1 − v dac2 )+ δ v · pn ( 22 ) if we subtract from v res2 the value estimated by the backend { circumflex over ( v )} res1 multiplied by 2 2 instead of g 2 and by using the output of sadc to estimate the sdac output ({ circumflex over ( v )} dac2 ) multiplied by 2 2 eq . ( 22 ) becomes : for capacitor mismatch of ± 0 . 2 % and opamp dc gain of 60 db we find that : the estimated value { circumflex over ( v )} is equal to v − q ( v ) where q ( v ) is the quantization error between the backend adc and the adc formed from stage 2 and the same backend or the error between the estimated output { circumflex over ( v )} dac2 of sdac of stage 2 and v dac2 . also var [ q ( v )] var [ v ]/ 2 2h where the precision of the backend is 10 - bit . from eq . ( 23 ), the variance σ 2 66e of the output of the averager δe can be estimated by : thus the number of samples needed without this signal subtraction is divided by 2 10 . that means , for adc with 14 - bit resolution , instead of requiring a number of 2 30 iterations now only 2 20 iterations are sufficient . that shortens the calibration cycle by 1000 . after calibration of stage 2 , stage 1 is calibrated using the same manner . the residue obtained from the stage 1 in the normal operation of the adc is given by : v res1 = g 1 ·( v in − v dac1 )+ δ v · pn ( 26 ) again to reduce the variance of the g 1 ·( v in − v dac1 ) the term v could be estimated using the already calibrated stage 2 and the following stages but that means that stage 2 need to run at double speed and that is not desirable . instead the same backend used to predict v res1 is now used to predict v in as shown in fig7 . the control signal ( cal ) switches the input of the backend to the input of the stage 1 . the other term v dac1 is replaced by estimated value from sadc of stage 1 obtained during the normal operation . as described above , global gain correction ggc equalizes the gain mismatch in the channels of tiadc &# 39 ; s . for offset mismatch compensation , a chopper - based background calibration is known in the art , for example in s . m . jamal , d . fu , s . h . lewis , and p . j . hurst , “ a 10 - bit 120 m sample / s time - interleaved analog - to - digital converter with digital background calibration ,” ieee j . solid - state circuits , vol . 37 , pp . 1618 – 1627 , december 2002 . in this method , the input signal is converted to a white signal by a random chopper at the input . the output for each channel will contain little information at dc in addition to the offset and then a low - pass filter is used to extract the offset from every channel . the extraction of the offset is inaccurate especially when a full - scale input signal is spread so its power at dc is significant . to accelerate the extraction cycles the same backend used to shorten the calibration cycles for the adc linearity could be used to predict the input signal before chopping as shown in fig1 . thus instead of low - pass filtering the adc output given by : d [ v c1 — new ]=( v in1 −{ circumflex over ( v )} in1 )· p n1 + v 0s1 · p n1 + v os1 ( 28 ) where v ob1 is the offset of the backend adc and { circumflex over ( v )} in1 is the input signal estimated by the adc &# 39 ; s backend . though the backend offset will be spread and it may have some component at dc but this spreading will slightly influence the offset extracting compared to the case where the full - scale analog input v in1 is spread and that will accelerate greatly the calibration cycles . simulations have been performed to verify the effectiveness of these background calibration techniques on a 14 - bit pipelined adc . this adc has two 2 . 5 - bit front - end stages and a backend pan of nine 1 . 5 - bit stages . a capacitor mismatch of ± 0 . 2 %, comparator offsets of ± v r / 10 , and opamp dc gain of 60 db were used in all the stages . the reference voltages for each flash sub - adc and the calibration voltages circuit were generated by a simulated resistor ladder wherein each resistance was chosen with a random error of ± 0 . 2 % standard deviation . only the 2 front - end 2 . 5 - bit stages were calibrated . without any special consideration to shorten the calibration cycles a number of samples around 2 31 for the coefficients measurement ( k = 8 ) were needed . when the backend adc and the sadc of the stage under calibration are used to shorten the calibration duration , the number of samples are shortened to 2 21 . a similar number of samples were needed when the input signal was supposed to have 0 power at fs / 2 frequency and when the coefficient to be measured were shifted at this frequency . a sinewave slightly lower that the full - scale signal around 1 / 20 the sampling frequency ( f s ) was applied to the input of the 14 - bit adc before and after calibration . the signal - to - noise - and - distortion ratio ( sndr ) is 64 db resulting in an effective number of bits ( enob ) of 10 . 3 bits , and the spurious free dynamic range ( sfdr ) is 68 . 4 db . the sndr becomes 84 db resulting an enob of 13 . 7 bits , and the sfdr is increased to 98 db . a 2 - channel time - interleaved adc was simulated before and after ggc . the 2 channels have the same configuration of the one used in the foregoing simulation and that were already calibrated by the proposed method and offset mismatch subtracted by shortening the calibration cycles as described above . before ggc , the sndr was 71 db resulting an effective number of bits enob of 11 . 5 bits , and the sfdr was 74 db . the sndr became 82 db resulting in an enob of 13 . 3 bits , and the sfdr was increased to 91 db . it will be appreciated that in the above described embodiments , there is provided a digital background calibration technique to compensate for the nonlinearity and the interstage gain error of the internal sdac , amplifier finite dc gain and reference voltage inaccuracy in multi - bit / stage pipelined adc . by injecting subtractive imprecise voltages ( siv ) in a modified conventional multi - bit multiplying digital - to - analog converter ( mdac ) and performing correlation based successive coefficient measurements ( scm ), a background calibration is performed . global gain correction of the adc is also provided , and it is feasible to shorten the calibration duration . simulation results demonstrate the effectiveness , of the above embodiments . it will also be appreciated that the invention is not limited to calibration of components in an mdac , but can be applied to other circuits in which the output of a first circuit or stage in which the components to be calibrated are found is measured by a second circuit or stage . it will also be appreciated that the invention can be used to calibrate a voltage reference to be used in a precise - voltage based application circuit . in the embodiment of fig8 c , the invention is used to calibrate a voltage reference using the already calibrated pipelined adc , so that a precision - voltage circuit 65 can make use of the calibration of the voltage reference . in this embodiment , the ratio of the resistances in a string - resistor 60 used to calibrate the adcs or used by any other circuits integrated in the same chip is identified . to simplify the teaching of this embodiment , the string resistance 60 presented in fig9 is redrawn in fig1 with k = 4 and equation 16 is rewritten as follows : g 1 = g a ·( v r3 −( c 4 / c f )· v r ) ( 29 . 1 ) g 2 = g a ·( v r3 −( c 4 / c f )· v r2 ) ( 29 . 2 ) g 3 = g a ·( v r1 −( c 4 / c f )· v r2 ) ( 29 . 3 ) the term g a ( c 4 / c f ) v r is obtained independently from the resistance values using : g a ( c 4 / c f ) v r =− g 1 + g 2 − g 3 + g 4 ( 30 ) now by repeating the eqs ( 29 ) by choosing the voltages in the manner written in the following equations : g 1 = g a ·( v r −( c 4 / c f )· v r3 ) ( 31 . 1 ) g 2 = g a ·( v r2 −( c 4 / c f )· v r3 ) ( 31 . 2 ) g 3 = g a ·( v r2 −( c 4 / c f ) · v r1 ) ( 31 . 3 ) g 4 =− g a ·( c 4 / c f )· v r1 ( 31 . 4 ) g a · v r = g 1 − g 2 + g 3 − g 4 ( 32 ) by replacing ( 32 ) in ( 29 . 1 ) we obtain g a · v r3 which is the needed v r3 multiplied by g a . now by dividing g a · v r3 by ( 32 ) we obtain v r3 / v r = a ( 33 ) independently from g a . by replacing ( 31 . 4 ) in ( 31 . 3 ) we obtain g a · v r2 = g 3 − g 4 . now by dividing g a · v r2 by ( 32 ) we obtain v r2 / v r = b ( 34 ) independently from g a . from ( 29 . 4 ) we have g a · v r1 . again by dividing the latter value by ( 32 ) we obtain v r1 / v r = c ( 35 ). it will now be shown how to find a digital ratio between v r and v r1 . . . i ∈{ 1 , 2 , 3 }, as performed by the resistor / voltage ratio estimator 62 shown in fig8 c . the equations ( 33 )–( 35 ) can also be used directly to obtain the resistances values compared to r t = r 1 + r 2 + r 3 + r 4 by using the following equations . ( r 1 + r 2 )/ r t = b then r 2 / r t = b − c ( 37 ) ( r 1 + r 2 + r 3 )/ r t = c then r 3 / r t = a − b ( 38 ) to obtain r 4 / r t we can switch the left side of r 1 , in fig1 . a , to v r and the right side of r 4 to the ground and compute ( 29 . 4 ) again as : by dividing ( 39 ) by ( 32 ) we obtain v r1 - new / v r = r 4 / r t = d ( 40 ). moreover , we can find all the resistance compared to r 1 as : the equations ( 33 – 35 ) can be used to trim the voltage values compared to v r . in addition ( 36 – 38 ) or ( 41 – 43 ) can be used to trim the ratio between the resistances . this string - resistance can be used in different applications such as resistor - string - dac ( fig1 ) and r / 2r - dac ( fig1 ) or any other circuits that relies on high precision resistances and reference voltages . in the case of a resistor - string - dac and r / 2r - dac the trimming of the resistance values is carried out without interrupting the operation of the dacs . since , the sting - resistances are available for the dac &# 39 ; s usage and the calibrating adc ( calibrated using the method of the preferred embodiment ), digital values corresponding to a , b , c , . . . etc are used to modify the digital input b 1 the dac ( see fig1 ) by corrective digital coefficients to compensate the non - linearity in the dac - analog output due to the resistor mismatch . in other applications , such as operational amplifier , gain stage or filter ( see fig1 ), the string resistances are not available to normal use and calibration . in this case , control switches c 1 , c 2 are used to configure the circuits between the calibration phase and the normal operation phase . for instance when c 1 = 1 and c 2 = 0 the string resistance is configured in trimming mode . when c 1 = 0 and c 2 = 1 the circuit is configured in the normal operation mode . also , the reference voltages used in the injection could be generated not only from string resistance but also from reference voltages of different analog blocks 66 ( see fig8 c ) that their outputs will converted to digital values after signal processing . digital coefficients could be found to take into consideration the mismatch between these voltages v r1 , v r2 and v r in order to compensate the effect of the reference voltage mismatch . also , passive trimming is not exclusive for resistor - based circuits . capacitive based circuits could be calibrated also . for instance , the voltage used in this subtractive injection could be generated directly from a charge capacitive dac , as shown in fig1 . in this case , the dac output v p can be used instead of v 1 and v 2 in order to find corrective coefficient to compensate the dac - nonlinearity due to the capacitor mismatch . it will be appreciated that these equations can be used not only to determine the ratio of the resistances or voltages in the digital domain but also to trim the resistances or the capacitors values in a feedback manner using an adaptive algorithm ( e . g . lms ). a matrix of passive element is used in parallel of the passive element used in the circuit to perform the trimming in the analog domain as shown in fig1 . first the difference between voltage to be trimmed v r1 ( r 2 ) and v r is found using the background calibrated adc as g a ·( v r − v r1 ( n )). the latter term is divided by g a · v r and subtracted from the desired value ( v r − v r1 — ideal )/ v r . an error signal e ( n ) is used to update the coefficients of an lms filter . the negative feedback in the circuit will help the convergence of g a ·( v r − v r1 ( n )) to the desire value ( v r − v r1 — ideal )/ v r . the invention can be applied to calibrate other circuits such as a sample - and - hold ( s / h ) circuit to correct gain error , for example . a prior art s / h is shown in fig1 where the output voltage is given by : gain error correction due to capacitor and finite op - amp gain is essential for s / h &# 39 ; s , especially when they are used in time - interleaved applications . for calibration purposes , the front - end s / h circuit according to this embodiment of the invention is changed as shown in fig2 . in this case , there is no need to add a capacitor to perform voltage subtraction . instead , the sign of the input signal v 1 is monitored using a comparator and a voltage equal to v r is injected without affecting the dynamic range of the s / h as shown in fig2 a . here , v 1 is chosen to be equal to ground and v 2 = sign ( v 1 )· v r where sign ( v 1 )=− 1 when v 1 is positive and sign ( v 1 )= 1 when v 1 is negative . in this case , the s / h output will be given by : v o = g a · g c ·( v 1 − pn · sign ( v 1 )· v r ) ( 45 ) using one comparator to compare v 1 with the ground and to find sign ( v 1 ) may lead to distortion in the s / h transfer function when the comparator is not accurate as shown in point a in fig2 b where v o exceeds the reference voltage v r . therefore , instead of using an accurate comparator , two imprecise comparators are used . one comparator compares v 1 with thus , the voltage v 2 is chosen equal to sign ( v 1 )· v r when v 1 ≥ v r 4 ⁢ ⁢ or ⁢ ⁢ v 1 ≤ - v r 4 . otherwise , v 2 is chosen equal 0 by forcing pn to be 0 ( see fig2 c ). in this case , an offset in every comparator as large as the output of the s / h v o is correlated with pn · sign ( v 1 ) in the background to extract the gain g a · g c of the s / h . a multiplication by 1 / g a · g c for the final output of the adc will compensate the gain error resulting from the s / h circuit .