as technologies evolve , reducing power consumption becomes an important topic . for example , reducing power consumption of portable electronic products , such as a laptop or a cell phone , is highly researched and concentrated . in designing a motor driving circuit , reducing the power consumption becomes important as well . a dc motor driving circuit is provided in the present invention . power consumption of the provided dc motor driving circuit reaches a degree of microamperes or less when the motor is not operated and stays at a standby mode . compared to conventional motor driving circuits having power consumption in a degree of milliamperes in a standby mode , power consumption is significantly saved in the dc motor driving circuit provided in the present invention . moreover , as microprocessors evolve , the motor is required to be operated less frequently , i . e ., the time for activating the standby mode of the motor is getting more frequently . therefore , the weaker the current of the motor under the standby mode is , the more the power consumption of the motor driving circuit is saved . the dc motor driving circuit provided in the present invention reduces power consumption of the motor by weakening the current of the motor under the standby mode . compared to the dc motor driving circuit 100 and the driving module 101 as shown in fig1 , a few elements are added in the present invention , and both the dc motor driving circuit 200 and the driving module 201 are thus formed . in other words , most utilized elements of both the driving modules 101 and 201 are the same so that overlapped couplings described in fig1 are not described again in fig4 . please refer to fig4 , which is a diagram of the dc motor driving circuit 200 provided in the present invention . the difference between the dc motor driving circuits 100 and 200 lies in the driving module 201 . compared to the driving module 101 shown in fig1 , the driving module 201 further includes a power cutter 250 , an oscillator 260 , a counter 270 , a s - r latch 280 , and a hall bias 290 . the power cutter 250 has an output terminal coupled to the first input terminal of the control module 102 , the third input terminal of the comparator 108 , the first input terminal of the lock / restart module 112 , an input terminal of the oscillator 260 , a first input terminal of the counter 270 , the input terminal of the thermal shutdown module 114 , the first input terminal of the operational amplifier 106 , and an input terminal of the hall bias 290 . the power cutter 250 is utilized for generating a disabling signal for disabling the control module 102 , the comparator 108 , the lock / restart module 112 , the oscillator 260 , the counter 270 , the thermal shutdown module 114 , the operational amplifier 106 , and the hall bias 290 . note that in the present invention , the power cutter 250 merely generates the disabling signal while the input terminal of the power cutter 250 stays low , whereas the power cutter 250 further generates an enabling signal while the input terminal of the power cutter 250 stays high . the oscillator 260 has an output terminal coupled to the first input terminal of the counter 270 . the oscillator 260 is utilized for outputting a switch current to the counter 270 . the counter 270 has a third input terminal coupled to the pin pwm , and an output terminal coupled to the set terminal of the s - r latch 280 . the counter 270 is utilized for counting how long the pin pwm is kept on staying low . the s - r latch 280 has the reset terminal coupled to the pin pwm , and a positive logic output terminal , which is denoted as q as well , coupled to the input terminal of the power cutter 250 for activating the disabling signal of the power cutter 250 . note that the pin vdd and the resistor 128 are not utilized for supplying power to the hall sensor 126 nor adjusting an input current of the hall sensor 126 in the dc motor driving circuit 200 , but the hall bias 290 disposed inside the driving module 201 is utilized for supplying power to the hall sensor 126 or adjusting the input current of the hall sensor 126 instead . the hall bias 290 has an output terminal coupled to the pin hb for supplying a constant power to the hall sensor 126 to detect variations in the magnetic field of the motor 116 . in the dc motor driving circuit 100 , the pin vdd is originally utilized for supplying power to the hall sensor 126 , and a corresponding hall bias has to be disposed outside the dc motor driving circuit 100 as well . as mentioned above , in the dc motor driving circuit 200 provided in the present invention , the hall sensor 126 is supplied power by the hall bias 290 disposed inside the driving module 201 . therefore , room for disposing the hall bias outside the dc motor driving circuit is saved , and the hall sensor 126 may be cut in power more rapidly with the aid of the neighboring power cutter 250 . note that the hall bias 290 may be implemented with a conventional regulator so that the hall sensor 126 may be supplied with a power having a variable voltage level . operations of the dc motor driving circuit 200 are roughly described as follows . when the fans of the motor 116 are not required to rotate , i . e ., when the dc motor driving circuit 200 stays at the standby mode , a duty cycle of a pulse width modulation signal at the pin pwm is 0 . in other words , the pulse width modulation signal is continuously low at this time . the counter 270 counts how long the pulse width modulation signal stays at low . when the pulse width modulation signal stays at low over a predetermined critical time , the power cutter 250 generates the disabling signal for disabling elements coupled to the output terminal of the power cutter 250 , and for switching off transistors of the h - shaped full - bridge circuit 104 as well . under such a circumstance , the power consumption of the dc motor driving circuit 200 reaches a degree of microamperes or less , and therefore , the aim of the present invention in significantly reducing the power consumption of the dc motor driving circuit under a standby mode is achieved . the power cutter 250 may be implemented with a conventional digital logic circuit so as to lead the dc motor driving circuit 200 to much less power consumption under the standby mode . moreover , when the power cutter 250 is implemented with complementary metal - oxide semiconductors ( cmos ), the corresponding power consumption is much significantly reduced . as mentioned above , when the hall bias 290 is implemented with a regulator , the hall sensor 126 is supplied with a power having a variable voltage level , which is directly proportional to a bias voltage of the dc motor driving circuit 200 , and therefore , the fact saves much power consumption when the motor is normally operated . moreover , when the dc motor driving circuit 200 is under the standby mode , the disabling signal generated by the power cutter 250 disables the hall bias 290 so that there is no power consumption in the hall bias 290 at this time . the power cutter 250 also disables the comparator 108 so that the gate of the transistor 110 stays low , and the transistor 110 is thus continuously switched off . at this time , the drain of the transistor 110 stays high so that the pin fg continuously stays high as well . please refer to fig5 , and please refer to fig4 as well . fig5 is a waveform diagram illustrating voltage levels at pins of the dc motor driving circuit 200 shown in fig4 . as mentioned before , when the dc motor driving circuit is normally operated , i . e ., during the operating period , voltage levels at the pins of the dc motor driving circuit 200 stay normal . when the voltage level at the pin pwm is kept on going low for a predetermined time , i . e ., when the dc motor driving circuit 200 enters at the standby mode , the counter 270 outputs a signal having a high voltage level to the set terminal of the s - r latch 280 so that the s - r latch 280 satisfies a condition that the set terminal stays high whereas the reset terminal stays low . at this time , the positive logic output terminal of the s - r latch 280 stays low , which is common with conventional s - r latches so as not to be discussed further . after sensing the low voltage level at the positive logic output terminal of the s - r latch 280 , the power cutter 250 generates the disabling signal for disabling most elements of the driving module directly or indirectly . for example , because the power cutter 250 disables the hall bias 290 , the pin hb stays low , the hall sensor 126 is not supplied with power , and both the pins h + and h − stay low . after receiving the disabling signal , the operational amplifier 106 pulls voltage levels at both the nodes po and no down to be low . both the lock / restart module 112 and the thermal shutdown module 114 also shut down its analog elements after receiving the disabling signal , and disable its digital elements so as not to affect the control module 102 . after the comparator 108 receives the disabling signal , the first output of the comparator 108 stays low so that the gate of the transistor 110 stays low as well , the transistor 110 is thus switched off , and the voltage level at the drain of the transistor 110 is raised to be high . in other words , at this time , the pin fg continuously stays at high so that the pin fg cannot indicate the rotational frequency of the motor 116 . after the control module 102 receives the disabling signal , the control module 102 switches off both the first p - type mosfet 130 and the second p - type mosfet 134 so that the motor 116 cannot be supplied with power through the pin vdd . the control module 102 also switches on both the first n - type mosfet 138 and the second n - type mosfet 142 so that the voltage levels at both the pins out 1 and out 2 continuously stay at ground . the oscillator 260 and the counter 270 are shut down after receiving the disabling signal . therefore , the oscillator 260 ceases outputting the switch current , and the counter 270 ceases counting for saving unnecessary power consumption . note that both the set terminal and the reset terminal of the s - r latch 280 stay low because the counter 270 is shut down . herein , the current of the driving module 201 is weakened to a degree of microamperes or less , and the aim of reaching a least current consumption in the dc motor driving circuit 200 under the standby mode is achieved . at last , when the system terminal tends to reactivate the motor 116 , the pulse width modulation signal is restored to a status of interleaving high and low voltage levels . when the pulse width modulation signal is restored to be high , the s - r latch is reset , and satisfies a condition that the set terminal stays high whereas the reset terminal stays low . therefore , the positive logic output terminal of the s - r latch 280 stays high so as to have the power cutter 250 to output the enabling signal . the elements disabled by the power cutter 250 directly or indirectly are enabled after receiving the enabling signal , and the motor 116 is returned to be normally operated again . note that whether the power cutter 250 outputs the enabling signal or the disabling signal , there is a certain operating order between the elements enabled or disabled . for example , the power cutter 250 merely outputs the enabling signal instead of the disabling signal after the pin hb is completely changed from low to high , therefore , the precision of the voltage levels at the pins h + and h − is ensured , and the precision of other functions replying on both the voltage levels at the pins h + and h − is ensured also . the present invention provides a dc motor driving circuit having a low current consumption under a standby mode , for improving the defect of having a higher current consumption under the standby mode in the prior art , where the higher current consumption leads to a higher power consumption as well . in the dc motor driving circuit provided by the present invention , a counter counts how long a pulse width modulation signal , which is inputted to the dc motor driving circuit , is kept on staying low , and has the dc motor driving circuit of the present invention enter the standby mode when the pulse width modulation signal stays at low over a predetermined period of time . then the counter triggers a s - r latch to have a power cutter to output a disabling signal . any element receiving the disabling signal is disabled or shut down , and thus has least current consumption , where the motor has least current consumption as well . at this time , the current consumption of the dc motor driving circuit of the present invention reaches a degree of microamperes or less . when the system terminal generates a high pulse width modulation signal for reactivating the motor , the s - r latch and the power cutter are utilized again for restoring the dc motor driving circuit back to normal operations . besides , since the hall sensor utilized in the present invention is supplied with power through a built - in hall bias , room for coupling an external hall bias is saved . the hall bias may also be implemented with a regulator . therefore , under normal operations of the dc motor driving circuit of the present invention , the hall bias may dynamically adjust the supplied power according to a bias voltage of the dc motor driving circuit , and significant current consumption may thus be saved . those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention .