fig1 shows a detailed schematic illustration of the base circuit according to the present invention , i . e . a non - ideal dynamic d - flip - flop formed by ten field effect transistors t 1 through t 10 with insulated grids . these transistors are known also as mos [ metal - oxide - semiconductor ] transistors . five of the transistors are channel p transistors and five transistors are channel n transistors . it is to be understood that this circuit generates three internal variables a , b and c and is supplied with two external variables , h and d , of which h is a clock signal and d is a command signal . variable c corresponds directly to the inverse of the output signal , i . e . signal q . the simplified schematic of the d - flip - flop shown in fig2 explains the operation of the circuit of fig1 . in fig2 the capital letters in the circles representing the transistors indicate the variable controlling the transistors . in this simplified schematic , three different gates can be distinguished ; i . e . gate a &# 39 ; producing internal variable a , gate b &# 39 ; producing internal variable b , and gate c &# 39 ; producing internal variable c , which corresponds to the inverse output signal q . in operation , it should first be remembered that an mos p channel transistor is blocked , if its grid is at a positive potential corresponding to a logic value 1 , and conducts if its grid is at ground corresponding to a logic value of 0 . the opposite case is true for an n channel mos transistor . assuming that the two external variables h and d are equal to zero i . e . h = 0 and d = 0 , transistors t 1 and t 2 conduct whereas transistor t 3 is blocked . consequently , node n 3 is connected to the positive pole +, which in turn causes the variable a to assume the value a = 1 . this blocks transistor t 4 and causes transistor t 5 to conduct . transistor t 6 also conducts while transistor t 7 is blocked . consequently , node n 7 floats , therefore , variable b floats . however , a stray capacitance made by the sum of the drain capacitances of t 5 and t 6 the connection capacitance and the grid capacitances of t 8 and t 9 controlled by variable b , makes it possible to achieve a tempory memory effect . the capacitance c b is drawn in dashed lines in fig2 because it is intrinsic to the circuitry and not included as a passive additional element . the capacitance represented by c b makes it possible for a node that is temporarily neither connected to the positive pole (+) nor to ground to maintain its previous value . this tempory state cannot last for a long time , as leakage current will discharge c b , there must be frequent changes of state . such a circuit has a dynamic character . assuming that variable b has the value b = 0 , the stray capacitance of node n 7 corresponding to b , which is floating , will maintain the value b = 0 . under these conditions , and in view of the fact that the value of the external variable h is equal to zero , transistor t 8 conducts , transistor t 9 is blocked and transistor t 10 is blocked , which means that node n 11 is connected to the positive pole (+), so that variable c assumes the value c = 1 . the structure hence assumes a first stable state i as follows : a = 1 , b = 0 floating , c = 1 , h = 0 and d = 0 , or in other words , abc = 101 and hd = 00 . if at this moment variable h is changed from zero to one , to produce a second stable state ii that corresponds to the following conditions abc = 101 and hd = 10 , the different transistors of gate a &# 39 ; assume the following conduction states : which results in the node n 3 is floating , so that variable a floats . because of the capacitance represented by capacitor c a variable a keeps its former value of a = 1 , therefore , at gate b &# 39 ; we have the following conditions : which has the effect of connecting node n 7 to zero , so that variable b takes the value b = 0 . which connects node n 11 to positive (+) and keeps variable c at the value c = 1 . if external variable h is then brought back to zero , none of the internal variables a , b or c will vary , because for gate a &# 39 ;: so that node n 3 is connected to positive pole (+) and variable a confirms its value of a = 1 . which causes variable b to float . because of the capacitance represented by capacitor c variable b is held to its previous value of b = 0 . so that variable c remains at its initial value of c = 1 . by this transition , the dynamic flipflop structure has passed from stable state ii to stable state i . from the afore - mentioned discussion , it can be seen that the result of changes in external variable h while variable d is held at d = 0 , do not in any way influence the value of variable c or of the output value q . if however from stable state i equal to abc = 101 and hd = 00 and variable d is changed from d = 0 to d = 1 , we have the following conditions for gate a &# 39 ;: which results in variable a changing from a = 1 to a = 0 , so that the circuit assumes an intermediate state , wherein abc = 001 and hd = 01 . this results in the following changes in the conditions of conductivity of transistors t 4 , t 5 , t 6 and t 7 of gate b &# 39 ;: consequently , variable b changes from b = 0 to b = 1 . thus the circuit passes to a second intermediate state corresponding to the conditions of abc = 011 and hd = 01 . this however causes the following modifications in the conductivities of the transistors of gate c &# 39 ;: the variable c thus becomes floating : but because of capacitance c c , variable c maintains its former value of c = 1 . as a consequence , the preceding intermediate state is confirmed and becomes a third stable state iii of the circuit which corresponds to the conditions abc = 011 and hd = 01 . when starting from stable state ii , wherein abc = 101 and hd = 10 and if the variant h = 1 is not brought back to zero but d is varied from d = 0 to d = 1 , the conductivities of the different transistors and consequently of internal variables a , b and c take the following values for gate a &# 39 ;: this has the effect that the value of variable a passes from a = 1 to a = 0 , which produces the following intermediate state : abc = 001 and hd = 11 , having the following influence on gate b &# 39 ;: this results in floating of the value of variable b . because of capacitance c b , variable b is kept at its earlier value of b = 0 . the value of variable c does not change because neither variable b nor variable h have changed . consequently , the earlier intermediate state is confirmed and becomes stable state iv with abc = 001 and hd = 11 . at the instant at which d flipflop structure according to the invention is in the above - mentioned stable state iv , variable d can be varied so as to pass from d = 1 to d = 0 . in other words , during the time when the clock signal h is positive , i . e . h = 1 , external variable d varies from zero to one and returns to zero . this disturbing impulse on variable d causes for gate a &# 39 ; the following changes : which makes variable a floating but holds it at former value of a = 0 . as a result , neither variable b nor variable c are going to change values , which means that the circuit passes to a first undesired stable state ndi characterized by abc = 001 and hd = 10 and does not return to the sought stable state ii . if from stable state iv when abc = 001 and hd = 11 , variable d is not changed but variable h is changed so that it changes from h = 1 to h = 0 , the following changes are caused for gate a &# 39 ;: so that variable a is held to the value a = 0 while for gate b &# 39 ;: as a result , variable b becomes positive , i . e . b = 1 . this provokes an intermediate state abc = 011 and hd = 01 influencing the state of gate c &# 39 ; as follows : in other words , the intermediate state becomes stable state iii corresponding to the conditions abc = 011 and hd = 01 . if starting from stable state iii variable d is returned to zero , the following happens in gate a &# 39 ;: so that variable a becomes positive and takes the value a = 1 , which again influences the transistors of gate b &# 39 ; as follows : thus variable b becomes floating but holds its value of b = 1 . the conditions for gate c &# 39 ; do not vary . variable c remains floating and held at c = 1 . the circuit is not returned to the desired stable state i , but passes into a second undesired stable state corresponding to conditions abc = 111 and hd = 00 . if , on the other hand , starting from stable state iii variable d is not varied , but variable h is varied so as to cause it to pass from h = 0 to h = 1 , the following happens in gate a &# 39 ;: so that variable a is unchanged and remains at a = 0 . for gate b &# 39 ;: this results in variable b floating but held at its value of b = 1 . the conductivities of the transistors of gate c &# 39 ; change in the following way : so that variable c passes to zero , i . e . c = 0 . the circuit has thus reached a new stable state v corresponding to the conditions abc = 010 and hd = 11 . by now bringing external variable h to zero , the circuit assumes the following state for gate a &# 39 ;: which has the effect that variable a remains at a = 0 . for gate b &# 39 ; the following conditions therefore occur : variable b is thus confirmed at its earlier value of b = 1 . for gate c &# 39 ; the following conditions therefore occur : so that variable c becomes floating but is held at its value of c = 0 . it follows that the structure takes a new stable state vi equal to abc = 010 and hd = 01 . this means that the changes of variable h while variable d remains equal to one do not affect internal variable c and thereby output q . if , starting from stable state v equal to abc = 010 and hd = 11 we do not vary h , but rather d so as to bring this variable d back from d = 1 to d = 0 , the following conditions result in gate a &# 39 ;: which has the effect that variable a becomes floating but remains at its value of a = 0 . for gate b &# 39 ; the following conditions therefore result : which has the effect that variable b becomes floating but remains held at b = 1 . for gate c &# 39 ; the following conditions therefore occur : so that variable c is confirmed at its earlier value of c = 0 . the structure has thus assumed a new stable state vii corresponding to the conditions abc = 010 and hd = 10 . now we may again vary external variable h so as to bring it from h = 1 to h = 0 , which causes the following changes for gate a &# 39 ;: which has the effect that variable a becomes positive , i . e . a = 1 , so that an intermediate state [ corresponding to ] abc = 110 and hd = 00 occurs , influencing gate b &# 39 ; as follows : variable b thus remains floating , held at value b = 1 . variable c also becomes floating , because for gate c &# 39 ;: which has the effect that the circuit assumes a new stable state viii corresponding to the conditions abc = 110 and hd = 00 . if from stable state vi corresponding to abc = 010 and hd = 01 we vary variable d , from d = 1 to d = 0 , the structure also will assume the above mentioned stable state viii , because for gate a &# 39 ;: and variable a takes the value a = 1 . therefore , for gate b &# 39 ; the following conditions result : so that variable b becomes floating but remains at b = 1 and for gate c &# 39 ;: which has the effect that variable c becomes floating but remains at its value of c = 0 . the stable state that is attained thus corresponds to above mentioned stable state viii for conditions abc = 110 and hd = 00 . if starting from this stable state we vary d from zero to one , the following happens for gate a &# 39 ;: so that variable a becomes a = 0 , bringing about an intermediate state corresponding to abc = 010 and hd = 01 . for gate b &# 39 ;: it follows that variable b is confirmed at its value of b = 1 . variable c does not change , however , because for gate c &# 39 ;: which has the effect that variable c becomes floating but is held at its value of c = 0 . it should be observed that bringing variable d back from zero under these conditions , to one , allows the circuit to return to stable state vi . when starting from stable state viii mentioned above , variable h is changed from zero to one , the circuit finally returns to stable state ii , because for gate a &# 39 ;: and variable a becomes floating but is held at a = 1 . therefore for gate b &# 39 ;: which has the effect that variable b takes the value b = 0 , so that an intermediate state abc = 100 and hd = 10 influence gate c &# 39 ; as follows : so that variable c becomes positive or c = 1 . the structure thus has assumed stable state ii corresponding to the conditions abc = 101 and hd = 10 . to bring the structure back to stable state iv from the undesired stable state ndi , it suffices to change variable d from d = 0 to d = 1 , which has the following effect on gate a &# 39 ;: so that variable a is confirmed in its value of a = 0 . therefore gate b &# 39 ; assumes the following condition : so that variable b remains floating and is held at its value of b = 0 . therefore gate c &# 39 ; assumes the following conditions : the stable state that is reached corresponds to sought stable state iv which corresponds to conditions abc = 001 and hd = 11 . if , starting from undesired stable state ndi corresponding to abc = 001 and hd = 10 , we change external variable h from one to zero , the following happens for gate a &# 39 ;: which has the effect that variable a assumes the value a = 1 . for gate b &# 39 ;, assuming that variable a has not yet changed , the following conditions result : the variation of h influences the two gates a &# 39 ; and b &# 39 ;. therefore , there is a contest between these two gates to determine which one will change its value first . this causes difficulties and it is for this reason that this transition is forbidden in normal operation of the circuitry . this flipflop is therefore called non - ideal . when the intermediate state is abc = 111 and hd = 00 , and the starting state was abc = 001 and hd = 10 , the two variables cannot simultaneously change value . consequently , there are two different behavior patterns resulting from the contest between the two variables a and b . in the first pattern , variable a changes before variable b and an intermediate state abc = 101 and hd = 00 , which results in the stable state i . in the second pattern , variable b changes before variable a , resulting in an intermediate state abc = 011 and hd = 00 . variable b is then impressed on gate c &# 39 ;, resulting in the following conditions : consequently , variable c is floating and retains its value of c = 1 . variable a then influences variable b , which becomes floating so that the state in which the structure ends up is abc = 111 and hd = 00 . this is undesired stable state ndii . starting from the undesired stable state ndii , which corresponds to abc = 111 and hd = 00 , it is also possible to make two different transitions , namely to change variable h from zero to one , which causes gate a &# 39 ; to have the following conditions : so that variable a becomes floating but keeps its value of a = 1 . for gate b &# 39 ; then , if variable b changes before variable c , the following conditions result : which changes the value of variable b from b = 1 to b = 0 and creates an intermediate state corresponding to abc = 101 and hd = 10 . for gate c &# 39 ;, varying after the change of b , the following conditions exist : which has the effect that variable c is held at c = 1 , which confirms the intermediate state and makes it a stable state corresponding to stable state ii , wherein abc = 101 and hd = 10 . here again , there is a contest between variables b and c . in fact , if variable c changes before variable b , we get different behavior . since variable b is still on b = 1 , if h passes from 0 to 1 , gate c &# 39 ; acts as follows : so that variable c takes the value c = 0 . then only gate b &# 39 ; changes its state taking , as before , the value b = 0 . consequently , we get an intermediate state abc = 100 and hd = 10 . since variable b has gone to zero , gate c &# 39 ; again changes state as follows : so that variable c takes the value c = 1 . the state in which the structure ends up is thus abc = 101 and hd = 10 , namely stable state ii . this transition is forbidden in normal operation of the structure , because in one case variable c temporarily passes to a value of zero , and in the other case , it is permanently equal to one . starting from undesired stable state ndii corresponding to abc = 111 and hd = 00 , it is also possible to change d from zero to one , which causes the following transitions : for gate a &# 39 ;: which has the effect that variable a passes from a = 1 to a = 0 , which establishes an intermediate state equal to abc = 011 and hd = 01 , which influences gate b &# 39 ; as follows : and variable b is confirmed in its value of b = 1 . for gate c &# 39 ;: t 10 is blocked which has the effect that variable c is floating and remains confirmed at its value of c = 1 . this changes the former intermediate state into a stable state corresponding to stable state iii with the conditions abc = 011 and hd = 01 . from what has been demonstrated above , it follows that the circuit never remains blocked or trapped in an undesired stable state , but ends always in a desired stable state . accordingly , the d - flip - flop circuit according to this invention has no parasitic cycles . in addition , except for the two transitions that we have forbidden or prevented in using this flip - flop so that it does not have these transitions , all the other transitions have only a single variable change state at one time and by transition , thus forbidding any possibility of competition between states , thereby ensuring risk free operation . operation of the dynamic d - flip - flop according to fig1 and 2 , can be conveniently understood , with the aid of a table of states , which shows the different transitions in a synchronous as well as an asynchronous mode of operation of the circuit . in table i , stable states i through viii assumed by the structure are surrounded by a solid - line circle , while the two undesired stable states ndi and ndii are surrounded by dashed - line circles . moreover , the transitions according to synchronous mode of operation are indicated by solid - line arrows , while the transitions according to asynchronous mode of operation are indicated by dashed - line arrows . in addition , the states of internal variables a , b and c that are held by capacitances only are underlined . to facilitate a comparison between this table and the above description , the same numbering of the stable states is included . fig . 2a gives the time diagram for this non - ideal dynamic d - flip - flop , showing each variable individually and again indicating by underlining the states retained by capacitance . the diagram clearly show that variable c ( output q ) is responsive only to the ascending transitions of the clock signal h . this diagram also shows why the described schematic cannot be designated as ideal : a disturbing pulse i p on variable d , while variable h is equal to 1 produces a distributing pulse i p c on variable d i . e . on output q . a disturbance of this kind must , therefore , be avoided to ensure proper operation of the described d - flip - flop . it must also be pointed out that clock signal h has to be kept above a certain minimum frequency so that the circuit will function correctly , since the circuit is dynamic . command or control signal d is not subject to such a restriction . in other words , there is no lower limit to the rate of change of signal d . fig3 shows how the basic structure described above can be made ideal . in other words , how the two undesired stable states ndi and ndii can be eliminated and a distrubing pulse i p on variable d made innocuous or harmless . it suffices to introduce two supplementary transistors , one parallel to transistor t 2 and the other parallel on transistor t 7 . a new transistor t 21 is connected in parallel with transistor t 2 l and must be controlled by internal variable b , while a new transistor t 71 connected in parallel with transistor t 7 must be commanded by internal variable c . the function and the transitions that this ideal dynamic d - flip - flop can effect are represented in the table of states labeled table 2 which follows , and give the same date as table 1 . fig . 3a shows quite well that in the circuitry of fig3 a disturbing pulse i p , as described above , has no influence whatsoever on variable c i . e . on output q . the circuit , therefore , functions ideally . the following detailed explanation of the transitions due to disturbing pulse i p illustrates the function of the new transistors t 21 and t 71 . if starting with stable state iv corresponding to abc = 001 and hd = 11 we change variable d from one to zero , this is what happens for gate a &# 39 ;: in contrast to the non - ideal dynamic d - flip - flop of fig1 and 2 , node n 3 of the ideal circuit in these conditions is connected to the positive pole , because the new transistor t 21 is conducting , since it is connected in parallel with blocked transistor t 2 . variable a thus assumes the value a = 1 , which implies an intermediate state corresponding to the conditions abc = 101 and hd = 10 . for gate b &# 39 ; the following conditions exist : which means that for this gate , it is not the new transistor t 71 , but changing of the value of variable a that confirms variable b at b = 0 . for gate c &# 39 ; the following conditions exist : t 10 conducts with the effect that for this variable nothing changes , and it remains confirmed at its value c = 1 . in other words , transistor t 21 is significant , because when it undergoes the above - described transitions , the circuit returns to the desirable stable state ii , which corresponds to the conditions abc = 101 and hd = 10 instead of switching into undesired state ndi . for the other transition critical for the non - ideal structure , according to fig1 and 2 which occurs when starting with stable state iii , when abc = 011 and hd = 01 , it is possible to make hd = 00 . for the ideal dynamic d - flip - flop circuit of fig3 the following happens within gate a &# 39 ;: variable a then assumes the value a = 1 , developing an intermediate state corresponding to abc = 111 and hd = 00 . gate b &# 39 ; then has the following conditions : which means that the new transistor t 71 causes the change of state of variable b , because since t 71 is conducting , node n 7 is connected to ground . this results in variable b taking the value b = 0 , so that there is a new intermediate state , wherein abc = 101 and hd = 00 , which has the following effect in gate c &# 39 ;: therefore , varaible c assumes the value c = 1 . it follows that , because of the new transistor t 71 , the ideal circuit does not switch to an undesired stable following said critical transition but return to desirable stable state i , which corresponds to the conditions abc = 101 and hd = 00 . the above discussion confirms the accuracy of table 2 , and the time diagram of fig3 a , which schematically illustrate the possible transitions of the different variables in the ideal dynamic d - flip - flop circuit according to fig3 . as mentioned above , a dynamic d - flip - flop , whether it is ideal or not , requires a certain minimum frequency clock signal h , in order to function correctly . this is because we consider that certain variables , for certain conductivities of the transistors of the structure , are held at their values only by capacitances . from the two time diagrams 1 and 2 , shown in fig2 a and 3a respectively , it can be seen that the internal variables b and c are momentarily held at their values by capacitances , while external variable h is at zero , just as well as when clock signal h is on &# 34 ; one &# 34 ;. this means that clock signal h must present limited duration of h = 1 and for h = 0 . a clock signal , whose duration is h = 1 or h = 0 is limited , but whose frequency may be arbitrarily low can command a so called semi - dynamic structure . to make the base structure according to fig1 and 2 semi - dynamic , one may introduce seven supplementary transistors , to produce a circuit with non - ideal semi - dynamic functioning , or eight transistors to have a circuit with ideal semi - dynamic functioning . such a semi - dynamic d - flip - flop structure requires a clock signal h whose durations h = 1 must be limited , whereas the durations during which h = 0 can be of any length . if the p type transistors are replaced by n type transistors and vice versa , the h = 0 durations will be limited , whereas h = 1 can be of any duration . fig4 shows the simplified schematic of an ideal semi - dynamic d - flip - flop . to make this structure non - ideal , we would eliminate transistor t 21 which would result in a circuit that could assume the undesired stable state ndi defined above . in fig4 we see that the semi - dynamic structure requires a supplementary internal variable e = c for its functioning , which variable is the true value q of inverse output q . table 3 which follows illustrates the transitions effected by this structure . it also gives all the other information in the same way as for the other two tables . the states of table 3 are practically identical with the states of tables 1 and 2 , except that in table 3 , each state is defined by an additional internal variable . the advantages brought by the invention with respect to the state of the art are numerous , and are detailed in part by the above description . nevertheless , it must also be observed that in addition to these functional advantages , the invention also allows the production of structures or circuits that require only a minimum surface area of a chip , because of the minimum number of active elements and the absolute absence of delay elements . this feature makes these structures especially advantageous for utilization in very small bulk apparatus , such for example , as electronic wrist watches . in addition , these circuits consume energy only during changes in state of the mos transistors . no energy is required to hold the structures in a given state , except for losses . accordingly , static energy consumption of the circuits is thus practically nil . the overall energy consumption is thus low , since consumption is practically limited only to dynamic consumption . moreover , the invention is particularly advantageous , because it lends itself very well to easy manufacture , especially in cmos technology . it may also readily be made responsive to the descending transistors of clock signal h by replacing the p channel transistors with n channel transistors and vice versa . furthermore , since the circuit is an integrated circuit having a p - type region and an n - type region , it is possible to form the channel n - type transistors in the p - type region and the channel p - type transistors in the n - type region . the invention is not strictly limited to the schematics that are shown , because it is possible to effect permutations among the transistors of the same channel in each gate without affecting the proper functioning of the described d flip - flops . the permutation of two transistors in series and with the same channel changes nothing in the function effected by these two transistors . it is also evident that all the d - flip - flops of the invention can be included within a complex circuit and on a chip that contains one or more different circuit structures .