the modulator 1 according to an embodiment of the invention shown in fig1 comprises a first transistor 11 for receiving phase information and comprises a second transistor 12 for receiving an envelope code . the phase information and the envelope code define a ( phase - modulated ) signal that is to be amplitude - modulated by the modulator 1 . the first and second transistors 11 and 12 each comprise first and second main electrodes ( sources and drains ). the first main electrode ( source ) of the second transistor 12 is coupled to the second main electrode ( drain ) of the first transistor 11 and the other second main electrode ( drain ) of the second transistor 12 constitutes and / or is coupled to an output 51 of the modulator 1 . the other first main electrode ( source ) of the first transistor 11 is coupled to a reference terminal . the first transistor 11 comprises a control electrode ( gate ) that constitutes and / or is coupled to a phase input 31 for receiving the phase information . the second transistor 12 comprises a control electrode ( gate ) that constitutes and / or is coupled to an envelope input 41 for receiving the envelope code . the modulator 1 further comprises a third transistor 13 for receiving the phase information and comprises a fourth transistor 14 for receiving a further envelope code also defining the ( phase - modulated ) signal that is to be amplitude - modulated by the modulator 1 . the third and fourth transistors 13 and 14 each comprise first and second main electrodes ( sources and drains ). the first main electrode ( source ) of the fourth transistor 14 is coupled to the second main electrode ( drain ) of the third transistor 13 and the other second main electrode ( drain ) of the fourth transistor 14 constitutes and / or is coupled to the output 51 of the modulator 1 . the other first main electrode ( source ) of the third transistor 13 is coupled to the reference terminal . the third transistor 13 comprises a control electrode ( gate ) that constitutes and / or is coupled to the phase input 31 for receiving the phase information . the fourth transistor 14 comprises a control electrode ( gate ) that constitutes and / or is coupled to a further envelope input 42 for receiving the further envelope code . the modulator 1 further comprises a fifth transistor 15 for receiving the phase information and comprises a sixth transistor 16 for receiving a yet further envelope code also defining the ( phase - modulated ) signal that is to be amplitude - modulated by the modulator 1 . the fifth and sixth transistors 15 and 16 each comprise first and second main electrodes ( sources and drains ). the first main electrode ( source ) of the sixth transistor 16 is coupled to the second main electrode ( drain ) of the fifth transistor 15 and the other second main electrode ( drain ) of the sixth transistor 16 constitutes and / or is coupled to the output 51 of the modulator 1 . the other first main electrode ( source ) of the fifth transistor 15 is coupled to the reference terminal . the fifth transistor 15 comprises a control electrode ( gate ) that constitutes and / or is coupled to the phase input 31 for receiving the phase information . the sixth transistor 16 comprises a control electrode ( gate ) that constitutes and / or is coupled to a yet further envelope input 43 for receiving the yet further envelope code . the backgates of the second and fourth and sixth transistors 12 and 14 and 16 are for example coupled to the reference terminal . alternatively , the backgates of the first and third and fifth transistors 11 and 13 and 15 may be used for receiving the phase information . further alternatively , the first main electrodes of the first and third and fifth transistors 11 and 13 and 15 may be used for receiving the phase information etc . in case the second , fourth and sixth transistors 12 and 14 and 16 have identical proportions , the modulator 1 functions as follows . in case the envelope of the phase - modulated signal that is to be amplitude - modulated has an amplitude “ 1 ”, for example only the first transistor 11 is to be activated and is to be brought into a conducting state , via the envelope codes . in case the envelope of the phase - modulated signal that is to be amplitude - modulated has an amplitude “ 2 ”, for example only the first transistor 11 and the third transistor 13 are to be activated and are to be brought into a conducting state , via the envelope codes . in case the envelope of the phase - modulated signal that is to be amplitude - modulated has an amplitude “ 3 ”, for example the first transistor 11 and the third transistor 13 and the fifth transistor 15 are to be activated and are to be brought into a conducting state , via the envelope codes etc . in case the second , fourth and sixth transistors 12 and 14 and 16 have non - identical proportions for example such that the second transistor 12 has a weighting factor “ 1 ” and the fourth transistor 14 has a weighting factor “ 2 ” and the sixth transistor 16 has a weighting factor “ 4 ”, the modulator 1 functions as follows . in case the envelope of the phase - modulated signal that is to be amplitude - modulated has an amplitude “ 1 ”, for example only the first transistor 11 is to be activated and is to be brought into a conducting state , via the envelope codes . in case the envelope of the phase - modulated signal that is to be amplitude - modulated has an amplitude “ 2 ”, for example only the third transistor 13 is to be activated and is to be brought into a conducting state , via the envelope codes . in case the envelope of the phase - modulated signal that is to be amplitude - modulated has an amplitude “ 3 ”, for example the first transistor 11 and the third transistor 13 are to be activated and are to be brought into a conducting state , via the envelope codes etc . this way the phase - modulated signal is amplitude - modulated . the phase - modulated signal originates from an oscillator as shown in fig2 . many alternatives are possible , such as more branches or less branches coupled in parallel to each other and each branch comprising two serially coupled transistors . further , per branch the two transistors may trade places etc . however , preferably , the transistors that receive the envelope codes are located closer to the output than the other transistors that receive the phase information , in view of the available voltage swings . the device 10 according to the invention shown in fig2 comprises a polar transmitter 2 according to the invention and comprises an interfacing and processing circuit 9 . the polar transmitter 2 comprises a digital circuit 3 such as a digital cordic for receiving for example analog in - phase and analog quadrature information from the interfacing and processing circuit 9 and for generating a digital phase / frequency code ( a digital phase / frequency code comprises a digital phase code and / or a digital frequency code ) and the digital envelope codes and comprises an oscillator 6 ( that for example forms part of a phase locked loop ) for receiving the digital phase / frequency code and for generating the phase information . the modulator 1 receives this phase information and the digital envelope codes . in case of the circuit 3 being an analog circuit 3 such as an analog cordic , it generates an analog phase / frequency code ( an analog phase / frequency code comprises an analog phase code and / or an analog frequency code ) and analog envelope codes that need to be low pass filtered by low pass filters 4 and 7 and that need to be digitized by analog to digital converters 5 and 8 . the output of the modulator 1 is , for example , coupled to an antenna possibly via one or more further components . preferably , the polar transmitter 2 further comprises means not shown such as a delay line for somewhere in the polar transmitter 2 creating a phase shift between the phase information and the envelope codes . such a phase shift reduces aliases . many alternatives are possible , such as generating envelope information at the circuit 3 and then converting the envelope information into individual envelope codes that are destined for the individual transistors etc . the modulator 1 according to the invention shown in fig3 corresponds with the one shown in fig1 apart from the fact that each branch has been extended with two further transistors . the first branch further comprises a further first transistor 21 for receiving the phase information and comprises a further second transistor 22 for receiving an inversion of the envelope code . the further first and further second transistors 21 and 22 each comprise first and second main electrodes ( sources and drains ). the first main electrode ( source ) of the further second transistor 22 is coupled to the second main electrode ( drain ) of the further first transistor 21 and the other second main electrode ( drain ) of the further second transistor 22 constitutes and / or is coupled to the output 51 of the modulator 1 . the first main electrode ( source ) of the further first transistor 21 is coupled to a further reference terminal . the further first transistor 21 comprises a control electrode ( gate ) that constitutes and / or is coupled to a phase input 61 for receiving the phase information ( so the phase inputs 31 and 61 are coupled to each other and / or receive the same phase information ). the further second transistor 22 comprises a control electrode ( gate ) that constitutes and / or is coupled to an inverted envelope input 71 for receiving an inversion of the envelope code . the second and third branches have been extended with further third and further fourth and further fifth and further sixth transistors 23 and 24 and 25 and 26 etc . this modulator 1 as shown in fig3 is a symmetric modulator that does not require a resonance circuit or a transformer at its output for filtering dc components but that only requires a capacitor at its output for filtering dc components . the backgates of the second and fourth and sixth transistors 12 and 14 and 16 are , for example , coupled to the reference terminal . the backgates of the further second and further fourth and further sixth transistors 22 and 24 and 26 are , for example , coupled to the further reference terminal . alternatively , the backgates of the first and third and fifth transistors 11 and 13 and 15 and of the further first and further third and further fifth transistors 21 and 23 and 25 may be used for receiving the phase information . further alternatively , the first main electrodes of the first and third and fifth transistors 11 and 13 and 15 may be used for receiving the phase information etc . the prior art transistor layout shown in fig4 discloses a metal layer with the source 81 and the drain 82 of the first transistor 11 and with the source 91 and the drain 92 of the second transistor 12 and discloses a silicon layer with the gate 83 of the first transistor 11 and with the gate 93 of the second transistor 12 located on this silicon layer and with a doped area 84 of the first transistor 11 and a doped area 94 of the second transistor 12 located in this silicon layer . in this case the drain 82 and the source 91 are coupled to each other via a metal coupling and a capacitance 101 is present between the drain 82 and the gate 83 and a capacitance 102 is present between the source 91 and the drain 92 . these two capacitances 101 and 102 are responsible for relatively much cross - talk . the transistor layout according to the invention shown in fig5 has overlapping doped areas 84 and 94 of the first and second transistors 11 and 12 with respect to the drain 82 and the source 91 . in this case , the drain 82 and the source 91 no longer need to be coupled to each other via a metal coupling and a capacitance 103 is now present between the gate 83 and the drain 92 , which capacitance 103 is smaller than the combination of the capacitances 101 and 102 . as a result , the cross - talk has been reduced and the silicon area can be reduced . to realize this , the integration masks need to be designed such that the doped areas of the coupled first and second main electrodes are overlapping . in fig6 , an ofdm signal is shown in a time domain ( y - axis − 4 to + 4 volt , x - axis 0 to 1000 nsec ). in fig7 , an envelope of the ofdm signal is shown in a frequency domain ( y - axis − 100 to 0 db , x - axis 0 to 1000 mhz ). in fig8 , a phase of the ofdm signal is shown in a frequency domain ( y - axis − 80 to 0 db , x - axis 0 to 450 mhz ). in fig9 , an output signal is shown in a time domain of the modulator according to the invention as shown in fig1 ( y - axis − 900 to + 900 mvolt , x - axis 0 to 1000 nsec ). in fig1 , the output signal is shown in a frequency domain ( y - axis − 100 to − 20 db , x - axis 0 to 1600 mhz ). in fig1 , the output signal is shown with aligned phase and amplitude sample moments in a frequency domain ( y - axis − 140 to 0 db , x - axis − 300 to + 300 mhz relative to the center frequency ). in fig1 , the output signal is shown with shifted sample moments in a frequency domain ( y - axis − 140 to 0 db , x - axis − 300 to + 300 mhz relative to the center frequency ). in fig1 , simulation results are shown for low pass filters 4 and 7 between an analog cordic and an oscillator at a cut - off frequency of 150 mhz ( y - axis − 80 to − 20 db , x - axis 220 to 420 mhz ). in fig1 , simulation results are shown for low pass filters 4 and 7 between an analog cordic and an oscillator at an infinite cut - off frequency ( y - axis − 80 to − 20 db , x - axis 220 to 420 mhz ). the modulator 1 shown in fig1 comprises the transistors 11 - 16 already shown in fig1 and indicated in fig1 by the block 11 - 16 . the modulator 1 further comprises a transistor 32 with a gate coupled via a resistor 33 to the phase input 31 and with a source coupled to the reference terminal and with a drain coupled to a bias input 34 . the transistor 32 makes a power control possible . when the amplitude of the phase - modulated signal is lowered the overall output current of the circuit is lowered also . the transistor 32 defines the current flowing through all the other transistors . when the amplitude of the phase - modulated signal at the input is lowered , the bias current at the bias input 34 can be lowered correspondingly to increase the efficiency . a further phase input 31 ′ corresponding with the phase input 31 might then be used for receiving the phase information . the modulator 1 further comprises a further transistor 52 with a source coupled to the output 51 and with a drain coupled to a further output 51 ′ and with a gate for receiving a possible attenuated output voltage of the output signal and with a backgate coupled to its source . the further transistor 52 increases the reliability and / or reduces reliability problems . the way it works is that the output signal is divided over the series connection of the further transistor 52 and the other transistors 11 - 16 . in this way each branch only gets half the voltage , which leads to a much higher reliability . in order to prevent breakdown of the gate - to - backgate voltage , the backgate of the further transistor 52 may be connected to its source . this can be done using a triple - well technology . this triple - well technology has become available in modern cmos090 and cmos065 processes . in fig1 the output signal as a function of the number of branches that are switched on is shown ( y - axis volt , x - axis number ). with the number of switches for example being 0 - 255 , the output signal starts to deviate from a linear transfer curve for large input codes . by measuring the output signal and using a conversion table before driving the transistors with the envelope codes , a more linear output signal can be obtained . thereto , a converter such as a table etc . is to be introduced for converting non - compensated envelope codes into compensated envelope codes . each transistor in general and each one of the ( further ) first and ( further ) third and ( further ) fifth transistors more in particular may be realized by a combination of two or more transistors , such as a serial construction or a parallel construction or a mixed serial parallel construction . further , the fact that two electrodes are coupled to each other does not exclude that the two electrodes are coupled to each other via one or more active or passive elements . for example , in case the two electrodes do not have overlapping doped areas , they might need to be coupled via a passive coupling that may have a parasitic resistance , capacitance and / or inductance . the two electrodes might also be coupled via an active element such as a yet further transistor , for example for further switching purposes or adaptation purposes or security purposes etc . it should be noted that the above - mentioned embodiments illustrate rather than limit the invention , and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims . in the claims , any reference signs placed between parentheses shall not be construed as limiting the claim . use of the verb “ to comprise ” and its conjugations does not exclude the presence of elements or steps other than those stated in a claim . the article “ a ” or “ an ” preceding an element does not exclude the presence of a plurality of such elements . the invention may be implemented by means of hardware comprising several distinct elements , and by means of a suitably programmed computer . in the device claim enumerating several means , several of these means may be embodied by one and the same item of hardware . the mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage . having thus described at least one illustrative embodiment of the invention , various alterations , modifications , and improvements will readily occur to those skilled in the art . such alterations , modifications , and improvements are intended to be within the spirit and scope of the invention . accordingly , the foregoing description is by way of example only and is not intended as limiting . the invention is limited only as defined in the following claims and the equivalents thereto .