typical ic packages are comprised of circuits and insulators and do not provide esd protection . an example of a typical area array package is provided in fig1 . in the figure the ic package substrate 100 is comprised of an insulating base material 101 on which is disposed redistribution circuits 102 which serve to interconnect the fine pitch i / o terminals on the chip to i / o terminals which allow for package egress at a larger i / o pitch . while the insulation material is critical for mechanical support and dimensional stability of the circuits it was noted that if the voltage breakdown limit of the material was low enough , it could naturally serve as a path to ground under esd conditions . unfortunately in order for the material to do this , it would likely be too thin to be practical for mechanical purposes . a solution to this problem is to create a substrate material that has areas and locals that could provide path ways from circuits to ground that would be preferentially used by esd events thus protecting the ic . there are a number of potential materials that could be interposed between the circuits and ground that could provide such a potential path . the simplest and most widely available is air . for example , an air gap of 25 μm will provide a spark gap at approximately 40 volts , a value which is suitable for the needs of ic protection . while air is suitable , there are practical matters that must be addressed to meet manufacturing needs . in addition to air , certain polymer materials , such as those described by schrier , et al . in u . s . pat . no . 4 , 726 , 991 , have been developed that are capable of rapidly shunting power spikes ( i . e . electrostatic discharges ) to ground and / or to power to protect the integrated circuit presently exist . thus in other embodiments of the present invention , esd protection is made an integral element of the base material used for manufacturing ic packages . in fig2 is shown an embodiment of the invention wherein an ic package interconnection substrate 200 has redistribution circuits 102 residing on an insulating base material 101 . in the enlarged image 200 a , the circuit redistribution traces 102 are shown to be overlapping an ordered pattern of multiple esd protective material areas 201 . in this matter the material is placed near or directly beneath i / o terminations providing a shunting pathway to ground and / or power planes / rings residing on the opposite side of the insulating material . ( not shown ). although the enlarged image 200 a shows circuits intersecting multiple esd protective areas , the number of intersections can be a single intersection or many . in addition , one or more of the circuits could be connected to the metal ground or power layer on the opposite side by a suitable means such as a metal plated via . in fig3 is shown an embodiment of the invention wherein an ic package interconnection substrate 300 has redistribution circuits 102 residing on an insulating base material 101 . in the enlarged image 300 a , the circuit redistribution traces 102 are shown to be overlapping multiple esd protective material areas 201 and there is a central die attach pad 301 . the esd protective material areas 201 are placed into a pattern covering a larger area of the substrate to provide a greater number of potential shunting pathways to ground or power . the pattern of the esd protective material areas may be arranged so that circuit traces randomly intersect the esd areas as they make their way from the center of the substrate ( where the chip resides ) 301 to the edge of the substrate where the circuit trace terminates 102 . a fig4 a through 4 d illustrates alternatively embodiments of the pattern of the esd protective material features . in the figures the circuits 102 are arranged so that circuit traces intersect multiple esd areas 201 in a deliberate and exact manner , inclusive of the number of esd protective material areas as well as the amount of overlap a circuit trace achieves with a particular esd protective material area ( not shown ). also illustrated in the figure are constructions having lateral protrusions 401 having respective distal ends disposed within respective esd protective material areas 201 . illustrates how circuit traces may be arranged in different overlap configurations . as with fig2 , one or more of the circuits could be connected to the metal ground or power layer on the opposite side by a suitable means such as a metal plated via . in fig5 a through fig5 i is illustrated a process for fabricating an embodiment of the invention . in fig5 a , an insulating base material film 501 , ( e . g . polyimide , lcp , fr4 , etc ) is either created on or laminated to a metal foil 502 such as copper . in fig5 b , holes 503 are place either randomly or in a pattern in the material to access the metal foil through the insulating material . in fig5 c , a squeegee pushing a suitable voltage switchable material 505 is pushed from position 504 a to 504 b and depositing the material into the previously open holes . deposition of the suitable voltage switchable material is not limited to a squeegee methodology and may include sputter or other material deposition processes . the finished height level of the suitable voltage switchable material is equal to the height of the film , creating an exact and predictable thickness value for the esd voltage switchable material to assure consistent performance . in fig5 d , the surface is then metallized or coated with a metal layer ( e . g . copper ) 506 using a suitable method . in fig5 e , the circuit pattern and other designs are defined on the metal layer 506 by an etch resist 507 . in fig5 f , the circuit features , such as redistribution circuits 508 and die attach pad 509 , are stripped of etch resist to expose the metal . the exposed metal may or may not be over plated with other metals ( e . g . nickel and gold ) to provide a wire bondable surface . for flip chip constructions the metal itself may be suitable . in fig5 g , an insulating polymer , such as a solder mask 510 can then be applied to protect the circuit and leave open areas for interconnection to both the chip and to next level interconnections 511 . in fig5 h , is illustrate a wire bond treatment of the ic package wherein an ic chip 512 is attached to the die attach pad using a suitable die attach adhesive 513 and the ic is interconnected to the circuits on the packaging substrate by means of wires 514 and the assembly is protected by a suitable encapsulant 515 . in fig5 i , the completed package assembly with integral esd protection material can next be provided with suitable terminations such as solder balls 516 . although the invention has been described with reference to specific exemplary embodiments thereof , it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention . the specification and drawings are , accordingly , to be regarded in an illustrative rather than a restrictive sense .