fig4 depicts by block diagram a preferred embodiment of the invention in the context of a computer system with processor integrated circuit , set associative cache integrated circuit , and a board level data bus . as preferably embodied , processor 12 is situated on integrated circuit chip 13 , chip 13 including multiplexer 14 , multilevel converter 16 and reference generator 17 . fig4 also depicts the presence of a two - way set associative cache comprised of two cache sections individually situated on separate integrated circuit chips 18 and 19 . each cache section , identified individually as cache section a and cache section b , includes respective associated memory array 21 and 22 for storing digital data in the form of cache lines , and respectively associated address tags 23 and 24 . search engine 26 receives addresses from processor 12 , and searches address tags 23 and 24 to select . the appropriate cache section , and accesses cache lines of data from cache memory sections 21 and 22 . the &# 34 ; late select &# 34 ; signal is transmitted to multiplexer 14 . particularly unique to the present invention is the use of multiple current source drivers 27 and 28 associated with respective cache memory sections 21 and 22 . current source drivers 27 and 28 inject currents into board level data bus 29 individually by line based upon the binary content of the data to be transmitted for such line . the levels of currents provided by drivers 27 and 28 differ . multilevel converter 16 connected to bus 29 detects the analog sums of the currents on the lines of bus 29 and decodes from such net line currents the binary equivalents by line of the data being provided by cache sections 21 and 22 . the relationship between net bus line current and digital data are presented at 31 in fig4 and set forth in table a , below . table a______________________________________net bus current ina bus line cache a data cache b data______________________________________0 0 0i / 2 0 1i 1 03i / 2 1 1______________________________________ note that the current values identified as net bus currents in table a are relative to bias currents to be described hereinafter . selection between cache sections , and the associated choice of the data to be presented to processor 12 , is accomplished by multiplexer 14 . the operation can be performed late in the cache read clock cycle since data from both sections of the cache are read from the cache sections , transmitted , fully decoded , and available on the processor chip 13 when the final selection is received from search engine 26 . an important aspect of the invention involves the accurate generation and differentiate of current levels in the context of field effect transistor implemented integrated circuit devices . early concepts were introduced in u . s . pat . no . 5 , 568 , 064 , the subject matter of which is incorporated herein by reference . later refinements , as will be described hereinafter , appeared in u . s . patent application ser . no . 08 / 703 , 317 , filed aug . 26 , 1996 , the subject matter of which is incorporated herein by reference , and in u . s . patent application ser . no . 08 / 703 , 318 , filed aug . 26 , 1996 , the subject matter of which is also incorporated herein by reference . accurate generation of current source signals , detection of current levels , and conversion to binary are accomplished through the use of reference generators 17 , 32 and 33 , where reference generator 17 resides on processor chip 13 , reference generator 32 resides on integrated circuit chip 18 in common with cache section a , and reference generator 33 resides on integrated circuit chip 19 in common with cache section b . reference generators 17 , 32 , and 33 are linked by line 34 having a common node voltage v ref . the voltage on line 34 establishes a mutually derived voltage level which is then used by each reference generator to accurately replicate corresponding levels of transmitted current ( i t ), bias current ( i b ) and reference bias voltage ( v b ). though the depiction and table are described in the context of a two - way set associative cache the underlying concepts are not that limited and therefore may be extended through analogous implementation to an n - way set associative cache . fig5 schematically depicts in greater detail elements from current source driver 27 in fig4 . in particular , the depiction shows the elements used to drive data example bus lines 0 and 5 . reference generator 32 provides transmission current ; signal i t on line 36 and bias current signal i b on line 37 to pairs of current source drivers connected to each data bus lines . for example , as to data bus line 0 , bias signal i b generates in driver 38 a bias current of level i b . similarly , signal i t causes current source 39 to generate a transmission current level i t when the data on line 0 is a binary 1 so as to enable gate 41 . when the data on line 0 is a binary 0 gate 41 is disabled and current source 39 produces no output . thus , current source 39 modulates between 0 output and output i t depending on the binary state of the data on line 0 . the bias and data currents driving line 5 of the data bus are similarly generated and modulated . line 0 data which enables gate 41 comes from the cache memory array in conventional manner for the respective line . for purposes of contrast , as illustrated by dashed lines generally at 40 , note that the corresponding bus line 0 of cache section b generates a bus current of 0 and i t / 2 for corresponding for binary data values of 0 and 1 . reference generators 17 , 32 and 33 in fig4 are critical elements in the successful operation of the system . since each reference generator resides on the corresponding integrated circuit chip , the operation of its active and passive devices reflects characteristics common to other devices on that chip . with the reference generator 17 being on a common chip with multilevel converter 16 , reference generator 32 being on a common chip with current source drivers 27 , and reference generator 33 being on a common chip with current source drivers 28 , not only are the respective fabrication effects linked but so too are the thermal effects as the individual chips vary in temperature . the three reference generators themselves are interconnected through node 34 , so that the commonly defined node voltage v ref can be used to precisely establish biases and transmission signals , namely v b , i b , and i t . bias signal i b eminating from reference generator 33 in fig4 is depicted by dashed line in that the current bias on each line of data bus 29 may originate at any one of the reference generators , or may be the result of multiple contributors as long as the net injected bias current is of value i b . fig6 schematically depicts a composite reference generator , namely one that provides all the reference signals v b , i b and i t as may be used in conjunction with current source drivers 27 and 28 as well as multilevel converter 16 . all the signal generators depicted in the composite reference generator of fig6 may not be needed on each chip . for example , multilevel converter 16 ( fig4 ) does not utilize reference signal i b , and correspondingly does not require the generation of the signal in reference generator 17 . in contrast , some signals may need to be generated as an aspect of operating the reference generator , an example being signal v b . reference generator 42 in fig6 uses signal v b to balance the currents i t flowing in terminators 44 and 46 , where the current i t flowing in terminator 46 is current mirror generated by field effect transistor 47 as effected by the interconnection with reference node v ref , while the current i t flowing in field effect transistor 48 is a direct current mirror outcome . the current i t flowing in field effect transistor 49 is a current mirror of that in field effect transistor 51 and appears as a signal output i t for current mirror matching . current i t flows through accurate resistors 52 and 53 , each resistor preferably having a value z o representing the characteristic impedance of the lines of data bus 29 ( fig4 ). amplifier 54 adjusts the level of signal i t accordingly . bias signal i b is generated through the current mirror operation of field effect transistors 57 and 58 responsive to amplifier 59 , where amplifier 59 detects the signal through the earlier noted characteristic impedance resistors 52 and 53 in relation to the bias current effects on terminator 61 . other refinements of reference generator 42 in fig6 are described in the aforementioned copending u . s . patent application ser . no . 08 / 703 , 317 , filed aug . 26 , 1996 . fig7 depicts a detailed embodiment of multilevel converter 16 ( fig4 ) as applied to board level data bus line 5 , functionally depicted as transmission line 62 . note that three current sources drive data bus line 5 , namely , line 5 bias current i b , line 5 data current from section a of the cache , having current levels 0 or i t , and line 5 data current from the cache section b , having data current levels of 0 or i t / 2 . the sum or net current received at node 63 , representing the input for line 5 of the board level data bus 29 ( fig4 ), appears in increments as shown depending on the data content read from the cache sections . the net currents start at a base level of i b , representing 0 , and increase in successive i t / 2 increments to represent data as described in table a . the net current appearing at node 63 is sunk by active terminator 64 . active termination 64 is preferred in that it maintains the accuracy sought through the use of multiple functionally matched reference generators . the current sinking signal generated in active terminator 64 is replicated by current mirror transistors 66 and 67 . the current sources 68 and 69 are generated using conventional current mirror techniques in response to the reference signal i t as created in reference generator 17 ( fig4 ). note that current source 69 is selectively enabled and disabled by high speed current source switch 71 . current source 72 of magnitude i t / 4 is similarly generated , with a current mirrored replication in field effect transistors 73 and 74 . the combination of switched and non - switched multiple level current sources in multilevel converter 16 allows one to distinguish between current levels , above the bias current i b , using thresholds of i t / 4 , 3i t / 4 and 5i t / 4 to differentiate between net current levels of 0 , i t / 2 , i t , and 3i t / 2 . waveforms depicting the differentiation and the corresponding binary outputs on bit lines 1 and 2 are depicted by plots in fig8 . the first plot shows the various levels of analog current sums , such as would appear on node 63 ( fig7 ) and the corresponding outputs on bit lines 1 and 2 . high speed current . source switch 71 ( fig7 ) ensures that the turn - on of bit 1 shown by the spike in the third plot is sufficiently brief to avoid an erroneous interpretation of the decoded output . fig9 shows active terminator transistors 76 , 77 , and 78 . note that transistor 77 is biased by the supply voltage v dd common to the other field effect transistor devices in the chips . transistor 76 , however , is subject to a gate drive defined by reference voltage v b . the currents being terminated , various levels of i t and i b , generate an output signal from node 79 suitable for current mirror replication in the manner used repeatedly in the present invention . the active terminator in fig9 is selected to maximize the match of transistor characteristics as may appear on different integrated circuit chips and as may be further affected by temperature variations . an implemention of high speed current source switch 71 appears in fig1 of the drawings . the switch is driven by bit line 2 and is utilized to enable current source 69 ( fig7 ) with minimum delay . the current sources i t / n are generated through current mirror scaled replication of signal i t from reference generator 17 ( fig4 ). the fundamental concept of simultaneously transmitting data from sections of a set associative cache as embodied for a two - way set associative cache in fig4 clearly is applicable for more than two sections , adjusting accordingly for the current source driver and multilevel converter granularity . the fundamental underlying concepts are fully applicable to the extent that integrated circuit tolerances permit differentiation between levels . the concepts embodied in the two - way set associative cache and simultaneous data transmission over a common bus are equally applicable to other forms of simultaneous multilevel transmissions of information over such bus . the key objective is to utilize accurately referenced current sources at the transmitting end and an accurately referenced multilevel converter at the receiving end , the accuracy preferably being established and maintained through the use of multiple reference generators and a common reference node . it will be understood that those skilled in the art that the embodiment set forth hereinbefore is merely exemplary of the numerous arrangements by which the invention may be practiced , and as such may be replaced by equivalents without departing from the invention which will now be defined by appended claims .