the following description is merely illustrative in nature and is in no way intended to limit the disclosure , its application , or uses . for purposes of clarity , the same reference numbers will be used in the drawings to identify similar elements . as used herein , the phrase at least one of a , b , and c should be construed to mean a logical ( a or b or c ), using a non - exclusive logical or . it should be understood that steps within a method may be executed in different order without altering the principles of the present disclosure . as used herein , the term module may refer to , be part of , or include an application specific integrated circuit ( asic ); an electronic circuit ; a combinational logic circuit ; a field programmable gate array ( fpga ); a processor ( shared , dedicated , or group ) that executes code ; other suitable components that provide the described functionality ; or a combination of some or all of the above , such as in a system - on - chip . the term module may include memory ( shared , dedicated , or group ) that stores code executed by the processor . the term code , as used above , may include software , firmware , and / or microcode , and may refer to programs , routines , functions , classes , and / or objects . the term shared , as used above , means that some or all code from multiple modules may be executed using a single ( shared ) processor . in addition , some or all code from multiple modules may be stored by a single ( shared ) memory . the term group , as used above , means that some or all code from a single module may be executed using a group of processors or a group of execution engines . for example , multiple cores and / or multiple threads of a processor may be considered to be execution engines . in various implementations , execution engines may be grouped across a processor , across multiple processors , and across processors in multiple locations , such as multiple servers in a parallel processing arrangement . in addition , some or all code from a single module may be stored using a group of memories . the apparatuses and methods described herein may be implemented by one or more computer programs executed by one or more processors . the computer programs include processor - executable instructions that are stored on a non - transitory tangible computer readable medium . the computer programs may also include stored data . non - limiting examples of the non - transitory tangible computer readable medium are nonvolatile memory , magnetic storage , and optical storage . the present disclosure relates to reducing dead times ( i . e ., conduction times of body diodes of high and low side drivers ) of dc - to - dc converters . specifically , the present disclosure relates to reducing the dead times in various modes of operation of the dc - to - dc converters irrespective of load conditions . for example , the dead times can be reduced according to the present disclosure in dc - to - dc converters operating in buck continuous conduction mode ( ccm ) with a heavy load , buck or boost forced ccm with a light load , and boost ccm with a heavy load . one way to reduce the dead times is to prevent the body diodes from conducting and turning on the high - side switch t hs or the low - side switch t ls before the respective body diodes can conduct . accordingly , the load current i l will flow through the high - side switch t hs or the low - side switch t ls instead of flowing through the respective body diodes . referring now to fig3 a - 3d , a dc - to - dc converter ( hereinafter converter ) 200 that reduces dead times in buck or boost forced ccm with a light load is shown . in fig3 a , the converter 200 includes the high - side switch t hs , the low - side switch t ls , the inductor l , the capacitor c out , and the load 104 . the high - side switch t hs and the low - side switch t ls ( collectively switches ) are connected in series . the inductor l is connected to the junction of the switches and is connected in series with the capacitor c out as shown . the load 104 is connected in parallel to the capacitor c out as shown . the pwm pulses generated by the pwm module 102 ( not shown ) control the on and off times of the switches . the converter 200 receives the input voltage v dd and outputs the output voltage v out across the load 104 . to reduce the dead times , the converter 200 further includes a feedback loop for each switch . the feedback loops compare timings of gate and drain voltage transitions of the switches . the feedback loops delay the pwm pulses that are output to the gates of the switches based on the timings to reduce the dead times . the word transition as used herein means a rising edge or a falling edge of a signal ( e . g ., a pwm pulse , a voltage , or a current ) when the signal begins to rise from a low value or fall from a high value , respectively . accordingly , a gate turn - on transition for the high - side switch t hs is a falling edge of a gate - to - source voltage of the high - side switch t hs since the high - side switch t hs is shown as a pmos device . a gate turn - off transition for the high - side switch t hs is a rising edge of the gate - to - source voltage of the high - side switch t hs since the high - side switch t hs is shown as a pmos device . conversely , a gate turn - on transition for the low - side switch t ls is a rising edge of a gate - to - source voltage of the low - side switch t ls since the low - side switch t ls is shown as an nmos device . a gate turn - off transition for the low - side switch t ls is a falling edge of the gate - to - source voltage of the low - side switch t ls since the low - side switch t ls is shown as an nmos device . similarly , a falling v lx transition is a falling edge of the voltage v lx , and a rising v lx transition is a rising edge of the voltage v lx . the feedback loop for the high - side switch t hs includes a timing module 202 , a charge pump 204 , a delay module 206 , and an inverting driver 208 . the feedback loop for the low - side switch t ls includes a timing module 210 , a charge pump 212 , a delay module 214 , and an inverting driver 216 . the inputs of the delay modules 206 and 214 receive the pwm pulses from the pwm module 102 . the delay module 206 delays a rising edge of a pwm pulse ( since t hs is a pmos device ) based on an output voltage of the charge pump 204 and propagates a falling edge of a pwm pulse without delay . the inverting driver 208 inverts the output of the delay module 206 and outputs the inverted output of the delay module 206 to the gate of the high - side switch t hs . the delay module 214 delays a falling edge of a pwm pulse ( since t ls is an nmos device ) based on an output voltage of the charge pump 212 and propagates a rising edge of a pwm pulse without delay . the inverting driver 216 inverts the output of the delay module 214 and outputs the inverted output of the delay module 214 to the gate of the low - side switch t ls . in the feedback loop for the high - side switch t hs , the timing module 202 has an inverting input and a non - inverting input . the inverting input is connected to the gate of the high - side switch t hs ( since t hs is a pmos device ). the non - inverting input is connected to the junction of the switches . accordingly , the inverting input senses a falling edge of a gate voltage of the high - side switch t hs , and the non - inverting input senses a rising edge of a voltage v lx at the junction of the switches . suppose a falling transition of the gate voltage of the high - side switch t hs occurs at time t 1 , and a rising transition of the voltage v lx occurs at time t 2 . the timing module 202 has two outputs : out 1 and out 2 . if t 1 is before t 2 , the timing module 202 outputs a pulse having a pulse width ( t 2 − t 1 ) on the output out 1 , and out 2 is low . conversely , if t 2 is before t 1 , out 1 is low , and the timing module 202 outputs a pulse having a pulse width ( t 1 − t 2 ) on the output out 2 . the charge pump 204 has two inputs that respectively receive the outputs out 1 and out 2 of the timing module 202 , and an output that outputs a voltage that increases or decreases based on the outputs out 1 and out 2 of the timing module 202 . for example , the output voltage of the charge pump 204 increases when the timing module 202 outputs a pulse on the output out 1 and decreases when the timing module 202 outputs a pulse on the output out 2 . the amount by which the output of the charge pump increases or decreases depends respectively on the pulse widths on the outputs out 1 and out 2 . the delay module 206 delays a rising edge of a pwm pulse . the amount of delay is based on the output of the charge pump 204 . for example , the delay increases or decreases based on whether the output of the charge pump 204 increases or decreases . further , the amount by which the delay increases or decreases depends on the amount by which the output of the charge pump 204 increases or decreases . the inverting driver 208 inverts the output of the delay module 206 and outputs the inverted output of the delay module 206 to the gate of the high - side switch t hs . in the feedback loop for the low - side switch t ls , the non - inverting input of the timing module 210 is connected to the gate of the low - side switch t ls ( since t ls is an nmos device ). the inverting input is connected to the junction of the switches . accordingly , the non - inverting input senses a rising edge of a gate voltage of the low - side switch t ls , and the inverting input senses a falling edge of the voltage v lx at the junction of the switches . suppose a falling transition of the voltage v lx occurs at time t 1 , and a rising transition of the gate voltage of the low - side switch t ls occurs at time t 2 . the timing module 210 has two outputs : out 1 and out 2 . if t 2 is before t 1 , the timing module 210 outputs a pulse having a pulse width ( t 1 − t 2 ) on the output out 1 , and out 2 is low . if t 1 is before t 2 , out 1 is low , and the timing module 210 outputs a pulse having a pulse width ( t 2 − t 1 ) on the output out 2 . the charge pump 212 has two inputs that respectively receive the outputs out 1 and out 2 of the timing module 210 , and an output that outputs a voltage that increases or decreases based on the outputs out 1 and out 2 of the timing module 210 . for example , the output voltage of the charge pump 212 increases when the timing module 210 outputs a pulse on the output out 1 and decreases when the timing module 210 outputs a pulse on the output out 2 . the amount by which the output of the charge pump increases or decreases depends respectively on the pulse widths of the outputs out 1 and out 2 . the delay module 214 delays a falling edge of a pwm pulse . the amount of delay is based on the output of the charge pump 212 . for example , the delay increases or decreases based on whether the output of the charge pump 212 increases or decreases . further , the amount by which the delay increases or decreases depends on the amount by which the output of the charge pump 212 increases or decreases . the inverting driver 216 inverts the output of the delay module 214 and outputs the inverted output of the delay module 214 to the gate of the low - side switch t ls . in use , when the high - side switch t hs is off and the low - side switch t ls is on , a rising edge of a pwm pulse is output to turn on the high - side switch t hs . the delay modules 206 and 214 receive the rising edge of the pwm pulse . the delay module 214 propagates the rising edge of the pwm pulse without delay . the inverting driver 216 outputs a falling edge to the gate of the low - side switch t ls , which turns off the low - side switch t ls . if the inductor current flows into the junction of the switches at that time , the voltage v lx starts to increase . the timing module 202 senses a time difference between a time at which the voltage v lx has risen and a time at which the gate - to - source voltage of the high - side switch t hs transitions and begins to fall ( i . e ., the gate turn - on transition of the high - side switch t hs ). the delay module 206 delays the gate turn - on transition of the high - side switch t hs based on the time difference to reduce this time difference , i . e ., the dead time . conversely , when the high - side switch t hs is on and the low - side switch t ls is off , a falling edge of a pwm pulse is output to turn off the high - side switch t hs . the delay modules 206 and 214 receive the falling edge of the pwm pulse . the delay module 206 propagates the falling edge of the pwm pulse without delay . the inverting driver 208 outputs a rising edge to the gate of the high - side switch t hs , which turns off the high - side switch t hs . if the inductor current flows out of the junction of the switches at that time , the voltage v lx starts to decrease . the timing module 210 senses a time difference between a time at which the voltage v lx has fallen and a time at which the gate - to - source voltage of the low - side switch t ls transitions and begins to rise ( i . e ., the gate turn - on transition of the low - side switch t ls ). the delay module 214 delays the gate turn - on transition of the low - side switch t ls based on the time difference to reduce this time difference , i . e ., the dead time . the delays generated by the delay modules 206 and 214 adjust ( reduce ) the dead times as shown in fig3 c . the delays , however , reduce the dead times only when the converter 200 operates in buck or boost ccm with a light load . the delays increase the dead times when the inductor current flows only out of the junction of the switches ( i . e ., when the converter 200 operates in buck ccm with a heavy load ) as shown in fig3 b and when the inductor current flows only into the junction of the switches ( i . e ., when the converter 200 operates in boost ccm with a heavy load ) as shown in fig3 d . referring now to fig4 a - 4d , a converter 300 that reduces dead times in various modes is shown . the converter 300 reduces dead times irrespective of load conditions . for example , the converter 300 reduces dead times when operating in buck ccm with a heavy load , buck or boost forced ccm with a light load , and boost ccm with a heavy load . in fig4 a , the converter 300 includes all of the components of the converter 200 shown in fig3 a except the delay modules 206 and 214 . the converter 300 further includes an additional feedback loop for the high - side switch t hs comprising a timing module 306 and a charge pump 308 and an additional feedback loop for the low - side switch t ls comprising a timing module 310 and a charge pump 312 . the converter 300 also includes a delay module 302 for the high - side switch t hs and a delay module 304 for the low - side switch t ls . the inputs of the delay modules 302 and 304 receive the pwm pulses from the pwm module 102 . the delay module 302 delays a rising edge of a pwm pulse based on the output of the timing module 202 and the charge pump 204 and delays a falling edge of a pwm pulse based on an output of the timing module 306 and the charge pump 308 . the delay module 304 delays a falling edge of a pwm pulse based on the output of the timing module 210 and the charge pump 212 and delays a rising edge of a pwm pulse based on an output of the timing module 310 and the charge pump 312 . the connections and functions of the timing module 202 , the charge pump 204 , the timing module 210 , and the charge pump 212 are the same as in the converter 200 . the connections and functions of the timing module 306 , the charge pump 308 , the timing module 310 , and the charge pump 312 are as follows . in the feedback loop for the high - side switch t hs , the timing module 306 has an inverting input and a non - inverting input . the inverting input is connected to the junction of the switches , and the non - inverting input is connected to the gate of the high - side switch t hs . accordingly , the inverting input senses a falling edge of the voltage v lx at the junction of the switches , and the non - inverting input senses a rising edge of the gate voltage of the high - side switch t hs . suppose a rising transition of the gate voltage of the high - side switch t hs occurs at time t 1 , and a falling transition of the voltage v lx occurs at time t 2 . the timing module 306 has two outputs : out 1 and out 2 . if t 1 is before t 2 , the timing module 306 outputs a pulse having a pulse width ( t 2 − t 1 ) on the output out 1 , and out 2 is low . conversely , if t 2 is before t 1 , out 1 is low , and the timing module 306 outputs a pulse having a pulse width ( t 1 − t 2 ) on the output out 2 . the charge pump 308 has two inputs that respectively receive the outputs out 1 and out 2 of the timing module 306 , and an output that outputs a voltage that increases or decreases based on the outputs out 1 and out 2 of the timing module 306 . for example , the output voltage of the charge pump 308 increases when the timing module 306 outputs a pulse on the output out 1 and decreases when the timing module 306 outputs a pulse on the output out 2 . the amount by which the output of the charge pump increases or decreases depends respectively on the pulse widths on the outputs out 1 and out 2 . the delay module 302 delays a falling edge of a pwm pulse by an amount based on the output of the charge pump 308 . for example , the delay increases or decreases based on whether the output of the charge pump 308 increases or decreases . further , the amount by which the delay increases or decreases depends on the amount by which the output of the charge pump 308 increases or decreases . the inverting driver 208 inverts the output of the delay module 302 and outputs the inverted output of the delay module 302 to the gate of the high - side switch t hs . in the feedback loop for the low - side switch t ls , the inverting input of the timing module 310 is connected to the gate of the low - side switch t ls , and the non - inverting input is connected to the junction of the switches . accordingly , the inverting input senses a falling edge of the gate voltage of the low - side switch t ls , and the non - inverting input senses a rising edge of the voltage v d ( at the junction of the switches . suppose a falling transition of the gate voltage of the low - side switch t ls occurs at time t 1 and a rising transition of the voltage v lx occurs at time t 2 . the timing module 310 has two outputs : out 1 and out 2 . if t 1 is before t 2 , the timing module 310 outputs a pulse having a pulse width ( t 2 − t 1 ) on the output out 1 , and out 2 is low . if t 2 is before t 1 , out 1 is low , and the timing module 310 outputs a pulse having a pulse width ( t 1 − t 2 ) on the output out 2 . the charge pump 312 has two inputs that respectively receive the outputs out 1 and out 2 of the timing module 310 , and an output that outputs a voltage that increases or decreases based on the outputs out 11 and out 2 of the timing module 310 . for example , the output voltage of the charge pump 312 increases when the timing module 310 outputs a pulse on the output out 1 and decreases when the timing module 310 outputs a pulse on the output out 2 . the amount by which the output of the charge pump increases or decreases depends respectively on the pulse widths of the outputs out 1 and out 2 . the delay module 304 delays a rising edge of a pwm pulse by an amount based on the output of the charge pump 312 . for example , the delay increases or decreases based on whether the output of the charge pump 312 increases or decreases . further , the amount by which the delay increases or decreases depends on the amount by which the output of the charge pump 312 increases or decreases . the inverting driver 216 inverts the output of the delay module 304 and outputs the inverted output of the delay module 304 to the gate of the low - side switch t ls . in use , when a rising edge of the pwm pulse is received , the delay module 302 delays the rising edge according to the feedback received from the timing module 202 and the charge pump 204 , and the delay module 304 delays the rising edge according to the feedback received from the timing module 310 and the charge pump 312 . when a falling edge of the pwm pulse is received , the delay module 302 delays the falling edge according to the feedback received from the timing module 306 and the charge pump 308 , and the delay module 304 delays the falling edge according to the feedback received from the timing module 210 and the charge pump 212 . for example , suppose that the high - side switch t hs is off , the low - side switch t ls is on , and the delay modules 302 and 304 receive a rising edge of the pwm pulse to turn on the high - side switch t hs . suppose also that the inductor current i l flows out of the junction of the switches at that time . since the rising edge of the pwm pulse turns on the high - side switch t hs , the rising edge of the pwm pulse may be called a turn - on transition of the converter 300 . in the feedback loop of the high - side switch t hs , the gate - to - source voltage of the high - side switch t hs falls before the voltage v lx can rise . accordingly , at the inputs of the timing module 202 , time t 1 at which the gate - to - source voltage of the high - side switch t hs starts falling is before time t 2 at which the voltage v lx starts rising . in other words , the gate turn - on transition of the high - side switch t hs occurs earlier than a rising v lx transition . the output out 1 of the timing module 202 outputs a pulse of pulse width ( t 2 − t 1 ) at the output out 1 , and the output out 2 of the timing module 202 is low . the output voltage of the charge pump 204 increases proportionally to the pulse width ( t 2 − t 1 ). the delay module 302 delays the rising edge of the pwm pulse proportionally to the increase in the output voltage of the charge pump 204 . the process continues until the output voltage of the charge pump 204 rails at v dd . the amount of delay continues to increase and reaches a maximum value when the output voltage of the charge pump 204 rails at v dd . at this point the feedback loop of the high - side switch t hs is saturated . in the feedback loop of the low - side switch t ls , the gate - to - source voltage of the low - side switch t ls is falling , and the voltage v d ( is rising . suppose that at the inputs of the timing module 310 , time t 1 at which the gate - to - source voltage of the high - side switch t hs starts falling is later than time t 2 at which the voltage v lx starts rising . in other words , the gate turn - off transition of the low - side switch t ls occurs later than a rising v lx transition . the output out 2 of the timing module 310 outputs a pulse of pulse width ( t 1 − t 2 ) at the output out 2 , and the output out 1 of the timing module 310 is low . the output voltage of the charge pump 312 decreases proportionally to the pulse width ( t 1 − t 2 ). the delay module 304 decreases the delay of the rising edge of the pwm pulse proportionally to the decrease in the output voltage of the charge pump 312 . over several cycles ( i . e ., pwm pulses ) the amount of delay continues to decrease until a time difference between the times t 1 and t 2 becomes nearly zero . at this point , the dead time during the turn - on transitions of the converter 300 is nearly zero when the inductor current i l flows out of the junction of the switches at that time . in this manner , when the inductor current i l flows out of the junction of the switches during the rising edges of the pwm pulses ( i . e ., during the turn on transitions of the converter 300 ), the feedback loop of the high - side switch t hs saturates , and the feedback loop of the low - side switch t ls adjusts ( reduces ) the dead time during the rising edges of the pwm pulse ( i . e ., during the turn - on transitions of the converter 300 ). now suppose that the high - side switch t hs is off , the low - side switch tls is on , the delay modules 302 and 304 receive a rising edge of the pwm pulse to turn on the high - side switch t hs , and the inductor current i l flows into the junction of the switches at that time . in the feedback loop of the low - side switch t ls , the gate - to - source voltage of the low - side switch tls falls before the voltage v lx can rise . accordingly , at the inputs of the timing module 310 , time t 1 at which the gate - to - source voltage of the low - side switch t ls starts falling is before time t 2 at which the voltage v lx starts rising . in other words , the gate turn - off transition of the low - side switch t ls occurs earlier than a rising v lx transition . the output out 1 of the timing module 310 outputs a pulse of pulse width ( t 2 − t 1 ) at the output out 1 , and the output out 2 of the timing module 310 is low . the output voltage of the charge pump 312 increases proportionally to the pulse width ( t 241 ). the delay module 304 delays the rising edge of the pwm pulse proportionally to the increase in the output voltage of the charge pump 312 . the process continues until the output voltage of the charge pump 312 rails at v dd . the amount of delay continues to increase and reaches a maximum value when the output voltage of the charge pump 312 rails at v dd . at this point the feedback loop of the low - side switch tls is saturated . in the feedback loop of the high - side switch t hs , the gate - to - source voltage of the high - side switch t hs is falling , and the voltage v lx is rising . suppose that at the inputs of the timing module 202 , time t 1 at which the gate - to - source voltage of the high - side switch t hs starts falling is later than time t 2 at which the voltage v lx starts rising . in other words , the gate turn - on transition of the high - side switch t hs occurs later than a rising v lx transition . the output out 2 of the timing module 202 outputs a pulse of pulse width ( t 1 − t 2 ) at the output out 2 , and the output out 1 of the timing module 202 is low . the output voltage of the charge pump 204 decreases proportionally to the pulse width ( t 1 − t 2 ). the delay module 302 decreases the delay of the rising edge of the pwm pulse proportionally to the decrease in the output voltage of the charge pump 204 . over several cycles ( i . e ., pwm pulses ) the amount of delay continues to decrease until a time difference between the times t 1 and t 2 becomes nearly zero . at this point , the dead time during the turn - on transitions of the converter 300 is nearly zero when the inductor current i l flows into the junction of the switches at that time . in this manner , when the inductor current i l flows into the junction of the switches during the rising edges of the pwm pulse ( i . e ., during the turn - on transitions of the converter 300 ), the feedback loop of the low - side switch t ls saturates , and the feedback loop of the high - side switch t hs adjusts ( reduces ) the dead time during the rising edges of the pwm pulse ( i . e ., during the turn - on transitions of the converter 300 ). similar analysis can be obtained during a turn - off transition of the converter 300 ( i . e ., when a falling edge of a pwm pulse is output to turn off the high - side switch t hs ). the delays generated by the delay modules 302 and 304 adjust ( reduce ) the dead times when the converter 300 operates in various modes irrespective of load conditions as shown in fig4 b - 4d . in summary , the timing module 306 senses a time difference between a time at which the voltage v lx transitions and begins to fall and a time at which the gate - to - source voltage of the high - side switch t hs transitions and begins to rise ( i . e ., the gate turn - off transition of the high - side switch t hs ). the delay module 302 delays the gate turn - off transition of the high - side switch t hs by delaying the falling edge of the pwm pulse based on the time difference to reduce this time difference , i . e ., the dead time . the timing module 202 senses a time difference between a time at which the voltage v lx transitions and begins to rise and a time at which the gate - to - source voltage of the high - side switch t hs transitions and begins to fall ( i . e ., the gate turn - on transition of the high - side switch t hs ). the delay module 302 delays the gate turn - on transition of the high - side switch t hs by delaying the rising edge of the pwm pulse based on the time difference to reduce this time difference , i . e ., the dead time . the timing module 310 senses a time difference between a time at which the voltage v lx transitions and begins to rise and a time at which the gate - to - source voltage of the low - side switch t ls transitions and begins to fall ( i . e ., the gate turn - off transition of the low - side switch t ls ). the delay module 304 delays the gate turn - off transition of the low - side switch t ls by delaying the rising edge of the pwm pulse based on the time difference to reduce this time difference , i . e ., the dead time . the timing module 210 senses a time difference between a time at which the voltage v lx transitions and begins to fall and a time at which the gate - to - source voltage of the low - side switch t ls transitions and begins to rise ( i . e ., the gate turn - on transition of the low - side switch t ls ). the delay module 304 delays the gate turn - on transition of the low - side switch t ls by delaying the falling edge of the pwm pulse based on the time difference to reduce this time difference , i . e ., the dead time . referring now to fig5 a - 5d , additional converters that reduce dead times are shown . each of the converters operates in a particular mode and reduces dead times in the particular mode using a plurality but not all of the feedback loops shown in fig4 a . for example , in fig5 a , a converter 400 - 1 operating in boost ccm reduces dead times using only the delay module 302 , the timing module 306 , the charge pump 308 , the timing module 202 , and the charge pump 204 . in fig5 b , a converter 400 - 2 operating in buck ccm reduces dead times using only the delay module 304 , the timing module 310 , the charge pump 312 , the timing module 210 , and the charge pump 212 . in fig5 c , a converter 400 - 3 operating in boost mode reduces dead times using only the delay modules 302 and 304 , the timing module 306 , the charge pump 308 , the timing module 202 , the charge pump 204 , the timing module 210 , and the charge pump 212 . in fig5 d , a converter 400 - 4 operating in buck mode reduces dead times using only the delay modules 302 and 304 , the timing module 202 , the charge pump 204 , the timing module 310 , the charge pump 312 , the timing module 210 , and the charge pump 212 . referring now to fig6 a and 6b , a converter 500 comprising a plurality of gate sensors and a plurality of common - mode feedback modules is shown . in fig6 a , the converter 500 includes all of the components of the converter 300 shown in fig4 a . the converter 500 further includes gate sensors 502 and 504 and common - mode feedback modules 506 and 508 . the gate sensors 502 and 504 trip at gate - to - source voltages between the plateau voltages and gate - to - source threshold voltages of the high - side switch t hs and the low - side switch t ls , respectively . the common - mode feedback modules 506 and 508 prevent the charge pumps from railing to v dd . a plateau voltage is defined in practice as the gate - to - source voltage at which the transistor delivers a current substantially equal to the inductor current . the gate - to - source threshold voltage is a gate - to - source voltage at which the transistor turns on . the trip voltages of the gate sensors 502 and 504 may be adjusted between the plateau voltage and the gate - to - source threshold voltage based on the inductor current i l . for example , for light load , the trip voltage may be set closer to the gate - to - source threshold voltage , and for heavy load , the trip voltage may be set farther from the gate - to - source threshold voltage and closer to the plateau voltage . the adjustment of the trip voltages of the gate sensors 502 and 504 based on the inductor current i l further compensates for variations in dead time as a function of load current . in fig6 a , each of the common - mode feedback modules 506 , 508 includes a circuit that functions as a charge - injecting common - mode voltage controller . these modules prevent the charge pumps from railing to v dd or ground . in fig6 b , an example of a charge pump 550 is shown . the charge pump 550 includes current sources 552 and 554 and switches 556 and 558 . the switches 556 and 558 of a charge pump ( e . g ., one of the charge pumps 308 , 204 , 312 , or 212 ) are respectively connected to the outputs out 1 and out 2 of a corresponding timing module ( e . g ., one of the timing modules 306 , 202 , 310 , or 210 ) to which the charge pump is connected . throughout the present disclosure , the high - side switch t hs is shown as a pmos device , and the low - side switch t ls is shown as an nmos device for example only . instead , the high - side switch t hs can be an nmos device , and the low - side switch t ls can be a pmos device . accordingly , while polarities of various signals including pwm pulses , voltages , and currents are discussed throughout the disclosure according to examples shown , the polarities will be opposite if the high - side switch t hs is an nmos device , and the low - side switch t ls is a pmos device instead . the broad teachings of the disclosure can be implemented in a variety of forms . therefore , while this disclosure includes particular examples , the true scope of the disclosure should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings , the specification , and the following claims .