the invention has several distinctive features . the first feature is envelope detection ( 1 ), which is performed more efficiently and with greater sensitivity , because two circuits are used to detect the envelope . one of the circuits , the polarizing detector circuit ( 15 ) is used to polarize the other , the polarized detector circuit ( 14 ), ensuring that the polarized detector circuit ( 14 ) has higher accuracy at envelope demodulation ( 1 ). the second feature is given by using a low - pass filter ( 16 ) between the polarization signal going from the polarizing detector circuit ( 15 ) to the polarized detector circuit ( 14 ). the third feature is the generation of the reference signal from the attenuated envelope ( 10 ) via a voltage divider ( 17 ) and not directly from the detected envelope ( 7 ). the fourth feature is the use of a low - pass filter ( 18 ) to generate a reference signal ( 11 ) from the attenuated envelope ( 10 ) produced in the voltage divider ( 17 ). a fifth feature is the low - pass filter itself ( as shown in fig1 ), which is fed back with the demodulated data signal ( 12 ) of the circuit output ( 20 ). this feed - back enables to suppress rapid changes in the input signal ( 38 ) of the low - pass filter ( fig1 ), which must be filtered . thus , the - low pass filter produces an average signal ( 11 ) very close to the amplitude maximum high value of the signal being filtered , as shown in fig4 . the feed - back scheme is used in both instances of low - pass filters ; i . e . : both the polarization low - pass filter ( 16 ) and the average low - pass filter ( 18 ). the five features listed above can all be combined into a data detector circuit for rfids labels , featuring low power and high quality , or be used separately . the topology of the complete circuit in fig7 can be rearranged by hierarchical blocks . an example is shown in fig1 , where a new hierarchical block ( 43 ) is created including the polarized detector circuit ( 14 ) and the voltage divider ( 17 ). similarly , the polarized detector circuit ( 14 ) and the polarizing detector circuit ( 15 ) could be grouped into a single hierarchy , without changing the invention . therefore , it is important to realize that the inclusion of new hierarchical levels in the proposed invention does not modify the invention . it is important to observe that some blocks could be implemented differently than proposed . for example , there are several ways to implement a voltage divider , not all resistive as shown in fig1 . similarly , there are several known implementations of low - pass filters different from that shown in fig1 . using equivalents modules for the proposed features does not characterize different invention . consider an example of signal processing through the complete circuit shown in fig1 , fig1 shows the ratio between the received signal envelope ( 45 ) and the envelope detected ( 49 ) by the polarizing detector circuit ( 15 ). note that the received signal has an upper envelope ( 45 ) and a lower envelope ( 46 ). the envelope detected ( 49 ) by the polarizing detector circuit ( 15 ) has a difference in potential very close to the threshold voltage of the pmos transistor ( 31 ) of the polarizing detector circuit ( 15 ). thus , the difference between the maximum high value ( 47 ) of an upper envelope ( 45 ) of the received signal and the maximum high value ( 50 ) of the envelope detected by the polarizing detector circuit ( 15 ) corresponds to the threshold voltage of the pmos transistor ( 31 ) of the polarizing detector circuit ( 15 ). similarly , the difference between minimum high value ( 48 ) of the upper envelope ( 45 ) of the received signal and the minimum high value ( 51 ) of the envelope detected ( 49 ) by the polarizing detector circuit ( 15 ) corresponds approximately to the threshold voltage of the pmos transistor ( 31 ) of the polarizing detector circuit ( 15 ). fig1 shows the ratio between the envelope of the received signal ( 45 ) and the envelope detected ( 52 ) by the polarized detector circuit ( 14 ). note that the received signal has a highcr an upper envelope ( 45 ) and a lower envelope ( 46 ). the envelope detected ( 52 ) by the polarized detector circuit ( 14 ) has a maximum high value ( 53 ) very close to the maximum high value ( 47 ) of the upper envelope ( 45 ) of the received signal . the envelope detected ( 52 ) by the polarized detector circuit ( 14 ) has a minimum high value ( 54 ) very close to zero . fig1 shows the polarization average ( 55 ) calculated by the polarization low - pass filter ( 16 ) from the envelope detected ( 49 ) by the polarizing detector circuit ( 15 ). note that the average polarization value ( 56 ) is very close to the maximum high value ( 50 ) of the envelope detected ( 49 ) by the polarizing detector circuit ( 15 ). fig1 shows the reference average ( 60 ) calculated by the reference low - pass filter ( 18 ) from the envelope detected ( 52 ) by the polarized detector circuit ( 14 ) attenuated by 75 % ( 57 ). the envelope detected ( 52 ) by the polarized detector circuit ( 14 ) is attenuated by 75 % through the voltage divider ( 17 ) generating an attenuated envelope ( 57 ) by 75 %. the reference average ( 60 ) calculated by the reference low - pass filter ( 18 ) from the envelope attenuated ( 57 ) by the voltage divider circuit ( 17 ). note that the reference average value ( 61 ) is very close to the maximum high value ( 58 ) of the envelope attenuated ( 57 ) by the voltage divider circuit ( 17 ). fig1 shows the calculation of the detected data ( 67 ) from the envelope detected ( 52 ) by the polarized detector circuit ( 14 ) and the reference average ( 60 ). note that the reference average value ( 61 ) is in an intermediate position related to the maximum high value ( 53 ) and minimum high value ( 54 ) of the envelope detected ( 52 ) by the polarized detector circuit ( 14 ). when the detected envelope ( 52 ) crosses the reference average ( 60 ) in the negative direction ( 62 ), the detected data has a high - to - low transition ( 64 ). when the detected envelope ( 52 ) crosses the with the reference average ( 60 ) in the positive direction ( 63 ), the detected data has an low - to - high transition ( 65 ). thus , it is possible to decode “ 1 ” ( 67 ) and “ 0 ” ( 66 ) binary states as encoded in the input signal . note that in countries allowing method claims , this example allows to claim a method where signals are processed according to the above sequence , regardless the circuit or device that implements the method .