fig1 shows , in block diagram form , a prior art random access memory ( ram ) circuit coupled to a testing apparatus tor burn - in testing of the circuit . in fig1 the ram circuit 10 to be subjected to burn - in will , for purposes of example only , be assumed to be a standard , prior art , static random access memory ( sram ) array containing a memory cell array 12 having the usual , word and bit decoders , driver circuits and sense amplifiers , etc . therewith . the array 12 further has a plurality of inputs including , an internal address line input 14 , a data - in input 16 , and a set input 17 and also has a pair outputs which include a data line output 19 and a dummy bit line output 18 . the internal address line input 14 is coupled , through an address generator 20 , to an internal self reset circuit 21 and thence through a clock receiver 23 to an external clock 24 . typically , under burn - in test conditions , the external clock is relatively slow and its pulses will cyclically power up and power down , i . e ., turn on and turn off , the sram 10 and the output latch once every 200 nanoseconds . the internal address line input 14 is further coupled , through the address generator 20 , the self reset circuit 21 and a first control receiver 25 to controller inputs 26 . the internal address lines input 14 is also coupled , through the address venerator 20 , to an address input 28 through a second receiver 27 . the array input 16 is coupled through a data receiver 30 to the array input / output data node 33 . the set input 17 of the array 12 is coupled through a sense amplifier / set circuit 29 to the dummy bitline output 18 of the array 12 . the sense amplifier / set circuit 29 also has an output 34 ( setg ) coupled to a first input of a first data latch 31 . the output 18 of the array 12 is coupled to a second input of this first data latch 31 . with reference now to fig1 and 2 , a burn - in test of a prior art sram will be discussed below . broadly , the chip 10 , is subjected to a burn - in test , by placing the chip in a suitable heating apparatus or oven , heating the chip to a selected temperature and operating the chip through a selected series of operations . such burn - in testing is well known and widely practiced in the art . once the chip reached the selected burn - in temperature , then at the start of the next external clock signal k 0 from the clock 24 , there is venerated at the output of the self reset circuit 21 a self - resetting signal pulse clki , as shown in fig3 . this pulse clki strobes the address inputs of the address true / compliment generator circuit 20 to create self - resetting address true / compliment pairs ( addt / c ) ( not shown in fig2 ) which are then provided to the sram array 12 , at via the internal address line input 14 to access the array data . at this time the self reset circuit , being driven by an internal clock ( not shown ) resets itself in typically within 3 to 5 nanoseconds and , once reset , will not be reactuated until a new clock signal k 1 is received . in some sram embodiments special timing chains are used to synchronize the sram &# 39 ; s sense amplifiers with the arrival of data from the array . in this instance , the array 12 generates signals , dumwl ( dummy wordline ) and dumbl ( dummy bitline ), internally that are used to generate , in the set circuit 29 , signals set and setg . the signal set is sent to the set input 17 to activate the sense amplifiers , in the array and thereby allow data to propagate , through output 19 , onto the data lines ( dl ) and subsequently the output latches 31 and 32 and thence to the chip output ( dq ) at node 33 . in detail , this test sequence of the prior art sram 10 during burn - in is as follows . the external clock 24 is running continuously and is sending 200 nanosecond clock cycles k to the clock receiver circuit 23 . each clock cycle k is for the first half of its cycle ( 100 nanoseconds ) positive or high and for the second half of its cycle ( 100 nanoseconds ) negative or low . when the tester indicates that a test is to begin , the rising , leading edge of the positive , first half of the cycle of the next clock signal k 0 , from clock 24 initiates , in the clock receiver circuit 23 , a positive pulse kclki which is sent to the self reset circuit 21 . when the rising , leading edge of the positive pulse kclki is received by the self reset circuit 21 , the self reset circuit 21 is conditioned to pass a single , 3 nanosecond positive pulse clki , initiated by the controller 26 , to the address generator 20 . as is well known to the art , when the sram 10 is turned on , a fast internal clock ( not shown ) having a cycle time , typically of about 3 to 5 nanoseconds , is activated therein and this internal clock signal is fed back to the self reset circuit 21 so that the self reset circuit 21 and the full sram is reset to await a news external clock signal . this pulse clki sets the address generator 20 in condition to pass , for 3 nanoseconds , a selected address signal addt / c , from the address input 28 , to the array 12 , via the internal address line input 14 to activate selected devices in the array 12 . with the selected address , the dummy wordline 12a , in the array 12 , sends a positive pulse dumwl to the dummy bitline 12b which now sends a negative pulse dumbl through an output 18 to the sense amplifier / set circuit 29 . the pulse dumbl causes the circuit 29 to send a signal set ( not shown in fig2 ) to the array 12 , via input 17 . signal set permits the sense amplifiers in the array 12 to send data , via the data line output 19 to the latch 31 . simultaneously , the set circuit 29 also send a positive signal setg ( not shown in fig2 ) to the first data latch 31 permitting the data latch 31 to pass the received data ( pulse dl ) to the second latching circuit 32 which goes high as shown by the positive pulse da . because the sram 10 is self resetting and each cycle therein is initiated by leading edge of the external clock cycle k , no additional pulse sequences occur until the entire 200 nanosecond external clock cycle k 0 ends and a new clock cycle , k 1 begins and the above described test sequence is repeated . this new clock cycle k 1 is also simultaneously sent to the latch 32 to unlatch it . when the latch 32 unlatches , the data is sent off chip via the input / output node 33 . in this instance , the positive pulse dq indicates that the tested address as good . conversely , if the data sent off chip does not match the expected data then it means that a failure has occurred in the sram . as discussed above , the tested devices , in the array , are active for only about 3 nanoseconds , i . e ., during the entire 200 nanosecond cycle of the system clock and inactive , i . e ., in the reset mode , for 197 nanoseconds of the system clock cycle time . thus , the prior art array devices now available cannot and are not evenly stressed during a burn - in test . the present invention is designed to relieve such uneven stressing of the self resetting devices during burn - in and accomplices this adding , to the sram circuit as will be discussed below in conjunction with fig3 special reset and data compare circuits with selective feedback paths . fig3 sets forth , in a block diagram , an improved random access memory ( ram ) designed in accordance with the present invention . for purpose of example only , this array will again be assumed to be a static random access memory ( sram ). it should be further noted , however , the present invention can be used with any type of random access memory , static or dynamic , a logic unit or a microprocessor , in either module or chip form . the improved sram of the present invention , as shown in this fig3 has a plurality of circuit elements that are identical to the circuit elements of fig1 but is different from that shown in fig1 by including an additional restore logic circuit and a compare latching circuit . those elements , in fig3 that are identical to the elements of fig1 are identified with the same numerals that were used in fig1 . thus , this improved sram 110 contains a memory cell array 12 having the usual , word and bit decoders , driver circuits and sense amplifiers , etc . therewith . the internal address line input 14 is again coupled , through the address generator 20 , to the self reset circuit 21 and thence through a three input , single output , 2 : 1 multiplexor circuit 22 , which forms a portion of the newly added restore logic circuit 36 , to the clock receiver 23 and the external clock 24 . again , under test conditions , the external clock is relatively slow and its pulses will cyclically power up and power down , i . e ., turn on and turn off , the sram 110 and the output latch , once every 200 nanoseconds . the internal address line input 14 is also again coupled , through the address generator 20 , the self reset circuit 21 and the first control receiver 25 to the control inputs 26 . the internal address line input 14 is also coupled , through the address generator 20 , to the address input 28 through the second receiver 27 . the array input 16 is again coupled through the data receiver 30 to the array input / output data node 33 . the set input 17 of the array 12 is again coupled through the sense amplifier / set circuit 29 to the dummy bitline output 18 of the array 12 . however , the sense amplifier / set circuit 29 now has its output 34 ( setg ) coupled not only to a first input of the first data latch 31 but also to input 22b of the multiplexor circuit 22 in the restore logic circuit 36 via line 34a . the restore logic circuit 36 , as shown in fig3 comprises , in addition to the multiplexor circuit 22 , discussed above , a single input , single output counter 38 , a two input , single output comparator 39 and a two input , two output reset logic circuit 40 . the counter 38 is set to a preselected number equal to the times the device is to be recycled during the first half of the external clock pulse . during the typical 200 nanosecond external clock pulse this number can typically range between 2 and 32 but can be in excess of 32 . the counter 38 is coupled between the output 22d of the multiplexor 22 and a first input 39a of the second comparator circuit 39 . the stop count line 35a , leading from the jtag test logic circuit 35 , is connected to the other input 39b of the comparator 39 . the output 39c of the comparator 39 is coupled to a first input 40a of the reset logic circuit 40 . the burn - in multi - mode line 35b leading from the jtag test logic circuit 35 is connected to the second input 40b of the reset logic circuit 40 and to the input 43c of the multiplexor 43 . the output 40c of the reset logic circuit is coupled to the input 22c of the multiplexor 22 . the output 19 , in addition to being coupled to data latch 31 , is also coupled to the compare latching circuit 37 . this compare latching circuit 37 comprises a three input , single output compare / inverting circuit 41 , a three input single output look aside latch circuit 42 and a three input , single output , multiplexor 43 . specifically the data output 19 , of the array 12 , is now coupled to the input of the first data latch 31 and to the look aside latch 42 . the outputs of both latches 31 and 42 are coupled to the multiplexor 43 and to the compare / invert circuit 41 which has its output coupled back to the look aside latch 42 . the latching circuit 37 comprises a two input , single output data latch 31 and a three input , single output , look aside latch 42 . each of these latches have their outputs coupled to the node 33 via a three input , single output , multiplexor 43 , and to a single input , single output , buffer / latch 32 . the first and second inputs , 43a and 43b , of the multiplexor 43 , as well as being coupled to the respective outputs of the data latch 31 and the look aside latch 42 are further respectively coupled to inputs , 41b and 41a , of the comparator / inverter circuit 41 . broadly speaking , the sram 110 , of the present invention is tested as will be described below and in conjunction with fig3 and 4 . for purposes of this description , it will be assumed that the chip is being subjected to burn - in and further that the jtag test logic circuit 35 has been loaded with a counter value ( vsc ) which is sent , via line 35a , to signal a stop to the cycle multiplying signal as will be further discussed below . the jtag test logic circuit 35 can also be loaded with special instructions designed for other purposes . while in the burn - in mode , the sram receives , from the external clock 24 , a 200 nanosecond clock pulse k 0 that passes through the multiplexor 22 to generate at the output of the self reset circuit 21 a signal pulse clki that is used to strobe , at input 26 , the address inputs ( addi ) ( not shown in fig4 ) being emitted by the address input 26 through the true / compliment address generator circuit 20 to create self - resetting address true / compliment pairs ( addt / c ) ( not shown in fig4 ) which are then provided to the sram array 12 , at internal address line input 14 , to access the selected memory cells in the array 12 . if necessary , special timing chains can be used to synchronize the sram &# 39 ; s sense amplifiers with the arrival of data from the array . in this instance , the dummy wordline ( dumwl ) and dummy bitline ( dumbl ) signals appear at the array output 19 and are sent to the set circuit 29 to generate in the set circuit the signals set ( not shown in fig4 ) and setg ( not shown in fig4 ). the signal set is fed to array input 17 and used to activate the array sense amplifiers and thereby allow data to propagate onto the data lines ( dl ), at output 19 , and subsequently through the two stages of output latching to the chip input / output data node 33 . simultaneously the signal setg is fed back , via line 34a , to the multiplexor 22 which is positioned between the clock input . the setg signal is here multiplexed , with the primary clock signal k 0 , to substitute for the clock input from external clock 24 during the burn - in mode . the key issue , for the present invention , is the routine of the signal setg that indicates that data has been read out of the array and that another sram cycle can start . it is this signal setg , which is used , in conjunction with the restore logic circuit 36 , to use the normal self setting action of the sram to initiate multiple internal test cycles in a single external cycle . the signal setg does this by controlling the multiplexor 22 such that the sram will recycle the predetermined number of times set in the restore logic circuit , counter 38 . fig4 illustrates , in greater , detail the operation of the invention , shown in fig3 . the jtag test logic circuit 35 is loaded and the burn - in mode becomes active and remains so for the selected burn - in duration . the signal kcontrol from the output 40c of the reset logic circuit 40 is initially low , allowing the primary system clock 24 , signal k 0 , as shown in fig4 in conjunction , with the restore logic circuit 36 , to be passed through the 2 - 1 multiplexor 22 and supply a positive signal kclki to the self reset circuit 21 and to the counter 38 in the restore logic circuit restore logic circuit 36 . this positive signal kclki starts the counter 38 and simultaneously causes the self reset circuit 21 to initiate the first of a series of kclki pulses which are sent to the address generator 20 . at this same time the signals kcontrol and load are activated , by the reset logic circuit 40 , and respectfully sent to the multiplexor 22 , to the look aside latch 42 and the compare invert circuit 41 . the signal kcontrol now sets the multiplexor 22 such that its output signal kclki will be now be controlled by the signal setg , fed back via line 34a from the set circuit 29 , instead of being controlled by the primary system clock 24 . since the signal setg is low when the signal kcontrol goes active or high , the signal kclki goes low , making the sram &# 39 ; s clock input appear to have a faster cycle time . meanwhile , the first clki pulse strobes the address generator 20 permitting the addresses from the address input 26 to be sent to the sram array internal address line input 14 . these addresses generate , in the array 12 , dummy wordline ( dumwl ) and dummy bitline ( dumbl ) signals ( not shown ) and ultimately , via the set circuit 29 , the signal setg . by the time the signal setg goes high , the sram array 12 has already generated data shown here as the high signal dl . once data has been sent out of the array the array is ready to accept new address inputs at internal address line input 14 . thus , the sram can now be cycled again . the restore logic circuit , does this by sending a clock lockout signal kcontrol to input 22c of the multiplexor 22 enabling the 2 : 1 clock multiplexor 22 to lock out the external clock signal k and thereby pass control of the self reset circuit to the setg signal . the restore logic circuit does this by having the counter 38 send a signal through the comparator 39 to the reset logic circuit 40 which in turns sends the clock lockout signal to the multiplexor 22 . with the multiplexor 22 blocking the external clock signal , the internal clock signal setg fed back to the array , via the multiplexor 22 to the self reset circuit 21 which emits a new high pulse clki to the address generator 20 thereby launching a second address signal addt / c to initiate another full addressing cycle in the array . the setg signals appearing at the output 22d of multiplexor 22 are also sent to the counter 38 . the presence of this internally generated , clock signal setg , which is typically running at 3 nanoseconds per cycle , thus causes the array 10 to cycle at 3 nanoseconds per cycle . this cycling of the array 10 continues until the number of signals at the output 22d of the multiplexor circuit 22 equals the number preset in the counter 38 . when this occurs , the addressing cycles cease until the a ne external clock signal k sends a new kclki signal to the self reset circuit 21 . in this way the array 10 will continue to cycle on itself , i . e ., basically oscillating , until the number of pulses matches the number preset in the counter 38 . when the number of kclki pulses so match the number stored in the counter 38 , the counter 38 sends a signal ( not shown ) to the comparator 39 . when the comparator 39 receives this signal which matches the preset value ( vsc ), the reset logic circuit 40 is deactivated and the signal to input 22c of multiplexor 22 is set low to return control of the multiplexor 22 back to the external system clock 24 . it should be noted , the array &# 39 ; s address and control inputs only change with the external system clock . thus while the multiplexor 22 is under the control of the signal setg , each of the self - generated cycles will repetitively test the same address . in the example shown in fig4 during the first sram cycle a &# 34 ; 1 &# 34 ; is read out of the array 12 , at output 18 , onto the data lines ( dl ) and to the latches 31a and 42 . because , as noted above , the load signal to the look aside latch 42 and the compare invert circuit 41 is active or high , this data , on the data lines , will be latched into both the data latch 31 and the look aside latch 42 causing their outputs , coupled to inputs 43a and 43b respectively of the multiplexor 43 , to go high . after the first bit of data has been stored into the look aside latch the signal load is reset and isolates the data stored in the look aside latch 42 so that it can be compared to data resulting to subsequent clocking cycles clki . the multiplexor 43 is thus set such that data , in the latches 31 and 42 will not be passed to the node 33 and off the chip 10 until the next rising edge of the external system clock ( k ). if all the data resulting from each clki signal are all identical , i . e ., the data is either all positive or all negative , then , at the next rising of the external clock k signal , when the data is clocked off chip at node 33 it will indicate the tested region is good . however , if , during the second cycle , i . e ., after the signals kclki and setg both go high , as shown in fig4 the data read from the same address is a &# 34 ; 0 &# 34 ;, this indicates a burn - in fail , the data output line dl , from array output 19 goes low or inactive . because a &# 34 ; 1 &# 34 ; was previously stored in the look aside latch 42 , a mismatch occurs when this new data is compared to the data previously stored in the look aside latch 42 and an inverted signal inv from the compare invert circuit 41 goes high to invert the data stored in the look aside latch . the data inversion causes the fail to be detected when the look aside data is driven off the chip during the next external clock cycle k . the inv signal can only go high once for a given system or external clock cycle k . as shown in fig4 even if , in the third cycle the array reads the data as a &# 34 ; 1 &# 34 ; the look aside latch 42 being already be set by the inv signal prevents the third cycles data from being read and only a fail or low signal will be passed to the node 33 at the start of the next external clock cycle k . thus a fail will be detected when dq is driven low at the start of the next external clock cycle k 1 . by using the present invention as described above and shown in fig3 and 4 , it can be seen that multiple addressing cycles can be completed during the first half of the external clock cycle k where normally there would be only one . the total number of cycles possible , in this first half of the external clock cycle k , is determined by the length of the addressing cycles and the length of the clock cycle k . for example , an sram with a 3 nanosecond minimum addressing cycle can easily clock approximately thirty - three ( 33 ) times within the typical 200 ns ( 100 ns positive phase ) burn - in cycle . power restrictions of the burn - in equipment might limit the number of cycles to some value less than the maximum . by increasing the number of cycles , burn - in effectiveness has been increased . thus there has been described a clocked test apparatus that will more rapidly test semiconductor devices by utilizing , an internal clock in the device to cycle the device multiple times during each test clock cycle . thus the present invention causes the device , under test , to be cycled internally at a rate that is a multiple of the test clock cycle time . this results in a significant reduction in burn - in time and test cost . the invention also provides more efficient stressing of the device under test thus improving the reliability of the tested devices . this completes the description of the preferred embodiment of the invention . since changes may be made in the above construction and method without departing from the scope of the invention described herein , it is intended that all the matter contained in the above description or shown in the accompany ing drawings will be interpreted in an illustrative sense and not in a limiting sense . thus other alternatives and modifications will now become apparent to those skilled in the art without departing from the spirit and scope of the invention as set forth in the following claims .