referring to fig3 a circuit 100 is shown in accordance with a preferred embodiment of the present invention . the circuit 100 generally comprises a block 102 , a block 104 , a gate 106 , a gate 108 , a delay block 110 and a delay block 112 . a group write bar signal gwrtb is generally presented to an inverter 114 that presents a group write signal gwrt to an input 116 of the block 102 as well as to an input 118 of the gate 106 and to an input 120 of the gate 108 . an output 121 of the block 102 presents a signal , through an inverter 122 , to an input 124 and to an input 126 of the block 104 . an output 128 of the block 104 generally presents a write enable signal wr -- 1 to an input 130 of the gate 106 . similarly , an output 131 of the block 104 generally presents a write enable signal wr -- 0 to an input 132 of the gate 108 . a signal din is a data input signal that is generally presented to an input 134 of the gate 106 as well as to an inverter 136 . the output of the inverter 136 is generally presented to an input 138 of the gate 108 . an output 140 of the gate 106 represents a write data signal wdatab . an output 142 of the gate 108 represents a write data signal wdata . the write data signals wdata and wdatab represent signals that are generally gated by the write pass gates ( not shown ) to control writing to the memory array ( not shown ). the write data signals wdata and wdatab , in one example , may be active low signals . the output 140 is also generally presented to an input 144 of the delay block 110 . the output 142 may also be presented to an input 146 of the delay block 112 . an output 148 of the delay block 110 generally presents a signal wdatab &# 39 ; to an input 150 of the block 102 as well as to an input 152 of the block 104 . an output 154 of the delay block 112 generally presents a signal wdata &# 39 ; to an input 156 of the block 102 as well as to an input 158 of the block 104 . the block 102 generally comprises a gate 160 and a gate 162 . the output of the gate 160 is generally represented as a node n1 . the output of the gate 162 is generally represented as a node n2 . the gate 160 generally receives a first input from the input 116 and a second input from the node n2 . the gate 162 generally receives a first input from the input 150 , a second input from the input 156 and a third input from the node n1 . the gate 160 and the gate 162 are generally implemented as nand gates . however , other combinations of gates may be implemented to provide a set and reset or a set bar and reset bar latching function . the block 102 generally sets the state of the block 104 so that both the write enable signals wr -- 0 and wr -- 1 are active at the beginning of write . this allows the first write to drive either the write data signal wdata or wdatab low . after this occurs , the block 102 is generally reset and the block 104 generally controls the write data signals wdata and wdatab until the global write signal gwrtb is deactivated . the block 104 generally comprises a gate 164 and a gate 166 . the gate 164 generally receives a first input representing the signal wdata &# 39 ;, a second input representing the signal gwrt &# 39 ; and a third input from the gate 166 . the gate 166 generally has a first input from the gate 164 , a second input representing the signal gwrt &# 39 ; and a third input representing the signal wdatab &# 39 ;. the gate 164 and the gate 166 are shown generally implemented as nand gates . however , other gates may be used that in combination provide a set and reset or set bar and reset bar latching function . the block 104 generally presents the write enable signals wr -- 1 and wr -- 0 in response to the write data signal wdatab &# 39 ;, the write data signal wdatab and the signal gwrt &# 39 ;. the amount of delay presented from the delay blocks 110 and 112 determines the delay in the signals wdata &# 39 ; and wdatab &# 39 ; which in turn determines the delay in the signals wr -- 1 and wr -- 0 . the delay blocks 110 and 112 should generally be designed to provide a proper amount of delay such that the end of write signal is provided accordingly . the block 104 generally prevents the memory array from continuing to write the same data . for example , if a &# 34 ; 0 &# 34 ; is written to the memory array , the write data signal wdata is generally low and the write data signal wdatab would generally be high . the delayed write data signals wdata &# 39 ; and wdatab &# 39 ; would then reset the block 104 to a state where the next write must be a &# 34 ; 1 &# 34 ;. the block 104 generally stores the last state of the write data signals wdata and wdatab for a comparison to detect a transition on the data input line din during a write to the particular memory group ( i . e ., the signal gwrtb is generally active ). referring to fig4 a more detailed diagram of the delay block 110 is shown . the delay block 112 is generally implemented similarly to the delay block 110 . the delay block 110 is shown generally comprising an inverter 170 , an inverter 172 , a nor gate 174 and an inverter 176 . the input 144 is generally presented to the inverter 170 and to the nor gate 174 . an output of the inverter 170 is generally presented to the inverter 172 which presents an output to the nor gate 174 . the output of the nor gate 174 is generally presented to the output 148 through the inverter 176 . as a result , the delay block 110 generally presents a fixed amount of delay between the input 144 and the output 148 . the delay block 110 may be implemented as any delay which provides a fixed amount of delay between the transition between a one and a zero . it may not be required to delay the transition between a zero and a one . in addition , a variable or programmable delay may be implemented in place of the delay block 110 . the delay block 110 may be implemented as a memory cell to provide the appropriate delay . if the delay block 110 is implemented as a memory cell , an additional advantage of verifying that data can actually be written to the memory array may be realized since actual data has been written to a memory cell ( i . e ., the memory cell of the delay block 110 ). if the delay block 110 and the delay block 112 are implemented as a programmable delay , the circuit 100 may be adjusted after the fabrication process in order to meet particular design specifications . additionally , with the implementation of a programmable delay , the circuit 100 may be designed closer to the fabrication tolerances since the programmable delay elements 110 and 112 may be adjusted after the fabrication process . additionally , the implementation of programmable delay elements 110 and 112 may be used as a design tool to test the fabrication process by designing for aggressive tolerances and then increasing the delay until the circuit 100 functions properly . referring to fig5 a timing diagram of various nodes of the circuit 10 is shown . the signal gwrtb is generally shown as a waveform 200 , the signal din is generally shown as a waveform 202 , the node n1 is generally shown as a waveform 204 , the node n2 is generally shown as a waveform 206 , the signal gwrt &# 39 ; is generally shown as a waveform 208 , the write enable signal wr -- 1 is generally shown as a waveform 210 , the write enable signal wr -- 0 is generally shown as a waveform 212 , the signal wdatab is generally shown as a waveform 214 , the signal wdata is generally shown as a waveform 216 , the signal wdatab &# 39 ; is generally shown as a waveform 218 and the signal wdata &# 39 ; is generally shown as a waveform 220 . the timing diagram of fig5 generally illustrates the case of writing a &# 34 ; 1 &# 34 ; to the memory array at the beginning of write , followed by changing the state of the data input signal din to write a &# 34 ; 0 &# 34 ; during the write . generally , when writing a particular state to the memory array , the signal gwrtb transitions low at a time al , which is an active state . in response , the signal gwrt will transition high . while signal gwrtb was high , the block 104 was set to a state where n1 is high . in response , the signal gwrt &# 39 ; is low indicating that the write enable signals wr -- 1 and wr -- 0 are both at a high thus enabling writing either a &# 34 ; 1 &# 34 ; or a &# 34 ; 0 &# 34 ; to the memory array depending on the state of the data input signal din . additionally , when the signal gwrtb is high , the signal gwrt is low so that both the write data signals wdata and wdatab are generally driven high by the nand gates 106 and 108 . when the signal gwrtb transitions low , the signal gwrt transitions high . when the signal gwrt transitions high , either the signal wdata or wdatab is generally driven low by the nand gates 108 or 106 depending on the state of the data input signal din . the signals gwrt and gwrt &# 39 ; generally trigger the next event . when the signal gwrtb transitions low , the signal wdatab generally transitions low when a one is written to the memory array ( i . e ., timing point b1 ). when the signal wdatab transitions low , the signal wdatab &# 39 ; transitions low after the delay is satisfied ( i . e ., timing point c1 ) which generally resets the block 102 to the state where the node n2 is generally high and the node n1 is generally low ( i . e ., timing points d1 and e1 ). the signal gwrt &# 39 ; is in the proper state ( high ) allowing the block 104 to be reset . at the time e1 , data has generally been written to the memory cell . since the write data signal wdatab was a &# 34 ; 0 &# 34 ;, a &# 34 ; 1 &# 34 ; was generally written . at the time e1 , the latch 102 is generally reset and the node n1 generally causes transition on the node gwrt &# 39 ;, causing a &# 34 ; 1 &# 34 ; to be generally presented to the inputs of the gates 164 and 166 . the signal wdatab &# 39 ; is generally a &# 34 ; 0 &# 34 ; which generally sets the latch 104 to detect a data transition during a write . the next state that may be written to the array is &# 34 ; 0 &# 34 ;. since the signal wdatab &# 39 ; is a &# 34 ; 0 &# 34 ;, the signal wr -- 0 is generally set to a &# 34 ; 1 &# 34 ; and the signal wr -- 1 is generally set to a &# 34 ; 0 &# 34 ;. in this state , the only data that can be written is a &# 34 ; 0 &# 34 ; since gate 106 generally has a &# 34 ; 0 &# 34 ; on one input 130 ( which is the signal wr -- 1 ) and the gate 108 generally has a &# 34 ; 1 &# 34 ; on the input 132 ( which is the signal wr . sub . -- 0 ). the gates 104 , 106 and 108 are generally configured to detect a data transition during a write that generally occurs at time a2 . the end of the first write ( triggered by the high to low transition of gwrtb ) occurs in fig5 at the time h1 . the block 102 is now set in a state that generally only allows the signals wdata or wdatab to be driven low when the data input din changes state . referring to fig5 the next thing that happens at the time a2 is that the data input din changes state during a write . after this transition , the signal wdata is driven low at time b2 since a zero is written to the memory array . at time a2 there is generally a transition on the data input line din from a &# 34 ; 1 &# 34 ; to a &# 34 ; 0 &# 34 ;. the &# 34 ; 1 &# 34 ; to &# 34 ; 0 &# 34 ; transition on the data input line din generally causes the input 138 of gate 108 to transition from a &# 34 ; 0 &# 34 ; to &# 34 ; 1 &# 34 ;. this makes the output 142 of gate 108 transition from a &# 34 ; 1 &# 34 ; to a &# 34 ; 0 &# 34 ; at time b2 since the gate 108 has a &# 34 ; 1 &# 34 ; on the write enable signal wr -- 0 and the gwrt input is a &# 34 ; 1 &# 34 ;. after the delay through element 112 , the wdata &# 39 ; line transitions from &# 34 ; 1 &# 34 ; to &# 34 ; 0 &# 34 ; at the time c2 . when the signal wdata &# 39 ; transitions from a &# 34 ; 1 &# 34 ; to a &# 34 ; 0 &# 34 ; ( at the time c2 ) the latch 104 is generally reset through the gate 164 . the signal wdata resets the latch 104 so that at time d2 the signal wr -- 0 transitions to a &# 34 ; 0 &# 34 ;. at the time e2 the signal wr -- 1 transitions to a &# 34 ; 1 &# 34 ;. the next data transition that can be written to the array is a &# 34 ; 1 &# 34 ; because signal wr -- 1 is a &# 34 ; 1 &# 34 ; and the signal wr -- 0 is a &# 34 ; 0 &# 34 ;. generally , the transition of the signal wr -- 0 to a &# 34 ; 0 &# 34 ; at time d2 forces the signal wdata to a &# 34 ; 1 &# 34 ; through gate 108 at the time f2 , thus ending the write . the time between the time f2 and the time g2 is generally the delay for the write data delay element 110 . the time a3 is basically the end of write at which time the circuit is set up for the next write . at the time a3 the signal gwrtb is generally deactivated which may force the signal gwrt to a &# 34 ; 0 &# 34 ; ( or an inactive state ). when the signal gwrt transitions to &# 34 ; 0 &# 34 ;, the latch 102 is reset so that the node n1 transitions to a &# 34 ; 1 &# 34 ; at the time b3 . the transition of the latch 102 propagates through the gate 162 to force the node n2 to a &# 34 ; 0 &# 34 ; at the time c3 . when the node n1 transitions to a &# 34 ; 1 &# 34 ; at the time b3 , the signal gwrt &# 39 ; transitions to a &# 34 ; 0 &# 34 ; at the time d3 . when the signal gwrt &# 39 ; transitions to a &# 34 ; 0 &# 34 ;, the inputs of both the gates 164 and 166 transition to a &# 34 ; 0 &# 34 ; which generally forces the signals wr -- 1 and wr -- 0 to a &# 34 ; 1 &# 34 ; at the time e3 . the transition at the time e3 is only at the signal wr -- 0 because the signal wr -- 1 was already at a &# 34 ; 1 &# 34 ; for the example shown in fig5 . at the end of write , the block 104 is generally set to the state to detect the first write . specifically , the node n1 would be a high and the node n2 would be low . as a result , the signal gwrt &# 39 ; is a low at time d3 which forces both of the write enable signals wr -- 1 and wr -- 0 to a high . while the invention has been particularly shown and described with reference to the preferred embodiments thereof , it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention .