as noted above , silicide or a metal silicon alloy between the contact and the source - drain region of a finfet device acts to lower resistance . when the pc pitch is scaled beyond 64 nanometers ( nm ), a self - aligned contact ( sac ) is needed to avoid potential gate ( pc ) to contact ( ca ) shorts . however , because of the limitation in overlay control at sub 64 nm contacted poly pitch ( cpp ), the contact may land partially at the top of the epitaxially grown raised source drain ( rsd ), causing a further reduced contact area even for a given pitch scaling . embodiments of the systems and methods detailed herein relate to silicide formation that increases the conductivity path and thereby further reduces resistance when compared with conventional finfet fabrication . specifically , a pseudo - silicide silicide process uses a metal ( e . g ., titanium ( ti )) liner to form a u - shaped silicide ( the silicide is on the side of the gate as well as on top of the rsd . this extends the contact area toward the top of the gate as further discussed below ( e . g ., on the order of 5 times ) and alleviates the contact resistance increase that occurs due to scaling . fig1 - 12 illustrate cross - sectional views of intermediate structures involved in the finfet fabrication . fig1 illustrates an initial structure in the replacement gate process . a dummy gate stack comprising a dummy oxide 115 , dummy gate 120 , and hard mask 125 is patterned above a substrate 110 . sidewall spacers 130 are formed through a nitride spacer deposition ( e . g ., silicon nitride ( sin )) and reactive ion etch ( rie ) process . the fin cap or dummy oxide 115 is deposited by molecular layer deposition ( mld ) followed by deposition of silicon ( dummy gate 120 ). fig2 shows the result of completing two processes . a known process of epitaxially growing dual raised source drain ( rsd ) 135 is performed for fin merge . a liner 140 ( e . g ., ti ) is then conformally deposited , as shown in fig2 . this liner 140 may be 10 to 15 nanometers ( nm ) in thickness , for example , and serves as the material that forms a salicide , as described in further detail below ( see e . g ., fig1 ). a flowable oxide 145 is deposited over the liner 140 to result in the structure shown in fig3 . a high density plasma ( hdp ) oxide and nitride may be deposited followed by a chemical mechanical planarization ( cmp ) to open up the gate region and result in the structure shown in fig4 . the nitride may be deposited using an in - situ radical assisted deposition ( irad ) tool , for example . the cmp process may be a known poly - open cmp process . fig5 illustrates the intermediate structure resulting from removal of the dummy gate stack ( 115 , 120 , 125 ). a poly - silicon rie is performed to remove the dummy gate 120 followed by chemical oxide removal ( cor ) to remove the dummy oxide 115 . a high - k preclean may then be performed . fig6 shows the structure that results from a replacement metal gate fill process as known in the art , including the formation of an interfacial oxide layer ( not specifically shown ), the deposition of a high - k dielectric layer 155 ( e . g ., hafnium oxide ( hfo 2 )), one or more workfunction metals and barrier layers ( not specifically shown ), and a gate metal layer 150 ( e . g ., tungsten w ). the high - k dielectric layer 155 may alternately cover the sidewalls ( inside of sidewall spacers 130 ), as well . as shown in fig6 , additional etch may be used to remove the high - k dielectric layer 155 from the sidewalls prior to deposition of the gate metal layer 150 . the gate metal 150 is etched back and a cap material 160 ( e . g ., silicon nitride ( sin )) is deposited as shown in fig7 . the cap material 160 forms a dielectric cap for the self - aligned contact ( sac ) process . the dielectric cap material 160 is then polished to result in the structure shown in fig8 . an oxide deglaze process is used to remove the flowable oxide 145 ( the interlayer dielectric between the gates ) and expose the ti liner 140 to result in the structure shown in fig9 . an hfo 2 layer 165 is then deposited conformally over the liner 140 in the structure of fig1 to act as a self - aligned contact etch stop layer . fig1 shows the structure that results from re - deposition of an oxide interlayer dielectric ( ild ) 170 followed by sac rie to define the contact openings . this rie process removes exposed portions of the hfo 2 layer 165 while leaving the liner 140 . fig1 is the structure that results from deposition of the contact metal 180 ( e . g ., w ) in the etched portions of the ild 170 . a high - pressure deuterium anneal ( hpd2 ) at , for example , approximately 400 degrees celsius for approximately 30 minutes may be performed following the contact metal 180 deposition . this forms silicide 175 ( e . g ., ti silicide ) from the liner 140 ( e . g ., ti ). specifically , based on the silicon in the rsd 135 below the liner 140 and the silicon in the sidewall spacers 130 , silicide 175 is formed above the rsd 135 as well as along portions of the sidewall spacers 130 that are above the rsd 135 , as shown in fig1 . because of the processes discussed herein that facilitate retaining the liner 140 at both the sidewall of the gate as well as the bottom of the contact , the subsequently formed silicide 175 contact area with the contact metal 180 is increased and contact resistance is further decreased from that of conventional devices . a complimentary metal - oxide - semiconductor ( cmos ) device includes complementary and symmetrical pairs of n - type and p - type metal - oxide - semiconductor field effect transistors ( mosfets ). thus , the finfet device may include pfet and nfet regions . the nfet and pfet regions may be processed in the same way ( and as shown in fig1 - 12 ). fig1 and 14 illustrate additional processes that are specific to the pfet region of the finfet device . fig1 shows the structure that results from removal of the contact metal 180 from the structure shown in fig1 , followed by deposition of a nickel - platinum alloy ( nipt ) 185 . the nipt 185 is formed as shown in fig1 according to known processes of patterning using a hard mask layer . the nipt 185 has a lower contact barrier than the liner 140 ( e . g ., ti ) and , thus , provides lower resistance in the pfet region . the contact metal 180 is then re - deposited on the nipt 185 . thus , the finfet device includes an nfet region according to fig1 and a pfet region according to fig1 . in an alternate embodiment , rather than as additional processes , the processes of fig1 and 14 may be performed as alternate processes to those shown in fig1 and 12 in the pfet region . the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention . as used herein , the singular forms “ a ”, “ an ” and “ the ” are intended to include the plural forms as well , unless the context clearly indicates otherwise . it will be further understood that the terms “ comprises ” and / or “ comprising ,” when used in this specification , specify the presence of stated features , integers , steps , operations , elements , and / or components , but do not preclude the presence or addition of one more other features , integers , steps , operations , element components , and / or groups thereof . the corresponding structures , materials , acts , and equivalents of all means or step plus function elements in the claims below are intended to include any structure , material , or act for performing the function in combination with other claimed elements as specifically claimed . the description of the present invention has been presented for purposes of illustration and description , but is not intended to be exhaustive or limited to the invention in the form disclosed . many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention . the embodiment was chosen and described in order to best explain the principles of the invention and the practical application , and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated the flow diagrams depicted herein are just one example . there may be many variations to this diagram or the steps ( or operations ) described therein without departing from the spirit of the invention . for instance , the steps may be performed in a differing order or steps may be added , deleted or modified . all of these variations are considered a part of the claimed invention . while the preferred embodiment to the invention had been described , it will be understood that those skilled in the art , both now and in the future , may make various improvements and enhancements which fall within the scope of the claims which follow . these claims should be construed to maintain the proper protection for the invention first described . the descriptions of the various embodiments of the present invention have been presented for purposes of illustration , but are not intended to be exhaustive or limited to the embodiments disclosed . many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments . the terminology used herein was chosen to best explain the principles of the embodiments , the practical application or technical improvement over technologies found in the marketplace , or to enable others of ordinary skill in the art to understand the embodiments disclosed herein .