while components such as resistors can have significant variations due to process , supply voltage and temperature ( pvt ), on - chip these components tend to be consistent . for instance , a resistor specified as 10 - kω may in fact be a 10 . 5 - kω resistor due to pvt . however , all resistors specified as 10 - kω would tend to be around 10 . 5 - kω resistors on the same chip . while pvt variations can have a significant impact on the tolerances of many components , the variations tend to affect like components in the same way . fig4 illustrates a block diagram of a circuit which exploits a single high tolerance external reference component to provide local reference to a plurality of circuits . external reference component 402 is connected to chip 400 through pin 404 . calibration circuit 406 is coupled to pin 404 and compares it to a plurality of components 408 each manufactured with slightly different values . calibration circuit 406 matches one of the plurality of components to external reference component 402 whose characteristics best matches . the calibration circuit then transfers that information to at least one analog circuit 410 which requires this reference . analog circuit 410 selects from a corresponding component in plurality of components 412 , perhaps using a plurality of switches such as switches 414 . also , shown in the figure another analog circuit 420 with plurality of components 422 using plurality of switches 424 . furthermore , after the calibration is completed and any analog circuit requiring the use of the reference component has obtained the correct reference component from the calibration circuit . the results can be latched by analog bias circuit 410 and the calibration circuit can be shut off to save power . in the specific example given , the reference component used is a 10 - kω resistor . external reference component 402 is a 10 - kω resistor . suppose calibration circuit 406 determines that resistor 408 c , which was manufactured as a 9 . 5 - kω resistor , actually matches the 10 - kω external resistor . calibration circuit 406 sends a signal to analog circuit 410 to select resistor 412 c . similarly , calibration circuit 406 can also send a signal to analog circuit 420 to select resistor 422 c . it should be noted that resistor 408 c need not match the external reference component . as later demonstrated below , the resistor 408 c might be on a different scale completely but rely on the external reference component to provide a consistent reference voltage or current . for example , using a 10 - kω resistor calibration circuit 406 may have a reliable 100 μa current which can be used to test the plurality of components . suppose the desired internal component is a 12 - kω resistor , then the calibration circuit chooses the resistor which exhibits 1 . 2v when the 100 μa is drawn through it . fig5 illustrates a general method by which the circuits operate . at step 502 , the circuit waits until it reaches an equilibrium after powering up . this is to insure that factors such as temperature do not alter the comparison of the external component and the plurality of components . at step 504 , the calibration circuit compares an external component to one of a collection of on - chip components and the on - chip component best matching the desired characteristics of the external component is selected . at step 506 , the selection of this on - chip component is transmitted to all the other analog circuits requiring a reference , e . g . a bias circuit . each analog circuit can then select the corresponding on - chip component to the selected on - chip component . at step 508 , the selected corresponding on - chip component is then used for reference by the analog circuit . at step 510 , the choice of on - chip components is latched and the calibration circuit is powered down . in the specific example of fig4 , the external component is an off - chip resistor and the desired characteristic of the resistor is 10 - kω of resistance . though the chip and algorithm described above , select a single on - chip component most closely matching the characteristics of the reference external component , one could select more than one on - chip component to better match the reference external component . for example , if the external resistance lies between the resistance of resistor 408 e and 408 f , both may be selected yielding a resistance that is the harmonic average of the two resistances . one of ordinary skill in the art could develop new algorithms employing the selection of multiple components . the remainder of the disclosure illustrates the above concept in the context of current bias circuits and the use of resistors as the reference components , but it should be understood that the invention is applicable to other types of circuits , such as voltage bias circuits , and other reference components that would be apparent to one of ordinary skill in the art . a specific implementation of the general design is described . it should be noted that while the description is given in terms of very specific details , such as the use of polysilicon resistors , these details are given for the sake of example and should not be taken to limit the invention as described . fig6 is an example floor plan of a highly integrated rf or analog chip that includes the global bias calibration circuit . the bias calibration circuit is pictured in the upper left corner of the die ; however it can be located in whichever location is best for a custom floor plan . package pin 604 is a single pin reserved for the calibration circuit . high precision , off - chip resistor 602 is connected to pin 604 . the perimeter of the floor plan , just inside the pad ring , contains two pair of buses 650 and 652 of four signals carrying the calibration codes for two polysilicon resistors . calibration bus 650 is also labeled rpolyh_cal , corresponding to a high sheet resistance polysilicon resistor , and calibration bus 652 is also labeled rpolyl_cal corresponding to a low sheet resistance polysilicon resistor . the individual , customized local bias circuits for each of analog circuits 610 , 614 , 618 and 622 are bias circuits 608 , 612 , 616 , and 620 , respectively . each of these bias circuits reads the appropriate resistor calibration code from the rpolyh_cal or rpolyl_cal calibration buses . the bias circuit then uses these digital codes to calibrate the bias resistance and bias current close to the nominal value . the accuracy of the calibration matches the tolerance of the high precision off - chip resistor . the calibration codes , which are routed globally , are digital and therefore , they are not sensitive to common mode noise disturbances . in this way , the calibration is achieved globally across the full chip without coupling any noise between different analog circuits through the separate supply domains or the local bias circuits . fig7 illustrates a block diagram of the global bias calibration circuit . the architecture comprises programmable bandgap current source 704 and programmable band gap current source 706 referenced to two different on - chip resistor types . for one particular process , these are the high sheet resistance polysilicon resistor , rpolyh , and the low sheet resistance polysilicon resistor , rpolyl . the current from each of these programmable bandgap current sources is connected to high precision off - chip resistor 602 also labeled r 1 , through the package pin 604 which is also labeled vtest . digital state engine 710 sequences through a calibration algorithm which can be run at power up or after an spi write to initiate the algorithm . this algorithm is shown in the flow chart in fig9 and is described in more detail below . six - bit adc 708 compares the voltage at pin 604 to a set of reference voltages defined by an on - chip bandgap reference , and produces a representative digital code , adc & lt ; 5 : 0 & gt ;. this digital code is processed by digital state engine 710 and used to generate a sequence of trial calibration codes . the calibrated values , rpolyh_cal_gb & lt ; 3 : 0 & gt ; and rpolyl_cal_gb & lt ; 3 : 0 & gt ;, are the final calibration values and they are enabled by digital state engine 710 when the calibration algorithm is complete . the two signals rpolyh_cal_done and rpolyl_cal_done release the final calibrated values to the global resistor calibration bus , which is accessible to the full chip . fig8 shows a detailed schematic of the implementation of the each programmable band - gap current source such as programmable band - gap current source 704 and 706 . current source 800 consists of 1 . 2v bandgap voltage reference 802 which is independent of supply voltage , process , and temperature . this voltage is buffered by operational amplifier 804 with unity gain feedback copying the bandgap voltage to node v 1 . this node is then connected to an array of parallel resistors , each with a series switch . resistors 810 , 812 , 814 , 816 , 818 , 820 , 822 , 824 , and 826 are in series with switches 830 , 832 , 834 , 836 , 838 , 840 , 842 , 844 , and 846 , respectively . all of the resistors are implemented with the same resistor type , which is rpolyh in one implementation . the nine resistors all have resistance values that each differ by a small percentage covering a full range of +/− 12 %, which matches the sheet resistance tolerance for an rpoly resistor in a typical silicon process . the pmos current mirror consisting of transistors 806 and 808 copies the current generated by the bandgap voltage over the resistance and mirrors it over to the output i bias — cal ( in a rpolyh programmable band gap current source , this is labeled i_rph_bias , and in a rpolyl programmable band gap current source , this is labeled i_rpl_bias ). i bias — cal is then connected to package pin 604 . a test voltage is generated at package pin 604 when this current is turned on and connected to high precision , off - chip resistor 602 as shown in fig7 . the same topology is used for the rpolyl programmable band gap current source when all of the rpolyh resistors are replaced with rpolyl resistors . it should be noted that in this example , the reference resistor is 10 - kω , but the desired internal resistor is a 12 - kω resistor . fig9 illustrates a detailed flow chart of the calibration algorithm as implemented in digital state engine 710 . the digital state engine algorithm is used to generate the rpolyh_cal and rpolyl_cal calibration codes as shown in the decoder table of fig1 . for example , when the sheet resistance of the rpolyh resistors for a particular die is at 9 % above the nominal value as a result of process variation , the algorithm finds the calibration code rpolyh_cal & lt ; 3 : 0 & gt ;=‘ 0111 .’ this 4 - bit code can then be decoded by each local bias circuit and mapped to select a programmable resistance value to calibrate out the process variation . the calibration algorithm first begins by powering up and letting the chip settle into a state of equilibrium . more specifically , at step 902 , the power up of the chip begins and all circuits are activated . at step 904 , the chip is allowed to reach a thermal equilibrium . at step 906 , calibration circuit 606 is activated with a serial peripheral interface ( spi ) write . the algorithm then determines which rpolyh resistor has essentially the same resistance as reference resistor 602 . specifically , at step 908 , rpolyh programmable bias current source 706 is turned on and rpolyl programmable bias current source 704 is shut off . this current is then fed to the package pin 604 into high precision off - chip resistor 602 . digital state engine 710 expects the vtest voltage to be about 1 . 2v which corresponds to the nominal resistance value 10 kω . for an unknown tolerance on the resistance for a particular die , state engine 710 begins at step 910 by setting the rpolyh & lt ; 3 : 0 & gt ; setting to ‘ 0000 ’ for the minimum resistance . the programmable bias current source then selects the resistor corresponding to minimum resistance and maximum current ( for example if fig8 is the rpolyh programmable bias current source , resistor 810 is selected ). adc 708 closes a digital feedback loop by converting the measured voltage to a corresponding digital code , adc & lt ; 5 : 0 & gt ;. state engine 710 then compares this value to the desired value of ‘ 0x20 ,’ which represents the nominal resistance at step 912 . if the measured value of the vtest voltage is less than the desired value ( that is the value of adc & lt ; 5 : 0 & gt ; is less than ‘ 0x20 ’), the calibration procedure ends and the resistance setting is latched in as the calibration value at step 914 . if the measured value is greater than the desired value , state engine 710 increments the resistance setting at step 916 , which decrements the bias current following a successive approximation algorithm . at step 918 , state engine 710 then compares the vtest voltage value to the desired value of ‘ 0x20 ,’ which represents the nominal resistance . if the measured value of the vtest voltage is less than the desired value , the calibration procedure ends and the resistance setting is latched in as the calibration value at step 920 ; otherwise , the process repeats at step 916 . when the vtest voltage falls below the desired value , the state machine latches the calibration code by pulling rpolyh_cal_done high at either step 914 or step 920 . with the calibration for rpolyh resistance complete , polyh programmable current source 706 is turned off at step 922 . the algorithm then determines which rpolyl resistor has essentially the same resistance as reference resistor 602 . the process is similar to that of the preceding steps . specifically , at step 924 , rpolyl programmable bias current source 704 is turned on and rpolyh programmable bias current source 706 is shut off . this current is then fed to the package pin 604 into high precision off - chip resistor 602 . at step 926 , the state engine 710 sets the rpolyl & lt ; 3 : 0 & gt ; setting to ‘ 0000 ’ for the minimum resistance . the programmable bias current source then selects the resistor corresponding to minimum resistance and maximum current ( for example if fig8 is the rpolyl programmable bias current source , resistor 810 is selected ). adc 708 closes a digital feedback loop by converting the measured voltage to a corresponding digital code , adc & lt ; 5 : 0 & gt ;. state engine 710 then compares this value to the desired value of ‘ 0x20 ,’ which represents the nominal resistance at step 926 . if the measured value of the vtest voltage is less than the desired value ( that is the value of adc & lt ; 5 : 0 & gt ; is less than ‘ 0x20 ’), the calibration procedure ends and the resistance setting is latched in as the calibration value at step 928 . if the measured value is greater than the desired value , state engine 710 increments the resistance setting at step 930 , which decrements the bias current following a successive approximation algorithm . at step 932 , state engine 710 then compares the vtest voltage value to the desired value of ‘ 0x20 ,’ which represents the nominal resistance . if the measured value of the vtest voltage is less than the desired value , the calibration procedure ends and the resistance setting is latched in as the calibration value at step 934 ; otherwise , the process repeats at step 930 . when the vtest voltage falls below the desired value , the state machine latches the calibration code by pulling rpolyl_cal_done high at either step 928 or step 934 . with the calibration for rpolyl resistance complete , polyl programmable current source 706 is turned off at step 936 . the calibration algorithm can be restarted if conditions , such as temperature , change at step 938 . the process can go back to step 906 . however , if calibration is not restarted , bias circuit 606 can be shut off with an spi write at step 940 . fig1 is an example timing diagram of the resistor calibration sequence for a particular die . the example device has an rpolyh sheet resistance 9 % above the nominal value and an rpolyl resistance 6 % below the nominal value . on power - up the calibration circuit is off and the global resistor calibration buses , rpolyh_cal_gb & lt ; 3 : 0 & gt ; and rpolyl_cal_gb & lt ; 3 : 0 & gt ;, hold a reset value equivalent to the nominal resistance calibration setting of ‘ 0100 .’ the calibration circuit is enabled and the algorithm begins when cal_en is pulled high through spi write cycle , shown at the end of time period a . the rpolyh programmable bg bias circuit is turned on at the beginning of time period a with the bias resistor set to rpolyh & lt ; 3 : 0 & gt ;=‘ 0000 ’ corresponding to the minimum resistance . this corresponds to a bias current of 102 μa . this current is above the desired value of 100 μa corresponding to the nominal case . therefore , the vtest voltage is 1 . 028v , which is also above the desired value . the adc converts this voltage to a corresponding digital hexadecimal value of ‘ 0x22 following the adc mapping table shown in fig1 . state engine 710 reads this adc code and compares it to the desired value of ‘ 0x20 ,’ representing the nominal value . since the measured voltage is above the desired value , state engine 710 increments the calibration resistance by setting rpolyh_cal & lt ; 3 : 0 & gt ; to ‘ 0001 ’ which incrementally reduces the bias current . the i_rph_bias current is now 99 . 2 μa at the beginning of time period c and the vtest voltage has gone down to 0 . 992v . the adc reads the new input voltage and produces a corresponding output code of ‘ 0x1f .’ the state machine compares ‘ 0x1f ’ to the desired ‘ 0x20 ’ and determines that the bias current has now dropped just below the desired nominal value . calibration of the rpolyh resistors is then completed when the state machine pulls rpolyh_cal_done high and latches the rpolyh_cal & lt ; 3 : 0 & gt ; value onto the rpolyh_cal_gb & lt ; 3 : 0 & gt ; bus . the bias current at a local bias circuit using rpolyh resistor ( i bias — local_rph ) then increases from its uncompensated value of 91 μa to 99 . 2 μa at the end of time period c . at the end of time period c , the state machine shuts off the rpolyh programmable bias circuit and i_rph_bias drops to zero . at the same time , the state machine turns on the rpolyl programmable bias circuit and i_rpl_bias jumps up to its maximum value of 118 μa . from time period d through time period j , the state machine repeats the successive approximation algorithm for the rpolyl resistance . afterwards , the calibration value is latched onto the rpolyl_cal_gb & lt ; 3 : 0 & gt ; global bus and both local bias currents are fully calibrated . the decoder in the local bias circuit reads the rpolyl_cal_gb & lt ; 3 : 0 & gt ; code and selects its bias resistance such that the bias current at a local bias circuit using rpolyl resistor ( i bias — local_rpl ) current jumps from 106 ua down to 99 . 6 ua . at the end of the calibration procedure , both programmable bias current sources , i_rph_bias and i_rpl_bias are turned off and their currents drop to zero . at the same time the vtest voltage drops to zero and all of the calibration circuits other than state engine 710 are turned off including the adc . in this way , the steady state current after the calibration algorithm is complete is zero . fig1 shows an example mapping table for the 6 - bit adc . the full scale range of the converter is 630 mv and is centered around an input voltage of 1v , which corresponds to the voltage on package pin 604 under nominal conditions . the 6 - bit resolution is equivalent to 10 mv and the full scale range is centered on the desired input voltage range . an example local bias circuit is shown as the ptat bias in fig1 . cross coupled npn transistors 1252 ( q 1 ), 1254 ( q 2 ), 1256 ( q 3 ), and 1258 ( q 4 ) establish a δv be voltage across the bias resistor array comprising resistors 1210 , 1212 , 1214 , 1216 , 1218 , 1220 , 1222 , 1224 , and 1226 , creating a ptat current through transistor 1262 ( m 1 ). this ptat current is then copied over to the current source 1264 ( m 2 ) by the pmos current mirror . the resistor array and decoder 1250 enable calibration of the ptat bias circuit when the circuit is programmed with the calibration codes from the global bias calibration circuit . these codes are easily accessible to each local bias circuit in the full chip by connecting to the rpoly calibration bus as shown in fig6 . fig1 shows an example decoder mapping table for each local bias circuit . each rpolyh & lt ; 3 : 0 & gt ; code corresponds to an equivalent measured sheet resistance tolerance . the nominal value corresponds to ‘ 0100 .’ the decoder within each local bias circuit maps this input code to select an appropriate programmable resistor from the array shown in fig1 to bring the actual resistance back to the nominal value . in the example case shown in fig1 , the rpolyh sheet resistance was measured to be 9 % above the nominal value . therefore , the bias circuit decoder selects the r b - 9 % resistor from the parallel resistor array to bring the effective resistance back to the nominal value in the presents of process variation . the solution provided here can also be expanded to produce precise transconductances for gmc filters and precise reference voltage / current for op amps and data converters , and henceforth to make these analog / mixed - signal circuits less dependent on process variation . the gmc filter using precise control of bias currents can provide accurate control of poles for accurate frequency response . op amps designed using the solution provided here for precise bias current can make the open - loop gain and phase margin well controlled in the target region so robust and high gain and large unit gain bandwidth ( ubw ) op amps can be achieved . precise reference voltages / currents provided by this solution minimize the snr degradation of analog - to - digital converters due to reference errors and large gain / ubw variations of op amps . the solution offered here can be used to minimize the current variation due to process , voltage , and temperature . in this way , the worst case power dissipation for the chip is very close to the nominal power dissipation under all pvt conditions . the result is a 10 - 15 % lower power budget for the chip , which is a significant improvement for extremely low power applications such as usb and battery powered devices . the chip would only require one high precision (≦+/− 1 %) off - chip resistor with a flexible pin location for this resistor with no effect on the noise performance of the analog circuits within chip . because the calibration takes place during the power - up sequences the calibration codes can be latched and calibration circuit powered off , hence no additional steady state power consumption is added . the chip is self calibrating requiring no operation to be performed in the factory or no non - volatile memory to store calibration codes . other advantages of this solution would no doubt be apparent to one of ordinary skill in the art . furthermore , the applications of this solution have great applicability in tuners with extremely low power dissipation in a wide range of applications including cable , satellite , and terrestrial tv . the solution is applicable in any analog , rf , or mixed - signal ic products in which multiple bias circuits are used for biasing different circuit blocks within the ic . this solution is also applicable in many different semiconductor process technologies and feature sizes , including cmos , bicmos , and bipolar . additional applications would no doubt be apparent to those of ordinary skill in the art . it should be emphasized that the above - described embodiments are merely examples of possible implementations . many variations and modifications may be made to the above - described embodiments without departing from the principles of the present disclosure . all such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims .