fig1 shows a block diagram of the dfe 101 combined with a feed - forward filter ( fff ) 100 . the fff 100 , having filter coefficients w ( n ) where n is the sample number , rejects pre - cursors , while the feedback filter ( fbf ) 102 eliminates post - cursors of the channel impulse response . if the sampled channel impulse response is h ( n ), then the feedback filter coefficients b ( n ) satisfy b ⁢ ( n ) = h ⁢ ( n ) h ⁢ ( 0 ) , n & gt ; 0 . after the fbf removes post - cursors , only the channel impulse response is left in the pre - cursors . then , the received signal at the equalizer input , represented by x ( n ), is as follows : x ⁢ ( n ) = ∑ i = - ∞ 0 ⁢ h ⁢ ( i ) ⁢ a ⁢ ( n - i ) where a ( i ) represents transmitted , noiseless data . if the feed - forward filter has n taps and the indexes of the taps decrease from the right - most main tap with index n − 1 , then the filtered output , â ( n ), is obtained as follows : a ^ ⁡ ( n ) = ∑ i = 0 n - 1 ⁢ w ⁡ ( n - i - 1 ) ⁢ x ⁡ ( n + i ) = ∑ i = 0 n - 1 ⁢ w ⁡ ( n - i - 1 ) ⁢ ∑ j = - ∞ 0 ⁢ h ⁡ ( j ) ⁢ a ⁡ ( n + i - j ) = ∑ i = 0 n - 1 ⁢ w ⁡ ( n - i - 1 ) ⁢ ∑ j = 0 ∞ ⁢ h ⁡ ( - j ) ⁢ a ⁡ ( n + i + j ) . after substitution of the sum of the indexes i + j by a new index k , the above equation is reduced to a ^ ⁢ ( n ) = ∑ k = 0 ∞ ⁢ a ⁢ ( n + k ) ⁢ ∑ j = 0 k ⁢ w ⁢ ( n - k + j - 1 ) ⁢ h ⁢ ( - j ) . the output of the feed - forward filter , â ( n ), is equal to a ( n ) when perfect equalization is achieved . under the zero - forcing condition , the terms in the above equation should be zeros except when k is equal to zero . w ⁢ ( n - 1 ) ⁢ h ⁢ ( 0 ) = 1 ∑ j = 0 k ⁢ w ⁢ ( n - k + j - 1 ) ⁢ h ⁢ ( - j ) = 0 , k ≠ 0 . where the main tap and the adjacent tap coefficients of the feed - forward filter are represented by the channel impulse response , h ( n ), as follows : w ⁡ ( n - 1 ) = 1 h ⁡ ( 0 ) w ⁡ ( n - 2 ) = - w ⁡ ( n - 1 ) ⁢ h ⁡ ( - 1 ) h ⁡ ( 0 ) = - h ⁡ ( - 1 ) h ⁡ ( 0 ) 2 . by combining the coefficients of the main tap 130 , the adjacent tap 128 , and the first feedback filter tap 132 , the following timing function can be obtained : z 0 ⁡ ( n ) = b ⁡ ( 1 ) w ⁡ ( n - 1 ) + w ⁡ ( n - 2 ) w ⁡ ( n - 1 ) 2 = h ⁡ ( 1 ) - h ⁡ ( - 1 ) ( 4 ) by removing w ( n − 1 ) in the denominator of both terms , another timing function is derived as follows : z 1 ⁡ ( n ) = b ⁡ ( 1 ) + w ⁡ ( n - 2 ) w ⁡ ( n - 1 ) = h ⁡ ( 1 ) - h ⁡ ( - 1 ) h ⁡ ( 0 ) . ( 5 ) a division operation usually relies upon more complicated hardware than a multiplication operation . therefore , one can derive another timing function that does not use division by multiplying : z 1 by w ( n − 1 ) to obtain : z 2 ⁡ ( n ) = b ⁡ ( 1 ) ⁢ w ⁡ ( n - 1 ) + w ⁡ ( n - 2 ) = h ⁡ ( 1 ) - h ⁡ ( - 1 ) h ⁡ ( 0 ) 2 . ( 6 ) alternatively , one can derive a timing function that does not involve multiplication of tap coefficients : z 3 ⁡ ( n ) = k 1 ⁢ b ⁡ ( 1 ) + k 2 ⁢ w ⁡ ( n - 2 ) = k 1 ⁢ h ⁡ ( 1 ) h ⁡ ( 0 ) - k 2 ⁢ h ⁡ ( - 1 ) h ⁡ ( 0 ) 2 . ( 7 ) where constants k 1 and k 2 , should be carefully chosen to balance the inherently different scaling factors of b ( 1 ) and w ( n − 2 ). for those channels with an asymmetrical impulse response , the above timing functions can be modified by incorporating two scale factors , α and β , as follows : z 0 ⁡ ( n ) = α 0 ⁢ b ⁡ ( 1 ) w ⁡ ( n - 1 ) + β 0 ⁢ w ⁡ ( n - 2 ) w ⁡ ( n - 1 ) 2 z 1 ⁡ ( n ) = α 1 ⁢ b ⁡ ( 1 ) + β 1 ⁢ w ⁡ ( n - 2 ) w ⁡ ( n - 1 ) z 2 ⁡ ( n ) = α 2 ⁢ b ⁡ ( 1 ) ⁢ w ⁡ ( n - 1 ) + β 2 ⁢ w ⁡ ( n - 2 ) z 3 ⁡ ( n ) = α 3 ′ ⁢ k 1 ⁢ b ⁡ ( 1 ) + β 3 ′ ⁢ k 2 ⁢ w ⁡ ( n - 2 ) = α 3 ⁢ b ⁡ ( 1 ) + β 3 ⁢ w ⁡ ( n - 2 ) . fig7 is a block diagram of one embodiment of the timing error detector 120 of fig4 according to the timing function z 0 ( n ). the first post - cursor b ( 1 ) and the main tap , w ( n − 1 ), are the a and b inputs , respectively , of an a / b divider 134 . the output of the a / b divider 134 is the input of an amplifier 136 for scaling the output of the a / b divider 134 by a factor of α 0 . the output of the amplifier 136 is the first of two inputs to a summing logic 144 . the main tap , w ( n − 1 ) is also the input to a squaring device 138 . the first pre - cursor , w ( n − 2 ), and the output of the squaring device are the a and b inputs , respectively , to a a / b divider 140 . the output of the a / b divider 140 is the input to an amplifier 142 for scaling the output of the a / b divider 140 by a factor of β 0 . the output of the amplifier 142 is the second of two inputs to the summing logic 144 . the output of the summing logic 144 is the timing function z 0 ( n ) and is the output of this embodiment of the timing error detector . fig8 is a block diagram of another embodiment of the timing error detector 120 of fig4 according to the timing function z 1 ( n ). the first post - cursor , b ( 1 ), is the input to amplifier 136 for scaling the post - cursor by a factor of α 1 . the output of the amplifier 136 is the first of two inputs to a summing logic 144 . the first pre - cursor , w ( n − 2 ), and the main tap , w ( n − 1 ), are the a and b inputs , respectively , for an a / b divider 140 . the output of the a / b divider 140 is the input of an amplifier 142 that scales the output of the a / b divider 140 by a factor of β 1 . the output of the amplifier 142 is the second of two inputs to the summing logic 144 . the output of the summing logic 144 is the timing function z 1 ( n ) and is the output of this embodiment of the timing error detector . fig9 is a block diagram of another embodiment of the timing error detector 120 of fig4 according to the timing function z 2 ( n ). the first post - cursor , b ( 1 ), and the main tap , w ( n − 1 ), are the a and b inputs , respectively to an a / b divider 134 . the output of the a / b divider 134 is the input to amplifier 136 for scaling the post - cursor by a factor of α 2 . the output of the amplifier 136 is the first of two inputs to a summing logic 144 . the first pre - cursor , w ( n − 2 ), is the input of an amplifier 142 that scales the first pre - cursor by a factor of β 2 . the output of the amplifier 142 is the second of two inputs to the summing logic 144 . the output of the summing logic 144 is the timing function z 2 ( n ) and is the output of this embodiment of the timing error detector . fig1 is a block diagram of another embodiment of the timing error detector 120 of fig4 according to the timing function z 3 ( n ). the first post - cursor , b ( 1 ), is the input to amplifier 136 for scaling the post - cursor by a factor of α 3 . the output of the amplifier 136 is the first of two inputs to a summing logic 144 . the first pre - cursor , w ( n − 2 ), is the input of an amplifier 142 that scales the first pre - cursor by a factor of β 3 . the output of the amplifier 142 is the second of two inputs to the summing logic 144 . the output of the summing logic 144 is the timing function z 3 ( n ) and is the output of this embodiment of the timing error detector . a s will be clear to those of skill in the art , a variety of other embodiments of the timing error detector are possible in hardware and / or software . the embodiments described above are intended to be illustrative and not limiting the scale factors shown above should be chosen properly according to the channel environment when the impulse response of the channel is asymmetrical . fig2 shows the impulse response of the 100 m - length utp category - 5 cable including the effect of a digital shaping filter having a filtering function = 0 . 75 + 0 . 25z − 1 ( where z is the complex impedance ), of an analog low - pass transmit / receive filter , and of a hybrid transformer with a cut - off frequency of 200 khz . for more details , see physical layer specification for 1000 mb / s operation on four pairs of category 5 or better balanced twisted pair cable , ieee std 802 . 3ab , 1998 , which is incorporated by reference in its entirety herein . the asymmetric characteristics of the utp category - 5 cable appear regardless of its length . table i shows the value of first post - cursor and pre - cursor of the utp category - 5 cable with a varied length . the suitable scale factors of the timing functions for the channels in table i are listed in table ii . table ii the scale factors of timing functions . cable length α 0 , α 1 , α 2 , α 3 β 0 , β 1 , β 2 β 3 5 m 1 1769 1185 10 m 1 1600 1072 20 m 1 2182 1309 30 m 1 150 81 40 m 1 89 43 50 m 1 37 16 60 m 1 20 7 . 6 70 m 1 13 4 . 5 80 m 1 9 . 5 2 . 9 90 m 1 7 . 0 1 . 9 100 m 1 3 . 5 2 . 2 α and β are selected to yield a zero for each timing function when in the optimal timing phase . in other words , to obtain the ratio between α and β , one inserts the measured values for h ( 1 ), h ( 0 ), and h (− 1 ) from table i into equations 4 , 5 , 6 , and 7 above , the equations having been modified so that the first term is multiplied by α and the second term is multiplied by β . then one sets the resulting equations equal to zero and solves for the ratio of α and β . having obtained the ratio , one can set α = 1 to obtain β . in this way , one selects α and β to provide a zero correction when in the timing phase is optimal . detector characteristics of the timing functions with scale factors for the impulse response of the 100 - m utp category - 5 cable are plotted in fig3 . although they are not monotonic for a small range of sampling phases , all four timing functions show linear characteristics around the zero phase or at the optimum sampling phase . a timing recovery system consists of a timing error detector 120 , a loop filter 122 , and a voltage - controlled oscillator ( vco ) 124 to form a phase - locked loop ( pll ). fig4 shows a block diagram of one embodiment of the invention , where the timing error detector 120 uses one of the timing functions derived above . although digitally controlled vcos or numerically controlled oscillators ( ncos ) are available , an analog loop filter and a vco may also be incorporated . the transfer function of the loop filter , h loop ( s ), and the transfer function of the vco , h vco ( s ), are h loop ⁢ ( s ) = k 1 + k 2 s where k1 and k2 are arbitrary constants and kvco is a constant for the vco and s represents frequency . for more details , see synopsys online documentation - designing synchronization subsystems in cossap , synopsys , inc ., 1998 , which is incorporated by reference herein in its entirety . h ⁢ ( s ) = 1 1 + k t ⁢ k vco ⁢ h loop ⁢ ( s ) / s where k t is the gain of the timing error detector . the damping ratio , ξ , and the normalized loop bandwidth , bl , have the following relationship ω n 2 = k t ⁢ k vco ⁢ k 2 ξ = k t ⁢ k vco ⁢ k 1 2 ⁢ ⁢ ω n bl = ω n 2 ⁢ ( ξ + 1 4 ⁢ ⁢ ξ ) where ω n , is a natural frequency of the system . k 1 and k 2 should be chosen to satisfy the desired damping ratio and the loop bandwidth . these equations allow for the calculation of k1 and k2 . for more details , see h . meyr and g . ascheid , synchronization in digital communication volume 1 , wiley series , which is incorporated by reference in its entirety herein . the timing functions are derived from the feed - forward and feedback filter coefficients with varying amounts of computation . the functions are based on the derived relations between the coefficients of feed - forward and feedback filters and the channel impulse response . the most complex timing function would need two divisions , three multiplications , and one addition , whereas the least complex one would need only two multiplications and one addition . fig2 , 5 , and 6 and tables i and ii show the results of the simulated performance of the four timing functions described above . the simulated performance used 125 - m baud signaling with 100 - m and 5 - m utp category - 5 cables . fig2 shows the channel impulse . the gains of the derived timing functions , k t , are 0 . 32 , 0 . 60 , 1 . 16 , and 0 . 74 , respectively . k vco has the normalized value of 1 , and k 1 and k 2 were selected as 0 . 001 and 0 . 0000001 , respectively . in the simulations , the free running frequency of the vco is displaced from the transmitter clock frequency by 200 parts per million ( ppm ). fig5 shows the frequency locking process of the vco and the acquisition of the sampling phase when z 0 ( n ), z 1 ( n ), z 2 ( n ), and z 3 ( n ) are used as timing functions with varied initial sampling phases from − 0 . 5 to 0 . 5 . since the impulse response is not symmetrical , the scale factor of z 0 ( n ) for a 100 - m cable shown in table ii is used . for equalization , the following decision - directed algorithm is incorporated to work jointly with the timing recovery y ⁢ ( n ) = ∑ i = 0 n - 1 ⁢ w n ⁢ ( i ) ⁢ x ⁢ ( n + n - 1 + i ) + ∑ i = 1 m ⁢ b n ⁢ ( i ) ⁢ y ^ ⁢ ( n - i ) w n + 1 ⁢ ( i ) = w n ⁢ ( i ) + μ ⁢ ⁢ e ⁢ ( n ) ⁢ x ⁢ ⁢ ( n + n - 1 + i ) ⁢ ⁢ i = 0 , … ⁢ , n - 1 b n + 1 ⁢ ( i ) = b n ⁢ ( i ) + μ ⁢ ⁢ e ⁢ ( n ) ⁢ y ^ ⁢ ( n - i ) ⁢ ⁢ i = 1 , … ⁢ , m where y ( n ) is filtered output , ý ( n ) is the nearest decision value , and n and m correspond to the number of taps in feed - forward and feedback filters , respectively . to assure the convergence of the decision - directed algorithm , the coefficient of the main tap , h ( 0 ), is initialized to a high value considering the variations of the channel impulse response see g . j . foschini , “ equalization without altering or detecting data ,” at & amp ; t technical journal , vol . 64 , pp . 1885 - 1911 , october 1985 , which is incorporated herein by reference in its entirety . blind equalization algorithms may also be used without altering the timing functions . a blind equalization algorithm is an equalization algorithm that does not enjoy the benefit of a training sequence . fig5 ( a ), 5 ( c ), 5 ( e ), and 5 ( g ) show the output of the loop filter . since the free running frequency of the vco clock of the receiver is slower than the transmitter clock by 200 ppm , the output of the loop filter should be 0 . 0002 when the frequency lock is reached . in fig5 ( b ), 5 ( d ), 5 ( f ), and 5 ( h ), the sampling phase is normalized to 2π so that − π and π correspond to − 0 . 5 and 0 . 5 , respectively . thus , the sampling phase should be settled at an integer value when the phase lock is reached . in most cases , since the channel impulse response is not known beforehand , the scale factors cannot be determined . however , based on the present simulations , one can estimate the worst - case impulse response , and one can use scale factors based on the worst case estimate without any severe degradation in performance . simulation results for the 5 - m cable ( best case ) with the scale factors obtained from the 100 - m cable ( worst case ) are shown in fig6 . frequency lock with the timing offset of less than 0 . 1 is reached with a negligible degradation in snr . the simulations show that frequency lock and phase lock are reached in less than 20 , 000 symbols with a settling behavior typically found in adaptive systems . the simulation results show that all of the timing functions derived work robustly in a severely distorted channel as well as in a moderately distorted one when they are incorporated in a pll with decision - directed equalization . the pll &# 39 ; s lock is reached in less than 20 , 000 symbols for all the timing functions and under all initial conditions with the steady - state phase offset of less than 0 . 1 symbol time . another advantage of embodiments of the present invention is the reduction in noise enhancement . as noted above , a linear equalizer includes a number of taps , each tap time delayed relative to its neighbor , the taps measuring the input . the linear equalizer multiplies the output of the taps by coefficients and sums the resulting terms . thus , the equalizer also multiplies the gaussian noise term in the input by the same coefficients and sums the resulting terms to increase the noise power . consequently , noise power is proportional to the number of taps . on the other hand , a dfe consists of a fff and a fbf and the input to the fbf is noiseless because the input to the fbf is from a slicer . thus , the number of taps in a fff is fewer than that in a linear filter . as a result , a dfe has less noise enhancement than a linear filter . while the invention has been described with reference to preferred embodiments , it is not intended to be limited to those embodiments . it will be appreciated by those of ordinary skilled in the art that many modifications can be made to the structure and form of the described embodiments without departing from the spirit and scope of this invention .