the present invention now will be described more fully hereinafter with reference to the accompanying drawings , in which a preferred embodiment of the invention is shown . this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein . there are many methods of manufacturing of semiconductor devices well - known in the art . the following discussion does not include details regarding the manufacturing of semiconductor devices . rather , the discussion focuses on modifying a conductive layer block mask used during the manufacturing of semiconductor devices in order to further confuse a reverse engineer . the present invention makes use of an artifact edge of a silicide layer that a reverse engineer might see when reverse engineering devices manufactured with other reverse engineering detection prevention techniques . in a reverse engineering detection prevention technique , described above , channel block structures are used to confuse the reverse engineer . as shown in fig1 b , the channel block structure 27 has a different dopant type than the channel areas 23 , 25 and has an interruption 30 in the overlying silicide . after using a reverse engineering process , such as cmp , the artifact edges 28 of a silicide layer may reveal to the reverse engineer that a channel block structure 24 , 27 has been used to interrupt the electrical connection between two channel areas 23 , 25 , as can be seen from comparing fig1 a and 1b . the type of dopant used in the channel areas and the channel block structure is not readily available to the reverse engineer during most reverse engineering processes . thus , the reverse engineer is forced to rely upon other methods , such as the artifact edges 28 of a silicide layer , to determine if the conductive channel has a channel block in it . fig2 depicts artifact edges 28 of a silicide layer of a device manufactured in accordance with the present invention . a silicide block mask is preferably modified to prevent a silicide layer from completely covering a pseudo channel block structure 29 . channel block structure 29 is of the same conductivity type as channel areas 23 , 25 ; therefore , the presence or absence of a silicide layer connecting the channel areas 23 , 25 does not have an impact on the electrical conductivity through the channel . however , by modifying the silicide block mask to prevent a silicide layer from completely covering the pseudo channel block structure 29 , the artifact edge 28 with interruption 30 appears to the reverse engineer to indicate that the channel is not electrically connected , i . e . the artifact edges 28 of fig2 are identical to the artifact edges 28 of fig1 b . thus , the reverse engineer , when viewing the artifact edge 28 , would leap to an incorrect assumption as to the connectivity of the underlying channel . in order to further camouflage the circuit , the dopant type used in channel block structure 29 may be created at the same time lightly doped drains ( ldd ) are created . thus , even using stain and etch processes , the reverse engineer will have a much more difficult time discerning the difference between the two types of implants , n - type versus p - type , vis - a - vis the much higher dose of the source / drain implants 22 , 26 . further , by creating the pseudo channel block structure 29 with the ldd processes , the channel block structure 29 can be made smaller in dimensions because of breakdown considerations . in the preferred method of manufacturing the present invention , the design rules of a semiconductor chip manufacturer are modified to allow implanted regions that are not silicided . in addition , the design rules may also be modified to allow for channel block structure 29 to be small and lightly doped ( through the use of ldd implants ) to further prevent detection by the reverse engineer . in modifying the design rules , it is important to ensure that the artifact edges of an actual conducting channel , as shown in fig2 , match the placement of the artifact edges of a non - conducting channel , as shown in fig1 b . for illustration purposes , the artifact edges 28 in fig1 b match the artifact edges 28 of fig2 . as one skilled in the art will appreciate , the artifact edges 28 do not have to be located as specifically shown in fig1 b or 2 . instead , the artifact edges may appear almost anywhere along the channel . however , it is important that ( 1 ) the silicide layer does not provide an electrical connection ( i . e . that the silicide layer does not completely cover channels with an intentional block or a pseudo block therein ), and ( 2 ) that the artifact edges 28 for an electrical connection ( i . e . a true connection ) are relatively the same as the artifact edges 28 for a non - electrical connection ( i . e . a false connection ). as such , while it may be advisable to include conducting and non - conducting channels of the types shown in fig1 a , 1 b and 2 all on a single integrated circuit device , it is the use of a mixture of channels of the types shown and described with reference to fig1 b and 2 that will keep the reverse engineer at bay . one skilled in the art will appreciate that while fig1 a , 1 b and 2 use n - type doped areas 22 – 25 , 29 with a p - type channel block structure 27 the above holds true for p - type doped areas with a n - type channel block structure . additionally , the invention is preferably used not to completely disable a multiple transistor circuit in which this invention is used , but rather to cause the circuit to function in an unexpected or non - intuitive manner . for example , what appears to be an or gate to the reverse might really function as an and gate . or what appears as an inverting input might really be non - inverting . the possibilities are practically endless and are almost sure to cause the reverse engineer so much grief that he or she will give up as opposed to pressing forward to discover how to reverse engineer the integrated circuit device on which these techniques are utilized . finally , the disclosed method and apparatus is compatible with other camouflaging techniques which may be used to protect integrated circuit devices from being reverse engineered . thus , this may be one of many techniques used with a given integrated circuit device to protect it from being successfully reverse engineered . having described the invention in connection with certain preferred embodiments thereof , modification will now certainly suggest itself to those skilled in the art . as such , the invention is not to be limited to the disclosed embodiments , except as is specifically required by the appended claims .