the following embodiments and aspects thereof are described and illustrated in conjunction with systems , apparatuses and methods which are meant to be illustrative , not limiting in scope . fig1 is a flowchart diagram illustrating a method 100 for encoding a codeword of data to be written to a medium , in accordance with an example embodiment . method 100 can be implemented by a controller of a media device , which scans code words for strings of zeroes that violate a coding constraint ( k ), and replaces violating sequences with an indicator that meets the coding constraint . the method includes pre - pending a 1 bit at the beginning of each code word . if there are no violating strings of zeroes of a length k in the codeword , then no additional modifications are performed to the codeword . if the controller finds a violating string of zeroes of a length k in the codeword , the controller changes the pre - pended bit to 0 and inserts a 1 ( guard bit ), k − 2 bits designating the address of the violation , followed by a 1 ( end flag ). the controller also replaces the violating string - of - zeroes with the data that was previously in the first k bits of the word . the controller then iterates , treating a final 1 in the first replacement in a similar manner as that of the pre - pended bit in the first pass . an exception can occur during the above - noted replacement operation in that if the address of the violator equals the value of the address table pointer , no bits are moved , and if the address of the violator is less than the address table pointer but greater than the address table pointer plus k , then only the bits from the address table pointer down to , but not including , the leftmost violator bit are moved . this exception handles “ inside ” violators which will be described in a subsequent section . initially , the controller receives n bits ( 102 ), constructs an initial codeword by pre - pending a 1 bit ( 104 ) and sets an address table pointer (“ a . t . pointer ”) equal to a first data bit address ( 106 ). restated , a scan bit address is set equal to a first data bit address . next , the controller scans the codeword ( 108 ) and determines if a k constraint has been violated ( 110 ). if no , the controller determines if an end of the codeword block has been reached ( 112 ). if yes , the controller transmits the block ( 113 ) and receives the next n bits ( 102 ). otherwise , the controller sets the scan bit address equal to the next data bit address ( 114 ). if the k constraint is violated ( 110 ), the controller records a scan bit address ( 116 ), and determines if the scan bit address is equal to the address table pointer ( 120 ). the controller does the determination at operation 120 in order to ascertain if alternate processing is necessary due to a type of violator that has been encountered — an outside violator or an inside violator . more specifically , operation 120 determines if alternate processing is necessary for a specific occurrence of an inside violator . a detailed description of the two types of violators will be provided at a subsequent section . if the scan bit address equals the address table pointer ( 120 ), the controller constructs an indicator ( 122 ), inserts the indicator at the address table pointers ( 124 ), clears a preceding end flag ( 126 ) and increments the address table pointer by k ( 128 ). next , the controller performs operation 112 . if the scan bit address does not equal the address table pointer ( 120 ), the controller determines if the scan bit address is less than the address table pointer and greater than the address table pointer minus k ( 130 ). if no , the controller replaces the first k bits of the violator sequence with the first k bits starting at the address table pointer ( 132 ). next , the controller executes operations 122 - 128 as previously described . if operation 130 is affirmative , the controller moves data bits from the address table pointer down to , but not including , the scan bit address to after the indicator location ( address table pointer — k ) ( 134 ). next , the controller executes operations 122 - 128 . operation 130 also determines if alternate processing is required due to an occurrence of an inside violator . this encoding method 100 of fig1 provides for a run length not exceeding k , because the sequences of k bits that can occur will be of the last k − 1 bits of one block and the prepended bit of the following block when the following block was transformed to eliminate violators . the guard bits ensure that no indicator can give rise to additional violations and the exception of operation 120 ( scan bit address = address table pointer so no bits are moved ) ensures that data bits which need to be moved from the address table cannot increase the number or length of violators . addresses of violators also cannot give rise to additional violations because even if addresses are all zeroes , they are enclosed within either a pair of guard bits , which are always 1 , or a guard bit and an end flag with the value 1 . additionally , since any combination of bits that includes a data pattern and a k - bit violator , whether that violator is external or internal , is replaced with the same number of bits . due to this , sufficient space , in a codeword , is maintained for indicators independent of a number of violators in the initial data word . in one implementation , if n & gt ; 2 k − 2 , then offset bit addresses are utilized . the offset bit addresses only address the first 2 k − 2 bits of a codeword as a violator can not be present in the remaining n − 2 k − 2 bits . for example , if n = 21 and k = 6 , the last 5 bits will not be addressed by the offset bit addresses as a violator of k ( 6 ) zeroes can not occur at those last 5 bits . when n & gt ; 2 k − 2 , indicators are constructed with address fields that point to offset bit addresses . alternatively stated , the scan bit address recorded at operation 116 is decreased by n − 2 k − 2 before it is placed into an indicator . it should be appreciated that given the construction of a maximum - length code , that is , with n = 2 k − 2 + k − 1 , it is possible to delete bits from the right - hand end of each user data block so as to produce a shorter code , that is , one with any smaller value of n . due to this , method 100 produces codes for all rates n /( n + 1 ) essentially without modification . fig2 a - 2d sequentially illustrate an example of data being encoded , in accordance with an example embodiment . in this example , the code run rate is 21 / 22 and k ( rll constraint ) has been set at 6 . 20 bits of data 10 are received and each bit has a corresponding bit address 12 ( fig2 a ). an additional bit 14 , with a value of 1 , is then pre - pended to the received bits to form an initial codeword 29 . if the codeword 29 does not contain any sequences of k contiguous zeroes ( violators ) then it is transmitted unchanged . each bit has a corresponding bit address . additionally , bit addresses # 5 - 20 have a corresponding offset bit address 16 . in the encoding example of fig2 a - 2d , n & gt ; 2 k − 2 so offset bit addresses are utilized . an address table pointer 17 is created which initially points to a bit address of a bit immediately adjacent to the pre - pended bit 14 . in the example of fig2 b , the address table pointer 17 initially points to offset bit address # 15 . the codeword 29 is then scanned , left to right , using a sliding window of k bits starting at offset bit address # 15 . when a violator 18 is offset detected , a bit address of a first bit address of the violator is recorded . in the example of fig2 b , the first bit address of the violator 18 is bit address # 8 as a sequence of k ( 6 ) zeroes begins there . when the first violator is detected , pre - pended bit 14 is changed to 0 . the k bits of the violator 18 are then replaced with k bits of the codeword 29 starting from the offset bit address that is being pointed to by the address table pointer 17 . referring to fig2 b - 2c , the sequence “ 0 1 0 0 1 1 ” which begins at offset bit address # 15 is moved to the location of the violator 18 and that transferred data is referred to as indicator data 20 . next , an indicator sequence 22 of k bits is constructed and placed in the codeword 29 starting at the offset bit address pointed to by the address table pointer ( fig2 b ). indicators , in one implementation , begin with a guard flag whose value is one , an address field , of length k − 2 , that identifies a first offset bit address of a violator and an end flag with an initial value of 1 . if an additional violator is detected , the end flag is changed to a 0 . referring to fig2 c , first indicator 22 includes the guard flag at offset bit address # 15 , the address field at offset bit addresses # 14 - 11 and the end flag at offset bit address # 10 . the address field of the first indicator 22 contains the sequence “ 1 0 0 0 ” which refers to offset bit address # 8 . from fig2 b to fig2 c , the address table pointer 16 is advanced by k such that it now points to offset bit address # 9 in fig2 c . also in fig2 c , the codeword 29 is further scanned and a second violator 24 is detected whose first bit is addressed by offset bit address # 6 which is recorded . referring to fig2 d , the end flag of the first indicator 22 , at offset bit address # 10 is changed from 1 to 0 and bits of the second violator 24 are replaced with k bits starting from the offset bit address pointed to by the address table pointer in fig2 c . specifically , k bits (“ 1 01 0 0 1 ”) starting from offset bit address # 9 ( refer to fig2 c ) and are placed into the bits occupied the second violator — bit addresses # 1 - 6 wherein bit addresses # 5 - 6 correspond to offset bit addresses # 0 - 1 . those replaced bits are referred to as indicator data 26 . referring to fig2 d , a second indicator 28 is then constructed with a guard flag at offset bit address # 9 whose value is 1 , an address field at offset bit addresses # 5 - 8 and an end flag whose value is 1 . the address field , at offset bit addresses # 5 - 8 , contains the string “ 0 0 0 1 ” which refers to offset bit address # 1 . as the second violator 24 extends into bits not addressed by the offset bit addresses 17 , scanning of the codeword 29 for further violators is discontinued . if the offset bit addresses 17 were not utilized in the encoding example of fig2 a - 2d then scanning of the codeword 29 for violators would continue until an end of the codeword 29 is reached . the claimed embodiments take into account two types of violators — external and internal which are illustrated in fig3 a - 3b , respectively . an external violator is a violator which does not begin within the location where the indicator referring to it is to be placed . an example of an external violator is external violator 30 . additional examples of external violators are violators 18 and 24 shown in fig2 b - 2c . similar to what was previously described , bits 34 , starting from a bit address pointed to by an address table pointer (“ atp ”) 35 , are moved to bit addresses 36 that were occupied by the external violator 30 . next , indicator 32 is constructed and placed at bit addresses starting from a bit address pointed to by the address table pointer 35 . referring to fig3 b , an internal violator is a violator which begins within the location where the indicator referring to it is to be placed . for example , internal violator 38 is only a few bit addresses away from address table pointer 40 . if k = 6 , for example , an indicator for violator 38 would be 6 bits long and would be written at bit addresses of the internal violator 38 . in this instance , only the leading non - zero data 42 is moved to fill in a portion of the bits occupied by the internal violator 38 . fig4 is a flowchart diagram illustrating a method 400 for decoding a codeword of data read from a medium , in accordance with an example embodiment . in the implementation shown , method 400 involves a controller of a media device examining a pre - pended bit of a codeword . if the pre - pended bit has a value of 1 , the pre - pended bit is discarded and the remaining bits are delivered unchanged . otherwise , the decoding of the codeword proceeds by creating an address table pointer with the initial value of the last indicator in the address table , which is that entry with an end flag equal to 1 . next , the controller extracts the address field from the indicator pointed to by the address table pointer and increasing it by n − 2 k − 2 , if necessary , so that a violator is addressed . next , the controller replaces the indicator with the k bits at the addressed violator . in turn , the controller replaces the k bits of the addressed violator with zeroes , decreases the address table pointer by k and repeats the extracting operation , the two replacing operations and decreasing operation until the first indicator has been replaced . an exception can sometimes occur for the first replacing operation in that if the value of the address table pointer equals the address of the violator , no bits are moved , and if the address of the violator is less than the address table pointer but greater than the address table pointer plus k , then only the bits from the rightmost violator bit up to , but not including , the end of the indicator are moved . to explain method 400 in more detail , reference to fig4 is made . first , the controller receives the next codeword ( 402 ) and determines if the pre - pended bit is equal to 1 ( 404 ). if yes , the controller discards the pre - pended bit and delivers the remaining n bits of the codeword ( 406 ). otherwise , the controller sets an address table pointer equal to an initial value of a last indicator in the address table ( 410 ) and extracts an address field from an indicator pointed to by the address table pointer ( 412 ). next , the controller determines if the extracted address is equal to the address table pointer ( 414 ). if yes , the controller replaces k bits starting at the extracted address with k number of zeroes ( 416 ) and decreases the address table pointer by k ( 418 ). in turn , the controller determines if the first indicator has been replaced . if yes , the controller receives the next codeword ( 402 ). if the extracted address does not equal the address table pointer ( 414 ), the controller then determines if the extracted address is less than the address table pointer but greater than the address table pointer minus k ( 422 ). if yes , the controller replaces indicator bits from a right - most violator up to an end of the indicator ( 424 ). otherwise , the controller replaces the indicator with k bits starting at the extracted address ( 426 ). due to bit errors in a channel , the received codeword may be malformed . restated , the received codeword fails to conform to the structure of a properly - encoded codeword as previously described . one detectable malformation is any guard bit equal to 0 . others are the occurrence of an indicator with an address smaller than that of the indicator itself , or than the address of any preceding indicator . a decoder may optionally detect these malformations and report an un - decodable codeword . fig5 a - 5d sequentially illustrate an example decoding of a codeword , in accordance with an example embodiment . in this example , the code rate n /( n + 1 ) is 21 / 22 and k has been arbitrarily set at 6 . the received codeword 29 of fig5 a is the same codeword that was constructed in the encoding example of fig2 a - 2d and includes prepended bit 14 , first and second indicators 22 and 28 and indicator data 26 . the prepended bit 14 has a value of 0 and decoding of codeword 29 is therefore necessary . address table pointer 16 is set at a first bit address of a lastly - encoded indicator . specifically , address table pointer 16 is set to point at bit address # 14 of the second indicator 28 . the lastly - encoded / second indicator 28 is located based on the value of the end flag . second indicator 28 has an end flag at bit address # 9 and its value is 1 which indicates that no further violators were detected after the second indicator was constructed . an address is extracted from second indicator 28 and the extracted address is increased by n − 2 k − 2 since n & gt ; 2 k − 2 . the extracted address points to bit address # 1 which in turn is increased to bit address # 6 which is the bit address of a first bit of the indicator data 26 . referring to fig5 b , bits occupied by the indicator data 26 are restored to zeroes and the indicator data 26 is moved to bits starting from a bit address that is pointed to by the address table pointer 16 . referring to fig5 c , the address table pointer 16 is decreased by k so that it points to bit address # 20 of first indicator 22 . an address is extracted from an address field , of first indicator 22 ( as shown in fig5 b before being replaced by indicator data 22 ) and that address points to bit address # 8 which is increased to bit address # 13 . k bits starting at bit address # 13 are therefore restored to zeroes and indicator data 20 from bit addresses # 13 - 8 as shown in fig5 b are placed at bit addresses # 20 - 15 as shown in fig5 c . next , in fig5 d , prepended bit 14 is deleted which results in the original 21 bits of data 10 that was initially shown in fig2 a . fig6 a - 6b are block diagrams illustrating a decision channel , implemented in hardware , for a write section 600 and a read section 650 , in accordance with an exemplary embodiment . fig6 a - 6b illustrate that rll encoding and decoding is “ outside ” an error correction mechanism . restated , for writing , the data is ecc encoded before being rll encoded . and , for reading , the rll encoding is removed before error correction takes place . this is possible because a hard - decision detector , typically employing a viterbi algorithm , is used , the output of which is a stream of determinate bits which can be treated by an rll decoder . fig7 a - 7b are block diagrams illustrating a soft - decision channel , implemented in software , for write section 700 and a read section 750 , in accordance with an exemplary embodiment . in this case , a soft - decision detector is used ( which may be bcjr , sova , or other type ), of which the outputs are not determinate bits , but probabilities . the error - control block , typically a turbo decoder or low - density parity check ( ldpc ) decoder , operates on these probabilities to produce the determinate output bits . hence the rll decoder does not operate on the detector output , but instead on the output of the error control block . consequently , the rll encoding and decoding is “ inside ” the error correction mechanism as shown . the claimed embodiments are efficient in comparison to the prior art due to reasons described in the following section . any user data block of length n has 2 n possible values , and in order for these to be mapped onto a codeword of length k , the codeword should have at least that many different values . for each codeword length n + 1 and for each value of k it is possible to calculate the number of codewords which ( 1 ) contain no all - zero sequences of length greater than k , and ( 2 ) which begin and end with all - zero sequences for which the sum of the lengths does not exceed k . such codewords may be freely concatenated without violating the k constraint . the minimum value of k for which the codeword has at least 2 n values is the optimum value of k for that codeword length . an rll code is deemed efficient if its k value is near the optimum value . rll codes constructed in accordance with the claimed embodiments are efficient in that sense . table i compares the values of k achieved by the claimed embodiments to the optimal values of k for the maximum number of user bits which can be encoded , that is , n . it can be seen that the achieved values diverge slowly from the optimal values as code length increases . further , since the only runs of k zeroes that can occur in a codeword are , as noted above , at the conjunction of two codewords , the elimination of k bit violators in all other locations makes the stream of codewords “ almost ” k − 1 . hence the average performance of these codes is even closer to optimum . while a number of exemplary aspects and embodiments have been discussed above , those of skill in the art will recognize certain modifications , permutations , additions and sub - combinations thereof . it is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications , permutations , additions and sub - combinations as are within their true spirit and scope .