hereinafter , embodiments of the present invention will be described with reference to the appended figures . a first embodiment of the present invention will be explained with reference to fig1 to 3 . fig1 is a diagram showing the structure of a pll circuit as the first embodiment of the present invention . the present pll circuit is of a charge pump type . in fig1 , reference numeral 100 indicates a voltage - controlled oscillator ( i . e ., vco ), reference numeral 101 indicates a phase comparator , reference numeral 102 indicates a charge pump circuit , reference numeral 103 indicates a loop filter , reference numeral 104 indicates a capacitor ( or capacitance ) which forms the loop filter 103 , and reference numeral 105 indicates a negative - voltage generating circuit . to the phase comparator 101 , a reference clock signal vin and a fed - back oscillation signal are input , where the latter is an oscillation signal vout of the vco 100 , which is fed back . the increase signal up and the decrease signal down output from the phase comparator 101 are each input into the charge pump circuit 102 , as a frequency control signal used for controlling the oscillation frequency of a signal output from the vco 100 . in addition , the output ( i . e ., for outputting the control voltage vcont ) of the charge pump circuit 102 is connected to one end of the capacitor 104 which forms the loop filter 103 , and the control voltage vcont is also input into the vco 100 . the other end of the capacitor 104 is grounded . additionally , the signal ( i . e ., negative voltage vb ) output from the negative - voltage generating circuit 105 is input as the reference voltage into the vco 100 . the operation of the present pll circuit will be explained below . first , the phase comparator 101 compares the phases of the reference clock signal and the fed - back oscillation signal , which are input into the pair of the inputs of the phase comparator 101 . based on the result of the comparison , the phase comparator 101 outputs the increase signal up or the decrease signal down . for example , ( i ) when the frequency of the fed - back oscillation signal is lower than that of the reference clock signal , the phase comparator 101 outputs the increase signal up , and ( ii ) when the frequency of the fed - back oscillation signal is higher than that of the reference clock signal , the phase comparator 101 outputs the decrease signal down . next , based on the increase signal up or the decrease signal down , the charge pump circuit 102 outputs or receives the relevant current . the loop filter 103 converts the current output from the charge pump circuit 102 into the control voltage vcont , and also performs a filtering process . the vco 100 generates an oscillation signal vout in accordance with the control voltage vcont , and outputs the signal , not only to the outside thereof , but also to the phase comparator 101 as the fed - back oscillation signal . the pll circuit repeatedly performs the above - described operation , so as to output the oscillation signal vout having a desired frequency which is locked . the negative - voltage generating circuit 105 generates the negative voltage vb which is lower than the ground voltage . the negative voltage vb is input as a reference voltage from the reference - voltage terminal of the vco 100 . accordingly , the oscillation frequency of the vco 100 is determined in accordance with the difference between the negative voltage vb and the control voltage vcont . a concrete example of the vco 100 will be shown with reference to fig2 . that is , fig2 is a circuit diagram showing the vco 100 of the first embodiment . in fig2 , reference numerals 201 , 203 , and 205 indicate pmos transistors , and reference numerals 202 , 204 , and 206 indicate nmos transistors . with respect to the pmos transistor 201 and the nmos transistor 202 , the gates are connected to each other , and the drains are also connected to each other . with respect to the pmos transistor 203 and the nmos transistor 204 , the drains are connected to each other , and the gates are also connected to each other , which are also connected to the drains of the pmos transistor 201 and the nmos transistor 202 . with respect to the pmos transistor 205 and the nmos transistor 206 , the gates are connected to each other , and are also connected to the drains of the pmos transistor 203 and the nmos transistor 204 . in addition , the drains of the pmos transistor 205 and the nmos transistor 206 are connected to each other , and they output the oscillation signal vout . they are also connected to the gates of the pmos transistor 201 and the nmos transistor 202 . the sources of the pmos transistors 201 , 203 , and 205 are connected to each other , and the control voltage vcont is input into the sources . in addition , the sources of the nmos transistors 202 , 204 , and 206 are connected to each other , and are also connected to the reference - voltage terminal , to which the negative voltage vb is input as the reference voltage . as described above , the negative voltage vb is generated using the negative - voltage generating circuit 105 , and is input as the reference voltage of the vco 100 , thereby decreasing the control voltage vcont by the negative voltage vb , without changing the oscillation frequency . for example , if the oscillation frequency of the vco 100 is 1 . 6 ghz when the reference voltage is 0 v and the control voltage vcont is 1 . 2 v , then by using the negative voltage vb which is − 0 . 5 v as the reference voltage , the oscillation frequency of the vco 100 becomes 1 . 6 ghz when the control voltage vcont is approximately 0 . 7 v . fig3 is a graph showing the relationship between the charge pump current and the control voltage vcont of the pll circuit . as shown in fig3 , when the reference voltage of the vco 100 is 0 v , the control voltage vcont is present at the point a . however , when using the negative voltage vb as the reference voltage , the control voltage vcont shifts to the point b , thereby avoiding a linear area 300 , and also setting the outflow current iup and the inflow current idown to almost identical values . that is , using the negative - voltage generating circuit 105 makes the transistor , by which the charge pump circuit 102 outputs the outflow current , operate in a saturation area . a second embodiment of the present invention will be explained with reference to fig4 to 6 . fig4 is a diagram showing the structure of a pll circuit of the present embodiment . the present pll circuit is also of the charge pump type . in fig4 , reference numeral 400 indicates a vco , reference numeral 402 indicates a charge pump circuit , and reference numeral 405 indicates a booster circuit . the other structural elements are identical to the corresponding elements in fig1 , and explanations thereof are omitted here . to the phase comparator 101 , the reference clock signal vin and a fed - back oscillation signal are input , where the latter is an oscillation signal vout of the vco 400 , which is fed back . the increase signal up and the decrease signal down output from the phase comparator 101 are each input into the charge pump circuit 402 . in addition , the output ( i . e ., for outputting the control voltage vcont ) of the charge pump circuit 402 is connected to one end of the capacitor 104 which forms the loop filter 103 , and the control voltage vcont is also input into the vco 400 . the other end of the capacitor 104 is grounded . additionally , the signal ( i . e ., voltage vp ) output from the booster circuit 405 is input as the power source voltage into the source terminal of the charge pump circuit 402 . the basic operation of the present pll circuit is identical to that of the first embodiment , and explanations thereof are omitted . below , distinctive operations of the present embodiment will be described . the booster circuit 405 generates the voltage vp , which is higher than the power source voltage vdd supplied from a power source . the charge pump circuit 402 is driven by the voltage vp generated by the booster circuit 405 . that is , the charge pump circuit 402 operates by the power source voltage vp (& gt ; vdd ), and the structural elements other than the charge pump circuit 402 operate by the power source voltage vdd . a concrete example of the charge pump circuit 402 will be shown with reference to fig5 . that is , fig5 is a circuit diagram showing the charge pump circuit and the loop filter of the present embodiment . in fig5 , reference numerals 501 , 503 , and 504 indicate pmos transistors , and reference numerals 502 , 505 , and 506 indicate nmos transistors . the other structural elements are identical to the corresponding elements in fig4 , and explanations thereof are omitted here . with respect to the pmos transistors 501 and 503 , the sources are connected to each other , and the gates are also connected to each other , to which a bias voltage vbias is input . the drain of the pmos transistor 501 is connected to the source of the nmos transistor 502 . the gate of the nmos transistor 502 is connected to the drain thereof , and also connected to the gate of the nmos transistor 506 . the sources of the nmos transistors 502 and 506 are each grounded . the source of the pmos transistor 504 is connected to the drain of the pmos transistor 503 , and the drain of the pmos transistor 504 is connected to the drain of the nmos transistor 505 , which is also connected to the loop filter 103 ( i . e ., the control voltage vcont ). the increase signal up is input into the gate of the pmos transistor 504 . the source of the nmos transistor 505 is connected to the drain of the nmos transistor 506 , and the decrease signal down is input into the gate of the nmos transistor 505 . the values of the outflow current iup and the inflow current idown are determined in accordance with the specific bias voltage vbias . in the present charge pump circuit 402 , when the increase signal up is input , the pmos transistor 504 is switched on , so that the outflow current iup is output to the loop filter 103 via the pmos transistor 503 . on the other hand , when the decrease signal down is input , the nmos transistor 505 is switched on , so that the inflow current idown is drawn from the loop filter 103 via the nmos transistor 506 . accordingly , the charge pump circuit 402 controls the control voltage vcont . as described above , the voltage vp , which is higher than the power source voltage vdd , is generated using the booster circuit 405 , and it functions as the power source voltage used for driving the charge pump circuit 402 . therefore , it is possible to increase the drain - source voltage vds of the pmos transistor 503 . for example , if the drain - source voltage vds of the pmos transistor 503 is approximately 0 . 6 v when the power source voltage vp and the control voltage vcont of the charge pump circuit 402 are respectively 1 . 8 v and 1 . 2 v , then by setting the power source voltage vp to 3 v , the drain - source voltage vds of the pmos transistor 503 becomes approximately 1 . 8 v . fig6 a and 6b are graphs showing the relationships between the charge pump current and the control voltage vcont of the present pll circuit . as shown in fig6 a , when the power source voltage is vdd , the control voltage vcont is present at the point a which belongs to a linear area 600 , where there is a considerable difference between the outflow current iup and the inflow current idown . however , as shown in fig6 b , when the power source voltage is vp which is larger than vdd , the control voltage vcont is also present at the point a , but it is possible to avoid a linear area 601 , and an area can be used where the outflow current iup and the inflow current idown are almost identical to each other . that is , using the booster circuit 405 allows the pmos transistor 503 , by which the charge pump circuit 402 outputs the outflow current , to operate in a saturation area . when a circuit consisting of the charge pump circuit 102 , the loop filter 103 , and the vco 100 of the first embodiment and a circuit consisting of the charge pump circuit 402 , the loop filter 103 , and the vco 400 are each regarded as an oscillation circuit , the negative - voltage generating circuit 105 of the first embodiment and the booster circuit 405 of the second embodiment each function as a bias control circuit for supplying a negative voltage or a voltage higher than the power source voltage to the oscillation circuit . a third embodiment of the present invention will be explained with reference to fig7 and 8 . in fig7 , reference numeral 700 indicates a voltage control circuit ( i . e ., negative - voltage control part ). the other structural elements are identical to the corresponding elements in fig1 , and explanations thereof are omitted here . to the phase comparator 101 , the reference clock signal vin and the fed - back oscillation signal are input , where the latter is the oscillation signal vout of the vco 100 , which is fed back . the increase signal up and the decrease signal down output from the phase comparator 10 are each input into the charge pump circuit 102 . in addition , the output ( i . e ., for outputting the control voltage vcont ) of the charge pump circuit 102 is connected to one end of the capacitor 104 which forms the loop filter 103 , and the control voltage vcont is also input into the vco 100 . the other end of the capacitor 104 is grounded . additionally , the signal ( i . e ., negative voltage vb ) output from the negative - voltage generating circuit 105 is input into the voltage control circuit 700 . in addition , the signal ( i . e ., negative voltage vb ) output from the voltage control circuit 700 is input as the reference voltage into the vco 100 . furthermore , a programmable voltage vprog is input into the voltage control circuit 700 via a control terminal thereof . the present pll circuit is also of the charge pump type . the basic operation of the present pll circuit is identical to that of the first embodiment , and explanations thereof are omitted . below , distinctive operations of the present embodiment will be described . the negative - voltage generating circuit 105 generates the negative voltage vb . the voltage control circuit 700 controls the negative voltage vb in accordance with the programmable voltage vprog , so as to convert the negative voltage vb into the negative voltage vb . the negative voltage vb is input as the reference voltage into the vco 100 . accordingly , the oscillation frequency of the vco 100 is determined in accordance with the difference between the negative voltage vb and the control voltage vcont . a concrete example of the voltage control circuit 700 will be shown with reference to fig8 . that is , fig8 is a circuit diagram of the voltage control circuit 700 . in fig8 , reference numeral 800 indicates an amplifier , and reference numerals 801 to 804 indicate nmos transistors . the gate and the drain of the nmos transistor 801 are connected to each other , and are also connected to the control terminal , into which the programmable voltage vprog is input . the gate and the drain of the nmos transistor 802 are connected to each other , and are also connected to the source of the nmos transistor 801 . the gate and the drain of the nmos transistor 803 are connected to each other , and are also connected to the source of the nmos transistor 802 and one of two input terminals of the amplifier 800 . the other input terminal of the amplifier 800 is grounded , and the output terminal thereof is connected to the gate of the nmos transistor 804 . the drain of the nmos transistor 804 is connected to the source of the nmos transistor 803 , and also outputs the negative voltage vb . in addition , the negative voltage vb is input into the source of the nmos transistor 804 . in this example , the nmos transistors 801 to 803 have the same transistor size . the operation of the voltage control circuit 700 will be explained below . here , it is assumed that the programmable voltage vprog input from the control terminal is 0 . 8 v , and the negative voltage vb is − 0 . 5 v . as the above - described other input terminal of the amplifier 800 is grounded , the above - described one input terminal thereof is 0 v . that is , the gate voltage and the drain voltage of the nmos transistor 803 are each 0 v . therefore , a current in accordance with the programmable voltage vprog and the resistances of the nmos transistors 801 and 802 flows through the nmos transistors 801 to 803 , and the current further flows through the nmos transistor 804 . as the nmos transistors 801 to 803 have the same transistor size , the voltage drop generated through the nmos transistors 801 and 802 is 0 . 8 v , and the voltage drop generated through the nmos transistor 803 is 0 . 4 v . that is , the negative voltage vb is − 0 . 4 v . similarly , the negative voltage vb can be changed by changing the programmable voltage vprog . for example , when the programmable voltage vprog is 0 . 7 v , the negative voltage vb is − 0 . 35 v , and when the programmable voltage vprog is 0 . 6 v , the negative voltage vb becomes − 0 . 3 v . in accordance with the above - described circuit , the reference voltage of the vco 100 can be programmably controlled and set to an appropriate value in accordance with the oscillation frequency . that is , similar to the first embodiment , with reference to fig3 which shows the relationship between the charge pump current and the control voltage vcont , when the reference voltage of the vco 100 is 0 v , the control voltage vcont is present at the point a . however , when using the negative voltage vb as the reference voltage , the control voltage vcont shifts to the point b , so that the linear area 300 can be avoided , and an area can be used where the outflow current iup and the inflow current idown are almost identical to each other . that is , using the negative - voltage generating circuit 105 and the voltage control circuit 700 allows the transistor , by which the charge pump circuit 102 outputs the outflow current , to operate in a saturation area . here , the first voltage control circuit of the present invention corresponds to the voltage control circuit 700 . in addition , the nmos transistors 801 to 803 may have different transistor sizes . a fourth embodiment of the present invention will be explained with reference to fig9 and 10 . fig4 is a diagram showing the structure of a pll circuit of the present embodiment . in fig4 , reference numeral 900 indicates a voltage control circuit ( i . e ., voltage control part ). the other structural elements are identical to the corresponding elements in fig4 , and explanations thereof are omitted here . to the phase comparator 101 , the reference clock signal vin and the fed - back oscillation signal are input , where the latter is the oscillation signal vout of the vco 400 , which is fed back . the increase signal up and the decrease signal down output from the phase comparator 101 are each input into the charge pump circuit 402 . in addition , the output ( i . e ., for outputting the control voltage vcont ) of the charge pump circuit 402 is connected to the one end of the capacitor 104 which forms the loop filter 103 , and the control voltage vcont is also input into the vco 400 . the other end of the capacitor 104 is grounded . additionally , the signal ( i . e ., voltage vp ) output from the booster circuit 405 is input into the voltage control circuit 900 . the signal ( i . e ., voltage vp ) output from the voltage control circuit 900 is input as the power source voltage into the charge pump circuit 402 . furthermore , a programmable voltage vprog is input into the voltage control circuit 900 via a control terminal thereof . the present pll circuit is also of the charge pump type . the basic operation of the present pll circuit is identical to that of the first embodiment , and explanations thereof are omitted . below , distinctive operations of the present embodiment will be described . the booster circuit 405 generates the voltage vp , which is higher than the power source voltage vdd . the voltage control circuit 900 controls the voltage vp in accordance with the programmable voltage vprog , so as to convert the voltage vp into the voltage vp . the charge pump circuit 402 is driven by the voltage vp output from the voltage control circuit 900 . that is , the charge pump circuit 402 operates by the power source voltage vp (& gt ; vdd ), and the elements other than the charge pump circuit 402 operate by the power source voltage vdd . a concrete example of the voltage control circuit 900 will be shown with reference to fig1 . that is , fig1 is a circuit diagram of the voltage control circuit 900 . in fig1 , reference numeral 1000 indicates an amplifier , and reference numeral 1001 indicates a pmos transistor . one input terminal of the amplifier 1000 functions as the control terminal of the voltage control circuit 900 , and the programmable voltage vprog is input into this control terminal . the other input terminal of the amplifier 1000 is connected to the drain of the pmos transistor 1001 , and is also used for outputting the voltage vp . the output terminal of the amplifier 1000 is connected to the gate of the pmos transistor 1001 . in addition , the voltage vp is input into the source of the pmos transistor 1001 . next , the operation of the voltage control circuit 900 will be explained . first , it is assumed that the programmable voltage vprog is 2 . 5 v , and the voltage vp is 3 . 0 v . as the programmable voltage vprog ( 2 . 5v ) is input into the above - described one input terminal of the amplifier 1000 , the voltage vp at the other input terminal of the amplifier 1000 is also 2 . 5 v . similarly , the voltage vp can be changed by changing the programmable voltage vprog . for example , when the programmable voltage vprog is 2 . 8 v , the voltage vp is also 2 . 8 v . that is , in the present circuit , the power source voltage of the charge pump circuit 402 can be programmably controlled . therefore , similar to the second embodiment , in the present embodiment , the linear area 601 ( see fig6 b ) can be avoided as indicated by the point a , and an area can be used where the outflow current iup and the inflow current idown are almost identical to each other . that is , using the booster circuit 405 and the voltage control circuit 900 allows the pmos transistor 503 , by which the charge pump circuit 402 outputs the outflow current , to operate in a saturation area . in addition , the second voltage control circuit of the present invention corresponds to the voltage control circuit 900 . a fifth embodiment of the present invention will be explained with reference to fig1 . the present embodiment relates to a pll circuit which is included in a dram . fig1 is a block diagram showing the dram and the pll circuit included in the dram of the fifth embodiment . in fig1 , reference numeral 2000 indicates the dram , reference numeral 2100 indicates a high - voltage generating part 2100 , reference numeral 2200 indicates a negative - voltage generating part , and reference numeral 2300 indicates the pll circuit . the other structural elements are identical to the corresponding elements in fig7 , and explanations thereof are omitted here . in addition , in the dram 2000 , structural elements other than those shown in fig1 are not shown in the figure . the dram 2000 includes the pll circuit 2300 used for controlling each part in the dram . the pll circuit 2300 has a structure in which the negative - voltage generating circuit 105 is excluded from the pll circuit of the third embodiment . the dram 2000 also includes the negative - voltage generating part 2200 for generating a back bias voltage vbb which is a negative voltage , and the high - voltage generating part 2100 for generating a word - line voltage vpp which is higher than the power source voltage vdd . as generally known , the back bias voltage vbb and the word - line voltage vpp are voltages used for operations such as writing , reading , and deletion of data with respect to the dram 2000 . for example , regarding a dram which operates with the power source voltage vdd of 1 . 8 v , the back bias voltage vbb is − 0 . 5 v , and the word - line voltage vpp is 3 v . as described in the third embodiment , the pll circuit in accordance with the present invention can be implemented by inputting the back bias voltage vbb into the voltage control circuit 700 , thereby omitting the negative - voltage generating circuit 105 . that is , the reference voltage of the vco 100 is the negative voltage provided by the dram 2000 which is controlled by the pll circuit 2300 . similar to the first embodiment , in accordance with the structure of the fifth embodiment , when the reference voltage of the vco 100 is 0 v , the control voltage vcont is present at the point a ( see fig3 ). however , when using the negative voltage vb as the reference voltage , the control voltage vcont shifts to the point b , thereby avoiding the linear area 300 , and also setting the outflow current iup and the inflow current idown to almost identical values . additionally , similar to the first embodiment , the back bias voltage vbb may be directly applied as the reference voltage of the vco 100 , without using the voltage control circuit 700 . a sixth embodiment of the present invention will be explained with reference to fig1 . the present embodiment also relates to a pll circuit which is included in a dram . fig1 is a block diagram showing the dram and the pll circuit included in the dram of the sixth embodiment . in fig1 , reference numeral 3000 indicates the dram , reference numeral 3100 indicates the pll circuit . the other structural elements are identical to the corresponding elements in fig9 and 11 , and explanations thereof are omitted here . in addition , in the dram 3000 , structural elements other than those shown in fig1 are not shown in the figure . the dram 3000 includes the pll circuit 3100 used for controlling each part in the dram . the pll circuit 3100 has a structure in which the booster circuit 405 is excluded from the pll circuit of the fourth embodiment . in addition , similar to the fifth embodiment , the dram 3000 also includes the negative - voltage generating part 2200 for generating the back bias voltage vbb which is a negative voltage , and a high - voltage generating part 2100 for generating the word - line voltage vpp which is higher than the power source voltage vdd . in the present embodiment , the pll circuit in accordance with the present invention can be implemented by inputting the word - line voltage vpp into the voltage control circuit 900 , thereby omitting the booster circuit 405 . that is , the charge pump circuit 402 is driven by a voltage higher than the power source voltage provided by the dram 3000 which is controlled by the pll circuit 3100 . similar to the second embodiment , in accordance with the structure of the sixth embodiment , as shown by the point a in fig6 b , the linear area 601 can be avoided , and the outflow current iup and the inflow current idown can be set to almost identical values . additionally , similar to the second embodiment , the word - line voltage vpp may be directly applied as the power supply voltage of the charge pump circuit 402 without using the voltage control circuit 900 , so that the charge pump circuit 402 is driven by the word - line voltage vpp . while preferred embodiments of the invention have been described and illustrated above , it should be understood that these are exemplary embodiments of the invention and are not to be considered as limiting . additions , omissions , substitutions , and other modifications can be made without departing from the scope of the present invention . accordingly , the invention is not to be considered as being limited by the foregoing description , and is only limited by the scope of the appended claims . for example , the vco and the charge pump circuit may each have a structure other than those described above . the structure of the pll circuit is also not limited to those described above . for example , ( i ) the signal output from the vco may be frequency - divided using a frequency divider , and then input into the phase comparator , or ( ii ) the reference clock signal may be frequency - divided using a frequency divider , and then input into the phase comparator . in addition , the negative voltages vb and vb , the voltages vp and vp , the back bias voltage vbb , and the word - line voltage vpp are provided as examples , and another kind of voltage may be used . furthermore , the pll circuit may simultaneously include some structural elements belonging to different embodiments described above . the oscillation circuit of the present invention corresponds to ( i ) a circuit consisting of the charge pump circuit 102 , the loop filter 103 , and the vco 100 in the first embodiment and the third embodiment , and ( ii ) a circuit consisting of the charge pump circuit 402 , the loop filter 103 , and the vco 400 in the second embodiment and the fourth embodiment . the bias control circuit of the present invention corresponds to ( i ) the negative - voltage generating circuit 105 in the first embodiment , ( ii ) the booster circuit 405 in the second embodiment , ( iii ) a circuit consisting of the voltage control circuit 700 ( i . e ., the first voltage control circuit ) and the negative - voltage generating circuit 105 in the third embodiment , and ( iv ) a circuit consisting of the voltage control circuit 900 ( i . e ., the second voltage control circuit ) and the booster circuit 405 in the fourth embodiment . additionally , in the voltage - controlled oscillator of the present invention , the first pmos transistor corresponds to the pmos transistor 201 , the second pmos transistor corresponds to the pmos transistor 203 , the third pmos transistor corresponds to the pmos transistor 205 , the first nmos transistor corresponds to the nmos transistor 202 , the second nmos transistor corresponds to the nmos transistor 204 , and the third nmos transistor corresponds to the nmos transistor 206 . on the other hand , in the charge pump circuit of the present invention , the first pmos transistor corresponds to the pmos transistor 501 , the second pmos transistor corresponds to the pmos transistor 503 , the third pmos transistor corresponds to the pmos transistor 504 , the first nmos transistor corresponds to the nmos transistor 502 , the second nmos transistor corresponds to the nmos transistor 505 , and the third nmos transistor corresponds to the nmos transistor 506 . additionally , in the first voltage control circuit of the present invention , the first nmos transistor corresponds to the nmos transistor 801 , the second nmos transistor corresponds to the nmos transistor 802 , the third nmos transistor corresponds to the nmos transistor 803 , the fourth nmos transistor corresponds to the nmos transistor 804 , and the amplifier corresponds to the amplifier 800 . on the other hand , in the second voltage control circuit of the present invention , the first pmos transistor corresponds to the pmos transistor 1001 , and the amplifier corresponds to the amplifier 1000 .