fig3 globally illustrates in the form of diagrams a circuit according to the invention . this circuit comprises , on the side of the control circuit 10 connected to the ground , a pulse coder 40 and , on the side of the gate control circuit 20 connected to the floating voltage v f , a decoder 50 , separated by a level translating circuit 30 . the decoder is illustrated at the input of circuit 20 . in fact , it will be embedded in this circuit in order to be arranged behind the places where parasitic pulses are liable to appear , to make it possible to differentiate coded pulses from coder 40 from parasitic pulses , as will clearly appear in the following description . an exemplary coding circuit 40 as part of control circuit 10 is illustrated in fig4 . this circuit 40 comprises a pulse generating oscillator 41 , the output of which is applied to the input c of a counter 42 . the control signal determining the circuit output appears on its input in and is set from a low level to a high level when it is desired to determine switching on of the power switch 1 . the outputs outa and outb of this circuit appear at the output of or gates o1 and o2 . signal in is applied to the input of an and gate a1 and , through an inverter i1 , to the input of an and gate a2 . the output of gate a1 is sent to a first input of an or gate o3 , and and gate a3 , an and gate a4 and an and gate a5 . the output of and gate a2 is sent to the second input of or gate o3 , and to the first inputs of the and gates a6 , a7 and a8 . the output of and gate a5 is sent to the input r of a d - type flip - flop 43 and to the input c of a d - type flip - flop 44 . the output of and gate as is sent to the input c of flip - flop 43 and to the input r of flip - flop 44 inputs d of flip - flops 43 and 44 are set to a positive voltage and the reverse outputs q of these flip - flops are respectively sent to each of the second inputs of and gates a1 and a2 . the output of the or gate o3 is sent to the input r of counter 42 . the output of rank 0 of this counter 42 is sent to a first input of a 3 - inputs and gate a9 , the second and third inputs of which receive the outputs of rank 1 and 2 of counter 42 through inverters i2 and i3 . the fourth output of counter 42 is sent to the second inputs of gates a5 and as . the output of rank 0 of counter 42 is also sent to the second inputs of gates a3 and a6 . the output of gate a9 is sent to the second inputs of gates a4 and a7 . gate o1 receives the outputs of gates a3 and a7 and gate o2 receives the output of 35 gates a4 and a6 . the operation of this circuit will be explained in case of a switching on order of the power switch 1 . for this purpose , one has indicated in fig6 signal in , which passes from a low level to a high level during the reception of a switching on order and the resulting coded output signals outa and outb , and by numbers , labelled in the same way , the signals appearing at various positions of the circuit . it is assumed that initially output q of flip - flop 44 ( 1 &# 39 ;) is at a high level and that output q of flip - flop 43 ( 2 &# 39 ;) is at a low level . the switching of input in causes the output ( 3 &# 39 ;) of and gate a1 to be set to high level and the output ( 4 &# 39 ;) of and gate a2 remains set to low level . the output ( 5 &# 39 ;) of gate o3 is also set to high level , simultaneously with the output ( 3 &# 39 ;) of and gate a1 . the output ( 6 &# 39 ;) of oscillator 41 continuously supplies square pulses . the signal ( 7 &# 39 ;) on the counting output 0 of counter 42 supplies square pulses at a frequency half of that of the oscillator 41 . the output ( 8 &# 39 ;) of and gate a9 only supplies the first square wave and the output signal ( 9 &# 39 ;) of the counting output 4 of counter 42 supplies a pulse when four square waves are obtained at the counting output 0 ( 7 &# 39 ;). this signal ( 9 &# 39 ;) applied to gates a5 and a8 causes signals ( 1 &# 39 ;) and ( 2 &# 39 ;) to change their state ( at outputs q of the d - type flip - flops 44 and 43 ). this results in the switching of the output state ( 3 &# 39 ;) of and gate a1 , and therefore of the output ( 5 &# 39 ;) of the or gate o3 , and inhibition of counter 42 . it can be seen that the output outa of gate o1 corresponds to signal ( 7 &# 39 ;) and that the output outb of gate o2 corresponds to signal ( 8 &# 39 ;). therefore , one finally obtains at the circuit output a signal outa constituted by four successive pulses and a signal outb constituted by one pulse coinciding with the first pulse on output outa . fig7 similarly shows signals appearing at input in , at positions ( 1 &# 39 ;) to ( 9 &# 39 ;) and on outputs outa and outb when signal in passes from high level to low level for determining the switching off of the power switch 1 . this figure can easily be understood by referring to the detailed description of fig6 . fig7 shows that a switching off order will correspond to the emission on output outa of one pulse , and on output outb to emission of four successive pulses , the first of which coincides with the pulse on output outa . those skilled in the art will note that there are very numerous methods for realizing logic circuits supplying output signals such as those labelled outa and outb . however , the choice of the type of control signals supplied at the output of the coding circuit 40 constitutes one of the aspects of the invention . indeed , according to the invention , and as will be seen later on , it has been noted that it was particularly advantageous to emit as coded signals , first , at least one simultaneous pulse onto the two output paths and , then , a succession of coded pulses on the only path that has to be specifically controlled . fig5 shows a general diagram of the circuit according to the invention , wherein the decoding part is illustrated in greater detail . control circuit 10 supplying an input signal in to a coder 40 provided with outputs outa and outb . these outputs are sent to level translators corresponding to components 31 - 34 of fig3 . these level translators send signals to inputs s and r of a flip - flop 21 through a decoding circuit 50 . level translators 31 , 33 and 32 , 34 are conventional circuits , similar to those that would be used in case of fig2 . therefore , they will be not be described in detail . their outputs are labelled out31 and out32 . in the absence of parasitic pulses , signals on outputs out32 and out31 respectively correspond to output signals outa and outb of coder 40 . in the figure , black triangles with their tip oriented downwardly represent the points connected to the floating reference v f . decoder 50 receives on its two inputs signals out32 and out31 . signal out32 is sent through two successive inverters i11 and i12 to the input c of a counter 51 and signals out31 is sent through two successive inverters i13 and i14 to the input c of a d - type flip - flop 52 . the junction of inverters i11 and i12 is connected to the first input of an and gate a11 , the second input of which is connected to the junction of inverters i13 and i14 and the output is connected to the reset terminals r of counter 51 and flip - flop 52 . the two outputs 0 and 1 of counter 51 are sent to two inputs of an and gate a12 , the output of which is connected to the input s of flip - flop 21 . the q output of flip - flop 52 is sent to the r input of the rs flip - flop 21 . the q output of flip - flop 52 is sent to its input d . this circuit operates as follows . signals outa and outb respectively appear at the output of inverters i12 and i14 . and gate a11 transmits the first pulse which is identical in outa and outb and resets counter 51 and flip - flop 52 . then : in case of a switching on order , the signal at the output of inverter i12 exhibits a succession of zero crossing ( pulses ) while the signal at the output of inverter i14 remains set to high level . as a result , counter 51 supplies simultaneous high outputs after counting a predetermined number of pulses ( here 3 ) and then and gate a12 controls the s input of flip - flop 21 , the q output of which then passes to high level . in case of a switching off order , inverter i14 supplies a succession of pulses at the clock input c of flip - flop 52 and , as soon as there is a first non - simultaneous pulse on the other path , the output q of this flip - flop , is set to high level and resets flip - flop 21 . it will be noted that parasitic pulses on the floating reference v f , resulting for example from very high voltage gradients , cause simultaneous pulses to occur at outputs out32 and out31 of the level translators . with the coding system according to the invention , providing simultaneous resetting pulses of the decoder before any information signal is sent , such parasitic pulses will have no effect on the circuit operation . according to another advantage of the invention , the switching on signal resulting from the output of counter 51 sent to input s of flip - flop 21 is delayed while the switching off signal resulting from the output q of flip - flop 52 is sent to the input r of flip - flop 21 and is immediately transmitted . then , a slight delay inherently occurs between a switching on and a switching off order , this delay being adjustable with the oscillation frequency of coder 40 . since , as explained above , a circuit according to the invention is designed to be inserted in a bridge - connected control circuit , this prevents two bridge power switches from being simultaneously switched on , which might cause shorting of a bridge leg . whereas a coder arranged on the side of circuits connected to the ground and a decoder arranged on the side of circuits connected to the floating voltage have been described , each of these components can be replaced by a coder / decoder for sending back monitoring information about the operating state of a floating power switch .