the data generating system of the present invention can be implemented in software , firmware , hardware , or a combination thereof . in the preferred embodiment of the invention , which is intended to be a non - limiting example , a portion of the system is implemented in software that is executed by a computer , for example , but not limited to , a server , a personal computer , work station , minicomputer , or main frame computer . the software based portion of the data generating system , which comprises an ordered listing of executable instructions for implementing logical functions , can be embodied in any computer - readable medium for use by , or in connection with , an instruction execution system , apparatus , or device such as a computer - based system or processor containing system , or other system that can fetch the instructions from the instruction execution system , apparatus , or device and execute the instructions . in the context of this document , a “ computer - readable medium ” can be any means that can contain , store , communicate , propagate or transport the program for use by or in connection with the instruction execution system , apparatus or device . the computer - readable medium can be , for example , but not limited to , an electronic , magnetic , optical , electromagnetic , infrared , or semiconductor system , apparatus , device , or propagation medium . more specific examples ( a non - exhaustive list ) of the computer - readable medium would include the following : an electrical connection ( electronic ) having one or more wires , a portable computer diskette ( magnetic ), a random access memory ( ram ) ( magnetic ), a read - only memory ( rom ) ( magnetic ), an erasable programmable read - only memory ( eprom or flash memory ) ( magnetic ), an optical fiber ( optical ), and a portable compact disk read - only memory ( cd rom ) ( optical ). note that the computer - readable medium could even be paper or another suitable medium upon which the program is printed , as the program can be electronically captured , via for instance , optical scanning of the paper or other medium , then compiled , interpreted or otherwise processed in a suitable manner , if necessary , and then stored in a computer memory . referring now to the drawings , wherein like reference numerals designate corresponding parts throughout the drawings , fig1 is a typical computer or processor - based system 2 that may be utilized to create a bsdl file for testing an ic . the computer system 2 generally comprises a processor 4 , a storage device 6 , and a computer memory 8 . the processor 4 accepts data from the computer memory 8 over a local interface 10 , such as a bus ( es ), or a dedicated path . specifically , with regard to the preferred embodiment of the invention , the local interface 10 is a pci bus . the computer memory 8 has an operating system 12 defined therein and data generation software 14 . the data generation software 14 is utilized to create the bsdl file , as is described in detail below . it should be noted that the data generation software may be perl , c +, or any other ascii producing software . the computer system 2 also comprises input device ( s ) 16 and output device ( s ) 18 . generally , the computer system 2 may run any of a number of different platforms and operating systems , including , but not limited to , the unix ®, windowsnt ®, sunsolaris ® or any such operating system . a pci slot 22 may also be located within the computer system 2 , which is attached to the local interface 10 , for providing a means for a peripheral device , such as a network interface card ( nic ), to attach to the computer system 2 . [ 0023 ] fig2 is a block diagram of an ic 102 that may be tested by the bsdl file after creation by the data generation software 14 . it should be noted that the bsdl file allows the description of testability features of components within the ic 102 that comply with the ieee standard 1149 . 1 . as is explained below , the bsdl file can be used by tools that make use of the testability features of components within the ic 102 . such tools include testability analyzers , test generators , and / or fault diagnosis routines , such as , but not limited to , simulation program for integrated circuit emphasis ( spice ). with the bsdl file , which describes the ic 102 , and with knowledge of the ieee 1149 . 1 standard , software tools are capable of understanding data transport characteristics of the ic 102 , specifically , how the ic 102 captures , shifts , and / or updates data . as is shown by fig2 the ic 102 comprises a series of pads , designated as pad 1 104 a , pad 2 104 b , pad 3 104 c , pad 4 104 d , pad 5 104 e , pad 6 104 f , pad 7 104 g , and pad 8 104 h . it should be noted that the number of pads ( summarily denoted as 104 ) within the ic 102 may differ from the number of pads 104 shown by fig2 . a logic portion 112 is located within the ic 102 , which comprises logic specific to the functionality of the ic 102 . therefore , the logic portion 112 may be structurally and functionally different for different ics 102 . each pad 104 is connected to an input / output ( i / o ) pin ( summarily denoted as 106 ) that allows the ic 102 to connect to a printed circuit board ( pcb ) ( not shown ). specifically , as shown by fig2 pad 1 104 a is connected to a first i / o pin 106 a ; pad 2 104 b is connected to a second i / o pin 106 b ; pad 3 104 c is connected to a third i / o pin 106 c ; pad 4 104 d is connected to a fourth i / o pin 106 d ; pad 5 104 e is connected to a fifth i / o pin 106 e ; pad 6 104 f is connected to a sixth i / o pin 106 f ; pad 7 104 g is connected to a seventh 1 / 0 pin 106 g ; and , pad 8 104 h is connected to an eighth i / o pin 106 h . the pads 104 are serially connected to each other via a boundary register scan chain 114 . as is known in the art , the boundary register scan chain 114 connects jtag registers ( shown by fig3 ) in serial within each pad 104 to allow for testing of electrical properties and / or conductivity of the ic 102 . an example of a testing procedure may include bypassing specific jtag registers and loading data into a different jtag register , wherein the data is later captured at a different location within the boundary - scan chain 114 , thereby allowing for verification of electrical properties and / or conductivity of the ic 102 . a test access port ( tap ) controller 116 is located within the ic 102 to facilitate ic 102 testing . the tap controller 116 , is described in detail by the ieee 1149 . 1 standard , which is incorporated herein by reference in its entirety . specifically , the tap controller 116 is utilized by an ic tester or testing program , such as , but not limited to , spice , to execute a set of ic 102 testing vectors that have been previously generated by use of the generated bsdl file . as is known in the art , the ic 102 testing vectors are test stimuli used to test integrity of pads 104 , connectivity within pads 104 , and testability within the ic 102 . the ic 102 testing process is further discussed below . the tap controller 116 is preferably a state machine that controls operations associated with jtag registers so that relationships between jtag registers and i / o pins 106 may be tested . preferably , the tap controller 116 is connected to the first pad 104 within the boundary register scan chain 114 . in addition , the tap controller 116 is connected to an output of the last pad 104 , in accordance with fig2 pad 8 104 h , located within the ic 102 . basic operation of the tap controller 116 is controlled through four pins that are located on the ic 102 and connected to the tap controller 116 via interconnect . the four pins include , a test clock ( tck ) pin 122 , a test mode select ( tms ) pin 124 , a test data in ( tdi ) pin 126 , and a test data out ( tdo ) pin 128 . the tck pin 122 and the tms pin 124 direct signals between tap controller 116 states . the tdi pin 126 and the tdo pin 128 receive data input and output signals for the boundary - scan chain 114 . more specifically , the tdi pin 126 may be utilized to receive serial data from the tester or test program that is to be transmitted to the boundary - scan chain 114 for testing purposes . the tap controller 116 receives the serial data from the tdi pin 126 via interconnect and is capable of transmitting the data to the boundary - scan chain 114 . it should be noted that a fifth pin ( trst ) may optionally be implemented as an asynchronous reset to the tap controller 116 . the tdo pin 128 may then be utilized by the tester or testing program to observe the serial data after being received by the tap controller 116 . [ 0030 ] fig3 is a block diagram further illustrating a pad 104 shown by fig2 . as shown by fig3 a pad 104 comprises a driver circuit 152 , a receiver circuit 154 , a jt jtag register 162 , a jo jtag register 164 , and a ji jtag register 166 . preferably , the jtag registers 162 , 164 , 166 are master / slave flip - flops that may be controlled by the tap controller 116 ( fig2 ). as has been mentioned above , the jtag registers 162 , 164 , 166 are serially connected via the boundary - scan chain 114 . the jt jtag register 162 may be utilized to tri - state the driver circuit 152 . the jo jtag register 164 may be utilized to drive serial data to the driver circuit 152 and / or communicate with the logic portion 112 ( fig2 ) of the ic 102 . in addition , the ji jtag register 166 receives an output of the receiver circuit 154 and / or communicates with the logic portion 112 of the ic 102 . preferably , the driver circuit 152 and the receiver circuit 154 are three - latch devices that may be shifted . the driver circuit 152 may be utilized to drive serial data received from the jo jtag register 164 , while the receiver circuit 154 may be utilized to transmit serial data to the ji jtag register 166 . the jt jtag register 162 is connected to an input of the pad 104 and the jo jtag register 164 via the boundary - scan chain 114 . as stated above , the jt jtag register 162 is also connected to the driver circuit 152 for tri - stating . the jo jtag register 164 is connected to the jt jtag register 162 and the ji jtag register 166 via the boundary - scan chain 114 . in addition , the jo tag register 164 is connected to an input of the driver circuit 152 for providing the driver circuit 152 with serial data utilized for testing the ic 102 . the ji jtag register 166 is connected to the jo jtag register 164 and an output of the pad 104 via the boundary - scan chain 114 . as mentioned above , the boundary - scan chain 114 is also connected to other pads 104 . the ji jtag register 166 is also connected to an output of the receiver circuit 154 . an output of the driver circuit 152 and an input of the receiver circuit 154 are connected to each other , as well as being connected to an i / o pin 106 ( fig2 ). prior to placement of the ic 102 onto a pcb , electrical characteristics and / or connectivity of the ic 102 are tested . testing of the ic 102 is performed via use of the bsdl file generated by the data generation software 14 . as stated above , the tester , or testing program , uses the generated bsdl file to generate a set of vectors for testing integrity of pads 104 and testability within the ic 102 . the bsdl file describes the internal structure of the ic 102 and relationships between jtag registers 162 , 164 , 166 and i / o pins 106 within each pad 104 , and between different pads 104 a - 104 h within the ic 102 . the tap controller 116 may then be utilized by the tester , or testing program , to execute the testing vectors . traditionally , the bsdl file is created by manually determining and providing relationships within each pad 104 . relationships within each pad 104 may be determined by utilizing a netlist , such as a verilog netlist , that represents conductivity within the pad 104 . the netlist may be stored within the storage device 6 ( fig1 ) or elsewhere . as is known in the art , a netlist is a logical representation of internal connectivity of an ic . relationships within each pad 104 include connections between jtag registers 162 , 164 , 166 , the driver circuit 152 , the receiver circuit 154 , and the i / o pin 106 . to complicate matters , the bsdl file requires definition of relationships for all pads 104 located within the ic 102 . since there may be many pads 104 located on a single ic 102 , different names are required for each different pad 104 , including associated jtag registers 162 , 164 , 166 , driver circuit 152 , receiver circuit 154 , and i / o pin 106 , when creating the bsdl file . manually determining and providing the names and relationships of each different pad 104 and associated jtag registers 162 , 164 , 166 , driver circuit 152 , receiver circuit 154 , and i / o pin 106 for the bsdl file , is a tedious task . [ 0035 ] fig4 is a flow chart that shows the architecture , functionality , and operation of a possible implementation of the present data generating system 100 that automates the process of creating the bsdl file . in this regard , each block represents a module , segment , or portion of code , which comprises one or more executable instructions for implementing the specified logical function ( s ). it should also be noted that in some alternative implementations , the functions noted in the blocks may occur out of the order noted . for example , two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order , depending upon the functionality involved , as will be further clarified herein below . as shown by block 202 , a flat netlist is created for the ic 102 . the flat netlist is created by traversing hierarchical netlists that describe portions of the ic 102 , for individual netlists focused upon the logic portion 112 of the ic 102 and the pads 104 , and combining connectivity information provided by the individual netlists into a single file , referred to herein as the flat netlist . the resulting flat netlist provides connectivity information , or data structures , that represent wires within the ic 102 , leaf cells within the ic 102 , and i / o pins 114 . as is known by those of ordinary skill in the art , leaf cells comprise registers and / or combinational cells such as an and gate or an or gate . as shown by block 204 , a script defined by the data generation software 14 ( fig1 ) is utilized to traverse the flat netlist , which defines data structures of the ic 102 , until a jtag register 162 , 164 , 166 is located . since the flat netlist represents data structures , the following describes traversal of the flat netlist as traversal of structures located within the ic 102 . traversal of the flat netlist begins from an input to the first pad 104 a , which is also the beginning of the boundary - scan line 114 , and which is connected to an output of the tap controller 116 . multiple logical devices may be connected to the boundary - scan line 114 including , but not limited to , buffers utilized to drive signals along the boundary - scan line 114 and leaf cells . as noted above , the traversal step preferably utilizes the previously created flat netlist ( block 202 ) since connections between leaf cells have been previously defined . as shown by block 206 , when a jtag register 162 , 164 , 166 has been located ( block 204 ), the name assigned to the located jtag register 162 , 164 , 166 is stored within a jtag register name list located within the storage device 6 ( fig1 ). a determination is then made as to whether additional jtag registers 162 , 164 , 166 are located within the ic 102 by progressing along the path of the boundary - scan line 114 ( block 208 ). determination of additional jtag registers 162 , 164 , 166 is performed by traversing the boundary - scan line 114 from an output of the previously located jtag register 162 , 164 , 166 until another leaf cell is found . if the next located leaf cell is not a jtag register 162 , 164 , 166 , wires connected to the next located leaf cell are then examined to determine if a jtag register 162 , 164 , 166 is connected to the wires . if another jtag register 162 , 164 , 166 is located , the name assigned to the located jtag register 162 , 164 , 166 is stored . the steps described by block 204 and block 206 are repeated until traversal of the ic 102 ends at the tap controller 116 . it should be noted that the jtag register names are stored within the storage device 6 in the same order that they were discovered during traversal . it should also be noted that completion of the traversing process , ending at the tap controller 116 , provides evidence that the jtag registers 162 , 164 , 166 located within the ic 102 are properly connected . as shown by block 212 , relationships between each jtag register 162 , 164 , 166 and an i / o pin 106 are determined and stored within the memory 8 ( fig1 ) for use in creating the bsdl file . it should be noted that the storage device 6 may be utilized for storing relationships between each jtag register 162 , 164 , 166 and an i / o pin 106 , as opposed to the memory 8 . determination of jtag register 162 , 164 , 166 and i / o pin 106 relationships is performed by the script sequentially searching the flat netlist for each jtag register 162 , 164 , 166 listed within the jtag register name list . for each jo jtag register 164 , the flat netlist is traversed , starting from the wire connected from an output of the jo jtag register 164 to the input of the driver circuit 152 . logic is continually traversed until an i / o pin 106 is located . the path from the output of the jo jtag register 164 to the i / o pin 106 is stored for use in creating the bsdl file . since description of the jo jtag 164 requires a description of the driver circuit 152 , which is tri - stated by the jt jtag register 162 , a description of the jt jtag register 162 is also required . therefore , the flat netlist is traversed from an output of the jt jtag register 162 to the driver circuit 152 and continued until an i / o pin is located 106 . the path from the output of the jt jtag register 162 to the i / o pin 106 is stored for use in creating the bsdl file . with reference to the ji jtag register 166 , the flat netlist is traversed from an output of the ji jtag register 162 to the output of the receiver circuit 154 and continued until an i / o pin 106 is located . the path from the output of the ji jtag register 166 to the i / o pin 106 is stored for use in creating the bsdl file . after storage of the jtag register names in the same order that they were discovered during traversal and storage of relationships between each jtag register 162 , 164 , 166 and an i / o pin 106 , the script automatically creates the bsdl ( block 214 ). the script automatically creates the bsdl file , or description of the ic 102 , by redefining the above mentioned stored names and relationships , using bsdl lexicography and syntax , into a format compatible with bsdl files . one of ordinary skill in the art would know how to redefine the stored names and relationships into a format compatible with bsdl files . it should be emphasized that the above - described embodiments of the present invention , particularly , any “ preferred ” embodiments , are merely possible examples of implementations , merely set forth for a clear understanding of the principles of the invention . many variations and modifications may be made to the above - described embodiment ( s ) of the invention without departing substantially from the spirit and principles of the invention . all such modifications and variations are intended to be included herein within the scope of this disclosure and the present invention and protected by the following claims .