the preferred embodiments of a semiconductor integrated circuit according to the present invention are described hereinbelow with reference to the accompanying figures . as shown in fig1 ( a ) and 2 ( b ), this semiconductor integrated circuit comprises a reference voltage generator 1 , aging voltage generator 2 , applied external voltage detector 3 , internal voltage selector 4 , power on detection circuit 9 , and voltage drop circuit 10 . it is to be noted that terminals ( a ) and ( b ) in fig2 ( a ) are connected to the same in fig2 ( b ) respectively . as shown in fig2 ( a ), the reference voltage generator 1 comprises a potential difference generator 11 , a differential amplifier formed from a comparator 12 and output buffer 13 , and an n - channel transistor nt3 connected between the ground ( indicated by an inverted triangle in the figures ) and connection t3 , which is between the comparator 12 and the output buffer 13 . the potential difference generator 11 comprises p - channel transistors pt1 , pt2 , and pt3 , which function as electrical resistances , and two diodes d1 and d2 , each with a different junction area . the transistor pt1 and diode d1 constitute one current path il connected to the ground , and the transistors pt2 and pt3 and the diode d2 constitute a current path i2 parallel to the current path i1 . the junction area ratio of the two diodes d1 and d2 is set at 1 : 10 ; when current is applied to these diodes d1 and d2 , a potential differential of approximately 60 mv is generated at the anodes of the diodes ( with diode d2 having the lower potential ) regardless of the ambient temperature . in addition , the on resistance of the transistors pt1 and pt2 is set equal , and the ratio of the on resistance of the transistors pt2 and pt3 is set to approximately 20 : 1 . thus , the connection t1 between the transistor pt1 and the diode d1 , and the connection t2 between transistors pt2 and pt3 , are both set to an approximately equal potential . the comparator 12 comprises a p - channel transistor pt4 which is connected to the external power supply 5 ( i . e ., the applied external voltage vex ) and functions as an electrical resistance , a pair of p - channel transistors pt5 and pt6 which are connected to the transistor pt4 , and a pair of n - channel transistors nt1 and nt2 each connected between and to the ground and transistors pt5 and pt6 , respectively . the gates of the transistors pt5 and pt6 are connected respectively to the connections t2 and t1 of the potential difference generator 11 , and the on resistances of the transistors pt5 and pt6 change according to the potentials of the connections t2 and t1 , respectively . the gates of the n - channel transistors nt1 and nt2 are connected to the external power supply 5 side terminal ( drain ) of the transistor nt1 , thus forming a current mirror circuit which provides an approximately equal current to the transistors pt5 and pt6 . therefore , a signal with a level corresponding to the potential difference ( negative or positive ) between the connections t1 and t2 of the potential difference generator 11 is output to the output terminal ( connection ) t3 between the transistors pt6 and nt2 . the output buffer 13 comprises a p - channel transistor pt7 which functions as an electrical resistance and is connected to the external power supply 5 , and a p - channel transistor pt8 and a n - channel transistor nt4 , which are complementary and are connected in direct sequence between the p - channel transistor pt7 and the ground . the gates of both transistors pt8 and nt4 are connected to the output terminal t3 , and a voltage ( reference voltage ) vc is generated at the connection t4 between the transistors pt8 and nt4 according to the signal level of the output terminal t3 . this voltage vc is applied to the potential difference generator 11 as negative feedback by a line 14 . a constant reference voltage vc ( here vc = 4 v ) is then generated at the connection t4 by the operation of a differential amplifier formed by the comparator 12 and output buffer 13 . the n - channel transistor nt3 receives an initialization signal described hereinbelow from the output terminal t6 of the power on detection circuit 9 , and is turned on or off by this initialization signal . referring to fig2 ( b ), the aging voltage generator 2 is composed of a p - channel transistor pt9 connected to the external power supply 5 , four diodes d4 , d5 , d6 , and d7 serially connected to the transistor pt9 , and a p - channel transistor pt10 connected between the ground and the last diode d7 . the gates of the transistors pt9 and pt10 are connected to the output terminal t10 of the internal voltage selector 4 , and are turned on or off by the signal level of the output terminal t10 . when power is supplied , the diodes d4 , d5 , d6 , and d7 each drop the voltage 0 . 5 - 0 . 6 v , resulting in a total voltage drop δv of 2 . 0 - 2 . 4 v . therefore , when the transistors pt9 and pt10 are on , the aging voltage generator 2 generates an aging voltage va , which is the applied external voltage vex dropped by δv , at the connection t5 between the diode d7 and transistor pt10 ( for simplicity , the on resistance of the transistor pt9 is ignored herein ). however , when the transistors pt9 and pt10 are off , the connection t5 is at floating state . again , as shown in fig2 ( a ), the applied external voltage detector 3 has a voltage dividing generator 31 and comparator 32 . the voltage dividing generator 31 comprises three p - channel transistors pt12 , pt13 , and pt14 , each having identical characteristics , connected serially between the ground and external power supply 5 . the gates of the transistors pt12 , pt13 , and pt14 are each connected to the terminal ( drain ) on the ground side . this voltage dividing generator 31 generates at the connection t7 between the transistors pt12 and pt13 a voltage - divided voltage , which is the applied external voltage vex voltage - divided to 2 / 3 , by means of the on resistance of the transistors pt12 , pt13 , and pt14 . the comparator 32 comprises a p - channel transistor pt15 , which is connected to the external power supply 5 and functions as an electrical resistance , a pair of p - channel transistors pt16 and pt17 which are connected to the transistor pt15 , and a pair of n - channel transistors nt7 and nt8 each connected between and to the ground and transistors pt16 and pt17 , respectively . the gate of the transistor pt16 is connected to the connection t7 of the voltage - dividing generator 31 , the gate of the transistor pt17 is connected to the output terminal ( connection ) t4 of the reference voltage generator 1 , and the on resistance of the transistors pt16 and pt17 changes according to the potential of the respective connections t7 and t4 . the gates of the transistors nt7 and nt8 are connected to the terminal ( drain ) on the external power supply 5 side of the transistor nt8 , forming a current mirror circuit , and supplying an approximately equal current to the transistors pt16 and pt17 . therefore , when the potential ( 2 / 3 ) vex of the connection t7 is greater than the potential ( reference voltage ) vc = 4 v of the connection t4 , the on resistance of the transistor pt16 becomes greater than the on resistance of the transistor pt17 , and a low level signal is output to the output terminal t8 between the transistors pt16 and nt7 . however , when the potential ( 2 / 3 ) vex of the connection t7 is less than the potential ( reference voltage ) vc = 4 v of the connection t4 , a high level signal is output to the output terminal t8 . in other words , the applied external voltage detector 3 outputs a low level signal to the output terminal t8 when the applied external voltage vex is greater than 6v , and a high level signal when the applied external voltage vex is less than 6 v . note that an n - channel transistor nt6 which functions as a capacitor is connected between the ground and the gate of the transistor pt16 of the comparator 32 to absorb noise . furthermore , an n - channel transistor nt5 is connected between the ground and the connection t7 of the voltage dividing generator 31 . the initialization signal output from the output terminal t6 of the power on detection circuit 9 is input to this transistor nt5 , which is turned on or off according to the level of the initialization signal . referring to fig2 ( b ), the internal voltage selector 4 comprises two serially connected invertors iv1 and iv2 , and a p - channel transistor pt18 . the input of the invertor iv1 is connected to the output terminal t8 of the applied external voltage detector 3 shown in fig2 ( a ). the invertor iv1 receives either a high or low level signal from the output terminal t8 , inverts the received signal , and outputs a wave - shaped signal to the output terminal t9 . specifically , when the applied external voltage vex is higher than 6 v , the signal output to the output terminal t9 is high , and when the applied external voltage vex is less than 6 v , the signal at output terminal t9 is low . the other invertor iv2 again inverts the signal output to the output terminal t9 by the invertor iv1 , and outputs the result to output terminal t10 . therefore , the signal output from the output terminal t10 is the same as that at the output terminal t8 , specifically , low when the applied external voltage vex is greater than 6 v , and high when the applied external voltage vex is less than 6 v . the p - channel transistor pt18 is connected between the output terminal t4 of the reference voltage generator 1 shown in fig2 ( a ) and the connection t5 of the aging voltage generator 2 , and is turned on or off by the low or high level signal applied to the gate from the output terminal t9 of the invertor iv1 . in other words , a high signal is applied to the gate when the applied external voltage vex is higher than 6 v and the transistor pt18 becomes off , and when the applied external voltage vex is less than 6 v , a low level signal is applied to the gate and the transistor pt18 becomes on . therefore , when the applied external voltage vex is higher than 6 v , the output terminal t4 of the reference voltage generator 1 is electrically separated from the connection t5 of the aging voltage generator 2 . because the output terminal t10 of the internal voltage selector 4 becomes low at this time as described above , both p - channel transistors pt9 and pt10 in the aging voltage generator 2 become on , and the level of the connection t5 becomes the aging voltage va . when the applied external voltage vex is lower than 6 v , conductivity exists between the output terminal t4 of the reference voltage generator 1 and connection t5 of the aging voltage generator 2 . because the output terminal t10 becomes high at this time , and both p - channel transistors pt9 and pt10 become off , the level of the connection t5 becomes the reference voltage vc . as shown in fig2 ( a ), the power on detection circuit 9 comprises an electrical resistance r1 connected to the external power supply 5 , three diodes d8 , d9 , and d10 connected serially between the resistance r1 and ground , and two invertors iv3 and iv4 serially connected to the connection t12 between the resistance r1 and the diode d8 . when the external power supply 5 is turned on , the potential of the connection t12 rises together with the rise in the applied external voltage vex , and reaches an approximately constant value when the 1 . 5 - 1 . 6 - v voltage drop of the three diodes d8 , d9 , and d10 is reached . at this time the invertor iv3 is driven by the applied external voltage vex , and receives the relative potential difference of the connection t12 based on the applied external voltage vex as the input . immediately after the external power supply is turned on , the input to the invertor iv3 is high , but becomes low when the value of the applied external voltage vex exceeds approximately 3 v . therefore , the output of the invertor iv3 is low immediately after the power is turned on , and becomes high after a specific amount of time . the invertor iv4 inverts the output of the first invertor iv3 , and therefore outputs to the output terminal t6 an initialization signal , which is a high level immediately after the power is turned on and becomes low after a specific period of time . as described hereinabove , the n - channel transistor nt3 of the reference voltage generator 1 and the n - channel transistor nt5 of the applied external voltage detector 3 are turned on ( after which they turn off ) based on this initialization signal for a specific period of time after the power supply is turned on . at this point in the reference voltage generator 1 , the connection t3 would be in floating state because the comparator 12 is not operating when the applied external voltage vex is low ( up to approximately 3 v ) immediately after the power supply is turned on , and the output of the output buffer 13 is therefore also in floating state . however , because the initialization signal causes the n - channel transistor nt3 to become on immediately after the external power supply is turned on , the connection t3 can be immediately set to a low level . therefore , the p - channel transistor pt8 and n - channel transistor nt4 of the output buffer 13 are respectively on and off , and the level of the output terminal t4 can track the applied external voltage vex immediately after the external power supply is turned on . furthermore , with the applied external voltage detector 3 , the connection t7 is open i . e . in floating state because p - channel transistors pt12 , pt13 and pt14 in the voltage dividing generator 31 are not on immediately after the external power supply is turned on , and the output of the comparator 32 would therefore normally be in floating state . however , by turning the n - channel transistor nt5 on by means of the initialization signal immediately after the external power supply is turned on , the connection t7 can be immediately set low . therefore , the p - channel transistor pt16 of the comparator 32 becomes on , and the output terminal t8 becomes high immediately after the external power supply is turned on . therefore , it is possible to turn the p - channel transistor pt18 of the internal voltage selector 4 on immediately after the external power supply is turned on , and immediately select the reference voltage generator 1 . as shown in fig2 ( b ), the voltage drop circuit 10 comprises a differential amplifier op11 , and a p - channel transistor pt11 connected between the external power supply 5 and internal circuit z as in a conventional device . a control voltage vcont ( vref or va ) occurring at the connection t5 of the aging voltage generator 2 is input to the inversion (-) terminal of the differential amplifier op11 and the internal voltage vint occurring at the connection t11 between the transistor pt11 and the internal circuit z is input to the non - inversion terminal (+) of the differential amplifier op11 , which thus controls the conductance of the transistor pt11 so that the potential difference ( vint - vref ) is approximately zero . in other words , this differential amplifier op11 and transistor p11 form a voltage follower . it is to be noted that except for those p - channel transistors for which connection wiring is shown in fig2 ( a ) ( pt13 and pt14 ), the applied external voltage vex is applied as the circuit board bias . furthermore , a circuit board bias potential of - 2 to - 3 v is applied to the well terminals of the n - channel transistors . in addition , the invertors iv1 to iv4 are driven by the applied external voltage vex . a semiconductor integrated circuit as thus described operates in whole as described below . during normal operation ( when applied external voltage vex = 4 - 6 v ), the applied external voltage detector 3 outputs a high level signal to the output terminal t8 . based on this signal , the internal voltage selector 4 outputs low and high level signals , respectively , to the output terminals t9 and t10 . thus , the p - channel transistor pt18 becomes on , and the p - channel transistors pt9 and pt10 become off . as a result , the reference voltage generator 1 is selected , and the reference voltage vref (= 4 v ) is output as the control voltage vcont to the output terminal t5 . then , as shown in fig3 an internal voltage vint approximately equal to the control voltage vcont = vref is generated by the voltage drop circuit 10 , and applied to the internal circuit z . however , during aging ( e . g ., when the applied external voltage vex & gt ; 6 v ), the applied external voltage detector 3 outputs a low level signal to the output terminal t8 as shown in fig2 ( a ). based on this signal , the internal voltage selector 4 shown in fig2 ( b ) outputs high and low signals , respectively , to the output terminals t9 and t10 . thus , the p - channel transistor pt18 becomes off , and the p - channel transistors pt9 and pt10 become on . as a result , the aging voltage generator 2 is selected , and the aging voltage va = vex - δv ( where δv = 2 . 0 - 2 . 4 v ) is output to the output terminal t5 as the control voltage vcont . the aging voltage va is thus greater than the constant reference voltage and less than the applied external voltage by an essentially constant voltage drop . then , as shown in fig3 the voltage drop circuit 10 generates an internal voltage vint approximately equal to the control voltage vcont = va , and applies the result to the internal circuit z . thus , according to the semiconductor integrated circuit , the internal voltage vint approximately equal to a constant reference voltage vref and lowered from the applied external voltage vext is applied to the internal circuit z during normal operation , while a high aging voltage va in response to the applied external voltage vext is applied to the internal circuit z during aging . it is to be noted that the voltage drop circuit 10 as described herein is constructed as is the conventional device shown in fig5 but it shall be not so limited . as shown in fig4 for example , the voltage drop circuit 10 may be comprised of a high current supply circuit 110 , low current supply circuit 120 , and standby current supply circuit 130 such that any one of these three circuits 110 , 120 , and 130 operates according to the consumption current level of the internal circuit z . in this example , the standby current supply circuit 130 operates in the standby mode during which current consumption is lowest . when this semiconductor integrated circuit is selected ( the chip enable signal ce is active ), the low current supply circuit 120 operates , and when the inactivation signal apd is inactive , the high current supply circuit 110 operates . the invention being thus described , it will be obvious that the same may be varied in many ways . such variations are not to be regarded as a departure from the spirit and scope of the invention , and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims .