fig4 depicts a pulse generating circuit 10 constructed in accordance with an embodiment of the present invention . the circuit 10 comprises a drift step recovery transistor ( dsrt ) 12 . the collector of the dsrt is connected to a direct current ( dc ) power source 14 . the emitter and base of the dsrt are connected across the secondary winding of a transformer 16 . also connected to the base of the dsrt is one end of a storage inductor 18 , the other end of the inductor 18 being connected to a common point or ground . the storage inductor 18 is connected in parallel with a separating diode 20 and a drift step recovery diode ( dsrd ) 22 , which are connected in series and in reverse polarity with respect to each other . as will be described below , the dsrd decreases the duration of the front of the load pulse , that is , contributes to a sharper pulse . a pumping inductor 24 and a pumping resistor 26 are connected in parallel with respect to the separating diode 20 to pump plasma into the dsrd . the dsrd and dsrt are available from the ioffe physico - technical institute , academy of science , st . petersburg , russia . a dsrd is preferred over other commercially available step recovery devices ( srds ) because a dsrd is characterized by fast voltage restoration and high holding voltage . a dsrd has a faster rise time ( e . g ., two to four times faster ) than a dsrt due to the difference in the dsrt structure . a dsrt has an additional gating electrode which , for the same voltage and current , increases the capacitance of the collector more so than in a two electrode dsrd . depending on the pulse characteristics desired , other commercially available step recovery devices ( srds ) can be used . for example , one or more srds can be used in the circuit 10 which undergo more than one stage of pulse compression to obtain a desired time characteristic . finally , the circuit 10 in fig4 comprises a load resistor 28 across which a pulse is generated . the load resistor 28 is connected at one end to the junction between the dsrd 22 and the pumping resistor 26 , and to a common point or ground at the other end . the inductor 18 , the separating diode 20 , the dsrd 22 , the pumping inductor 24 , the pumping resistor 26 and the load resistor 28 shall hereinafter be collectively described as a pulse forming network ( pfn ). the operation of the circuit in fig4 will now be described with reference to the graphs depicted in fig5 and 6 . at the initial state , the dsrt 12 blocks dc power from the pfn until a triggering pulse is applied to the dsrt via the transformer 16 ( as indicated at 30 in fig5 and 6 ). following the triggering pulse , the dsrt 12 switches to a conducting state and , accordingly , voltage is applied to the storage inductor 18 and to the pumping inductor 24 and pumping resistor 26 . the conducting state of the dsrt is indicated at 32 in fig6 . the voltage across the dsrt is less negative when it is conducting dc power to the pfn . the current in the storage and pumping inductors 18 and 24 , respectively , grow linearly with time , as indicated at 34 in fig5 . due to the blocking polarity of the separating diode 20 , no current flows through the separating diode while the dsrt 12 is conducting . the current from the pumping inductor 24 and resistor 26 instead flows into the dsrd 22 and injects electron - hole plasma into the dsrd , as evidenced by the coinciding lines in fig5 representing the current through pumping inductor 24 and the dsrd and indicated at 36 . at the end of the triggering pulse , the dsrt breaks current ( i . e ., after approximately 70 ns in the exemplary circuit 10 ), as indicated at 38 in fig6 . at essentially the same time , the storage inductor 18 changes polarity . accordingly , the separating diode 20 is biased in the conducting direction , and the current in the storage inductor is switched to the dsrd 22 . since the voltage drop across the dsrd 22 is relatively small , the storage inductor current is nearly constant , as indicated at 40 in fig5 . the current causes the plasma that had been injected into the dsrd to be extracted . once the plasma has been extracted , the dsrd very quickly breaks current ( within approximately 1 ns ), as indicated at 42 in fig5 and switches the storage inductor 18 current into the load to form an output pulse , as indicated at 44 in fig6 . with continued reference to fig4 and 6 , the front of the load current pulse ( indicated at 46 in fig5 ) corresponds to the turn off time of the dsrd , and the decay time is determined approximately by the relation : where l18 is the inductance of the storage inductor and r28 is the resistance of the load resistor . after the decay time has elapsed , the circuit elements in circuit 10 are returned to the initial , zero - current state in order for a new cycle of pulse generation to commence . thus , the minimum period between generated pulses is substantially determined by the sum of the pumping period , the duration of the highly conducting phase of the dsrd during reverse current , and the pulse decay time , as indicated at i , ii and iii , respectively , in fig5 . for high power dsrds , this minimum period does not exceed hundreds of nanoseconds , and can be as short as tens of nanoseconds . thus , the pulse repetition frequency of the pulse generating circuits constructed in accordance with various embodiments of the present invention can reach tens of megahertz . the pulse generating circuit 10 provides high pulse repetition frequency , but the decay time is increased by the capacitance cc 12 of the dsrt 12 collector , which is represented by a capacitor 48 ( fig4 ) drawn in phantom . when the dsrd 22 breaks current , part of the current is used to charge this capacitance cc 12 . consequently , the duration of the front of the load pulse becomes longer than the dsrd turn off time . during the pulse decay period , the capacitance cc 12 is discharged into the load , thereby lengthening the decay time . it must be noted that maximum blocking voltage of the dsrt is preferably not less than the sum of the output pulse voltage and the dc supply voltage . to eliminate or suppress these disadvantages , a pulse generating circuit 50 ( fig7 ) is provided with an additional inductor 52 connected between the base of the dsrt 12 and the junction of the storage inductor 18 and the separating diode 20 . after a triggering pulse is applied to the dsrt 12 via the transformer , dc source voltage is applied to inductors 18 and 52 which are connected in series . the current in each of these inductors is equal . thus , when the dsrt 12 breaks current , the dsrd 22 shunts the inductor 18 , and the inductor 52 starts to charge the collector capacitance cc 12 via the separating diode 20 and the dsrd 22 . as in the previous circuit 10 ( fig4 ), the inductor 18 current is nearly constant ( see 40 in fig4 ). the inductor 52 current , upon charging cc 12 , oscillates and changes its direction . thus , both currents of the inductors 18 and 52 flow in reverse direction to the dsrd and pull out the plasma which was previously injected into the dsrd via the pumping inductor 24 and resistor 26 . when the dsrd 22 breaks current , the total current of both of the inductors 18 and 52 is switched into the load resistance 28 . for the maximum efficiency , the pumping circuit ( i . e ., inductor 24 and resistor 26 ) is adjusted such that the dsrd 22 breaks current at the moment when the current in inductor 52 reaches its maximum value while oscillating ( as indicated at 54 in fig5 ). thus , the load pulse front is equal to the turn off time of the dsrd and is independent of the capacitance cc 12 of the collector of the dsrt 12 . further , the decay time is determined by : where l t is the total inductance of inductors 18 and 52 connected in parallel . thus , the decay time is also independent of the collector capacitance cc 12 . it is known that working voltage of the dsrd 22 can be increased by assembling a large number of dsrds in series , i . e ., in a stack . the same approach for the dsrt 12 is complicated and inefficient . the ratio of dsrt voltage to dsrd voltage depends on the collector &# 39 ; s capacitance cc 12 . the larger the capacitance cc 12 is , the less likely the dsrt voltage will be at the same dsrd peak voltage . it is possible to increase both the output voltage and the dsrd voltage , while keeping dsrt voltage low , by increasing capacitance cc 12 . this can be accomplished by adding an additional capacitor c , which is connected in parallel with the capacitance cc 12 as shown in phantom in fig7 . this approach , however , decreases the efficiency of the circuit 50 shown in fig7 . this is because the additional capacitor is initially charged from the dc voltage source 14 . while the dsrt 12 conducts , however , the energy stored in the capacitances cc 12 and c is lost to the heating of the dsrt . to avoid such losses , an additional capacitor 60 is connected at one end via a diode 58 to the junction of the dsrt 12 base and inductor 52 in accordance with another embodiment of the invention depicted in fig8 . the other end of the capacitor 60 is connected to a common point ( i . e ., can be grounded ). with continued reference to fig8 the diode 58 is connected with a polarity suitable to prevent the charge of capacitor 60 from the dc power supply 14 when the dsrt 12 is conducting . thus , the additional capacitor 60 does not store or lose energy from the power supply 14 , and has no negative effect on efficiency of the pulse generating circuit 56 in fig8 . when the dsrt 12 breaks current , the current in the inductor 52 charges the collector capacitance cc 12 and the additional capacitor 60 via the diode 58 , which passes the current from inductor 52 . the current through the capacitor 60 subsequently oscillates and is added to the dsrd 22 current . the connection of additional diode 58 and capacitor 60 increases the voltage across the dsrd 22 by increasing the period of time during which dsrd 22 is in a conducting state . in the circuit 56 , the pumping charge can be increased by decreasing the size of the pumping inductor 24 . when the dsrd 22 breaks current , that part of the dsrd current that is switched into the pumping inductor 24 increases . the energy corresponding to that part of the current , however , will be lost . to substantially avoid these losses , another pumping circuit is provided in a pulse generating circuit 62 constructed in accordance with another embodiment of the present invention . with reference to fig9 the end of the pumping inductor 24 , which had been connected to the base of dsrt ( fig4 ), is now connected to the base of a second dsrt 64 . a circuit comprising a diode 66 and a capacitor 68 is connected to the base of the second dsrt 64 in the same manner as the circuit comprising the diode 58 and capacitor 60 is connected to the base of the first dsrt 12 . the collector of the second dsrt 64 is connected to a dc power source 71 , which may be the same source 14 that is connected to the collector of the first dsrt . the emitter of the second dsrt 64 is connected to a transformer 70 . in the pumping circuit ( i . e ., inductor 24 and capacitor 68 ), an oscillating process occurs that is essentially identical to that of the main pumping circuit ( i . e ., the inductors 18 and 52 , and capacitor 60 ). when the dsrt 64 is turned on by a triggering pulse via the transformer 70 , the pumping current via the inductors 18 , 24 and 52 linearly increases , as shown in fig1 . when the dsrt 64 breaks current , the inductor 24 current reverses direction , and the currents of the inductors 18 , 24 and 52 are summed up on the dsrd 22 . when the dsrd 22 breaks current , as shown in fig1 , the currents of these inductors are switched into the load resistor 28 . generally speaking , the circuit 62 can be configured such that , during the current switching , the exchange of currents between the inductors is essentially negligible . for example , when one part of the inductor current goes to the load , the other part of the current goes to the pumping inductor 24 , and this part is lost . this current exchange is essentially absent , when the following conditions are satisfied : where i52 , i18 and i24 are the inductor currents ; l52 , l18 , and l24 are the corresponding inductances ; c60 , c68 are capacitances of the capacitors 60 and 68 ; and cc 12 , cc 64 are the capacitances of the dsrt collectors . the preferred method by which to satisfy conditions ( 3 ) and ( 4 ) is to make all inductors and capacitors equal , that is , in the case when only one dc power supply is used for both dsrts , the second dsrt 64 is preferably turned on at the middle of the turn on state period of the first dsrt 12 . the dsrt 12 or 64 current is where v is the power supply dc voltage , l is the total inductance , and t is the time . for the first dsrt 12 , the total inductance is the sum of the two inductors 52 and 18 . for the second dsrt 64 , there is only one inductor 24 . to reach the same current in both arms , the turn on period of the second dsrt is preferably half of the first turn on period ( fig1 ): in the case of turn on time being the same for both dsrts , the collector voltage of the first dsrt 12 is preferably twice the voltage of the second dsrt 64 : the pulse generating circuit 62 ( fig9 ) increases the current switched to the load resistor 28 . the energy associated with pumping current into the pumping inductor 24 is switched by the dsrd into the load in the same manner as the energy in the inductors 18 and 52 . current in the capacitor 68 oscillates to increase the current in the pumping inductor 24 . when the dsrt breaks , the current in the pumping inductor 24 is added to the dsrd 22 , along with the current in inductors 18 and 52 . while certain advantageous embodiments have been chosen to illustrate the invention , it will be understood by those skilled in the art that various changes and modifications can be made herein without departing from the scope of the invention as defined in the appended claims .