embodiments of methods and systems for low pin count ( lpc ) firmware hub recovery using a firmware hub recovery module . in the following description , for purposes of explanation , numerous specific details are set forth to provide a thorough understanding of the present invention . it will be appreciated , however , by one skilled in the art that the present invention may be practiced without these specific details . in other instances , structures and devices are shown in block diagram form . furthermore , one skilled in the art can readily appreciated that the specific sequence in which methods are presented and performed are illustrative and it is contemplated that the sequences can be varied and still remain within the spirit and scope of the present invention . fig1 illustrates a block diagram of a computer system &# 39 ; s circuit board 27 including a low pin count ( lpc ) bus 39 according to an embodiment of the present invention . circuit board 27 may be a mother board and typically includes a processor such as a central processing unit or cpu 20 . the cpu is the “ brains ” or “ engine ” of the computer system responsible for overseeing all execution of operations in the computer . motherboard 27 also includes cpu interface logic 21 , coupled to cpu 20 and interfacing cpu 20 with other circuit components such as a system bus interface controller 33 and main memory 26 . as shown , system bus interface controller 33 may be any type of expansion bus controller such as a pci bus or peripheral bus i / o controller . system bus interface controller 33 is coupled to cpu interface logic 21 and is coupled to peripheral connectors 25 via expansion bus 38 . a bus that complies with a peripheral component interconnect ( pct ) standard ( e . g ., pci local bus specification , version 2 . 1 , a copy of which may be obtained from the pci special interest group ) is a example of such an expansion bus . main memory 26 may include random access memory ( ram ) 28 and read only memory ( rom ) 30 which coupled to cpu interface logic 21 . also included on motherboard 27 is a header connector 40 and a jumper 41 . header connector 40 is an internal connector soldered to motherboard used to connect a firmware hub recovery module to the motherboard . jumper 41 may be a strapping jumper for setting an identification ( id ) for a basic input output system ( bios ) firmware hub 24 as described in detail below . firmware hub 24 includes a collection of software routines and functions that communicate directly with the hardware of motherboard 27 . the bios of firmware hub 24 includes code that performs a limited diagnostic of the computer system during the power - on stage know as the “ power on self test ( post ).” when power is applied to the computer system , bios firmware is executed by the cpu 20 before the computer system &# 39 ; s operating system is activated . firmware hub 24 further includes id pins which require configuration to have cpu 20 recognize it as the booting firmware hub . strapping jumper 41 is added to the motherboard to allow the id for the booting firmware hub to changed . this enables an alternative firmware hub , beside firmware hub 24 , to be recognized by the cpu as the booting firmware hub , by simply moving the strapping jumper 41 from one location to another location . in the event the firmware located on firmware hub 24 has become corrupted , strapping jumper 24 can be moved such that another firmware hub can be recognized as the booting firmware . according to an embodiment of the present invention and described in detail below , firmware hub 24 can be reprogrammed by a firmware hub recovery module . referring back to fig1 , the hardware components of motherboard 27 communicate along data pathway or busses 35 , 36 , 37 , 38 and 39 which is included on motherboard 27 which houses the cpu 20 , main memory 26 , and other components including bios firmware chip 24 and bus and i / o controller 33 . several types of busses shown in fig1 may include for example , cpu interface busses , memory interface busses , system expansion busses and industry standard architecture ( isa ) buses . fig2 is a block diagram of a firmware hub recovery module according to an embodiment of the present invention . firmware hub recovery module 50 may be implemented as an external card coupled to header connector 40 which communicates with lpc bus 39 on motherboard 27 . according to an embodiment of the present invention , firmware hub recovery module requires no external connections via cable , etc . all necessary signals are presented on the lpc bus 39 . firmware hub recovery module 50 includes firmware hub module 51 and a connector 52 . connector 52 is plugged into connector 40 on motherboard 27 to connect the module with the motherboard . firmware hub module 51 may be stored on an erasable programmable read only memory ( eprom ). firmware hub module 51 is powered by motherboard 27 through connectors 40 and 52 as shown by power line 53 , and communicates with the other system components of motherboard 27 via lpc bus 39 . firmware hub module 51 provides firmware so that cpu 20 can perform various functions of compensating for an inadequate bios found on firmware hub 24 . such functions may include booting operations , system diagnostics and system reprogramming . by way of further illustration , fig3 illustrates a method for a low pin count ( lpc ) firmware hub recovery that may be implemented using the structures described with reference to the embodiments in fig1 - 2 . in accordance with this embodiment , the firmware hub recovery module 50 is coupled to the motherboard 27 by mating connector 52 of the recovery module with header connector 40 of the motherboard ( step 100 ). this coupling provides an electrical as well as a mechanical connection between firmware hub recovery module 50 and motherboard 27 such that power will be supplied to the recovery module 50 and information will be transmitted to and from the motherboard 27 and firmware hub recovery module 50 . strapping jumper 41 is moved from one pin location to another pin location such that firmware hub 24 is no longer recognized as the booting firmware hub . instead , firmware hub recovery module 50 , once connected to motherboard 27 , is now recognized as the booting firmware hub ( step 200 ). the computer system is then powered on ( step 300 ). the cpu out an id for the booting firmware hub . since strapping jumper 41 changed the booting firmware hub id from firmware hub 24 to firmware hub recovery module 50 , the system is booted by firmware hub module 51 on the recovery module 50 . after the computer has been booted up , the firmware hub module 51 is used along with cpu to reprogram the firmware hub 24 on the motherboard ( step 400 ). after the firmware hub has been reprogrammed , the computer system is powered off and jumper 41 is moved back to its original pin position , assigning firmware hub 24 as the booting firmware hub ( step 500 ). thus , the next time the computer system is powered on , firmware hub 24 is used for the booting process . in the foregoing , detailed descriptions of the apparatus accordance with embodiments of the present invention have been described with reference to specific exemplary embodiments . accordingly , the present specification and figures are to be regarded as illustrative rather than restrictive . moreover , although software or hardware are described to control the certain functions , such functions may be performed using either software , hardware , or a combination of software and hardware , as is well know in the art .