herein , a particle - containing polarizable liquid medium is sandwiched between a common electrode and a semiconductor chip . see fig4 . on the chip side , the liquid medium is in direct contact with a thin layer insulator that covers an array of pixel electrodes . the pixel electrodes are individually addressable . they are connected via interconnects to the driving circuitry below , which supplies to them their designated voltage waveforms . there is a shielding layer between the pixel array and the driving circuitry in order to eliminate electronic interference between the two . in one embodiment , each microelectrode in the pixel array is connected with a switch . each switch has one end connected with the microelectrode pixel , and the other end connected with a column line which provides the signal voltage data column - by - column , and a row line that provides the enabling signal . row lines are sequentially scanned . the signal voltage can be provided in a specified waveform and at a specified frequency . in operation , the data bus provides a signal to all columns , then a particular row is enabled . the cycle is repeated for each row in succession , and then started over from the beginning after enablement of the last row . an exemplary system is shown in fig1 where each pixel is individually addressable by selecting the appropriate two contact pads at the ends of the rows and columns . by scanning the gate bus - lines sequentially , and applying signal voltages to all source bus - lines in a specified sequence , all pixels can be addressed . when the row driver is addressing one row , all other rows are deselected and all switches in those rows are turned off . each pixel is designed to hold the majority of the charge applied ( i . e ., the microelectrodes have minimal current leakage ) when it is de - selected and “ off ” between addressing cycles . the frequency of the signal switching is high enough to allow the dynamic imaging of a “ pseudo - waveform ” ( which is a stepped waveform representation of the actual analog signal provided by the switches ) on the pixel electrode . for example , if a pixel has an operating frequency of about 500 hz , a switching frequency of about 10 khz would be the right order of magnitude . the switching frequency for forming the pseudo - waveform has to exceed a certain frequency threshold such that the irregularity of the waveform has a negligible impact on particles in the adjacent medium undergoing electrokinesis . for example , when the pixel operating frequency is in the low frequency ( 500 hz ) ac mode , the irregularity induced by a switching frequency of greater than 100 khz will have a negligible impact on the adjacent electrolyte , in terms of the magnitude of the high frequency , because the ions in solution have a low mobility and cannot follow such a rapid transition . because the switching mechanism provides control over the voltage change of individual pixels , for each pixel , both the frequency and the signal waveform can be independently controlled . accordingly , different regions of the substrate can operate at different frequencies . however , only a low frequency signal , e . g ., 1 khz or less , can induce ionic flow ( and therefore , fluid or particle flow ) whereas a high frequency signal ( typically above 10 khz ) cannot . a high frequency field will , however , induce an electrokinetic effect , because the high frequency field can penetrate the ionic double layer in the electrolyte with little attenuation . either ionic and fluid flow alone or electrophoresis alone may be desired for certain applications . in addition , a combination of low and high frequency signals allows both ionic flow / fluid flow and dielectrophoresis to take place simultaneously , which may also be desired for certain applications . if different regions are provided with different signal waveforms , the control of fluid flow patterns and particle motion can be achieved . it is then possible to form a number of regions of particles , and move the particles in and out of these regions as desired . similarly , as noted above , providing different frequencies to different regions permits separation of particles based on their relaxation frequencies . the separation between adjacent pixels should be sufficiently small to ensure the continuation of the fluid flow and the assembly of particles in a designated collection area , delineated by a group of pixels supplied with the same voltage signal . moreover , in operation , in order to produce particle movement , one must generate minimal spatial modulation in the interfacial polarization of medium which is in fluidic contact with adjacent pixels operating at the same waveform and voltage , while maximizing the spatial modulation of interfacial polarization of such medium between pixels at different waveforms or voltages . thus , the gap distance between the adjacent pixel electrode edges is adjusted to optimize operation . the gap distance is adjusted as a function of the size of the pixel , the thickness of the upper thin oxide layer , and the thickness of the dielectric layer between the pixel electrode and the shielding . it should be designed such that the transitional voltage along the surface of the upper thin oxide layer between adjacent pixels is always between the high and low voltage levels of the two pixels (“ not to form a dip ”), when two different voltage voltages are applied , whereas the field strength about the gap is below breakdown . in implementation , the microelectrode layout and vertical profile may vary , but the same profile at the interface between the microelectrode layer and thin dielectric layer covering it should be maintained . in one embodiment , the dynamically configurable electrode is produced monolithically , modeled on a conventional cmos fabrication . the addressable pixel array is integrated with the driving circuitry . [ 0075 ] fig3 and 4below depict a simple exemplary integrated structure of an individual pixel microelectrode . this microelectrode can be fabricated as follows . on a p / p + epi substrate , an n - channel mos transistor is fabricated , following active region patterning and field oxide growth . after dielectric - i deposition and planarization , metal - 1 is sputtered and patterned by photolithography , followed by etching . the same procedure is repeated until the top electrode of the capacitor , metal - 3 , is formed . the dielectric layer separating metal layers in this embodiment is silicon oxide ( sio 2 ). following formation of metal - 3 , a dielectric layer of ta 2 o 5 is deposited , planarized , and then etched such that metal - 3 is exposed but the gaps between the metal - 3 electrodes are filled . finally , a high quality , thin , high dielectric constant ( ε ) material such as ta 2 o 5 is coated over the entire upper surface to insulate the electrodes from the electrolyte . anodization can be used as the coating method , because of the low leakage associated with the resulted film . metal - 1 forms signal electrodes , connected to the sources of the switching transistors , and also serves as part of the interconnection between the pixel electrode and the underlying device . heavily doped poly wires the transistor gates to the row selection buses . in some cases , following poly doping , a metal coating and silicide formation step may be preferred to further reduce serial resistance of the poly wires . metal - 2 forms a common electrode of all the pixels . this electrode serves as a shielding layer between the upper electrodes ( metal 3 ) and the driving circuitry . the gap distance between the pixel electrode and the shielding layer should be adjusted such that the capacitance between the two is small compared to the capacitance between the pixel electrode and the liquid medium . furthermore , the top ta 2 o 5 layer should be thin enough to ensure that the capacitance between pixel electrode and the liquid - insulator interface is smaller than or at least comparable with the double - layer capacitance at the interface . the net result is that between the pixel electrode and the common voltage , the double - layer capacitor receives substantial signal voltage . for example , a 1 - μm thick sio 2 ( ε r = 3 . 9 ) dielectric layer ( c = 3 . 45 nf / cm 2 ) and a 100 - a thick ta 2 o 5 ( ε r = 25 ) top layer ( c = 2 . 2 uf / cm 2 ) ensures the areal capacitance of liquid - medium double layer ( c dl ˜ 1 uf / cm 2 for 0 . 01 mm 1 : 1 electrolyte ) dominates so that 60 % of the voltage signal is dropped across the liquid - medium double layer to induce the fluid motion . for a 2 × 2 um 2 pixel , the overall capacitance is about 30 ff , which is a typical value of the state - of - art dram storage node . there is no need to fabricate additional storage structures , as c dl is already one of a kind . holes extending through metal - 2 allow interconnections between the upper metal 3 electrodes and the transistor drains . the architecture of the platform chip , illustrated in fig5 comprises four major functional blocks : a command block that generates synchronous and control signals , a data buffer , an internal data and control bus , and a pixel array which may include a plurality of subarrays . to accommodate the appropriate frame rate in the subarray , the operating frequency of an internal master clock residing in the command block should match the highest switching rate of the chip , that is , the scan rate of the column driver lines . random dynamic random access memory ( dram ) chips usually provide adequate storage capacity and bandwidth — for example , pc266 sdram has a 64 - bit bus , 266 mhz clock and a bandwidth of 2 . 128 gb / sec . the clock frequency of the internal bus will normally differ from that of the internal master clock and , for a large array , may exceed it . this necessitates a data transfer interface to match the internal and external buses . in fig5 a data buffer translates a 64 - bit external data stream into an internal 26 - bit stream . this configuration permits the rise of a faster internal bus at a frequency of 655 mhz to meet the requirement of the internal switching circuitry , while permitting full utilization of the external bus bandwidth . subarrays are operating synchronously and in parallel to form a large combined array capable of displaying a large seamless “ image .” the total number of subarrays depends on how high a clock frequency of the master clock can be realistically achieved . the upper bound is set by the time scale of the transient response , including transmission line delay and / or charging of the pixel capacitor . for example , a typical interconnect has a capacitance of 2 pf / cm when metal linewidth matches insulator thickness . the rc delay of a 0 . 25 × 0 . 25 um 2 100 - um long aluminum wire ( ρ w ≈ 3 × 10 − 6 ω · cm ) can be estimated as τ w ≈ π   ɛ ins  ρ w  l w 2 w w  t w ≈ 0 . 5   p   s . the dominating capacitance of pixel elements is that of the ionic double - layer at liquid - insulator interface which , for a 0 . 01 mm 1 : 1electrolyte , is about 10 − 6 f / cm 2 , or approximately 40 for a 2 × 2 um 2 pixel . assuming the channel resistance ( 10 4 ω ) of the switching transistor to dominate the total resistance , the transient time due to charging of the double - layer capacitance can be calculated as : considering both contributions , the total transient response time will be of the order of ˜ 1 ps , which is negligible compared to the 1 ns time interval of the master clock . in this situation , it is not absolutely necessary to divide a 1024 × 1024 array into four 256 × 256 subarrays as shown in fig5 ; nevertheless , this configuration illustrates a parallel design that may be employed when the entire array is so large that the transient response becomes comparable to the characteristic time of the master clock . each subarray consists of an analog channel division block , a switch array , and a pixel array , as shown in fig6 . in the invention , subarrays are operated by transforming the original waveform of each channel into a number of similar but lower amplitude waveforms for corresponding subchannels . after passing through analog buffers such as voltage followers , signals from those subchannels are distributed by a cross point switch array onto the column driver lines which are connected to the pixel array . to improve the transient response , the preferred mechanism permits the use of a mosfet switch transistor and a pass gate , an inverter and a storage node in each switching cell . as illustrated in fig6 the gate of a switch transistor is connected to the column scan logic line , its drain to the decoder line and its source to the top electrode of the storage node , the pass gate , with one end connected to a subchannel line and the other to the column driver line , may be turned on by a logic “ 1 ” pass through the switch transistor , which is turned on by a logic “ 1 ” applied on the decoder line in the mean time . the storage node preferably employs a typical structure of that of a state - of - art dram cell , which has a typical capacitor of ˜ 30 ff . the charge corresponding to the logic state stored in those cells is allowed to leak ; however , compared to the time required to scan all of the column driver lines , the decay of stored charge is negligible . this “ dynamic ” logic also saves precious layout space . as the column scan logic sequentially selects each of the column select lines , data , indicating which one ( and only one ) of the switches along the selected column should be turned on , is allowed to decode in the decoder by the same clock signal and generates a logic “ 1 ” on the designated decoder line . as a result , the corresponding switch is turned on and voltage is connected to the column line . as the current column is deselected and next column is selected , the stored nodes of deselected cells should hold the correct logic states at the gate of the second transistor until they are next selected , so long as the fraction of stored charge that is allowed to “ leak ” is negligibly small . the column select logic preferably is a shift register which is configured in such a way that only one column is selected at a time and all columns are selected in turn . once all column driver lines are ready , the row select line of the designated pixel row in the pixel array receives a “ 1 ”. as a result , the corresponding switching transistors of the entire row are turned on , thereby allowing all pixel capacitors along the row to receive updated voltage signals from the column lines . similar to the switch array , the row select logic generates one logic “ 1 ” at a time , allowing only one row of pixels to be set updated , all rows being selected and updated in turn in order to form one frame corresponding to a specific voltage state of the pixel array . as an example , in fig5 for a master clock frequency matching the unknown scan rate of 655 mhz , and the row scan at a fraction of the master clock , for example , 2 . 56 mhz for 256 rows , the corresponding frame rate is 10 khz . when adjacent pixel electrodes are connected to different voltage levels , an electric field is generated which surrounds the electrodes . as simulated and shown in fig9 the field is distributed in the liquid as well in the insulating layer . a large gap may allow equi - potential lines to “ leak ” into the liquid through the gap and cause a voltage dip as illustrated in the plot in fig7 b . an preferable arrangement of the electrodes is shown in fig7 c , in which the thin extension of one electrode is buried underneath the thin extension of the adjacent electrode . the vertical alignment of the edges of the two extensions allows some overlaps , which prevents the equi - potential lines within the insulator from “ leaking ” into the liquid . as such , a dip will be absent , as illustrated in the plot of fig7 c . as an example of fabricating such structure , multiple steps are involved which include the deposition of a dielectric stop - etch layer and of metal film deposition , repeated three times , and patterning twice with dielectric layer deposition and planarization . at first , one deposits a thin layer of aluminum oxide ( al 2 0 3 ) on the insulating layer which is on top of the shielding layer . a layer of aluminum ( al ) is then evaporated , patterned and etched , following which a second layer of transition metal tantalum ( ta ) is deposited , patterned , and etched . this step involves an etching gas mixture that , in plasma state , etches ta at a much faster rate than al . as soon as the exposed ta is all etched away , the process will automatically stop as the plasma reaches the al 2 o 3 layer . the measurement on the etch rate of different materials is described in k . r . william , et al ., j . microelectromech . sys . vol . 12 , no . 6 , pp . 761 - 777 shows that ta ion - mill - deposited at 1250 v , with a current density of about 2 ma / cm 2 , p = 3 × 10 − 4 torr , has an etch rate of 37 nm / min in an rie chamber ( surface technology system 320 ) using sf 6 = 25 sccm , o 2 = 10 sccm , p = 100 w at 13 . 56 mhz , p = 20 mtorr . aluminum evaporated from a tungsten wire in the same plasma was measured with an etch rate of & lt ; 2 . 8 nm / min , and al 2 o 3 evaporated from an alumina source had an etch rate less than 0 . 41 nm / min . following the etching of ta , a dielectric layer is deposited conformally to fill up the gaps . then the entire surface is planarized until the dielectric layer covering the metal layer is all removed and filled dielectric material with gaps is flat with the metal . a third layer of metal , that is ta , is then deposited , patterned and etched . again , a layer of dielectric layer is deposited conformally to fill the gap , which is then etched away only to leave a filled gap flat with the metal . finally , a high quality thin layer of ta 2 o 5 film is deposited on top of the pixel layer , preferably & lt ; 200 - a thick , to cover the entire surface . the low - temperature deposition of an ultrathin ta 2 o 5 film may be performed using state - of - art chemical vapor deposition ( cvd ) such as uv - assisted cvd . see j . y . zhang and i . w . boyd , app . phys . left ., vol . 77 , issue 22 , pp . 3574 - 3576 . there are two primary reasons for using a high dielectric material , e . g ., ta 2 o 5 ( having an ε of about 25 ) on the upper surface of the pixel . first , it is possible to increase the dielectric layer thickness by using a higher ε material for a given capacitance . the insulating layer capacitance should be comparable in magnitude to that of the electrolyte double layer , typically several micro - farads per cm 2 . for sio 2 the corresponding insulating layer thickness would be in the range of tens of angstroms . making such a film stable is very difficult . by using high ε material , such as ta 2 o 5 , a film up to hundreds of angstroms in thickness may be used , which greatly reduces the number of pinholes in the film , and also improves the surface uniformity . the second reason for using a high e material is that the coupling of the electric field into the liquid medium ( for example , water with 6 of about 70 ) becomes more efficient . this relates to an important part of the design of the dynamically configurable electrode of the invention . the distance between adjacent pixel electrodes should be small enough to produce a continuous transverse field across such distance , in order to prevent a significant dip and the possibility of localized flow , or no net flow , in between pixels . see fig7 a - c showing the voltage drop between adjacent pixels at different gaps and conformations . simulations were performed to demonstrate that a transverse field could be generated with a pixel arrangement as described above . in these simulations ( summarized below and illustrated in fig9 to 11 ), a dc rather than an ac current was used to illustrate such an effect . a set of simulations was performed using matlab ( mathworks , ma ) to demonstrate the effect of the material and the thickness of upper dielectric layer , and spacing of adjacent pixel electrodes , on the lateral field gradient . the dimensions of the upper electrodes in fig9 are : 8 - μm long and 1 - μm thick . the applied voltage on the left top electrode is 2 v and on the right top electrode it is 1 v . the bottom electrode is grounded to 0 v . the dielectric medium above the electrodes is water , and sio 2 is below . the material insulating the top electrodes is a 1000 - a ° thick ta 2 o 5 layer . the distance between top electrodes is 2 μm . as can be seen in fig9 the equipotential lines in the sio 2 , corresponding to the potential transition between 0 and 1 v , are completely sealed within the structure . only the vertical potential contours between 1 and 2 v is seen above the ta 2 o 5 layer , and the field is directed along the surface , pointing from the left top to the right top pixel electrode , as expected . in fig1 , all conditions are the same as in fig9 except that the distance between top electrodes is 8 μm , and the top layer is sio 2 with a thickness of 0 . 5 μm . as can be seen , the equipotential lines in the sio 2 layer , corresponding to the potential transition between 0 and 1 v , is not completely sealed within the structure and “ leaks out ” into the water . this makes the effective gap distance smaller and voltage dependent . in addition , the transverse field is non - uniform and the ionic flow is likely discontinuous near such a “ voltage dip ”. [ 0091 ] fig1 depicts the field resulting from three pixel electrodes , with a gap distance of 2 - elm between top electrodes . the voltage on the left electrode is 3 v , in the middle it is 2 v , and on the right it is 1 v . the bottom electrode is grounded at 0 v . a monotonic potential transition of potential is observed along the electrodes . thus , a continuous ionic flow will be expected along the channel formed by the three electrodes . these simulations demonstrate that with a proper selection of the distance between pixels and of the dielectric media , a monotonic potential along multiple pixel electrodes near the insulator / electrolyte interface is possible . such field can induce continuous ionic flow and particle movement across the gap distance between adjacent electrodes and along the surface above multiple electrodes . the invention can also include a software interface , to provide direct and real - time control . fig1 shows the schematic of the control system , which consists of a control chip and the generation of real time data flow provided to a computer / controller interface . the role of the control chip is to generate analog signals and to coordinate with pattern updating on the platform chip . the inputs include waveform specification and real - time pattern generated by software programming interface . there is provided , therefore , a platform on which particle movement can be controlled , and on which biological assays on samples associated with beads or particles , or cells , can be conducted . an overlap of functionality of the chips may be needed in practice . refreshing or rewriting individual pixels is a high frequency operation , which has some regularity because , in general , one would not be generating arbitrary waveforms on each electrode on each cycle . the role of the control chip would be to maintain patterning , or , in implementation , to update registers in the memory that are associated with the pixel array ( values such as waveform type , waveform magnitude , phase , frequency , etc ) on the platform chip , in a slower time - varying fashion . the platform chip takes those values from the on - chip memory and generates column voltage values at high frequency and sets the voltages on pixel electrodes . the difference corresponding to high and low frequency regimes may be necessary , because in practice , clock frequency and data transfer rate among chips have limitations . a control chip coordinates the programming interface and platform chip . as shown in fig8 it comprises a waveform generation block , a command block and two memory circuit blocks . timing signals of the control chip are routed from the switching clock ( sclk ), row scan clock ( rclk ) on a platform chip , and a system clock from the programming interface . there are two memory blocks on the control chip shown in fig8 : memory - h and memory - l . memory - h is synchronized with sclk , for example 655 mhz . it constantly feeds data into the input bus of the platform chip at a matching transfer rate . real - time subchannel id &# 39 ; s of all the pixel elements in the entire pixel array are stored in memory - h . coordinated with the command block , memory - l periodically updates the designated memory elements of memory - h at a far slower rate so that data transfer from memory - h to the platform chip is not affected . one may elect to use rclk , say 2 . 56 mhz , for its synchronization . if 10 % of the array area evolves over time , it takes 40 ms to update all the designated elements . this is a time interval smaller than the typical time period for a particle to travel across one pixel . for example , if a particle moves at a velocity of 8 μm / s and the pixel size is 2 × 2 μm 2 , it takes it 250 ms to pass the distance of one pixel length , which is long compared to 40 ms . while updating the memory content in memory - h , memory - l also receives data from the programming interface . those two actions may occur at similar frequencies . for example , if rclk is used for updating memory - l , after each storage node releases its content ( containing address and subchannel ids ), it immediately receives an updated one from the programming interface . of course , actual frequency and implementation may differ to better serve such a purpose . if the control chip uses bicmos technology , it may contain a waveform generation block that generates a set of analog signals with differing waveform shapes and / or frequencies in accordance with the waveform specifications sent from the programming interface . in general , there is no time - dependence requirement on the specification data ; however , one may explore such a global evolution , as it is available . to implement this design , it is also possible to use a separate chip for waveform generation fabricated using bipolar technology or even a off - the - shelf device , and pack all digital circuitry on a second chip using cmos technology . the electric field generated may be configured in different ways by the control system . transient fields can be configured to simulate the bright and dark regions associated with illumination - related control over the electric field . fine control over particle movement and electrolyte flow is made possible by active matrix addressing and the ability to generate time - continuous , non - intermittent pseudo - waveforms , as described above , which is particularly beneficial to medium to low frequency operations . simulations , using light to induce electric field gradients , demonstrated that when illumination is applied on an enclosed region of a ito - electrolyte - semiconductor sandwich structure , with an ac voltage of frequency f applied across it , ions are redistributed at the beginning of each half - cycle . fig1 represents a simplified equivalent circuit that generates the voltage waveform in fig1 . the semiconductor surface was modeled as a diode in parallel connection with a dc current source that simulates the photocurrent induced by illumination . the voltage probes were placed on top of the equivalent capacitors corresponding to a double layer structure , to sense the voltage waveforms generated at an electrolyte - semiconductor interface in illuminated and dark regions . in the simulated voltage waveforms shown in fig1 , the dashed line , representing the potential above the double layer in the dark region , has a much smaller magnitude than that of the solid curve , representing such a potential in the illuminated region . the dash - dotted curve shows the difference in voltage between dark and bright regions . as illustrated in fig1 , because the sign of the potential in the illuminated area changes between half - cycles , the sign of the excess charge within the double layer also changes . if , in the up - cycle in the ac - voltage , a negative excess charge of counterions accumulates , a transient transverse ionic current is carried by negative ions and flows to regions of higher surface potential ( i . e ., simulated bright regions ). in the down - cycle , a positive charge , and a transient transverse current carried by negative ions will flow to regions of higher surface potential . in both half - cycles , the transient current flows in the same direction , namely toward “ bright ” regions of higher surface potential . that is , the transient current , and the corresponding fluid flow , are rectified . the voltage waveform at the electrolyte / insulator interface always has a higher peak - to - peak value in the illuminated region than in the dark background of the substrate . accordingly , similar ionic flow can be induced if the voltage waveforms , such as those shown in fig1 , can be generated above the corresponding area of a substrate surface . the electrode in this invention generates voltage waveforms by supplying a proper voltage signal directly to electrodes , which are buried just below the electrolyte - insulator interface . if the geometrical and physical parameters are properly selected , the voltage signal can be efficiently coupled into the interface and can generate the desired voltage waveform in the double layer structure . an equivalent circuit and simulated waveform for the pixel structure described herein is shown , respectively , in fig1 and 16 . [ 0104 ] fig1 and 18demonstrate the effect of having a d - type signal ( of a smaller ac magnitude ) outside of a circular region on the pixel array and a b - type signal ( of a larger ac magnitude ) inside such circular region . this generates a fluid flow field pointing towards the center of circle and thus is able to collect and assemble particles ( which could be beads , cells or other types of particles ) in b region . if this circular structure is moved along the array surface , the particles will be maintained in the same spatial configuration relative to each other ( i . e ., they will maintain an array configuration ) but will be transported along the surface . array fragmentation and merger can also be accomplished . as shown in fig2 and 21 , at time 0 , the particle array is formed and entrapped in regions which have an applied b - type signal . in fig2 , when a d - type signal region is created in the middle of b - type region , the array is split . the migration of arrays in different directions separates one array into two . on the two - dimensional electrode , fragmentation of a single array into multiple arrays can be accomplished using analogous signals . alternatively , multiple arrays can be merged into one single array , as illustrated in fig2 . particle transport can be accomplished with either a digital - style signal , in a “ boxcar ” sequence , or with an analog - style signal , using an alternating long - range transport channel . for short - range transport , the digital style is preferred because only two types of signals are needed . the particles are then grouped into b - type regions , and several groups can be moving along the transport channel to other parts of the surface . see fig2 . in this method there is no ac magnitude gradient needed along the channel . if a large number of particles need to be transported , the short - range digital mode is not efficient , because groups of particles are separated during transport . an analog mode utilizing an ac field gradient can function efficiently . as shown in fig2 and 24 , the b - type region is a channel much longer than that present in digital mode . the ac field created in the b - type subchannel has a monotonically increasing magnitude . the magnitude at the high end is limited by some cutoff value that is predetermined not to affect the electrolyte and / or assays . at time 0 , such subchannels are created and separated by d - type regions . the particles are then captured into the b - type subchannels and migrate to accumulate at one end . after a time interval , the channel structure shifts by half a subchannel length , then the accumulated particles will gather at a new end . this process repeats until all particles in the channel are transported to a designated end . by using only small separating gaps among subchannels , large and potentially detrimental ac potentials can be avoided . in strong field gradient regions , the field - polarized particles can interact with the field gradient due to the interaction between inhomogeneous field distribution and their dipole moments . such behavior is expected to be strong at the d / b interface and is characterized by a certain relaxation frequency , above which such force is negligible . if the d / b interface is created such that it moves towards a gathering region , only certain types of particles , which have a relaxation frequency greater than that of applied ac field , will be carried and collected within the moving boundary of d / b interface . thus , the fractionation and sorting of particles can be accomplished . the shape of such interface may be arbitrary . see fig2 . at high frequencies , i . e ., & gt ; 100 khz , particle fractionation and separation can be accomplished without participation of fluid flow . at low frequencies of about 1 khz , the fractionation and separation can be coupled with and enhanced by the fluid flow across the moving boundary . because individual pixels and the frequency of each pixel can be controlled , the relaxation frequency sensitive sorting and assays can be conducted independently on different regions of the same electrode as illustrated in fig2 a and 26b . the combination of such independent sorting operations permits assays to be conducted on the same surface in sequence or at the same time in different surface regions . the electrode of the invention can also be used in a gated particle transport structure . two effects , coating patterning ( for particle confinement and collection ) and gating , are combined in one step under electronic control . as shown in 27 , the octagonal regions are collection areas for particles . the arrows denote the flow field near the surface , which shows that the particles carried in the fluid field tend to flow along the channels and to gather in the octagonal areas . the dark regions are applied with a “ d ”- type signal . the “ gate ” blocking the channel can be switched “ on ” by applying a configurable “ b ”- type signal but with a certain magnitude gradient along the channel . if the signal gradient is designed such that component of electrokinetic force along the channel on the one side of the gate vanishes , macroscopic flow will be established to transport particles from one gathering area to another — left to right in this particular case . to demonstrate the dynamic reconfigurability of the electrode structure , and to determine the optimal value of the separation between constituent pixels , a prototype was constructed to emulate certain features of the integrated device disclosed herein . design considerations — as illustrated in fig2 , the prototype comprises eight pairs of planar electrodes , each having a first electrode in the form of an octagonal core and a second electrode in the form of a ring that encloses the core ; the width of the ring being 80 μm in the central region and 160 μm in the outer region . in each pair , the inner electrode represents a dynamic electrode formed by a group of contiguous pixels operated at the same voltage waveform , v 1 , whereas the ring electrode represents a second dynamic electrode formed by a group of contiguous pixels surrounding the core electrode region , all operated at same voltage waveform , v 2 . in each of the electrode pairs of the prototype , core and ring are separated by a planar gap and are electrically insulated from each other . in the electrode design shown in fig2 , respective values for the four inner electrode pairs were chosen to be 1 , 2 , 4 , and 8 μm . the multi - layer structure of the prototype , shown in cross - section in fig2 , consists of : a highly n - doped ( 0 . 001 ohm . cm ) silicon substrate ; a silicon oxide dielectric layer of approximately 2000 - a ° thickness covering the entire substrate ; a layer of tantalum of approximately 4000 - a ° thickness covering a portion of the substrate ; and , a layer of tantalum pentoxide ( ta 2 o 5 ) of approximately 700 - nm thickness capping the tantalum layer . the layers of the multi - layer structure of the prototype shown in fig2 respectively represent corresponding layers of the integrated device illustrated in fig4 . that is , the corresponding layers in fig4 are , respectively : metal 2 (“ sheilding ”); dielectric 3 ; metal 3 ; high - ε dielectric uppermost layer . tantalum pentoxide was selected as the preferred dielectric upper layer because it provides : ( i ) a high dielectric constant enabling , for a preset capacitance , the use of relatively thick and well insulating films , especially when the films are produced by anodization , as described below ; ( ii ) effective anti - reflection properties , especially at the interface between silicon and aqueous solutions ( such solutions are present in the bioanalytical assay applications of the invention ); and , ( iii ) in contrast to semiconductor oxides , it is chemically stable in the presence of applied electric fields . anodization — to fabricate the electrode structure shown in fig2 , each electrode , produced by sputtering , was uniformly anodized in turn by placing a small teflon ring , typically of a diameter of 5 mm , onto the central portion of the multi - electrode structure as shown in fig2 . the ring was overfilled with 8 microliters of 0 . 01 % citric acid , so as to form a sessile drop , and the upper surface of the drop was contacted with a planar tantalum counter - electrode , whose area was large compared to that of the confining ring , in order to provide uniformity . the counter - electrode was separated from the test chip surface by a 400 - micrometer gap formed by kapton spacers lying outside of the teflon ring . to anodize a selected electrode , that electrode was connected by its respective pad to an external voltage or current source via a tungsten probe and the counter - electrode was grounded . in a given pass , only the selected electrode was anodized . the procedure consisted of two steps . first , to grow an oxide film by anodization , a constant current was applied to attain a desired voltage and a corresponding desired oxide thickness . next , to close remaining pin holes in the film , a constant voltage was applied . in this second step , oxide grows primarily to fill in pin holes until the current drops to a baseline value reflecting the insulating properties of the final film . to automate the process , a labview ( national instruments , tx ) program was written to apply constant voltage and / or current in accordance with a selected protocol and to record voltage and current in real time using a keithley 2400 source meter ( keithley instruments , ny ). [ 0118 ] fig3 and 31 show a typical voltage and current time relation in the anodization process for growth of a 600 - a ° ta 2 o 5 film on the core electrode , having a 1 - μm - gap core - ring pair , as shown in fig2 . fig3 shows the constant current characteristic of the first step and the exponential decay of the leakage current of the second step as pin holes are filled in . a plan view of the anodized core electrode is depicted in fig3 . electrical characteristics : impedance — to demonstrate the performance of the prototype device — notably the desired capacitive coupling between adjacent electrodes (“ pixels ”) via the intervening polarizable liquid medium — an impedance analysis was performed using : an analog lock - in amplifier ( stanford research 530a ), a dsp dual channel lock - in amplifier ( stanford research sr 830 ), a function generator ( hp 3312a ), and a source meter ( keithley 2400 ). a labview program ( labview vi , national instruments , tx ) was designed to control the configuration and automate the sequence of setting frequency and recording instrument readings . to scan frequency — typically over a range from 10 hz to 10 khz — a series of values of frequency were selected and produced in turn by applying the corresponding voltage to the voltage - controlled - oscillator of the hp 3312a . for each value of the frequency , the resulting magnitude and phase of ac current and voltage were simultaneously recorded by the sr 830 and sr 530 , respectively . magnitude (| z |) and phase ( φ ) of the impedance , z , computed from the current and voltage signals recorded for the 1 - μm core - ring electrode of the prototype structure of fig2 , are respectively displayed in fig3 and 34 as a function of frequency . these profiles indicate the desired capacitive coupling . introduced here is a practical approach to numerical device simulation — currently not available — for electrolyte - insulator - conductor heterostructures . in accordance with this method , a 1 : 1electrolyte ( a solution containing two types of mobile ionic species of equal and opposite charge ) is modeled as a semiconductor of low mobility where the generation and recombination activities of carriers are zero . this simulates the electrical properties of a reconfigurable electrode of the invention ; specifically , the distribution of ion concentration , ionic current , and electric potential and fields near the interface , in the presence of lateral spatial modulations . the same simulation method can also be applied to simulate an electrolyte - insulator - semiconductor structure , with use of an appropriate solver . using the luminous and s - pisces modules in an atlas simulator ( from silvaco , ma ), a simulation was performed to compute the current distribution produced in response to a voltage ramp at the interface between a dielectric film and an electrolyte ( modeled as a low mobility semiconductor ) in the region of the lateral gap between two electrodes , where each electrode represents pixels or contiguous groups of pixels operating at the same voltage . the electrodes are modeled to be embedded in the dielectric film and to be operating at different voltages . the following conditions and parameters were used : temperature of 3000 k . same electron affinity and bandgap as si @ 300 ° k . intrinsic material . by assuming the validity of the boltzmann distribution , the pseudo band structure can be introduced with identical values of the density states of valence and conduction bands , which are set to match the correct ion density in the electrically neutral electrolyte bulk . for example , for 0 . 26 mm tris , nc and nv are 1 . 842 × 10 26 cm − 3 @ 300 ° k . bulk mobilities replaced by ion mobilities ( a factor of 10 − 4 , which is an order of magnitude smaller than those of electron and hole carriers in a semiconductor ); specifically , to model tris - acetate , published values of ion mobilities were used : tris + 1 = 3 . 0476 × 10 − 4 cm 2 s − 1 v − 1 , acetate − 1 = 4 . 236 × 10 − 4 cm 2 s − 1 v − 1 .) dielectric constant of 80 — same as water . zero photogeneration . infinite recombination lifetime ( in this case , was assumed to be 1 s , which is long compared to the 0 . 25 - ms duration of ramps ). zero recombination velocities at interface . a pseudo 10 - a ° sio 2 is inserted at all interfaces with electrolyte with tunneling option off ( to cut off carrier or ion exchange between electrolyte and semiconductor ). only the electrical field is allowed to permeate . if fluid flow needs to be taken into account , zero ion mobilities at the interface or no - slip flow boundary conditions should be assumed . also , an extra convection term needs to be included in the ionic current expression to indicate the reality of ionic flow in the bulk medium and interfacial layer . however , in this simulation these additional conditions were neglected for simplicity . the sandwich structure for this simulation was composed of a conductive ito electrode , a bulk electrolyte , and a pair of metal electrodes separated by a lateral gap of 1 μm and embedded in a ta 2 o 5 film of 600 - angstrom thickness . see fig3 . the ito and one of the embedded metal electrodes , vi were connected to a common ground ( v = 0 ). the other embedded metal electrode v2 was connected to a voltage source . to model the effects of an applied ac voltage , the response to two linear ramps was computed , namely : a positive linear ramp from v = 0 to v =+ 1v in 0 . 25 ms ; and a negative linear ramp from v = 0 to v =− 1v in 0 . 25 ms . linear profiles of the current distribution along the x and y - directions at an elevation of 100 angstroms above the ta 2 o 5 layer ( at which elevation one is in the semiconductor (“ electrolyte ”) interface ) as shown in the four panels of fig3 a - d , reveal that at the end of the positive ramp , an excess of negatively charged ions accumulated in the electrolyte near the electrolyte - insulator interface above the active electrode , while a slight excess of positively charged ions accumulated near the electrolyte - insulator interface above the grounded electrode , due to the fact that the potential in the bulk of the electrolyte is slightly elevated . the total ionic current is directed primarily along the interface — in a direction away from the active electrode — and is composed primarily of negatively charged ions . that is , in response to the positive ramp , there is net ion transport from the grounded electrode to the active electrode . conversely , as shown in fig3 a - d , in response to the negative ramp , the current and the predominant positive ionic species also flows from the grounded to the active electrode . this simulation supports the conclusion that the transverse ionic current — and the anticipated coupled electrokinetic fluid flow — set up in the electrolyte adjacent to the dynamically configurable electrode in response to applying differential ac voltages to adjacent pixels , will be directed toward regions of stronger voltage potentials , in both positive and negative cycles of the waveform . that is , lateral ionic flows are rectified . to demonstrate the reconfigurability of the electrode of example 1 in controlling the transport and assembly of microparticles at the interface between the electrode and a polarizable liquid medium , the device was used to generate planar arrays of particles in two distinct configurations . a suspension of particles was formed by placing oligo ( dt ) 25 microparticles (“ dynabeads , dynal biotech , oslo ) in a solution of 0 . 26 mm tris with 0 . 01 % triton in 18 - mω water . the particle density of the suspension was adjusted so as to produce a layer of settled particles on the electrode corresponding to less than complete monolayer coverage . an aliquot of the suspension was placed onto the reconfigurable electrode of example 1 and was contacted by an ito - coated glass cover - slip so as to form a “ sandwich ” configuration , typically accommodating 0 . 5 μl of suspension in a 100 μm gap . the gap was defined by a pair of kapton spacers . using a translation stage , one of the 1 um core - ring electrodes of the structure was placed in the viewing field of a stereo microscope ( bausch & amp ; laumb ), to permit real - time observation , using a long - working distance 10 × objective . when the same ac voltage of typically 2 vpp , 0 . 5 khz , was applied between the core and the ( grounded ) ito counterelectrode , v ( core ), and between the ring and the counterelectrode , v ( ring ), particles were collected from the areas of the substrate surrounding the electrodes . fig3 illustrates that particles were collected with equal efficiency by both core and ring electrodes (“ b type ” regions in fig3 ) from the surrounding areas (“ d type ” regions in fig3 ). a depletion zone — clearly visible in fig3 — was formed along the interior of the entire core - ring electrode circumference but not between core and ring , indicating that — under the condition v ( core )= v ( ring )— core and ring were acting in tandem without generating differential displacement of particles between core and ring . in contrast , as shown in fig3 , under the condition v ( core )& gt ; v ( ring ), particles were observed to migrate from the ring to the core . setting v ( core )& lt ; v ( ring ) inverts the direction of transport ( not shown ). a depletion zone was formed along the circumference of the core electrode where none was visible before , indicating differential displacement of particles from the region of lower - voltage to that of higher - voltage waveform signal . that is , the device permitted the desired electronically programmable array reconfiguration , in this instance involving the segmentation of the initial array into two arrays . the example depicted in fig3 and 39 illustrate a configuration when the boundary of the core and ring is fixed , and particles are accumulated . in a case when the boundary is reconfigurable and mobile , in addition to accumulation , the segmentation and transport of particles can be achieved . as with conventional electroosmotic flow , the rectified lateral current directed from electrode regions of lower - voltage waveform to electrode regions of higher - voltage waveform induces electrokinetic transport in the direction of the local current . using the prototype design of example 1 , fluid flow was generated in the vicinity of the electrode in a direction parallel to the electrode surface and normal to the contour delineating groups of contiguous pixels , which act in concert by virtue of being connected to identical voltages . as explained in example 2 for particle transport , flow fields were reconfigured , for example , by first defining , for the condition v ( core )= v ( ring ), the relevant flow - defining contour to be that delineating the exterior contour of the “ paired ” core and ring structure . under the condition v ( core )& gt ; v ( ring ), flow was generated , in addition to the flow normal to the exterior contour , in the direction normal to the interior contours separating core and ring structures and into the core . setting v ( core )& lt ; v ( ring ) inverts the direction of flow . counter - propagating flows originating , for example , from opposite portions of parallel contour , produce upflow in the center of the electrode structure . see fig3 and 39 . particles differing in size , chemical surface properties and / or electrical properties such as polarizibility or , in the case of vesicles or cells ,. differing in transmembrane membrane conductance , can be separated based on their respective dielectric relaxation frequencies . under conditions as described in example 3 , such particles and cells can be fractionated using the devices and method of the present invention , in analogy to the methods described in allowed u . s . patent application ser . no . 09 / 813 , 571 ( analogous to international patent application publication wo 02 / 076585 entitled “ analysis and fractionation of particles near surfaces ”). particles in a suspension containing polymer (“ latex ”) microparticles of two different sizes , each typically in the range from 1 - 10 microns , in an aqueous solution of 0 . 25 mm tris with 0 . 01 % triton , when placed on an electrode of the design of example 1 , may be fractionated into homogeneous subpopulations by selectively collecting , under conditions similar to those in example 2 , only one of the subpopulations into the designated region of the electrode to which the highest voltage is applied . specifically , given relaxation frequencies ω r ( 1 ) and ω r ( 2 ) & gt ; ω r ( 1 ) for particle populations ( 1 ) and ( 2 ), particle fractionation is accomplished by selectively collecting particle population ( 1 ) into the designated area of the electrode by setting the frequency , ω , of the applied voltage such that ω r ( 2 ) & gt ; ω & gt ; ω r ( 1 ) . by concatenating sets of fundamental operations such as directed translation , collection / array formation and holding , as well a fractionation and sorting step ( as in example 5 ), complex operations may be performed , sequentially and concurrently in multiple designated portions of a dynamically reconfigurable electrode . this allows one to realize an integrated format of array cytometry analogous to the methods and designs disclosed in u . s . pat . no . 6 , 387 , 707 , entitled array cytometry ( and incorporated herein by reference ). see fig4 below . it should be understood that the examples and discussion above are exemplary only , and not limiting , and that the scope of the invention is defined only in the claims which follow , and includes all equivalents of the subject matter of the claims .