in the following description , certain specific details are set forth in order to provide a thorough understanding of various aspects of the disclosed subject matter . however , the disclosed subject matter may be practiced without these specific details . in some instances , well - known structures and methods of semiconductor processing comprising embodiments of the subject matter disclosed herein have not been described in detail to avoid obscuring the descriptions of other aspects of the present disclosure . unless the context requires otherwise , throughout the specification and claims that follow , the word “ comprise ” and variations thereof , such as “ comprises ” and “ comprising ” are to be construed in an open , inclusive sense , that is , as “ including , but not limited to .” reference throughout the specification to “ one embodiment ” or “ an embodiment ” means that a particular feature , structure , or characteristic described in connection with the embodiment is included in at least one embodiment . thus , the appearance of the phrases “ in one embodiment ” or “ in an embodiment ” in various places throughout the specification are not necessarily all referring to the same aspect . furthermore , the particular features , structures , or characteristics may be combined in any suitable manner in one or more aspects of the present disclosure . reference throughout the specification to integrated circuits is generally intended to include integrated circuit components built on semiconducting substrates , whether or not the components are coupled together into a circuit or able to be interconnected . throughout the specification , the term “ layer ” is used in its broadest sense to include a thin film , a cap , or the like and one layer may be composed of multiple sub - layers . reference throughout the specification to conventional thin film deposition techniques for depositing silicon nitride , silicon dioxide , metals , or similar materials include such processes as chemical vapor deposition ( cvd ), low - pressure chemical vapor deposition ( lpcvd ), metal organic chemical vapor deposition ( mocvd ), plasma - enhanced chemical vapor deposition ( pecvd ), plasma vapor deposition ( pvd ), atomic layer deposition ( ald ), molecular beam epitaxy ( mbe ), electroplating , electro - less plating , and the like . specific embodiments are described herein with reference to examples of such processes . however , the present disclosure and the reference to certain deposition techniques should not be limited to those described . for example , in some circumstances , a description that references cvd may alternatively be done using pvd , or a description that specifies electroplating may alternatively be accomplished using electro - less plating . furthermore , reference to conventional techniques of thin film formation may include growing a film in - situ . for example , in some embodiments , controlled growth of an oxide to a desired thickness can be achieved by exposing a silicon surface to oxygen gas or to moisture in a heated chamber . reference throughout the specification to conventional photolithography techniques , known in the art of semiconductor fabrication for patterning various thin films , includes a spin - expose - develop process sequence typically followed by an etch process . alternatively or additionally , photoresist can also be used to pattern a hard mask ( e . g ., a silicon nitride hard mask ), which , in turn , can be used to pattern an underlying film . reference throughout the specification to conventional etching techniques known in the art of semiconductor fabrication for selective removal of polysilicon , silicon nitride , silicon dioxide , metals , photoresist , polyimide , or similar materials includes such processes as wet chemical etching , reactive ion ( plasma ) etching ( rie ), washing , wet cleaning , pre - cleaning , spray cleaning , chemical - mechanical planarization ( cmp ) and the like . specific embodiments are described herein with reference to examples of such processes . however , the present disclosure and the reference to certain deposition techniques should not be limited to those described . in some instances , two such techniques may be interchangeable . for example , stripping photoresist may entail immersing a sample in a wet chemical bath or , alternatively , spraying wet chemicals directly onto the sample . specific embodiments are described herein with reference to finfets that have been produced ; however , the present disclosure and the reference to certain materials , dimensions , and the details and ordering of processing steps are exemplary and should not be limited to those shown . turning now to the figures , fig1 shows a top plan view of an existing finfet design 100 on a silicon substrate . the finfet design 100 includes three fins 102 , a metal gate 104 , a gate contact 106 , and a source / drain contact 108 . the source / drain contact 108 forms an electrical connection to a region of epitaxial silicon that acts as a charge reservoir for the transistor . portions of the fins 102 underlying the metal gate 104 serve as the current - carrying channels for the transistors . portions of the fins 102 on either side of the metal gate 104 are coupled to source and drain regions underlying the source / drain contact 108 . the source / drain contact 108 bridges all of the fins 102 , and extends beyond the fins 102 to allow for some margin of error in alignment of a contact lithography mask for establishing a pattern of electrical contacts with respect to the fins 102 . depending on the particular design layout , a gate contact corner 110 may be close enough to an adjacent source / drain contact corner 112 that there is a risk of a short circuit forming between the two contacts . for this reason the gate contact 106 is positioned as far away as possible from the fins 102 . because the contacts are so closely spaced , the fins 102 are prone to damage during the contact etch process . fig2 shows an exemplary sequence of steps in a method 120 of fabricating finfets having tapered source / drain contacts , according to one embodiment . the tapered source / drain contacts reduce the risk of a short circuit to the gate contact 106 . the process shown and described may make use of techniques for nanoscale fin formation , e . g ., a self - aligned sidewall image transfer ( sit ) process , and gate formation , e . g ., a replacement metal gate process , which techniques are known and therefore are not explained herein in detail . the steps 122 - 140 for fabricating high - reliability , low - resistance finfet contacts are described further below , with reference to fig3 a - 6c . in each set of figs . a - c , a is a top plan view showing the finfet gate electrode in a transverse orientation with respect to the fins ; b is a cross - sectional schematic view at a cut line x - x through the gate region , along a particular fin ; and c is a cross - sectional view at a cut line y - y through a source / drain region , across a plurality of fins , adjacent to the gate region . in accordance with convention , arrows on each cut line represent the direction of an observer &# 39 ; s eye looking at the corresponding cut plane . fig3 a - 3c show a partially formed finfet 150 on a silicon substrate 151 , according to one embodiment . the partially formed finfet 150 has raised isolation regions 152 , fins 154 , and a dummy gate 155 . at 122 , the raised isolation regions 152 are formed to define a valley 153 that will accommodate the finfet 150 . the raised isolation regions 152 are made of sio 2 and can be formed according to any suitable process known in the art of semiconductor fabrication . at 124 , the fins 154 are formed in the valley 153 by epitaxial growth extending about 40 - 60 nm from a surface of the silicon substrate 151 . three elongated fins 154 are shown in the valley 153 , however more or fewer fins can be formed in the valley 153 in other embodiments . alternatively , the fins 154 can be formed first at step 122 , and then at step 124 the valley 153 can be defined around the fins , according to another exemplary embodiment . for example , a full array of fins 154 initially can be patterned on the substrate 151 using a thin sin hard mask . then , spaces between the fins 154 are filled with oxide to cover the fins 154 completely , and the oxide is planarized to stop on the thin sin hard mask . the oxide formation is then followed by formation of a thick sin layer , in the range of about 30 - 40 nm . next , the thick sin layer is patterned using a standard photoresist mask to form a hard mask for the valley 153 . that is , the thick sin layer is masked in the center to protect the underlying fins 154 that are to be retained , while the sin layer is removed on either side of the valley 153 . at the same time that the sin is removed , the extraneous fins can also be removed , along with non - active regions of the substrate 151 located outside the valley 153 , using an anisotropic , low selectivity etching process . the non - active regions outside the valley 153 are then over - filled with oxide to form the raised isolation regions 152 . the raised isolation regions 152 remain in place as the sin protective mask overlying the valley 153 and the original thin sin hard mask are removed together . the sin can be removed by for example , a hot phosphoric acid wet etch that attacks sin while leaving behind the sio 2 raised isolation regions 152 . finally , the oxide between the fins 154 is partially removed down to the surface of the valley 153 , revealing the retained fins 154 . the oxide removal step that reveals the fins 154 can be carried out using a isotropic etch that is highly selective to silicon , e , g , a hydrofluoric acid dip . other embodiments in which fins are formed in a valley surrounded by isolation regions can be substituted for either one of the processing sequences described above with respect to steps 122 and 124 . at 126 , a gate electrode 155 is formed including a polysilicon gate 156 , a gate dielectric 157 , silicon nitride sidewall spacers 158 , and a silicon nitride cap 159 . the polysilicon gate 156 and the gate dielectric 157 are temporary layers that will be replaced during a subsequent step . fig4 a - 4c show one embodiment of a partially formed finfet 170 after carrying out a replacement metal gate process and following formation of un - merged epitaxial extensions . at 128 , epitaxial extensions 172 of the fins are formed in the source / drain regions by epitaxial growth outward from the fins 154 . the epitaxial extensions 172 can be made of , for example , doped silicon or silicon germanium to provide charge reservoirs for the device . the epitaxial extensions 172 have diamond - shaped profiles in the example shown , but in general , profiles of the epitaxial extensions 172 can have a variety of different shapes . for example , the epitaxial extensions 172 can be shaped like cubes , ovals , ellipsoids , prismatic shapes , shapes having a corrugated surface , or any number of acceptable shapes , and do not need to be diamond - shaped as shown in fig4 c . the epitaxial extensions 172 do not merge together , but remain un - merged , or spaced apart from one another by a gap that is at least a few nm wide . in the gate region ( fig4 b ), epitaxial growth results in planar layers being formed on a top surface of the silicon substrate 151 . the epitaxial extension 172 serves to increase the electrical contact area to the fins by a factor of about 10 - 12 . at 130 , a protective liner 174 is conformally deposited over the surface of the valley 153 , the epitaxial extensions 172 , and the raised isolation regions 152 . the liner 174 is made of silicon nitride ( sin ), in the range of about 3 - 10 nm thick . in the gate region , the liner 174 conformally covers the planar layers and the gate electrode 155 . at 132 , the valley 153 is filled with amorphous silicon 176 to encapsulate the epitaxial extensions 172 . the amorphous silicon 176 is positioned so as to isolate the epitaxial extensions 172 from effects of the subsequent ild etching process described below . the amorphous silicon 176 may not fill completely the regions between the epitaxial extensions 172 , leaving voids therein . incomplete fill is acceptable because the amorphous silicon 176 is also a sacrificial layer . a top surface of the amorphous silicon 176 is then recessed below the liner 174 by about 10 nm . in the gate region ( fig4 b ) the amorphous silicon 176 forms a planar layer on top of the liner 174 . at 134 , a thick , insulating inter - layer dielectric ( ild ) 180 , e . g ., silicon dioxide ( sio 2 ) or a low - k ild is formed in contact with the amorphous silicon 176 and the liner 174 . the ild 180 is planarized , using the polysilicon gate 156 as a stop layer . during planarization , the cap 159 is removed , along with top portions of the sidewall spacers 158 . at 135 , the polysilicon gate 156 and the gate dielectric 157 are replaced by a metal gate 182 and a high - k gate dielectric 184 , respectively , according to a replacement metal gate process as is known in the art . the metal gate 182 can be made of tungsten ( w ), for example , or a metal stack including tungsten and a work function metal . fig5 a - 5c show one embodiment of a partially formed finfet 200 after forming source / drain contact openings 202 . footprints of the source / drain and gate contact openings are indicated in fig6 a by dashed lines . the footprint areas are about 10 - 20 nm wide × 50 - 100 nm long . at 136 , tapered contact openings 202 are formed using , for example , a two - step etch process : in a first step , a reactive ion etch ( rie ) process etches the ild 180 anisotropically , in a downward vertical direction , to form a tapered column having a top surface width 204 , a bottom surface width 206 , and sidewalls that slope inward from the top surface . the rie for ild removal is a high - power , mechanically harsh process that uses ion bombardment to eject chunks of the ild 180 . in the inventive method , the rie stops on the amorphous silicon 176 so as not to damage the epitaxial extensions 172 . the sin liner 174 may further protect the epitaxial extensions 172 from damage during the contact etch process . the rie can be followed by a second step that uses an isotropic etchant , e . g ., a wet chemical etchant , to more gently remove the amorphous silicon . thus is formed an enlarged pedestal opening 218 at the bottom of the tapered column , the enlarged pedestal opening 218 having a width that is wider than the top surface width 204 . the isotropic etchant attacks the amorphous silicon 176 , selective to the sin liner 174 and the silicon nitride sidewall spacers 158 . in the gate region ( fig5 b ) the planar layer of amorphous silicon is removed , undercutting the ild 180 . the electrical contact area provided by the epitaxial extensions 172 is about 10 - 15 times greater than the surface area of the fins without the extensions . the enlarged pedestal opening 218 will allow the electrical contact to access this larger surface area while maintaining a small footprint , 206 , on the contact mask . fig6 a - 6c show one embodiment of a completed finfet 230 after the source / drain and gate contacts have been filled . at 138 , the liner 174 is removed , for example , using a wet chemical etchant such as hot phosphoric acid that attacks sin selective to both silicon and oxide . thus , the liner 174 is gone in fig6 b and 6c , while the epitaxial extensions 172 and the ild 180 remain intact . at 140 , the tapered source / drain contact openings 202 are filled with a contact metal to form a tapered source / drain contact structure . the contact metal can be , for example , copper , aluminum , tungsten , silver , titanium , titanium nitride , or any other metal , metal alloy , metal stack , or other combinations thereof suitable for interconnections among finfet devices . a first layer of the contact metal can be a thin layer that reacts with the epitaxial extensions 172 to form a silicide as is known in the art . the contact metal fills the valley 153 and the contact openings 202 to form source / drain contacts 232 . a lower portion of the source / drain contacts 232 in the valley 153 forms a bottom pedestal 233 . gate contacts 234 are formed in a similar manner , and can be tapered , and filled in the same step as the source / drain contacts 232 . the bottom pedestal 233 provides increased contact area to the epitaxial extensions 172 . but , by tapering the source / drain contacts 232 down to a depth below the gate contact 234 , the risk of creating a short circuit between the gate contact and the source / drain contact is reduced . the various embodiments described above can be combined to provide further embodiments . all of the u . s . patents , u . s . patent application publications , u . s . patent applications , foreign patents , foreign patent applications and non - patent publications referred to in this specification and / or listed in the application data sheet are incorporated herein by reference , in their entirety . aspects of the embodiments can be modified , if necessary to employ concepts of the various patents , applications and publications to provide yet further embodiments . it will be appreciated that , although specific embodiments of the present disclosure are described herein for purposes of illustration , various modifications may be made without departing from the spirit and scope of the present disclosure . accordingly , the present disclosure is not limited except as by the appended claims . these and other changes can be made to the embodiments in light of the above - detailed description . in general , in the following claims , the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims , but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled . accordingly , the claims are not limited by the disclosure .