it is necessary to notice that the manufacture processes and the structures described below do not include the complete ones . the present invention can be implemented by any kind of manufacturing technologies , and only the necessary manufacturing technologies promoting to understand are described in the following . the invention will be explained in detail in accordance with the accompanying drawings . it is necessary to illustrate that the drawings in the below are only in simplified forms and not drawn in proportion to the real cases . further , the dimensions of the drawings are enlarged for explaining and understanding more clearly . in one embodiment of the present invention , an integrated circuit inductance is formed with the integrated - circuit process . referring to fig1 a , a dielectric layer 102 and a photo - resist layer 104 thereon are provided , and a first pattern is formed in the photo - resist layer 104 by a photolithography process . the substrate under the dielectric layer 102 can be a wafer , or a multi - layer interconnect structure of the integrated circuit , or a multi - layer interconnect structure itself including the dielectric layer 102 . fig1 b shows a top view of the first pattern , wherein the view of the cross - section aa ′ is just fig1 a . before forming the photo - resist layer 104 on the dielectric layer 102 , the dielectric layer 102 should be planarized with a planarization process to acquire a plane surface . the planarization process can be the chemical mechanical polishing method . referring to fig1 b , it can be found that the first pattern has a plurality of first conductive wires substantially in parallel with one another , but the parallel condition is not a necessary condition . referring to fig1 c , it shows a conductive material is filled into the first pattern of fig1 b to form the first conductive wires 106 . fig1 d is the top view of the first conductive wires 106 , wherein the view of the cross - section cc ′ is just the fig1 c . the first conductive wires 106 can be formed by various deposited methods , such as physical and chemical deposition methods , which include evaporation , sputtering , chemical vapor deposition and electroless plating methods , etc . however , before the first conductive material being deposited to form the first conductive wires 106 by the eletroless plating method , a metal layer or a conductive layer must be formed as an electrode or a seed layer . subsequently , the planarization process could be applied to acquire a plane surface after the first conductive wires 106 are formed . the material of the first conductive wires 106 can be aluminum or copper , etc , but other conductive materials could not be excluded . referring to fig1 e , it shows a photo - resist layer 104 is removed and a dielectric layer 108 is formed on the first conductive wires 106 and the first dielectric layer 102 , then , a photo - resist layer 110 is formed on the dielectric layer 108 . a plug pattern is formed in the photo - resist layer 110 for exposing the dielectric layer 108 by the photolithography process . following , the dielectric layer 108 is etched with the plug pattern as a mask to expose a portion of the first conductive wires 106 . fig1 f is a top view of the plug pattern , wherein the view of the cross - section ee ′ is just fig1 e , and the portion of the first conductive wires exposed by etching is shown in fig1 f . the method applied to etch the dielectric layer 108 can be selected from wetting etching , drying etching , isotropic etching and anisotropic etching methods , etc . subsequently , referring to fig1 g , it shows plugs 112 are formed by filling a conductive material into the plug pattern as shown in fig1 e . the plugs 112 can be formed by various deposited methods , such as a physical deposition and chemical deposition , which include evaporation , sputtering , chemical vapor deposition and electroless plating methods , etc . however , before the conductive material being deposited to form the plugs 112 by the eletroless plating method , a metal layer or a conductive layer must be formed as an electrode - or a seed layer . the material of the plugs 112 can be aluminum or copper , etc , but other conductive materials can not be excluded . referring to fig1 h , it shows a photo - resist layer 114 is formed on the dielectric layer 108 after the photo - resist layer 110 is removed . a second pattern is formed in the photo - resist layer 110 by the photolithography process for exposing a portion of the dielectric layer 108 and the plugs 112 . fig1 i is a top view of the second pattern , wherein the view of the cross - section hh ′ is just fig1 h , and the view of the cross - section jj ′ is just fig1 j . before the photo - resist layer 114 being formed on the dielectric layer 108 , the dielectric layer 108 could be planarized with a planarization process to acquire a plane surface . the planarization process can be the chemical mechanical polishing method . referring to fig1 i , it can be found that the second pattern has a plurality of second conductive wires substantially in parallel with one another , additionally , by the plugs 112 , the second conductive wires connect the first conductive wires by an angle ; every second conductive wire and first conductive wire connects the plugs 112 by an another angle which is not necessary a right angle . also , the parallel condition of the second conductive wires is not a necessary condition . referring to fig1 k , it shows a conductive material is filled into the second pattern of fig1 to form the second conductive wires 116 . the second conductive wires 116 can be formed by various deposition methods , such as physical deposition and chemical deposition , which include evaporation , sputtering , chemical vapor deposition and electroless plating methods , etc . however , before the second conductive material being deposited to form the second conductive wires 116 by the eletroless plating method , a metal layer or a conductive layer must be formed as an electrode or a seed layer . subsequently , a planarization process could be applied to acquire a plane surface after the second conductive wires 116 are formed . the material of the second conductive wires 116 could be aluminum or copper , etc , but other conductive materials could not be excluded . fig1 l shows a view of the cross - section ll ′ of fig1 k , wherein the two parts of the first conductive wires 106 with the plugs 112 are respectively located in the diagonal relation . as fig1 m shown , after the photo - resist layer 114 is removed , a dielectric layer 118 is formed on the dielectric layer 108 and the second conductive wires 116 . fig1 m shows a cross - section view in parallel with the cross - section hh ′, wherein each part of the second conductive wires 116 of fig1 m respectively belong to individual conductive wires in parallel with one another . a planarization process could be applied to acquire a plane surface after the dielectric layer 118 is formed , and the planarization process includes a chemical mechanical polishing method . fig1 n shows a cross - section view in parallel with the cross - section ll ′, wherein each part of the first conductive wires 106 respectively belongs to individual conductive wires which are in parallel with one another . the plugs 106 in fig1 n are respectively located at the terminals of each of the first conductive wire . fig2 and fig3 respectively show a top and oblique view of the integrated circuit inductance of the present invention . except for the process of the above - mentioned embodiments , other similar process also could be provided to form an integrated circuit inductance shown as fig3 . referring to fig4 a , a dielectric layer 202 and a photo - resist layer 204 thereon are provided , and a first pattern is formed in the photo - resist layer 204 by a photolithography process . the substrate under the dielectric layer 202 can be a wafer , or a multi - layer interconnect structure of integrated circuit , or a multi - layer interconnect structure itself comprising the dielectric layer 102 . fig4 b is the top view of the first pattern , wherein the view of the cross - section aa ′ is just the fig4 a . before forming the photo - resist layer 204 on the dielectric layer 202 , the dielectric layer 202 should be planarized with a planarization process to acquire a plane surface . the planarization process can be the chemical mechanical polishing method . from fig4 b , it can be found that the first pattern has a plurality of first conductive wires substantially in parallel with one another , but the parallel condition is not a necessary condition . as fig4 c shown , a conductive material is filled into the first pattern of fig4 b to form first conductive wires 206 . fig4 d is the top view of the first conductive wires 206 , wherein the view of the cross - section cc ′ is just the fig4 c . the first conductive wires 206 can be formed by various deposition methods , such as physical and chemical deposition , which include evaporation , sputtering , chemical vapor deposition and electroless plating methods , etc . however , before the first conductive material is deposited to form the first conductive wires 206 by the eletroless plating method , a metal layer or a conductive layer must be formed as an electrode or seed layer . subsequently , the planarization process is applied to acquire a plane surface after the first conductive wires 206 are formed . the material of the first conductive wires 206 can be aluminum or copper , etc , but other conductive materials can not be excluded . referring to fig4 e , it shows the photo - resist layer 204 is removed and a dielectric layer 208 is formed on the first conductive wires 206 , then , a photo - resist layer 210 is formed on the dielectric layer 208 . a plug pattern is formed in the photo - resist layer 210 to expose the dielectric layer 208 by the photolithography process . following , the dielectric layer 208 is etched with the plug pattern as a mask to expose a portion of the first conductive wires 206 . as fig4 f shown , each the first conductive wire defines a cross wire equal in length passing through the center of the first conductive wire . the plug pattern has a plurality of plugs located at a plurality of terminals of the first conductive wires 206 and the cross wires . the method applied to etch the dielectric layer 208 can be selected from wetting etching , drying etching , isotropic etching and anisotropic etching , etc . fig4 e and fig4 f both show the conductive material is filled into the plug pattern to form the plugs 212 . the plugs 212 could be formed by various deposited methods , such as physical and chemical deposition , which comprise evaporation , sputtering , chemical vapor deposition and electroless plating methods , etc . however , before the first conductive material being deposited to form the plugs 212 by the eletroless plating method , a metal layer or a conductive layer must be formed as an electrode or seed layer . the material of the plugs 212 can be aluminum or copper , etc , but other conductive materials can not be excluded . subsequently , as fig4 g shows a photo - resist layer 214 is formed on the dielectric layer 208 after the photo - resist layer 210 is removed . applying the photolithography process , a plug pattern is formed in the photo - resist layer 210 to expose a portion of the dielectric layer 208 and a portion of the plugs 112 . fig4 h is a top view of the second pattern , wherein the view of the cross - section gg ′ is just fig4 g . the second pattern has a plurality of wires substantially in parallel with one another , wherein the second pattern connects two plugs 212 which are respectively located at the terminals of each the cross wire . before the photo - resist layer 214 is formed on the dielectric layer 208 , the dielectric layer 208 and the plugs 212 should be planarized with a planarization process to acquire a plane surface . the planarization process can be the chemical mechanical polishing method . from fig4 h , it shows the second pattern has a plurality of wires substantially in parallel with one another , additionally , by the plugs 212 , the second conductive wires connect the first conductive wires by an angle ; every second conductive wire and first conductive wire connects the plugs 212 by an another angle which is not necessary a right angle . also , the parallel condition of the second conductive wires is not a necessary condition . fig4 i shows a conductive material that is filled into the second pattern of fig4 g to form the second conductive wires 216 , and then the photo - resist 214 is removed . the second conductive wires 216 can be formed by various deposition methods , such as physical deposition and chemical deposition , which comprise evaporation , sputtering , chemical vapor deposition and electroless plating methods , etc . however , before the second conductive material being deposited to form the second conductive wires 216 by the eletroless plating method , a metal layer or a conductive layer must be formed as an electrode or a seed layer . subsequently , a planarization process method could be applied to acquire a plane surface after the second conductive wires 216 are formed . the material of the second conductive wires 216 could be aluminum or copper , etc ., but other conductive materials could not be excluded . fig4 j shows a top view cross - section of the second conductive wires 216 , and the view of the cross - section ii ′ is just fig4 . fig4 k shows that a dielectric layer 218 is formed on the dielectric layer 208 and the second conductive wires 216 . a planarization process method could be applied to acquire a plane surface after the dielectric layer 218 is formed , the planarization process method can be the chemical mechanical polishing method . the integrated circuit inductance formed in the above second embodiment is equal to the one of fig3 rotated clockwise or counterclockwise by 180 degree . the above - mentioned of the present invention , such as , the related embodiments , the component nouns of the embodiments , the angles between the components and the relative position of certain components , are only for example , not limits . for instance , “ plug ” is only the usual noun of the components installed through a dielectric layer . as a full inductance concerned , the plugs and the wires in the present invention are actually identical , they are all the portions of the inductance . besides , the angles between the components are not necessary right angles , as shown in the drawings or the above mentions , as long as the inductance loops composed of the plugs and the conductive wires can induce the variation of the passing current to generate the electromotive force ( emf ) or voltage . additionally , the amount of the loops composed of the plugs and the conductive wires can be increased according to the demand . also , the terminals of the integrated circuit inductance can be connected with other components in the wafer to make up a demanded circuit , wherein the connecting method can be selected form photolithograph process , deposition process , etching process , and so on . the above - mentioned preferred embodiments of the present invention are just for example , not limits . thus , many equal variations and modifications of the embodiments made without departing form the spirit of the present invention should be covered by the following claims .