the present invention relates to an improvement in the generation of video signals in the graphics mode . the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a particular application and its requirements . various modifications to the preferred embodiment will be readily apparent to those skilled in the art , and the generic principles defined herein may be applied to other embodiments . thus , the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and novel features disclosed herein . referring now to fig1 what is shown is a typical video graphics array ( vga ) system 12 coupled to a central processing unit ( cpu ) 22 and display devices 24 and 26 . the vga system 12 under control of the cpu 22 produces images to be displayed on display devices 24 and 26 . the vga system 12 comprises a video memory 14 ( which includes a plurality of planes 15 ( b0 - b3 ) coupled in parallel which is in turn coupled to a controller 16 . the controller receives clock signals from &# 34 ; dot &# 34 ; clock 20 and also is coupled to a digital to analog converter ( dac ) 18 . the dac 18 converts digital signals from the controller 16 to analog signals , based on an internal color palette , and drives display device 26 . many display devices require digital signals to display images . hence , as is shown , a digital signal is derived directly from the controller 16 to display device 24 so that images can be displayed on display device 24 . in this embodiment the video memory 14 comprises a plurality of banks 15 ( b0 - b3 ) in the video memory . each bank can typically hold 64 kilobytes ( kb ) of memory and the total memory storage area is 256 kb . although four banks are shown , it should be understood , however , that there can be any number of banks 15 in the video memory and that different number would be within the spirit and scope of the present invention . to explain further the operation of the above - identified vga system , the term &# 34 ; plane &# 34 ; will be defined . as has been before - mentioned , there are a plurality of banks 15 in the video memory which are typically a physical group of random access memories ( ram ). a plane represents a portion of the video memory . referring now to fig2 shown are four planes of memory ( p0 - p3 ). in this embodiment , four planes are utilized ; however , one of ordinary skill in the art will recognize that a different number of planes could represent the video memory and that would be within the spirit and scope of the present invention . each of these planes represents a part of the color information of the image . these planes can be configured into two types of memory organizations , packed pixel and planar . to further describe the environment of the present invention , the next few paragraphs in conjunction with fig3 - 5 will describe the two major types of memory organizations of the vga system of fig1 . fig3 depicts a packed pixel architecture . fig4 depicts a planar architecture . fig5 depicts a portion of the video memory 14 , internal registers of the vga controller 16 , color plane enable register 48 , attribute logic 50 , and two color select registers 52 and 54 . the color plane register 48 , attribute logic 50 , and color enable registers 52 and 54 have been depicted in block diagram form . it is well known that these elements can comprise a variety of types of logic circuits . to understand the present invention , it is not necessary to describe the specific implementation of these elements and hence any further explanation concerning these elements will be their function in relation to the below described video modes . in the packed pixel memory organization , one pixel is stored in one byte of the video memory 14 ( fig1 ). from the programmer point of view , the memory 14 is one contiguous memory space . thus , in this memory organization the image is stored in all four planes . to generate four pixels utilizing this memory organization , the controller 16 generates an address signal to the video memory 14 . at this location four different pixels are stored , one in each plane ( p0 - p3 ). the controller 16 reads those pixels and then buffers them internally . then responsive to the next four clock signals from the dot clock 20 , it sends one pixel at a time to the dac 18 . fig3 depicts the shifting of pixels of information from video memory 14 into video shift registers 162 , 164 , 166 , 168 of the vga controller 16 . in packed pixel mode 13 , video information is generated in the following way : at regular intervals ( every 4 pixel times ) new pixel data is loaded into the vga controller 16 from the video memory 14 . four adjacent pixels are stored at the same address in the four planes ( p0 - p3 ) of the video memory 14 . in this embodiment , the first pixel is stored in the first plane , the second in the second plane , etc . the video shift registers 162 , 164 , 166 , 168 of the vga controller 16 are loaded in such a way that the first pixel is shifted out first , the second pixel is shifted out next until all of the pixels are shifted out of the vga controller 16 . since the internal data path of the vga controller 16 is only four bits wide , and since the pixel is defined by 8 bits , a nibble ( 4 bits ) at a time must be shifted through the vga controller 16 . the upper nibble of each pixel is shifted out first ( d4 - d7 ), then the lower nibble of each pixel is shifted out next . the upper nibble is stored at the end of the attribute logic 50 ( fig5 ) ( d0 - d3 ), and is joined by the lower nibble when the lower nibble is shifted through the attribute logic 50 . the color plane enable register 50 is not used in packed pixel mode 13 . no alteration to the 2 four bit values are performed by the attribute logic 50 in packed pixel mode 13 . the vga controller 16 then outputs the resultant 8 bit pixel quantity from the vga into the external dac 18 . for the duration of one pixel time ( two internal clock cycles ) the 8 bit value is output from the vga controller 16 . in planar memory organization , one pixel is stored in multiple planes of the video memory 14 . in this type of organization , each pixel is represented by four bits of video information . hence , eight adjacent pixels are stored in four bytes located at the same address in the four planes of memory 14 . to access the video memory 14 , control registers ( not shown ) are used to select the specific plane to be accessed . to generate video signals from this memory organization , the controller 16 generates an address to the memory 14 . it then reads four bytes from the memory 14 and assembles eight four - bit pixels . in this embodiment , the first pixel is defined by bit 7 in each plane . the next pixel is defined by bit 6 in each plane and so on and so forth until each pixel is generated . fig4 depicts the shifting of pixels of information into video shift registers 162 , 164 , 166 , 168 in planar mode . in planar video mode , video is generated in the following way : at regular intervals ( every 8 pixel times ) new pixel data is loaded into the vga controller 16 from the video memory 14 . eight pixels are defined by the 4 bytes located at the same address in the video memory 14 . thus , every pixel is defined by 4 bits . each pixel is defined by a specific bit in each byte in the four planes . referring again to fig5 the internal shift registers 162 , 164 , 166 , 168 of the vga controller 16 are loaded in such a way that the first pixel is shifted out first , the second pixel is shifted next . the pixel then passes through the color plane enable register 50 . in this video mode the register 48 acts as a mask which can disable individual pixel bits from specific planes . the pixel information is then shifted into the attribute logic 48 . here an internal palette of 16 entries , each 6 bits wide , is used to transform the 4 bit input value to a 6 bit output value . this 6 bit value is supplemented by 2 bits from the color select registers 52 and 54 to form an 8 bit value . this value is output from the vga controller 16 and sent to the external dac 18 . in describing the operation of a vga system in a computer , only those elements that are necessary for an understanding of the present invention have been described in detail . it is understood by one of ordinary skill in the art that there are other elements within the vga system that must be present to provide an efficiently operating system . now referring back to the overall operation of the vga system , the controller 16 is responsible for both generating video signals to display devices 24 and 26 , and managing the cpu interface . the controller 16 reads the information out of the video memory 14 and sends the video information to the dac 18 . the cpu interface allows an application program from the cpu 22 to write into and read from the video memory 14 . the dac 18 contains a palette which has a plurality of entries . in a typical vga system , a palette contains 256 entries . each entry in turn contains a color value . these values are typically called rgb values for the primary colors red , blue and green . in a preferred embodiment each component of the value ( r , g and b ) individually contains 6 bits of information . hence , each rgb value comprises 18 bits of information . for each digital input from the controller 16 , the dac 18 looks up a corresponding rgb value . based upon this rgb value , the dac 18 produces three analog signals ( r , g and b ), which are sent to monitor 26 . therefore , to generate video signals to be displayed by monitor 26 , the following sequence of events occur : 1 . an address signal into the video memory 14 is generated by the controller 16 . 2 . data is read out of memory 14 and into the vga controller 16 . 3 . for each clock cycle initiated by clock 20 , a pixel of information is sent out of the vga as a digital value to the dac . 5 . the three analog signals are formed and sent to the monitor 26 . this system works effectively for generating the analog signals to be displayed by display device 26 . however , this system cannot be used for display device 24 in which digital signals are required to produce the image . these types of monitors require a digital video signal of grayscale information . as has been mentioned before the rgb value stored in one of the entries of the dac 18 will determine the color of a specific pixel . after the digital information representing that rgb value enters the dac , the pixel is assigned a color value . in other words , the digital information entering the dac 18 represents an address into the dac , which will become an rgb value after leaving the dac 18 . the dac 18 does not directly drive the grayscaling display device 24 . this display device 24 requires a digital video signal that comprises the grayscale equivalent of the analog rgb value , and is driven directly by the vga . it is known that there is a certain graphic video mode , mode 13 hex , in which the color of a pixel is defined first in the dac 18 . by bypassing the dac 18 , where the colors are defined , the resultant image displayed on the grayscaling display device 24 will be distorted . the present invention is directed to a system for ensuring that the packed pixel image created by a vga system is displayed on a digital grayscaling display device accurately . referring now to fig6 what is shown is a system diagram of the operation of the vga system in accordance with the present invention . shown is the vga controller 16 , the dac 18 and display devices 24 and 26 of fig1 . what is also shown is an application program 60 which will reside in the cpu memory address space , the video memory 14 and the system 64 of the present invention . the system 64 uses to advantage the unused video memory space 63 of video memory 14 to allow for the generation of an image that does not have a grayscale equivalent within the dac 18 . in this embodiment , the application program 60 draws an image into the first portion of the memory 14 at location 61 . the system 64 will then read one pixel of that image from the video memory 14 . it will read the pixel color from the dac 18 and compute a grayscale value , based on a grayscale algorithm . that grayscale value is then written into the unused video memory portion 63 . then that grayscale information is handled by the vga controller 16 and delivered to the display device 24 . in this embodiment the display device 24 can be a so - called &# 34 ; flatpanel &# 34 ; display device utilized to display monochrome or grayscale images . through the use of this system 64 , a video mode which has heretofore been poorly displayed on digital monitors can now be accurately displayed . to provide a more specific embodiment , refer now to fig7 . in fig7 shown is a flow chart of a system to achieve the above - identified result . the present invention is described in terms of mode 13 in fig3 but one of ordinary skill in the art should recognize that future video modes may also be improved by the invention . the basic purpose of the system depicted by the flow chart is to convert an image drawn by an application program to the grayscale equivalent in real time . whenever a mode 13 initialization request is issued by the application program to the computer system software embedded in the read only memory ( rom ), called video basic input / output system ( bios ), the request is intercepted ( box 100 ) by the system of the present invention . the present invention then programs the vga system 12 ( fig1 ) for planar organization ( box 104 ) rather than packed pixel architecture as would normally happen . thereafter , the present invention causes the controller 16 to direct video information from the application to plane 0 only of the video memory ( box 108 ). the present invention then allows plane 1 - 3 to be accessed by the controller for video generation and prevents plane 0 from being used ( box 138 ). the present invention continues to cause the controller to operate in the planar mode so as to read the information out of planes 1 - 3 ( box 138 ). thereafter at regular intervals , the present invention is invoked by the computer clock ( box 112 ) to initiate a grayscaling refresh cycle . the system then reads the contents of the dac and converts the entries of the dac into grayscale values ( boxes 116 and 118 ). in a typical system each gray shade is defined by 3 bits , thereby creating eight different shades of gray . since plane 0 is used to hold the packed pixel video image , three other planes are available in an ordinary vga system . thus 2 3 = 8 gray levels can be generated . thereafter , the system reads the first eight pixels from the image stored in plane 0 ( box 124 ) . then those eight pixels are converted into their grayscale equivalents using the grayscale equivalent of the dac , stored in the program workspace . the color of each pixel is thereby converted into a 3 - bit grayscale value . the grayscale values are then reformatted to be written into the video memory in the planar mode ( box 132 ). planes 1 - 3 will be written . the present invention will repeat blocks 132 , 136 and 138 until the image is completely processed ( decision box 142 ). the system can then be invoked again by the clock ( box 112 ) to start a new refresh cycle . through the use of the above identified system , a visually correct color image can be displayed on a display device that is driven by a digital signal without significantly increasing the cost or complexity of the vga system . in a preferred embodiment , the present invention of fig6 or fig7 is a software program that is resident within the cpu . the program has the advantage of not requiring any new hardware or take up additional space in the system as well as not consuming additional power . in addition , a hardware embodiment would require format and timing synchronization . this could also add significant complexity to the vga system . these may all be of significant commercial importance if the present invention is utilized in &# 34 ; laptop &# 34 ; or &# 34 ; notebook &# 34 ; type personal computers . therefore , at the present time , this type of system is advantageously implemented in software . it will be understood , however , by one of ordinary skill in the art that the present invention could be readily implemented in hardware components . as the technology develops , the above - mentioned disadvantages may be overcome . in so doing , many of the aforementioned advantages of the present invention could still be readily obtained . it is understood that the above - described embodiment is merely illustrative of but a small number of the many possible specific embodiments which can represent applications of the principles of the present invention . numerous and various other arrangements can be readily devised in accordance with these principles by one of ordinary skill in the art without departing from the spirit and scope of the present invention . the scope of the present invention is limited only by the following claims :