a brief explanation will now be given as to the qpsk modulation with reference to fig1 for the better understanding of the present invention . referring to fig1 it is assumed that a transmit signal includes two - bit codes . i . e ., 00 , 01 , 11 and 10 , and a symbol rate is determined as 21 k symbol / s . when the carrier wave signal is modulated with the transmit signals , the vector α makes 45 °, 135 °, - 135 ° and - 45 ° rotations on the iq plane with a reference point p as the reference of rotation . that is , the qpsk - modulated carrier is phase - shifted by an angle equal to that formed by the vector α which rotates on the iq plane and the axis i . further , since one rotation of the vector α on the iq plane means 1 hz shift of the frequency , the aforementioned angle shift of the carrier is equivalent to the frequency shift . for example , since the angle shift is 45 ° when the transmit signal is 00 , one rotation of the vector α on the iq plane means 8 - symbol rate ( 45 °/ 360 °), and at this time the frequency shift of the carrier is hence : the relationship among the transmit signals , the angle shift of the carrier and the frequency shift is shown in table . table______________________________________transmit signal angle shift frequency shift______________________________________00 45 ° 2 . 625 khz01 135 ° 7 . 875 khz11 - 135 ° - 7 . 825 khz10 - 45 ° - 2 . 625 khz______________________________________ the qpsk demodulation will now be described in connection with fig2 . referring to fig2 it is assumed that the frequency deviation of a desired if signal is 0 khz when no frequency shift is made by the qpsk modulation . when the frequency deviation of the if signal is 0 to 5 . 25 khz , a receiver recognizes that the transmit signal is 00 . further , the demodulation of the next transmit signal to be received is performed on the basis of the frequency shift of the if signal which is currently received . in other words , since the transmit signal which is currently received is recognized as 00 , the frequency shift 2 . 625 khz is determined as a reference value . when the shift of the if which is subsequently received is within ± 2 . 625 khz with respect to the above reference value , the transmit signal is recognized as 00 ; when the same is equal to or above 2 . 625 khz and equal to or below 7 . 875 khz , the transmit signal is recognized as 01 ; when the same is equal to or above - 7 . 875 khz and equal to or below - 2 . 625 khz , the transmit signal is recognized as 10 ; and when the same is equal to or above - 13 . 125 khz and equal to or below - 7 . 875 khz , the transmit signal is recognized as 11 . when any deviation other than that caused by the qpsk modulations included in the frequency of the if signal , however , there occurs a problem in the above - described demodulation . concretely , when the frequency of the if signal deviates by ± 1 / 8 or more with respect to one symbol , i . e ., when this frequency deviates from the reference if by ± 2 . 625 khz or more due to a factor other than the qpsk modulation , the accurate demodulation is not possible . referring again to fig2 the brief explanation will be given hereinbelow . it is assumed that the transmit signals has been transmitted in the order of 10 , 11 and 00 . when the frequency shift obtained by qpsk modulation with the firstly - received signal 10 is - 2 . 625 khz and the frequency is shifted within the range from - 5 . 25 khz to 0 khz with respect to the desired if signal 450 khz , the transmit signal is detected as 10 . however , when the frequency of the if signal deviates by - 2 . 625 khz or more due to the deviation of the oscillation frequency output from a reference oscillation circuit , the frequency shift of the if signal to be detected becomes - 2 . 625 khz +(- 2 . 625 khz ) or more , i . e ., - 5 . 25 khz or more and the detection of the transmit signal would be mistaken , i . e ., the transmit signal is detected as 11 . further , since the demodulation of the next signal to be received is carried out by using the frequency shift - 7 . 875 khz as a reference , the accurate modulation is impossible . referring again to the afc described in the aforementioned reference 1 , a desired if is obtained by eliminating the frequency shift due to the qpsk modulation from the frequency of the if signal , the deviation is thus produced to the oscillation frequency output from the reference oscillation circuit constituting the afc . when the transmit signal is 10 and the deviation exceeds - 2 . 625 khz , the accurate demodulation becomes impossible , as described above . therefore , a desired if signal can not be obtained in the afc according to reference cited 1 . the present invention which can solve the above - described problems will now be explained . in fig3 a frequency mixing circuit 1 mixes a frequency output from a non - illustrated antenna with a local oscillation frequency signal output from a local oscillator ( referred to as a pll circuit hereunder ) 14 and outputs an if signal . a reference oscillation circuit 13 outputs a reference frequency signal to the pll circuit 14 in accordance with a control voltage signal output from a later - described digital - to - analog conversion circuit ( referred to as a dac hereinafter ) 12 . a frequency measurement counter circuit 8 counts the frequency of the if signal on the basis of the reference frequency signal and outputs a frequency count signal . a qpsk demodulation circuit 2 demodulates the if signal and outputs a demodulated signal . a first frequency compensation circuit 3 receives the demodulated signal and detects the frequency shift of the if signal due to the qpsk modulation . thus , the first frequency compensation circuit 3 integrates the detected frequency shift in accordance with the reference frequency signal to obtain its mean value and outputs a frequency shift count signal . in addition , the first frequency compensation circuit 3 does not output frequency shift count signal to a first subtraction circuit 4 when the power supply is turned on . the first subtraction circuit 4 subtracts the frequency shift count signal from the frequency count signal . in other words , the first subtraction circuit 4 subtracts the amount of the frequency shift of the if signal caused by the qpsk modulation from the frequency of the if signal and outputs a compensation signal . a first frequency compensation control circuit 5 detects that the if signal is converged until qpsk demodulation circuit 2 can demodulate the if signal and outputs a first control signal . that is , since the frequency of the if signal deviates due to the frequency shift of the reference frequency signal caused by a temperature change besides the frequency shift caused by the qpsk modulation , the first frequency compensation control circuit 5 is used to overcome such a drawback that the qpsk demodulation circuit 2 can not perform the demodulation when the deviation of the frequency of the reference frequency signal is large . since the range of the frequency deviation of the if signal with which the qpsk demodulation circuit 2 can carry out the demodulation is within 2 . 625 khz , the first frequency compensation control circuit 5 outputs the first control signal when the frequency of the if signal is converged within this range and controls to input the frequency shift count signal output to the first subtraction circuit 4 . a convergence judgement circuit 7 judges whether the frequency of the if signal is converged within the allowance with respect to a value on which the frequency is to be finally converged , and outputs a convergence completion signal . in other words , since the allowance of the frequency deviation of the if signal from the desired frequency of the if signal is within 3 ppm , the convergence judgement circuit 7 outputs the convergence completion signal when the frequency deviation of the if signal is converged within this range . a second frequency compensation circuit 6 adds or subtracts a fixed value to or from the compensation signal in order to compensate the frequency deviation of the if signal due to the temperature change or the like , and outputs a second control signal . a switch signal generation circuit 10 receives the frequency count signal and outputs a switch signal synchronized with such a timing that the second frequency compensation circuit 6 outputs the second control signal . a switch circuit 11 interrupts the input of the switch signal to a retention circuit 9 upon receiving the convergence completion signal . the retention circuit 9 is constituted by a d flip - flop and receives the switch signal at a clock terminal ck thereof . further , a power supply control signal from the power supply is input to a pr terminal , and the value of retention circuit 9 is set to an initial value . moreover , the retention circuit 9 receives the second control signal at a d terminal thereof and outputs a value retained therein as a retention signal from an output terminal q thereof . a dac 12 subjects the retention signal to the digital - to - analog conversion and outputs a control voltage signal . as shown in fig4 the pll circuit 14 comprises a frequency division circuit 15 , a phase comparison circuit 16 , a low - pass filter 17 and a voltage control oscillation circuit 18 . the frequency division circuit 15 divides the frequency of the local oscillation frequency signal output from the voltage control oscillation circuit 18 and outputs a frequency division signal . the phase comparison circuit 16 receives the frequency division signal and the reference frequency signal and outputs a phase difference signal indicating the phase difference between the received two signals . the low - pass filter 17 interrupts high - frequency components of the phase difference signal , namely , the filter 17 integrates the phase difference signals for a predetermined time and outputs an integration signal . the voltage control oscillation circuit 18 outputs a local oscillation frequency signal controlled by the integration signal . referring to fig5 the first frequency compensation circuit 3 comprises a first memory circuit 19 , an integration circuit 20 and a division circuit 21 , the first memory circuit 19 uses the demodulation signal as an address and outputs a frequency shift digital signal indicating the frequency shift of the if signal whose frequency has shifted due to the qpsk modulation . the integration circuit 20 uses the reference frequency signal as a clock and integrates the frequency shift digital signals in synchronism with the frequency count of the frequency measurement counter circuit 8 to output a frequency shift integration signal . the division circuit 21 divides the frequency shift integration signal by the number of frequency shift digital signals output from the first memory circuit 19 . that is , the division circuit 21 calculates a mean value of the output frequency shift digital signals and outputs the frequency shift count signal . further , the division circuit 21 receives the first control signal and outputs the frequency shift count signal to the first subtraction circuit 4 only when the qpsk demodulation circuit 2 can accurately demodulate the if signal . in addition , the division circuit 21 is so controlled as not to output the frequency shift count signal when the power supply is turned on . in fig6 the first frequency compensation control circuit 5 is constituted by a second subtraction circuit 22 , a first comparison circuit 23 , a second memory circuit 24 and a third memory circuit 25 . the second memory circuit 24 stores a truth value signal having a value on which the frequency of the if signal is to be converged , and outputs this value to the second subtraction circuit 22 . the second subtraction circuit 22 subtracts the truth value from the compensation signal and outputs a first frequency shift signal . the third memory circuit 25 stores the frequency deviation within such a range that the qpsk demodulation circuit 2 can demodulate the if signal , i . e ., 2 . 625 khz as a first frequency shift allowance signal , and outputs this signal to the first comparison circuit 23 . the first comparison circuit 23 compares the first frequency shift signal with the first frequency allowance signal and outputs the first control signal which is equal to a high level signal when the first frequency shift signal belongs to the first frequency shift allowance signal , and subsequently controls the division circuit 21 to output the compensation signal to the first subtraction circuit 4 . the first comparison circuit 23 outputs a low level signal when no first control signal is output and controls the division circuit 21 not to output the compensation signal . in fig7 the convergence judgement circuit 7 includes a third subtraction circuit 26 , a second comparison circuit 27 , a fourth memory circuit 28 and a fifth memory circuit 29 . the fourth memory circuit 28 stores a truth value signal having a value on which the frequency of the if signal is to be converged and outputs the truth value signal to the third subtraction circuit 22 . the third subtraction circuit 26 subtracts the trueth value signal from a compensation signal and outputs a second frequency shift signal ( the value of the second frequency shift signal is equivalent to the aforementioned value of the first frequency shift signal ). the fifth memory circuit 29 stores the deviation of 3 ppm from the frequency of the predetermined if signal as a second frequency allowance signal and outputs this stored signal to the third subtraction circuit 27 . the second comparison circuit 27 compares the second frequency shift signal with the second frequency allowance signal , and outputs the convergence completion signal which is a low level signal when the second frequency shift signal belongs to the second frequency shift allowance signal and interrupts the input of the switch signal , through the switch circuit 11 , to the retention circuit 9 . referring now to fig8 the second frequency compensation circuit 6 is composed of a fourth subtraction circuit 30 , a sixth memory circuit 31 , an addition / subtraction circuit 32 and a seventh memory circuit 33 . the sixth memory circuit 31 stores a truth value signal having a value on which the frequency of the if is to be converged and outputs the truth value signal to the fourth subtraction circuit 22 . the fourth subtraction circuit 26 subtracts the truth value signal from the compensation signal and outputs a third frequency shift signal ( the value of the third frequency shift signal is equivalent to the value of each of the above first and second frequency shift signals ). the seventh memory circuit 33 stores a step width signal having a fixed step width and outputs the step width signal to the addition / subtraction circuit 33 . the addition / subtraction circuit 32 performs the addition or subtraction with respect to the step width signal in accordance with the third frequency shift signal which is a control signal . namely , the addition / subtraction circuit 32 subtracts the step width signal from the retention signal which is the output of the retention circuit 9 when the third frequency shift signal has a positive value while the circuit 32 adds the step width signal to the retention signal which is the output of the retention circuit 9 when the third frequency shift signal has a negative value , and outputs the second control signal . in fig9 the switch signal generation circuit 10 is composed of a pulse generation circuit 34 and a delay circuit 35 . the pulse generation circuit 34 receives the frequency measurement count value signal and generates a pulse signal every time when the frequency measurement count value signal is reset to 0 . the delay circuit 35 delays the pulse signal and outputs a switch signal . the amount of delay of the delay circuit 35 is determined in such a way that the switch signal is supplied to the retention circuit 9 through the switch circuit 1 in synchronism with the timing when the second control signal is input to the retention circuit 9 . the detailed description will now be given as to the operation of the frequency control circuit shown in fig3 . when the power supply is turned on , the voltage control signal is input from the power supply circuit to the pr terminal of the retention circuit 9 and the retention circuit 9 is set to the initial value . this initial value is set to a count value at which the frequency in the middle of the range of the oscillation frequencies , which can be oscillated , of the reference frequency signal output from the reference oscillation circuit 13 is output . that is , assuming that the retention signal output from the retention circuit 9 is the 8 - bit digital signal , the frequency of the reference frequency signal output from the reference oscillation circuit 13 has a maximum value when the count is 255 which is the maximum value of the 8 - bit digital signal , meanwhile the same has a minimum value when the count is 0 . accordingly , the count 128 is the initial value of the retention circuit 9 . further , when the power supply is turned on , the output of the frequency shift count signal supplied from the division circuit 21 constituting the first frequency circuit 3 to the first subtraction circuit 4 is interrupted . the retention signal which is a digital signal is converted to an analog signal by the dac 12 and fed to the reference oscillation circuit 13 as the control voltage signal . the reference oscillation circuit 13 outputs the reference frequency signal having a frequency according to the received control voltage signal . the voltage control oscillation circuit 18 constituting the pll circuit 14 outputs a value which has been locked before the power supply is turned on as an initial value , and the local oscillation frequency signal which is equal to this initial value is frequency - divided by the frequency division circuit 15 and the obtained frequency division signal is output to the phase comparison circuit 16 . the phase comparison circuit 16 also receives the reference frequency signal and outputs a phase difference signal corresponding to the amount of the phase difference between the reference frequency signal and the frequency division signal to the low - pass filter 17 . the low - pass filter 17 carries out the suppression of the high frequency components of the phase difference signal , i . e ., the integration of the phase difference signal to output an integration signal . the voltage control oscillation circuit 18 fetches the integration signal as the control signal and outputs the local oscillation frequency signal synchronized with the phase of the reference frequency signal . the frequency of the reference frequency signal is directly proportional to the frequency of the local oscillation frequency signal . thus , the frequencies of the local oscillation frequency signal and the if signal can be set to desired frequencies , respectively , by setting the frequency of the reference frequency signal to a desired frequency . the local oscillation frequency signal is input to the frequency mixing circuit 1 , and the frequency mixing circuit 1 performs the frequency mixing of the local oscillation frequency signal and the signal received from the non - illustrated antenna to output the if signal . in this embodiment , the frequency mixing is carried out in the upper local manner , and the intermediate frequency signal is generated by subtracting the frequency of the received signal from the local oscillation frequency signal . in the frequency measurement counter circuit 8 , the if signal is subjected to the frequency count with the reference frequency signal as the clock signal , and the frequency count signal is output to the first subtraction circuit 4 . in this embodiment , the time period during which the frequency measurement counter circuit 8 counts the frequency of the if signal is one second . the if signal is also input to the qpsk demodulation circuit 2 to be demodulated therein . in this demodulation , assuming that the symbol rate of the transmit signals is 21 k symbol , the if signals during one second are equal to 21 k , i . e ., 21 , 000 symbols , and the qpsk demodulation circuit 2 performs the demodulation 21 , 000 times during one second and outputs the demodulation signals . the demodulation signal is input to the first memory circuit 19 constituting the first frequency compensation circuit 3 as the address signal . the first memory circuit 19 outputs the frequency shift digital signal which is assigned by the address signal . the frequency shift digital signal is input to the integration circuit 20 and integrated with the reference frequency signal as a clock . since the reference frequency signal is also input to the frequency measurement counter circuit 8 , the integration carried out in the integration circuit 20 is synchronized with the frequency count performed in the frequency measurement counter circuit 8 , and the integration circuit 20 integrates the frequency shift digital signals to be input thereto during one second , i . e ., 21 , 000 frequency shift digital signals and outputs the integration signal . the integration signal is input to the division circuit 21 . the value of the integration signal is divided by 21 , 000 and the frequency shift count signal is output . at this time , the output of the frequency shift count signal to the first subtraction circuit 4 is , however , interrupted because the power supply has been turned on . the frequency count signal is input to the first subtraction circuit 4 , but this signal is directly output as the compensation signal since the frequency shift count signal is not supplied thereto . the compensation signal is input to the second subtraction circuit 22 constituting the first frequency compensation control circuit 5 , and the truth value signal is subtracted from the compensation signal to detect the deviation from a desired frequency of the if signal . thereafter , the first frequency shift signal is output . the first frequency shift signal is input to the first comparison circuit 23 , and the first control signal which is a high level signal is output if the first frequency shift signal belongs to the first frequency shift allowance signal . the first comparison circuit 23 is controlled in such a manner that the division circuit 21 outputs the frequency shift count signal to the first subtraction circuit 4 when the frequency measurement counter circuit 8 outputs the next frequency count signal . meanwhile , if the first frequency shift signal does not belong to the first frequency shift allowance signal , a low level signal is output , and the setting which is the same as the power supply is turned on , i . e ., the state in which the output to the division circuit 21 is interrupted is maintained when the frequency measurement counter circuit 8 output the next frequency counter signal . here , it is assumed that the first frequency shift signal does not belong to the first frequency shift allowance signal ; the first comparison circuit 23 outputs the low level signal ; and the division circuit 21 is so controlled as not to output the frequency shift count signal to the first subtraction circuit 4 even when the frequency measurement counter circuit 8 outputs the next frequency count signal . since the output of the division circuit 21 is currently interrupted , the compensation signal , i . e . the frequency count signal is also input to the third subtraction circuit 26 constituting the convergence judgement circuit 7 . the third subtraction circuit 26 subtracts the truth value signal from the compensation signal to detect the deviation from a desired frequency of the if signal and outputs the second frequency shift signal . the second frequency shift signal is input to the second comparison circuit 27 , and the convergence completion signal which is the low level signal is output if the second frequency shift signal belongs to the second frequency shift allowance signal . thereafter , the renewal of the retention signal retained in the retention circuit 9 is stopped . meanwhile , if the second frequency shift signal does not belong to the second frequency shift allowance signal , the high level signal is output , and the retention signal retained in the retention circuit 9 is renewed every time when the clock signal is supplied to the retention circuit 9 , thereby compensating the deviation of the frequency of the reference frequency signal step by step . here , it is assumed that the second frequency shift signal does not belong to the second frequency shift allowance signal ; the second comparison circuit 27 outputs the high level signal ; and the retention signal in the retention circuit 9 is renewed every time when the clock signal is fed to the retention circuit 9 . further , since the compensation signal , i . e ., the output of the division circuit 21 is currently interrupted , the frequency count signals also input to the fourth subtraction circuit 30 constituting the second frequency compensation circuit 6 . the third subtraction circuit 30 subtracts the truth value signal from the compensation signal to detect the deviation from a desired frequency of the intermediate frequency signal , and outputs the third frequency signal . assuming that the value of the frequency of the if signal is lower than that of the desired frequency of the if signal , the addition / subtraction circuit 33 adds the retention signal in the retention circuit 9 , which is currently the initial value initialized when the power supply is turned on , to the step width signal stored in the seventh memory circuit 33 , and outputs the second control signal to the retention circuit 9 . since the switch circuit 11 is currently closed , the second control signal is fetched to the retention circuit 9 in synchronism with the input of the switch signal , and the retention circuit 9 outputs the second control signal to the dac 12 as the retention signal . the retention signal is converted into an analog signal by dac 12 and output to the reference oscillation circuit 7 as the control voltage signal . the above - described operation is thereafter repeated until the comparison in the first comparison circuit 23 constituting the first frequency compensation control circuit 5 is completed . that is , the operation is repeated until the first frequency shift signal belongs to the first frequency shift allowance signal and the first comparison circuit 23 outputs the first control signal which is the high level signal . if the first frequency shift signal belongs to the first frequency shift allowance signal and the first comparison circuit 23 outputs the first control signal which is the high level signal , it means that the qpsk demodulation circuit 2 can carry out the demodulation by using the if signal . then , the devision circuit 21 is controlled by the first control signal and outputs the frequency shift count signal to the first subtraction circuit 4 . therefore , after the frequency shift count signal is input to the first subtraction circuit 4 , the compensation signal obtained by subtracting the amount of the frequency shift caused by the qpsk modulation from the frequency of the if signal is input to the fourth subtraction circuit 30 composing the second frequency compensation circuit 6 . the detailed explanation will not be given as to the frequency shift count signal and the compensation signal which is obtained by subtracting the amount of the frequency shift caused by the qpsk modulation . as for the frequency of the if signal measured by the frequency measurement counter circuit 8 for one second , the value of the frequency shift obtained by the qpsk modulation corresponds to the value of the integration signal , and the frequency shift count signal divided by the value of this integration signal corresponds to a mean value of the values which are subjected to the frequency shift with one transmit signal , i . e ., one symbol . since the scrambling is performed on the transmit signal , the integration signal can not have a considerably large value . namely , for example , even when the qpsk modulation is continuously performed ten times with the symbol 00 , the frequency may not be shifted by and the maximum amount of the frequency shift may be a small value of approximately 2 . 625 khz corresponding to 1 / 8π symbol . meanwhile , the measurement of the frequency of the if signal for one second by the frequency measuring counter circuit 8 means that the frequency of the if signal output for one second is integrated and the value obtained by counting the frequency corresponding to one symbol of the received signal , i . e ., the frequency of the if signal in the frequency measuring counter circuit 8 during is output as the frequency count signal . accordingly , the compensation signal obtained by subtracting the frequency shift count signal from the frequency count signal means a signal obtained by subtracting the amount of the shift of the frequency of the if signal which is produced with one symbol of the transmit signal from the frequency count signal . therefore , a desired frequency of the if signal can be obtained by subjecting the compensation signal which is obtained by subtracting the frequency shift count signal from the frequency count signal to a prior art afc circuit . the subsequent operation will be explained hereinunder . the compensation signal obtained by subtraction of the amount of the frequency shift due to the qpsk modulation is input to the second subtraction circuit 26 constituting the convergence judgement circuit 7 and the fourth subtraction circuit 3 composing the second frequency compensation circuit 6 , respectively . as described above , the convergence judgement circuit 7 outputs the high level signal until the second frequency shift signal belongs to the second frequency shift allowance signal and so controls as to input the switch signal to the retention circuit 9 via the switch circuit 11 . on the other hand , the second frequency compensation control circuit 6 also adds the step width signal to the compensation signal every time when the compensation signal is input thereto and repeatedly compensates the deviation of the frequency of the reference frequency signal caused by the temperature change , as described above . the compensation signal obtained by subtraction of the amount of the frequency shift due to the qpsk modulation is compensated step by step by adding the step width signal thereto in the second frequency compensation circuit 9 , and the frequency of the reference frequency signal is also compensated step by step . consequently , the frequency of the if signal is also converged on a desired frequency gradually . the above - described compensation is repeated , and the second comparison circuit 27 constituting the convergence judgement circuit 7 outputs the convergence completion signal which is a low level signal when the second frequency shift signal belongs to the second frequency allowance signal . when this convergence completion signal is output , the switch circuit 11 is opened , and the input of the clock signal to the retention circuit is interrupted . at this time , the renewal of the retention signal retained in the retention circuit 9 is stopped , and the convergence is completed , namely , the desired frequency of the if signal is output . thereafter , the frequency of the reference frequency signal is output in accordance with the retention signal retained in the retention circuit 9 at the time of the convergence completion , and the if signal having the desired frequency is constantly output . obviously , numerous additional modifications and variations of the present invention are possible in light of the above teachings . it is , therefore , to be understood that within the scope of the appended claims , the invention may be practiced otherwise than as specifically described herein .