the following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention . as used herein , the word “ exemplary ” means “ serving as an example , instance , or illustration .” thus , any embodiment described herein as “ exemplary ” is not necessarily to be construed as preferred or advantageous over other embodiments . all of the embodiments described herein are exemplary embodiments provided to enable persons skilled in the art to make or use the invention and not to limit the scope of the invention which is defined by the claims . furthermore , there is no intention to be bound by any expressed or implied theory presented in the preceding technical field , background , brief summary , or the following detailed description . in this regard , although embodiments are described herein as being implemented in a rotary - wing aircraft , such as a helicopter , it will be appreciated that the systems and methods described herein may be implemented in various other environments and applications that utilize a multi - engine output . moreover , although embodiments are described herein as being implemented with two gas turbine engines , other numbers of engines greater than two could be used , and various other engine types , including diesel and combustion engines , may also be used . referring first to fig1 , a functional block diagram of a portion of a multi - engine power train system 100 for a rotary - wing aircraft , such as a helicopter , is depicted . the power train includes two engines 102 ( a first engine 102 - 1 and a second engine 102 - 2 ), a gear train 104 , and two engine controllers 106 ( a first engine controller 106 - 1 and a second engine controller 106 - 2 ). it should be noted that although the system 100 of fig1 is depicted as including only two engines 102 , it could be implemented with more than this number of engines 102 , if needed or desired . the engines 102 , at least in the depicted embodiment , are implemented using gas turbine engines , and more particularly single - spool turbo - shaft gas turbine propulsion engines . thus , each engine 102 includes a compressor section 108 , a combustion section 112 , and a turbine section 114 . the compressor section 108 , which may include one or more compressors 116 , draw air into its respective engine 100 and compresses the air to raise its pressure . in the depicted embodiment , each engine includes only a single compressor 116 . it will nonetheless be appreciated that each engine 102 may include one or more additional compressors . no matter the particular number of compressors 116 that are included in the compressor sections 108 , the compressed air is directed into the combustion section 112 . in the combustion section 112 , which includes a combustor assembly 118 , the compressed air is mixed with fuel supplied from a non - illustrated fuel source . the fuel and air mixture is combusted , and the high energy combusted air mixture is then directed into the turbine section 114 . the turbine section 114 includes one or more turbines . in the depicted embodiment , the turbine section 114 includes two turbines , a high pressure turbine 122 and a free power turbine 124 . however , it will be appreciated that the engines 102 could be configured with more or less than this number of turbines . no matter the particular number , the combusted air mixture from the combustion section 112 expands through each turbine 122 , 124 , causing it to rotate an associated power shaft 126 . the combusted air mixture is then exhausted from the engines 102 . the power shafts 126 are each coupled to , and supply a drive torque to , the gear train 104 . the gear train 104 is coupled to receive the drive torque supplied from each of the engines 102 . the gear train 104 , which may include one or more gear sets , preferably includes at least a combiner transmission , which in turn supplies the combined drive torque to one or more rotors . the engine controllers 106 are each in operable communication with one of the engines 102 . in the depicted embodiment , for example , the first engine controller 106 - 1 is in operable communication with the first engine 102 - 1 , and the second engine controller 106 - 2 is in operable communication with the second engine 106 - 2 . each engine controller 106 is configured , among other things , to control the operation of its associated engine 102 so as to minimize the performance margin difference between the engines 102 . to implement this functionality , the engine controllers 106 are each coupled to receive various control and performance data from its associated engine 102 . thus , as fig1 further depicts , each engine 102 additionally includes a plurality of sensors 128 . each of the sensors 128 is coupled to its associated engine controller 106 and is operable to sense an engine parameter and supply control and performance data representative of the sensed parameter to the engine controller 106 . it will be appreciated that the particular number , type , and location of each sensor 128 may vary . it will additionally be appreciated that the number and types of control and performance data supplied by the sensors 128 may vary depending , for example , on the particular engine type and / or configuration . in the depicted embodiment , however , at least a subset of the depicted sensors 128 supply control and performance data representative of , or that may be used to determine , engine inlet pressure , engine inlet temperature , engine speed , fuel flow , compressor discharge pressure , power turbine inlet temperature , engine torque , shaft horsepower , and thrust , to name just a few . the engine controllers 106 may be variously configured to implement the associated functionality . in the depicted embodiment , each engine controller 106 includes one or more processors 132 ( for clarity , only one shown ). the processors 132 are coupled to receive at least a portion of the control and performance data from the sensors 128 and are each configured , in response to these data , to continuously conduct performance analyses of its associated engine 102 . moreover , each engine controller 106 also receives various sensor data , such as torque , turbine inlet temperature , and engine speed , from the other engine controller 106 via a data link 134 that interconnects the two engine controllers 106 . the processors 132 are additionally configured , based on the performance analyses , to control the operation of its associated engine 102 to minimize the difference between the performance margins of each engine 102 . to do so , the processors 132 are each configured to conduct continuous , real - time performance analyses of its associated engine 102 to thereby continuously determine , in real - time , the performance margin of its associated engine 102 . the processors 132 are additionally configured to implement identical feedback controllers that will shift the load between the engines 102 so that there is more load on the engine 102 with higher performance margin . one embodiment of the feedback controllers 200 are implemented in each of the processors 132 is depicted in fig2 , and will now be described in more detail . before proceeding with the description , it is noted that the feedback controller 200 depicted in fig2 is the one implemented in the first engine controller 106 - 1 , and is thus associated with the first engine 102 - 1 ( e . g ., “ engine 1 ”). it will be appreciated that the feedback controller 200 implemented in the second engine controller 106 - 2 , and thus associated with the second engine ( e . g ., “ engine 2 ”) is an identical , “ mirror - image ,” copy of the one implemented in the first engine controller 106 - 1 . it is additionally noted that although the depicted feedback controller 200 is configured to implement a torque matching function , various other load matching functions may be implemented . for example , the feedback controller 200 may be configured to implement a load matching function based on temperature or speed , just to name a few . turning now to the description of the feedback controller 200 , it is seen that the feedback controller 200 receives the control and performance data supplied by the sensors 128 . the control and performance data are supplied , at least in the depicted embodiment , to signal conditioning and bit ( built - in - test ) logic , which provides appropriate signal conditioning and testing of the data supplied from the sensors 128 . at least a portion of the control and performance data are supplied to and processed by a continuous performance analysis ( cpa ) function 202 - 1 . the cpa function 202 - 1 is configured to conduct continuous , real - time performance analyses of the first engine 102 - 1 , and supply data representative of the instantaneous performance margin of the first engine 102 - 1 . as fig2 also depicts , the feedback controller 200 also receives , from a cpa function 202 - 2 in the feedback controller 200 of the second engine controller 106 - 2 , data representative of the instantaneous performance margin of the second engine 102 - 2 . before proceeding further , it is additionally noted that the continuous , real - time performance analyses conducted by the cpa functions 202 may be implemented using any suitable algorithm capable of supplying instantaneous performance margins . preferably , however , the continuous , real - time performance analyses are preferably conducted using the methodology described in u . s . pat . no . 8 , 068 , 997 , entitled “ continuous performance analysis system and method ,” and assigned to the assignee of the instant application . the entirety of this patent , which issued on nov . 29 , 2011 , is hereby incorporated by reference . returning now to the description of the feedback controller 200 , the instantaneous performance margins of each engine ( mrg1 , mrg2 ) are supplied to a first difference function 204 . the first difference function 204 determines a performance margin difference ( mrg_diff ) between the two engines 102 , and supplies the determined performance margin difference ( mrg_diff ) to a margin matching control function 206 . the margin matching control function 206 is configured , in response to the performance margin difference ( mrg_diff ), to generate and supply a torque bias signal ( q_bias ). though not depicted in fig2 , it should be noted that the instantaneous performance margins supplied from the cpa functions 202 - 1 , 202 - 2 may be filtered to remove noise . if not adequately filtered , noise in the instantaneous performance margins can cause undesirable swings in the torque bias signal ( q_bias ). it will be appreciated that the margin matching control function 206 may be implemented using any one of numerous types of controllers . in a particular preferred embodiment , the margin matching control function 206 is implemented as a proportion - plus - integral ( pid ) controller . this is because the proportional action provides relatively fast and measured correction , the integral action eliminates any steady state error of synchronization , and the derivative action provides anticipatory correction to avoid overshoot and hunting issues . no matter how the margin matching control function 206 is implemented , the torque bias signal ( q_bias ), at least in the depicted embodiment , is supplied to a limiter 208 . the limiter 208 , as is generally known , is configured to limit the torque bias signal supplied from the margin matching control function 206 . in particular , it is configured to limit the torque bias signal to less than the maximum allowable torque split between the first and second engines 102 - 1 , 102 - 2 . the limit values may vary , but are preferably chosen to limit stress to the gear train 104 . the limited torque bias signal ( q_bias_lmt ) is supplied to a second difference function 212 . the second difference function 212 is coupled to receive , in addition to the limited torque bias signal ( q_bias_lmt ), a torque matching error signal ( q_err ). the torque matching error signal ( q_err ) is supplied from a third difference function 214 , which receives , and determines the difference between , a first engine torque signal 216 and a second engine torque signal 218 . the determined difference is supplied as the torque matching error signal ( q_err ). as may be appreciated , the first engine torque signal 216 is a signal representative of the instantaneous torque ( q1 ) being supplied by the first engine 102 - 1 , and the second engine torque signal 218 is a signal , supplied from the second engine controller 106 - 2 , representative of the instantaneous torque ( q2 ) being supplied by the second engine 102 - 2 . the output of the second difference function 212 is supplied to a torque matching function 222 . the torque matching function 222 is preferably configured to implement a conventionally known torque matching algorithm . it will be appreciated , however , that any one of numerous torque matching algorithms developed in the future could also be used . the torque matching function 222 supplies a speed control signal to the speed governor 224 in the first engine 102 - 1 , which in turn supplies a fuel control signal to a fuel control function 226 . the fuel control function 226 , which is implemented in the first engine controller 106 - 1 , supplies appropriate commands to appropriate control devices to meter an appropriate amount of fuel to the first engine 102 - 1 . from the above description it may be readily understood that when there is a non - zero performance margin difference between the first and second engines 102 - 1 , 102 - 2 , the feedback controllers 200 use the determined performance margin difference ( mrg_diff ) to purposely create , within acceptable torque split limits , a load imbalance . the feedback controllers 200 are also configured to indirectly control load shifting via the torque matching function 222 . in particular , the feedback controllers 200 supply the limited torque bias signal ( q_bias_lmt ) to the torque matching error signal ( q_err ) such that both engines will settle into a desirable unbalanced load condition as long as performance margin difference exists between the two engines 102 . for completeness , a brief description of the operation of the system 100 implementing the feedback controllers 200 will be provided . initially , it is assumed that the instantaneous performance margins ( mrg1 , mrg2 ) of the first and second engines 102 - 1 , 102 - 2 are equal ( or at least substantially equal ). such a situation may occur , for example , when both engines 102 are new . as a result , the performance margin difference ( mrg_diff ) will be zero and the limited torque bias signal ( q_bias_lmt ) supplied to the second difference function 212 will also be zero . this will result in the first and second engines 102 - 1 , 102 - 2 being controlled in accordance with a conventional torque matching control loop . if any divergence in the performance margins ( mrg1 , mrg2 ) of the first and second engines 102 - 1 , 102 - 2 occurs , the feedback controllers 200 will implement immediate corrective action to drive the performance margin difference ( mrg_diff ) to zero in closed - loop fashion . for example , as graphically depicted in fig3 , the performance margin ( mrg2 ) of the second engine 102 - 2 has decreased faster and becomes smaller relative to the performance margin ( mrg1 ) of the first engine 102 - 1 . as a result , the performance margin difference ( mrg_diff ) will be non - zero and the limited torque bias signal ( q_bias_lmt ) supplied to the second difference function 212 will also be non - zero . more specifically , the margin matching control function 206 associated with the first engine 102 - 1 , which has the higher performance margin , will supply a positive value for the torque bias signal ( q_bias ) and the limited torque bias signal ( q_bias_lmt ), such that it will reduce the torque error value ( q_err ) before it is used in the torque matching function 222 . this operation has an equivalent effect of lowering the torque signal value of the first engine and thus causes the torque matching function 222 to increase the power and load share of the first engine 102 - 1 . the opposite will occur in the feedback controller 200 associated with the second engine 102 - 2 , which has the lower performance margin . thus , a desirable torque split condition is purposely created as a result of the power imbalance of the first and second engines 102 . because the first engine 102 - 1 ( the higher performance margin engine ) now has a greater power usage than the second engine 102 - 2 ( the lower performance margin engine ), the first engine 102 - 1 will degrade faster than the second engine 102 - 2 . as fig4 depicts , over time this will result in the performance margin differences of the two engines 102 converging to zero ( e . g ., mrg1 = mrg2 ). once the performance margins are matched , the feedback controllers 200 will continue to keep them matched until both engines 102 are fully degraded . it should be noted that in some contexts , such as certain helicopter engine control systems , even though the engine with lower performance margin will bias its associated torque signal to a higher value , it will not decrease the engine power directly . this is because the torque matching control loops in some helicopter do not allow lowering the power of the high torque signal engine . thus , the increased power to the engine with the higher performance margin will result in the speeds of both engines increasing , and further result in a power reduction from the speed governor of the lower performance margin engine . it is generally known that various parameters can be used as a measure of performance margin . for example , in the context of gas turbine engines , turbine inlet temperature and turbine speed can be used . although multiple performance margin types could be used in the feedback controllers 200 , it is preferable to choose one margin type for synchronization , rather than switching among a plurality of different margin types . different types of performance margins ( e . g ., temperature margin , speed margin , etc .) typically move in the same direction . thus , if one performance margin type is in synch , then the other types are likely to be in synch ( or at least closely in sync ). moreover , it is preferable to choose the performance margin type that reaches its performance limit more frequently and / or cause more engine removals . in the context of a helicopter , the turbine inlet temperature margin is typically chosen because it meets these criteria . the system and method described herein provides numerous significant benefits for various multi - engine systems , such as multi - engine helicopters . in particular , the system and method provides reduced maintenance cost , reduced pilot workload , increased engine life , and increased aircraft availability . maintenance costs can be reduced since the removal of engines with small performance margins , which are often removed along with fully degraded engines , can be avoided , and because only a single maintenance test flight is needed after engine replacements . pilot workload is reduced since the pilot does not need to manually switch from one load sharing method to another in order to get maximum power from both engines when one engine reaches a performance limit before the other . engine life is increased since two engines with matched performance margins will experience lower maximum temperature and speed during transients than unmatched engines over their life span . as a result , the rate of damage to hot section life - limited components , which accelerates at higher engine speed and temperature , will be reduced . moreover , the rate of performance degradation , which also accelerates at higher engine speed and temperature , is reduced due to slower surface oxidation or blade tip deformation . aircraft availability is increased since aircraft downtime for fully degraded engine removal and replacement is reduced by 50 percent , since two maintenance events are reduced to just one . those of skill in the art will appreciate that the various illustrative logical blocks , modules , circuits , and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware , computer software , or combinations of both . some of the embodiments and implementations are described above in terms of functional and / or logical block components ( or modules ) and various processing steps . however , it should be appreciated that such block components ( or modules ) may be realized by any number of hardware , software , and / or firmware components configured to perform the specified functions . to clearly illustrate this interchangeability of hardware and software , various illustrative components , blocks , modules , circuits , and steps have been described above generally in terms of their functionality . whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system . skilled artisans may implement the described functionality in varying ways for each particular application , but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention . for example , an embodiment of a system or a component may employ various integrated circuit components , e . g ., memory elements , digital signal processing elements , logic elements , look - up tables , or the like , which may carry out a variety of functions under the control of one or more microprocessors or other control devices . in addition , those skilled in the art will appreciate that embodiments described herein are merely exemplary implementations . the various illustrative logical blocks , modules , and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor , a digital signal processor ( dsp ), an application specific integrated circuit ( asic ), a field programmable gate array ( fpga ) or other programmable logic device , discrete gate or transistor logic , discrete hardware components , or any combination thereof designed to perform the functions described herein . a general - purpose processor may be a microprocessor , but in the alternative , the processor may be any conventional processor , controller , microcontroller , or state machine . a processor may also be implemented as a combination of computing devices , e . g ., a combination of a dsp and a microprocessor , a plurality of microprocessors , one or more microprocessors in conjunction with a dsp core , or any other such configuration . the steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware , in a software module executed by a processor , or in a combination of the two . a software module may reside in ram memory , flash memory , rom memory , eprom memory , eeprom memory , registers , hard disk , a removable disk , a cd - rom , or any other form of storage medium known in the art . an exemplary storage medium is coupled to the processor such that the processor can read information from , and write information to , the storage medium . in the alternative , the storage medium may be integral to the processor . the processor and the storage medium may reside in an asic . the asic may reside in a user terminal . in the alternative , the processor and the storage medium may reside as discrete components in a user terminal . in this document , relational terms such as first and second , and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions . numerical ordinals such as “ first ,” “ second ,” “ third ,” etc . simply denote different singles of a plurality and do not imply any order or sequence unless specifically defined by the claim language . the sequence of the text in any of the claims does not imply that process steps must be performed in a temporal or logical order according to such sequence unless it is specifically defined by the language of the claim . the process steps may be interchanged in any order without departing from the scope of the invention as long as such an interchange does not contradict the claim language and is not logically nonsensical . furthermore , depending on the context , words such as “ connect ” or “ coupled to ” used in describing a relationship between different elements do not imply that a direct physical connection must be made between these elements . for example , two elements may be connected to each other physically , electronically , logically , or in any other manner , through one or more additional elements . while at least one exemplary embodiment has been presented in the foregoing detailed description of the invention , it should be appreciated that a vast number of variations exist . it should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples , and are not intended to limit the scope , applicability , or configuration of the invention in any way . rather , the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention . it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims .