fig1 shows the circuit construction of a memory element in which the degradation of the saturation current of a transistor is utilized for storing data . the memory element has a first memory cell group 101 ( illustrated in dotted fashion ), which in each case has a first memory cell 103 ( illustrated in dashed fashion ) with a first signal connection 105 and a second memory cell 104 ( illustrated in dashed fashion ) with a second signal connection 107 . a second memory cell group 102 is illustrated as a circuit block with a first signal connection 106 and a second signal connection 108 . its internal construction is equivalent to that of the memory cell group 101 . it is possible to provide as many additional further memory cell groups as desired in each case having any desired number of transistors in the memory cells . the first memory cell 103 and the second memory cell 104 respectively comprise a plurality of transistors 110 , 111 , 112 and 113 , 114 , 115 , the source - drain paths of which are connected in series . a respective signal path via the series circuit of this source - drain path in the first memory cell 103 or in the second memory cell 104 connects the first signal connection 105 to a control connection 125 . the gate terminals of the transistors 110 , 111 , 112 and 113 , 114 , 115 receive an access control signal from an access control output of a decoder 109 via a cell selection line . in this case , the memory cell group 101 , 102 is assigned a respective access control output of the decoder 109 . the decoder 109 additionally has a first input for an activation signal 116 and a parallel input for address signal 117 . a data input 118 for a data signal to be stored is connected via an inverter 119 to the input of a first tristate driver 120 and directly to the input of a second tristate driver 121 . the first tristate driver 120 and the second tristate driver 121 are inhibited or opened by means of a state control signal provided at a respective inhibiting input . the state control signal is introduced into the switching element via a state control input 122 and likewise passed to the gate terminal of a first pmos transistor 123 and to the gate terminal of a second pmos transistor 124 and also to the control connection 125 . a respective source terminal of the pmos transistors 123 , 124 is fed with an applied voltage v dd from a constant - voltage source 126 . a first data line 127 connects an output of the first tristate driver 120 to a drain terminal of the first pmos transistor 123 , to the first signal connection 105 , 106 and to a first voltage input of a differential amplifier 129 . a second data line 128 connects an output of the second tristate driver 121 to a drain terminal of the second pmos transistor 124 , to the second signal connection 107 , 108 and to a second voltage input of the differential amplifier 129 . an output data signal is provided at a voltage output 130 of the differential amplifier 129 , and is passed to a signal input of a multiplexer 131 . the multiplexer 131 has two signal outputs that are respectively connected to a data input of two registers 132 , 133 set up as d - type flip - flops . the output data signal provided at the signal input of the multiplexer 131 is switched in a manner dependent on activation signals input at the control input of the multiplexer 131 . the control inputs are respectively connected to an access control signal output of the decoder 109 . the method of operation of the memory element illustrated in fig1 is based on particular properties of mosfet transistors . the latter are subject to a degradation of the saturation current in the course of their operation . the degradation is particularly pronounced if the electric current when writing to the memory element has a different direction or a different sign than the electric current which flows through the memory cell in reading out a stored datum . this phenomenon is connected with the asymmetrical damage of the transistor in the drain region thereof . the effect is additionally amplified by means of the series circuit of the transistors 110 , 111 , 112 and 113 , 114 , 115 in the first memory cell 103 and in the second memory cell 104 , respectively , as illustrated in fig1 . in the present embodiment , each memory cell 103 , 104 comprises three transistors 110 , 111 , 112 and 113 , 114 , 115 , respectively . it is equally possible to use more or fewer transistors per memory cell 103 , 104 . the first memory cell 103 and the second memory cell 104 increase the sensitivity of the system . the data stored in the memory cells 103 , 104 are evaluated differentially by means of the differential amplifier 129 . the cell selection lines are driven by the decoder 109 , which , on the basis of an address information item of the address signal 117 sets an access control signal on one of the cell selection lines to the value logic “ 1 ”, provided that the activation signal 116 likewise has a value logic “ 1 ”. for a better understanding it is assumed below that the value logic “ 1 ” corresponds to a potential v dd and the value logic “ 0 ” corresponds to a zero potential . a voltage pulse shall additionally be defined below for a simpler representation . in this case , a 0 - 1 - 0 pulse is a temporal pulse in which , on an electrical connection , firstly a zero potential is present , which is switched over to the voltage v dd during a specific time duration . correspondingly , a 1 - 0 - 1 pulse on an electrical connection is an applied potential v dd which is switched over to a zero potential during a specific time duration . the time duration and thus the length of the pulse result from the effect respectively desired and may have a different length . by virtue of the potential present on the cell selection line , there are present in a memory cell group 101 , 102 , at the gate terminals of the transistors 110 , 111 , 112 and 113 , 114 , 115 , respectively , in each case such large electrical potentials that the charge carrier channels of the respective source - drain paths are open . a current can thus flow through them . the respective memory cell group 101 , 102 is thus activated . at the same time , on account of the access control signal , the multiplexer 131 switches the signal path from the voltage output 130 to a register 132 , 133 assigned to the memory cell group 101 , 102 . in order to write to a memory cell group 101 , 102 , the latter is selected by means of the address signal 117 . the data signal to be stored is provided at the data input 118 . a switching state is established by the state control signal being set to the value logic “ 1 ”. as a result , the first tristate driver 120 and second tristate driver 121 are activated and the first pmos transistor 123 and the second pmos transistor 123 are turned off . the data input 118 is thus connected to the first signal connection 105 , 106 and the second signal connection 107 , 108 . the complement of the data signal to be stored is present at a first signal connection 105 , 106 , while the value of the data signal to be stored is present at the second signal connection 107 , 108 . the value logic “ 1 ” is present in the channel connection 125 . in order to impress the datum to be stored into the memory cell group 101 , 102 a 0 - 1 - 0 pulse is provided as activation signal 116 . as a result , the memory cell group 101 , 102 is activated and a current flows through the first memory cell 103 or through the second memory cell 104 , which current degrades the saturation current of the transistors 110 , 111 , 112 or 113 , 114 , 115 , respectively . the length of the 0 - 1 - 0 pulse of the activation signal 116 is chosen correspondingly in order to achieve a measurable degradation . in order to read out a datum from a memory cell group 101 , 102 , the latter is likewise selected by means of the address signal 117 . a read state is established by the state control signal being set to the value logic “ 0 ”. as a result , the two tristate drivers 120 , 121 are inhibited , while the first pmos transistor 123 and second pmos transistor 124 are open . the value logic “ 1 ” is present at the first signal connection 105 , 106 and also at the second signal connection 107 , 108 , while the value logic “ 0 ” is present at the channel connection 125 . if the activation signal then obtains a value logic “ 1 ”, the gate terminals of the transistors 110 , 111 , 112 and 113 , 114 , 115 of the first memory cell 103 and of the second memory cell 104 , respectively , in the selected memory cell group 101 , 102 are open . a current can flow , limited by the saturation current . in accordance with the respective saturation current and the thereby afforded conductivity of the first memory cell 103 and of the second memory cell 104 , the voltage is dropped across the first signal connection 105 , 106 and the second signal connection 107 , 108 . a voltage difference between the first signal connection 105 , 106 and the second signal connection 107 , 108 is detected by means of the differential amplifier 129 and stored as a value in one of the registers 132 , 133 via the multiplexer 131 . as long as the registers 132 , 133 are supplied with a supply voltage , the datum stored from the memory cell group 101 , 102 can be provided by the register 132 , 133 . fig2 illustrates a second embodiment of the memory element , which differs from fig1 by the use of a read amplifier 201 ( illustrated in dotted fashion ). the memory cell groups 101 , 102 are constructed as in fig1 and are likewise activated via an access control output of a decoder 109 . fig2 likewise differs from fig1 in that the tristate drivers 120 , 121 are activated by a tristate control signal 202 . by contrast , the control connection 125 is connected to a control input 200 . the first signal connection 105 , 106 is connected to a line 127 of the read amplifier 201 and the second signal connection 107 , 108 is connected to the second line 128 of the read amplifier 201 . the potentials on the first line 127 and the second line 128 can be equalized by means of a transistor 203 . for this purpose , the transistor 203 is switched or turned off via an equalization signal input 204 . furthermore , the first line 127 and the second line 128 are coupled to one another via an nmos latch 210 ( illustrated in dashed fashion ) and a pmos latch 220 ( illustrated in dashed fashion ). the read amplifier 201 provides the stored datum and the complement with respect thereto at a first output 205 and at the second output 206 , respectively . the nmos latch 210 has a feedback transistor stage comprising two nmos transistors 211 , 212 . in this case , the gate terminal of a respective one of the nmos transistors 211 , 212 is connected to the source terminals of the respective other nmos transistor 211 , 212 . the source terminal of one nmos transistor 211 is connected to the first line 127 , while the source terminal of the other nmos transistor 212 is connected to the second line 128 . the drain terminals of the two nmos transistors 211 , 212 are coupled to a switching transistor 213 , which connects them through to a zero potential in a manner dependent on a voltage signal at a first supply input 214 . the pmos latch 220 is constructed analogously from a feedback transistor stage comprising two pmos transistors 221 , 222 . the source terminals thereof are coupled to a supply voltage v dd via the source - drain path of a further switching transistor 223 . the further switching transistor 223 switches in a manner dependent on a voltage signal provided to it at a second supply input 224 by means of an inverter 225 . fig3 shows the performance of a writing and reading operation in a memory element in accordance with the embodiment in fig2 . during the writing operation , firstly the signal at the control input 200 is set to the value logic “ 1 ”. the value logic “ 0 ” is present at the first supply input 214 and the second supply input 224 and also at the equalization signal input 204 . the read amplifier 201 is thus not activated . a memory cell group 101 , 102 is written to by being selected by means of an address signal 117 and being activated by the activation signal 116 by means of a 0 - 1 - 0 pulse . at the same time , the tristate drivers 120 , 121 are momentarily opened by a 1 - 0 - 1 pulse of the tristate control signal 202 , so that a potential corresponding to the value of the datum present at the data input 118 and to its complement , respectively , is present at the first signal connection 105 , 106 and at the second signal connection 107 , 108 . during the writing operation , the datum and the complement thereof are impressed into the selected memory cell group 101 , 102 by means of an irreversible change in the saturation currents of the transistors 110 , 111 , 112 and 113 , 114 , 115 , respectively . in order to read out the datum contained in a memory cell group 101 , 102 , the said datum is selected by means of the address signal 117 . the potential at the control input 200 is set to the value logic “ 0 ”. a potential having the value logic “ 0 ” is initially present at the first supply input 214 and the second supply input 224 as well as at the equalization signal input 204 . an arbitrary signal having a valid value logic “ 0 ” or logic “ 1 ” is provided at the data input . by means of a 1 - 0 - 1 pulse of the tristate control signal 202 , the first line 127 and the second line 128 are occupied by a value 0 and 1 , respectively , by a conductive connection to the data input being momentarily produced . the potentials of the first line 127 and the second line 128 are then equalized by means of a 0 - 1 - 0 pulse at the equalization signal input 204 , so that a potential v dd / 2 is present on both . afterwards , the datum stored in the selected memory cell group 101 , 102 is read out by a 0 - 1 - 0 pulse simultaneously being provided at the activation input 116 and also at the first supply input 214 and at the second supply input 224 . fig4 shows the circuit construction of a memory element having severable fuses . the circuit differs from fig1 in a different embodiment of the first memory cells 103 and of the second memory cell 104 and also in that the control connection 125 is set to a zero potential . the first memory cell 103 and the second memory cell 104 respectively comprise an activation transistor 403 , 404 , the source - drain path of which couples the first and second signal connection 105 , 106 , 107 , 108 , respectively , to a thin interconnect ( fuse ) 401 , 402 . the gate terminals of the activation transistors 403 , 404 are connected to the access control output of the decoder 109 . a writing and reading operation is effected in accordance with the sequence described in fig1 . a current flowing through the thin interconnect 401 , 402 destroys the latter and thus its conductivity . a possible healing of the severing of the thin interconnect 401 , 402 is insignificant due to the differential construction of the memory element , since the datum stored in the memory element is determined from the comparison of the first partial - datum with the second partial datum .