fig1 is a block diagram showing a preferred embodiment of the present invention a configurable 8k × 9 static random access memory ( sram ) 10 . in this embodiment , sram 10 includes input address buffers 12 , x decode circuitry 14 , y decode circuitry 16 , a pair of memory arrays 18 , pull - up circuitry 20 , fuse structures 22 , sense amplifiers 24 , and input / output ( i / o ) buffers 26 . each memory array 18 includes sixteen memory blocks 28 each containing 256 × 9 memory cells . address lines a1 - a13 provide a thirteen bit address to input address buffers 12 . the first eight address bits ( from lines a1 - a8 ) represent the x address , and are used to select one of the memory rows for reading or writing the remaining five bits ( from lines a9 - a13 ) represent the y address , and select the appropriate bank of memory columns and the corresponding sense amplifiers 24 . x decode circuit 14 and y decode circuit 16 decode the address received on lines a1 - a13 and enable a byte of nine ( or eight ) bits of memory to be selected depending on the particular binary address which is supplied . during a read operation , those nine ( or eight ) bits are interrogated for a logical &# 34 ; 1 &# 34 ; or &# 34 ; 0 &# 34 ; by the sense amplifiers 24 , and the outputs of the sense amplifiers are provided to i / o buffers 26 . the nine - bit output is supplied by i / o buffers 26 on data lines d1 - d9 . if sram 10 has been reconfigured to an 8k × 8 device ( due to defective memory cells within memory blocks 28 ) the eight - bit byte is supplied by i / o buffers 26 on data lines d1 - d8 . similarly , during a write operation the nine ( or eight ) bits of memory receive and store a nine ( or eight ) bit word received from i / o buffers 26 . fig2 is a block diagram of two 256 × 9 memory blocks 28 and 28 &# 39 ;. address lines a1 - a8 apply the first eight address signals to x decode circuitry 14 . x decode circuitry 14 applies select signals to memory blocks 28 and 28 &# 39 ;, and particularly to columns of memory cells 30 . the select signals from x decode circuitry 14 select one nine - bit ( or eight - bit ) byte of information from each memory block 28 and 28 &# 39 ; for a read or write operation . the nine bit ( or eight - bit ) byte of information is made up of one cell from each of the nine columns of memory cells 30 in memory blocks 28 and 28 &# 39 ;. the bit and bit lines of the columns of memory cells 30 are connected to the sense amplifiers 24 through the fuse structures 22 . during a read operation , the sense amplifiers 24 detect a logical &# 34 ; 1 &# 34 ; or &# 34 ; 0 &# 34 ; stored in the selected cells of columns of memory cells 30 which make up the nine bit ( or eight - bit ) byte of information from memory blocks 28 or 28 &# 39 ;. during a write operation , the bits to be written flow from i / o buffers 26 to data bus 32 and through the sense amplifiers 24 to the desired bit and bit lines . the last five address bits are applied to y decode circuitry 16 on lines a9 - a13 . y decode circuitry 16 provides select signals to the sense amplifiers 24 associated with memory blocks 28 and 28 &# 39 ;. when a set of sense amplifiers is selected , the information derived from the corresponding nine bit ( or eight - bit ) byte of information ( logical 1 &# 39 ; s or 0 &# 39 ; s ) is supplied to data bus 32 from sense amplifiers 24 , or vice versa . during a read operation , data bus 32 applies the information derived from sense amplifiers 24 to i / o buffers 26 . the nine - bit ( or eight - bit ) output is supplied by i / o buffers 26 on data lines d1 - d9 . during a write operation , data flows in the opposite direction from data lines d1 - d9 to memory blocks 28 , 28 &# 39 ;. fig2 a is a block diagram which shows a more detailed depiction of a single column of memory cells 30 corresponding to one of the memory blocks 28 or 28 &# 39 ; shown in fig2 . the column of memory cells 30 is broken up into individual cells 34 each of which stores a single bit of information ( a logical 1 or 0 ). fig3 shows a block diagram of a defective 8k × 9 sram which has been reconfigured to form an 8k × 8 sram . in this block diagram , defective memory cells were found , through testing , in columns of memory cells 36 and 38 ; therefore , columns of memory cells 36 and 38 must be made effectively invisible to the user during operation of sram 10 . this is accomplished by reconfiguring the outputs of the remaining columns of memory cells 30 through fuse structures 22 . as shown , the bit and bit lines of defective columns 36 and 38 of memory cells are effectively decoupled from their corresponding sense amplifiers 24 . also , the outputs of the columns of memory cells 30 located to the right of defective columns 36 and 38 , in memory blocks 28 and 28 &# 39 ; respectively , are effectively shifted to the left one place along sense amplifiers 24 . the output of the sense amplifier located on the far right of each memory block 28 and 28 &# 39 ;, respectively , becomes fixed in a known state . hence , data bus 32 effectively becomes an eight bit data bus and data line d9 becomes unused . shifting the outputs of columns of memory cells 30 does not change the operation of sram with respect to data flow during reading and writing . however , only an eight bit byte of information is read from or written to each block of memory . therefore , sram 10 has now been reconfigured to function as an 8k × 8 sram . fig4 a shows one embodiment of fuse structures 22 used to accomplish reconfiguration . in this embodiment , fuse structures 22 are made up of a decoupling means 40 and a shifting means 42 . when a defective cell is found , the decoupling means is used to decouple the column of memory cells containing the defective cell and the shifting means is used to shift the outputs of the remaining columns of memory cells , which lie to the right of the defective column , to the left one place along sense amplifiers 24 . for example , if bit two corresponds to the column of memory cells containing the defective cell , fuses 44 , 46 and 48 would be blown using a laser means ( not shown ) breaking the connection of the bit and bit lines of the column of memory cells associated with bits two , three and four from the sense amplifiers . shifting means 42 then operates to shift the bit and bit lines of columns of memory cells associated with bits three and four to the left one place . this is done by blowing fuse 50 with a laser means resulting in the switching on of shifting transistors 52 , 54 and 56 . with these transistors conducting , bits three and four are effectively shifted to the left one place along sense amplifiers 24 , and the lines located on the far right of fuse structures 22 become fixed in a known state . fig4 b shows a second embodiment of fuse structures 22 used to accomplish reconfiguration . similar to that shown in fig4 a , this embodiment is comprised of decoupling means 40 and shifting means 42 . if , as in the example discussed above , bit two is associated with the defective column of memory cells , fuse 58 is blown , using laser means , resulting in the switching off of decoupling transistors 60 , 62 and 64 . with the decoupling transistors in the nonconducting state , bits two , three and four are effectively decoupled from the sense amplifiers 24 . shifting means 42 functions the same as that shown in fig4 a and results in reconfiguration of sram 10 into an 8k × 8 part . fig4 c shows another embodiment of fuse structures 22 used to accomplish reconfiguration of sram 10 . once again , the fuse structures 22 consist of decoupling means 40 and shifting means 42 . decoupling means 40 operates the same as that shown in fig4 b . shifting means 42 , however , is comprised of transistors which are opposite in conductivity to those shown in fig4 b . therefore , if , as in the example discussed above , bit two is associated with the column of memory cells containing the defective cell , fuse 66 is blown using laser means . in this embodiment , blowing fuse 66 operates to both switch off decoupling transistors 68 , 70 and 72 , and to switch on shifting transistors 74 , 76 and 78 . therefore , by blowing fuse 66 , bits two , three and four are effectively decoupled from sense amplifiers 24 and shifted to the left one place along sense amplifiers 24 . hence , reconfiguration of sram 10 into an 8k × 8 part is accomplished . fig4 d shows another embodiment of fuse structures 22 used to accomplish reconfiguration of sram 10 . again , fuse structures 22 are comprised of decoupling means 40 and shifting means 42 . decoupling means 40 , in this embodiment , operates the same as that discussed in fig4 b and 4c above . shifting means 42 is comprised of shifting transistors , which are of the same conductivity as those in decoupling means 40 , and inverters . therefore , if , as discussed above , bit two is associated with the column of memory cells containing the defective cell , fuse 80 is blown resulting in switching off of decoupling transistors 82 , 84 and 86 . additionally , blowing fuse 80 results in the application of a voltage on the gates of shifting transistors 88 , 90 and 92 which turns them on . this voltage is applied from inverters 94 , 96 and 98 , respectively . with decoupling transistors 82 , 84 and 86 in the nonconducting state , and shifting transistors 88 , 90 and 92 in the conducting state , bits two , three and four are effectively decoupled from the sense amplifiers and bits three and four are shifted to the left one place . therefore , reconfiguration of sram 10 into an 8k × 8 part is accomplished . as is apparent from the above description , switching of the shifting and decoupling transistors is controlled by using a laser means to blow certain fuses which connect the gates of the shifting and decoupling transistors to voltage supplies . however , workers skilled in the art will recognize this as only one of many obvious control means for selectively switching the decoupling and shifting transistors . the redundancy scheme of the present invention allows production of a single device which is capable of utilizing 100 % of the memory cells located thereon when no defects are detected . however , if a defect is detected , the product can be reconfigured , thereby eliminating the defect , and sold as a second product . additionally , the redundancy achieved by the present scheme is very high , and the power dissipation of the device does not increase after it has been repaired . also , since a single column is deactivated upon error detection and the remaining columns are shifted , no additional active circuitry is required . for these reasons , the present invention allows one hundred percent of the memory to be tested for access time and functionality under various test patterns thereby allowing the fix - to - attempt ratio for the present design to be nearly 100 %. this translates into less extra prober , laser trimmer , test time , and wafer handling to be expended on the device and results in a device which can be nearly guaranteed to work upon repair . although the present invention has been described with reference to preferred embodiments , workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention .