this invention relates to programmable integrated circuits , where a given device can be customized to perform a desired logic function , including or excluding memory . listed below are definitions of various terms used to describe the structure and the function of the present invention . these definitions apply to the terms as they are used throughout the specification ( unless the are otherwise limited in specific instances either individually or as a part of a larger group ). the term “ logic - level representations ” refers to any logic level - representation in electronic design method that capable of being implemented by a plurality of programmable logic functions . the term “ programmable logic function ” refers to any configurable logic element that my include all of the circuit elements necessary to provide one or more of the logical functions provided by , for example , an and gate , flip - flop , inverter , nor gate exclusive or gate , and combinations of these functions to form more complex functions . the term “ interconnect ” refers to any interconnect that connects logic - level representations within a programmable integrated circuit and to any wire that connects configurable logic elements among each other within any logic level representation . the term “ adjacent ” refers to any two logic - level representations that located next to each other in the programmable integrated circuit structure . the term “ switch matrix ” refers to any sets of input lines and any set of output lines wherein any one set of input lines connected to any one corresponding set of output lines . the term “ substantially identical 2 - dimensional array ” refers to memory arrays that maintained an aspect ration close to square . the term “ memory representations ” refers to any memory array comprises a plurality of logic - level representations . the term “ memory block ” refers to any memory block comprises two or more configurable logic elements . fig1 shows the generic structure of the programmable integrated circuit architecture . in the present invention a programmable integrated circuit structure comprising a plurality of logic - level representations ff through ln , wherein each - logic level representation comprises a plurality of programmable logic functions . the structure also comprises a first interconnect representation between adjacent logic - level representations such as ff and l 1 , wherein the first interconnect representation couples an output ( 11 ) of a programmable logic function in a first logic - level representation ff to an input ( 12 ) of a corresponding programmable logic function in a second logic - level representation l 1 that is adjacent to the first logic level representation ff . the first interconnect representation between adjacent levels is substantially localized . this interconnect representation comprises a non - programmable interconnect representation or fixed representation . a bank of flip - flops ( 13 ) feeds the first logic - level representation ff . there is a switch matrix ( 14 ) inserted between a carefully chosen pairs of logic - levels representations . each logic - level representation consists of a bank of programmable logic functions , where a programmable logic function ( 15 ) is shown in fig2 . to describe how programmable logic functions are interconnected with each other within a given logic - level representation and how programmable logic functions of one logic - level representation are interconnected with other programmable logic functions from other logic level representations , each logic - level representation is divided into a number of memory blocks in such way that a first memory block comprises an output ( 1 ) of the first programmable logic function of a first logic - level representation and an output ( 2 ) the second programmable logic function of the first logic level representation , and a second memory block comprises an output ( 3 ) of the third programmable logic function of a second logic - level representation and an output ( 4 ) of the fourth programmable logic function of the second logic level representation ; wherein within the first memory block the output ( 1 ) of the first programmable logic function of the first logic - level representation corresponds to the output ( 2 ) of the second programmable logic function of the first logic - level representation , and within the second memory block the output ( 3 ) of the third programmable logic function of the second logic - level representation corresponds to the output ( 4 ) of the fourth programmable logic function of the second logic - level representation . the output ( 1 ) of the first programmable logic function of the first logic - level representation of the first memory block is coupled to the output ( 3 ) of the third programmable logic function and to the output ( 4 ) of the fourth programmable logic function of the second logic - level representation of the second memory block , and the output ( 1 ) of the first programmable logic function of the first logic - level representation is uncoupled to the output ( 2 ) of the second programmable logic function of the first logic - level representation within the first memory block . thus , there is no interconnect representation among programmable logic functions within the first logic - level representation , wherein in traditional programmable integrated circuit architecture the output ( 1 ) of the first programmable logic function of the first logic - level representation is coupled to the output ( 2 ) of the second programmable logic function of the first logic - level representation within the first memory block . the output ( 3 ) of the third programmable logic function of the second logic - level representation of the second memory block is coupled to the output ( 1 ) of the first programmable logic function and to the output ( 2 ) of the second programmable logic function of the first logic - level representation of the first memory block , and the output ( 3 ) of the third programmable logic function of the second logic - level representation is uncoupled to the output ( 4 ) of the fourth programmable logic function of the second logic - level representation within the second memory block . thus , there is no interconnect representation among programmable logic functions within the second logic - level representation , wherein in traditional programmable integrated circuit architecture the output ( 3 ) of the third programmable logic function of the second logic - level representation is coupled to the output ( 4 ) of the fourth programmable logic function of the second logic - level representation within the second memory block . the interconnections for a programmable logic function are fixed and local , such as the wire in ( 16 ). thus , the programmable integrated circuit achieves , dense short wiring without the need for programmable interconnect . fig3 shows an embodiment of the chip layout , showing the connections between the output of one level ( 17 ) to the next level ( 18 ). the layout of the configurable logic elements , such as ( 19 ) and the connections , such as ( 20 ), are shown . all routing is achieved over the cells , without any need for routing matrices , leading to denser implementation . the figure is merely representative , and an embodiment may have several thousands of configurable logic elements in a level . fig4 shows how a 15 - level implementation of the architecture can be realized , while maintaining an aspect ratio that is close to square . thus , in the presently claimed invention a plurality of the logic - level representations is implemented as substantially identical 2 - dimensional arrays . the figure is merely representative , and an embodiment may have a plurality of the logic - level representative that is implemented as memory arrays that are different in sizes . in fig5 , an embodiment where interconnects from different levels are mingled . the wires from the output of one level are interleaved with outputs from a separate level , which enables the wires of one level to act as virtual shields , avoiding crosstalk between wires of the same level , which switch at the same time . a joint patent application describes how to map an arbitrary design onto this architecture . the description in fig3 is only representative — the actual embodiment could have a 100 × 100 array , for instance , so each logic level has 10 , 000 combinational logic elements . with 15 such levels , the chip might contain 150 , 000 configurable logic elements . any path from the output of a memory element to its input goes through the same number of levels and every path is therefore critical . traditional methods leave some paths non - critical and other paths critical , which can directly be exploited by a custom implementation to speed up critical paths at the expense of non - critical ones — such bottlenecks are inherently avoided by the current architecture . also , the absence of switches to program the interconnect means that the circuit not only operates faster , but is also more dense . there is less stray wiring than conventional programmable circuits , so the power dissipation at similar operation speed is lower . also , there is a clear demarcation between elements , which are purely sequential ( memory elements ) and logic elements , which are purely combinational ( no memory ), leading to better layout density than architectures where each element has a mix of these elements , leading to poor utilization in conventional architectures .