hereinafter , exemplary embodiments will be described in detail with reference to the accompanying drawings . throughout the drawings and the detailed description , unless otherwise described , the same drawing reference numerals will be understood to refer to the same elements , features , and structures . the relative size and depiction of these elements may be exaggerated for clarity , illustration , and convenience . the following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods , apparatuses , and / or systems described herein . accordingly , various changes , modifications , and equivalents of the methods , apparatuses , and / or systems described herein will be suggested to those of ordinary skill in the art . also , descriptions of well - known functions and constructions may be omitted for increased clarity and conciseness . the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments . as used herein , the singular forms “ a ,” “ an ” and “ the ” are intended to include the plural forms as well , unless the context clearly indicates otherwise . it will be further understood that the terms “ comprises ” and / or “ comprising ,” when used in this specification , specify the presence of stated features , integers , steps , operations , elements , and / or components , but do not preclude the presence or addition of one or more other features , integers , steps , operations , elements , components , and / or groups thereof . hereinafter , exemplary embodiments will be described in detail with reference to the accompanying drawings . in an embodiment , a multiplex - based lpc access scheme is proposed for implementing low - complexity mpeg - 4 als very large - scale integration ( vlsi ) and a recursive fir filter structure using the characteristic of a long lpcs calculation time compared with the fir filter operation and signal dependency of a short - term predictor calculation block . a calculation time for an iterative time of fir filter processing and lpc calculation is considered for deciding an appropriate pipeline control system and a recursive fir filter architecture . the processing start time of a short - term predictor depends on the lpcs calculation end time and mpeg - 4 als encoder needs large number of filter taps for supporting 1024 prediction order . in this reason , pipeline architectures for a short - term predictor have been proposed to use the limited prediction order for high - speed and area - efficient implementations . however these limited prediction order does not satisfy mpeg - 4 als standard and it decrease the compression ratio of audio data . these architectures also have the pipeline hazard due to the mismatch of coefficient estimation and fir filter calculation time . to overcome these implementation problems , iterative fir filter structure and multiplex based lpcs access scheme using the property of long lpcs calculation time compared to the fir filter operation are proposed for low complexity mpeg - 4 als encoder hardware . to decide a suitable iterative fir filter architecture and optimal selection of prediction filter tap , we define the calculation time ratio that is the relative division value of the lpcs calculation and fir filter processing time . we use clock numbers for deciding lpcs calculation time and these values are easily obtained from mpeg - 4 als standard . in addition , clock numbers for direct form and radix - 2 fir filter are calculated by using previous work . fig1 shows comparison results of calculation time ratio for a 1024 tap and a 16 tap fir filter . the horizontal dash - dot line in the y - axis of fig1 denotes a decision bound where calculation time ratio is 1 and it means that the filter coefficients calculation time is equal to the fir filter calculation time . in case of the upper decision bound , lpcs calculation block needs more processing time than fir filter operation . from this result , we can decide that the optimal number of tap is 16 for recursive fir filter scheme . although the recursive scheme using a 16 tap fir filter increase the calculation time of higher 16 orders as shown in gray color region of fig1 , lpcs calculation time is still too long and fir filter block must be stalled until lpcs calculation is finished . consequently , short - term predictor for the higher order over 16 can be calculated recursive method . in addition , the proposed recursive fir filter design is based on the radix - 2 algorithm for odd and even order calculation . to apply the modified radix - 2 algorithm with recursive parameter l to direct convolution fir filter , y ( n ) can be defined as : where a parameter “ n ” is a prediction order , a parameter “ t ” is the number of fir filter taps , a parameter “ l ” is the number of loops , h k is a linear prediction coefficient , x ( n ) is a sample signal , and y ( n ) is an output of a filter . by applying the radix - 2 algorithm , total complexity per output point is a 3n / 4 multiplication and a 3n / 4 addition . fig2 is a block diagram illustrating a structure of a variable order short - term predictor according to an embodiment . referring to fig2 , a variable order short - term predictor 100 according to an embodiment includes a pre - decision module 110 , a loop controller module 120 , an fir filter module 160 , and an output module 180 . the variable order short - term predictor 100 may further include a memory controller module 130 , a coefficient module 140 that buffers a coefficient , a sample module 150 that buffers an input sample such as an audio stream , and a data controller module 170 . the pre - decision module 110 is a module that decides the number of iterations of a filtering operation performed by an fir filter , and receives a prediction order value through a user interface such as a computing apparatus . herein , the prediction order value is a value that has been defined by the mpeg - 4 als standard . the pre - decision module 110 computes a prediction order value , defined by the mpeg - 4 als standard , to calculate a modified prediction order value . the modified prediction order value is a maximum integer value that is obtained by dividing a prediction order , inputted through the user interface , by the optimal number ( i . e ., sixteen ) of taps that have been decided in the description of fig1 . the loop controller module 120 controls an output of the output module 180 , and generates a control signal according to the modified prediction order value being the maximum integer value that is obtained by dividing the modified prediction order value ( i . e ., prediction order ), inputted from the pre - decision module 110 , by sixteen . the control signal is a signal for deciding the number of iterations of the filtering operation performed by the fir filter module 160 , and allows the output of the output module 180 to be held until the number of iterations of the filtering operation reaches the maximum integer value . the memory controller module 130 generates an address signal and a read signal for a sample value inputted to the sample module 150 and an appropriate coefficient value that is inputted to the coefficient module 140 for the calculation of the recursive fir filter . the recursive architecture and the radix - 2 algorithm , modified for low complexity , are applied to the fir filter module 160 . specifically , the fir filter module 160 is configured with a plurality of dependently - connected stages . each of the stages , as illustrated in fig1 , is configured with a plurality of multipliers , a plurality of adders , and two delay cells d , for implementing the radix - 2 algorithm in hardware . the fir filter module 160 ( modified radix - 2 fir filter ) is configured with eight stages ( stage 0 to stage 7 ), for implementing the radix - 2 algorithm in hardware . herein , when the prediction order is greater than or equal to 17 , the short - term predictor 100 is implemented with a 16 - tap fir filter . this is because the fir filter calculates a residual value by using the recursive fir filter architecture . to apply the recursive architecture , the loop controller module 120 decides the number of iterations of the filtering operation based on the prediction order . when the number of iterations of the filtering operation performed by the fir filter module 160 reaches the maximum integer value , the output module 180 adds a filtering operation result per iteration number while the output of the fir filter module 160 is being held , and thus outputs y ( n ) of equation ( 1 ) that is a final operation result . in this way , the fir filter module 160 ( modified radix - 2 fir filter ) with the modified radix - 2 algorithm and recursive architecture applied thereto calculates an odd output by using a current even output and a previous even output to generate two outputs , namely , an even output and an odd output simultaneously . the data controller module 170 controls the coefficient module 140 and the sample module 150 to control the data flow of the coefficient and sample . fig3 is a block diagram illustrating an internal configuration of a coefficient calculator module which is operationally connected to the variable order short - term predictor of fig2 . referring to fig3 , the coefficient calculator module 200 calculates the coefficient value , and supplies the coefficient value to the coefficient module 140 of the variable order short - term predictor of fig2 through a multiplexer ( mux ) 130 and a register 150 . the coefficient calculator module 200 includes a harming windowing block 210 , an autocorrelator 220 , a levinson - durbin block 230 , a quantizer block 240 , a parcor to lpc block 250 , and a memory controller block 260 . the hanning windowing block 210 receives a sample value from the outside , and performs a multiplication operation on the received sample value with a hanning function . the autocorrelator 220 receives the multiplied result from the hanning windowing block 210 , and autocorrelates the multiplied result for generating an input of the levinson - durbin block 230 . the levinson - durbin block 230 estimates a partial autocorrelation ( parcor ) coefficient value that is less sensitive to an error , based on the levinson - durbin algorithm . the quantizer block 240 quantizes the parcor coefficient value from the levinson - durbin block 230 . the parcor to lpc block 250 sequentially stores the quantized parcor coefficient values as linear prediction coefficient ( lpc ) values in the coefficient register 150 . the multiplexer 130 selectively outputs the stored lpc values to the variable order short - term predictor 100 according to the address signal and read signal from the short - term predictor 100 . subsequently , the variable order short - term predictor 100 reads the lpc that is selectively inputted through the multiplexer 130 , and thus , the fir filter module 160 with the recursive fir filter architecture applied thereto calculates a residual value . according to the embodiment , complexity can be reduced in implementing mpeg - 4 als hardware . a number of exemplary embodiments have been described above . nevertheless , it will be understood that various modifications may be made . for example , suitable results may be achieved if the described techniques are performed in a different order and / or if components in a described system , architecture , device , or circuit are combined in a different manner and / or replaced or supplemented by other components or their equivalents . accordingly , other implementations are within the scope of the following claims .