preferred embodiments of the present invention will be explained below with reference to the accompanying drawings . wherever possible , the same reference numbers will be used throughout the drawings to refer to the same or like parts . as shown in fig4 a , a static electricity preventing device of a tft - lcd of the present invention has a structure in which an intrinsic semiconductor layer 12 is formed between an n + or p + doped semiconductor layer , which will form a source and drain in the completed device . an insulating layer 10 is formed on intrinsic semiconductor layer 12 and the heavily doped semiconductor layers , and a floating gate 9 is provided on insulating layer 10 overlying intrinsic semiconductor layer 12 . the structure of the esd ( electrostatic discharge ) preventing device of the present invention is similar to that of the conventional transistor , but includes a floating gate mos structure , as discussed in more detail below . while the conventional static electricity preventing device , as described above , has a structure in which two transistors whose gate and drain are connected to each other , the static electricity preventing device of the present invention has a similar structure to that of an mos tft but uses a simpler structure in which floating gate 9 is made to float and only two connecting terminals 14 of doped semiconductor layer 11 are used . reference number 13 denotes a superposed parasitic capacitance ( parasitic capacitance generated by superposition of floating gate and source / drain of n + or p + layers ). fig4 b is an equivalent circuit diagram of the static electricity preventing device shown in fig4 a . referring to fig5 static electricity preventing device 15 of the present invention consisting of a transistor having a floating gate is connected between a common line and each signal line 5 , and between the common line and each gate line 4 . the operation of the static electricity preventing device of the present invention will be explained below with reference to fig6 which shows a comparison of voltage - current characteristics of the conventional static electricity preventing device and the present invention . when an lcd operates normally , within a voltage range of the signals supplied from the driving circuit , a slight amount of current flows . accordingly , lines are opened , which are , however , supposed to be connected to both terminals of the static electricity preventing device , having no effect on signal voltage . if a high voltage is induced by static electricity , the potential difference between the two lines disappears because currents flow through both terminals of the static electricity preventing device . this prevents the insulating layer from being destroyed due to static electricity . unlike the conventional static electricity preventing device , the static electricity preventing device of the present invention consists of a single transistor , simplifying its fabrication process and improving the yield . moreover , even if a significant amount of current flows between the doped semiconductor layer and floating gate due to partial malfunction of the gate insulating layer of the static electricity preventing device , a short between the signal line and gate line does not occur , having no effect on the operation of pixel . fig7 a and 7b show a static electricity preventing device of the present invention embodiment using a typical inverted staggered - type transistor structure . referring to fig7 a showing the static electricity preventing device consisting of a thin film transistor having a bottom gate structure , wherein a floating gate 9 is formed on a substrate 100 . an intrinsic semiconductor layer 12 is formed on the floating gate , having a gate insulating layer 10 therebetween . a doped semiconductor layer 11 , constituting a source and drain , is formed on the intrinsic semiconductor layer 12 , and provided at predetermined intervals on the substrate . in addition , metal electrodes serving as connecting terminals 14 respectively contact doped semiconductor layer 11 through a contact hole which is formed in a predetermined portion of an insulating layer 16 . fig7 b shows a static electricity preventing device having a tft top gate structure . the top gate structure includes an intrinsic semiconductor layer 12 formed on a substrate 100 , and a doped semiconductor layer 11 to be a source and drain formed on the intrinsic semiconductor layer at predetermined intervals . a floating gate 9 is formed on the doped semiconductor layer 12 , having a gate insulating layer 10 therebetween , and metal electrodes serving as terminals 14 contact doped semiconductor layer 11 through a contact hole which is formed in a predetermined portion of an insulating layer 16 overlying floating gate 9 . fig8 shows an equivalent circuit diagram of the static electricity preventing device of the present invention . at the low signal voltage , resistance rch of intrinsic semiconductor layer 12 is large , which results in little current flow . in case that voltage v is applied to both terminals of the device , voltage vg induced to the floating gate can be given by the following equation . here , c ol1 and c ol2 are superposed parasitic capacitance generated between the doped semiconductor layer , which is formed on both sides of the intrinsic semiconductor layer , and the floating gate metal . when voltage vg is induced , electrons or holes are induced in intrinsic semiconductor layer 12 to form a channel , and a large current flows at a voltage above the threshold voltage of the device . the threshold voltage becomes higher than that of the conventional static electricity preventing device having a structure in which the gate and drain are connected . therefore , the threshold voltage of the static electricity preventing device varies with the superposed or overlap area of floating gate 9 and doped semiconductor layer 11 . because the conventional static electricity preventing device has a low threshold voltage , leakage current at low signal voltage levels is relatively large . accordingly , if the current driving capacity of the external driving circuit is not very high , the signal supplied to the pixel may be distorted . however , the static electricity preventing device of the present invention improves its threshold voltage , to thereby reduce current driving capacity . this decreases the driving power of the lcd . the superposed parasitic capacities c ol1 and c ol2 may be different from each other in order to control threshold voltage , as shown in fig9 . in addition , the static electricity preventing device may have a symmetric construction in such a manner that two transistors are connected in parallel . in fig9 l 1 and l 2 show a superposed width of the doped semiconductor layer and the floating gate . fig1 is an equivalent circuit diagram of fig9 . as shown in fig1 a and 11b , the static electricity preventing circuit may be constructed in an lcd , using the static electricity preventing devices connected in parallel . in the static electricity preventing device of the present invention , in order to make a large current flow at a high voltage caused due to static electricity , intrinsic semiconductor layer 12 ( channel length ) is shortened . this makes both ends of doped semiconductor layer 11 fully depleted , resulting in punchthrough . in accordance with another embodiment of the present invention , a doped semiconductor layer may be employed instead of the metal gate . alternatively , the static electricity preventing device may be donstructed with n + semiconductor layer / intrinsic semiconductor layer / n + semiconductor or p + semiconductor layer / intrinsic semiconductor layer / p + semiconductor structures , using only punchthrough characteristics and without the metal gate . in accordance with yet a further embodiment of present invention , only the metal pattern is introduced as the source / drain region instead of heavily doped n - type semiconductor as shown in fig1 b . in this case , the static electricity preventing device ( esd preventing device ) includes two metal layers 21 and 24 , an undoped semiconductor layer 22 and an insulator layer 23 . since the electrical potential of floating layer 24 can not be lower than that of the source 21 of the esd preventing device , the n - type doped semiconductor layer is not needed between source / drain electrode 21 and undoped semiconductor layer 22 . the operation of this device is same as that of an esd preventing device with n + doped semiconductor . according to the present invention described above , the static electricity preventing device having excellent performance is realized in a simplified structure , preventing insulation destruction caused due to static electricity during tft - lcd fabrication . even in case that the static electricity preventing device is poor , display characteristics are unaffected , thereby improving the yield during tft - lcd fabricating process .