in fig1 is shown a top view of a portion of a semiconductor device , with a set of finger - like collectors connected to a common collector lead 12 . the emitters are split into emitter finger portions , each connected to a common emitter lead 10 . the base leads are not shown in this figure . the emitter finger portions are arranged generally elongately in a common direction , and the ballast resistors are substantially parallel to the common direction . it can further be seen in this figure that the emitter ballast resistors are connected at one end to the respective emitters and with the opposite end to the common emitter lead 10 . although not shown in this figure , it is possible to have a base region underneath , split into portions , one under each emitter , and such that the border of which is toward the respective collector is overlaid with sandwiched isolation by the respective ballast resistor . in this embodiment , the collectors are elongate fingers cooperating each with a linear set of emitters . it should be understood that the number of emitters shown is so low only for illustration purposes and that the number may be at least an order of magnitude higher . fig2 shows a top view of an overlay structure of a further embodiment of the invention . vertical cross sections taken at a -- a , b -- b and c -- c of fig2 are shown in fig3 and 5 respectively . in this embodiment , each emitter finger as of fig1 is part of a unit cell , which may form a complete transistor with the emitter , base and collector separately arranged in an isolated portion of the silicon chip . this is shown in all the figures , where grossly hatched portions 16 denote either an isolating layer as e . g . silicon oxide material , as is normal in the soi technology , or a layer having the opposite conduction type relative to the collector . in another , related embodiment , the same cell structure may be multiplied at will , the isolating portions 16 then being transferred to the exterior of the plurality of unit cells . this cell thus has an immersed collector slab of n silicon 1 , in which is diffused a base p zone 2 . in which are in turn diffused an n + emitter zone 3 and a p + base connector zone . in the same surface is diffused an n + collector contact zone 5 . ( naturally all those features may have opposite conduction types for a pnp type bipolar transistor .) the contacting of those zones is accomplished by connectors which are submersed in the top silicone oxide . thus , the unit cells are joined by means of a set of connectors of metal , as the common emitter lead 10 , the common base lead 1 land the common collector lead 12 . as shown in fig2 and in the cross section views in fig3 and 5 , the collector contact zone 5 is connected to the metallic collector lead 12 by point contacts denoted k 12 - 5 . ( it is also possible to make one long continuous connection .) the metallic base lead 11 is connected in the same way to the base contact zone 4 , by contacts denoted k 11 - 4 . as shown in the figures , the collector contact zone 5 is arranged in the same surface as the emitter 3 and base 4 zones which is generally preferred in a soi embodiment . there is , however , nothing to prevent , in a more general embodiment of the invention , to arrange the collector connection from the opposite side , or in a layer near the bottom oxide layer , as a buried layer collector , without departing from the invention . these and other modifications would be within the knowledge of one skilled in the art . the connection between the common emitter lead 10 and the emitter zone 3 is , however , slightly more complicated , due to the ballast resistor 14 . this resistive , elongate device , which is preferentially made from suitably doped polysilicon , but may be made of any suitable thin film resistor material , is laid on top of a thin sio 2 layer and on top of the edge of base zone 2 . the metallic common emitter lead 10 is point - connected to one end of isolated second metal lead 13 , parallel thereto and which may cover most of the cell length , but is here about one third thereof . this connection , seen in the section of fig5 is denoted k10 - 13 . at another point , visible in fig2 a connection k13 - 14 is made between second metal lead 13 and ballast resistor layer 14 . the ballast layer 14 is in turn connected at k14 - 15 ( also shown in fig5 ) to the short limb of l - shaped third metal lead 15 , the long limb of which overlays emitter zone 3 . the two latter are joined by numerous contact points k15 - 3 ( also seen in fig3 and 5 ). it is clear that the position of contact k13 - 14 may be varied for obtaining different amounts of ballast resistance , in dependence of the intended use . as understood by the man of the art , the cross - sectional views of fig3 - 5 have exaggerated thickness scales . the manufacture of such soi material and soi - material based components are also well - known . the manufacture of such material is described in sorin cristoveanu and sheng s . li : &# 34 ; electrical characterization of silicon - on - insulator materials and devices &# 34 ;, 1995 , kluwer academic publishers , massachusetts . usa . for further information on the various and many processing steps which can be used , reference is made to monograph literature in the field , as e . g . wolf + tauber , &# 34 ; silicon processing for the vlsi era &# 34 ;) ( lattice press , sunset beach , calif ., 1986 ). said publications are hereby included by reference into the present disclosure . in the present example , the buried insulator is made of silicon dioxide and the substrate of silicon . the thickness of the device layer may vary between 0 . 1 and 30 μm , but in a preferred embodiment , it is between 5 and 10 μm . the thickness of the buried layer can vary between 0 . 1 and 10 μm , but it is also possible to make the whole carrying substrate from insulator material . from such material is then made in successive steps the various layers as shown in fig3 and 5 , including the eventual separating isolation walls , added in ditches etched down to the buried insulation layer . it is also understood by the man of the art that the unit cell as shown in fig2 - 5 , and which can be used either singly or in multitude as in fig1 is subject to many possible variations . the collector may be a buried collector , or the collector zone may be doubled ( mirroring the overlay in fig2 around conductor 11 ), etc . in fig6 and 7 are shown characteristic curves for a system with an array of 5 × 20 unit cells , built according to fig2 - 5 , where in fig6 external ballast resistors are applied to each column , using the old technique , whereas in fig7 each cell is provided with a ballast resistor of about 140 ω . thermal breakdown is obtained , as seen from the power curve of 10 w , at about that power , except for the high voltage end of the collector voltage , where avalanche breakdown occurs earlier . the same system but with ballast resistors is consistently better , consistent with some 25 w power , except for the high - voltage end . in fig8 and fig9 is shown a comparison made for one sole unit cell , having an emitter with the dimensions 100 × 2 μm . in both figures are shown the base current and emitter current in logarithmic scale ( one division per decade ) as a function of the emitter - base voltage . the base - collector voltage was kept constant at + 60 v . it can be seen that without the emitter ballast resistance , an emitter - base breakdown occurs at an emitter - base voltage of about - 0 . 65 v and a collector current of about 0 . 5 ma . ( the currents shown at higher emitter - base voltages are limited by the measuring apparatus .) with a ballast resistor of about 140 ω , as in fig9 no runaway is apparent even at a collector current of some 5 ma . the invention has been described essentially around a detailed embodiment , illustrated in the drawings . some possible variations have been shortly mentioned , but it is apparent for the man of the art that the possibilities of variation are practically innumerable , and that the scope of the invention is limited only by the appended claims .