referring generally to the block diagram in fig1 , a display presentation 20 is generated to demonstrate the timing relationship between a test video signal at input 22 and a reference such as a second or reference video signal at input 23 . when a signal is processed , there is the potential for it to be delayed with respect to a reference signal . the timing display shown in fig1 is used to indicate when a video input is deviating in time from the reference . the reference can be , for example , a video signal or at least synchronization elements , which are used in a video product facility as the standard to which secondary sources are matched when used in switching operations or the like . the timing display as shown can be one of a plurality of display modes for presentation on a multi - format display apparatus such as disclosed in u . s . pat . nos . 6 , 069 , 607 and 6 , 532 , 024 , which are hereby incorporated . such apparatus include processors operable to generate alternative display formats as selected by the user , and can function by populating a display memory or display output signaj that is used to produce an output image on a vga or svga or other form of monitor device . as shown in fig1 , the test video signal at input 22 is applied to a timing extraction circuit 25 , which produces output pulse signals synchronized to the pixels or samples that correspond to serially adjacent positions along the horizontal lines in the video program (“ horizontal ”). the timing extraction circuit 25 also produces a pulse (“ vertical ”) for each horizontal line in the succession of vertically adjacent horizontal lines in the video picture . the timing extraction circuit 25 also produces a field id signal that occurs at the completion of a video field and in the case of interleaved video can distinguish between fields . the outputs of the timing extraction circuit 25 are coupled to a timing generator block 32 , which contains respective horizontal and vertical counters 33 , 35 , that respectively count time increments at the high frequency sampling or pixel rate and tat the lower frequency line rate . the pixel counter 33 and line counter 35 can be reset so as to count lines over one field or frame , and to count pixels during each horizontal line , for example by resetting each counter as shown . the accumulated counts in the two registers are loaded in parallel into registers in a timing latch circuit 40 , upon a pulse signal generated synchronously with the reference signal to which the test signal is being compared . assuming that the reference signal is a second video signal , a timing extraction circuit 27 can be used to extract horizontal pixel displacement and vertical line displacement information , and a field id value that can toggle in the case of interleaved fields . the reference timing signals are applied to a frame id circuit 42 that produces one pulse output per frame , which can be arranged to occur consistently at an optionally selected point during the reference signal or simply at a known point such as the first pixel in the first line . the output pulse of frame id circuit 42 loads the values h - count and v - count from counters 33 , 35 into registers in latch 40 , the outputs of which are coupled in turn to processor 50 . the h count can be reset at each successive line . the v or line count is reset at each successive field or frame . the processor 50 contains data memory including a display memory or buffer wherein the processor stores data in composing a display of contrasting luminance and colors so as to simulate a dual meter on display 20 . the contents of the display memory are read out repetitively as the corresponding input signals 22 , 23 vary . fig2 shows the timing offset display in a typical situation wherein there is some extent of timing offset between two arbitrary input signals . the static elements of the display presentation include a scale line 62 with graduation marks 64 . a preferably - fixed reference indicator box 65 ( labeled [ ref ]) is located at a nominal position such as the center of the timing display graduated line , also indicated by a distinct graduation line 66 . two legends 67 , 68 show which side of the central mark or graduation 65 , 66 indicates that the test signal is advanced and which side indicates delayed , relative to the reference signal whose timing is aligned to the distinct graduation line 66 , preferably at the midpoint . a first movable indicator box 72 ( labeled [ line ]), preferably with an associated movable distinct graduation line marker 73 , is placed by the display processor at the position corresponding on the graduation scale line to the vertical or line count offset determined from the line counter 35 in fig1 . in the example shown , the position of the line count indicator is determined with reference to a scale pitch or resolution of one horizontal line per graduation mark 64 . a different scale pitch is possible , for example two lines per shorter graduation mark and ten lines per longer graduation mark . the line count indicator is generally placed above and over the graduation line 62 . a second movable indicator box 82 ( labeled [ μsec ]), also preferably having an associated movable distinct graduation line marker 83 , is placed by the display processor at the position corresponding on the graduation scale line to the horizontal timing offset . this value is the count offset determined from the pixel counter 32 in fig1 . this counter is incremented at a timing offset that can be equal to one sample period at the highest sampling rate in a digital embodiment , which determines the resolution of the graduation scale marks 64 . in an analog embodiment ( or selectable analog mode of operation ), the resolution should be a fraction of the period of the color subcarrier . the necessary frequency ( i . e ., a multiple of the subcarrier frequency ) can be generated in the timing extraction circuit 25 , e . g ., using a multiplying phase locked loop or the like ( not shown in fig1 ). the horizontal offset indicator box 82 is generally on a an under the graduation line 62 . in the example shown in fig2 , the position of the line count indicators 72 , 73 is determined with reference to a scale pitch or resolution of one horizontal line per graduation line . this is labeled as a “ vertical ” count in a text legend portion 85 because the horizontal lines are placed over one another in vertical succession , wherefore a given count of horizontal lines is intuitively considered a vertical displacement in a video picture . a different scale pitch is possible , for example two lines per short graduation line and ten per long graduation line , etc . the position of the μsec indicators 82 , 83 in fig2 is determined to a scale pitch or resolution of 100ηs per graduation mark 64 . again , a different resolution is possible . both the vertical and horizontal indicator sets 72 , 73 and 82 , 83 , are positioned at either side of the central reference box 65 and marker 66 , for indicating whether the test signal is advanced or delayed relative to the reference signal . the display processor 50 also preferably provides tabular or numeric entries on the display area 20 . a legend 85 names parameter categories and entries 87 state the values therefore . the two inputs are identified as the ref and test inputs . in this case , ref a has been selected and its offset is against test input a . in a preferred arrangement , there can be more than one ref signal chosen among alternatives such as plural internally generated signals , plural inputs coupled as inputs to the test apparatus or the like . the tabular entries in the display area 20 preferably include the numeric values that correspond to the indicated positions of the indicator blocks 72 , 83 , namely the line count and the horizontal color alignment offset . in fig2 , these delays are 11 lines and 500 ηs ( or 0 . 5 μs ), respectively , as might be obtained from two arbitrary signals . fig3 is a flow chart showing the programmed steps of the display processor 50 , taken in generating the contents of display area 20 . the static part of the display contents can be stored in memory and used as the blank field on which contrasting pixel data is to be inserted to provide the movable elements in the display presentation . as a first step 122 , the processor reads the latched v and h counts from timing latches 40 ( fig1 ). if the values are unchanged , decision block 123 loops back , leaving the display memory unchanged . if the values have changed , the new values are stored and offsets are applied as necessary to the video format ( ntsc , pal , etc .) at step 124 , to provide functionally similar line and timing indications regardless of format . the scale line 62 in fig2 only has sufficient span for a certain number of v line - count values and / or μsec time period - count values . it is possible to have a changeable scale , but preferably instead , the scale values are preset and the manner of presentation of the display is changed if the count values run out of the span that can be displayed graphically . in fig3 for this purpose , a decision step 125 includes comparing the data values to thresholds to determine whether a nominal or special display situation is presented . step 126 concerns adjusting for a special situation . step 128 finally comprises generating the display data in the display memory , whereupon a display driver ( not shown ) can present the data on a monitor or transmit the data for remote viewing , etc . a special display situation can be presented wherein one or more values are found to be off the scale of scale line 62 . alternatively , user selectable thresholds can be involved to distinguish , for example by color , when the offset is more or less than some threshold warning level . a special display situation also may be presented ( and a response accomplished through steps 125 , 126 ) when one or more values is found to be aligned to the reference , or at least aligned to within some threshold value such as a within a single scale increment ( zero to one line or zero to 100 ηs ). these special situations can be handled by varying the presentations used for the indicator boxes 72 , 82 and / or associated lines 73 , 83 and / or the fixed portions such as ref box 65 and center line 66 . fig4 shows one advantageous presentation . in this example , the h count is aligned and can be shown as a green box 82 . the v or line count is off scale , which situation is shown by using a distinct color for box 72 ( e . g ., orange ). box 72 can be blinked . in lieu of an associated graduation line mark 73 , an off - scale arrow can be presented . fig5 shows a situation in which the reference and test inputs are fully aligned and both the v and h offsets are zero ( or at least less than the smallest resolution of error ). in a preferred embodiment , the ref box is placed so as to represent the reference - timing points for the type of signal being monitored . the ref box is green when the vertical line count and horizontal color alignment time increment count ( in nanoseconds or microseconds ) cursors are all aligned . if the test signal falls out of timing alignment with the referenc , the line count marker 72 and the ηsec marker 82 are changed in color and moved outwardly in the appropriate advanced or delayed direction from ref . the ref box preferably is then colored red . each hash mark proceeding outwardly from the reference point represents one line on the top scale and 100 ηs on the bottom scale . when line - count or μsec values reach or exceed the edge of the scale span , an arrow such as arrow 75 is added to the right or left of the scale . on the other hand , when both signals are aligned , the ref box preferably is colored green . also in the preferred arrangement , the legend area of display area 20 contains category designations 85 and selections 87 including the following . ref is the selected reference input that represents the ref signal line in the display , which can preferably use one of several inputs or internally generated references ( input a , b , c , d , bb , tri ). similarly , the test — indicator shows which of several possible input signals is currently selected to be the applicable test input to be monitored ( a , b , c , or d ). vertical states the line offset count in full - video lines between the reference and the test video signal , including the capability to indicate positive or negative counts for leading or lagging . horizontal is the offset time in microseconds between the reference and the displayed video . horizontal can be yellow at zero μsec . it displays the minimum scale resolution at 100 ns and the minimum timing resolution at 37 ηsec . in a preferred arrangement , the subject timing indicator is one of a number of functions that are possible and can be selected in a multi - format display device . the device is capable of dealing with various signal conditions , but it is also possible that some signal conditions may be anomalous with respect to the idea of comparing line counts and the like . therefore , the horizontal and the μsec cursor are entirely blanked and will will not be caused to appear if the reference format has a different line length than the input format . thus , the line and μsec cursors 72 , 82 and preferably the associated legends are omitted if the timing display is selected but there is a combination of a test input format of sd ( standard definition ) and a ref format of hd ( high definition ) or tri ( tri - level ). the cursors and legends also are omitted if the test input is hd and the ref format is sd or bb ( external composite ). the apparatus as disclosed can be used to reference a digital test input to an analog ref or vice versa . as shown generally in fig6 , an analog input applied to the timing extraction circuit can be used to derive the line count signal and a horizontal pixel sampling clock . as shown in fig6 , the reference signal used can be related to some outside timing reference as opposed to being derived specifically from one of two video signals . the invention having been disclosed in connection with the foregoing preferred arrangements , variations will now be apparent , and should be considered encompassed within the scope and spirit of the invention .