referring now to fig1 , there is illustrated a block diagram describing an exemplary circuit for displaying encoded video data 5 . the encoded video data 5 comprises a series of pictures 10 ( 1 ) . . . 10 ( x ) for display . the encoded video data 5 can be both compressed and encrypted . the circuit comprises a dma module 12 , a video decoder 14 , and a display engine 16 . during regular playback , the dma module 12 fetches batches of the video data 5 from a memory 18 and provides the batches of the video data 5 to the video decoder 14 . the batches contain the pictures 10 ( 1 ) . . . 10 ( x ) in the decode order . the video decoder 14 decodes the pictures 10 ( 1 ) . . . 10 ( x ) in a forward decode order . the display engine 15 provides the pictures 10 ( 1 ) . . . 10 ( x ) for display in a forward display order . it is noted , that the decoding order and display order may be different . in cases where the decoding order and the display order are different , frame buffers 16 can be used to receive the decoded pictures 10 and provide the decoded pictures to the display engine 15 in the display order . the circuit can also display the pictures in high - speed rewind . during high - speed rewind , a portion of the pictures are displayed and in reverse order , e . g ., 10 ( x ), 10 ( x - 3 ), 10 ( x - 6 ), . . . . the dma module 12 fetches batches of video data 5 that include the pictures 10 in the high - speed rewind order . however , the pictures 10 in the high - speed rewind order are not necessarily stored consecutively in the memory 18 . a processor 20 can determine address ranges of batches that include the pictures 10 in the high - speed rewind order . the processor 20 provides the address ranges to the dma module 12 . the dma module 12 fetches the batch of video data . the video decoder 14 parses the batch starting from the beginning until the video decoder 14 detects the picture 10 in the high - speed rewind order . the video decoder 14 decodes the picture 10 in the high - speed rewind order . however , the batches do not necessarily begin with or end with the pictures 10 in the high - speed rewind order . fig2 illustrates an exemplary batch 25 . the batch 25 comprises a beginning portion 25 a , a picture 10 in the high - speed rewind order , and a remaining portion 25 b . referring again to fig1 , the video decoder 14 parses the beginning portions 25 a of the batches of data . according to certain aspects of the invention , the video decoder 14 decodes the picture in the high - speed rewind order . additionally , the video decoder 14 can also decrypt to picture . the display engine 15 provides the particular pictures for display . according to certain aspects of the present invention , a controller 25 can issue a command to the video decoder 14 that is followed by the batch . the command commands the video decoder 14 to parse the beginning portion 25 a , decode the picture 10 in the high - speed rewind order , and discard the remaining portion 25 b of the batch . referring now to fig3 , there is illustrated a flow diagram for displaying pictures in accordance with an embodiment of the present invention . at 30 , the circuit receives a high - speed rewind signal . responsive thereto , the dma module 12 fetches ( 35 ) a batch of video data from the memory that includes the next picture in the high - speed rewind order . at 40 , the controller 25 sends a command to the video decoder 14 . the command is received , followed by the batch by the video decoder 14 . the command causes the video decoder 45 to parse ( 45 ) the beginning portion 25 a of the batch , decode the picture ( 50 ), and discard ( 55 ) the remaining portion 25 b of the batch . at 60 , the display engine 15 provides the decoded picture for display . the foregoing invention will now be described in exemplary embodiments with video data encoded in accordance with the mpeg - 2 standard . it will be understood that the invention is not limited to mpeg - 2 . in contrast , the invention can be used with a variety of encoding standards . according to certain aspects of the present invention , the high - speed rewind operation can be effectuated by displaying only intra - coded pictures in reverse order . fig4 a illustrates a block diagram of an exemplary moving picture experts group ( mpeg ) encoding process of video data 101 , in accordance with an embodiment of the present invention . the video data 101 comprises a series of frames 103 . each frame 103 comprises two - dimensional grids of luminance y , 105 , chrominance red c r , 107 , and chrominance blue c b , 109 , pixels . the two - dimensional grids are divided into 8 × 8 blocks , where a group of four blocks or a 16 × 16 block 113 of luminance pixels y is associated with a block 115 of chrominance red c r , and a block 117 of chrominance blue c b pixels . the block 113 of luminance pixels y , along with its corresponding block 115 of chrominance red pixels c r , and block 117 of chrominance blue pixels c b form a data structure known as a macroblock 111 . the macroblock 111 also includes additional parameters , including motion vectors , explained hereinafter . each macroblock 111 represents image data in a 16 × 16 block area of the image . the data in the macroblocks 111 is compressed in accordance with algorithms that take advantage of temporal and spatial redundancies . for example , in a motion picture , neighboring frames 103 usually have many similarities . motion causes an increase in the differences between frames , the difference being between corresponding pixels of the frames , which necessitate utilizing large values for the transformation from one frame to another . the differences between the frames may be reduced using motion compensation , such that the transformation from frame to frame is minimized . the idea of motion compensation is based on the fact that when an object moves across a screen , the object may appear in different positions in different frames , but the object itself does not change substantially in appearance , in the sense that the pixels comprising the object have very close values , if not the same , regardless of their position within the frame . measuring and recording the motion as a vector can reduce the picture differences . the vector can be used during decoding to shift a macroblock 111 of one frame to the appropriate part of another frame , thus creating movement of the object . hence , instead of encoding the new value for each pixel , a block of pixels can be grouped , and the motion vector , which determines the position of that block of pixels in another frame , is encoded . accordingly , most of the macroblocks 111 are compared to portions of other frames 103 ( reference frames ). when an appropriate ( most similar , i . e . containing the same object ( s )) portion of a reference frame 103 is found , the differences between the portion of the reference frame 103 and the macroblock 111 are encoded . the location of the portion in the reference frame 103 is recorded as a motion vector . the encoded difference and the motion vector form part of the data structure encoding the macroblock 111 . in the mpeg - 2 standard , the macroblocks 111 from one frame 103 ( a predicted frame ) are limited to prediction from portions of no more than two reference frames 103 . it is noted that frames 103 used as a reference frame for a predicted frame 103 can be a predicted frame 103 from another reference frame 103 . the macroblocks 111 representing a frame are grouped into different slice groups 119 . the slice group 119 includes the macroblocks 111 , as well as additional parameters describing the slice group . each of the slice groups 119 forming the frame form the data portion of a picture structure 121 . the picture 121 includes the slice groups 119 as well as additional parameters that further define the picture 121 . i 0 , b 1 , b 2 , p 3 , b 4 , b 5 , p 6 , b 7 , b 8 , p 9 , in fig4 b , are exemplary pictures . the arrows illustrate the temporal prediction dependence of each picture . for example , picture b 2 is dependent on reference pictures i 0 , and p 3 . pictures coded using temporal redundancy with respect to exclusively earlier pictures of the video sequence are known as predicted pictures ( or p - pictures ), for example picture p 3 is coded using reference picture i 0 . pictures coded using temporal redundancy with respect to earlier and / or later pictures of the video sequence are known as bi - directional pictures ( or b - pictures ), for example , pictures b 1 is coded using pictures i 0 and p 3 . pictures not coded using temporal redundancy are known as i - pictures , for example i 0 . in the mpeg - 2 standard , i - pictures and p - pictures are also referred to as reference pictures . the foregoing data dependency among the pictures requires decoding of certain pictures prior to others . additionally , the use of later pictures as reference pictures for previous pictures requires that the later picture is decoded prior to the previous picture . as a result , the pictures cannot be decoded in temporal display order , i . e . the pictures may be decoded in a different order than the order in which they will be displayed on the screen . accordingly , the pictures are transmitted in data dependent order , and the decoder reorders the pictures for presentation after decoding . i 0 , p 3 , b 1 , b 2 , p 6 , b 4 , b 5 , p 9 , b 6 , b 7 , in fig4 c , represent the pictures in data dependent and decoding order , different from the display order seen in fig4 b . referring again to fig4 a , the pictures are then grouped together as a group of pictures ( gop ) 123 . the gop 123 also includes additional parameters further describing the gop . groups of pictures 123 are then stored , forming what is known as a video elementary stream ( ves ) 125 . the ves 125 is then packetized to form a packetized elementary sequence . the packetized elementary stream includes parameters , such as the decode time stamp and the presentation time stamp . the packetized elementary stream is then further packetized into fixed length packets , each of which are associated with a transport header , forming what are known as transport packets . the packetized elementary stream can also be encrypted . the transport packets can be multiplexed with other transport packets carrying other content , such as another video elementary stream 125 or an audio elementary stream . the multiplexed transport packets form what is known as a transport stream . the transport stream is transmitted over a communication medium for decoding and displaying . referring now to fig5 , there is illustrated a block diagram of an exemplary circuit for decoding the compressed video data , in accordance with an embodiment of the present invention . a buffer 201 within a synchronous dynamic random access memory ( sdram ) 202 receives a transport stream . the buffer 201 can receive the transport stream , either from a storage device 204 , such . as , for example , a hard disc or a dvd , or a communication channel 206 . a data transport processor 205 demultiplexes the transport stream into audio transport streams and video transport streams . the data transport processor 205 provides the audio transport stream to an audio portion 215 and the video transport stream to a video transport processor 207 . the video transport processor 207 parses the video transport stream and recovers the video elementary stream . the video transport processor 207 writes the video elementary stream to a compressed data buffer 208 . a video decoder 209 reads the video elementary stream from the compressed data buffer 208 and decodes the video . the video decoder 209 decodes the video on a picture by picture basis . when the video decoder 209 decodes a picture , the video decoder 209 writes the picture to a frame buffer 210 . the video decoder 209 receives the pictures in decoding order . however , as noted above , the decoding and displaying orders can be different . accordingly , the decoded pictures are stored in frame buffers 210 to be available at display time . at display time , display engine 211 scales the video picture , renders the graphics , and constructs the complete display . once the display is ready to be presented , it is passed to a video encoder 216 where it is converted to analog video using an internal digital to analog converter ( dac ). the digital audio is converted to analog in an audio digital to analog converter ( dac ) 217 . the frame buffers 210 also allow the video decoder 209 to predict predicted pictures from reference pictures . the decoder 209 decodes at least one picture , i 0 , b 1 , b 2 , p 3 , b 4 , b 5 , p 6 , b 7 , b 8 , p 9 , during each frame display period , in the absence of personal video recording ( pvr ) modes when live decoding is turned on . due to the presence of the b - pictures , b 1 , b 2 , the decoder 209 decodes the pictures , i 0 , b 1 , b 2 , p 3 , b 4 , b 5 , p 6 , b 7 , b 8 , p 9 in an order that is different from the display order . the decoder 209 decodes each of the reference pictures , e . g ., i 0 , p 3 , prior to each picture that is predicted from the reference picture . for example , the decoder 209 decodes i 0 , b 1 , b 2 , p 3 , in the order , i 0 , p 3 , b 1 , and b 2 . after decoding i 0 and p 3 , the decoder 209 applies the offsets and displacements stored in b 1 and b 2 , to the decoded i 0 and p 3 , to decode b 1 , and b 2 . the frame buffers 210 store the decoded pictures , i 0 and p 3 , in order for the video decoder 209 to decode b 1 and b 2 . the video decoder 209 also writes a number of parameters associated with each picture in a buffer descriptor structure 212 . each frame buffer 210 is associated with a buffer descriptor structure 212 . the buffer descriptor structure 212 associated with a frame buffer 210 stores parameters associated with the picture stored in the frame buffer 210 . the parameters can include , for example presentation time stamps . a display manager 213 examines the buffer descriptor structures , and on the basis of the information therein , determines the display order for the pictures . the display manager 213 maintains a display queue 214 . the display queue 214 includes identifiers identifying the frame buffers 210 storing the pictures to be displayed . the display engine 211 examines the display queue 214 to determine the next picture to be displayed . the display manager 213 can determine the next picture to be displayed by examining the pts parameters associated with the pictures . the display manager 213 can compare the pts values associated with pictures to a system clock reference ( scr ) to determine the ordering of the pictures for display . alternatively , the display manager 213 can also determine the order of the pictures to be displayed by examining the type of pictures decoded . in general , when the video decoder 209 decodes a b - picture , the b - picture is the next picture to be displayed . when the video decoder 209 decodes an i - picture or p - picture , the display manager 213 selects the i - picture or p - picture that was most recently stored in the frame buffer 210 to be displayed next . a particular one of the frame buffers 210 stores b - pictures , while two other frame buffers 210 store i - pictures and p - pictures . when the video decoder 209 decodes a b - picture , the video decoder 209 writes the b - picture to the particular frame buffer 210 for storing b - pictures , thereby overwriting the previously stored b - picture . when the video decoder 209 decodes an i - picture or a p - picture , the video decoder 209 writes the i - picture or p - picture to the frame buffer 210 storing the i - picture or p - picture that has been stored for the longest period of time , thereby overwriting the i - picture or p - picture . the circuit also includes a controller 220 that acts as the master for the data transport processor 205 , the video transport processor 207 , the video decoder 209 , the display engine 211 , and the display manager 213 . the circuit also supports a number of functions allowing the user to control the presentation of the video . these functions include high - speed rewind . in high - speed rewind , the circuit provides the pictures of a video elementary stream for display in reverse order . when the pictures are displayed in reverse order , the video appears in reverse and faster . the video appears faster because the circuit provides only the i - pictures for display . the high - speed rewind is initiated by a receipt of a user signal by receiver 225 . upon receiving the signal , the receiver 225 notifies the controller 220 . the controller 220 then issues commands to the video transport processor 207 , the video decoder 209 , and the display engine 211 , that perform the high - speed rewind operation . according to certain aspects of the present invention , the commands can be provided in transport packets . during the high - speed rewind operation , the video transport processor 207 fetches batches of data from the sdram in reverse order via a dma module 208 . the video transport processor 207 can determine the address ranges for the batches by examining the transport packets . the transport packets include a parameter identifying pictures in terms of what are known as access units . based on the number of transport packets between access units , the video transport processor 207 can determine the address ranges for batches that include i - pictures . each batch includes the next i - picture for display in the high - speed rewind order . the video decoder 209 parses the beginning portions of the batches of data , decodes the i - picture , and discards the remaining portion of the batch . the display engine 211 provides the i - picture for display . the circuit as described herein may be implemented as a board level product , as a single chip , application specific integrated circuit ( asic ), or with varying levels of the system integrated on a single chip with other portions of the system as separate components . the degree of integration of the monitoring system may primarily be determined by speed of incoming mpeg packets , and cost considerations . because of the sophisticated nature of modern processors , it is possible to utilize a commercially available processor , which may be implemented external to an asic implementation of the present system . alternatively , if the processor is available as an asic core or logic block , then the commercially available processor can be implemented as part of an asic device wherein the memory storing instructions is implemented as firmware . while the invention has been described with reference to certain embodiments , it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention . in addition , many modifications may be made to adapt particular situation or material to the teachings of the invention without departing from its scope . therefore , it is intended that the invention not be limited to the particular embodiment ( s ) disclosed , but that the invention will include all embodiments falling within the scope of the appended claims .