the preferred embodiment of the invention employs a variation of a resistively - loaded npn transconductance pair , 10 , which includes transistors 1 q 1 and 1 q 2 , as seen in fig1 . as shown , both 1 re and 1 rc are continuously variable , to change the overall gain of the block . the voltage gain , a , is given by equation 1 , where “ gm ” refers to the transconductance of transistors 1 q 1 and 1 q 2 . a = 1  rc 1 / gm + 1  re ( eq . 1 ) as can be seen , if the gm of the transistors is high enough , a is set by 1 rc / 1 re . this allows the gain to be affected by varying either of these quantities , depending on specific desired qualities . to reach maximum gain ( amax ), resistor 1 rc is placed at its maximum value and resistor 1 re at its minimum . gain reduction from amax is accomplished by first increasing 1 re and then decreasing 1 rc . varying these resistances produces other effects , as well . for a given bias current through transistors 1 q 1 and 1 q 2 , increasing 1 re decreases gain . additionally , the third - order output intercept point ( oip 3 ), which is a chief measure of linearity , remains relatively unaffected , while the third - order input intercept point ( iip 3 ) increases . the noise figure of the device increases approximately one - half db per db of gain decrease . decreasing 1 rc decreases gain for a given bias current , and also reduces oip 3 . however , iip 3 remains constant , while the noise figure increases a full db per db of gain decrease . as can be seen in fig2 these behaviors cause distinctly different operating characteristics , depending on the gain selected . region one behavior is exhibited while changing 1 re , while region two has 1 rc changing . these two regions define two different applications for the tuner system as a whole . when the vlna is supplied by a cable system , a multitude of carriers exist at its input , each with a similar limited power range . these multiple signals cause a large number of possible cross - modulated products , requiring very high output linearity , or oip 3 , in the amplifier . region one is defined such that it encompasses the range of power supplied from different cable systems . when the vlna is fed by an antenna , the amplifier must deal with far fewer carriers which are typically tightly regulated as to channel spacing and power , such that channel - to - channel interference is reduced thereby reducing the need for high linearity in the front end . a single channel , however , may contain much higher power than would be seen in a cable system thereby requiring a much lower level of gain . in this case the noise figure may be degraded by a larger amount , but a larger input linearity , or iip 3 , must be maintained to avoid input compression . region two shows these characteristics . the above observations about input and output intercept show general trends that will occur if the 1 rc and 1 re resistances are varied linearly , and if the resistors themselves remain non - distortive . the distortion due to the non - constant gm of the bipolar transistors will then dominate . however , anything with a transconductance that can be changed , i . e . 1 rc and 1 re , will be an active device , and have non - linearities of its own which must be controlled . while simple in concept , changing 1 rc and 1 re in an analog and predictable manner is quite difficult . as will be discussed in more detail hereinafter , the circuit uses a network of resistors and mos devices to overcome this difficulty . fig3 and 4 illustrate a preferred embodiment of resistors 1 rc and 1 re , respectively , which are variable , highly linear resistors . the nodes “ ve ” and “ vc ” correspond to the respective points in fig1 . the control voltages vp1 , vp2 , vp3 , change the effective resistance of 1 rc by changing the gate voltages of pmos devices 3 mp 1 , 3 mp 2 , 3 mp 3 , etc ., and voltages vn1 , vn2 , vn3 , etc ., likewise control 1 re ( fig4 ). all subsequent discussion will describe 1 re , which uses nmos transistors . the operation of 1 rc ( fig3 ) may be understood by inverting the sense of the described control voltages vp1 , vp2 , vp3 , etc . ( discussed with respect to fig6 and 7 ). to set 1 re to its minimum resistance , all of the vnx ( where x can be any number 1 , 2 , 3 , etc .) control lines are set to the highest available voltage . due to bias conditions on ve and the choice of values of rnx , all of the mos devices will be in a triode mode of operation . this gives a predictable drain - to - source resistance , inversely proportional to the gate voltage . equation 2 provides a first order approximation of the equivalent resistance rds provided by an nmos , where vth is the threshold voltage of the device , and c is a constant depending on process and transistor geometry . rds = 1 c * ( vnx - vth ) ( eq . 2 ) the resistance of 1 re is increased by changing the vnx control lines in a successive manner . first , vn1 is gradually reduced , then vn2 , then vn3 , etc ., so as to reduce the voltage vnx thereby increasing the effective resistance of the mos device . but , the overall resistance is also affected by resistor rnx , which has several effects . by limiting the contribution of total resistance of the mos devices , it reduces the sensitivity of resistor 1 re to the control voltage , reduces the effect of the mos &# 39 ; s nonlinearity , and helps confine the transistors to the triode mode of operation . fig6 shows the method of changing the vnx control lines . 1 re &# 39 ; s resistance is increased by changing the vnx control lines in a successive manner . when reducing the amplifier &# 39 ; s gain from its maximum point , first vn1 is gradually reduced , then vn2 , then vn3 , etc ., continually increasing 1 re &# 39 ; s effective resistance . 1 rc &# 39 ; s effective resistance is decreased after 1 re reaches its effective maximum by subsequently reducing the vpx control lines . fig6 illustrates the response of the gain control circuitry to a differential control voltage . fig7 shows a simplified diagram of the control circuitry for the voltages shown in fig6 . as shown , the control signal is applied to a fully differential amplifier 7 ad 1 with gain ks , which produces signal vc . amplifier 7 ad 1 sets the sensitivity of the vlna &# 39 ; s gain to the applied differential control voltage vcontrol . a larger ks makes the vlna &# 39 ; s gain more sensitive with respect to vcontrol . control voltage vc is then distributed to separate amplifiers , 7 an 1 to 7 ap 3 , each controlling a vnx or vpx control line contained in the vlna amplifier core . each amplifier has an individual input offset voltage represented by a discrete voltage source at its input . the offset voltages are increased successively , starting with amplifier 7 an 1 and offset voltage von1 , and ending with amplifier 7 ap 3 with offset vop3 . the gradually increasing offset voltages set the point where each control line will begin to change , or “ breaks ”. also note that each amplifier has an individual gain knx or kpx , which sets the slope of the corresponding control line vnx or vpx during its transition . the amplifiers have a high output swing ( from ground to vcc ) to correctly drive the mos gates they control . returning now to fig1 the steady - state bias current 1 c 1 and 1 c 2 through transistors 1 q 1 and 1 q 2 is determined by the value of 1 re and the voltage applied at vb . if vb is set to a constant value , 1 c 1 will be reduced as 1 re is increased . this would further reduce the gain of the amplifier ( gm would decrease ) and reduce oip 3 . to keep a constant oip 3 , a constant bias current must be maintained . as a result , when changing 1 re , vb must be changed appropriately . fig5 shows the circuit which generates voltage vb . resistors 5 rb , 5 re and transistor 5 q 1 are sized to match similar components in the circuit of fig1 . current 51 c is the desired bias current . the actual current 1 c 1 and 1 c 2 may differ slightly due to matching of the devices . buffer amplifier 501 drives vb , with 5vb as its input . although the present invention and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims . moreover , the scope of the present application is not intended to be limited to the particular embodiments of the process , machine , manufacture , composition of matter , means , methods and steps described in the specification . as one of ordinary skill in the art will readily appreciate from the disclosure of the present invention , processes , machines , manufacture , compositions of matter , means , methods , or steps , presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention . accordingly , the appended claims are intended to include within their scope such processes , machines , manufacture , compositions of matter , means , methods , or steps .