referring to fig1 , a block diagram illustrating a microprocessor 100 according to the present invention is shown . microcode memory 104 stores microcode instructions 108 that are provided by the microcode memory 104 to execution units 112 in response to microprocessor 100 receiving user program instructions . although not shown , microinstructions from the other sources are also provided to the execution units 112 for execution , such as from an instruction translator or instruction cache ( not shown ) of the microprocessor 100 . in one embodiment , the execution units 112 execute microinstructions in an out of order fashion . the microprocessor 100 also includes a reorder buffer 122 coupled to the execution units 112 . the microprocessor 100 allocates an entry 124 / 126 in the reorder buffer 122 for each microinstruction issued to the execution units 112 , such as microcode instructions 108 . along with each microcode instruction 108 , the microprocessor 100 provides to the reorder buffer 122 the address of the microcode instruction 108 in the microcode memory 104 and an indication that the microcode instruction 108 was supplied by the microcode memory 104 rather than from another instruction source . after the execution units 112 execute microinstructions , they update the status 114 of the executed microinstructions within the reorder buffer 122 . this enables the reorder buffer 122 to insure that microinstructions are retired in program order . specifically , each clock cycle , the reorder buffer 122 checks the status 114 of the oldest microinstruction therein to see whether it has completed execution and is therefore ready to be retired , shown in fig1 as the microinstruction in entry 126 . the reorder buffer 122 also contains a microcode instruction address register 128 . the microcode instruction address register 128 stores the address of a microcode instruction 108 in microcode memory 104 for which it is desired to measure the number of times the microcode instruction 108 is executed . the microcode instruction address register 128 is writeable by a user program . in one embodiment , when a program executes a write msr ( wrmsr ) instruction , the execution units 112 write a microcode instruction address 118 specified by the wrmsr instruction to the microcode instruction address register 128 . a comparator 138 compares a compare address 136 provided from the microcode instruction address register 128 with a retire address 134 provided from the retired instruction entry 126 of the reorder buffer 122 to determine if the address of the microinstruction being retired matches the microcode memory address 136 programmed into the microcode instruction address register 128 . the comparator 138 produces a positive match 142 if the compare address 136 is the same as the retire address 134 , and produces a negative match 142 if the compare address 136 is not the same as the retire address 134 . an address match counter 144 increments its current count every time it receives a positive match 142 . in this way , the address match counter 144 stores a count equal to the number of times a microcode instruction 108 at a location in microcode memory 104 specified by the compare address 136 is retired . in one embodiment , the address match counter 144 is incremented if it receives a positive match 142 only if the above - mentioned indication indicates that the retired microinstruction 126 was sourced by the microcode memory 104 . in one embodiment , the reorder buffer 122 capable of retiring the oldest n microinstructions 126 in the reorder buffer 122 , where n is design dependent . in one embodiment , up to three microinstructions 126 are retired at the same time , thus generating n retire addresses 134 . in such an embodiment , the reorder buffer 122 includes n comparators 138 , each configured to compare a respective retire address 134 with the compare address 136 . if any of the comparators 138 generates a positive value , the counter 144 increments its count . the address match counter 144 provides its count 146 to the execution units 112 . in one embodiment , a user program executes a read msr ( rdmsr ) instruction to read the matched addresses count 146 from the counter 144 . in one embodiment , the address match counter 144 is initialized to a count value of zero when the microcode instruction address 118 is programmed into the microcode instruction address register 128 . referring now to fig2 , a flowchart illustrating operation of the microprocessor 100 of fig1 according to the present invention is shown . flow begins at block 204 . at block 204 , a write msr ( wrmsr ) instruction writes a microcode instruction address 118 to the microcode instruction address register 128 . the microcode instruction address 118 is the address of an instruction in microcode memory 104 . it is desired to count how many times the instruction at the microcode instruction address 118 is executed by the microprocessor 100 . the wrmsr instruction may be part of a user program . flow proceeds to block 208 . at block 208 , in response to the write msr ( wrmsr ) instruction writing a microcode instruction address 118 to the microcode instruction address register 128 in block 204 , the microprocessor 100 clears the address match counter 144 . clearing the address match counter 144 initializes the count to a zero value . flow proceeds to block 212 . at block 212 , a microsequencer of a microcode unit ( not shown ) of microprocessor 100 fetches microcode instructions 108 from the microcode memory 104 and sends the microcode instructions 108 to the execution units 112 . flow proceeds to block 216 . at block 216 , the execution units 112 execute the microcode instructions 108 and subsequently update the status 114 of the executed microinstructions in their associated entries 124 / 126 of the reorder buffer 122 . flow proceeds to block 218 . at block 218 , the reorder buffer 122 retires the oldest microinstruction 126 in reorder buffer 122 . in one embodiment , the reorder buffer 122 can simultaneously retire a plurality of microinstructions 126 , as discussed above . flow proceeds to block 224 . at block 224 , the comparator 138 compares the retire address 134 of the retired microinstruction 126 with the compare address 136 in the microcode instruction address register 128 to generate the match signal 142 to indicate whether the address 134 of the retiring microinstruction 106 is the same as the compare address 136 in instruction address register 128 . flow proceeds to decision block 228 . at decision block 228 , if the addresses compared at block 224 match , flow proceeds to block 232 ; otherwise , flow proceeds to block 212 where the process is repeated . at block 232 , the microprocessor 100 increments the address match counter 144 , in response to receiving a positive match 142 from the comparator 138 . flow proceeds to block 212 , where the process is repeated . referring now to fig3 , a block diagram illustrating a microprocessor 300 according to an alternate embodiment of the present invention is shown . the embodiment shown in fig3 is similar to the embodiment shown in fig1 and like - numbered elements are similar . differences between the embodiment of fig3 and the embodiment of fig1 will now be described . in the embodiment of fig3 , the reorder buffer 122 contains an instruction mask register 308 . the instruction mask register 308 stores an address mask 312 that is used to mask off bits of the compare address 136 and the retire address 134 before being compared by the comparator 138 . the consequence is that a positive match 142 indicates that a microcode instruction 108 was retired whose microcode memory 104 address is within a range of addresses specified by the combination of the compare address 136 and the address mask 312 , rather than indicating that a microcode instruction 108 was retired whose microcode memory 104 address matches a particular address of the microcode memory 104 as with the embodiment of fig1 . the instruction mask register 308 is writeable by a user program . in one embodiment , when a program executes a wrmsr instruction , the execution units 112 write an instruction mask address 304 specified by the wrmsr instruction to the instruction mask register 308 . although embodiments have been described in which the counter measures the actual execution of microcode instructions , other embodiments are contemplated in which the counter 144 measures the fetching of microcode instruction from the microcode memory 104 , which may be different from the actual execution thereof , such as due to speculative execution by the microprocessor 100 . additionally , although embodiments are described that include a single microcode instruction address register 128 , comparator 138 , and address match counter 144 , other embodiments are contemplated in which the microprocessor 100 includes multiple of these elements to enable counting executions of more than one microcode instruction within the microcode memory 104 . while various embodiments of the present invention have been described herein , it should be understood that they have been presented by way of example , and not limitation . it will be apparent to persons skilled in the relevant computer arts that various changes in form and detail can be made therein without departing from the scope of the invention . for example , software can enable , for example , the function , fabrication , modeling , simulation , description and / or testing of the apparatus and methods described herein . this can be accomplished through the use of general programming languages ( e . g ., c , c ++), hardware description languages ( hdl ) including verilog hdl , vhdl , and so on , or other available programs . such software can be disposed in any known computer usable medium such as semiconductor , magnetic disk , or optical disc ( e . g ., cd - rom , dvd - rom , etc .). embodiments of the apparatus and method described herein may be included in a semiconductor intellectual property core , such as a microprocessor core ( e . g ., embodied in hdl ) and transformed to hardware in the production of integrated circuits . additionally , the apparatus and methods described herein may be embodied as a combination of hardware and software . thus , the present invention should not be limited by any of the herein - described exemplary embodiments , but should be defined only in accordance with the following claims and their equivalents . specifically , the present invention may be implemented within a microprocessor device which may be used in a general purpose computer . finally , those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the scope of the invention as defined by the appended claims .