referring now to the drawings , this invention finds utility in a digital switching system known as system ` x `. details of the digital switching sub system of system ` x ` are disclosed in an article by a . s . philip in the publication , systems technology no . 32 september 1979 , and it is in this system that the present invention is embodied by way of illustrative example . referring to fig1 this shows a block schematic diagram of a line frame . the main feature of this arrangement is the switchblock or switching network swn which is duplicated for security purposes . it will be seen that two separate identical networks are provided each comprising receive time switch rx , a central space switch csw and a transmit time switch tx all of which are interconnected . each of these blocks have their own control / switch interfaces csi which give access to their respective general processor units gpu . on the receive side rx of the switching network swn there is a 40 . 96 m bit / sec optical fibre interface ofi and it will be seen that while the line communication multiplexers lcm are duplicated , and are therefore secured , the remote terminal units rtu , the subscribers line units slu , and the digital line termination units are not , and are therefore , unsecured . on the transmission tx side of the switching network swn the arrangement of the various units is similar to the receive side . on this side of the switching network swn is shown a peripheral card controller pcc associated with the peripheral subscribers line unit slu . it is the pcc which is arranged to detect and validate synchronisation signals and to distribute such signals and clock signals from one serial multiplex data stream only to the unsecured peripherals . the source of the clock and synchronisation signals is the triplicated waveform generator wfg and the wveform distribution arrangements wfd1 and wfd0 which will now be discussed . referring to fig2 the waveform generation and distribution arrangements comprise triplicated waveform generators wfg1 , wfg2 and wfg3 driving duplicated waveform distribution wfd0 and wfd1 . each waveform generator contains the following : ( i ) an oscillator capable of locking on to several external references osc1 , osc2 , and osc3 . ( ii ) a selection mechanism for choosing the appropriate reference ref for the locked oscillator . ( iii ) a selector , for selecting one of the selectors sel1 , sel2 , and sel3 when one of them agrees with the other two selectors to determine which oscillator output will drive the waveform distribution . ( i ) majority decision logic ( not shown ) to process the three clocks received from the selectors sel1 , sel2 and sel3 . ( ii ) generation means ( not shown ) for generating clocks , in addition to this provided by the used waveform generator . the waveform generator provides an 8 khz waveform and a 500 hz waveform to the waveform distribution which generates the other frequencies required . the following features are provided to ensure the secure operation of the waveform generators and the waveform distribution . the waveform generator is able to lock to one of two external reference source types ref , 500 hz which is derived from a host subsystem and 8 khz which is derived from a digital line termination subsystem . if none of the above are available , then the waveform generator uses an internal oscillator . two oscillators are required , one of which normally has its output distributed to switch and control planes . this oscillator is termed the worker . the other is termed the standby . note that although there are three waveform generators , ie . three oscillators , only two are selectable . the single fault philosophy indicates that the third is never uses . triplicated selectors are provided , one on each waveform generator . they decide which of the two oscillators is worker and which is standby . they also decide whcih external reference ( if any ) the worker oscillator will follow . the standby oscillator follows the worker oscillator . timing information is distributed across the control / switch or switch / peripheral boundaries by encoding it into a 2 . 048 mb / s data stream . this information is passed , via the waveform distribution , to the duplicated system eventually meeting at a common point on the peripheral known as the peripheral card controller ( pcc ). data and synchronisation information is passed across the control / switch and switch / peripheral boundaries by a 40 . 96 mbit / s serial highway consisting of various multiplexed data streams . at the receiving end of the highway any frequency below 40 . 96 mhz can be derived by binary division of the 40 . 96 mhz clock . however to achieve synchronisation between planes a low frequency sync pattern is also transmitted . the sync pattern is generated by the control interface to the switch ( cis ), fig1 and consists of two bit - interleaved 1 . 024 mbit / s stream to produce the 2 . 048 mbit / s data . each 1 . 024 mbit / s stream is as follows : ( a ) one stream comprises of continuous 1010101010 etc . this provides a simple pattern for a sync detector to lock onto when searching a multiplexed stream for the 2 . 048 mbit / s sync data , as well as providing a rapid indication of errors . ( b ) the other stream comprises four patterns each of 8 bits representing the low frequency synchronisation signals , e . g . frame start and multiframe sync , these are pattern a , pattern b , pattern 1 ( one ) pattern 0 ( zero ). pattern a is always preceeded by pattern 1 and are collectively referred to as sync a . pattern b is also preceeded by pattern 1 and are collectively referred to as sync b . sync a and sync b are separated by six pattern 0 &# 39 ; s . table 1______________________________________sync a z z z z z z sync b z z z z z z sync a______________________________________ -- -- -- time11111111001100s1 11111111110011s1 000ee000pat . 1 pat . a pat . 1 pat . b pat . zero______________________________________ bit e in pattern zero can be used in the transmit tx direction to convey additional information if necessary , however the pcc does not validate these bits . the sync a and sync b format are used to transmit the 8 khz and 500 hz synchronisation pulses . bit s is a binary coded pattern to identify the 500 hz sync signal as shown in table 2 : table 2______________________________________ s signal type______________________________________ 0 500 hz ( low ) 1 500 hz ( high ) ______________________________________ sync b is used as the system reference . sync a is phase displaced or skewed with respect to sync b by 1 / 2 ( one half ) frame . thus the 2 . 048 mbit / s bit - interleaved pattern takes the form shown in table 3 : table 3__________________________________________________________________________bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 // bit128 bit129 bit130sync a 0 sync a 1 sync a 0 // sync 3 0 sync bbit 0 bit 1 bit 2 // bit 0 bit 1__________________________________________________________________________ -- -- -- time__________________________________________________________________________ some synchronisation patterns are internally looped around to provide synchronisation back to the source . this ensures that timing on a particular interface is controlled from one point . referring to fig3 which shows a block schematic of a portion of the peripheral card controller pcc , concerned with the present invention . the three main blocks shown are the sync detect and validate ( plane ` o `) sdvo the synch detect and validate ( plane ` 1 `) sdv1 and the select and distribute sync and clocks sdsc . input to the pcc is taken from the duplicated area of the switching network ( see fig1 ). extracted from the data stream of plane ` 0 ` data - cont - sync - 0 and 8 khz - clko and from plane ` 1 ` data - cont - sync - 1 and 8 khz - clk1 . these represent 2 . 048 mbit / sec control ( cont ) and synchronisation ( sync ) frame structured serial multiplex streams while the data represents an 8 . 192 mbit / sec serial multiplex comprising four 2 . 018 mbit / sec streams which are bit interleaved whereas the 8 khz ( clko ) ( clk1 ) are 8 khz clock signals . these signals are fed to the appropriate sync detect and validate blocks sdvo and sdv1 respectively and also to demultiplexers dem0 and dem1 respectively ( not shown ) concerned with other functions within the peripheral card controller . in the two sync detect and validate blocks clock clk0 and clk1 are detected together with frame sync pulses fsp0 and fsp1 in addition to with low frequency sync pulses lsp0 and lsp1 . these are input to the select and distribute sync and clocks block sdsc where the various signals are selected from one only of the serial multiplex data streams for distribution to the peripheral card controller and the peripheral to which it is associated . some signals are indicated as local clock lclk , low frequency signal lfs , clock and sync clk / sync . ce indicates clock error signals and cts indicates current time slot signal . it should be understood that the blocks sdv0 , sdv1 and sdsc of the pcc ( see fig3 ) contain various standard type counters , registers d - type toggles together with standard logic mechanisms . as will be seen from the control algorithm progression diagrams ( fig4 to fig1 a list of which follows ) a synchronous counter is provided including frame , comparison and bit ( 3lsb ) sections in addition to sixteen bit a and b pattern registers . drop - out counters ( d / o ), slip counter ( decode 7 ) are also provided together with numerous memory devices ( 1 - 0 - 1 not ok ). etc . if the sync a and sync b waveforms are generated by a single unit then one failure can generate phase problems . if the wrong clock is used to drive the link the gaps between sync a and sync b will not contain the correct number of bits . to ensure that the peripheral card controller can have confidence in the integrity of the phase of the synchronisation information , each waveform distribution arrangement wfd has two independent majority voters receiving the three 8khz clocks from the three selectors . one majority voter causes sync a to be generated , and the other majority voter causes sync b to be generated . the sync a and sync b waveforms are independently inserted into the output o / po ( o / op1 for the plane 1 wfd ). therfore , any single fault in the generation of a sync pattern or the frequency synthesis function performed by the wfd will cause either a pattern to be corrupted or displaced . the recipient of the waveform is able to determine if it is a good or corrupt waveform . the waveform can be multiplexed and demultiplexed and passed through several distribution stages with differing rates without its integrety being lost . at a peripheral card controller pcc , data is not necessarily taken from the same plane as the clock and synchronisation . the two planes therefore must be held within a defined relative phase relationship which ensures that if an 8 khz reference is corrupted and therfore its phase position questionable , it can be detected and rejected . if the sync a and sync b relationship / checks fail the whole synchronisation stream is rejected . if a worker oscillator fails the synchronisation streams are swopped at the peripheral card controller pcc . the following text is a description of the progression charts , which are defined on the following figures : ______________________________________sync detect outer loop fig4 - 0 - 1 fig5 - 0 - 1 fail fig6 pattern fig7 pattern check fig8 multiframe b fig9 pattern b fig1 pattern 0 fig1 pattern 1 fig1 multiframe a fig1 pattern a fig1 end pattern 1 fig1 fault fig1 slip fig1 time 7 fig1 clock selection fig1 ______________________________________ the 2 mbit / s synchronisation data from the waveform distribution system will contain the following sync patterns : this pattern will be an alternating 0 / 1 pattern in all odd numbered bits in the sync stream . this will provide a simple sync pattern for the sync detector to lock onto in the 8 mbit / s data from the switch . this pattern will be a frame and multi - frame reference in the even numbered bits to indicate the position of the tx frame sync . this pattern will be a frame and multi - frame reference marker in the even numbered bits to provide a reference by which sync pattern a may be validated . a pattern of zeros in the even numbered bits occurring between sync pattern a or b and the next pattern 1 . a pattern of ones in the even numbered bits that preceed a sync pattern a and a sync pattern b . after sync loss or power - on the sync detect function of the pcc searches the 8 mbit / s data from the switch for the 2 mbit / s sync data stream . having found the identificaition pattern , pattern a , pattern b , ones and zeros will then be looked for checking that they occur at the correct time . if they continue to be correct for three frames , the pcc will be considered to be in sync and the ok signal at 8 khz will continually toggle ; if not , the sync detect will return to search for the identification pattern in the 8 mbit / s data . once in sync , the identification pattern may contain bits in error in any one frame without loss of sync . if there are a total of four failures in the a , b , ones or zeros patterns since the last good frame ( i . e . one in which a , b , ones and zeros were present with no bit errors and at the correct separation ), then sync is lost and the ok 8 khz signal will be held at a constant level . the algorithm will revert to ` looking for b ` for two frames and if not found will again search for the identification pattern . to find 500 hz sync , the sync detect looks for the falling transition in the 500 hz bit in pattern b and uses this to synchronise its counter and set 500 hz in sync . whilst in sync the 500 hz in pattern a and pattern b will be compared with the predicted state of the 500 hz from the counter . should a second fault occur before the second falling edge of the 500 hz after the first fault , this will cause loss of 500 hz sync . only when in sync will the 500 hz provide an &# 34 ; an ok signal at 500 hz &# 34 ; signal . when in sync , one sync detector will set a cross - coupled nand gate and the other detector on the other plane will clear it , so that when both detectors are seeing the same data the output will be a 500 hz square wave . the two ok signals will be multiplexed into a single ok signal for use by the clock selection function . the pcc has two modes of clock selection , master mode and slave mode . in slave mode an input is used to force the clock selection a particular way , however , in master mode the pcc itself determines which clock to select . the following text describes the master mode of operation . the pcc achieves clock selection by using information supplied by the plane 0 sync detector and the plane 1 sync detector . for the purpose of clock selection each sync detector has three states : commencing from ` no sync found ` the detectors search their respective 8 mbit / s data inputs from the switch plane for the 8 khz sync data . once a detector gets to ` 8 khz sync found ` it will try and achieve ` 500 hz sync found `. the two detectors are totally independent such that the progress of one through the states has no effect on the other . finding and losing 500 hz sync has no effect on ` 8 khz sync found ` and if 8 khz sync is lost then 500 hz sync is also lost . ______________________________________no 8 khz sync → 8 khz sync → 8 khz syncno 500 hz sync ← no 500 hz sync ← 500 hz sync______________________________________state 1 state 2 state 3______________________________________ each sync detector has an input into the clock selection . if the detector is in ` state 1 ` then this input is stead state , ie fixed at either high or low . however , if in ` state 2 ` or ` state 3 ` this input pulses . the pulse pattern is repreated every 125 μs and there are a possible eight pulses . seven of these occur if ` state 2 ` is reached and the eighth only occurs if ` state 3 ` is achieved . plane 0 pulses high and plane 1 pulses low such that the selector will usually see a rising edge alternatively from plane 0 and then from plane 1 . if the selector sees two or more consecutive rising edges from the same plane then it will select the clock from that plane . for example , if plane 0 is in ` state 2 ` and plane 1 has just achieved ` state 3 ` then plane 0 will not have the eighth pulse whereas plane 1 will and two consecutive edges will appear on the plane 1 input causing the selector to choose plane 1 clocks . if plane 1 subsequently fell back to ` state 2 ` and plane 0 was still at ` state 2 ` the selector would not be affected , however if plane 1 went to ` state 1 ` then plane 0 would supply two consecutive edges and the selector would change to choosing the clock from plane 0 . the selector will only change to the other plane if that plane supplies two consecutive edges . fig2 shows the logic diagram for a periphereal card controller pcc clock selector . the two signals a and b represent ok signals and are processed by the logic circuitry to form the select signal c . it will be appreciated that the logic used is standard logic and its function will readily be appreciated by those skilled in the art . the above description is not intended to limit the scope of the present invention . alternative implementations may be envisaged by those skilled in the art . for example , information may be transmitted at different rates and over different mediums than those discussed , and each rate can be detected and checked in a similar manner to that already described .