fig4 a illustrates an example of a parity control matrix m for calculating the detection bits for 16 - bit words , in an error correction / detection code according to the present invention . the number of detection bits is equal to 6 and matrix m is a matrix of dimension 6 × 16 . each column of matrix m is different from another and the columns are linearly independent two by two . further , each column of matrix m is complementary to an immediately adjacent column , except for the first two columns . matrix m can be decomposed in eight couples a 1 of two adjacent columns , i ranging from 0 to 7 . couple ao corresponds to the columns of rank 0 and of rank 1 , couple a i to the columns of rank 2 and of rank 3 , etc . in the non - limiting example of matrix m shown in fig4 a , the two columns of a couple a i are complementary , except for couple a 0 . in fig4 a , the couples a i are formed as follows . for couples a 1 to a 7 , the first four elements of the first column of a couple correspond to the binary representation of rank i of couple ai . thus , the first column of couple a 3 has its first four elements equal to “ 0011 ”, which is the binary representation of number 3 . the first four elements of the first column of couple a 0 ( column of rank 0 ) are chosen to be equal to “ 0011 ”. this choice is not critical . the first four elements of the column of rank 0 may indeed have any value , provided that the column of rank 0 once completed is different from any other column of matrix m or from the columns relative to the detection bits of the matrix used for the decoding , m ′, which will be described hereafter . the retained choice (“ 0011 ”) has the advantage of using a small number of “ 1s ”, which simplifies the coding and decoding circuits , the number of “ 1s ” corresponding , as will be seen hereafter , to the number of adders in the circuit . the last two elements of each first column of a couple a i ( columns of even rank ) are equal to “ 10 ”, except for the first and last couples a i ( columns of rank 0 and 14 ), where they are equal to “ 01 ”. except for the first couple , a 0 , each second column of a couple a i is complementary to the first column of the couple . in other words , except for the column of rank 1 , the elements of each column of odd rank are the complements to two of the elements of the immediately preceding column of even rank , and vice versa . for example , the elements of the first column of couple a 4 are equal to “ 010010 ” and the elements of the second column of this couple are “ 101101 ”. in fig4 a , couple a 0 has “ 001101 ” as its first column and “ 111110 ” as its second column . it should be noted that the penultimate line of matrix m , referred to as k , having as elements “ 0110101010101001 ”, is complementary to the last line of matrix m , referred to as l , having as elements “ 1001010101010110 ”. this provides advantages , as will be seen hereafter . when matrix m is multiplied by a column vector of sixteen components corresponding to the bits of the word to be coded , six detection bits c 0 – c 5 are obtained , which are added to the word to be coded to form a 22 - bit coded word . fig4 b illustrates matrix m ′ used for the decoding . at the decoding , a vector having 22 components , corresponding to the 22 bits of the word to be decoded ( 16 data bits and 6 detection bits after any processing , for example , a storage in a memory or a transmission ), is multiplied by matrix m ′ to form a syndrome having six components s 0 – s 5 . matrix m ′ is a matrix of dimension 6 × 22 . in matrix m ′, the first sixteen columns form a block identical to matrix m . the first five lines of the five next columns ( ranks 16 to 20 ) form a block a of dimension 5 × 5 formed by a diagonal matrix which only includes “ 1s ” on its main diagonal and “ 0s ” elsewhere . under block a , the elements of the last lines of the columns of rank 16 to 20 are chosen to be equal to “ 11110 ”, to correspond to the inverses of the elements of the last line of block a (“ 00001 ”). the last column of matrix m ′, which enables correcting an error on the sixth detection bit , includes “ 0s ” on the first five lines and a “ 1 ” on the last line . it should be noted that , in matrix m ′, the columns corresponding to the data bits are complementary two by two , except for the first two . further , the last two lines are also complementary . if the sum modulo 2 of the last two syndrome components , s4 and s 5 , is calculated , the sum modulo 2 of all the data bits and the detection of the word to be decoded , that is , a total parity bit p r , are obtained . total parity bit p r is here simply obtained and is substantially calculated in twice as less time as in the case of the corresponding hamming code . further , upon coding , conversely to the corresponding hamming code , no total parity bit p is calculated . total parity bit p r is used as follows . if the syndrome is equal to the zero vector , there are no errors , either in data bits , or in the detection bits . if the syndrome is different from the zero vector and total parity bit p r is equal to 1 , this means that there has been a single error , which can be corrected . indeed , the syndrome components , in this case , correspond to the elements of the column of matrix m ′ corresponding to the erroneous bit . if the syndrome is different from the zero vector and total parity bit p r is equal to 0 , two errors are present , which are detected . fig5 a schematically shows the principle of a circuit used for the coding , enabling calculating the detection bits from the data bits . coding circuit 1 includes 16 inputs e 0 to e 15 , which receive the 16 data bits x 0 to x 15 of the word to be coded . circuit 1 also includes 6 outputs c 0 to c 5 providing the six detection bits . each input e 1 is connected to a column of rank i of the circuit . each output c j is connected to a line of rank j . an adder modulo 2 g i , j schematically indicated herein by a circle marked with a cross may be present at the intersection of column i and of line j . the adders modulo 2 may be any adders , and formed for example by xor gates . as shown in fig5 b , adder g i , j includes two inputs e i , j 1 and e i , j2 , often respectively called e 1 and e 2 hereafter , for simplification . input e i , j 1 is connected to input e i and input e i , j 2 receives the signal present on line j to the left of adder g i , j . adder g i , j also includes an output s i , j located on line j to the right of adder g i , j , often more simply called s hereafter . when there is no adder at the intersection of column i and of line j , column i and line j cross with no influence upon each other . this means that the bit provided to the concerned input is not used to calculate detection bit c j . an additional column , a , located to the left of the column of rank 0 connects input e 2 of each first adder of a line to ground ( gnd ). the operation of circuit 1 will be explained for the calculation of detection bit c 4 , corresponding to the line of rank 4 . starting from the left , the first encountered adder is adder g 1 , 4 . input e 2 of adder g 1 , 4 is grounded , via column a , and input e 1 of adder g 1 , 4 receives data bit x 1 via input e 1 of the circuit . at the output of adder g 1 , 4 , s = 0 ⊕ x 1 , that is , x 1 . the signal provided by adder g 1 , 4 reaches input e 2 of adder g 2 , 4 , which calculates x 1 ⊕ x 2 . the calculation carries on until reaching adder g 15 , 4 , which performs the addition modulo 2 of the result provided by adder g 12 , 4 and data bit x 15 . thus : c 4 = x 1 ⊕ x 2 x 4 ⊕ x 6 ⊕ x 8 ⊕ x 10 ⊕ x 12 ⊕ x 15 , which does correspond to the multiplication of the fifth line of matrix m by a vector having as components the bits of the word to be coded . generally speaking , circuit 1 has the structure of matrix m , the circuit lines and columns corresponding to the lines and columns of matrix m , an adder modulo 2 being located where matrix m includes a “ 1 ”. in prior art , each adder takes up a space corresponding to the interval between two circuit columns . the advantage provided by the fact that adjacent columns of matrix m are complementary will now be described . indeed , in the present invention , an adder modulo 2 of circuit 1 is not contiguous on both sides to another adder , except , possibly , for the first two columns . as a result , such an adder can laterally occupy the place of two adders and be , for a same surface area of the circuit , twice as large as in prior art . the adder can then be optimally formed , and be much faster . fig5 c illustrates the line of rank 4 of circuit 1 , providing detection bit c 4 . each adder g i , j is shown in the form of a rectangular block . the first adder encountered is adder g 1 , 4 . its input e 2 ( e 1 , 4 2 ) is grounded via column a . its input el ( e 1 , 4 1 ) receives bit x 1 via input e 1 . in fig5 c , the columns of circuit 1 which are not connected to the input of an adder of the line of rank 4 are shown in dotted lines . output s i , j of each of the adders supplies input e 2 of the next adder or , for the last adder , the circuit output . the line of rank 4 of the coding circuit includes eight adders ( g 1 , 4 , g 2 , 4 , g 4 , 4 , g 6 , 4 , g 8 , 4 , g 10 , 4 , g 12 , 4 , and g 15 , 4 ), the data bits used to calculate detection bit c 4 being x 1 , x 2 , x 4 , x 6 , x 8 , x 10 , x 12 , and x 15 . all the adders of the line of rank 4 have a double surface area as compared to what is provided in prior art . although in fig5 c , the input e 1 of an adder g i , j is located either to the left , or to the right of the adder , all circuit adders may have the same physical structure . in this case , input e 1 is arranged at a same determined location of the adder , a set of vias or connections enabling the desired bit to supply the concerned input . in matrix m of fig4 a , the first two columns are not complementary . however , independently from this , the adders corresponding to the first two columns of circuit 1 may have the same size as the adders of the rest of the circuit . first , a problem is only posed when two consecutive “ 1s ” are present on the first two columns of a same line of the matrix . this only occurs for the lines of rank 2 and 3 . then , it is possible , even in these cases , to use adders having a size twice as large as in prior art . consider , for example , the case of the line of rank 3 . the first adder in the line , g 0 , 3 ( fig5 a ) is followed by adder g 1 , 3 . adder g 0 , 3 adds modulo 2 bit x 0 and 0 ( ground voltage ). adder g 0 , 3 outputs bit x 0 . its function thus only is to transmit the data bit that it receives to the next adder . in the present invention , the two adders g 0 , 3 and g 1 , 3 are replaced with a single adder , which is not grounded and receives on its two inputs bits x 0 and x 1 . thus , in fig5 d , which shows the line of rank 3 of circuit 1 , a single adder , referred to as g 0 - 1 , 3 replaces adders g 0 , 3 and g 1 , 3 of fig5 a . adder g 0 - 1 , 3 has two inputs e 1 and e 2 respectively receiving data bits x 0 and x 1 . adder g 0 - 1 , 3 outputs the sum modulo 2 of bits x 1 and x 2 . adder g 0 - 1 , 3 occupies the surface area of the two adders g 0 , 3 and g 0 , 1 . adder g 0 - 1 , 3 has the same size as the adders following it , that is , adders g 2 , 3 , g 5 , 3 , g 6 , 3 , g 9 , 3 , g 10 , 3 , g 13 , 3 , and g 14 , 3 , connected according to the above - discussed principles . the line of rank 3 of the circuit provides detection bit c 3 , which is the sum modulo 2 of data bits x 0 , x 1 , x 2 , x 5 , x 6 , x 9 , x 10 , x 13 , and x 14 . the first two adders of the line of rank 2 of fig5 a , g 0 , 2 and g 1 , 2 are similarly replaced with a single adder not shown , g 0 - 1 2 which is not grounded and receives on its two inputs data bits x 0 and x 1 . circuit 1 is thus formed of 48 adders ( 8 adders per line ), all having a same silicon surface area , which is twice that provided by prior art . each of the adders may have a more careful implementation and , due to the optimal individual performances of each of the adders , the calculation of the detection bits can be much faster . further , due to the fact that coding matrix m has two complementary lines , no total parity bit p is ever calculated upon coding . the 6 detection bits c 0 to c 5 may be calculated in parallel and added to the word to be coded with no additional time loss . fig6 schematically shows a circuit 10 used upon decoding . circuit 10 includes 22 inputs e ′ 0 to e ′ 21 receiving the 22 bits of the word to be decoded ( 16 data bits x ′ 0 to x ′ 15 and 6 detection bits c ′ 0 to c ′ 5 ). circuit 10 includes six outputs s 0 to s 5 , each providing a component of the syndrome . circuit 10 shown herein is directly made at the output of a memory , of which only a line 12 of 22 sense amplifiers sa 0 to sa 21 is shown . sense amplifiers sa i are each located at the end of a bit line , not shown ( two bit lines for a dram ), and each provide a bit of the word to be decoded . sense amplifiers sa 0 to sa 15 provide data bits x ′ 0 to x ′ 15 and sense amplifiers sa 16 to sa 21 provide detection bits c ′ 0 to c ′ 5 . decoding circuit 10 is formed on the same silicon chip as the memory in which the coded word is stored and may be an integral part thereof . each of inputs e ′ i of circuit 10 is spaced apart from another input by the interval separating two sense amplifiers sai . circuit 10 first includes , connected to inputs e ′ 0 to e ′ 15 , a block y formed of a regular paving of six lines of eight adders g ′ i , j each . the structure of block y is the structure of coding circuit 1 , the first 16 columns of matrix m ′ corresponding to matrix m . adders g ′ i , j of block y are connected in the same way as previously described in relation with fig5 a to 5d . an image of circuit 1 can besides be obtained by referring to block y , replacing the elements marked with a “ prime ” with elements with no “ prime ”. adders g ′ 1 , 0 , g ′ 1 , 1 , g ′ 1 , 4 and g ′ 0 , 5 , respectively corresponding to the first adders of the lines of rank 0 , 1 , 4 , and 5 , have an input connected to a ground line a ′ and an input connected , according to cases , to data bit x 0 or x 1 . the first adders of the lines of rank 2 and 3 , g ′ 0 - 1 , 2 and g ′ 0 - 1 , 3 , receive as an input the two data bits x 0 and x 1 . the other adders of block y , corresponding to the columns of rank 2 to 15 , include an input connected to the output of the immediately preceding adder and another input connected to one of the two inputs e ′ i likely to supply the adder . in addition to block y , circuit 10 includes a block z of ten adders connected to inputs e ′ 16 to e ′ 21 , in charge of carrying out the mathematical operations on the data bits . on the line of rank 0 of block z , there is a single adder , g ′ 16 , 0 , which receives the output of adder g ′ 15 , 0 on one input , and detection bit c ′ 0 on another input . the output of adder g ′ 16 , 0 supplies output s 0 of the circuit . adder g ′ 16 , 0 may occupy , if desired , a space extending over six columns of circuit 10 ( sense amplifiers sa 16 to sa 21 ). however , for practical reasons , adder g ′ 16 , 0 is of the same type as adders g ′ i , j of block y and takes up a surface area which is double that provided in prior art . the line of rank 1 of block z also includes a single adder g ′ 17 , 1 , of same surface area as adder g ′ 16 , 0 , receiving on its two inputs the output of adders g ′ 14 , 1 and detection bit c ′ 1 . the output of adder g ′ 17 , 1 supplies output s 1 of circuit 10 . line 2 of block z includes an adder g ′ 18 , 2 of same size as adder g ′ 16 , 0 or g ′ 17 , 1 , receiving on an input the output of adder g ′ 14 , 2 and on its other input detection bit c ′ 2 . adder g ′ 18 , 2 supplies output s 2 of the circuit . on the next lines of block z is adder g ′ 19 , 3 , of same size as adder g ′ 18 , 2 , receiving as an input the output of adder g ′ 14 , 3 and detection bit c ′ 3 . adder g ′ 19 , 3 supplies output s 3 of circuit 10 . the line of rank 4 of block z includes an adder g ′ 20 , 4 , receiving the output of adder g ′ 15 , 4 and detection bit c ′ 4 . adder g ′ 20 , 4 supplies output s 4 of circuit 10 . the last line of block z , of rank 5 , includes five adders which cannot each use a double circuit surface area . indeed , on this line , adder g ′ 14 , 5 of block y supplies an adder g ′ 16 , 5 followed , in this order , by adders g ′ 17 , 5 , g ′ 18 , 5 , g ′ 19 , 5 , and g ′ 21 , 5 . adder g ′ 21 , 5 supplies output s 5 of circuit 10 . adders g ′ 16 , 5 , g ′ 17 , 5 , g ′ 18 , 5 , and g ′ 19 , 5 , which respectively receive detection bits c ′ 0 , c ′ 1 , c ′ 2 , and c ′ 3 , cannot be wider than the interval separating two circuit columns . their width thus cannot be greater than that of a sense amplifier . adder g ′ 21 , 5 , however , receiving the output of amplifier g ′ 19 , 5 and detection bit c ′ 5 , may be as wide as two sense amplifiers and of a size similar to that of the adders of block y . the examination of fig6 shows that almost all adders of the decoding circuit occupy a surface area which is double that provided in prior art . adders of double surface area can be much faster than adders having half their surface area and thereby , the decoding circuit is much faster than in prior art . it should further be noted that , as much as concerns the coding circuit as the decoding circuit , the number of adders per line is reduced as compared to prior art . this results in an additional time gain . as a comparison , reference will be made to the last line of matrix h ″ of prior art ( fig3 a ), formed of 22 consecutive “ 1s ”. thus , the last line of the corresponding decoding circuit includes 22 small adders in series . in the present invention , with matrix m ′, the last line of the decoding circuit only includes 13 adders , 9 of which have a surface area which is double that of prior art . the time gain thus is present at two levels . indeed , in the present invention , not only are all adders more bulky and thus faster , but also is their number per line smaller . since the general calculation time corresponds to the sum of the processing times in each of the adders , the circuit according to the present invention is much faster and with much higher performances than the circuit of prior art . further , the more careful implementation of the adders of larger surface area enables them to be more reliable . of course , the code of the present invention is not limited to codes intended for 16 - bit words . indeed , it is possible , provided that at least two consecutive columns are complementary , which enables reducing the processing time of the adders concerned by these columns , to define codes enabling coding words having any number of bits . for example , it is possible to generalize matrix m of fig4 a to code any even number m of bits . number r of detection bits must be at least greater by 2 than the number necessary to binarily represent the number of bits of the word to be coded . preferably , r will be equal to its minimum value , to avoid making the code too heavy . thus , when m is equal to 16 , four bits are required to binarily represent sixteen possibilities and r is chosen to be equal to 6 , as seen previously . for m = 32 , the number of detection bits is chosen to be equal to 7 , 32 being equal to 25 . for m = 128 , 9 detection bits are required , and so on . to generalize matrix m , number r of necessary detection bits is first determined . then , matrix mm used for the coding is built , so that the first r − 2 elements of each column of even rank indicate , except for the first column , the rank of the couple to which the column belongs ( a couple ai , of rank i , is formed of the column of even rank 2 i and of the column of odd rank 2 i + 1 ; the rank of the first column is 0 , and that of the last columns is m − 1 ). the last two elements of the columns of even rank are equal to “ 10 ”, except for the column of rank 0 and the column of rank m − 2 , where they are “ 01 ”. the first column of matrix mm may be formed of r − 4 elements equal to “ 0 ”, followed by elements “ 1101 ”. the second column of matrix mm , of rank 1 , may be formed of r − 4 elements equal to “ 1 ”, followed by elements “ 1110 ”. the columns of odd rank , except for the column of rank 1 , are complementary to the immediately preceding column of even rank . it should be noted that the last line of matrix mm is complementary to its penultimate line . it should also be noted that the first r − 2 elements of the first column of matrix mm may be identical to the r − 2 elements of any column of matrix mm , at the following conditions : that the first column is different from all other columns of matrix mm ; the first four elements of the first column must not be all “ 0s ” and must include more than one “ 1 ”, so that the column is different from the columns of the matrix used upon decoding , which correspond to the detection bits . to form matrix m ′ m used for the decoding , parity control matrix mm is first taken , and completed to the right by a square sub - matrix r of dimension r × r . sub - matrix r includes “ 1s ” on its main diagonal , and “ 0 ” everywhere else except on its last line , the elements of which are the inverses of those of the penultimate line of sub - matrix r . the last line of sub - matrix r thus includes “ 1s ” everywhere except at the penultimate column . the code using matrixes mm and m ′ m has a minimum code distance equal to four . it enables correcting one error and detecting two errors . upon decoding , the obtained syndrome has r components . a total parity bit is obtained by adding modulo 2 the last two syndrome components . if the syndrome is the zero vector , there is no error . if the syndrome is different from the zero vector and the total parity bit is equal to “ 1 ”, there is a single error . this error is easily corrected since the syndrome corresponds to the matrix column having had its elements multiplied by the erroneous bit . if the syndrome is different from the zero vector and the total parity bit is equal to “ 0 ”, two errors are present . all adders of the coding circuit and almost all adders of the decoding circuit , respectively calculating the detection bits and the syndrome components by means of matrixes mm and m ′ m , may extend over two intervals separating two circuit columns and have a surface area which is double that provided by prior art . fig7 , as an example , illustrates a matrix m ′ 32 used to decode 32 - bit words . matrix m ′ 32 has dimension 7 × 39 . its 32 first columns correspond to matrix m 32 used upon coding . matrixes m 32 and m ′ 32 are formed on the model of what has been previously described . the corresponding coding and decoding circuits , not shown , are easily deduced from matrixes m 32 and m ′ 32 by means of the principles defined in relation with fig5 a - 5d and 6 . of course , the present invention is likely to have various alterations , modifications , and improvements which will readily occur to those skilled in the art . in particular , any line permutation in a parity control matrix according to the present invention is within the scope of the present invention and changes nothing to the code of the present invention . any column permutation in a matrix of the present invention is also within the scope of the present invention , provided that at least two consecutive columns remain complementary . number n of bits of the word to be coded may be even or odd . if number n is odd , a matrix mm such as described hereabove with an even m equal to n + 1 may for example first be formed . then , matrix m n to be used upon coding can easily derive from matrix mm by suppression of any column , for example , the first column . the present invention has mainly been described in the context of the storage of words in a memory . of course , the present invention also applies to any coding and decoding of words to which an error detection and / or correction code is desired to be assigned . for example , the present invention applies to transmission . such alterations , modifications , and improvements are intended to be part of this disclosure , and are intended to be within the spirit and the scope of the present invention . accordingly , the foregoing description is by way of example only and is not intended to be limiting . the present invention is limited only as defined in the following claims and the equivalents thereto .