referring now to fig2 , an exemplary computer system 90 is shown to illustrate the principles of the present invention . as shown in fig2 , computer system 90 comprises a plurality of processors 100 , each of which has an associated memory 125 and an input / output (“ i / o ”) controller 135 . in fig2 , the computer system 90 includes twelve processors 100 a - l for purpose of illustration . each processor preferably includes four ports for connection to adjacent processors . as such , each processor 100 can be connected to four other processors . the processors on both ends of the system layout ( e . g ., 100 a and 100 d ) wrap around and connect to implement a 2d torus - type connection . although twelve processors 100 a - l are shown in the exemplary embodiment of fig1 , any desired non - prime number of processors ( e . g ., 64 , 128 , 256 , etc .) can be included . as noted , each processor may have an associated i / o controller 135 . the i / o controller 135 provides an interface to various input / output devices such as disk drives 105 and 110 , as shown in the lower , left - hand corner of fig2 . data from the i / o devices thus enters the 2d torus via the i / o controllers . the system memory in computer system 90 comprises a distributed memory architecture , with the memory dispersed throughout the system . according to the preferred embodiment , each processor 100 has an associated memory device 125 . in accordance with the preferred embodiment , the memory 125 preferably comprises some form of synchronous dram , including sdram , ddr dram , or rdram memory devices , but other types of memory devices can be used , if desired . the capacity of the memory device 125 can be any suitable size . according to the preferred embodiment , discrete memory devices 125 a - l , in aggregate , form the system memory of the computer system 90 . each processor preferably includes appropriate logic for controlling the operation of the portion of the distributed memory to which it connects . thus , for example , processor 100 c couples to and controls discrete memory 125 c . as an alternative , memory may be associated only with select processors . in general , computer system 90 preferably are configured so that any processor 100 can access its own memory and i / o devices , as well as the memory and i / o devices of all other processors in the system . thus , as an example , processor 100 g can access memory device 125 b , or any other portion of the distributed memory 125 a - l in the computer system . preferably , the computer system may have physical connections between each processor resulting in low inter - processor communication times and improved memory and i / o device access reliability . if physical connections are not present between each pair of processors , a pass - through or bypass path is preferably implemented in each processor that permits accesses to a processor &# 39 ; s memory and i / o devices by another processor through one or more pass - through processors . referring still to fig2 , and in accordance with normal convention , each processor 100 a - l preferably includes at least one memory cache 115 . thus , as shown in fig2 , each processor 100 a - l has an associated memory cache 115 a - l . more preferably , each processor includes more than one memory cache , and may for example include both a level one (“ l1 ”) cache and a level two (“ l2 ”) cache . while the cache 115 is shown integrated with the processor 100 , one skilled in the art will understand that one or more of the memory caches may be located off - chip . in accordance with normal convention , the l1 cache preferably is located on - chip while the l2 chip is located off - chip . as one skilled in the art will understand , the processor retrieves data from one or more of the distributed memory devices 125 a - l during the course of executing one or more programs . data that is likely to be used or re - used by the processor is stored in one of the memory caches 115 of the processor . in the event that the data is not used , the data may be displaced from the cache and stored back in the distributed memory system 125 a - l . storage of often - used data in the cache 115 reduces the time that would otherwise be required to retrieve data from the distributed memory system 105 a - l . according to the preferred embodiment , the possible cache states include those listed in table 1 . to write to a data block in system memory ( other than the local memory of that processor ), the processor preferably must have a data block with a dirty cache state . to ensure data coherency , each processor 100 preferably includes a memory coherence directory 150 that reflects the status of each block of memory in the portion of the distributed memory system associated with and under control of that processor . thus , for example , memory coherence directory 150 d reflects the status of memory 125 d . in particular , the directory 150 tracks which processor has obtained a copy of a particular memory block , and also whether the copy is a read only copy ( and thus can be shared ) or whether the copy is a writeable copy ( and thus is exclusive ). the directory may exist in registers or memory within the processor , or may be physically located in a memory external to the processor , including the portion of system memory associated with that processor . fig4 is a conceptual illustration of one register that may be used to store status information for one block of memory . a plurality of similar registers would be provided , with one register associated with each memory block . in accordance with an exemplary embodiment , each register is dedicated to a particular memory block . as an alternative , the register may include additional bits to permit identification of a particular memory block . as shown in fig4 , the register includes two primary fields . the first field identifies the status of the memory block , and indicates whether a copy of the data in the memory block has been copied to a processor . further , the status bits preferably also indicate if the copy of the data block is a read - only copy , or whether the copy is writeable . the second portion of the register identifies the processor or processors that have obtained copies of the data block . thus , each processor in the computer system is identified by a binary code , to enable the directory to track processors that have access to a memory block . according to an exemplary embodiment , local memory accesses from the home processor need not be tracked in the memory coherence directory . any remote requests , however , preferably are used to update the directory as a mechanism to globally track the status of each data block . as shown in table 2 , there are at least six different states that may be used to identify the status of a data block in the memory coherence directory 150 : the number of bits used to encode the state of a data block may be arbitrarily chosen , depending on the number of states available , and the amount of detail that is to be tracked . similarly , the number of bits used to identify the processor or processors with access to the data block may also be chosen arbitrarily , depending on the number of processors in the system , and the number of processors who can concurrently share data . an example of the type of data that be encoded in the memory coherence directory is shown in table 3 . according to this exemplary embodiment , the four least significant bits are used to identify status of the memory block , while the eighteen most significant bits may be used to identify the processor or processors that have copies of the memory block , as follows : the foregoing table is only for purposes of illustration , and is not intended to limit the manner in which status data is encoded in the memory coherence directory . one of the coherence protocol messages found in many dsm multi - processor systems is a “ victim to shared ” message . the present invention uses this message in a unique way to handle data that has been displaced from a cache prior to issuing a store conditional instruction . thus , in accordance with the present invention , when an exclusive ( or a writeable ) cache block x is displaced from a cache , the owner processor checks to see if it has previously executed a load lock instruction for that cache block x . if the owner processor discovers that it has previously issued a load lock ( but not a store conditional instruction ), the owner processor preferably sends a victim to shared message to the home directory , rather than the standard victim message . the victim to shared message indicates that the owner processor is no longer the exclusive owner of the data block , but that it desires to continue to share the data block . thus , by issuing the victim to shared message , the processor continues to be listed as a sharer of that data block in the associated directory of the home processor for that data block . as a result , if any other processor subsequently attempts to write to that data block before the store conditional instruction is issued , the processor that issued the victim to shared instruction will receive an invalidate message from the home directory , thereby causing the failure of the load lock / store conditional operation , and thus maintaining coherency . the foregoing concept will now be illustrated with reference to fig2 . assume processor 100 a obtains exclusive control of a block x of data from memory 125 d by issuing a load lock signal . directory 150 d in processor 100 d will update its table to indicate that processor 100 a has exclusive control of data block x . block x is then loaded into the cache 115 a of processor 100 a . prior to the time that processor 100 a completes operation on data block x , processor 100 a may begin to execute another program , or otherwise begin processing some other instructions not pertinent to block x . as a result , cache 115 a desires to expel block x to make room for other data that is currently being used by the processor 100 a , as dictated by the cache algorithms that control which data is stored in the cache 115 a . before displacing block x from its cache , processor 100 a determines if it has previously issued a load lock instruction for data block x . if so , then processor 100 a returns the data to processor 100 d , and sends a victim to shared message to directory 150 d . as a result , the directory 150 d changes the status of data block x to note that processor 100 a is no longer the exclusive owner of data block x . however , because of the victim to shared message ( instead of the victim message ), directory 150 d lists processor 100 a as a sharer of data block x . in the event that that another processor subsequently attempts to write to data block x before processor 100 a executes the store conditional instruction , processor 100 a will receive an invalidate message from directory 150 d . in response , processor 100 a will fail the load lock / store conditional operation . if , instead , processor 100 a executes the store conditional instruction for data block x , prior to receiving an invalidate signal from directory 150 d , processor 100 a sends a read - with - modify intent store conditional (“ rdmodstc ”) instruction to the directory 150 d . stated differently , when the store conditional half of the load lock / store conditional pair is executed and misses in the cache , the message rdmodstc is transmitted to the targeted directory . if the directory 150 d finds that processor 100 a is a sharer of block x , then the directory 150 d sends a writeable copy of block x to processor 100 a and invalidates all other sharers , if any exist . if directory 150 d finds that processor 100 a is no longer a sharer of block x , then the directory 150 d knows an intervening write to block x has occurred after the load lock instruction from processor 100 a . thus , the load lock / store conditional instruction pair of processor 100 a is invalid , and the directory 150 d sends a store conditional failure to processor 100 a . as one skilled in the art will understand , the generation of the victim to shared message may be generated in many ways . one exemplary technique is depicted in fig3 . as shown in the exemplary embodiment of fig3 , a single register 205 is implemented for each program or thread , which records the address of the pending load lock / store conditional pair . each register 205 preferably has an associated comparator 215 . the output of comparator 215 functions as a select input to a multiplexer 240 . the input signals to the multiplexer 240 are a victim signal and a victim to shared signals . when an exclusive cache block 220 is displaced , the contents of the displaced data block register ( s ) 220 are compared to the address of the load lock register 205 . if the addresses are the same , the comparator output selects the victim to shared message in multiplexer 240 . as a result , the victim to shared message is delivered to the home directory , rather than the victim message that otherwise is transmitted with a displaced data block . as shown in fig3 , a store conditional signal causes the load lock register 205 to be reset . the above discussion is meant to be illustrative of the principles and various embodiments of the present invention . numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated . for example , the directory states and encodings shown in table 1 , table 2 , and table 3 may be extended to other encodings and directory states ( e . g ., a shared4 state , sharing with four sharers ) in the preferred embodiment of the invention . it is intended that the following claims be interpreted to embrace all such variations and modifications .