the block diagram of fig3 illustrates a preferred embodiment of a new ota 19 . a matched differential pair of bipolar transistors 18 forms a differential input stage with the bases of the transistors providing a differential input 20 . as will be described in greater detail in relation to fig4 a current source i1 sinks bias current from identical current conducting terminals 21 , i . e ., both collectors or both emitters , of the differential pair 18 , and the transistors &# 39 ; remaining current conducting terminals 23 ( collectors in the preferred embodiment ) are connected to identical current conducting terminals 25 ( collectors ) of a second differential pair 27 . the bases of the second differential pair 27 form a differential output port 22 . a current source i2 sinks bias current from the differential pair 27 . this connection , between the two pairs of collectors 23 / 25 in the preferred embodiment , provides differential feedback which , as will be discussed in greater detail in relation to fig4 cancels ac distortion in the pairs 18 , 27 . the current conducting terminals 25 of the second differential pair are coupled through a current - steering circuit 24 to an active load 26 and , from there , to a positive voltage terminal v +. the current steering circuit 24 includes an input control terminal vcon which controls the amount of current flowing into the differential pairs 18 , 27 , and thereby controls the transconductance of the amplifier 19 . a common mode feedback circuit 28 , in conjunction with the active load 26 , yields differential high impedance points a and b which may be used , for example , to connect a capacitor in order to produce a voltage controlled filter . the schematic diagram of fig4 illustrates a preferred embodiment of a new voltage controlled low pass filter which employs the novel ota . base currents are neglected in the following discussion . in this exemplary embodiment , a differential pair 18 includes npn transistors q1 and q2 coupled from their respective emitters through degeneration resistors r1 and r2 , respectively , to a current source i1 . similarly , a differential pair 27 includes npn transistors q3 and q4 connected through degeneration resistors r3 and r4 , respectively , to a current source i2 . currents i1 and i2 are equal . the degeneration resistors r1 - r4 increase the input range of the respective differential pairs 18 , 27 and reduce filter distortion . the collectors of the transistors q1 and q3 are connected together , as are the collectors of the transistors q2 and q4 . this connection provides differential feedback which cancels ac distortion . due to the new amplifier &# 39 ; s fully differential design , in the case of a voltage controlled filter with zero input voltage , adjustment of the control voltage will have substantially no effect upon the filter &# 39 ; s differential output . in the preferred embodiment , the current steering circuit 24 includes two differential pairs of npn transistors . one pair , consisting of transistors q5 and q6 , is connected , at the constituent emitters , to the collectors of transistors q3 and q1 . similarly , the pair consisting of transistors q7 and q8 have their emitters connected to the collectors of the transistors q2 and q4 . the transistors q5 and q8 have their respective collectors connected to a terminal bias which supplies a bias voltage to the amplifier and their bases are connected to another fixed voltage , &# 34 ; ground &# 34 ; in this example . the bases of the matched transistors q6 and q7 are connected to one another and form the voltage control terminal vcon . the collectors of the transistors q6 and q7 are coupled through active load matched pnp transistors q9 and q10 , respectively , to the bias terminal . an optional noise reduction circuit includes diode pairs d1 , d2 and d3 , d4 that are connected to couple current from the bias terminal bias to the load transistors q9 and q10 , respectively . the diode pairs d1 , d2 and d3 , d4 produce equal forward voltage drops and the base - emitter voltages of the transistors q9 and q10 are equal , thus establishing equal currents through the matched pair q9 , q10 . because they are matched transistors , their bases are shorted to one another , and their collectors are connected to the collectors of matched , equal - biased transistors q9 and q10 , the transistors q6 and q7 , respectively , also tend to carry equal currents . in operation , the current steering circuit 24 routes some fraction of the fixed current supplied to the collectors of the transistors q3 , q1 and q2 , q4 , through the transistors q6 and q7 , respectively . with the control voltage vcon at a level which cuts off the transistors q5 and q8 , substantially all the current from the load transistors q9 and q10 flows into the collectors of transistors q1 , q3 and q2 , q4 , respectively . that is , the current through transistor q6 equals the sum of currents through transistors q1 and q3 and the current through transistor q7 equals the sum of currents through the transistors q2 and q4 . as the control voltage vcon is reduced , the proportion of current supplied to the differential pairs 18 and 20 by the transistors q6 and q7 is reduced , thereby reducing the transconductance of the differential pair q6 , q7 . a common mode feedback stage 28 includes pnp transistors q11 and q12 with their emitters connected to the shorted bases of transistors q9 and q10 and their collectors connected to a negative supply voltage v -. the bases of transistors q11 and q12 are connected to the bases of transistors q3 and q4 , and to current sources i3 and i4 , respectively . npn transistors q13 and q14 are both connected at their collectors to the bias voltage terminal , bias and their emitters are connected to the bases of transistors q11 and q12 , respectively . variations in the output voltage , available at bases of transistors q11 and q12 , are fed back through the transistors q11 and q12 to the bases of the load transistors q9 and q10 . the complete left / right symmetry of the design ensures no systematic control feedthrough error and errors due to mismatches of the q13 and q14 base currents are minimized by keeping their emitter currents i3 and i4 small . in the illustrated filter , a capacitor c2 is placed across high impedance nodes a and b formed at the junctions of the collectors of transistors q9 and q6 and q7 and q10 respectively . the cutoff frequency of this low pass filter is given by the expression : the control voltage vcon is thus variable ( theoretically ) from zero to 1 /( 2πc ( r +( qi1 / 2kt ))). a high pass filter may be implemented by substituting an inductor l1 in the place of the capacitor c1 as the reactive element 40 . the forgoing description of specific embodiments of the invention has been presented for the purposes of illustration and description . it is not intended to be exhaustive or to limit the invention to the precise forms disclosed , and many modifications and variations are possible in light of the above teachings . for example , pnp and npn transistors could be substituted for one another , with appropriate adjustment of circuit polarities . other voltage controlled filters : high pass and bandpass , may employ the new ota . the embodiments were chosen and described in order to best explain the principles of the invention and its practical application , to thereby enable others skilled in the art to best utilize the invention . it is intended that the scope of the invention be limited only by the claims appended hereto .