fig1 shows a circuit schematic of a continuous variable - gain lna constructed in accordance with one embodiment of the present invention . the circuit of fig1 includes an input transconductance stage 102 , a current - steering circuit 104 , and an output load network 106 . the input stage consists of an inductively degenerated common - emitter transistor q 1 with its collector connected to the emitters of q 2 and q 3 , which form the cascode current steering circuit . the output load network consists of resistors r 4 and r 5 connected in series between the supply voltage v cc and node z . transistors q 2 and q 3 are arranged in a common - base configuration with the collectors of q 2 and q 3 tied to output load network nodes y and z , respectively . the base of transistor q 3 is connected to a reference voltage v ref , while the base of q 2 is connected to the gain control voltage v agc . a shunt feedback network 108 is connected from node y of the load network to the base of the input stage transistor q 1 . the output network 106 is also coupled to an inductor l 2 in parallel with the series combination of r 4 and r 5 and a series capacitor c 2 the components l 2 and c 2 are used to match the output impedance to an external load and can be realized either as on - chip or external components . in operation , an rf input signal is applied at the base of transistor q 1 , which converts the input voltage to a current . cascode transistors q 2 and q 3 , acting as both a current - steering circuit and common - base amplifiers , route the signal current at the collector of q 1 to either node y or node z of the load network . when the control signal v agc is sufficiently low compared to v ref so that q 3 turns on completely and q 2 turns fully off , the amplifier achieves its highest gain because all of the signal current from q 1 flows through q 3 and is injected at node z , which has the highest possible resistance , ( r 4 + r 5 ). for example , v agc and v ref are generated by known techniques to achieve a desired gain characteristic and compensate for temperature effects . the lowest gain is achieved by setting v agc high enough compared to v ref so that q 1 turns off and q 2 turns on . all of the signal current from q 1 flows through q 2 and is routed to node y of the loading network which attenuates the output signal compared to high gain by the ratio r 5 /( r 4 + r 5 ). in one embodiment , r 4 is nine times larger than r 5 so that the gain change between high gain and low gain is 20 db . intermediate gain values are achieved by partitioning the amount of signal current from the transconductance stage that is steered to node y relative to that routed to node z . in one embodiment , ( r 4 + r 5 ) is approximately 500 ohms . to compensate for the nonlinear components in the output current as the signal current is steered and the lna gain is reduced , the shunt feedback network 108 is connected between node y of the loading network and the base of the input transistor q 1 . the shunt feedback network is comprised of feedback resistor r f and a feedback capacitor c f ( which typically only acts as a dc blocking capacitor ). the shunt feedback network senses the voltage at node y and returns a proportional current to the base of q 1 , which tends to offset the nonlinearities of the amplifier gain response . the influence of the shunt feedback network can be readily seen from the expression for the small - signal voltage gain of the lna . for frequencies & lt ;& lt ; f t , ( unity gain cut - off frequency ) the magnitude of the small - signal voltage gain of the intrinsic amplifier ( a v ) in fig1 ( i . e ., neglecting voltage transformations across input ( not shown ) and output matching networks ( l 2 and c 2 )), can be approximated as | a v | ≈ g m 13 ⁡ [ g m 15 g m 14 + g m 15 ⁢ ( r 5 + r 4 ) + g m 14 g m 14 + g m 15 ⁢ r 5 - r 5 2 r f + r 5 ] the first two terms describe the variation in gain as the collector current of q 1 is partitioned between transistors q 3 and q 2 and accordingly produces output voltages across resistances r 4 + r 5 and r 5 , respectively . without any shunt feedback ( r f =∞), the high gain becomes g m1 ( r 4 + r 5 ) because g m2 = 0 when all the current is routed through q 3 to node z . likewise , the low gain becomes g m1 r 5 because g m3 = 0 when all the current is diverted through q 2 to node y . the third term in above equation reflects the presence of negative feedback , which reduces the small - signal gain and also linearizes the amplifier gain response . fig2 is a graph providing a comparison of the input third - order intercept point ( iip 3 ) versus v agc of the amplifier according to the invention , with and without shunt feedback . the graph was created with input signal tones at f 1 = 1 . 99 ghz and f 2 = 2 ghz , v ref = 1 . 75v , and with values of r f = 500 ohms and r f = 2 pf in the case when shunt feedback was applied . as can be seen from fig2 , at low gains the application of shunt feedback has significantly improved the input third - order intercept point . over the v agc range of 1 . 8 to 2 . 0v ( corresponding to a gain control range of 3 to 4 db ), the amplifier with shunt feedback shows an improvement in iip 3 of 3 to 5 db compared to that of the amplifier without feedback . because the shunt feedback network is connected to the output resistor chain at node y rather than node z , the amplifier only experiences light feedback at the highest gain . as a result , the shunt feedback network only contributes slightly to the input noise at high gain , allowing a low noise figure at high gain . since both the signal and noise currents of the transconductance stage are injected into the same node in the loading network , the output snr and noise figure of the lna are only modestly degraded as the gain is reduced . fig3 shows the gain and noise figures at 2 ghz versus v agc of the lna in accordance with the present invention . the lna achieves noise figures of 1 . 5 and 5 . 7 db at gains of 16 and − 4 db , respectively . the present invention includes an lna that provides continuously variable gain along with high - performing noise and linearity characteristics , and achieves other characteristics wanted in an lna . since a shunt feedback network connects the input of the lna to an intermediate node of a loading network rather than the output , excellent reverse - isolation characteristic of the cascode amplifier is preserved . the output impedance is independent of gain because it only depends on the impedance seen at node z . by properly choosing the size of input device q 1 , the value of r f , the current through q 1 , and the value of emitter inductor l e2 , the input impedance only changes slightly as the gain is varied . the present invention includes an lna with continuously variable gain . the embodiments described above are illustrative of the present invention and are not intended to limit the scope of the invention to the particular embodiments described . accordingly , while several embodiments of the invention has been illustrated and described , it will be appreciated that various changes can be made therein without departing from the spirit or essential characteristics thereof . accordingly , the disclosures and descriptions herein are intended to be illustrative , but not limiting , of the scope of the invention , which is set forth in the following claims .