referring to fig3 in accordance with a first aspect of the invention , a five terminal rf power amplifier package 140 employs a first preferred push - pull transistor chip 120 attached to a mounting flange 124 . attached to , but electrically isolated from , a first side of the flange 124 are a first input ( gate ) lead 141 , and a second input ( gate ) lead 142 . attached to an opposite side of , and electrically isolated from , the flange 124 is a first output ( drain ) lead 143 and a second output ( gate ) lead 144 . referring also to fig4 the transistor chip 120 includes two ldmos transistors having similar characteristics formed on a single semiconductor die 122 . the first transistor includes a drain region 126 and gate region 128 , and the second transistor includes a drain region 130 and gate region 132 , respectively , with the two transistors formed on opposite sides of a shared source region 134 . the first and second input leads 141 and 142 are electrically connected via wire bond conductors to the respective first and second gate regions 128 and 132 . similarly , the first and second output leads 143 and 144 are electrically connected via wire bond conductors to the respective first and second drain regions 126 and 130 . the shared source region 134 is electrically connected via a wire bond conductor to the surface of the mounting flange 124 . in alternate embodiments , the shared source region 134 may be electrically coupled to the flange 124 through the device itself , e . g ., using a highly doped path through the die 122 . with reference also to fig5 when an activating voltage is applied to the first gate region 128 ( via lead 141 ), electrical conduction occurs from the first drain region 126 ( via lead 143 ) to the common source region 134 . similarly , when an activating voltage is applied to the second gate region 132 ( via lead 142 ), electrical conduction occurs from the second drain region 130 ( via lead 144 ) to the common source region 134 and , ultimately , the “ ground reference ” flange 124 . in alternate transistor package embodiments , the common element ground reference may be different than the mounting flange 124 , in which case the source region 134 is electrically connected to the actual ground reference instead of the flange 124 . this geometry for fabricating the two transistors on a single die 122 eliminates the need for sinker region in the vicinity of the source region 134 by formation of a “ virtual ground ” within the device . this virtual ground is a result of the two gate signals applied to leads 141 and 142 being 180 degrees out of phase and of equal amplitude , and provides a local alternating current ( ac ) ground , or null point , that is independent of the inherent resistance and inductance in the common lead current path . instead , the common lead current path need only provide an adequate direct current ( dc ) path to ground for the transistors , providing for higher frequency performance and enhanced stability of the device 140 , which is relatively insensitive to the physical placement of the transistors on the semiconductor die 122 relative to the flange 124 and / or the general magnitude of the inherent resistive and inductive elements of the common lead current path . a particular advantage of not having a sinker region is that the power density per chip is significantly higher , thereby reducing the size of the semiconductor die . even order distortion products are cancelled at the shared source region 134 , whereas the odd order distortion products create a voltage drop . notably , the transistor chip 120 is shown as an n - channel device , but this construction is by example and does not limit the invention . it will be apparent to those skilled in the art that each of the push - pull transistor device embodiments disclosed herein could be fabricated with opposite polarity ; i . e ., a p - channel device and remain within the scope of the invention . it will also be apparent to those skilled in the art that the transistor device geometry depicted in the figures is representative only and is not necessarily to scale . in order to extend the power handling capability of a push - pull transistor device , it would be desirable to have multiple conduction channels operating essentially in parallel . with such a device , activation of the first gate lead 141 will facilitate conduction from the first drain lead 143 to flange 124 , while still maintaining isolation of the second drain lead frame 144 . towards this end , fig6 is an alternate preferred push - pull transistor chip 220 for use in the five terminal package 140 . the transistor chip 220 comprises first and second ldmos transistors , each having multiple channels operated in parallel , fabricated on a single semiconductor die 222 . the first transistor has a source region 151 , a drain region 153 , and first and second gate regions 152 and 154 disposed on opposite sides of the drain region 153 . the second transistor has a source region 159 , a drain region 157 , and first and second gate regions 158 and 156 disposed on opposite sides of the drain region 157 . the two transistors also share a common source region 155 . with reference also to fig7 and 8 , the drain region 153 is electrically connected to the first drain lead 143 , and the first and second gate regions 152 and 154 are electrically coupled to the first gate lead 141 . similarly , drain region 157 of the second transistor is electrically coupled to the second drain lead 144 , and gate regions 156 and 158 are electrically coupled to the second gate lead 142 . each of the source regions 151 , 155 and 159 are electrically coupled via wire bands to the surface of the flange 124 . in alternate embodiments , the shared source regions 151 , 155 , and 159 may be electrically coupled to the flange 124 through the device itself , e . g ., using a highly doped path through the die 222 . each of the first and second transistors have double conduction channels . the first transistor uses gate regions 152 and 154 to activate two conduction channels . when activating voltage is applied to the first input lead 141 , electrical conduction is facilitated between drain region 153 and source region 151 , and between drain region 153 and source region 155 , respectively . this , in turn , facilitates electrical conduction from the first output lead 143 to the flange 124 ( as seen in fig . 7 ). in alternate transistor package embodiments , the common element ground reference may be different than the mounting flange 124 , in which case the source regions 151 , 155 and 159 are electrically connected to the actual ground reference instead of the flange 124 . similarly , the second transistor uses gate regions 156 and 158 to activate two conduction channels . when an activating voltage is applied to the second input lead 142 , electrical conduction is facilitated between drain region 157 and the common source region 155 , and between drain region 157 and source region 159 , respectively . this , in turn , facilitates electrical conduction between the second drain lead 144 and the flange 124 . in accordance with a yet another aspect of the invention , a push - pull transistor device can be fabricated having further conduction channels in the first transistor , which are added in pairs and interleaved with corresponding channels added to the second transistor . this concept is illustrated in fig9 which depicts a further push - pull transistor chip 320 similar to that of fig6 with two additional first transistor conduction channels interleaved with two additional second transistor conduction channels , respectively , all formed on a single die 322 . in particular , the transistor chip 320 includes a first transistor having first , second , third and fourth gate regions 162 , 164 , 170 and 172 , respectively , and first and second drain regions 163 and 171 . the device includes a second transistor having first , second , third , and fourth gate regions 166 , 168 , 174 , and 176 respectively , and first and second drain regions 167 and 175 . the two transistors share source regions 161 , 165 , 169 , 173 and 177 , with each transistor having double interleaved conduction channels on each side of drain region 171 . with reference to fig1 and 11 , the first and third drain regions 163 and 171 are electrically coupled to the first output lead 143 . the second and fourth drain regions 167 and 175 are electrically coupled to the second output lead 144 . the first , second , fifth and sixth gate regions 162 , 164 , 170 and 172 are electrically coupled to the first input lead 141 . the third , fourth , seventh and eighth gate regions 166 , 168 , 174 and 176 are electrically coupled to the second input lead 142 . the first , second , third , fourth and fifth source regions 161 , 165 , 169 , 173 , and 177 are electrically coupled to the surface of the flange 124 . in alternate embodiments , the shared source regions 161 , 165 , 169 , 173 , and 177 may be electrically coupled to the flange 124 through the device itself , e . g ., using a highly doped path through the die 322 . the first transistor uses the first , second , fifth and sixth gate regions 162 , 164 , 170 and 172 to activate its four conduction channels . when activating voltage is applied to first input lead 141 , electrical conduction is facilitated between drain region 163 and source regions 161 and 165 , as well as between drain region 171 and source regions 169 and 173 . this , in turn , facilitates electrical conduction from the first output lead 143 to the flange 124 . similarly , the second transistor uses the third , fourth , seventh and eighth gate regions 166 , 168 , 174 and 176 , respectively , to activate its four conduction channels . when activating voltage is applied to the second input lead 142 , electrical conduction is facilitated between the second drain 167 and second source 165 , second drain 167 and third source 169 , and between the fourth drain 175 and fourth source 173 , the fourth drain 175 and fifth source 177 , respectively . this , in turn , facilitates electrical conduction between the second drain lead 144 and the flange 124 . in alternate transistor package embodiments , the common element ground reference may be different than the mounting flange 124 , in which case the source regions 161 , 165 , 169 , 173 , and 177 are electrically connected to the actual ground reference instead of the flange 124 . it will be apparent to those skilled in the art that this concept can be extended to further interleaving pairs of conduction channels in the push - pull transistor devices . also those skilled in the art will recognize that transistors other than ldmos transistors , for example , bipolar power transistors , may be used in push - pull configuration in accordance with the above teachings . accordingly , the invention is not to be restricted , except in light of the claims and their equivalents .