referring now more particularly to the drawing , like numerals indicate like parts and structural features in the various diagrams . a using unit 10 , such as a central processing unit ( cpu and the like ) is connected via a peripheral connection 11 to storage director 12 . storage director 12 includes a programmable processor for operating storage devices which store data for using unit 10 . storage director 12 in turn is connected via device connection 13 to dasd 14 . data is transferred from dasd 14 through storage director 12 to using unit 10 and in the reverse direction , all in accordance with i / o of peripheral commands supplied by using unit 10 over input / output connection 11 to storage director 12 . storage director 12 decodes the received i / o commands and generates a series of device commands transmitted to dasd 14 over device connection 13 using known procedures . one or more dasds 14 may be connected to storage director 12 . to enhance operation of the just - described storage system , including director 12 and dasd 14 , a cache 15 is connected to storage director 12 via memory connection 16 . cache 15 is preferably a high - speed random - access multi - megabyte storage unit addressable as any random access storage unit is addressed . a storage director 12 having independent access to dasd 14 and cache 15 can operate independently with those units . predetermined data from dasd 14 is promoted to cache 15 for access by using unit 10 in reduced time . in accordance with the invention , operation of the storage system including director 12 , cache 15 and dasd 14 is enhanced by a limited bypassing access to cache 15 upon a cache miss . whenever a given peripheral command requesting data or for supplying data to the system finds that no space in cache 15 is allocated for such data , the remainder of the chain of peripheral commands addressing data within a cylinder of dasd 14 is handled directly between using unit 10 , storage director 12 and dasd 14 . such bypass occurs even though space may be allocated in cache 15 for data referred to by the peripheral commands . an advantage of this arrangement is that orientation of dasd 14 with respect to operations of using unit 10 is maintained . a cylinder of data in dasd 14 is defined in accordance with the international standards organization as data contained in a set of tracks all residing within the same nominal distance from the rotational axis of a dasd . a cylinder is also defined as all of the record tracks in a disk storage device , such as a dasd , that are accessible without repositioning the dasd 14 transducer access mechanism ( not shown , but as described in u . s . pat . no . 3 , 503 , 060 ); i . e ., all of the tracks that can be accessed as a group through electronic switching . data integrity requires congruence between data stored in cache 15 and data stored in dasd 14 . storage director 12 includes a flag bit or flip - flop 20 indicating for each dasd 14 whether or not access to the data is to be achieved through cache 15 or directly to dasd 14 . when bit 20 is set to c , cache 15 is accessed ; when bit 20 is set to d , then dasd 14 is accessed . upon a miss , i . e ., data being written to the peripheral system or to be retrieved from the peripheral system is not in cache 15 , storage director 12 supplies a signal over bus 21 setting bit 20 to the d state . upon certain other conditions , as will become apparent , but 20 is set to the c state . the memorized state of bit 20 is supplied to storage director 12 controls via line 22 . accordingly , when using unit 10 requests data from the peripheral system , storage director 12 after decoding the command , examines bit 20 for the addressed dasd 14 . if the value is c , then a directory , later described , is searched for cache space allocations ; if space is allocated in cache 15 , the data transfer occurs directly with cache , avoiding accessing dasd 14 . on the other hand , when bit 20 is in the d state , dasd 14 is accessed . the present invention relates to certain controls for controlling bit 20 for enhancing data integrity and performance , as will become apparent . when cache 15 is being bypassed during a write operation , there is a possibility that data in dasd 14 is more current or more recent than the data stored in cache 15 , i . e ., there is no longer congruence between the data in cache 15 and that in dasd 14 . to help reduce this problem , during such direct accesses to dasd 14 , storage director 12 provides a device access tally 23 , a data processing table accessed via bus 24 . this table identifies each track updated in dasd 14 in the direct mode , i . e ., when bit 20 is d ; and the fact that a dasd 14 track was updated is noted in device access tally 23 . upon completion of a peripheral chain of commands , a series of commands ; the device access tally 23 is accessed via bus 24 and compared with entries of data stored in cache 15 in a later described directory . for all comparisons , i . e ., for all tracks changed in dasd 14 that have space allocated in cache 15 , are then handled in accordance with one aspect of the invnetion . for tracks or records bound to cache 15 that were altered in dasd 14 , a replication of the data stored in dasd 14 is moved to cache 15 , i . e ., is promoted to cache 15 ; for all tracks or records that are not bound to cache and modified on dasd 14 , are erased from cache 15 by destroying addressability , i . e ., the entry for such cached data in the later described directory is erased . the machine operations chart for implementing the invention in the illustrated system through a programmed processor , which typically includes a control store , includes starting a data storage access by receiving a command from using unit 10 . following decoding the command as at 30 , certain preparatory commands are received at 31 for priming the peripheral system to receive data transfer commands . in the illustrated storage apparatus these preparatory commands include a seek command which causes the access transducer mechanism to move to an addressed track and commands to select an addressed dasd 14 . following such known preparatory steps , loop 32 of data processing operations is performed . the first step in loop 32 is to receive peripheral commands at 33 for commanding a dasd search followed by either a read r or a write w data transfer operation . at 34 , storage director 12 examines bit 20 to see whether or not cache 15 or the addressed dasd 14 is to be accessed . normally , for performance reasons , cache 15 is desired to be accessed ; then logic path 35 is followed to step 36 which examines the later described directory to determine if space is allocated in cache 15 for the data in the commanded transfer . assuming that such space is allocated , a so - called &# 34 ; hit &# 34 ; occurs . then at 37 , cache 15 is accessed and the data processing operation ensues . upon completion of that operation , storage director 12 at 38 examines system status to determine if there has been a change in operations . a change can be indicated by the end of chain signal as commonly used on computers manufactured by international business machines corporation . such end of chain is indicated by removing a so - called suppress out tag signal when another tag signal &# 34 ; service out &# 34 ; is active at final status in time , i . e ., upon completion of command execution . another change in operation which includes a seek command , i . e ., a commanded movement of the transducer access mechanism ; an end of cylinder indication which also requires a movement of the transducer access mechanism ; and the like indicates a change of accessing from electronic switching between transducers to a mechanical motion of the access mechanism . with addressing tracks in the cylinder and within a chain of command , no change of operation requiring access mechanism motion occurs . then peripheral system receives an additional read / write command as indicated at 33 for repeating the loop 32 of operations . a plurality of such commands can be executed directly with cache 15 for either reading or writing . dasd 14 is only accessed when bit 20 is set to the d state as sensed at 34 or a cache miss occurs at 36 , i . e ., no space is allocated in cache 15 . in that event , storage director 12 follows logic path 40 to access dasd 14 at 41 . this access , of course , includes transferring data either to a dasd 14 or to using unit 10 . upon completion of the access for a write operation , i . e ., transfer of data to a dasd 14 , at 42 the storage director 12 updates device access tally 23 for use upon detection of a change at 38 ; for a read operation no action occurs , but as an alternate embodiment read accesses can be tallied either separately or with the write tally to achieve the purpose of the present invention . upon detection of a change at 38 , storage director 12 at 43 performs a congruence check and control , as later detailed . such congruence check compares the device access tally 23 with a later described directory for cache 15 for determining any writes to dasd 14 that create noncongruence . upon completion of this later described operation , storage director 12 at 44 returns to receive additional peripheral commands which may be within the same chain of commands or be a separate chain of commands . fig2 illustrates a preferred embodiment of the invention as employed in a two storage director 12 arrangement . each storage director 12 includes a plurality of so - called channel adaptors ( external means ) 50 , also separately denominated as caa through cad which connect the respective storage directors 12 to a plurality of using units 10 via a plurality of input / output connections 11 . each storage director 12 includes a programmed processor 51 which as usual includes a processing unit ( not shown ) having a control store ( not shown ) which contains computer programs for performing the storage director functions . the programmed processor 51 includes programs constituting address and command evaluator ace 52 which receive and evaluate peripheral commands . such functions are also performed in present day storage directors for noncached dasd as widely sold throughout the world . the programmed processor 51 also includes direct access control 53 which responds to commands evaluated and decoded by ace 52 to control data transfers between using units 10 and addressed ones of dasd 14 , as well as providing device commands to dasd 14 for performing well known dasd access and control functions . program processor 51 further includes cac 54 which is a cache access control for accessing cache 15 . cd bits 20 for each of the dasds 14 are accessed by dac 53 and cac 54 respectively for determining whether to access cache or dasd and for setting the bits to d at a cache miss . connections from storage director 12 to dasd 14 are via dasd circuits 55 which are constructed using known device adaptor and data flow design techniques . cache 15 is accessed via memory circuits 56 which includes those circuits for generating addresses and access requests . cache 15 is a portion of a large random access store 57 , hereinafter referred to as a system store . a directory 58 for cache 15 is also stored in system store 57 . the directory 58 is accessed using known hashing techniques based upon the address structure of dasd 14 . each unit of data , track or record stored in cache 15 has an entry in directory 58 , as is known in the data processing art . additionally , using unit 10 can command the storage directors 12 to keep data in cache , i . e ., pin or bind the data to cache 15 . for all bound tracks and records a cache bound list 60 , stored within directory 58 but shown separately for clarity , indicates to both storage directors 12 which data stored in cache 15 is to remain in cache 15 . this bound list is used in the congruence check and control step 43 , as detailed later with respect to fig3 . each storage director 12 has its own device access tally 23 . access to dasds 14 is via a so - called string arrangement in which a plurality of dasds 14 are connected to the storage directors 12 via controllers 65 , separately denominated as dca through dcd . each storage director 12 connects to the controllers 65 via a daisy - chain device connection 13 . a radial connection of known design may also be employed . the operation of the fig2 illustrated system in accordance with the invention is best understood by referring to fig3 a machine operations chart . programmed processor 51 at 70 receives a storage access request . this request is decoded and evaluated in ace 52 using known techniques . at 71 , programmed processor 51 dac 53 portion examines dc bit 20 to determine whether cache 15 or dasd 14 is to be accessed . for a cache c access , processor 51 searches directory 58 at 72 to see if the track or record requested in the received i / o command is stored in cache 15 . searching directories for determining contents of cache or other memories is well known and not detailed for that reason . in this regard , it is noted that some commands will require a direct connection to dasd 14 . accordingly , ace 52 in detecting such a peripheral command will set bit 20 for the addressed dasd to the direct mode . an example of such a peripheral command is to recalibrate dasd 14 . searches and search id equal commands can be performed for cache within directory 72 or within cache 15 , i . e ., the commands are performed in a virtual manner not involving dasd 14 . in the constructed embodiment directory 58 did not separately identify records in a track ; only tracks were identified , no limitation thereto intended . upon completion of the directory search , programmed processor 51 at 73 determines whether or not a hit has occurred . if a hit has occurred , which is preferred for performance reasons , programmed processor 51 follows logic path 75 to access cache 74 for transferring data between using unit 10 and cache 15 using known data transfer techniques . upon completion of that transfer , programmed processor 51 returns through logic path 85 for receiving a next peripheral command using known techniques . then a second storage access request is received at 70 for repeating the above described operation for cache 15 accessing . when a cache miss occurs at 73 , the direct mode of data transfer is set at 76 . this means that using unit 10 will transfer data directly with dasd 14 within the cylinder of tracks and for the continuation of the particular chain of commands independent of whether or not space is allocated in cache 15 for any of the data transfers . once bit 20 for the addressed device is set to the direct state , any subsequently received commands following step 70 cause programmed processor 50 to follow logic path 77 to join the exit of step 76 for accessing dasd 14 and tallying the access for write commands at 78 ( no tallying for read commands , no limitation thereto intended ). accessing dasd 14 for data transfers , then updating a least recently used linked list for cache replacement control , is well known and not detailed for that reason . the address of the track / record to be written in the addressed dasd 14 for each write operation is stored in device access tally 23 for later described postchain / postcylinder operations . upon completion of the command execution , by executing step 78 , programmed processor 51 reports final status at 79 to using unit 10 . upon posting final status , programmed processor 51 then determines whether or not there is a change in operations as detected at step 38 of fig1 and as detected within a series of branch operations 80 of fig3 . these checks may be performed upon sending final status to using unit 10 or upon receiving a next peripheral command but before execution of such next peripheral command . a first check at 81 checks for end of the chain ( eoch ) which is detected by the absence of the suppress out tag signal at final status time . the second check at 82 is for the end of the cylinder ( eocyl ). all of the tracks within a cylinder have a predetermined address space , tracks 1 through 17 , for example . depending upon the addressing increment direction , i . e ., increasing or decreasing track addresses , upon completion of an access to a track at 78 , the next track can be in an adjacent cylinder or within the same cylinder . if the next track to be accessed is expected to be in an adjacent cylinder , then at 82 programmed processor 51 indicates end of cylinder , a change indicated in step 38 . the third check at 83 is for out of bounds ( oob ). it is common practice in present day dasd peripheral systems to have a define extent command received from a using unit 10 . a define extent command establishes a range of addresses which defines bounds of permitted access . accordingly , if programmed processor 51 in processing the peripheral command at 78 indicates that the address being processed is at the boundary of the defined extent ; then an out of bounds condition occurs , i . e ., the next desired access will be outside of the previously defined extent , i . e ., a change in operation . a fourth check at 84 is for a received command decoded by step 70 which is a device related command . this type of command includes the recalibrate command as used on present day dasd . if all of the steps 81 - 84 indicates no such change , then programmed processor 51 follows path 85 to receive the next peripheral command . if any one of the conditions set forth for steps 81 - 84 are met , then programmed processor 51 follows logic path 90 to reset bit 20 to the c state at step 91 . then at 92 program processor 51 in step 93 scans cache bound list 60 and compares each entry in cache bound list with the contents of device access tally 42 . for each hit , i . e ., favorable comparisons , programmed processor 51 actuates the peripheral system to transfer data from dasd 14 to cache 15 corresponding to that data , i . e ., data stored in a track on dasd 14 was changed when data contained in cache 15 was bound to that cache . for congruence and data integrity cache 15 is updated . at completion of the scan or no hit , step 94 is omitted . at 95 , the tracks on dasd 14 which were modified and not bound to cache 15 are demoted from cache 15 . at 96 , programmed processor 51 examines a sequential bit ( not shown ) to see whether or not a using unit 10 had indicated that the previous storage requests were indicated as being sequential data , i . e ., the using unit 10 is using the data in the batch mode such that sequential processing occurs as opposed to interactive modes where partitioned data sets or random accesses to the data occur . if the data are not sequential , then programmed processor 51 goes to logic path 85 . for sequential , data programmed processor 51 at 97 promotes the entire contents of the last track accessed in the dasd 14 to cache 15 . this occurs of read operations . for purposes of brevity the sequential indicator is not shown in the drawing , but it is a bit in a control store ( not shown ) of programmed processor 51 for each of the addressed dasd 14 . in the above described operation , accessing dasd 14 ensures recording data from using unit 10 into the retentive store of dasd 14 as quickly as possible thereby avoiding transferring the data to cache and then from cache to dasd 14 whenever orientation of the dasd 14 has been established and whenever allocation is required in cache 15 . practicing this invention in a test environment has shown that this has protected data integrity while enhancing performance of the peripheral storage system . while the invention has been particularly shown and described with reference to preferred embodiments thereof , it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention .