the present invention will now be described more specifically with reference to the following embodiments . it should be noticed that the embodiments of the present invention described below are used for illustrative purposes only ; it doesn &# 39 ; t mean that the present invention has been described in detail or is used to limit the disclosed aspect . first , please refer to fig1 with fig8 at the same time . it shows an architecture of a feed forward sigma - delta analog to digital conversion modulator 1 of 3 order . the feed forward sigma - delta analog to digital conversion modulator 1 includes an input end capacitor switching circuit 10 , a feed forward integrator 20 , a multi - bit quantizer 30 , a continuously progressive control circuit 40 and a weighted average data circuit 50 . the input end capacitor switching circuit 10 receives an input timing control signal 125 , an input voltage s 123 and a capacitor switching signal s 52 , and generates an integration input signal s 261 . the feed forward integrator 20 receives the integration input signal s 261 , a continuously progressive control signal s 263 and an input timing control signal s 125 , and generates an integration output signal s 264 . the multi - bit quantizer 30 receives the integration output signal s 264 and a quantization reference control signal s 31 , and generates a modulation output signal s 32 . the continuously progressive control circuit 40 receives the modulation output signal s 32 , and generates quantization reference control signal s 31 , the continuously progressive control signal s 263 and a weighted average data signal s 51 . the weighted average data circuit 50 receives the weighted average data signal s 51 and generates the capacitor switching signal s 52 . next , please refer to fig2 . it shows an architecture of a feed forward integrator 20 . the feed forward integrator 20 is formed by serially connecting a number of integration circuits for processing integral operation and controls outputs of every stage integrating circuits by a control signal . for the present invention , the feed forward integrator 20 includes a first stage integrating circuit 21 , a second stage integrating circuit 22 and a third stage integrating circuit 23 . the first stage integrating circuit 21 receives the integration input signal s 261 and an integration timing control signal s 262 . after integral operation , two output signals are generated and sent to the next stage integrating circuit and a last output end , respectively . the following stage integrating circuits except the last one receives the output signal and the control signal from a stage integrating circuit in previous level . after integral operation , two output signals are generated and sent to the next stage integrating circuit and the last output end , respectively . the last stage integrating circuit receives the output signal and the control signal from a stage integrating circuit in previous level . after integral operation , one output signal is generated and directly sent to the last output point . please refer to fig3 . it shows an architecture of a single stage integrating circuit of the feed forward integrator 20 . take the first stage integrating circuit 21 in the feed forward integrator 20 as an example . the first stage integrating circuit 21 includes an amplifier 247 , 3 capacitors ( first capacitor 244 , second capacitor 245 and third capacitor 246 ) and 3 switching circuit groups ( first switching circuit group 241 , second switching circuit group 242 and third switching circuit group 243 ). an input end of the first switching circuit group 241 is coupled to the integration input signal s 261 . its output end is coupled to one input end of the amplifier 247 . the other input end of the amplifier 247 connects to ground . its output end is coupled to both an input end of the second switching circuit group 242 and an input end of the third switching circuit group 243 at the same time . the first capacitor 244 is coupled between the output end of the first switching circuit group 241 and the input end of the amplifier 247 . the second capacitor 245 is coupled between the output end of the second switching circuit group 242 and the integration output signal s 264 . the third capacitor 246 is coupled between the output end of the third switching circuit group 243 and a serially connected output signal s 265 . the following stage integrating circuit except the last one has the same architecture as that of the first stage integrating circuit 21 . difference is the input end of the first stage integrating circuit 21 receives the integration input signal s 261 , while the input end of the following stage integrating circuit except the last one receives the serially connected output signal s 265 from the previous level . next , please refer to fig3 and fig4 at the same time . it shows a circuit diagram of the feed forward integrator 20 in the present invention . the last stage integrating circuit 23 of the feed forward integrator 20 includes an amplifier 247 , 2 capacitors and 2 switching circuit groups . the input end of the first switching circuit group 241 is coupled to the integration input signal s 261 and the integration timing control signal s 262 . its output end is coupled to the input end of the amplifier 247 . the other input end of the amplifier 247 connects to ground . the output end is coupled to the input end of the second switching circuit group 242 . the first capacitor 244 is coupled between the output end of the first switching circuit group 241 and the input end of the amplifier 247 . the second capacitor 245 is coupled between the output end of the second switching circuit group 242 and the integration output signal s 264 . please refer to fig5 . it shows an architecture of a single level integration differential circuit of the feed forward integrator 20 in the present invention . according to the present invention , the first stage integrating circuit 21 of the feed forward integrator 20 may use the differential architecture to implement . it has an effect to increase snr for signals . the architecture includes a differential amplifier 257 , 6 capacitors ( first capacitor 244 , second capacitor 245 , third capacitor 246 , negative - end first capacitor 254 , negative - end second capacitor 255 and negative - end third capacitor 256 ) and 6 switching circuit groups ( first switching circuit group 241 , second switching circuit group 242 , third switching circuit group 243 , negative - end first switching circuit group 251 , negative - end second switching circuit group 252 and negative - end third switching circuit group 253 ). the input end of the first switching circuit group 241 is coupled to the integration input signal s 261 and the integration timing control signal s 262 . its output end is coupled to a positive input end of the differential amplifier 257 . an negative output end of the differential amplifier 257 is coupled to the second switching circuit group 242 and the input end of the third switching circuit group 243 at the same time . the first capacitor 244 is coupled between the output end of the first switching circuit group 241 and the positive input end of the differential amplifier 257 . the second capacitor 245 is coupled between the output end of the second switching circuit group 242 and the integration output signal s 264 . the third capacitor 246 is coupled between the output end of the third switching circuit group 243 and the serially connected output signal s 265 . an input end of the negative - end first switching circuit group 251 is coupled to the negative - end input signal . its output end is coupled to a negative input end of the differential amplifier 257 . a positive output end of the differential amplifier 257 is coupled to an input end of the negative - end second switching circuit group 252 and an input end of the negative - end third switching circuit group 253 . the negative - end first capacitor 254 is coupled between the output end of the negative - end first switching circuit group 251 and the negative input end of the differential amplifier 257 . the negative - end second capacitor 255 is coupled between an output end of the negative - end second switching circuit group 252 and the negative - end integration output signal s 264 . the negative - end third capacitor 256 is coupled between an output end of the negative - end third switching circuit group 253 and the negative - end serially connected output signal s 265 . the following stage integrating circuits except the last one has the same architecture as that of the first stage integrating circuit 21 . difference is the input end of the first stage integrating circuit 21 receives the input signal and the negative - end input signal , while input ends of the following stage integrating circuits except the last one receive the positive serially connected output signal s 265 and negative - end serially connected output signal s 265 from the previous level . the last stage integrating circuit 23 of the feed forward integrator 20 in the present invention may use a differential architecture to implement . its architecture includes a differential amplifier 257 , 4 capacitors ( first capacitor 244 , second capacitor 245 , negative - end first capacitor 254 and negative - end second capacitor 255 ) and 4 switching circuit groups ( first switching circuit group 241 , second switching circuit group 242 , negative - end first switching circuit group 251 and negative - end second switching circuit group 252 ). the input end of the first switching circuit group 241 is coupled the input signal . its output end is coupled the positive input end of the differential amplifier 257 . the negative output end of the differential amplifier 257 is coupled to the input end of the second switching circuit group 242 . the first capacitor 244 is coupled between the output end of the first switching circuit group 241 and the positive input end of the differential amplifier 257 . the second capacitor 245 is coupled between the output end of the second switching circuit group 242 and the integration output signal s 264 . the input end of the negative - end first switching circuit group 251 is coupled to the negative - end input signal . its output end is coupled to the negative input end of the differential amplifier 257 . the positive output end of the differential amplifier 257 is coupled to the input end of the negative - end second switching circuit group 252 . the negative - end first capacitor 254 is coupled between the output end of the negative - end first switching circuit group 251 and the negative input end of the differential amplifier 257 . the negative - end second capacitor 255 is coupled between the output end of the negative - end second switching circuit group 252 and the negative - end integration output signal s 264 . next , please refer to fig9 . it shows structures of the first switching circuit group 241 and the second switching circuit group 242 in each stage integrating circuit in the present invention . as it shown , the first switching circuit group 241 includes 2 switches ( first switch 248 and second switch 249 ). the first switch 248 is coupled between the input end and the output end and controls switch status of signal control . the second switch 249 is coupled between the input end and the ground and controls switch status of signal control . the second switching circuit group 242 also has 2 switches ( first switch 248 and second switch 249 ). the first switch 248 is coupled between the input end and the output end and controls switch status of signal control . the second switch 249 is coupled between the output end and the ground and controls switch status of signal control . for the second capacitor 245 or the negative - end second capacitor 255 in each stage integrating circuit of the feed forward integrator 20 in the present invention , their capacitance is able to adjust and the volume of the integration output signal 264 is adjusted accordingly . a control method of the switch circuits of the feed forward integrator 20 in the present invention has three operating timings . in a first operating timing , a first timing signal is generated . two contacts on the left end and the right end of each first switching circuit group 241 are not conducted at this moment . the contact on the left is connected to ground and the contact on the right stays suspension . two contacts on the left end and the right end of each second switching circuit group 242 are conducted at the same time . two contacts on the left end and the right end of each third switching circuit group 243 are not conducted so that charging sampling is processed on the second capacitors 245 of each stage integrating circuit at this timing . next , come to a continuously progressive control timing . the continuously progressive control signal 263 is generated . sequentially conduct the third switching circuit groups 243 in each stage integrating circuit . control charged power in the third capacitors 246 in each stage integrating circuit . two contacts on the left end and the right end of each second switching circuit group 242 and third switching circuit group 243 are not contacted at this timing . last , come to a second timing . two contacts on the left end and the right end of each first switching circuit group 241 are conducted . two contacts on the left end and the right end of each second switching circuit group 242 are not conducted at the same time . the contact on the left stays suspension while the contact on the right is connected to ground . two contacts on the left end and the right end of each third switching circuit group 243 are not conducted . since the integration circuit has a feature of feed forward path , directly connecting by capacitors , utilize said timing operating control capacitor to charge and discharge sigma - delta integral operation can be achieved . adder circuit in the output end can be saved . please refer to fig6 . it shows an architecture of the input end capacitor switching circuit 10 in the present invention . the input end capacitor switching circuit 10 of the feed forward sigma - delta analog to digital conversion modulator 1 in the present invention includes a number of input capacitor switching units 101 connected to one another . the input capacitor switching units 101 receive the positive reference voltage s 121 , the negative reference voltage s 122 , the input voltage s 123 , the timing signal and the switching signal , and generate the output signal . please refer to fig7 . it shows an architecture of the input capacitor switching unit 101 . the input capacitor switching unit 101 in the present invention includes 5 switches ( first switch 111 , second switch 112 , third switch 113 , fourth switch 114 and fifth switch 115 ) and 2 capacitors ( first switched - capacitor 116 and second switched - capacitor 117 ). one end of the first switch 111 is connected to the positive reference voltage s 121 . the other end is connected to the second switch 112 , the third switch 113 and the first switched - capacitor 116 . the other end of the second switch 112 is connected to the negative reference voltage s 122 . the other end of the third switch 113 is connected to ground . the other end of the first switched - capacitor 116 is connected to the second switched - capacitor 117 . the other end of the second switched - capacitor 117 is connected to the fourth switch 114 v and the fifth switch 115 . the other end of the fourth switch 114 is connected to the input voltage s 123 . the other end of the fifth switch 115 is connected to ground . a control method for the switches includes two operating timing . in a first operating timing , a first timing signal is generated . directly conduct the fourth switch 114 and sequentially conduct the first switches 111 and the second switches 112 of each capacitor switching unit 101 according to a thermometer signal s 124 at the same time . the third switch 113 and the fifth switch 115 are not conducted at this moment . in a second operating timing , a second timing signal is generated . directly conduct the third switch 113 and the fifth switch 115 . the first switch 111 , the second switch 112 and the fourth switch 114 are not conducted at the moment . the effect is sequentially switching the capacitors in the capacitor switching units to generate the input signal of the feed forward integrator 20 according to the output signal of the weighted average data circuit 50 . it is to reduce the noise caused by mismatching of capacitances . last , please refer to fig8 . it shows a circuit diagram of the differential circuit and the multi - bit quantizer 30 of the feed forward integrator 20 in the present invention . the multi - bit quantizer 30 in the present invention can be implemented by a comparator and uses a continuously progressive control circuit to generate a quantization reference control signal s 31 for adjusting a comparative level of the comparator so that the comparator generates a multi - bit modulation output signal s 32 . while the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments , it is to be understood that the invention needs not be limited to the disclosed embodiments . on the contrary , it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims , which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures .