in the following , embodiments of the present invention will be described with reference to the accompanying drawings . although descriptions below explain embodiment examples of emi evaluation of an lcd as an example of an image display apparatus , the present invention is applicable to other image display apparatuses such as a pdp ( plasma display panel ) display apparatus , an el ( electro luminescence ) display apparatus and so on . [ 0026 ] fig2 shows a block diagram of an lcd 1 of the embodiment of the present invention . the lcd 1 of fig2 includes a timing controller 10 , a gate driver 11 , a source driver 12 , a liquid crystal panel 13 , and an oscillator 14 . that is , the lcd 1 of fig2 does not require a signal ( for example , a display enable signal , and a display data signal ) from an external source in displaying a predetermined screen for emi evaluation . the oscillator 14 , such as a crystal oscillator , generates a clock signal ck , and supplies the generated clock signal ck to the timing controller 10 . the timing controller 10 generates a gate driver control signal ( for example , a gate clock signal gclk , and a gate start signal gst ) that controls the gate driver 11 , using the supplied clock signal ck , and transmits the gate driver control signal to the gate driver 11 . the timing controller 10 further generates a source driver control signal ( for example , a dot clock signal dck , an output - control signal lp , a polarity signal pol , a display data signal dxx , and a data start signal dst ) that controls the source driver 12 , using the supplied clock signal ck , and transmits the source driver control signal to the source driver 12 . that is , the timing controller 10 of fig2 generates the gate driver control signal , and the source driver control signal , using the clock signal ck . details of process that generate the gate driver control signal and the source driver control signal using the clock signal ck are given later . further , the gate driver 11 and the source driver 12 display a predetermined image for emi evaluation on the liquid crystal panel 13 according to the gate driver control signal and the source driver control signal . the predetermined image for emi evaluation includes one or more h - patterns aligned horizontally and one or more the h - patterns aligned vertically . an example of an h - pattern is shown in fig3 . the h - pattern in this example occupies a dot matrix of 15 × 12 , and uses a black dot as a background , and a white dot to represent an h - pattern . here , row numbers 0 - 14 are given to horizontal lines from top to bottom , and column numbers 0 - 11 are given to vertical columns from left to right . hereafter , processing of the timing controller 10 is explained in detail . fig4 shows a block diagram of the timing controller 10 of the embodiment of the present invention . the timing controller 10 of fig4 includes input terminals 21 and 22 , output terminals 23 - 25 , an internal - timing start checking circuit 31 , a horizontal cycle counter 32 , a vertical cycle counter 33 , a control signal generating circuit 34 , an h - pattern horizontal cycle counter 35 , an h - pattern vertical cycle counter 36 , and an h - pattern generating circuit 37 . the input terminal 21 is connected to the oscillator 14 . a clock signal ck is supplied to the internal - timing start checking circuit 31 from the input terminal 21 . in addition , the input terminal 22 may be connected to the pc 2 through the cable 3 , if necessary . when the pc 2 is connected to the input terminal 22 by the cable 3 , a display enable signal enab as a display - position control signal is supplied to the internal - timing start checking circuit 31 from the input terminal 22 . the internal - timing start checking circuit 31 switches a timing mode between an external timing mode and an internal - timing mode , depending upon whether or not the display enable signal enab is supplied from the input terminal 22 . here , the external timing mode is the mode that displays an image on the liquid crystal panel 13 according to a signal ( for example , a clock signal , a display enable signal , a display data signal ) received from the pc 2 . conversely , the internal - timing mode is the mode that displays an image on the liquid crystal panel 13 according to the signal ( for example , the gate driver control signal , the source driver control signal ) generated by the timing controller 10 . for example , the internal - timing start checking circuit 31 counts the number of clock pulses while a level of the display enable signal enab supplied does not change , and when the counted number reaches a predetermined value , the mode is changed from the external timing mode to the internal - timing mode . in addition , if the level of display enable signal enab changes while operating under the internal - timing mode , the internal - timing start checking circuit 31 switches the mode from the internal - timing mode to the external timing mode . when the internal - timing start checking circuit 31 switches the mode from the external timing mode to the internal - timing mode , a pulse that starts the internal - timing mode is supplied to the horizontal cycle counter 32 . when the pulse that starts the internal - timing mode is received from the internal - timing start checking circuit 31 , the horizontal cycle counter 32 starts counting the clock pulses ck supplied from the input terminal 21 . the horizontal cycle counter 32 resets a counted number when the counted number reaches a predetermined value ( for example , the number of clock pulses equivalent to one horizontal cycle ), while supplying a one - clock - wide pulse to the vertical cycle counter 33 , the control signal generating circuit 34 , and the h - pattern vertical cycle counter 36 . further , the horizontal cycle counter 32 supplies a display - position start signal itmstart that indicates a display - position start ( for example , left end of a display area ) to the h - pattern horizontal cycle counter 35 and the h - pattern vertical cycle counter 36 . the vertical cycle counter 33 counts the number of the one - clock - wide pulses supplied from the horizontal cycle counter 32 , resets the counted number , when the counted number reaches a predetermined value ( for example , the number of the pulses equivalent to one vertical cycle ), and supplies a one - clock - wide pulse to the control signal generating circuit 34 . the timing controller 10 generates a horizontal cycle and a vertical cycle by the horizontal cycle counter 32 and the vertical cycle counter 33 , respectively . the control signal generating circuit 34 generates the gate driver control signal and the source driver control signal , using the one - clock - wide pulse supplied from the horizontal cycle counter 32 , and the one - clock - wide pulse supplied from the vertical cycle counter 33 , respectively . further , the control signal generating circuit 34 outputs the source driver control signal from the output terminal 24 , while outputting the gate driver control signal from the output terminal 23 . the h - pattern horizontal cycle counter 35 starts counting the number of the clock pulses ck supplied from the input terminal 21 , when the display - position start signal itmstart is supplied from the horizontal cycle counter 32 . the h - pattern horizontal cycle counter 35 counts the number of clock pulses that corresponds to the horizontal cycle of the h - pattern ( for example , 0 - 11 of the h - pattern of fig3 ), and supplies the counted number to the h - pattern generating circuit 37 . in addition , the h - pattern horizontal cycle counter 35 resets the counted number , when the number of clocks equivalent to the horizontal cycle of the h - pattern is reached . the h - pattern vertical cycle counter 36 counts the number of the one - clock - wide pulses supplied from the horizontal cycle counter 32 . the h - pattern vertical cycle counter 36 counts the number of the pulses that corresponds to the vertical cycle of the h - pattern ( for example , 0 - 14 of the h - pattern of fig3 ), and supplies the counted number to the h - pattern generating circuit 37 . in addition , the h - pattern vertical cycle counter 36 resets the counted number when the number of the pulses equivalent to the vertical cycle of the h - pattern is reached . the h - pattern generating circuit 37 generates the display data according to the h - pattern using the counted number supplied from the h - pattern horizontal cycle counter 35 , and the counted number supplied from the h - pattern vertical cycle counter 36 . the h - pattern generating circuit 37 outputs the generated display data from the output terminal 25 . in the case of the h - pattern of fig3 for example , the h - pattern horizontal cycle counter 35 supplies the numbers of counts 0 - 11 , and the h - pattern vertical cycle counter 36 supplies the numbers of counts 0 - 14 , each to the h - pattern generating circuit 37 . here , the h - pattern of fig3 is configured by black lines ( line numbers 0 , 1 , 13 , and 14 ) which consist of only black cells , black - and - white mixed lines ( line numbers 2 - 6 , 8 - 12 ) for vertical strokes of the character “ h ”, and a line ( line number 7 ) for a horizontal stroke of the “ h ”. the black lines are displayed by the h - pattern generating circuit 37 generating a display data signal of 12 consecutive black dots , and outputting from the output terminal 25 . in the case of the black - and - white mixed lines , the h - pattern generating circuit 37 generates “ black , black , black , white , black , black , black , black , white , black , black and black ” dots in this sequence and outputs from the output terminal 25 . in the case of displaying the horizontal stroke , the h - pattern generating circuit 37 generates three black dots , six white dots and three black dots in this order , and outputs from the output terminal 25 . selection of a black line , a black - and - white mixed line , and a line for the horizontal stroke can be performed by matching a counted number 0 - 14 supplied from the h - pattern vertical cycle counter 36 , and the line numbers 0 - 14 . thus , it is possible to generate a display data signal representing the h - pattern by using a counter that is reset according to the horizontal and vertical cycle of the h - pattern . [ 0050 ] fig5 shows a block diagram of the h - pattern horizontal cycle counter 35 of the embodiment of the present invention . the h - pattern horizontal cycle counter 35 of fig5 includes not circuits 40 and 41 , and circuits 42 and 43 , an or circuit 44 , a jk - flip - flop circuit ( henceforth a jk - ff circuit ) 45 , and a counter circuit 46 . hereafter , processing of the h - pattern horizontal cycle counter 35 is explained , referring to a timing chart of fig6 that shows operational timing of an example of the h - pattern horizontal cycle counter 35 . the display - position start signal itmstart such as shown by ( b ) in fig6 is supplied from the horizontal cycle counter 32 to the or circuit 44 . in the present embodiment , the display - position start signal itmstart is active when at a high level , and expresses the display - position start . if the display - position start signal itmstart becomes high , the or circuit 44 will supply the high - level signal to the terminal j of the jk - ff circuit 45 . when the high - level signal is supplied to terminal j , the jk - ff circuit 45 supplies the high - level signal hldn as shown by ( c ) of fig6 to a terminal ldn of the counter circuit 46 . when the high - level signal hldn is supplied to the terminal ldn , the counter circuit 46 starts counting the clock signal ck as shown by ( d ) of fig6 which is supplied from the input terminal 21 . the counter circuit 46 outputs a counted number of clock pulses of the clock signal ck as shown by ( a ) of fig6 ( a ) in a binary number from terminals qa - qd . for example , when the counted number is 11 , the outputs are 1 from terminal qa , 1 from terminal qb , 0 from terminal qc and 1 from terminal qd . the counter circuit 46 supplies the output counted number to the h - pattern generating circuit 37 . the and circuit 43 supplies a high - level signal to a terminal k of the jk - ff circuit 45 , when the counted number output from the counter circuit 46 is 10 . the jk - ff circuit 45 changes the level of the signal hldn to low as shown by ( c ) of fig6 which is supplied to the terminal ldn of the counter circuit 46 , when the high - level signal is supplied to the terminal k . the counter circuit 46 resets the counted number of the clock signal ck , when the signal hldn indicating the low level is supplied to terminal ldn . the and circuit 42 supplies a high - level signal to the terminal j of the jk - ff circuit 45 through the or circuit 44 , when the counted number output from the counter circuit 46 is 11 . the jk - ff circuit 45 supplies the signal hldn in the high level to the terminal ldn of the counter circuit 46 , when the high - level signal is supplied to the terminal j . the counter circuit 46 starts counting the number of clock pulses of the clock signal ck , when the high - level signal hldn is supplied to terminal ldn . therefore , the h - pattern horizontal cycle counter 35 counts the number of clocks equivalent to the horizontal cycle of the h - pattern ( for example , 0 - 11 in fig5 ), and supplies the counted number to the h - pattern generating circuit 37 . [ 0058 ] fig7 shows a block diagram of an h - pattern vertical cycle counter 36 of the embodiment of the present invention . the h - pattern vertical cycle counter 36 of fig7 includes an and circuit 50 , a jk - ff circuit 51 , and a counter circuit 52 . processing of the h - pattern vertical cycle counter 36 is explained , referring to the timing chart of fig8 that shows operational timing of an example of the h - pattern vertical cycle counter 36 . the display - position start signal itmstart , as shown by ( c ) of fig8 is supplied from the horizontal cycle counter 32 to a terminal j of the jk - ff circuit 51 . when a high - level signal is supplied to the j terminal , the jk - ff circuit 51 supplies a high - level signal vldn , as shown by ( d ) of fig8 to a terminal ldn of the counter circuit 52 . when the high - level signal vldn is supplied to the terminal ldn , the counter circuit 52 starts counting the number of 1hpls pulses , shown by ( b ) of fig8 supplied from the horizontal cycle counter 32 for every 1 horizontal cycle . the counter circuit 52 counts the number of the 1hpls pulses , as shown by ( a ) of fig8 ( a ), and outputs the number in a binary number from terminals qa , qb , qc and qd . for example , when the counted number is 7 , 1 is output from the terminal qa , 1 is output from the terminal qb , 1 is output from the terminal qc , and 0 is output from the terminal qd . the counter circuit 52 supplies the output counted number to the h - pattern generating circuit 37 . when the counted number output from the counter circuit 52 is 15 , the and circuit 50 supplies a high - level signal to the terminal k of the jk - ff circuit 51 . the jk - ff circuit 51 supplies the signal vldn in a low level as shown by ( d ) of fig8 to the terminal ldn of the counter circuit 52 , if a high - level signal is supplied to the terminal k . the counter circuit 52 will reset the counted number of the 1hpls pulses , when the signal vldn of a low level is supplied to the terminal ldn . accordingly , the h - pattern vertical cycle counter 36 counts the number equivalent to the vertical cycle of the h - pattern ( for example , 0 - 15 in fig5 ), and supplies the counted number to the h - pattern generating circuit 37 . [ 0064 ] fig9 shows a block diagram of an h - pattern generating circuit 37 of the embodiment of the present invention . the h - pattern generating circuit 37 of fig9 includes or circuits 60 , 65 , 69 , 74 , and 76 , and and circuits 61 - 64 , 66 - 68 , 70 - 73 and 75 . incoming signals hpth 1 - 4 of fig9 are the same as hpth 1 - 4 signals output from the counter circuit 46 of fig5 respectively . incoming signals hptv 1 - 4 are the same as signals hptv 1 - 4 output from the counter circuit 52 of fig7 respectively . incoming signals xhptv 1 - 4 and xhpth 1 - 4 are reverse signals of the incoming signals hptv 1 - 4 and hpth 14 , respectively . here , inverter circuits that generate the reverse signals are omitted . the and circuit 61 outputs a high - level signal to the or circuit 65 , when the counted number output from the counter circuit 52 is one of 2 and 3 . the and circuit 62 outputs a high - level signal to the or circuit 65 , when the counted number output from the counter circuit 52 is one of 4 , 5 and 6 . the and circuit 63 outputs a high - level signal to the or circuit 65 , when the counted number output from the counter circuit 52 is one of 8 through 11 . the and circuit 64 outputs a high - level signal to the or circuit 65 , when the counted number output from the counter circuit 52 is 12 . accordingly , the or circuit 65 outputs the signal verlnv which becomes high - level to the and circuit 70 , when the counted number output from the counter circuit 52 is one of 2 through 6 , and 8 through 12 . in other words , the signal verlnv becomes high when the black - and - white mixed lines are processed . on the other hand , the and circuit 66 outputs to the and circuit 75 a signal horlnv that becomes high , when the counted number output from the counter circuit 52 is 7 . in other words , the signal horlnv becomes high when processing the line that includes the horizontal stroke of the character “ h ”. the and circuit 67 outputs a high - level signal to the or circuit 69 , when the counted number output from the counter 46 is 3 . the and circuit 68 outputs a high - level signal to the or circuit 69 , when the counted number output from the counter 46 is 8 . consequently , the or circuit 69 outputs to the and circuit 70 a signal that becomes high , when the counted number outputted from the counter circuit 46 is one of 3 and 8 . accordingly , the and circuit 70 outputs a signal that becomes high to the or circuit 76 , when the counted number output from the counter circuit 52 is one of 2 through 6 , and 8 through 12 , and when the counted number output from the counter circuit 46 is one of 3 and 8 . in other words , the and circuit 70 outputs to the or circuit 76 a signal that becomes high when one of the line numbers 2 through 6 and 8 through 12 , and one of the column numbers 3 and 8 of the h - pattern of fig3 are processed . on the other hand , the and circuit 71 outputs a high - level signal to the or circuit 74 , when the counted number output from the counter 46 is 3 . the and circuit 72 outputs a high - level signal to the or circuit 74 , when the counted number output from the counter circuit 46 is one of 4 through 7 . further , the and circuit 73 outputs a high - level signal to the or circuit 74 , when the counted number output from the counter circuit 46 is 8 . consequently , the or circuit 74 outputs to the and circuit 75 a signal that becomes high , when the counted number outputted from the counter circuit 46 is one of 3 through 8 . accordingly , the and circuit 75 outputs to the or circuit 76 a signal that becomes high , when the counted numbers output from the counter circuit 52 is 7 , and when the counted number output from the counter circuit 46 is one of 3 through 8 . in other words , the and circuit 75 outputs to or circuit 76 a signal that becomes high when the line number 7 , and one of the column numbers 3 through 8 of the h - pattern of fig3 are processed . as mentioned above , the or circuit 76 can output display data corresponding to the h - pattern as shown in fig3 . although this embodiment is explained around an example of outputting display data of the h - pattern , it is possible to output display data corresponding to various patterns by changing the combination of the logical circuits of the h - pattern horizontal cycle counter 35 , the h - pattern vertical cycle counter 36 , and the h - pattern generating circuit 37 . in the manner described above , a predetermined test image can be displayed without having to receive display data from an outside source via a cable , both of which are sources of disturbance when ascertaining an emi level of a display apparatus to be examined . further , the present invention is not limited to these embodiments , but various variations and modifications may be made without departing from the scope of the present invention . the present application is based on japanese priority application no . 2001 - 251720 filed on aug . 22 , 2001 with the japanese patent office , the entire contents of which are hereby incorporated by reference .