now referring to the drawings wherein like numerals refer to like matter throughout , and more specifically referring to fig1 there is shown a system of the present invention generally designated 100 , including a main system microprocessor 102 , which could be any type of processor which is capable of both executing the programs in main system memory 106 and administering the system 100 . main system memory 106 is coupled to main system microprocessor 102 via memory access bus 104 . main system memory 106 can be any suitable ram memory . in a preferred embodiment , main system memory 106 is a partitioned ram memory having “ n ” partitions of either a physical or logical nature . each partition contains an independent proprietary avionics software program . several competing avionics manufacturers can be the sources for these programs . memory access bus 104 can be any suitable data bus . coupled to memory access bus 104 is debug dump memory 108 . this debug dump memory 108 is preferably any type of ram memory which is capable of rapidly receiving large amounts of data from memory access bus 104 . debug dump memory controller / processor 110 can be a microprocessor , a programmable logic device , or any direct memory access controller which will facilitate the copying of the desired data in main system memory 106 to debug dump memory 108 , so such data can be used by another processor which is independent of main system microprocessor 102 and which will perform debugging operations . these debugging operations may be done either synchronously or asynchronously , depending upon the precise overall system application . debug dump transmitter 112 and debug control transceiver 114 are shown as intermediate structure and / or functions which may be support for or part of the debugging processor 116 , which could be a general purpose microprocessor or any application specific integrated circuit or other computing device capable of performing debugging operations or an external storage device or combination thereof . in operation , the apparatus and method of the present invention as described in fig1 could function as follows : the partitions of main system memory 106 are executed by main system microprocessor 102 in a context switching arrangement , which is when the main system microprocessor 102 brings one partition into focus , and the code resident therein is allowed to actually execute . fig1 shows two lines between the partition n − 1 and the memory access bus 104 . this depicts that this partition is currently the one being executed by main system microprocessor 102 . when a partition is switched into context , the code therein is executed until either 1 ) it is finished ( non - preemptive scheduler ) or 2 ) until main system microprocessor 102 detects that it is time to suspend further execution of that partition ( preemptive scheduler ). at this time , the contents of all registers and transitory memory locations are saved into main system memory 106 ; i . e ., it is “ switched out .” the scheduler function performed by main system microprocessor 102 , or another device , then cycles to the next partition and switches it in for execution . the process is repeated until all “ n ” partitions have been switched in and out . in all cases , the contents of the memory locations preserve the final or intermediated products of the processes which run during the partition time . when all partitions have had their execution time , then main system microprocessor 102 transfers control of memory access bus 104 to debug dump memory controller / processor 110 for a short time to allow for the debug dump process to occur . during the time that debug dump memory controller / processor 110 has control of memory access bus 104 , the actions are merely reading one or more chosen memory locations in main system memory 106 and simultaneously writing such data into debug dump memory 108 . due to its dedicated function and use of direct memory access , data is copied into the debug dump memory 108 at a much higher rate than data would be processed if the main system microprocessor 102 were to perform the debugging operations itself . after the desired data is copied into debug dump memory 108 , control of memory access bus 104 is switched back to main system microprocessor 102 , which then begins to cycle through the partitions executing the code therein . during this time when main system microprocessor 102 is executing the partitions of main system memory 106 , the debug dump memory 108 is “ off line ” and is accessible to debugging processor 116 . this system allows for simultaneous normal operation and debugging operations . it should also be noted that the system 100 does not require that an entire copy of main system memory 106 be made for debugging purposes because it allows debug dump memory controller / processor 110 to have access to whatever portions of main system memory 106 as are necessary to perform the desired debugging operations . throughout this description , reference is made to avionics and partitioned computers and to partitioned proprietary avionics software programs , because it is believed that the beneficial aspects of the present invention would be most readily apparent and valuable when used in connection with such computers and such programs ; however , it should be understood that the present invention is not intended to be limited to avionics computers , partitioned computers , or avionics software programs and should be hereby construed to include other non - avionics , non - partitioned computers and non - avionics software programs as well . it is thought that the method and apparatus of the present invention will be understood from the foregoing description and that it will be apparent that various changes may be made in the form , construct steps , and arrangement of the parts and steps thereof , without departing from the spirit and scope of the invention or sacrificing all of their material advantages . the form herein described is merely a preferred exemplary embodiment thereof .