reference will now be made in detail to the present preferred embodiments of the invention , examples of which are illustrated in the accompanying drawings . wherever possible , the same reference numbers are used in the drawings and the description to refer to the same or like parts . in the following embodiment , a two - layered defer queue is used as an example of the multiple - layer defer queue . however , anyone familiar with the technology knows that the invention is actually applicable to a multiple - layer defer queue having at least two layers . [ 0022 ] fig1 is a block diagram showing a control chip having a multiple - layer defer queue therein according to one preferred embodiment of this invention . as shown in fig1 the control chip 10 is coupled to a cpu bus 102 and a pci bus 112 . the control chip 10 at least includes a pci request queue ( pcq ) 106 , a multiple - layer defer queue ( dfq ) 104 , a pci access queue ( paq ) 108 and a pci controller ( pcic ) 110 . the multiple - layer defer queue 104 is able to store a plurality of defer request records , such as two . each defer request record at least includes an identification code field , an effective data field and a flag field . the pci request queue 106 and the pci access queue 108 are able to store a plurality of pci request records . each pci request record at least includes an identification code field . according to the foregoing structure of control chip with multiple - layer defer queue , it can be achieved to have multiple - layer defer queue to simultaneously support transactions of retry and defer by using the identification code field , the effective data field and the flag field . when the cpu issues a second - type request at the cpu bus 102 , this second - type request is stored in the pci request queue 106 , and the identification code field of the pci request record will be filled with 00 . the code 00 represents that this second - type request does not exit in the multiple - layer defer queue . then , the control chip responds to the cpu again , causing the cpu to treat the second - type request as one request which has been accomplished . the second - type request together with the pci request record are shifted to the pci access queue 108 and wait for the pci controller 110 to be sent to the pci bus 112 . when the cpu issues a first - type request at the cpu bus 102 , this first - type request is stored in the pci request queue 106 . if the multi - layer dfq 104 is fully occupied , the control chip then issues a retry response to the cpu . then , the identification code field of the pci request record in the pci request queue 106 is filled with 00 . the code 00 represents that this first - type request does not exit in the multiple - layer defer queue . this first - type request and the pci request record are not shifted to the pci access queue 108 . in other words , the retry response with respect to the first - type request is not sent by the pci controller 110 to the pci bus 112 . when the multi - layer dfq 104 inside the control chip is not yet fully occupied , the first - type request is stored the multi - layer dfq 104 and the pci request queue 106 , and the identification code fields of the dfq request record and the pci request record are filled with the same identification code , which is 01 or 10 because the invention has two dfq layers with different identification codes . then , according to whether or not the defer bit in the first - type request is enabled , it is determined to issue a defer response or a retry response to the cpu , which information will be stored in the flag field . after then , the first - type request together with the pci request record are transferred to the pci access queue 108 via the pci request queue 106 , and waits for being transmitted to the pci bus 12 by the controller 110 . after the first - type request receives the response from the pci bus and the responded data , wherein the status can be known from the content of 01 , 10 in the identification code field , the pci controller 112 will fill an enable into the effective data filed . if the first - type request is a defer response , which can be judged according to the flag field , then the data is directly sent to the cpu and the transaction accomplishes . the first - type request in the multi - layer dfq 104 is deleted . if the first - type request is a retry response , which can be judged according to the flag field , then the data is temporarily stored in the control chip . when the next identical first - type request is issued by the cpu , then , the data is directly sent to the cpu and the transaction accomplishes . then , the first - type request in the multi - layer dfq 104 is deleted . additionally , in order to make the multiple - layer defer queue to simultaneously support transactions of retry and defer , when the cpu issues the first - type request , it is necessary to check whether or not the multiple - layer dfq 104 has stored the first - type request , which may also be the first - type request of retry response previously issued by the control chip . when it is assured that the first - type request has been stored in the multi - layer dfq 104 , it should proceed another check to see whether or not the data in stored in the multi - layer dfq 104 at the effective data field has the enable . ( i ) in the situation of disable , the control chip issues a retry response to the cpu . the identification code field of the pci request record is filled with 00 . this first - type request and the pci request record are not stored in the pci access queue 108 . ( ii ) in the situation of enable , the control chip will respond to the cpu with the data and the transaction accomplishes . the first - type request stored in the multi - layer dfq is deleted . the identification code field of the pci request record is filled with 00 . the first - type request and the pci request record are not shifted to the pci access queue 108 . [ 0028 ] fig2 is a flow chart showing the steps for a control chip having a multiple - layer defer queue therein to process cpu requests picked up from a cpu bus according to one preferred embodiment of this invention . fig3 is a flow chart showing the steps for a control chip having a multiple - layer defer queue therein to process a pci bus response picked up from a pci bus according to one preferred embodiment of this invention . the following is a full description of the operation of the control chip with reference to fig1 and 3 . the control chip 10 receives a cpu request through the cpu bus 102 . then the cpu request is transferred to the pci request queue 106 for storage ( in step s 200 ). if the cpu request is a first - type request , that is , an input / output read request , an input / output write request or a memory read request ( in the step s 202 ), then it is checked whether or not the first - type request is existing in the multi - layer dfq 104 ( as shown in step s 208 ). when the multi - layer dfq 104 has stored the first - type request , the effective data field of the request record in the dfq is check whether or not is an enable ( in step s 210 ). in the situation of disable , the control chip issues a retry response to the cpu ( in step s 216 ). the identification code field of the pci request record is filled with 00 ( in step s 218 ) and the request is accomplished . in the situation of enable , the control chip will respond to the cpu with the data and the transaction accomplishes . the first - type request stored in the multi - layer dfq is deleted ( in step s 212 ). the identification code field of the pci request record is filled with 00 ( in step s 214 ) and the request is accomplished . when the multi - layer dfq 104 has not stored the first - type request , and the multi - layer dfq 104 still has no sufficient storage space ( as shown in step s 220 ), then the control chip issues a retry response to cpu ( as shown in step s 216 ). then , the identification code field of the pci request record is filled with 00 ( as shown in step s 218 ), and the request is accomplished . when the multi - layer dfq 104 has not stored the first - type request , and when the multi - layer dfq 104 still has storage space ( in step s 220 ), then an identification code of 01 or 10 is assigned to both of the identification code field of the request record of dfq and the request record of pci queue ( in step s 222 ). it is judged whether or not the first - type request can provide defer response ( in step s 224 ). if the first - type request can provide defer response , then a defer flag is assigned to the flag field of the request record in dfq ( in step s 226 ). the defer response is responded to cpu bus 102 ( in step s 228 ). if the first - type request cannot provide defer response , then a retry flag is assigned to the flag field of the request record in dfq ( in step s 230 ) and the retry response is responded to the cpu bus 102 ( in step s 232 ). then , the pci request record in the pci request queue 106 is stored in the pci access queue 108 ( in step s 206 ). after that , the pci controller 110 takes out the first - type request of the pci access queue 108 and sends it to the pci bus 112 ( in step 234 ). when the cpu request is a second - type request , that is , a write - in request for the memory , then an identification code of 00 is assigned to the identification code field of the pci request record in the pci access queue ( in step s 204 ), and an accomplishing response is responded to the cpu bus 102 ( in step s 236 ), and the transaction is accomplished . then , the pci request record in the pci request queue 106 is stored into the pci access queue 108 ( in step s 206 ). afterward , the pci controller 110 takes out the second - type request of the pci access queue 108 and sends it to the pci bus 112 ( in step 234 ). when the pci controller 110 receives a response from the pci bus 112 and the requested data ( in step s 310 ), the pci controller 110 first judges whether or not the identification code field is filled with 01 or 10 ( in step s 320 ). if the identification code is not the 01 or 10 , it indicates that the request is a second - type request . if the identification code is 01 or 10 , then a dfq request record with a value in the identification code field being the same as the value of the identification code is searched from the request records in the multi - layer dfq 104 , according to the value of the identification code . then , the effective data field of the dfq request record , which has the value in the identification code field being the same as the value of the identification code , is enabled ( in step s 330 ). afterward , the flag field is judged whether it indicates a defer response or a retry response ( in step s 335 ). if the flag field of the dfq request record , which has the value in the identification code field being the same as the value of the identification code , is a defer flag , then the control chip 10 actively sends the requested data to the cpu bus 102 . also and the request record , having the value in the identification code field being the same as the value of the identification code , is deleted ( in step s 340 ). if the flag field of the dfq request record , which has the value in the identification code field being the same as the value of the identification code , is a retry flag , then the control chip 10 temporarily stores this data until the same first - type request is again issued to the control chip . 1 . the system is capable of processing a plurality of first - type requests from the cpu . moreover , the multiple - layer defer queue supports retry and defer transactions concurrently . 2 . the amount of data shuttling between the cpu and the control chip is greatly reduced so that the system efficiency and performance is improved . it will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention . in view of the foregoing , it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents .