embodiments of the present invention will now be described in detail with reference to the accompanying drawings . fig1 is a block diagram of a power quality monitoring apparatus for a railway power system according to an embodiment of the present invention and fig2 shows a photograph of the power quality monitoring apparatus for the railway power system according to the embodiment of the present invention . as the power quality monitoring apparatus 2 for the railway power system according to an embodiment of the present invention , a monitoring device for collecting data in real time was manufactured and tested by woojin industrial systems co ., ltd . here , tsm320c32 was used as a digital signal processor that performs main calculations and data values was collected at 5 ms sampling . sampled data was recorded on a compact flash ( cf ) card and the recorded data was analyzed through a pc analysis program and is then output as graphical data . table 1 shows details of main components of the power quality monitoring apparatus 2 for the railway power system according to an embodiment of the present invention . the power quality monitoring apparatus 2 for the railway power system according to an embodiment of the present invention includes voltage detectors 6 and 12 and current detectors 8 and 14 , a signal input unit 16 , a signal converter 18 , a converter 20 , a memory 22 , a communication module 28 , a display driver 30 , and a display unit 32 . the voltage detectors 6 and 12 and the current detectors 8 and 14 are provided in a power supply portion 4 and a load 10 , respectively , to detect voltage and current levels . the signal input unit 16 receives signals from the voltage detectors 6 and 12 and the current detectors 8 and 14 . the signal converter 18 converts analog signals received from the signal input unit 16 into digital signals . the memory 22 includes a data storage unit 26 that stores received data in real time and a data recording unit 24 that records collected data . the display unit 32 displays monitored data . the display driver 30 drives the display unit 32 . the converter 20 receives detected current and voltage values in real time from the power supply portion 4 and the power quality monitoring apparatus 2 , monitors changes in the detected current and voltage values , stores power flow and the amount of supplied power , and transmits corresponding information to a remote location through the communication module 28 . more specifically , the converter 20 includes an arithmetic unit of a tms320c32 - 60 dsp , which is a digital signal processor that performs analog - to - digital conversion , card recording , and data operation and processing and is capable of 32 - bit floating - point calculations and is suitable for precise data processing . table 2 shows functionality and characteristics of the dsp . the display unit 32 and the display driver 30 are provided in a modular form . for example , the display unit 32 and the display driver 30 are designed as a graphic lcd module which generally includes an interface unit , a controller , a display unit , and a backlight unit . an lsi including a character generator ( cg ) rom , a cg ram , and a display data ram , which correspond to main elements of the graphic lcd module , was first developed in japan and thus the character cg rom has a function to display japanese characters . signal or power units for connecting the lcd module to the cpu include 14 - pin terminals , where 15th and 16th pins are added to perform backlight functions . the signal converter 18 uses an ad7891as - 1 a / d converter and is used to receive and convert analog signals such as current , voltage , or variable load signals into digital values . fig3 is a circuit diagram of the signal converter 18 . the following are characteristics of the ad7891as - 1 a / d converter . fast 12 - bit adc with 1 . 6 ms conversion time eight single - ended analog input channels overvoltage protection on each channel selection of input ranges : ± 5 v , ± 10 v for ad7891 - 1 parallel and serial interface on - chip track / hold amplifier on - chip reference single supply , low power operation ( 85 mw max ) the power quality monitoring apparatus 2 for the railway power system further includes a tlp620 - 4 photocoupler which is used to isolate input and output signals . for example , the tlp620 - 4 photocoupler is used to input a dc100v level signal such as a p ( 11 ), b 0 ( 27 ), b 1 ( 28 ), b 2 ( 29 ), or door ( 145 ) signal . fig4 is a circuit diagram of the tlp620 - 4 photocoupler . the power quality monitoring apparatus 2 for the railway power system further includes an ad202jy isolation amplifier which is used to isolate input and output signals including variable load and notch input signals to minimize the influence of the monitor apparatus upon the signals when interfacing with main elements used for control of a vvvf controller . fig5 shows a circuit diagram of the ad202jy isolation amplifier . the following are characteristics of the ad202jy isolation amplifier . small size : 4 channels / lnch high cmr : 130 db ( gain = 100 v / v ) wide bandwidth : 5 khz full - power high cmv isolation : ± 2000 v pk continuous isolated power outputs the power quality monitoring apparatus 2 for the railway power system further includes a ds12c887 timer ic which is used to set a time to be stored in a recording device ( cf card ). even when control power is turned off , the time of the ds12c887 timer ic continues to advance since a battery is included . the following are characteristics of the ds12c887 timer ic . totally nonvolatile with over 10 years of operation in the absence of power self - contained subsystem includes lithium , quartz , and support circuitry . counts seconds , minutes , hours , days , day of the week , date , month , and year with leap year compensation valid up to 2100 binary or bcd representation of time and calendar 15 bytes of clock and control registers 113 bytes of general purpose ram the voltage detectors 6 and 12 included in the power quality monitoring apparatus 2 for the railway power system use a voltage sensor ( dcpt 2516 ). the following are characteristics of the voltage sensor ( dcpt 2516 ). sensor scale : 3000v / 10v rated voltage : 1800 vdc polarity : unipolar purpose : voltage measurement of filter capacitor the voltage detectors 8 and 14 included in the power quality monitoring apparatus 2 for the railway power system use a current sensor ( kll3 . 0k - 10vd ). the following are characteristics of the current sensor ( kll3 . 0k - 10vd ). sensor scale : 3000 a / 10v polarity : bipolar purpose : current measurement of inverter and siv specifically , the converter 20 included in the power quality monitoring apparatus 2 for the railway power system is provided with a tms320c32 - 60 dsp from texas instruments co ., ltd ., which is capable of real - time floating point calculations . the converter 20 includes a main controller , a dc power source that supplies control power , and an a / d board for analog input / output isolation . fig6 is a block diagram of the control board of the converter 20 . for example , the converter 20 performs status data monitoring , data collection and recording , time setting through rs232c communication with a pc , and the like . more specifically , the converter 20 includes a tms320c32 circuit and a power source monitoring circuit ( reset circuit ). fig7 is a circuit diagram of the power source monitoring circuit . the power source monitoring circuit of fig7 is used to generate a reset signal for other circuits . the power source monitoring circuit of fig7 includes a ds1232 unit . the ds1232 unit outputs a reset signal when power is equal to or less than 4 . 5v when a 3rd pin ( tol ) of the ds1232 unit has been connected to vcc and outputs a reset signal when power is equal to or less than 4 . 75v when the 3rd pin has been connected to gnd , which corresponds to a power source monitoring operation . the ds1232 unit also has a watch dog function to monitor whether or not a program of the cpu is properly running . to accomplish this , the watch dog function outputs a reset signal when no pulse is input to a 7th pin ( st ) of the ds1232 unit . the watch dog function outputs a reset signal if no pulse is input for 1 . 2 seconds when a 2nd pin ( td ) of the ds1232 unit has been connected to vcc , outputs a reset signal if no pulse is input for 150 msec when the 2nd pin ( td ) has been connected to gnd , and outputs a reset signal if no pulse is input for 500 msec when the 2nd pin ( td ) has been opened . a 1st pin ( pbrst ) of the ds1232 unit is connected to a push button to allow manual reset . the following is a more detailed description of the dsp described above . the tms320c32 circuit basically includes 24 - bit address and 32 - bit data buses . one serial port of the tms320c32 circuit may be connected to a pc through a connector for program data downloading and program monitoring and a 32 - bit and 2 - channel timer thereof allows periodic data processing . dc 5v is used as a power source voltage of the dsp and a 60 mhz crystal oscillator is used as an operation clock of the dsp . the memory 22 basically needs to include a rom and a ram . here , an 8 - bit rom and a 16 - bit ram are used for the memory 22 . fig9 is a circuit diagram of the memory . a flash rom which allows repetitive recording is basically used as the rom of the memory and an sram for program operations / calculations and a non - volatile sram ( nvsram ) for storing malfunction data are used as rams of the memory . such memory chips include an address bus input portion and a data input portion . each memory chip also includes pins ( cs or ce pins ) for receiving a chip selection signal to allow selection of the chip and input pins such as rd and wr pins . the chip selection signal is used to select each chip and is generated from logic circuits of an fpga through address decoding . fig1 shows the fpga which is programmable through logic circuits and which constitutes logic circuits for allowing the monitor pcb to control address decoding and digital input and output of each chip . since the fpga performs address decoding , an address bus signal needs to be input to the fpga . in addition , since the fpga needs to perform sequence control or malfunction processing , a digital input and a digital output need to be connected to pins of the fpga . chip selection signals of the chips and a data bus of the cpu are also connected to the fpga . the following is a description of the communication module 28 . the communication module 28 is designed such that the main control board has two communication channels . one of the two channels is designed to exchange data with a pc through rs232 communication and a serial communication controller , which is referred to as “ z85c30 ” is used for the channel . fig1 and 12 are circuit diagrams of a z85c30 circuit and an rs232 driver circuit . the other channel is designed to support additional rs485 communication . a communication port of a second channel of the z85c30 is used as a communication port of the channel for rs485 communication . fig1 shows a circuit for converting a z85c30 signal into an rs485 signal . the signal input unit 16 is used to input analog and digital signals and the main control board has current and voltage inputs as analog inputs . since variable load and notch values are used for control signals , corresponding signals need to be electrically isolated from the main control board to guarantee stability ( or reliability ). accordingly , there is a need to design and add an additional analog isolation board . fig1 shows the analog isolation circuit . as shown in fig1 , an input voltage of this circuit is divided through a resistor and is then input to an input terminal of an ad202 unit , which is an isolation amplifier , via a filter . here , the voltage division resistor needs to be highly precise and to have a capacity high enough to receive high voltage . a signal output from an output terminal of the ad202 unit is input to the cpu via a filter and a buffer . in addition , as shown in fig1 , the main control board includes 12 digital input signal channels for receiving signals at a level of dc 100v through the photocoupler . currently used channels of the 12 channels receive a powering signal ( p ), regenerative braking signals ( b 0 , b 1 , b 2 ), a notch input signal , and a door signal . the main control board included in the power quality monitoring apparatus 2 for the railway power system according to the present invention has a pcmcia connector ( see fig1 ) for inserting a compact flash ( cf ) card , which is designed to store up to 2 gigabytes . since the pins are connected to address and data buses , a control pin for controlling the cf card interfaces with the dsp through the fpga . the minimum recording unit of the cf card is 512 bytes per sector so as to simultaneously store 512 bytes . analog and digital input values are first stored in a temporary memory and then , when the stored memory size reaches a memory size corresponding to the minimum recording unit , the values are recorded in the cf card . data recorded in the cf card is divided into a header , a body , and measured data that is calculated as a power value . 64 × 1 , 024 bytes are recorded as one block and the maximum number of blocks is 30 , 720 such that the total capacity is 2 gigabytes . when blocks are recorded , each block includes 1 header and 1820 bodies . tables 5 and 6 show configurations of header and body memory maps . the time required to record one memory block is the time required to record a sampling period of 5 ms 1 , 820 times such that the required time is a total of 9 . 1 seconds . accordingly , the time required to record the total memory size of 2 gigabytes is 279 , 552 seconds (= 30 , 720 blocks × 9 . 1 seconds ) which is 77 . 65 hours . when the recorded time exceeds this time , data is again recorded in initial - state blocks , overwriting previous data . as is apparent from the above description , the power quality monitoring apparatus for the railway power system according to the present invention has a variety of advantages . for example , it is possible to monitor changes in voltage and current values of trains , which are loads , and ac lines to output the changes in the voltage and current values , power consumption , and power flow in a graphical or text format , thereby making it possible to easily determine overall overhead line environments . the power quality monitoring apparatus for the railway power system according to the present invention is not limited to the above embodiments and may be modified in various ways without departing from the spirit of the present invention .