fig1 shows a driving method according to one embodiment of the present invention . the display elements are formed on the crossing portions between the scanning and signal electrodes , arranged in the form of a matrix . the flat display device is driven by two segment and scanning side driving circuits of the transparent electrode ( i . e . ito ( indium tin oxide )). the amplitudes of the voltages simultaneously applied to the both ends of the scanning and signal side driving circuits are equal . a shift clock input , xscl , is input to a shift register 2 . in addition , the display data , xd , is switched in parallel into shift register 2 . shift clock input , xscl , is synchronized with a latch signal , lp , by a latch 3 , and display data , xd , is converted through a level shifter 4 and driver 5 to a liquid crystal driving waveform having an amplitude equal to one of four voltage levels employed in the voltage standard method to either activate or deactivate each display element . fig1 also illustrates the functioning of the scanning driving circuits . a shift register 6 receives a start pulse , yd , and latch signal , lp . the output of shift register 6 is converted to a liquid crystal driving waveform by a level shifter 7 and a driver 8 . when power is applied to the flat display device ( i . e . power - on ), the circuits become unstable , and the output voltages of the two driving circuits which are connected to each other through a transparent electrode are not equal . since the liquid crystal driving voltage is 20 - 40 v , a current of several hundred μa - several ma is applied across each electrode during each output period . this amount of current causes degradation of the driving circuit and liquid crystal panel . therefore a driving circuit is provided to control the output for a predetermined time until the waveform of the driving circuit is stabilized by a prohibit signal , inh , at the time of power - on in order to create a short circuit across the liquid crystal panel . fig3 is an electronic model of the driving circuit according to a dot matrix flat display device of the present invention . in fig3 × 3 matrix panel is driven from both terminals of the scanning electrodes . display element a signifies the display element farthest from either terminal of a scanning electrode driven by a dual driving mechanism in accordance with the present invention . display element b represents the display element farthest from the terminals of a scanning electrode driven by a single driving circuit in accordance with the prior art . resistance values between the driving circuit and the portions a and b are as follows : herein , r c and r s are the resistance between display elements , and r c and r s are the output resistances of the driving circuits . r c is greater than or equal to 1 kω . when the number of display elements is increased , r c increases to several hundred or more kω and the value of r c becomes negligible . therefore , when the number of display elements is increased , the resistance ratio a : b approaches 1 : 4 . since the capacitor , c , coupled to the electrodes is not changed , the display quality obtained according to the driving method of the present invention is the same as that of the prior driving method while the resistance of the transparent electrodes is reduced to one quarter . since the display quality of the present invention is the same as that of the prior art , a liquid crystal cell having twice as many display elements can be realized while preserving the high resolution of the flat display . fig4 shows one embodiment of the scanning driving circuit . the circuitry which is surrounded by a dotted line 42 shows the driving circuits for one scanning electrode . two circuits are utilized for each electrode . each circuit is coupled to the next and previous electrode circuits . the portion surrounded by the dotted line 43 shows circuitry which utilizes high a . c . voltages as opposed to the other portions of the circuit which utilize digital logic . in fig4 a shift register which is operated by a shift clock , sck , is comprised of a d type flip flop 21 . a latch signal , lp , shown in fig1 is input to the shift clock , sck . therefore , the output d n + 1 is input to the d type flip flop input , dn , of the next electrode driving circuit in accordance with shift clock , sck . in addition , a start pulse , yd , is input to flip flop 21 . the output of flip flop 21 , q n is connected to the inputs i and i of the level shifter 23a through nor gate 24 which can force the driver output , out , to an equivalent electric level depending on the state of prohibit signal , inh . the outputs o and o of the level shifter are connected to the transfer gates 26 and 27 of a co - compensative transistor . in addition , the outputs , o and o , are connected to the input of the nor gate 32 and nand gate 31 respectively . nor gate 32 and nand gate 31 are utilized to change the non - selected potential to a . c . the signal which is obtained by combining the frame signal , fr , with prohibit signal , inh , through the nor gate 36 is input to the other sides of nand gate 31 and nor gate 32 through the level shifter 23b and an invertor 38 . the outputs of nand gate 31 and nor gate 32 are connected to a transfer gate 28 of a p channel transistor and a transfer gate 29 of an n channel transistor , respectively to control the output of the non - selected levels v 1 and v 4 . the selected voltages , v 0 and v 5 are multiplexed by the transfer gate 40 of the p channel transistor and the transfer gate 41 of the n channel transistor . the output o of the level shifter 23b acts as a gate input to each transistor . in addition level shifter 23b outputs , o and o are also connected to the gates of co - compensative transistors 26 and 27 . when only the output , q n , of shift register 21 is high , transfer gates 26 and 27 are conductive and the &# 34 ; select &# 34 ; voltage level is transmitted to the output , out . when prohibit signal , inh , is high , transfer gates 26 and 27 are conductive , thus the driver output out remains high ( i . e . v 5 or v ). therefore , when the flat display device and thus the driving circuit is on , and prohibit signal , inh , is high , the outputs of drivers 8 , out , are at the same voltage level , so that current cannot flow across the electrode and damage the liquid crystal . as a matter of course , the level of the equivalent voltage potential need not be only v 5 but can also be v 0 , v 1 , v 4 or high impedance . further , it is possible to implement this dual driving circuit for the signal electrodes also . on the other hand , if the driving method of the present invention has tab construction wherein a semiconductor ic is used for driving and bonded to flexible tape or cog ( chip on glass ) construction , the driving circuits are connected to both terminals of the liquid crystal cell and are stored easily . in particular , cog construction is superior in that there are wires between the driving circuit and electrodes , and the connecting resistance is kept to a minimum . furthermore , even if the driving method of the present invention is only applied to the scanning electrodes , such a construction is effective in preventing the phenomenon shown in fig2 . since the amplitude of the driving voltage of the scanning electrodes is about 5 to 10 times larger than that of the signal electrodes , the delay time during charge and discharge is likely to effect the display quality . this method is most suitable for color liquid crystal cells which have narrow electrode pitches . in addition , the resistance of the signal electrodes can also be reduced by utilizing thicker transparent electrode films or by coupling a different metal having low resistance to the transparent electrodes , so that the resistance of the scanning electrodes is reduced equivalently . the display quality can be improved in this manner without great cost . a simple matrix type lcd in the flat display device is explained above . the deterioration of the display quality which may be generated is dependent on the resistance of the display electrodes . this can be improved by the method of the present invention . therefore , the method of the present invention is widely applicable for active type liquid crystal displays having tft ( thin film transistor ) or mim ( metal - insulator - metal ), or for flat display till pdp ( plasma display panel ) wherein much current flows or eld ( electro - luminescence display ). as mentioned above , in accordance with the present invention , since the transparent electrode resistances are reduced to one quarter , this method of driving has the following advantages . first , in the case of a passive type matrix liquid crystal cell , the voltage applied to a liquid crystal cell approaches a predetermined value which is obtained by the voltage standardizing method . even if the display device has low or moderate capacitance and is driven by a two - frame a . c . driving method , it is possible to obtain a high contrast display . secondly , a large scale panel display having fine pitch can be obtained without deterioration of the display quality . in addition , since it is not necessary to excessively reduce the output resistance of the driving circuit , it is possible to use an ic having more pins and at a lower cost than those utilized in the prior art . finally , since the present invention utilizes thin electrodes , it is possible to obtain flat display panels which are low in cost . it will thus be seen that the objects set forth above , among those made apparent from the preceding description , are efficiently attained and , since certain changes may be made in carrying out the above method and in the constructions set forth without departing from the spirit and scope of the invention , it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense . it is also to be understood that the following claims are intended to cover all of the generic and specific features of the invention herein described and all statements of the scope of the invention which , as a matter of language , might be said to fall therebetween .