fig2 depicts in a block diagram an exemplary test system 200 that includes the packet generator 300 , which is in accordance with an embodiment of the present invention and described in more detail with respect to fig3 . all elements of fig2 except packet generator 300 are conventional . test system 200 is used to test a memory dut 202 , such as a direct rdram ™ memory device , responsive to packet based communications having interspersed instructions , address , and / or data . herein “ signal ” means any or a combination of an instruction , data , or an address . a conventional controller 204 , such as a personal computer , controls the output of the packet generator 300 and provides the status of the memory dut 202 . the relationship between the controller 204 and packet generator 300 is described in more detail later . timing and formatting circuitry 206 converts bits , input in parallel , into serial ordered bits . for examples of timing and formatting circuitry 206 , see the following united states patents issued to herlein , et al ., which are incorporated by reference herein in their entirety : u . s . pat . nos . 5 , 430 , 400 ; 4 , 849 , 702 ; 4 , 837 , 521 ; 4 , 820 , 944 ; 4 , 789 , 835 ; 4 , 675 , 562 ; 4 , 635 , 256 ; 4 , 511 , 846 ; and 4 , 165 , 092 . pin electronics circuitry 208 conventionally converts binary values from the timing and formatting circuitry 206 into voltage values which are applied to the pins ( terminals ) of memory dut 202 . conversely , the pin electronics circuitry 208 converts voltage values output from the memory dut 202 into binary values and provides the binary values to the timing and formatting circuitry 206 . the controller 204 reads the results of the test and displays pass / fail information to the user . fig3 depicts in more detail a block diagram of a packet generator 300 in accordance with an embodiment of the present invention . packet generator 300 includes a packet control memory ( pcm ) 302 , an algorithmic pattern generator ( apg ) 304 , row packet generator ( rpg ) 306 , column packet generator ( cpg ) 308 , and data packet generator ( dpg ) 310 . when memory dut 202 is a direct rdram ™, multiple mostly similar replicas of rpg 306 , cpg 308 , and dpg 310 are used to generate packet based commands described with respect to fig1 b for the direct rdram ™. the pcm 302 is a conventional instruction memory that provides “ group instructions ” to the rpg 306 , cpg 308 , and dpg 310 . each group instruction defines separate time offset instructions of dapr , dapc , and dapd , that specify either a time delay before a respective address , column , or data packet is transmitted . each group instruction further defines instructions ctrlr , ctrlc , typ - selr , and typ - selc . exemplary uses of instructions ctrlr , ctrlc , typ - selr , and typ - selc are described in more detail later . the controller 204 supplies the group instructions to be stored in the pcm 302 . instructions ctrlr and the scrambled x are interspersed into commands “ rowa ” and “ rowr ”. instruction ctrlr includes bits “ av ”, “ dr 4 t ”, “ dr 4 f ”, and “ dr 0 ” to “ dr 3 ” whereas the scrambled x includes “ r 0 ” to “ r 8 ”, “ br 0 ” to “ br 3 ”, “ rsvr ”, and “ br ”. instructions ctrlc and the scrambled y are interspersed into command “ colc / m ”. instruction ctrlc includes bits “ s ”, “ dc 0 ” to “ dc 4 ”, “ n ” , “ ma 0 ” to “ ma 7 ”, and “ mb 0 ” to “ mb 7 ”, whereas the scrambled y includes “ c 0 ” to “ c 5 ”, “ bc 0 ” to “ bc 3 ”, “ cop 0 ” to “ cop 3 ”, 2 bits of “ rsvb ”, and “ rsvc ”. instructions ctrlc , the scrambled x , and the scrambled y are interspersed into command “ colc / x ”. instruction ctrlc includes bits “ s ”, “ dc 0 ” to “ dc 4 ”, “ m ”, and “ dx 0 ” to “ dx 4 ”; the scrambled y includes “ co ” to “ c 5 ”, “ bc 0 ” to “ bc 3 ”, “ cop 0 ” to “ cop 3 ”, 2 bits of “ rsvb ”, and “ rsvc ”; and the scrambled x includes “ xop 0 ” to “ xop 4 ” and “ bx 0 ” to “ bx 3 ”. note that use of instructions dapr , dapc , and dapd to delay the beginning of commands uses less circuitry than use of timing and formatting circuitry 206 to delay previously output commands . the mostly conventional apg 304 provides addresses and accompanying data to the rpg 306 , cpg 308 , and dpg 310 every clock cycle of the tester clock signal of tester clock 210 . in this embodiment , the controller 204 loads the test pattern into the instruction memory of the apg 304 . the apg 304 generates addresses and m bits of data which respectively specify addresses of memory cells of the memory dut 202 and data to be stored in such addresses . in this embodiment , each address defines a row and column of a memory cell of memory dut 202 . in one embodiment , the apg 304 provides row ( x ) and column ( y ) addresses and m bits of data to the dpg 310 . the apg 304 provides “ scrambled ” row and column addresses to the cpg 308 whereas the apg 304 provides “ scrambled ” row addresses to the rpg 306 . scrambled row and column addresses are versions of the row and column addresses which have been modified to match the specific address topology ( arrangement ) of memory cells of the memory dut 202 . the apg 304 further outputs a program counter ( pc ) which is used to address the pcm 302 . the pcm 302 outputs a group instruction associated with data and addresses output by the apg 304 . the pcm 302 outputs a group instruction every clock cycle of the tester clock signal of tester clock 210 . fig4 depicts in a block diagram an embodiment of rpg 306 used to generate a single stream of the three stream commands “ rowa ” or “ rowr ” ( fig1 b ). to generate all three streams of commands “ rowa ” or “ rowr ”, rpg 306 is replicated three times but the replicas differ only in the configurations of cross point multiplexers 402 a and 402 b . the three mostly similar replicas of rpg 308 provide parallel ordered versions of streams of command “ rowa ” or “ rowr ” to the timing and formatting circuitry 206 . the timing and formatting circuitry 206 converts the parallel ordered versions of the streams into serial order and thereby outputs command “ rowa ” or “ rowr ”. advantageously , the mostly similar replicas of the rpg 306 increase the speed that row addresses are output above that at which the apg 304 provides row addresses . thereby multiple , speed enhanced apgs are not needed . further , the mostly similar replicas of the rpg 306 control variable timing output of commands “ rowa ” and “ rowr ”. rpg 306 includes conventional cross point multiplexers 402 a and 402 b . a cross point multiplexer has the capability to assign any input signal to any output or multiple outputs . each cross point multiplexer 402 a and 402 b is coupled to receive the scrambled row ( x ) address ( from the apg 304 of fig3 ) and a ctrlr instruction ( from the pcm 302 of fig3 ). each cross point multiplexer 402 a and 402 b is coupled to receive instruction selectr from the controller 204 ( fig2 ). the four bit instruction selectr controls cross point multiplexers 402 a and 402 b and specifies a relationship between the bits output by and input to the cross point multiplexers 402 a and 402 b . in one embodiment , the associations between output and input bits for each cross point multiplexer 402 a and 402 b are different for the same value of instruction selectr . the difference is because output signals from each of cross point multiplexer 402 a and 402 b correspond to different streams of commands “ rowa ” and “ rowr ”. the output bits are described earlier with respect to fig1 b . note that each of cross point multiplexers 402 a and 402 b outputs a parallel order version of a distinct stream of command “ rowa ” and “ rowr ”. the output signals from cross point multiplexers 402 a and 402 b are provided as input signals to a conventional multiplexer 404 . the output signal of multiplexer 404 , i . e ., either the output signal of cross point multiplexer 402 a or 402 b , is controlled by instruction typ - selr from the pcm 302 . when memory dut 202 is a direct rdram ™, instruction typ - selr selects between output of a distinct stream of the “ rowa ” or “ rowr ” command . the output signal from multiplexer 404 is provided to a conventional first - in - first - out ( fifo ) memory device 406 . instruction dapr ( from the pcm 302 ) specifies the number of clock cycles of the tester clock signal of tester clock 210 ( fig2 ) to count prior to outputting the output signal from multiplexer 404 . the tester clock signal is coupled to input terminals wt and rd of the fifo device 406 . the input to the wt terminal . controls when data from the mux 404 is loaded into the fifo memory device 406 , whereas the input to the rd terminal controls when the fifo memory device 406 outputs data . fifo memory device 406 outputs eight bits of data in parallel . fig5 depicts in a block diagram an embodiment of the cpg 308 that is structurally similar to the embodiment of rpg 306 described with respect to fig4 . when memory dut 202 is a direct rdram ™, each cpg 308 generates a distinct stream of the five stream commands “ colc / m ” or “ colc / x ”. to generate all five streams of command “ colc / m ” or “ colc / x ”, cpg 308 is replicated five times but the replicas differ only in the configurations of cross point multiplexers 502 a and 502 b . the five mostly similar replicas of cpg 308 provide parallel ordered versions of streams of command “ colc / m ” or “ colc / x ” to the timing and formatting circuitry 206 . the timing and formatting circuitry 206 converts the parallel ordered versions of the streams into serial order and thereby outputs command “ colc / m ” or “ colc / x ”. advantageously , the multiple mostly similar replicas of the cpg 308 increase the speed that column addresses are output above that at which the apg 304 provides column addresses . thereby multiple , speed enhanced apgs are not needed . further , the multiple mostly similar replicas of the cpg 308 support variable timing output of commands . cross point multiplexer 502 a is coupled to receive the scrambled column ( y ) and a ctrlc instruction . cross point multiplexer 502 b is coupled to receive the scrambled column ( y ) and row ( x ) addresses and a ctrlc instruction . each of cross point multiplexers 502 a and 502 b is coupled to receive instruction selectc from the controller 204 ( fig2 ). the four bit instruction selectc controls cross point multiplexers 502 a and 502 b and specifies a relationship between the bits output by and input to the cross point multiplexers 502 a and 502 b . the output signals of cross point multiplexers 502 a and 502 b are provided as input signals to a conventional multiplexer 504 . the output signal of multiplexer 504 , i . e ., either the output signal of either cross point multiplexer 502 a or 502 b , is controlled by instruction typ - selc from the pcm 302 . the instruction typ - selc selects - between output of a distinct stream of the five stream commands “ colc / m ” and “ colc / x ”. in one embodiment , the associations between output and input bits for each of cross point multiplexers 502 a and 502 b are different for the same value of instruction selectc . the difference is because output signals from each of cross point multiplexers 502 a and 502 b correspond to different stream of commands “ colc / m ” and “ colc / x ”. the output bits are described earlier with respect to fig1 b . note that each of cross point multiplexers 502 a and 502 b outputs a parallel order version of a distinct stream of command “ colc / m ” or “ coblc / x ”. the output signal of multiplexer 504 is provided to a conventional first - in - first - out ( fifo ) 8 bit wide memory device 506 . instruction dapc ( from the pcm 302 ) specifies the number of clock cycles of the tester clock signal of tester clock 210 ( fig2 ) to count prior to outputting the output signal from multiplexer 504 . the tester clock signal is coupled to input terminals wt and rd of the fifo memory device 506 . the input to the wt input terminal controls when data from the mux 504 is loaded into the fifo memory device 506 , whereas the input to the rd input terminal controls when the fifo memory device 506 outputs data . fig6 in a combination schematic and block diagram depicts an embodiment of a dpg 310 for a single bit of the m bits of data from apg 304 . for each bit of the m bits of data from apg 304 , there is an associated distinct replica of dpg 310 . when dut 202 is a direct rdram ™ memory device , m is 18 in order to generate two 9 streams that correspond to commands “ dqa ” and “ dqb ”. note that the m replicas of dpg 310 provide parallel ordered versions of streams of command “ dqa ” or “ dqb ” to the timing and formatting circuitry 206 . the timing and formatting circuitry 206 converts the parallel ordered versions of the streams into serial order and thereby outputs command “ dqa ” or “ dqb ”. advantageously , the dpg 310 increases the speed that data is output above that at which the apg 304 provides data . thereby multiple , speed enhanced apgs are not needed . dpg 310 - n includes a conventional cross point multiplexer 602 that is coupled to receive inputs of row and column addresses output from the apg 304 . instruction selectd from the controller 204 ( fig2 ) controls the cross point multiplexer 602 . the cross point multiplexer 602 provides its output signal to a data memory 604 . the memory 604 stores a table of associations between data values and column and row addresses . memory 604 is a conventional memory such as a static random access memory ( sram ) that is readily addressable . memory 604 uses the column and row addresses from the apg 304 to look up a data value and provides the data value to logic array 606 . such associations between column and row addresses and data values are readily programmable by the controller 204 of fig1 . logic array 606 generates a multibit data value from a combination of the data value output from the data memory 604 and a single bit d m of the m data bits from apg 304 . the logic array 606 includes n logic gates , each logic gate being a xor type . in this embodiment , each of the n logic gates is coupled to receive a ) a distinct bit of the data value from the data memory 604 and b ) a single bit dm of the m data bits from apg 304 . each of the n logic gates generates an output bit by xoring the a ) and b ) input bits . thus the logic array 606 generates n bits from each bit of the m data bits from apg 304 , where n is 8 in this embodiment . the n bit output from logic array 606 is provided to a conventional first - in - first - out ( fifo ) memory device 608 . instruction dapd specifies the number of clock cycles ( offset ) of the tester clock signal of tester clock 210 ( fig2 ) to count prior to outputting the n bits from logic array 606 . the tester clock signal is coupled to input terminals wt and rd of the fifo memory device 608 . the signal input to the wt terminal controls when the n bit output from the logic array 606 is loaded into the fifo memory device 608 , whereas the signal input to the rd input terminal controls when the fifo memory device 608 outputs an n bit output . the timing and formatting circuitry 206 converts the n bits output from fifo memory device 608 into a serial ordered bit stream of n bits . where the memory dut 202 is a direct rdram ™, n is 8 , and each 8 - bit output from fifo memory device 608 corresponds to a single stream of a packet - based data command , e . g ., either “ dqa ” or “ dqb ”. thus by use of logic array 606 , test system 200 generates data at a bit rate higher than that achievable by use of apg 304 alone . for example , if the apg 304 outputs data at a rate of 10 megabits / second , and the memory dut 202 requires a data input at a rate of 80 megabits / second , dpg 310 is used to increase the rate at which data is input to the memory dut 202 . the logic array 606 multiplies the bit rate at which data is output by the apg 304 by n fold , where n is the number of logic gates and corresponding output bits from the logic array 606 . all parameters provided herein are exemplary . the above - described embodiments of the present invention are merely meant to be illustrative and not limiting . it will thus be obvious to those skilled in the art that various changes and modifications may be made without departing from this invention in its broader aspects . therefore , the appended claims encompass all such changes and modifications as fall within the true scope of this invention .