certain details are set forth below to provide a sufficient understanding of the invention . however , it will be clear to one skilled in the art that the invention may be practiced without these particular details . in other instances , well - known circuits , control signals , and timing protocols have not been shown in detail in order to avoid unnecessarily obscuring the invention . fig2 illustrates a sense amplifier 200 according to an embodiment of the invention . components and signals that were previously described with reference to fig1 have been given the same reference numbers in fig2 . the sense amplifier 200 of fig2 includes an nmos amplifier stage 201 having a pair of nmos transistors 222 , 224 coupled to the sources of the nmos transistors 112 , 114 to provide source degeneration . the drains to each of the nmos transistors 222 , 224 are coupled to the sources of the nmos transistors 112 , 114 , and the sources of the nmos transistors 222 , 224 are coupled to a common node coupled to ground . the gates of the nmos transistors 222 , 224 are coupled together and receive a control signal slat that provides a voltage signal to the respective gates . in the source degenerate configuration , the nmos transistors 222 , 224 provide a resistance on the sources of the nmos transistors 112 , 114 . the effect of adding resistance at the nmos amplifier stage 201 reduces the gain of the nmos transistors 112 , 114 . as a result , an offset that typically would have been amplified due to a threshold voltage mismatch is reduced , which in turn minimizes its interference with amplifying the digit line signal . the resistance provided by the nmos transistors 222 , 224 may be changed by adjusting the voltage of the slat signal . the slat signal may be predetermined for the sense amplifier 200 by design or be an adjustable control signal by a user . in operation , the digit and digit_ lines are precharged to vcc / 2 and the voltages of the digit lines are equilibrated by activating the eq signal and coupling the two digit lines together through the transistor 110 . the eq signal is then deactivated to isolate the digit and digit_ lines in preparation for a sense operation . a word line ( not shown ) of the memory cell array is activated to couple a row of memory cells to a respective digit line and to a respective sense amplifier 200 . as previously described , coupling a memory cell to the respective digit line causes a voltage differential between the digit and digit_ lines . in the present example , it will be assumed that the accessed memory cell is coupled to the digit line and increases the voltage to slightly above vcc / 2 . as a result , the gate - to - source voltage of the nmos transistor 114 is greater than for the nmos transistor 112 . prior to activation of the rnl_ and act signals , the slat signal is activated to couple the sources of the transistors 112 , 114 to a common node 226 through the transistors 222 , 224 . as a result , voltage of both the digit and digit_ lines slightly decrease . with the greater gate - to - source voltage for the nmos transistor 114 , the voltage of the digit_ line is discharged more quickly to the common node 226 than for the digit line , resulting in the pmos transistor 102 having a greater gate - to - source voltage than for the pmos transistor 104 . the act signal is then activated ( typically providing vcc , a power supply voltage ), and due to the greater gate - to - source voltage of the pmos transistor 102 , the transistor 102 begins to switch on before the pmos transistor 104 , further increasing the gate - to - source voltage of the nmos transistor 114 . the rnl_ signal is activated coupling the sources of the nmos transistors 112 , 114 to ground , fully switching on the transistor 114 and fully coupling the digit_ line to ground . the pmos transistor 102 is consequently fully switching on by the grounded digit_ line and fully couples the digit line to vcc , latching the digit and digit_ lines to respective voltages vcc and ground . as previously discussed , the transistors 222 , 224 increase the source - to - ground resistance of the nmos transistors 112 , 114 to provide source degeneration and reduce the gain of the nmos transistors 112 , 114 . the trade - off for reducing the gain of the nmos transistors 112 , 114 is that the current gain is also reduced , which slows the amplification of the digit and digit_ lines . the slower amplification of the nmos amplifier stage 201 allows time for the pmos transistors 102 , 104 to recover towards vcc before the nmos transistors 112 , 114 are fully driven to ground . as a result , failure to pull - up the voltage of one of the digit lines due to transistor threshold voltage mismatch is reduced during normal operation of the sense amplifier 200 . fig3 illustrates a sense amplifier 300 according to another embodiment of the invention . the sense amplifier 300 is similar to the sense amplifier 200 previously described with reference to fig2 . the transistors 222 , 224 of the sense amplifier 200 , however , have been replaced in the sense amplifier 300 with resistors 322 , 324 . as previously discussed , the transistors 222 , 224 increased the source - to - ground resistance of the nmos transistors 112 , 114 to provide source degeneration . the resistors 322 , 324 are used to provide increased source - to - ground resistance in place of the transistors 222 , 224 . operation of the sense amplifier 300 is the same as for the sense amplifier 200 except that provision of an active slat signal is not necessary . fig4 illustrates a sense amplifier 400 according to another embodiment of the invention . the sense amplifier 400 is similar to the sense amplifier 200 previously described with reference to fig2 . however , additional nmos transistors 216 , 218 are included in the sense amplifier 400 and the common node 226 is coupled to ground . the nmos transistors 216 , 218 are used to enhance pull - down of the digit and digit_ lines to ground during sensing . the drains of the nmos transistors 216 , 218 are coupled to the respective drains of the nmos transistors 112 , 114 , and the gates of the nmos transistors 216 , 218 are also respectively coupled to the gates of the nmos transistors 112 , 114 . the sources of the nmos transistors 216 , 218 are coupled together and share a common node to which the rnl_ signal is coupled . operation of the sense amplifier 400 is similar to operation of the sense amplifier 200 . the increase of gate - to - source voltage of one of the nmos transistors 112 , 114 in response to coupling a memory cell to either the digit or digit_ line also increases the gate - to - source voltage of one of the nmos transistors 216 , 218 . with the common node 226 coupled to ground , rather than to receive the rnl_ signal , the voltage of the digit and digit_ lines begin to discharge to ground immediately rather than waiting for the rnl_ signal to become active . as previously discussed with reference to the sense amplifier 200 , the decreasing voltage of the digit or digit_ line creates a gate - to - source voltage imbalance between the pmos transistors 102 , 104 , with one of the two transistors switching on before the other in response to the act signal becoming active . in addition to causing either of the nmos transistors 112 , 114 to switch on more fully , the corresponding nmos transistors 216 , 218 is more fully switched on as well . in response to the rnl_ signal becoming active , the conductive nmos transistor 216 or 218 provides additional drive capability to pull - down the digit or digit_ line to ground more quickly than compared to the sense amplifier 200 . in another embodiment , the sense amplifier 300 of fig3 is modified to includes additional transistors to provide greater drive capability to pull - down the digit or digit_ line , as previously discussed with reference to the sense amplifier 400 of fig4 . resistors , multiple transistors , impedances sources or any other components , or combinations thereof may be used in place of the nmos transistors 222 , 224 , as is known in the art , to provide source degeneration and reduce the gain of the nmos transistors 1112 , 114 . the sense amplifiers 200 , 300 , and 400 were previously described in operation according to a particular activation sequence of signals , for example , the eq , slat , act , and rnl_ signals . in other embodiments of the invention , the activation sequence of signals is different than that previously described . those ordinarily skilled in the art will obtain sufficient understanding from the description provided herein to make such modifications to practice these other embodiments . the present invention is not limited to the particular sequence previously described for the previously described embodiments of the invention . fig5 illustrates an embodiment of a memory device 500 including at least one sense amplifier according to an embodiment of the present invention . the memory device 500 includes an address register 502 that receives row , column , and bank addresses over an address bus addr , with a memory controller ( not shown ) typically supplying the addresses . the address register 502 receives a row address and a bank address that are applied to a row address multiplexer 504 and bank control logic circuit 506 , respectively . the row address multiplexer 504 applies either the row address received from the address register 502 or a refresh row address from a refresh counter 508 to a plurality of row address latch and decoders 510 a - d . the bank control logic 506 activates the row address latch and decoder 510 a - d corresponding to either the bank address received from the address register 502 or a refresh bank address from the refresh counter 508 , and the activated row address latch and decoder latches and decodes the received row address . in response to the decoded row address , the activated row address latch and decoder 510 a - d applies various signals to a corresponding memory bank 512 a - d , including a row activation signal to activate a row of memory cells corresponding to the decoded row address . each memory bank 512 a - d includes a memory - cell array having a plurality of memory cells arranged in rows and columns . data stored in the memory cells in the activated row are sensed and amplified by sense amplifiers 511 in the corresponding memory bank . the sense amplifiers 511 are designed according to an embodiment of the present invention . the row address multiplexer 504 applies the refresh row address from the refresh counter 508 to the decoders 510 a - d and the bank control logic circuit 506 uses the refresh bank address from the refresh counter when the memory device 500 operates in an auto - refresh or self - refresh mode of operation in response to an auto - or self - refresh command being applied to the memory device 500 , as will be appreciated by those skilled in the art . a column address is applied on the addr bus after the row and bank addresses , and the address register 502 applies the column address to a column address counter and latch 514 which , in turn , latches the column address and applies the latched column address to a plurality of column decoders 516 a - d . the bank control logic 506 activates the column decoder 516 a - d corresponding to the received bank address , and the activated column decoder decodes the applied column address . depending on the operating mode of the memory device 500 , the column address counter and latch 514 either directly applies the latched column address to the decoders 516 a - d , or applies a sequence of column addresses to the decoders starting at the column address provided by the address register 502 . in response to the column address from the counter and latch 514 , the activated column decoder 516 a - d applies decode and control signals to an i / o gating and data masking circuit 518 which , in turn , accesses memory cells corresponding to the decoded column address in the activated row of memory cells in the memory bank 512 a - d being accessed . during data read operations , data being read from the addressed memory cells is coupled through the i / o gating and data masking circuit 518 to a read latch 520 . the i / o gating and data masking circuit 518 supplies n bits of data to the read latch 520 , which then applies two n / 2 bit words to a multiplexer 522 . in the embodiment of fig3 , the circuit 518 provides 64 bits to the read latch 520 which , in turn , provides two 32 bits words to the multiplexer 522 . a data driver 524 sequentially receives the n / 2 bit words from the multiplexer 522 and also receives a data strobe signal dqs from a strobe signal generator 526 . the dqs signal is used by an external circuit such as a memory controller ( not shown ) in latching data from the memory device 500 during read operations . the data driver 524 sequentially outputs the received n / 2 bits words as a corresponding data word dq , each data word being output in synchronism with a rising or falling edge of a clk signal that is applied to clock the memory device 500 . the data driver 524 also outputs the data strobe signal dqs having rising and falling edges in synchronism with rising and falling edges of the clk signal , respectively . each data word dq and the data strobe signal dqs collectively define a data bus data . during data write operations , an external circuit such as a memory controller ( not shown ) applies n / 2 bit data words dq , the strobe signal dqs , and corresponding data masking signals dm on the data bus data . a data receiver 528 receives each dq word and the associated dm signals , and applies these signals to input registers 530 that are clocked by the dqs signal . in response to a rising edge of the dqs signal , the input registers 530 latch a first n / 2 bit dq word and the associated dm signals , and in response to a falling edge of the dqs signal the input registers latch the second n / 2 bit dq word and associated dm signals . the input register 530 provides the two latched n / 2 bit dq words as an n - bit word to a write fifo and driver 532 , which clocks the applied dq word and dm signals into the write fifo and driver in response to the dqs signal . the dq word is clocked out of the write fifo and driver 532 in response to the clk signal , and is applied to the i / o gating and masking circuit 518 . the i / o gating and masking circuit 518 transfers the dq word to the addressed memory cells in the accessed bank 512 a - d subject to the dm signals , which may be used to selectively mask bits or groups of bits in the dq words ( i . e ., in the write data ) being written to the addressed memory cells . a control logic and command decoder 534 receives a plurality of command and clocking signals over a control bus cont , typically from an external circuit such as a memory controller ( not shown ). the command signals include a chip select signal cs *, a write enable signal we *, a column address strobe signal cas *, and a row address strobe signal ras *, while the clocking signals include a clock enable signal cke * and complementary clock signals clk , clk *, with the “*” designating a signal as being active low . the command signals cs *, we *, cas *, and ras * are driven to values corresponding to a particular command , such as a read , write , or auto - refresh command . in response to the clock signals clk , clk *, the command decoder 534 latches and decodes an applied command , and generates a sequence of clocking and control signals that control the components 502 - 532 to execute the function of the applied command . the clock enable signal cke enables clocking of the command decoder 534 by the clock signals clk , clk *. the command decoder 534 latches command and address signals at positive edges of the clk , clk * signals ( i . e ., the crossing point of clk going high and clk * going low ), while the input registers 530 and data drivers 524 transfer data into and from , respectively , the memory device 500 in response the data strobe signal dqs . the detailed operation of the control logic and command decoder 534 in generating the control and timing signals is conventional , and thus , for the sake of brevity , will not be described in more detail . although previously described with respect to a dynamic random access memory device , embodiments of the present invention can be utilized in applications other than for a memory device where it is desirable to reduce the effects a threshold voltage mismatch when the voltage level of an input signal is amplified . fig6 is a block diagram of a computer system 600 including computer circuitry 602 including the memory device 500 of fig5 . typically , the computer circuitry 602 is coupled through address , data , and control buses to the memory device 500 to provide for writing data to and reading data from the memory device . the computer circuitry 602 includes circuitry for performing various computing functions , such as executing specific software to perform specific calculations or tasks . in addition , the computer system 600 includes one or more input devices 604 , such as a keyboard or a mouse , coupled to the computer circuitry 602 to allow an operator to interface with the computer system . the computer system 600 may include one or more output devices 606 coupled to the computer circuitry 602 , such as output devices typically including a printer and a video terminal . one or more data storage devices 608 may also be coupled to the computer circuitry 602 to store data or retrieve data from external storage media ( not shown ). examples of typical storage devices 608 include hard and floppy disks , tape cassettes , compact disk read - only ( cd - roms ) and compact disk read - write ( cd - rw ) memories , and digital video disks ( dvds ). from the foregoing it will be appreciated that , although specific embodiments of the invention have been described herein for purposes of illustration , various modifications may be made without deviating from the spirit and scope of the invention . for example , many of the components described above may be implemented using either digital or analog circuitry , or a combination of both . accordingly , the invention is not limited except as by the appended claims .