referring to fig1 a memory cell used in a static random access memory using c - mos field effect transistor includes a flip - flop circuit 1 formed by two c - mos invertors 1a and 1b , and two transmission gates 2a and 2b , each formed by one mos field effect transistor . the transmission gates 2a and 2b are placed in an off state by the voltage on the word line 3 when information is stored in the memory cell . the transmission gates 2a and 2b are placed in an on state when information is written in or read out from the memory cell . bit lines 4a , 4b each connected to the c - mos invertors of the flip - flop circuit write in or read out the information signals b , b via the transmission gate circuits 2a , 2b which are kept in the on state . the word lines 3 and the bit lines 4a , 4b are extended vertically and horizontally in mesh form , and the memory cells are connected to each cross point of the word lines 3 and the bit lines 4a , and 4b . therefore , the number of transmission gates 2a and 2b which are connected to one word line 3 is twice the number of the memory cells used in one word line . in the memory cell which is formed by using an mos field effect transistor having an sos ( silicon on sapphire ) construction , it is recognized that the access time to the memory cell increases when the thickness xox of the gate insulating film of the transistor becomes thinner than 500 [ a ]. in the memory device which is formed by using the usual mos field effect transistor having a bulk construction , the access time to the memory cell is larger than that of the memory device using the mos field effect transistor having an sos construction . however , the access time becomes small when a thin gate insulating film is used . in the memory device which is formed by an mos field effect transistor having an sos construction , the capacitances which are connected to the word line 3 are formed only by the gate capacitances of the transistors ; the stray capacitances of wire and the junction capacitances , which occur in the memory cell using an mos memory device having a bulk construction , can be neglected . the following equation exists between the gate capacitance cg of the transistor having an sos construction and the thickness xox of the gate insulating film of the transistor ; on the other hand , the following equation exists between a current amplification factor and the thickness xox of the gate insulating film of the transistor : that is , the current amplification factor β of the transistor used as a driver decreases when the thickness of the gate insulating film increases . therefore , it is expected that the access time of the memory cell of a sos construction does not depend on the thickness xox of the gate insulating film . however , according to the result of the simulation , it is recognized that the access time increases when the thickness becomes smaller than 500 [ a ], as shown in fig2 . further , in the memory device which is formed by using a usual mos memory device having a bulk construction , as in the memory cell using an mos field effect transistor having an sos construction , it is recognized that the access time to the memory cell increases when the gate insulating film of the transistor becomes thinner than 300 [ a ]. it is understood that this phenomenon is due to the fact that the stray capacitances of wire connections and the junction capacitances can be neglected with respect to the gate capacitance which is determined by the thickness xox of the gate insulating film when the thickness of the gate insulating film is smaller than 300 [ a ] so that the function of the mos field effect transistor having a bulk construction becomes similar to that of the mos field effect transistor having an sos construction . on the other hand , in the static type random access memory , usually when the bit lines 4a , 4b are formed by using a metal such as an aluminum material , the word line 3 are formed by using a polycrystalline silicon material . therefore , as shown in fig3 one word line 3 is equivalently represented by an rc network which is formed by resistances r which are connected in series , and capacitances c which correspond to the gate capacitance of the mos field effect transistors forming the transmission gates 2a , 2b and which are connected to the word line in parallel , so that the access time to the memory device increases . the value of the capacitances c in the above rc network increases when the thickness xox of the gate insulating film decreases ; therefore , the delay time of the signal which is supplied from a drive terminal 5 of the word line where a driving transistor is connected increases along the word line 3 . when the integration of the memory device increases and the word lines become long , the problem of the delay time is serious . in the memory cell which is positioned near the drive terminal 5 , the problem of the delay time is not serious ; however , in the memory cell which is distant from the drive terminal 5 , the problem of the delay time is very serious . fig4 is a circuit of one embodiment of the present invention . fig4 illustrates one part of the static random access memory having the sos construction , and the same symbols as those of fig1 show the same parts as indicated in fig1 . referring to fig4 the memory cells 6 including one flip - flop circuit 1 and two transmission gates 2a , 2b are arranged in matrix form , and these memory cells 6 are connected to cross points between the word lines 3 , 3 , . . . , which are arranged horizontally , and the bit lines 4a , 4b ; 4a , 4b ; . . . , which are arranged vertically ; and these memory cells 6 are selectively driven by the word lines and the bit lines . in the present invention , amplifiers 7 are inserted between the memory cells in the word line 3 . the amplifier 7 is formed by two invertors 7a , 7b which are connected in series , so that the output and the input are in phase . when the amplifier 7 is placed in the word line 3 , the voltage distribution on the word line 3 at a certain time after the voltage is applied to the driving terminal is shown in fig5 . referring to fig5 the horizontal axis illustrates the word line 3 , p o illustrates the driving terminal , p 1 illustrates an input terminal of the amplifier 7 , and p 2 illustrates an output terminal of the amplifier 7 . the driving terminal 5 is connected to a driver ( not shown in the drawing ) having a sufficient driving power , and when the word line 3 is selected , the voltage which is equal to the source voltage ( in this example , the source voltage is 5 [ v ]) is supplied to the driving terminal 5 . therefore , the voltage at the position p 0 instantly rises to 5 [ v ], and after a certain time , the voltage is distributed in the word line 3 as shown in fig5 . when the voltage is distributed , as shown in line ( a ), in fig5 after a time which is determined by the delay time of the rc network , the inverter 7a included in the amplifier inverts the input voltage 1 . 7 v ( threshold voltage ) at the point p 1 to about 0 . 2 v and the inverter 7b inverts this 0 . 2 v to about 5 [ v ], so that the output voltage at the point p 2 rises to 5 [ v ]. the time required for inverting the voltage is about 1 [ ns ]˜ several [ ns ] and this time is very much smaller than the delay time from one end to the other end of the word line , which is for example 20 [ ns ]. the voltage at the point p 2 is propagated after a lapse of time and voltage distribution shown by solid line ( c ) is obtained along the word line 3 . hereinafter , the voltage distributions ( a ) and ( b ) change so that the voltage distribution approaches to the line p 0 - p 2 , and finally the voltage 5 [ v ] is distributed along all of the word line 3 . in fig5 the broken line ( b ) shows the voltage distributions when the amplifier 7 is not used . accordingly , the transmission gates 2a and 2b positioned downstream of the amplifier 7 in the word line 3 are rapidly turned on by the rise of the voltage and an increase of the access time can be prevented if the gate capacitance c is increased by using the thin gate oxide film . the semiconductor memory device formed by an integrated circuit having an sos construction according to the present invention is shown in fig6 a . in the embodiment shown in fig6 a , the word lines are formed by polycrystalline silicon , the bit lines are formed by aluminum wire and the amplifier is placed in the word line . fig6 a illustrates a plan view of the integrated circuit , and the portion including the amplifier 7 and the memory cells 6 positioned at both sides of the amplifier is shown in fig6 a . fig6 a illustrates an epitaxial silicon island pattern which forms a first layer 11 ( the lowest layer ), a polycrystalline silicon pattern which forms a second layer 12 , a contact hole pattern 13 in a phosphosilicate glass ( psg ) layer which forms a third layer for the purpose of insulating between the layers , and an aluminum wiring pattern 14 which forms a fourth layer . fig6 b illustrates a sectional view along line b -- b in fig6 a , and shows a sapphire substrate ( layer ) 15 , an epitaxial silicon island pattern 11 which is formed on the sapphire substrate 15 , the gate insulating film 17 which is formed by silicon dioxide and selectively formed on the silicon island pattern 11 , an insulating layer 16 which is formed by silicon dioxide to isolate between silicon island patterns and to fill up the silicon island patterns so as to form a nearly flat surface , a polycrystalline silicon layer 12 which forms a gate electrode and a part of a wire connection , a psg layer 18 for insulating between the polycrystalline silicon layer 12 and an aluminum wiring layer , the aluminum wiring layer 14 and a cover psg layer 19 . fig6 c illustrates a sectional view along line c -- c in the part of the memory cell shown in fig6 a , and the sapphire substrate 15 , the epitaxial silicon island layer 11 , the insulating layer 16 , the polycrystalline silicon layer 12 , the psg layer 18 , the aluminum wiring layer 14 and the cover psg layer 19 are shown referring to fig6 c . fig6 d illustrates a sectional view of the amplifier along line d -- d in fig6 a , and the sapphire substrate 15 , the silicon island pattern 11 , the insulating layer 16 , the polycrystalline silicon layer 12 , the psg layer 18 , the aluminum wiring layer 14 and the cover psg layer 19 are shown referring to fig6 d . fig7 a illustrates an equivalent circuit in a portion of the amplifier 7 in the semiconductor memory device according to the present invention . as shown in fig7 a , the amplifier 7 is formed by the c - mos invertors 7a and 7b which are connected in series . the portions 21 , 22 , 23 , 24 , 25 , 26 and 27 in the amplifier 7 shown in fig7 a correspond to the same reference numerals 21 through 27 shown in fig7 b . referring to fig7 b , the portions which is correspond to fig6 a are shown by the reference numerals in the brackets . as explained in detail above , in the present invention , the amplifier is inserted , for example , in the word line so that the resistance loss in the word line is compensated in the rc network . therefore , the delay time is further increased when the word line is longer , and it is clear that the increase of the access time can be removed by inserting several amplifiers in different portions of the same word line . accordingly , according to the present invention , the increase of the access time can be easily prevented when the thin gate oxide film is used for the purpose of increasing the value β of the transistor or by using the short channel of the transistor , or when long bit lines are used in the memory device . in the above - mentioned embodiment according to the present invention , the amplifier is placed in the word lines . however , when the bit lines are formed by the wire connection regions which are formed in the polycrystalline semiconductor layer or in the bulk semiconductor substrate ( layer ) by diffusion , the resistance in the bit lines increases so that the access time to the bit lines also increases . this increase of the access time can be improved by inserting the amplifier in a suitable position between memory cells in the bit lines .