a description will be given , with reference to fig9 through 11 , of a first embodiment of the present invention . fig9 is a circuit diagram of a dram according to a first embodiment of the present invention . the dram includes main isolation signal generating circuits 290 - 295 having different circuit configurations from those of the main isolation signal generating circuits 84 - 89 . the dram also includes sub isolation signal generating circuits 296 - 331 having different circuit configurations from those of the sub isolation signal generating circuits 102 - 137 . that is , the dram according to the first embodiment of the present invention is provided newly with main isolation signal generating circuits 290 - 295 configured differently from those shown in fig3 and sub isolation signal generating circuits 296 - 331 configured differently from those shown in fig3 . the other parts of the dram according to the first embodiment of the present invention are configured in the same manner as those of the dram shown in fig3 . in the first embodiment of the present invention , the main isolation signal generating circuits 290 - 295 are configured in such a way as to generate a main isolation signal that swings between the external power supply potential vdd ( or the step - down power supply potential vii ) and the ground potential vss . the sub isolation signal generating circuits 296 - 331 are configured in such a way as to generate a sub isolation signal that swings between the boosted power supply potential vpp and the ground potential vss . fig1 is a circuit diagram of a circuit configuration of the main isolation signal generating circuits and the sub isolation signal generating circuits employed in the first embodiment of the present invention . referring to fig1 , there is illustrated a main isolation signal generating circuit 332 , which includes a nand circuit 333 . the main isolation signal generating circuit 332 receives a row block selection signal rbs 1 and a timing signal tm , and generates a main isolation signal mis 1 therefrom . the nand circuit 333 has a cmos structure in which the power supply potential vii ( that may be vdd ) and the ground potential vss serve as the power supply potentials on the high - potential and low - potential sides , respectively . the dram includes a sub isolation signal generating circuit 334 , which receives the main isolation signal mis 1 and a column block selection signal cbs , and generates a sub isolation signal sis 1 . the circuit 334 includes a logic circuit of a nor circuit , which performs a nor operation on the main isolation signal mis 1 and the column block selection signal cbs . the nor circuit has a cmos structure in which the power supply potential vii and the ground potential vss serve as the power supply potentials on the high - potential and low - potential sides , respectively . the dram includes a level conversion circuit 336 , which converts the level of the output of the nor circuit 335 to thus produce the sub isolation signal sis 1 . the circuit 336 includes an inverter 337 that inverts the output of the nor circuit 335 , pmos transistors 338 and 339 , and nmos transistors 340 and 341 . the inverter 337 is a cmos structure , which receives the power supply potential vii on the high - potential side and the ground potential vss on the low - potential side . the sources of the pmos transistors 338 and 339 are connected to a vpp line via which the boosted potential vpp is supplied . a main isolation signal generating circuit 342 receives a row block selection signal rbs 2 and the timing signal tm , and thus generates a main isolation signal mis 2 . the circuit 342 includes a nand circuit 343 of a cmos structure , which receives the power supply potential vii on the high - potential side and the ground potential vss on the low - potential side . a sub isolation signal generating circuit 344 receives the main isolation signal mis 2 and the column block selection signal cbs , and thus generates a sub isolation signal sis 2 . a nor circuit 345 performs a nor operation on the main isolation signal mis 2 and the column block selection signal cbs . the nor circuit 345 has a cmos structure , which receives the power supply potential vii on the high - potential side and the ground potential vss on the low - potential side . a level conversion circuit 346 converts the output of the nor circuit 345 to thus produce the sub isolation signal sis 2 . the circuit 346 includes an inverter 347 inverting the output of the nor circuit 345 , pmos transistors 348 and 349 , and nmos transistors 350 and 351 . the inverter 347 has a cmos structure , which receives the power supply potential vii on the high - potential side and the ground potential vss on the low - potential side . the sources of the pmos transistors 348 and 349 are connected to the vpp line via which the boosted potential vpp is supplied . the dram includes cell arrays 352 and 353 , and a sense amplifier part that is shared by the cell arrays 352 and 353 . nmos transistors 355 through 357 form a bit line precharge circuit that precharges the bit lines bl and / bl to a precharge potential vpr . a symbol pr is a bit line precharge signal , which controls on / off of the nmos transistors 355 through 357 . a sense amplifier 358 includes pmos transistors 359 and 360 and nmos transistors 361 and 362 . a pmos transistor 363 is turned on / off by a sense amplifier driving signal psa , and supplies the sense amplifier 358 with the power supply potential vii . an nmos transistor is turned on / off by another sense amplifier driving signal nsa , and supplies the sense amplifier 358 with the ground potential vss . nmos transistors 365 and 366 are nmos transistors that forms a column selection circuit . a symbol cl is a column selection signal , which controls on / off of the nmos transistors 365 and 366 . symbols db and / db are data bus lines . an isolation circuit 367 includes nmos transistors 368 and 369 serving as isolation transistors that are turned on / off by the sub isolation signal sis 1 . an isolation circuit 370 includes nmos transistors 371 and 372 serving as isolation transistors that are turned on / off by the sub isolation signal sis 2 . when the cell array 352 is activated , the row block selection signal rbs 1 and rbs 2 are respectively set at vss and vii , and the timing signal tm is set at vii , the column block signal cbs being set at vss . thus , the main isolation signal mis 1 is set at vii and the sub isolation signal generating circuit 334 operates as follows : the output of the nor circuit 335 is equal to vss ; the output of the inverter 337 is vii ; the nmos transistor 340 is off ; the nmos transistor 341 is on ; the pmos transistor 338 is on ; the pmos transistor 339 is off ; and the sub isolation signal sis 1 becomes equal to vpp . the nmos transistors 368 and 369 in the isolation circuit 367 are turned on . the main isolation signal mis 2 is set at vss , and the sub isolation signal generating circuit 344 operates as follows : the output of the nor circuit 345 is vii ; the output of the inverter 347 is vss ; the nmos transistor 350 is on ; the nmos transistor 351 is off ; the pmos transistor 348 is off ; the pmos transistor 349 is on ; and the sub isolation signal sis 2 becomes equal to vss . the nmos transistors 371 and 372 in the isolation circuit 370 are turned off . as a result of the operation , the cell array 352 and the sense amplifier part 354 are electrically isolated , and the cell array 353 and the sense amplifier part 354 are electrically isolated . in contrast , when the cell array 353 is activated , the row block selection signals rbs 1 and rbs 2 are respectively set at vii and vss , and the timing signal tm is set at vii , the column selection signal cbs being set at vss . thus , the main isolation signal mis 1 is set at vss and the sub isolation signal generating circuit 334 operates as follows : the output of the nor circuit 335 is equal to vii ; the output of the inverter 337 is vss ; the nmos transistor 340 is on ; the nmos transistor 341 is off ; the pmos transistor 338 is off ; the pmos transistor 339 is on ; and the sub isolation signal sis 1 becomes equal to vss . the nmos transistors 368 and 369 in the isolation circuit 367 are turned off . the main isolation signal mis 2 is set at vii , and the sub isolation signal generating circuit 344 operates as follows : the output of the nor circuit 345 is vss ; the output of the inverter 347 is vii ; the nmos transistor 350 is off ; the nmos transistor 351 is on ; the pmos transistor 348 is on ; the pmos transistor 349 is off ; and the sub isolation signal sis 2 becomes equal to vpp . the nmos transistors 371 and 372 in the isolation circuit 370 are turned on . as a result of the operation , the cell array 353 and the sense amplifier part 354 are electrically connected , while the cell array 352 and the sense amplifier part 354 are electrically isolated . fig1 is a circuit diagram of another circuit configuration of the sub isolation signal generating circuit employed in the first embodiment of the present invention . the circuit includes a level conversion circuit 373 that &# 39 ; s converts the level of the main isolation signal mis into another level . the circuit 373 includes an inverter 374 inverting the main isolation signal mis , pmos transistors 375 and 376 , and nmos transistors 377 and 378 . the inverter 374 has a cmos structure that receives the power supply potential vii on the high - potential side and the ground potential vss on the low - potential side . the sources of the pmos transistors 375 and 376 are connected to the vpp line via which the boosted potential vpp is supplied . a level conversion circuit 379 converts the level of the column block selection signal cbs , and includes an inverter 380 inverting the column block selection signal cbs , pmos transistors 381 and 382 , and nmos transistors 383 and 384 . the inverter 380 has a cmos structure that receives the external power supply potential vii on the high - potential side and the ground potential vss on the low - potential side . the sources of the pmos transistors 381 and 382 are connected to the vpp line via which the boosted potential vpp is supplied . a nor circuit 385 performs a nor operation on the outputs of the level conversion circuits 373 and 379 . the nor circuit 385 and the inverter 386 each have a cmos structure that receives the boosted voltage vpp on the high - potential side and the ground potential vss on the low - potential side . when the isolation transistors are turned off by the sub isolation signal sis , the main isolation signal mis is set at vss , and the column block selection signal cbs is set at vss . thus , the level conversion circuit 373 operates as follows : the output of the inverter 374 is vii , the nmos transistor 377 is off , the nmos transistor 378 is on , the pmos transistor 375 is on , the pmos transistor 376 is off , and the output of the level conversion circuit 373 is vss . the level conversion circuit 379 operates as follows : the output of the inverter 380 is vii , the nmos transistor 384 is on , the nmos transistor 383 is off , the pmos transistor 382 is off , the pmos transistor 389 is on , and the output of the level conversion circuit 379 is vss . thus , in the above case , the output of the nor circuit 385 is vpp , the output of the inverter 386 , namely , the sub isolation signal sis is vss . as a result , the isolation transistors controlled by the sub isolation signal are turned off . in contrast , when the isolation transistors controlled by the sub isolation signal sis are turned on , the main isolation signal mis is set at vii . thus , the level conversion circuit 373 operates as follows : the output of the inverter 374 is vss , the nmos transistor 377 is on , the nmos transistor 378 is off , the pmos transistor 375 is off , the pmos transistor 376 is on , and the output of the level conversion circuit 373 becomes equal to vpp . thus , in this case , the output of the nor circuit 385 becomes equal to vss , and the output of the inverter 386 , namely , the sub isolation signal sis becomes equal to vpp . as a result , the isolation transistors controlled by the sub isolation signal sis are turned on . as described above , according to the first embodiment of the present invention , only the high - potential - side potential of the sub isolation signal is set at the boosted potential vpp , while the high - potential - side potential of the main isolation signal is set at the step - down potential vii . it is therefore possible to reduce the number of signal lines that have the potential vpp on the high - potential side . this results in reduction of consumption power of semiconductor devices that has the shared sense amplifier system and a hierarchical configuration in which the word drivers are hierarchically divided into the word drivers and sub word drivers and the isolation signal generating circuits are hierarchically divided into the main isolation signal generating circuits and the sub isolation signal generating circuits . in a case where the boosted voltage vpp is needed for the potential of the bit line precharge signal pr on the high - potential side in the sub - isolation signal generating circuits configured as shown in fig1 , the sub isolation signal sis can be used to generate the bit line precharge signal . the main isolation circuits may be configured so as to generate the main isolation signals that swing between the step - down potential vii obtained by stepping down the external power supply voltage vii and the ground potential vss . a description will be given , with reference to fig1 and 13 , of a second embodiment of the present invention . fig1 is a circuit diagram of a part of a core part of the second embodiment of the present invention . in fig1 , main sub - word selection signal generating circuits 387 - 390 have a different circuit configuration from that of the main sub - word selection signal generating circuits 248 - 251 shown in fig7 . main isolation signal generating circuits 391 and 392 have a different circuit configuration from that of the corresponding circuits 260 and 261 shown in fig7 . sub isolation signal generating circuits 393 - 396 have a different circuit configuration from that of the corresponding circuits 262 - 265 shown in fig7 . in short , the second embodiment of the present invention substitutes the main sub - word selection signal generating circuits 387 - 390 , the main isolation signal generating circuits 391 and 392 , and the sub isolation signal generating circuits 393 - 396 for the corresponding circuits shown in fig7 while the other parts of the second embodiment are the same as those of the dram shown in fig7 . in the second embodiment , the main sub - word selection signal generating circuits are configured so as to generate main sub - word selection signals that swing between the step - down potential vii on the high - potential side and the ground potential vss on the low - potential side . the main isolation signal generating circuits are configured so as to generate main isolation signals that swing between the step - down potential vii on the high - potential side and the ground potential vss on the low - potential side . the sub isolation signal generating circuits are configured so as to generate sub isolation signals that swing between the boosted potential vpp on the high - potential side and the ground potential vss on the low - potential side in response to the main isolation signal that swings the step - down potential vii on the high - potential side and the ground potential vss on the low - potential side . referring to fig1 , broken lines with arrows denote signal lines that carry signals that swing between the step - down potential vii on the high - potential side and the ground potential vss on the low - potential side . solid lines with arrows denote signals that carry signals that swing between the boosted potential vpp and the ground potential vss . more particularly , the signal lines swinging between the step - down potential vii and the ground potential vss are used for the address signal lines 224 , the main sub - word selection signal lines that are the output lines of the main sub - word selection signal generating circuits 387 - 390 , and the main isolation signal lines that are the output lines of the main isolation signal generating circuits 391 and 392 . the signal lines swinging between the boosted potential vpp and the ground potential are used for the main word lines that are the output lines of the main word drivers 225 - 227 , the sub sub - word selection signal lines that are the output lines of the sub sub - word selection signal generating circuits 252 - 259 , the sub isolation signal lines that are the output lines of the sub isolation signal generating circuits 393 - 396 , and the bit - line precharge signal lines that are the output lines of the bit line precharge signal generating circuits 266 and 267 . fig1 is a circuit diagram of a circuit arranged in the ss cross areas of the core part in the second embodiment of the present invention . the circuit includes sub isolation signal generating circuits 397 and 398 , a bit line precharge signal generating circuit 399 , a sub sub - word selection signal generating circuit 400 , and a sub word driver 401 . the bit line precharge signal generating circuit 399 , the sub sub - word line signal generating circuit 400 and the sub word driver 401 are the same as the bit line precharge signal generating circuit 276 , the sub sub - word selection signal generating circuit 279 , and the sub word driver 286 shown in fig8 . the sub isolation signal generating circuit 397 includes an input circuit part 402 , which includes a pmos transistor 403 , and nmos transistors 404 and 405 . the input circuit part 402 operates with the step - down potential vii on the high - potential side and the ground potential vss on the low - potential side . a pmos transistor 406 serves as a level stabilization element , and the source thereof is connected to the vii line via which the step - down potential is supplied . a level conversion circuit 407 converts the potential of the output of the input circuit part 402 on the high - potential side from the step - down potential vii to the boosted potential vpp . the circuit 407 includes an inverter 408 inverting the output of the input circuit part 402 , pmos transistors 409 and 410 , and nmos transistors 411 and 412 . the inverter 408 operates with the step - down potential vii on the high - potential side and the ground potential vss on the low - potential side . the sources of the pmos transistors 409 and 410 are connected to the vpp line via which the boosted potential is supplied . inverters 413 and 414 operate with the boosted potential vpp on the on the high - potential side and the ground potential on the low - potential side . according to the second embodiment of the present invention , only the potential of the sub sub - word selection signals on the high - potential side is set at the boosted potential vpp , while the potential of the main sub - word selection signals on the high - potential side is set at the step - down potential . it is therefore possible to reduce the number of signal lines that have the boosted potential vpp on the high potential side . this results in reduction of consumption power of semiconductor devices that has the shared sense amplifier system and a hierarchical configuration in which the word drivers are hierarchically divided into the word drivers and sub word drivers and the isolation signal generating circuits are hierarchically divided into the main isolation signal generating circuits and the sub isolation signal generating circuits .