fig1 through 3 , discussed below , and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention . those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged packet switching or routing device . fig1 illustrates exemplary communication network 100 containing data packet switches 111 - 114 in accordance with the principles of the present invention . communication network 100 comprises subnetwork 105 ( indicated by a dotted line ) that contains data packet switches 111 - 114 , that interconnects end - user devices 131 - 134 with each other and with other switches ( not shown ) and other end - user devices ( not shown ) associated with communication network 100 . data packet switches 111 - 114 are interconnected by heterogeneous data links 121 - 126 . according to an advantageous embodiment of the present invention , each one of data links 121 - 126 comprises multiple heterogeneous data links ( i . e ., multilinks ). for example , data link 121 may comprise two or more of : t 1 lines , t 3 lines , fiber optic lines , and / or wireless links ( i . e ., rf channels ). subnetwork 105 is intended to be a representative portion of communication network 100 , which may contain many other switches similar to data packet switches 111 - 114 . communication network 100 may also comprise wireless equipment , such as a base station , that enables communication network 100 to communicate with wireless devices , such as cellular telephones and / or computers equipped with cellular modems . in accordance with the principles of the present invention , each of data packet switches 111 - 114 comprises a packet scheduler that schedules the transmission of data packets over the multiple heterogeneous data links coupled to each data packet switch . the packet scheduler in a source node ( or transmitting node ) receives data packets from some network data packet generator ( e . g ., one of user devices 131 - 134 ) and schedules each data packet to be transmitted over one of the data links — coupling the source node to the destination node ( or receiving node ). however , the packet scheduler is not constrained to use the same type of data link for data packets received from the same data packet generator . thus , the packet scheduler may select different types of links for different data packets from the same data packet generator . fig2 illustrates exemplary data packet switch 111 in greater detail according to one embodiment of the present invention . in the illustrated example , data packet switch 111 ( labeled “ source node ”) is receiving outbound data packets from a data packet generator ( e . g ., end - user device 131 ). data packet switch 111 then schedules and transmits the data packets to data packet switch 112 ( labeled “ destination node ”). the data packets are transmitted between the source node and the destination node by up to n heterogeneous data links 121 , including exemplary data links 121 a , 121 b and 121 c . data packet switch 111 ( i . e ., source node 111 ) comprises packet scheduler 210 , and n packet queues 220 , including exemplary packet queue ( q ) 220 a , 220 b , and 220 c . according to an exemplary embodiment of the present invention , packet queues 220 comprise data buffers capable of holding ( queuing ) data packets that are to be transmitted across data links 121 . data packet switch 111 also comprises queue statistics monitor 230 , which monitors selected statistics about each packet queue . these statistics may include the number of queued data packets in each packet queue 220 , the queued data packet sizes , or the like . according to an alternate embodiment , queue statistics monitor 230 may not be a separate device from packet scheduler 210 . instead , queue statistics monitor 230 may be integrated into the packet processing circuitry of packet scheduler 210 , or into packet queues 220 themselves . during routine operation , data packets enter data packet switch 111 ( i . e ., source node 111 ) and are sent to data packet switch 112 ( i . e ., destination node 112 ) over the n data links 121 at varying speeds . it is assumed that the aggregate bandwidth of the n data links 121 is greater than , or equal to , the sustained traffic rate from source node 111 and destination node 112 . the present invention is capable of supporting switching systems that have output queuing , but no input queuing . according to an exemplary embodiment of the present invention , packet scheduler 210 may be embodied as a controller ( or packet processor ) comprising a data processor and a memory for storing instructions executable by the data processor . the present invention implements an algorithm that is executed by packet scheduler 210 in data packet switch 111 ( i . e ., the source node ). for each incoming data packet , the novel algorithm selects an optimal outgoing data link among the multiple data links 121 a , 121 b , 121 c , and so forth . during routine operation , packet scheduler 210 is configured with the following operating parameters about each data link 121 at startup : 1 ) state of the link ( e . g ., available or not available for packet queuing ); 2 ) quality of service ( qos ) types supported by the link ; 3 ) link bandwidth ( bw ) partitioned by qos types ; and 4 ) link propagation delay ( d ). packet scheduler 210 may be configured with these link parameters by any conventional means , including , for example , a management interface ( e . g ., snmp , cli , etc .) or a link discovery protocol . the total delay incurred by a packet in reaching the destination is the sum of : 1 ) queuing delay at the output queue ; 2 ) transmission delay for sending the complete packet ; and 3 ) the propagation delay of the selected data link 121 . the algorithm of the present invention selects a link such that the delay incurred is for each data packet is minimal . such a selection invariably ensures that : 1 ) the end - to - end delay is the minimum for each packet ; 2 ) the probability of data packet reordering is minimal ; and 3 ) no additional buffering is required at the destination node for packet reordering . fig3 depicts flow diagram 300 , which illustrates the operation of exemplary data packet processing node 111 according to one embodiment of the present invention . as noted above , packet scheduler 210 is initially configured with operating parameters about each data link 121 at startup ( process step 305 ). for each new outgoing data packet that packet scheduler 210 receives , packet scheduler 210 determines the qos requirement of the packet and selects a suitable set of data links 121 that can support the qos requirements ( process step 310 ). next , packet scheduler 210 computes the packet delay ( pd ) factor for each selected data link 121 using the equation : pd i is the packet delay for the ith data link 121 ; d i is the link propagation delay of the ith data link 121 ; ps is the packet size ; qs i is the queue size of the ith data link 121 ; and bw i is the bandwidth of the ith data link 121 ( process step 315 ). once the packet delay ( pd ) is known for each data link 121 , packet scheduler 210 selects the data link 121 with the minimum packet delay ( process step 320 ). next , packet scheduler 210 inserts the data packet to the end of the output queue 220 associated with the selected data link 121 ( process step 325 ). next , queue statistics monitor 230 updates the statistics for all packet queues 220 ( process step 330 ). queue statistics monitor 230 reads the current queue size for each of packet queues 220 . the complexity of the present invention increases with the number of data link 220 supported . the calculation above may be done in software in packet scheduler 210 for a limited number of links on a per packet basis . in alternate embodiments , hardware - based implementations may be used for high packet rate requirements . one important goal of the algorithm is to minimize the packet - reordering problem at destination node 112 . simulations have shown that link utilization reaches 100 % if there are enough data packets to fill in the entire bandwidth . this type of packet queuing can be useful specifically for delay and jitter sensitive applications like voice over ip . this mechanism also supports the qos requirements for applications by choosing a set of links that can meet the requirements . the most common prior art methods of load balancing assume the links to be homogeneous in nature and balancing of the bandwidth ( i . e ., optimizing the link utilization ) is the main concern . methods based on bandwidth optimization need a large and indefinite amount of buffering at the destination node in order to deliver the packets in sequence . this attribute makes support of real - time and delay - sensitive applications across heterogeneous links difficult , if not impossible , due to the introduction of indefinite latency and the resultant jitter . the proposed mechanism is suitable for implementation in any real - time system . it is protocol independent and scales well for a large number of heterogeneous links with different delay and bandwidth properties . it can be adopted in network devices supporting multi - link ppp and frame relay over wan links . although the present invention has been described with an exemplary embodiment , various changes and modifications may be suggested to one skilled in the art . it is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims .