hereinafter , the present invention will be described referring to the accompanying drawings . first , an embodiment of the present invention will be described referring to fig1 a through 1j . as shown in fig1 a , an oxide layer 102 is deposited on a silicon substrate 101 , and a portion of the oxide layer 102 is etched by a mask process . an etching process to form a trench in the silicon substrate 101 is performed . as shown in fig1 b , an oxide spacer layers 103 are formed on the sidewall of the oxide layer 102 to form the trench which has a narrower width than that of the patterned oxide layer by the mask process in fig1 a , and a trench 104 is formed by etching the exposed silicon substrate 101 , using the oxide layer 102 and the oxide spacer layers 103 as an etching mask . of course , since oxide spacer layers 103 are used for decreasing the width of the trench 104 , the step of forming the oxide spacer layers 103 can be skipped according to manufacturing conditions . as shown in fig1 c , the residual oxide layers 102 and 103 on the silicon substrate 101 are removed , and an oxide layer 105 is formed on the resulting structure , thereby filling in the trench 104 . next , as shown in fig1 d , the oxide layer 105 is etched back except for the oxide layer 105 &# 39 ; in the trench 104 . also , the etching rate is controled in order that the depth &# 34 ; d &# 34 ; is formed from the surface of the silicon substrate 101 to the surface of the oxide layer 105 &# 39 ; in the trench 104 . the depth &# 34 ; d &# 34 ; is needed for forming a channel of the mos transistor which will be described by following process . referring now to fig1 e , a polysilicon layer 106 is formed on the resulting structure , filling in the trench 104 which is not still filled with the oxide layer 105 &# 39 ;. the polysilicon layer 106 can be substituted for a silicon layer . as shown in fig1 f , the polysilicon layer 106 over the surface of the silicon substrate 101 is oxidized by an oxidation process which is used in the conventional semiconductor process . then , an oxide layer 107 is formed by the the oxidation process and a polysilicon layer 106 &# 39 ; remains from the surface of the silicon substrate 101 to the surface of the oxide layer 105 &# 39 ; in the trench 104 . at this time , the polysilicon layer 106 &# 39 ; serves as a substrate . the oxide layer 107 is removed and an ion implantation is performed to adjust the threshold voltage of the transistor , as shown in fig1 g . fig1 h illustrates the step of forming , in turn , an oxide layer 108 and a polysilicon layer 109 for the gate electrode . fig1 i illustrates the step of patterning the oxide layer 108 and the polysilicon layer 109 in a predetermined size , and then , forming a gate oxide layer 108 &# 39 ; and a gate electrode 109 &# 39 ;. finally , as shown in fig1 j , a source / drain region 110 is formed by an ion implantation . as illustrated above , the transistor , in accordance with an embodiment of the present invention , differs from the conventional transistor in the formation of the oxide layer 105 &# 39 ; and the polysilicon layer 106 &# 39 ; in the silicon substrate 101 , in order to improve the feature of the punchthrough of the transistor . now , another embodiment of the present invention will be described referring to fig2 a through 2i . as shown in fig2 a , low concentration ions ( n - or p -), whose impurity type is different from that of a substrate 201 , are implanted into a silicon substrate 201 , and then a doped region 202 is formed on the silicon substrate 201 . as shown in fig2 b , a nitride layer 203 is formed on the doped region 202 , and the nitride layer 203 is patterned in order to expose a portion of the silicon substrate 201 using a mask process and an etching process . as shown in fig2 c , a trench 204 is formed by etching the doped region 202 and the exposed silicon substrate 201 , using the nitride layer 203 as an etching mask . of course , oxide spacer layers as illustrated in fig1 b can be used for decreasing the width of the trench 204 . after forming the trench 204 , an oxide layer 205 is formed on the resulting structure , thereby filling in the trench 204 . next , as shown in fig2 d , the oxide layer 205 is etched back except for the oxide layer 205 &# 39 ; in the trench 204 . also , the etching rate must be controled in order that the depth &# 34 ; d &# 34 ; is formed from the surface of the silicon substrate 201 to the surface of the oxide layer 205 &# 39 ; in the trench 204 . the depth &# 34 ; d &# 34 ; is needed for forming a channel of the mos transistor which will be described by the following process . referring now to fig2 e , a polysilicon layer 206 is formed on the resulting structure , filling in the trench 204 which is not still filled with the oxide layer 205 &# 39 ;. as shown in fig2 f , the polysilicon layer 206 is etched back such that a polysilicon layer 206 &# 39 ;, which serves as a substrate , is formed only in the trench 204 , and an ion implantation is performed to adjust the threshold voltage of the transistor . fig2 g illustrates the step of forming , in turn , an oxide layer 207 and a polysilicon layer 208 for the gate electrode , and fig2 h illustrates the step of patterning the gate oxide layer 207 &# 39 ; and a gate electrode 208 &# 39 ; in a predetermined size . finally , as shown in fig2 i , a source / drain region 209 , which is highly doped region , is formed by an ion implantation . as illustrated above , this embodiment shows that transistors having the ldd structure in fig1 j are accomplished with the doped region 202 . furthermore , another embodiment of the present invention will be described referring to fig3 a through 3h . as shown in fig3 a , an oxide layer 302 and a nitride layer 303 is , in turn , deposited on a silicon substrate 301 , and a portion of the oxide layer 302 and the nitride layer 303 are etched by a mask process and an etching process in order to form a trench in the silicon substrate 301 . as shown in fig3 b , a nitride spacer layer 304 are formed on the sidewall of the oxide layer 302 and the nitride layer 303 to form the trench , which has a narrower width than that of the patterned oxide and nitride layer , by the mask process in fig3 a . as shown in fig3 c , a trench 305 is formed by etching the exposed silicon substrate , using the nitride layer 303 and the nitride spacer layers 304 as an etching mask . of course , since the nitride spacer layer 304 is used for decreasing the width of the trench 305 , the step of forming the nitride spacer layers 304 can be skipped according to manufacturing conditions as illustrated in fig1 b . next , as shown in fig3 d , the exposed substrate 301 is oxidized using the nitride layer 303 and the nitride spacer layer 304 as an oxidation mask so that an oxide layer 306 is formed in the trench 305 . after the nitride layer 303 and the nitride spacer layer 304 are removed , the oxide layer 306 is etched back except for the oxide layer 306 &# 39 ; in the trench 305 , as shown in fig3 e . at this time , the etching rate is controled in order that the depth &# 34 ; d &# 34 ; is formed from the surface of the silicon substrate 301 to the surface of the oxide layer 306 &# 39 ; in the trench 305 . the depth &# 34 ; d &# 34 ; is needed for forming a channel of the mos transistor which will be described by the following process . referring now to fig3 f , an epitaxy process is applied to the exposed silicon substrate 301 such that a silicon layer 307 is filled in the trench 305 which is not still filled with the oxide layer 306 &# 39 ;. after forming the silicon layer 307 , impurity ions to control the threshold voltage is implanted into the silicon layer 307 using the oxide layer 302 as an ion implanting mask as shown in fig3 g , a gate oxide layer 308 is formed on the polysilicon layer 307 grown by epitaxy process and a polysilicon layer 309 for the gate electrode is formed on the resulting structure . referring to fig3 h , a polysilicon layer 309 &# 39 ; and an oxide layer 302 &# 39 ; is patterned in a predetermined size , and a source / drain region 310 is formed by an ion implantation . as stated above , the present invention can effectively improve punchthrough feature pmos transistors having a short channel and forming an insulating layer under the channel , therefore , having an effect on stability of transistors &# 39 ; operation . in compliance with statute , the invention has been described in language more or less specific as to structural and methodical features . it is to be understood , however , that the invention is not limited to the specific features shown and described , since the means herein disclosed comprise preferred forms of putting the invention into effect . the invention is , therefore , claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents .