the present invention would be described with reference to the drawings wherein like numerals represent similar elements throughout . for purposes of describing the present invention , the phrase low , medium , or high voltage levels may be used . it will be appreciated that the words “ low ”, “ medium ”, and “ high ” are relative terms and not necessarily a fixed voltage . accordingly , the phrase low , medium , or high voltage level may be any voltage and may vary , for example , based on the processing technology and / or the material in which an electronic device is implemented . the word “ level ” may represent a fixed voltage or a voltage range , as desired . moreover , predetermined voltage levels in the description forthcoming can be any voltage level and may be dependent on the design , structure , and materials used to configure a circuit element . a node , a voltage at a node , or a current at a node may be used interchangeably and a load capacitance may be a parasitic capacitance in the description forthcoming . it should be understood by those of skill in the art that the equations and variables set forth below are exemplary and should not be understood to limit the invention . a block diagram of a pipelined adc in accordance with the present invention is shown in fig3 . the adc 200 includes a bias current unit 201 , a track and hold ( t & amp ; h ) unit 204 , a plurality of pipeline stages including pipeline stages 1 through 4 206 0 - 3 , pipeline stages 5 through 8 206 4 - 7 , and a flash adc unit 216 . although stages 1 through 4 and 5 through 8 are shown as separated into two distinct groups this is only for simplicity of explanation . each stage may be provided with an independent reference current level by bias current unit 201 , as will be explained in detail hereinafter , and an independent operating point . the adc circuit 200 may also have any number of pipeline stages depending upon the desired resolution of the adc circuit 200 . it should be understood by those of skill in the art that pipelined adcs may comprise many other components to support the various resolutions of the adc circuit 200 . however , for simplicity , only those portions of the pipelined adc in accordance with the present invention are described in detail hereinafter . the bias current unit 201 includes a reference current generator 202 which may be a proportional to the absolute temperature ( ptat ) reference current generator , a constant mode current generator 205 and an active speed current generator 210 . the reference current generator 202 generates and provides reference current , which is proportional to temperature in the case of a ptat reference current , to the constant mode current generator 205 and the active speed current generator 210 . a ptat reference current generator 202 may be desirable in order to make the present invention insensitive to temperature effects . considering a programmed adc speed , the use of a ptat reference current generator would maintain the desired ota bandwidth constant over any temperature variations providing compliance for any desired operational temperature range for the present invention . the constant mode current generator 205 generates constant mode bias current ic to the individual pipeline stages 206 0 - 7 . the active speed current generator 210 selectively generates variable or programmable bias current ia to the individual pipeline stages 206 0 - 7 . in general , the bias current unit 201 generates and distributes current to the t & amp ; h unit 204 and the individual pipeline stages 206 0 - 7 via 2 separate channels ; a first channel 212 for conducting constant mode current ic and a second channel 214 for conducting variable current ia . the first channel 212 comprises a bus of nine lines ; one line for each active component ; ( i . e . the t & amp ; h unit 204 and the pipeline stages 206 0 - 7 ). accordingly , constant mode current ic is distributed via one of the lines to the t & amp ; h unit 204 and the pipeline stages 206 0 - 7 . the constant mode current ic , generated by the constant mode current generator 205 , is a fixed current which depends on the mode of operation of the adc . the second channel 214 comprises a bus of nine lines ; one line for each active component . accordingly , active speed current ia is distributed via one of the lines to the t & amp ; h unit 204 and the pipeline stages 206 0 - 7 . the active speed current ia may be used to provide increased flexibility and greater bandwidth to the t & amp ; h unit 204 , as desired . the mode & lt ; 1 : 0 & gt ; input to bias current unit 201 may be used to selectively control the operation of the currents ic and ia . the active speed current ia is proportional to the desired speed & lt ; s - 1 : 0 & gt ;, where s may be any number , which may offer 2 s codes of programmability . although up to two bits of programmability is shown in fig3 , s may be any value used to provide higher desired levels of analog to digital resolution , as desired . still referring to fig3 , the t & amp ; h unit 204 samples an analog input signal , maintains that signal level for a predetermined duration , and passes the signal to the pipelined stages 206 0 - 7 for sequential processing of the signal . the final pipeline stage transfers the last analog signal to the flash adc unit 216 for quantization of the pipeline remaining residue . in accordance with the present invention , the bias current unit 201 selectively delivers constant mode and active speed current ic , ia , respectively , to each of the active components 204 and 206 0 - 7 . since each stage may be selectively provided with a constant mode and an adaptive active speed currents ic , ia respectively , the pipelined adc 200 can be programmed to provide any desired data rate while minimizing power requirements . power is conserved since the use of an unnecessarily high active current may be prevented by independently adjusting the current level of each pipelined stage . referring to fig4 , a schematic diagram of the bias current unit 201 which generates and selectively outputs current for each pipelined stage 206 0 - 7 in accordance with the present invention is provided . the bias current unit 201 includes the reference current generator 202 , which may be a ptat reference current to compensate for any temperature effects , and a plurality of bias stages 250 0 - 8 ; one for each pipelined stage 206 0 - 7 and the t & amp ; h unit 204 . the constant mode current generators 205 0 - 8 and the active speed current generators 210 0 - 8 may comprise separate and distinct components as shown in fig4 . in fig4 , each current generator may comprise a portion of a bias stage 250 . the reference current generator 202 distributes a reference current ib i [ i = 0 . . . 8 ] to each of the plurality bias stages 250 0 - 8 that provide current to each pipelined stage 206 0 - 7 and the t & amp ; h unit 204 . although nine bias stages are shown in fig4 , any number of bias stages may be used depending upon the desired number of pipelined stages . each bias stage 250 0 - 8 receives ib i , which is used as a current reference iref as shown by 203 0 - 8 , and transmits both constant mode current ic i and active speed current ia i to its corresponding pipeline stage 206 0 - 7 and t & amp ; h unit 204 . the transfer function of the local bias stage number i is given as follows : where iref is the reference current provided by unit 202 , c is a constant integer dependent upon the desired ota operating point , and a i is a programmable or variable number , such as an integer , dependent upon the desired variable program speed & lt ; s - 1 : 0 & gt ;. since a i is a variable , the adc can be used to provide an active current that is proportional to any desired data or conversion rate . table 1 provides purely as an example a case where s = 2 . since a i is a variable , each ota in the pipeline adc 200 may be programmed using any amount of current ia i as given in equation ( 3 ) and shown in table 1 . since the ota in accordance with the present invention may be programmable , the ota can provide a bandwidth large enough to be compatible with any desired adc data rate . each pipelined stage 206 0 - 7 in accordance with the present invention may be configured similar to the general configuration shown in fig2 . however , the present invention includes an ota 300 which is adapted to take advantage of the two - part current distribution scheme shown in fig3 and 4 for adjusting the power consumption to any desired data rate . with the power consumption adapted to the desired adc data rate , this data rate is considered as the maximum data rate ( mdr ) of the adc . referring to fig5 , a transistor level schematic of an ota 300 in accordance with the present invention is shown . although , there are a plurality of bias stages 250 0 - 8 in a pipelined adc having a corresponding plurality of otas 300 , only one ota 300 is shown for simplicity . the ota 300 is a fully differential folded cascode topology using an n - type metal - oxide semiconductor ( nmos ) transistor input pair . as those that are skilled in the art would realize , the p - type metal - oxide semiconductor ( pmos ) type transistor input pair version could also be considered . the output of the ota 300 may be loaded by single - ended load capacitors cl . the common mode feedback box ( cmfb ) provides regulation of the common mode output voltage ensuring that either vop = von = vcm when vip = vin at the input of the ota 300 or ( vop + von )/ 2 = vcm for all other cases . the two separate input currents , the active speed current ia at node 302 and the constant mode current ic at node 304 are received from a respective bias stage 250 0 - 8 . the constant mode current ic is derived from equation ( 2 ) and is used to set the internal cascode voltage nodes vcas 304 , 306 , and 308 in order to maximize the dynamic output range of the ota 300 . the active speed current ia is derived from equation ( 3 ) and is used to provide a desirable unity gain bandwidth for ota 300 . a metric used to measure the performance of circuits 200 and 300 is the ratio of the maximum data rate ( mdr ) to the power dissipation , sometimes referred to as the figure of merit ( fom ) of an adc device , given by equation ( 4 ) as follows : the mdr of adc 200 is given by equation ( 5 ) as follows : in equation ( 5 ), a is a fixed parameter dependent upon a desired processing technology and the desired resolution ( i . e . number of bits ) of an adc , and k is the current amplification factor of ota 300 . therefore , mdr is directly proportional to the current amplification factor k , the reference current iref , and the local active current variable a i for each stage as set forth in equation ( 3 ) and shown in fig4 . mdr is inversely proportional to the equivalent capacitance , including any parasitic capacitances , cl seen at the output of circuit 300 . in equation ( 4 ), the dissipated power metric is calculated by summing the current consumed by each pipeline stage 206 0 - 7 and t & amp ; h unit 204 . since each pipeline stage 206 0 - 7 and t & amp ; h unit 204 may include an ota similar to 300 , the total dissipated power is given by equation ( 6 ) as follows : in equation ( 6 ), p is the total number of ota circuits 300 used in adc 200 , v dd is the supply voltage level , and current idd is the supply current level at node 310 for each stage given by equation ( 7 ) as follows : in equation ( 7 ), k is the current amplification factor of ota 300 , ic i is the constant mode current at node 304 , and ia i is the active speed current at node 302 . substituting equations ( 2 ) and ( 3 ) into equation ( 7 ) gives equation ( 8 ) as follows : idd = ( c + 2 ( 2 k + 1 )( a i + 1 )) * i ref . equation ( 8 ) in equation ( 8 ), the variables c , k , a i , and iref are the same as those provided in equations ( 2 ), ( 3 ) and ( 7 ) above . since the supply current idd of each ota stage 300 is dependent upon the programmable variable a i , both the ota unity gain bandwidth and power consumption may be optimized for ota 300 and adc 200 , respectively . substituting equations ( 5 ), ( 6 ), and ( 8 ) into equation ( 4 ) and assuming 2 ( 2k + 1 )& gt ;& gt ; c , the fom may be given by equation ( 9 ) as follows : in equation ( 9 ), c , a i and iref have been removed from the expression for the fom . the adc 200 has been made independent of the programmed data rate and corresponding current consumption which results in adc 200 performing at a desirably optimized constant speed over power ratio . fig6 is a process 400 for providing steps for analog to digital conversion having a selectable data rate and optimized power dissipation in accordance with the present invention . an adc is reset and the mode and speed are preset to a default value providing a default bias current setting which includes a set of constant bias current and a set of ( preset ) variable or active bias current ( step 402 ). a variable analog signal level is sampled ( step 404 ) to provide a constant analog signal . the constant analog signal level is provided to an analog to digital converter for producing a first digital output number which is then converted back to a converted analog signal via a digital to analog converter ( step 406 ). a first analog remainder is provided by subtracting the second analog signal from the sampled analog signal level ( step 408 ). the first analog remainder signal is used to produce a second digital output number and a second analog remainder ( step 410 ). the first and second digital output numbers are summed to produce a digital output signal ( step 412 ). changing the speed programming to generate a new set of variable bias current , for producing the digital output signal to the desired data rate while dissipating a minimum amount of power ( step 414 ) may then be performed . although the features and elements of the present invention are described in the preferred embodiments in particular combinations , each feature or element can be used alone without the other features and elements of the preferred embodiments or in various combinations with or without other features and elements of the present invention . the present invention may be implemented in a computer program or firmware tangibly embodied in a computer - readable storage medium having machine readable instructions for execution by a machine , a processor , and / or any general purpose computer for use with or by any non - volatile memory device . suitable processors include , by way of example , both general and special purpose processors . typically , a processor will receive instructions and data from a read only memory ( rom ), a ram , and / or a storage device having stored software or firmware . storage devices suitable for embodying computer program instructions and data include all forms of non - volatile memory , including by way of example semiconductor memory devices , read only memories ( roms ), magnetic media such as internal hard disks and removable disks , magneto - optical media , and optical media such as cd - rom disks and digital versatile disks ( dvds ). types of hardware components , processors , or machines which may be used by or in conjunction with the present invention include application specific integrated circuits ( asics ), field programmable gate arrays ( fpgas ), microprocessors , or any integrated circuit .