an embodiment of the present invention will be explained in detail with reference to the attached drawings . an npn type algaas / gaas hbt of the present embodiment is featured in that , as shown by an energy band in its emitter base junction in fig1 with respect to the band gap 125 mev of the original emitter / base junction , the band gap can be made narrow by 74 mev and thus the band gap difference can be made to be 199 mev , by making the impurity concentration of a base layer as high as 1 × 10 20 cm - 3 . the heterojunction bipolar transistor , as shown in fig2 comprises an n + type gaas layer having a thickness of 5000 å as a collector contact layer 102 stacked on a semi - insulating gaas substrate 101 , an n - type gaas layer having a thickness of 5000 å as a collector layer 103 stacked on the collector contact layer 102 , a p + type al x ga 1 - x as ( x : 0 → 0 . 1 ) layer having a thickness of 900 å , an undoped al 0 . 1 ga 0 . 9 as layer having a thickness of 100 å and an al x ga 1 - x as layer ( x : 0 . 1 → 0 . 24 ) having a thickness of 300 å which form a graded structure in which the value of x is gradually increased toward an emitter layer 105 so as to slant a conduction band and which form a base layer 104 formed on the n - type gaas ; an n type al x ga 1 - x as ( x = 0 . 24 ) layer having a thickness of 1500 å , an n type al x ga 1 - x as layer ( x : 0 . 24 → 0 ) having a thickness of 300 å and an n type in x ga 1 - x as layer ( x : 0 → 0 . 5 ) having a thickness of 500 å which form the emitter layer 105 formed on the base layer 104 ; and an n type in x ga 1 - x as ( x = 0 . 5 ) layer as an emitter cap layer 106 formed on the emitter layer 105 . in addition , a collector electrode 111 , a base electrode 112 and an emitter electrode 113 are formed through the contact of a silicon oxide film 109 covering the above laminated layers . in the illustrated embodiment , the collector electrode 111 is made of an auge / ni / au layer , the base electrode 112 is made of a cr / au layer , and the emitter electrode 113 is made of a ti / pt / au layer , respectively . the illustrated structure of fig2 further includes an insulating layer 107 for inter - device isolation which is formed by boron ion implantation , and an insulating layer 108 for inter - device isolation which is formed by proton implantation . explanation will next be made how to fabricate the hereto junction bipolar transistor . it is necessary first of all to epitaxially grow these semiconductor layers sequentially on the gaas substrate in a lattice - aligned relation to the layers . in this connection , as the epitaxial growth technique , a molecular - beam epitaxy technique ( mbe technique ), a gas source molecular - beam epitaxy technique ( gsmbe technique ), or a low - pressure metal organic cvd technique ( lpmocvd technique ) is used . the fabrication conditions of the transistor when the molecular - beam epitaxy technique is employed will be detailed sequentially in connection with its fabrication steps . first , an n + type gaas layer of 5000 å thickness as the collector contact layer 102 having an si impurity concentration of 3 × 10 18 cm - 3 and then an n - type gaas layer of 5000 å as the collector layer 103 having an impurity concentration of 8 × 10 16 cm - 3 are sequentially epitaxially grown on the semi - insulating gaas substrate 101 . then epitaxially grown on the n - type gaas layer is a p + type al x ga 1 - x as ( x : 0 → 0 . 1 ) of 900 å thickness having a be impurity concentration of 1 × 10 20 cm - 3 . in this case , the value of x is set so as to be increased from 0 to 0 . 1 upward from its bottom , whereby an electric field can be established to accelerate electrons within the base from its emitter side to the collector side . next , sequentially grown on the p + type al x ga 1 - x as ( x : 0 → 0 . 1 ) layer are an undoped al x ga 1 - x as ( x = 0 . 1 ) of 100 å and an n type al x ga 1 - x as ( x : 0 . 1 → 0 . 24 ) of 300 å having an si impurity concentration of 5 × 10 17 cm - 3 . in the layers , the value of x is set so as to be increased from 0 . 1 to 0 . 24 upward from its bottom , whereby the conduction band in the base / emitter junction can be made smooth . epitaxially grown on the n type al x ga 1 - x as ( x : 0 . 1 → 0 . 24 ) layer are an n type al x ga 1 - x as ( x = 0 . 24 ) layer of 1500 å having an si impurity concentration of 5 × 10 17 cm - 3 and then an n type al x ga 1 - x as ( x : 0 . 24 → 0 ) layer of 300 å having an impurity concentration of 1 × 10 18 cm - 3 . in this case , the value of x is set so as to be decreased from 0 . 24 to 0 upward from its bottom . further on the n type al x ga 1 - x as ( x : 0 . 24 → 0 ) layer , an n type in x ga 1 - x as ( x : 0 → 0 . 5 ) layer is epitaxially grown so that the conduction band in a gap between the emitter and emitter cap can be made smooth together with the n type al x ga 1 - x as ( x : 0 . 24 → 0 ) layer . finally , an n type in x ga 1 - x as ( x = 0 . 5 ) layer of 500 å having an si impurity concentration of 2 × 10 19 cm - 3 is epitaxially grown thereon as the emitter cap layer 106 . in this manner , such an epitaxial wafer as shown in fig3 is obtained . subsequently , the epitaxial wafer thus formed is used so that the substrate 101 is subjected first to an h + ion implantation to form the insulating layer 108 for inter - device isolation therein and to a b + ion implantation to form the insulating layer 107 for inter - device isolation reaching the n + type gaas layer 102 inside the transistor . the semiconductor layer wafer is then subjected to an etching process with use of a predetermined mask to such a depth as reaching the base layer 104 to expose the base , on which a cr / au film is deposited as the base electrode 112 . after this , the semiconductor layer wafer is subjected to a plasma cvd process to form a silicon oxide film 109 on the entire top surface of the wafer . the wafer is subjected to an etching process to such a depth as reaching the n + type gaas layer 102 of the collector contact layer 102 from the top surface of the wafer , on which a thin auge / ni / au layer is formed to provide the collector electrode 111 . next , the wafer is subjected to a window - making process to the emitter , a beer - hall opening process to the collector and base electrodes 111 and 112 , and then subjected to an internal wiring ( not shown ) to the emitter electrode 113 as a ti / pt / au layer . the hbt thus formed ( having dimensions of 2 μm × 5 μm ) had an emitter resistance of 3ω and a current gain of 80 . an ecl circuit using this hbt , when a load resistance was set to be 100 ω to form a ring oscillator , has a delay time τ as very small as 8 psec . in the present embodiment , since the value of x in the material al x ga 1 - x as of the base layer is gradually varied from 0 . 1 to 0 from its emitter side , that is , the base layer has a graded structure , the vnb in the equation ( 2 ) can be set large and therefore the requirements of the heterojunction for the band gap difference can be set loosely . however , in the present embodiment , the band gap difference is strictly set to be 150 mev , taking the band gap narrowing effect into consideration . the impurity concentration and thickness of these semiconductor layers may be suitably modified as necessary . further , it goes without saying that the present invention can be applied also to a reverse transistor . in addition , the present invention may be carried out in various ways within the spirit and scope of the inventions as defined in the appended claims .