the invention is to use a diode arrangement separate from the rectification section supplying power to the chip as sketched in fig1 . fig1 . is a block diagram of a tag antenna 70 , a tag rectification power supply 2 , a tag receiving section 4 , comprising an rf diode 40 and a tag signal capacitor 50 , a tag signal capacitor drain section 6 , and a gain section 80 for producing digital signals from the analog signal voltage vsig produced across signal capacitor 50 by rf diode 40 . optional vsig averaging and compare circuit 7 , protection circuit 8 , and hysteresis circuit 9 are also shown . additional tag electronic components and memory elements are not shown . the main power supply diodes 10 and 20 feed current to the main power supply capacitor 30 in block 2 in the voltage doubling scheme shown in fig2 . while a simple voltage rectification and doubling scheme is shown in the diagram , other full or partial wave rectification schemes as known in the art , and voltage doubling or other - voltage multiplication and addition schemes known in the art of power supplies , could be used as well . the raw power fed to capacitor 30 is conditioned by block 34 which has a voltage protection circuit and which supplies a steady and reliable chip power supply voltage vdd as output to run the tag electronics ( the connections for powering the blocks are not shown ). several other voltage sources needed by the tag electronics may optionally be produced by the power supply 2 . these are shown in fig1 as vpmr and vnmr , and will be explained later . rf diode 40 which is separate from the tag power rectification circuit 2 feeds current to charge signal capacitor 50 . the signal capacitor 50 charges up rapidly when the rf field ( which is amplitude modulated ) changes from the zero to the one state for on - off key signal modulation . ( amplitude modulation schemes where the rf carrier does not drop to zero are anticipated herein , but the examples given are for a 100 % amplitude modulation of the carrier signal . other modulation schemes such as phase and frequency modulation also anticipated .) the voltage vsig which appears across the signal capacitor 50 is used to produce a digital signal . when the base station turns off the rf field in order to modulate the rf signal to send information to the tag , the charge stored in signal capacitor 50 is drained off by the signal capacitor current drain section 6 , which in the embodiment of fig2 comprises a resistor 60 . the signal capacitor 50 does not then further drain current from the capacitor 30 during the time where the rf power is turned off , and the capacitor 30 can power circuits such as a clock circuit for a longer time than if the receiver circuit were draining current . the rc time constant for draining signal capacitor 50 must be short compared to the pulse length of the pulse modulation of the rf . if the rc time constant is long , the waveform recovered from the field modulation will be badly distorted , making it difficult to generate the correct recovered bit pattern on the chip . if the resistor 60 is very large , there is not much current draw to load down the antenna 70 , but the time constant becomes long for a reasonable size signal capacitor 50 . if signal capacitor 50 is too small , it does not act as an rf short , and rf can leak into the gain circuit 80 and perturb the tag electronics with unpredictable results . furthermore , with a small signal capacitor 50 , the circuit is more susceptible to noise and performance values vary strongly with parasitic capacitance changes . vsig is sent to a gain circuit 80 via line 62 where it is turned into the clipped ones and zeros needed for the digital electronics circuits . such methods of turning a modulated analog signal into a digital signal are well known to one skilled in the art . the resimicrosecond time constant and a reasonable size signal capacitor 50 is also very expensive to build on a chip , because large resistors take up a lot of chip area . in addition , the current drain through a resistor will have a strong dependence on vsig . a more preferred embodiment of the invention is a novel circuit sketched in fig3 . in place of the resistor 60 used to drain down the signal capacitor 50 when the rf is shut off , the fet 120 is used . in contrast to the circuit of fig2 , a constant current is drawn through fet 120 independent of the voltage vsig . the magnitude of the current through the n - fet 120 is determined by a voltage vnmr on line 132 . vnmr is derived from a constant current source ( not shown ) in the power supply 2 . because the current is drawn from the signal capacitor 50 both when the rf field is on and when it is off , the amount of current drained by fet 120 must be chosen carefully . the current must be large enough for a quick discharge of signal capacitor 50 when the field turns off , yet small enough that the recharging of the power capacitor 30 is minimally affected when the field turns on . vnmr is produced by a well known technique of mirroring the current in a well known low current reference generator circuit . vnmr is very stable with respect to the circuit ground , and is relatively independent of the ( possibly ) fluctuating voltage vdd produced by the power rectification circuit of the tag . the current through n - fet 120 is thus determined by the current through another n - fet , the determination being made principally by the dimensional relationships of the two fets . the modulated rf power sent to the tag is sketched in fig4 a , and the voltage vdd across the capacitor 30 is sketched in fig4 b . in the sample data pattern shown , data is manchester encoded , meaning that the order of two half bits of different polarity determines the bit value being sent . here , a half - bit 1 followed by a half - bit 0 denotes a 1 while a half - bit 0 followed by a half - bit 1 denotes a 0 . the voltage across resistor 60 is the raw signal voltage vsig which is sketched in fig4 c . fig4 d shows a time expanded sketch of the signal voltage vsig across resistor 60 of fig2 , while fig4 e shows a time expanded sketch of the signal voltage vsig when the n mirror fet 120 of fig3 is used fig4 f is a time expanded sketch of the signal voltage vsig when an optional hysteresis circuit 9 , discussed later , is used with the n mirror controlled fet of fig3 . the voltage vsig is shown in fig4 d as a function of time for a single pulse with expanded time scale for the circuit shown in fig2 . note that the falling edge of the pulse is an exponential with a time constant given by rc , where r is the resistance of resistor 60 and c is the capacitance of signal capacitor 50 . in contrast , the voltage falls linearly with the circuit of fig3 , as sketched in curve 4 e . the time taken for vsig to reach zero is determined by vnmr . the transistor current drain 120 takes up much less space on the chip than a resistor which would give an adequate rc time constant . an additional preferred embodiment of the invention is shown in fig5 . the voltage vsig on signal capacitor 50 is averaged in an innovative way in block 7 over a time which may be comparable or may be short compared to an rf modulation frequency half cycle . the instantaneous voltage vsig is then compared in block 7 to this moving average and when the instantaneous voltage vsig drops to some threshold compared to the moving average , the gain circuit 80 drains the signal capacitor 50 much faster than the transistor current drain current drain 120 can to give a good falling edge to vsig . the gain circuit 80 sends a spike voltage to transistor 590 in block 9 of fig5 . the novel method of taking the average sketched in fig5 is preferred to a standard averaging circuit using a capacitor and a resistor which is well known in the art for the same reasons that the circuit of fig3 is preferrepacitor circuit shown takes less chip area and is more controllable and less variable than the standard capacitor and resistor arrangement for averaging a voltage . the p - mirror set up shown in fig5 uses p - fet 510 and a current defined by vnmr thorough the n - fet 520 to define a voltage vpmr_local , which is defined with respect to vsig . the p mirror circuit shown is well known in the art as a way of defining a voltage with respect to another voltage which is not at ground potential . the averaging capacitor 525 charges and discharges relatively slowly , so that vpmr_local is related to a moving average of vsig . vpmr_local is used to compare the present value of vsig with its moving average in a voltage comparator pull up pull down circuit , where p - fet 540 is controlled by vpmr_local to pass twice the current as transistor 510 in saturation mode , and n - fet 550 is controlled by vnmr to pass the same current as transistor 510 in saturation mode . when vsig is steady , the voltage vpupd is high , since transistor 540 can supply twice the current that transistor 550 needs . however , when vsig drops a by a percentage , preferrably 25 % and more preferably 10 %, voltage vsig minus voltage vpmr_local drops by a very much higher percentage , while vnmr is unchanged with respect to ground , and transistor 540 can not supply the current needed to transistor 550 , so vpupd drops rapidly to a very low value . the voltage vpupd is then used by the gain stage 80 as the signal voltage . an innovative optional protection circuit 8 is also shown in fig5 to protect the signal path electronics 50 , 7 , 80 , and 6 . since the diode 40 rectifying the incoming rf from the antenna 70 is not part of the chip power supply , the voltage vsig may build up to large values if the tag is close to the base station . the signal capacitor 50 would then be at risk unless some means of protecting it such as protection circuit 8 were implemented . protection circuit 8 is innovative in that it requires less current and much less space on the chip than the conventional protection circuits used for the main power section included in block 2 . the voltages developed elsewhere on the chip can be used in a novel fashion to cut down the number of devices needed by the protection circuit . block 2 provides a voltage vdd which powers the chip circuits , and vdd is regulated and limited block 2 also contains a p mirror circuit which provides a voltage vpmr related to vdd and a n - mirror circuit which provides a voltage vnmr related to ground . vpmr controls the gate on the p mirror p - fet 560 . if vsig is less than or equal to vdd , fet 560 demands ¼ the current of 570 ; thus , the voltage on “ shunt ”, the gate voltage of the high current fet 580 , is low and fet 580 is off . if vsig & gt ; vdd , by an amount on the order of tenths of a volt , ( vsig - vpmr ) will be large enough to cause fet 560 to source more current than fet 570 can sink . thus , the gate of the high current fet 580 will be pulled up , turning on fet 580 and acting to pull down vsig , which will provide the desired protection . this protection circuit draws less than 50 na when there is no overvoltage condition . the specific ratio of current demanded by fet 560 versus fet 570 when vsig is less than or equal to vdd is not critical , but is preferably substantially less than 1 . if the ratio is near or above 1 , the shunt may turn on when vsig is less than vdd , draining power from the field into the signal path unnecessarily . an optional feedback circuit is shown as block 9 in fig5 to provide a hysteresis in the signal measuring circuit . when the gain circuit 80 detects a falling edge on vsig , circuit 80 provides a voltage pulse to a high current transistor 590 to short signal capacitor 50 to ground . the transistor 590 preferably can carry vsig in this case is shown in fig4 f . the p - channel transistors 510 , 540 , and 560 of fig5 and 610 and 640 of fig6 may optionally have their n - wells connected to vsig or vdd . there is less noise when the n - wells are connected to vdd . the n - channel transistors of fig5 have their bulk contact connected to ground . fig6 shows an alternative implementation of a moving average circuit where the roles of the p - channel and n - channel devices have been reversed . here , vpmr is used to generate vnmr_local for the moving average generation . while the particular circuits shown in fig5 and 6 are preferred because they are particularly suited to low current operation and use the least number of devices and chip area possible , it is anticipated by the inventors that a number of equivalent circuits are possible which perform the same functions as the circuits shown . in particular , circuits where the roles of the p - channel devices and the n - channel devices are reversed are anticipated .