an input signal according to the present invention is a digital signal converted by an a / d converter preceding a digital receiver . it will be apparent that a prescribed sampling frequency is used to convert an analog signal to the digital signal . a sampling rate for sampling the analog signal is determined by the sampling frequency . if the sampling frequency increases , the sampling rate increases in proportion thereto . in the following description , the above terms will be used without additionally describing the previously stated contents . referring to fig2 a digital receiver according to a preferred embodiment of the present invention includes : adders 216 - 1 , . . . 216 - n , 222 - 1 , . . . , 222 - n , 230 and 232 ; filters 214 - 0 , . . . , 214 - n and 220 - 0 , . . . , 220 - n , down - samplers 212 - 0 , . . . 212 - n and 218 - 0 , . . . , 218 - n , delays 210 - 1 , . . . , 210 - n , and multipliers 224 , 226 and 228 . the down - samplers 212 - 0 , . . . 212 - n and 218 - 0 , . . . , 218 - n receive a discrete time signal x [ n ] having a frequency ( sampling rate ) fs and produce an output signal which occurs at time periods equal to multiples of m , where m is an integer and is chosen so that aliasing can be avoided . although not shown in fig2 the frequency fs denotes a sampling frequency used in an a / d converter connected to an input stage . the filters 214 - 0 , . . . , 214 - n and 220 - 0 , . . . , 220 - n have a polyphase structure of a prototype filter which has a function for multiplying an output of the decimating low pass fir filter 16 ( shown in fig1 ) by a complex gain , including an intermediate frequency of a desired channel . the polyphase structure is described in detail in ieee , vol . 73 , january 1990 , pp . 56 - 93 , “ multirate digital filters , filter banks , polyphase networks , and application ” by vaidyanathan . the delays 210 - 1 , . . . , 210 - n each delay the input signal x [ n ] by one sampling period , respectively . the adders 216 - 1 , . . . 216 - n and 222 - 1 , . . . , 222 - n add two signals , provided either from two filters or from a previous adder and a filter , to each other during each sampling period . for example , the adder 216 - 1 adds signals generated from the filters 214 - 0 and 214 - 1 to each other . the adder 222 - 1 adds signals generated from the filters 220 - 0 and 220 - 1 to each other . the adders 232 and 230 generate a sum signal and a difference signal , respectively , between signals generated from the multipliers 224 and 226 with respect to every sampling period . the other adders each add signals generated from the preceding adder and a corresponding filter to each other . the multiplier 224 generates a signal obtained by multiplying sampling data by e − jwsmn . the multiplier 226 generates a signal obtained by multiplying sampling data by e jwsmn . the delays 210 - 1 , . . . , 210 - n are interconnected to each other so as to sequentially delay the input signal x [ n ] by one sampling period . the down - samplers 212 - 0 , . . . , 212 - n and the filters 214 - 0 , . . . , 214 - n are connected in series pairs to the inputs of the adders 216 - 1 , . . . , 216 - n . down - sampler 212 - 0 and filter 214 - 0 are connected in a pair between an input signal terminal and the adder 216 - 1 . the down - samplers 212 - 1 , . . . , 212 - n and the filters 214 - 1 , . . . , 214 - n are connected in pairs between the outputs of the delays 210 - 1 , . . . , 210 - n and the adders 216 - 1 , . . . , 216 - n . the down - samplers 218 - 0 , . . . , 218 - n , the filters 220 - 0 , . . . , 220 - n , and the adders 221 - 1 , . . . , 222 - n have a symmetric structure with the down - samplers 212 - 0 , . . . , 212 - n , the filters 214 - 0 , . . . , 214 - n , and the adders 216 - 1 , . . . , 216 - n on the basis of the delays 210 - 1 , . . . , 210 - n . that is , both sides are connected to delays 210 - 1 , . . . , 210 - n with similar construction . hereinafter , the down - samplers 212 - 0 , . . . , 212 - n , the filters 214 - 0 , . . . , 214 - n , and the adders 216 - 1 , . . . , 216 - n will be referred to as a first branch ; and the down - samplers 218 - 0 , . . . , 218 - n , the filters 220 - 0 , . . . , 220 - n , and the adders 221 - 1 , . . . , 222 - n will be referred to as a second branch . the output of the adder 216 - n of the first branch is connected to the multiplier 224 , and the output of the adder 222 - n of the second branch is connected to the multiplier 226 . the outputs of the multiplier 224 is connected to an inverting input of adder 230 and a non - inverting input of adder 232 . the output of the multiplier 226 is connected to non - inverting inputs of adders 230 and 232 . the output of the adder 230 is connected to the multiplier 228 . multiplier 228 multiplies the output of multiplier 230 by a complex number to provide a resultant q output signal . the output of adder 232 is a resultant i output signal . in operation , the digital receiver of fig2 differs greatly from the digital receiver of fig1 in receiving the input signal . in the digital receiver of fig1 the input signal which has passed through the a / d converter is multiplied by sinusoidal signals , cos [ ] and sin [ ], and then the resultant signals are transmitted to the next stage . however , in the digital receiver of fig3 a received signal first has a sampling rate lowered by a down rate m of the down - sampler prior to multiplication by sinusoidal signals cos [ ] and sin [ ]. it will be appreciated that with multipliers 224 and 226 situated at the rear of the digital receiver that the sinusoidal signals cos [ ] and sin [ ] are multiplied by an input signal having the rate lowered by the down rate m . note , the down rate m of the down - samplers depends upon the input signal to the receiver and is a common value for all down - samplers in the receiver . the digital receiver of fig2 is operated in two branches . the discrete time signal received from the a / d converter ( x [ n ]) passes through ( m − 1 ) delays 210 - 1 . . . , 210 - n . in this case , the number of delays is less than a value corresponding to the down rate m by 1 , which means that the hardware architecture , i . e . a number of stages of delay , is also input signal dependent because of the dependency of the down rate on the applied input signal . the outputs of the delays 210 - 1 , . . . , 210 - n are convoluted in parallel with m filters 214 - 0 , . . . , 214 - n and 220 - 0 , . . . , 220 - n . the filters 214 - 0 , . . . , 214 - n and 220 - 0 , . . . , 220 - n have a polyphase structure of a filter which has a function for multiplying an output of the fir filter shown in fig1 by a complex gain including an intermediate frequency ws of a desired channel . the outputs of the filters 214 - 0 , . . . , 214 - n and the outputs of the filters 220 - 0 , . . . , 220 - n are all added to each other , and the respective sums are multiplied by the normalized complex gains e − jwsmn and e jwsmn , respectively . the multiplication results are added to each other by adder 232 , thereby obtaining an i component of the desired channel . similarly , in order to obtain a q component , a difference between output signals of both branches is calculated by adder 231 and the difference is multiplied by − j in multiplier 228 , as known from the correlation characteristic of the sinusoidal signals cos [ ] and sin [ ]. the digital receiver of fig1 can be mathematically modeled by the diagram of fig3 . an output signal y [ n ] shown in fig3 can be stated by : y  [ n ] = ∑ r  h ( mn - r ]  _   x  [ r ]  _cos   w s  r ( 2 ) where x [ n ] is an input signal which has passed through the a / d converter , w s is a normalized intermediate frequency of a desired channel , h [ n ] is a system impulse response , and m is a down rate . fig4 illustrates a branch structure of the receiver of the present invention depicted in fig2 . the equivalence in the resulting output signals provided by fig3 and that illustrated in fig4 can be derived from the following equation . the above equation ( 2 ) can be represented by the following equation ( 3 ). that is : y  [ n ] = ∑ r  h  [ mn - r ] · x  [ r ] · (  j   w s  r +  - j   w s  r 2 ) = 1 2   ∑ r  h  [ mn - r ] · x  [ r ] · (  j   w s  ( mn - mn + r ) +  - j   w s  mn - mn + r ) = 1 2   ∑ r  h  [ mn - r ] · x  [ r ] · (  j   w s  r +  - j   w s  r ) y  [ n ] =  1 2    j   w s  mn  ∑ r  h  [ mn - r ] · x  [ r ] ·  - j   w s  ( mn - r ) +  1 2    - j   w s  mn  ∑ r  h  [ mn - r ] · x  [ r ] ·  j   w s  ( mn - r ) ( 3 ) while providing an equivalent signal , the multipliers of fig4 are operated at a low frequency exponential function as compared to that in fig3 . filters 410 a and 410 b can be designated as ½ { h [ n ] e − jwsn } and ½ { h [ n ] e jwsn }, respectively . in the present invention , the filters 410 a and 410 b indicated in fig4 are polyphase filters . down - samplers 412 a and 412 b and the filters 410 a and 410 b are interchanged in position by “ the noble identities ”. for details for “ the noble identities ”, refer to vaidyanathan , “ multirate system and filter banks ” pp . 119 - 122 , englewood cliffs , 1993 . this is illustrated in the digital receiver of fig2 . the z - transform h ws , k ( z ) of the filters 214 - 0 , . . . , 214 - n shown in fig2 is as follows : h ws , k  ( z ) = ∑ n  h ws  ( k + mn )  z - n , 0 ≤ k ≤ m - 1 the z - transform h − ws , k ( z ) of the filters 220 - 0 , . . . , 220 - n shown in fig2 is as follows : h - ws , k  ( z ) = ∑ n  h - ws  ( k + mn )  z - n , 0 ≤ k ≤ m - 1 where h ws , k ( z ) is the z - transform of a polyphase filter of h ws [ n ], and h − ws , k ( z ) is the z - transform of a polyphase filter of h − ws [ n ]. in the digital receiver constructed in accordance with equation ( 3 ) and “ the noble identities ”, the input signal x [ n ] is applied to the filters 214 - 0 and 220 - 0 through the down - samplers 212 - 0 and 218 - 0 . the outputs filtered through the filters 214 - 0 and 220 - 0 by h ws , k ( z ) and h − ws , k ( z ) are supplied to the adders 216 - 1 and 222 - 1 . the input signal x [ n ] is sequentially delayed by the delays 210 - 1 , . . . , 210 - n and is then applied to the down - samplers 212 - 1 , . . . , 212 - n and 218 - 1 - 218 - n in which their sampling rates are down . the outputs of the down - samplers 212 - 1 , . . . , 212 - n and 218 - 1 - 218 - n are filtered through the filters 214 - 1 , . . . , 214 - n and 220 - 1 , . . . , 220 - n . the outputs of the filters 214 - 1 , . . . , 214 - n and 220 - 1 , . . . , 220 - n are supplied to the adders 216 - 1 - 216 - n and 222 - 1 , . . . , 222 - n . the two signals applied to the adders 216 - 1 and 222 - 1 are combined as a sum signal which is applied to the adder of the next stage . the output signals of the adders 216 - n and 222 - n are applied to the multipliers 224 and 226 . these signals are then multiplied by e − jwsmn and e jwsmn , respectively . the outputs of the multipliers 224 and 226 are applied to the adder 230 . the adder 230 generates a difference signal between the outputs of the multipliers 224 and 226 . the output of the adder 230 is applied to the multiplier 228 where it is multiplied by − j , thereby generating a q channel signal . the outputs of the multipliers 224 and 226 are supplied to the adder 232 which generates a sum signal therefrom . the sum signal produced from the adder 232 is the final output signal y [ n ] corresponding to an i channel . as described above , the inventive digital receiver of a polyphase structure reduces the signal rate of an input terminal within the range of a unique characteristic of a signal by using “ the noble identities ”. the digital receiver which can process an input signal at a high processing rate is obtained by a commercially available dsp . since it is possible to process signals in parallel according to a unique characteristic of the polyphase structure , the digital receiver according to the present invention exhibits a faster signal processing rate than that of a conventional digital receiver . therefore , the efficiency of a system is maximized . while the invention has been shown and described with reference to a certain preferred embodiment thereof , it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims .