fig5 a - 5i show the fabrication process of a semiconductor device according to a first embodiment of the present invention . referring to fig5 a , a substrate 70 carries thereon a first - layer conductor pattern 71 of cu with an insulation film ( not illustrated ) interposed between the conductor pattern 71 and the substrate 70 . the interconnection pattern 71 , in turn , is covered by a barrier layer 72 of sin formed by a plasma cvd process with a thickness of about 30 nm . the barrier layer 72 , on the other hand , is covered by an organic sog film 74 formed as a first interlayer insulation film by a spin - coating process with a thickness of about 700 nm , and another insulation film 76 of sio 2 is formed on the first interlayer insulation film 74 by a plasma cvd process with a thickness of about 20 nm . the insulation film 76 may also be formed of an sin film , an sion film or an sic film . further , another organic sog film 78 is formed on the insulation film 76 as a second interlayer insulation film by a spin - coating process with a thickness of about 400 nm , and an etching stopper structure 81 , formed of a stacking of two etching stopper layers , is provided on the second interlayer insulation film 78 . more specifically , the etching stopper structure 81 includes a first etching stopper film 80 of sin formed on the second interlayer insulation film 78 with a thickness of about 20 nm and a second etching stopper film 82 of sio 2 formed on the first etching stopper film 80 with a thickness of about 100 nm . the etching stopper film 80 and the etching stopper film 82 may be formed by a plasma cvd process . after the formation of the etching stopper film 82 , a resist pattern 84 having a resist window 84a corresponding to the interconnection groove to be formed in the organic sog film 78 , is formed on the etching stopper film 82 . alternatively , the etching stopper film 80 may be formed of sion and the etching stopper film 82 may be formed of sio 2 . further , any of sio 2 , sion , sin and sion may be used for the etching stopper film 80 in combination with the etching stopper film 82 of amorphous silicon . further , any of sio 2 , sion , sin and sion may be used for the etching stopper film 80 in combination with the etching stopper film 82 of tin . further , in any of the foregoing examples , it is possible to form the etching stopper film 80 as a stacking of an sio 2 film and an sic film . the etching stopper films 80 and 82 are preferably formed by a plasma cvd process , although other suitable process may also be used for this purpose . next , in the step of fig5 b , the etching stopper film 82 is subjected to a dry etching process conducted in an etching gas of cf 4 and ar while using the resist pattern 84 as a mask , and the resist pattern 84 is removed subsequently by an asking process . as a result of the foregoing patterning of the etching stopper film 82 , there is formed an opening 82a in the etching stopper film 82 in correspondence to the resist window 84a , wherein the foregoing opening 82a exposes the etching stopper film 80 underlying the etching stopper film 82 . in the step of fig5 b , another resist pattern 86 having a resist window 86a corresponding to the contact hole to be formed in the organic sog film 74 , is formed , after the removal of the resist pattern 84 , on the etching stopper film 82 so as to cover the part of the etching stopper film 80 exposed by the opening 82a , such that the resist window 86a is formed inside the opening 82a . in the foregoing process of forming the resist pattern 86 , it is necessary to align the exposure mask within the precision of several microns or less in order to ensure that the resist window 86a is formed inside the foregoing opening 82a , while the alignment of the exposure mask with such a precision is generally difficult . thus , there is a substantial possibility that the resist window 86a is located outside the opening 82a as represented in fig5 c . when the position of the resist opening 86a is offset to the region outside the opening 82a as represented in fig5 c , it is necessary to remove the resist pattern 86 and re - form the resist pattern 86 again , wherein the removal of the resist pattern 86 is typically conducted by an asking process . in the present embodiment , it should be noted that such a removal of the resist pattern 86 is conducted without problem as the organic sog film 78 is protected by the etching stopper film 80 , and the problem pertinent to the conventional multilayer interconnection structure , which uses the organic interlayer insulation film , in that a part of the organic interlayer insulation film such as the organic sog film 78 or 74 is removed together with the resist pattern 86 , is effectively avoided . next , in the step of fig5 d , the etching stopper film 80 is subjected to a patterning process while using the resist pattern 86 of fig5 b as a mask , followed by a dry etching process of the underlying organic sog film 78 while using a mixture of o 2 and n 2 as an etching gas , to form an opening 93 in the organic sog film 78 . after the formation of the opening 93 , the resist pattern 86 is removed by an asking process . next , in the step of fig5 e , the etching stopper film 80 thus exposed by the opening 82a is removed by a dry etching process conducted by a mixture of cf 4 and ar while using the etching stopper film 82 as a mask , wherein the dry etching process removes simultaneously the sin film 76 exposed at the bottom of the opening 93 . it should be noted that the etching stopper film 82 has been formed with a thickness of typically about 100 nm such that the film 82 remains during the dry etching process . next , in the step of fig5 f , the second organic sog film 78 and the first organic sog film 74 are patterned by a dry etching process conducted in an etching gas mixture of o 2 and n 2 while using the remaining etching stopper film 82 as a mask , to form an interconnection groove 91 and a contact hole 89 simultaneously . in this patterning process , it should be noted that the sio 2 film 76 exposed at the bottom of the interconnection groove 91 functions as a hard mask during the etching process of forming the contact hole 89 . next , in the step of fig5 g , the barrier layer 72 exposed at the bottom of the contact hole 89 is removed by a dry etching process conducted by using a mixture of cf 4 and ar as an etching gas , followed by the step of fig5 h in which a cu layer 83 is deposited on the structure of fig5 g by a cvd process so as to fill the contact hole 89 and the interconnection groove 91 . further , the cu layer 83 is subjected to a cmp process in the step of fig5 i for removing the cu layer 83 for the part locating above the etching stopper film 82 , and a cu pattern is obtained such that the cu pattern fills the interconnection groove 91 and the contact hole 89 . according to the present embodiment , it is possible , in the process of forming an interconnection groove and a contact hole in a layered structure including organic sog films by a dual damascene process , to remove the resist pattern 86 when the resist pattern 86 is defective , by covering the organic sog film by the etching stopper films 80 and 82 . thereby , the yield of production of the semiconductor device is improved substantially . in the present embodiment , it is also possible to use a low - dielectric insulation film such as f - doped sio 2 for the lower interlayer insulation film 74 . further , the etching stopper structure 81 may include three or more layers of sio 2 , sin or sic . in the step of fig5 h , it should be noted that the deposition of the cu layer 83 is possible also by an electroplating process . in this case , a thin cu film is deposited by a sputtering process so as to cover the inner surface of the contact hole 89 and the interconnection groove 91 and cause a growth of the cu layer 83 in an electrolytic solution while using the thin cu film as an electrode . next , the fabrication process of a semiconductor device according to a second embodiment of the present invention will be described with reference to fig6 a and 6b , wherein those parts of fig6 a and 6b corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted . referring to fig6 a , it can be seen that the resist pattern 86 is intentionally is placed with respect to the opening 82a such that the resist window 86a includes an edge part of the opening 82a formed in the etching stopper film 82 . thereby , the size of the contact hole 89 formed as a result of the etching process of fig6 b is reduced as compared with the size of the resist window 86a . it should be noted that such a displacement of the resist pattern 86 for forming extremely minute contact holes raises the problem of the contact hole may not be resolved when there is a minute error in the position of the resist pattern 86 , as explained with reference to fig3 a and 3b . even in such a case , the present embodiment allows a free removal of the defective resist pattern 86 and a re - formation . thus , the problem of decrease of production yield of the semiconductor device is successfully avoided . in any of the foregoing embodiments , it is also possible to use an amorphous fluorocarbon film having a formula ## str1 ## for the interlayer insulation films 74 and 78 in place of the organic sog described previously . it should be noted that such an amorphous fluorocarbon film has a dielectric constant of typically 2 . 4 - 2 . 7 and can be formed by a cvd process . further , the present invention is not limited to the embodiments described heretofore , but various variations and modifications may be made without departing from the scope of the invention .