the present method is an improvement upon the semi - additive techniques for production of printed circuits . as such the invention addresses many of the concerns and problems experienced by past techniques through the use of a specific processing sequence . the present invention proposes the following basic cycle for the production of double - sided and multilayer printed circuit boards : 3 . create circuitry on outer surfaces of copper clad laminate or multilayer package ; 5 . optionally , strip print and etch resist applied in step ( 2 ); * note : copper clad laminate and multilayer package are used herein and in the claims interchangeably . the first step calls for holes to be drilled or punched in the copper clad laminate . thus holes will penetrate through the entire board . vias may penetrate through one side of the board into the interior of the board but not through to the other side . the second step is optional , but recommended , and involves deburring the holes . deburring is typically a mechanical process whereby any burrs left on the holes from the drilling process are removed . the fact that the process of this invention does not utilize a &# 34 ; desense mask &# 34 ; as disclosed in knopp , allows the advantageous flexibility of deburring at this point . the third step calls for the formation of circuitry on the outer surfaces of the copper clad laminate . typically this is accomplished by applying print and etch resist in an image - wise fashion to the outer surfaces of the copper clad laminate . most notably , dry film resists are applied , exposed and developed to create a positive image of the desired circuitry on the outer surfaces . the exposed copper surfaces are then etched away causing the resist covered circuitry to stand out in vertical relief . next , the holes are activated to accept plating . activation of the holes can range in complexity from a single dip in a previous metal activator ( or other non - precious metal activates known in the art ) to a full desmear ( or etch bath ), plated through - hole cycle involving numerous steps . optionally , if desmear is desired , the desmear portion of the activation cycle may be separated from the activation cycle and inserted between step 2 ( optional deburr ) and step 3 ( creation of circuitry ) of the overall process of this invention . desmear generally consists of hole condition , dielectric etch , neutralization and optional glass etch . the most complex hole activation cycle might consist of hole condition ( m - pyrol ), potassium permanganate desmear , neutralization ( acid / reducer ), glass etch ( ammonium bifluoride ), ( the foregoing steps comprising desmear ) conditioner ( surfactant or other type ), microetch , activator ( pdci 2 / sncl 2 colloid ) and accelerator . clean water rinses are interposed between each chemical treatment . various combinations will be apparent to those skilled in the art . regardless of which hole activation cycle is chosen , its primary purpose is to treat the holes so that the hole surfaces will initiate plating . a wide variety of methods for achieving this are known in the art , any of which may be advantageously be utilized here . please refer to u . s . pat . nos . 5 , 032 , 427 ( kukanskis et al . ), u . s . pat . no . 4 , 976 , 990 ( back et al . ), u . s . pat . no . 4 , 608 , 275 ( kukanskis et al .) and u . s . pat . no . 4 , 863 , 758 ( rhodenizer ), the teachings all of which are incorporated herein by reference in their entirety . next , the print and etch resist which was applied in the second step is stripped off the surfaces of the copper clad laminate . typically an alkaline or solvent based solution is used to strip the resist . preferably the stripping action does not affect the activation in the holes . in this regard a mildly alkaline stripping solution is advantageous . in another embodiment of this invention the print and etch resist is not stripped at this point but is left in place on the board and stripped later in the process in the same step where the plating mask is stripped . at this point , the outer surfaces of the double - sided or multilayer circuitry are coated with a plating mask . the plating mask can be applied in several ways including dry film lamination , roller coating , curtin coating , screening , or various similar techniques . the most important aspect here is for the plating mask to cover all surfaces which are not to be plated . it must be particularly noted that since the print and etch resist was exposed to activation , the print and etch resist must either be stripped or covered with the plating mask to avoid plating on such resist . generally the plating mask is imaged so that the areas to be subsequently plated are not covered and the plating mask covers all other areas of the surface . the plating mask can be imaged in various ways including screening , photoimaging followed by development , or similar techniques . finally the plating mask is cured either by application of heat , photoradiation or both . compositions and methods of application of plating masks are well known in the art . it has been found most advantageous to apply the plating mask such that it covers substantially all of the exterior areas of the board except for the holes . this allows for plating in the holes only , and thus reduces the amount of plating chemicals required . heretofore prior art had taught the necessity of plating the holes as well as the surface features of printed circuit boards . note that if any print and etch resist is showing after application of the plating mask it may easily be removed at this point , particularly if the print and etch resist chosen has different solubility or stripping characteristics than the plating mask . after this it is optionally advantageous to clean the exposed copper surfaces , particularly exposed copper surfaces in and around the holes . this is advantageously performed with typical alkaline or acid based cleaning compositions widely used in the industry . preferably the cleaning operation will not affect the activation in the holes . the next step is to initiate plating in the holes and possibly upon the areas of connection and / or circuits ( depending upon the image of the plating mask ). this initiation can occur in several ways . one preferred example is through the application of electroless copper . another is through the application of electroless nickel . either of these solutions will initiate plating upon the activated areas only . thus , only the holes and other areas not covered by the plating mask will be plated . it has been discovered that initiation of plating can be made directly through the use of electroless nickel phosphorous in this case . this is possible because the surface features have been etched on the surface prior to this stage . if electroless nickel - phosphorous is used it is preferable to continue to build the entire required thickness with the electroless nickel - phosphorous solution . it is most advantageous to utilize a &# 34 ; high phosphorous &# 34 ; nickel - phosphorous bath which deposits nickel with 10 % or greater phosphorous content . the next step could be a continuation of the previous step , or , it could be a separate step as indicated on the former sequence . the object of this step is to plate the holes and other uncovered areas to the appropriate metal thickness . thus , if an appropriate electroless copper is used in the previous step , the board could be left in the electroless copper for an extended time to build the appropriate thickness of copper . one preferred method , however is to initiate plating in the previous step with electroless copper ( 10 to 150 microinches of copper ) and then to follow that initiation with either electroless nickel phosphorous preferably , ( with prior activation of the copper ) or a strike of electroless nickel - boron followed by electroless nickel - phosphorous . it is more preferable , however to accomplish all of the plating in a single electroless nickel , preferably electroless nickel - phosphorous , plating step . after metalization of the desired surfaces the plating mask can now be stripped away . in addition , if the print and etch resist was not previously stripped it should now be stripped along with the plating mask . typically an alkaline or solvent based solution will be used to strip the resist and the mask . the next step is to , optionally , remove any residual catalyst from the surfaces of the board . this step may be desired , depending upon the activation cycle used , in order to improve or restore the surface insulation resistance of the board . typical methods of performing these optional operations are described in u . s . pat . nos . 5 , 221 , 418 ; 5 , 207 , 867 ; and 4 , 978 , 422 , the teachings each of which are incorporated herein by reference . the final step is optional , but recommended . this step consists of applying some form of final finish to the holes and other areas of connection . these final finishes have as their objective , the protection and / or enhancement of the solderability of these surfaces . a final finish may take one of many forms . it may consist of an organic treatment which preserves and enhances the solderability of these surfaces , such as is described in u . s . pat . no . 5 , 362 , 334 ( adams et al .) the teachings of which are incorporated herein by reference in their entirety . alternatively or in addition , it may consist of a series of metallic treatments , possibly culminating in a precious metal coating as described in u . s . pat . nos . 5 , 235 , 139 , the teachings of which are incorporated herein by reference in their entirety . the final finish step ( 9 ) can consist of any one of several variations , including the following : 9 ( a ) plate final finish metal coating or coatings ( typically palladium , copper or gold over nickel ) onto all surfaces not covered by the plating mask . 9 ( b ) apply solder mask to selected areas of the surfaces of the copper clad laminate , typically all areas other than areas of connection ( ie . holes , pads , lands etc .) 9 ( c ) apply final finish metal coating or coatings ( typically palladium , copper or gold over nickel ) onto all surfaces not covered by the solder mask . typical solder masks and processes for their use are described in u . s . pat . no . 5 , 296 , 334 , the teachings of which are incorporated by reference herein in their entirety . one typical final finish is described in u . s . pat . no . 5 , 235 , 139 , the teachings of which are incorporated herein by reference in their entirety . one typical organic solderability preservative is described in u . s . pat . no . 5 , 362 , 334 the teachings of which are incorporated herein by reference in their entirety . various additional steps may be inserted between the steps of the proposed process sequence . in addition , substitutions may also be made . these insertions or substitutions may be such as would be obvious to one skilled in the art . in addition please note that it is recommended that fresh water rinses be included between chemical treatment steps unless specifically noted otherwise . this invention is further described in the following examples which are given for illustrative purposes only , and are in no way limiting . a printed circuit board was fabricated in the following manner according to the teachings of this invention : 2 . a dry film print and etch resist was laminated onto both surfaces of a sized piece of copper clad laminate ( board ). the film was then exposed to u . v . radiation in an imagewise manner . the unexposed areas of the resist were then developed off the surfaces using a solution of 1 % potassium carbonate . the copper clad laminate was then subjected to an ammoniacal copper etchant , thereby etching away the exposed copper and causing the circuits and other desired surface features to stand out in vertical relief . 3 . the holes were activated to accept and initiate plating on their surface by subjecting the boards to the following treatments : a . cleaner / conditioner ( macdermid 9420 ) for 4 minutes at 110 ° f . by immersion therein . b . activation ( macdermid mactivate 10 ) for 4 minutes at 110 ° f . by immersion therein . 4 . the print and etch resist applied in step ( 2 ) above was then stripped in a 10 % caustic solution . 5 . macumask 9251 plating mask was then screened onto the surfaces of the board in an imagewise manner , then cured by baking at 320 ° f . for 15 minutes . 6 . the exposed copper surfaces were cleaned in macdermid 9271 cleaner at 115 ° f . for 4 minutes . 7 . the holes and other exposed copper areas , were plated using macdermid 101 high phosphorous electroless nickel plating solution to a thickness of approximately 1 . 0 mil . 8 . a final finish was applied using the following process sequence : a . electroless gold was then plated in the holes and any other exposed nickel surface . b . the plating mask was stripped using stripper 10067 solution at 95 ° f . for 4 minutes . a printed circuit board was fabricated in the same manner as in example 1 , except that after step 7 was replaced by the following : a . the plating was initiated by immersing the boards in macdermid electroless nickel - boron for three minutes at 115 ° f . to plate approximately one to three microinches of nickel - boron . b . the boards were then immersed in macdermid high phosphorous electroless nickel for 120 minutes at 190 ° f . to plate approximately 1 . 0 mil of nickel - phosphorous . a printed circuit board was fabricated in the same manner as in example i , except that the board was a multilayer printed circuit board and therefore the board was subjected to the following treatments directly before step 3 ( a ): b ). potassium permanganate ( macdermid 9275 ), 60 gr / l , 10 minutes , 160 ° f . * note . fresh water rinses are interposed between each chemical treatment step . a printed circuit board was fabricated in the same manner as in example i , except that step 8 was as follows : 8 ( a ) stripped plating mask in stripper 10067 solution at 95 ° f . for 4 minutes . 8 ( c ) plated electroless gold using macdermid planar electroless gold onto all surfaces not covered by the solder mask . a printed circuit board was fabricated in the same manner as in example 1 , except that step 8 was as follows : 8 ( a .) electroless copper was then plated in the holes and on any other exposed nickel surface using macdermid 9048 electroless copper 8 ( d .) applied organic solderability protectant to the final surface of the printed circuit board using macdermid m - coat +. a printed circuit board was fabricated in the same way as example i , except that step 4 was eliminated and the print and etch resist was stripped off in step 8 ( b ) along with the plating mask . the printed circuit boards in all the above examples were tested in a variety of ways including standard solder shock tests , conductivity tests , cross section tests , and various functional testing . the results of all testing revealed that all of the printed circuit boards produced , functioned acceptably , for the purposes intended . as can be seen from the current specification , the proposed process has many advantages over the prior art processes . one of the most important advantages is that it provides an efficient method of producing printed circuit boards which substantially reduces the number of required steps and processes required . in addition , the proposed process provides a workable semi - additive approach to producing printed circuit boards .