referring to fig1 there is shown a bit switch according to the prior art . a first differential pair comprises emitter coupled pnp transistors 4 and 6 . the base of transistor 4 is coupled to input terminal 8 , and the base of transistor 6 receives a reference voltage at terminal 10 . if the bit switch is to be ttl compatible , the reference voltage would be approximately 1 . 4 volts . the emitters of transistors 4 and 6 receive a current i 1 from current source 2 . a second differential pair comprises npn emitter coupled transistors 14 and 16 . the base of transistor 14 is coupled to the collector of transistor 4 , and the base of transistor 16 is coupled to the collector of transistor 6 . the collector of transistor 14 is coupled to an output bus 12 , and the collector of transistor 16 is coupled to ground ( or , if desired , to a second output bus ). the emitters of transistors 14 and 16 are coupled to current source 22 which supplies a binary scaled bit current ( i bit ). resistors 18 and 20 are coupled between a source of supply voltage v a and the bases of transistors 14 and 16 respectively . the amount of current supplied by source 2 ( i 1 ) need only be large enough to supply a voltage drop across resistors 18 and 20 sufficient to cause differential pair 14 and 16 to switch . the circuit of fig1 is configured so as to apply the bit current i bit to output bus 12 when a logical 0 is applied to input terminal 8 . that is , with a logical 0 at its base , transistor 4 is turned on causing a voltage to appear at the base of transistor 14 equivalent to v a plus the voltage drop in resistor 18 caused by current i 1 . this turns transistor 14 on , thus providing a path for the bit current to the output bus 12 . on the other hand , with a logical 1 applied to its base , transistor 4 is off . current i 1 will flow through transistor 6 producing a base voltage at transistor 16 which turns transistor 16 on . in this case , the bit current has a completed path to ground . a problem with this circuit appears when a high speed transition occurs at input terminal 8 . input pnp transistor 4 is very slow and exhibits a high parasitic capacitance . additionally , parasitic capacitance appears at the emitters of transistors 14 and 16 . when , for example , the input at terminal 8 quickly changes from a low to a high state , the voltage at the base of transistor 14 should fall and the voltage at the base of transistor 16 should rise . however , a momentary capacitive glitch through the parasitic capacitance of transistor 4 will cause the voltage at the base of transistor 14 to rise . the voltage at the base of transistor 16 , however , remains stable . therefore , the voltages at the bases of transistor 14 and 16 are not symmetrical . this will cause the voltage at the common emitters of transistors 14 and 16 to vary , and due to the relatively low bit current ( e . g . on the order of 1 microamp ) a substantial amount of time ( e . g . 1 microsecond ) will be necessary to discharge the parasitic capacitance and stabilize the voltage at the emitters of transistors 14 and 16 . the inventive circuit shown in fig2 enables the voltage at the common emitters of transistors 14 and 16 to be maintained relatively constant . the two differential pairs which appear in the prior art circuit of fig1 also appear in the inventive circuit shown as fig2 . these comprise pnp transistors 4 and 6 and npn transistors 14 and 16 . resistors 26 and 28 in fig2 function in the same manner as do resistors 18 and 20 in fig1 . the circuit of fig2 however , includes an additional differential pair comprised of npn transistors 30 and 32 coupled in a common emitter configuration . the bases of transistors 30 and 32 are coupled to the collectors of transistors 4 and 6 respectively and to v a ( approximately 1 . 4 volts above v ee ) via resistors 26 and 28 . the collector of transistor 30 is coupled to the base of transistor 14 and to a supply voltage v b ( approximately 8 volts above vee ) via resistor 18 . similarly , the collector of transistor 32 is coupled to the base of transistor 16 and to supply line 24 ( v b ) via resistor 20 . an additional current source 34 ( i 2 ) is coupled to the emitters of transistors 30 and 32 . resistors 18 and 20 may typically have a value of 5 k ohms and current sources 2 and 34 generate currents i 1 and i 2 of , for example , 50 - 200 microamps . as should be obvious , the glitch which appeared at the base of transistor 14 in fig1 as a result of the parasitic capacitance will also appear at the base of transistor 30 . however , due to the buffering by transistors 30 and 32 between the input differential pair and the bit current switching differential pair , it is no longer necessary to discharge parasitic capacitance at the emitters of transistors 14 and 16 and there will be an immediate response by transistor 14 to the base drive produced at the collector of transistor 30 . furthermore , since i 2 is substantially greater than the bit current at the lower end of the ladder network , any parasitic capacitance at the common emitters of transistors 30 and 32 will be quickly discharged . thus , the inventive dac bit switch eliminates a substantial amount of the common mode signal coming from the pnp input differential stage . therefore , the emitters of transistors 14 and 16 remain at a relatively constant voltage requiring little time to settle out . the above description of a preferred embodiment is given by way of example only . changes in the form and details may be made by one skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims .