fig3 shows a floorplan of a chip layout . as usual , series of pads 11 are arranged at the periphery of the chip 2 ′. vss and vdd wiring 12 a , 12 b extends over the chip 2 ′ from one side to the other . a switchable power ring 13 having three power / ground wires ( i . e . one more than the standard power ring ) is provided on the chip 2 ′. vss wires are denoted by the suffix a and vdd wires are denoted by the suffix b . in addition to vss wire 13 a and vdd wire 13 b , the power ring 13 has a switched vss wire 14 . a hierarchical entity or block is enclosed by the switchable power ring 13 . the hierarchical entity comprises one or more functional modules 15 . 1 , 15 . 2 , 15 . 3 , 15 . 4 electrically connected to vdd wire 13 b and switched vss wire 14 . the functional modules 15 . 1 , . . . , 15 . 4 are embedded on - chip modules of the integrated circuit 2 ′ or soc design , for instance memories , logic , controllers , processor cores , interfaces , etc . further , the switchable power ring 13 encloses a logic module 16 . as any component situated within the switchable power ring 13 , the logic module 16 is also powered by vdd wire 13 b and switched vss wire 14 . an enable signal pwr_ctrl 17 ( cf . fig4 ) is provided for activating / deactivating the embedded switchable power ring 13 . in the activated state , the switched vss wire 14 is connected to vss wire 13 a , in deactivated state , the switched vss wire 14 is cut - off from vss wire 13 a . the enable signal pwr_ctrl 17 has to be generated by some part of the chip where the power is always on , i . e . some part outside the power ring 13 . the integrated circuit 2 ′ may comprise further functional modules 18 . 1 , 18 . 2 and 18 . 3 , which are external to the embedded switchable power ring 13 . these functional modules 18 . 1 , 18 . 2 , 18 . 3 are connected to vss wire 12 a and vdd wire 12 b . it is to be noted that switched wire 14 may also support switched vdd instead of switched vss as shown in fig3 . in this case wires 12 a and 13 a are vdd wires and wires 12 b and 13 b are vss wires . fig4 illustrates two basic building blocks of the embedded switchable power ring 13 , namely the switch control sub - block 20 and the switch power sub - block 30 . the switch control sub - block 20 consists of driver 21 , inverter 22 , fets 23 and an or - gate with one inverted input 24 . the switch power sub - blocks 30 have a driver 31 and a fet 32 , the gate thereof is controlled by the driver 31 output . depending on the voltage level of a switch power control signal 25 as output by the switch control sub - block 20 , the fet 32 of switch power sub - block 30 is gated or conductive . if fet 32 is gated , the embedded switchable power ring is switched off . otherwise , in the conductive state , the embedded switchable power ring 13 is switched on . the switch control sub - block 20 and one switch power sub - block 30 , in combination , contain the circuitry of a conventional romswitch 7 . 1 , 7 . 2 . starting from such conventional romswitch , the idea of the invention is to separate such romswitch in the switch control sub - block 20 and in the switch power sub - block 30 , to provide for a plurality of switch power sub - blocks 30 and to use this plurality of switch power sub - blocks 30 as building blocks of a power ring as depicted in fig3 . it is to be noted that driver 31 routes the control signal 25 from one switch power sub - block 30 to the next switch power sub - block 30 . multiple switch power sub - blocks 30 are needed to provide enough current to the components 15 . 1 , . . . , 15 . 4 , 16 encircled by the power ring 13 . fig5 illustrates an implementation example of the embedded switchable power ring 13 . identical or similar parts are denoted by the same reference signs as used in the previous figures . from fig5 , it can be seen that the switch power sub - blocks 30 illustrated as rectangles are arranged in direct abutment to one another without any separation in between . further , in this example , the one switch control sub - block 20 is integrated in the embedded power ring 13 . in relation to the known concept of romswitches , this means that the sub - blocks 20 and 30 have to be redesigned in a way that makes it possible to abut as many sub - blocks 20 , 30 as needed , cf . fig5 . the power ring 13 is then created by abutting these sub - blocks 20 , 30 , 30 , . . . , 30 or 30 , 30 , . . . , 30 . the switch control sub - block 20 is controlled by the external enable signal 17 ( pwr_ctrl ). of course , the design shown in fig5 is flexible and the invention also covers cases in which one or more switch power sub - blocks 30 are replaced by a triple wire connection . fig6 illustrates the layout of the switchable power ring 13 architecture in more detail . there are shown two sub - blocks , either switch control sub - block 20 and switch power sub - block 30 or two switch power sub - blocks 30 . it is apparent from fig6 that the connectors ( pins ) 13 a ( vss ), 13 b ( vdd ) and 14 ( here switched vdd ) are aligned to one another and are in direct electrical contact . fig7 illustrates the implementation of the embedded switchable power ring 13 in metal 2 and metal 3 of a chip layout . it appears that the ring wiring of the power ring 13 is generated in metal 2 for horizontal wiring and in metal 3 for vertical wiring . power ring - internal pins are established in metal 3 for pin series orientated in vertical direction and are generated in metal 4 for pin series orientated in horizontal direction . signal routing into or out of the power ring 13 is performed by exemplary wires 33 , 34 connected to the internal pins . it is desired to use as lower metal layers as possible for the wiring of the switchable power ring 13 in order to maintain high pin accessibility to the circuit modules 15 . 1 , . . . , 15 . 5 surrounded by the embedded switchable power ring 13 . this ensures that the power ring 13 blocks only these lower metal layers and that the higher metal layers can be used for routing signals over the power ring 13 by wires 33 , 34 . therefore , metal 2 and metal 3 ( i . e . the second and third lowest metal layers of the metal layer design of the chip 2 ′) are preferred for implementing the power ring 13 . one of the most important advantages of the invention is the fact that powering down of any design part or components of the chip 2 ′ can be implemented internally . this increases the granularity of the components that can be powered down within the integrated circuit . thus , no extra power pads will be needed and the power control strategy will become easier and faster as there is no need to interface to another chip . the power - on can be done smoothly to avoid any current pick - up and chip voltage drop that could have timing impacts on other working parts of the design . a plurality of embedded switched power ring 13 ( probably using different supply voltages ) may be arranged on one chip 2 ′. in this case , it is preferred that the various enable signals 17 for each ring 13 are generated in a power control unit situated in a chip domain that is always on , usually called standby . computational design flow tools are widely used for designing the layout of semiconductor devices . fig8 is a schematic block diagram of a computer system adapted for design flow calculations . briefly , the computer system comprises a processor 40 , an input device 41 , a display 42 , a first memory 43 , a second memory 44 and a third memory 45 . the input device 41 , the display 42 and the memories 43 to 45 are connected to the processor 40 . program data 43 a of the computer program for design flow development of integrated circuits is stored in memory 43 . a cell library 44 a containing technology data of the cells to be used in the design flow development process are stored in memory 44 . layout data ( i . e . processed data ) 45 a calculated by the processor 40 is stored in memory 45 . the cell library 44 a may be a conventional state - of - the - art cell library , except that two additional cells are contained : the first additional cell is data defining the switch control sub - block 20 as depicted in fig4 . the second additional cell is data defining the switch power sub - block 30 also depicted in fig4 . the computer system of fig8 executes the ( simplified ) flowchart of fig9 . in a first design step s 1 , the desired functionality of the integrated circuit 2 ′ or soc is described using a hardware description language , in most cases vhdl . this design level is called rtl ( register transfer level ). in complex soc systems , step s 1 comprises the generation of all modules ( memories , processor cores , bus and peripheral components , etc .) of the integrated circuit or soc . in step s 2 , system integration and synthesis is done . the cell coordinates and connectivity netlists for top - level integration are extracted and the netlist is synthesized . the netlist describes the logical cells contained in the integrated circuit to be designed and the cell connections . steps s 1 and s 2 are well - known in the state - of - the - art . in step s 3 , arranging and wiring ( so - called “ place and route ”) of the cells is done . the pad ring 5 is created and the power nets of the integrated circuit are routed . in this step , the cells switch control 20 and switch power 30 are arranged to establish one or more embedded switchable power rings 13 as illustrated in fig5 to 7 . thus , it is not necessary to place spacer cells between switch control cells 20 and switch power cells 30 and / or switch power cells 30 and adjacent switch power cells 30 . the embedded switchable power ring 13 may be placed and routed by using algorithms which already exist to place pad rings in the design . then , level shifters and isolation clamp cells at domain boundaries as well as the remaining standard cells are placed and routed . after completing global routing in step s 3 , timing analysis ( step s 4 ) is performed in order to calculate the optimised netlist s 5 . steps s 4 and s 5 may be performed by any appropriate timing analysis tool known in the state - of - the - art .