in the present invention , the problem described with reference to fig1 ( b ) is solved by optimizing the construction of the precharge signal generator portion shown in fig9 such that a normal read of the memory cell content is possible even when the power source voltage is lowered . this optimization can be realized by making an absolute value of the threshold voltage of the transistor constituting the inverter of the prior art precharge signal generator portion small . however , with such circuit construction , the problem described with reference to fig1 ( c ) occurs . therefore , according to the present invention , the problem shown in fig1 ( b ) is solved by optimizing the construction of the precharge signal generator as mentioned , while solving the problem related to fig1 ( c ) by providing a plurality of second precharge circuits in parallel to the precharge circuits of the prior art semiconductor memory device . now , the present invention will be described in detail with reference to the drawings . a basic construction of a semiconductor memory device according to the present invention is similar to that shown in fig7 . that is , the semiconductor memory device is constructed with a memory cell array portion 701 and a peripheral circuit portion 702 . the peripheral circuit portion 702 includes an x decoder 703 inputted with an x address , a y decoder 704 inputted with a y address , a data latch circuit 706 for reading out a memory data from a memory cell specified by the x and y addresses and a timing generator circuit 705 inputted with an external clock signal for generating an internal clock signal including a precharge signal and a sampling clock signal . as shown in fig1 which shows a first embodiment of the present invention , the memory cell array portion 701 includes a number of memory cells arranged in a column and row matrix and a number of bit lines ( bl1 to bln ) are arranged in respective columns of the memory cells . a plurality of sub bit lines subbl each including a plurality of cell transistor groups each including a selection transistor s and four cell transistors m1 to m4 , all of which are connected in series , are nor - connected to each bit line bl . in order to select one of the memory cells related to each bit line , a corresponding selection transistor s is turned on , a corresponding word line wl is made active (&# 34 ; l &# 34 ;) and other word lines wl are made inactive (&# 34 ; h &# 34 ;). when a content of the thus selected memory cell is &# 34 ; 1 &# 34 ; ( off ), the potential of the bit line becomes &# 34 ; h &# 34 ; at the sampling time point and , when it is &# 34 ; 0 &# 34 ; ( on ), the bit line potential becomes &# 34 ; l &# 34 ; at the sampling time point . the data latch circuit portion 706 is constructed with precharge transistors q1 to qn , sense amplifiers sa1 to san , latch circuits l1 to ln and p type transistors p1 to pn and n type transistors n1 to nn , all of which are arranged for the respective bit lines bl1 to bln . the p type transistors p1 to pn and the n type transistors n1 to nn constitute second precharge circuit portions , respectively . in reading out the data from the selected memory cell , the data latch circuit portion 706 charges the bit lines through the precharge transistors ( q1 to qn ) when the precharge signal / pr is in an active state . since the reference voltage vref is applied to the gates of the precharge transistors ( q1 to qn ), each bit line is charged up to a voltage obtained by subtracting the threshold voltage of the precharge transistor from the reference voltage vref . since , in this embodiment , the threshold voltage vth is 0 v , potentials of the bit lines becomes vref . the sense amplifiers ( sa1 to san ) detect voltage change of the bit lines at the sampling time and output &# 34 ; h &# 34 ; or &# 34 ; l &# 34 ;. that is , when the potential of the bit line is larger than the threshold voltage vth which is a half of the reference voltage vref , the sense amplifier outputs &# 34 ; h &# 34 ; data and , when it is smaller than the threshold voltage vth , the sense amplifier outputs &# 34 ; l &# 34 ; data . an operation of the first embodiment will be described with reference to fig1 and fig2 which shows a signal timing chart . when the precharge signal / pr becomes &# 34 ; l &# 34 ;, the p type transistors ( p1 to pn ) are turned on . the n type transistors ( n1 to nn ) having the gates applied with the reference voltage vref are also turned on . therefore , in addition to the charging by the sense amplifiers ( sa1 to san ) and the n type transistors ( q1 to qn ) which constitute the first precharge circuit , a charging by the second precharge circuit is started , so that the potential of the bit lines is increased up to a potential vref - vth , where vth is the threshold voltage of the n type transistor . since the threshold voltage vth is 0 v in this case , the bit line potential is increased up to vref . in response to the rising edge of the precharge signal / pr , a word line corresponding to the address is selected and , when the information stored in the selected memory cell is &# 34 ; 0 &# 34 ;, the charge of that bit line is discharged and , when the information is &# 34 ; 1 &# 34 ;, the charge of the bit line is not discharged . in the example shown in fig2 the information stored in the selected memory cell is &# 34 ; 0 &# 34 ; in the first and third read cycles and the bit line is charged up to the precharge voltage and then the potential is reduced . in the second read cycle , the information stored in the selected memory cell is &# 34 ; 1 &# 34 ;. therefore , the bit line is charged up to the precharge voltage and there is substantially no discharge thereafter , so that the bit line is kept at the high potential . the potential of the bit line is detected by the sense amplifier ( sa1 , . . . , san ) at a time when the sampling clock becomes &# 34 ; h &# 34 ;. in this case , it is judged at the rising edge of the sampling clock clk whether the information stored in the selected memory cell is &# 34 ; 0 &# 34 ; or &# 34 ; 1 &# 34 ;. the judged data is held in the latch circuit ( l1 , . . . , ln ) and then outputted externally . in the semiconductor memory device of this embodiment , the bit line is precharged by the first precharge circuit which is the conventional circuit and the second precharge circuit . therefore , it is possible to obtain a sufficient precharge voltage within a short time even when the pulse width of the precharge signal is small at high power source voltage . consequently , there is no detection error of the sense amplifier ( sa1 , . . . , san ) occurs in the first to third read cycles . charge precharged on the bit line is supplied from the power source vdd through the transistors pn and nn . since the drive performance of the transistors pn and nn is large , it is possible to precharge within a short time and , since the gate voltage of the transistor nn is vref , the source potential , that is , the bit line potential , does not become larger than vref . therefore , the precharge by the transistors pn and nn is automatically stopped , so that unnecessary current does not flow and the power consumption can be restricted minimum . fig3 shows a construction of a semiconductor memory device according to a second embodiment of the present invention . the semiconductor memory device shown in fig3 differs from the semiconductor memory device shown in fig1 in that the second precharge circuit is constructed with an inverter in , nand gate circuits ( nand1 to nandn ), comparators ( cmp1 to cmpn ) and p type transistors ( p1 to pn ). the remaining portion of the semiconductor memory device according to the second embodiment shown in fig3 is similarly constructed to that of the first embodiment shown in fig1 . the precharge signal / pr is supplied to an input of the inverter in whose output is connected to one input of the nand gates ( nand1 to nandn ). positive inputs of the comparators ( cmp1 to cpmn ) are connected to the reference voltage vref and negative inputs thereof are connected to the respective bit lines ( bl1 to bln ). outputs of the comparators are connected to the other inputs of the respective nand gates ( nand1 to nandn ). the outputs of the nand gages ( nand1 to nandn ) are connected to gates of the respective p type transistors ( p1 to pn ) whose sources are connected to the power source vdd and drains are connected to the respective bit lines ( bl1 to bln ). an operation of the semiconductor memory device according to the second embodiment shown in fig3 will be described with reference to fig4 which shows a signal timing chart . when the precharge signal / pr is &# 34 ; h &# 34 ;, the output of the inverter in becomes &# 34 ; l &# 34 ; and the outputs of the nand gates ( nand1 to nandn ) become &# 34 ; h &# 34 ;. therefore , p type transistors ( p1 to pn ) are in off state . when the precharge signal / pr becomes &# 34 ; l &# 34 ;, the output of the inverter in becomes &# 34 ; h &# 34 ;. the inverted inputs of the comparators ( cmp1 to cmpn ), that is , the potentials of the bit lines are compared with the reference voltage vref , respectively . when the potential of the bit line is lower than the reference voltage vref , the output ( node a1 , . . . , an in fig4 ) of the comparator cmp becomes &# 34 ; h &# 34 ; and the output of the nand gate becomes &# 34 ; l &# 34 ;. therefore , the p type transistor ( p1 , . . . , pn ) is turned on to rapidly charge the bit line ( bl1 , . . . , bln ) from the power source vdd . when the potential of the bit line ( bl1 , . . . , bln ) becomes higher than the reference voltage vref , the output of the comparator is inverted to &# 34 ; l &# 34 ; and the output ( node a1 , . . . , an ) of the nand gate ( nand1 , . . . , nandn ) becomes &# 34 ; h &# 34 ;, so that the p type transistor ( p1 , . . . , pn ) is turned off to stop the charging of the bit line . the precharging by the n type transistor ( q1 , . . . , qn ) continues for a time period in which the precharge signal / pr is &# 34 ; l &# 34 ;. in this embodiment , the bit line is rapidly charged from the power source vdd while sensing the potential of the bit line by the comparator cmp . therefore , the sufficient precharge voltage can be obtained within a short time even if the power source voltage is increased and the width of the precharge signal / pr becomes small . as a result , there is no detection error of the sense amplifier ( sa1 . . . , san ) occurs . fig5 shows a construction of a semiconductor memory device according to a third embodiment of the present invention . the semiconductor memory device of the third embodiment differs from the semiconductor memory device of the second embodiment of the present invention in that a dummy circuit portion 707 is provided to control the second precharge circuit . the dummy circuit portion 707 is composed of a p type transistor pd , an or gate ( ord ), a comparator cmp and an and gate ( andl ) the second precharge circuit is composed of p type transistors ( p1 to pn ) and or gates ( or1 to orn ). the remaining circuit portion of the semiconductor memory device shown in fig5 is constructed similarly to that of the second embodiment shown in fig3 . one input of the dummy or gate ( ord ) of the dummy circuit portion 707 is supplied with a precharge signal / pr and an output thereof is connected to a gate of the p type transistor pd and one inputs of the or gates ( or1 to orn ) of the respective bit lines . an inverted input of the comparator cmp is connected to the reference voltage vref and a positive input thereof is connected to the dummy bit line bld . an output of the comparator cmp is connected to the other input of the or gate ord . the other inputs of the or gates ( or1 to orn ) are connected the respective latch circuits ( l1 to ln ). an operation of the semiconductor memory device according to the third embodiment shown in fig5 will be described with reference to fig6 which shows a signal timing chart . when the precharge signal / pr is &# 34 ; h &# 34 ;, the output of the or gate ord ( node bd in fig6 ) is &# 34 ; h &# 34 ; and the p type transistor pd is in off state . when any one of the selection lines sl is selected , the output of the and gate ( andl ) become &# 34 ; h &# 34 ; and the potential charged on the dummy bit line is discharged through a dummy sub bit line subbl having an information corresponding to data of all of the memory cells ( m1 to m4 ) which are &# 34 ; 0 &# 34 ;. when the precharge signal / pr becomes &# 34 ; l &# 34 ;, one input of the dummy or gate prd becomes &# 34 ; l &# 34 ;. the potential of the dummy bit line bld is compared with the reference voltage vref and , when it is lower than the reference voltage vref , the output of the comparator cmp becomes &# 34 ; l &# 34 ; and the output of the or gate ord ( node bd in fig6 ) also becomes &# 34 ; l &# 34 ;. thus , the p type transistor pd is turned on , so that the dummy bit line bld is rapidly charged from the power source vdd . one inputs of the or gates ( or1 to orn ) of the bit lines are supplied with the data read out in the preceding read cycle and the other inputs thereof are supplied with the output of the dummy or gate ord . when the data read out in the preceding read cycle is &# 34 ; 0 &# 34 ;, the potential on the bit line ( bl5 in fig6 ) is discharged . in this case , the output ( nodes bl1 to bln in fig6 ) of the or gates ( or1 to orn ) become &# 34 ; l &# 34 ;. therefore , the p type transistors ( p1 to pn ) are turned on so that the bit lines ( bl1 to bln ) are charged rapidly from the power source vdd . when the potential of the dummy bit line bld becomes higher than the reference voltage vref , the output of the comparator cmp becomes &# 34 ; h &# 34 ; and the output ( nodes b1 to bn in fig6 ) of the or gate ord also becomes &# 34 ; h &# 34 ;. therefore , the p type transistor pd is turned off to stop the charging to the bit lines . incidentally , the precharge by the n type transistors q1 to qn continues for a period in which the precharge signal / pr is &# 34 ; l &# 34 ;. when the data read out in the preceding read cycle is &# 34 ; 1 &# 34 ;, the bit line ( bl in fig6 ) is not discharged . in this case , the output of the or gate ( or1 , . . . , orn ) becomes &# 34 ; h &# 34 ; ( b1 , . . . , bn in fig6 ) and the p type transistor ( p1 pn ) is kept off . therefore , the bit line is not charged from the power source vdd . in this embodiment , the dummy bit line is rapidly charged from the power source vdd while sensing the potential of the dummy bit line by the comparator cmp and confirming the preceding discharge by the or circuit . therefore , a sufficient precharge voltage can be obtained within a short time even if the power source voltage is increased and the width of the precharge signal becomes small . consequently , there is no detection error of the sense amplifiers ( sa1 to san ). as a modification of the third embodiment , the and gate and1 may be removed . in such case , &# 34 ; 0 &# 34 ; is written in all of the dummy memory cells such that the potentials thereof can be discharged through the sub bit line subbl when any one of the selection transistors s thereof is turned on during the sampling period . when the conventional timing generator circuit designed in accommodation to the low power voltage source is used with a high voltage power source , the pulse width of the precharge signal becomes too small to sufficiently precharge the bit lines , resulting in the erroneous reading of the memory content . according to the semiconductor memory device of the present invention , which is additionally provided with the second precharge means , however , it is possible to increase the precharge drive power and there is no erroneous reading of the memory content even if the width of the precharge pulse signal is small . further , since the present semiconductor memory device can accommodate to the precharge signal having small width , it is possible to shorten the time necessary to read out the memory content , that is , increase the operating speed of the semiconductor memory device . therefore , the repetition period can be shortened when a continuous reading is performed . although the present invention has been described with reference to the specific preferred embodiments , the present semiconductor memory device is not limited to them and various modifications thereof may be possible within the scope of the present invention . as described hereinbefore , the semiconductor memory device according to the present invention performs a stable voltage detection with a wide range power source voltage , so that it is possible to reliably read the memory content from a low voltage to a high voltage .