fig1 shows , in block diagram form , the central subsystem ( css ) unit 14 which takes the form of the production data processing system of the related patent application of ming - tzer miu and thomas f . joyce . as shown , css unit 14 includes a central processing unit ( cpu ) 20 , a virtual memory unit ( vmu ) 40 and a cache unit 60 . the cache unit 60 couples to system bus 11 through a bus interface unit ( biu ) 100 . as shown , the main elements of cpu 20 include an instruction unit ( i unit ) stage 20 - 2 , an address unit ( a unit ) stage 20 - 4 and an execution unit ( e unit ) stage 20 - 6 . in the preferred embodiment , the execution unit stage 20 - 6 includes a scientific unit ( s - unit ) and a commercial instruction processing unit ( c - unit ). the cache unit stage 60 includes an instruction cache ( i - cache ) 60 - 2 for storing instructions which are to be executed and an execution cache unit ( e - cache ) 60 - 4 for storing operands or data which are to be operated on according to the instructions being executed . the i - unit 20 - 2 performs two main functions . it prefetches instructions from the i - cache unit 60 - 2 and cracks or decodes these instructions to determine how the other units , namely the a - unit 20 - 4 and the e - unit 20 - 6 , will further process those instructions . the i - unit 20 - 2 also completes the execution of certain branch instructions , which are then removed from the production line . the a - unit 20 - 4 generates addresses from instructions it receives from the i - unit 20 - 2 . additionally , it completes the execution of certain types of instructions , such as register - to register type instructions , removing them from the production line . when the instruction is a type of instruction which is to be executed by e - unit 20 - 6 , the a - unit 20 - 4 sends a virtual address to vmu 40 , which translates it into a physical address for fetching the specified operands from the e - cache unit 60 - 4 . the operands fetched from the e - cache unit 60 - 4 are then transferred to the e - unit 20 - 6 for completing the execution of the instruction originally received by the i - unit 20 - 2 from the i - cache unit 60 - 2 . the a - unit 20 - 4 will also confirm the execution of a branch instruction and send the branch address back to the i - unit 20 - 2 , which will have already requested the next instruction from the i - cache unit 60 - 2 , as specified by the i - unit 20 - 2 prefetch branch address . as seen from fig1 both the a - unit 20 - 4 and e - unit 20 - 6 include register files which store the contents of the registers which are software programmer accessible . also , both the i - cache unit 60 - 2 and e - cache unit 60 - 4 are updated with instructions and operands fetched from main memory via system bus 11 and biu 100 . as shown in fig1 the i - unit stage 20 - 2 and a - unit stage 20 4 share a common firmware control store element 20 - 8 . similarly , e - unit , s - unit , and c - unit execution units 20 - 6 share another common firmware control store element 20 - 10 . fig2 shows in greater detail , e - unit stage 20 - 6 . as shown , e - unit stage 20 - 6 includes an instruction fifo buffer 20 - 600 for storing up to four instructions received from the i - unit stage 20 - 2 . the i - unit 20 - 2 generates i - efirst and i - elast signals when the instruction being cracked is to be executed by e - unit 20 - 6 . these signals are applied to fifo buffer 20 - 600 . signal i - efirst enables the fifo buffer 20 - 600 to store a double word instruction while signal i - elast enables buffer 20 - 600 to store a single word instruction . the next instruction is applied by fifo buffer 20 - 600 to a next address generator 20 - 602 . generator 20 - 602 generates an address applied to e - unit control store 20 - 604 . this results in a firmware word being read out into an output register ( rdr ) 20 - 606 . when a - unit 20 - 4 sends a virtual address to vmu40 , vmu 40 translates the virtual address into a physical address which is sent to e - cache unit 60 - 4 . e - cache unit 60 - 4 forwards the contents of the addressed location to a data fifo buffer 20 - 630 , in response to e - cache signal ld - dat - 16 - 32 for a single word transfer and e - cache signal ld - dat - 00 - 15 for a double word transfer . signal ld - dat - 00 - 15 also increments by one the write address stored in fifo buffer 20 - 630 to accept the next word transfer . the e - unit 20 - 6 executes instructions whose operands are stored in software visible register locations of register file 20 - 610 . fig3 shows , in greater detail , the next address generator circuits of block 20 - 602 . as shown , the generated address is stored in a control store address register 20 - 603 each clock cycle . the content of register 20 - 603 addresses control store 20 - 604 to read out a firmware word and store it in rdr register 20 - 606 . the firmware word controls the e - unit stage 20 - 6 . the next address generator 20 - 602 can determine the next control store address by cracking the next high level instruction in the i - fifo 20 - 600 ( mbr ) or by combining a base address in rdr 20 - 606 with one to four status bits selected by other fields in rdr20 - 606 ( tb , tb4 , tb8 , tb16 ), or by copying a next - address field of rdr20 - 606 ( jmp ), or by incrementing the current control store address 20 - 603 ( inc ), or by selecting the top of a firmware subroutine return stack ( pop ), or by being forced ( independently of the coding in rdr20 - 606 ) to a vector address by some external event ( vint , smfint , uev , etc .). the next address generator 20 - 602 performs similar services for c - unit firmware ( ctb , ctb4 , ctb8 , ctb16 , cjmp , cinc , cpop , etc .). for further information regarding the next address generator and the e - unit stage , reference may be made to the referenced related patent application entitled , &# 34 ; control store address generator for developing unique instruction execution starting address .&# 34 ; fig4 a shows the format of the firmware word of the 64k by 115 - bit e / c - unit control store 20 - 604 . as mentioned , this control store is shared between the c - unit chip and e - unit chip . the unit using the control store is defined by rdr bits 28 and 29 . only the fields of the firmware word of interest to the present invention will be described . bits 01 - 03 are a three - bit field which defines the branch type used for deriving the next control store address in a given microprogram sequence . bits 4 - 19 are a 16 - bit field which define the test and major branch conditions or the next firmware address to be executed . bits 22 - 27 , 57 - 59 , 88 - 99 , and 102 - 112 are concatenated to form a 32 - bit literal constant ( fwc32 ) which can be deposited , by codes in other fields , not shown , into the a - unit register file location specified by the spav field bits 32 - 37 . with reference to fig1 through 4a , the method and apparatus of the present invention will now be described with reference to fig4 b . in accordance with the present invention , each vacant , unused , potentially illegal branched to , reserved , and wait for trap location contained in control store 20 - 604 is coded to contain a different unique command pattern . additionally , control store 20 - 604 is programmed to store a firmware reporting routine which joins a uev handler routine described in the referenced related george j . barlow patent application . the firmware reporting routine as shown includes a number of collector processing routines designated as $ vag , $ imf , $ purg , and $ damt . the coding of these routines is set forth in the appendix . as mentioned , all firmware locations of the control store 20 - 604 not explicitly loaded with command words , such as those formatted as shown in fig4 a , are loaded with predetermined command patterns . one pattern is used to identify unused locations . this pattern contains an address value identifying the location &# 39 ; s address and a first tag code which specifies the location as &# 34 ; unused .&# 34 ; appropriate bits within the pattern are coded to specify a branch or jump to an entry point within the firmware reporting routine . this corresponds to the starting location of the $ vag collector routine . during control store 20 - 604 operation , if the next address generator circuits 20 - 602 are caused , by a transient or intermittent error , to access for execution an unused firmware location , the command bit pattern is read out into rdr register 20 - 606 . the coded fields contained in rdr register 20 - 606 cause the vag routine to be entered . this routine causes the address of that unused location of the e - unit control store being accessed to be written into working location 7 ( wl7 ) of the a - unit 20 - 4 register file . this results in the storage of information , such as that shown in fig4 b . also , in accordance with the present invention , a similar type of command pattern is used to designate impossible branch destination firmware locations . this pattern is used to detect a type of fault occurring when a transient or intermittent condition produces some of the branch ways of a four , eight or sixteen - way branch which are impossible because of the logic of the value being tested ( e . g . only three conditions of a four - way branch are valid ) or by convention ( e . g . a particular internal flag is defined for only 12 of 16 values ). for example , a four - way branch may be defined by the most significant bit ( msb ) and = 0 of a value which should yield the cases & lt ; 0 ,= 0 and & gt ; 0 . when the fourth way (= 0 and msb = 1 ) occurs , this indicates a hardware failure or a uev condition . a two &# 39 ; s complement number can only be & lt ; 0 , = 0 , or & gt ; 0 . therefore , a four - way branch on a number &# 39 ; s sign and on the number being = φ , logically cannot transfer to the case corresponding to both = φ and the sign bit value which implies the number is & lt ; φ . during the operation of control store 20 - 604 , if the input conditions to the next address logic circuits produce an invalid branch , the resultant access is to one of the illegal branched to locations such as shown in fig4 c . when this location is accessed , the control store 20 - 604 is caused to reference a second collector routine $ imf . this causes a second tag code &# 34 ; 8002 &# 34 ; designating badbranch along with the e - unit firmware address of the control store location $ badbranch of fig4 c . in certain cases , a firmware designer can put a branch in place to reserve a destination firmware location for a possible future implementation . in accordance with the present invention , each such reserved location is coded to store a command pattern which specifies loading a - unit location wl7 with a further tag code &# 34 ; 8009 &# 34 ; and the address of the reserved location . during control store operation , when a reserved location is referenced , such as that of figure 4c , the command pattern is read out into rdr register 20 - 606 . the decoding of the command causes the control store to branch to the $ vag collector routine . this result causes the tag code &# 34 ; 8009 &# 34 ; and the address of the reserved location in fig4 c to be loaded into register file location wl7 . the result is as shown in fig4 b . in addition to the above , the method and apparatus of the present invention can be extended to detect a failure to receive a trap . the e - unit firmware control unit , in the case of i - unit detected traps , must wait for the vmu40 to send interrupt signal vint to send the e - unit control store 20 - 604 to the appropriate handler . if one of the &# 34 ; wait for trap &# 34 ; locations is accidently entered as the result of a transient or intermittent condition , or if the i - chip stage 20 - 2 fails to consummate the interrupt request , the wait - for trap loop could loop forever . to prevent this , a coded command pattern replaces in all loop - on - self locations . this command pattern specifies the loading of a - unit wl7 register file location with a trapwait code of &# 34 ; 8003 &# 34 ; and the address of the wait for trap location . additionally , the command pattern specifies that the e - unit control store 20 - 604 is to jump to the routine $ purg which sets up a limited loop ( i . e ., count of 64 k clock cycles ) waiting for receipt of the vint interrupt signal . accordingly , during e - unit operation , when a wait for trap location is accessed accidentally , this causes the read out of the command pattern into rdr register 20 - 606 . the command pattern , upon being read out , causes a - unit wl7 location to be loaded with the wait - for - trap location address along with the trapwait tag code of &# 34 ; 8003 .&# 34 ; this produces the result shown in fig4 b . also , the e - unit control store 20 - 604 is caused to jump to routine $ purg which sets a second a - unit working location awi to all ones . this location is used for the count down ; its contents are decremented by one for each cycle of the e - unit loop . next , the e control store references routines $ purg : n , $ purg : p , purg : z , and $ damt as a function of the time the e - unit stage is required to wait for interrupt signal vint from vmu40 . if the loop count is decremented to all zeros again before signal vint is received , the routine $ purg : z is entered which causes a jump to routine $ damt . the routine $ damt causes the referencing of the uev firmware handler for signalling the detection of a uev fault . when the interrupt signal vint is received prior to the loop count reaching zeros , the count down is aborted . this frees up a - unit wl7 location to be overwritten for any firmware purpose . from the above , it is seen how the method apparatus of the present invention enables the identification of probable reasons for faults occurring within the e - unit firmware control unit indicative of a runaway condition . this can be achieved with no changes to the e - unit firmware control unit . for further information regarding the manner in which the codes are allocated and stored in the control store , reference may be made to the appendix . the following is a pseudo - code representation of the relevant part of the firmware statements in terms of a higher - level syntax used for specifying the desired actions performed by the present invention . ______________________________________ $ unusedthis label name causes the assembler / linker to act as if these actions were explicitly coded for every otherwise unallocated firmware address - aw7 & lt ;- 8001 #: 0 :$ self $ self is the 15 - bit address of the location being assembled . &# 34 ; nnnn #&# 34 ; represents a 16 - bit hexadecimal literal . the &# 34 ;:&# 34 ; concatenates the values on either side . jmp ($ vag )$ badbranch ( 1234 #) the label and allocated address , 1234 . sub . 16 , are purely for illustration of how a &# 34 ; bad branch &# 34 ; type location should be coded .- aw7 & lt ;- 8002 #: 0 :$ selfjmp ($ imf );$ stub ( 4567 #) the label and allocated address , 4567 . sub . 16 , are purely for illustration of how a &# 34 ; stub &# 34 ; type location should be coded .- aw7 & lt ;- 8009 #: 0 :$ selfjmp ($ vag );$ trapwait ( 89ab #) the label and allocated address , 89ab . sub . 16 , are purely for illustration of how a &# 34 ; wait - for - trap &# 34 ; type location should be coded .- aw7 & lt ;- 8003 #: 0 :$ selfjmp ($ purg );$ vag ( 7fed #) this is one of the runaway firmware reporting routines - wl7 & lt ;- aw7jmp ($ fw - uev );$ imf ( 7fef #) this is one of the runaway firmware reporting routines - wl7 & lt ;- aw7jmp ($ fw - uev );$ purg ( 7fed #) this is one of the runaway firmware reporting routines - aw1 & lt ;- 65535loop count . this sets alu - sign and clears alu - zero flags - jmp ($ purg : n );$ purg : n ( 7fe2 #) aw1 & lt ;- aw1 - 1some external event should break the firmware out of this loop before 65535 decrements of aw1 have occurred . this also updates the alu - sign and alu - zero flags .- if alu - zero and not alu - sign jmp ($ purg : z ) i . e ., previous step put zero into aw1 .- if alu - zero and alu - sign jmp ($ purg : imf ) - i . e ., the impossible occurred in the previous step .- if not alu - zero and not alu - sign jmp ($ purg : p ) i . e ., previous step made aw1 & gt ; 0 - if not alu - zero and alu - sign jmp ($ purg : n ) i . e ., the previous step made aw1 & lt ; 0 -;$ purg : p ( 7fc2 #) aw1 & lt ;- aw1 - 1some external event should break the firmware out of this loop before 65535 decrements of aw1 have occurred . this also updates the alu - sign and alu - zero flags .- if alu - zero and not alu - sign jmp ($ purg : z ) i . e ., previous step put zero into aw1 .- if alu - zero and alu - sign jmp ($ purg : imf ) - i . e ., the impossible occurred in the previous step - if not alu - zero and not alu - sign jmp ($ purg : p ) i . e ., previous step made aw1 & gt ; 0 - if not alu - zero and alu - sign jmp ($ purg : n ) i . e ., the previous step made aw1 & lt ; 0 -;$ purg : z ( 7fd2 #) jmp ($ damt ) the firmware must have a problem toreach here -. ;$ purg : imf ( 7ff2 #) a real example of an impossible branch -- aw7 & lt ;- 8002 #: 0 :$ selfjmp ($ imf );$ damt ( 7fec #) wl7 & lt ;- aw7jmp ($ fw - uev ); ______________________________________ it will be appreciated , however , that the present invention is not limited or restricted to any particular assembling technique or apparatus . many changes may be made to the preferred embodiment , such as specifying different codes , etc . while in accordance with the provisions and statutes there has been illustrated and described the best form of the invention , certain changes may be made without departing from the spirit of the invention as set forth in the appended claims and , in some cases , certain features of the invention may be used to advantage without a corresponding use of other features .