fig1 a illustrates the improvement to the tlm architecture of fig4 . the improvement is the addition of an off - chip tap ( oct ) interface 1106 . the oct interface can be selected between the ics tdi and tdo pins , via the tlm &# 39 ; s tap link control bus , exactly as the ic and core tap domains were described being selected . once selected , the oct interface can serve as a master tap interface to a slave tap interface ( i . e . a conventional 1149 . 1 tap interface ) on another ic . thus an ic having the tlm architecture improvement shown in fig1 a would have the conventional 1149 . 1 tap interface 1102 plus the selectable oct interface 1106 for mastering the tap interface of another ic or ics 1108 . while one oct interface 1106 is shown in fig1 a , any number of oct interfaces may be provided . fig1 b illustrates the oct interface 1106 being coupled 1110 to a tap interface of another ic 1108 . as seen in fig1 b , the oct interface consists of buffers which couple the tdi oct , tck , tms oct , tdo oct , and trst tlm architecture signals up to tdo , tck , tms , tdi , and trst pads 1104 , respectively , of the ic in which the tlm architecture resides . the tdo , tck , tms , tdi and trst pads 1104 can be coupled to the tdi , tck , tms , tdo and trst pads of the other ic 1108 , via connections 1110 , to provide access the tap domain of the other ic 1108 . the tap domain of the other ic could be similar to that shown in fig1 a . fig1 - 14 illustrate the changes required to the input and output linking circuitry of fig5 - 7 , respectively , to add the oct interface of fig1 a . as seen in fig1 , an additional and gate 1202 is added to provide gating on and off the tms input ( tms oct ) of the oct interface . as seen in fig1 , an additional multiplexer 1302 is provided for selecting the tdi input ( tdi oct ) of the oct interface , and the other multiplexers are provided with an additional input for receiving the tdo output ( tdo oct ) of the oct interface . as seen in fig1 , an input is added to the output multiplexer to receive the tdo output ( tdo oct ) of the oct . additionally , control signals are added to the tlm &# 39 ; s tap link control bus to provide for controlling the added tms oct and gate , the additional tdi oct multiplexer , and the additional tdo oct input to the multiplexers . fig1 illustrates examples of the possible tap link arrangements ( link 0 - link 13 ) of the tlm architecture of fig1 a during tap instruction register scan operations . the link arrangements include those previously shown in fig9 , plus additional link arrangements that include the oct interface . as seen , there are two powerup / reset options for the default tap link , link 0 and link 7 . the link 0 ( option 1 ) selects only the ic &# 39 ; s tap in the link , whereas link 7 ( option 2 ) selects the ic &# 39 ; s tap plus the oct interface in the link . an example of why option 2 may be necessary is shown in example f of fig1 . fig1 is provided to simply show , as did fig9 , that the tlm is transparent during tap data register scan operations . fig1 a - 17o show examples of various tap link arrangements between two die ( die 1 and 2 ) located on a common substrate . while each die 1 and 2 is shown including the improved tlm architecture ( tlma ) of fig1 it should be understood that only die 1 of each example requires the tlm architecture of fig1 to provide access to die 2 . die 2 of each example could simply have a jtag architecture as shown in fig1 a . in each example , the conventional tap interface 1702 of die 1 ( tdi , tck , tms , trst , and tdo ) is the tlma interface of die 1 and is coupled to a jtag bus controller , such as a tester , debugger , emulator , or other controller . also in each example , the oct interface 1704 of die 1 ( tdi , tck , tms , trst and tdi ) is coupled to the conventional tap interface 1706 of die 2 ( tdi , tck , tms , trst and tdi ) which is the tlma interface of die 2 . in example a , only the ic tap of die 1 is included in the link to the jtag controller . in example b , only the core n tap is included in the link to the jtag controller . in example c , only the core 1 tap is included in the link to the jtag controller . in example d , the core 1 and core n taps are included in the link to the jtag controller . in example e , all taps of die 1 are included in the link to the jtag controller . in example f , the ic taps of die 1 and 2 are included in the link to the jtag controller , the ic tap of die 2 being accessed via the oct interface of die 1 . the link of example f would be selected to allow performing jtag extest interconnect testing on both die 1 and die 2 . as mentioned in regard to option 2 of fig1 , the link arrangement of example f may be selected as the powerup / reset link to allow the ic taps of both die 1 and 2 to be accessed for interconnect testing . in example g , the taps of die 1 are all bypassed while the ic tap of die 2 is included in the link to the jtag controller via the oct of die 1 . in this arrangement , the tap link of die 1 would be as shown in link 13 of fig1 and 16 . examples h through l similarly bypass the die 1 taps to access the taps of die 2 via the oct . example m through o illustrates various links that include taps of both die 1 and die 2 . examples l and o illustrate that the oct of die 2 could be used if necessary to link to tap interfaces of other die . fig1 illustrates an example of a more complex die on substrate arrangement whereby the flexibility of the improved tlm architecture can be further seen . the tlma interface 1802 of die 1 serves as the die coupled to the jtag controller , as it did in the previous examples . die 1 also serves as the tap access point , via its oct 1804 , to daisy - chained tlma interfaces 1806 and 1808 of die 2 and 3 . die 2 and die 3 serve as further tap access points , via their octs 1810 and 1812 , to tlmas 1814 and 1816 of die 4 and 5 , respectively . by dotted line arrows it is seen that any one or more tap domains of each die 1 - 5 may be selected and linked for access via the jtag controller connection to die 1 . further , bypassing of die 1 , as in examples g through l allows direct access to die 2 and 3 . die 2 and 3 can be similarly bypassed to provide direct access to die 4 and 5 . fig1 illustrates two substrates 1902 and 1904 each with two die that include the improved tlm architecture of fig1 a . substrate 1902 includes a die labeled die 1 : 1 and a die labeled die 1 : 2 . substrate 1904 includes a die labeled die 2 : 1 and a die labeled die 2 : 2 . the tlma interface 1906 of die 1 : 1 is daisy - chained with the tlma interface 1914 of die 2 : 1 . the daisy - chained path is coupled to a jtag controller . the tlma interface 1910 of die 1 : 2 is coupled to the oct interface 1908 of die 1 : 1 . the tlma interface 1918 of die 2 : 2 is coupled to the oct interface 1916 of die 2 : 1 . the importance of fig1 is the showing of a serial access approach whereby the jtag controller may access tap domains vertically as well as horizontally . the die labeling is done such that the left number indicates the horizontal position of the die &# 39 ; s substrate on the daisy - chained path and the right number indicates the vertical position of the die on the substrate . in a first example , the jtag controller may horizontally access tap domains of only die 1 : 1 and 2 : 1 in the daisy - chain arrangement without accessing the tap domain of vertically accessible die 1 : 2 and 2 : 2 . in a second example , the jtag controller may vertically access the tap domains of die 1 : 2 , via the oct of die 1 : 1 , and include those tap domains in with the daisy - chained horizontal access of tap domains in die 1 : 1 and 2 : 1 . in a third example , the jtag controller may vertically access the tap domains of die 1 : 2 via the oct of die 1 : 1 , the tap domains of die 2 : 2 via the oct of die 2 : 1 , and include those tap domains in with the daisy - chained horizontal access of tap domains in die 1 : 1 and 2 : 1 . in a forth example , the jtag controller may bypass ( as shown in fig1 j - 17i ) the tap domains of die 1 : 1 and 2 : 1 to vertically access the tap domains of die 1 : 2 and 2 : 2 such that only the tap domains of die 1 : 2 and 2 : 2 are included in the horizontal daisy - chain path to the jtag controller . as can be seen , access to additional vertical die is possible using the oct interfaces 1912 and 1920 of die 1 : 2 and 2 : 2 . fig2 is provided to indicate that the tlm can be positioned at the beginning of the ic &# 39 ; s tdi to tdo serial path instead of at the ending as shown in fig1 a , if desired . the tlm circuit would operate as previously described to control the input and output linking circuitry . the only difference would be that the tlm &# 39 ; s instruction shift register would no longer need to capture the jtag required 0 and 1 bits shown in fig8 b , since those 0 and 1 bits would be provided during instruction scan operations to the ic &# 39 ; s tdo by the selected tap domain ( s ) instruction register . the leading position of the tlm in fig1 would alter the tap link arrangement examples of fig1 and 16 to the extent that the tlm would be shown existing at the beginning of the linked tap domains ( i . e . closes to the tdi pin ) instead of at the ending of the linked tap domains ( i . e . closes to the tdo pin ). fig2 illustrates an ic including the present invention . the ic has functional inputs and outputs and functional circuitry responsive thereto . the ic has a conventional primary jtag port ( i . e . tlma interface of the present invention ) and a secondary jtag port ( i . e . oct interface of the present invention ). while a detail description has been given of how the tlm architecture can be improved to include the secondary jtag port ( oct ) of fig2 , there may be alternative / derivative approaches that could be envisioned to couple a primary jtag port of a functional ic to a secondary port of the same functional ic . these other approaches would be inspired by the teachings provided by the present invention . to the extent that the present invention has provided an original teaching of at least one preferred way of doing this , the invention deserves claims that would broadly cover a functional ic that includes a conventional primary jtag port for coupling to a jtag controller and a secondary jtag port for coupling to another primary jtag port of another ic .