the principles and operation of error correction encoding and decoding according to the present invention may be better understood with reference to the drawings and the accompanying description . the preferred embodiments of the present invention that are described herein are systematic ecc embodiments . it will be clear to those skilled in the art how to implement nonsystematic ecc embodiments of the present invention . the solution to the problem described in the field and background section lies in using two different and independent ecc schemes for protecting the same data . ( for the purpose of the present invention the term “ ecc scheme ” means a specific instantiation of an ecc algorithm , with all adjustable parameters set to specific fixed values ). suppose we have d data bits that should be protected against any combination of not more than e bit errors . also suppose we have two ecc schemes with the following characteristics a . a first ecc scheme capable of correcting e bit errors in d data bits , but having a relatively slow decoding time , not meeting the goal set for the average read speed . b . a second ecc scheme capable of correcting e 1 bit errors in d data bits , where e 1 & lt ; e . additionally , this second ecc scheme is capable of detecting its own failure — in case the number of bit errors is higher than e 1 but not higher than e , the decoding algorithm provides a failure indication . ecc schemes that provide ( for some error numbers ) only error detection capability and not error correction capability are typically simpler than corresponding ecc schemes with full error correction capabilities . therefore , this second ecc scheme is typically simpler than the first ecc scheme , and hence is also faster , meeting the read speed goal . we now use the two ecc schemes for protecting d data bits in the following manner : a . before writing data to the memory , the first ecc algorithm is applied to the data bits in order to compute p 1 parity bits . a combination of the d data bits and the p 1 parity bits provides for correcting up to e errors in the data . b . before writing data to the memory , the second ecc algorithm is applied to the data bits in order to compute p 2 parity bits . a combination of the d data bits and the p 2 parity bits provides for correcting up to e 1 errors in the data , and for detecting up to e errors in the data . c . the data bits , the p 1 parity bits , and the p 2 parity bits , are all recorded into the flash memory . note that formally speaking we should not call the combination of the data bits , the p 1 parity bits and the p 2 parity bits a “ codeword ”. the data bits plus the p 1 parity bits constitute a codeword for the first ecc scheme . the data bit plus the p 2 parity bits constitute a codeword for the second ecc scheme . but formally speaking there is no ecc scheme for which the combination of data bits plus the p 1 parity bits plus the p 2 parity bits is a codeword . still , in order to simplify the language used herein , any combination of data bits with parity bits associated with that data and generated from that data is called herein a “ codeword ”, regardless of whether there is a single known - in - the - art ecc algorithm that generates all of the parity bits from the data bits . d . when the data are retrieved from the memory , the entire content is read — the data bits , the p 1 parity bits and the p 2 parity bits . e . the decoder of the second ecc scheme is applied to the combination of the d data bits and the p 2 parity bits . if the number of errors happens to be equal to or less than e 1 , the decoding ends successfully , the errors ( if there were any ) are corrected , the data are sent to the requesting software application and the reading operation ends . r . if , on the other hand , the number of errors happens to be more than e 1 ( but still less than e ), the decoder of the second ecc scheme identifies this condition . in such case we apply the decoder of the first ecc scheme to the combination of the d data bits and the p 1 parity bits . as long as the number of errors is not higher than e ( and by setting the reliability requirements to e errors we implicitly indicated that the probability of having more than e errors can be neglected ), the decoding succeeds , all errors are corrected , the data are sent to the requesting software application and the reading operation ends . because the probability of a large number of errors in the data is typically much smaller than the probability of a small number of errors , the above procedure typically results in average decoding time that is close to the decoding time of the second ecc scheme , which is the faster of the two ecc schemes . this can easily be seen from the following simplified calculation example . suppose e = 3 ( that is — we must correct up to 3 errors in the data ). suppose e 1 = 2 ( that is — the second ecc corrects only up to two errors ). suppose the probability of one error in the d data bits is 10 − 1 . then we can approximate the probability of two errors in the data as 10 − 2 , and the probability of three errors in the data as 10 − 3 . if the decoding time of the first ecc is 1000 microseconds and the decoding time of the second ecc is 10 microseconds , then the average decoding time of the above method is — t =( 1 − 10 − 3 )× 10 + 10 − 3 × 1000 = 9 . 99 + 1 = 10 . 99 microseconds . if the probability for an error in the data is lower ( as is the case in many types of flash memories ), then the average speed of the above method gets even much closer to the speed of the second ecc scheme . therefore we see that the method of the present invention achieves both of the following two goals simultaneously : b . providing the desired reliability level at the output of the memory system . it should be noted that the benefits of the present invention do not come at no cost . the method requires the storing in the flash memory of parity bits of both the first ecc scheme and the second ecc scheme . the number of parity bits stored ( which is the number of overhead bits spent for the error correction ) is thus higher than the number of parity bits needed for the first ecc scheme , that provides the same level of error correction ( i . e . e errors ). we thus have traded average decoding speed for extra storage space used for parity bits , storage that is unavailable for storing data . however , there are many cases in which this trade - off is well justified , as the reading speed of the memory is much more important than the wasted storage space . as there are already in the prior art ecc solutions that use two ecc decoders , we should emphasize the differences between those solutions and the present invention . ( 1 ) one ecc algorithm well known in the prior art is the turbo ecc algorithm . in turbo ecc the data bits are encoded twice by the same encoder , each time with the data bits in different order . when decoding , two similar decoders are operated in parallel on the same bits , such that the parity bits of both encodings contribute together to the errors correction , and information is exchanged between the two decoders during the decoding process . one must remember that turbo codes are an example of what is called “ soft decoders ” in the ecc literature , where decoded bits are represented by nodes in a graph and the decoding is done iteratively in successive cycles , allowing the propagation of information between any two bits in the graph . this is unlike the present invention , in which only one decoder is operating on the data at any given time , and each decoder makes use only of its own parity bits and not of any other information . ( 2 ) even if there would have existed variants of the turbo ecc algorithm that first attempt to decode using only one decoder , and only if that decoder fails activate the second decoder ( and the present inventor is not aware of such variants ), this is still different from the present invention in that the second decoder in these hypothetical turbo ecc variants operates not on the data as read from the memory , but on modified data that already have been processed and modified by the first decoder . this is unlike the present invention , in which each decoder operates on the raw data bits as read from the memory , with no other input affecting its operation ( except its own parity bits ). ( 3 ) some prior art solutions ( such as the solution taught by lasser et al . in u . s . application ser . no . 10 / 197 , 316 and the solution taught by joshi et al . in u . s . pat . no . 4 , 712 , 215 ) also utilize two ecc schemes in the following way — some ( usually a small ) portion of the data is protected by a first ecc scheme . all of the data , including the portion protected by the first ecc scheme and including the parity bits of the first ecc scheme , are protected by a second ecc scheme . such solutions are meant to provide relatively fast and simple decoding for a small portion of the data , for example for control information describing some features of the main data portion . these solutions do not provide fast decoding of the full encoded data chunk , unlike the present invention . ( 4 ) even if there would have existed extensions of these solutions in which the first ecc encodes all of the data bits and not just a portion of the data bits , and the second ecc encodes all of the data bits including the parity bits of the first ecc ( and the present inventor is not aware of such systems ), this would still be different from the present invention , in which there is no information flow between the two decoders . this difference is an important advantage of the present invention , as it allows the two encoding operations to take place in parallel and thus complete relatively fast . this is unlike the above hypothetical systems , in which the second encoder must operate only after the first encoder has finished operating , as the output of the first encoder is an input to the second encoder . the scope of the present invention includes the error correction methods described above . the scope of the present invention is not limited to flash memory systems , but also extends to any type of memory — magnetic , optical , or any other . the scope of the present invention also includes a memory system comprising a memory and a controller for the memory that employs the methods of the present invention . the scope of the present invention also includes a computing system that includes a memory system that employs the methods of the present invention . the scope of the present invention also includes a computing system that includes a memory and a host computer that employs the methods of the present invention , with no dedicated memory controller being used . it should be noted that the methods of the present invention are not limited to memory systems . error correction is also employed in communication systems , to recover from errors introduced into transmitted data bits while on their way to their destination . the scope of the appended claims should therefore also be construed to extend to errors correction methods and systems employed in correcting errors in transmitted data . referring now to the drawings , fig1 is a high - level block diagram of a flash memory device 10 of the present invention , coupled to a host 20 . fig1 is adapted from fig1 of ban , u . s . pat . no . 5 , 404 , 485 , which patent is incorporated by reference for all purposes as if fully set forth herein . flash memory device 10 includes a flash memory 14 , a controller 12 and a random access memory ( ram ) 16 . controller 12 , that corresponds to “ flash control 14 ” of u . s . pat . no . 5 , 404 , 485 , manages flash memory 14 , with the help of ram 16 , as described in u . s . pat . no . 5 , 404 , 485 . when writing data to flash memory 14 or when reading data from flash memory 14 , controller 12 applies the error correction method of the present invention as described above . fig2 is a high - level partial block diagram of a data storage system 40 of the present invention . data storage system 40 includes a processor 42 and four memory devices : a ram 44 , a boot rom 46 , a mass storage device ( hard disk ) 48 and a flash memory device 30 , all communicating via a common bus 50 . like flash memory device 10 , flash memory device 30 includes a flash memory 32 . unlike flash memory device 10 , flash memory device 30 lacks its own controller and ram . instead , processor 42 emulates controller 12 by executing a software driver that implements the methodology of u . s . pat . no . 5 , 404 , 485 in the manner e . g . of the trueffs ™ driver of m - systems flash disk pioneers ltd . of kfar saba , israel . when writing data to flash memory device 30 or when reading data from flash memory device 30 , processor 42 applies the error correction method of the present invention as described above . flash memory device 30 also includes a bus interface 34 to enable processor 42 to communicate with flash memory 32 . the code of the software driver that processor 42 executes to manage flash memory 32 is stored in mass storage device 48 and is transferred to ram 44 for execution . mass storage device 48 thus is an example of a computer - readable code storage medium in which is embedded computer - readable code for managing flash memory 32 according to the principles of the present invention . fig3 is a schematic high - level block diagram of a data communication system 60 of the present invention . system 60 includes a transmitter 62 , a transmission medium 64 and a receiver 66 . transmitter 62 transmits data to receiver 66 via medium 64 . before transmitting the data , transmitter 62 applies the error correction encoding of the present invention to the data . upon receiving the transmitted data , receiver 66 applies the error correction decoding of the present invention to the data . transmission medium 64 may be any suitable medium for transmitting data using any suitable carrier of the data . common examples of such media include free space and coaxial cables for radio frequency transmissions , and optical fibers for optical frequency transmissions . transmitter 62 and receiver 66 are adapted to the nature of transmission medium 64 . data communication systems similar to system 60 that use prior art methods for error correction encoding and decoding are well known , and it is straightforward for one ordinarily skilled in the art to modify such a prior art system to use the error correction methodology of the present invention . while the invention has been described with respect to a limited number of embodiments , it will be appreciated that many variations , modifications and other applications of the invention may be made .