referring to fig5 and 6 , an input protection transistor 180 according to the present invention comprises : a p well 202 formed on a p type substrate 200 ; a field oxide film 204 for electrically isolating a field region 203 from another field region ; n + source / drain regions 206a and 206b formed in the field region 203 apart from each other ; an oxide film 210 formed on a region in a major surface of the substrate , between the n + source / drain regions 206a and 206b ; a first gate 212 formed on the oxide film 210 ; an oxide film 214 formed on the first gate 212 ; a second gate 216 formed on the oxide film 214 ; an interlayer insulation film 218 formed on the semiconductor substrate 200 so as to cover the first and second gates ; and an aluminum interconnection 222 electrically connected to the n + source / drain regions 206a and 206b through a contact hole 220 made in the interlayer insulation film 218 . as shown in fig5 the second gate 216 is electrically connected to an aluminum interconnection 219 through a contact hole 217 . fig7 a and 7b show the input protection transistor and its peripheral circuit shown in fig5 and 6 . referring to fig7 a , an electrode pad 12 is connected through an interconnection 14 to an inverter 160 as one example of an internal logic circuit . the above described input protection circuit 180 is connected to the interconnection 14 so as not to apply an overvoltage to the inverter 160 . in the input protection transistor 180 , one n + source / drain region 206a is connected to the interconnection 14 , while the other n + source / drain region 206b , the second gate 216 as a gate electrode and the semiconductor substrate 200 are all grounded . when a surge voltage is applied to the electrode pad 12 , a charge flows into the semiconductor substrate 200 through the interconnection 14 and through the n + source / drain region 206a , but is prevented from flowing into a gate electrode of the inverter 160 . a drain of the input protection transistor 180 is formed only of a high concentration impurity region without the low concentration impurity region as shown in fig2 c , so that the gradient of intensity of an electric field in the drain is comparatively large , resulting in no destruction of the input protection transistor . modifications of the input protection transistor are shown in fig8 a , 8b , 8c , 8d , 8e , 8f and 8g . in an input protection transistor shown in fig8 a and 8b , not second gate 216 but the first gate 212 is grounded . the first gate 212 is grounded for the purpose that a charge is made possible to be stored between the first gate 212 and the semiconductor substrate 200 so as to increase a capacitance of the input protection transistor and thus make an extra charge provided to the electrode pad 12 easily escape into the semiconductor substrate 200 . fig8 c and 8d show such a case that both the first and second gates 212 and 216 are grounded . fig8 e and 8f show a case where the first gate 212 is grounded , while the second gate 216 is connected to the electrode pad 12 . when the connection is carried out as shown in the fig8 e and 8f , it gives a structure that a drain - gate overlap capacitance c 1 , a capacitance across a floating gate and a control gate ( an interlayer capacitance ) c 2 , and a drain - substrate junction capacitance c 3 are connected in parallel , as shown in fig8 g , so that charge absorbing capabilities by these capacitances are increased and thus a surge breakdown voltage is increased . description will now be given of a process for manufacturing the semiconductor device according to one embodiment of the present invention , with reference to fig9 a - 9k . since processing steps to be carried out before the step of fig9 a are identical to those shown in fig3 a - 3f , a description thereof will not be repeated . the processing steps shown in fig9 a - 9k are in correspondence with those shown in fig3 g - 3q . referring to fig9 a , a polysilicon film 212 having a thickness of approximately 3000 å is formed on the overall surface of a p type silicon substrate 200 , and is then doped with phosphorus to be made of n type . a resist film 234 is then formed on the polysilicon film in an eprom region 32 and in an input protection transistor region 36 by employing photolithography . next , with the resist film 234 used as a mask , the polysilicon film 212 is etched , so that the polysilicon film 212 is left at the eprom region 32 and input protection transistor region 36 . the resist film 234 is then removed . in order to regulate a threshold voltage of an mos transistor , repetition of applying the resist and implanting ions carries out channel doping for each transistor , and further , the oxide film 66 other than beneath the polysilicon film 212 is removed . referring to fig9 b , a gate oxide film 236 having a thickness of approximately 250 å is formed in the cmos region 34 by oxidation . at this time , an oxide film 214 is formed on the side surface and the upper surface of the polysilicon film 212 . a polysilicon film 216a having a thickness of approximately 2800 å is formed on the overall surface of the silicon substrate 200 and is then doped with phosphorus . thereafter , a molybdenum silicide film 216b having a thickness of approximately 2300 å is formed on the polysilicon film 216a . as shown in fig9 c , a resist film 238 is formed on the overall surface of the cmos region 34 and in gate forming regions of the eprom region 32 and input protection transistor region 36 . etching is then carried out , with the resist film 238 used as a mask , so as to remove the molybdenum silicide film 216b , the polysilicon film 216a , the oxide film 214 , the polysilicon film 212 and the gate oxide film 66 in regions in the eprom region 32 and input protection transistor region 36 other than their gate forming regions . the polysilicon film 212 left in the eprom region 32 constitutes a floating gate , and the polysilicon film 216a and molybdenum silicide film 216b constitute a control gate . the polysilicon film 212 left in the input protection transistor region 36 constitutes the first gate shown in fig6 while the polysilicon film 216a and molybdenum silicide film 216b in the region 36 constitute the second gate 216 . a gate length of the gate in the eprom region 32 is approximately 1 . 2 μm , while that of the gate in the input protection transistor region 36 is approximately 3 . 0 μm . the resist film 238 is then removed . referring to fig9 d , arsenic is ion - implanted into the overall surface of the semiconductor substrate 200 , with the molybdenum silicide film 216b used as a mask , thereby forming an n + source / drain region 206 in a surface region of each of the eprom region 32 and the input protection transistor region 36 . with reference to fig9 e , a resist film 240 is formed on a gate forming region of the cmos region 34 and on the overall surface of the eprom region 32 and input protection transistor region 36 . with the resist film 240 used as a mask , etching is then carried out so as to remove the molybdenum silicide film 216b and polysilicon film 216a formed in regions in the cmos region 34 other than its gate forming region . therefore , gate electrodes 242 and 244 are formed in the cmos region 34 . a gate length lc of the gate electrode 242 is approximately 1 . 5 μm , while that of the gate electrode 244 is approximately 1 . 3 μm . the resist film 240 is then removed . referring to fig9 f , a resist film 246 is formed on the overall surfaces of the eprom region 32 , a p channel transistor region 33 which is a portion of the cmos region 34 , and the input protection transistor region 36 . phosphorous is then ion - implanted with the resist film 246 and the gate electrode 244 used as masks , thereby forming an n - source / drain region 248 in an n channel transistor region 35 . the resist film 246 is then removed . referring to fig9 g , an oxide film is formed by a cvd ( chemical vapor deposition ) method on the overall surface of the silicon substrate 200 having gate electrodes on its surface , and is then subjected to anisotropical etching by an rie ( reactive ion etching ) method . accordingly , sidewalls 250 are formed at peripheries of the gates 212 and 216 in the cmos region 32 and input protection transistor region 36 , and at peripheries of the respective gate electrodes 242 and 244 in the p channel transistor region 33 and n channel transistor region 35 . a resist film 252 is formed on the overall surface of the p channel transistor region 33 . next , arsenic is ion - implanted , employing the resist film 252 , the gates 212 , 216 and 244 in the cmos region 32 , n channel transistor region 35 and input protection transistor region 36 , and the sidewalls 250 at their peripheries as masks . thus , an n + source / drain region 254 is formed in the n channel transistor region 35 , resulting in a so - called ldd structure . at this time , since n + ions are further implanted into the n + source / drain region 206 in the eprom region 32 and input protection transistor region 36 , impurity concentration of regions other than beneath the sidewalls 250 is further increased . implantation of arsenic into molybdenum silicide films 216 and 244 in the eprom region 32 , n channel transistor region 35 and input protection transistor region 36 is useful for planarization of a film to be formed on the films 216 and 244 , as will be described later . the resist film 252 is then removed . with reference to fig9 h , a resist film 256 is formed on the overall surfaces of the eprom region 32 , n channel transistor region 35 and input protection transistor region 36 . boron is then ion - implanted with the resist film 256 , the gate 242 and the sidewalls 250 at their peripheries used as masks . thus , a p + source / drain region 258 is formed in the p channel transistor region 33 . the resist film 256 is then removed . for activation , a heat treatment is then carried out , for example , in nitrogen atmosphere . referring to fig9 i , a bpsg film 260 having a thickness of approximately 1000 å is formed on the whole surface of the silicon substrate 200 by the cvd method . a resist film 262 is formed thereafter on a predetermined region of the bpsg film 260 . etching is then carried out with the resist film 262 used as a mask so as to form contact holes 264 . the resist film 262 is then removed . referring to fig9 j , an al -- si film 266 is formed by sputtering on the bpsg film 260 so as to fill the contact holes 264 . a resist film 268 is then formed on a predetermined region on the al -- si film 266 , and thereafter etching is carried out with the resist film 268 used as a mask . accordingly , an al -- si interconnection layer is formed . the resist film 268 is then removed . with reference to fig9 k , a protection film 270 made of a silicon nitride or a silicon oxide is formed on the whole surface of the silicon substrate 200 . through the foregoing steps , such a semiconductor device is manufactured as to have a double - gate structure in the eprom region 32 and in the input protection transistor region 36 and have an ldd structure in the n - channel transistor region other than the eprom region 32 and input protection transistor region 36 . this manufacturing method makes it possible to simultaneously form the input protection transistor and the memory transistor , through a smaller number of the processing steps than those required for forming the input protection transistor as a single - layered gate separately from the memory transistor , thereby facilitating the manufacture . when source / drain regions are formed in the eprom region 32 and input protection transistor region 36 in the process shown in fig9 g described above , arsenic is also ion - implanted into a molybdenum silicide film 216b of the gate 216 . accordingly , there is an advantage that a flat film can be formed on the molybdenum silicide film 216b as will be describe later . fig1 a - 10e show the changing process , according to the process after fig9 d , of the gate electrode and its peripheries in cross section in case where arsenic is not ion - implanted into the molybdenum silicide film . fig1 a - 11c show the process in cross - section in case where arsenic is ion - implanted into the molybdenum silicide film . the above described advantage will now be described with reference to fig1 a - 10e and 11a - 11c . referring to fig1 a , the gate 216 is exposed . this state of the gate 216 exposed corresponds to the state shown in fig9 d . arsenic is ion - implanted into regions to be source / drain so that ions are not implanted into the gate 216 . then , a heat treatment is carried out for oxidation and activation . accordingly , a silicon oxide film 217 is formed on the surface of the gate 216 , and thus molybdenum silicide of the film 216b is polycrystallized , as shown in fig1 b . next , in order to form sidewalls , a silicon oxide film 219 is formed on the overall surface of the substrate and is then etched by the rie method . this causes sidewalls 250 to be formed at peripheries of the gates 216 and 212 , with the surface of the molybdenum silicide film 216b being exposed , as shown in fig1 c . this state corresponds to the state shown in fig9 g . next , in the step of forming p + source / drain in the p - channel transistor region 33 , when a heat treatment is carried out for oxidation and activation after ion implantation , molybdenum silicide is sublimated as moo 2 , moo 3 , as shown in fig1 d , so that the film 216b becomes thinner , whereby a porous thick silicon oxide film 21 is formed on the molybdenum silicide film 216b with its peripheries built up higher than its central portion . this produces a steep step or a steep configuration at gate portion . when the bpsg film 260 is formed covering the gate portion , as shown in fig1 e , the bpsg film 260 has a steep step portion 260a . therefore , if an al interconnection layer is formed after the formation of bpsg film 260 , an undesired residue al remains at the step portion 260a . referring to fig1 a , as shown in the embodiment of the present invention , if arsenic is ion - implanted into the molybdenum silicide film 216b upon the formation of source / drain regions , molybdenum silicide of a portion 216c of the film 216b is made amorphous . thus , a silicon oxide film 217 is formed uniformly on the molybdenum silicide film 216b as shown in fig1 b . accordingly , as shown in fig1 c , the bpsg film 260 no longer has such a steep step portion as shown in fig1 e , but is well planarized , which thus becomes advantageous for forming a multilayer interconnection . while the semiconductor device having the eprom has been described in the above embodiment , the present invention is not limitative to the eprom but also applicable to any semiconductor devices having the double - layered gate structure . for example , the invention is applicable to an eeprom ( electrically erasable programmable read only memory ). while the p type substrate is employed as the substrate in the above embodiment , an n type substrate may be employed , offering the same effect . although the present invention has been described and illustrated in detail , it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation , the spirit and scope of the present invention being limited only by the terms of the appended claims .