one embodiment of the present invention will now be described with reference to fig6 to 10 . this embodiment , i . e ., an electromagnetic flow meter , is identical with the known flow meter of fig1 except that it uses a timing control circuit 40 shown in fig6 not the timing control circuit shown in fig3 . the circuit 40 is designed so as to generate two switch controlling signals n , s . the signal n controls the switches 12 and 16 both shown in fig1 and the signal s controls the switch 17 shown in fig1 . both signals n and s are pulse signals as shown in fig7 . the signal n has a frequency obtained by dividing 50 hz by an even number . the pulse width of the signals s is 1 / 60 sec . alternatively , the signal n may have a frequency obtained by dividing 60 hz by an even number , and the signal s may have a pulse width of 1 / 50 sec . fig8 shows a timing control circuit for producing a switch controlling signal n whose frequency is 50 / 8 hz and a switch controlling signal s whose pulse width is 1 / 60 sec . this timing control circuit 40 comprises a free - running oscillator 41 , a frequency dividing circuit 44 , a logic circuit comprised of inverters 44a , 44b and nor gates 45a to 45g , a d - type flip - flop 47 and an inverter 47 . the oscillator 41 divides the frequency of a pulse signal generated by , for example , a quartz crystal oscillator , so as to produce a pulse signal p41 of 300 hz which is shown in fig9 . the frequency of this pulse signal p41 is divided by 24 by the frequency dividing circuit 44 . the circuit 44 is comprised of d - type flip - flops 42a to 42c and jk - type flip - flops 43a , 43b the k terminals of which are connected to a high voltage source v dd . the flip - flops 42a to 42c are of the positive edge trigger type and produce q outputs , i . e ., qa , qb , qc which are shown in fig9 . the jk - type flip - flop 43b produces a q output , i . e ., qd which is also shown in fig9 . these outputs qa , qb , qc and qd are supplied to the logic circuit , which generates a switch controlling signal s which is shown in fig9 . this signal s has a frequency of 300 / 24 hz and an on - period of 1 / 60 sec , i . e ., 5 - cycle period of the signal p41 . the signal s is supplied to the d - type flip - flop 46 , which divides the frequency ( i . e ., 300 / 24 hz of the signal s by 2 , thereby generating a switch controlling signal n having a frequency of 50 / 8 hz (= 300 / 48 hz ), which is also shown in fig9 . since the d - type flip - flop 46 is of the positive edge trigger type , the signal s is inverted by the inverter 47 and then supplied to the flip - flop 46 as a clock signal . the nor gates 45c , 45d produce output signals qf and qg , respectively , which are shown in fig9 . since the switches 12 , 16 by the signal n and the switch 17 is controlled by the signal s . the flow rate signal can be sampled for a predetermined period , when the magnetic fluxer become stable , that is , immediately before the switch 12 is changed over . the operation of the electromagnetic flow meter using the timing control circuit 40 shown in fig8 will now be described . when the switch 12 is changed over by the signal n to select the constant current source 13 , a negative voltage will be applied to the output terminal of the ac amplifier 15 . at the same time , the switch 16 is turned on by the signal n and samples the output signal ec from the ac amplifier 15 . on the other hand , when the switch 12 is changed over by the signal n to select the constant current source 14 , the signal ec will be at a positive potential and the output signal from the inverting amplifier 26 will be at a negative potential . in this case , the switch 16 will be connected to the output of the inverting amplifier 16 . in other words , the switch 16 is changed over so a negative voltage is applied to the switch 17 at all times . let us assume that the commercially available ac current of 60 hz is supplied to the coil 3 and that 60 hz - noise is induced in the output signal from the flow rate detector 1 . fig1 ( j ) shows the output signal ec from the ac amplifier 15 , on which the noise is superposed . this noise is integrated for 1 / 60 sec ., i . e ., the one - cycle period of the ac current . hence , any two immediate half waves of the induced noise cancel out each other . therefore , the noise does not adversely influence the output signal ef from the double integration circuit shown in fig1 the waveform of which is illustrated in fig1 ( l ). fig1 ( k ) shows the waveform of the switch controlling signal s . fig1 ( m ) shows the waveform of the output signal eg from the flip - flop 23 . as shown in fig1 ( l ), the output signal ef of the double integration circuit will be represented by the broken lines if it is produced when no noise is superposed on the output signal ec from the ac amplifier 15 . also as shown in fig1 ( l ), the signal ef reaches the same peak voltage upon the completion of the integration , whether or not noise is superposed on the output signal ec from the ac amplifier 15 . as a result , as shown in fig1 ( m ), the flip - flop 23 produces the same output signal eg , whose pulse width is proportional to the flow rate of the fluid , whether or not noise is superposed on the signal ec . now , let us assume that the commercially available ac current of 50 hz is supplied to the coil 3 and that 50 hz noise is induced in the output signal from the flow rate detector 1 . in this case , the output signal ec from the ac amplifier 15 has the waveform as shown in fig1 ( n ). fig1 ( p ) shows the switch controlling signal s . the output signal ef from the double integration circuit has the waveform as illustrated in fig1 ( q ). the broken line in fig1 ( q ) indicates the waveform which the signal ef will have if no noise is superposed on the output signal ec from the ac amplifier 15 . the output signal eg from the flip - flop 23 has the waveform as illustrated in fig1 ( r ). the broken lines shown in fig1 ( r ) represent the waveform of the signal eg which the flip - flop 23 will produce if noise is superposed on the signal ec from the ac amplifier 15 . the pulse width of the signal eg is proportional to the peak voltage which the signal ef reaches upon completion of the integration ( e . g ., sampling ) of the output signal ec from the ac amplifier 15 . while the signal ec is at a positive potential , the output signal from the inverting amplifier 26 is supplied to the double integration circuit shown in fig1 . hence , the influence δn 30 upon the output signal eg from the flip - flop 23 is given as follows : ## equ1 ## where ts is the sampling time ( i . e ., 1 / 60 sec ), k is a constant and θ is the phase of noise at the time of t = 0 . the sign &# 34 ;-&# 34 ; preceding sin ( 100πt + θ ) shows that the output signal of the inverting amplifier 26 has been selected . equation ( 1 ) reduces to the following : ## equ2 ## while the signal ec shown in fig1 ( n ) is at a negative potential , the influence δn - upon the output signal eg from the flip - flop 23 is represented as follows : ## equ3 ## δn + and δn - may have a positive or negative value in accordance with θ . when δn + has a positive value , δn - must have a negative value , and vice versa . nonetheless , the noise does not adversely influence the signal eg since the smoothing capacitor 36 smoothes δn + , δn - as indicated by the following equation : as mentioned above , the timing control circuit 40 of fig8 can remove noise from the output signal ec from the ac amplifier 15 , whichever commercially available ac current is supplied to the flow rate detector 1 , 50 hz - current or 60 hz - current . it should be noted that the logic circuit comprised of the inverters 44a , 44b and nor gates 45a to 45g is designed so as to avoid hazards . if the frequency dividing circuit 44 is comprised of two d - type flip - flops and three jk - type flip - flops and if its frequency division ratio is 1 / 20 , the timing control circuit 40 will then generate a switch controlling signal s whose pulse width is 1 / 50 sec and whose frequency is 60 / 4 hz and a switch controlling signal n whose frequency is 60 / 8 hz . in this case , the sampling period is 1 / 50 sec . when the commercially available 50 hz - current is used as the exciting current , the induced noise will be integrated for the one - cycle period of this current , i . e ., for 1 / 50 sec , and will eventually be removed . on the other hand , when the commercially available 60 hz - current is used , the results of integrating the induced noise for 1 / 50 sec will be given as follows : ## equ4 ## in equations ( 5 ), ( 6 ), ( 7 ), t t is the sampling time , i . e ., 1 / 50 sec . the frequency dividing circuit 44 is not limited to the type comprising d - type flip - flop and jk - type flip - flops . it may comprise other kinds of flip - flops and / or other logic elements . fig1 shows another timing control circuit 40 according to the present invention . this circuit 40 includes an 8 - bit shift register 51 and an 18 - bit shift register 52 . the shift register 51 is a parallel - in / serial - out and serial - in / serial - out one , e . g ., c 2 mos tc4021bp manufactured by toshiba . the shift register 52 may be toshiba &# 39 ; s tc4006bp . the shift registers 51 , 52 are combined to form a 24 - bit shift register . first , an initializing circuit 53 sets the parallel input terminals pi1 to pi5 at the high level and the other parallel input terminals pi6 to pi8 at the low level . the pulse signal is supplied to the shift register 51 from the signal oscillator 41 , whereby the contents of the 24 - bit shift register ( i . e ., the combination of the shift register 51 , 52 ) are shifted to the right every 1 / 300 sec . at the same time , a signal of the &# 34 ; 0 &# 34 ; level is supplied to the serial - in terminal si of the shift register 51 . the signal delivered from the output terminal b 24 of the shift register 52 is used as switch controlling signal s . this signal a falls to the low level upon lapse of 1 / 60 sec (= 1 / 300 sec × 5 ) after it reaches the high level . this falling of the signal s is detected by a serial - in / parallel - in control circuit 54 . upon detecting the signal s , the control circuit 54 sets the shift register 51 to the parallel - in mode . as a result , the parallel input terminals pi1 to p15 of the register 51 are set at the high level again and the parallel input terminals pi6 to pi18 are set at the low level again . the sequence of operations , as described in the preceding paragraph is repeated , thereby to produce a switch controlling signal s whose sampling time is 1 / 60 sec and whose frequency is 50 / 4 hz . the frequency of the signal s is divided by 2 by a d - type flip - flop 46 , which outputs a switch controlling signal n whose frequency is 50 / 8 hz . if the parallel input terminal pi6 of the shift register 51 is set at the high level and the shift registers 51 , 52 are so re - designed to form a 20 - bit shift register , a switch controlling signal s whose sampling time is 1 / 50 sec and whose frequency is 60 / 4 hz will then be generated . this signal s may be frequency - divided by 2 , to thereby providing a switch controlling signal n whose frequency is 60 / 8 hz . further , if the output of the 20 - bit shift register , i . e ., the output terminal b 24 of the shift register 52 , is coupled to the serial - in input terminal si of the shift register 51 , it will be sufficient to input data to the register 51 through the parallel input terminals , only once . thereafter it is unnecessary to input data in parallel fashion . fig1 illustrates a signal oscillator 41 including a phase locked loop circuit 60 . in this oscillator 41 , a comparator 62 compares the output of the commercially available power source 61 with the ground level , thus generating a pulse signal which is synchronous with the ac current from the source 61 . the phase locked loop circuit 60 is operated in synchronism with this pulse signal , thereby producing an output signal of 300 hz . the circuit 60 comprises a phase comparator 601 , a voltage - controlled oscillator 602 , a frequency dividing circuit 603 and a change - over switch 604 . the switch 604 is used to select the frequency division ratio , 1 / 5 or 1 / 6 , for the frequency dividing circuit 603 . owing to the use of the phase locked loop circuit 60 and the fact that the frequency of the ac current is usually stable , the noise can be perfectly removed . the frequency of a commercially available ac current is typically not exactly 50 hz or 60 hz , but fluctuates a little within an allowable range . accordingly , the frequency of the exciting current need not be exactly 50 hz or 60 hz . it can vary within an allowable frequency range of a commercially available ac current ( i . e ., a frequency close to the officially - designated frequency ). we will define such a frequency to be a commercially available frequency . also , the sampling time should not exactly be 1 / 50 s or 1 / 60 s as long as it is the reciprocal of the commercially available frequency of 50 hz or 60 hz . in most of the embodiments described above , the sampling time is 1 / 60 sec and the frequency of the exciting current is 50 / 8 hz . according to the present invention , however , the sampling period and the frequency of the exciting current are not limited to these . even in the case where the sampling time is 1 / 60 sec , the sampling frequency is 50 / q , and the frequency of the exciting current is 50 / 2q , where q is an integer , the noise can be removed whichever commercially available current , 50 hz - current or 60 hz - current , is used as exciting current . similarly , in the case where the sampling time is 1 / 50 sec , the sampling frequency is 60 / q and the frequency of the exciting current is 60 / 2q , the noise can be removed whichever commercially available current , 50 hz - current or 60 hz - current , is used as exciting current .