with reference to the drawings , and particularly to the example of fig2 , a driver circuit according to an embodiment for driving a piezoelectric load 2 is generally and schematically indicated with circuit 1 . the circuit 1 , comprises an operational amplifier 3 having the output in feedback to its inverting input (−) and further coupled to one terminal of the load 2 , in a node x , to supply a current iamp . the other non - inverting (+) input of the amplifier 3 receives a reference signal from an input terminal in of the circuit 1 . this amplifier 3 can be considered as the core of the linear portion of the circuit 1 . the circuit 1 comprises at least a half - bridge circuit portion , including at least a switching device , coupled to the node x through an inductance . more particularly , the circuit 1 further comprises respective half - bridge circuit portions 4 , 5 , each portion being coupled to the node x through a corresponding inductor li , l 2 . the portions 4 , 5 are structurally independent one from the other . the inductors li and l 2 have preferably different value , although it is possible to use inductors having the same value . the half - bridge circuit portion 4 , indicated with lf , is associated to the inductor li with higher value . likewise , the half - bridge circuit portion 5 , indicated with hf , is associated to the inductor l 2 with lower value . a control block 7 is provided to drive the half - bridge circuit portions 4 and 5 . the embodiment of fig2 is aimed at supplying the highest amount of current required by the load 2 by means of the two half - bridges 4 and 5 , while also avoiding frequent switching . the linear , portion 3 therefore supplies the current difference &# 39 ; a mp that is required to follow precisely the voltage reference signal , formed , for instance , by a series of predetermined slew - rate ramps . thus , the half - bridge circuit portions 4 and 5 supply with high efficiency , in the transient and in the steady state respectively , a considerable portion of the overall current required by the load 2 , during which the linear circuit portion 3 ensures the accuracy of the voltage waveform by supplying only the current difference taw , with considerable power saving . as just mentioned , in order to meet the load 2 current demands , the half - bridge portion lf utilizes a switching device . more particularly , the switching device comprises a pair of transistors mi , m 2 are interconnected together in a node x 1 . the half - bridge lf is powered between a first supply voltage reference valim and a second ground reference gnd . the inductor li is inserted between the nodes x 1 and x . in one embodiment , the half - bridge lf comprises mos power transistors ; however , it is also possible to use a bipolar transistor bridge or half - bridge . the control terminals of the half - bridge lf transistors mi and m 2 are coupled to the control block 7 . the control block 7 acts on the transistors mi and m 2 to obtain a current profile as close as possible to the required profile . for this reason , the control block 7 requires information about the duration , the ramp slew - rate and the load cload value . in a similar and symmetrical manner , the half - bridge hf comprises a pair of transistors m 3 , m 4 interconnected together at a node x 2 . the half - bridge hf is powered , in turn , between the first supply voltage reference valim and the second ground reference gnd . the inductor l 2 is inserted between the nodes x 2 and x . the control terminals of the half - bridge hf transistors m 3 and m 4 are all coupled to a respective output of the control block 7 . the use of two half - bridges 4 and 5 allows , by an appropriate strategy for closing the transistor switches incorporated therein , an approximation of the profile of the signal in voltage applied to the load . the lower value inductor l 2 is suitably sized as to be able to follow the initial transient and the current final queue . the half - bridge 4 with higher value inductor li follows the waveform supplying the steady state current value without the need for too frequent switching , which ′ might be required if the half - bridge 5 were used during this phase . the control strategy is important since it determines the efficiency which can be obtained in terms of power dissipation , as well as the switching frequency of half - bridge switches . the control method for the circuit 1 is based on the measurement of the current i mo ) outputted by the operational amplifier 3 and is implemented by dividing the piezoelectric load charge period into three phases . these three method phases are described with reference to the schematic fig3 , 4 and 5 . the diagram of the circuit 1 shown in fig3 , 4 and 5 has been modified to show the current i a mp outputted by the linear portion 3 as variable . a sensor 8 is located downstream of the portion 3 , upstream of the node x and coupled to the control block 7 to detect the current ia mp value ., the control block 7 comprises a logic interface coupled with the current sensor 8 and a digital - technology logic network having analog output stages coupled to the control terminals of the half - bridge 4 and 5 transistors . depending on the value of the current ia mp , the half - bridge devices are switched according to appropriate control strategies described hereinafter . steady state transient , ti : during this phase , the switch mi of the half - bridge lf is closed for the time needed by the current on the inductor li to reach the value io required in the steady condition by the load 2 . in this phase , the switch m 3 of the half - bridge hf is conveniently switched so that the current injected by the system on the load approximates at best that demand , with the aim , once again , of minimizing the amount of current supplied by the linear portion 3 . the control flow is represented by the dot - line 9 . steady state , t 2 : once the current value on the inductor li has reached the steady state value io , the half - bridge hf is deactivated , i . e . the switch m 3 is open . at the same time , the half - bridge lf , through the switch mi control , keeps the output current close to the current required . the control flow is represented by the dot - line 11 . fall phase , t 3 : during this phase , it is necessary to shut the half - bridge lf off so that the inductor li is not charged at a current value other than zero when the current is no longer required by the load 2 . this current would otherwise be absorbed by the linear stage in a dissipating manner . during this phase , the half - bridge hf is activated and follows the fast - changing signals having faster charge and discharge transistors . the control flow is represented by the dot - line 12 . the circuit substantially splits the current necessary to be generated for the load 2 into three distinct parts : ( 1 ) two current peaks supplied by the half - bridge hf in correspondence with the fronts load ; ( 2 ) most of the current in the central portion , in the steady state , supplied by the half - bridge lf ; and ( 3 ) a corrective current supplied by the linear portion 3 . fig6 shows graphical plots of the currents injected by the two half - bridges , ilf for the bridge lf and ihf for the bridge hf , of the current ia mp supplied by the operational and of &# 39 ; load required by the load 2 . for implementing the control method according to an embodiment , two procedures are used : a feedback and a feed - forward procedure . the times t 1 and t 3 are derived analytically . in feed - forward mode , once the inductor li value , the voltage supply valjm , the load value c load , the slew - rate and the initial and final ramp voltages are known , the times t 1 and t 3 can be ascertained the feedback variable used in the diagram is represented , on the contrary , by the current iamp outputted by the linear stage . depending on this current iamp value , the stage lf is switched during the phase t 2 and the stage hf during the phases t 1 and t 3 , according to the criteria described hereinafter . the feedback variable iamp may be controlled in several ways . for example , the transistor m 1 can be opened at predetermined times and closed again when the current ia mp exceeds a predetermined threshold . a different control scheme provides the use of a hysteresis loop . in this control scheme for example , when the current outputted by the linear portion 3 exceeds an appropriate threshold &# 39 ; mom the switch m 1 or m 3 of the half - bridge lf or hf coupled to the supply is closed and , consequently , the current outputted by the non - linear portion increases , whereas the current ia mp of the linear portion decreases until the latter reaches a lower threshold &# 39 ; low at which the switch m 1 or m 3 is opened , thus repeating the cycle . in this way the hysteresis type of control is : the outcome of this control and the corresponding waveforms are shown in fig7 for a time period indicated with t 2 at which the feedback variable acts on the half - bridge lf . during the times indicated with t * the switch mi is closed since the operational 3 current is higher than the value &# 39 ; low . the switch m 1 is closed until the threshold low is reached . the ih ys t value choice is a compromise - choice . a small value results in a high half - bridge switching speed whereas a high value results in a higher dissipation by the linear portion . the previous comments are based on the use of a single feedback variable acting on the two half - bridges lf and hf in time - distinct phases . fig8 shows schematically a different embodiment illustrating the possibility of measuring a second quantity in addition to the linear portion current ia mp . in this embodiment , a second current sensor 9 inserted between the inductor l 2 and the node x is provided . therefore , if another quantity is measurable through the second sensor 9 , this quantity can be so used as to control both half - bridges . knowing , for example , the current outputted by the half - bridge hf , &# 39 ; amp could be used as variable for controlling both the switching of the half - bridge hf during the whole period and the sum iamp ihf ( equal to i load - i lf ) to drive the lf stage . the manner for determining the three times t 1 , t 2 , and t 3 in an analytical manner will now be described . the following formulas , obtained analytically , allow a real time calculation of said times during the load 2 control phase to be achieved . another method for formulating the differential equation which determines the time pattern of the inductor current can be used in other embodiments . a finite difference equation is determined in which the current value , in a precise instant , is given by the sum of the value , in the previous instant plus an increase depending on the voltage present at the inductor terminals . through simple addition using accumulating circuit blocks , it is possible to calculate the inductor current and assess ( as clock stroke number ) the time required by the current to reach the steady state value io , thus obtaining ti . likewise , it is possible to calculate t 3 by inverting the time scale . if the inductor starts from a current value equal to zero and reaches the steady state value io , it is possible to obtain a transient having the same duration as the discharge transient t 3 by using a voltage signal which is time - inverted with respect to the signal required . in this case too , simple addition using accumulating circuit blocks are sufficient for the assessment . fig1 and 14 show respective embodiments of circuit networks comprising adding and accumulating blocks which can be used for the above purposes . fig1 shows a circuit for calculating the time ti . the current in value is compared with the current io value , t 1 being reached when these values coincide . fig1 shows a circuit for calculating the time t 3 . the current in value is compared with the current io value , t 3 being reached when these values coincide . from the control point of view , four different situations shown in fig9 , 10 , 11 and 12 can occur . the cases shown in fig1 and 11 require a special control . in the case of fig1 , the time t 3 is known later than the moment of its use for shutting the half - bridge lf off . this occurs because the algorithm does not produce the desired results in the instant of their application . in the case of fig1 , the current is so high that the sum of times t 1 and t 3 is higher than the ramp duration , the assessment being , therefore , useless for control purposes . in both cases , it is useful to know a time tx defined as the instant of intersection between the charge and discharge currents of the inductor li . the time tx allows the inductor li charge to be interrupted so that no residual current is present at the ramp end , the current being otherwise recovered by the linear stage , with subsequent detrimental power dissipation . steady state rise time for the inductor li , i . e . the time required by li to reach the current theoretic value ( src ): discharge time required to let the inductor li have no residual current at the ramp end : rise ramp : time t 1 calculation : at the inductor li terminals ( l indicating the inductor li value ) the following differential equation applies : v l = v alim - v c = l · ⅆ i ⅆ t δ ⁢ ⁢ ⅈ t cl = v alim - v c l by solving it in a discrete form also the voltage at the capacitive load terminals : time t 3 calculation : to calculate the discharge time , when the inductor passes from a current io to a current equal to zero at the real end of the voltage ramp , assuming to be in said last instant and to go back in time till the instant t 3 when the current io flows through the inductor , it is evident that ( by applying the variable replacement t == r ) that the system is analogue to another one being advanced in time , but with negative voltage ramp , in formulas : l · ⅆ i ⅆ i = - v d - v c ⁡ ( t ) with v c ⁡ ( t ) = v f + sr · t the previous equation with negative t is equivalent to the following one with positive t : l · ⅆ i ⅆ i = v d + v c ⁡ ( t ) with v c ⁡ ( t ) = v f - sr · t δ ⁢ ⁢ i t cl = v c - v c l by solving the voltage value in a discrete form at the capacitive load terminals : sr = v f - v o t on sr = v f - v o n on · t cl sr _ = v f - v o n on and sr = sr _ t cl from the foregoing description , it will be appreciated that , although specific embodiments have been described herein for purposes of illustration , various modifications may be made without deviating from the spirit and scope of the present disclosure . accordingly , the present disclosure is not limited except as by the appended claims .