one embodiment of a frequency doubler constructed in accordance with the teachings of this invention is shown in the schematic diagram of fig1 . frequency doubler 10 includes input terminal 11 for receiving an input signal v in having a frequency f . frequency doubler 10 also includes output terminal 24 for providing an output voltage v out having a frequency 2f , double the frequency of the input voltage v in . the input signal v in is shown in graphical form in fig2 and is typically within the range of approximately 500 hz to 3 khz and has a duty cycle within the range of approximately 30 % to 70 %. input signals having higher frequencies can be used , and thus higher frequency output signals provided , if desired . the input signal v in is directly applied to one input lead of exclusive or gate 13 . input voltage v in is also applied to the input lead 12a of delay means 12 , whose output lead 12b is connected to the other input lead of exclusive or gate 13 . delay means 12 may comprise any suitable delay means , including a chain of inverters with capacitive loading on their output , as is shown in fig7 . in one embodiment of this invention , delay means 12 delays the input signal v in by a few microseconds prior to applying the delayed input signal to the second input lead of exclusive or gate 13 . it is generally desired that the delay provided by delay means 12 be sufficient to allow nor gate 14 to charge its output lead to the negative supply voltage in order to provide a logical zero output signal . exclusive or gate 13 thus provides an output voltage v49 ( as shown in fig3 ) on output node 49 . as can be seen from fig3 v49 goes high for a short period of time ( approximately equal to the time delay provided by delay means 12 ) in response to each rising and falling edge of input signal v in . thus , signal v49 has a frequency 2f , twice the frequency of input voltage v in . however , signal v49 generally does not have a 50 % duty cycle , as is often desired , but has a duty cycle of the remainder of the circuit shown in fig1 serves to provide an output signal v out having a frequency of 2f , and which has a 50 % duty cycle . terminal 15 is connected to a positive supply voltage vdd ( typically 5 volts ). switches 16 and 18 , together with capacitor 20 , serve as a switched capacitor resistor equivalent . in the embodiment of this invention shown in fig1 switches 16 and 18 are n channel mos transistors being controlled by clock signals φ and φ , respectively . switched capacitor resistor equivalents are well known in the prior art and thus will not be described in detail in this application . a more complete description of the q operation of a switched capacitor resistor equivalent is given by b . j . hostica , r . w . brodersen , p . r . gray , in &# 34 ; mos sampled data recursive filters using switched capacitor integrators &# 34 ;, ieee journal of solid state circuits , december 1977 , pps . 600 - 609 , which is hereby incorporated by reference . clock signals φ and φ preferably have a frequency fφ within the range of approximately 10 khz to 500 khz where the input signal has a frequency within the range of approximately 1 khz to 50 khz . the switched capacitor resistor equivalent formed by switches 16 and 18 and capacitor 20 serves to charge capacitor 21 to supply voltage vdd with time constant ( c21 / c20 ) fφ . c21 is the capacitance of capacitor 21 ( typically approximately 20 picofarads ); c20 is the capacitance of capacitor 20 ( typically approximately 1 picofarad ); and in one embodiment of this invention , a resistor is used in place of switches 17 , 19 and capacitor 20 . this embodiment requires more area and provides less yield due to greater variations in resistance ( where the circuit is implemented using mos technology ) and thus greater variations in the resulting time constant . the voltage v50 thus generated on terminal 50 is shown in fig4 . capacitor 21 is discharged when nor gate 14 provides a logical zero output signal which occurs in one instance in response to a logical one output signal from exclusive or gate 13 . thus , when v49 goes high , the output signal of nor gate 14 goes low and voltage v50 follows this and is discharged as shown in fig4 . voltage comparator 22 has its inverting input lead connected to node 50 and its noninverting input lead connected to the output lead of operational amplifier 27 . the output signal v51 from comparator 22 , which appears on node 51 , is positive ( logical 1 ) when v50 is discharged to a value less than the voltage which is provided on the output lead of operational amplifier 27 . the output lead of operational amplifier 22 is connected to the input lead of inverter 23 , whose output lead is connected to output terminal 24 to provide the output signal v out and , through resistor 25 , to the noninverting input lead of operational amplifier 27 . capacitor 26 is connected between the noninverting input lead of operational amplifier 27 and ground . resistor 28 is connected between ground and the inverting input lead of operational amplifier 27 , and resistor 29 is connected between the inverting input lead of operational amplifier 27 and the output lead of operational amplifier 27 , thereby causing operational amplifier 27 to have a closed loop gain of g = the closed loop gain of operational amplifier 27 ( typically 1 to 10 ); capacitor 26 integrates the output voltage v out , and operational amplifier 27 provides an amplified signal equal to g ∫ v out dt to the noninverting input lead of operational amplifier 22 . for stability , the voltage on the output lead of operational amplifier 27 should be relatively constant . this requires that the result of the integration v out dt when v out is high equal the result of the integration of v out dt when v out is low . if this were not so , net current would flow into the integrator and change the output voltage . by providing the negative feedback through operational amplifier 27 , the output signal v out maintains a 50 % duty cycle . for example , if the output signal v out has a duty cycle less than 50 % such that during each cycle v out remains a logical 0 longer than it remains a logical 1 , the voltage stored on capacitor 26 will be less than when the duty cycle of v out is 50 %. with this decreased voltage applied to the noninverting input lead of operational amplifier 27 , operational amplifier 27 provides a decreased output voltage to the noninverting input lead of operational amplifier 22 . the output signal v51 from operational amplifier 22 is a logical 0 when the voltage v50 is greater than the output voltage of operational amplifier 27 , thereby causing v51 to have a logical 0 value for a greater period of time , which in turn causes the output signal v out to have a logical 1 output signal for an increased period of time . conversely , if the output signal v out has a duty cycle greater than 50 % such that during each cycle v out remains a logical 1 longer than it remains a logical 0 , the voltage stored on capacitor 26 will be greater than when the duty cycle of v out is 50 %. with this increased voltage applied to the noninverting input lead of operational amplifier 27 , operational amplifier 27 provides an increased output voltage to the noninverting input lead of operational amplifier 22 . the output signal v51 from operational amplifier 22 is a logical 0 when the voltage v50 is greater than the output voltage of operational amplifier 27 , thereby causing v51 to have a logical 0 value for a greater period of time , which in turn causes the output signal v out to have a logical 1 output signal for a increased period of time . in this manner , the feedback provided by operational amplifier 27 provides output signal v out with a 50 % duty cycle . in an alternative embodiment of my invention , it is desired to provide an output signal v out having other than a 50 % duty cycle . in this embodiment of my invention integrator 127 ( fig1 ) is replaced with integrator 227 of fig8 . integrator 227 of fig8 is the same as integrator 127 of fig1 with the addition of inverter 29 and buffer 30 . inverter 29 is an inverter receiving as its input lead the output signal from operational amplifier 27 . buffer 30 is an inverter receiving on its input lead the output signal from inverter 29 , and which provides an output signal on output lead 27 - 1 to the noninverting input lead of operational amplifier 22 ( fig1 ). buffer 30 is powered by a positive reference voltage + vref and a negative reference voltage - vref which are generated in any one of a number of ways well known in the prior art . the magnitudes of + vref and - vref are selected to provide the desired duty cycle of the output signal v out provided on output lead 24 ( fig1 ). thus , the duty cycle is defined as : thus , if a 60 % duty cycle is desired , the magnitude of vref must be 1 . 5 times the magnitude of - vref . conversely , if a 25 % duty cycle is desired , the magnitude of + vref must be one - third the magnitude of - vref . the specific embodiments of this invention described in this specification are intended to serve by way of example and are not a limitation on the scope of my invention . numerous other embodiments of this invention will become apparent to those of ordinary skill in the art in light of the teachings of this specification .