reference will now be made in detail to the preferred embodiments of the present invention , examples of which are illustrated in the accompanying drawings . wherever possible , the same reference numbers will be used throughout the drawings to refer to the same or like parts . a method for making a mask in a process of fabricating a semiconductor device according to one embodiment of the present invention will be described with reference to fig4 to fig6 . first , as shown in fig4 , one input database is divided into an sram block 100 and a random logic block 102 . then , target bit cell 10 as shown in fig2 are extracted from the sram block 100 , and opc is performed for the extracted target bit cell 10 . more than one target bit cell 10 can undergo opc 10 . the result from the opc process for the extracted target bit cells 10 is shown in fig5 . referring to fig6 , target bit cells 20 in which opc has been performed are repeatedly arranged to reform an sram block 200 . a random logic block ( not shown ) in which opc has been performed is added to the sram block 200 . in other words , the input database is divided into the sram block 100 and the random logic block 102 so that opc is separately performed for the sram block 100 and the random logic block 102 , thereby improving performance of the opc . however , although performance of the opc is improved in the above embodiment , opc is performed for a line end portion 25 of the target bit cell 20 as shown in fig5 . if the target bit cells 20 in which opc has been performed are repeatedly arranged to form the sram block 200 , undesired opc is performed for the line end portion 25 where the target bit cells 20 are connected to one another . that is , opc is performed for an undesired portion , i . e ., the line end portion 25 , as the line end portion 25 is recognized as some of an extension line without being recognized as the line end . in the another exemplary embodiment of the present invention , dummy bit cells are provided at both sides of the target bit cell 20 so as to perform opc for only the target bit cell 20 , excluding the line end portion 25 of the target bit cell 20 . this will be described in detail with reference to fig7 to fig9 . first , the target bit cells 10 are extracted from the sram block 100 . then , as shown in fig7 , dummy bit cells 10 a and 10 b are connected to both sides of the extracted target bit cell 10 . in the exemplary embodiment of the present invention , to easily remove the dummy bit cells 10 a and 10 b from the target bit cell 10 after opc , the dummy bit cells 10 a and 10 b have layers different from those of the target bit cell 10 . at this time , the dummy bit cells 10 a and 10 b have layers different from those of the target bit cell 10 , but may have the same layers as one another . alternatively , the bit cells 10 , 10 a and 10 b may have different layers from one another . furthermore , to connect the dummy bit cells 10 a and 10 b to the target bit cell 10 , the target bit cells 10 have connecting portions at both sides . however , since the dummy bit cells 10 a and 10 b are connected to any one side of the target bit cell 10 , the connecting portion may be formed on either side . next , opc is simultaneously performed for the target bit cell 10 and the dummy bit cells 10 a and 10 b . in this case , if opc is performed for only the target bit cell 10 , it is possible to prevent opc from being performed for the line end portion 25 . referring to fig8 , after opc is performed for the target bit cell 10 and the dummy bit cells 10 a and 10 b , the dummy bit cells 10 a and 10 b are removed from the target bit cell 10 . it is noted that opc has not been performed for both sides 55 of target bit cell 50 shown in fig8 , unlike the target bit cell 20 shown in fig6 . afterwards , as shown in fig9 , the target bit cells 50 in which opc has been performed are repeatedly arranged to reform the sram block 200 . unlike the sram block 200 shown in fig6 , in the sram block 300 shown in fig9 , opc is not performed for the portions 55 where the respective target bit cells 50 are connected to each other . finally , the reformed sram block 300 is connected to a random logic block ( not shown ) in which opc has been performed . in the aforementioned exemplary embodiment , the dummy bit cells are connected to both sides of the target bit cell . in another exemplary embodiment , the dummy bit cells may be connected to only one side of the target bit cell . in this case , the dummy bit cells can have layers different from those of the target bit cell . if the target bit cell are connected to one dummy bit cell , a connecting portion may be formed only at either side of the target bit cell . in the present invention , since one database is divided into the sram block and the random logic block so as to separately perform opc for the sram block and the random logic block , it is possible to improve performance of the opc . as a result , it is possible to maximize pattern fidelity and reduce the turn around time ( tat ) required for the manufacture of the mask . in addition , since opc is simultaneously performed for the target bit cell and the dummy bit cells after the dummy bit cells are connected to the target bit cell , it is possible to prevent opc from being performed for the portion where the respective target bit cell are connected to each other when the sram block is formed . it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions . thus , it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents .