the many embodiments of the present invention , its advantages and concepts as related to the method for refreshing a flash memory are best understood by referring to the figures . the following definitions are provided to promote understanding of the invention . a . sensing ratio — sa ( sense amplifier ) signal voltage divided by rwl ( read wordline ) voltage i . v [( icell - 0 ) x ( x )]— converted voltage of a cell current of a charge loss cell using sensing ratio 1 : x ( x & gt ; 1 ) j . v [( icell - 1 ) x ( y )]— converted voltage of a cell current of a charge gain cell using sensing ratio 1 : y ( y & lt ; 1 ) k . v [( iref ) x ( x )]— converted voltage of a reference cell current using sensing ratio 1 : x ( x & gt ; 1 ) 1 . v [( ire ) x ( y )]— converted voltage of a reference cell current using sensing ratio 1 : y ( y & lt ; 1 ) fig1 is a diagram of the flash high vt ( threshold voltage ) and the low vt read margin . the high vt design parameters are defined by data retention , temperature effect , sensing deficiency , array effect and initial drop . the program margin ( pm ) is the total sum of the high vt design parameters . the low vt design parameters are defined by charge gain , temperature effect , sensing deficiency , and 2 nd bit effect and cycle margin . the erase margin ( em ) is the total sum of low vt design parameters . fig2 - 4 show schematic diagrams for the sensing ratio at the cell side of the flash memory where fig2 judges the high vt charge loss cells , fig3 judges the low vt charge gain cells , and fig4 judges both high vt charge loss cells and low voltage charge gain cells . fig2 - 4 show i - v converters that directly convert the cell current to a voltage . fig5 shows a graph for the sa signal voltage versus the wl voltage for sensing ratios a , b and c of fig2 - 4 . for example , the sensing ratio for a is 1 : 1 , b is 1 : x ( x & gt ; 1 ) where x equals 2 , and c is 1 : y ( y & lt ; 1 ) where y equals ⅔ . fig6 - 8 show the schematic diagrams for the sensing ratio at the reference cell side of the flash memory where fig6 judges the high vt charge loss cells , fig7 judges the low vt charge gain cells , and fig8 judges both the high vt charge loss cells and low vt charge gain cells . fig9 shows the graph for the sa ( sense amplifier ) signal voltage versus rwl ( read wordline ) voltage for sensing ratios a , b and c of fig6 - 8 . for example , the sensing ratio for a is 1 : 1 , b is 1 : x ( x & gt ; 1 ) where x equals 3 / 2 , and c is 1 : y ( y & lt ; 1 ) where y equals ½ . fig1 shows the i - v graph for the sa signal and fig1 shows the flow diagram for the sensing ratio for “ 0 ” charge loss cells refreshing by using a cell side sensing ratio . the i - v graph shows transfer characteristic for programmed and initial or erased states . fig1 shows a method that begins by reading the cell using a constant gate voltage , vg , then it uses sensing ratio a ( 1 : 1 ) to judge the cell for “ 0 ”/ high vt or “ 1 ”/ low vt , by determining v [ icell - 1 ]& gt ; v [ iref ]& gt ; v [ icell - 0 ]. if it finds v [ icell ] is higher than v [ iref ], another test determines if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , it reads the next cell and starts over . however , if v [ icell ] is lower than v [ iref ], then sensing ratio b ( 1 : x , x & gt ; 1 ) judges the cell for “ 0 ”/ high vt by determining v [ iref ]& gt ; v [( icell - 0 ) x ( x )] indicating a normal “ 0 ” bit or v [ iref ]& lt ; v [( icell - 0 ) x ( x )] indicating a charge loss bit , that needs refreshing . fig1 shows the i - v graph for the sa signal and fig1 shows the flow diagram for the sensing ratio for “ 1 ” charge gain cells refreshing by using cell side sensing ratio . fig1 shows a method that begins by reading the cell using a constant gate voltage , vg , then it uses sensing ratio a ( 1 : 1 ) to judge the cell for “ 0 ”/ high vt or “ 1 ”/ low vt , by determining v [ icell - 1 ]& gt ; v [ iref ]& gt ; v [ icell - 0 ]. if it finds that v [ icell ] is lower than v [ iref ], another test determines if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , it reads the next cell and starts over . however , if v [ icell ] is higher than v [ iref ], then sensing ratio c ( 1 : y , y & lt ; 1 ) judges the cell for “ 1 ”/ low vt by determining v [ iref ]& lt ; v [( icell - 1 ) x ( y )] indicating a normal “ 1 ” bit or v [ iref ]& gt ; v [( icell - 1 ) x ( y )] indicating a charge gain bit , that needs refreshing . if sensing ratio c determines v [( icell - 1 ) x ( y )] is higher than v [ iref ], a test is done to determine if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , the method starts again for the next cell . however , if sensing ratio c determines v [( icell - 1 ) x ( y )] is lower than v [ iref ], it reads data from the refresh unit ( ru ) to memory , then it erases the ru , then programs the ru with data from memory and finishes . fig1 shows a flow diagram for both “ 1 ” charge gain cells and “ 0 ” charge loss cells refreshing by using a cell side sensing ratio . the method begins by using a constant gate voltage , vg , and the sensing ratio a ( 1 : 1 ) judges v [ icell ]& gt ; v [ iref ]. if v [ icell ] is lower than v [ iref ], then sensing ratio b ( 1 : x , x & gt ; 1 ) judges v [( icell - 0 ) x ( x )]& gt ; v [ iref ]. if v [( icell - 0 ) x ( x )] is lower than v [ iref ], another test is done to check if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , it reads the next cell and the method starts over . however , if v [( icell - 0 ) x ( x )] is greater than v [ iref ], it refreshes and reprograms the cell . then it tests the cell for the last cell . if the sensing ratio a ( 1 : 1 ) finds v [ icell ] is higher than v [ iref ], then sensing ratio c ( 1 : y , y & lt ; 1 ) judges v [( icell - 1 ) x ( y )]& gt ; v [ iref ]. if v [( icell - 1 ) x ( y )] is higher than v [ iref ], a test is done to determine if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , it reads the next cell with a constant gate voltage , vg , and starts sensing ratio a again . if v [( icell - 1 ) x ( y )] is lower than v [ iref ], it reads data from the refresh unit ( ru ) to memory , then it erases the ru , then programs the ru with data from memory and finishes . fig1 shows the i - v graph for the sa signal and fig1 shows the flow diagram for the “ 0 ” charge loss cells refreshing by using a reference cell side sensing ratio . fig1 shows a method that begins reading the cell by using a constant gate voltage , vg , then sensing ratio a ( 1 : 1 ) judges the cell for “ 0 ”/ high vt or “ 1 ”/ low vt by determining v [ icell - 1 ]& gt ; v [ iref ]& gt ; v [ icell - 0 ]. if v [ icell ] is higher than v [ iref ], another test determines if this is the last cell . if it is the last cell , the method finishes . if the test finds it is not the last cell , it reads the next cell and starts over . however , if v [ icell ] is lower than v [ iref ], then sensing ratio c ( 1 : y , y & lt ; 1 ) judges the cell for “ 0 ”/ high vt cell by determining v [( iref ) x ( y )]& gt ; v [( icell - 0 )] indicating a normal “ 0 ” bit or v [( iref ) x ( y )]& lt ; v [( icell - 0 )] indicating a charge loss bit , that needs refreshing . fig1 shows the i - v graph for the sa signal and fig1 shows the flow diagram for the “ 1 ” charge gain cells refreshing by using a reference cell side sensing ratio . fig1 shows a method that begins by reading the cell using a constant gate voltage , vg , then sensing ratio a ( 1 : 1 ) judges the cell for “ 0 ”/ high vt or “ 1 ”/ low vt by determining v [ icell - 1 ]& gt ; v [ iref ]& gt ; v [ icell - 0 ]. if v [ icell ] is lower than v [ iref ], another test determines if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , it reads the next cell and starts over . however , if v [ icell ] is higher than v [ iref ], then sensing ratio b ( 1 : x , x & gt ; 1 ) judges the cell for “ 1 ”/ low vt cell , by determining v [( iref ) x ( x )]& lt ; v [( icell - 1 )] indicating a normal “ 1 ” bit or v [( iref ) x ( x )]& gt ; v [( icell - 1 )] indicating a charge gain bit , that needs refreshing . if sensing ratio b determines v [( icell - 1 )] is higher than v [( iref ) x ( x )], a test is done to determine if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , the method starts again for the next cell . however , if sensing ratio b determines v [( icell - 1 )] is lower than v [( iref ) x ( x )], it reads the data from the refresh unit ( ru ) to memory , then it erases the ru and programs the ru with data from memory then finishes . fig1 show a flow diagram for both “ 1 ” charge gain cells and “ 0 ” charge loss cells refreshing using the reference cell side sensing ratio . the method begins by using a constant gate voltage , vg . next sensing ratio a ( 1 : 1 ) judges v [ icell ]& gt ; v [ iref ]. if v [ icell ] is lower than v [ iref ], then sensing ratio c ( 1 : y , y & lt ; 1 ) judges v [( icell - 0 )]& gt ; v [( iref ) x ( y )]. if v [( icell - 0 )] is lower than v [( iref ) x ( y )], another test is done to check if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , it reads the next cell and the method starts over . however , if v [( icell - 0 )] is greater than v [ iref ], then the algorithm refreshes and reprograms the cell . then it tests this cell for the last cell . if the sensing ratio a ( 1 : 1 ) finds v [ icell ] is higher than v [ iref ], then sensing ratio b ( 1 : x , x & gt ; 1 ) judges v [( icell - 1 )]& gt ; v [( iref ) x ( x )]. if v [( icell - 1 )] is higher than v [( iref ) x ( x )], a test determines if this is the last cell . if it is the last cell , the method finishes . if v [( icell - 1 )] is lower than v [( iref ) x ( x )], it reads data from the refresh unit ( ru ) to memory , then it erases the ru and programs the ru with data from memory then finishes . fig2 - 22 show the sensing ratio at the reference cell side of the flash memory , where fig2 judges the high vt charge loss cells , fig2 judges the low vt charge gain cells and fig2 judges both high vt charge loss cells and low voltage charge gain cells . fig2 - 22 show i - v converters that directly convert the cell current to a voltage . fig2 shows a graph for the sa signal voltage versus the rwl voltage for sensing ratios a , b and c for fig2 - 22 . for example , iref - re =( 3 / 2 ) x ( iref ) and iref - r =( ½ ) x ( iref ). fig2 shows the i - v graph for the sa signal and fig2 shows the flow diagram for the reference cell for “ 0 ” charge loss cell refreshing . the flow diagram in fig2 , shows the method begins by reading the cell using a constant gate voltage , vg , then the iref cell judges the cell for “ 0 ”/ high vt or “ 1 ”/ low vt by determining v [ icell - 1 ]& gt ; v [ iref ]& gt ; v [ icell - 0 ]. if v [ icell ] is higher than v [ iref ], then another test determines if this is the last cell . if it is the last cell , the method finishes . if the test determines it is not the last cell , it reads the next cell and starts over . however , if v [ icell ] is lower than v [ iref ], then iref - r cell judges the cell for “ 0 ”/ high vt cells by determining v [ iref - r ]& gt ; v [( icell - 0 )] indicating a normal “ 0 ” bit or v [ iref - r ]& lt ; v [( icell - 0 )] indicating a charge loss bit , that needs refreshing . fig2 - 22 show i - v converters that directly convert the cell current to a voltage . fig2 shows the i - v graph for the sa signal and fig2 shows the flow diagram for “ 1 ” charge gain cells refreshing . the flow diagram in fig2 , shows the method begins by reading the cell using a constant gate voltage , vg , then the iref cell judges the cell for “ 0 ”/ high vt or “ 1 ”/ low vt by determining v [ icell - 1 ]& gt ; v [ iref ]& gt ; v [ icell - 0 ]. if v [ icell ] is lower than v [ iref ], another test determines if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , it reads the next cell and starts over . however , if v [ icell ] is higher than v [ iref ], then iref - re cell judges the cell for “ 1 ”/ low vt cell by determining v [ iref - re ]& lt ; v [( icell - 1 )] indicating a normal “ 1 ” bit or v [ iref - re ]& gt ; v [( icell - 1 )] indicating a charge gain bit , that needs refreshing . if iref - re cell determines v [( icell - 1 )] is higher than v [ iref - re ], a test determines if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , the method starts again for the next cell . however , if iref - re cell determines v [( icell - 1 )] is lower than v [ iref - re ], it reads the data from the refresh unit ( ru ) to memory , then it erases the ru and programs the ru with data from memory then finishes . fig2 shows a flow diagram for a reference cell for both “ 1 ” charge gain cell and “ 0 ” charge loss cell refreshing . the method begins by using a constant gate voltage , vg , then the iref cell judges v [ icell ]& gt ; v [ iref ]. if v [ icell ] is lower than v [ iref ], then iref - r cell judges v [( icell - 0 )]& gt ; v [ iref - r ]. if v [( icell - 0 )] is lower than v [ iref - r ], another test determines if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , it reads the next cell and the method starts over . however if v [( icell - 0 )] is greater than v [ iref - r ], the algorithm refreshes and reprograms the cell . then it tests the cell for the last cell . if v [ icell ] is higher than v [ iref ], then iref - re cell judges v [( icell - 1 )]& gt ; v [ iref - re ]. if v [( icell - 1 )] is higher than v [ iref - re ], a test determines if this is the last cell . if it is the last cell , the method finishes . if v [( icell - 1 )] is lower than v [ iref - re ], it reads the data from the refresh unit ( ru ) to memory , then it erases the ru and programs the ru with data from memory then finishes . fig2 - 32 show schematic diagrams for current mirrors at the reference cell side of the flash memory where fig2 judges the high vt charge loss cell , fig3 judges the low vt charge gain cell and fig3 judges both high vt charge loss cell and low vt charge gain cell . fig3 shows a graph for the sa signal voltage versus the rwl voltage for current mirrors a , b and c for fig2 - 31 . for example , the reference current is iref , and if x = 3 / 2 , iref - b =( 3 / 2 ) x ( iref ) and if y = ½ , iref - c =( ½ ) x ( iref ). fig3 - 36 show the current mirror at the cell side of the flash memory where fig3 judges the high vt charge loss cell , fig3 judges the low vt charge gain cell and fig3 judges both high vt charge loss cell and low voltage charge gain cell . fig3 shows a graph for the sa signal voltage versus the wl voltage for current mirrors a , b and c of fig3 - 35 . for example , the cell current is icell , if x = 2 , cell current = 2x ( icell ) and if y = ⅔ , cell current =( ⅔ ) x ( icell ). fig3 shows the i - v graph for the sa signal and fig3 shows the flow diagram for “ 0 ” charge loss cell refreshing and using a current mirror on the reference cell side . fig3 begins by reading the cell by using a constant gate voltage , vg , then current mirror a judges the cell for “ 0 ”/ high vt or “ 1 ”/ low vt by determining v [ icell - 1 ]& gt ; v [ iref ]& gt ; v [ icell - 0 ]. if v [ icell ] is higher than v [ iref ], another test determines if this is the last cell . if it is the last cell , the method finishes . if the test determines it is not the last cell , it reads the next cell and starts over . however , v [ icell ] is lower than v [ iref ], then current mirror c judges the cell to determine the “ 0 ”/ high vt cell by determining v [ iref - c ]= v [( iref ) x ( y )]& gt ; v [ icell - 0 ] indicating a normal “ 0 ” bit or v [ iref - c ]= v [( iref ) x ( y )]& lt ; v [ icell - 0 ] indicating a charge loss bit , that needs refreshing . for example , current mirror a uses iref and for y = ½ , current mirror c reference current equals iref - c =( ½ ) xiref . fig3 shows the i - v graph for the sa signal and fig4 shows the flow diagram for “ 1 ” charge gain cell refreshing using a current mirror at reference cell side . fig4 shows a method that begins by reading the cell using a constant gate voltage , vg , then current mirror a judges the cell for “ 0 ”/ high vt or “ 1 ”/ low vt by determining v [ icell - 1 ]& gt ; v [ iref ]& gt ; v [ icell - 0 ]. if v [ icell ] is lower than v [ iref ], another test determines if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , it reads the next cell and starts over . however , if v [ icell ] is higher than v [ iref ], then current mirror b judges the cell for “ 1 ”/ low vt cell by determining v [ iref - b ]= v [( iref ) x ( x )]& lt ; v [ icell - 1 ] indicating a normal “ 1 ” bit or v [ iref - b ]= v [( iref ) x ( x )]& gt ; v [ icell - 1 ] indicating a charge gain bit , that needs refreshing . if current mirror b determines v [( icell - 1 )] is higher than v [ iref - b ], a test determines if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , the method starts over for the next cell . however , if v [( icell - 1 )] is lower than v [ iref - b ], it reads the data from the refresh unit ( ru ) to memory , then it erases the ru and programs the ru with data from memory then finishes . fig4 shows a flow diagram for both “ 1 ” charge gain cell and “ 0 ” charge loss cell refresh using a current mirror at the reference cell side . the method begins by using a constant gate voltage , vg , then current mirror a judges v [ icell ]& gt ; v [ iref ]. if v [ icell ] is lower than v [ iref ], then current mirror c judges v [( icell - 0 )]& gt ; v [ iref - c ]. if v [( icell - 0 )] is lower than v [ iref - c ], another test determines if this is the last cell . if it is the last cell , the method finishes . if it is not the last cell , it reads the next cell and the method starts over . however if v [( icell - 0 )] is greater than v [ iref - c ], it refreshes and reprograms the cell . then it tests the cell for the last cell . if v [ icell ] is higher than v [ iref ], then current mirror b judges v [( icell - 1 )]& gt ; v [ iref - b ]. if v [( icell - 1 )] is higher than v [ iref - b ], a test determines if this is the last cell . if it is the last cell , the method finishes . if v [( icell - 1 )] is lower than v [ iref - b ], it reads the data from the refresh unit ( ru ) to memory , then it erases the ru and programs the ru with data from memory then finishes . fig4 shows a sector mapping of a flash memory containing 256 sectors having 1 mbits per sector . it shows that each sector contains four refresh units ( ru ) and each ru has a corresponding refresh index ( ri ). for each operation , whether it is sector erase , power on or sleep mode , the refresh method is an embedded function . fig4 shows a block diagram refreshing only the high threshold voltage charge loss cell using a difference sensing ratio method on the cell side . for example , sensing ratio a is 1 : 1 and sensing ratio b is 1 : x , x & gt ; 1 such as x = 2 . fig4 shows a block diagram refreshing only the low threshold voltage charge gain cell using a difference sensing ratio method on the cell side . for example , sensing ratio a is 1 : 1 and sensing ratio c is 1 : y , y & lt ; 1 such as y = ⅔ . fig4 shows a block diagram refreshing both the high threshold voltage charge loss cell and the low threshold voltage charge gain cells using a difference sensing ratio method on the cell side . for example , sensing ratio a is 1 : 1 , sensing ratio b is 1 : x , x & gt ; 1 such as x = 2 and sensing ratio c is 1 : y , y & lt ; 1 such as y = ⅔ . fig4 shows a block diagram refreshing only the high threshold voltage charge loss cell using a difference sensing ratio method on the reference cell side . for example , sensing ratio a is 1 : 1 and sensing ratio c is 1 : y , y & lt ; 1 such as x = ½ . fig4 shows a block diagram refreshing only the low threshold voltage charge gain cell using a difference sensing ratio method on the reference cell side . for example , sensing ratio a is 1 : 1 and sensing ratio b is 1 : x , x & gt ; 1 such as y = 3 / 2 . fig4 shows a block diagram refreshing both the high threshold voltage charge loss cell and the low threshold voltage charge gain cells using a difference sensing ratio method on the reference cell side . for example , sensing ratio a is 1 : 1 , sensing ratio b is 1 : x , x & gt ; 1 such as x = 3 / 2 and sensing ratio c is 1 : y , y & lt ; 1 such as y = ½ . fig4 shows a block diagram refreshing only the high threshold voltage charge loss cell using a difference reference cell method . for example , iref - r =( ½ ) x ( iref ). fig5 shows a block diagram refreshing only the low threshold voltage charge gain cell using a difference reference cell method . for example , iref - re =( 3 / 2 ) x ( iref ). fig5 shows a block diagram refreshing both the high threshold voltage charge loss cell and the low threshold voltage charge gain cell using a difference reference cell method . for example , iref - re =( 3 / 2 ) x ( iref ), iref - r =( ½ ) x ( iref ). fig5 shows a block diagram refreshing the high threshold voltage charge loss cell using a current mirror method with the current mirror at reference cell side . for example , current mirror a is iref and current mirror c , iref - c =( ½ ) x ( iref ). fig5 shows a block diagram refreshing only the low threshold voltage charge gain cell using a current mirror method with the current mirror at the reference cell side . for example , current mirror a is iref and current mirror b is iref - b =( 3 / 2 ) x ( iref ). fig5 shows a block diagram refreshing both the high threshold voltage charge loss cell and the low threshold voltage charge gain cells using a current mirror method with the current mirror at the reference cell side . for example , current mirror a is iref , current b is iref - b =( 3 / 2 ) x ( iref ) and current mirror c is iref - c =( ½ ) x ( iref ). fig5 shows a flow diagram and fig5 shows the charge loss bits that need refreshing at the reference cell side . fig5 shows the flow diagram for the refresh algorithm using a sensing ratio for “ 0 ” cell charge loss on the reference cell side . the algorithm begins by setting n to 0 . it reads ri ( n ) and determines its state . if ri ( n )= 0 , n is incremented by 1 . then it compares the value of n to 1024 . if true , it erases ri ( 0 ) to ri ( 1023 ) with a “ 1 ” and the algorithm restarts from the beginning . if false , the algorithm restarts at read ri ( n ) for the next value of n . when the data in ri ( n ) =“ 1 ”, it refreshes ru ( n ). next , the cell is read with constant gate voltage , vg , and sensing ratio a judges v [ icell ]& gt ; v [ iref ]. if v [ icell ] is higher than v [ iref ], it tests the cell for the last cell . if false , it reads the next cell with the constant gate voltage , vg , and starts the sensing ratio a over . if it is the last cell , it programs ri ( n ) with a “ 0 ” and the algorithm finishes . if v [ icell ] is lower than v [ iref ], then sensing ratio c judges v [ icell - 0 ]& gt ; v [( iref ) x ( y )]. if v [ icell - 0 ] is lower than v [( iref ) x ( y )], a test for the last cell is done . if false , it reads the next cell with the constant gate voltage , vg , and starts the sensing ratio a over . if true , then it programs ri ( n ) with a “ 0 ” and the algorithm finishes . if v [ icell - 0 ] is higher than v [( iref ) x ( y )], it refreshes and reprograms the cell . then it tests the cell for the last cell . if false , it reads the next cell with the constant gate voltage , vg , and starts the sensing ratio a over . if true , it programs ri ( n ) with a “ 0 ” and the algorithm finishes . fig5 shows an example of which bits need refreshing of using the sensing ratios a and c . for example , sensing ratio a is 1 : 1 and sensing ratio c is 1 : y , y = ½ and the fig5 shows where the refreshing occurs . fig5 and 58 show a flow diagram and which charge gain bits need refreshing at the reference cell side . fig5 shows the flow diagram for the refresh algorithm using a sensing ratio for “ 1 ” cell charge gain on the reference cell side . the algorithm begins by setting n to 0 . it reads ri ( n ) and determines its state . if ri ( n )= 0 , n is incremented by 1 . then , it compares n to 1024 , if true it erases ri ( 0 ) to ri ( 1023 ) with a “ 1 ” and the algorithm restarts from the beginning . if false , the algorithm restarts at read ri ( n ) for the next value of n . when the data in ri ( n )=“ 1 ”, it refreshes ru ( n ). next , the cell is read with constant gate voltage , vg , and sensing ratio a judges v [ icell ]& gt ; v [ iref ]. if v [ icell ] is lower than v [ iref ], then it tests the cell for the last cell . if false , it reads the next cell with the constant gate voltage , vg , and starts the sensing ratio a over . if it is the last cell , it programs ri ( n ) with a “ 0 ” and the algorithm finishes . if v [ icell ] is higher than v [ iref ], then sensing ratio b judges v [ icell - 1 ]& gt ; v [( iref ) x ( x )]. if v [ icell - 1 ] is higher than v [( iref ) x ( x )], a test for the last cell is done . if false , it reads the next cell with the constant gate voltage , vg , and starts the sensing ratio a over . if true , it programs ri ( n ) with a “ 0 ” and the algorithm finishes . if v [ icell - 1 ] is lower than v [( iref ) x ( x )], it reads the ru ( n ) data to memory , then it erases ru ( n ) and programs the data from memory to ru ( n ). finally , it programs ri ( n ) with “ 0 ” and finishes . fig5 shows an example of which bits need refreshing as a result of using ratios a and b . for example , sensing ratio a is 1 : 1 and sensing ratio b is 1 : x , x = 3 / 2 and fig5 shows where the refreshing occurs . fig5 shows the refreshing algorithm for both “ 0 ” charge loss and “ 1 ” cell charge gain for the reference cell side sensing ratio . the algorithm begins by setting n to 0 , next it reads ri ( n ). if ri ( n ) is 0 , n is incremented by 1 and it tests for n = 1024 . if n equals 1024 , it erases ri ( 0 ) to ri ( 1023 ) to “ 1 ”, if n less than 1024 , the algorithm starts at read ri ( n ) for the next value of n . when ri ( n ) is “ 1 ”, the algorithm refreshes ru ( n ). next the cell is read using a constant gate voltage , vg , and sensing ratio a judges v [ icell ]& gt ; v [ iref ]. if v [ icell ] is lower than v [ iref ], sensing ratio c judges v [ icell - 0 ]& gt ; v [( iref ) x ( y )]. if v [ icell - 0 ] is higher , it refreshes and reprograms the cell . then it tests the cell for the last cell . if v [ icell - 0 ] is lower , then it tests the cell for the last cell . if it is not the last cell , it reads the next cell with the constant gate voltage , vg , and starts the sensing ratio a over . if it is the last cell , it programs ri ( n ) with a “ 0 ” and the algorithm finishes . however , if v [ icell ] is higher , then sensing ratio b judges v [ icell - 1 ]& gt ; v [( iref ) x ( x )]. if v [ icell - 1 ] is higher , then it tests the cell for the last cell . if v [ icell - 1 ] is lower , it reads ru ( n ) data to memory and then it erases ru ( n ). next , it programs the data from memory to ru ( n ), then programs ri ( n ) to “ 0 ” and finishes . in an alternative embodiment of the present invention , iref may be a generated reference cell current level , and not the reference cell current of an actual reference cell . in one preferred embodiment of the present invention , the single and lower control gate voltage can range from about 0v to about 10v . in fig2 , the current mirror is used to generate current ( a ) and current ( c ). current ( a ) is the same value as the reference cell current , iref , and current ( c ) is half of the value of the reference cell current , iref . the present invention shortens the process development time and provides high data retention and endurance , which uses a circuit design method without increasing the process complexity . it will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof . it is understood , therefore , that this invention is not limited to the particular examples disclosed , but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims .