the following description is presented to enable any person skilled in the art to make and use the invention , and is provided in the context of a particular application and its requirements . various modifications to the disclosed embodiments will be readily apparent to those skilled in the art , and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention . thus , the present invention is not intended to be limited to the embodiments shown , but is to be accorded the widest scope consistent with the principles and features disclosed herein . fig1 illustrates a computer system that executes vliw instructions in accordance with an embodiment of the present invention . the computer system illustrated in fig1 includes semiconductor chip 100 coupled with dynamic random access memory ( dram ) 150 . dram 150 may include any type of random access memory for storing code and data to be executed by vliw processor 101 located on semiconductor chip 100 . semiconductor chip 100 includes circuitry to implement a vliw processor 101 . this circuitry includes instruction cache 102 , aligner 104 , instruction buffer 106 , pipeline control unit 108 , data cache 134 , as well as register files 110 , 112 , 114 and 116 . vliw processor 101 additionally includes universal functional units 118 , 120 , 122 and 124 . these universal functional units are coupled to exception registers 126 , 128 , 130 and 132 , respectively . during operation of vliw processor 101 , vliw instructions are fetched from dram 150 into instruction cache 102 . instruction cache 102 may include any type of cache memory for storing vliw instructions , including a directed - mapped or a set - associative instruction cache . a vliw instruction feeds through aligner 104 which performs alignment functions before feeding the instruction into instruction buffer 106 . this alignment may be necessary for a vliw instruction because sub - instructions within the vliw instruction may not be properly aligned when the vliw instruction originates from instruction cache 102 . aligner 104 ensures that sub - instructions are left - aligned , if such alignment is necessary . instruction buffer 106 contains storage for a plurality of vliw instructions . recall that each vliw instruction is composed of a plurality of sub - instructions . the sub - instructions for a currently executing vliw instruction feed into corresponding universal functional units 118 , 120 , 122 and 124 . universal functional units 118 , 120 , 122 and 124 contain circuitry to perform arithmetic operations on data from register files 110 , 112 , 114 and 116 , respectively . universal functional units 118 , 120 , 122 and 124 support arithmetic operations on a number of data types including floating point , fixed point , integer and saturated data types . saturated data types are typically used to specify control signals . a saturated variable remains at its highest value if incremented above its highest value , and remains at its lowest value if decremented below its lowest value . thus , problems due to abrupt swings in a control signal caused by wrap around during arithmetic operations are avoided . universal functional units 118 , 120 , 122 and 124 perform a number of common arithmetic and data manipulation operations including addition , multiplication and shift operations , as well as bit extract and byte shuffle operations . note that universal functional unit 118 differs from universal functional units 120 , 122 and 124 in that it additionally handles load , store and branch instructions to facilitate flow control and data movement within vliw processor 101 . register files 110 , 112 , 114 and 116 contain data to be manipulated by associated universal functional units 118 , 120 , 122 and 124 , respectively . a number of registers are local to register files 110 , 112 , 114 and 116 and a number of registers are shared between register files . in one embodiment of the present invention , a given register file contains 96 shared registers and 32 local registers out of 128 visible registers . data to be manipulated by a vliw program flows from dram 150 into data cache 134 . data cache 134 may include any type of cache memory for storing data to be executed by vliw processor 101 , including a set associative or a direct - mapped cache . during load operations , data is transferred from data cache 134 into register files 110 , 112 , 114 and 116 . during store operations , data is written from register files 110 , 112 , 114 and 116 into data cache 134 , and ultimately back to dram 150 . note that vliw processor 101 illustrated in fig1 is a pipelined processor . this means that at any given point in time during execution of a vliw program , vliw instructions are staged so that multiple vliw instructions are concurrently executing . pipelined execution is controlled by pipeline control unit 108 . pipeline control unit 108 controls the movement of instructions through vliw processor 101 and additionally controls exception conditions , such as interrupts and traps . this includes handling exception conditions where at least one sub - instruction within a vliw instruction requires emulation in software . when an exception condition occurs in one of the universal functional units 118 , 120 , 122 and 124 , the exception condition causes a corresponding bit to be set in one of the corresponding exception registers 126 , 128 , 130 and 132 , respectively . note that there is a different bit in each exception register for each different type of exception condition . for example , one exception condition may indicate that the current sub - instruction requires emulation in software , and another exception condition may indicate that the corresponding sub - instruction caused an overflow during an arithmetic operation . also note that multiple exception conditions can occur during execution of a given sub - instruction . this means that multiple bits in an exception register can be set by the same sub - instruction . a series of or gates 135 , 136 , 138 , 140 and 144 are used to aggregate the contents of exception registers 126 , 128 , 130 and 132 into an single exception signal 146 , which feeds into pipeline control unit 108 . more specifically , the bits of exception register 126 feed into inputs of or gate 135 ; the bits of exception register 128 feed into inputs of or gate 136 ; the bits of exception register 130 feed into inputs of or gate 138 ; and the bits of exception register 132 feed into inputs of or gate 140 . next , the outputs of or gates 135 , 136 , 138 and 140 feeds into inputs of or gate 144 . finally , the output of or gate 144 becomes exception signal 146 , which feeds into an input of pipeline control unit 108 . exception signal 146 is asserted whenever any of the bits in exception registers 126 , 128 , 130 and 132 are asserted . in response to an asserted exception signal 146 , pipeline control unit 108 initiates an exception handling process . this exception handling process involves ( among other things ) reading exception registers 126 , 128 , 130 and 132 in order to determine what type of exception occurred . although the vliw processor 101 illustrated in fig1 resides on a single semiconductor chip , the present invention is not limited to vliw processors that fit entirely on a single semiconductor chip , but rather applies to any type of vliw processor , even those that span multiple semiconductor chips . fig2 illustrates a single vliw instruction 200 in accordance with an embodiment of the present invention . vliw instruction 200 includes four sub - instructions 202 , 204 , 206 and 208 . sub - instruction 202 is a load sub - instruction specifying a load operation for universal functional unit 118 . this load operation moves data from dram 150 into at least one register within register files 110 , 112 , 114 and 116 . sub - instruction 204 specifies a multiplication operation for universal functional unit 120 . sub - instruction 206 specifies a subtraction operation for universal functional unit 122 . finally , sub - instruction 208 specifies an addition operation for universal functional unit 124 . note that although vliw instruction 200 includes four sub - instructions , in general a vliw instruction may include any number of sub - instructions . fig3 illustrates part of the internal structure of pipeline control unit 108 in accordance with an embodiment of the present invention . among other circuitry , pipeline control unit 108 includes instruction breakpoint mask register 302 and trap handler 304 . trap handler 304 includes circuitry for handling traps and other exception conditions that arise during execution of vliw instructions . trap handler 304 acts in concert with instruction breakpoint mask register ( ibmr ) 302 . ibmr 302 contains a single bit for each of the universal functional units 118 , 120 , 122 and 124 in vliw processor 101 . each bit acts as an enable signal for the corresponding universal functional unit . hence , when a bit is asserted , the corresponding functional unit is enabled . as illustrated in fig3 ibmr 302 includes four bits , three of which are asserted . this means that when a the corresponding vliw instruction executes , only three of four universal functional units will be enabled . this selective enablement mechanism allows instructions that are not emulated in software to be executed in hardware as is described below with reference to fig5 . fig4 illustrates how a register file 110 is coupled to shadow registers 402 in accordance with an embodiment of the present invention . in order to improve processor performance , vliw processor 101 includes shadow registers 402 , which are located on the same semiconductor chip as register file 110 . during an exception condition , registers within register file 110 or control registers within pipeline control unit 108 can be temporarily saved to shadow registers 402 instead of saving them out to external memory ( dram 150 ). this can greatly improve processor performance during exception conditions because saving registers out to external memory typically requires a large number of clock cycles . fig5 is a flow chart illustrating the instruction emulation process in accordance with an embodiment of the present invention . during execution of a vliw program , a vliw instruction generates an exception condition ( step 502 ). vliw processor 101 detects this exception condition and notifies pipeline control unit 108 ( step 504 ). in the embodiment of the invention illustrated in fig1 this detection process involves loading at least one of exception registers 126 , 128 , 130 and 132 with a value indicating the type of exception that occurred . note that more than one exception can occur for each functional unit at the same time . the contents of exception registers 126 , 128 , 130 and 132 feed through or gates 135 , 136 , 138 , 140 and 144 to form exception signal 146 , which feeds into pipeline control unit 108 . exception signal 146 will be asserted whenever any bits are set in exception registers 126 , 128 , 130 and 132 . next , vliw processor 101 saves the contents of some registers with register files 110 , 112 , 114 and 116 ( step 506 ). in one embodiment of the present invention , this is accomplished by writing the registers out to memory . in another embodiment , this is accomplished by writing the registers to “ shadow registers ” illustrated in fig4 . this can greatly reduce the time required to write the registers out to an external memory . next , vliw processor 101 is placed in a privileged mode so that it can access all of the internal registers within vliw processor 101 in order to process the exception condition ( step 508 ). the system then goes to a trap handler routine ( step 510 ). in one embodiment of the present invention , this is accomplished by looking up a trap vector , which contains the address of a trap handling routine , and then jumping to the address . at this point trap handling software takes over from the hardware within pipeline control unit 108 . this trap handling software may initially store more of the vliw processor 101 &# 39 ; s state out to memory or into shadow registers . note that processing an exception condition for a vliw instruction causes all subsequent vliw instructions to be flushed from the pipeline . hence , after the exception condition is complete , vliw processor 101 must reload vliw instructions starting from the instruction immediately following the vliw instruction that caused the exception condition . the trap handling routine next reads the exception register of each universal functional unit ( step 512 ). if a particular sub - instruction caused at least one exception , the system processes the exceptions in order of priority ( step 514 ). in one embodiment of the present invention , this is accomplished by reading an exception register for the universal functional unit associated with the sub - instruction and using the “ count consecutive clear bits ” ( cccb ) instruction to find the highest bit in the exception register that is set . this process identifies the highest priority exception because each bit in the exception register corresponds to a different exception condition , and the bits are mapped into the exception register in priority order . next , the system jumps a specific handler for the exception condition . for example , if the exception condition requires the sub - instruction to be emulated in software , the system jumps to a piece of code to emulate the sub - instruction . finally , if other exceptions remain to be processed for the sub - instruction , they are processed in priority order . next , the results of the exception condition , if any , are stored out to memory ( step 516 ). for example , if the exception condition caused a sub - instruction to be emulated , the emulation results are written out to memory . the system next stores a pattern of enablement signals for all of the remaining sub - instructions that have not been emulated into instruction breakpoint mask register ( ibmr ) 302 within pipeline control unit 108 ( step 518 ). recall that ibmr 302 contains enablement signals for each of the universal functional units 118 , 120 , 122 and 124 in the system . hence , storing the pattern of enablement signals in ibmr 302 causes selected universal functional units to the enabled . next , the system executes in hardware the vliw instruction that caused the exception condition ( step 520 ). note that since the sub - instructions that caused the exception condition are not enabled , the vliw instruction should finish executing without generating an exception condition . next , if at least one bit of ibmr is equal to zero ( or stated conversely if ibmr is not equal to 1111 ), a trap is generated after execution of the vliw instruction ( step 522 ). this trap causes the emulated results stored out to memory in step 516 to be retrieved from memory and stored into their destination locations within register files 110 , 112 , 114 and 116 . the vliw instruction has now successfully executed and vliw processor 101 commences executing the next vliw instruction in the vliw program . note that the discussion above refers to actions carried out by vliw processor 101 . these actions may be carried out under direction of a micro - sequencer or controller for vliw processor 101 , as would be the case for a non - vliw processor . this micro - sequencer or controller coordinates actions of all of the functional components illustrated in fig1 . the foregoing descriptions of embodiments of the invention have been presented for purposes of illustration and description only . they are not intended to be exhaustive or to limit the invention to the forms disclosed . accordingly , many modifications and variations will be apparent to practitioners skilled in the art . additionally , the above disclosure is not intended to limit the invention . the scope of the invention is defined by the appended claims .