fig1 is a schematic representation of a circuit according to one embodiment of the disclosure . referring to fig1 , circuit 100 receives first input signal 110 and second input signal 120 . the first input signal 110 comprises an ac signal component 114 and a dc signal component 112 . similarly , the second input signal 120 comprises ac signal component 124 and dc signal component 122 . at node 111 , ac signal component 114 is separated from dc signal component 112 . at node 121 , ac signal component 124 of second signal 120 is separated from dc signal component 122 . in one embodiment of the disclosure , the ac and the dc components of the incoming signals are separated such that a spike in the ac signal does not affect the signaling . thus , in the embodiment of fig1 , dc component 112 of first signal 110 is processed through preamplifier circuit 140 while ac component 114 of first signal 110 is directed to first capacitor 130 . first capacitor 130 defines a first bypass circuit . similarly , dc component 122 of second signal 120 is directed to preamplifier circuit 140 while ac component 124 of second signal 120 is directed to second capacitor 132 . second capacitor 132 defines a second bypass circuit . first capacitor 130 and second capacitor 132 advantageously isolate and control any spike in first signal 110 and second signal 120 , respectively . it should be noted that while the embodiment of fig1 shows first capacitor 130 and second capacitor 132 , other circuit elements or other circuits can be used to obtain the same result . namely , any circuit elements or circuits can be used as long as such circuit is able to absorb fluctuations in the ac signal . the fluctuation in the ac signal can comprise a current spike , etc . the dc component of first signal 112 and dc component of second signal 122 are processed through preamplifier circuit 140 . preamplifier circuit 140 can have a gain of 1 , 1 . 5 , 2 or other suitable gains . in one embodiment , preamplifier circuit 140 applies a unity gain to each of dc component signal 112 and dc component signal 122 . consequently , first processed dc signal 118 is substantially identical to dc component of first signal 112 and second processed dc signal 128 is substantially identical to dc component of second signal 122 . as stated , ac component of first signal 114 is processed through first capacitor 130 to obtain first ac output signal 116 . ac component of second signal 124 is processed through second capacitor 132 to obtain second ac output signal 126 . at first node 117 , first ac output signal 116 is combined with first processed dc signal 118 . similarly , at second node 127 , second processed dc signal 128 is combined with second ac output signal 126 . each of first node 117 and second node 127 can define a node , an adder or a junction . first combined output 119 and second combined output 129 are directed to amplifier circuit 150 . amplifier circuit 150 can comprise a conventional amplifier circuit . amplifier circuit 150 can have a sufficiently high gain to convert lvds level to cmos level ( e . g ., from 350 mv to 3 . 5 v ). as discussed in greater detail below , the built - in hysteresis prevents output from changing when differential signals dwell around 0 volts . such event can occur during signal transition or when pre - amplifier 140 is turned off in response to an out - of - range input common mode voltage . the output from amplifier circuit 150 comprises first amplified signal 152 and second amplified signal 154 . first amplified signal 152 and second amplified signal 154 can provide the input to a receiver circuit ( not shown ). advantageously , the common mode voltage is set internally at the preamplifier circuit 140 , hence there is less jitter noise in the main amplifier 150 . thus , in the case of large and sudden common mode jump , dc path provides sufficient gain even though the ac path is momentarily turned off or isolated . fig2 is a transconductance circuit according to another embodiment of the disclosure . circuit 200 of fig2 is similar to circuit 100 of fig1 , except for the addition of pull - up resistors r 1 and r 2 . in circuit 200 , the signal information is carried on lines 110 and 120 which have same magnitude voltage swing with opposite polarities with respect to a common mode voltage level . pre - amplifier 140 can be a transconductance amplifier for converting the input differential voltage to differential output currents . preamplifier 140 can be connected to an internal termination network 210 , which sets the internal common mode voltage and converts current signal back to voltage . amplifier 150 can process both ac and dc components , as long as the incoming signal is within its common mode input range , which is typically from 0 . 2v to 2 . 2v . there is also a parallel signal path from differential inputs , where inputs are bypassed by capacitors 130 and 132 to the internal termination network . bypass capacitors 130 , 132 only pass the ac level of the signal , independent of the input common mode voltage . the gain of the pre - amplifier 140 can be adjusted to be unity , such that the current through the bypass capacitors 130 , 132 is 0 , hence the circuitry is not loaded as long as the input signals are within the common mode range of pre - amplifier 140 . signal at the internal termination network can be amplified by a second amplifier stage 150 , which convert its inputs from lvds level ( e . g ., 1v - 1 . 4v ) to cmos level ( e . g ., 0v - 3 . 3v ). furthermore , amplifier 150 can have a built - in hysteresis for suppressing noise when the differential input signal crosses zero level . fig3 schematically represents a built - in hysteresis voltage diagram for amplifier 150 . a built - in hysteresis can prevent state changes at the output of the second stage ( i . e ., amplifier 150 ) even if its inputs are held at the same potential with zero differential voltage . this occurs when preamplifier 140 turns off if the receiver inputs exceed its common mode range , and only the ac component of the signal can be passed through the integrated bypass capacitors . therefore , hysteresis network can also be considered a feature that remembers the dc component of the signal , and compensates for the loss of the dc component due to out - of - range common mode variations . referring to fig2 and 3 , the gain of preamplifier 140 can be identified as the transconductance gain , or gm . the resistance of termination network 210 can be described as : it should be noted that termination network 210 can be implemented using diode connected pull - up transistors ( not shown ). if diode connected pull - up transistors are used , the resistance will be equal to 1 / gm ( where gm is the transconductance gain ). for the bypass network , the following relationship applies : thus , the gain in the first stage ( or , the preamplifier stage ) can be chosen such that : with this relationship , there will be no current through the caps as long as the inputs are within the common mode range of preamplifier 140 . in one embodiment of the disclosure , c should be selected such that time constant r * c does not limit the speed of operation ( that is , r * c & lt ; t bit / 2 ; where t bit is the shortest input pulse width ). when the input falls outside the common mode range , pre - amp turns off and the current proportional to the ac component in the signal flows into the termination network by blocking the input dc level . having blocked the dc current , steady input levels result in zero differential voltage at the termination network outputs . therefore , the second amplifier stage ( amplifier 150 ) needs to have a built - in hysteresis in order to prevent the output state to change in response to noise at the termination network . thus , in fig3 even if the input differential voltage is set to zero , the output preserves its last state due to the built - in hysteresis voltage . the input to the amplifier should go lower than v i or higher than v h to register a change in the output state . fig4 is a representative algorithm according to one embodiment of the disclosure . the process of fig4 starts at step 410 , where a first and a second input signal are received . each of the first and the second input signals comprises an ac and a dc component . in step 420 , the ac and the dc components of each of the first and the second signals are separated . in step 430 , the ac components for the first and the second signal are directed to a bypass circuit . in one embodiment , the ac component of the first signal is directed to a first bypass circuit and the ac component of the second signal is directed to a second bypass circuit . in step 435 , the dc component of the first signal and the dc component of the second signal are directed to a preamplifier circuit . the preamplifier circuit can define a conventional amplifier with a unity gain . in one embodiment of the disclosure , the dc component of the first signal and the dc component of the second signal are directed to a preamplifier circuit . in another embodiment , the dc component of the first signal is directed to a first preamplifier circuit while the dc component of the second signal is directed to a second preamplifier circuit . in step 440 , the dc component of the first signal is combined with the ac component of the first signal . in addition , the ac component of the second signal is combined with the dc component of the second signal . thus , a first signal and a second signal are reformed after being processed through bypass circuits and preamplifier circuit ( s ). finally , in step 450 , the first and the second circuits are processed through an amplifier circuit having a gain , g . fig5 is a representative algorithm according to another embodiment of the disclosure . algorithm 500 of fig5 starts in step 510 by receiving first and second input signals . each input signals can have an ac and a dc component . in step 520 , the input voltage is converted to a current signal using a transconductance amplifier ( or , a preamplifier ). the input dc component is blocked and the ac input component is bypassed using bypass capacitors in step 530 . thus , the ac component is bypasses the transconductance amplifier . in step 540 , pull - up devices are used between the output of the transconductance amplifier and the input to the subsequent amplifier stage . the pull - up devices between the internal termination voltage and the transconductance preamplifier circuit convert the current back to voltage . thus , the ac component is inputted into a second stage amplifier . in step 550 , the output of the termination network is amplified by the second stage amplifier . typically , the gain can be made sufficiently high to convert lvds levels to cmos levels ( e . g ., from 350 mv to 3 . 3v ). while the specification has been disclosed in relation to the exemplary and non - limiting embodiments provided herein , it is noted that the inventive principles are not limited to these embodiments and include other permutations and deviations without departing from the spirit of the disclosure . for example , while the exemplary embodiments are directed to a combination filter device protecting human eyes from laser , the principles can be used to filter out photons of any undesirable wavelength or wavelengths .