with reference to fig1 to 11 , on a semiconducting substrate 1 , isolation structures 2 are defined and formed as uninterrupted parallel strips , which extend for the entire height of the columns of the array of cells . the isolation structures 2 may be constituted by a field oxide layer , thermally grown on unmasked portions of the surface of the semiconductor 1 which may have previously been ion implanted , according to one of the well known techniques of masking with silicon nitride , as the so - called locos technique ( by philips ) or the planox technique ( by sgs - thomson ) or alike . alternatively the isolation strips may be &# 34 ; inlaid &# 34 ;, i . e . made by first cutting trenches on the surface of the semiconducting substrate which , after an ion - implantation , are filled by deposition with a dielectric material such as silicon oxide ( box type isolations ), thus advantageously ensuring a perfect planarity of the surface of the wafer . as it may be observed the photolithographic definition of the isolation strips 2 is practically free of the inconveniences which derived by the rounding , during the image transfer process , of the corners of substantially rectangular geometries , such as was the case with the known prior art architecture of these devices . the photolithographic definition of parallel strips is far more easy , optically , because the diffraction problems are markedly less pronounced than in the case of rectangular or bi - directionally defined features . after having formed the isolation structures 2 by utilizing any of the known techniques , also by following common practices , the gate structures , indicated with 3 as a whole , are formed , which gate structures , in accordance with the present invention , are partially sacrificial structures because they will be further defined later in the process by further masking and etching . as it may be observed in fig2 the gate structures for an array of unit memory cells are , at this stage , parallel spaced strips , which intersect orthogonally the isolation strips 2 previously formed on the front of the semiconducting wafer by crossing over them . as shown in the cross sectional view a -- a of fig3 for the specific case of eprom type cells , each individual gate structure comprises a first conducting layer 4 , usually of polycrystalline silicon ( poly i ), which is electrically isolated from the underlying semiconductor 1 by a gate dielectric layer , normally of silicon oxide , 5 , previously formed over the active areas between two adjacent isolation strips 2 , and which first conducting layer 4 will constitute the floating gate of the eprom cells of the device , completely insulated by a dielectric layer or multilayer 6 , on top of which a second conducting layer of polycrystalline silicon ( poly ii ) 7 is deposited and patterned to constitute a control gate electrode of the cell . the flanks of the composite gate structures 3 are covered by an insulating dielectric layer 8 , having a tapered cross sectional profile for forming lateral spacers for conducting the subsequent ion implantation of the drain and source areas of the semiconductor and for forming , in a selfalignment condition , electrical interconnection lines for the drain and source regions of individual cells , as will described later . also the formation of these tapered dielectric spacers 8 is a well known practice and therefore will not be reiterately described in detail . briefly , the fabrication process after having completed the formation of isolation structures in the form of parallel uninterrupted strips 2 , in the case of an eprom memory , may comprise the following steps : a ) thermally oxidizing the semiconductor 1 to form a layer of gate oxide 5 on active areas ; b ) depositing by chemical vapor deposition a layer of polycrystalline silicon ( poly i ) and doping it ; c ) forming by thermally oxidizing the surface of the deposited polycrystalline silicon , or by deposition , a dielectric layer or multilayer 6 for isolating the floating gate constituted by the patterned layer of polycrystalline silicon 4 ( poly i ); d ) depositing by chemical vapor deposition a second layer of polycrystalline silicon 7 ( poly ii ), through which the control gates will be patterned eventually , and optionally also a layer of silicon silicide in order to complete in practice the deposition step of all the layers which form the gate structure stack of the memory matrix ; e ) patterning by masking and etching the parallel lines of the gate structure ; f ) forming side wall spacers 8 of a dielectric material on the flanks of the lines of the gate structure , and implanting source and drain areas according to common practices . at the end of this sequence of fabrication steps , the structure is as shown in fig2 and 3 , in particular in the sectional view of fig3 a gate structure for eprom cell is depicted . of course , in case of cells formed by a simple mos transistor , the gate structure will comprise a single conducting layer ( i . e . the gate structure will be formed substantially by the poly i layer only ). at this point the fabrication process may proceed in accordance with two different embodiments of the invention . according to a first embodiment , which is schematically depicted in the series of fig4 - 11 , the process proceeds through the following steps : g ) conformally depositing a single , electrically conducting , matrix layer 9 or a conducting multilayer , followed by the deposition of a layer of a planarizing material 10 ( e . g . a silicon oxide glass ; sog ) or of a material which lend itself to be planarized ( e . g . a mixture of oxides which may be thermally reflown ), as depicted in fig4 ; h ) maskless &# 34 ; blanket &# 34 ; etching of the layer 10 until exposing the tops of the peaks of the underlying matrix conducting layer 9 which was previously deposited , as shown in fig5 ; i ) selective etching of the conducting material of the matrix layer 9 , exposed during the preceding etching step , while utilizing the residues of the planarizing material 10 as a mask during this etching step , until lowering the etch front of the conducting material down the sides of the dielectric spacers 8 , as shown in fig6 . with this last step , the source and drain interconnection lines are jointly formed directly on the substrate , above source and drain regions of the cells , respectively , which lines geometrically cross - over the isolation strips when they cross with the latter which extend in an orthogonal direction in respect to said connection lines . it is evident as the contact area on the source regions as well as on the drain regions is advantageously as large as possible . moreover , the fact that the electrical contact is established on an area of the semiconducting substrate which has not been purposely &# 34 ; exposed &# 34 ; by means of an etching of an isolation dielectric layer which is customarily formed for isolating the gate structures , avoids the problems due to etch induced crystal defects and / or implantation of polluting species and / or to an imperfect or only partial cleaning of the contact area from oxide and / or polymeric residues which normally are formed during the customary reactive ion etching process used for making the contact holes through an isolating dielectric layer . of course , the most remarkable advantage is represented by the fact that the drain and source connection metal lines are realized without the use of patterning masks whose alignment could be critical . in fact , the metal source and drain connection lines 9 are formed in a substantially self - alignment manner in respect to the existing , partially sacrificial , gate structures , which at this stage are still in the form of uninterrupted parallel strips . at this point , the fabrication process may proceed further through the following steps : j ) removing the residual strips of planarizing material 10 still present over the conducting lines 9 , applying a layer of resist and defining a gate separation mask , whose pattern is schematically shown in fig7 by the profiles g drawn with a dash line . as it is easily observed , this mask has a pattern formed by parallel strips and is substantially free of critical features . etching through the openings of the mask the unmasked portions of the partially sacrificial gate structure , i . e . of the strips 3 where they cross over the underlying isolation strips , thus interrupting the continuity of the strips of the partly sacrificial gate structure which was formed and defining the permanent gate structures of the single cells , as depicted in fig7 and 8 ; k ) depositing a layer of dielectric material 11 as intermediate isolation layer , l ) defining by means of a dedicated gate contact mask and etching the layer of dielectric material 11 of intermediate isolation until exposing the surface of the conducting layer of the patterned control gate of eprom cells or of the unique gate conducting layer in the case of normal mos transistors , as depicted in fig9 . this gate contact mask is appreciably far less critical than the mask normally used for &# 34 ; opening &# 34 ; the drain contacts in prior art architectures . in fact , the surface to be exposed for the contact is at a relatively higher and constant level on the front of the wafer , which front , after depositing the intermediate isolation dielectric layer 11 , is relatively flat and may easily be further planarized if needed . m ) depositing a conducting layer ( doped polycrystalline silicon , aluminum , aluminum alloy and the like ) and patterning by means of dedicated mask the gate connection lines 12 , which are lines parallel to each other and orthogonal in respect to the underlying source and drain connection lines and run projectively parallel to two underlying adjacent isolation strips , as shown in fig1 and 11 . according to an alternative embodiment of the invention , it is possible to form the source and drain connection lines by depositing above the patterned , partially sacrificial strips of the gate structure 3 , a layer of conducting material ( e . g . tungsten ), not in a conformal manner , but in such a way that the deposited layer of conducting material substantially planarizes the surface of the front of the wafer , as depicted in fig1 . this may be obtained by utilizing techniques which favor the tendency of the specific metallic material deposited to readily fill the cavities of the surface by growing thicker therein rather than on the top of the peaks of the surface . such a planarizing conducting layer 9 &# 39 ; may than be etched under highly anisotropic conditions , e . g . by a rie etch process , until the etch front of the conducting material 9 &# 39 ; is lowered down the sides of the dielectric spacers 8 which are present on the flanks of the underlying strips 3 of the gate structure , as schematically depicted in fig1 , in order to form in a simplified manner the drain and gate metallic connection lines , self - aligned to the existing strips 3 of the gate structure . while in fig3 a typical composite stack gate structure of an eprom cell has been shown in detail , in the following figures the gate structure has been more generally indicated with 3 , as a whole , purposely without showing the intrinsic specific multilayered structure , because as it will be evident to the skilled technician , the present invention is equally applicable both in the case of eprom type unit cells , as well as in the case of unit cells formed by a standard mos transistor or alike structure , i . e . having a single gate electrode . the so - called rom memories are normally made with such a type of unit cells which cannot be erased ( neither programmed ) solely by electrical means . the discrimination between the status &# 34 ; 1 &# 34 ; and &# 34 ; 0 &# 34 ; of the binary code is conventionally implemented by either one of the following methods : a ) by creating ( or not creating ) a transistor structure in a particular location of the array ( matrix ) of transistors ; b ) by differentiating by means of channel implantation , the switch - on threshold of a particular transistor of the array ; c ) by connecting ( or not connecting ) a particular transistor of the array . the latter technique is often preferred because it permits to &# 34 ; customize &# 34 ; a device advantageously during the terminal steps of the fabrication process so as to permit standardization of the greater part of the preceding fabrication steps . according to known techniques , this customization may occur by connecting each drain to two selectable channels . the advantage of such an architecture is given by a 100 % redundancy , while the drawback is the requirement for a relatively large area of silicon . the lithographic difficulties are practically the same which are encountered when fabricating eprom type cells . by contrast , the present invention allows the implementation of a &# 34 ; programmed &# 34 ; connection of each transistor of the memory array during the terminal steps of the fabrication , by means of the gate contact mask and this fact greatly reduces the criticity of alignment and patterning in respect to the prior art practice of employing for the same purpose a far more critical drain contact mask , as mentioned before . advantageously each transistor or memory cell may be addressed through two selectable channels thus obtaining the same 100 % redundancy as in the case of the prior art , while taking advantage of the extreme compactness of the array of the invention , in respect to an array made according to the prior art . in more general terms , or in particular in the case of eprom memory arrays , different decoding circuits may be used which would include or not a certain redundancy . in other words , in case single memory cells are to be individually addressed , the memory matrix must be provided with an appropriate decoding circuitry for discriminating among the source lines , in accordance with a well known technique . by contrast if a more traditional decoding circuitry is utilized , with all the source lines electrically connected in common , each memory &# 34 ; cell &# 34 ; must be considered as formed in practice by two half cells , i . e . by a pair of unit cells or of transistors of the memory array , which will act in conjunction to each other thus determining a 100 % redundancy , according to well known practices .