hereinafter , an embodiment of the present invention will be described with reference to the drawings . fig1 is a diagram schematically showing a semiconductor device according to an embodiment of the present invention . in fig1 , reference numeral 1 denotes a semiconductor device , and the semiconductor device 1 has an nmos integrated circuit 2 including a plurality of n - channel type mosfets , and a pmos integrated circuit 3 including a plurality of p - channel type mosfets . the nmos integrated circuit 2 and the pmos integrated circuit 3 are integrated circuits in , for example , a system lsi , and do not comprises a circuit including gate electrodes repeatedly disposed at intervals of minimum dimension ( for example , memory cell circuits in a storage device such as a dram or the like ) and a peripheral circuit thereof . or , the nmos integrated circuit 2 and the pmos integrated circuit 3 are logic ics or asics , and more specifically , those are cmos integrated circuits in those integrated circuits . the former logic ics are circuits in a system lsi in some cases . the nmos integrated circuit 2 comprises a first nmos integrated circuit 2 1 including a plurality of n - channel type mosfets in which the film thicknesses of the gate oxide films are tox1 and a second nmos integrated circuit 2 2 including a plurality of n - channel type mosfets in which the film thicknesses of the gate oxide films are tox2 . the pmos integrated circuit 3 comprises a first pmos integrated circuit 3 1 including a plurality of p - channel type mosfets in which the film thicknesses of the gate oxide films are tox3 and a second pmos integrated circuit 3 2 including a plurality of p - channel type mosfets in which the film thicknesses of the gate oxide films are tox4 . in the present embodiment , the description will be carried out supposing that tox1 ≠ tox2 , tox3 ≠ tox4 , tox1 = tox3 , tox2 = tox4 . to describe more concretely , that is tox1 = tox3 = 15 nm , tox2 = tox4 = 4 nm . a power supply voltage of the mosfets of tox1 = tox3 = 15 nm is 3v , and a power supply voltage of the mosfets of tox2 = tox4 = 4 nm is 1v . fig2 is a cross - sectional view showing the mosfets in the nmos integrated circuit 2 ( 2 1 , 2 2 ). in fig2 , reference numerals tr 1 to 5 denote n - channel type mosfets in the nmos integrated circuit 2 1 , and reference numerals tr 6 to 10 denote n - channel type mosfets in the nmos integrated circuit 2 2 , and reference numerals 10 and 10 ′ denote gate oxide films , and reference numerals 11 and 11 ′ denote gate electrodes , and reference numerals 12 and 12 ′ denote gate sidewall insulating films ( spacers ), and reference numerals d 1 denote distances between the gate electrodes 11 adjacent to one another in the nmos integrated circuit 2 1 , and reference numerals d 2 denote distances between the gate electrodes 11 ′ adjacent to one another in the nmos integrated circuit 2 2 . the distance d 1 is a distance between the right end of a mosfet tri ( i = 1 , 2 , 3 , 4 ) 2 and the left end of a mosfet tri + 1 which is at the right side thereof . in the same way , the distance d 2 is a distance between the right end of a mosfet trj ( j = 6 , 7 , 8 , 9 ) 2 and the left end of a mosfet trj + 1 which is at the right side thereof . in the present embodiment , the mosfet tr 2 is a dummy mosfet ( dummy gate electrode section ), and does not carry out transistor operations . the dummy mosfet is provided so as to make the distances d 1 between the respective mosfets equal to one another , and the mosfet tr 2 is not necessarily made a dummy mosfet . further , the number of dummy mosfets is not limited to one , and may be two or more in some cases . in the same way , the mosfet tr 7 is a dummy mosfet provided for making the distances d 2 equal to one another . fig3 is a cross - sectional view showing the mosfets in the pmos integrated circuit 3 ( 3 1 , 3 2 ) in fig3 , reference numerals tr 11 to 15 denote p - channel type mosfets in the pmos integrated circuit 3 1 , and reference numerals tr 16 to 20 denote p - channel type mosfets in the pmos integrated circuit 3 2 , and reference numerals 13 and 13 ′ denote gate oxide films , and reference numerals 14 and 14 ′ denote gate electrodes , and reference numerals 15 and 15 ′ denote gate sidewall insulating films ( spacers ), and reference numerals d 3 denote distances between the gate electrodes 14 adjacent to one another in the pmos integrated circuit 3 1 , and reference numerals d 4 denote distances between the gate electrodes 14 ′ adjacent to one another in the pmos integrated circuit 3 2 . here , the distances d 3 and d 4 are defined as in the same way as the distances d 1 and d 2 . the mosfets tr 12 and tr 17 are dummy mosfets in the same way as the mosfets tr 2 and tr 7 . in the present embodiment , distances between the respective gate electrodes in the integrated circuit 2 1 are d 1 which are constant . in the same way , distances between the respective gate electrodes in the integrated circuit 2 2 are d 2 which are constant . further , as shown in fig3 , in the present embodiment , distances between the respective gate electrodes in the integrated circuit 3 1 are d 3 which are constant . in the same way , distances between the respective gate electrodes in the integrated circuit 3 2 are d 4 which are constant . the distances d 1 to d 4 between the gate electrodes in the respective integrated circuits 2 1 , 2 2 , 3 1 , and 3 2 have specific values determined in accordance with a channel type of a mosfet and a film thickness of a gate oxide film . generally , a distance between the gate electrodes in a case of an n - channel is shorter than that in a case of a p - channel , and the thinner the film thickness of a gate oxide film is , the shorter the distance between gate electrodes is . moreover , the film thicknesses t 1 to t 4 of the spacers 12 , 12 ′, 15 , and 15 ′ in the respective integrated circuit 2 1 , 2 2 , 3 1 , and 3 2 as well are respectively constant in the same way as the distances d 1 to d 4 between the gate electrodes . the film thicknesses t 1 to t 4 are , as shown in fig2 and fig3 , sizes in the direction of the channel length of portions of the spacers 12 , 12 ′, 15 , and 15 ′. the portions contact on a surface of the substrate . concretely , that is d 1 = 150 nm , d 2 = 200 nm , d = 250 nm , and d 4 = 300 nm . due to the d 1 to d 4 being set on the values , optimum spacer film thicknesses which are , for example , t 1 = 20 nm , t 2 = 23 nm , t 3 = 26 nm , and t 4 = 28 nm can be selected . in other words , the spacer film thicknesses t 1 and t 3 of the mos integrated circuits 2 1 and 3 1 whose power supply voltages are 3v and the spacer film thicknesses t 2 and t 4 of the mos integrated circuits 2 2 and 3 2 whose power supply voltages are 1v can be respectively set to optimum values . the cross - sectional views of the comparative example nmos integrated circuit and pmos integrated circuit which correspond to fig2 and fig3 of the present embodiment are shown in fig4 and fig5 . note that portions corresponding to those in fig2 and fig3 are denoted by the same reference numerals in fig2 and fig3 . as shown in fig4 and fig5 , in cases of the nmos integrated circuit 2 and pmos integrated circuit 3 , since there are no dummy mosfets ( mosfets tr 2 , tr 7 , tr 12 , and tr 17 ), a space between the mosfets tr 1 and tr 3 , a space between the mosfets tr 6 and tr 8 , a space between the mosfets tr 11 and tr 13 , and a space between the mosfets tr 16 and tr 18 are broadened . as a result , the pattern density difference in the gate electrodes is caused , which brings about a fluctuation in the film thicknesses t 1 to t 4 of the spacers 12 , 12 ′, 15 , and 15 ′ in the integrated circuits 2 1 , 2 2 , 3 1 and 3 2 . next , a manufacturing method for the semiconductor device of the preset embodiment will be described with reference to fig6 to 12 . first , as shown in fig6 , an insulating film 22 whose thickness is tox1 and a conducting film 23 such as a polycrystalline silicon film or the like including impurities are successively formed on a silicon substrate 21 . at that time , as shown in fig1 , the insulating film 22 and the conducting film 23 are formed in a state that the regions of the integrated circuits 22 and 32 are covered with a resist 24 . after the insulating film 22 and the conducting film 23 are formed , the resist 24 is removed . next , as shown in fig7 , a resist pattern 25 is formed on the conducting film 23 , and thereafter , the conducting film 23 and the insulating film 22 are etched by rie process by using the resist pattern 25 as a mask , thereby gate electrodes 23 and gate insulating films 22 are formed . after the gate electrodes 23 and the gate insulating films 22 are formed , the resist pattern 25 is removed . next , as shown in fig8 , ion implantations of n - type and p - type impurity ions are carried out by using the gate electrodes 23 as a mask , and thereafter , extensions 26 are formed by annealing . at this time , the implantation of n - type impurity ions is , as shown in fig1 , carried out in a state that the regions of the integrated circuits 2 2 , 3 1 , and 3 2 are covered with a resist 27 . on the other hand , the implantation of p - type impurity ions is , as shown in fig1 , carried out in a state that the regions of the integrated circuits 2 1 , 2 2 , and 3 2 are covered with a resist 28 . next , as shown in fig9 , insulating film to be the spacers 12 and 15 is deposited so as to cover the top surface and the side surface of the gate section ( the gate insulating films 22 and the gate electrodes 23 ) by lpcvd process , and thereafter , the spacers 12 and 15 are formed by etching the insulating films by rie process . next , as shown in fig9 , ion implantations of n - type and p - type impurity ions are carried out by using the spacers 12 and 15 , and the gate insulating films 22 as a mask , and thereafter , sources / drains 29 are formed by annealing . the ion implantations are carried out in the same way as the ion implantations for forming the extensions 26 . that is , the resists 27 and 28 are formed such that the predetermined impurity ions are selectively implanted into the regions of predetermined integrated circuits . the n - channel and p - channel type mosfets in the integrated circuit 2 1 and the integrated circuit 3 1 in which the film thicknesses of the gate oxide films are tox1 (= tox3 ) are obtained via the above processes . the n - channel and p - channel type mosfets in the integrated circuit 2 2 and the integrated circuit 3 2 in which the film thicknesses of the gate oxide films are tox2 (= tox4 ) are obtained via the same processes . the integrated circuits 2 1 , 3 1 in which the film thicknesses of the gate oxide films are tox1 , and the integrated circuits 2 2 , 3 2 in which the film thicknesses of the gate oxide films are tox2 are obtained even by the following process ( multi - oxied process ). first , a thick gate insulating film is formed on the silicon substrate 21 . next , the thick gate insulating film on the region of the integrated circuits 2 2 , 3 2 is removed by etching the thick gate insulating film in a state that the region of the integrated circuits 2 1 , 3 1 are covered with resist next , a thin gate insulating film is formed on regions including the integrated circuits 2 1 , 2 2 , 3 1 , 3 2 . the gate insulating film (= the thick gate insulating film + the thin gate insulating film ) on the regions of the integrated circuits 2 1 , 3 1 is thicker than the gate insulating film (= the thin gate insulating film ) on the regions of the integrated circuits 2 2 , 3 2 by the thick gate insulating film ). the thicknesses of the thick gate insulating film and the thin gate insulating film are selected such that the gate insulating films on the integrated circuits 2 1 , 3 1 are to be tox1 and the gate insulating films on the integrated circuits 2 2 , 3 2 are to be tox2 . thereafter , the gate electrodes , extensions , and source / drain regions are formed by conventional process . thereafter , a process for constructing the circuits by connecting the mosfets in the respective integrated circuits with wirings is followed . at this time , the mosfets tr 2 , 7 , 12 , and 17 are made dummy mosfets by disconnecting the mosfets tr 2 , 7 , 12 , and 17 electrically to other mosfets . or , the mosfets tr 2 , 7 , 12 , and 17 are made dummy mosfets by omitting extensions and source / drain regions in the mosfets tr 2 , 7 , 12 , and 17 . such dummy mosfets can be easily realized by forming a resist such that the ions are not implanted into the regions of the dummy mosfets in the process of ion implantations for forming extensions and source / drain regions . the plan views of the mosfets in the integrated circuits of the present embodiment are shown in fig1 and fig1 . in the drawings , g denote gate electrodes , sp denote spacers , s / d denote source / drain regions , d denote distances between the spacers on the active region ( element region ), and d ′ denote distances between the spacers on the isolation region . in the drawings , the mosfets in the integrated circuits 2 1 , 2 2 , 3 1 and 3 2 are not discriminated from one another . fig1 shows a plan view in a case of d = d ′, and fig1 shows a plan view in a case of d ≠ d ′. in a semiconductor manufacturing process , in particular , from the standpoint of a lithography process , as shown in fig1 , there is the advantage in the case in which the distances between the spacers are constant regardless of a place . next , another embodiment will be described . the semiconductor device of the present embodiment does not include dummy mosfets ( dummy gate electrode portion ). the spacers provided on sidewalls of the mosfets have thickness corresponding to the kind ( characteristic ) of the mosfets . fig1 to 18 are cross - sectional views showing the manufacturing method for the semiconductor device of the present embodiment . in the fig1 to 18 , the left side shows a mosfet ( first mosfet ) in the first nmos integrated circuit 2 1 , the right side shows a mosfet ( second mosfet ) in the first pmos integrated circuit 3 1 . each of the integrated circuits 2 1 , 3 1 includes a plurality of mosfet , however , for simplicity , only one mosfet in the each of the integrated circuits 2 1 , 3 1 is shown in the fig1 to 18 . first , the aforementioned steps of fig6 and 8 are carried out . next , as shown in fig1 , an insulating film 31 is formed on the entire region . here , the insulating film 31 is a silicon nitride film . next , as shown in fig1 , an insulating film 32 is formed on the insulating film 31 , thereafter , in a state that the first pmos integrated circuit 3 1 is covered with resist 33 , the insulating film 32 is etched by rie process . wet etching , which is isotropic etching , is better than rie process . as the result , the insulating film 32 on the first nmos integrated circuit 2 1 is removed . here , by using a bsg film as the insulating film 32 , the insulating film 32 can be etched in condition that the etching rate of the insulating film 32 is sufficiently higher than the etching rate of the insulating film 31 . therefore , the surface of the silicon substrate 21 is not exposed . that is , the substrate damage is suppressed . next , the resist 33 is removed , thereafter , as shown in fig1 , an insulating film 34 is formed on the entire region . here the insulating film 34 is a silicon nitride film . next , as shown in fig1 , the insulating film 34 is etched by rie process . as the result , a spacer 33 is formed on the gate sidewall of the first mosfet ( left side ), and spacers 32 , 33 are formed on the gate sidewall of second mosfet ( right side ). thickness of the spacer 33 of the first mosfet is t 1 , thickness of the spacers 32 , 33 is t 3 (& gt ; t 1 ). the thickness of the insulating films 31 - 33 is selected such that the thickness t 1 , t 2 can be obtained . thereafter , source / drain regions are formed as in the same way as the fig9 , further , the process for constructing the circuits by connecting the mosfets in the respective integrated circuits with wirings is followed . as in the same way as the present embodiment , the mosfet in the second nmos integrated circuit 2 2 and the mosfet in the second pmos integrated circuit 3 2 can be formed ( in a case of different channel types ). further , the mosfet in the first nmos integrated circuit 2 1 and the mosfet in the first pmos integrated circuit 3 1 , or the mosfet in the second nmos integrated circuit 2 2 and the mosfet in the second pmos integrated circuit 3 2 can be formed ( in a case of different power supply voltages ). in this case , the mosfet for the higher power supply voltage includes the thicker gate insulating film than the mosfet for the lower power supply voltage . further , the mosfet in the first nmos integrated circuit 2 1 and the mosfet in the first pmos integrated circuit 3 1 , and the mosfet in the second nmos integrated circuit 2 2 and the mosfet in the second pmos circuit 3 2 can be formed ( in a case of different channel types and power supply voltages ). the present embodiment is not limited to the above specific example . that is , it may be performed , if each of the thicknesses of the spacers is different for each of a plurality of mosfet line - ups which are subjected to the present invention . in the embodiments , the present invention is applied to the integrated circuits which do not include a memory and a peripheral circuit thereof , however , the present invention is applicable to an integrated circuit which includes a memory and a peripheral circuit such as a cache memory including a memory ( sram ) and a peripheral circuit , or an embedded dream including a dram and a peripheral circuit . additional advantages and modifications will readily occur to those skilled in the art . therefore , the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein . accordingly , various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents .