preferred embodiments of a display device according to a present invention will be explained in conjunction with accompanying drawings . fig2 is a schematic diagram showing the overall configuration of a liquid crystal display device according to the present invention . this drawing constitutes a plan view which is drawn corresponding to an actual geometrical arrangement . in the drawing , for example , a transparent substrate sub 1 , which is formed of a glass substrate , constitutes one of a pair of transparent substrates that are arranged to face each other in an opposed manner through a liquid crystal . on a central portion ( display portion ar ), excluding the periphery of the liquid - crystal - side surface of the transparent substrate sub 1 , gate signal lines gl , which extend in the x direction and are arranged in the y direction in the drawing , and drain signal lines dl , which extend in the y direction and are arranged in the x direction in the drawing , are formed . each region , which is surrounded by neighboring gate signal lines gl and the neighboring drain signal lines dl , define a pixel region . the pixel region is provided with a thin film transistor tft , which is operated upon receiving scanning signals from the gate signal line gl at one side and a pixel electrode px to which video signals are supplied from the drain signal line dl at one side through the thin film transistor tft . that is , scanning signals ( voltages ) are sequentially supplied to the respective gate signal lines gl from the top to the bottom in the drawing , for example , and the thin film transistors tft are turned on in response to these scanning signals . in synchronism with this timing , video signals ( voltages ) are supplied from the respective drain signal lines dl , and these video signals are applied to the pixel electrodes px through those thin film transistors tft that are in the on state . these respective pixel electrodes px generate an electric field between the pixel electrodes px and a counter electrode ( not shown in the drawing ) which is commonly formed at respective pixel regions on a liquid crystal side surface of other transparent substrate , which is arranged to face the transparent substrate sub 1 in an opposed manner , for example . the light transmittivity of the liquid crystal is controlled by this electric field . the respective gate signal lines gl have one end thereof ( left side in the drawing ) connected to a pixel driving shift register 1 , and the scanning signals are sequentially supplied to respective gate signals lines gl by the pixel driving shift register 1 . the respective drain signal lines dl have one end ( upper side in the drawing ) connected sequentially to a d - a conversion circuit 2 , a memory 3 , an input data entry circuit 4 and an h - side address decoder 5 , while a v - side address decoder 6 and a memory driving shift register 7 are connected to the memory 3 . to the liquid crystal display device having such a constitution , information including a start pulse clock signal , pixel data , a pixel address ( h ) and a pixel address ( v ) are inputted . the start pulse clock signal is inputted to the memory driving shift register 7 and the pixel driving shift register 1 . the pixel address ( h ) is inputted to the h - side address decoder 5 . the pixel data is inputted to the input data entry circuit 4 . the pixel address ( v ) is inputted to the v - side address decoder 6 . here , at a display part ar , which is formed on a surface of the transparent substrate sub 1 , and at respective circuits arranged around the display part ar , the thin film transistors ( mistft ) which are formed by laminating conductive layers , semiconductor layers , insulation layers and the like , and the pixel electrodes , the signal lines and the like , which are formed into a given pattern by an selective etching using a photolithography technique , are provided . in this case , the semiconductor layer is formed of polycrystalline silicon ( p — si ), for example . fig1 a is a circuit diagram showing one embodiment of the pixel driving shift register . further , fig1 b is a timing chart for the circuit shown in fig1 a , showing outputs vn 1 to vn 6 respectively corresponding to nodes n 1 to n 6 with respect to an input pulse φin and synchronous pulses φ 1 , φ 2 . in fig1 a , first of all , an n - type mos transistor nmt 1 is provided . of the source and drain terminals , one terminal is connected to an input terminal φin of the input pulse φin , and the gate terminal is connected to an input terminal of the synchronous pulse φ 1 . this mos transistor nnt 1 constitutes an inputting part . the other terminal of the mos transistor nmt 1 is connected to a gate terminal of an n - type mos transistor nmt 2 , one terminal of an n - type mos transistor nmt 4 and one terminal of a capacitance element cs 1 . the other terminal of the capacitance element cs 1 is connected to a fixed voltage vbias , and one terminal of the mos transistor nmt 2 is connected to an input terminal of the synchronous pulse φ 2 which forms an inverse phase with respect to the previously mentioned synchronous pulse φ 1 . the other terminal of the mos transistor nmt 2 is connected to one terminal of the n - type mos transistor nmt 3 and the gate terminal , and it is further connected to one terminal of the capacitance element cb 1 . the other terminal of the capacitance element cb 1 is connected to the other terminal of the mos transistor nmt 1 , the gate terminal of the mos transistor nmt 2 and one terminal of the n - type mos transistor nnt 4 . the other terminal of the mos transistor nmt 3 is connected to a gate terminal of an n - type mos transistor nmt 5 and one terminal of a mos transistor nmt 7 . further , the other terminal of the mos transistor nmt 3 is connected to one terminal of the capacitance element cs 2 . the other terminal of the mos transistor nmt 3 constitutes the first output terminal . the other terminal of the capacitance element cs 2 is connected to a fixed voltage vbias , and one terminal of the mos transistor nmt 5 is connected to an input terminal of the synchronous pulse φ 1 . the other terminal of the mos transistor nmt 5 is connected to one terminal and a gate terminal of an n - type mos transistor nmt 6 and a gate terminal of the mos transistor nmt 4 . the other terminal of the mos transistor nmt 5 is further connected to one terminal of the capacitance element cb 2 . the other terminal of the mos transistor nmt 5 constitutes the second output terminal . the other terminal of the capacitance element cb 2 is connected to the other input terminal of the mos transistor nmt 3 , the gate terminal of the mos transistor nmt 5 and one terminal of the n - type mos transistor nmt 7 . the other terminal of the mos transistor nmt 4 and the other terminal of the mos transistor nmt 7 are connected to a fixed power source or a ground potential ( vss / vdd ) which is equal to a voltage , which becomes a source voltage of the mos transistor out of the voltages of the above - mentioned synchronous pulses φ 1 , φ 2 ( minimum voltage when the transistor is of n - type and maximum voltage when the transistor is of p - type ), or which will be the source voltage of the first or the second synchronous pulse φ 1 , φ 2 which is not less than the threshold voltage value of mos transistor nmt 4 . such a connection is adopted in a next stage and succeeding stages in a similar manner , wherein the gate terminal of the mos transistor nmt 7 is connected to a gate terminal of a mos transistor nmt 9 corresponding to the mos transistor nmt 4 in the next stage . with respect to the shift register having such a constitution , as shown in fig1 a , one side of load capacitances cs 1 , cs 2 , cs 3 , . . . is respectively connected to the nodes n 1 , n 3 , n 5 , . . . which can be floating , and the other side of these load capacitances cs 1 , cs 2 , cs 3 , . . . is connected to a fixed potential vbias . due to such a constitution , the above - mentioned equation ( 9 ) can be rewritten as following equation ( 11 ). vn 3 = v φ ×( cdg 5 /( cdg 5 + cn 3 + cs 2 )) ( 11 ) here , the capacitance cs 2 constitutes a design parameter and , at the same time , can be formed of a direct parallel plate capacitance . even when the capacitance cn 3 is ignored , the output vn 3 can be expressed by the following equation ( 12 ). further , the following equation ( 13 ), which is formulated by adding the capacitance cs ( cs 2 from node n 3 ) to the previously mentioned equation ( 4 ), is satisfied . vn 1 =( vφ − v th )+ v φ ( cb /( cb + cs + cs ))& gt ; vφ + v th ( 13 ) from the above , the design tolerance , in the case in which the above - mentioned unstable elements are eliminated can be expanded so that the stable dynamic ratioless shift register which includes thin film transistors formed of polycrystalline silicon can be realized . fig3 a is a cross - sectional view of a thin film transistor which constitutes a circuit in which the above - mentioned dynamic ratioless shift register is formed on the transparent substrate sub 1 . in forming the load capacitance cs in this thin film transistor , the capacitance cs 1 between the polysilicon thin film and the wiring material , the capacitance cgl between the gate forming thin film and the wiring material , the capacitance ctg between the gate forming thin film and the pixel electrode , the capacitance ct 1 between the wiring material and the pixel electrode or the like can be designated a specific candidate . in the above - mentioned constitution , the added load capacitance cs performs an important role from the viewpoint of stable operation of the circuit and can enhance the degree of freedom of design . however , the load capacitance cs totally constitutes a parasitic capacitance from the view point of a bootstrap efficiency . accordingly , the mos capacitance shown in fig3 b and fig3 c are formed as the load capacitance cs , and the bootstrap efficiency can be enhanced with such load capacitance cs . that is , assuming that the fixed voltage vbias is set as expressed in a following equation ( 14 ), and the source side is connected to the floating node and the gate side is connected to the bias , a variable capacitance , can be generated in which , when the floating node n 3 , n 5 , . . . ) is “ l ”, an inversion layer is formed so that the capacitance becomes large ( csl ), while when the floating node ( n 3 , n 5 , . . . ) is “ h ”, the inversion layer is not present , so that the capacitance becomes small . ( css ). that is , the relationship expressed by a following equation ( 15 ) can be obtained . accordingly , the above - mentioned equations ( 12 ) ( 13 ) are respectively rewritten as following equations ( 16 ), ( 17 ) so that the stabilized capacitance becomes heavy and the bootstrap efficiency can be enhanced . fig4 shows another embodiment which represents a further improvement over the circuit shown in fig1 . in this embodiment , assuming a circuit which forms the first output of a next stage and a circuit which forms the second output in a subsequent stage in an inputting part as basic circuits , a mos transistor nmtr 2 is incorporated into the first - stage basic circuit and a mos transistor nmtr 1 and the mos transistor nmtr 2 are incorporated into the respective subsequent - stage basic circuits . in each basic circuit , the mos transistor nmtr 2 has the first terminal thereof connected to the seventh mos transistor nmt 4 , or the first terminal of a mos transistor corresponding to the seventh mos transistor nmt 4 and a gate terminal thereof connected to an input terminal of an input pulse tin . then , the second terminal of the mos transistor nmtr 2 is connected to a fixed power source or to a ground potential which is equal to a voltage which becomes a source voltage of the mos transistor out of voltages of respective synchronous pulses φ 1 , φ 2 ( the minimum voltage when the mos transistor is of n - type and the maximum voltage when the mos transistor is of p - type ), or which will be the source voltage of the first or second synchronous pulse φ 1 , φ 2 which is not less than the threshold voltage value of the fourth mos transistor . further , the transistor nmtr 1 has the first terminal thereof connected to the fourth mos transistor nmt 4 or the first terminal of a mos transistor corresponding to the fourth mos transistor nmt 4 and a gate terminal thereof connected to the input terminal of the input pulse φin . then , the second terminal of the mos transistor nmtr 2 is connected to a fixed power source or to a ground potential which is equal to a voltage which becomes a source voltage of the mos transistor out of voltages of respective synchronous pulses φ 1 , φ 2 ( the minimum voltage when the mos transistor is of n - type and the maximum voltage when the mos transistor is of p - type ) or which will be the source voltage of the first or second synchronous pulse φ 1 , φ 2 which is not less than the threshold voltage value of the fourth mos transistor . the dynamic ratioless shift register having such a constitution performs a resetting effect such that , when respective nodes are in an unstable circumstance such as at the timing of supplying electricity , the circumstance can be improved . further , in the above - mentioned respective circuits , the input part is not limited to the part shown in fig1 a and may be constituted as shown in fig5 in which one terminal and the gate terminal of the mos transistor nmt 1 are connected to an input terminal of the input pulse φin . with this arrangement , substantially the same effect can be obtained . fig6 a is a circuit diagram which shows another embodiment of a shift register formed in a liquid crystal display device according to the present invention . this embodiment is constituted differently from the embodiment 1 in which the off level is held by adding the load capacitance . that is , this embodiment is constituted such that a circuit is added which changes an input gate of a shift register which is not selected to “ l ”. that is , as shown in fig6 a , first of all , a mos transistor nmt 1 has the first terminal and a gate terminal thereof connected to an input terminal of an input pulse win thus forming an inputting part . the mos transistor nmt 1 has the second terminal thereof connected to a gate terminal of a mos transistor nmt 4 and the first terminal of a mos transistor nmt 2 . further , the second terminal of the mos transistor nmt 1 is connected to the first terminal of a capacitance element cb 1 . the second terminal of a capacitance element cb 2 is connected to the second terminal of a mos transistor nmt 4 and the first terminal and a gate terminal of a mos transistor nmt 5 . the first terminal of the mos transistor nmt 2 is connected to a gate terminal of a mos transistor nmt 7 and a gate terminal of the mos transistor nnt 2 and the second terminal of a mos transistor nmt 3 are connected to the second terminal of a mos transistor nmt 10 . the second terminal of the mos transistor nmt 2 is connected to a fixed power source vss or a ground potential ( vdd ) which is equal to a voltage , which becomes a source voltage of the mostft out of the voltages of the first and second synchronous pulses φ 1 , φ 2 , or which will be the source voltage of the first or second synchronous pulse φ 1 , φ 2 which is not less than the threshold value voltage of the mos transistor nmt 4 . further , the second terminal of the mos transistor nmt 3 is connected to the fixed power source vss or the ground potential ( vdd ), which is equal to the voltage which becomes the source voltage of the mostft out of the voltages of the first and second synchronous pulses φ 1 , φ 2 , or which is not different from the voltage which becomes the source voltage of the first or second synchronous pulse φ 1 , 92 to an extent that the fixed power source or the ground potential at least does not exceed a threshold value voltage of the mos transistor nmt 4 . the first terminal of the mos transistor nmt 4 is connected to the input terminal of the synchronous pulse φ 2 , while the second terminal of the mos transistor nnt 5 is connected to a gate terminal and a first terminal of a mos transistor nmt 6 , and is further connected to the first terminal of the capacitance element cb 2 . the second terminal of the capacitance element cb 2 is connected to the second terminal of a mos transistor nmt 8 , the first terminal and the gate terminal of a mos transistor nmt 9 and the first terminal and the gate terminal of the mos transistor nnt 1 thus constituting a first output terminal . the first terminal of the mos transistor nmt 6 is connected to a gate terminal of a mos transistor nmt 11 , while the second terminal of the mos transistor nmt 11 is connected to the fixed power source vss or to the ground potential ( vdd ), which is equal to the voltage which becomes the source voltage of the mostft out of the voltages of the first and second synchronous pulses φ 1 , φ 2 , or which will be the source voltage of the first or second synchronous pulse φ 1 , φ 2 which is not less than the threshold value voltage of the mos transistor nnt 4 . the first terminal of the mos transistor nmt 8 is connected to the input terminal of the synchronous pulse φ 1 and the second terminal of the tenth mos transistor nmt 9 , thus constituting a second output terminal . the gate terminal of the mos transistor nmt 6 and the first terminal of the mos transistor nmt 7 are connected to the second terminal of other mos transistor , which corresponds to the previously - mentioned mos transistor nmt 10 of a circuit of next stage which adopts a constitution similar to that of the above - mentioned circuit . the manner of operation of the shift register having such a constitution will be described hereinafter in conjunction with the timing chart shown in fig6 b . when the input pulse φin is changed such that “ l ” “ h ” at the time t 0 , the mos transistor nmt 3 is turned on so that the node n 5 and the ground potential vss (= gnd ) are connected so that the outputs vn 5 , vss become vn 5 = vss , the mos transistor nmt 2 , which uses node n 5 as the gate turns off and the node n 1 becomes the floating state . at this point of time , the output vn 1 of the node n 1 simultaneously becomes such that vn 1 = vφ − vth due to the diode connection of the mos transistor nmt 1 . when the relationship vφ − vth & gt ; vth is established , since vn 1 = vφ − vth , the mos transistor nmt 7 also turns on so that the node n 8 and the ground potential vss (= gnd ) are connected , whereby the relationship vn 8 = vss is established . further , the mos transistor nmt 6 , which uses the node n 5 as the gate , turns off , and the node n 3 becomes the floating state . at this point of time ; among the mos transistors nmt 5 which have the drains thereof connected to the synchronous pulses φ 1 , φ 2 , only the gates of the mos transistor nnt 4 and the mos transistor nmt 7 become the floating state . when the synchronous pulse φ 2 is changed such that “ l ” “ h ” at the time t 1 , since the mos transistor nmt 4 is in the on state , the potential of the node n 2 rises and the potential vn 2 becomes vn 2 = vφ due to the bootstrap capacitance cb 1 as mentioned previously . at this point of time , due to the boosting of voltage at the node n 1 , the output vn 1 rises until the voltage v 1 becomes vn 1 =( vφ − vth )+ vφ ( cb /( cb + cs )). however , the input pulse φin is in the “ h ” state and the gate of the mos transistor nmt 2 is set to the relationship vss (= gnd ) so that the forced off state is held . then , due to the mos transistor nmt 5 , which is subjected to the diode connection , the output vn 3 becomes vn 3 = vφ − vth . accordingly , the mos transistor nmt 11 , which uses the node n 3 as the gate becomes the on state , so that the node n 11 is changed such that “ h ” “ l ”, the mos transistor nnt 15 turns off , and the node n 6 becomes the floating state . at this point of time t 2 , the synchronous pulse φ 1 is changed such that “ l ” “ h ”, while the synchronous pulse φ 2 is changed such that “ h ” “ l ”. although the output vn 2 becomes “ h ” “ l ” when the synchronous pulse φ 2 is changed such that “ h ” “ l ”, the output vn 3 is held at “ h ”. when the synchronous pulse φ 1 is changed such that “ l ” “ h ”, the output vn 4 of the node n 4 becomes vn 4 = vφ through the mos transistor nmt 8 , which is in the on state . accordingly , the mos transistor nmt 16 which uses the node ng as the gate becomes the on state and the node n 14 is changed such that “ h ” “ l ” so that the mos transistor nmt 20 becomes the off state and the node n 9 becomes the floating state . simultaneously , due to the mos transistor nmt 10 , which is subjected to the diode connection , the output vn 5 becomes vn 5 = vφ − vth . accordingly , the mos transistor nmt 2 which uses the node n 5 as the gate becomes the on state so that the node n 1 and the ground potential vss are connected to each other and the mos transistor nmt 4 is forced off , in which the gate of the mos transistor nmt 4 is connected to the ground potential vss . since the mos transistor nmt 10 is subjected to the diode connection , even when the output vn 4 becomes vn 4 =“ l ” thereafter , the output vn 5 holds the “ h ” state ( previously - mentioned a element being omitted for the sake of brevity ). that is , until the input pulse φin becomes “ h ” again , the forced off state in which the gate of the mos transistor nnt 4 is connected to the fixed power source vss is held . at a point of time t 3 , the synchronous pulse φ 2 is changed such that “ l ” “ h ”, while the synchronous pulse φ 1 is changed such that “ h ” “ l ”. although the output vn 4 becomes “ h ” “ l ” when the synchronous pulse φ 1 is changed such that “ h ” “ l ”, the output vn 6 is held at “ h ”. when the synchronous pulse φ 2 is changed such that “ l ” “ h ”, the output vn 7 of the node n 7 becomes vn 7 = vφ through the mos transistor nmt 12 which is in the on state . due to the mos transistor nmt 13 , which is subjected to the diode connection , the output vn 9 becomes vn 9 = vφ − vth . accordingly , the mos transistor nnt 21 , which uses the node n 9 as the gate , turns on and the node n 14 is changed such that “ h ” “ l ” so that the mos transistor nnt 25 turns off and the node n 12 becomes the floating state . simultaneously , due to the mos transistor nmt 14 , which is subjected to the diode connection , the output vn 8 becomes vn 8 = vφ − vth . accordingly , the mos transistor nmt 6 , which uses the node n 8 as the gate , turns on so that the node n 3 and the ground potential vss are connected to each other and the mos transistor nnt 8 forced off in which the gate of the mos transistor nmt 8 is connected to the ground potential vss . since the mos transistor nmt 14 is subjected to the diode connection , even when the output vn 7 becomes vn 7 =“ l ” thereafter , the output vn 8 holds the “ h ” state ( previously - mentioned a element being omitted for the sake of brevity ). that is , until the voltage vin becomes the “ h ” again , the forced off state in which the gate of the mos transistor nnt 4 is connected to the ground potential vss is held . thereafter , the shift register is operated by sequentially repeating the above - mentioned operations . the shift register having the above - mentioned constitution is configured such that , among the mos transistors which are connected to the synchronous pulses φ 1 and φ 2 , unnecessary gates are all connected to the ground potential vss . accordingly , it becomes possible to make the mos transistor assume the forced off state so that the occurrence of instability in operation can be obviated . in the above - mentioned embodiment , the input part is not limited to the constitution shown in fig6 a . that is , as shown in fig8 , the input part may be constituted such that the first terminal of the mos transistor nnt 1 is connected to the input terminal of the input pulse φin and the gate terminal of the mos transistor nnt 1 is connected to the input terminal of the synchronous pulse φ . with this configuration , substantially the same advantageous effects can be obtained . fig7 a is a circuit diagram which shows another embodiment of the shift register formed on the liquid crystal display device of the present invention . in the drawing , a circuit is constituted such that thin film transistors nntr 1 , nmtr 2 , nntr 3 , . . . which are subjected to the diode connection using respective nodes n 11 , n 14 , n 17 , as sources thereof and the input pulse signal φin as drains and gates thereof are connected to the circuit exemplified in the embodiment 2 . these respective thin film transistors nmtr 1 , nntr 2 , nmtr 3 , . . . reinforce the “ h ” level of respective nodes in the floating state when the input pulse signal φin becomes the “ h ” state , thus making the forced off state of the non - selected input gate more reliable . further , an advantageous effect is obtained in that , at the start of scanning immediately after the supply of electricity , an initialization equal to that of the normal operating state can be performed . although the thin film transistors which constitute the shift register have been described as n - type transistors in the above - mentioned respective embodiments , it is needless to say that p - type transistors can be used as the thin film transistors . this is because , by using the absolute potential of “ h ” and “ l ” levels of respective signals in an inverted manner , the advantageous effects of the present invention can be obtained substantially in the same manner . further , although the thin film transistors are exemplified as mos transistors whose gate insulation films are made of sio 2 , for example , in the above - mentioned respective embodiments , it is needless to say that the gate insulation films may be made of sin , for example . fig1 is a circuit diagram showing another embodiment of a ratioless - type dynamic shift register which is used in the display device of the present invention . that is , this embodiment shows a further improvement of the dynamic shift registers shown in the above - mentioned respective embodiments . further . fig1 shows an input pulse timing chart of the circuit shown in fig1 . here , to clarify the characterizing portion of the ratioless - type dynamic shift register which is used in the display device of the present invention , a circuit diagram which is used for comparison is shown in fig1 . further , fig1 shows an input pulse timing chart of the circuit shown in fig1 . in such a circuit , a jumping of the h 1 clock is observed at a vss ( gnd ) level of a node 3 in fig1 . fig1 a illustrates this phenomenon , wherein an h 1 clock after an input signal hin appears at the vss ( gnd ) level ( lower side of the drawing ) of the node 3 . due to a pulse which enters a node 5 through a diode from a node 4 shown in fig1 , a mis transistor mtrl is turned on . if this state continues until the next frame time is over ( if leakage does not occur at the node 5 ), no problem arises . however , in actual operation as shown in fig1 d , the leakage of signals occurs at the node 5 . accordingly , the above - mentioned mis transistor mtrl turns off and , hence , the node 1 becomes the floating state and unstable . the similar phenomenon occurs also at the node 2 . in view of the above , in the ratioless dynamic shift register of this embodiment , which is used in the present invention , to a mis transistor mtr 2 which is connected to ground levels of respective outputs of respective stages of the dynamic shift register , a mis transistor mtr 3 , which is provided separately from the mis transistor mtr 2 , is connected in parallel . that is , the mis transistor mtrl shown in fig1 , which drops the potential level of the node 2 to the ground potential vss ( gnd ), is , first of all , constituted of the mis transistor mtr 2 and the mis transistor mtr 3 , which are connected in parallel . in such a constitution , the mis transistor mtr 3 has a function similar to that of the mis transistor mtr 1 shown in fig1 , while the mis transistor mtr 2 has a function of always dropping the node 1 to the vss level , except for a case in which a high signal is supplied to the node 1 shown in fig1 . to be more specific , the gate of the mis transistor mtr 2 is always held at the high state due to a potential charged in response to an h 2 clock . to avoid a phenomenon in which the charge which is charged to the node 7 leaks to the node 6 as a diode inverse current due to the lowering of the potential of the node 6 below the ground potential vss , a mis transistor mtr 9 is provided . in connection with the ratioless dynamic shift register having such a constitution , a step for charging the charge to the node 7 will be explained . first of all , since the node 6 constitutes a floating node ( the node which is not connected to the power supply ), the node 6 is oscillated in response to the timing of a clock h 2 ( see the waveform chart of the node 6 shown in fig1 ). during the period in which the node 1 is set to “ high ”, the potential at the node 7 is dropped to the vss level and becomes the floating state while holding this potential . thereafter , when the node 6 is elevated due to the clock h 2 , the current flows through the diode , and even when the potential of the node 6 is lowered , the charge is held due to the inverse - direction connection of the diode ( see the waveform chart of the node 7 shown in fig1 ). assuming that the charge held by the node 7 is lost due to a sort of leakage of current , the node 6 is oscillated in response to the timing of the clock h 2 so that the node 7 is charged again immediately . accordingly , the potential is set such that the potential is not lowered below ( vss −( vth of mtr 8 )) with the provision of the transistor mtr 9 . when the potential of the node 6 is set to the ground potential vss , the potential held by the node 7 is expressed by an equation (( high of amplitude of the node 6 )−( vth of the diode )). further , the amplitude , of the node 6 is determined by the capacitance c 1 and other floating capacitance c 0 and is expressed by an equation (( high of the clock h 2 )× c 1 /( ci + co )). further , in the ratioless dynamic shift register shown in fig1 , with respect to the ground levels other than signals of high level in the outputs of respective stages , means which surely drops the outputs to the ground levels is constituted of mis transistors mtr 4 , mtr 5 , mtr 6 , mtr 7 and mtrb . first of all , the mis transistors mtr 4 and mtr 5 will be described . the waveforms of the node 4 and the node 5 are formed as shown in the timing chart of fig1 in response to the clocks h 1 , h 2 , respectively . the node 4 and the node 5 become the on state when the clocks h 1 , h 2 become high and drop the potential of the node to the gate signal line to the vss level thus performing a role to make the node stable . in this case , when the node 2 is at the high level ( when the high level signal is outputted to the gate signal line ), the mis transistors mtr 6 and mtr 7 are turned on and the potentials of the node 4 and the node 5 are dropped to the vss level so that the mis transistors mtr 4 and mtr 5 are turned off . the mis transistor mtr 8 is connected to prevent the potential of the node 4 from becoming smaller than ( vss −( vth of mtr 8 )). when the potential of the node 4 is largely lowered from the ground potential vss , the amplitude of the clocks h 1 , h 2 does not meet the threshold voltage vth of the mis transistors mtr 4 , mtr 5 ( the potential equal to or more than vss + vth being necessary to turn on the mis transistors mtr 4 , mtr 5 ) and hence , the provision of mis transistors mtr 8 becomes meaningless . further , as shown in fig1 , this embodiment includes a mis transistor mtr 2 which is connected to the ground levels of respective outputs of respective stages , and a mis transistor which is operated with an output of the front stage and has one end thereof connected to the ground level and the other end thereof connected to the h 2 clock through the capacitance element c 1 and further connected to the gate of the mis transistor mtr 2 . a capacitance c 2 is disposed between the other end of the mis transistor mtr 2 and the ground level . when the potential of the node 1 is dropped to the vss level due to the node 3 , the node 7 becomes the floating node which is not connected to the vss level and , simultaneously , the node 2 is elevated in response to the hi clock . at this point of time , there exists a possibility that the gate ( node 7 ) is elevated due to the capacitance cg between the gate and the drain of the mis transistor mtr 2 so that the node 2 is connected with the ground potential vss . to prevent such a phenomenon , the capacitance c 2 is provided . accordingly , a boosted amount of potential at the node 7 becomes cg /( cg + c 2 + other floating capacitance ) times so that by increasing the capacitance c 2 compared to cg , the elevated amount of potential becomes a value which can be ignored . although the present invention has been explained with respect to dynamic ratioless shift registers which are provided for liquid crystal devices , for example , in the respective embodiments , the present invention is not limited to these shift registers and it is needless to say that the present invention is applicable to dynamic ratioless shift registers which are provided for el display devices , for example . as has been described heretofore , according to the present invention , the display device which includes the dynamic ratioless shift register which is operated in a stable manner and can expand the degree of freedom of designing can be realized .