as shown in fig1 a computer system 10 of the present invention comprises a mainframe computer 20 , a controller 30 , an array 40 of processing elements and a communication network 70 which interconnects the processing elements . this arrangement of mainframe computer , controller , array of processing elements and communication network is found in other bit - serial parallel processors such as those described in u . s . pat . 4 , 598 , 400 . mainframe computer 20 illustratively is a suitably programmed commercially available , general purpose computer such as a vax ™ computer manufactured by digital equipment corporation . controller 30 is an instruction sequencer of general design for generating a sequence of instructions that is applied to array 40 by means of a thirty - two bit parallel bus 34 . communication network 70 illustratively is a hypercube interconnection network such as those described in u . s . pat . no . 4 , 598 , 400 and application ser . no . 043 , 126 . array 40 comprises a multitude of processing elements 42 each of which comprises a read / write memory 44 , a first set 50 of sixteen bit - serial processors , a second set 52 of sixteen bit - serial processors , a transposer 56 and a word - oriented processor 60 . the memory , the bit - serial processors , and the transposer are interconnected by a thirty - two bit wide memory data bus 45 and the transposer and the word - oriented processor are interconnected by a thirty - two bit wide transposer data bus 57 . advantageously , each set 50 , 52 of sixteen bit - serial processors is implemented on a single integrated circuit and each bit - serial processor of a unit has associated with it a 64k × 1 bit portion of read / write memory 44 . memory 44 may be implemented in the form of thirty - two separate 64k × 1 bit memory chips . the interrelationship between the sets of sixteen bit - serial processor and memory 44 is described in detail in application ser . no . 902 , 290 and need not be discussed further . advantageously , as described in application ser . no . 939 , 599 , memory 44 also stores error control and correction ( ecc ) bits which can be used to detect and correct errors in the data stored in the memory . as this feature plays no part in the present invention , it is not illustrated in fig1 but it will be understood that additional memory and additional data paths are used for handling ecc bits . as shown in fig2 a single bit - serial processor 75 of any one of sets 50 , 52 and associated memory comprises an arithmetic logic unit ( alu ) 80 , a 64k × 1 bit read / write memory 90 and a flag register 94 . alu 80 has three single bit inputs a , b , f and two single bit outputs 82 , 83 . inputs a and b are obtained from addressed bit cells in memory element 90 and input f from a flag in flag register 94 . output 82 is provided to one of the addressed bit cells in memory 90 and output 83 is provided to the flag register . advantageously , alu 80 is implemented in the form of a series of look - up tables , each of which specifies the output on lines 82 and 83 that is produced by different arithmetic or logical functions in response to the eight possible combinations of input signals on the three inputs a , b , f . advantageously , as shown in fig2 each bit - serial processor 75 also has a context control 96 which makes it possible to selectively suppress the effect of any particular instruction received at the bit - serial processor from controller 30 . this makes it possible for the bit - serial processor to ignore instructions from the controller when conditions at the bit - serial processor make it desirable or even necessary to do so . for example , if a divisor stored in a particular bit - serial processor is a zero , it will be necessary for that individual processor to ignore a divide instruction issued by the controller to all the processors . as shown in fig3 word - oriented processor 60 comprises an alu 100 and thirty - two thirty - two - bit registers 102 . advantageously , the word - oriented processor is a commercially available processor . numerous such processors are available which are suitable for use in the practice of the invention . in particular the weitek model 3132 floating point processor has been implemented in the apparatus shown in fig1 ; and the sixty - four bit word weitek model 3164 floating point processor could readily be implemented if sixty - four bit words were desired . in addition to floating point processors , numerous other types of word - oriented processors may also be used in the practice of the invention . for example , depending on the application , integer processors such as those also made by weitek or signal processors such as those made by texas instruments could also be used . transposer 56 is a device for converting bit - serial data into word organized data . transposers are known in the art and are described , for example , in u . s . pat . no . 3 , 800 , 289 to batcher which is incorporated herein by reference . the general operation of transposer 56 is best understood from the simplified schematics of fig4 which depict an array 110 of memory cells arranged in n rows and m columns . transposing array 110 has n inputs , one for each column of cells and a single m - bit wide parallel output . data is input into array 110 from n sources by shifting the data from each of n sources serially down one of the columns of cells or by writing it into successive cells of a column under control of an address pointer 112 . data is read out of array 110 in parallel one column at a time , either by shifting it out or by reading it under control of a second address pointer 114 . thus , a transposer converts an array of data organized by rows to an array organized by columns ; and similarly , if columns of data are loaded into the transposer one at a time with each bit position in a column serving as one of the n sources , the transposer converts columns of data to an array organized by rows . transposers , accordingly , have the useful property that the transpose of the transpose of an input is the original input . to exploit this , the number of rows advantageously equals the number of columns , i . e . m equals n , so that the array of cells is square . in the practice of the invention , we have found it advantageous to use a transposer having several such transposing arrays 110 to access each such word - oriented processor as shown in fig5 . as depicted therein , a preferred embodiment of the transposer of the present invention comprises first and second internal transposer databuses 121 , 122 and first and second internal memories data buses 125 , 126 , a first plurality of two - to - one multiplexers 131 - 134 , a second plurality of two - to - one multiplexers 141 - 145 , a plurality of address pointers 151 - 155 , a plurality of transposing arrays 161 - 165 and seven - to - one output multiplexers 171 , 172 . the transposer also comprises register 175 , opcode decoder 181 , instruction decoder 182 , first and second bypass multiplexers 191 and 193 , bypass register 195 , condition register 197 and status register 199 . internal transposer databuses 121 , 122 are connected by drivers 123 , 124 to transposer databus 57 and internal memory buses 125 , 126 are connected by drivers 127 , 128 to memory databus 45 . data is supplied to the transposing arrays in bit - serial format on bus 125 from bus 45 or in word - parallel format on bus 121 from word - oriented processor 60 . data from the transposing arrays is applied to word - oriented processor 60 via bus 122 and to memory 44 or bit - serial processors 75 via bus 126 . multiplexers 131 - 134 are two - to - one multiplexers each having one input from the first transposer databus 121 and one input from one of the outputs ta - out , tb - out , tc - out and td - out of the transposing arrays 161 - 164 . the outputs of multiplexers 131 - 134 are supplied as one of the inputs to two - to - one multiplexers 141 - 144 . the other input to each of these multiplexers comes from internal memory bus 125 . the output of these multiplexers is provided to one of the transposing arrays 161 - 164 . the transposing arrays 161 - 164 are 32 × 32 arrays which operate as disclosed in connection with fig4 to convert bit - serial inputs to parallel word - oriented outputs under the control of address pointers 151 - 155 . the output of the transposing arrays is applied in parallel to multiplexers 171 , 172 . multiplexers 171 , 172 are seven - to - one multiplexers , each of which selects one input and provides it to internal memory databus 126 in the case of multiplexer 181 and to internal transposer databus 122 in the case of multiplexer 182 . signals on data bus 126 are then provided to memory 44 or units 52 , 56 of bit serial processors . signals on transposer databus 122 are provided via bus 57 to word - oriented processor 60 . transposing array 165 is a 13 × 32 array that is used for storing the status of floating point operations on the word - oriented processor . it is written from internal memory bus 125 or from a status bus 167 from the word - oriented processor under control of multiplexer 145 . since the status information is in coded form , a decoder 169 is used to decode the information supplied to this transposing array . decoders 181 and 182 are used to decode opcodes and instructions for the transposer . signals from these decoders are provided by control lines ( not shown ) to the various elements of the transposer . bypass register 195 is 32 bits wide and one word deep . as its name suggests , it may be used to bypass the transposing arrays . it can also be used to store status information in register 199 which can later be read out through multiplexer 193 . multiplexer 193 also permits instructions to be written into register 195 from the instruction decoder 182 . condition register 197 is a thirty - two bit wide register that is used to control multiplexers 131 - 134 and conditionalize various operations . register 175 supplies floating point conditional data from the word - oriented processor . in accordance with the invention , the use of a plurality of processing arrays makes it possible to pipeline the conversion of data from bit serial to word - oriented format for use by the word - oriented processor and to convert word - oriented data back to bit serial format for storage in memory 44 or for further processing in bit serial processors 50 , 52 . to describe the flow of data through the transposer , a compact notation will be used . a capital letter a , b , or c represents 64k 32 - bit single - precision floating point numbers , one for each data processor 75 in all the units 50 , 52 . when stored in a memory 44 , each number is stored in bit - serial format , and when in the word - oriented processor 60 it is in word - oriented format . the symbols &# 34 ; t0 &# 34 ;, &# 34 ; t1 &# 34 ; and &# 34 ; t2 &# 34 ; represent three transposing arrays in the transposer . the symbol &# 34 ; m &# 34 ; represents memory . the symbol &# 34 ; regfile &# 34 ; represents the thirty - two registers 102 of the word - oriented processor . the notation &# 34 ; x ( a )&# 34 ; represents x ( either memory , a transposing array or the register file ) holding the value of a for thirty - two processors . finally , the notation x ( a )-- y represents operand a moving from x to y . the operation of the transposer is represented in four columns of the following tables 1 , 2 and 3 . each horizontal line in each table represents a group of repeated operations . the first column ( cycles ) shows how many operations are performed . the second and third columns show what happens on the memory and transposer buses 45 , 57 of the transposer . the final column shows what happens at the word - oriented processor 60 . the example in table 1 introduces this notation for the case of a simple floating point multiply of a and b , resulting in c where values of a and b are initially stored in memories 44 for all 64k processors 75 in bit - serial format and the results c in bit - serial format are returned to these memories . the operation is done using only one transposing array . a line - by - line explanation of the table follows immediately after it . table 1______________________________________m ( a ) * m ( b ) -- m ( c ) line cycles memory bus transposer bus processor 60______________________________________1 32 m ( a ) -- t02 32 t0 ( a ) -- regfile3 32 m ( b ) -- t04 32 t0 ( b ) -- alu regfile ( a )* input ( b ) -- regfile5 32 regfile ( c ) -- t06 32 t0 ( c ) -- m______________________________________ line 1 : operand a in bitserial format is loaded from memory 44 into transposing array t0 . line 2 : the transposed form of operand a is written from transposing arra t0 to the register file 102 of the floating point processor . line 3 : operand b in bitserial format is loaded from memory 44 into transposing array t0 . line 4 : on each cycle , one of the thirtytwo instances of transposed operand b is written from transposing array t0 to the alu 100 of the floating point processor . the other input of the alu is supplied by the corresponding instance of operand a from the register file 102 . the resul c is stored back into the register file 102 in the same location as operand a , which is overwritten . line 5 : the result c in wordoriented format is moved from the register file 102 to transposing array t0 . line 6 : the result c , now transposed to bitserial format , is written from transposing array t0 into memory 44 . note that each operation ( each line of the table ) represents thirty - two cycles . assuming an operating speed of 6 . 5 mhz , the above operation requires thirty microseconds to perform a single precision floating point multiply for each processor , or 64k total 32 - bit multiplies . this results in a rate of 2 , 100 single - precision mflops for this operation . table 2 shows how the previous result can be improved if two transposing arrays are used . while the a operand is being moved from transposing array t0 to the register file , the memory bus is available to transfer operand b from memory to another transposing array . since the transposing arrays cannot be pipelined , a second transposing array is employed to take advantage of this unused bandwidth . with this pipelining , this operation now requires 24 microseconds , resulting in a rate of 2 , 600 mflops , or a speedup of 20 % over the unpipelined case . table 2______________________________________m ( a ) * m ( b ) -- m ( c ) line cycles memory bus transposer bus processor 60______________________________________1 32 m ( a ) -- t02 32 m ( b ) -- t1 t0 ( a ) -- regfile3 32 t0 ( b ) -- alu regfile ( a )* input ( b ) -- regfile4 32 regfile ( c ) -- t05 32 t0 ( c ) -- m______________________________________ as described in application ser . no . 832 , 913 , which is incorporated herein by reference additional processors in a single - instruction , multiple - data , parallel computer can advantageously be simulated by subdividing the memory associated with each physical processor into identical sub - memories and executing in sequence the same instruction or set of instructions on data stored at the same relative locations in each identical sub - memory . this same technique can also be used with the word - oriented processors of the present invention to further increase the computation rate of the word - oriented processors by maximizing use of the memory bus and the transposer bus . for example , in accordance with application ser . no . 832 , 913 , each physical processor can be made to simulate four processors by subdividing the memory assigned to each physical processor into four parts and performing the same set of operations on each of these four parts in turn . this operation is illustrated in table 3 which illustrates the performance of the same mathematical operation as in tables 1 and 2 but now it is performed on at least four simulated processors . to track the data , the operands or arguments supplied by the first processor are identified by a0 and b0 and the result of the operation is c0 ; the operands of the second processor are a1 and b1 and the result is c1 ; and so forth . table 3__________________________________________________________________________m ( a ) * m ( b ) -- m ( c ) line cycles memory bus transposer bus processor 60__________________________________________________________________________1 32 m ( a0 ) -- t02 32 m ( b0 ) -- t1 t0 ( a0 ) -- regfile4 32 m ( a1 ) -- t0 t0 ( b0 ) -- alu regfile ( a0 )* input ( b0 ) -- regfile5 32 m ( b0 ) -- t1 regfile ( c0 ) -- t26 32 t2 ( c0 ) -- m t0 ( a1 ) -- regfile7 32 m ( a2 ) -- t0 t1 ( b1 ) -- alu regfile ( a1 )* input ( b1 ) -- regfile8 32 m ( b2 ) -- t1 regfile ( c1 ) -- t29 32 t2 ( c1 ) -- m t0 ( a2 ) -- regfile10 32 m ( a3 ) -- t0 t1 ( b2 ) -- alu regfile ( a2 )* input ( b2 ) -- regfile11 32 m ( b3 ) -- t1 regfile ( c2 ) -- t212 32 t2 ( c2 ) -- m t0 ( a3 ) -- regfile__________________________________________________________________________ it can be shown that at an operating speed of 6 . 5 mhz this arrangement approaches a computation rate of 4 , 300 single precision mflops if a large number of processors are simulated . as will be apparent to those skilled in the art , numerous variations in the invention may be practiced .