in the following description of the embodiments , reference is made to the accompanying drawings that form a part hereof , and in which is shown by way of illustration of specific embodiments in which the invention may be practiced . it is to be understood that other embodiments may be utilized without departing from the scope of the present invention . it should be noted that the figures discussed herein are not drawn to scale and thicknesses of lines are not indicative of actual sizes . the cross section view in the figures is generally taken through the approximate center the memory cell in a plane perpendicular to the substrate except where otherwise noted . although only one cell is shown in the figures , the method may used for the simultaneous fabrication of a many cells on a wafer according to standard techniques . fig2 illustrates a cross sectional view of a completed memory cell according to a first embodiment of the invention wherein the sidewalls of the memory element and bottom electrode are covered by sidewall protection sleeve 200 . the material for sidewall protection sleeve 200 is selected to have a relative low etch rate in the etching gas ambient for dielectric material of etch stop layer 210 and is selected to be , for example , aluminum oxide , a borazinic film , silicon nitride , nitrogen - doped silicon carbide . a low dielectric constant borazinic film suitable for general mram applications can be deposited by a chemical vapor deposition ( cvd ) system such as the maple ( multi application plasma equipment ) cvd system of mitsubishi heavy industries . the sidewall protection layer 200 conforms to the shape of the patterned memory device and in this embodiment is an open - topped elliptical cone shape . after describing the completed device , the process of fabricating the device will be described and illustrated . the memory device includes a top electrode 120 , a bottom electrode 100 and an mtj element formed by fixed ferromagnetic layer 112 , free ferromagnetic layer 116 and barrier layer 114 . multi - layer structures can be substituted for single free and fixed layers in the mtj as is known in the art . the bottom electrode can be connected to a control device like a transistor or diode ( not shown ) in the standard manner . the top electrode is electrically connected by metal bit line interconnect 300 , which is typically copper . the via area of the bit line interconnect 300 around the centrally located memory device is formed by etching away the dielectric etch stop layer 210 down below the plane of the upper surface of the top electrode , then refilling with metal as part of the interconnect process . because the sidewall protection sleeve 200 extends the entire distance from the lower edge of the bottom electrode up onto the sides of the top electrode , the etching depth for the interconnect via in the dielectric etch stop layer 210 is less critical than in prior art designs . as long as the via exposes the upper surface of the top electrode , the depth of the via below the plane of the upper surface is not critical . the via could be etched all the way down the bottom electrode without causing a short failure . the invention , therefore , allows for higher yields even with inevitable variations in the etching depth during fabrication . the etch depth for the via in fig2 is shown at approximately the midpoint of the vertical height of the layer stack for the memory device as an example and variations in the depth are to be expected . the dielectric layer 220 is an inter - layer dielectric ( ild ). ild layer 220 is preferably silicon oxide , which works well for cmp planarization . an etch - stop layer 210 under ild 220 works as an etch - stop layer during etching of the ild 220 . the dielectric material for etch stop layer 210 is selected to have a relatively slow etching rate in the etching ambient gas used for layer 220 etching . a dielectric material is selected for the protection sleeve 200 to be resistant during etching of layer 210 . therefore , the protection sleeve 200 should be a different material than layer 210 . in embodiments a material such as aluminum oxide or a borazinic film is selected for the sidewall protection sleeve 200 , because it has slow etching rate in the typical ambient gas for layer 210 etching . the sidewalls of the memory element and the bottom electrode are covered by sidewall protection sleeve 200 , but the upper surface of the top electrode is left exposed to the bit line interconnect 300 . the sidewall protection sleeve 200 as shown extends almost to the plane of the upper surface of the top electrode and , therefore , covers most of the sidewall of the top electrode . the cross section view in fig2 and the other figures is taken through the approximate center the memory cell in a plane perpendicular to the substrate . in a plan view ( not shown ) parallel to the substrate surface the top electrode 120 and the other layers in the mtj are generally elliptically shaped and , therefore , the sidewall protection sleeve 200 , which conforms to the shape of the mtj will typically be an elliptically shaped concentric band . however , the shape of the mtj is not critical for any of the embodiments of the invention , because the sidewall protection sleeve will conform to whatever shape the mtj has . thus , the sidewall protection sleeve 200 is a generally a sleeve or ring of material that encircles the sidewalls of the layers of the memory element and the bottom electrode , separates these layers from contact with the surrounding metal material of bit line interconnect 300 , and thereby electrically insulates the sidewalls of these layers . the process of fabricating a memory cell according to the first embodiment invention will be described starting with fig3 . a vertical cross sectional illustration after patterning the memory element stack is shown in fig3 . the bottom electrode layer 100 , mtj layer stack 112 , 114 , 116 and the top electrode layer 120 are deposited in sequence . the film stack is then patterned using conventional photolithography and vertical etching . next a layer 200 ′ is deposited over the film stack as shown in fig4 a . this layer provides the bulk material for the sidewall protection structures 200 after controlled etching . the layer 200 ′ is vertically etched until the top electrode 120 is exposed , which leaves residual material on the sidewalls as shown in fig4 b forming the sidewall protection sleeve 200 . the exposed upper surface of top electrode 120 will be connected to the bit line in later process steps . as shown in fig5 a , etch stop layer 210 is then deposited over the patterned film stack . next the ild oxide layer 220 is deposited . the ild layer 220 is then planarized by chemical - mechanical polishing ( cmp ) as shown in fig5 a . from the state shown in fig5 a , conventional interconnect processing such as a dual damascene process is used . during the interconnect process , the sidewalls of the memory element and the bottom electrode are protected with the sidewall protection sleeve 200 . an exemplary dual damascene process can include multiple etch steps . for example , in one etch , using a photoresist mask defining the via , the exposed portion of the ild layer 220 overlying the etch stop layer 210 is removed . a subsequent etch removes the etch stop layer 210 from the via area around the memory element stack . during the etching , the memory element stack is protected by sidewall protection sleeve 200 which is resistant to etching ambient used to remove layer 210 . the result of the sequence of etching steps is shown in fig5 b . as noted above the via etching depth can be shallower or deeper than shown , with the requirement being that the upper surface of the top electrode is exposed . the remainder of the interconnect process is performed including depositing a metal , e . g ., copper , over the wafer to form the bit line connection to the top electrode . the result is the memory cell having a sidewall protection sleeve embodiment of the invention as shown in fig2 . in an alternative embodiment illustrated in fig1 , function of etch stop layer 210 is performed by sequentially deposited bottom and top etch stop layers 211 , 212 . the stage of the process illustrated in fig1 is comparable to the one illustrated in fig5 a but with two layers 212 , 211 replacing single layer 210 . fig1 illustrates a cross sectional view of a completed memory cell according to the alternative embodiment of the first embodiment of the invention with a single layer sidewall protection sleeve and a dual layer etch stop layer structure . the combined thickness of the two etch stop layers 212 , 211 is comparable to that of the single etch stop layer 210 . an advantage of this alternative embodiment is that it helps address the problem of thickness variations of ild 220 after cmp planarization across a wafer and between wafers . the material for the top etch stop layer 212 is selected to have high selectivity during etching of ild 220 so that the etching depth reliably stops in the top etch stop layer 212 even when the ild 220 is thinner than average . thus the added etch resistance provided by top etch stop layer 212 reduces variation resulting from the ild etching step caused by the thickness variation of ild 220 . the result is that variation of residual thickness of the layers over the memory element is considerably smaller compared that of ild 220 . the dielectric material for top etch stop layer 212 is selected to have a relatively slow etching rate in the etching ambient gas used for layer 220 etching so that etching stops in the layer 212 controllably . for example , the material for top etch stop layer 212 can be silicon nitride , nitrogen - doped silicon carbide , aluminum oxide or a borazinic film . the material for bottom etch stop layer 211 , for example , can be silicon nitride , silicon oxide , silicon carbide and so on is combined with a material of bottom top etch stop layer 212 . subsequent etching of the dual etch stop layer embodiment is well controlled by selecting an etching ambient that etches the material in top etch stop layer 212 at a rate that is equal to or faster than the material in bottom etch layer 211 . top etch stop layer 212 should not be the same material as ild layer 220 . the 3 materials for layers 220 , 212 , 211 should be selected with regard to each other . materials are selected using the following criteria . the etch rate of top etch stop layer 212 in ild layer 220 etching ambient is much smaller ( slower ) than ild layer 220 . this criterion is the same as for the single etch stop layer 210 embodiments . the etch rate of top etch stop layer 212 in bottom etch stop layer 211 etching ambient is comparable or faster than for top etch stop layer 212 . therefore , bottom etch stop layer 211 can be a same material as top etch stop layer 212 . a . top etch stop layer 212 =( nitrogen - doped silicon carbide , aluminum oxide or a borazinic film ) with bottom etch stop layer 211 =( silicon nitride , or silicon oxide ); b . top etch stop layer 212 =( silicon nitride ) with bottom etch stop layer 211 =( silicon nitride , or silicon oxide ). an exemplary embodiment can use a low k oxide such as silicon oxide for ild 220 , nitrogen - doped silicon carbide for top etch stop layer 212 , and silicon nitride ( low temperature ) for bottom etch stop layer 211 . a cross sectional view of the second embodiment of the invention with a dual - layer sidewall protection sleeve is illustrated in fig6 . the memory element is the same as in the first embodiment . a first layer 230 of sidewall protection is preferably an oxygen free dielectric to avoid oxidation of the mtj stack and can be patterned as described above for the first embodiment . the inner sidewall protection layer 230 is in contact with and covers the sidewall of the memory element . as in the first embodiment , the sidewall protection layer 230 conforms to the shape of the patterned memory element which in this embodiment is an open - topped cone . after the inner sidewall protection layer 230 has been etched down to expose the upper surface of the top electrode , the second sidewall protection layer 240 is deposited over and covers the inner sidewall protection layer 230 . for the outer sidewall protection layer 240 a material having a relatively slow etching rate in etching ambient gas used to etch layer 210 . the material can be selected to be aluminum oxide or a comparable material . the upper surface of top electrode 120 is not covered with either of the sidewall protection layers to allow connection to the bit line interconnect 300 for standard interconnection . the initial steps in a process according to second embodiment of the invention are generally the same as for the first embodiment , and the first sidewall protection layer 230 can be patterned as described above for layer 200 in the first embodiment . however , the material for the inner sidewall protection layer 230 , is preferably an oxygen free dielectric such as silicon nitride or a silicon carbide . a bulk dielectric material 240 ′ is deposited over the wafer and inner protection layer 230 as shown in fig7 which will be patterned into the outer sidewall protection layer 240 . the material for the outer sidewall protection layer 240 is preferably aluminum oxide or borazinic film or a comparable material . the outer sidewall protection layer 240 protects the inner sidewall protection layer 230 during the interconnect process . the outer sidewall protection layer 240 is vertically etched until top of the memory element is exposed to allow interconnection with the bit line as shown in fig8 . the process continues in the conventional manner after the outer sidewall protection layer 240 is vertically etched . etch stop layer 210 and ild oxide layer 220 are deposited sequentially . ild 220 is planarized by cmp as shown in fig8 . the etch stop layer 210 in the second embodiment as shown in fig8 can be replaced by a dual layer as described above for the first embodiment . a dual etch stop layer consisting of a top layer 212 and a bottom layer 211 is illustrated in fig9 . the stage of the process illustrated in fig9 is comparable to that shown in fig8 . fig1 illustrates a cross sectional view of a completed memory cell according to the alternative embodiment of the second embodiment of the invention with a dual - layer sidewall protection sleeve and a dual layer etch stop layer structure . it is followed by conventional interconnect processing such as a dual damascene process . after this processing , a memory cell having dual sidewall protection layers is completed as shown in fig6 . during the interconnect process , the outer sidewall protection layer 240 protects the inner sidewall protection layer 230 covering the sidewall of the memory element and thereby protects the memory element .