embodiments of the present application are directed to a capacitive sensing system . those of ordinary skill in the art will realize that the following detailed description of the capacitive sensing system is illustrative only and is not intended to be in any way limiting . other embodiments of the capacitive sensing system will readily suggest themselves to such skilled persons having the benefit of this disclosure . reference will now be made in detail to implementations of the capacitive sensing system as illustrated in the accompanying drawings . the same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts . in the interest of clarity , not all of the routine features of the implementations described herein are shown and described . it will , of course , be appreciated that in the development of any such actual implementation , numerous implementation - specific decisions must be made in order to achieve the developer &# 39 ; s specific goals , such as compliance with application and business related constraints , and that these specific goals will vary from one implementation to another and from one developer to another . moreover , it will be appreciated that such a development effort might be complex and time - consuming , but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure . in accordance with the present application , some of the components , process steps , and / or data structures may be implemented using various types of processing systems , including hardware , software , or any combination thereof . in addition , those of ordinary skill in the art will recognize that devices of a less general purpose nature , such as hardwired devices , application specific integrated circuits ( asics ), or the like , may also be used without departing from the scope and spirit of the inventive concepts disclosed herein . embodiments of a capacitive sensing system are configured to sense a capacitance value and convert the sensed capacitance value to a digital format . in some embodiments , the capacitive sensing system uses a sinusoidal excitation signal , provides flexibility in selection of the excitation frequency , and operates in spread spectrum mode . fig1 illustrates an exemplary block diagram of a capacitive sensing system according to an embodiment . a capacitor cx is a sensed capacitor . during a measurement mode of operation , a switch sw 2 is open , and a switch sw 1 is closed so that the sensed capacitor cx is 5 connected to a capacitance - to - amplitude converter 20 and a measured capacitance cx is input to the capacitance - to - amplitude converter 20 . the capacitance - to - amplitude converter 20 also receives as input an excitation signal provided by a signal generator 70 . in some embodiments , the signal generator 70 is a direct digital synthesis ( dds ) sine wave generator . in some embodiments , the excitation signal is a sinusoidal signal . in other embodiments , the excitation signal is a spread spectrum signal . within the capacitance - to - amplitude converter 20 , the measured capacitance cx is excited with the sinusoidal or spread spectrum signal . ac current flowing through the measured sensed capacitance is converted to ac voltage in the capacitance - to - amplitude converter 20 . the amplitude of the ac signal output from the capacitance - to - amplitude converter 20 is proportional to the measured sensed capacitance . the ac signal is output from the capacitance - to - amplitude converter 20 and input to a hybrid demodulator 30 , where the ac signal is demodulated to a dc compliment voltage . the dc voltage output from the hybrid demodulator 30 is proportional to the amplitude of the input ac signal . the hybrid demodulator 30 also receives as input a digital local oscillator ( lo ) signal . the ac signal input to the hybrid demodulator 30 is analog , but the input lo signal is digital . depending on the embodiment , the digital values of the lo signal represent samples of a sinusoidal wave , or a spread spectrum signal . the lo signal is a sequence of binary numbers coded using some number of bits n . in an exemplary implementation , n is equal to four . the values constituting the lo signal are generated in such a way that they are as close as possible to consecutive samples of a sinusoidal wave or a spread spectrum signal . in the hybrid demodulator 30 , the analog ac signal is multiplied by the digital lo signal . the two signals are aligned in phase and their multiplication results in a sum of a dc value and an ac signal of frequency being twice the frequency of the multiplied waveforms . the dc value is a dc component proportional to the input ac signal amplitude , and the ac component has a frequency twice the input ac signal frequency . the signal output from the demodulator 30 is amplified by amplifier 40 and input to an analog - to - digital converter ( adc ) 50 . in some embodiments , the adc 50 is a dual slope integrating adc . in other embodiments , any other conventional adc can be used . the adc is clocked by a clock generator 60 . the adc 50 outputs a digital conversion result , which is proportional to the dc component at the output of the hybrid demodulator 30 , which in turn is proportional to the sensed capacitance . the clock generator 60 also provides the clock signal to the dds sine wave generator 70 . in general , dds is an electronic method for digitally creating arbitrary waveforms and frequencies from a single , fixed source frequency . the dds sine wave generator 70 digitally generates two output waveforms according to the input clock signal . the first output is connected to a digital - to - analog converter ( dac ) 80 , which in turn outputs the analog excitation signal input to the capacitance - to - amplitude converter 20 via a low - pass filter 90 . the second output is the digital lo signal input to the hybrid demodulator 30 . the phase between the two output signals of the dds sine wave generator 70 is adjusted to compensate for a phase shift in the capacitance - to - amplitude converter 20 . the capacitance - to - amplitude converter 20 is an active circuit having some frequency response in the path from the excitation signal input to the converter output . the frequency response describes both amplitude and phase relationship between the input and the output signals . in general , both the signal amplitude and phase will be different at the output than at the input . the phase between the two dds outputs is adjusted to compensate for the phase shift of the excitation signal in the capacitance - to - amplitude converter 20 and in the low - pass filter 90 at the output of the dac 80 . the phase adjustment is achieved in the digital domain by adding a constant value to a phase accumulator in the dds sine wave generator 70 . in some embodiments , the spectral purity requirements for the excitation signal are low , and therefore the complexity of the dds sine wave generator 70 can also be low . fig8 illustrates an exemplary block diagram of the dds sine wave generator 70 according to an embodiment . the dds sine wave generator 70 includes a phase - to - amplitude converter 71 , a register 72 , an adder 73 , and a frequency control word generator 74 . the adder 73 functions as a phase accumulator . the phase - to - amplitude converter 71 converts phase generated by the phase accumulator 73 to instantaneous values at the dds output . in some embodiments , the phase - to - amplitude converter 71 converts linear phase into a sine wave . the input to the dac 80 ( fig1 ) is connected to the output of the phase - to - amplitude converter 71 . in an exemplary implementation , the size of the phase accumulator 73 within the dds sine wave generator 70 is equal to 10 bits , and the phase is truncated to 7 bits at the input of the phase - to - amplitude converter 71 . referring again to fig1 , the dac 80 that outputs the excitation signal is a low resolution converter . in an exemplary implementation , a 4 - bit dac is used to synthesize the excitation signal . in some embodiments , the low - pass filter 90 is a reconstruction filter configured to eliminate spectral images generated by the dac 80 . the bandwidth of the low pass filter 90 is set to accommodate the required frequency range of the excitation signal . since the adc 50 is clocked with the same clock signal as the dds sine wave generator 70 , the integration period equals an integer number of excitation signal cycles . in a dual slope integrating adc , the integration period is an amount of time , during which , the input signal is integrated in an adc internal integrator circuit . this results in perfect suppression of the ac components present at the output of the hybrid demodulator 30 without need of other filtering at the output of the hybrid demodulator 30 . the capacitive sensing system 10 includes a sensor gain error and an offset error which need to be compensated for during the conversion of a sensed capacitance . the sensor gain error and offset error are compensated by means of measuring a full scale capacitance and the offset error before each conversion of the sensed capacitance . during an offset cancellation phase , the switches sw 1 and sw 2 at the input of the capacitance - to - amplitude converter 20 are each opened , thereby disconnecting the full scale reference capacitor cref and the sensed capacitor cx . the offset error is then determined with the two capacitors disconnected , as described in relation to fig4 a and 4b below . during a full scale calibration phase , the switch sw 1 is open and the switch sw 2 is closed , thereby disconnecting the sensed capacitor cx . the sensor gain error , also referred to as the full - scale error is then determined , as described in relation to fig4 a and 4b below . during a measurement phase , the switch sw 1 is closed and the switch sw 2 is open , thereby disconnecting the full - scale reference capacitor cref . the sensed capacitance is then determined as described in detail above , the capacitance measurement result is adjusted to compensate for the determined sensor gain error and the offset error , as described in relation to fig4 a and 4b below . the capacitive sensing system includes at least the following features . first , the excitation signal is generated in digital domain using a simple dds circuit . in general , the complexity of a dds circuit is determined by the length of the phase accumulator , the number of bits driving the phase - to - amplitude converter , the number of bits in the output word , and the requirements for the spectral purity of the output signal . in most applications , a dds is used to generate a sinusoidal wave of high spectral purity . a conventional “ complex ” dds circuit requires the phase accumulator to have width of more than 20 bits , input to the phase - to - amplitude converter being more than 18 bits wide , and the dds output providing more than 16 bit resolution . the complexity of the phase - to - amplitude converter grows exponentially with the number of input bits . the dds sine wave generator 70 is “ simple ” in a sense that its performance and complexity is substantially lower than in typical dds implementations . this allows for easy generation of the sinusoidal excitation signal of arbitrary frequency by the dds sine wave generator 70 without any addition hardware , exact synchronization between the adc integration cycle time and the excitation signal frequency , and implementation of a hybrid analog / digital demodulator use of the hybrid analog / digital demodulator is advantageous because of its low complexity , low power consumption , and high accuracy compared to a strictly analog implementation . additionally , in this system where the lo signal is already synthesized using dds , the hybrid demodulator integrates a function of a dac and analog demodulator in one circuit having a complexity lower than the dac itself . the configuration of the dds sine wave generator 70 also allows for easy and precise synchronization and phase adjustment of the digital lo signal to the analog ac signal within the hybrid demodulator 30 without need for additional hardware dedicated to for those tasks , and simple implementation of a spread spectrum excitation signal . spread spectrum limits sensitivity to interference present at some distinct frequency , and also lowers the electromagnetic emissions measured in narrow band around a test frequency . second , the capacitive sensing system includes use of the hybrid analog / digital demodulator , which is easy to implement and can be connected directly to the output of the dds sine wave generator . third , the adc 50 is exactly synchronized with the excitation signal frequency , which allows for perfect suppression of ac components present at the demodulator output . fourth , the offset error and the full scale error are calibrated before each measurement by means of first disconnecting all capacitance from the sensor input and then connecting a known reference capacitance equal to the full scale of the converter . fifth , the excitation signal is converted from digital to analog in a very simple , low resolution dac . in this context , “ simple ” means a lower complexity . for example , in many conventional applications , it is uncommon for a dac used in signal synthesis to have resolution lower than 8 bits . in an exemplary implementation , a 4 - bit dac 80 is used to synthesize the excitation signal . it is understood that the capacitive sensing system is not limited to these features , and that other features and related advantages are readily apparent to those skilled in the art . fig2 illustrates an exemplary schematic diagram of the capacitance - to - amplitude converter 20 coupled to the sensed capacitor cx and reference capacitor cref of figure according to an embodiment . the capacitance - to - amplitude converter 20 is configured to output an ac signal with an amplitude proportional to the unknown measured capacitance cx . in fig2 , element i 00 is added between the capacitor cx and the switch sw 1 to represent the shield of the trace or wire connecting the sensed capacitance to the input of the sensor . in some embodiments , the wire and the shield have the same potential , which effectively cancels the shield capacitance and prevents it from affecting the measurement of the sensed capacitance . the exemplary component elements of the capacitance - to - amplitude converter 20 include an amplifier a 1 , an amplifier a 2 , resistors ri and r 2 , and capacitors c 1 and c 2 . the output ac signal of the capacitance - to - amplitude converter 20 is represented in fig2 as a differential signal output at the nodes n 3 and n 4 . the excitation signal received from the output of the low - pass filter 90 is coupled to the non - inverting input of the amplifier a 1 , and a feedback loop forces the same voltage at the inverting input of the amplifier a 1 . the feedback loop includes the capacitor c 2 , the noninverting input of the amplifier a 2 , the amplifier a 2 , the resistor r 1 , and the inverting input of the amplifier a 1 . the inverting input of amplifier a 1 is connected to the sensed capacitor cx . the frequency response of the capacitance - to - amplitude converter 20 , measured at the differential output , has a character of a high - pass filter response . the operating frequency of the capacitive sensing system 10 is sufficiently high above the corner frequency of the low - pass filter 90 , where the frequency response is flat . the corner frequency fd is calculated from the following formula : above the corner frequency f 0 , the frequency response is flat , and the output differential signal amplitude is equal to : where vext is the excitation voltage amplitude . from the above equation ( 2 ) it follows that the output differential signal amplitude is proportional to the measured sensed capacitance cx . the output differential signal amplitude does not depend on the excitation signal frequency . the capacitance - to - amplitude converter has a high - pass filter frequency response . as such , the capacitance - to - amplitude converter suppresses any dc current being injected into the sensor input . this prevents any leakage on the printed circuit board from effecting the sensed capacitance measurement . the maximum amount of dc current , which can be suppressed , is determined by the maximum voltage at the output of the amplifier a 2 divided by the value of the resistor r 1 . the topology of the capacitance - to - amplitude converter circuit results in an output amplitude of the ac signal being proportional to the measured sensed capacitance and independent of the excitation frequency . fig3 illustrates an exemplary schematic diagram of the hybrid demodulator 30 and the amplifier 40 of fig1 according to an embodiment . the exemplary component elements of the hybrid demodulator 30 include multiple resistors r , multiple resistors 2 r , and switches d 0 , d 1 , d 2 , d 3 . the exemplary component elements of the amplifier 40 include an amplifier 110 and multiple feedback resistors rf . the hybrid demodulator 30 functions similarly to a multiplying r 2 r dac . the four bits of the input digital lo signal control the toggle switches d 0 , d 1 , d 2 , and d 3 . if the corresponding bit has value “ 1 ,” the toggle switch is connected to the right terminal ( as shown in fig3 ), and if the bit has value “ 0 ”, the toggle switch is connected to the left terminal . the switches d 0 , d 1 , d 2 , d 3 , d 0 , d 1 , d 2 , d 3 are controlled by inverted bits of the digital lo signal . the two resistors rf constitute feedback , and through the feedback loop the amplifier 110 forces both inputs iout + and iout − to the same potential . with the same potential at nodes iout + and iout − and no current flowing through the high impedance inputs of the amplifier 110 , the current flowing through the two resistors rf can be expressed as : i out =((( v in +)−( v in −))/( 4 ≅ r ))≅(( 2 ̂− 1 )≅ a 3 +( 2 ̂− 2 )≅ a 2 +( 2 ̂− 3 )≅ a 1 +( 2 ̂− 4 )≅ a 0 ) ( 3 ) the coefficients a n take value 1 if the corresponding bit dn is “ 1 ,” or value − 1 if the corresponding bit dn is “ 0 .” the current iout flowing through the resistors rf creates a differential voltage vout at the output of the amplifier : v out =((( v in +)−( v in −))≅( rf )/( 2 r ))≅(( 2 ̂− 1 )≅ a 3 +( 2 ̂− 2 )≅ a 2 +( 2 ̂− 3 )≅ a 1 +( 2 ̂− 4 )≅ a 0 ) ( 5 ) equation ( 5 ) shows that the demodulator input differential voltage is multiplied by a value determined by the digital lo input word , as desired . the hybrid demodulator 30 receives as input the differential signal output from the capacitance - to - amplitude converter 20 of fig2 , shown in fig3 as input differential voltage ( vin +)−( vin −). the hybrid demodulator also receives as input the digital lo signal output from the dds sine wave generator 70 ( fig1 ). the output of the hybrid demodulator is an output differential current ( iout +)−( iout −), which is proportional to the input differential voltage and the digital lo signal . the input digital lo signal and the input differential voltage are multiplied together to perform the demodulating function . the amplifier 110 is configured according to a current - to - voltage converter configuration such that the input differential current ( iout +)−( iout −) is converted to a voltage . in contrast to a switching demodulator in which a square lo signal switches the sign of an input signal , the hybrid demodulator does not generate sensitivity at odd harmonics of the lo signal frequency . this behavior results in sensor immunity to noise and interference . fig4 a illustrates an exemplary block diagram of the adc 50 of fig1 according to an embodiment . the exemplary component elements of the adc 50 include switches swa and swb , an integrator 120 , an integrator 130 , an inverting buffer 140 , a comparator 150 , and a counter 160 . the adc 50 is configured to integrate the signal output from the amplifier 40 . the signal input to the adc 50 includes the dc component , proportional to the measured sensed capacitance , and the ac component , which is a byproduct of the synchronous demodulation performed by the hybrid demodulator 30 . the integration interval includes an integer number of the ac component cycles , and therefore the integration completely removes the ac component from the adc input signal . although shown in fig4 a as a single - ended analog input , the input of the adc is a differential analog signal . however , showing the signal flow in fig4 a with a single - ended signal makes the diagram easier to follow , without compromising its accuracy . the conversion performed by the adc 50 is performed in four phases . fig4 b illustrates an exemplary voltage versus time graph over the four phases for the voltage value v 1 at the output of the integrator 120 and the voltage value v 2 at the output of the integrator 130 . in phase one , the input of the sensor is disconnected from all capacitance , that is the capacitance - to - amplitude converter 20 is disconnected from the sensed capacitor cx and the reference capacitor cref by opening switches sw 1 and sw 2 ( fig1 ), and the adc 50 measures the offset voltage , which is the offset error . the switch swa is closed on terminal n 1 and the switch swb is closed , thereby coupling the inputs of integrators 120 and 130 to the adc input , and the offset voltage is integrated in both integrators . during the offset error measurement , the input signal to the adc 50 is inverted in order to subtract the offset from the adc conversion result . in the differential configuration , the input signal is inverted by means of swapping the positive and negative inputs to the adc . in the second phase , the switch swa is open , the switch swb is closed , the switch sw 1 ( fig1 ) is open , and the switch sw 2 ( fig1 ) is closed . the integrator 120 is disconnected from the adc input by opening the switch swa and the integrator 120 holds the voltage integrated in phase one . switch sw 2 ( fig1 ) is closed such that the capacitance - to - amplitude converter 20 is coupled to the reference capacitance cref . the switch swb remains closed so that the integrator 130 is coupled to the adc input , and the integrator 130 integrates the full scale signal . in phase three , the switch swb is open , the switch swa is closed on the terminal ni , the switch sw 1 ( fig1 ) is closed , and the switch sw 2 ( fig1 ) is open . the integrator 130 is disconnected from the adc input by opening the switch swb , and the integrator 130 holds the full - scale voltage integrated in phase two . the switch sw 2 ( fig1 ) is opened and the switch sw 1 ( fig1 ) is closed so that the capacitance - to - amplitude converter 20 is coupled to the sensed capacitor cx . the integrator 120 is coupled to the adc input through the switch swa closed on the terminal n 1 , and the integrator 120 integrates the measured signal . in phase four , the switch sw 1 ( fig1 ) is closed , the switch sw 2 ( fig1 ) is open , the switch swa is closed on terminal n 2 , and the switch swb is open . the full - scale voltage stored on the integrator 130 is used as a reference voltage to discharge the integrator 120 . the switch swa closed on the terminal n 2 couples the input of the integrator 120 to the output of the integrator 130 through the inverting buffer 140 . the length of phase four is used to determine the conversion result . the counter 160 is enabled from the beginning of phase four through the time when the output of the integrator 120 crosses zero volts , at which point the counter is disabled . at the end of phase four , the value in the counter 160 is the a - to - d conversion result , which is the output of the capacitive sensing system 10 . the discharge phase ( phase four ) duration of the integrator 120 varies with the adc input signal , and the integrator 120 therefore cannot be used to integrate the reference full scale level . the integrator 130 is used to integrate the full scale reference signal over an integer number of excitation signal cycles . in an exemplary application , the duration of the integration phases are as follows : phase one ( offset voltage integration ) is 100 usec ; phase 2 ( reference voltage integration ) is 100 usec ; phase three ( measured signal integration ) is 200 usec ; phase four ( discharge ) is up to 100 usec . this resulted in a total conversion time of approximately 500 usec . the conversion result c adc output from the counter 160 is expressed by the following equation : n fs is a full scale code . the full scale code is a digital value at the adc output , which corresponds to the input capacitance at the high end of the input capacitance range . t i is an integrator time constant . ti is the time constant of the integrator 130 . t 2 is the duration of the reference voltage integration phase , which is the same phase as phase two described above . cx is the measured sensed capacitance . cr is the reference capacitance . the conversion result output from the adc 50 is independent of the analog front end gain . the dc component at the adc input ( or demodulator output ) is proportional to the input capacitance , but the proportionality constant , or gain , is not exactly known and can vary with temperature , power supply voltage , etc . equation ( 6 ) indicates that the proportionality constant does not affect the conversion result , and therefore its variability is irrelevant . the conversion result output from the adc 50 is also independent of the excitation signal amplitude and the excitation signal frequency . if the full scale error is to be tightly controlled , the full scale error can be trimmed and it will not change due to the excitation frequency or amplitude variation , or changes of the analog front end gain . in some embodiments , a spread spectrum excitation signal is used to further reduce the circuit sensitivity to electromagnetic interference as well as to reduce the electromagnetic emissions . a spectrum spreading algorithm generates a spread spectrum excitation signal occupying only a specified frequency band and caring little energy outside the band . in the capacitance sensing system 10 , due to the way the ac signal components are suppressed in the integrating adc 50 , the spread spectrum excitation signal has to be periodic , with adc integration time equaling an integer number of the excitation signal periods . these requirements can be met if the spread spectrum excitation signal frequency is continuously swept up and down during the adc integration phase , which includes the integration phases one , two , and three described above in relation to fig4 b . integration phase four has variable duration , and thus , its duration cannot stay in any fixed relationship to the excitation signal period . the frequency of the spread spectrum excitation signal is swept by means of varying a frequency control word within the dds sine wave generator 70 . fig5 illustrates a value of an exemplary dds frequency control word as a function of time in the spread spectrum mode . the plot of fig5 shows one exemplary implementation , in which the dds frequency control word is swept with a period of 512 dds clock cycles , and the dds phase accumulator length is equal to 10 bits . fig6 illustrates an exemplary spectral plot of a spread spectrum excitation signal resulting from application of the dds frequency control word of fig5 . in order for the spread spectrum excitation signal to be periodic with the same period as the period of the dds frequency control word sweep , the phase accumulation in the dds sine wave generator 70 over the frequency control word sweep period has to be a multiple of 2π . such a condition is met by the frequency control word generator 74 shown in fig7 . the frequency control word generator 74 of fig7 is included in the dds sine wave generator 70 ( fig1 ). in the frequency control word generator 74 of fig7 , the spread spectrum frequency band is programmed by providing the range of the frequency sweep as input b to the accumulator 1 , and writing the bottom end of the frequency range fb , as an initial value in the accumulator 2 . if both values band fb are even , the phase accumulation in the dds sine wave generator 70 over the frequency control word sweep is a multiple of 2π . if both values band fb are not even , then the phase accumulation in the dds sine wave generator 70 over the frequency control word sweep is not a multiple of 2π . the spectrum spreading frequency control word generator generates a strictly periodic signal and allows for easy programmability of the signal frequency range . if the spread spectrum excitation signal is used , the hybrid demodulator 30 ( fig1 ) becomes a correlator . in general , in a spread spectrum mode , the signal coming to both inputs of the hybrid demodulator 30 ( the input from the capacitance - to - amplitude converter 20 and the input from the dds sine wave generator 70 ) can be considered random noise . in this case , the multiplication function of the hybrid demodulator 30 results in a dc component , which is proportional to the correlation between the two signals . in this spread spectrum mode , the output signal from the hybrid demodulator 30 still includes the dc component , which is proportional to the input signal amplitude , and the ac component , which is completely suppressed in the integrating adc 50 . it is understood that the schematic diagrams shown for the capacitance - to - amplitude converter , the hybrid demodulator , the adc , the dds sine wave generator , and the frequency control word generator are for exemplary purposes only , and that alternative configurations that result in the same functionality are also contemplated . the present invention has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of the invention . such references , herein , to specific embodiments and details thereof are not intended to limit the scope of the claims appended hereto . it will be apparent to those skilled in the art that modifications can be made in the embodiments chosen for illustration without departing from the spirit and scope of the invention .