hereinafter , embodiments of the present invention will be described with reference to the drawings . a drive circuit in the embodiments of the present invention can apply a matrix - type flat panel display device using a capacitive load , for instance , an ac drive - type pdp device 1 , of which entire configuration is shown in fig1 , and of which cell configuration is shown in fig1 . in the embodiments explained below , explanation will be made for the case of applying it to the ac drive - type pdp device 1 shown in fig1 and fig1 as an example . in the respective embodiments , only a y - side circuit 3 will be explained with reference to the drawing , but an x - side circuit 2 can be configured similarly to the y - side circuit 3 , or similarly to a drive circuit shown in fig1 . fig1 is a view showing a configuration example of a drive circuit according to a first embodiment of the present invention . in fig1 , a load 20 is total capacity of a cell formed between a common electrode x and a scanning electrode y which is an arbitrary scanning electrode among a plurality of scanning electrodes y 1 to yn . in the load 20 , the common electrode x and the scanning electrodes y are formed . the y - side circuit for driving the scanning electrode y includes a negative potential supply circuit 30 , in addition to a power supply circuit 22 and a drive circuit 21 . the power supply circuit 22 includes a capacitor cy 1 , and three switches swy 1 , swy 2 , swy 3 . the switches swy 1 and swy 2 are connected in series between a first power supply line through which a voltage vs is supplied from a first power source and a ground ( gnd ) which is a reference potential . one of terminals of the capacitor cy 1 is connected to an interconnection point of the two switches swy 1 and swy 2 , and the switch swy 3 is connected between the other terminal of the capacitor cy 1 and the ground . note that a signal line connected to one terminal of the capacitor cy 1 is taken for a first signal line outay and a signal line connected to the other terminal is taken for a second signal line outby . each of three switches swy 1 , swy 2 and swy 3 is usually composed of a mosfet , an igbt ( insulated gate bipolar transistor ) or the like . but the switch swy 3 can also be formed with only a diode connecting a cathode thereof to the ground side . the drive circuit 21 are provided with two switches swy 4 and swy 5 . the switches swy 4 and swy 5 are connected in series to both sides of the capacitor cy 1 of the power supply circuit 22 , namely , between the first and second signal lines outay and outby . an interconnection point of the two switches swy 4 and swy 5 is connected to the scanning electrode y of the load 20 via an output line outcy . here , the drive circuit 21 can be composed of a circuit for conducting a selective operation of the scanning electrode y for each line by outputting a scan pulse at the time of scanning during an address period for selecting a display cell based on display data d ( period to conduct the selective operation of the switches swy 4 and swy 5 in sequence ), and the circuit for conducting a sustain discharge operation at the scanning electrodes y of the total lines by outputting sustain pulses during the sustain discharge period for conducting discharge to make a display cell emit light according to the display data d ( period for performing charge and discharge to and from the load 20 repeatedly using the switches swy 4 and swy 5 ), namely , a line drive circuit . in other words , the drive circuit 21 can be formed by using a scan drive circuit which applies the scan pulse to the scanning electrode y during the address period and applies the sustain pulse during the sustain discharge period . the negative potential supply circuit 30 is provided with a switch swy 6 . the switch swy 6 is connected between an interconnection point ( node na ) of the switches swy 1 and swy 2 , and a second power supply line in which a voltage (− vy ) (− vy ≦ vs ) is supplied from the second power source . in other words , the switch swy 6 is connected between the second power source line and the first signal line outay . next , operation of the drive circuit shown in fig1 will be explained with reference to fig2 to fig4 . fig2 is a waveform diagram showing an operation during the address period in a drive circuit shown in fig1 . as shown in fig2 , explanation will be made assuming an initial state in which the switches swy 1 , swy 3 , swy 5 , and swy 6 are off , and the switches swy 2 and swy 4 are on , and an electric charge in accordance with the voltage vs has already been stored in the capacitor cy 1 . at this time , the voltage of the first signal line outay is at the ground potential level , the voltage of the second signal line outby is (− vs ), and the voltage of the first signal line outay is applied to the load 20 ( y electrode ) via the output line outcy . first , at a time t 1 , the voltage of the first signal line outay is reduced to (− vy ) by turning the switch swy 2 off and the switch swy 6 on , and the voltage is applied to the load 20 via the output line outcy . the voltage of the second signal line outby becomes lower than that of the first signal line outay by the voltage vs in accordance with the electric charge stored in the capacitor cy 1 , that is , (− vs − vy ). next , at a time t 2 when the address pulse at the voltage va is applied to the address electrode similarly to the conventional manner , the switch swy 4 is turned off , and the switch swy 5 is turned on . thereby , the voltage (− vs − vy ) of the second signal line outby is applied to the load 20 via the output line outcy . thereafter , at a time t 3 , the voltage (− vy ) of the first signal line outay is again applied to the load 20 via the output line outcy by turning the switch swy 5 off and the switch swy 4 on . next , at a time t 4 , the voltage of the first signal line outay increases to the ground potential level by turning the switch swy 6 off and the switch swy 2 on . thereby , the voltage of the second signal line outby becomes (− vs ). as described above , by controlling the switches swy 1 to swy 6 , a scan pulse having lower potential (− vs − vy ) than the conventional potential (− vs ), that is , the potential difference between the ground potential level and the reference potential is large , can be applied to the load 20 ( y electrode ). fig3 is a waveform diagram showing an operation of the sustain discharge period by the drive circuit shown in fig1 . as shown in fig3 , explanation will be made assuming an initial state in which the switches swy 1 , swy 3 , swy 5 , and swy 6 are off , and the switches swy 2 and swy 4 are on . at this time , the voltage of the first signal line outay is at the ground potential level , the voltage of the second signal line outby is (− vs ), and the voltage of the first signal line outay is applied to the load 20 via the output line outcy . at a time t 11 , the switch swy 2 is turned off and at the same time the switches swy 1 and swy 3 are turned on . thereby , the voltage in the first signal line outay increases to vs and the voltage in the second signal line outby goes to the ground potential level . further , the voltage vs in the first signal line outay is applied to the load 20 via the output line outcy . at this time , the electric charge corresponding to the voltage vs which is given by the switches swy 1 and swy 3 is stored in the capacitor cy 1 . next , at a time t 12 , the voltage in the first signal line outay is reduced to the ground potential level by turning the switches swy 1 and swy 3 off , and the switch swy 2 on , which is applied to the load 20 via the output line outcy . further , the voltage of the second signal line outby becomes lower than that of the first signal line outay by the voltage vs which corresponds to the electric charge stored in the capacitor cy 1 , namely , the voltage (− vs ). next , at a time t 13 , the switches swy 2 and swy 4 are turned off , and the switches swy 5 and swy 6 are turned on . thereby , the voltage (− vy ) of the first signal line outay is reduced further , which leads the voltage of the second signal line outby to (− vs − vy ). further , since the switch swy 4 is turned off , and the switch swy 5 is turned on , the voltage (− vs − vy ) of the second signal line outby is applied to the load 20 via the output line outcy . thereafter , at a time t 14 , by turning the switches swy 5 and swy 6 off , and the switches swy 2 and swy 4 on , the voltage of the first signal line outay increases to the ground potential level , and the voltage of the second signal line outby becomes (− vs ). further , since the switch swy 4 is turned on again , the voltage of the first signal line outay is applied to the load 20 via the output line outcy . next , at a time t 15 , the switch swy 2 is turned off and at the same time the switches swy 1 and swy 3 are turned on in a similar manner to that at the time t 11 . hereinafter , operations described above are repeated a predetermined number of times . as described above , by controlling the switches swy 1 to swy 6 , the sustain pulse having a potential (− vs − vy ) lower than the conventional (− vs ) can be applied to the load 20 . fig4 is a waveform diagram showing another example of the operation during the sustain discharge period in the drive circuit shown in fig1 . in the operation during the sustain discharge period showing the waveform diagram thereof in fig3 , the voltage applied to the load 20 is directly changed between the ground potential level and the voltage (− vs − vy ), but the operation during the sustain discharge period shown in fig4 is intended to change once between the ground potential level and the voltage (− vs − vy ) via the voltage (− vs ). since operations by a time t 22 are similar to operations by the time t 12 shown in fig3 , the explanation thereof will be restrained . at a time t 23 , the switch swy 4 is turned off , and the switch swy 5 is turned on . thereby , the voltage (− vs ) of the second signal line outby is applied to the load 20 via the output line outcy . next , at a time t 24 , by turning the switches swy 2 off , and swy 6 on , the voltage of the first signal line outay is further reduced to (− vy ), which leads a voltage of the second signal line outby to reach (− vs − vy ). then , a voltage applied to the load 20 via the output line outcy becomes (− vs − vy ). thereafter , at a time t 25 , by turning the switch swy 6 off , and the switch swy 2 on , the voltage of the first signal line outay increases to the ground potential level , and the voltage of the second signal line outby reaches (− vs ). accordingly , the voltage applied to the load 20 via the output line outcy becomes (− vs ). then , at a time t 26 , the switch swy 5 is turned off and the switch swy 4 is turned on . through this operation , the voltage of the second signal line outby is applied to the load 20 via the output line outcy . next , at a time t 27 , the switch swy 2 is turned off , and the switches swy 1 and swy 3 are turned on . hereinafter , operations described above are similarly repeated a predetermined number of times . as described above , by controlling the switches swy 1 to swy 6 , the sustain pulse having a potential of (− vs − vy ) can be applied to the load 20 similarly to the operation showing the wave diagram thereof in fig3 . as explained above , according to the first embodiment , a negative potential (− vy ) is supplied from the negative potential supply circuit 30 to the first signal line outay in a state that electric charge in accordance with the voltage vs is stored in the capacitor cy 1 . thereby , a voltage of the second signal line outby is made to (− vs − vy ) lower than (− vs ) so that this voltage can be applied to the load 20 via the output line outcy . further , even when the negative potential (− vy ) is supplied from the negative potential supply circuit 30 to the first signal line outay , the voltages applied to the respective switches swy 1 to swy 6 including the switches swy 4 and swy 6 in the drive circuit are vs at maximum . accordingly , the voltage larger than was previously possible can be applied to the load 20 without enhancing the withstand voltage of the respective switches swy 1 to swy 6 in the drive circuit . besides , for instance , when a voltage of the scan pulse applied during the address period as shown in fig2 is made to be (− vs − vy ) which is lower than the conventional value of (− vs ), it becomes possible to make the potential difference between the scan pulse and the address pulse large , in other words , becomes possible to obtain a large selection potential . then , a voltage margin relating to addressing can be increased to perform a stable address discharge . further , for instance , when the voltage of the sustain pulse applied during the sustain discharge period as shown in fig3 and 4 is made (− vs − vy ) lower than the conventional (− vs ), it becomes possible to make the potential difference between the scanning electrode y and the common electrode x due to the sustain pulse is made large so that the brightness per one sustain pulse can be made large , which results in improvement in display quality . next , a second embodiment of the present invention will be explained . the second embodiment explained below further includes a coil circuit for realizing an electric power recovery function in the drive circuit according to the first embodiment described above . fig5 is a view showing an example of configuration of the drive circuit according to the second embodiment of the present invention . in fig5 , the same symbols and numerals are attached to components having the same functions as the components shown in fig1 . therefore , overlapping explanation thereof will be restrained . in fig5 , a coil circuit a is connected between an interconnection point of two switches swy 1 and swy 2 , and a ground , and a coil circuit b is connected between an interconnection point of a switch swy 3 and a capacitor cy 1 , and the ground . in other words , the coil circuit a is connected between a first signal line outay and the ground , and the coil circuit b is connected between a second signal line outby and the ground . the coil circuit a includes a diode da , a coil la , and a switch swy 7 . a cathode terminal of the diode da is connected to an interconnection point of the switches swy 1 and swy 2 , and an anode terminal is connected to the ground via the coil la and the switch swy 7 . the swy 7 is provided to prevent current from flowing in from the coil circuit a when the negative potential (− vy ) is supplied from a negative potential supply circuit 30 to the first signal line outay . the coil circuit b includes a diode db and a coil lb . the anode terminal of the diode db is connected to the interconnection point of the switch swy 3 and the capacitor cy 1 , and the cathode terminal is connected to the ground via the coil lb . the coils la and lb are composed to perform an l - c resonance with a load 20 via the switches swy 4 and swy 5 . as shown in forward directions of the diodes da and db , the coil circuit a is a charge circuit for supplying an electric charge to the load 20 via the switch swy 4 , and the coil circuit b is a discharge circuit for releasing an electric charge to the load 20 via the switch swy 5 . an electric power recovery function to the load 20 is realized by properly controlling timing of a charge process of the charge circuit composing of the coil circuit a , the switch swy 4 , and the load 20 , and a discharge process of the discharge circuit composing of the coil circuit b , the switch swy 5 and the load 20 . incidentally , the coil circuit b shown in fig5 is configured without including a switch , but it is also acceptable to include a switch similarly to the coil circuit a . fig6 is a waveform diagram showing the operation during the address period in the drive circuit shown in fig5 . the operation during the address period represented by the wave diagram in fig6 is different only in that the switch swy 7 in the coil circuit a is turned off while the switch swy 6 is turned on , that is , only while negative potential is supplied to the first signal line outay from the negative potential supply circuit 30 ( during the times from t 31 to t 34 in fig6 ), and is similar to the operation during the address period of the drive circuit in the first embodiment shown in fig2 . times t 31 , t 32 , t 33 and t 34 in fig6 correspond to times t 1 , t 2 , t 3 and t 4 in fig2 , respectively . accordingly , in the drive circuit shown in fig5 , it is possible to apply the scan pulse of (− vs − vy ) lower in potential than was previously possible to the load 20 by controlling the switches swy 1 to swy 6 as shown in fig2 , and turning the switch swy 7 off during the switch swy 6 is turned on . fig7 is a waveform diagram showing an operation during the sustain discharge period by the drive circuit shown in fig5 . as shown in fig7 , explanation will be made assuming an initial state in which the switches swy 1 , swy 2 , swy 3 , swy 5 and swy 6 are off , and the switches swy 4 and swy 7 are on . at this time , a voltage of the first signal line outay is increasing gradually owing to the function of the coil circuit a , and the voltage of the first signal outay is applied to the load 20 via the output line outcy . the voltage of the first signal line outay turns the switches swy 1 and swy 3 on to clamp the voltage of the first signal line outay at vs at a time t 41 , at which the voltage is near the peak of its rise ( before reaching the voltage vs ). next , the switches swy 1 , swy 3 , and swy 4 are turned off at a time t 42 , and then at a time t 43 , the switch swy 5 is turned on . thereby , the second signal line outby and the output line outcy are connected electrically . accordingly , the voltage of the output line outcy is gradually decreasing and at the same time , a portion of the electric charge is recovered by the coil circuit b . at a time t 44 , at which the voltage is near the lowest point of its descent ( i . e ., before reaching the voltage (− vs ), the voltage of the second signal line outby is clamped to (− vs − vy ) by turning the switch swy 7 off , and the switch swy 6 on . next , after the switches swy 5 and swy 6 are turned off , and the switch swy 7 is turned on at a time t 45 , the switch swy 4 is turned on at a time t 46 . thereby , the first signal line outay and the output line outcy are electrically connected to each other . accordingly , the voltage of the first signal line outay is increased by the function of the first coil circuit a ( releasing of the electric charge , namely , discharging ), and as it increases , the voltage of the output line outcy is also gradually increased . hereinafter , operations described above are similarly repeated a predetermined number of times . as described above , it is possible to apply the sustain pulse having a potential of (− vs − vy ) lower than the conventional potential of (− vs ) to the load 20 while realizing the electric power recovery function owing to the coil circuits a and b , by controlling the switches swy 1 to swy 7 . as explained above , according to the second embodiment , it is possible to obtain the similar effect to that obtained by the drive circuit of the first embodiment described previously , and at the same time to realize an electric power recovery function by the coil circuit so that power consumption of the ac drive type pdp device can be reduced . it should be noted that in the second embodiment described above , the drive circuit in which the coil circuit a for supplying an electric charge to the load 20 as shown in fig5 is connected to the fist signal line outay , and the coil circuit b for discharging the electric charge to the load 20 is connected to the second signal line outby , is explained as an example , but the present invention is not limited to this . for instance , as shown in fig8 , it is also possible to apply the present embodiment to a drive circuit in which a coil circuit c provided with a function to supply an electric charge to the load 20 and together with a function to discharge the electric charge to the load 20 , is connected to the second signal line outby . fig8 is a view showing another example of configuration of the drive circuit according to the second embodiment . in this fig8 , the same symbols and numerals are attached to component and the like having the same functions as the component and the like shown in fig5 , so that overlapping explanation thereof will be restrained . in fig8 , the coil circuit c includes diodes dc 1 and dc 2 , coils lc 1 and lc 2 , and switches swy 8 and swy 9 . a function to discharge electric charge to the load 20 is realized by the diode dc 1 , the coil lc 1 and the switch swy 8 . an anode terminal of the diode dc 1 is connected to a second signal line outby , and a cathode terminal of the diode dc 1 is connected to the ground via the coil lc 1 and the switch swy 8 . similarly , a function to supply electric charge to the load 20 is realized by the diode dc 2 , the coil lc 2 and the switch swy 9 . a cathode terminal of the diode dc 2 is connected to the second signal line outby and an anode terminal of the diode dc 2 is connected to the ground via the coil lc 2 and the switch swy 9 . further , for instance , as shown in fig9 , it is also possible to apply the present embodiment to a drive circuit in which a coil circuit a for discharging electric charge to a load 20 is connected to a first signal line outay , and a coil circuit b for supplying electric charge to the load 20 is connected to a second signal line outby . fig9 and fig1 are views showing still another examples of the drive circuit according to the second embodiment . in these fig9 and fig1 , the same symbols and numerals are attached to components having the same functions as the components shown in fig5 , so that overlapping explanation thereof will be restrained . in fig9 , the coil circuit a includes a diode da , a coil la and a switch swy 7 . an anode terminal of the diode da is connecting an interconnection point ( a first signal line outay ) of switches swy 1 and swy 2 , and a cathode terminal is connected to the ground via the coil la and the switch swy 7 . further , the coil circuit b includes a diode db , a coil lb and a switch swy 10 . a cathode terminal of the diode db is connected to an interconnection point ( a second signal line outby ) of a switch swy 3 and the other terminal of a capacitor cy 1 , and an anode terminal is connected to the ground via the coil lb and the switch swy 10 . in fig1 , a ramp wave generation circuit 40 includes a resistor ry 1 and a switch swy 11 . the ramp wave generation circuit 40 is a circuit to generate a ramp wave waveform which changes an impressed voltage value according to the time , which can supply a negative potential (− vy ), instead of a negative potential supply circuit 30 , to the first signal line outay more slowly than the negative potential supply circuit 30 . further , during a reset period , the potential of generated ramp wave can be reduced to (− vs − vy ) by turning the swy 11 of the ramp wave generation circuit 40 on . it is also possible to obtain an effect similar to that of the drive circuit shown in fig5 , with the drive circuit according to the second embodiment shown in fig8 to fig1 . fig1 is a waveform diagram showing the operation of an ac drive type pdp device 1 in the embodiments of the present invention . fig1 shows an example of the waveform of the voltage applied to a common electrode x , a scanning electrode y and an address electrode in a sub - field portion of a plurality of sub - fields which form one frame . one sub - field is divided into the reset period composing of the entire writing period and the entire erasing period , the address period and the sustain discharge period . incidentally , the waveform diagram shown in fig1 shows the case of the drive circuit having the negative potential supply circuit 30 and the ramp wave generation circuit 40 described above on the y side drive circuit . during the reset period , the voltage applied to the common electrode x is first reduced from the ground potential level , the reference potential , to (− vs ). on the other hand , the voltage applied to the scanning electrode y is gradually increased with time and a final voltage obtained by combining the writing voltage vw and the voltage vs is applied to the scanning electrode y . thus , the potential difference between the common electrode x and the scanning electrode y becomes ( 2 vs + vw ) in spite of being still in a display state as before , discharge is performed in all cells of whole display lines , so that a wall electric charge is formed . ( entire writing ). next , after the voltage of the scanning electrode y is restored to vs , the voltage applied to the common electrode x is gradually increased from (− vs ) to vs , and at the same time , the impressed voltage to the scanning electrode y is gradually reduced from the voltage vs as time passes . on the scanning electrode y side , a final voltage (− vs − vy ) is applied to the scanning electrode y by turning the switch swy 11 of the ramp wave generation circuit 40 on . thereby , a discharge is started because the voltage of the wall electric charge itself exceeds the discharge start voltage over all cells , so that the stored wall electric charge is erased ( entire erasing ). next , during the address period , in order to perform on / off of respective cells according to display data , the address discharge is performed linear sequentially . at this time , the voltage vs is applied to the common electrode x . by controlling the respective switches swy 1 to swy 6 on the scanning electrode y side as shown in fig2 or fig6 , a scan pulse at (− vs − vy ) level is applied to the scanning electrode y selected linear sequentially , and the voltage (− vy ) is applied to a not - selected scanning electrode y , when a voltage is applied to a scanning electrode y corresponding to a certain display line . at this time , the address pulse at a voltage va is selectively applied to an address electrode aj corresponding to a cell causing the sustain discharge , that is a cell to be lit , among respective address electrodes a 1 to am . as a result , discharge is taken place between the address electrode aj of the cell to be lit and the scanning electrode y selected linear sequentially , and a certain amount of wall electric charge required for next sustain discharge is stored on an mgo protection film surface over the common electrode x and the scanning electrode y , using the above discharge as a priming ( pilot frame ). it should be noted that though fig . 11 shows an example in which the address period is divided into a first half address period ( for instance , sequential scan pulses are applied to the scanning electrodes y in odd numbered lines ) and the second half address period ( for instance , sequential scan pulses are applied to scanning electrodes y in even - numbered lines ), it is also acceptable to apply the sequential scan pulse to the scanning electrode y without dividing the address period . thereafter , during the sustain discharge period , sustain discharge is performed by applying a predetermined voltage ( sustain pulse ) in a manner that the phases are in a reverse relation to each other to the common electrode x and the scanning electrodes y of respective display lines , so that an image of one sub - field is displayed . at this time , as a sustain pulse , voltages (+ vs , − vs ) are alternately applied to the common electrode x . and as shown in fig3 , by controlling the respective switches swy 1 to swy 6 , voltages (+ vs , − vs − vy ) are alternately applied as a sustain pulse to the scanning electrode y . note that the switch control is not limited to that shown in fig3 above , it is acceptable to apply voltages (+ vs , − vs − vy ) alternately to the scanning electrode y by controlling the switches as shown in fig4 and fig7 described above . note that the voltage ( vs + vx ) is applied only when a high voltage is applied first to the scanning electrode y during the sustain discharge period . this voltage vx is that to be added for generating a voltage necessary to the sustain discharge by adding to the voltage of the wall electric charge generated during the address period . the present embodiments are to be considered in all respects as illustrative and no restrictive , and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein . the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof . according to the present invention , by supplying a potential lower than the reference potential to the first signal line from the potential supply circuit , the potential of the second signal line connected to the first signal line via the capacitor is made to be a third potential lower than the second potential so that the third potential is applied to the capacitive load from the second signal line . accordingly , since no voltage larger than the potential difference between the reference potential and the first and second potential is applied to the respective elements in the drive circuit , a voltage having a potential difference larger than was previously possible in relation to the reference potential can be applied to the capacitive load without increasing withstand voltage of the respective elements .