an illustration of a 3gpp 8 - state parallel concatenated convolutional code ( pccc ), with coding rate 1 / 3 , constraint length k = 4 is illustrated in fig2 . an implementation using siso log - map decoders is illustrated in fig3 . in accordance with an exemplary embodiment , a diversity processing turbo codes decoder includes two parallel blocks 40 a , 40 b of turbo codes decoders for each path of received data rxda and rxdb . each identical turbo codes decoder block 40 a , 40 b has concatenated max log - map siso decoders a 42 and b 44 connected in a feedback loop with interleaver memory 43 and interleaver memory 45 . the soft output of turbo codes decoder block 40 a is fed into the input of the diversified logic block 48 . conversely , the soft output of turbo codes decoder block 40 b is fed - back into the input of the diversified logic block 48 . the sum of the two outputs z 1 , z 3 of the turbo codes decoder block 40 a , 40 b is fed into the hard - decoder to generate output y data . the diversified logic block 48 computes the intrinsic feedback values z 5 for the input into the turbo codes decoder blocks 40 a and 40 b through adder 231 . signals ra 2 , ra 1 , ra 0 are received soft decision signals of data path a from the system receiver . signals xo 1 and xo 2 are output soft decision signals of the log - map decoders a 42 and b 44 , respectively , which are stored in the interleaver memory 43 and memory 45 module . signals z 2 and z 1 are the output of the interleaver memory 43 and interleaver memory 45 . z 2 is fed into log - map decoder b 44 and z 1 is looped back into log - map decoder a 42 through adder 231 . signals rb 2 , rb 1 , rb 0 are received soft decision signals of data path b from the system receiver . signals xo 1 and xo 2 are output soft decision of the log - map decoders a 42 and b 44 , respectively , which are stored in the interleaver memory 43 and memory 45 module . signals z 4 and z 3 are the output of the interleaver memory 43 and interleaver memory 45 . z 4 is fed into log - map decoder b 44 and z 3 is looped back into log - map decoder a 42 through adder 231 . in accordance with the invention , signal z 5 is fed back into log - map decoder a 42 of block 40 a through adder 231 , and signal z 5 is fed back into log - map decoder a 42 of block 40 b through adder 231 for diversity processing . each interleaver memory 43 , 45 , shown in fig2 , includes one interleaver 201 and a dual - port ram memory 202 . input memory blocks 41 , 48 , 49 , shown in fig2 , includes dual - port ram memory 211 . control logic module ( clsm ) 47 consists of various state - machines , which control all the operations of the turbo codes decoder . the hard - decoder module 46 outputs the final decoded data . more particularly , as illustrated in fig3 , ra 0 , rb 0 are data bits corresponding to the transmit data bit u , ra 1 , rb 1 are the first parity bits corresponding to the output bit of the first rsc encoder , and ra 2 , rb 2 are interleaved second parity bits corresponding to the output bit of the second rsc encoder . in accordance with the invention , corresponding ones of data bits ra 0 , rb 0 are added to the feedback signals z 5 , z 1 and z 3 , then fed into the decoder a . corresponding ones of data bits ra 1 , rb 1 are also fed into decoder a for decoding the first stage of decoding output x 01 . z 2 and corresponding ones of ra 2 , rb 2 are fed into decoder b for decoding the second stage of decoding output x 02 . in accordance with the invention , as shown in fig5 , the turbo codes decoder utilizes a sliding window of block n 61 on the input buffers 62 to decode one block n data at a time , the next block n of data is decoded after the previous block n is done in a circular wrap - around scheme for pipeline operations . in another embodiment , the sliding window of block n is used on the input buffer memory so that each block n data is decoded at a time one block after another in a pipeline scheme . in accordance with the invention , the turbo codes decoder decodes an 8 - state parallel concatenated convolutional code ( pccc ). the turbo codes decoder also decodes a higher n - state parallel concatenated convolutional code ( pccc ) as illustrated in fig3 , the turbo codes decoder functions effectively as follows : received soft decision data ( rxda [ 2 : 0 ]) is stored in three input buffers memory blocks 48 , 49 , 41 to produce data bits ra 0 , ra 1 , and ra 2 that correspond to data words . each output data word ra 0 , ra 1 , ra 2 contains a number of binary bits . received soft decision data ( rxdb [ 2 : 0 ]) is stored in three input buffers memory blocks 48 , 49 , 41 to produce rb 0 , rb 1 , and rb 2 that correspond to data words . each output data word rb 0 , rb 1 , rb 2 contains a number of binary bits . a sliding window of block n is imposed onto each input memory to produce corresponding ones of ra 0 , rb 0 , ra 1 , rb 1 , ra 2 , and rb 2 output data words . in accordance with the method of the invention , when an input data block of size n is ready , the turbo decoder starts the log - map decoder a , in block 40 a , to decode the n input data based on the soft - values of ra 0 , z 1 , z 5 and ra 1 , then stores the outputs in the interleaver memory a . the turbo decoder also starts the log - map decoder b , in block 40 a , to decode the n input data based on the soft - values of ra 2 and z 2 , in pipelined mode with a delay latency of n , then stores the output in the interleaver memory . when an input data block of size n is ready , the turbo decoder starts the log - map decoder a , in block 40 b , to decode the n input data based on the soft - values of rb 0 , z 5 , z 3 and rb 1 , then stores the outputs in the interleaver memory a . the turbo decoder also starts the log - map decoder b , in block 40 b , to decode the n input data based on the soft - values of rb 2 and z 4 , in pipelined mode with a delay latency of n , then store the outputs in the interleaver memory . the turbo decoder performs iterative decoding for l number of times ( l = 1 , 2 , . . . , m ). the log - map decoder a receives the sum of ( z 1 and z 3 and corresponding ones of ra 0 , rb 0 as inputs . the log - map decoder a also receives corresponding ones of ra 1 , rb 1 as inputs . the log - map decoder b receives the data z 2 and r 2 as inputs . when the iterative decoding sequence is complete , the turbo decoder starts the hard - decision operations to compute and produce soft - decision outputs . as shown in fig6 , siso log - map decoders 42 , 44 include a branch metric ( bm ) computation module 71 , a state metric ( sm ) computation module 72 , a log - map computation module 73 , a bm memory module 74 , a sm memory module 75 , and a control logic state machine module 76 . soft - value inputs enter the branch metric ( bm ) computation module 71 , where euclidean distance is calculated for each branch , the output branch metrics are stored in the bm memory module 74 . the state metric ( sm ) computation module 72 reads branch metrics from the bm memory 74 and computes the state metric for each state ; the output state - metrics are stored in the sm memory module 75 . the log - map computation module 73 reads both branch - metrics and state - metrics from bm memory 74 and sm memory 75 modules to compute the log maximum a posteriori probability and produce soft - decision output . the control logic state - machine module 76 provides the overall operations of the decoding process . as shown in fig6 which is one example of 3gpp turbo codes decoder , the log - map decoder 42 44 functions effectively as follows : the log - map decoder 42 , 44 reads each soft - values ( sd ) data pair input , then computes branch - metric ( bm ) values for all paths in the turbo codes trellis 80 as shown in fig7 . the computed bm data is stored into bm memory 74 . the process of computing bm values is repeated for each input data until all n samples are calculated and stored in bm memory 74 . the log - map decoder 42 44 reads bm values from bm memory 74 and sm values from sm memory 75 , and computes the forward state - metric ( sm ) for all states in the trellis 80 as shown in fig7 . the computed forward sm data is stored into sm memory 75 . the process of computing forward sm values is repeated for each input data until all n samples are calculated and stored in sm memory 75 . the log - map decoder 42 44 reads bm values from bm memory 74 and sm values from sm memory 75 , and computes the backward state - metric ( sm ) for all states in the trellis 80 as shown in fig7 . the computed backward sm data is stored into the sm memory 75 . the process of computing backward sm values is repeated for each input data until all n samples are calculated and stored in sm memory 75 . the log - map decoder 42 44 then computes log - map posteriori probability for u = 0 and u = 1 using the bm values and sm values from bm memory 74 and sm memory 75 . the process of computing log - map posteriori probability is repeated for each input data until all n samples are calculated . the log - map decoder then decodes data by making soft decision based on the posteriori probability for each stage and produces soft - decision output , until all n inputs are decoded . the branch metric ( bm ) computation module 71 computes the euclidean distance for each branch in the 8 - states trellis 80 as shown in the fig7 based on the following equations : where sd 0 and sd 1 are soft - value input data and g 0 and g 1 are the expected input for each path in the trellis 80 . g 0 and g 1 are coded assigned antipodal values , meaning that 0 corresponds to + 1 and 1 corresponds to − 1 . therefore , the local euclidean distances for each path in the trellis 80 are computed by the following equations : as shown in the exemplary embodiment of fig8 , the branch metric computing module includes one l - bit adder 91 , one l - bit subtracter 92 , and a 2 ′ complementer 93 . the euclidean distances are computed for path m1 and m5 . path m2 is 2 ′ complement of path m1 . path m6 is 2 ′ complement of m5 . path m3 is the same path m2 , path m4 is the same as path m1 , path m7 is the same as path m6 , path m8 is the same as path m5 , path m9 is the same as path m6 , path m10 is the same as path m5 , path m11 is the same as path m5 , path m12 is the same as path m6 , path m13 is the same as path m2 , path m14 is the same as path m1 , path m15 is the same as path m1 , and path m16 is the same as path m2 . the state metric computing module 72 calculates the probability a ( k ) of each state transition in forward recursion and the probability b ( k ) in backward recursion . fig1 shows the implementation of state - metric in forward recursion with add - compare - select ( acs ) logic . fig1 shows the implementation of state - metric in backward recursion with add - compare - select ( acs ) logic . the calculations are performed at each node in the turbo codes trellis 80 ( fig7 ) in both forward and backward recursion . fig1 shows the forward state transitions in the turbo codes trellis 80 ( fig7 ). fig1 shows the backward state transitions in the turbo codes trellis 80 ( fig7 ). each node in the trellis 80 as shown in fig7 has two entering paths : one - path 84 and zero - path 83 , from the two nodes in the previous stage . in an exemplary embodiment , the acs logic includes an adder 132 , an adder 134 , a comparator 131 , and a multiplexer 133 . in the forward recursion , the adder 132 computes the sum of the branch metric and state metric in the one - path 84 from the state s ( k − 1 ) of previous stage ( k − 1 ). the adder 134 computes the sum of the branch metric and state metric in the zero - path 83 from the state ( k − 1 ) of previous stage ( k − 1 ). the comparator 131 compares the two sums and the multiplexer 133 selects the larger sum for the state s ( k ) of current stage ( k ). in the backward recursion , the adder 142 computes the sum of the branch metric and state metric in the one - path 84 from the state s ( j + 1 ) of previous stage ( j + 1 ). the adder 144 computes the sum of the branch metric and state metric in the zero - path 83 from the state s ( j + 1 ) of previous stage ( j + 1 ). the comparator 141 compares the two sums and the multiplexer 143 selects the larger sum for the state s ( j ) of current stage ( j ). a ( k )= max [( bm 0 + sm 0 ( k − 1 )), ( bm 1 + sm 1 ( k − 1 )] b ( j )= max [( bm 0 + sm 0 ( j + 1 )), ( bm 1 + sm 1 ( j + 1 )] time ( k − 1 ) is the previous stage of ( k ) in forward recursion as shown in fig1 , and time ( j + 1 ) is the previous stage of ( j ) in backward recursion as shown in fig1 . the log - map computing module calculates the posteriori probability for u = 0 and u = 1 , for each path entering each state in the turbo codes trellis 80 corresponding to u = 0 and u = 1 or referred as zero - path 83 and one - path 84 . the accumulated probabilities are compared and the u with larger probability is selected . the soft - decisions are made based on the final probability selected for each bit . fig9 shows the implementation for calculating the posteriori probability for u = 0 . fig1 shows the implementation for calculating the posteriori probability for u = 1 . fig1 shows the implementation of compare - and - select for the u with larger probability . fig1 shows the implementation of the soft - decode compare logic to produce output bits based on the posteriori probability of u = 0 and u = 1 . the equations for calculating the accumulated probabilities for each state and compare - and - select are shown below : sum — s 01 = sm 3 i + bm 7 + sm 1 j sum — s 02 = sm 4 i + bm 9 + sm 2 j sum — s 03 = sm 7 i + bm 15 + sm 3 j sum — s 04 = sm 1 i + bm 4 + sm 4 j sum — s 05 = sm 2 i + bm 6 + sm 5 j sum — s 06 = sm 5 i + bm 12 + sm 6 j sum — s 07 = sm 6 i + bm 14 + sm 7 j sum — s 10 = sm 1 i + bm 3 + sm 0 j sum — s 11 = sm 2 i + bm 5 + sm 1 j sum — s 12 = sm 5 i + bm 11 + sm 2 j sum — s 13 = sm 6 i + bm 13 + sm 3 j sum — s 14 = sm 0 i + bm 2 + sm 4 j sum — s 15 = sm 3 i + bm 8 + sm 5 j sum — s 16 = sm 4 i + bm 10 + sm 6 j as shown in fig6 , the control logic module controls the overall operations of the log - map decoder . the control logic state machine 171 , referred as clsm , is shown in fig1 . the clsm module 171 ( fig1 ) operates effectively as follows . initially , the clsm module 171 operates in idle state 172 . when the decoder is enabled , the clsm module 171 transitions to calc - bm state 173 , where the branch metric ( bm ) module starts operations and monitors for completion . when branch metric calculations are completed , referred to as bm - done , the clsm transitions to calc - fwd - sm state 174 , where the state metric module ( sm ) begins forward recursion operations . when the forward sm state metric calculations are completed , referred to as fwd - sm - done , the clsm transitions to calc - bwd - sm state 175 , where the state metric module ( sm ) begins backward recursion operations . when backward sm state metric calculations are completed , referred to as bwd - sm - done , the clsm transitions to calc - log - map state 176 , where the log - map computation module begins calculating the maximum a posteriori ( map ) probability to produce soft decode output . when log - map calculations are completed , referred to as log - map - done , the clsm module 171 transitions back to idle state 172 . the branch - metric memory 74 and the state - metric memory 75 are shown in fig6 as the data storage components for bm module 71 and sm module 72 . the branch metric memory module is a dual - port ram that contains m - bits of n memory locations as shown in fig1 . the state metric memory module is a dual - port ram that contains k - bits of n memory locations as shown in fig1 . data can be written into one port while reading at the other port . as shown in fig3 , the interleaver memory a 43 stores data for the first decoder a 42 and interleaver memory b 45 stores data for the second decoder b 44 . in iterative pipelined decoding , the decoder a 42 reads data from interleaver memory b 45 and writes results data into interleaver memory b 43 , the decoder b 44 reads data from interleaver memory a 43 and write results into interleaver memory b 45 . as shown in fig2 , the de - interleaver memory 41 includes a de - interleaver module 201 and a dual - port ram 202 , which contains m - bits of n memory locations . the interleaver is a turbo code internal interleaver as defined by 3gpp standard etsi ts 125 222 v3 . 2 . 1 ( 2000 - 05 ), or other source . the interleaver permutes the address input port a for all write operations into dual - port ram module . reading data from output port b are done with normal address input . the interleaver memory module uses an interleaver to generate the write - address sequences of the memory core in write - mode . in read - mode , the memory core read - address is normal sequences . as shown in fig2 , the input buffer memory 43 45 comprises of a dual - port ram 211 , which contains m - bits of n memory locations . as shown in fig3 , the turbo decoder control logics module 47 , referred to as tdclsm , controls the overall operations of the turbo codes decoder . log - map a 42 starts the operations of data in memory b 45 . at the same time , log - map b starts the operations in memory a 43 . when log - map a 42 and log - map b 44 finish with block n of data , the tdclsm 47 starts the iterative decoding for l number of times . when the iterative decoding sequences are completed , the tdclsm 47 transitions to hard - dec to generate the hard - decode outputs . then the tdclsm 47 transitions to start decoding another block of data . turbo codes decoder performs iterative decoding and diversity processing by feeding back the output z 1 , z 3 of the second log - map decoder b into the corresponding first log - map decoder a before making decision for hard - decoding output . as shown in fig2 , the counter 233 counts the preset number l times . as shown in fig . [[ 4 ]] 3 , the diversified logic module 48 computes the feedback intrinsic values z 5 into the decoders 40 a and 40 b inputs through adder 231 . in accordance with the method of the invention , the diversified logics module 48 performs the following calculations to produce the intrinsic value z 5 . computes the “ running - average filter ” over windows n of all error values to produce current average error value y ( i ) as shown in equation below : as shown in fig . [[ 4 ]] 3 , the diversified logic module 48 also computes the sum z 1 + z 3 for output to the hard - decoder block .