the fig4 diagram is in three parts . a first part a 1 relates to the input signals , a second part a 2 relates to the sigma - delta analog - to - digital converter itself , and a third part a 3 relates to a control system . the first part a 1 has a zero value input 15 used during a calibration phase and an input 16 receiving the analog signal to be digitized by the sigma - delta analog - to - digital converter . a switch 17 connects either to the input 15 or to the input 16 . in the second part a 2 , a signal from the input 15 or 16 reaches the positive input 18 a of an adder 19 . a noise - shaping filter 20 recovers the output signal of the adder 19 . the signal 21 leaving the noise - shaping filter 20 is fed to the input of a quantizer 22 with three quantizing levels : − 1 , 0 and 1 . the quantizer 22 generates a digital signal 23 which , during a normal operation phase , is fed to the input of a corrector module 27 via a switch 26 . the output signal of the corrector module 27 is then passed through a digital filter 28 in order to undersample it . undersampling reverts to a frequency in the vicinity of the nyquist frequency . the digital signal 23 also passes through a feedback loop 25 including a digital - to - analog converter 24 whose output signal is fed to the negative input 18 b of the adder 19 . the third part a 3 is a control device including an accumulator 29 , a counter 30 and a second counter 31 , all three of which are connected to a random access memory module 32 connected to a digital processor module 33 . the digital processor module 33 performs calculations and generates data signals 35 that are sent to the corrector module 27 of the sigma - delta analog - to - digital converter and control signals 34 that are sent to the quantizer 22 and the switches 17 and 26 . in normal operation , the digital - to - analog converter 24 receives three different digital values ( for example in the form of pairs of bits 01 , 00 and 10 coding the values − 1 , 0 and 1 ), and converts them into three analog values , which should ideally be − 1 , 0 and 1 . the three analog points do not usually correspond ideally to the values − 1 , 0 and 1 . for example , the analog point leaving the digital - to - analog converter whose ideal value is 0 can be corrected . the correction of the 0 point is independent of the zero value at the input 15 . it is possible to correct the + 1 and − 1 points with the zero value still present at the input 15 . during the first calibration phase the switch 17 is switched to the zero value input 15 and the switch 26 is switched to an input 36 common to the accumulator 29 , the counter 30 and the second counter 31 . the quantizer 22 operates in a three - level quantizing mode . the counter 31 then counts the number n 0 of 0 points ( points to be corrected ) contained in the digital signal 23 passing from the input 36 to the counter 31 . the count continues until the number n 0 reaches a predetermined value . to facilitate subsequent calculations the predetermined value is a power of two . it is equal to 2 18 , for example , i . e . to 262 144 . the accumulator 29 calculates the sum s 1 of the values of the output signal of the quantizer 22 . the sum s 1 is stored in the random access memory 32 , together with the number n 1 of points generated by the quantizer 22 and counted by the second counter 30 . the value 2 18 is chosen so that it is sufficiently large for the values stored in memory to be accurate . the second calibration phase consists of converting the sigma - delta analog - to - digital converter with three quantizing levels into a sigma - delta analog - to - digital converter with two quantizing levels . for this it suffices to convert the three - level quantizer 22 into a two - level quantizer . the two levels are the − 1 and + 1 points . the switch 17 is still switched to the input 15 and the switch 26 is still switched to the input 36 . during this phase the sigma - delta analog - to - digital converter is operated with zero at the input during n 1 samples . the accumulator 29 also calculates the sum s 2 of the n 1 output samples . a zero point correction value is finally calculated from the equation : the division is simple to effect in the digital processor module 33 because a power of two has been chosen for the value of n 0 . the value c is then saved in the memory 32 , which has three compartments in which it saves the number n 1 , the sum s 1 and the value c . once these two calibration phases have been completed , the phase of normal operation of the sigma - delta analog - to - digital converter with three quantizing levels begins . the switch 17 is switched to the input 16 , the switch 26 is switched to the corrector module 27 , and the quantizer 22 operates with three quantizing levels − 1 , 0 and + 1 . the analog signal to be digitized is fed to the input 16 and leaves the quantizer 22 in the form of a digital signal 23 which is modified by the corrector module 27 and then digitally filtered by the module 28 . the corrector module 27 executes an algorithm that can be summarized as in the table below : thus if the digital value 0 is present at the output of the quantizer 22 , it is replaced by its correction value c at the output of the corrector module 27 . fig5 shows the three - level quantizer 22 made up of two comparators 37 and 38 and a digital processor module 39 . the comparator 37 has two inputs , a first of which receives the signal 21 from the noise - shaping filter 20 and the second of which is maintained at a fixed voltage v equal to a positive quantizing threshold voltage . the comparator 38 also has two inputs , the first of which also receives the signal 21 , and the second input of the comparator 32 is maintained at a voltage equal to − v . the output of the comparator 37 and that of the comparator 38 enter the digital processor module 39 generating the digital output signal 23 . if the value of the input signal 21 is greater than v , the digital signal 23 takes the value + 1 . if the value of the input signal 21 is less than − v , the signal 23 takes the value − 1 . if the value of the input signal 21 is between − v and v , the signal 23 is equivalent to 0 . the digital processor module 39 is governed by the following algorithm , in which s 37 is the output of the comparator 37 , and s 38 is the output of the comparator 38 : to convert the three - level quantizer 22 into a two - level quantizer the values v and − v at the second inputs of the comparators 37 and 38 are replaced by a null value and the algorithm of the digital processor module 39 is modified so that , when the value of the input signal 21 is positive , the signal 23 is equivalent to + 1 and , when the value of the input signal 21 is negative , the signal 23 is equivalent to − 1 . to this end , the algorithm of the digital processor module 39 is as follows : in fact , only the comparator 37 is used , the comparator 38 being rendered “ invisible ”. the non - linearity of the sigma - delta analog - to - digital converter described above can be compensated by carrying out a calibration phase without modifying the structure of the sigma - delta analog - to - digital converter . fig6 a and 6b show the conversion of the five - level quantizer into a three - level quantizer . the e axis represents the input signal 7 and the s axis represents the output signal 9 . fig6 a shows the transfer function of a five - level quantizer (− 1 ; − 0 . 5 ; 0 ; 0 . 5 ; 1 ). for example , any input signal having a value between two positive values v 1 and v 2 delimiting a range of values on the e axis is converted into a digital signal of value equal to 0 . 5 on the s axis . to correct the zero level by converting the quantizer to three levels , the intermediate levels (− 0 . 5 and 0 . 5 ) are eliminated , as shown in fig5 b . the remaining three levels are therefore (− 1 ; 0 ; 1 ). for example , in a simulation for a signal to be converted of maximum amplitude and no correction in accordance with the invention , a sigma - delta analog - to - digital converter with three quantizing levels sampled at a frequency of 2 048 khz had a signal / noise ratio of 46 db . the results obtained after applying the first calibration phase with n 0 = 262 144 were as follows : n 1 = 372 522 and s 1 =− 6 408 . executing the second calibration phase yielded a sum s 2 =− 3 116 and a 0 point correction value c such that : a signal / noise ratio of 105 db was then obtained in normal operation for a signal to be converted of maximum amplitude and with correction in accordance with the invention . the method described above performs a calibration phase using a three - level quantizer and then a two - level quantizer but retains the general structure of the sigma - delta analog - to - digital converter . the calibration phase is effected simply by controlling the various switches .