reference will now be made in detail to the present preferred embodiments of the invention , examples of which are illustrated in the accompanying drawings . wherever possible , the same reference numbers are used in the drawings and the description to refer to the same or like parts . fig1 is a cross - sectional view showing the structure of a flash eeprom cell according to one preferred embodiment of this invention . as shown in fig1 the characteristic of this flash eeprom structure 200 of the invention is a triple well structure 100 that forms an isolated well during memory erase operation . the triple well structure 100 includes a p - well 30 , an n - well 20 and a p - type substrate ( p - sub ) 10 . the p - well 30 and the n - well 20 are located inside the p - sub 10 and the n - well 20 isolates the p - well 30 from the p - sub 10 . the memory structure 200 includes the triple well structure 100 , a pair of source / drain regions 40 and 50 , a floating gate 60 and a control gate 70 . the pair of source / drain regions 40 and 50 is located inside the p - well 30 of the triple well structure 100 . the floating gate 60 is located above the triple well structure 100 and lies between the source / drain regions 40 and 50 . the control gate 70 is located above the floating gate 60 . because a triple well structure is employed in this invention , a higher positive channel voltage together with a matching negative gate voltage can be used to achieve a memory erase operation . there is no need for the provision of an additional high voltage source from outside as required by most conventional flash memory designs . furthermore , to obtain better properties for the triple well structure 100 , the p - well 30 can be a shallow p - base well and the n - well 20 can be a deep n - well . the triple well structure 100 can be formed using similar processes as in the fabrication of a conventional cmos . in fact , there are two methods for forming the triple well structure . the first method is to form a shallow p - well in the original n - well , and the second method is to form a deeper n - well outside the p - well . for example , a deep n - well is first formed in a p - type substrate , and then a p - well is formed inside the deep n - well ; or , an n - well is first formed in the p - type substrate , and then a shallow p - base well is formed inside the deep n - well . table 1 below shows an example of bias voltages applied to various constituent parts of the memory cell during programming , erasing and reading operations according to this invention . table 1______________________________________control gate 70 drain 40 source 50 p -/ n - well 30 / 20______________________________________program 9v 5v 0v 0verase - 9v floating 9vread 3 . 3v 0v______________________________________ fig2 is a cross - sectional view showing a flash eeprom cell in a programming operation according to one preferred embodiment of this invention . in a programming operation , the control gate 70 is set to about 9v , the drain terminal 40 is set to about 5v and the source terminal 50 is set to 0v . furthermore , the p - well / n - well 30 / 20 are both set to 0v . hence , hot carriers are able to inject into the floating gate following the direction as shown by an arrow 80 . fig3 is a cross - sectional view showing a flash eeprom cell in a channel erase operation according to one preferred embodiment of this invention . in a channel erase operation , the control gate 70 is set to about - 9v , the drain terminal 40 is set to a floating state and the source terminal 50 is also set to a floating state . then , the p - well / n - well 30 / 20 are both set to 9v . hence , charges will flow from floating gate 60 in the direction as indicated by an arrow 90 according to the fowler - nordheim ( fn ) tunneling effect . since a high voltage is not applied to the source terminal 50 as in most conventionally designed flash memories , the source terminal 50 can be a single diffused junction . the main characteristic in the design of this flash eeprom 200 is the triple well structure 100 . during memory erase , the triple well structure 100 forms an independently isolated well . hence , a higher positive channel voltage together with a matching negative gate voltage can be used for a uniform erase operation . the purpose of having a triple well structure 100 is to allow the application of a high voltage to individual p - well 30 rather than having to apply a high voltage to every p - well . this is because the n - well 20 isolates the p - well 30 from the p - sub 10 . in other words , the embodiment of this invention provides a flash eeprom structure capable of hot carrier injection programming and negative gate voltage channel erasing operations . the read operation of this invention is similar to a conventional flash eeprom , so detailed description is omitted here . furthermore , the above description of operation refers to an n - channel flash memory . however , the principles behind the working of a p - channel flash memory are the same . the structural changes that are necessary for a p - channel flash memory is to form a triple well structure having an n - well 30 , a p - well 20 and an n - sub 10 instead . as a summary , the advantages of using the flash eeprom of this invention include : ( 1 ) compared with a conventional negative gate terminal / source terminal memory erase method , the channel erase operation provided by the memory structure of this invention is more uniform , and so the reliability of the memory is increased . ( 2 ) the negative voltage applied to the gate terminal and the positive voltage applied to the channel can be tuned to any value as long as their sum in voltage after taking their absolute values remain low . hence , there is no need for an additional high voltage source from outside . ( 3 ) since the memory of this invention does not employ a source terminal erase mechanism , hot holes due to a band - to - band tunneling current disappear . without hot holes , gate disturbance due to trapped hot holes inside an oxide layer can be avoided . ( 4 ) unlike a conventional eeprom that uses a source terminal erase mechanism for memory erase , a high voltage at the source terminal is unnecessary for this invention . hence , a single diffused junction rather than a double diffused graded junction can be used . a single diffused junction is always preferred because it can produce memory with smaller cell dimensions . ( 5 ) at present , two modes of operation for flash memory exist . one mode uses hot carrier injection for programming and source terminal erasing mechanism for memory erase . in a second mode , fn tunneling is used for carrying out both programming and erasing operations . the memory architecture of this invention provide a third mode of operation that utilizes hot carrier injection for carrying out programming and a negative gate voltage for carrying out channel erase operation . it will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention . in view of the foregoing , it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents .