referring to fig1 a memory cell transistor employed in a nand cell eeprom in accordance with one preferred embodiment of the present invention is generally designated by reference mark &# 34 ; m .&# 34 ; two different cross - sectional structures of the transistor m are illustrated respectively in fig2 and 3 , taken along the lines which perpendicularly cross each other . principally , this transistor may be a floating - gate tunneling semiconductor field effect transistor . as shown in fig2 the memory cell transistor m is formed on a silicon substrate . this substrate may be a silicon layer of p - type conductivity . a thick insulative or dielectric layer 12 , which is patterned to define therein an element - forming region of a predetermined area , is formed on the top surface of substrate 10 . this insulating layer 12 serves as an element - isolation layer . a thin insulative or dielectric film 14 is deposited on the selected top surface of substrate 10 which is surrounded by the element - isolation layer 12 . insulative film 14 is 11 nanometers ( nm ) in thickness , for example , and acts as a first gate insulation film of the memory cell transistor m . a polycrystalline silicon layer 16 is formed on the first gate insulation film 14 . this layer 16 overlies insulative layer 12 at its two opposite end portions thereof as shown in fig2 . a second gate insulation film 18 is laminated on layer 16 to cover the same . another thin polycrystalline silicon layer 20 is stacked on film 18 , covering layer 18 . layer 16 serves as a charge - storage layer for transistor m , i . e ., a floating gate ; the overlying layer 20 functions as a control gate electrode of transistor m . a heavily - doped p - type semiconductor layer ( s ) is formed beneath element - isolation layer 12 as a channel stopper ; it is not visible in fig2 . as shown in fig3 the lamination structure of layers 14 , 16 , 18 , 20 has been subjected to a patterning process to have a constant width along the vertical direction in fig1 i . e ., in the direction along the line iii -- iii of fig1 . p - type substrate 10 is doped with an n - type impurity to a concentration of 1 × 10 15 atoms per cubic centimeter by a well - known ion injecting technique , providing two spaced - apart n - type semiconductor layers 22 , 24 . these layers serve as the source and the drain of memory cell transistor m respectively . drain and source layers 22 , 24 are self - aligned with gate electrodes 16 , 20 . the distance between layers 22 , 24 defines the effective channel length of transistor m . in the present embodiment , the channel length is set short up to on the order of submicrons , for example , about 0 . 2 micrometers or less , to achieve higher integration . as apparent from fig1 the control gate electrode 20 extends linearly to be coupled integrally with control gate electrodes of adjacent ones of memory cell transistors ( not shown ) on substrate 10 . floating gate 16 of transistor m is cut out short beneath control gate 20 , and is electrically isolated from all the components of transistor m , i . e ., rendered electrically &# 34 ; floating .&# 34 ; in other words , floating gate 16 is capacitively coupled with substrate 10 and control gate electrode 20 at different capacitances . very importantly , the memory cell transistor m is specifically arranged to satisfy the following two requirements : ( 1 ) the withstanding voltage of drain layer 22 is potentially greater than a voltage to be applied to this drain layer 22 in a read mode of an eeprom which employs transistor m as one of its memory cells , when an &# 34 ; l &# 34 ;- level voltage ( for example , 0 volts ) is applied to substrate 10 and control gate electrode 20 ; ( 2 ) the withstanding voltage of drain 22 is potentially less than a voltage to be applied to the drain layer when electrons are discharged from floating gate 16 to drain layer 22 . such &# 34 ; drain withstanding voltage &# 34 ; arrangement may be easily attained by those skilled in the art without using any special fabrication technique . typically , the &# 34 ; withstanding voltage &# 34 ; arrangement may be accomplished by performing an impurity - doping process into substrate 10 under the dose condition as described previously . with the specific &# 34 ; drain withstanding voltage &# 34 ; feature , when an &# 34 ; h &# 34 ;- level voltage ( for example 20 volts ) is applied to drain layer 22 during an erase period , a substrate surface portion between drain 22 and source 24 is then depleted to form a depletion layer therein . in other words , the depletion layer expands through the channel region of memory cell transistor m . a &# 34 ; punch - through &# 34 ; phenomenon thus occurs , causing the source potential to rise positively . the rise of the source potential causes the internal electric field being created near drain 22 of transistor m along the lateral direction thereof to decrease in intensity . it is thus possible to suppress or inhibit the generation of hot holes , which is a problem in the prior art . this can improve the operational reliability of the eeprom significantly . fig4 a illustrates a model of the potential distribution inside the substrate 10 of memory cell transistor m under the punch - through phenomenon . this potential distribution is based on the measurements by the present inventors . each of the thin lines is added to represent a curve linking equal potential points . a voltage vd denotes a positive voltage to be applied to drain 22 . the source potential is represented by &# 34 ; open ,&# 34 ; indicating that the source is potentially isolated from other parts . fig4 b shows the potential distribution in the substrate of a conventional memory cell transistor which has a long channel length of 2 . 0 micrometers , and does not have the above &# 34 ; drain withstanding voltage &# 34 ; feature of the present invention , in the same conditions as in fig4 a . as apparent from the comparison between the potential distributions in these diagrams , the potential distribution inside the substrate of transistor m was demonstrated to be well symmetrical with respect to the source and the drain . the inventors also measured the endurance characteristic of the memory cell transistor structure according to the present invention and that of the conventional memory cell transistor . the results are shown in fig5 . the horizontal scale of the graph in fig5 represents the repeating number of write / erase cycles , while the vertical scale represents the potential threshold value ( threshold voltage ), vth , of the memory cell transistor . if the fluctuating range of the threshold voltage vth is 0 . 5 volts , conventionally , the characteristic of the threshold voltage tends to rapidly drop after the write / erase operation is repeated about 105 times , as apparent from a curve 30 . in other words , the threshold voltage tends to change beyond the allowable fluctuating range of 0 . 5 volts , and never return to the normal condition . the assured repeating number of write / erase cycles remains approximately 105 . in contrast , the eeprom using the memory cell transistor m of the present invention could operate almost normally even when the write / erase operation was repeated up to about 10 7 times . in other words , the assured repeating number of the operations was increased by a factor of two digits , compared with the conventional number . these results demonstrate the fact that the endurance characteristic of memory cell transistor m can be significantly enhanced . turning now to fig6 there is shown an array of rows and columns of memory cell transistors of a nand cell type eeprom 40 employing the above - described transistor structure for each cell . a memory cell block 42 includes a plurality of memory cell units u . each cell unit ui ( i = 1 , 2 , . . . ) includes a series circuit of a preselected number ( four , in this embodiment ) of memory cell transistors m , each having the mos transistor structure as previously described referring to fig1 to 3 . for example , the cell unit u1 has memory cell transistors m11 , m12 , m13 and m14 . the number of the memory cell transistors in each unit is not limited to four ; it may be increased to eight , sixteen , and so forth in accordance with the memory capacity as required when reduced to practice . in the series - circuit of the memory cell transistors , each active layer 22 ( or 24 ) is commonly shared by two neighboring cell transistors . for example , the layer ( 24 in fig3 ) serving as the source of the cell transistor m11 also serves as the drain of the cell transistor m12 neighboring thereto . as shown in fig6 individual cell unit ui is provided with two insulated gate mos transistors s1 , s2 at two opposite ends thereof respectively . the first transistor s1 is arranged between cell unit u1 and a corresponding data transfer line ( bit line ) bli associated therewith . the second transistors s2 of cell units u are commonly connected to the source potential ( e . g . ground potential ). control gate lines cg1 , cg2 , cg3 , cg4 extend to insulatively cross the bit lines bl perpendicularly . each control gate line cgj ( j = 1 , 2 , 3 , or 4 ) is electrically connected to the control gate electrodes of a corresponding row of the memory cells . for instance , control gate line cg2 is associated with memory cell transistors m12 , m22 , m23 , m24 . control gate lines cg may serve as program lines , i . e ., word lines in eeprom 40 . the first transistors s1 in the units u are connected at their gate electrodes to a wiring line sg1 . the gate electrodes of the second transistors s2 are connected to another wiring line sg2 . these lines sg1 , sg2 run in parallel with the word lines cg . transistors s1 , s2 in every cell unit ui are responsive to the potential change on lines sg1 , sg2 to perform a switching operation . in this respect , transistors s1 , s2 serve as the &# 34 ; first and second select transistors .&# 34 ; lines sg1 , sg2 are called &# 34 ; select gate lines &# 34 ; hereinafter . a row decoder circuit 44 is connected to word lines cg and select gate lines sg . the circuit 44 may be arranged similarly as in ordinary nand cell eeproms . a sense amplifier circuit 46 is responsive to the column decoder output of a column decoder circuit 48 . any desired cell address among memory cells m can be specified by a combination of the row decoder 44 and column decoder 48 . sense amplifier 46 amplifies a storage data at a selected memory cell being specified . to erase data in the memory cell block 42 being selected , voltages as shown in fig7 are applied to the bit lines bl , word lines cg and select gate lines sg . during the erase operation in the selected block , all the lines sg , cg , bl associated with the remaining non - selected memory cell blocks ( not shown in fig6 ) are kept constantly at &# 34 ; l &# 34 ; level voltage . as a result , all the memory cell transistors m in the selected block 42 can be erased at a time , while keeping the memory storage states in the remaining cell blocks ( not shown in fig6 ) unchanged . this is so - called &# 34 ; block erase operation .&# 34 ; more specifically , in the erase mode the first select gate line sg1 is kept at an &# 34 ; h &# 34 ; level potential ( e . g ., 20 volts ), while the second select gate line sg2 is kept at an &# 34 ; l &# 34 ; level potential ( e . g ., 0 volts ). in response to the voltage application , while select transistor s2 turns off , select transistor s1 turns on , causing nand cell units u to be electrically coupled to bit lines bl . under this condition , all the word lines cg1 through cg4 are set at the &# 34 ; l &# 34 ; level potential in response to the output of row decoder 44 . either &# 34 ; h &# 34 ; or &# 34 ; l &# 34 ; level potential is applied to bit lines bl in response to the output of column decoder 48 ; &# 34 ; h &# 34 ; level potential is applied thereto when erase is performed . as a result , punch - through occurs simultaneously in every memory cell transistor m in cell block 42 , causing all the floating gate electrodes to discharge . this means simultaneous erasing of the memory cell transistors m . during the erase operation , when the &# 34 ; l &# 34 ; level potential is applied to first select gate lines associated with the other non - selected cell blocks ( not shown in fig6 ), the above - described erasing would not take place in these blocks for the following reason . in the non - selected blocks , all the first select transistors s1 are turned off , so that the potentials appearing on the bit lines bl connected thereto are prevented from being transferred to the nand cell units in the non - selected blocks . the advantage of attaining the block - erase operation without employing any additional circuits is one of the unexpected results of the above - described &# 34 ; drain withstanding &# 34 ; feature of the present invention . in addition , it can perform a block erase operation for selectively erasing only the selected block ( s ) with the minimum power consumption . the reason for this is that the flow of through - current generated during an erase period can be minimized by forcing first select transistors s1 in non - selected cell blocks to turn off . this would significantly widen the applicability of large - capacity nand cell eeproms . a nor cell type eeprom 50 of fig8 in accordance with another embodiment of the present invention includes a memory cell array section , which employs the transistor structure previously described with reference to fig1 to 3 for each of its memory cell transistors . the memory cell array portion includes a plurality of nor cell units r1 , r2 , . . . , r ( n - 1 ), rn . every two neighboring nor cells in each nor cell unit ri are connected to a corresponding bit line bli at a circuit node where at the drain of one memory cell transistor and the source of the other cell transistor are connected together . the other source and drain of those cell transistors are coupled together to an extra wiring line sl as shown in fig8 . source line sl is provided with a select transistor sg . this transistor may be a known insulated gate mos transistor . each of the memory cell transistors m in an individual nor cell unit ri is similar to that shown in fig1 to 3 . in a case wherein each unit ri includes eight memory cell transistors m , four source lines sl1 , . . . , slk are required . each row of memory cell transistors m are connected to a word line wl at the control gates thereof . a block erase operation in the nor cell eeprom 50 is as follows . as shown in fig9 &# 34 ; l &# 34 ; level potential ( 0 volts ) is applied to the word lines wl1 , wl2 , . . . , wln , the gate electrodes of the source select transistors sg1 , . . . , sgk , and source lines sl1 . . . , slk , all being associated with a selected cell block . also , &# 34 ; h &# 34 ; level potential ( e . g ., 18 volts ) is applied to bit lines bl1 , bl2 , . . . , bl ( n - 1 ), bln . as a result , punch - through occurs in the memory cell transistors in the selected cell block in substantially the same manner as in the previously explained embodiment . these memory cell transistors are thus erased simultaneously . as source select transistors sg are forcibly turned off , the flow of through - current can be inhibited in every nor cell unit ri . it can thus carry out a block erase operation with minimal power consumption and the maximized operational reliability . this should contribute to further enhancement of the performance of a so - called &# 34 ; nor cell type flash eeprom .&# 34 ; note that the above source select transistors sg may be replaced with a single transistor which is connected in common with source lines sl . it is also an important feature of eeprom 50 that while a block erase operation is being performed in a selected memory cell block 42 , first and second select gate lines sg1 , sg2 , control gate ( word ) lines cg1 to cg4 , and bit lines bl associated with the remaining , non - selected memory cell blocks on substrate 10 are forced to remain at the &# 34 ; l &# 34 ; level voltage ( 0 volts ). such &# 34 ; l &# 34 ; voltage application feature in the non - selected blocks can introduce a significant advantage into the nand cell type eeprom ; it is low power consumption . this may be attained due to the fact that it is no longer required to apply the &# 34 ; h &# 34 ; level voltage to any lines of the non - selected blocks in order to prevent the occurrence of erroneous erase operation therein , unlike as in the presently - available nand cell type eeproms . another nand cell eeprom 60 is shown in fig1 . this embodiment is similar to that of fig6 with the second select transistors s2 being replaced with insulated gate mos transistors t2 , each of which is arranged between the source of the last - stage memory cell transistor m4 and a corresponding bit line bli associated therewith . second select transistors t2 have gate electrodes respectively connected to terminal voltage vs . as shown in fig1 a row decoder circuit 62 is connected to a first select gate line sd1 and control gate lines cg1 to cg4 ( word lines wl1 to wl4 ). each bit line bli is associated with an intermediate voltage generator circuit 64 and a control circuit 66 . intermediate voltage generator 64 is connected to one end of a corresponding bit line bl , while circuit 66 is to the other end thereof voltage generator 64 includes a pair of series - connected mos transistors q1 , q2 which have a common connection node 68 connected to bit line bli . transistor q1 has a gate electrode connected to its drain , at which a boosted voltage vpp such as a 10 - volt dc voltage is supplied . transistor q2 has a gate electrode connected to terminal e . each control circuit 66 includes a sense amplifier circuit section 70 , a data discriminating circuit section 72 , and a write control circuit section 74 . these sections may be constituted by using mos transistors q3 to q7 , a capacitor c , and a nor gate g , which are interconnected as shown in fig1 . another intermediate voltage generator circuit 76 is arranged with respect to each bit line bli . circuit 76 includes a constant voltage source 78 and a pair of parallel - connected mos transistors q8 , q9 . these transistors have gate electrodes , which are connected to first and second mode control signals mod1 , mod2 , respectively . the sources of transistors qs , q9 are connected together to serve as an output of circuit 76 . the circuit arrangement employs three kinds of intermediate voltages : a first intermediate voltage vm1 that is applied to the drain of transistor q3 in each control circuit 66 , a second voltage vm2 that is supplied to row decoder 62 , and a third voltage vm3 that is the output of circuit 76 . fig1 is the associated pulsing sequence of the memory cell array shown in fig1 . to erase all memory cells m in a selected block at one time , gate line sd is first selected , gate terminals vs of second select transistors t2 , and bit lines bl are then potentially raised to the &# 34 ; h &# 34 ; level (= 18 volts ), while control gate lines cg ( word lines wl ) are kept at the &# 34 ; l &# 34 ; level potential such as 0 volts . at this time , substrate voltage is also at the &# 34 ; l &# 34 ; level potential . with such a voltage application , block erasing can be performed successfully while nand cell units u1 , u2 . . . are connected to bit lines bl by second transistors t2 being forced to turn on in response to voltage vs . the present invention is not limited to the above - described specific embodiments and may be practiced or embodied in still other ways without departing from the spirit or essential character thereof .