embodiments of the communication apparatus according to the present invention will now be described with reference to fig2 and 3 . fig2 is a diagram used to explain the first embodiment of the communication apparatus according to the present invention and shows an arrangement of a transmission portion of the time - division multiplex communication system . a power amplifier 11 used in the first embodiment is constructed like the semiconductor power amplifier integrated circuit according to the second embodiment shown in fig3 for example . the semiconductor power amplifier integrated circuit is constituted in the following manner . that is , as shown in fig3 junction type gallium arsenic field effect transistors ( gaas jfets ) ( hereinafter simply referred to as jfets ) 38 , 41 and 42 are connected in a multi - stage fashion to form an amplifier circuit . this amplifier circuit is connected to a positive power source to be operated thereby . coupling capacitors 37 and 40 are provided between the adjacent amplifier stages to couple the adjacent amplifier stages so that the respective amplifier stages are independently operated in terms of dc components . further , phase adjusting and impedance matching circuits which are respectively formed of capacitors and resistors 58 , 59 and 60 , 61 are provided between the adjacent amplifier stages so as to adjust a phase of a signal to thereby prevent the oscillation . with this arrangement , the amplifier circuit can operate stably even if amplitudes of the jfets of the respective amplifier stages are increased , so that the number of the amplifier stages can be decreased by increasing the amplitude for one stage of the amplifier . as a consequence , the semiconductor power amplifier integrated circuit can be miniaturized and a power consumed by the integrated circuit can be decreased . further , the semiconductor power amplifier integrated circuit is provided with an input impedance matching circuit formed of elements 31 to 34 at the rear stage of an input terminal 52 , and an output impedance matching circuit formed of elements 43 to 45 at the preceeding stage of an output terminal 55 so as to facilitate the connection with other circuits . a power source connection terminal 54 to the respective amplifier states is provided with bypass capacitors 49 to 51 between the former and the latter so as to eliminate an influence due to stray capacitances of leading wires , thereby facilitating the connection with the power source and mass production of the integrated circuit . the amplifier 38 of the primary stage employs a dual gate junction type gaas fet . a voltage applied to the second electrode of the gaas fet 38 is controlled through a resistor 35 by an external driving control terminal 53 so that the gain of the power amplifier according to the present invention is controlled . an amplifier 41 of the next stage is formed of a single gate junction gas fet 41 whose gate is controlled in gain from a first gate bias terminal 56 through a resistor 47 . the drain of the fet 41 is connected through a load resistor 36 to a power supply 54 . further , the gate of the jfet 42 which finally forms a controller is also controlled in gain by varying a bias from an external control terminal 57 through a resistor . a gate bias terminal for determining the operating points of the jfets at the respective amplifier stages is provided so that the operating points can be controlled from the outside of the amplifier stages . a plurality of or first and second gate bias terminals 56 and 57 are provided to be connected to the gates of fets 38 and 41 through resistors 46 and 47 as shown in fig3 so that the respective amplifier stages can be controlled in such a manner that the amplifier of the primary stage is operated as a class a amplifier with a good linearity and the amplifier of the rear stage is operated as a class ab amplifier which is less in power consumption . turning back to fig2 operation of the transmission portion will be described below . a high - frequency signal is supplied to the semiconductor power amplifier integrated circuit ( hereinafter referred to as a power amplifier ) 11 from a main controller 14 . the high - frequency signal is amplified by the power amplifier 11 and then supplied to a transmission antenna 16 . a part of the high - frequency signal delivered from the main controller 14 is supplied to a detector 12 , which in turn performs a dc detection of the high - frequency signal and outputs a dc voltage which is applied to a gate bias generator 13 . the gate bias generator 13 generates a gate bias voltage in accordance with the dc voltage . the gate bias voltage is applied to a first input terminal of an adder 15 . the adder 15 receives a control signal voltage from the main controller 14 at its second input terminal , thereby obtaining a sum of the gate bias voltage and the control signal voltage to output the sum voltage . an output terminal of the adder 15 is connected to a gate bias terminal 17 of the power amplifier 11 . operation of the thus constituted transmission portion of the communication apparatus according to the embodiment will be described . the high - frequency signal from the main controller 14 is input to the power amplifier 11 and the detector 12 . the power amplifier 11 amplifies the input high - frequency signal and sends the amplified high - frequency signal to the transmission antenna 16 connected at the rear stage thereof . the detector 12 performs the dc detection of the input high - frequency signal to generate the dc voltage . the dc voltage is input to the gate bias generator 13 , which in turn converts the dc voltage into a voltage and applies the converted voltage to the first input of the adder 15 . the voltage of the control signal applied to the second input of the adder 15 from the main controller 14 is at a high level during a time slot which is allotted to the communication apparatus itself , so that in this case the gate bias voltage appearing at the output terminal of the adder 15 has fallen in the operation range of the power amplifier 11 . at this time , when a power of the high - frequency signal from the main controller 14 is small , the dc voltage which is an output from the bias generator 13 becomes low . accordingly , the gate bias voltage applied to the power amplifier 11 becomes also low to thereby decrease a power source current flowing through the power amplifier 11 . in contrast , when a power of the high - frequency signal from the main controller 14 is large , the dc voltage output from the bias generator 13 becomes high . accordingly , the gate bias voltage applied to the power amplifier 11 becomes also high to thereby increase a power source current flowing through the power amplifier 11 . as a consequence , the degradation of efficiency of the power amplifier can be prevented because the power source current of the power amplifier 11 becomes small when a transmission output is small . during a time slot allotted to the communication apparatus other than itself , since the voltage of the control signal voltage from the main controller 14 is set to be lower than a pinch - off voltage of the gaas jfets used in the power amplifier 11 , the gate bias voltage applied to the gate bias terminal 17 of the power amplifier 11 from the adder 15 is low . therefore , the jfet of the power amplifier 11 is set in an off state . accordingly , the power source current flowing through the power amplifier 11 becomes zero . as described above , according to the communication apparatus of the present invention , since the power amplifier is operated during the transmission operation but not operated when no transmission is carried out , an amount of power consumption can be decreased . further , since the power amplifier according to the present invention can control an amount of the power source current flowing therethrough in accordance with an amount of the transmission power even in the signal transmission , the power amplifier can always be used at a high efficiency state . furthermore , in the time - division multiplex system , since the power amplifier can be turned on and off by changing a voltage applied to its gate bias terminal , the power amplifier can be switched at a high speed . therefore , the present invention is advantageous in that the power source current which is not effective to the power amplifier is not required to flow therethrough during the adjacent time slots . the aforesaid advantages will be remarkable when the semiconductor power amplifier integrated circuit according to the present invention is used in a portable telephone . having described the preferred embodiments of the invention with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments and that various changes and modifications thereof could be effected therein by one skilled in the art without departing from the spirit or scope of the novel concepts of the invention as defined in the appended claims .