the present invention is an n - stage synchronizer that reduces the latency associated with the synchronization process without sacrificing reliability . referring to fig3 the synchronizer of the present invention is shown generally at 300 . the synchronizer has two stages . it is understood that even though only two stages are shown in fig3 the n - stage synchronizer of the present invention may have many more stages . there are three inputs to n - stage synchronizer 300 . the first is s signal 302 , the second is abort signal 306 , and the third is clock b signal 312 . s signal 302 is an asynchronous signal that is to be synchronized . when asserted , abort signal 306 blocks synchronization of the asynchronous signal . clock b signal 312 is the clocking signal for the destination time domain . asynchronous s signal 302 is the second input to first stage and gate 304 . the first signal input to and gate 304 is abort signal 306 which is input to the negative / true input of and gate 304 . the output of first stage and gate 304 is the s1 signal on line 308 . the s1 signal will track the s signal as long as the abort signal is de - asserted . the s1 signal is input to the data input of first stage flip - flop 310 . first stage flip - flop 310 is clocked by clock b signal 312 . the output of first stage flip - flop 310 is the s2 signal on line 314 . the s2 signal is the second input to second stage and gate 316 . the first input to second stage and gate 316 is abort signal 306 which is input to the negative / true of and gate 316 . the output of second stage and gate 316 is the s3 signal on line 318 . the s3 signal will track the s2 signal as long as the abort signal is de - asserted . the s3 signal is input to the data input of second stage flip - flop 320 . the second stage flip - flop is clocked by clock b signal 312 . the output of the second stage flip - flop 320 is sync s signal 322 which is the synchronized version of s signal 302 . referring to fig4 the timing diagrams for the operation of the n - stage synchronizer of the present invention as shown in fig3 will be discussed . in fig4 the dotted lines represent the result if the abort signal is not asserted . clock a signal 400 is the clocking signal for asynchronous s signal 302 and abort signal 306 . as shown , s signal 302 has a period equal to clock a signal 400 . abort signal 306 is not asserted unless it is determined that signal 302 is not to be synchronized and must be blocked . signal s 302 and abort signal 306 are input to first stage and gate 304 . as long as the abort signal 306 is de - asserted , the output of first stage and gate 304 will track s1 signal 402 . during the period that s1 signal 402 is asserted and clock b signal 312 is at the beginning of a cycle , the asserted s1 signal at the data input of first stage flip - flop 310 is clocked to the output of that flip - flop . this signal is s2 signal 404 ( fig4 ) on line 314 . s2 signal 404 tracks the s1 signal 402 but lags it by up to one clock period of clock b signal 312 . s2 signal 404 is input to second stage and gate 316 . as long as abort signal 306 is de - asserted , the output of and gate 316 is s3 signal 406 ( fig4 ) on line 318 will track s2 signal 404 . the s3 signal is input to the data input of flip - flop 320 . this input signal is output from flip - flop 320 at the beginning of the next cycle of clock b signal 312 . this output is sync s signal 322 , thus providing the synchronized version of asynchronous s signal 302 to the destination system . as can be readily seen , if at any time it is determined during the synchronization process that asynchronous s signal 302 should not be provided to the destination system , abort signal 316 is asserted which blocks synchronization of asynchronous s signal 302 at an and gate at one of the n synchronizer stages . this happens at the beginning of the cycle of clock b signal 312 after abort signal 306 is asserted . the affects of asserting the abort signal is shown in fig4 at s1 signal 402 , s2 signal 404 , and s3 signal 406 . referring again to fig4 if the time for determining whether the asynchronous s input 302 is to input to a destination system is at time t2 , which is evidenced by the assert or de - assert of abort signal 306 , and the synchronization process is initiated at t1 , some of the latency associated with synchronization process is reduced . referring to fig5 if the present invention was incorporated in state machine 500 , which is similar to the state machine in fig2 and the portion of state machine 500 that is shown includes state a 502 , state b 504 , state c 506 , and state d 508 , synchronization could be started in state b 504 before the decision is made whether to proceed to state c or state d . if state c 506 is selected which requires synchronization , the latency associated with the synchronization operation is reduced without affecting reliability . however , if state c 504 is not selected and state d 508 is selected , the abort signal is asserted to block synchronization of the asynchronization signal . the terms and expressions which are employed herein are used as terms of expression and not of limitation . and , there is no intention , in the use of such terms and expressions , of excluding the equivalents of the features shown , and described , or portions thereof , it being recognized that various modifications are possible within the scope of the invention .