fig1 provides a functional block representation of a data storage device 100 constructed and operated in accordance with various embodiments of the present invention . top level control of the device 100 is carried out by a suitable controller 102 , which may be a programmable or hardware based microcontroller . the controller 102 communicates with a host device via a controller interface ( i / f ) circuit 104 . a memory space 106 comprises a number of memory arrays 108 ( denoted array 0 - n ). each array 108 comprises a block of semiconductor memory of selected storage capacity . fig2 shows an exemplary construction for a memory cell 110 of the memory space 106 of fig1 . the memory cell 110 has a complementary 2t2r configuration , with first and second resistive memory elements ( rmes ) 112 , 114 and first and second switching devices 116 , 118 . in some embodiments , the switching devices 116 and 118 are characterized as n - channel metal oxide semiconductor field effect transistors ( nmosfets ). the rmes 112 , 114 are each selectively programmable to different resistive states , such as a high resistance or a low resistance . the programmed states are complementary in that when the first rme 112 is programmed high , the second rme 114 is concurrently programmed low , and vice versa . as explained below , this cell configuration facilitates improved sensing margin and enhanced data transfer rate performance including high data rate page - mode read operations . an overall memory state of the cell 110 can be determined in relation to the programmed state of the first rme 112 ; for example , the memory cell 110 may be identified as storing a logical 0 when the first rme 112 is programmed to the low resistance and the second rme 114 is programmed to the high resistance . the memory cell 110 may be alternatively identified as storing a logical 1 when the first rme 112 is programmed to the high resistance and the second rme 114 is programmed to the low resistance . the memory cell 110 is connected between complementary bit lines 120 , 122 denoted bl and bl ′. a cell plate ( cp ) line 124 is provided between the cell transistors 116 , 118 . a word line ( wl ) 126 is connected to respective control gates of the transistors 116 , 118 . fig3 shows an elevational semiconductor representation of the memory cell 110 of fig2 in accordance with some embodiments . it will be appreciated that other cell configurations can be used as desired . regions of n + doped material 128 , 130 and 132 are formed in a semiconductor substrate 134 . isolated control gates 136 , 138 span adjacent pairs of the doped regions to form the first and second transistors 116 , 118 . a support structure 140 establishes the aforementioned cp line connection with the middle doped region 130 . support structures 142 and 144 respectively support and interconnect the first and second rmes 112 , 114 with the regions 128 and 132 . the first and second rmes 112 , 114 are characterized in fig3 as magnetic tunneling junctions ( mtjs ) of a spin - torque transfer random access memory ( stram ). each mtj includes a fixed reference layer ( rl ) 146 and a free layer ( fl ) 148 separated by an intervening tunneling barrier layer 150 . each reference layer 146 has a fixed magnetic orientation in a selected direction , such as via pinning to a separate permanent magnet layer ( not shown ). the free layers 148 each have a variable magnetic orientation that can be aligned in the same direction as the associated reference layer 146 ( parallel ) or in an opposing direction as the associated reference layer 146 ( anti - parallel ). the mtjs will have a low resistance in the parallel state and a high resistance in the anti - parallel state . these respective states can be obtained by passing write currents of suitable magnitude and pulse width through the mtjs in opposing ( bipolar ) directions . while the rmes 112 , 114 have been characterized as mtjs in fig3 , it will be appreciated that such is exemplary and not limiting . other rme configurations can readily be used including but not limited to mram , rram , and pmc structures . suitable rme configurations can include structures that are programmable to different states with the application of bipolar write currents . the first rme 112 can be provided with the same physical orientation within the cell as the second rme 114 , as shown in fig3 , or the rmes can be provided with opposing physical orientations . in some embodiments , the memory cells 110 are arranged into columns of memory cells in the array 108 . two such columns are identified at 152 and 154 in fig4 . each column is connected between adjacent , complementary bit lines bl 120 and bl ′ 122 , and includes a selected number of memory cells 0 - n . adjacent memory cells 110 in the respective columns 152 , 154 form rows 156 of selected length . the cells along each row 156 are coupled to a separate word line 126 , denoted wl 0 to wln in fig4 . each row 156 of cells will be referred to herein as a page of memory , although such is not limiting . fig5 shows control circuitry 160 used during write and read operations upon the memory cells 110 in accordance with various embodiments . a separate set of the control circuitry 160 in fig5 can be provided for each column , and will fit within the 2t2r width 161 of the associated column . for clarity , it will be contemplated that the circuitry 160 in fig5 is coupled to the memory cells 110 in column 152 in fig4 . the control circuitry 160 includes a sense amplifier 162 , an equalization circuit 164 and a write circuit 166 . the sense amplifier 162 is utilized during read operations and includes n - channel switching devices ( transistors ) 168 , 169 and p - channel switching devices ( transistors ) 170 , 171 cross - connected as shown . the equalization circuit 164 provides voltage equalization prior to a read operation and includes transistors 172 , 173 and 174 . the write driver 166 is utilized to write the complementary states to the memory cells 110 and includes complementary driver circuits 175 , 176 and four switching transistors 177 , 178 , 179 and 180 . a number of control signals are supplied to or from the circuitry 160 during respective write and read operations . these signals include sense amplifier differential outputs sap and san via lines 180 , 182 ; a bit line precharge v pre signal via path 184 ; an equalization enable eq signal via line 186 ; a current select csl signal via line 188 ; and a write enable we signal via line 190 . a corresponding timing diagram 200 for selected ones of these signals is set forth in fig6 . during a read operation , the bit lines bl , bl ′ 120 , 122 are precharged to the v pre voltage level . this can be carried out by supplying the v pre voltage to line 184 and asserting the eq signal , as shown in fig6 at 202 . the cell plate cp line 124 is set to an appropriate voltage v cp , such as 0 . 5v cc where v cc is a selected source voltage level ( such as about + 3 . 0v ). the precharge voltage v pre will be less than v cc and greater than v cp ( i . e ., v cc & gt ; v pre & gt ; 0 . 5v cc ). the associated word line wl 126 for the selected memory cell 110 to be read is asserted high ( 204 in fig6 ), which allows the charge stored on the bit lines bl , bl ′ to begin discharging through the respective rmes 112 , 114 of the selected cell to the cp line 124 . because the respective resistances of the rmes 112 , 114 will be different ( e . g ., one high and one low ), the speed of discharge from the respective bit lines bl , bl ′ will be different . upon deassertion of the word line wl 126 and activation of the sap and san via lines 180 and 182 , the sense amplifier 162 will initiate sensing of the differential voltages of the bit lines bl , bl ′ as exemplified at 206 and 208 in fig6 . these voltages will indicate the stored state of the memory cell 110 . for example , if the programmed resistance of the first rme 112 is higher than that of the second rme 114 , the bl ′ will discharge at a greater rate than the bl , so that the voltage on the bl will be greater than that of the bl ′ when the wl is deasserted . the bit line differential voltages will be respectively outputted and will indicate the stored state of the memory cell 110 ( see signals 206 , 208 in fig6 ). the foregoing read operations can be simultaneously carried out for each memory cell 110 along a selected row 156 ( fig4 ), allowing simultaneous page - mode reading and latching of the contents of each row ( page ) in the array . to write a selected memory state to the selected cell 110 , the wl 126 for the selected cell is asserted high . the csl and we signals on lines 188 , 190 are also asserted high , allowing bipolar write currents 192 and 194 to be respectively supplied by the driver circuits 175 , 176 through the selected cell 110 . a first direction of write current can be from the bl 120 to the bl ′ 122 , and an opposing , second direction of write current 194 can be from the bl ′ 122 to the bl 120 . in some embodiments the first write current from bl to bl ′ can operate to concurrently set the first rme 112 to a first programmed state ( such as the parallel , low resistance state ) and the second rme 114 to a second programmed state ( such as the anti - parallel , high resistance state ). the second write current from bl ′ to bl can correspondingly operate to concurrently set the first rme 112 to a second programmed state ( such as the anti - parallel , high resistance state ) and the second rme to the first programmed state ( such as the parallel , low resistance state ). as can be appreciated by one skilled in the art , the various embodiments illustrated herein provide a number of advantages over the prior art , including higher sensing margin , self - referenced read sensing , smaller total semiconductor ( chip ) area , and faster readout via page - mode reading . it will be appreciated that the various embodiments discussed herein have numerous potential applications and are not limited to a certain field of electronic media or type of data storage devices . it is to be understood that even though numerous characteristics and advantages of various embodiments of the present invention have been set forth in the foregoing description , together with details of the structure and function of various embodiments of the invention , this detailed description is illustrative only , and changes may be made in detail , especially in matters of structure and arrangements of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed .