fig1 shows a flowchart of a method according to the invention for automatically determining model signals of an fpga program , which are readable from the fpga with the aid of a readback following an fpga build , according to a first , preferred specific embodiment . with reference to fig2 , the interplay of hardware components for carrying out the method and running the fpga code is first described . fig2 shows a data processing device 1 for generating an fpga model 2 and an fpga code 3 from the fpga model , for which purpose a build 4 is carried out on data processing device 1 . an fpga hardware configuration is generated as fpga code 3 from fpga model 2 in fpga build 4 , using vhdl , a common hardware description language . the method according to fig1 , which is described in detail below , is carried out on data processing device 1 , it also being possible , in principle , to create fpga model 2 and build 4 on different data processing devices 1 . a cpu code 5 is usually generated in build 4 in addition to fpga code 3 . cpu code 5 and fpga code 3 are generated from a shared model , which comprises fpga model 2 . in the present exemplary embodiment , the model is generated with the aid of simulink . cpu code 5 and fpga code 3 may then be transferred to a compute node 6 . accordingly , compute node 6 comprises a cpu 7 for running cpu code 5 and an fpga 8 for running fpga code 3 . fpga 8 in this exemplary embodiment is an xilinx fpga . fig2 also shows a host system 9 for controlling compute node 6 . compute node 6 is connected to host system 9 via a network connection , which is not illustrated . in build 4 , additional trace files 10 are also generated , which enable host system 9 to access signal values of both cpu 7 and fpga 8 during the operation of compute node 6 , a read access to fpga 8 taking place by means of a readback and a write access taking place by means of partial reconfiguration . the a method for automatically determining model signals of an fpga program , which are readable from the fpga with the aid of a readback following an fpga build , is described below according to an exemplary embodiment . the method begins in step s 100 by generating an fpga model 2 on data processing device 1 . fpga model 2 describes a function to be implemented with the aid of fpga 8 . part of an exemplary fpga model 2 is also illustrated in fig3 . as is apparent therein , fpga model 2 is a hierarchical fpga model 2 , a superordinate subsystem 11 having a subordinate subsystem 12 being illustrated in fig3 . subsystems 11 , 12 form individual , self - contained blocks . as illustrated in fig3 , a read marking 14 is set in a signal path 13 in superordinate subsystem 11 , for the purpose of marking a model signal in fpga model 2 for readout with the aid of a readback . no changes are made to fpga model 2 . a first step of an automatic analysis for identifying signals which are readable from fpga 8 with the aid of a readback takes place in a step s 110 . for this purpose , fpga model 2 is automatically analyzed for identifying signals which are readable from fpga 8 with the aid of a readback . implementations of a register 15 for the storage or temporary storage of a signal , as illustrated in fig3 , are automatically detected in fpga 8 at an arbitrary point in signal path 13 . implementations of a time - delay element are also automatically detected at an arbitrary point in signal path 13 of a signal . signal paths 13 are automatically traced , so that implementations which are present at an arbitrary point in a signal path 13 and which facilitate a readout of the corresponding signal with the aid of a readback may be identified and collected . the automatic analysis carries out a recursive analysis of fpga model 2 , starting with superordinate subsystem 11 . identical signals in superordinate and subordinate subsystems 11 , 12 are ascertained in the recursive analysis . signals which are readably implemented with the aid of a readback in one of subsystems 11 , 12 are correspondingly available as being readable with the aid of a readback at an arbitrary point . one implementation of the recursive analysis is illustrated in fig4 . as is apparent therein , a forecast of whether the signal is readable with the aid of a readback is generated for each signal s in a module 16 , which in this case is referred to as traceabilityforecast . for this purpose , a source block of signal s is first read in with the aid of a function srcblock . a check in issubsystem subsequently checks whether an input block represents a subsystem within fpga model 2 . if this is the case , function traceabilityforecast is called again . otherwise , a check is made in step isatomic of whether the input block is not a subsystem and is thus unable to be further divided into atomic blocks . if this is the case , a check is made in step isregistered of whether a block is mapped to a register 15 following the synthesis , i . e ., the signal is stored or temporarily stored in a register 15 . in addition to the aforementioned cases of implementing a register 15 or a time - delay element , this is true even if the block has a delay zx of x & gt ; 0 , or if the block is part of a predefined list , i . e ., if it is a special block for which it has already been defined that it contains a readable implementation . in the next step , function equals is checked for whether two signals represent the same signal beyond a hierarchical level , i . e ., in superordinate subsystem 11 and in subordinate subsystem 12 . if this applies , the signal is marked as being readable from the fpga with the aid of a readback in step domarksignal , and it is added to a first list of signals which are readable from the fpga with the aid of a readback . build 4 is started in a step s 120 . build 4 originates in fpga model 2 , the fpga code being generated at the end of build 4 . fpga code 3 is an fpga hardware configuration , based on the fpga model in a hardware configuration language . a synthesis for generating a network list takes place in a step s 130 as the first step in build 4 . the high - level description of the system is transformed into the network list according to fpga model 2 in a synthesis tool . in a step s 140 , the network list is automatically analyzed for identifying signals which are readable from fpga 8 with the aid of a readback . a second list is created , which includes signals which are readable from fpga 8 with the aid of a readback following build 4 . the lists from steps s 110 and s 120 , i . e ., the first and the second list of signals which are readable from fpga 8 with the aid of a readback , are compared in a step s 150 . a consolidated list of signals which are readable from fpga 8 with the aid of a readback is created , the consolidated list containing signals which are contained in both the first and the second list as being readable from fpga 8 with the aid of a readback . a warning , which is displayed , for example , in fpga model 2 , is generated for signals which are contained in only one of the two lists , i . e ., which were not transferred to the consolidated list . the output of the signals which are readable from fpga 8 with the aid of a readback takes place in a step s 160 . the output of the signals which are readable from fpga 8 with the aid of a readback takes place in the form of a list in the development environment for generating the fpga code . in addition , model signals in fpga model 2 , which belong to the signals which are readable from fpga 8 with the aid of a readback , are automatically marked in fpga model 2 . a check is made in step s 170 of whether all signals marked with a read marking 14 are readable from fpga 8 with the aid of a readback , i . e ., whether they are part of the consolidated list . if a signal which is not readable with the aid of a readback is marked with a read marking 14 , a warning is output by generating and displaying a warning at read marking 14 of the model signal . in step s 180 , the model signal is automatically implemented in fpga 8 as a signal which is readable with the aid of a readback , if the check in step s 170 resulted in the fact that this signal marked with read marking 14 is not readable from fpga 8 with the aid of a readback . for this purpose , a register 15 for temporarily storing the signal value is automatically implemented in signal path 13 of this signal . if the automatic implementation of register 15 fails , a warning to this effect is output . the generation of fpga code 3 is concluded in step s 190 . accordingly , the steps “ map ,” “ place ” and “ route ” are carried out in build 4 and fpga code 3 is generated . in accordance with the method for determining signals of an fpga 8 which are readable from fpga 8 with the aid of a readback following the generation of fpga code 3 , these signals may also be written by means of a corresponding partial reconfiguration of fpga 8 , to the extent that this is supported by fpga 8 . in a second specific embodiment of the invention , the method described above is carried out for the purpose of determining signals which are modifiable by a partial reconfiguration after the generation of fpga code 3 . the only requirement is that fpga 8 provide corresponding manipulation options , such as the aforementioned partial reconfiguration . the method is implemented as a computer program product having computer - implemented instructions , which executes the steps of the above method after being loaded to and run in data processing device 1 . a digital storage medium provides electronically readable control signals , which interact with data processing device 1 in such a way that the above method is carried out on data processing device 1 . the invention being thus described , it will be obvious that the same may be varied in many ways . such variations are not to be regarded as a departure from the spirit and scope of the invention , and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims .