the invention substantially reduces unnecessary power drain from a battery power source in a keyless entry system transponder and associated circuits thereto . the invention comprises an asymmetrical time constant low pass filter connected between an electromagnetic energy or radio frequency receiver / detector and wake - up logic which controls the connection of battery power to the keyless entry system transponder and associated circuits thereto . another embodiment of the invention also determines the length of time a signal is present and if the signal time is within a certain time frame , a wake - up signal is then sent to wake - up the keyless entry system transponder . referring now to the drawings , the details of the preferred embodiment of the invention are schematically illustrated . elements in the drawings that are the same will be represented by the same numbers , and similar elements will be represented by the same numbers with a different lower case letter suffix . referring now to fig1 a schematic block diagram of a keyless entry system , according to an embodiment of the invention , is illustrated . a keyless entry system is generally indicated by the numeral 100 . the keyless entry system 100 comprises a reader / interrogator 102 , a receiver 106 , an asymmetrical time constant low pass filter 130 , wake - up and power control 118 , a transponder and associated circuits thereto 120 , and a battery 124 . the receiver 106 , asymmetrical time constant low pass filter 130 , wake - up and power control 118 , and transponder and associated circuits thereto 120 may be fabricated in one or more integrated circuit packages , and may be further integrated with the battery 124 into a small keyfob , embedded into the head of a key , made in the shape of an access card and the like . the reader / interrogator 102 transmits an interrogation signal 104 that is received by the receiver 106 . the receiver 106 is adapted to receive signals at a desired frequency and signal strength , and will receive any signal at that desired frequency plus or minus the bandwidth of tuned circuits ( not illustrated ) of the receiver 106 . when the desired frequency interrogation signal is received by the receiver 106 , the resulting detected signal at the output 132 of the receiver 106 is delayed for a desired time by the low pass filter 130 before the wake - up logic 116 detects the signal being present at its input 134 . once the desired frequency interrogation signal is present for a sufficient time period ( determined by the low pass filter 130 ) the wake - up power control 118 connects the battery 124 to the transponder and associated circuits thereto ( 120 ). information in the received interrogation signal 104 is connected from the output 132 , through a resistor 112 , to a data input of the transponder 120 . after detection and synchronization of the received interrogation signal 104 , the transponder 120 transmits an acknowledgement or verification signal 122 to the reader / interrogator 102 . upon receipt of a correct verification signal 122 , the reader / interrogator 102 causes a desired action to occur , such as for example , unlocking an automobile door , garage door , building entrance , opening a security gate , turning on or off lights , disarming a security system , and the like . an embodiment of the keyless entry system 100 includes an electronic key or keyfob that can remain in a pocket or purse , and when brought into , for example , a low frequency magnetic field surrounding a vehicle ( not illustrated ) generated by the reader / interrogator 102 , the electronics in the key or keyfob wakes up and starts communicating with the reader / interrogator 102 in the vehicle ( not illustrated ). once a proper verification is detected by the reader / interrogator , the vehicle door may unlock , or even automatically open . the present invention substantially reduces false and unnecessary wake - up of the electronics in the key or keyfob and thus increases the useful battery life thereof . the resistor 110 ( r1 ) may preferably be about one megohm ( 106 ohm ) and the capacitor 114 ( c1 ) may preferably be about two nanofarads ( 2 × 10 − 9 farads ). these values give a time constant , τ = rc , of about 2 × 10 − 3 seconds , or two milliseconds . this is a sufficient time delay to insure that the wake - up logic 116 is not false triggered by undesired noise signals . according to the invention , if the capacitor has not been charged for at least the time constant , τ , then the wake - up threshold has not been reached on the input 134 . when there is no signal on the output 132 the voltage thereon may be less than the voltage on the capacitor 114 and input 134 after some charging of the capacitor 114 . whenever the signal voltage on the output 132 is less than the voltage on the capacitor 114 , the diode 108 quickly discharges the voltage on the capacitor 114 ( the diode 108 effectively shorts out the resistor 110 ). therefore , if the received signal at the output 132 does not remain at the desired voltage level for at least the time constant , τ , then the wake - up threshold is never reached , and whatever voltage level happens to be present on the capacitor 114 is quickly discharged through the diode 108 . once the capacitor 114 has been discharged , the signal at the output 132 must be at a desired value for at least the time constant , τ , before the wake - up threshold at the input 134 may be reached . thus , noise , or periodic or aperiodic nuisance signals will not activate the wake - up and power control 118 . it is contemplated and within the scope of the present invention that in addition to , or in lieu of , the wake - up and power control 118 , clock logic gates may be used to inhibit clocking of power consuming logic circuits which , in complementary metal oxide semiconductor ( cmos ) transistor logic , effectively and substantially reduces the power drain of the circuits . referring now to fig2 a schematic block diagram of a keyless entry system , according to another embodiment of the invention , is illustrated . a keyless entry system 100 a comprises the circuits of the embodiment illustrated in fig1 except that the transponder and associated circuits thereto 120 are directly connected to the battery 124 . a clock inhibit 218 enables and disables clock signals in the transponder and associated circuits thereto 120 so that the cmos circuits thereof draw minimal power from the battery 124 . the wake - up logic 116 controls the clock inhibit 218 in a similar fashion to the power control 118 illustrated in fig1 and described herein above . when a signal is present on input 134 , the wake - up and clock inhibit 218 enables the clocks in the transponder and associated circuits thereto 120 , and the response signal 122 is sent to the interrogator 102 . referring to fig3 a schematic block diagram of an embodiment requiring an interrogation signal to be on for only a certain time period before system wake - up is initiated is illustrated . the keyless entry system 100 b comprises a reader / interrogator 102 , a receiver 106 , an asymmetrical time constant low pass filter 130 , signal duration verification logic 300 , wake - up and power control 118 , a transponder and associated circuits thereto 120 , and a battery 124 . the keyless entry system 100 b works substantially the same as the system 100 of fig1 except that the signal duration verification logic 300 actuates when a signal is received from the low pass filter 130 at its input 136 , and the signal duration verification logic 300 then determines if the this signal is of a certain time duration . if the signal at the input 136 stays on for an anticipated time and then turns off , the wake - up and power control 118 will be enabled at its input 134 by an output signal from the signal duration verification logic 300 . if the signal at the input 136 stays on longer than it should , then the signal duration verification logic 300 will not enable the wake - up and power control 118 . this embodiment of the invention prevents undesired noise signals that have sufficient energy to present a signal at the input 136 , but are of such duration that they are not the desired interrogation signals . referring not to fig4 a more detailed schematic block diagram of the signal duration verification logic of fig3 is illustrated . the signal duration verification logic 300 comprises a signal duration timer 402 , a signal status memory such as an rs flip - flop 404 , a no signal timer 406 and an inverter 408 . other logic circuits are contemplated and may be used equally and effectively under the spirit and scope of the embodiments of the present invention . the signal duration timer 402 is adapted to start a timing pulse of a duration that is slightly longer in time than the desired interrogation signal . the timer 402 starts its timing pulse when a signal is received at the input 136 . the rs flip - flop 404 may be a positive edge triggered flip - flop such that when the signal is removed ( logic 0 ) from the input 136 , the inverter 408 output will be at a logic 1 and will clock the logic level at the s input of the flip - flop 404 which then retains this logic level at its q output connected to the input 134 . if the signal at the input 136 stays at a logic 1 for longer than the time period of the timer 402 ( times out to a logic 0 output ), then a logic zero will be loaded into the flip - flop 404 and no wake - up signal will occur at the input 134 . the wake - up signal at the input 134 stays at logic 1 until no signal is received for a time period longer than the time period of the no signal timer 406 . the timer 406 will time out when an input thereto ( from the inverter 408 ) stays at a logic 1 for longer than the time period of the timer 406 . this will occur when no signal is present at the input 136 . a logic 0 at the clr input of the flip - flop 404 will reset the q output to a logic 0 , thus removing the wake - up signal from the input 134 . the invention , therefore , is well adapted to carry out the objects and attain the ends and advantages mentioned , as well as others inherent therein . while the invention has been depicted , described , and is defined by reference to particular preferred embodiments of the invention , such references do not imply a limitation on the invention , and no such limitation is to be inferred . the invention is capable of considerable modification , alteration , and equivalents in form and function , as will occur to those ordinarily skilled in the pertinent arts . the depicted and described preferred embodiments of the invention are exemplary only , and are not exhaustive of the scope of the invention . consequently , the invention is intended to be limited only by the spirit and scope of the appended claims , giving full cognizance to equivalents in all respects .