a flicker reducing circuit according to the present invention is shown in fig1 with reference to fig5 a - 5h and fig6 a - 6c . this invention is applied to , by way of example , conversion of a non - interlaced digital video source , such as that supplied by a computer graphics frame buffer , to an interlaced analog video signal in rgb format , suitable for conversion to ntsc format in order to drive a standard ntsc output device such as a television receiver . other embodiments of the present invention are diagrammed in fig2 and 4 . the example diagrammed in fig2 will reference fig5 a - 5h , fig7 a and 7b and fig8 a and 8b . the example diagrammed in fig3 will reference fig9 a - 9c and fig6 a - 6c . the example diagrammed in fig4 will reference fig9 a - 9c , fig7 a and 7b and fig8 a and 8b . fig5 a - 5h diagram field timing of the video signals shown in fig1 and 2 , where l1 . . . l525 represent line 1 through line 525 of video signal , and which in aggregate make up a full frame of video . the horizontal axes of fig5 a - 5h are in time units . fig6 a - 6c diagram the time division multiplexed pixel output timing of the video signals output by the triple dacs with luts a 340 and b 350 shown in fig1 and 3 , where pixel n - 1 , pixel n and pixel n + 1 represent horizontally adjacent pixels in a given line of video , and where line m - 1 , line m and line m + 1 represent vertically adjacent lines of video in a given image frame . fig7 a and 7b diagram the time division multiplexed pixel output timing of the triple dac with luts 345 in fig2 and 4 . fig7 a represents the pixel timing when flicker reduction is enabled . fig7 b represents the pixel timing when no flicker reduction is performed . fig8 a and 8b diagram the muxsel 70 and dclk 90 signal waveforms used to generate the pixel output timings diagrammed in fig7 a and 7b , respectively . fig9 a - 9c diagram field timing of the video signals shown in fig3 and 4 , where l1 . . . l525 represent line 1 through line 525 of video signal , and which in aggregate make up a full frame of video . the horizontal axes of fig9 a - 9c are in time units . in the embodiment of the invention shown in fig1 a signal source 10 of non - interlaced digital video is directed to line buffers a 300 , b 310 and c 320 . the timing for this non - interlaced digital video input signal is as shown in fig5 a . the video input signal 10 is clocked into said line buffers a 300 , b 310 and c 320 at the pixel clock rate represented by signal clk 20 . write enable signal we lb1 30 enables loading of the video input signal 10 into the line buffer a 300 . the timing of the video input signal 10 as loaded into the line buffer a 300 is represented in fig5 b . note that the line buffer a 300 is loaded with every other line of input video , alternating between all even lines in a frame and all odd lines in a frame . write enable signal we lb2 40 enables loading of the video input signal 10 into the line buffer b 310 . the timing of the video input signal 10 as loaded into the line buffer b 310 is represented in fig5 c . note that the line buffer b 310 is loaded with every fourth line of input video , alternating between even lines in a frame and odd lines in a frame . write enable signal we lb3 50 enables loading of the video input signal 10 into the line buffer c 320 . the timing of the video input signal 10 as loaded into the line buffer c 320 is represented in fig5 d . note that the line buffer c 320 is loaded with every fourth line of input video , alternating between odd lines in a frame and even lines in a frame . the above described write enable timing signals effect the result that in the field time during which the line buffer a 300 is loaded with even lines , odd lines are alternated into the line buffers b 310 and c 320 . similarly , in the field time during which line buffer a 300 is loaded with odd lines , even lines are alternated into the line buffers b 310 and c 320 . buffered video signal outputs of said line buffers a 300 , b 310 and c 320 , which outputs are represented by reference numerals 100 , 110 and 120 , respectively , are each clocked at the pixel clock rate represented by signal clk / 2 60 , which is one half the clock rate of the signal clk 20 . this clocking enables output of the buffered video signals 100 , 110 and 120 as represented by fig5 e , 5f and 5g , respectively . the line buffer a 300 presents the buffered video signal 100 , as represented by fig5 e . note that the line buffer a 300 presents every other line of input video at one half clock rate , i . e . at the interlaced output video horizontal sweep rate , delayed by one input line period , and alternating between all even input lines in a frame and all odd input lines in a frame . the line buffer b 310 presents buffered video signal 110 , as represented by fig5 f . note that the line buffer b 310 presents every fourth line of input video at one half clock rate repeated for a total output time of two output video horizontal sweep periods with the starting line presented progressing by three lines each field . the line buffer c 320 presents buffered video signal 120 , as represented by fig5 g . note that the line buffer c 320 presents every fourth line of input video at one half clock rate repeated for a total output time of two output video horizontal output sweep periods , with the starting line presented progressing by three lines each field . the above described line timing effects the result that for each line of the buffered signal 100 presented by the line buffer a 300 during an output video horizontal sweep period , the line buffers b 310 and c 320 present the adjacent lines of buffered signal . the line buffers b 310 and c 320 alternate frame by frame in presenting prior lines of buffered signal and following lines of buffered signal . the output of the line buffer 300 , signal 100 , is presented to triple dac with luts a 340 . this integrated component clocks in the signal 100 at the pixel clock rate clk / 2 60 . the rgb components of the input signal are then internally translated using three look - up tables ( luts ) and presented to three digital to analog signal converters ( dacs ). the triple dac with luts a 340 outputs red , green and blue analog signals r 160 , g 170 and b 180 , respectively . signal vref1 140 represents a bias voltage controlling the intensity of the analog output signals 160 , 170 and 180 . the vref1 140 can vary between logic levels 0 . . . 1 , producing the analog output signals 160 , 170 and 180 in zero to full intensity . the pixel timing of the output signals 160 , 170 and 180 is as shown in fig6 a . the output signals of the line buffers b 310 and c 320 , signals 110 and 120 , respectively , are presented to multiplexor 330 . the multiplexor 330 input signal selection is controlled by the signal clk / 2 60 , which alternates selection between the signals 110 and 120 pixel by pixel . the multiplexor 330 outputs multiplexed signal 130 which is composed of alternate pixels from the line buffers b 310 and c 320 , clocked at twice the output video horizontal sweep rate . note , that the frame by frame alternation of prior and following lines of buffered signal presented by the line buffers b 310 and c 320 causes frame by frame alternation of the source , prior or following line , of the starting pixel selected by the multiplexor 330 for each line of the multiplexed output signal 130 . the multiplexor 330 output signal 130 is presented to triple dac with luts b 350 . this integrated component clocks in the signal 130 at the pixel clock rate clk 20 , twice the rate the signal 100 is clocked into the triple dac with luts a 340 . as described above for the triple dac with luts a 340 , the triple dac with luts b 350 outputs red , green and blue analog signals r 190 , g 200 and b 210 , respectively . signal vref2 150 represents a bias voltage controlling the intensity of the analog output signals 190 , 200 and 210 . the vref2 150 can vary between logic levels 0 . . . 1 , producing the analog output signals 190 , 200 and 210 from zero to full intensity . example pixel timing of the output signals 190 , 200 and 210 is shown in fig6 b and 6c , where fig6 b and 6c represent sequential frames of output video . the output signals r 190 , g 200 and b 210 are therefore time division multiplexed analog signals derived from the two lines of digital video input adjacent to the line of digital video input which was the source for the analog output signals r 160 , g 170 and b 180 . note that the frame by frame alternation of the source , prior or following line , of the first pixel presented by the multiplexor 330 for each line of the output signal 130 causes frame by frame alternation of the source of the pixel in each time division , as shown in fig6 b and 6c . this feature prevents a perceivable horizontal displacement that would otherwise occur in the output video signal . finally , the signal 160 is wire - or &# 39 ; ed with the signal 190 , the signal 170 with the signal 200 , and the signal 180 with the signal 210 , having the effect of summing the currents for each signal pair , to produce output signal combined interlaced analog video output 225 in rgb format . line timing of the signal 220 is as diagrammed in fig5 h . as shown above , the ratio of the signal vref1 140 to the signal vref2 150 controls the contribution of adjacent video lines to the current line of video output . for example , when the vref1 140 is 0 . 5 and the vref2 150 is 0 . 5 , one quarter is contributed by the prior line , one half by the current line , and one quarter by the following line . this results in significant reduction of apparent flicker , at some loss of vertical resolution . when the vref1 140 is 1 . 0 and the vref2 150 is 0 . 0 , the circuit described becomes a non - interlaced to interlaced video converter with no flicker reduction and no loss of resolution . note that the time division multiplexed pixel timing of the rgb output signals 160 , 170 , 180 , 190 , 200 and 210 remains as shown in fig6 a - 6c , while the relative intensity of the rgb output signals 160 , 170 and 180 shown in fig6 a and that of the rgb output signals 190 , 200 and 210 shown in fig6 b and 6c vary as the signals vref1 140 and vref2 150 vary . an alternative embodiment of the invention is shown in fig2 where the same reference numerals as those of fig1 represent the same components and signals , and their detailed explanation will be omitted for the sake of brevity . here the invention is similarly applied to conversion of a non - interlaced digital video source to an interlaced analog video output signal . in this example , however , the output signals of the line buffers a 300 , b 310 and c 320 , signals 100 , 110 and 120 , respectively , are time division multiplexed by a multiplexor 335 to a single triple dac with luts 345 . a clock generator and timing circuit 380 controls the contribution of adjacent video lines to the current line of video output . here , the triple dac with luts 345 is run at twice the rate of the triple dac with luts b 350 shown in fig1 to achieve the same level of flicker reduction . the output signals of the line buffers a 300 , b 310 and c 320 , the signals 100 , 110 and 120 respectively , which are as described for fig1 above , are presented to the multiplexor 335 . in this embodiment , however , a signal muxsel , 70 from the clock generator and timing circuit 380 selects the signal , 100 , 110 or 120 , to be output from the multiplexor 335 at any given time . the multiplexor 335 outputs a time division multiplexed signal 135 . the clock generator and timing circuit 380 also provides a signal dclk 90 , which is a clock signal of a frequency equal to or exceeding the maximum frequency of the signal muxsel 70 . the multiplexed output signal 135 is presented to the triple dac with luts 345 . this integrated component clocks in the time division multiplexed video signal 135 at the clock rate dclk 90 . as described above for the triple dacs with luts a 340 and b 350 in fig1 the triple dac with luts 345 outputs red , green and blue analog video signals r 165 , g 175 and b 185 , respectively . taken together , the signals r 165 , g 175 and b 185 represent rgb format output signal interlaced analog video output 220 . line timing of the signal 220 is as diagrammed in fig5 h . the signal muxsel 70 controls the contribution of adjacent video lines to the current line of video output in order to effect flicker reduction . although many implementations of the clock generator and timing circuit 380 can be envisioned , one possible implementation is to pre - program a programmable array logic component ( pal ) with several selectable muxsel and dclk signal patterns . to achieve , for example , the flicker reduction effected by pixel timing as diagrammed in fig7 a , the signals muxsel 70 and dclk 90 would be as diagrammed in fig8 a . to achieve the flicker reduction effected by pixel timing as diagrammed in fig7 b , the signals muxsel 70 and dclk 90 would be as diagrammed in fig8 b . another embodiment of the invention is shown in fig3 where the same reference numerals as those of fig1 represent the same components and signals , and their detailed explanation will be omitted for the sake of brevity . here the invention is applied to a circuit with an interlaced , rather than non - interlaced , digital video source , so the line buffers a 300 , b 310 and c 320 of fig1 are replaced in fig3 by a field buffer 360 and a line buffer 305 . the signal 130 presented to the triple dac with luts b 350 , the rgb ; output signals 160 , 170 , 180 , 190 , 200 and 210 , and the resulting combined interlaced analog video output signal 225 are as described for fig1 above , and their detailed explanations will therefore be omitted in the following description . in fig3 input signal 15 is a signal source of interlaced digital video input . the timing for the input signal 15 is as shown in fig9 a . note that the signal 15 operates at a rate of clk / 2 , that is , the signal 15 operates at the interlaced output video horizontal sweep rate , and is identical to the line buffer a 300 output signal 100 of fig1 described above . the video input signal 15 is presented to the triple dac with luts a 340 , and also to the field buffer 360 . the video input signal 15 is clocked into the field buffer 360 at the pixel clock rate represented by the signal clk / 2 60 . the field buffer 360 , therefore , is first loaded with all odd lines in a frame , then with all even lines in a frame . the output of the field buffer 360 , a buffered video signal 115 , is clocked at the pixel clock rate represented by the signal clk / 2 60 . this clocking enables output of said buffered video signal 115 as diagrammed in fig9 b . the buffered video signal 115 is presented both to the multiplexor 330 and to the line buffer 305 . the line buffer 305 outputs a signal 125 which is also clocked at the pixel clock rate represented by the signal clk / 2 60 . the horizontal line timing of the output signal 125 is diagrammed in fig9 c . the line buffer 305 , therefore , has the effect of delaying its input by one period . note that the field buffer 360 presents every line of interlaced video input , delayed by one field , at the interlaced output video horizontal sweep rate . the line buffer 305 also presents every line of interlaced video input , delayed by one field plus one input line period . the above described line timing effects the result that for each line of the interlaced video input signal 15 presented during an output video horizontal sweep period , the field buffer 360 and the line buffer 305 present the adjacent lines of video signal from the prior field of interlaced video input . the output signals of the field buffer 360 and the line buffer 305 , the signals 115 and 120 respectively , are presented to the multiplexor 330 . the multiplexor 330 input signal selection is controlled by a signal 75 , which signal is composed of the signal clk / 2 60 exclusive - or &# 39 ; ed with a signal oddframe 65 . selection alternates , therefore , between the signals 115 and 125 pixel by pixel and alternates frame by frame whether , for each line , a pixel from the signal 115 or from the signal 125 is presented first . the multiplexor 330 outputs a multiplexed signal 130 which is composed of alternate pixels from the field buffer 360 and from the line buffer 305 , clocked at twice the output video horizontal sweep rate . the remainder of the circuit diagrammed in fig3 operates as described for the circuit diagrammed in fig1 above . flicker reduction is achieved by time division multiplexing of the video output signal as described therein . horizontal displacement of the output signal is prevented by the frame by frame alternation of the starting pixel presented by the multiplexor 330 as described above . yet another embodiment of the invention is shown in fig4 where this invention is directed to a circuit which operates on an interlaced video source . the input portion of the circuit is as described for fig3 above . the remainder of the circuit diagrammed in fig4 operates as described for the circuit diagrammed in fig2 above . in fig4 the same reference numerals as those of fig2 and 3 represent the same signals , and their detailed explanation and the detailed explanation of the circuit is omitted for the sake of brevity . flicker reduction is achieved by time division multiplexing of the video output signal as described for the circuit diagrammed in fig2 . although the above description has been given of particular preferred embodiments of the invention , with reference to the accompanying drawings , these should not be construed as limiting the scope of the invention , but as merely providing what i presently regard as the best modes for practicing this invention . it will be apparent that many modifications and variations on this invention could be effected by one skilled in the art without departing from the spirit and scope of the novel concepts of the invention . thus , the scope of the invention should be determined by the appended claims and their legal equivalents , rather than by the examples given .