in a traditional ring oscillator , each stage is connected to the next stage in series . in an interleaved ring oscillator , each stage has more than one input , and the inputs are connected to the output of more than one other stage . by interconnecting the stages in an interleaved configuration , more delay subdivisions than the 2 * n phases of a traditional oscillator can be achieved , as discussed below . fig4 a shows a simplified circuit diagram of an interleaved ring oscillator 40 . fig4 b shows a schematic signal - flow diagram of the symmetrical interconnection between the delay - interpolating mixer cells 42 shown in fig4 a . each of the four stages a - d is a simple delay - interpolating mixer , similar to the delay - interpolating mixer 34 shown in fig3 . each stage 46 of the interleaved ring oscillator 40 is comprised of a delay - interpolating mixer cell 42 that has two inputs 136 and 138 , and an output 39 . each delay - interpolating mixer cell 42 is connected to two other delay - interpolating mixer cells 42 , as shown in fig4 a and 4b , such that the two inputs of each delay - interpolating mixer cell 42 are connected to the outputs of two other cells , and the output of each delay - interpolating mixer cell 42 drives an input of two other delay - interpolating mixer cells 42 . one of the inputs 138 of each cell 42 is connected to the output 39 of the stage 46 immediately to the left . the other of the inputs 136 of the cell 42 is connected to the output of the opposite cell 42 . for example , the first input 136 of stage c is connected to the output 39 of stage a , the second input 138 of stage c is connected to the output 39 of stage b , and the output 39 of stage c is connected to the input 136 of stage a and to the input 138 of stage d . note that the input 136 of stage a inverts the incoming signal from output 39 of stage c . in each mixer cell 42 a - d , the two inputs 136 and 138 are combined with a predetermined weighting . the output 39 of each stage a - d includes a contribution from each of the inputs of the stage . in the preferred embodiment , the two inputs 136 and 138 of each mixer cell are combined with equal weighting so that the output of the stage is the average of the two inputs . the resulting four - stage interleaved ring oscillator 40 can oscillate at a frequency of 1 . 5 /( 8 * t d ), higher than the traditional limit of 1 /( 2 * n * t d ). the oscillation frequency is discussed below for one tuning state ( equation 1 ) of a tunable interleaved ring oscillator 90 ( fig5 ), in which four stages a - d are interconnected in a similar manner to the interleaved ring oscillator 40 . the interleaved ring oscillator 40 also produces more output phases without resorting to external interpolators . since the outputs 39 are generated by identical stages a - d , there is no need to match delays of interpolators 26 and dummy interpolators 24 ( fig2 a , 2b ) for the outputs to have evenly - spaced phases . while the interleaved ring oscillator 40 shown in fig4 a and 4b is not tunable , it has no phase spacing problems , as occurs with external interpolators . one way to view the four - cell ring oscillator 40 of fig4 a is as a pair of cross - coupled &# 34 ; two - ring &# 34 ; oscillators , operating in quadrature , as shown in fig4 b . cells a and c operate at phases of 0 and 180 degrees , while cells b and d operate at phases of 90 and 270 degrees . in addition , by symmetrically cross - coupling cells , b to c , c to d , d to a , and a to b respectively , two &# 34 ; two - stage &# 34 ; ring oscillators are formed . the two &# 34 ; two - stage &# 34 ; ring oscillators stay locked to each other , or &# 34 ; interleaved &# 34 ;. fig4 a and 4b show a preferred way of interconnecting four mixer cells 42 . in these figures , the &# 34 ; a &# 34 ; mixer cell 42a is shown as being driven by mixer cells d and c . however , there are several ways multiple mixer cells 42 can be interconnected to form a ring oscillator 40 . for example , mixer cell a can be driven by mixer cells b and c , or by mixer cells b and d . however , some ways of interconnecting the mixer cells 42 are preferable to others , as will be discussed below . fig5 shows a preferred embodiment of a four - stage , tunable interleaved ring oscillator 90 , which is referred to in the first row of table 1 . each stage 146 comprises a dual mixer cell 72 having an output 139a . the output of the dual mixer cell 72 is also connected to the delay cell 74 . the delay cell 74 generates the second output 139b , which is delayed relative to output 139a , by the delay of the delay cell 74 . each dual mixer cell 72 has four inputs x , y , x d , and y d . each dual mixer cell 72 also has a tuning input 73 . the tuning inputs 73 of the four dual mixer cells 72 are connected to the oscillator tuning input 76 . the oscillator tuning input 76 adjusts the operating frequency of the tunable interleaved ring oscillator 90 , as described below . in each stage of the four - stage , tunable interleaved ring oscillator 90 , the output signals 139a and 139b are taken from before and after the delay cells 74 to provide the output signals a , b , c , and d , and the delayed output signals a d , b d , c d , and d d . in a practical embodiment of the interleaved ring oscillator 90 , each of the single - ended inputs and outputs shown in fig5 ( as well as in fig8 discussed below ) is actually implemented as a two - conductor differential connection . however , only single - ended connections are shown to simplify the drawings . stages a , b , c and d of the preferred four - stage , tunable interleaved ring oscillator 90 are interconnected such that the non - delay inputs x and y of each stage are connected to the non - delay outputs 139a of the two other stages shown in fig4 b , and the delay inputs x d and y d of each stage are connected to the delay outputs 139b of two other stages shown in fig4 b . for example , the inputs x , x d , y , and y d of stage a are connected to the outputs c and c d of stage c and to the outputs d and d d of stage d , respectively . similarly , the inputs to stage b are connected to the outputs d and d d of stage d and to the outputs a and a d of stage a , the inputs to stage c are connected to the outputs a and a d of stage a and to the outputs b and b d of stage b , and the inputs to stage d are connected to the outputs b and b d of stage b and to the outputs c and c d of stage c . in a four - stage , interleaved ring oscillator , there are three different ways of interconnecting the dual mixer cells 72 , as shown in table 1 . the table also shows the resulting phase delay t e for each four - stage interleaved ring oscillator , in terms of the cell delay t d . some methods of interconnection between dual mixer cells 72 are more preferable than others , as discussed below . as will be described below with reference to the inversion of inputs , the prime symbol &# 39 ; is used to indicate an inverted input . for example , in the first row of table 1 , c &# 39 ; indicates that the inversion of the output signal of stage c is used as an input to stage a . table 1______________________________________interconnections t . sub . e unwanted modes ? comments______________________________________a = 0 . 5c &# 39 ; + 0 . 5d &# 39 ; t . sub . d / 1 . 5 unlikely preferred embodimentb = 0 . 5d &# 39 ; + 0 . 5ac = 0 . 5a + 0 . 5bd = 0 . 5b + 0 . 5ca = 0 . 5b &# 39 ; + 0 . 5c &# 39 ; t . sub . d / 2 . 5 somewhat likelyb = 0 . 5c &# 39 ; + 0 . 5d &# 39 ; c = 0 . 5d &# 39 ; + 0 . 5ad = 0 . 5a + 0 . 5ba = 0 . 5d &# 39 ; + 0 . 5b t . sub . d / 4 likelyb = 0 . 5a + 0 . 5cc = 0 . 5b + 0 . 5dd = 0 . 5c + 0 . 5a &# 39 ; ______________________________________ the preferred structure of the dual - input mixer 72 used in the four - stage , tunable interleaved ring oscillator 90 is shown in fig6 . the dual - input mixer 72 is based on the delay - interpolating mixer cell 34 shown in fig3 . to aid in understanding the circuit shown in fig6 frequency tuning for the interpolating mixer cell 34 shown in fig3 will first be described in more detail . in fig3 an analog tuning input 37 adjusts the relative current between the left differential transistor pair 33a and the right differential transistor pair 33b . at one end of the tuning range , the left transistor pair 33a is fully conducting , while the right transistor pair 33b is hardly conducting at all , so that nearly all the current from the current generator 35 passes through the left half 33a of the delay - interpolating mixer 34 . consequently , the output voltage is generated across the common collector resistors 31 in response to the input voltage 36 . this results in a mixer delay equal to the delay of the delay - interpolating mixer 34 itself . at the other end of the tuning range , the left transistor pair 33b is hardly conducting at all , while the right transistor pair 33b is fully conducting , so that nearly all the current from the current generator 35 passes through the right half 33b of the delay - interpolating mixer 34 . consequently , the output voltage is generated across the collector resistors 31 in response to the input voltage delayed by the delay cell 32 . this results in a mixer delay equal to the sum of the delays of both the delay - interpolating mixer 34 and the delay cell 32 . elsewhere in the tuning range , when both transistor pairs 33a and 33b are conducting , the output voltage across the collector resistors 31 is generated in response to a weighted sum of the input voltage 36 and the input voltage delayed by the delay cell 32 . the weighting depends on the tuning voltage 37 . the dual - input mixer 72 shown in fig6 combines four differential pairs of inputs 82 together , and can be thought of as two interconnected delay - interpolating mixers 34 , which comprise a left half 73a and a right half 73b of the dual - input mixer 72 . the delay interpolating mixers 34 both feed the common collector resistors 81 across which the output voltage 139 is generated . each dual - input mixer 72 has a tuning input 84 , four differential inputs 82 labelled x , x d , y , y d , and a differential output 139a labelled z . current generators 79a and 79b are connected to the left half 73a and a right half 73b of the dual - input mixer 72 , respectively . the total current flowing through the collector resistors 81 is divided equally between the current generators 79a and 79b , as described below . when implemented within an interleaved ring oscillator , one of the outputs 139a and its delayed version 139b from a neighboring stage 146 are connected to differential inputs 82 x and x d respectively , while a second output 139a and its delayed version 139b from another neighboring stage 146 are connected to differential inputs 82 y and y d respectively . since equal currents i 1 and i 2 are conducted through the left half 73a and the right half 73b of the dual - input mixer 72 , through the current generators 79a and 79b , the relative contributions of x and y and of x d and y d remain equally weighted in the output 139a z . therefore , the two non - delayed input pairs 139a entering each stage 146 are averaged with equal weighting by the dual - input mixer 72 . the two delayed input pairs 139b are also averaged with equal weighting by the dual - input mixer 72 . alternatively , the input pairs may be combined with unequal weighting by setting the ratio between the currents i 1 and i 2 to a value different from 1 . in the preferred embodiment , the sum of the weights of input pairs x and x d is 0 . 5 , and the same is true for input pairs y and y d . therefore , the &# 34 ; x &# 34 ; contribution to the output and the &# 34 ; y &# 34 ; information contribution to the output remain constant at a 50 : 50 ratio . for example , in fig5 for stage a , input signals from stages c and d are averaged , using signals c and d , connected to inputs x and y of stage a , as well as signals c d and d d , connected to inputs x d and y d of stage a . the outputs and inputs of the stages 146 remain fully coupled by a fixed amount . hence , the four stages 146 remain uniformly coupled together over the entire tuning range , resulting in a fully differential tuning system . referring again to the dual - input mixer 72 in fig6 as the tuning input 84α is adjusted between 1 and - 1 , the relative weights given to the input pairs x and y , and x d and y d in the output z of the dual - input mixer 72 are changed . varying the tuning input 84α between 1 to - 1 causes the left half 73a of the mixer cell 72 to change the proportion between inputs x and x d , and causes the right half 73b to change the proportion between inputs y and y d . when α =- 1 , z is nearly all x d , y d , and there is essentially no x , y contribution . when α = 1 , z is nearly all x , y , and there is essentially no x d , y d contribution . the frequency of the dual - input mixer 72 is continuously tunable between a frequency f min , at which the delay of each dual - input mixer 72 is a maximum , and f max , at which the delay of each dual - input mixer 72 is a minimum . elsewhere in the tuning range , the frequency of the dual - input mixer 72 lies between a f min and f max . the frequency depends upon the relative contributions of the non - delayed inputs x and y and the delayed inputs x d and y d to the output of each stage 146 . when tuning input 84α = 1 , currents substantially equal to i 1 and i 2 flow through steering transistors q9 and q11 . consequently , transistor pairs q1 , q2 and q5 , q6 are fully conducting , while transistor pairs q3 , q4 and q7 , q8 are hardly conducting at all . output z is then derived solely and equally from inputs x and y . if the mixer delay is denoted as t dm , and recalling that phase delay t e = t dm / 1 . 5 for the preferred four - stage oscillator 90 of fig5 and table 1 , then the frequency of oscillation is given by ## equ1 ## which is the maximum operating frequency f max . when tuning input 84α =- 1 , currents substantially equal to i 1 and i 2 flow through steering transistors q10 and q12 . consequently , transistor pairs q1 , q2 and q5 , q6 are hardly conducting , while transistor pairs q3 , q4 and q7 , q8 are fully conducting . output z is then derived solely and equally from inputs x d and y d . ## equ2 ## this realizes an interleaved oscillator that oscillates at the lowest frequency , where t dc is the delay of the delay cell 74 . in fig6 the dual - input mixer 72 first does variable weight ( i . e ., tuning ) summing between x and x d and between y and y d , and then does fixed - weight summing between ( x + x d ) and ( y + y d ). the circuit shown in fig6 can be alternatively be reconfigured to perform equal , fixed - weight summing of x and y and of x d and y d , followed by variable - weight ( i . e ., tuning ) summing between ( x + y ) and ( x d + y d ). as discussed above , there are multiple ways , referred to as topologies , in which multiple stages 146 of an interleaved ring oscillator can be interconnected . for example , in a four - stage , interleaved ring oscillator , there are three ways of interconnecting the dual - input mixer cells 72 , as shown in table 1 . a preferred interconnection topology is one in which the phases required for generating harmonics are much higher , possibly by a factor of 2 to 3 , than the phase required for the oscillator to oscillate at the fundamental frequency . when this condition is met , the frequency roll - off of the stages 146 forming the interleaved ring oscillator causes such a large gain loss at the frequency of the next harmonic that oscillation at the harmonic frequency can not be supported . this provides stable operation at the fundamental frequency . the preferred four - stage interleaved ring oscillator 90 shown in fig5 has been shown to be stable by both simulation and measurement . the lowest spurious frequency mode is at a frequency of twice that of the fundamental mode . this frequency is generally well down on the gain - bandwidth curve of the stages 146 . two other topologies ( rows 2 and 3 in table 1 ) are possible for a four - cell interleaved oscillator . for example , output a can also be derived from inputs b &# 39 ; and c &# 39 ;, or from inputs b and d &# 39 ;. these connections yield phase delays of t e = t d / 2 . 5 and t e = t d / 4 , respectively . however , interconnecting the stages with these topologies permits the resulting ring oscillator to oscillate at frequencies other than the fundamental frequency . the possibility of the oscillator having such unwanted modes is listed as being &# 34 ; somewhat likely &# 34 ; or &# 34 ; likely &# 34 ; in table 1 , since when the stages are interconnected as indicated , the oscillator has spurious modes of oscillation that fall within the amplifier gain profile . in simulation , these alternative topologies show hopping between various modes , as the ring oscillator is tuned . for some interleaved ring oscillator embodiments that have spurious modes of oscillation that fall within the amplifier gain profile , the oscillators must be preset to a known state to guarantee that they oscillate at a desired frequency . fig7 is a graph 100 that shows phase relationships between the four output waveforms 102 a - d generated by the four stages a , b , c and d 146 for the preferred ring oscillator 90 of fig5 . the output of stage c 102c is derived from the weighted sum of the outputs of stages a 102a and b 102b . the time spacing between the outputs of stages a and b ( t e ) is 1 / 1 . 5 of the delay t d of the stage . this can be understood by realizing that the effective input edge 106 to stage c occurs at a time midway between the times at which edges occur in the outputs of stages a and b ( 104a and 104b ). then , at a time equal to the gate delay t d of stage c after the effective input edge 106 , the output 102c of stage c changes state . the dual - input mixer cell 72 of stage c averages the outputs of stages a and b with equal weighting , so that the transitions 104a and 104b become the effective edge 106 . consequently , the midpoint 104c of the edge in the output 102c of stage c occurs following the gate delay t d of stage c . in a similar manner , half of the output of stage c and half of the output of stage b are used to generate the input of stage d . to generate the input of stage a , inversions c &# 39 ; of the output of stage c and d &# 39 ; of the output of stage d are used . to generate the input of stage b , the output of stage a and d &# 39 ; of the output of stage d are used . in all embodiments of the invention , which are comprised of a total of three or more total stages , each stage is driven by two previous stages , in a symmetrical way . fig8 is a single - ended schematic of a frequency - tunable interleaved oscillator 70 having three stages 146 , in which each stage 146 comprises a dual - input mixer cell 72 ( fig6 ) driven by the output of two other mixer cells , a delay cell 74 , an output 139a and a delayed output 139b . the inputs to stage a are driven by outputs from stages b and c , the inputs to stage b are driven by outputs from stages c and a , and the inputs to stage c are driven by outputs from stages a and b . a tuning signal 76 is used to adjust the operating frequency of the interleaved ring oscillator 70 , as discussed above . although the invention is described herein with reference to the preferred embodiment , one skilled in the art will readily appreciate that other applications may be substituted for those set forth herein without departing from the scope of the present invention . accordingly , the invention should only be limited by the claims included below .