fig3 represents a data coding / decoding and security / correction device ecc 3 according to the present invention . the device ecc 3 comprises a data coding and security circuit wr 3 and a data decoding and correction circuit rd 3 . the circuit wr 3 has one input in 1 to receive a binary word x 0 , and one output out 1 to deliver a secured code word x 2 . the circuit rd 3 has one input in 2 to receive a secured code word x 3 having an error e ( that can be zero ), and one output out 2 to deliver a corrected decoded word x 5 . according to the present invention , the circuit wr 3 comprises a block b 1 ′ that applies a coding and security function a * g to the word x 0 , and delivers the secured code word x 2 to the output out 1 . the function a * g is the product of a coding function a and of a security function g as readily known by one skilled in the art . as an example , it will be assumed that only one bit is to be detected and corrected in a word of eight bits by means of the hamming algorithm . the parameters k and j already described above are , in this case , equal to 3 and to 4 . the function g , in this case , is the matrix of 8 lines and 12 columns described in part 2 of the supplemental information . the function a is , for example , the matrix of 8 lines and 8 columns described in part 8 of the supplemental information . the corresponding function a * g according to the present invention , in this case , is equal to the matrix product of a and g and is described in part 10 of the supplemental information . generally speaking , the transit time of the data in the block b 1 ′ is roughly equal to the transit time of data in one of the prior art blocks b 0 or b 1 described above . the conversion time of the word x 0 into the secured code word x 2 is , therefore , noticeably reduced by half in accordance with the present invention . it will now be considered , as above , that the word x 2 is stored in a memory mem , and the word read subsequently in the memory shall be designated x 3 . x 3 is equal to the sum of the word x 2 and an error e . the correction of the error e and the decoding of the word x 3 are carried out by the circuit rd 3 . the circuit rd 3 comprises an error correcting block b 2 , a pattern generator block b 3 , an error vector ev ′ generator block b 4 ′, and a decoding block b 5 . the blocks b 2 , b 3 , b 5 are identical to the blocks in the prior art circuit ecc 2 described above . the block b 4 ′ delivers error vectors ev 1 ′ having 2 k bits corresponding to an error on the data and forming the useful part of an error vector ev ′ of the type : in which ev 2 ′ is an error vector of j bits corresponding to an error on security codes . ev 2 ′ is not used in practice . according to the present invention , the decoding block b 5 that applies the decoding function a − 1 to the data it receives at input , is arranged on the data path between the input in 2 of the circuit rd 3 and the input e 1 of the correction block b 2 . in other terms , the block b 2 receives at its input el non - corrected decoded data . as illustrated above , the word x 3 applied to the input in 2 of the circuit rd 3 can be written : the symbol + is the bit to bit addition without carrying the sum forward , and e is a word of 2 k + j bits representing the error affecting the word x 2 . the word x 3 and the error e can be written in the following form : data ( x 3 ) is a word comprising the 2 k data bits of the word x 3 , code ( x 3 ) is a word formed by the j security bits of the word x 3 , err 1 is a word comprising the 2 k first bits of the error e , and err 2 is a word comprising the j following bits of the error . the result is : data ( x 3 )= data ( x 2 )+ err 1 =( data ( x 0 )* a * g )+ err 1 the word data ( x 3 ) is applied to the input of the block b 5 without the security bits code ( x 3 ). therefore , the word x 4 ′ delivered by the block b 5 is equal to : x 4 ′= data ( x 3 )* − 1 =( x 0 * a * g * a − 1 )+ err 1 * a − 1 as a and a − 1 are reciprocal functions , the result is : x 4 ′=( x 0 * g )+ err 1 * a − 1 since the security function g does not change the data bits , the result is : x 4 ′= x 0 + err 1 * a − 1 . therefore , the word applied x 4 ′ to the input of the correction circuit b 2 is not a secured code word as in previous practices , but a decoded word comprising a coded error . the decoded word is the word x 0 and the coded error is the term err 1 * a − 1 i . e ., the transform of the error err 1 by the decoding function a − 1 . the decoding function a − 1 is comparable to a coding function when it is applied to an element that has not previously been coded by the reciprocal function a . the error vector ev 1 ′ that must be applied to the input e 2 of the block b 2 to correct the coded error err 1 * a − 1 should now be determined . as the word x 3 is applied entirely to the pattern generator block h , the result is : since the product of the functions h and g is zero , the pattern syn is therefore equal to : consequently , the pattern generated by the block b 3 is identical to the pattern generated by the block b 3 l of the devices ecc 1 and ecc 2 described above . moreover , the error vector ev 1 is equal to the non - coded error err 1 , such that the error vector ev 1 ′ can be expressed from the error vector ev 1 : the error vector ev 1 ′ according to the present invention is therefore a coded error vector , equal to the transform by the function a − 1 of the classical error vector ev 1 . the block b 4 ′ can be produced by combining in series the block b 4 and a block performing the function a − 1 . advantageously , a table of direct correspondence is determined giving the vector ev 1 ′ for each pattern value according to the present invention . each vector ev 1 ′ of the table of direct correspondence is calculated by applying the function a − 1 to the vectors ev 1 given by a classical table of correspondence . a hard - wired logic block b 4 ′ is then produced performing the conversion function given by the table of direct correspondence . for a better understanding , a table of correspondence according to the present invention is described in part 11 of the supplemental information . this table of correspondence ( table 2 ) is obtained by applying the function a − 1 to the vectors ev of the table of correspondence ( table 1 ) described in part 7 of the supplemental information . the operation of the device ecc 3 can therefore be summarized as follows . the block b 1 ′ generates a secured code word x2 from the initial word x 0 . the block b5 carries out the decoding of the secured code word x 3 and delivers a non - corrected decoded word x 4 ′ comprising a coded error err 1 * a − 1 . the block b 2 carries out the correction of the coded error by a coded error vector ev 1 ′ in the same way as the coded error , i . e ., by applying the function a − 1 to a classical error vector ev 1 . preferably , the block b 4 ′ delivers directly from the pattern syn the error vector ev 1 ′. the decoding and correction circuit rd 3 according to the present invention offers the advantage of having a parallel architecture , in which the decoding of the word x 3 by the block b 5 is carried out at the same time as the determination of the pattern and of the error vector ev 1 ′ by the blocks b 3 and b 4 ′. therefore , the decoding operation does not involve any slowing down of the data transfer time as in the prior art circuit ecc 2 , in which the decoding block b 5 is arranged downstream from the correction block . for a better understanding a description will now be given of an example of implementation of the decoding and correction method according to the present invention , using the functions a , g and h described in the supplemental information . it will be assumed that the word x 1 indicated below is to be written then read in the memory mem : after coding and securing the word x 0 using the function a * g ( block b 1 ′) the following is obtained : x 3 is written in the memory mem , and then a word is reread : x2 = ⁢ 0 ⁢ ⁢ 1 ⁢ ⁢ 0 ⁢ ⁢ 0 ⁢ ⁢ 0 ⁢ ⁢ 0 ⁢ ⁢ 1 ⁢ ⁢ 1 ⁢ ⁢ 0 ⁢ ⁢ 1 ⁢ ⁢ 0 ⁢ ⁢ 1 + e = ⁢ 0 ⁢ ⁢ 0 ⁢ ⁢ 0 ⁢ ⁢ 1 _ ⁢ ⁢ 0 ⁢ ⁢ 0 ⁢ ⁢ 0 ⁢ ⁢ 0 ⁢ ⁢ 0 ⁢ ⁢ 0 ⁢ ⁢ 0 ⁢ ⁢ 0 = x3 = ⁢ 0 ⁢ ⁢ 1 ⁢ ⁢ 0 ⁢ ⁢ 1 _ ⁢ ⁢ 0 ⁢ ⁢ 0 ⁢ ⁢ 1 ⁢ ⁢ 1 ⁢ ⁢ 0 ⁢ ⁢ 1 ⁢ ⁢ 0 ⁢ ⁢ 1 . using the function h ( block b 3 ) the corresponding pattern syn is calculated : using the table 2 in part 11 of the supplemental information ( block b 4 ′) the coded error vector ev 1 ′ is determined : at the same time as the determination of the pattern and of the error vector , the non - corrected decoded word x 4 ′ is determined by the function a − 1 ( block 5 ): x ′=( data ( x 2 )+ err 1 )* a − 1 = 0 1 0 1 0 1 1 0 . it will be clear to those skilled in the art that the data coding / decoding and security / correction device according to the present invention is susceptible to different embodiments and applications . in particular , the applications concern integrated circuits fitted with a memory . the device according to the present invention is interposed between the inputs and outputs of the memory . in particular , these are integrated circuits for smart cards , microcontrollers , integrated memories such as eprom , eeprom , flash eeprom type memories , etc . as another example of application , the coding and security circuit wr 3 can be arranged at one end of a data transmission line and the decoding and correction circuit rd 3 can be arranged at the other end of the line . this is done to decode and correct the data received , as errors can be due to transmission problems or to disturbances along the line . x 1 = x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 2 = x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 p 0 p 1 p 2 p 3 data ( x 2 )= x 1 = x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 p 0 , p 1 , p 3 , p 4 are security bits . part 2 — matrix generating security bits according to the hamming algorithm when k = 3 and j = 4 ( correction of only one error bit ): p 2 = x 4 xor x 5 xor x 6 xor x 1 xor x 3 part 4 — words e , err 1 , err 2 , x 3 , data ( x 3 ), code ( x 3 ): e = er 1 // er 2 = e 0 e 1 e 2 e 3 e 4 e 5 e 6 e 7 e 8 e 9 e 10 e 11 err 1 = e 0 e 1 e 2 e 3 e 4 e 5 e 6 e 7 x 3 = x 2 + e =( x 0 + e 0 ) ( x 1 + e 1 ) ( x 2 + e 2 ) ( x 3 + e 3 ) ( x 4 + e 4 ) ( x 5 + e 5 ) ( x 6 + e 6 ) ( x 7 + e 7 ) ( p 0 + e 8 ) ( p 1 + e 9 ) ( p 2 + e 10 ) ( p 3 + e 11 ) data ( x 3 )=( x 0 + e 0 ) ( x 1 + e 1 ) ( x 2 + e 2 ) ( x 3 + e 3 ) code ( x 3 )=( p 0 + e 8 ) ( p 1 + e 9 ) ( p 2 + e 10 ) ( p 3 + e 11 ) part 6 — value of the pattern syn generated by the matrix h when k = 3 and j = 4 : s 1 = x 2 xor x 3 xor x 4 xor x 7 xor x 1 xor p 1 s 2 = x 4 xor x 5 xor x 6 xor x 3 xor x 1 xor p 2 s 3 = x 6 xor x 7 xor x 3 xor x 2 xor x 0 xor p 3 part 7 — example of a classical table of correspondence when k = 3 and j = 4 :