referring initially to fig1 a multi - node computing system is shown , generally designated 10 . as shown , the system 10 includes a network of nodes 12 connected together by links 14 . some of the nodes are faulty nodes 16 . some links 14 may also fail as well ; for convenience , a failed link 14 can be , but not must be , represented by modeling the nodes at the ends of the link 14 “ faulty ” nodes 16 . it is one non - limiting purpose of the present invention to promote the tolerance of the system 10 to faulty nodes during operation . in one intended embodiment , although illustrated in fig1 as a 12 × 12 grid of nodes for simplicity , the computer system 10 may be a multi - node system such as , by way of non - limiting example only , ibm &# 39 ; s blue gene system . while blue gene has a mesh topology , other systems and other topologies can be used , such as but not limited to grids , meshes , hypercubes , and torus graphs . a group controller 18 communicates with a preferably software - implemented logic module 20 to execute the logic disclosed below in designating a set of “ lamb ” nodes to be used for routing messages through the system 10 in the presence of faulty nodes 16 and / or faulty links . by “ lamb ” node is meant a node whose processing capability is sacrificed for routing messages only ; that is , a lamb node only routes messages , and does not send or receive messages . while the controller 18 is shown for illustration as being separate from the nodes 12 of the system 10 and connected thereto for message routing purposes , it is to be understood that the present logic can be undertaken by one of the nodes 12 or distributed within the system 10 for coordinated processing between plural nodes 12 . with the above overview of the present architecture in mind , it is to be understood that the present logic is executed on the architecture shown in fig1 in accordance with the flow charts discussed below . the flow charts herein illustrate the structure of the logic of the present invention as embodied in computer program software . those skilled in the art will appreciate that the flow charts illustrate the structures of logic elements , such as computer program code elements or electronic logic circuits , that function according to this invention . manifestly , the invention is practiced in its essential embodiment by a machine component that renders the logic elements in a form that instructs a digital processing apparatus ( that is , a computer ) to perform a sequence of function steps corresponding to those shown . in other words , the logic may be embodied by a computer program that is executed by a processor as a series of computer - executable instructions . these instructions may reside , for example , in ram or on a hard drive or optical drive , or the instructions may be stored on a dasd array , magnetic tape , electronic read - only memory , or other appropriate data storage device . in an illustrative embodiment of the invention , the computer - executable instructions may be lines of compiled c ++ compatible code . now referring to fig2 the overall logic of the present invention can be seen . commencing at block 22 , the identities of the faulty nodes 16 are received . moving to block 24 , based on what nodes are faulty , a “ lamb ” set of nodes is determined as set forth further below . in block 26 the system removes or reallocates the user &# 39 ; s jobs or processes running on all nodes in the lamb set to other healthy non - lamb nodes , thereby eliminating the possibility that messages will be sent from or received into any lamb node . however , the lamb set nodes are physically functioning nodes and are used to route by - passing messages as any other healthy , non - lamb node . in the following , definitions are set forth that assume that the interconnection network has a d - dimensional structure , in describing one presently preferred embodiment . it is to be understood that the below definitions can be modified for a general interconnection network . for example , the π - routing or π - ordered routing can be generalized to any routing on any interconnection network . “ d ” represents the number of dimensions of the system 10 topology , e . g ., the dimensions of a mesh ; & lt ; v , w & gt ; represents a link from a source node v to a destination node w ; “ dimension - ordered routing ” is a static routing in which every message travels according to the same predetermined order of dimensions . an ordering is specified by a permutation π of { 1 , 2 , . . . , d }, and the resulting dimension - ordered routing is called π - routing . in the case of faulty nodes , a single round of π - routing from one node to another may not always be sufficient , and up to “ k ” rounds consequently may be necessary , with each round using a different virtual channel from the other rounds to avoid deadlock . in this case a routing is specified by a vector “ π vector ”= π 1 , . . . π k of “ k ” 1 - round orderings , where for 1 ≦ i ≦ k the π i - routing is used during the i th round . in one non - limiting embodiment k = 2 ; a node “ u i ” can ( f , π i )- reach a node u i + 1 , if the π i - routing from u i to u i + 1 does not pass through any faulty node or link ; f / c = set of faults on ( d − 1 )- dimensional mesh obtained by taking all node and link faults in f whose last coordinate is “ c ”, and truncating this last coordinate ; a destination node “ w ” is ( k , f , π vector )- reachable from a source node “ v ” , and “ v ” can ( k , f , π vector )- reach “ w ”, if there exists nodes u 0 , u 1 , . . . , u k such that u 0 = v , u k = w , and u 1 can ( f , π i )- reach u i + 1 for 0 ≦ i & lt ; k ; a source equivalence class ( sec ) is a maximal set of non - faulty nodes v that all have the same reachability properties , i . e ., all source nodes in a sec can reach , in one round , the same destination nodes by π - ordered routing ; a destination equivalence class ( dec ) is a maximal set of non - faulty nodes v that all have the same reachability properties , i . e ., all destination nodes in a dec can be reached , in one round , from the same source nodes by π - ordered routing ; a source equivalence subclass ( ses ) is any nonempty subset of an sec , and a destination equivalence subclass ( des ) is any nonempty subset of a dec ; a subset v of the nodes of the system is a ( k , f , π vector ) survivor set if , for all v , w εv , v can ( k , f , π vector )- reach w ; in particular , v ∩ f n = 0 . a subset λ ⊂ all nodes is a ( k , f , π vector )- sacrificial lamb set , for short , a ( k , f , π vector )- lamb set , if λ ∩ f n = 0 and the set m of all nodes −( λ ∪ f n ) is a ( k , f , π vector )- survivor set , such that , by disallowing nodes in the lamb set to send or receive messages but allowing them to be on the routing paths of messages , all nonfaulty nodes not in the lamb set can communicate with each other in at most k rounds : finding a maximal survivor set , which is equivalent to finding a minimal lamb set , for a given dimensionality , fault set , and route ordering , is one purpose of the present invention . [ 0047 ] fig3 shows the overall logic for determining the lamb set at block 24 in fig2 . starting at block 28 in fig3 for each potential round π t in the set of rounds ( π 1 , . . . , π k ), small source ( ses ) and destination ( des ) partitions of non - faulty nodes are determined , with each partition having a representative node . details of the preferred non - limiting way to find the partitions are set forth further below in reference to fig4 . essentially , the ses partitions of the non - faulty nodes in the system 10 are pairwise disjoint ( between “ i ” and “ j ” for any “ i ” not equal to “ j ”. the des partitions likewise are pairwise disjoint . the union of all partitions encompasses all the non - faulty nodes in the system 10 . then , at block 30 for each source ses partition , it is determined whether its representative node “ v ” can reach each representative node “ w ” of each destination des partition within a predetermined reachability criteria . more specifically , it is determined , for each “ v ”, whether it can ( k , f , π vector )- reach each destination des representative node “ w ”, wherein “ k ” is the number of rounds and f is the set of faulty nodes and links . details of a preferred implementation of block 30 are set forth further below in reference to fig5 . all ses / des that do not satisfy the reachability test of block 32 are candidates for the lamb set and are sent to block 32 , the goal of which is to prune the candidates and , thus , minimize the size of the lamb set . as set forth further below in reference to fig6 and 7 , the lamb set minimization problem of block 32 is solved by reducing the problem to a weighted graph cover problem ( e . g ., a weighted vertex cover problem ) and solving the weighted graph problem . now referring to fig4 the details of one preferred , non - limiting logic for partitioning the non - faulty nodes into ses partitions is shown . it is to be understood that the nodes are partitioned into des using the same logic , except that the recursion considers coordinates from left to right in the des case instead of from right to left as in the ses case . in the discussion below , using , by way of non - limiting illustration only , a rectangular subset of nodes of a mesh m = m d ( n 1 , . . . , n d ), each coordinate “ j ” can be designated by one of three objects : “*”, meaning that any value v j with 0 ≦ v j & lt ; n j can appear in the coordinate , an interval [ l j , r j ], meaning that any value v j with l j ≦ v j ≦ r j can appear in the coordinate , and a constant c j , meaning that only the value c j can appear in the coordinate . the below algorithm finds ses &# 39 ; s of the form s =(*, . . . ,*,[ l j , r j ], c j + 1 , . . . , c d ) and des &# 39 ; s of the form d =( c 1 , . . . , c j − 1 ,[ l j , r j ],*, . . . ,*). the representative node of an ses is of the form ( 0 , . . . 0 , 1 j , c j + 1 , . . . , c d and of a des is ( c 1 , . . . , c j − 1 , 0 , . . . 0 ). while the discussion below describes the algorithm recursively , it is to be understood that other implementations can be used . for instance , at the start of the algorithm the faults can be sorted by radix sort with the significance of the coordinates increasing from left to right , and with calls to the algorithm below the top level adding ses &# 39 ; s directly to the solution set , rather than passing them up to the calling program . it is to be further understood that , without loss of generality , the π ordering is assumed to be in ascending order ( 1 , 2 , . . . , d ). for a general π ordering ( j 1 , . . . , j d ), the algorithm is modified to consider the coordinates in the reverse order given by π . an input to decision diamond 34 is a d - dimensional mesh of the form n 1 by n 2 by . . . by n d , denoted m d ( n 1 , . . . , n d ). also input is the set f of faulty nodes . commencing at decision diamond 34 , it is determined whether the system 10 is one - dimensional , i . e ., whether d = 1 . if so , the logic flows to block 36 to partition the non - faulty nodes into maximal intervals [ l 1 , r 1 ], . . . ,[ l m , r m ] such that each interval contains no node fault or link fault . then , at block 38 the solution set , i . e ., the set of maximal intervals , is returned . on the other hand , when d & gt ; 1 the logic moves from decision diamond 34 to block 40 to initialize the solution set to zero and to define a fault set h of values “ c ” such that (*, . . . *, c ) contains either a node fault or a link fault . proceeding to block 42 , a do loop is entered for each value “ c ” in the fault set h . at block 44 , a find ses partition is called wherein an ses partition “ ses ” is found on an input ( d − 1 , n 1 , . . . , n d − 1 ) and f / c . then , moving to block 46 , for each of the ses &# 39 ; s found at block 44 , its product with “ c ” is added to the solution set , i . e ., s ′· c , which is of the form (*, . . . ,*,[ l j , r j ], c j + 1 , . . . , c d − 1 , c ), is added to the solution set . the do loop ends at block 48 . after completing the do loop the logic proceeds to block 50 to partition the values that are not in h into maximal intervals [ l , r ] such that (*, . . . *,[ 1 , r ]) contains no node fault or link fault . at block 52 , for each maximal interval [ l , r ], (*, . . . *,[ l , r ]) is added to the solution set , which is returned . to save memory , each ses partition and des partition can be computed at the point where the below - described reachability matrix r is needed , after which the reachability matrix and associated partitions can be erased . it is to be understood that while the logic of fig4 applies particularly to mesh topologies , in other topologies the partitions can be found by explicitly computing the reachability sets ( as a source and as a destination ) for each node . now referring to the reachability algorithm of fig5 commencing at block 54 , for each “ t ” in 1 ≦ t ≦ k , p t is defined to be the size of the corresponding ses in the solution set from fig4 ( with “ π ” being understood to be π t ), s t , i is the i th partition in this solution set , s t , i is its representative node , q t is the size of the corresponding des in the solution set of fig4 ( with “ π ” being understood to be π t ), d t , j is the j th partition in this solution set , and d t , j is its representative node . moving to block 56 , for each “ t ” in 1 ≦ t ≦ k , the one - round reachability entries of a p t × q t reachability matrix “ r t ” are computed , where r t ( i , j )= 1 iff s t , i can ( f , π t )- reach d t , j . next , proceeding to block 58 , for 1 ≦ t ≦ k − 1 , the entries of a q t × p t + 1 intersection matrix i are computed , where i t ( j , i )= 1 iff d t , j ∩ s t + 1 , 1 ≠ 0 . the product r k of the matrices , i . e ., r 1 i 2 r 2 i 2 . . . r k − 1 i k − 1 r k is returned . if the same ordering π and same ses and des partitions are used in each round , the algorithm can be simplified because in such a case r 1 = r 2 =. . . = r k and likewise the intersection matrices are equal to each other . define p = p 1 and q = q k . the product r k , rectangualr abbreviations s 1 , . . . , s p for the partitions s 1 , 1 , . . . , s 1 , p , and rectangular abbreviations d 1 , . . . , d q for the partitions d k , 1 , . . . , d k , q are sent from the logic of fig5 to the logic of fig6 . commencing at block 62 , a weighted bipartite graph g is constructed with vertex partition { s 1 , . . . , s p } and { d 1 , . . . , d q }. as recognized herein , an edge between s i and d j exists iff r k ( i , j )= 0 . the weights are w ( s i )=| s i | and w ( d j )=| d j |. moreover , the weights can be made not only a function of the size of a set of nodes , but also of individual node values that are based on the number of processors in the node that function properly ( or equivalently that are malfunctioning ). the individual node values can be added to or multiplied by the size value . in this way , a node ( e . g ., a chip in a multiprocessor ) that has only one good processor and that consequently would be a good candidate to be a lamb node ( since not much processing capability is lost by sacrificing it ) is more likely to be chosen as a lamb node . moving to block 64 , a minimum weight vertex cover c is determined for the graph g in accordance with principles known in the weighted graph art and returned . the lamb set is returned at block 66 as the union of those ses partitions s i with s i ε c and those d j with d j ε c . instead of the logic of fig6 the logic of fig7 can be used to minimize the lamb set . commencing at block 68 , a weighted graph g is constructed with vertices u ={ u i , j | s i ∩ d j ≠ 0 }. as recognized herein , an edge between u i , j and u i ′ j , exists iff either r k ( i , j ′)= 0 or r k ( i ′, j )= 0 . the weights are w ( u i , j )=| s i ∩ d j |. moving to block 70 , a vertex cover c is determined for the graph g in accordance with principles known in the weighted graph art and returned . the lamb set is returned at block 72 as the union of those ses partitions s i ∩ d j over all ( i , j ) such that i , j ε c . while the particular system and method for fault tolerance in multi - node system as herein shown and described in detail is fully capable of attaining the above - described objects of the invention , it is to be understood that it is the presently preferred embodiment of the present invention and is thus representative of the subject matter which is broadly contemplated by the present invention , that the scope of the present invention fully encompasses other embodiments which may become obvious to those skilled in the art , and that the scope of the present invention is accordingly to be limited by nothing other than the appended claims , in which reference to an element in the singular means “ at least one ”. all structural and functional equivalents to the elements of the above - described preferred embodiment that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims . moreover , it is not necessary for a device or method to address each and every problem sought to be solved by the present invention , for it to be encompassed by the present claims . furthermore , no element , component , or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element , component , or method step is explicitly recited in the claims . no claim element herein is to be construed under the provisions of 35 u . s . c . § 112 , sixth paragraph , unless the element is expressly recited using the phrase “ means for ”.