referring to fig4 - 9 , fig4 - 9 are schematic diagrams of a method of forming a polysilicon resistor according to the present invention . as shown in fig4 , a dielectric layer 22 and a polysilicon layer 24 are formed on a substrate 20 , respectively . following that , as shown in fig5 , an ion implantation process is performed using both of n - type dopants and p - type dopants to dope the polysilicon layer 24 , thus adjusting the resistance of the polysilicon layer 24 . in a better embodiment of the present invention , a dosage of the n - type dopants and a dosage of the p - type dopants have the same order of magnitude . for example , the n - type dopants can be as − ions with a dosage of approximate 3e15 , and the p - type dopants can be bf 2 + ions with a dosage of approximate 1 . 5e15 . however , the present invention is not limited , other n - type dopants ( such as p or sb ) and p - type dopants ( such as ge or b ) having the same order of magnitude can also be applied in the present invention to adjust the resistance of the polysilicon layer 24 . when a cross section area of the polysilicon layer 24 of 100 μm × 10 μm is suggested , a high resistance value of approximate 29 kohm / sq for the polysilicon layer 24 can be obtained . since the variance for 25 wafers is measured to below 5 %, an excellent uniformity in the polysilicon resistors can also be obtained according to the present invention . as shown in fig6 , a photolithographic process and an etching process are then used to remove portions of the polysilicon layer 24 and the dielectric layer 22 down to the surface of the substrate 20 , thus defining the pattern of the polysilicon resistor . alternatively , the pattern of the polysilicon resistor can be defined using the photolithographic process and the etching process prior to the ion implantation process using both of the n - type dopants and the p - type dopants for adjusting the resistance of the polysilicon layer 24 . as shown in fig7 , a high resistance region 26 is defined at a central region of the polysilicon layer 24 , and at least a low resistance region 28 is defined at the either side of the high resistance region 26 . following that , a salicide block ( sab ) 30 is formed on the portions of the polysilicon layer 24 within the high resistance region 26 . using the sab 30 as a mask , a salicide layer 32 is formed on the portions of the polysilicon layer 24 within the low resistance region 28 . an example of the methods of forming the sab 30 and the salicide layer 32 is further explained below . a dielectric layer ( not shown ) is deposited on the surface of the substrate 20 followed by using a photolithographic process and an etching process to completely remove the portions of the dielectric layer in the low resistance region 28 , thus forming the sab 30 by the remainder of the dielectric layer in the high resistance region 26 . subsequently , a salicide process is performed by first using a physical vapor deposition ( pvd ) method to sputter a metal layer ( not shown ) on the surface of the substrate 20 . the metal layer is composed of tungsten or titanium . a thermal treatment process is thereafter performed to allow the reaction of the metal layer with the portions of the polysilicon layer 24 in the low resistance region 28 , thus forming the salicide layer 32 . in a better embodiment of the present invention , the polysilicon resistor has a sandwich - like structure which sandwiches the high resistance region 26 for providing high resistance between two low resistance regions 28 for forming the interconnection contact plugs . the present invention is characterized by using two different types of dopants to adjust the polysilicon resistance in the high resistance region , and forming the salicide layer to reduce the polysilicon resistance in the low resistance region . therefore , the present invention is not limited to the sandwich - like polysilicon resistor , and can also be applied in the polysilicon resistors of other structures to adjust the polysilicon resistance thereof . fig8 and 9 illustrate a method of forming an interconnection between the polysilicon resistor and other wirings . as shown in fig8 and fig9 , an inter layer dielectric ( ild ) 34 , such as a silicon oxide layer or a borophosphosilicate glass ( bpsg ), is formed on the surface of the substrate 20 to insulate the salicide layer 32 from other conductive materials . following that , a photolithographic process and an etching process are performed to form at least a contact hole 36 in the inter layer dielectric 34 to connect to the salicide layer 32 . a conductive layer 38 is then formed on portions of the inter layer dielectric 34 and within the contact hole 36 , thus connecting the polysilicon resistor to wirings formed above the inter layer dielectric 34 via the conductive layer 38 filling in the contact hole 36 . in contrast to the prior art method of forming the polysilicon resistor , the present invention uses two different types of dopants to adjust the polysilicon resistance in the high resistance region . being controlled by the dosage of the dopants , the polysilicon resistance in the high resistance region has a value ranging between ten and thousands kohm / sq according to the present invetion . therefore , the polysilicon resistor of the present invention is capable of providing a uniform and stable value of high resistance to satisfy the high resistance requirements for the sram , analog , digital / analog mixed mode and radio frequency circuit designs . in this case , a cross section area of the polysilicon resistor can also be reduced to enhance the device integration . those skilled in the art will readily observe that numerous modifications and alterations of the method may be made while retaining the teachings of the invention . accordingly , the above disclosure should be construed as limited only by the metes and bounds of the appended claims .