fig1 is a simplified circuit diagram of a known double resonance electronic converter , while fig2 is a curve showing the modulus of the frequency response of the resonant circuit between an input voltage ve and an output voltage vs . as shown in fig1 a double resonance electronic converter comprises four parts : a switching circuit 10 ; a double resonance circuit 12 ; a rectifying and filtering circuit 14 ; and a control circuit 16 for the switching circuit 10 . the switching circuit 10 comprises two switches t 1 and t 2 whose switching on ( conduction ) or off ( break ) are controlled by the control circuit 16 , the control being represented by a broken line 18 . the two switches t 1 and t 2 can be formed , e . g . of igbt ( insulated gate bipolar transistor ) type transistors , and their switching drive circuitry comprises an inductor l 1 ( or l 2 ) in series with the transistor / switch , a serial circuit r 1 c 1 ( or r 2 c 2 ) and a diode d 1 ( or d 2 ) in parallel . a dc voltage e is applied to the terminals of both switches t 1 and t 2 so that the potential of the positive pole is applied to the resonance circuit 12 when only switch t 1 is on , while the potential of the negative pole is applied when only switch t 2 is on . a known resonance circuit 12 comprises : a parallel resonant circuit comprising an inductor lp and a capacitor cp ; a series resonant circuit comprising inductors l 1 , l 2 , lr and lm , as well as a capacitor cr and a transformer tr having a transformer ratio equal to m . a known rectifying and filtering circuit 14 comprises : two rectifier diodes dr 1 and dr 2 , two filtering capacitors cf 1 and cf 2 and a load resistor rc . the output voltage v of the converter is taken from the terminals of resistor rc . the control circuit 16 controls the conduction and blockage of switches t 1 and t 2 as a function the following three parameters : the series current is in inductor lr , as measured by a device 20 ; the parallel current ip in inductor lp , as measured by a device 22 ; the output voltage v measured by a device 24 . the operating characteristics of the resonant circuit 12 provides a curve 26 , shown in fig2 of the modulus of the frequency response between an input voltage ve at the common node 24 of switches t 1 and t 2 , and an output voltage vs at the terminals of capacitor cp . this curve 26 shows two resonance frequencies f 0 and f 2 , and zero transmission at an intermediate frequency f 1 . as an example , the values can be as follows : f 0 = 18 . 16 khz , f 1 = 19 . 37 khz and f 2 = 138 . 59 khz . the converter in an embodiment of the invention may be used between frequencies f 1 and f 2 , between which the gain varies from 40 to 80 decibels , to enabling varying the voltage and power at the converter output . the operation is shown in fig3 where the series current is as a function of time , is being measured by device 20 , as follows . the instant when switch t 1 or t 2 begins to conduct is defined with respect to the instant x k , x k + 1 , x k + 2 or x k + 3 of end of conduction of the preceding switch , which corresponds to a passage to zero of the series current is , along one direction or the other , by counting respectively a period t ( k − 1 ), t ( k ) or t ( k + 1 ). accordingly , the start of conduction of switch t 2 is determined by counting down a duration t ( k ) that was calculated at the time of the preceding cycle during the conduction time of diode d 2 , referred to as a freewheeling diode . this aspect of calculating durations t is shown in the diagrams of fig4 . thus , fig4 a shows curves for the series current is ( full lines ) and parallel current ip ( broken lines ) upon starting a supply sequence . after starting , for example , a radiological ( x - ray ) image acquisition , and in a stable mode , switch t 1 , for instance is conducting , a calculation of duration t ( 4 ) is carried out during interval ( 4 ) and its value is counted down from the instant x 4 when the series current is an switch t 2 passes to zero . at the end of the interval t ( 4 ), switch t 1 is conducting between the instants x 4 and x 5 . t ( 5 ) is calculated during interval ( 5 ), and its value is counted down from the instant x 5 when the series current is in switch t 1 passes to zero , and so on for the values t ( 6 ) and t ( 7 ). when starting , for example , the radiological image acquisition , one of switches t 1 or t 2 is systematically caused to be conducting , for instance t 1 in the example of fig4 ( curve 40 ). also , there is carried out a first calculation of the countdown duration t ( 1 ), immediately from the starting instant , during the interval ( 1 ). t 1 being counted down from the instant x 1 when the series current is in switch t 1 passes to zero . from the start of counting down t ( 1 ), t ( 2 ) is calculated during the interval ( 2 ), which corresponds substantially to the conduction time of diode d 1 . duration t ( 2 ) is counted down from the instant x 2 when the series current is shown by curve 42 passes to zero . when the countdown of t ( 2 ) ends , switch t 1 becomes conducting again . meanwhile , the countdown duration t ( 3 ) is calculated during interval ( 3 ), the countdown of t ( 3 ) taking place from the instant x 3 when the series current is through switch t 1 passes to zero . fig4 d shows the intervals during which switch t 1 is conducting while fig4 e shows the intervals during which switch t 2 is conducting . the diagrams of fig4 show that the start sequence of the converter leads to very asymmetrical series currents is in going from one switch to the other . the conduction of the first switch establishes a direct current in the resonant circuit , which unbalances the series current is and deactivates the parallel current ip . the drawings of fig5 a to 5 e are analogous to those of fig4 a to 4 e , but correspond to an embodiment of the invention . the embodiment of the invention comprises making , e . g ., switch t 1 conducting , which yields the curves 40 and 42 for the series current is as well as curve 44 for the parallel current ip as in fig4 a . however , there is no calculation of the duration of times t ( 1 ) and t ( 2 ) to switch on switches t 2 and t 1 , respectively . in an embodiment , switch t 2 is set to the on state when the parallel current ip reaches a maximum positive value max at peak 46 . during the time interval ( 1 ′), the time period t ( 1 ′) is calculated for the count down starting from the point of passage to zero x ′ 1 of the start of switch t 1 being conducting . during the time interval ( 2 ′), the time period t ( 2 ′) is calculated for the count down starting from the point of passage to zero x ′ 2 of the start of switch t 2 being conducting . during the time interval ( 3 ′), the time period t ( 3 ′) is calculated for the count dawn starting front the point of passage to zero x ′ 3 of the start of switch t 1 being conducting ( curve not shown ). to obtain the above - described operation , the control circuit 16 comprises two state arrangements 50 and 60 that are shown schematically in fig6 and 7 , respectively . when off , the two state arrangements 50 and 60 are at the rest state rep for arrangement 50 and lib for arrangement 60 . before starting , for example , a radiological image acquisition , the operator carries out a number of settings according to the type of image to be acquired by inputting the corresponding parameters , and then starts the image acquisition by pressing a button . this button triggers the two state arrangements 50 and 60 by a reset to zero signal raz that bring them to an initial state . in , for example , a radiological acquisition , there is produced the logic signal p = 1 so that arrangement 50 passes to a state r 1 of counting down the time period t ( p ) while arrangement 60 passes to a state m . when the countdown in completed . t ( p )= 0 , switch t 1 is conducting , so bringing arrangement 60 to a run state corresponding to logic signal sq = 1 . when the series current is becomes equal to zero , logic signal ispos = 1 while sq = 1 , arrangement 50 returns to the rest state rep . the signal of that rest state rep causes arrangement 60 to pass to state synip , referred to as the state of synchronization with the parallel current ip . this state synip enables the definition of the instant of the maximum value of the parallel current ip , for instance by counting down a time period dip corresponding to one quarter of the time period of current ip . when dip = 0 and sq = 1 , arrangement 50 passes to state r 2 . in the general case of a starting sequence ; there is no countdown of the time period t ( p ), i . e . t ( p )= 0 or that period is fixed , so that switch t 2 is conducting . arrangement 60 then passes to a done state , which signifies the end of the starting sequence . arrangement 60 then passes to the lib state at the end of the acquisition when the arrangement 50 returns to the rest state rep at the end of the radiological image acquisition , i . e ., when the logic signal p = 0 appears , that signal p = 0 occurring during the countdown states r 1 or r 2 . an embodiment has been described for a control circuit 16 which first triggers the conducting state of switch t 1 , then that of switch t 2 when the parallel current ip attains the maximum positive value max . however , the embodiment can be implemented with a control circuit that first triggers the conducting state of switch t 2 and then that of switch t 1 but , in this case , the maximum value that is taken into account is the negative value of the parallel current ip . the invention and embodiments thereof is therefore directed to a double resonance electronic converter comprising : a switching circuit comprising a first switch and a second switch ; a double resonance resonant circuit comprising a series resonant circuit and a parallel resonant circuit ; a rectifying and filtering circuit , and a control circuit for controlling the switching circuit comprising two arrangements : a first arrangement for controlling states of the switching circuit and a second arrangement for controlling the start of the first arrangement . in an embodiment of the invention , the second arrangement comprises : means for measuring a current ip in the parallel resonant circuit ; and means for triggering first the conduction of the first switch and for triggering thereafter the conduction of the second switch when the parallel current reaches a maximum value . in an embodiment of the invention the instant of the maximum value of the parallel current is determined by a countdown of the duration of one quarter of the time period of the parallel current starting from the passage to zero of the parallel current . in an embodiment of the maximum value of the parallel current is of the same polarity as the series current flowing in the series resonant circuit . one skilled in the art may make or propose various modifications to the function and / or way and / or result of the disclosed embodiments without departing from the scope and extent of protection .