reference will now be made in detail to the presently preferred embodiments of the invention , examples of which are illustrated in the accompanying drawings . fig1 is a schematic block diagram illustrating an exemplary 3d graphics system 100 in which the present invention may be implemented . the graphics system 100 includes media 102 , a central processing unit ( cpu ) 104 communicatively coupled to a main memory 106 , a graphics processing unit ( gpu ) 108 communicatively coupled to a frame buffer 110 residing in a dedicated video memory , and a display controller or display processor 112 communicatively coupled to both the frame buffer 110 and a display device 114 such as a tv , lcd ( liquid crystal display ), and the like . the graphics system 100 may read data from the media 102 and display the corresponding 3d graphics on the display device 114 . in the 3d graphics systems , an object is typically drawn using numerous polygons such as triangles , and the like . a basic flow of operations in the graphics system 100 is shown as follows . the cpu 104 prepares a list of gpu rendering commands ( or rendering commands ) in the main memory 106 . the gpu 108 reads the rendering commands from the main memory 106 . the gpu 108 then decodes the rendering commands and draws pixel data to the frame buffer 110 . the display controller 112 reads pixel data that gets displayed on the screen from the frame buffer 110 . after each line gets drawn , a typical implementation of the display controller 112 generates a status signal allowing the cpu 104 or gpu 108 to synchronize its processing with the display controller 112 . this status signal is commonly referred to as horizontal synchronization ( hsync ) signal . similarly , there is a vertical synchronization ( vsync ) signal that the display controller 112 asserts when the display controller 112 has finished displaying the full screen . this vsync signal allows the cpu 104 and gpu 108 to know when to start drawing the next frame data . when the gpu 108 processes the rendering commands and generates the pixels to be drawn , the gpu 108 stores the pixel data in the frame buffer 110 which typically resides in a dedicated video memory . in order for the gpu 108 to store pixel data for the next frame while the display controller 112 reads data out from the frame buffer 110 , a technique called double buffering is used . the double buffering mechanism reserves two frames worth of memory space in the frame buffer 110 so that the data that are displayed on the screen through the display controller 112 may be held mutual exclusive to the memory location used by the gpu 108 to store the calculated results . the memory region that is read by the display controller 112 is often called a display region , and the region that the gpu 108 used to store the data for the next frame is referred to as a drawing region ( see , e . g ., fig2 and 5 ). the vsync signal from the display processor 112 is used to trigger both the cpu 104 and gpu 108 to swap the display and drawing regions . fig2 shows the content of a typical frame buffer 200 . as shown , the frame buffer 200 may include a texture area 202 for storing texture , a display region 204 for displaying a current frame , a drawing region 206 for drawing the next frame , and a clut area 208 for storing cluts . in a typical 32 - bit generation game system such as sony &# 39 ; s playstation and the like , the frame buffer size is roughly 1 mb ( megabytes ). the following calculations show a typical memory usage of the frame buffer in this system : 320 × 240 display resolution @ 16 bits per pixel = 320 × 240 × 16 bits = 1 , 228 , 800 bits = 153 , 600 bytes = 153 kb / frame 2 frames stored in the frame buffer , so 153 kb × 2 ≅ 300 kb out of 1 mb used for display and drawing regions so 700 kb is left for cluts and textures the frame buffer size is critical for the performance of a 3d graphics system as loading and unloading textures from the main memory usually takes a very long time . therefore , it is desirable to have as much free space in the frame buffer as possible to store textures and cluts . on the other hand , a large frame buffer may directly affect the cost and power consumption of the system , which are both critical factors to consider in a mobile electronics system such as pdas , cell phones , mobile gaming systems , and the like . the present invention may reduce the size of the frame buffer required in a 3d graphics system by eliminating the need of storing two full frame worth of data in the frame buffer to perform double buffering . by sorting the rendering commands based upon the location of a triangle ahead of time , the graphics system only needs to process those triangles that fall in particular section of the screen . in a preferred embodiment , the location of the screen that gets processed should be chosen so that it is easy to manage the sorting and processing of the rendering commands . for example , the rendering commands may be sorted based on whether the polygon falls in the top half or the bottom half of the screen . once the rendering commands are sorted , the gpu may draw half of the screen while the display controller reads and displays the other half of the screen . presorting triangles to sub - frame level and restricting which of them gets drawn based on the current display activity is an advantageous feature compared to a typical 3d graphics system known in the art . fig3 shows a flow chart illustrating an exemplary method 300 for reducing the frame buffer size in a graphics system in accordance with the present invention . the method or process 300 may be implemented in the graphics system 100 shown in fig1 . as shown in fig3 , the method or process 300 may start with a step 302 in which a cpu generates two lists of gpu rendering commands ( or rendering commands ) in the main memory for the next frame to be drawn : a first rendering command list ( or a first list ) is for a first section of the screen , and a second rendering command list ( or a second list ) is for a second section of the screen . in a preferred embodiment , the first section may be the top half of the screen , and the second section may be the bottom half of the screen . alternatively , the first section may be the bottom half of the screen , and the second section may be the top half of the screen . in a further embodiment , the first section may be the top ⅓ of the screen , and the second section may be the rest of the screen . it is understood that the location of the section on the screen may be selected as contemplated by a person of ordinary skill in the art without departing from the scope and spirit of the present invention . in the step 302 , the cpu may also sort polygons such as triangles and the like of next frame based upon the location of the polygons on the screen . in a preferred embodiment , for each rendering command that the cpu generates , the cpu may check whether the polygon &# 39 ; stop and bottom vertices fall in the first section of the screen or the second section of the screen and may then add the command to a corresponding list . for example , if a triangle &# 39 ; stop and bottom vertices fall in the first section of the screen , the cpu may add the corresponding rendering command to the first list . if the polygon crosses the boundary between the first section and the second section of the screen , the cpu may add the corresponding rendering command to both the first list and the second list . in step 304 , a third rendering command list for the second section of the screen of the current frame may be provided . for example , the third list may be saved from the previous iteration ( see step 312 below ). in step 306 , when the display controller asserts the vertical synchronization ( vsync ) signal , the display controller may read the pixel data from the display region of the frame buffer to display the first section of the screen of the current frame , and , preferably simultaneously , gpu may fetch rendering commands from the third rendering command list and draw the pixels for the second section of the screen in the frame buffer to complete the full picture of the current frame . next , in step 308 , when the display controller completes displaying the first section of the screen of the current frame , the display controller may signal gpu to swap the display and drawing regions . then , in step 310 , the cpu may discard the third list and initiate the gpu to start processing the rendering commands in the first list to draw pixels for the first section of the next frame into the frame buffer , and , preferably simultaneously , the display controller may start reading pixel data for the second section of the screen for the current frame . in a preferred embodiment , the cpu needs to complete creating the first and second rendering command lists for the next frame before the steps 308 and 310 in order to be able to process all rendering commands properly . next , in step 312 , when the gpu completes drawing all polygons in the first list , the cpu may discard the first list and rename the second list as the third list , and the process 300 may then return to the step 302 . those of ordinary skill in the art will understand that renaming the second list as the third list does not physically have to take place . in other words , in a preferred embodiment , there are always three lists in fifo . the first list may be processed by the gpu and is thrown away as it is finished . then the gpu moves on to process the next list . the cpu may add more lists to the fifo as the fifo becomes ready . alternatively , in the step 312 , the process 300 may return to the step 302 for the cpu to start generating rendering command lists for the next frame without waiting for the gpu to complete drawing all polygons in the first list . in this case , preferably , the cpu may not corrupt the first list that gpu is working on and need save the third list that the gpu has not worked on yet . fig4 shows an exemplary sequence of steps involved in the process 300 shown in fig3 , where a first section of the screen is the top half of the screen and a second section of the screen is the bottom half of the screen . fig5 shows the content of an exemplary frame buffer 500 with a reduced memory size in accordance with an exemplary embodiment of the present invention . as shown , the frame buffer 500 may include a texture area 502 for storing texture , a display region 504 for displaying a current frame frame x , a drawing region 506 for drawing the next frame frame x + 1 , and a clut area 508 for storing a clut . in comparison with the frame buffer 202 shown in fig2 , the size of the frame buffer 400 is reduced to one half ( ½ ). it is understood that although the bottom half of the screen is used for displaying a current frame and the top half of the screen is used for drawing the next frame , they are not necessarily so . for example , the top half of the screen may be used to display the current frame and the bottom half of the screen may be used to draw the next frame . the section of the screen used to display the current frame and the section of the screen used to draw the next frame may be selected as contemplated by a person of ordinary skill in the art without departing from the scope and spirit of the present invention . it is to be noted that the foregoing described embodiments according to the present invention may be conveniently implemented using conventional general purpose digital computers programmed according to the teachings of the present specification , as will be apparent to those skilled in the computer art . appropriate software coding may readily be prepared by skilled programmers based on the teachings of the present disclosure , as will be apparent to those skilled in the software art . it is to be understood that the present invention may be conveniently implemented in forms of software package . such a software package may be a computer program product which employs a storage medium including stored computer code which is used to program a computer to perform the disclosed function and process of the present invention . the storage medium may include , but is not limited to , any type of conventional floppy disks , optical disks , cd - roms , magneto - optical disks , roms , rams , eproms , eeproms , magnetic or optical cards , or any other suitable media for storing electronic instructions . it is understood that the specific order or hierarchy of steps in the processes disclosed is an example of exemplary approaches . based upon design preferences , it is understood that the specific order or hierarchy of steps in the processes may be rearranged while remaining within the scope of the present invention . the accompanying method claims present elements of the various steps in a sample order , and are not meant to be limited to the specific order or hierarchy presented . it is believed that the present invention and many of its attendant advantages will be understood by the foregoing description . it is also believed that it will be apparent that various changes may be made in the form , construction and arrangement of the components thereof without departing from the scope and spirit of the invention or without sacrificing all of its material advantages . the form herein before described being merely an explanatory embodiment thereof , it is the intention of the following claims to encompass and include such changes .