with reference to fig1 the device of the invention comprises essentially a logic section and an analogic section . the logic section comprises a programmable logic circuit 3 , apt to function as a state machine capable of performing certain logic processing in function of logic signals applied to a plurality of logic inputs thereof and of delivering output logic signals through a number of logic outputs thereof and of driving a digital / analog converter circuit 4 ( dac ) in order to generate a resulting analog output signal . the analog section of the device of the invention comprises at least a comparator ( e . g . a zero - crossing detector ) 2 , and preferably as in the case shown , also at least an analog output buffer 1 , as well as a plurality of integrated analog switches s1 , s2 , s3 and s4 . these analog switches are also driven by the programmable state machine and permit to select the path of the analog signals : the s1 switch enabling the output of the analog signal delivered by the dac through the output analog buffer 1 ( which may be also preferably enableable by the same state machine ) and an analog output pin out ; the switches s2 and s3 permitting to feed the same analog signal produced by the dac and / or an external analog signal applied to an analog input pin in1 , to a first input of the comparator circuit 2 ; the switch s4 permitting to feed a second external analog signal applied to a second analog input pin in2 to the second input of the comparator circuit 2 . the output signal of the comparator circuit 2 is directly fed to one of the inputs of the programmable state machine . therefore the integrated mixed device of the invention possesses a plurality of logic inputs , a plurality of logic outputs and a plurality of analog inputs and it may also be provided preferably ( as in the example shown in the figures ) with at least an analog signal output pin . as it will be evident to a skilled technician , also the pin or the pins for the output of analog signals from the integrated device may be easily configured as bidirectional input / output ( i / o ) analog pins ( in the same way as bidirectional logic input / output pins ) by providing the respective output analog buffer of these pins with enabling / disabling means and with an integrated &# 34 ; by pass &# 34 ; analog switch , all driven by the same state machine of the integrated device . in this way a single physical pin of the integrated device may function either as an analog output or as an analog input pin . by means of the comparator circuit 2 the analog section of the integrated circuit directly acts upon the programmable state machine . in order to clarify better the interaction among the various blocks , a simple application of the invention in reference to a system for keeping constant the temperature of a certain enclosure by switching on and off a heating resistor , will serve as an example . the heating resistor could be advantageously powerable with two distinct supply voltages by means of two electrically controlled switches according to whether the temperature is lower or higher than a certain lower internal value ; utilizing the high voltage supply for quickly approaching a value close to the set desired temperature and the low voltage supply for reaching and maintaining the set temperature . for such a relatively common application the programmable integrated circuit of the invention may be easily programmed in order to implement a state machine capable of performing the following operations : ( a ) loading into an input register of the dac a digital data defining a certain interval of temperatures grossly lower than the desired temperature ; ( b ) closing the switch s2 while maintaining open the switch s3 in order to load the capacitance of the respective input of the comparator 2 to the desired level for a time sufficient for a sampling procedure ; ( c ) closing the switch s4 for a sufficient sampling time , in order to load the capacitance of the other input of the comparator 2 to a level corresponding to the analog signal coming from a temperature sensor and fed to the pin in2 of the integrated device ; ( d ) closing through a relative output pin the high voltage supply switch of the heating resistor and repeating the sequence from step ( a ) if the temperature is comprised in said interval of temperatures or viceversa , if the temperature is outside said interval of temperatures , performing the following alternative sequence of steps : ( a &# 39 ;) charging a digital data corresponding to the desired temperature in an input register of the dac ; ( b &# 39 ;) closing the switch s2 while keeping open the switch s3 in order to load the capacitance of the respective input of the comparator 2 to the desired level for a sufficient sampling time ; ( c &# 39 ;) closing the switch s4 for a sufficient sampling time in order to load the capacitance of the other input of the comparator 2 to a level corresponding to the analog signal coming from the temperature sensor and which is fed to the pin in2 of the integrated device ; ( d &# 39 ;) closing , through a relative output pin , the low voltage supply switch of the heating resistor if the temperature is below the desired value and restarting again from the step ( a ) or viceversa , if the temperature is equal to or higher than the desired value , none of the supply switches will be closed and the state machine will repeat again the sequence starting from step ( a ). of course at every clock &# 39 ; s pulse the state machine will step forward from a state to the successive state , thus performing the desired control function . naturally , not only in the case of a relatively simple application such as the one described above , the normally vast processing capabilities of the programmable state machine may be exploited for performing a number of other duties by implementing other logic functions depending or not from the relative status of the output of the comparator 2 , by utilizing the available logic inputs and outputs . the control performed in the simple example described above , is a discrete type of control , however it is also possible to use the analog output pin ( out ) of the dac for generating an analog control driving signal . in this case it will be obvioulsy necessary an analog type power interface between the device and the controlled heating resistance . as schematically shown in fig2 the logic section of the programmable integrated device of the invention , and in particular the section which more properly is usable for implementing a true programmable state machine , may have preferably a typical structure of a programmable logic device ( pld ). an array 5 of programmable cells ( eprom or flash or eeprom ) constitutes a programmab1e &# 34 ; and - level &# 34 ; the logic function of which is indicated by the graphic symbol , recognizable as a logic and gate , depicted on each of the outputs of the and - level shown in the figure . in the shown example , four outputs or product terms of the programmable and - level respectively drive the four integrated analog switches s1 , s2 , s3 and s4 of the analog section of the integrated device of the invention ( which is evidenced in fig2 by showing the wired connections with a thick line ). as typical of a large number of common pld devices , cascaded from the programmable and - level there is a fixed or wired &# 34 ; or - level &# 34 ; 6 , the logic function of which is schematically shown , in relation to two typical output signals of the and - level , i . e . for a common clock signal and for a digital signal or bit being fed to a respective input register of the digital / analog converter dac , by the logic symbol corresponding to the function of a logic or - gate . the dac converter is in fact driven by the programmable state machine through a series of input registers ( flip - flop ), one of which ( r 1 ) is depicted within the block 7 . a preset conversion reference voltage vref is selectively fed to the dac converter . the management of the input and output logic data to and from the state machine ( i . e . the programmable pld section of the device ) may take place through a plurality of input and output pins , suitably buffered , and / or by means of a plurality of bidirectional input / output ( i / o ) pins , each being provided with an enableable output buffer 8 in order to force an output logic signal . in particular , bidirectional i / o pins are managed by means of an equal number of input / output circuit , generally depicted in fig2 by the block 9 . the output logic signals of the and - level which are directed to as many bidirectional i / o pins are necessarily fed to the respective input / output circuits by means of flip - flop registers or latches , which are generally indicated by the block 10 in fig2 . each input / output circuit is commonly formed by an input selection block , followed by a block of registers and finally by an output selection block , the functions of which may be selected ( i . e . programmable as the cell array forming the and - level ). these i / o circuits or blocks are amply described in literature and are well known to the skilled technician and therefore a reiterated description thereof is not necessary . notably these programmable i / o blocks enormously increase the possibility of exploiting the programmable resources of the pld section . the i / o blocks represent additional &# 34 ; static &# 34 ; programmable resources which permit to easily implement &# 34 ; feedback &# 34 ; paths of signals coming from and directed to the programmable cell array . furthermore the system is provided with a clock signal generator 11 and preferably also with a programmable divider circuit 12 . the required select signals for the various i / o blocks , as well as for the programmable divider 12 and for the input registers of the dac converter are produced by means of a programmable static selection circuit 13 . this circuit is formed in practice by a plurality of identical circuits each capable of taking one or the other of two different static operating conditions in function of the status of an eprom or flash or eeprom cell present in the circuit . the prior italian patent application no . 22219 a / 88filed on oct . 6 , 1988 , ( corresponding to u . s . patent application ser . no . 411 , 661 filed on sept . 25 , 1989 ) by the present applicant , describes a particularly advantageous type of such static selection circuits employing a pair of series connected programmable cells wherein one of the cell is conducting and the other nonconducting . the description of such a static selection circuit is here incorporated by express reference to said prior patent application . as it will be evident to the skilled technician , the programmable , mixed logic and analogic device of the present invention may also be &# 34 ; duplicated &# 34 ;, in the sense of being provided with two or more dac and / or two or more comparators ( zero - crossing detectors ), whereby each one of them may receive analog signals coming from distinct analog input pins which may be suitably switched by the integrated programmable logic section of the device . the programmable logic section of the integrated device may also have a substantially different architecture from the normal architecture of a pld , such as the one described above with reference to the example depicted in fig2 . for example , the programmable logic section of the integrated device may contain a second array of programmable cells forming an or - level , which is also programmable , or this second array may be used as a multilevel logic ( outputs of product terms fedback to the inputs ).