while this invention is described in detail herein with specific reference to certain illustrated embodiments , there is no intent to be limited to those embodiments . on the contrary , the aim is to cover all modifications , alternatives and equivalents falling within the scope of the invention as defined by the claims . for a general understanding of the features of the present invention , reference is made to the drawings in which like references have been made throughout to designate identical elements . fig2 is a block diagram showing an iioc based architecture for an electronic reprographic system employing the chain interface controller of the present invention . it will become evident from the following discussion that the present invention is equally well suited for use in a wide variety of electronic systems and is not necessarily limited in its application to the particular system shown herein . turning initially to fig2 during operation of the system , a number of iiocs 20 are used to control various electrical , mechanical , optical and electromechanical devices within the electronic reprographic system . each iioc 20 controls a single device within the system . the iiocs 20 communicate with the host microprocessor 15 through the controller 10 which multiplexes onto a five wire input / output bus 18 . each input / output bus 18 consists of five wires and is capable of communicating signals to and from up to 32 iiocs . other configurations accommodating more or less than 32 iiocs are also possible , depending on the data clock interval and required system response time . each input / output bus 18 and its associated iiocs 20 make up a chain . each chain is linked back to the microprocessor 15 via its own dedicated chain interface controller 30 . therefore , there is a one - to - one correspondence between the number of chains and the number of chain interface controllers . the chain interface controllers are formed in a single chip configuration using field programmable gate array ( fpga ) techniques . currently , each fpga is capable of supporting up to four chain interface controllers . in a preferred embodiment , each fpga supports three individual chain interface controllers . for ease of description and understanding , the general operation of the chain interface controller will be described with reference to only one chain of iiocs and one chain interface controller , with the understanding that multiple chain interface controllers may be implemented in a single fpga 50 . signals indicating the current state of each iioc 20 in a chain are communicated to the host microprocessor 15 via the chain interface controller 30 dedicated to that particular chain . the input chain of data is subjected to various environmental conditions that may affect the signal on the bus 18 and , therefore , the accuracy of the data read by the host microprocessor 15 . every input that is read by the host microprocessor 15 is subjected to two types of noise . the first type of noise consists of random voltage spikes that are coupled onto the harness ( i . e ., bus 18 ) that carries the input signal to the processor board 10 . this can cause erroneous readings of the input by the host microprocessor 15 , such as , for example , indication of an open switch when in fact the switch is closed . the second type of noise is called &# 34 ; bounce &# 34 ;. bounce is caused by the mechanical action of a switch . when a switch is activated , i . e ., opened or closed , the host microprocessor 15 may see multiple &# 34 ; ons &# 34 ; and &# 34 ; offs &# 34 ; until the mechanical action has settled . ideally , the host microprocessor 15 only wants to know when the switch has changed state and has settled . in order to more accurately assess the information on the individual chains and filter out undesired noise , the chain interface controllers 30 employ a sophisticated , yet simple architecture to process the incoming signals . with reference to fig7 the bus configuration , as described above , consists of five wires , one wire each for serial input data ( sid ), serial output data ( sod ), clock , power and ground / return . each iioc 20 responds to a particular edge of the data clock to which it has been programmed . the sid wire carries output data as a serial stream to the iiocs 20 while the sod wire carries input data as a serial stream to the controller 30 . with reference to fig3 showing a block diagram representative of the chain interface controller 30 , the sod lines are connected to the oversampling circuit 35 of the chain interface controller . the oversampling circuit 35 filters out random noise , such as , for example , voltage spikes , which have coupled onto the serial output data signal . the input data is sampled ( i . e ., read by the controller ) multiple times during its data clock period at predetermined intervals . this is called oversampling . in the oversampling scheme of the present invention , each chain of input data is sampled on a bit - by - bit basis three times during a data clock period of the chain of data . each sample is taken , for example , at a 1 μs interval from the immediately preceding sample . the oversampling circuit outputs a binary value for each bit that is representative of a majority of the three samples ( i . e ., at least two of the three samples ) taken during the data clock period . oversampling in this manner filters out noise associated with random voltage spikes coupled to the input lines . a diagram showing the logic circuitry of the oversampling circuit of the present invention is shown in fig4 . with continued reference to fig3 the data output by the oversampling circuit 35 is then debounced by the filtering circuit 40 . the filtering circuit 40 debounces the input data on a bit - by - bit basis by storing two successive readings at the frame interval into the previous read registers 45 . the filtering circuit then compares the current input data to the previously read data and updates the debounced input register 75 if all three readings have not changed . for example , if three successive high signals have occurred , over three frame intervals , it would take three low signals to reflect a change in the corresponding bit of the debounced input register 75 . the filtering circuit used in the present invention , shown in fig5 is unique because there is only one filtering circuit per input data chain . the data clock increments a selector to the corresponding bit in the last read , previous read and debounced state registers so only one bit of each register is fed through the filtering circuit 40 . other filtering schemes condition inputs in parallel , which requires one filtering circuit per bit and , therefore , a very high gate count . the output from this circuit is stored on a bit basis in the debounced input register 75 ( i . e ., the filtered input register ). thus , extremely efficient filtering with a minimal gate count is achieved . referring again to fig3 the input change detector circuit 51 together with the interrupt logic circuit 65 is designed to generate an interrupt signal that is sent to the host microprocessor 15 when an input bit has changed state . the input change detector circuit 51 also sets the corresponding bit in the status register 60 . with a change of input state an interrupt will occur . a read of the status register 60 will give the interrupting chain . the data word read can then be written to the interrupt clear register and the proper interrupting chain will be cleared without missing and input changes . software must then be responsible for isolating the input that changed state by maintaining an input map and comparing it to the filtered input registers of the interrupting chain . once again the circuit is unique and a very low gate count is achieved by taking advantage of the additional multiplexing of the filtered input registers to accomplish input detection . without this additional multiplexing scheme , every input would need to be exclusively ored with its last filtered input reading , and all of them would need to be ored to clock a flip flop . therefore , the need for dedicated microprocessors having sophisticated polling schemes is eliminated . the input change detection circuitry is shown in fig6 . referring again to fig3 the host microprocessor 15 writes output data to the 16 - bit wide output registers 55 . the output register &# 39 ; s data is fed to the multiplexers 80 . the multiplexer 80 uses the data clock to shift out ( i . e ., serialize ) the data onto the sid wire . this parallel - to - serial conversion occurs every frame interval , allowing the outputs to be refreshed . output refresh is required because voltage spikes can induce noise on the sid wire that could change the state ( i . e ., on or off ) of an output . the refresh circuit resends the data from the output register 55 onto the sid wire every frame interval . the iioc responds to the value on the sid line at the appropriate data clock time and echoes the bit value to the output pin , thereby effectuating the desired output signal . the chain interface controller is also adapted to run in a variety of operational modes . the above description relates to the normal operational mode of the chain interface controller designated as the runmode . in the runmode , outputs will be refreshed every frame interval . and input sampling and addressing will also be performed as described above with additional filtering and oversampling . in addition to the runmode of operation , the chain interface controller has two &# 34 ; turnaround &# 34 ; modes of operation called internal turnaround and external turnaround . the turnaround modes of operation are generally used in a self - test or integration and test environment . the internal turnaround feature is added for diagnostic purposes . when in internal turnaround mode , the chain interface controller will internally connect the sid and sod signals , via an internal turnaround circuit 70 ( see fig3 ), thereby allowing monitoring and verification of operation of the oversampling and filtering circuits as well as all the input and output registers . the external turnaround feature is implemented via the iioc specification by writing a binary &# 34 ; 1 &# 34 ; to the external turnaround bit of the control register . this will initiate an iioc turnaround during the next framing pulse and successive framing pulses until the external turnaround bit is cleared . by putting the iioc in external turnaround mode , the host microprocessor can send test signals to the iioc and technicians are then able to check the settings and connections of the various components the iiocs control . referring now to fig4 a logic diagram of the oversampling circuit is shown . when data is received by the chain interface controller , it is sampled three times at successive 1 μs . intervals as described above . the chain of data is sampled on a bit - by - bit basis . as can be seen in fig5 sample one , sample two and sample three , are each gated to the logic circuitry and whenever the majority of the samples is the same ( i . e ., two out of three match ), the oversampled bit is sent to the filtering circuit to be debounced . the clocks of the chain interface controller are manipulated such that a 1 mhz clock pulse will provide successive sampling pulses at 1 μs . intervals . thus , the oversampling circuit will filter out any high frequency noise that may couple onto the sod lines . using karnaugh maps , a minimal gate count was achieved in implementing the oversampling circuit . referring to fig5 a logic diagram of the filtering , or debounce , circuit is shown . the oversampled data from the oversampling circuit described above is sent to the filtering circuit to debounce the signal . the signals are sampled on a frame basis , i . e ., at 500 μs intervals , the framing pulse of the system . the filter circuitry stores the filtered ( debounced ) input to the input register for reading by the host microprocessor when an input change is detected by the change detection circuitry . the filtering circuit shown achieves this debouncing function by comparing old debounced signals stored in the filtered input register with previous reads of the same bit in the previous read registers and the data currently being sampled . again , using karnaugh maps , the gate count was minimized . the input detect circuitry of the present invention is shown in fig6 . the input detect circuit employs an exclusive or scheme to generate an input change detected signal when the previous debounced state signal corresponding to a particular bit of the chain of data and the current debounced state signal corresponding to the same address are different . once this signal is generated , the interrupt signal generator outputs an interrupt signal to the microprocessor indicating that at least one bit of the input data stream has changed . therefore , by implementing this simple input detect circuit , input change detection is achieved with almost no significant additional gate count . moreover , input detection interrupt achieved in the above described manner allows drastic reduction in software overhead by eliminating the need for software to poll the debounced input register to detect when an input data bit has changed . while this invention has been described in conjunction with a specific embodiment thereof , it is evident that many alternatives , modifications and variations will be apparent to those skilled in the art . accordingly , the preferred embodiments of the invention , as set forth herein , are intended to be illustrative , not limiting . various changes may be made without departing from the spirit and scope of the invention as defined in the following claims .