various embodiments of the present invention will be described with reference to the accompanying drawings . it is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings , and the description of the same or similar parts and elements will be omitted or simplified . generally , and as is in the representation of the cross - sectional diagram , it will be appreciated that the various drawings are not drawn to scale from one figure to another nor inside a given figure , and in particular that the circuit diagrams are arbitrarily drawn for facilitating the reading of the drawings . in the following descriptions , numerous specific details are set forth such as specific material layers , etc . to provide a thorough understanding of the present invention . however , it will be obvious to those skilled in the art that the present invention may be practiced without such specific details . in other instances , the material layers well - known have been shown in the cross - sectional diagrams form in order to not obscure the present invention with unnecessary detail . drawings are schematic , not actual , and may be inconsistent in between in scale , ratio , etc . the embodiments shown below exemplify a semiconductor device that are used to implement the technical ideas according to the present invention , and do not limit the technical ideas according to the present invention to those that appear below . these technical ideas , according to the present invention , may receive a variety of modifications that fall within the claims . the embodiment shown in the following exemplifies the device and method for materializing the technical idea of this invention , and this embodiment of the invention does not specify assignment of each component parts , etc . as the following . this embodiment of the invention can add various change in scope of claims . a schematic plane pattern configuration of a semiconductor device according to a first embodiment of the present invention is expressed as shown in fig1 . a schematic section structure explaining one process of a fabrication method of the semiconductor device according to the first embodiment is expressed as shown in fig2 and fig3 . the semiconductor device according to the first embodiment includes a semiconductor substrate 4 a , a field effect transistor 4 , and a hollow protective film 5 , as shown in fig1 to fig3 . the field effect transistor 4 includes a gate electrode 1 , a drain electrode 2 , and a source electrode 3 which are formed on the semiconductor substrate . the hollow protective film 5 is provided on the semiconductor substrate 4 a so that an inner surface may bond to an upper surface of the drain electrode 2 and the source electrode 3 of the field effect transistor 4 . the hollow protective film 5 includes a first cap layer 7 contacting the drain electrode 2 and the source electrode 3 , and a second cap layer 10 placed on the first cap layer 7 . the hollow protective film 5 further includes a third cap layer 11 placed on the second cap layer 10 . the first cap layer 7 and the second cap layer 10 can be composed by an insulating film , for example , can be composed by a silicon dioxide film ( sio 2 film ). the third cap layer 11 can be composed by an insulating film , for example , can be composed by a silicon nitride film ( sin film ). as shown in fig1 and fig3 , the field effect transistor 4 includes the hollow protective film 5 , and the field effect transistor 4 including the gate electrode 1 , the drain electrode 2 , and the source electrode 3 is formed on the semiconductor substrate 4 a . the hollow protective film 5 is provided on the semiconductor substrate 4 a so that the polar zone composed of the gate electrode 1 , the drain electrode 2 , and the source electrode 3 of this field effect transistor 4 may be covered . here , the hollow protective film 5 is provided so that the inner surface may bond to the upper surface of the drain electrode 2 and the source electrode 3 . the fabrication method of the semiconductor device according to the first embodiment includes : the step of forming the gate electrode 1 , the drain electrode 2 , and the source electrode 3 on the semiconductor substrate 4 a , thereby forming the field effect transistor 4 ; and the step of forming the hollow protective film 5 on the semiconductor substrate 4 a so that the inner surface may bond to the upper surface of one or both of the drain electrode 2 , and the source electrode 3 of the field effect transistor 4 , as shown in fig1 to fig3 . moreover , the step of forming the hollow protective film 5 includes : the step of forming the sacrifice layer 6 on the gate electrode 1 and the semiconductor substrate 4 a except for the drain electrode 2 and the source electrode 3 ; the step of forming the first cap layer 7 contacting the upper surface of one or both of the drain electrode 2 and the source electrode 3 ; the step of forming an opening 12 in the edge of the first cap layer 7 ; the step of sending oxygen plasma through the opening 12 , and gasifying and removing the sacrifice layer 6 by an oxygen plasma asher , and forming the hollow unit 9 ; and the step of forming the second cap layer 10 on the first cap layer 7 , and sealing the opening 12 . the step of forming the hollow protective film 5 may further include the step of forming the third cap layer 11 on the second cap layer 10 . next , the fabrication method of the semiconductor device according to the first embodiment will be explained using fig1 to fig3 . ( a ) first of all , form the field effect transistor 4 composed of the gate electrode 1 , the drain electrode 2 , the source electrode 3 , etc . on the semiconductor substrate 4 a . ( b ) next , form the sacrifice layer 6 composed of , for example , photosensitive polyimide on the part except for the drain electrode 2 and the source electrode 3 , i . e ., the active part of the gate electrode 1 , and the semiconductor substrate 4 a . that is , after applying the sacrifice layer 6 completely on the semiconductor substrate 4 a , it patterns toward this sacrifice layer 6 so that the active part of the gate electrode 1 except for the drain electrode 2 and the source electrode 3 may be covered . in addition , not only the photosensitive polyimide but other photosensitive heat - resistant materials may be sufficient as the sacrifice layer 6 . moreover , if heat treatment is not used for future steps , photosensitive materials , such as photoresist , may be sufficient as the sacrifice layer 6 . ( c ) next , form the first cap layer 7 composed of an insulating film so that the sacrifice layer 6 may be covered on the upper part of the sacrifice layer 6 . this first cap layer 7 can be formed , for example by depositing a silicon dioxide film by cvd ( d ) next , as shown in fig2 , further form the photoresist layer 8 composed of photosensitive materials on the upper part of the first cap layer 7 . ( e ) next , as shown in fig2 , perform a patterning process so that the edge of the first cap layer 7 may be exposed by the photoresist layer 8 . via this photoresist layer 8 , the first cap layer 7 is etched by rie ( reactive ion etching ) method , and the edge of the first cap layer 7 is exposed . ( f ) next , form the opening ( extracting hole ), not illustrated , on the edge of the first cap layer 7 after removing the photoresist layer 8 . ( g ) next , send the oxygen plasma through the opening , and gasify and remove the sacrifice layer 6 by an oxygen plasma asher , thereby form the hollow part ( cavity part ) 9 . although fig3 is a sectional view of the field effect transistor showing the state where this sacrifice layer 6 is removed and the hollow part 9 is formed , the sacrifice layer 6 is removed from the active part of the gate electrode 1 , and the hollow part 9 is formed , as shown in the same figure . ( h ) next , as the second cap layer 10 , deposit , for example , a silicon dioxide film as the insulating film by a spattering process , and secure the airtightness of the hollow part 9 . ( i ) next , as shown in fig3 , deposit a nitride film as the third cap layer 11 by using , for example , plasma cvd , on the second cap layer 10 . by the third cap layer 11 , the airtightness and moisture resistance are securable . thus , the hollow protective film 5 which laminates the first cap layer 7 , second cap layer 10 , and third cap layer 11 is formed . the first cap layer 7 that is an innermost ( lowest ) layer of this hollow protective film 5 contacts the upper surface of the drain electrode 2 and the source electrode 3 . for this reason , since the drain electrode 2 and the source electrode 3 may support the hollow protective film 5 from that inner side , the mechanical intensity of the hollow protective film 5 is reinforced . in addition , other insulating films which are excellent in the airtightness and the moisture resistance may be sufficient as the third cap layer 11 . moreover , if the second cap layer 10 is provided with sufficient airtightness and moisture resistance , there may not be the third cap layer 11 . since the hollow protective film 5 formed in this way has composition which the electrodes except active gate electrode 1 electrically , i . e ., the drain electrode 2 , and the source electrodes 3 , supports as a support unit , the mechanical strength of the hollow protective film 5 does not become weaker even if the volume of the hollow sections becomes large , and the bad influence of electrical characteristics is also eliminated . a detailed schematic plane pattern configuration of the semiconductor device according to the first embodiment is expressed as shown in fig4 . as clearly from fig4 , the opening 12 , which is not shown in fig2 to fig3 , is shown in the periphery of the hollow protective film 5 . since this opening 12 is formed toward the first cap layer 7 on the fabricating process and is sealed by the subsequent fabricating process of the second cap layer 10 , this opening 12 is shown by the dotted line . as shown in fig5 , a detailed schematic plane pattern configuration of a semiconductor device according to a modified example 1 of the first embodiment is an example by which a plurality of openings 12 are placed at the periphery of the hollow protective film 5 , and other configurations are the same as that of the first embodiment . by placing a plurality of openings 12 at the periphery of the hollow protective film 5 , oxygen plasma is sendable through the opening 12 , the sacrifice layer 6 can be gasified and removed by an oxygen plasma asher , and the processing time of the step of forming the hollow part 9 can be shortened . as shown in fig6 , a detailed schematic plane pattern configuration of a semiconductor device according to a modified example 2 of the first embodiment is an example by which the openings 12 are placed at rectangle stripe shape at the periphery of the hollow protective film 5 , and other configurations are the same as that of the first embodiment . by placing the openings 12 to rectangle stripe shape at the periphery of the hollow protective film 5 , oxygen plasma is sendable through the openings 12 , the sacrifice layer 6 can be gasified and removed by an oxygen plasma asher , and the processing time of the step of forming the hollow part 9 can be further shortened . the schematic section structure of the semiconductor device according to the modified examples 2 to 3 of the first embodiment includes a semiconductor substrate 4 a , a field effect transistor 4 , and a hollow protective film 5 , as shown in fig7 . the field effect transistor 4 has a gate electrode 1 , a drain electrode 2 , and a source electrode 3 which are formed on the semiconductor substrate 4 a . the hollow protective film 5 is provided on the semiconductor substrate 4 a so that an inner surface may bond to the upper surface of the drain electrode 2 and the source electrode 3 of the field effect transistor 4 . the hollow protective film 5 includes a first cap layer 7 contacting the drain electrode 2 and the source electrode 3 , and a second cap layer 10 placed on the first cap layer 7 . the hollow protective film 5 further includes a third cap layer 11 placed on the second cap layer 10 . the opening 12 is formed in the first cap layer 7 in the periphery of the hollow protective film 5 , the sacrifice layer 6 is gasified and removed by an oxygen plasma asher through this opening 12 , and the opening 12 is sealed by the second cap layer 10 in the sealed part 12 a after forming the hollow part 9 . since the hollow protective film 5 is supported by the drain electrode 2 and the source electrode 3 as a support unit according to the first embodiment , even if the volume of hollow sections becomes large , the mechanical strength of the hollow protective film 5 does not become weaker . moreover , reliable semiconductor device can be obtained without receiving the electrical influence from others in the process in which the hollow protective film 5 is formed , since the electrodes 2 except active gate electrode 1 electrically , i . e ., the drain electrode , and the source electrodes 3 are applied as the support unit . a schematic plane pattern configuration of a semiconductor device according to a second embodiment of the present invention is similarly expressed as fig1 or fig4 to fig6 . a schematic section structure of the semiconductor device according to the second embodiment is expressed as shown in fig8 . the semiconductor device according to the second embodiment includes a semiconductor substrate 4 a , a field effect transistor 4 , and a hollow protective film 5 , as shown in fig4 to fig6 , and fig8 . the field effect transistor 4 has a gate electrode 1 , a drain electrode 2 , and a source electrode 3 which are formed on the semiconductor substrate 4 a . the hollow protective film 5 is provided on the semiconductor substrate 4 a so that an inner surface may bond to the upper surface of the source electrode 3 of the field effect transistor 4 . the hollow protective film 5 includes a first cap layer 7 contacting the source electrode 3 , and a second cap layer 10 placed on the first cap layer 7 . the hollow protective film 5 further includes a third cap layer 11 placed on the second cap layer 10 . the first cap layer 7 and the second cap layer 10 can compose an insulating film , for example , can be composed by a silicon dioxide film . the third cap layer 11 can compose an insulating film , for example , can be composed by a silicon nitride film . the opening 12 is formed in the first cap layer 7 in the periphery of the hollow protective film 5 , the sacrifice layer 6 is gasified and removed by an oxygen plasma asher through this opening 12 , and the opening 12 is sealed by the second cap layer 10 in the sealed part 12 a after forming the hollow part 9 . since the hollow protective film 5 is supported by the source electrode 3 as a support unit according to the second embodiment , even if the volume of hollow sections becomes large , the mechanical strength of the hollow protective film 5 does not become weaker . moreover , a reliable semiconductor device can be obtained without receiving the electrical influence from others in the process in which the hollow protective film 5 is formed , since the electrodes 2 except active gate electrode 1 electrically , i . e ., the source electrodes 3 is applied as the support unit . a detailed schematic section structure of a semiconductor device according to a modified example 1 of the second embodiment is not a configuration whose the first cap layer 7 contacts all the source electrodes 3 but a configuration placed so that the source electrode 3 placed at stripe shape may be contacted by every other one for example , as shown in fig9 . the opening 12 is formed in the first cap layer 7 in the periphery of the hollow protective film 5 , the sacrifice layer 6 is gasified and removed by an oxygen plasma asher through this opening 12 , and the opening 12 is sealed by the second cap layer 10 in the sealed part 12 a after forming the hollow part 9 . the first cap layer 7 may be placed so that the source electrode 3 placed at stripe shape may be contacted by every two for example . or the first cap layer 7 may be provided with the configuration which contacts the source electrode 3 at random . since the hollow protective film 5 is supported by the source electrode 3 as a support unit according to the modified example 1 of the second embodiment , even if the volume of hollow sections becomes large , the mechanical strength of the hollow protective film 5 does not become weaker . moreover , a reliable semiconductor device can be obtained without receiving the electrical influence from others in the process in which the hollow protective film 5 is formed , since the electrodes 2 except active gate electrode 1 electrically , i . e ., the source electrodes 3 are applied as the support unit . a detailed schematic section structure of a semiconductor device according to a modified example 2 of the second embodiment has the characteristic at the point that the first cap layer 70 is composed of a metal layer , as shown in fig1 . aluminum can compose the first cap layer 70 , for example . as shown in fig1 , the opening 70 is formed in the first cap layer 7 in the periphery of the hollow protective film 5 , the sacrifice layer 6 is gasified and removed by an oxygen plasma asher through this opening 12 , and the opening 12 is sealed by the second cap layer 10 in the sealed part 12 a after forming the hollow part 9 . according to the modified example 2 of the second embodiment , since the first cap layer 70 formed by a metal layer is connected to the source electrode 3 , a shielding effect is obtained and a stable semiconductor device is provided electrically by applying potential of the first cap layer 70 into earth potentials . moreover , since the hollow protective film 5 is supported by the source electrode 3 as a support unit according to the modified example 2 of the second embodiment , even if the volume of hollow sections becomes large , the mechanical strength of the hollow protective film 5 does not become weaker . moreover , a reliable semiconductor device can be obtained without receiving the electrical influence from others in the process in which the hollow protective film 5 is formed , since the electrodes 2 except active gate electrode 1 electrically , i . e ., the source electrodes 3 are applied as the support unit . as shown in fig1 , a detailed schematic section structure of a semiconductor device according to a modified example 3 of the second embodiment has the characteristic in the point that the first cap layer 70 is composed of a metal layer , and the source electrode 3 placed at stripe shape may be contacted every other one for example , instead of the configuration which contacts all the source electrodes 3 . as shown in fig1 , the opening 70 is formed in the first cap layer 7 in the periphery of the hollow protective film 5 , the sacrifice layer 6 is gasified and removed by an oxygen plasma asher through this opening 12 , and the opening 12 is sealed by the second cap layer 10 in the sealed part 12 a after forming the hollow part 9 . the first cap layer 70 may be placed so that the source electrode 3 placed at stripe shape may be contacted by every two for example . or the first cap layer 70 may be provided with the configuration which contacts the source electrode 3 at random . according to the modified example 3 of the second embodiment , since the first cap layer 70 formed by a metal layer is connected to the source electrode 3 , a shielding effect is obtained and a stable semiconductor device is provided electrically by applying potential of the first cap layer 70 into earth potentials . moreover , since the hollow protective film 5 is supported by the source electrode 3 as a support unit according to the modified example 3 of the second embodiment , even if the volume of hollow sections becomes large , the mechanical strength of the hollow protective film 5 does not become weaker . moreover , a reliable semiconductor device can be obtained without receiving the electrical influence from others in the process in which the hollow protective film 5 is formed , since the electrodes 2 except active gate electrode 1 electrically , i . e ., the source electrodes 3 is applied as the support unit . a schematic plane pattern configuration of a semiconductor device according to a third embodiment of the present invention is similarly expressed as fig1 or fig4 to fig6 . a schematic section structure of the semiconductor device according to the third embodiment is expressed as shown in fig1 . the semiconductor device according to the third embodiment includes a semiconductor substrate 4 a , a field effect transistor 4 , and a hollow protective film 5 , as shown in fig4 to fig6 , and fig1 . the field effect transistor 4 has a gate electrode 1 , a drain electrode 2 , and a source electrode 3 which are formed on the semiconductor substrate 4 a . the hollow protective film 5 is provided on the semiconductor substrate 4 a so that an inner surface may bond to the upper surface of the drain electrode 2 of the field effect transistor 4 . the hollow protective film 5 includes a first cap layer 7 contacting the drain electrode 2 , and a second cap layer 10 placed on the first cap layer 7 . the hollow protective film 5 further includes a third cap layer 11 placed on the second cap layer 10 . the first cap layer 7 and the second cap layer 10 can compose an insulating film , for example , can be composed by a silicon dioxide film . the third cap layer 11 can compose an insulating film , for example , can be composed by a silicon nitride film . the opening 12 is formed in the first cap layer 7 in the periphery of the hollow protective film 5 , the sacrifice layer 6 is gasified and removed by an oxygen plasma asher through this opening 12 , and the opening 12 is sealed by the second cap layer 10 in the sealed part 12 a after forming the hollow part 9 . the first cap layer 7 may be placed so that the drain electrode 2 placed at stripe shape may be contacted by every two for example . or the first cap layer 7 may be provided with the configuration which contacts the drain electrode 2 at random . since the hollow protective film 5 is supported by the drain electrode 2 as a support unit according to the third embodiment , even if the volume of hollow sections becomes large , the mechanical strength of the hollow protective film 5 does not become weaker . moreover , a reliable semiconductor device can be obtained without receiving the electrical influence from others in the process in which the hollow protective film 5 is formed , since the electrodes 2 except active gate electrode 1 electrically , i . e ., the drain electrode is applied as the support unit . while the present invention is described in accordance with the aforementioned first through third embodiments , it should not be understood that the description and drawings that configure part of this disclosure are to limit the present invention . this disclosure makes clear a variety of alternative embodiments , working examples , and operational techniques for those skilled in the art . such being the case , the present invention covers a variety of embodiments , whether described or not . according to the present invention , a semiconductor device has a wide range of application fields , such as an internally matched power amplifier , a power mmic ( monolithic microwave integrated circuit ), a microwave power amplifier , a millimeter - wave power amplifier , and a high frequency mems ( micro electro mechanical systems ) device .