with reference to fig1 , a block cipher device 100 is non - recursive and may include an input unit ( not shown ), nine encryption stages 1 – 8 and 12 , an output unit ( not shown ), and a key scheduling unit 9 . the input unit and output unit assemble and buffer input and output data to and from the block cipher device 100 . the structure of the input unit and output unit generally depends on an application ( e . g ., serial or parallel ). the input unit and output unit are not unique to the block cipher device 100 . the block cipher device receives three input variables , x , z 1 , and z 9 and produces an output variable , y . x is the primary traffic input to the block cipher device 100 and y is the primary traffic output . z 1 and z 9 may be externally applied variables . z 9 may be a secret “ key ” variable which is input to the block cipher device 100 via a secure channel ( e . g ., a courier with sealed cover ) prior to encryption or decryption . z 1 ( or “ customer algorithm modification ” variable ) and subunits of z 1 ( i . e ., z 2 , z 3 , z 5 and z 6 ) are operated on in the first , second , third , fourth and fifth units 1 , 2 , 3 , 4 and 5 of the block cipher device 100 . the output y of the block cipher device 100 is a unique function of the primary traffic x , the key variable z 9 and the variable z 1 . with continued reference to fig1 , each encryption stage has at least a 64 - bit i / o space . encryption stages 1 , 5 , 6 and 8 consist of modular arithmetic logic . stages 1 , 5 and 8 perform modular additions and stage 6 performs a modular cubing operation . each stage employs a different modulus . stage 7 is a non - invertable “ mid transform ”. in addition , stages 1 , 5 , 6 , 7 and 8 can not be segmented into a set of lower level operations . these design features make the block cipher device secure against popular “ cryptanalysis ” or cracking techniques . stages 2 and 4 are “ nibble swapping ” blocks . these blocks allow the structure of the algorithm to be changed based on an externally applied input , z 1 . stage 3 is a customizable substitution / expansion block . this allows a custom operation with inputs w 2 and z 3 and output w 3 to be inserted into the block cipher device structure . this allows unique algorithm variants to be implemented . the structure of block 3 is not arbitrary and must meet the requirements of secure cipher design . custom substitution / expansion block designs are disclosed only to the intended end user . an input unit 10 assembles and buffers input data to the block cipher device 100 and the output unit 11 assembles and buffers output data from the block cipher device 100 . encryption stage 12 , like stages 1 , 5 and 8 , performs a modular addition operation . key scheduling unit 9 accepts an externally applied input variable , z 9 , and deterministically generates three pseudo random bit patterns , z 4 , z 7 , and z 8 . these patterns are used as operands for blocks 12 , 5 and 8 respectively . to facilitate the description , fig2 , 3 , 4 and 5 illustrate 64 bit block implementations . 64 bit blocks are used only as an example . generally , in 64 bit block implementations , each unit includes at least a 64 bit input / output space . a block cipher device of the present invention having any input or output size can be designed by appropriately scaling the size of block cipher device operations . with reference to fig2 , the first unit 1 performs a modulo 2 addition ( exclusive - or ) on primary traffic input x with variable z 1 resulting in first unit 1 output w 1 . the second unit 2 performs a nibble swap operation . the second unit 2 segments w 1 into 8 pairs of nibbles ; each nibble holding 4 bits . the second unit 2 transposes each segment based on z 2 ( e . g ., bits 0 – 7 of z 1 ) resulting in second unit 2 output w 2 . for example , when the value of bit “ 0 ” in z 2 is equal to binary “ 1 ” then the order of the nibbles pair “ 0 ” will be transposed . likewise , if bit “ 0 ” in z 2 is equal to binary “ 0 ” then the order is left unchanged . the order of each nibble pair will be determined by the value of the corresponding bit in z 2 . the value of bit 0 controls the order of nibble pair 0 , the value of bit 1 the order of nibble pair 1 continuing through to bit 7 which controls the order of nibble pair 7 . the third unit 3 is a custom unit providing a custom substitution and expansion operation . the custom operation with inputs w 2 and z 3 and output w 3 may be inserted into the block cipher device 100 in the form of a look - up table . z 3 may be bits 24 through 31 of z 1 . providing a custom unit allows unique system variants to be designed and provided while meeting the requirements of secure cipher design . for example , the customized substitution or expansion operation of a look - up table is only disclosed to intended end users . the fourth unit 4 may be another nibble swap operation where w 8 is segmented into 16 nibbles . z 5 ( for example , bits 24 through 31 of z 1 ) controls the re - ordering of w 8 in a slightly different manner than explained for the second unit 2 . for example , when the value of bit “ 8 ” in z 5 is equal to a binary “ 0 ” then the first nibble in the pair will be written to the first position in the high order segment of w 4 and the second nibble will be written to the first position in the low order segment of w 4 . when the value of bit “ 8 ” in z 5 is equal to a binary “ 1 ” then the two nibbles will be transposed before being written to w 4 . as with the second unit 2 , the re - ordering of each nibble pair will be determined by a corresponding bit in z 5 . the fifth unit 5 performs a modulo addition operation . w 4 and z 7 are operands of the fifth unit 5 . w 4 is the output of the fourth unit 4 and z 7 is an output from the key scheduler unit 9 . the modulus q of the operation is determined using z 6 by the following relation : z 6 may be bits 33 through 64 of z 1 . the sixth unit 6 performs a modular cubing operation . in other words , w 5 is raised to the third power modulo p and the result is designated as w 6 . the modulus p is determined by the following relation : the variable x is chosen such that the greatest common denominator between the order of the operation “ 3 ” and ( p − 1 ) is equal to 1 . this is captures in the following equation : the seventh unit 7 performs a non - invertible operation such as an operation known as a mid transform . the input to the operation , w 6 , is 128 bits in length and the output of the operation , w 7 , is 64 bits in length . the mid transform simply maps bits 64 bits of the input to a 64 bit output . for example , the mid transform may map bits 30 through 93 of w 6 to bits 0 through 63 of w 7 . the rest of the bits in w 6 are discarded . the eighth unit 8 performs another modulo addition operation . w 7 and z 8 are operands of this unit . w 7 is an output from the seventh unit 7 and z 8 is an output from the key scheduler 9 . the modulus of the operation is chosen as 2 64 . the output of this stage is the output of the block cipher device and is designated as y 1 . although specific values are specified for moduli of the first , fifth , sixth , and eighth units 1 , 5 , 6 , and 8 , the objective of the block cipher device will be satisfied by a range of choices . it is required , however , that the constraint of equ . 3 be satisfied and that a unique modulus be used in each stage . the “ modulo ” units 1 , 5 , 6 , and 8 along with “ non - invertible ” unit 7 are not segmentable into a set of lower level operations . with reference to fig3 , the key scheduler unit 9 comprises a first function unit 13 , a second function unit 16 , a third function unit 15 , a fourth function unit 18 , a fifth function unit 22 , a first shift register 14 , a second shift register 17 , a first mod 2 add logic gate 19 , a second mod 2 add logic gate 20 , and a third mod 2 add logic gate . the key scheduling unit 9 processes key variable z 9 to produce variables z 4 , z 7 , and z 8 . these variables are used during encryption and decryption . z 10 and z 11 , are deterministic functions , h , of the higher and lower halves of key variable z 9 . z 10 and z 11 are the outputs of the third function unit 15 and fourth function unit 18 , respectively , and are input to shift register 14 and shift register 17 , respectively . each of these registers is shifted to the right one bit at a time until its contents have been completely recirculated . with each shift , the least significant bit in each register is mod 2 added to the output of its associated function unit , the first function unit 13 or the second function unit 16 . the result is moved into the most significant bit position of each register . when the contents of the first shift register 14 and the second shift register 17 have been completely processed , it is output as variables z 7 and z 13 , respectively . z 7 becomes one of three pseudo random outputs of the key scheduling unit 9 . z 13 is modulo 2 added to z 7 to produce pseudo random output z 4 . in addition , z 13 is input to fifth function unit 22 to produce variable pseudo random output z 8 . the first function unit 13 and the second function unit 16 are custom lookup tables . they map at least 6 one bit inputs to a single one bit output . each of the inputs to the first function unit 13 and the second function unit 16 is a “ tap ” connected to an individual bit position in the first shift register 14 and the second shift register 17 , respectively . the tap locations can be arbitrarily chosen with the following constraint . no tap can be connected to either the least significant or to the most significant bit positions on shift register 14 and shift register 17 . the structure of the first function unit 13 and the second function unit 16 are not arbitrary and must meet the requirements of secure cipher design . note that the first function unit 13 and the second function unit 16 can be independently specified . however , as described below , the first function unit 13 must be set equal to the second function if the block cipher 100 is to operate in a mode compatible with the prior art block cipher described in u . s . pat . no . 6 , 108 , 421 . the first function unit 13 and the second function unit 16 may be customized and disclosed only to the intended end user . the fifth function unit 22 performs a bit - wise mod 2 add without carry of the higher and lower order halves of z 13 to produce z 8 . the third function unit 15 and the fourth function unit 18 perform a bit - wise mod 2 add without carry of each of each half of key variable z 9 and a custom bit pattern of equal length , producing variables z 10 and z 11 . note that a third function unit 15 and the fourth function unit 18 can be independently specified . however , as described below the third function unit 15 must be set equal to the fourth function unit 18 , if the block cipher 100 is to operate in a mode compatible with the prior art block cipher described in u . s . pat . no . 6 , 108 , 421 . the value of the custom bit pattern is disclosed only to the intended end user . with reference to fig2 , the ninth unit 12 is a modulo addition stage . it adds the output w 3 of the third unit to z 4 from the key scheduling unit 9 to produce output w 8 . outputs z 7 and z 8 are used as inputs to the fifth unit 5 and the eighth unit 8 , respectively . a significant feature of the key scheduling unit 9 is that it uses a key variable , z 9 , which is twice the length of the key variable of the prior art system of u . s . pat . no . 6 , 108 , 421 and therefore offers significantly increased cryptographic strength . in addition , when a symmetric key variable ( i . e . upper half and lower half are equal ) is input , then z 4 will evaluate to zero . this negates any effect of encryption block 12 . in fact , when a symmetric key variable is input , all operations will evaluate such that the block cipher device 9 will produce the same output for a given input as the prior art block cipher of u . s . pat . no . 6 , 108 , 421 . significant , equipment can be designed to use the present embodiment of block cipher 100 with double the key length having significantly increased cryptographic strength while still providing a mode for inter - operating with equipment using prior art block ciphers . when required , the value of the original key variable z 9 can be recovered . variables z 7 and z 13 are reloaded into the first shift register 14 and the second shift register 17 , respectively . each register is shifted to the left one bit at a time until its contents have been completely re - circulated . with each shift , the most significant bit in each register is mod 2 added to the outputs of the first function unit 13 and the second function unit 16 . the result is moved into the least significant bit position . when the contents of the first shift register 14 and the second shift register 17 have been completely processed , each is input to the third function unit 15 and the fourth function unit 18 , respectively . in the third function unit 15 and the fourth function unit 18 , the same custom bit pattern is bit - wise mod 2 added to reproduce the upper and lower halves of z 9 . this permits an original encryption key to be recovered for other cryptographic operations , for example key wrapping ( key encryption ). alternately , a copy of the original key may be kept in an auxiliary register . however , this would require a 256 bit auxiliary storage register which would add to the gate count of a hardware rendering . the block cipher device may be operated in various modes such as a self - synchronizing cipher feedback mode ( sscfb ), a minimum error propagation ( or counter ) mode ( mep ), or a block cipher feedback mode ( bcfb ). with reference now to fig4 illustrating a bcfb mode , a block of unencrypted data or “ plain text ” ( pt ) is applied to the input of the encrypter 500 labeled pt e . pt e is then modulo 2 added to a block of “ key stream ” ks . ks represents the output of the block cipher device 100 - 1 . ct represents the resulting block ( i . e ., cipher text ). ct is output at the port labeled ct e and is then transmitted over a channel 200 . in the next iteration , ct is fed back as input to the block cipher device 100 - 1 . the block cipher device processes the fed back block to produce a new block of ks . ks is then combined with the next block of pt and the encryption process continues . at the decrypter 600 , received ct is represented by ct d . ct d is combined with a block of ks to produce as output a block of recovered plain text pt d . the ct d block is simultaneously applied to the input of the block cipher device 100 - 2 . the block cipher device 100 - 2 uses the ct d block as input to produce another block of ks . this ks block is used to process the next block of ct d . this mode is intended for relatively error free communication channels . with reference now to fig5 illustrating a mep mode , unencrypted data or “ plain text ” pt is applied to the input of the encrypter 500 labeled pt e . pt e is then modulo 2 added to a block of ks to produce a block of cipher text . ct is output at a port labeled ct e and is then transmitted over the channel 200 . for a next iteration , encrypter counter 300 - 1 is incremented and the output of the counter 300 - 1 is input to the block cipher device 100 - 1 . the block cipher device 100 - 1 processes to produce a new block of ks . the new block of ks is then combined with the next block of pt and the encryption process continues . at the decrypter 600 , received ct is represented by ct d . ct d is combined with a block of ks to produce as output a block of recovered plain text pt d and decrypter counter 300 - 2 is incremented . the block cipher device 100 - 2 uses the output of the counter to produce another block of ks . this ks block is used to process the next block of ct d . this mode is intended for noisy or error prone communication channels . a toggled bit error on the channel will likely result in only a one bit error on pt d . in other words , in this mode the cryptographic system will likely have only one bit of error extension . with reference now to fig6 illustrating a sscfb mode , unencrypted data or “ plain text ” ( pt ) is applied one bit at time to the input labeled pt e . each pt e bit is modulo 2 added to a bit of ks to produce a bit of cipher text ct . encryption continues until another iteration is initiated . another iteration may begin when either the entire block of ks is consumed or when the pattern detector 400 - 1 is triggered . the pattern detector 400 - 1 continually monitors ct for a specific bit sequence and when the sequence is detected a new iteration is triggered . because ct appears statistically random , this mechanism will initiate a new iteration at pseudo - random intervals . when a new iteration is initiated , all remaining ks is purged from the key buffer 401 - 1 and the most recent bit block of ct , ct e , is input to the block cipher device 100 - 1 . the block cipher device 100 - 1 uses the most recent block as input to produce another block of ks . the new block of ks is stored in the key buffer 401 - 1 and is used to continue the encryption process . at the decrypter 600 , the received ct is applied one bit at time to input labeled ct d . each ct d bit is modulo 2 added with a bit of ks to produce a bit of recovered “ plain text ” as output pt d . the ct bit stream is simultaneously applied to the input buffer 402 - 2 ( cb 1 ) of the block cipher device 100 - 2 . when either the input buffer 402 - 2 becomes full or the pattern detector 400 - 1 triggers , the following will occur : 1 ) the key buffer 401 - 2 is purged ; 2 ) the most recent block of ct , ct e , is input to the block cipher device 100 - 2 ; 3 ) the block cipher device uses the most recent block of ct to produce a new block of ks ; and 4 ) the new block of ks is stored in the key buffer 401 - 2 . the block cipher device 100 - 2 continues processing and ct d continues to be shifted into input buffer 402 - 2 until another iteration is initiated . this mode is intended for communication channels that are subject to synchronization errors . in this mode , a communication system will be able to automatically recover from loss cryptographic and block boundary synchronization . to operate in any of the modes shown in fig3 – 63 , the encrypter 500 and the decrypter 600 must first be initialized such that their internal states are all identical . initialization may be obtained using an initialization vector “ iv ” which is generated on the encrypter side and is used to initialize all internal states of the encrypter . the iv is then transmitted over the channel 200 to the decrypter 600 . using the iv , all internal states of the decrypter 600 are initialized to the same values . the method of the present invention offers the many advantages including twice the cryptographic strength without a proportional increase in the gate count of hardware renderings . this is extremely significant in that operational parameters , such as heat dissipation and power consumption increase proportionally with gate count . other parameters such as data rate and production yield will generally be inversely proportional to gate count . the method is also more robust cryptographically . it does not suffer from the strength vulnerabilities associated with other approaches , most notably , multiple encryption schemes . moreover , the method of the present invention provides the above mentioned and other advantages while maintaining backward interoperability with less robust systems of the prior art such as disclosed in u . s . pat . no . 6 , 108 , 421 , referenced above . while preferred embodiments of the present invention have been described in the foregoing , it is to be understood that the embodiments described are illustrative only and the scope of the invention is to be defined solely by the appended claims when accorded a full range of equivalence , many variations and modifications naturally occurring to those of skill in the art from a perusal hereof .