now , the invention will be described in conjunction with an exemplary embodiment thereof shown in fig1 . referring to fig1 reference numerals 1 to 6 denote input terminals , respectively , 7 denotes an output terminal , 8a and 8b denote gates , respectively , 9 denotes a flip - flop , and reference numerals 10 , 20 , 30 and 40 denotes delay units . the delay unit 10 includes a gate circuitry 10a , a setting circuitry 10b and a counter 10c interconnected in the manner as shown . each of the remaining delay units 20 , 30 and 40 is of a same structure as the delay unit 10 . accordingly , the following description is primarily directed to the operation of the delay unit 10 , being understood that the description holds true for the other delay units unless specified otherwise . referring to fig1 signals 1a to 4a are applied to input terminals 1 to 4 , respectively , while a reference signal 5a is applied to an input terminal 5 . a clock signal 6a is applied to the clock input terminal 6 . a test signal 9a is derived from the output terminal 7 . the input signal 1a is a digital signal having binary logic levels &# 34 ; 1 &# 34 ; and &# 34 ; 0 &# 34 ;. the reference signal 5a serves as a reference for the repetition period of the input signal 1a . in other words , it is so arranged that the repetition period of the signal 1a coincides with the period of the reference signal 5a . the clock signal 6a has a shorter repetition period than that of the reference signal 5a and is applied to the counter 10c of the delay unit 10 . the input signal 1a and the reference signal 5a are applied to the gate 10a of the delay unit 10 . when the signal 1a is &# 34 ; 1 &# 34 ;, the reference signal 5a is transmitted to the counter 10c of the delay unit 10 . the setting circuitry 10b of the delay unit 10 serves to set a delay time at the counter 10c of the delay unit 10 . to this end , the setting circuitry 10b may be constituted by a memory in which a set value corresponding to a desired delay time may be previously stored from a central processing unit or cpu ( not shown ). the setting circuitry 10b of the delay unit 10 sends the set value corresponding to a first delay time to the counter 10c , whereby the counter 10c is loaded with the set value corresponding to the first delay time under the timing of the reference signal 5a . the counter 10c of the delay unit 10 counts the clock pulses 6a in a number corresponding to the loaded set value , whereby a signal delayed for the first delay time relative to the reference signal 5a is applied to one input of a gate 8a . it is assumed , by way of example , that the period of the clock signal 6a is 10 ns . on the assumption , in order to have the first delay time be equal to 900 ns , the set value of &# 34 ; 90 &# 34 ; may be placed in the counter 10c of the delay unit 10 . in a similar manner , the delay unit 20 applies to the other input of the gate 8a a signal delayed relative to the reference signal 5a for a second delay time . on the other hand , the delay units 30 and 40 apply signals to a gate 8b which signals are delayed relative to the reference signal 5a for third and fourth delay times , respectively . the gates 8a and 8b are each constituted by an or gate . the output of the or gate 8a sets a flip - flop 9 , while the output of the gate 8b resets the flip - flop 9 . accordingly , the flip - flop 9 is set in response to the output signals of the delay units 10 and 20 , respectively , while it is reset by the output signals of the delay units 30 and 40 . in this connection , it should be mentioned that the first to fourth delay times may be of a same duration or different durations . fig2 shows a time chart for illustrating operation of the test signal generating circuit shown in fig1 . in fig2 the waveforms of the aforementioned signals 1a to 4a are illustrated at ( a ) to ( d ), respectively . as will be seen in fig2 the waveforms ( a ) and ( b ) are same and the waveforms ( c ) and ( d ) are same , wherein the waveform ( c ) corresponds to inversion of the waveform ( a ). the waveform of the reference signal 5a is shown at ( e ) in fig2 . as will be seen , the reference signal 5a includes clock pulses p and q . the waveform of the clock signal 6a is illustrated at ( f ) in fig2 . there is shown in fig2 at ( g ) a waveform of the reference signal 5a outputted from the gate 10a of the delay unit 10 when the signal shown at ( a ) in fig2 assumes logic &# 34 ; 1 &# 34 ; level . a clock pulse p1 shown at ( g ) in fig2 corresponds to the clock p shown at ( e ). the output waveform of the delay unit 10 is shown at ( h ) in fig2 . as will be seen , the output p11 shown at ( h ) is delayed for a delay time t1 relative to the clock p1 shown at ( g ) in fig2 . shown at ( i ) in fig2 is a waveform of the reference signal 5a outputted from the gate 20 of the delay unit 20 at the time when the signal shown at ( b ) assumes logic &# 34 ; 1 &# 34 ;, wherein the clock p2 corresponds to the clock p shown at ( e ) in fig2 . shown at ( j ) in fig2 is the signal waveform outputted from the delay unit 20 . as will be seen , the output signal p21 is delayed for a delay time t2 relative to the clock p2 shown at ( i ) in fig2 . shown at ( k ) in fig2 is a waveform of the reference signal 5a outputted from the gate 30a of the delay unit 30 at the time the signal shown at ( c ) assumes logic &# 34 ; 1 &# 34 ;, wherein the clock q1 shown at ( k ) corresponds to the clock q shown at ( e ) in fig2 . shown at ( 1 ) in fig2 is the output waveform of the delay unit 30 . as will be seen , the output signal q11 shown at ( 1 ) in fig2 is delayed for a delay time t3 relative to the clock q1 shown at ( k ) in fig2 . shown at ( m ) in fig2 is the waveform of the reference signal 5a outputted from the gate 40a of the delay unit 40 . the clock q2 shown at ( m ) in fig2 corresponds to the clock q shown at ( e ) in fig2 . shown at ( n ) in fig2 is the output waveform of the delay unit 40 . it will be seen that the output signal q21 is delayed by a delay time t4 relative to the clock q2 shown at ( m ) in fig2 . shown at ( o ) in fig2 is the waveform of the test signal 9a outputted from the flip - flop 9 . more specifically , the output signal r shown at ( o ) in fig2 is produced by the flip - flop 9 when the latter is set in response to the output p11 shown at ( h ) in fig2 and reset by the output signal q11 shown at ( 1 ) in fig2 . further , the output signal s shown at ( o ) in fig2 is produced by the flip - flop 9 when it is set by the signal p21 shown at ( j ) in fig2 and reset by the signal q21 shown at ( n ). although the output signal of the flip - flop 9 is illustrated over two periods at ( o ) in fig2 it will be understood that the waveform shown at ( o ) in fig2 is obtained consecutively from the output of the flip - flop 9 because the signals 1a to 4a and the reference signal 5a are repetitive signals . as will be appreciated from the foregoing description , the timing of the test signal outputted from the flip - flop 9 can be delayed for a desired time with the waveform of the test signal being varied in a facilitated manner by virtue of such arrangement in which the first to fourth delay times are set in the counters 10c to 40c of the delay units 10 to 40 , respectively , wherein the clock signal 6a is counted by these counters . although the invention has been described in conjunction with a preferred embodiment thereof , it is obvious that changes and modifications will readily occur to those skilled in the art without departing from the spirit and scope of the invention .