a representative hardware environment is depicted in fig1 which illustrates a typical hardware configuration of a computer in accordance with the subject invention having a central processing unit 10 , such as a conventional microprocessor , and a number of other units interconnected via a system bus 12 . the computer shown in fig1 includes a random access memory ( ram ) 14 , read only memory ( rom ) 16 , an i / o adapter 18 for connecting peripheral devices such as disk units 20 to the bus , a user interface adapter 22 for connecting a keyboard 24 , a mouse 26 , a speaker 28 , a microphone 32 , and / or other user interface devices such as a touch screen device ( not shown ) to the bus , a communication adapter 34 for connecting the computer to a data processing network and a display adapter 36 for connecting the bus to a display device 38 . fig2 is a block diagram of an audio system in accordance with the subject invention . the host computer is as described in fig1 . the audio subsystem 210 is attached to the bus of the host computer and includes a digital signal processor ( dsp ) 220 to implement the recursive digital filters in accordance with the subject invention . stereo data enters the computer at the analog to digital converter ( adc ) 230 and is transmitted via the digital to analog converter ( dac ) 240 to speakers or other audio device . when recording or playing back digital audio data , recursive digital filters are used to remove unwanted noise effects and to smooth the data . implementation of these filters is facilitated with a digital signal processor ( dsp ) 220 such as a texas instruments tms320 dsp . if stereo sound is involved , separate filters are used for each of the channels . even though the filter characteristics of each channel , including bandwidth and sample rate , are usually the same , separate filters are employed because the states of each filter channel differ . the mathematical equations which constitute a five pole recursive digital filter for right and left channel stereo processing are shown in fig3 . the conventional structure for non - parallel processing of these filters is shown functionally in fig4 . note , the filter gains gain1 400 , gain2 402 and gain3 403 and coefficients b1 to b5 for each channel are loaded separately even though the numerical values for each channel are the same . this redundant loading of gains and coefficients uses machine cycles inefficiently . even though the particular example uses five pole filters , the implementation process holds independent of filter size . inefficiency increases with the size of the filter . the ibm digital signal processor ( isp ) provides parallel processing capability that are employed by the invention to significantly reduce processing time . a detailed description of the isp is presented below . the structure for parallel processing two , five pole recursive digital filters is shown in fig5 . the filter gains and coefficients for both channels are loaded only once . this processing reduces the number of loads required and permits some of the unique instructions to be executed at the same time due to the parallel processing features of the isp . fig6 through 9 present the parallel nature of the processing structure in accordance with the subject invention . processing is divided into three sections : ( 1 ) right for processing those instructions unique to the right channel , ( 2 ) left for processing those instructions unique to the left channel , and throughout the structure , multiple instructions appear on the same line . instructions occurring on the same line get processed during the same cycle . this processing reduces the overall number of cycles required . arranging the filters in this manner affords an opportunity to exploit the isp &# 39 ; s parallel processing capability . fig1 presents the isp source code for parallel processing two channel stereo data employing two , five pole digital filters . this structure reduces filter processing requirements by over thirty percent . the ibm signal processor ( isp ) is a digital signal processor that operates at sixteen million instructions per second ( mips ). the isp has a harvard architecture with data address space completely separate from instruction address space . the isp can address up to 64k instructions and up to 32k data words . instructions are 24 bits wide and data words are 16 bits wide . instructions pass through a three - phase pipeline : ( 1 ) fetch , ( 2 ) decode , and ( 3 ) execute . the arithmetic logic unit ( alu ) is separate from the multiplier , so an alu operation and a multiply can occur simultaneously in a single machine cycle . instructions can be classified into two categories : ( 1 ) simplex instructions , and ( 2 ) parallel instructions . a simplex instruction performs a single operation , such as a load from memory , during a machine cycle . the operations within a parallel instruction are encoded as a single 24 - bit instruction . the isp contains eight general purpose 16 - bit registers , r0 - r7 . registers r2 and r6 have 16 - bit extensions that enable usage in certain 32 - bit operations . r0 and r4 can be used as index registers to form base - displacement addresses for load , store , store immediate and most branch instructions . r0 and r4 can also perform modulo or circular addressing . modulo addressing is controlled by bit settings in the machine control register . r4 can perform table addressing , but r0 cannot . register r5 ( also called rx ) is always one of the data sources in a multiplication . r1 , r3 and r7 have no special properties . r7 is traditionally used to store a return address for subroutine calls . the general purpose registers are arranged in two banks : r0 - r3 and r4 - r7 . in a compound instruction that includes a load or load immediate instruction , the target of the transfer and the target of the alu operation must come from opposite register banks . the isp can multiply two 16 - bit numbers in a single machine cycle . the product is stored in the 32 - bit multiplier product ( rp ) register . rp can be used to perform 32 - bit accumulations to wr2 or wr6 . the low bits of the product can be accessed as register rpl , and the high order 16 - bits as rph . the machine control register is divided into two 16 - bit registers , mcrh and mcrl . isp programs use mcrh extensively to control modulo addressing , arithmetic saturation and multiplier scaling . the eight low - order bits in mcrl are used to enable or inhibit interrupt levels 0 - 7 . the instruction link register ( ilr ) is normally equal to the location counter . it is also used to save the location counter after an interrupt and to perform position - relative branches . the common data bus ( cdb ) is used implicitly by all data transfer operations . the cdb generally holds the last value loaded or stored . the cdb is explicitly referenced for the following reasons : some branch instructions take the new contents of the location counter from the cdb ; and a test and branch can be performed on a specified bit in the cdb . the processor status register consists of two 16 - bit registers , psrh and psrl . psrh is normally accessed explicitly only during interrupt processing . psrh is frequently accessed implicitly , since it contains the condition codes or flags for the isp chip . the psrl register should not be accessed by an isp programmer . the indirect program access register ( ripa ) is used when loading data from the instruction address space with the bipar instruction . isp addressing is a word addressable architecture . sixteen bits are always read from memory and only even addresses are accessible . indexed addressing is facilitated using the r0 and r4 index registers . the contents of a register is combined with an eight bit or sixteen bit offset . offset limits exist depending on whether simple or parallel instructions are used . circular addressing is also enabled through modulo n addressing using the r0 and r4 registers . however , a buffer must be aligned and sized in powers of two . table addressing is also facilitated using the r4 register . instructions in the isp pass through a three phase pipeline . phase 1 is a fetch operation . phase 2 is a decode operation . phase 3 is an execute operation . during each machine cycle , three actions are occurring simultaneously . an instruction is being fetched from instruction memory . the previously fetched instruction is decoded , including the resolution of operands and addresses . the previously decoded instruction is executed . the net effect is that the instruction throughput is one instruction per machine cycle . most instructions execute at the end of phase 3 . however , branch instructions execute at the end of phase 2 with no additional hardware action during phase 3 . the instruction immediately after a branch instruction is being fetched during the same phase that the branch is decoded and executed . the instruction immediately after a branch is always executed . while the invention has been described in terms of a preferred embodiment in a specific system environment , those skilled in the art recognize that the invention can be practiced , with modification , in other and different hardware and software environments within the spirit and scope of the appended claims .