reference is now has to fig3 illustrating an embodiment of the present invention as applied to the aforementioned audio bit rate reduction system . in the decoder shown in fig3 the parts or portions similar to those shown in fig1 are indicated by the same reference numerals . referring to this figure , to an input terminal 31 , there are supplied signals from the output terminal 22 shown in fig1 these signals being transmitted and supplied through a transmission medium or a recording medium after having been processed in such a manner that the mode and the range are switchingly selected blockwise as described above . when transmitting these signals on the transmission medium or the recording medium , it is customary that these signals are converted by a multiplexer into serial data strings , word or block sync data are affixed to these serial data strings and the resulting signals are modulated by a modulating system proper to transmission . at a receiving or reproducing side , there are provided a demodulating circuit 70 , a sync separating circuit 71 and a error correcting and detecting circuit 72 so that signals corresponding to the audio signal component are supplied to a terminal 31 and the range information signals are supplied to a terminal 36 while the mode selection information signals are supplied to a terminal 37 . in addition , an error flag from the error detecting circuit 72 is supplied to a terminal 38 , while a word clock from a word clock generator 73 is applied to the terminal 39 . the input signal from the terminal 31 corresponding to the transmitted audio signal components in the block form are supplied through an input terminal 51 of an interpolating circuit 50 to a one - word delay circuit 52 and to a terminal b of a changeover switch 53 . the output of a one - word delay circuit 52 is supplied to a terminal a of the changeover switch 53 . the one - word delay circuit 52 and the changeover switch 53 take charge of the succeeding - value interpolation or holding , as later described in detail . the output from the changeover switch 53 is supplied to a terminal a of a changeover switch 54 , the output of which is supplied through the one - word delay circuit 55 to the terminal b of the changeover switch 54 . the changeover switch 54 and the one - word delay circuit 55 take charge of the previous value interpolation or holding or zero &# 39 ; th order interpolation , as also described later in detail . the output from the one - word delay circuit 55 is supplied to a terminal a of a changeover switch 56 and to a mean value circuit 57 . the circuit 57 computes a value equal to 1 / 2 of the sum of the output data from the delay circuit 55 and the output data of the changeover switch 53 , or the mean value , which is then supplied to a terminal b of the changeover switch 56 . these changeover switches 54 , 56 , the delay circuit 55 and the mean value circuit 57 take charge of the mean value interpolation or first order interpolation of the error . the output from the changeover switch 56 is taken out at an output terminal 59 of the interpolating circuit 50 so as to be supplied to the shifter 32 of the decoder shown in fig1 . the structure and operation of the circuit downstream of the shifter 32 are similar to those of the decoder 30 shown in fig1 so that the corresponding description is omitted for simplicity . the changeover switches 53 , 54 and 56 are switched by switching control signals s 1 , s 2 and s 3 from an interpolating control circuit 60 . as an example of the switching control operation , when there is no code error , the switches 53 , 54 and 56 are all connected to the terminals a . when a code error is caused at the leading or first word of a block , the switch 53 is switched to the terinal b by the signal s 1 so that the error is interpolated by the next following value or by the second word in the block . when a code error is caused in the last word of a block , the switch 54 is switched to the terminal b by the signal s 2 so that the error is interpolated by the preceding value ( previous value holding ). when the code error is caused in some other positions , the switches 54 , 56 are switched to the terminal b to make a mean value interpolation . for producing these switching control signals s 1 , s 2 and s 3 , timing pulses t 1 , t 2 and t 3 are first produced in a timing pulse generator 61 for designating interpolation modes to be selected in dependence upon the word position in a block , and are used to gate control the error flag ef . sub . o supplied to the terminal 38 by using and gates 66 , 67 and 68 . in view of the word delay caused in the delay circuits 52 and 55 in the interpolation circuit 50 , it is necessary to set the timing of the pulses t 1 , t 2 and t 3 or to delay the error flag ef . to this end , the error flag from the terminal 38 is sequentially delayed one word by two one - word delay circuits 62 and 63 . reference is made to fig4 for illustrating a more specific example of interpolating operation . in the present example , it is assumed that , for simplicity of illustration , the word number in one block is 8 , the words are indicated as w 1 , w 2 , . . . , w 8 from the first word in the block , and code errors are caused in the first , last and some other interjacent word , such as the fifth word . that is , the input data a shown in fig4 is supplied to the input terminal 51 shown in fig3 and the words w 1 &# 39 ;, w 5 &# 39 ; and w 8 &# 39 ; of the eight words in one block are invalid data containing code errors . hence , the error flag ef o supplied to the terminal 38 is &# 34 ; 1 &# 34 ; at the position of these words w 1 &# 39 ;, w 5 &# 39 ; and w 8 &# 39 ;. it is noted that the circled numerals 1 to 8 in fig4 stand for the corresponding word numbers in the block at the signal input and output points and thus in disregard of the word number deviation caused by word delaying . since the input data a is delayed one word in the delay circuit 52 , the error flay ef o is also delayed one word by a delay circuit 62 to produce an error flag ef 1 shown in fig4 . the timing pulse t 1 from the timing pulse generator 61 represents a signal that goes to &# 34 ; 1 &# 34 ; at the first word position of the signal thus delayed one word and that designates the word position for which the succeeding - value interpolation mode should be selected if the code error exists . an and is taken of this error flag ef 1 and the timing pulse t 1 at the and circuit 66 to produce the switching control signal s 1 of the switch 53 . this control signal s 1 goes to a &# 34 ; 1 &# 34 ; at , for example , the second word position of the orignial undelayed input data a , that is , at the first word position after the one - word delay of the input data . when the control signal s 1 is &# 34 ; 1 &# 34 ;, the switch 53 is switched to the terminal b . hence , in the output b from the switch 53 , the first word in the block or the error word w 1 &# 39 ; is substituted by the second word w 2 so that the output is the suceeding - value interpolated output . the timing pulse t 2 specifies the range of selection of the preceding - value hold and the mean value interpolation mode , and has a waveform which is an inversion of the timing pulse t 1 , and thus goes to &# 34 ; 1 &# 34 ; at other than the first word in the block of the signal delayed by one word . the switching control signal s 2 of the switch 54 is obtained by taking an and of this timing pulse t 2 and the error flag ef 1 at the and circuit 67 and goes to &# 34 ; 1 &# 34 ; at the fifth and last or eighth words . when the switching control signal s 2 is &# 34 ; 1 &# 34 ;, the switch 54 is switched to the terminal b so that the output from the delay circuit 55 is fed back to the delay circuit 55 . thus , the output c from the delay circuit 55 has its word numbers further delayed by one word and thus delayed by two words from the original input data a , while the output c produced when the control signal s 2 goes to &# 34 ; 1 &# 34 ; ( words w 4 and w 7 ) is produced with one word delay for substituting the fifth and the eighth ( or last ) words in the two - word - delay signal . in association with the delay caused by this delay circuit 55 , the error flag ef 1 is delayed one word in a delay circuit 63 to produce an error flag ef 2 delayed by two words from the original input error flag ef o . the timing pulse t 3 specifies the range of selection of the mean value interpolate mode for the two - word - delay signal . thus , it goes to &# 34 ; 1 &# 34 ; at the second to seventh word positions excluding the first and last or eighth word positions . the switching control signal s 3 for the switch 56 is obtained by taking an and of the error flag ef 2 and the timing pulse t 3 at the and circuit 68 . the control signal s 3 goes to &# 34 ; 1 &# 34 ; only at the fith word position of the two - word - delay signal . at this time , the switch 56 is switched to the terminal b such that a mean value of the word w 6 of the output b from the switch 53 and the word w 4 of the output c from the delay circuit 55 or ( w 4 + w 6 )/ 2 is taken from the mean value circuit 57 and supplied to an output terminal 59 . hence , the interpolated output from the switch 56 is delayed by two words with respect to the orignial input data a such that the word order in the block is w 2 , w 2 , w 3 , w 4 , ( w 4 + w 6 )/ 2 , w 6 , w 7 , w 7 . in other words , the first word w 1 &# 39 ; in the block where the code error has occurred is interpolated by the second word w 2 ( succeeding value interpolate or hold ), the last word w 8 &# 39 ; is interpolated by the word w 7 one word before ( previous value holding ) and the interjacent fifth word w 5 &# 39 ; is interpolated by the mean value of the preceding and the next following or succeeding words ( w 4 + w 6 )/ 2 ( mean value interpolation ) such that the interpolation is realized only using the data in the block containing the word where the code error has occurred and thus without using data of any other blocks . this results in satisfactory interpolation since it becomes possible to prevent interpolation of error data by data of different or heterogeneous nature , such as predictive coding processing modes comprising differential or straight pcm modes or range data , that is , the bit compression rate data . in addition , it is only possible to make the interpolation for the data of a shorter word length before the decoding operation such as bit expansion by for example the shifter 32 so that the operation word length is reduced , thus resulting in correspondingly simplified circuit design and increased processing speed . reference is now made to fig5 and 6 for explaining a modified embodiment of the present invention . in will be noted that , in case of application of the present invention to , for example , a cd - rom using an optical disk as the recording medium , it becomes necessary to perform an interleaving in conformity to the recording format . for example , in case of a decoding device in which the data of a four channel audio signal data are repeatedly applied word by word at the four - word periods , the interpolating circuit for the four channels may be provided in a parallel circuit configuration . however , it is also possible to make the interpolation within the block by a simpler arrangement using two four - word delay circuits 72 and 75 , as shown in fig5 . in the interpolating circuit 70 shown in fig5 the parts similar to those shown in fig3 are designated by the same reference numerals . the circuit structure is similar to that of fig3 except that the delay circuit 72 and 75 perform the four - word delaying . thus , the delay circuit 72 and the changeover switch 53 take charge of the succeeding value interpolation or holding in case the code error has occurred at the first word in the block of each channel . similarly , the changeover switch 54 and the delay circuit 75 take charge of the preceding - value interpolation or holding in case the code error has occurred at the last word in the block in each channel , while the changeover switches 54 , 56 , the delay circuit 75 and the mean value circuit 57 take charge of the mean value interpolation in case the code error has occurred at the words other than the leading word and the last word in the block . an example of the four - channel audio signals recorded on the aforementioned cd - rom is shown in fig6 . the left and right channel sterophonic audio signals are separately sampled to produce two - channel data having a word length of for example 16 bits . these data are separately subjected to the aforementioned bit compression processing to produce the left - channel data strings l 1 , l 2 , 3 . . . and the right - channel data strings r 1 , r 2 , r 3 , . . . , each having the word length of , for example , eight bits . when the two - channel data string with each word consisting of eight bits is recorded on the recording medium such as an optical disk , the data are subjected to interleaving using , for example , a random access memory ( ram ). fig6 shows an example of such interleaving for a 28 - row 4 - column memory area . thus , the left channel data strings l 1 , l 2 , . . . and the right channel data strings r 1 , r 2 , . . . are written in the first and the second rows in the regular order in the vertical direction as indicated by an arrow mark p , starting from the first row . after the words l 28 and r 28 are written in the 28th lines , the data strings l 29 , l 30 , . . . and the data strings r 29 , r 30 , . . . are sequentially written in the third and fourth rows , respectively . when the data are read from the memory , the data are read transversely in the sequence of the first column of the first row , the second column of the first row et seq ., as indicated by an arrow mark q , that is , in the order of the words l 1 , r 1 , l 29 , r 29 , l 2 , r 2 , l 30 , r 30 , . . . so as to be recorded on the recording medium such as the optical disk . thus , the reproduced data signals are temporarily continuous data with the four - word periods , such that it becomes necessary to perform the interleaving on the data strings having four - word periods . the interpolating circuit of fig5 may be advantageously employed for the interleaving of the signals having such recording format . in the above described embodiments , the succeeding value interpolation , the previous value holding and the mean value interpolation are selected for the leading word , the last word and the interjacent word in the block . however , the present invention is not limited to these specific embodiments . for example , the succeeding value or previous value interpolation may be used in place of the mean value interpolation for the interjacent word positions , while it is also possible to effect the second or higher order interpolation .