fig2 is a simplified side cross - sectional view of a portion of a field emission display 10 ′ including a spacer 62 ′, in accordance with an embodiment of the present invention . fig2 is not drawn to scale . many of the components used in the field emission display 10 ′ shown in fig2 are identical to components used in the field emission display 10 of fig1 . therefore , in the interest of brevity , these components have been provided with the same reference numerals , and an explanation of them will not be repeated . in the embodiment of fig2 , the spacer 62 ′ may be formed from silicon . in one embodiment , an insulating layer 64 positioned at the end of the spacer 62 ′ is formed from spin - on glass . in one embodiment , the insulating layer 64 has a thickness in excess of two microns . a layer 66 may be included between the insulating layer 64 and the transparent conductive layer 24 . in one embodiment , the layer 66 is formed from conventional polycrystalline silicon . in another embodiment , a conventional layer of metal , such as aluminum , nickel or other metal , forms the layer 66 . the layer 66 is used to protect the transparent conductive layer 24 from chemical attack at a later stage in fabrication when the insulating layer 64 is etched . in one embodiment , the spacer 62 may be conductive and attached to the insulating layer 64 through a process of anodic bonding , as described below . fig3 is a simplified side cross - sectional view of a portion of a faceplate at one stage in fabrication , according to an embodiment of the present invention . the grille 28 has previously been fabricated on the transparent viewing screen 22 using conventional photolithography and deposition techniques . the transparent conductive layer 24 has previously been fabricated on the transparent viewing screen 22 and the grille 28 using conventional deposition techniques . the layer 66 has previously been fabricated of polycrystalline silicon or metal using conventional deposition techniques . the insulating layer 64 may be formed using spin - on - glass ( e . g ., teos and a sodium or potassium salt dissolved in ethanol ), as described in “ silicon - silicon anodic - bonding with intermediate glass layers using spin - on glasses ,” by h . j . quenzer et al . ( proc . ninth annual int . workshop on micro electro mech . sys ., ieee cat . no . 96ch35856 ( feb . 11 - 15 , 1996 ), pp . 272 - 267 .). alternatively , the insulating layer 64 may be formed by sputtering , as described in “ field - assisted bonding below 200 ° c . using metal and glass thin - film interlayers ,” by w . y . lee et al . ( app . phys . lett ., vol . 59 , no . 9 ( 1987 ), pp . 522 - 524 .). in another embodiment , the insulating layer 64 may be formed using other conventional processes , such as electron beam evaporation . in one embodiment , the insulating layer 64 may be planarized and smoothed using conventional chemical - mechanical polishing . fig4 is a simplified side cross - sectional view of the faceplate of fig3 at a later stage in fabrication , according to an embodiment of the present invention . a silicon wafer 67 having one metallized surface 68 is placed to have another surface 70 in intimate contact with the insulating layer 64 to form a composite assembly 72 . a voltage source 74 has a negative lead coupled to the transparent conductive layer 24 and to the layer 66 . a positive lead of the voltage source 74 is coupled to the metallized surface 68 . in one embodiment , the metallized surface 68 forms an ohmic contact with the silicon wafer 67 . in another embodiment , the metallized surface forms a schottky contact with n - type silicon forming the silicon wafer 67 . the composite assembly 72 is heated and a voltage of several hundred volts is supplied by the voltage source 74 to anodically bond the silicon wafer 67 to the insulating layer 64 . anodic bonding is described in u . s . pat . no . 3 , 397 , 278 , entitled “ anodic bonding ,” issued to d . i . pomerantz , and in “ field assisted glass - metal sealing ,” by g . wallis et al . ( jour . app . phys ., vol . 40 , no . 10 ( september 1969 ), pp . 3946 - 3949 .). anodic bonding of silicon to an insulating layer is described in “ anodic bonding technique for silicon - to - ito coated glass bonding ,” by w . b . choi et al . ( proc . soc . phot . opt . inst . eng ., vol . 3046 ( 1997 ), pp . 336 - 341 .). selection of glass composition for the insulating layer 64 to provide temperature coefficient of expansion matching to the silicon wafer 67 and to allow room - temperature anodic bonding is discussed in “ low - temperature silicon - to - silicon anodic bonding with intermediate low melting point glass ,” by m . esashi et al . ( sensors and actuators , a21 - a23 ( 1990 ), pp . 931 - 934 .). significantly , anodic bonding provides bonds having superior mechanical strength and does not introduce additional materials that can result in contamination of the interior of the field emission display 10 ′. fig5 is a simplified side cross - sectional view of the faceplate of fig4 at a later stage in fabrication , according to an embodiment of the present invention . the metallization on the surface 68 ( fig4 ) has been stripped using conventional etching techniques and a hard mask 76 is formed from a material such as sio 2 deposited by conventional teos or si 3 n 4 deposited by conventional pecvd . the hard mask 76 is patterned using conventional photolithographic techniques . fig6 is a simplified side cross - sectional view of the faceplate of fig5 at a later stage in fabrication , according to an embodiment of the present invention . reactive ion etching is used to anisotropically etch the silicon wafer 67 ( fig4 and 5 ), leaving the spacers 62 ′. anisotropic etching is discussed in “ reactive ion etching for high aspect ratio silicon micromachining ,” by i . w . rangelow ( surf . and coatings tech . 97 ( 1997 ), pp . 140 - 150 .). reactive ion etchers capable of etching & gt ; 300 microns of silicon at an etch rate of 3 microns a minute using positive photoresist or a hard mask are available from surface technology systems usa , inc ., 611 veterans boulevard , suite 107 , redwood city , calif . 94063 . in one embodiment , the spacers 62 ′ are formed from silicon having a dopant concentration of about 2 × 10 14 / cm 3 or less to realize an avalanche breakdown voltage of in excess of 1 , 000 volts , and in any case a dopant concentration of 7 × 10 14 / cm 3 or less to realize an avalanche breakdown voltage of in excess of 400 volts . in one embodiment , a cathode of the spacer 62 ′ is coupled to the faceplate 18 ′. in one embodiment , the cathode is formed as a schottky contact with the faceplate 18 ′. in one embodiment , an anode is formed by doping the portion of the spacer 62 ′ that will contact the baseplate 20 with acceptors . in one embodiment , the spacer 62 ′ is formed from intrinsic silicon in order to realize a high resistivity . gold doping may be used to reduce mobile charge carrier concentrations in the spacer 62 ′. in one embodiment , the spacer 62 ′ is formed from polycrystalline silicon . in one embodiment , the spacer 62 ′ is formed as a diode having a carrier concentration such that a depletion region in the diode extends along most of the length of the spacer from the faceplate 18 ′ to the baseplate 20 when the anode voltage v a is applied to the faceplate 18 ′. it will be appreciated that spacers 62 ′ that include diodes may be formed in a variety of different ways , and may have a p - n junction that may be placed anywhere along the height of the spacer 62 ′ by suitable choice of doping levels and other conventional diode parameters . it will also be appreciated that a schottky junction may be formed at either end of the spacer 62 ′ by appropriate choice of conductivity type for the spacer 62 ′. in one embodiment , the spacer 62 ′ is coated with a conventional passivation layer ( not shown ). in one embodiment , respective ends of the spacer 62 ′ are coupled to conventional conductors ( not shown ) formed on the faceplate 18 ′ and on the baseplate 20 . in one embodiment , ends of the spacers 62 ′ corresponding to the anodes shown in fig6 couple to bumps of soft conductive material ( not shown ) formed on the baseplate 20 . fig7 is a simplified plan view of a portion of the faceplate of fig6 including spacers 62 ′ of arbitrary geometry , according to an embodiment of the present invention . in one embodiment , a faceplate for a display 10 ′ having xga resolution includes an array of approximately 1024 by 768 pixels formed from cathodoluminescent layers 26 . in this type of display 10 ′, each pixel is about 60 microns by 180 microns , providing a faceplate having a display area of 9 . 65 inches by 7 . 28 inches . the cathodoluminescent layer 26 may be formed using a resist formed from polyvinyl alcohol and an ammonium dichromate sensitizer . the resist may be deposited and patterned after the spacers 62 ′ are formed . the insulating layer 64 may then be etched , for example with a buffered oxide etch containing hydrofluoric acid . the layer 66 may be etched using conventional etching processes . isopropyl alcohol may be used as a carrier medium to selectively deposit the cathodoluminescent layer 26 , using the transparent conductive layer 24 as one electrode in a conventional electrophoretic deposition process . fabrication of the field emission display 10 ′ is subsequently completed via conventional fabrication steps . fig8 is a simplified plan view of a portion of a faceplate 18 ′ including spacers 62 ′ and an insulating layer 64 surrounding an area where the spacer 62 ′ contacts the faceplate 18 ′, in accordance with an embodiment of the present invention . the insulating layer 64 is formed to have a thickness sufficient to withstand the anode voltage v a , and is patterned to provide an area surrounding the spacer 62 ′ that is wide enough to prevent arcing from the spacer 62 ′ to the transparent conductive layer 24 , i . e ., having a width comparable to the height of the spacer 62 ′. for example , for a glass having a breakdown field strength of 1 . 4 × 10 5 volts / cm . to withstand an anode voltage v a of 500 volts , an insulating layer 64 having a thickness of about forty microns is required . in one embodiment , the pixels 26 are formed of cathodoluminescent materials chosen to emit different colors of light when bombarded by electrons . for example , the lower left and upper right pixels 26 may include phosphor p - 56 and emit red light . the upper left pixel 26 may include phosphor p - 53 and emit green light , and the lower right pixel 26 may include phosphor p - 47 and emit blue light . fig9 is a simplified block diagram of a portion of a computer 100 including the field emission display 10 ′ having the spacer 62 ′ as described with reference to fig2 through 8 and associated text . the computer 100 includes a central processing unit 102 coupled via a bus 104 to a memory 106 , function circuitry 108 , a user input interface 110 and the field emission display 10 ′ including the spacer 62 ′, according to the embodiments of the present invention . the memory 106 may or may not include a memory management module ( not illustrated ) and does include rom for storing instructions providing an operating system and a read - write memory for temporary storage of data . the processor 102 operates on data from the memory 106 in response to input data from the user input interface 110 and displays results on the field emission display 10 ′. the processor 102 also stores data in the read - write portion of the memory 106 . examples of systems where the computer 100 or the display 10 ′ finds application include personal / portable computers , camcorders , televisions , automobile electronic systems , microwave ovens and other home and industrial appliances . field emission displays 10 ′ for such applications provide significant advantages over other types of displays , including reduced power consumption , improved range of viewing angles , better performance over a wider range of ambient lighting conditions and temperatures and higher speed with which the display can respond . field emission displays find application in most devices where , for example , liquid crystal displays find application . although the present invention has been described with reference to various embodiments , the invention is not limited to these embodiments . rather , the invention is limited only by the appended claims , which include within their scope all equivalent devices or methods which operate according to the principles of the invention as described .