in the present invention , a rotary encoder optically detects the rotation angle and magnetically detects the number of rotations . the rotation angle is detected as a 15 - bit digital signal ( 2 15 = 32768 divisions ). the upper eight bits are detected using an absolute code pattern and the lower seven bits are detected using an incremental code pattern . the number of rotations is detected as an 8 - bit digital signal ( 2 8 = 256 , 0 - 255 rotations ). as shown in fig1 an encoder 2 has a housing 8 . the housing 8 includes a substrate 4 and a cover 6 . a rotor shaft 10 projects from the substrate 4 , and is supported by bearings 12 mounted on the substrate 4 . a rotating disk 14 , mounted on the rotor shaft 10 , rotates with the rotor shaft 10 . as described later , an absolute code pattern , an incremental code pattern , and a standard position pattern are located on the rotating disk 14 . emission elements 16 are located behind the rotating disk 14 , and are mounted on a waveform - shaping circuit substrate 18 . the waveform - shaping circuit substrate 18 is fixed in the housing 8 , and extends toward one face of the rotating disk 14 . a fixed slit board 20 faces the other face of the rotating disc 14 , and has multiple slits in its face as described later . light - receiving elements 22 are disposed opposite the rotating disc 14 , which faces the back of the fixed slit board 20 . absolute signals and incremental signals are detected at a detection portion where the slits in the fixed slit board 20 are combined with the corresponding light - receiving elements 22 . the light - receiving elements 22 transmit information to the waveform - shaping circuit substrate 18 . the waveform - shaping circuit substrate 18 transmits information through a lead wire 24 to outside the housing 8 . a circular magnetic strip 26 , on which a standard position pattern is recorded , is mounted on the back of the rotating disk 14 . two magnetic detection elements 28a and 28b are mounted on the waveform - shaping circuit substrate 18 and opposite the magnetic strip 26 . the magnetic detection elements 28a and 28b transmit information to the waveform - shaping circuit substrate 18 . the information then is transmitted through the lead wire 24 outside the housing 8 together with the rotation angle signal . as shown in fig2 an incremental code pattern 30 consists of evenly spaced slits in the outer periphery of the rotating disk 14 . an absolute code pattern 32 consists of eight concentric circular patterns 32a - 32h on the inner periphery of the rotating disk 14 . a timing code pattern 34 is located between the incremental code pattern 30 and the absolute code pattern 32 . the magnetic strip 26 is also mounted on the rotating disk 14 , and bears the standard position pattern . these patterns 30 , 32 and 34 , excluding the standard position pattern , are rows of slits formed according to a predetermined rule . these rows of slits are formed by coating the transparent rotating disk 14 with a shielding evaporation membrane , and then etching slits in the membrane . for the standard position pattern , north and south magnetic poles n and s are recorded on the magnetic strip 26 mounted on the back of the rotating disk 14 . the magnetic detection elements 28a and 28b detect two standard position signals : one where the north magnetic pole n switches to the south magnetic pole s and the other where the south magnetic pole s switches back to the north magnetic pole n during one rotation of the rotating disk 14 . in fig2 the magnetic detection elements 28a and 28b shown by dashed - line rectangles are mounted on the waveform - shaping circuit substrate 18 . luminous energy compensation tracks 36a and 36b are provided between the circular patterns 32d and 32e , and between the circular pattern 32h and the timing code pattern 34 , respectively . the absolute code pattern 32 consisting of eight concentric circular patterns 32a - 32h extends peripherally from a predetermined standard diameter . this embodiment uses 4 - bit gray code ( reflected binary code ), which logically represents the absolute code pattern 32 as follows : ______________________________________decimal code gray code______________________________________0 00001 00012 00113 00104 01105 01116 01017 01008 11009 1101______________________________________ the logical value of the circular patterns 32a - 32h is formed by a shading pattern in the rows of slits . on the other hand , as shown in fig3 the fixed slit board 20 has incremental signal detection slits 40a and 40b , timing signal detection slits 42 , absolute signal detection slits 44a - 44h and luminous energy compensation slits 46a and 46b . the incremental signal detection slits 40a and 40b generate a - phase and b - phase incremental signals in cooperation with the incremental code pattern 30 on the rotating disk 14 . the output phase of the a - phase incremental signal deviates by ninety degrees from that of b - phase incremental signal . the timing signal detection slits 42 generate the timing signal in cooperation with the timing code pattern 34 on the rotating disk 14 . since the timing signal should rapidly rise or fall , the slits 42 are very narrow , as narrow as 30 microns each . there are five slits 42 to secure more luminous energy . on the other hand , the absolute signal detection slits 44a - 44h generate absolute signals a - h in cooperation with the circular patterns 32a - 32h on the rotating disk 14 . since the absolute signals a - h are issued using the timing pulses , the slits 44a - 44h can be as wide as 240 microns and sufficient luminous energy can be secured . the timing signal changes at a half interval of the absolute signal h . the rotating disk 14 and the fixed slit board 20 are fixed in the housing 8 so that one circular signal pattern corresponds to each slit and the magnetic strip 26 faces the magnetic detection elements 28a and 28b . as shown in fig6 the light - receiving elements 22 issue signals when the rotating disk 14 rotates . in the circuit shown in fig4 these signals are turned into a 15 - bit digital signal b1 - b15 which represents the rotation angle . first , the timing signal and the gate - delayed timing signal are transmitted to an exclusive - or ( ex - or ) 50 to obtain a timing pulse . when the absolute signals a - h are fed into a d - flipflop circuit 52 and the timing pulse is fed to a clock terminal ck in the flipflop circuit 52 , the upper eight bits b8 - b15 of the rotation angle signal are delivered from the flip - flop circuit 52 . the a - phase and b - phase incremental signals , which deviate ninety degrees from each other , are fed into an updown identification circuit 54 . the circuit 54 determines whether the rotating disk 14 rotates forward or backward , and delivers an updown signal of zero when the disk 14 rotates forward and an updown signal of one when the disk 14 rotates backward . the a - phase and b - phase incremental signals are also fed to a frequency multiplier circuit 56 . the frequency multiplier circuit 56 delivers the pulse signal multiplied by four . subsequently , the updown signal is transmitted into the updown terminals d / u and preset terminals a1 - a4 of two 4 - bit updown counters 58 and 60 . a clock pulse is fed to a clock terminal ck in the first updown counter 58 . each time one clock pulse is fed , each bit increases or decreases by one . when the timing pulse is fed to the load terminals l of the updown counters 58 and 60 , each bit is set to zero when the rotating disk 14 rotates forward , and each bit is set to one when the disk 14 reverses . as a result , the lower seven bits b1 - b7 of the rotation angle signal are delivered from output terminals b1 - b4 of the first counter 58 and output terminals b1 - b3 of the second counter 60 . in this embodiment , output from the last output terminal b4 of the second counter 60 is not used . thus , the 15 - bit digital signal b1 - b15 is derived by obtaining bits b8 - b15 from the absolute signal and bits b1 - b7 from the incremental signal in response to the timing pulse . in this embodiment , when the timing pulse is generated , the absolute signal is received and the incremental signal is initialized . consequently , the rotation angle can be detected with high resolution and precision using the incremental signal . on the other hand , the number of rotations is detected by processing two standard position signals za and zb , which are detected by the magnetic detection elements 28a and 28b in fig1 in the circuit shown in fig4 . as shown in fig7 - bit digital signals are obtained by counting the number of pulses of the standard position signals za and zb . bit b15 is the most significant bit of the rotation angle signal . the number of rotations is detected as shown in fig7 . the standard position signals za and zb are detected by the magnetic detection elements 28a and 28b , and are fed into an updown identification circuit 70 . the updown identification circuit 70 determines whether the rotating disk 14 is rotating forward or backward , and delivers an updown signal of zero when the rotating disk 14 rotates forward and an updown signal of one when the disk 14 rotates backward . a pulse - waveform - shaping circuit 72 receives the standard position signals za and zb and delivers a pulse signal . the updown signal is sent to the updown terminal d / u of a 9 - bit updown counter 74 . the pulse signal is sent to the clock terminal ck of the updown counter 74 . subsequently , the updown counter 74 delivers the upper eight bits of nine bits counted into an adder 76 . on the other hand , an and gate 78 receives the least significant bit of the counted values , and the inverted signal of the most significant bit b15 of the rotation angle signal . the result from the and gate 78 is sent to a terminal co of the adder 76 , where the result is added to the upper eight bits of the counted value to obtain an 8 - bit rotation number r8 - r1 . as shown in fig7 when the most significant bit b15 of the rotation angle is one , the upper eight bits of the counted value represent the number of rotations . also , when the most significant bit b15 of the rotation angle signal is zero and the least significant bit of the counted value is zero , the upper eight bits of the counted value represent the number of rotations . however , when the most significant bit 15 of the rotation angle signal is zero and the least significant bit of the counted value is one , the number of rotations is obtained by adding one to the upper eight bits of the counted value . another embodiment is now explained with reference to fig5 . this second embodiment has the same signal detecting system as that of the first embodiment , shown in fig1 - 3 , and processes the same signals as those of the first embodiment , shown in fig6 - 7 . in the second embodiment , the upper eight bits of the rotation angle signal are calculated in a signal detecting system 102 in the same way as in the first embodiment as follows . first , the timing signal and the gate - delayed timing signal are transmitted in an exclusive - or gate ( ex - or ) 150 to obtain timing pulses . when the absolute signals a - h are fed into a d - flipflop circuit 152 and the timing pulse is fed to a clock terminal ck in the flipflop circuit 152 , the upper eight bits b8 - b15 of the rotation angle signal are delivered from the flipflop circuit 152 . in the second embodiment , the number of rotation is calculated in the signal detecting system 102 in the same way as the first embodiment as follows . the standard position signals za and zb are detected by the magnetic detection elements 28a and 28b shown in fig1 and are fed into an updown identification circuit 160 . the updown identification circuit 160 determines whether the rotating disk 14 rotates forward or backward , and delivers an updown signal of zero when the rotating disk 14 rotates forward and an updown signal of one when the disk 14 rotates backward . a pulse - waveform - shaping circuit 162 receives the standard position signals za and zb and delivers a pulse signal . the updown signal is sent to the updown terminal d / u of a 9 - bit updown counter 164 . the pulse signal is sent to the clock terminal ck of the updown counter 164 . subsequently , the updown counter 164 delivers the upper eight bits of nine bits counted into an adder 166 . on the other hand , an and gate 168 receives the least significant bit of the counted values , and the inverted signal of the most significant bit b15 of the rotation angle signal . the result from the and gate 168 is sent to a terminal co of the adder 166 , where the result is added to the upper eight bits of the counted value to obtain an 8 - bit rotation number r8 - r1 . as shown in fig7 when the most significant bit b15 of the rotation angle is one , the upper eight bits of the counted value represent the number of rotations . also , when the most significant bit b15 of the rotation angle signal is zero and the least significant bit of the counted value is zero , the upper eight bits of the counted value represent the number of rotations . however , when the most significant bit 15 of the rotation angle signal is zero and least significant bit of the counted value is one , the number of rotations is obtained by adding one to the upper eight bits of the counted value . as aforementioned , in the second embodiment , the upper eight bits of the rotation angle signal and the timing pulse are converted to 9 - bit data in the same way as the first embodiment . however , unlike the first embodiment , in the second embodiment as shown in fig5 the 9 - bit data is converted to a serial signal by a parallel - to - serial converter 170 . the serial signal is delivered through a driver 172 to a lead wire 124c . the number of rotations is converted to a serial signal by a parallel - to - serial converter 174 . the serial signal is delivered through the driver 172 to a lead wire 124d . the detected a - phase and b - phase incremental signals are delivered through the driver 172 to lead wires 124a and 124b , respectively , without being converted . a signal processing system 180 converts the serial signals to parallel signals and calculates the lower seven bits b7 - b1 of the rotation angle signals . first , signals are transmitted through the lead wires 124a - 124d to a receiver 182 . the serial - to - parallel converters 184 and 186 receive the serial signals from the lead wires 124c and 124d , convert the serial signals into the timing pulse , the upper eight bits b15 - b8 of the rotation angle signal , and the eight bits r8 - r1 of the number of rotations . in the same way as the first embodiment , the a - phase and b - phase incremental signals are fed into an updown identification circuit 190 . the circuit 190 determines whether the rotating disk 14 rotates forward or backward , and delivers an updown signal of zero when the disk 14 rotates forward and an updown signal of one when the disk 14 rotates backward . the a - phase and b - phase incremental signals are also fed to a frequency multiplier circuit 192 . the frequency multiplier circuit 192 delivers the pulse signal multiplied by four . subsequently , the updown signal is transmitted into the updown terminal d / u and the preset terminals a1 - a4 of two 4 - bit updown counters 194 and 196 . the pulse signal is fed to the clock terminal ck in the first updown counter 194 . when the timing pulse is fed to the load terminals l of the updown counters 194 and 196 , each bit is set to zero when the rotating disk 14 rotates forward , and each bit is set to one when the disk 14 rotates backward . each time one pulse signal is sent , each bit increases or decreases by one . as a result , the lower seven bits b1 - b7 of the rotation angle signal are delivered from output terminals b1 - b4 of the first counter 194 and output terminals b1 - b3 of the second counter 196 . in the second embodiment also , the output from the output terminal b4 of the second counter 196 is not used . thus , the 15 - bit digital signals b1 - b15 is derived by obtaining bits b8 - b15 from the absolute signal and bits b1 - b7 from the incremental signal . this signal processing system 180 delivers a 15 - bit rotation angle signal and an 8 - bit number - of - rotations signal . the delivered information is transmitted , for example , to a motor controller , and is used for control . in the compound rotary encoder for the second embodiment , the signal detecting system 102 is connected with the signal processing system 180 by only four lead wires 124a - 124d . however , this compound rotary encoder can detect the rotation angle and the number of rotations with high resolution and high precision . in the second embodiment , when the timing pulse is generated , the absolute signal is read and the counted value of the incremental signal is initialized . the rotation angle information based on the absolute signal is thus synchronized with the number - of - rotations information based on the incremental signal . the rotation angle information can be precisely detected from the incremental signals with high resolution . the lower seven bits of the rotation angle signal can be obtained from the incremental signals with high resolution without delay , because the bits are not converted in the serial - to - parallel converter . in these embodiments , when the number of rotations is detected , the standard position signals za and zb are first changed to 9 - bit digital signals . subsequently , the upper eight bits of the digital signal are compensated using the least significant bit of the 9 - bit digital signal and the most significant bit of the rotation angle signal . thus , the number of rotations is obtained . consequently , when the pulse is generated from the standard position signals za and zb , and the most significant bit b15 of the rotation angle signal does not change , the correct number of rotations can be detected . the magnetic detection elements 28a and 28b can be precisely mounted quickly and easily . output values may fluctuate some . the encoder can be assembled and adjusted in short time . the reliability of the encoder is enhanced . since the prior - art absolute rotary encoder delivers the rotation angle signals as 15 - bit digital signals , at least fifteen circular patterns are required . however , in these embodiments , by combining the absolute code pattern with the incremental code pattern , the rotation angle signal can generate the 15 - bit digital signal with high precision using fewer circular patterns . since the number of circular patterns is minimized , the rotary encoder for these embodiments can be compact . moreover , fewer circular patterns permit a larger diametrical width for each circular pattern , and each signal can be precisely detected . one rotary encoder can detect the rotation angle and the number of rotations at the same time ; thus , the number of components in use can be decreased . furthermore , the rotation angle information is used for detecting the number of rotations . consequently , the detected rotation angle information corresponds to the detected rotation number information . in these embodiments , the rotation angle is optically detected , but it could also be detected magnetically . alternatively , part of the code patterns could be optically detected , and remaining patterns could be magnetically detected . conversely , the rotation number signal could be optically detected . the absolute code patterns for these embodiments are based on gray code , but they could be based on any other code . these are only two possible embodiments of the invention claimed below . these embodiments are only illustrations of the claims , and in no way restrict the scope of the claims .