while the present invention will be illustrated with reference to a particular power supply , having particular components , and used in a particular environment , it should be understood at the outset that the invention may also be implemented with other power supplies , components , and used in other environments . referring now to fig1 , a welding power source 100 includes an input circuit 101 , a preregulator 102 , an output circuit 103 , a controller 104 , a controller power supply 105 , and an aux power supply 106 . input circuit 101 receives input utility or generator power , and provides a signal to preregulator 102 . the input is ac , and the input circuit includes a rectifier and capacitor bank in the preferred embodiment . thus , the output of the input circuit is a dc ( uni - polar ) signal , having a frequency twice that of the input frequency . input circuit 101 is comprised of other components in alternative embodiments . preregulator 102 receives the signal from input circuit 101 and provides preregulated signal . preregulator 102 includes a boost converter and boosts the rectified signal to be a dc bus ( about 800 vdc ) in the preferred embodiment . preregulator 102 is controlled so that , regardless of the input , the dc bus voltage is about 800 v . thus , the magnitude of the dc bus voltage is independent of input magnitude . ( as used herein a second voltage is independent of first voltage when magnitude of the second voltage is controlled to be a value which is not proportional to or a function of the first voltage ). also , the dc bus frequency ( substantially zero , but with ripple ) is independent of the input frequency . ( as used herein a second voltage is independent of first voltage when magnitude of the second voltage is controlled to be a value which is not proportional to or a function of the first voltage ). preregulator 102 includes other types of converters , such as an inverter , a series resonant converter , etc ., in other embodiments . converter , as used herein , includes a power circuit that receives or provides an ac or dc signal , and converts it to the other of an ac or dc signal , or to a different frequency . inverter , as used herein , includes a power circuit that receives or provides a dc bus signal that is inverted to be an ac signal . if a dc input signal is received , input circuit 101 simply passes the dc signal to preregulator 102 , or is omitted altogether . if the dc input signal is of a sufficient magnitude , preregulator 102 may pass simply provide the dc input as the dc bus , or be omitted altogether . output circuit 103 receives the dc bus and provides an output suitable for welding / heating / cutting . output circuit 103 includes , in the preferred embodiment , an inverter , followed by a transformer , followed by a rectifier and an output inductor . the output power is also frequency and voltage independent of the dc bus and the input signal . output circuit 103 is comprised of other components in other embodiments , and may provide an ac or dc output . controller 104 includes control circuitry similar to that known in the prior art , and causes the boost and inverter switches to switch in response to feedback and a setpoint ( such as 800v for the boost converter and a user setpoint for the output inverter ). control power is provided to the controller by controller power supply 105 . controller power supply 105 derives power from the output of preregulator 102 , in the preferred embodiment . controller power supply 105 includes a buck converter that steps down the 800v to 15v dc . the magnitude and frequency of the output of controller power supply is thus independent of the dc bus , and the input power . it is easily seen that , once the 800v dc bus is present control power is easily derived from the bus rather than from a control power transformer , any input voltage and frequency is acceptable . thus , linking , such as adjusting transformer taps , need not be performed . the circuitry that controls preregulator 102 , output circuit 103 and controller power supply 105 is collectively called controller 104 because of the common function ( controlling ). however , in practice they may form distinct and remotely located circuits , they may share circuitry , they may reside in a common microprocessor or dsp , and they may share control signals and feedback . one potential difficulty at start up is a result of the switching of the buck converter in controller power supply 105 being controlled by controller 104 : the 800v dc bus is not created until the controller causes the boost converter switch to switch on and off , but the controller cannot control the switch until it has power , and the power for the controller is derived from the dc bus . this difficulty is overcome in the preferred embodiment because even before the boost converter begins to switch to create the 800v dc bus , the dc bus will have the same magnitude as the rectified input voltage , which is typically at least 110v rms . since the buck converter steps down the bus voltage to 15v dc , even a relatively low magnitude input voltage ( 110v ac e . g .) is sufficient to create the controller power . also , control power for the buck converter is derived from a floating 15 volt supply , by bleeding current from the bus . the start up sequence will be described in detail below , but generally is as follows . at start up the dc bus quickly rises to the rectified input voltage , through a precharge resistor . the precharge resistor is bypassed after the bus is charged . current bled from the bus charges capacitors which provide power for the buck converter controller . the buck converter controller controls the buck converter , causing it to produce 15v dc power for all of controller 104 . controller 104 controls the boost converter in preregulator 102 to step up the rectified input and produce an 800v dc bus . thus , the 800v dc bus is created , and can provide power to output circuit 103 when the user begins to weld . additionally , aux power supply 106 includes an inverter , and produces a synthetic aux power , i . e ., a desired output voltage at a desired output frequency ( 110v ac at 60 hz , e . g .). controller 104 also controls aux power supply 106 . input circuit 101 , preregulator 102 , output circuit 103 , and the portions of controller 104 that control them , are implemented using the circuitry shown in u . s . pat . no . 5 , 601 , 741 ( and correspond to like numbered features of the drawings therein ) in one embodiment . however , a wide variety of circuits may be used to implement this part of the present invention , and the details of will not be described in detail herein . a particular switching circuit is used for the preregulator in another embodiment because it provides for efficient slow voltage switching and slow current switching . this circuit is described in patent application ser . no . 09 / 111 , 950 , filed , jul . 9 , 1998 , entitled power converter with low loss switching , and owned by the owner of this invention . slow voltage / current transitions or switching ( svt and sct ) as used herein , describe transitions where the voltage or current rise is slowed ( rather than held to zero ), while the switch turns off or on . the circuit used in the preferred embodiment to implement preregulator 102 is shown in fig2 ( along with input circuit 101 and voltage source 109 ). the embodiment of fig2 uses a 90 – 250 volt ac power line as input voltage 109 . input circuit 101 is comprised of diodes d 60 , d 70 , d 80 , and d 9 , which rectify the input voltage to provide a single polarity sinusoidal input voltage . a power factor correction portion ( described below ) of preregulator 102 functions best when the input , voltage is sinusoidal , although it could be another alternating input . thus , a small ( 10 μf ) capacitor ( not shown ) is provided across the input rectifier in one embodiment to smooth the input line voltage . the rectified input voltage is applied to a boost inductor l 10 ( 750 μh ) which is connected with a boost switch z 1 ( preferably an igbt ) to form a boost convertor . an anti - parallel diode d 50 is connected across switch z 1 to protect switch z 1 during transitions . the portion of the circuit which provides the lossless switching includes a snubber inductor l 2 ( 3 . 9 μh ) a pair of capacitors c 100 ( 1 μf ) and c 200 ( 0 . 068 μf ), and diodes d 10 , d 20 , d 30 , and d 40 . switch z 1 is switched in a known manner such that the output of preregulator 102 is a desired voltage , no matter what the input voltage is . the output is provided across a capacitor c 50 ( 2000 μf ) that provides a stable voltage source ( 200 volts in the preferred embodiment ) for the downstream convertor . also , capacitor c 50 prevents the voltage from being dangerously high and damaging switch z 1 . the portion of preregulator 102 that provides power factor correction is a power factor correction circuit 204 ( fig2 ), and generally senses the input voltage waveform , and conforms the shape of the current waveform to be that of the line voltage waveform . this provides a power factor of very close to 1 , 0 . 99 in the preferred embodiment . power factor correction circuit 204 may be implemented using an integrated circuit , such as a uc3854 or an ml4831 , or with discrete components , such as those shown in the above - referenced power converter with low loss switching , incorporated herein by reference . power factor correction circuit 204 receives as inputs the output voltage from input circuit 101 , the output voltage from preregulator 102 , and the output current of preregulator 102 ( using a ct ). because the frequency of preregulator 102 ( 25 khz ) is much higher than that of the line ( 60 hz ) the pre - regulator current can be made to track the input line voltage shape by sensing the shape of the input voltage , and controlling the input current in response thereto . output circuit 103 can include a conventional inverter , output transformer , output rectifiers , and an output - inductor such as in u . s . pat . no . 5 , 601 , 741 . however , in one embodiment , the inverter is a switched snubber , such as that described in power converter with low loss switching , and shown in fig3 . the invertor implemented with a switched snubber includes a dc voltage source 1501 , a pair of switches 1502 and 1504 , with a pair of anti - parallel diodes 1503 and 1505 , a pair of capacitors 1507 and 1508 ( 1410 μf ), a transformer 1509 , a capacitor 1512 ( 0 . 099 μf ), an output - rectifier including diodes 1510 and 1511 , and an output inductor 1513 . capacitor 1512 is switched across transformer 1509 by switches 1502 and 1504 . switches 1402 and 1403 are used to soft switch switches 1502 and 1504 . switches 1402 and 1403 do not need any special timing , and run with the main clock at effectively 50 % duty cycle . for example , switches 1502 and 1402 turn on together , and switch 1502 delivers current to transformer 1509 , while switch 1402 does nothing . when switch 1502 turns off , switch 1402 remains on , and current is directed through switch 1402 and diode 1405 into capacitor 1512 , thus giving an svt ( slow voltage transition ) turn off . switch 1402 is turned off after the transition and diode 1405 prevents the back flow of current from capacitor 1512 . this occurs in complimentary fashion with switches 1502 and 1402 and diode 1405 . thus , this circuit provides full - wave transformer usage , pwm control , complete capacitor balance control with no extra circuitry , and efficient use of switches with svt . an alternative embodiment includes using a full bridge version of the snubber . the specific circuitry used to control the switched snubber may be conventional control circuitry , such as that described in power converter with low loss switching . a circuit used to implement controller power supply 105 , and a portion of controller 104 that controls controller power supply 105 is shown . controller power supply 105 includes a buck converter in the preferred embodiment , and includes a switch 401 , a freewheeling diode 403 and a buck inductor l 1 , configured in a conventional buck arrangement , and a resistor 404 ( 0 . 5 ohms ). the circuitry that controls the buck converter ( or regulator ), in the preferred embodiment , is also shown on fig4 , and is part of controller 104 . one skilled in the art will readily recognize that the control circuitry may be located on the same control board as the portion of controller 104 that controls preregulator 102 and output circuit 103 , or it may be located remotely therefrom , for example on the pc board for controller power supply 105 . generally , the buck converter is controlled such that at startup current is bled from the dc bus to charge a capacitor , thus providing sufficient power to turn on and off the buck switch . the voltage across the capacitor is a floating voltage and is sufficient to operate the buck converter control circuitry . the control circuitry causes the buck switch to turn on and off repeatedly to create a control power of about 15 volts dc . the 15 volts dc is then used to power the remaining control circuitry . more specifically , when the power supply is turned on the dc bus will have a voltage equal to the peak voltage of the input rectified signal ( about 200 volts dc for an input having 140 volts rms , e . g .). current bleeds from the bus through a pair of resistors r 5 ( 150 kohms ) and r 4 ( 150 kohms ) to charge a pair of capacitors c 5 ( 0 . 1 μf ) and c 2 ( 100 μf ). the voltage across capacitors c 2 and c 5 is called the buck − com and buck + 15v , and is the floating voltage supply for the circuitry that controls the buck converter , proper selection of the resistance of resistors r 5 and r 4 ( and other components described below ) determines the minimum voltage needed on the dc bus to operate the buck converter control circuitry . in the preferred embodiment the minimum voltage is no higher than that obtained by rectifying 110v ac power . when the voltage across capacitors c 5 and c 2 reaches approximately 11 . 7 volts a switch q 1 turns on , switch q 1 is used to enable ( or disable ) the logic or control circuitry for the buck converter . when the voltage across capacitors c 2 and c 5 is less than about 11 . 7 volts , then switch q 1 off , and the logic circuitry is disabled . a resistor r 2 ( 10 kohms ), a resistor r 3 ( 100 kohms ) and a zener diode d 1 ( 11 volts ) are associated with switch q 1 , and create the turn on voltage . thus , the resistance of resistor r 3 also sets the minimum voltage needed to operate the circuitry that controls the buck controller . the logic circuitry includes a plurality of nand gates u 4 a , u 4 b , u 4 c , and u 4 d , and associated circuitry capacitors c 1 ( 0 . 1 μf ) and c 3 ( 0 . 001 μf ), resistors r 6 ( 20 kohms ), r 7 ( 332 kohms ) and r 8 ( 20 kohms ). this circuitry controls a plurality of paralleled not gates u 3 , whose output is the on / off signal to the - base of buck switch 401 , through a resistor r 12 ( 10 ohms ). the supply voltage for the logic circuitry is the floating buck − com / buck + 15v voltage supply . when not gates u 3 output is 1 , buck switch 401 is on , and when not gates u 3 output is 0 , buck switch 401 is off . not gates u 3 output is 1 when their input is 0 , which requires both inputs of nand gate u 4 d to be 1 . at start up , before the bus charges the buck − com / buck + 15v voltage supply to 11 . 7 volts switch q 1 is off . thus , an input to nand gate u 4 a is 0 , and the output of nand gate u 4 a is 1 . this output is fed through diode d 3 and resistors r 6 and r 7 to the inputs pin 2 of nand gate u 4 b , and the output of nand gate u 4 b is thus 0 . the output of nand gate u 4 b is fed to input pin 2 of nand gate u 4 a , thus holding the output of nand gate u 4 d high ( and holding switch 401 off ). also , at start up the output of nand gate u 4 c is 1 because both its inputs from nand gate u 4 b is 0 . when the bus charges the buck − com / buck + 15v voltage supply to 11 . 7 volts switch q 1 is turned on , and input pin 9 of nand gate u 4 a goes high , thus enabling the output of nand gate u 4 a to go low , and enabling the output of nand gate u 4 b to go high and the output of nand gate u 4 d to turn on switch 401 ( through gates u 3 ). also , when the output of nand gate u 4 a goes to 0 , capacitor c 3 discharges through resistor r 7 ( with a relatively long rc time constant ). when capacitor c 3 has discharged , the output of nand gate u 4 b goes to 1 causing the output of nand gate u 4 d to go 0 , turning on buck switch 401 . the associated circuitry causes the logic to latch until input pin 8 of nand gate u 4 a goes to zero . this happens because when switch 401 is on current through inductor l 1 increases , turning on a switch q 3 through a pair of resistors r 11 ( 2 kohms ) and r 10 ( 100 kohms ) and a capacitor c 4 ( 0 . 001 μf ). when switch q 3 is turned on , input pin 8 of nand gate u 4 a is 0 and the output of nand gate u 4 d is 1 , causing ( eventually ) the output of nand gate u 4 b to be 0 , the output of nand gate u 4 c to be 1 , and the output of nand gate u 4 d to be 1 , turning off switch 401 . the process of turning switch 401 on and off is repeated , and limited after the necessary 15v dc bus is created on a pair of outputs precom and pre + 15v . the current through inductor l 1 charges a pair of capacitors c . 13 and c 14 ( 2200 μf ). outputs precom and pre + 15v are connected across capacitors c 14 and c 14 , thus , when they have charged to + 15v , the needed control power is provided . a zener diode d 5 prevents the magnitude of the voltage across outputs precom and pre + 15v from getting to high . a resistor r 13 ( 1 kohm ), a pair of zener diodes d 5 and d 2 ( 6 . 8v ), an opto - isolator oc 3 , and a resistor r 1 ( 1 mohm ) limit the turning on of buck switch 401 when the voltage across outputs precom and pre + 15v reaches 15 volts . when the voltage drop across diodes d 5 and d 6 and opto oc 3 reaches 15 volts , opto oc 3 turns on , pulling up the inputs to nand gate u 4 b , turning off switch 401 . a circuit used to implement aux power supply 106 , and a portion of controller 104 that controls aux power supply 106 is shown in fig5 . one skilled in the art will readily recognize that the control circuitry may be located on the same control board as the portion of controller 104 that controls preregulator 102 and output circuit 103 , or it may be located remotely therefrom , for example on the pc board for aux power supply 106 . aux power supply 106 includes an inverter in the preferred embodiment , and operates much like a motor drive , or typical ac inverter circuit ( the output follows a pattern of high , zero and negative , zero , high , zero , . . . ). the output is , in the preferred embodiment , a synthetic ac , 60 hz , 575v supply ( dependent on magnitude of the 800v bus ). the 575 volt supply may be transformed to any desired magnitude . alternatively , the magnitude may be controlled to a lower value by having a different bus value , or by bucking the bus value down to a desired level . the regulated level could be preset or user selected . also , the frequency can be user selected ( 50 or 60 hz e . g .) or preset . the inverter includes 4 switches 501 – 505 , which are turned on and off to produce ac power on a pair of outputs ac / 2 and ac / 1 . specifically , normally switches q 3 and q 4 are on and freewheeling ( when there is no applied voltage difference across outputs ac / 1 and ac / 2 ). ac / 1 is made high ( and ac / 2 low ) by - turning switch 502 on and switch 504 off . thus , the conduction path is from the bus , through switch 502 , to ac / 1 and the load , and then from ac / 2 through switch 503 to ground ( precom ). conversely , ac / 1 is made low ( and ac / 2 high ) by turning switch 501 on and switch 503 off . thus , the conduction path is from the bus , through switch 501 , to ac / 2 and the load , and then from ac / 3 through switch 504 to ground ( precom ). the remaining circuitry on fig5 is control circuitry , and is powered by precom and pre + 15v . the circuitry operates in a conventional manner and includes drive circuitry level shifters , current limiters and an enable circuit . the gate drives for the switches operate in a conventional fashion , and include resistors r 16 ( 10 ohms ), r 17 ( 5 . 11 kohms ), r 18 ( 1 mohms ), r 19 ( 22 . 1 ohms ), r 20 ( 10 ohms ), r 21 ( 1 mohms ), r 22 ( 5 . 11 kohms ), r 23 ( 22 . 1 ohms ), r 24 ( 2 kohms ), r 25 ( 2 kohms ), r 26 ( 2 kohms ), r 27 ( 2 kohms ), r 28 ( 20 kohms ), r 29 ( 20 kohms ), r 30 ( 20 kohms ), and r 31 ( 20 kohms ), capacitors c 6 ( 100 μf ), c 7 ( 0 . 1 μf ), c 10 ( 100 μf ), c 11 ( 0 . 1 μf ), switches q 6 , q 7 , q 8 , q 9 , q 10 and q 11 , diodes d 61 and d 7 , and opto - isolators oc 1 and oc 2 . latch circuitry current limits each cycle , and operates in a conventional fashion . the latch circuitry includes level shifter u 1 a ( 40109 ), gates u 2 a , u 2 b , u 2 c , u 2 d , resistors r 32 ( 22 . 1 kohms ), r 33 ( 22 . 1 kohms ), r 34 ( 20 kohms ), r 35 ( 20 kohms ), r 36 ( 3 . 01 kohms ), r 37 ( 5 . 11 kohms ), r 38 ( 16 kohms ), r 39 ( 1 kohms ) and r 40 ( 20 kohms ), a capacitor c 15 ( 0 . 000 μf ) and a pair of switches q 12 and q 13 . a pair of level shifters u 1 b and u 1 c ( 40109 ) are also provided . an enable circuit includes opto - isolator oc 4 , resistors r 41 ( 1 mohms ) and r 42 ( 20 kohms ), and capacitor c 16 ( 0 . 1 μf ). a voltage regulator circuit includes voltage regulator vr 1 , capacitor c 18 ( 0 . 1 μf ), capacitor c 17 ( 0 . 1 μf ) and regulator vr 1 , and produces a regulated + 5v supply form the + 15v supply generated by the buck regulator . a timing circuit sets the clock - for the control circuitry and aux frequency . the timing circuitry includes a microprocessor mpu1 , capacitor c 19 ( 22 μf ) and capacitor c 20 ( 22 μf ), a crystal oscillator y 1 ( 4 . 096 mhz ), and a level shifter u 1 d . these components cooperate in a known manner to produce the desired 575v ac , 60 hz output . as stated above , the circuit could be modified to allow the user to select the voltage magnitude and / or frequency . numerous modifications may be made to the present invention which still fall within the intended scope hereof . thus , it should be apparent that there has been provided in accordance with the present invention a method and apparatus for providing welding type power from any typical input voltage or frequency that fully satisfies the objectives and advantages set forth above . although the invention has been described in conjunction with specific embodiments thereof , it is evident that many alternatives , modifications and variations will be apparent to those skilled in the art . accordingly , it is intended to embrace all such alternatives , modifications and variations that fall within the spirit and broad scope of the appended claims .