fig1 shows one circuit embodiment of the invention that will be used for the detailed description . capacitors 11 and 15 may be connected in the configuration shown , with i / o connections a , b , and c . capacitor 11 is formed by plates 12 and 13 , and capacitor 15 is formed by plates 16 and 17 . this capacitor pair is shown implemented using an interdigitated interconnect structure in fig2 . substrate 21 represents any known ic substrate including but not limited to silicon , gallium arsenide , indum phosphide or an ipd substrate such as ceramic . the substrate is shown cut - away indicating that this is a portion , typically a small portion , of a larger substrate or wafer . due to processing variables , it is not uncommon for the thickness of the blanket layer that is patterned to form the discrete interdigitated devices 11 and 15 in fig2 to vary over the surface of the substrate . in ic device manufacture , the substrate is typically a silicon wafer with a plurality of identical die formed in a repeated pattern on a surface of the wafer . state of the art wafers may be as large as 12 ″ ( 300 mm ) in diameter . thousands of ic devices are produced from a single wafer . in ipd manufacture , the substrate is typically an insulating substrate , for example , ceramic . the device sites for ipds are characteristically larger than for ic die or chips . in each case , any layer that is deposited over the whole substrate will vary in thickness in the x - y plane of the substrate or wafer . this thickness variation is indicated by the arrow , and “ δt ”, in the y or vertical direction of fig2 . similar thickness variations also occur in an orthogonal , x direction of fig2 . it means that the layers that form capacitor 11 may have a thickness different from the layers that form capacitor 15 . in that case the capacitance of capacitor 11 will be different from the capacitance of capacitor 15 . if the variations indicated by δt are significant , making a matched pair of capacitors will be difficult or impossible . an interdigitated capacitor pair with a common interleaved plate according to one embodiment of the invention is shown in fig3 . the substrate 26 may be an ic wafer , or an ipd substrate , the surface of which typically is covered with an insulating layer , for example sio 2 for a silicon wafer . in this layout the electrode structure 22 corresponds approximately to electrode structure , or plate , 12 of fig1 and 2 , and electrode structure 27 corresponds approximately to electrode structure , or plate 17 of fig1 and 2 . each capacitor plate 22 and 27 has a comb structure with the fingers of plate 22 interdigitated with the fingers of plate 27 . plates 13 and 16 of fig1 and 2 have been combined as a common interleaved plate 31 . interdigitated structure 22 is connected as node a , interdigitated structure 27 is connected as node b , and interleaved structure 31 is connected as node c . as shown in fig3 , the spacing between edges of interleaved runner c and edges of the fingers of plates 22 and 27 ( shown as “ x ” in fig4 ) may be less than the spacing between edges of interleaved runner c and edges of the portions of plates 22 and 27 that do not form the fingers ( shown as “ p ” in fig3 ). providing a different spacing in the two regions lessens the capacitance between the portions of interleaved runner c that provide direction reversals and the non - finger portions of plates 22 and 27 , resulting in better control of the capacitance , and of the resulting matched capacitor pair . a recommended , but not required , range for the ratio p / x is 3 to 20 . the capacitor plates 12 , 13 , 16 and 17 , are preferably formed from a single level of interconnect . it may be any convenient interconnect level . the metal may be any suitable conductive material , metal or compound , including but not limited to al , cu , au , ni , ta , ti , tan , tin , wn , si , pt , or combinations thereof for example sillicides . from a process standpoint , it is most convenient to form the capacitor plates from the same metal used for interconnecting or fabricating other devices on the ic . a metal layer is blanket deposited on the substrate , or on any of the interlevel dielectric layers of the ic , and patterned by conventional photoresist techniques to form both the device interconnections for that level , and the capacitor plates shown in fig3 . if desired , and also within the scope of the invention , a separate step may be used to deposit and pattern a layer to form the capacitor plates . in that case a different metal may be used for the ic interconnects and the capacitor plates . also within the scope of the invention is the use of different metals to form the various interdigitated structures of the capacitor . this option is most likely to be used in multi - level structures , such as those described in more detail below . the interdigitated metal pattern shown in fig3 is covered with a dielectric layer that fills the space between the interdigitated metal runners to form the dielectric between the capacitor plates , thus forming the capacitor pair . the dielectric layer may also serve as the interlevel dielectric between metal levels . for silicon wafers , preferably the dielectric layer is sio 2 , but other insulating materials , such as silicon nitride , or even a polymer such as polyimide , may be used . one skilled in the art would know what dielectric materials to use for other than silicon wafers . other step sequences may be used to reach the same or similar results . the blanket metal layer may be deposited , as well as a blanket dielectric layer , and the combined layers patterned to form the interdigitated structure . this may be a more likely sequence in producing ipds . in the usual ic manufacturing process , where transistor devices are part of the ic structure , the metal layers are often patterned prior to depositing the interlevel dielectric . however , either of these step sequences , as well as others , is useful . in state - of - the - art integrated circuits with , for example , a 0 . 13 micron design rule , the runners are very small and the space between interdigitated runners is small . continuing the 0 . 13 micron design rule example , interdigitated runners 12 , 13 , 16 and 17 in fig2 may have a width of 0 . 16 to 0 . 5 microns , a thickness of 0 . 2 to 1 . micron , and a spacing of 0 . 18 to 0 . 55 microns . the efficiency of the layout of the capacitor pair in fig3 , when compared with that of fig2 , is evident . moreover , it is intuitively apparent that variations like δt will have an equivalent influence on both capacitors . this allows matched capacitor pairs to be produced even when process conditions cause significant variations in δt . fig3 as shown may be a single level capacitor , or it may have additional levels above or below that shown where added capacitors may be stacked . a stacked interdigitated device is represented in the schematic of fig4 . the levels 1 - 5 indicate levels of metalization in an ic or ipd device . the first level , the first layer that is formed on the substrate ( not shown ), is the bottom level of the finished structure . in fig4 , the first level corresponds to a section through 4 - 4 of fig3 . for clarity , not all of the runners that appear in fig3 are depicted in fig4 , but the pattern is evident . each subsequent level is formed as shown . typically each level will be identical to , or similar to , the level shown in fig3 . the stacked device embodiment may be used for at least two useful options . the matched capacitor pair at each level may be utilized in an ic or ipd and interconnected with other devices thereon as a separate matched pairs of capacitors , meaning that five separate matched pairs of capacitors may be formed in the same die area that is occupied by the device of fig4 . this option offers the possibility that each matched pair of capacitors may be different physically than the matched pair of capacitors of the other layers such as having a different interdigitated structure resulting in different capacitance than the matched pairs of capacitors of the other layers . another option for this structure is to interconnect the “ a ” plates from each level , as well as the “ b ” and “ c ” plates respectively . when the capacitance of the matched pair of capacitors of each level are identical , this results in a matched capacitor pair with n times the capacitance of a matched pair of capacitors made on a single level . in fig4 , n is five as five levels are illustrated . a convenient method for implementing this embodiment is to provide through hole interconnections between corresponding plates of adjacent levels . in fig4 , interconnections between corresponding plates at each level 1 - 5 are shown at 41 . for the purpose of illustration only , five metalization levels are represented in the ic device depicted in fig4 . that suggests that the ic device depicted has at least five - level metalization . obviously , the ic may have more or fewer levels of metal , all or less than all of the metalization layers may be used to fabricate matched capacitors . alternatively , the matched capacitor pair shown may be part of a passive device section on the ic chip , a section that may have as many levels of metal as are convenient for fabrication of the passive device structures , independent of the metal levels in the active device region ( s ). the same holds true for ipds , where the number of levels in the stacked multi - level matched capacitor pair device may be whatever is needed or convenient . fig3 shows the matched capacitor pair a - c and b - c connected to other devices on the integrated circuit ( or to i / o leads in an ipd ) at one end of the capacitor pair . to improve high frequency performance it may be helpful to have distributed connections to the matched capacitor pair . fig5 shows the matched capacitor pair of fig3 with interconnections 35 to the “ back ” of the capacitor structure . the matched capacitor pair structures according to the invention offer convenient means for adjusting the capacitance ratio of capacitance a - c to capacitance b - c . the above illustrations have had a one - to - one ratio resulting in a matched capacitor pair . the ratio is varied by simply omitting a portion of the length of one of the interdigitated runners . fig6 shows a capacitor pair similar to that of fig3 , but with five interdigitated runners for capacitor a - c , and only three interdigitated runners for capacitor b - c . this yields a capacitor ratio a - c to b - c of five to three . whole finger portions of runners may be eliminated to adjust the ratio , as shown in fig6 , or as shown in fig7 , fractional parts of finger portions of runners may be left out , i . e . the finger portions of runners for one of the plates may simply be made shorter than the finger portions of runners for the other plate . in the embodiment shown in fig7 , where the finger portions of runners for plate b are shorter ( in the y - direction ) than the finger portions of runners for plate a , the capacitance ratio a - c to b - c is the ratio of the length of the fingers of runner a overlap with runner c , to the length of the fingers of runner b overlap with runner c . the resulting capacitors provide a proportional matched pair of capacitors . the proportional matched capacitor pairs of fig6 and 7 may also be designed with the plate - interleaved runner spacing shown in fig3 and the discussion thereof . as described in connection with fig3 , the dimension “ p ” in fig3 should exceed dimension “ x ” in fig4 in the manner described earlier . in the embodiment of fig6 , this allows greater control over the ratio of capacitances between the capacitor pair . in some circuit applications , the use of a common capacitor plate , i . e . plate 31 of fig3 , may be undesirable . a variety of options for splitting the common plate are available . two of these are shown in fig8 and 10 respectively . fig8 shows a matched capacitor pair with two interleaved intermediate plates , c 1 and c 2 . this structure allows the more familiar four electrode interconnection for the capacitor pair . the circuit may be designed to allow for the small capacitive coupling between c 1 and c 2 , or the space separating c 1 and c 2 may be suitably enlarged . fig9 shows a stacked version of the matched capacitor pair of fig8 . again , five levels are shown , with corresponding plates , and plates that are vertically aligned are interconnected by vias . as pointed out earlier , the vias are one option , as is the repetition of the pattern between levels . other arrangements may be used wherein the capacitance of the matched capacitor pairs differ between levels or where the plates on adjacent levels differ . among other options are to place resistors and / or inductors at some levels . in this manner whole ipd circuits may be built using two or more levels . or levels with passive device circuits may be used with levels with active devices . fig1 shows yet another embodiment wherein two interleaved interior capacitor plates are provided , thus providing two plates where there is a common interleaved plate 31 of fig3 . it will be recognized that the embodiment of fig1 is similar to that of fig8 , but the capacitive coupling between c 1 and c 2 is eliminated by a ground plane “ gr ”. the ground plane comprises an interleaved runner typically of the same material and dimensions as the runners c 1 and c 2 . the matched capacitor of fig1 shares the virtues of the embodiment of fig3 in terms of reduced susceptibility to δt for example , but with the added feature that it has a true four - node design , a , b , c 1 and c 2 , and the two capacitors are electrically isolated from one another . a stacked version of the matched capacitor of fig1 is shown in fig1 , with the ground plane “ gr ” isolating the interior plates c 1 and c 2 . although this embodiment is slightly more complex than that of fig4 , the electrical performance may be more suitable for some circuit applications . the matched capacitor pairs of fig8 and 10 may also be designed with different capacitances , resulting in a proportional matched pair of capacitors , using the techniques shown in fig6 or fig7 and the discussion thereof , or the plate - interleaved runner spacing shown in fig3 and the discussion thereof . the conductors that form the capacitor plates are referred to as runners . it will be recognized that in the capacitor structures of the invention , the edges or sides of the runners form the capacitor surfaces . thus , increasing the width of the runners does not increase capacitance . therefore , for space efficiency , the runners should be designed with a width the same as any other portion of the metalization that serves an interconnection function . that width will typically be the minimum dimension allowed by the design rule . the thickness of the runners does contribute to the capacitor value . however , an advantage of the devices described above is that they may be formed as part of the metalization levels already used to manufacture the ic device . in that case the thickness of the runners will have a thickness determined by the process design . that restriction may not be the case in ipd production . here the runner thickness may be adjusted to suit the capacitor design . taking all these factors into account , the aspect ratio , width / thickness , for the runners in the devices described here will most typically be in the range of 3 to 0 . 5 . other ratios may be found useful . it is noted here that the ratio of width to thickness of these runners will also affect the capacitor density , an additional factor to be taken into account . the structures described herein have features that are easily described heuristically , but a precise prescription of the generic base of the invention may be aided by additional definitions . each of the capacitor plates in the embodiments described comprises a main runner , and a plurality of side runners extending from the main runner to form a comb structure . the comb structure is evident in each of fig3 , 6 , 7 , 8 , and 10 . the side runners are analogous to the teeth of the comb , but in the context of an interdigitated arrangement , are referred to here as fingers of the comb . among other features of the invention the matched capacitor pairs and proportional matched capacitor pairs described herein comprise at least three capacitor plates , with two of the capacitor plates each having a comb structure , and the fingers of one comb structure interdigitated with the fingers of the other comb structure . the third capacitor plate extends , or is interleaved , between the two interdigitated plates . according to a common interpretation , the term interdigitated describes fingers from two sources that extend between each other with every other finger originating from a first one of the two source and the alternate fingers originating from the second of the two sources . with the outer plates of the capacitor defined above as having a comb structure , the devices may be described simply as a two - comb structure with the fingers of the combs interdigitated . the interdigitated fingers and interleaved capacitor plate have a spacing therebetween . because design rules change , it is preferable to prescribe the spacing as a ratio . although other spacings may be used , a recommended spacing “ s ”, as a ratio with the runner width “ w ”, is : another feature common to the embodiments shown is that runners that form at least some of the capacitor plates are boustrophedonic , that is , they follow a meandering or back - and - forth path . these are runners c 1 , c 2 , and the ground runner gr ( fig1 ). the boustrophedonic path changes direction in 90 ° increments , and to form a matched capacitor pair or a proportional matched pair of capacitors in a configuration according to the invention requires at least two path changes . thus in the context of the invention , a meandering or boustrophedonic path may be defined as one that turns through at least 180 °. it is noted that the paths shown in the figures comprise straight sections . other options may be found useful . the various configurations of the invention may alternatively be described by reference to the section views . thus the capacitor pair shown in fig3 comprises a planar structure having a plurality of runners , with a cross section normal to the runners having alternating runners in the sequence a , c , b , c , a , . . . wherein runners a , b , c are separated by insulator , and are , respectively , interconnected . the process steps for forming the structures described are conventional and straightforward . the fundamental steps comprise providing a substrate , the substrate either insulating , or covered with an insulating layer , depositing a metal layer on the substrate , and patterning the metal layer to form the metal runners . the metal may be deposited by any of a variety of known techniques , including evaporation , sputtering , plating , and chemical vapor deposition ( cvd ). the deposited metal layer may be patterned by conventional photolithography . to take advantage of the process compatibility feature of the invention , all of the metal patterns forming the capacitor plates may be formed in a single patterning operation . in addition , for ic manufacture , that single patterning operation forms the metalization pattern that is used to interconnect other elements of the integrated circuit on a given metalization level . the term “ other elements ” is meant to include resistors , inductors , transistors , diodes , etc . the matched capacitor pairs or proportional matched capacitor pairs fabricated as described above are fabricated as part of an ipd or a die and are interconnected to other components on the ipd or if on a die are interconnected to other components on the wafer . a plurality of identical die are typically formed in a repeated pattern on a surface of the wafer . the individual die are cut or diced from the wafer , then packaged as an integrated circuit . one skilled in the art would know how to dice wafers and package die to produce integrated circuits . integrated circuits so manufactured including matched capacitor pairs or proportional matched capacitor pairs are considered part of this invention . while the invention has been described mostly with respect to processing silicon wafers , the invention is not limited thereto . the invention may be formed using other processing technologies including but not limited to processing technologies to fabricate matched capacitor pairs or proportional matched capacitor pairs in gallium arsenide and indium phosphide wafers . various additional modifications of this invention will occur to those skilled in the art . all deviations from the specific teachings of this specification that basically rely on the principles and their equivalents through which the art has been advanced are properly considered within the scope of the invention as described and claimed .