embodiments of the inventive concept will be described hereinafter with reference to the accompanying drawings . however , the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the inventive concept . fig1 is a block diagram of a semiconductor memory device according to one embodiment . as illustrated in fig1 , semiconductor memory device may be configured to include a first data i / o block 1 and a second data i / o block 2 . the first data i / o block 1 may be configured to include a first pad 11 , a first input buffer 12 , a first write path unit 13 , a first read path unit 14 , a first monitor signal generator 15 and a first output unit 16 . the second data i / o block 2 may be configured to include a second pad 21 , a second input buffer 22 , a second write path unit 23 , a second read path unit 24 , a second monitor signal generator 25 and a second output unit 26 . the first input buffer 12 may buffer a first input data din 1 supplied through the first pad 11 to generate a first internal input data int_din 1 when the first data i / o block 1 operates in a write mode . the first write path unit 13 may drive a first global i / o line gio 1 to transmit the first internal input data int_din 1 to the first global i / o line gio 1 when the first data i / o block 1 operates in the write mode . the first write path unit 13 may also generate and output a write internal signal wt_int when the first internal input data int_din 1 is transmitted to the first global i / o line gio 1 . the first read path unit 14 may receive first internal output data rdata 1 and fdata 1 from data loaded on the first global i / o line gio 1 when the first data i / o block 1 operates in a read mode . the first monitor signal generator 15 may buffer a read internal signal rd_int to generate a first monitor signal ms 1 when a monitor enable signal m_en is enabled . the first output unit 16 may selectively output the first internal output data rdata 1 and fdata 1 or the first monitor signal ms 1 as a first output data dout 1 in response to the monitor enable signal m_en . the first output data dout 1 may be supplied through the first pad 11 . the first output unit 16 may output the first monitor signal ms 1 as the first output data dout 1 when the monitor enable signal m_en is enabled . the first output unit 16 may output the first internal output data rdata 1 and fdata 1 as the first output data dout 1 in synchronization with internal clock signals rclk and fclk when the monitor enable signal m_en is disabled . the monitor enable signal m_en may be enabled to monitor the write internal signal wt_int and the read internal signal rd_int . the second input buffer 22 may buffer a second input data din 2 supplied through the second pad 21 to generate a second internal input data int_din 2 when the second data i / o block 2 operates in a write mode . the second write path unit 23 may transmit the second internal input data int_din 2 to a second global i / o line gio 2 when the second data i / o block 2 operates in the write mode . the second read path unit 24 may receive second internal output data rdata 2 and fdata 2 from data loaded on the second global i / o line gio 2 when the second data i / o block 2 operates in a read mode . the second read path unit 24 may also generate and output the read internal signal rd_int when the second internal output data rdata 2 and fdata 2 are extracted from the data loaded on the second global i / o line gio 2 . the second monitor signal generator 25 may buffer the write internal signal wt_int to generate a second monitor signal ms 2 when the monitor enable signal m_en is enabled . the second output unit 26 may selectively output the second internal output data rdata 2 and fdata 2 or the second monitor signal ms 2 as a second output data dout 2 in response to the monitor enable signal m_en . the second output data dout 2 may be supplied through the second pad 21 . the second output unit 26 may output the second monitor signal ms 2 as the second output data dout 2 when the monitor enable signal m_en is enabled . the second output unit 26 may output the second internal output data rdata 2 and fdata 2 as the second output data dout 2 in synchronization with the internal clock signals rclk and fclk when the monitor enable signal m_en is disabled . fig2 is a circuit diagram of an example of first monitor signal generator 15 of the semiconductor memory device of fig1 . fig3 is a circuit diagram of an example of first output unit 16 of the semiconductor memory device of fig1 . as illustrated in fig2 , the first monitor signal generator 15 may be configured to have a nand gate nd 11 . the nand gate nd 11 may receive the monitor enable signal m_en and the read internal signal rd_int as two input signals thereof and may generate the first monitor signal ms 1 as an output signal thereof . when the monitor enable signal m_en is enabled to have a logic “ high ” level , the first monitor signal generator 15 may inversely buffer the read internal signal rd_int and may output the inversely buffered read internal signal rd_int as the first monitor signal ms 1 . the second monitor signal generator 25 may have the same or similar configuration as the first monitor signal generator 15 . that is , the second monitor signal generator 25 may also be configured to have a nand gate , and the nand gate may receive the monitor enable signal m_en and the write internal signal wt_int as two input signals thereof and may generate the second monitor signal ms 2 as an output signal thereof . as illustrated in fig3 , the first output unit 16 may be configured to include an internal data transmitter 161 , a monitor signal transmitter 162 , a latch unit 163 and an output driver 164 . the internal data transmitter 161 may inversely buffer the first internal output data rdata 1 and fdata 1 and may transmit the inversely buffered first internal output data rdata 1 and fdata 1 to an internal node nd 11 in synchronization with the internal clock signals rclk and fclk when the monitor enable signal m_en is disabled to have a logic “ low ” level . the monitor signal transmitter 162 may inversely buffer the first monitor signal ms 1 and may transmit the inversely buffered first monitor signal ms 1 to the internal node nd 11 when the monitor enable signal m_en is enabled to have a logic “ high ” level . the latch unit 163 may latch a signal on the internal node nd 11 and may buffer and output the latched signal . the output driver 164 may generate the first output data dout 1 in response to the output signal of the latch unit 163 . the second output unit 26 may have substantially the same configuration as the first output unit 16 . in other words , the second output unit 26 may have the same circuit as the first output unit 16 . the only difference between the first and second output units 16 and 26 is that i / o signals of the first output unit 16 are different from i / o signals of the second output unit 26 . hereinafter , a monitoring operation of the semiconductor memory device described above will be developed . the monitoring operation may include a first monitoring operation which is executed when the first data i / o block 1 operates in a write mode and a second monitoring operation which is executed when the second data i / o block 2 operates in a read mode . first , when the first data i / o block 1 operates in a write mode , the second monitor signal generator 25 may buffer the write internal signal wt_int generated by the first write path unit 13 to generate the second monitor signal ms 2 if the monitor enable signal m_en is enabled . the second output unit 26 may buffer the second monitor signal ms 2 and may transmit the buffered second monitor signal ms 2 to the second pad 21 . next , when the second data i / o block 2 operates in a read mode , the first monitor signal generator 15 may buffer the read internal signal rd_int generated by the second read path unit 24 to generate the first monitor signal ms 1 if the monitor enable signal m_en is enabled . the first output unit 16 may buffer the first monitor signal ms 1 and may transmit the buffered first monitor signal ms 1 to the first pad 11 . as described above , the write internal signal wt_int generated when the first data i / o block 1 operates in a write mode may be verified through the second pad 21 . hence , a write operation of the first data i / o block 1 can be monitored by reading out the write internal signal wt_int through the second data i / o block 2 which is separated from the first data i / o block 1 . thus , a design margin relating to the write internal signal wt_int may be verified by the monitoring operation , and failure analysis of the semiconductor memory device may be more readily performed . further , the read internal signal rd_int generated when the second data i / o block 2 operates in a read mode may be verified through the first pad 11 . hence , a read operation of the second data i / o block 2 can be monitored by reading out the read internal signal rd_int through the first data i / o block 1 which is separated from the second data i / o block 2 . thus , a design margin relating to the read internal signal rd_int may be verified by the monitoring operation , and failure analysis of the semiconductor memory device may be more readily performed . fig4 is a block diagram of a semiconductor memory device 200 according to another embodiment . as illustrated in fig4 , semiconductor memory device 200 according to the present embodiment may be configured to include a data input block 3 and a data i / o block 4 . the data input block 3 may be configured to include a first pad 31 , a first input buffer 32 and a first write path unit 33 . the data i / o block 4 may be configured to include a second pad 41 , a second input buffer 42 , a second write path unit 43 , a read path unit 44 , a monitor signal generator 45 and an output unit 46 . the first input buffer 32 may buffer a first input data din 1 supplied through the first pad 31 to generate a first internal input data int_din 1 when the data input block 3 operates in a write mode . the first write path unit 33 may drive a first global i / o line to transmit the first internal input data int_din 1 to the first global i / o line gio 1 when the data input block 3 operates in the write mode . the first write path unit 33 may also generate and output a write internal signal wt_int when the first internal input data int_din 1 is transmitted to the first global i / o line gio 1 . the second input buffer 42 may buffer a second input data din 2 supplied through the second pad 41 to generate a second internal input data int_din 2 when the data i / o block 4 operates in a write mode . the second input buffer 42 may interrupt buffering the second input data din 2 in response to a buffer off signal boff when a monitor enable signal m_en is enabled . the second write path unit 43 may transmit the second internal input data int_din 2 to a second global i / o line gio 2 when the data i / o block 4 operates in the write mode . the read path unit 44 may receive internal output data int_dout from data loaded on the second global i / o line gio 2 when the data i / o block 4 operates in a read mode . the monitor signal generator 45 may buffer the write internal signal wt_int to generate a monitor signal ms when the monitor enable signal m_en is enabled . the monitor signal generator 45 may also generate the buffer off signal boff for interrupting the operation of the second input buffer 42 when the monitor enable signal m_en is enabled . the output unit 46 may selectively output the internal output data int_dout or the monitor signal ms as an output data dout in response to the monitor enable signal m_en . the output data dout may be supplied through the second pad 41 . the output unit 26 may output the monitor signal ms as the output data dout when the monitor enable signal m_en is enabled . alternatively , the output unit 26 may output the internal output data int_dout as the output data dout when the monitor enable signal m_en is disabled . as described above , the write internal signal wt_int generated when the data input block 3 operates in a write mode may be verified through the second pad 41 . hence , a write operation of the first data input block 3 can be monitored by reading out the write internal signal wt_int through the data i / o block 4 which is separated from the data input block 3 . thus , a design margin relating to the write internal signal wt_int may be verified by the monitoring operation , and failure analysis of the semiconductor memory device may be more readily performed . further , the operation of the second input buffer 42 may be interrupted when the write internal signal wt_int is monitored . this is for preventing the write internal signal wt_int from being disrupted by the operation of the second input buffer 42 when the write internal signal wt_int is monitored through the second pad 41 . fig5 is a block diagram illustrating a configuration of a semiconductor memory device 300 according to yet another embodiment . as illustrated in fig5 , semiconductor memory device 300 may be configured to include a first data input block 5 , a second data input block 6 and a data i / o block 7 . the first data input block 5 may be configured to include a first pad 51 , a first input buffer 52 and a first write path unit 53 . the second data input block 6 may be configured to include a second pad 61 , a second input buffer 62 and a second write path unit 63 . the data i / o block 7 may be configured to include a third pad 71 , a third input buffer 72 , a selection input unit 73 , a third write path unit 74 , a read path unit 75 , a monitor signal generator 76 and an output unit 77 . the first input buffer 52 may buffer a first input data din 1 supplied through the first pad 51 to generate a first internal input data int_din 1 when the first data input block 5 operates in a write mode . the first write path unit 53 may drive a first global i / o line gio 1 to transmit the first internal input data int_din 1 to the first global i / o line gio 1 when the first data input block 5 operates in the write mode . the first write path unit 53 may also generate and output a write internal signal wt_int when the first internal input data int_din 1 is transmitted to the first global i / o line gio 1 . the second input buffer 62 may buffer a second input data din 2 supplied through the second pad 61 to generate a second internal input data int_din 2 when the second data input block 6 operates in a write mode . the second write path unit 63 may transmit the second internal input data int_din 2 to a second global i / o line gio 2 when the second data input block 6 operates in the write mode . the third input buffer 72 may buffer a third input data din 3 supplied through the third pad 71 to generate a third internal input data int_din 3 when the data i / o block 7 operates in a write mode . the third input buffer 72 may interrupt buffering the third input data din 3 in response to a buffer off signal boff when a monitor enable signal m_en is enabled . the selection input unit 73 may selectively output the second internal input data int_din 2 or the third internal input data int_din 3 as a selection input data din_sel in response to the monitor enable signal m_en . the third write path unit 74 may transmit the selection input data din_sel to a third global i / o line gio 3 when the data i / o block 7 operates in the write mode . the read path unit 75 may receive internal output data int_dout from data loaded on the third global i / o line gio 3 when the data i / o block 7 operates in a read mode . the monitor signal generator 76 may buffer the write internal signal wt_int to generate a monitor signal ms when the monitor enable signal m_en is enabled . the monitor signal generator 76 may also generate the buffer off signal boff for interrupting the operation of the third input buffer 72 when the monitor enable signal m_en is enabled . the output unit 77 may selectively output the internal output data int_dout or the monitor signal ms as an output data dout in response to the monitor enable signal m_en . the output data dout may be supplied through the third pad 71 . the output unit 77 may output the monitor signal ms as the output data dout when the monitor enable signal m_en is enabled . alternatively , the output unit 77 may output the internal output data int_dout as the output data dout when the monitor enable signal m_en is disabled . fig6 is a circuit diagram illustrating an example of a selection input unit included in the semiconductor memory device 300 of fig5 . as illustrated in fig6 , the selection input unit 73 may be configured to include a transfer gate t 71 supplying the second internal input data int_din 2 as the selection input data din_sel when the monitor enable signal m_en is enabled to have a logic “ high ” level , and a transfer gate t 72 supplying the third internal input data int_din 3 as the selection input data din_sel when the monitor enable signal m_en is disabled to have a logic “ low ” level . as described above , the write internal signal wt_int generated when the first data input block 5 operates in a write mode may be verified through the third pad 71 . that is , a write operation of the first data input block 5 can be monitored by reading out the write internal signal wt_int through the data i / o block 7 which is separated from the first data input block 5 . thus , a design margin relating to the write internal signal wt_int may be verified by the monitoring operation , and failure of the semiconductor memory device 300 may be more readily performed . further , the operation of the third input buffer 72 may be interrupted when the write internal signal wt_int is monitored . this is for preventing the write internal signal wt_int from being disrupted by the operation of the third input buffer 72 when the write internal signal wt_int is monitored through the third pad 71 . moreover , according to the present embodiment , a write operation may be executed by the second internal input data int_din 2 transmitted to the selection input unit 73 even when the write internal signal wt_int is monitored through the third pad 71 . therefore , even when the data i / o block 7 receives data from the second data input block 6 to execute a write operation for transmitting the data to the third global i / o line gio 3 , a write operation of the first data input unit 5 may be monitored . thus , an additional and special time may not be required to monitor the write operation of the first data input unit 5 . the example embodiments of the inventive concept have been disclosed above for illustrative purposes . those skilled in the art will appreciate that various modifications , additions and substitutions are possible , without departing from the scope and spirit of the inventive concept as disclosed in the accompanying claims .