referring to the drawing figures , fig1 illustrates an exemplary parallel decimator adaptive filter 10 in accordance with the principles of the present invention . the exemplary parallel decimator adaptive filter 10 is adapted to filter input signal that is input at a high clock rate on the order of many gigasamples per second , for example , using relatively low speed circuits that are clocked at a rate on the order of 100 megasamples per second , for example , to produce a filtered output signal at the high clock rate . the exemplary parallel decimator adaptive filter 10 comprises a plurality of polyphase filter integrated circuits 11 a , 11 b , 11 c each having a plurality of inputs 12 . each polyphase filter integrated circuits 11 a , 11 b , 11 c implements a filter such as is described below . in order to fully understand polyphase filter integrated circuits 11 a , 11 b , 11 c , a standard finite impulse response ( fir ) filter will be explained . then , an efficient method of implementing the fir filter , known as a polyphase filter , will then be explained . fig3 illustrates an exemplary finite impulse response filter , while fig4 illustrates an exemplary decimate - by - four polyphase filter structure . and a description of the finite impulse response ( fir ) filter is as follows , taken with reference to fig3 . an 8 - tap fir filter structure is shown in fig3 . a fir filter has two parts , including a delay section and a multiplier - adder section . the delay section stores a finite number of past input samples . for example , let the number of storage elements be denoted by n . this filter is called an n - tap fir filter . the input data enters the delay line on the left side of fig3 . on each clock cycle all the data shifts over one delay to the right and the new input enters on the left , the data are shown as s 0 - s 7 in fig2 (“ s ” is an abbreviation for sample ). the content of each delay element is multiplied by an associated fixed coefficient , labeled c 0 - c 7 in fig2 (“ c ” is an abbreviation for coefficient ). all the multiplier outputs are summed to form the filtered result . consider the specific example shown in fig3 . the contents of the shift register are s 7 , s 6 , s 5 , s 4 , s 3 , s 2 , s 1 , s 0 ( i . e ., samples zero through seven are stored in the shift register ). each of these samples are multiplied by its associated multiplier coefficient within the filter ( c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 ) to form the final filter output at time zero , f ( 0 ). the final filter output at time zero is : f ( 0 )= s 0 * c 0 + s 1 * c 1 + s 2 * c 2 + s 3 * c 3 + s 4 * c 4 + s 5 * c 5 + s 6 * c 6 + s 7 * c 7 . the f ( 0 ) filtered result is output . on the next clock cycle the contents of the shift register are right shifted and the next data sample is added on the left side of fig2 . the contents of the register are : s 8 , s 7 , s 6 , s 5 , s 4 , s 3 , s 2 , s 1 . the filtered output at time 1 is f ( 1 ) and is : f ( 1 )= s 1 * c 0 + s 2 * c 1 + s 3 * c 2 + s 4 * c 3 + s 5 * c 4 + s 6 * c 5 + s 7 * c 6 + s 8 * c 7 . the filtered outputs at time 2 , 3 , and 4 are as follows : f ( 2 )= s 2 * c 0 + s 3 * c 1 + s 4 * c 2 + s 5 * c 3 + s 6 * c 4 + s 7 * c 5 + s 8 * c 6 + s 9 * c 7 , f ( 3 )= s 3 * c 0 + s 4 * c 1 + s 5 * c 2 + s 6 * c 3 + s 7 * c 4 + s 8 * c 5 + s 9 * c 6 + s 10 * c 7 , f ( 4 )= s 4 * c 0 + s 5 * c 1 + s 6 * c 2 + s 7 * c 3 + s 8 * c 4 + s 9 * c 5 + s 10 * c 6 + s 11 * c 7 a description of the polyphase filter is as follows , taken with reference to fig3 . suppose that a decimated output is required from an fir filter , say only every fourth output of the fir filter , for example . a straightforward implementation described with reference to the above - described fir filter would be very inefficient because it computes f ( 0 ), f ( 1 ), f ( 2 ), f ( 3 ), f ( 4 ), and so forth . however , only f ( 0 ), f ( 4 ), f ( 8 ), . . . are desired ( i . e ., a decimated by 4 output ). a polyphase filter provides an efficient way to compute a decimated output of a prototype fir filter . the original filter and its coefficients are referred to as the “ prototype ” filter . the polyphase filter implementation rearranges the prototype filter so that it efficiently implements only the decimated outputs of the prototype filter . consider the polyphase structure shown in fig4 . this decimate by 4 polyphase structure includes four length - 2 fir filters ( called polyphase filters ). note that the total number of coefficients in all of the four polyphase filters matches the total number of coefficient in the prototype filter ( i . e ., 2 * 4 = 8 ). the polyphase filter coefficients are simply decimated versions of the prototype filter . decimating the filter coefficients of the prototype filter means taking every fourth filter coefficient . the first polyphase filter takes coefficients 0 and 4 from the prototype filter . the second polyphase filter takes coefficients 1 and 5 from the prototype filter . the third polyphase filter takes the 2 and 6 th coefficient from the prototype filter . the fourth polyphase filter takes coefficients 3 and 7 from the prototype filter . the left side of fig4 is the input commutator . the first sample from the commutator feeds the lower 2 - tap polyphase filter . the next sample from the commutator feeds the third from top polyphase filter . the third sample from the commutator feeds the second from the top polyphase filter . the fourth sample feeds the top polyphase filter . after all four commutator input samples are collected , a single output sample is generated ( i . e ., every fourth input clock a single decimated output is formed ). the single output is the sum of the output of all four length - 2 polyphase filters . consider the output this filter structure produces . the lower polyphase filter produces the output s 0 * c 0 + s 4 * c 4 . the third from the top polyphase filter produces the output s 1 * c 1 + s 5 * c 5 . the second from the top polyphase filter produces the output s 2 * c 2 + s 6 * c 6 . the top polyphase filter produces the output s 3 * c 3 + s 7 * c 7 . the sum of all these outputs is : p ( 0 )= s 0 * c 0 + s 1 * c 1 + s 2 * c 2 + s 3 * c 3 + s 4 * c 4 + s 5 * c 5 + s 6 * c 6 + s 7 * c 7 = f ( 0 ). p ( 0 ) exactly matches the output of the prototype filter at time 0 , f ( 0 ). thus , the structure is equivalent to the output of the prototype filter at time 0 . further analysis will show that the filter structure matches the output of the prototype filter at every fourth output sample . the second output of the polyphase filter is : p ( 1 )= s 4 * c 0 + s 5 * c 1 + s 6 * c 2 + s 7 * c 3 + s 8 * c 4 + s 9 * c 5 + s 10 * c 6 + s 11 * c 7 = f ( 4 ). the advantage of the polyphase filter is now clear . at each new input sample to the polyphase filter only a 2 - tap fir filter must be update , versus a 8 - tap fir filter for the direct implementation of the prototype fir filter . also , each polyphase filter must only be updated every 4 - clock cycles since this is the revisit rate of the input commutator . after all four inputs from the commutator are processed , and then the outputs of all four 2 - tap polyphase filters are summed to form the decimated output . the reason people use polyphase filters for decimator filters is that it is d times more efficient then the direct implementation of the prototype filter , where d is the decimation ratio . only 1 polyphase filter with 2 - taps must be evaluated every input clock cycle , versus the 8 - taps that must be evaluated if the direct prototype filter is implemented . alternatively , four pairs of multipliers can be run in parallel to achieve a high - speed filter where each of the four parallel polyphase filters only runs at one - fourth of the input data rate . this allows high - rate input data to be processed by relatively low - rate filter circuits behind the commutator . if a full - rate output is desired , the additional outputs can be generated ( i . e ., sample 0 plus samples 1 or 2 or 3 ) by adding additional polyphase filter structures in parallel with the one shown in fig3 , with input delays of 1 , 2 , and 3 respectively . thus , if four filters are run in parallel then the output of the aggregate is a full - rate filter output . however , each of the four parallel circuits is running at one - fourth of the input data rate . thus , it is possible to build a high - speed modem with parallel processing in lower - rate back - end polyphase filters . referring again to fig1 , each of the plurality of inputs of the polyphase filter integrated circuits 11 a , 11 b , 11 c comprise a filter bank 11 . each of the plurality of inputs of the polyphase filter integrated circuits 11 a , 11 b , 11 c are fed from a commutator 13 having a single input 14 and a plurality of commutated outputs 14 a . each of the polyphase filter integrated circuits 11 a , 11 b , 11 c or filter banks 11 comprise a plurality of short - length polyphase finite impulse response ( fir ) filters 15 . outputs of the plurality of short - length polyphase fir filters 15 of each of the polyphase filter integrated circuits 11 a , 11 b , 11 c or filter banks 11 are combined ( added ) to produce a single output 16 of each respective polyphase filter integrated circuit 11 a , 11 b , 11 c . signals supplied to the first polyphase filter integrated circuit 11 a is not delayed . signals supplied to the second and third polyphase filter integrated circuits 11 b , 11 c are coupled through and delayed by first and second pluralities of delay elements 17 a , 17 b respectively . for example , in the exemplary filter 10 , the input data from the commutator 13 is delayed by two samples by the first delay elements 17 a prior to being input to the second filter bank 11 comprising the second polyphase filter integrated circuit 11 b . the input data from the commutator 13 is delayed by four samples by the second delay elements 17 b prior to being input to the third filter bank 11 comprising the third polyphase filter integrated circuit 11 c . in operation , an input signal arrives at the input 14 of the commutator 13 at a predetermined input rate r . for example , an input rate of 400 megasamples per second ( msps ) may be used . the input signal is commutated into n parallel paths 14 a ( six paths are shown in the exemplary filter 10 ) by the commutator 13 . the commutated input data is fed to three ( n / 2 ) sets of filter banks 11 or polyphase filter integrated circuits 11 a , 11 b , 11 c that each comprise the plurality of short - length polyphase fir filters 15 . each filter bank 11 operates in parallel with the other filter banks 11 , generating one of n / 2 filtered output signals 16 required every n input samples . the input data from the commutator 13 is not delayed prior to being input to the first filter bank 11 . the input data from the commutation 13 is delay by 2 samples prior to being input to the second filter bank 11 . the input data from the commutator is delayed by 4 samples prior to being input to the third filter bank 11 . each output of the respective filter banks 11 is formed by adding the outputs of the six ( n ) short - length polyphase fir filters 15 . each polyphase filter 15 operates at a rate equal to r / n . the present invention also allows the filter length to increase as the bandwidth of the signal decreases ( all - rate operation ). that is , when only a sub - set of the outputs are required , the computing resources of the unused outputs are directed to assist the desired outputs . for example , if one of the n / 2 filter outputs 16 is not needed in a particular application , its polyphase filters 15 may be appended to one of the other filter banks 11 to extend the effective filter length of the filter banks 11 that remain in operation . the present invention thus provides for operation of multiple decimators ( the filter banks 11 ) in parallel to enable non - decimated filtering beyond the limit of the technology that is used to produce the filter 10 . for example , the present invention allows filtering of giga - bit - per - second signals with low - cost cmos integrated circuits as the respective filter banks 11 that have a maximum clock rate of 100 mhz . thus , the filter 10 has a systolic , parallel architecture structure that is amenable to asic implementation and allows a vast reduction in the number of integrated circuit chips required to process high - rate signals . in addition , the use of filter coefficient double buffering allows filter coefficients to be changed “ on - the - fly ”, enabling adaptive filter coefficient updates . also , high - rate transmitter pulse shaping and interpolation by two may be implemented using the polyphase decimator structure of the present filter 10 . fig4 illustrates an exemplary adaptive filtering method 30 in accordance with the principles of the present invention . the exemplary adaptive filtering method 30 comprises the following steps . an input signal to be filtered is commutated 31 to provide a plurality of commutated signals . a plurality of parallel filter banks 11 are provided 32 that each comprise a plurality of polyphase filters 15 . the plurality of commutated signals are filtered 33 using the plurality of polyphase filters of a first filter bank to generate a first plurality of filtered signals . each of the plurality of commutated signals are delayed 34 by a first delay value and each of the plurality of delayed commutated signals is adaptively filtered 35 using the plurality of polyphase filters of a second filter bank to generate a second plurality of filtered signals . each of the plurality of commutated signals is delayed 36 by a second delay value and each of the plurality of delayed commutated signals is adaptively filtered 37 using the plurality of polyphase filters of a third filter bank to generate a third plurality of filtered signals . the first , second and third pluralities of filtered signals are respectively combined 38 to produce first , second and third filtered output signals that comprise a filtered version of the input signal . thus , a parallel decimator adaptive filter for use with all - rate gigabit - per - second modems , and the like , has been disclosed . it is to be understood that the described embodiment is merely illustrative of some of the many specific embodiments that represent applications of the principles of the present invention . clearly , numerous and other arrangements can be readily devised by those skilled in the art without departing from the scope of the invention .