the invention is a method and apparatus for a data switch port . in the following description , numerous specific details are set forth to provide a more thorough description of embodiments of the invention . it is apparent , however , to one skilled in the art , that the invention may be practiced without these specific details . in other instances , well known features have not been described in detail so as not to obscure the invention . the present invention provides a data port circuit with fewer transistors and higher performance than prior art schemes . a diagram of the data port of the present invention is illustrated in fig6 . the a input is coupled to cells 603 . 1 and 603 . 2 . the output of cell 603 . 1 is coupled through inverter 604 to d output 605 . the output of cell 603 . 2 is coupled through inverter 606 to e output 607 . the b input is coupled through inverter 608 to cells 603 . 3 and 603 . 4 . the output of cell 603 . 3 is coupled through inverter 606 to e output 607 . the output of cell 603 . 4 is coupled through inverter 604 to d output 606 . the cells are configured so that a high ci signal enables cells 603 . 1 and 603 . 3 , and disables cells 603 . 2 and 603 . 4 . this results in the a input being coupled to the d output 605 and the b input being coupled to the e output 607 . conversely a high cb signal enables cells 603 . 2 and 603 . 4 , and disables cells 603 . 1 and 603 . 3 . as a result , the a input is coupled to the e output 607 and the b input is coupled to the d output 605 . a circuit diagram of the cells of fig6 is illustrated in fig7 . the cell is a transmission gate and consists of transistors m 1 and m 2 . transistor m 1 is a p type transistor with its source coupled to the drain of n type transistor m 2 at input node 701 . the drain of transistor m 1 is coupled to the source of transistor m 2 at output node 703 . transistor m 1 has a substrate connection to vdd and transistor m 2 has a substrate connection to ground . the gate of transistor m 1 is coupled to signal cb and the gate of transistor m 2 is coupled to signal ci . these signals are complementary so that both transistors are either open or closed . ( the example shown corresponds to cells 603 . 1 and 603 . 4 of fig6 . cb and ci are reversed for cells 603 . 2 and 603 . 3 ). when cb is enabled , the transmission gate of fig7 is open , permitting a signal to pass from input node 701 to output node 702 . when cb is low , the gate is closed . the present invention uses only twelve transistors including a perfect driver as opposed to 16 transistors with poor driver and 56 transistors of the prior art implementations . the circuit topology is inherently superior in area , speed , and transient power properties addressed as individual design criteria or as a whole . in an alternate embodiment , a single n - type transistor is used instead of the transistor pair . this further reduces the transistor count , resulting in a simpler and faster circuit for the primary circuits and the c driver . although the invention has been described in connection with 2 × 2 ports , it has equal application to m × n × d ports . the principal circuit and topology can be a handcrafted hardware macro , as well as a software macro with a given vendor &# 39 ; s device library . ports and depths are scalable at the discretion of the designer based upon the silicon foundry vendor library , and constraints and objectives of the design or sub - design . circuit simulations have shown several orders of magnitude ( e . g . 1000 ×) of improvement in area delay and power parameters are achievable over three generations of technology , including 0 . 35 , 0 . 25 and 0 . 18 micron ruled based technologies . for a 2 × 2 × 256 port using 0 . 18 micron , benchmark performance is less than 200 ps for the data path , translating into a bandwidth of 640 gbps ( gigabytes per second ). in other embodiments , ports can be of depth of 1024 and bandwidths of 5 . 0 terabytes per second can be achieved . thus , a data switch port is described in conjunction with one or more specific embodiments . the invention is defined by the claims and their full scope of equivalents .