disclosed herein are pwm solutions with comparators not relying on a variable reference to adjust duty cycle . in accordance with some embodiments , a waveform ( such as a triangle , sawtooth , or sinusoidal wave ) is applied to a comparator with a fixed reference to generate a bit stream with a controllable duty cycle . in some embodiments , the offset level of the applied waveform can be varied to adjust the duty cycle . however , before describing such pwms , a dual rail generator that may be used to create an adjustable waveform will be discussed . fig2 a and 2b generally show a dual rail generator providing first and second ( high and low ) voltage rail outputs , v h , and v l , based on applied amplitude ( v amp ) and offset ( v offset ) inputs , relative to a reference voltage ( v ref ). ( in the depicted embodiment , the reference voltage is fixed and set within the dual rail generator and thus is not shown in fig1 a . however , in some embodiments , an externally applied and / or variable reference could be used . moreover , the reference voltage could have a value of 0 in some embodiments .) mathematically , v h = v ref + v amp v offset and v l = v ref − v amp + v offset . as graphically illustrated in fig2 b , this results in the difference between the high and low rails being two times ( twice ) the applied amplitude . they are symmetrical about the reference voltage ( v ref ) when there is no offset ( v offset equals 0 ), but if an offset is applied , the high and low rails are equally shifted , either upward or downward in accordance with the offset value . thus , by appropriately adjusting the v offset and v amp signals , numerous different v h − v l combinations may be attained . fig2 c shows a signal flow representation of the dual rail generator of fig2 a in accordance with some embodiments . it comprises adders 202 , 204 , 206 , and 208 to generate the high and low rails ( v h , v l ) in accordance with the equations set forth above . the reference voltage v ref is applied to adders 202 , 204 and respectively added to v amp and − v amp thereby generating v ref + v amp and v ref − v amp at their outputs . in turn , these outputs are respectively added to the offset ( v offset ) at adders 204 and 208 to generate v h and v l , as indicated . fig3 is a schematic diagram of a circuit to implement the signal flow diagram of fig2 c and generate the high and low reference signals , v h and v l . however , instead of using the above described amplitude ( v amp ) and offset ( v offset ) signals , referenced versions , v a and v off ( where v a = v ref + v amp and v off = v ref + v offset ) are used instead to more conveniently accommodate circuits ( such as the circuit described below with reference to fig4 ) that have an inherent reference component . therefore , va and voff are still amplitude and offset signals , as are those used for the diagram of fig2 c , except that they have an additional reference component built within . the dual rail generator of fig3 generally comprises a dual rail signal generator circuit 302 and an output driver section 322 , coupled together as indicated . the dual rail signal generator 302 comprises adder circuits 303 , 305 , 307 , 308 , 309 , 311 , and 313 , coupled together as shown to appropriately add / subtract vref , va , and voff in accordance with the above equations to generate high and low reference rails , v href and v lref . the reference rails , v href and v lref , correspond to v h and v l above in value but may not be sufficiently amplified ( buffered ) for use as supplies to an actual load . accordingly , they are amplified / regulated in the output driver section 322 by linear voltage regulators 322 h and 322 l , respectively , which provide a their outputs the regulated high and low rails , v h and v l . in the depicted embodiment , each adder circuit in the dual rail reference generator section 302 has a voltage gain of a = 1 and is implemented with a difference adder , which subtracts a first value from a second value . as shown in fig3 , they are appropriately configured to perform the above equations for v h ( v href ) and v l ( v lref ). it should be appreciated that they could be implemented with any suitable circuit for performing an addition or subtraction operations on two analog inputs , many of which are known to persons of ordinary skill . ( below , however , with reference to fig4 , a novel approach using inverters is presented .) for simplicity sake , the gain of each adder is one but this certainly is not required . the high and low rail equations defined above could be implemented with adders having other gain values and depending on desired applications , variations on the above described equations may be desired ( e . g ., the addends could be weighted differently ). each regulator ( 322 h or 322 l ) is a unity gain linear regulator formed from an amplifier coupled to pmos and nmos transistors , all coupled together as shown . the high - side regulator 322 h is formed from amplifier 323 , pmos transistor p 1 and nmos transistor n 1 . it receives at its input ( negative input of amplifier 323 ) the high reference signal ( v href ), while its output is coupled to the gates of transistors p 1 and n 1 . in turn , the transistor outputs ( at their drains ) are coupled back to the positive input of amplifier 323 . the low side regulator 322 l is configured in the same way except that it is formed from amplifier 325 , pmos transistor p 2 and nmos transistor n 2 . ( note the term “ pmos transistor ” refers to a p - type metal oxide semiconductor field effect transistor . likewise , “ nmos transistor ” refers to an n - type metal oxide semiconductor field effect transistor . it should be appreciated that whenever the terms : “ transistor ”, “ mos transistor ”, “ nmos transistor ”, or “ pmos transistor ” are used , unless otherwise expressly indicated or dictated by the nature of their use , they are being used in an exemplary manner . they encompass the different varieties of mos devices including devices with different vts and oxide thicknesses to mention just a few . moreover , unless specifically referred to as mos or the like , the term transistor can include other suitable transistor types , e . g ., junction - field - effect transistors , bipolar - junction transistors , and various types of three dimensional transistors , known today or not yet developed .) because each amplifier is configured with negative feedback , the voltage at the input terminals are forced to equal one another . this results in the output voltages ( v h , v l ) tracking ( or following ) the input voltages ( v href , v lref ) and at the same time , being able to drive actual loads . note that transistors n 1 and p 2 are represented with dashed lines . this is so because in some embodiments , the high side rail v h may be used to primarily source current to its load , while the low side rail v l may primarily be used to sink current from its load . in such a case , n 1 and p 2 could be smaller than p 1 and n 2 or even omitted . fig4 shows a dual rail generator circuit , in accordance with some embodiments , that uses inverters for synthesis and regulation of the two output rails , v h and v l , based on analog amplitude and offset voltage inputs , v a and v off , respectively . v a and v off are referenced versions of v amp and v offset as defined above , based on an inherent reference voltage , v ref , corresponding to the trip point of inverters used in the circuit . the dual rail generator generally comprises a dual rail reference generator section 402 coupled to an output driver section 422 . the reference generator portion 402 comprises inverters u 1 , u 2 , u 3 and resistors r 1 to r 8 , while the output driver section 422 comprises inverters u 4 to u 11 , transistors p 1 , p 2 , n 1 , n 2 , resistors rh and rl , and capacitors ch and cl , all coupled together as shown . in some embodiments , the inverters are formed from pmos and nmos transistors with their gates coupled together to provide an inverter input and their drains coupled together to provide an inverter output . in some embodiments , the inverters ( except possibly u 7 and u 11 ) are designed to have the same trip points , and u 1 - u 5 , u 8 and u 9 are sized to have the same strengths . for example , the pmos and nmos transistors in u 1 - u 6 , and u 8 - u 10 may be designed to have the same current carrying capability . the actual trip point value is not necessarily critical , so long as the values in the inverters are sufficiently close to one another , although it may be desirable to target the trip point at vcc / 2 so that v h and v l may have a wider operating range . u 6 and u 10 may be designed to be weaker in strength . in contrast , u 7 and u 11 may be designed to be stronger , and their trip points need not necessarily be the same as the others . the reference generator portion 402 will initially be discussed . inverters u 1 and u 2 , along with resistors r 1 - r 4 , make up a low - side section to generate a reference signal ( v lref ) for the low rail , while inverter u 3 and resistors r 7 and r 8 make up the high - side section to generate the high rail reference ( v href ). with the depicted embodiment , the high and low side sections generate inverted versions , relative to inverter trip points , of the high and low side rails . the output driver section thus comprises driver circuits that invert the reference signal to provide the high and low rails . inverter u 1 is configured to be an inverting amplifier having a gain of about r 2 / r 1 acting on the v amp component of v a , relative to vref ( the trip point of the inverter ). that is , an inverter , with feedback , acts similarly to an amplifier with negative feedback , except that it has an inherent offset corresponding to its trip point . therefore , with resistors r 1 and r 2 configured as shown , the inverter &# 39 ; s output voltage is equal to : (− r 2 / r 1 )( va − vref )+ v ref . when r 1 and r 2 are equal , this reduces to : 2v ref − v a , or v ref − v amp . so , for example , if v ref = 0 . 6v and v a = 0 . 8v , then v u1 would be 0 . 4v . ( note that this analysis assumes that the inverter gain is high , which may not be completely accurate , especially when inputs are close to the trip point . accordingly , in some embodiments , the gain terms may be “ tweaked ” to achieve desired results , e . g ., for a particular operating range .) inverter amplifier circuits u 2 and u 3 are essentially the same . they are configured to function as summing inverter amplifiers ( relative to the inverter trip points , i . e ., the reference voltage ). summing inverter u 2 sums the output from u 1 ( v u1 , which is v ref − v amp ) with v off ( v offset + v ref ), while u 3 sums v a with v off . ( note that the high - side section doesn &# 39 ; t have an inverter stage corresponding to u 1 in the low - side path . this is so because in the high - side path , to generate v l , the vamp component in va is added rather than subtracted .) the gain and relative weighting for the summed terms are determined by their associated resistors . with regard to u 2 , r 4 / r 3 determines the gain for the v u1 term while r 4 / r 5 determines the gain for the v off term . the output of u 2 ( v ref ) will be : v lref =−( r 4 / r 3 )( v u1 − v ref )−( r 4 / r 5 )( v off − v ref )+ v ref . similarly , with regard to u 3 , r 8 / r 7 determines the gain of the applied v a term , while r 8 / r 6 determines the gain of the offset term v off . the output , v href , is : v href =−( r 8 / r 7 )( v a − v ref ) ( r 8 / r 6 )( v off − v ref )+ v ref . thus , if r 3 , r 4 , and r 5 are the same and if r 6 , r 7 , and r 8 are the same , the output equations reduce to : v lref =−( v u1 − v ref )−( v off - vref )+ v ref and v href =−( v a − v ref )−( v off − v ref )+ v ref . the outputs , v lref and v href , result in inverted , relative to the inverter trip points , versions of the high and low rails . the amplifiers ( or drivers ) in the output driver section 422 correct this in providing the high and low rails . as an example to illustrate how the dual rail reference generator 402 works , assume that r 1 = r 2 ( e . g ., 10k ohms ), r 3 = r 4 = r 5 ( e . g ., 10k ohms ) and r 6 = r 7 = r 8 ( e . g ., 10k ohms ). also assume , as with the above example , that v ref = 0 . 6v , the offset is to be 0 . 1v ( the applied v off would thus be 0 . 7v ), and v amp is to be 0 . 2v ( the applied v a would thus be 0 . 5v and v u1 would be 0 . 4v ). with these values , the high and low rails should be 0 . 9v and 0 . 7v , respectively . applying these values to the equations for u 2 and u 7 , the low reference voltage , v lref , would be 0 . 7 while the high reference voltage , v href , would be 0 . 3v . this is correct because after being inverted by the output driver sections ( relative to the 0 . 6v reference ), they become 0 . 5v and 0 . 9v respectively , which are the correct values . ( again , it should be appreciated that the actual resistor values , amplifier gains , and weights are not necessarily important , so long as the overall transfer functions for v h /( v a , v off ) and v l /( v a , v off ) provide for sufficiently consistent , predictable results for acceptable input and output operating ranges . this also applies to the circuits in the output driver section 422 , discussed in the following section .) the output driver section 422 comprises inverters u 4 to u 11 , mos transistors n 1 , n 2 , p 1 , p 2 , and load resistors and capacitors r h , r l , c h , and c l . the low side driver is formed from inverters u 4 to u 7 , transistors p 1 , p 2 , resistor rl , and capacitor cl ; while the high side driver comprises inverters u 7 to u 10 , transistors p 2 , n 2 , resistor rh , and capacitor ch . with the low side driver , inverters u 4 and u 5 are coupled together at their inverter outputs at node n 1 in a mirrored configuration . with this configuration , they act like an inverting analog amplifier to provide at an input ( v lref , v l ) the analog inverse of the other input , relative to v ref ( inverter trip points , which are to be the same ). therefore , the voltage at v l will be : v l − 2v ref − v lref ( note that as used in this circuit , the inverter inputs ( at v lref and v l ) function both as inputs and outputs . it may be helpful to think of them as ends of a see - saw , with a fulcrum in the middle pushing up to the reference voltage level . as one side goes up , the other goes down and when perfectly balanced , the inputs and node n 1 approach v ref . on the other hand , when v lref goes up or down , i . e ., in response to changes in v a and / or v off it forces the voltage ( v l ) at the other end of the “ see - saw ” to go down or up in the opposite direction accordingly . inverter u 6 is a relatively weak inverter , designed to have its trip point at v ref . with its input shorted to its output , it generates at its output the reference signal , v ref , and is coupled to the inverter outputs of mirrored inverters u 4 , u 5 ( node n 1 ) to provide them with a relatively weak load . it serves to reduce their gain , acting like ballast to stabilize their analog performance . inverter u 7 is relatively large ( e . g ., twice the current carrying capability as inverters u 1 , u 2 , u 3 , u 4 , or u 5 ) and has it trip point relatively close to those of the others , but this is not critical . it functions to drive push / pull output transistors p 1 , n 1 to appropriately regulate v l . thus , u 4 / u 5 , u 6 , and p 1 / n 1 form the negative feedback loop to regulate v l . as v l goes up ( e . g ., due to changes in the output load ), it causes n 1 to go lower , which causes n 2 to go up thereby turning down p 1 and turning up n 1 to bring v l back down . it works the same way , but in the opposite direction , when v l goes down . resistor rl and capacitor cl are coupled in series between v l and vss to provide stability at the output , v l . the high side driver is configured and operates essentially the same as the low side driver , so it will not be described to the same extent . however , it &# 39 ; s worth pointing out that in some embodiments , with the high side driver , because the high rail , v h , may serve primarily as a current source , the pull - up fet , p 2 , may be sized larger than the pull - down transistor n 2 and in some cases , n 2 may be omitted altogether . conversely , with the low side driver , the pull - down transistor n 1 may be sized larger than p 1 when the low rail , v l , serves primarily as a current sink . in some embodiments , p 1 may be omitted altogether . fig5 shows an n - phase , switching type voltage regulator 501 . it generally comprises a vr controller 503 coupled to n switch drivers ( or switches ) s 1 to s n , one for each phase . in turn , the switches are coupled to n corresponding output sections formed from inductors l 1 to l n , which are coupled to a common , regulated output voltage node v out at capacitor c . feedback sensors 507 1 to 507 n are coupled to the output ( e . g ., at the inductor ) to provide output feedback information back to the controller 503 for closed loop control of the output voltage v out ( it should be appreciated that the depicted switching regulator is presented in a simplified form , for illustrative purposes , to put into context the fixed reference type pwms of this disclosure . accordingly , the switches , output sections , feedback sensors and other elements known in the art are not limited to any specific implementation but rather are intended to cover any devices suitable to perform their functions . similarly , the depicted elements could be implemented in a single chip , a chip and external circuit board , or in multiple chips and / or multiple chips in combination with one or more circuit boards . for example , in some embodiments , the vr controller could be in a chip , while the switch drivers and / or output sections could be implemented with external discrete components on a circuit board . on the other hand , they could all be implemented in a single module .) the vr controller comprises a phase control section 504 coupled to fixed reference pwm ( frpwm ) circuits ( pwm 1 to pwm n ). it controls these pwms to generate bit stream drive signals for their respective switches . for each pw m , it controls their duty cycle , in response to feedback from their associated sensor 507 , to regulate the output voltage at a consistent level . it may also control their phase relationships , relative to each other and perform other tasks . each pwm comprises a fixed reference comparator to generate its bit stream . such pwms will be discussed in more detail in the following sections . fig6 shows a portion of a pwm with a fixed reference comparator in accordance with some embodiments . it generally comprises a variable waveform generator 601 coupled to a fixed reference comparator 603 to generate at its output a bit stream with a controllably variable duty cycle . ( as used herein , the term , “ fixed reference comparator ” refers to a circuit to compare an input against a substantially fixed reference signal . the fixed reference signal may be supplied to the comparator circuit , or it could be defined by or within the comparator circuit itself . moreover , the fixed reference may actually be adjustable , e . g ., for a trimming , calibration or adjustment setting . the fact that it is referred to as “ fixed ” is meant to indicate that it is not adjusted during operation to adjust the duty cycle of the bit stream generated by the comparator .) the waveform generator generates a periodic waveform , cycling between low and high values . it may generate any suitable waveform including but not limited to a sinusoidal waveform , a triangular waveform , and a saw - tooth waveform , although a linearly changing waveform may be desired to provide for a linearly adjustable duty cycle . the waveform generator has a control input to control the amplitude and / or offset of the waveform . the waveform generator output is coupled to the positive input of the fixed reference comparator 603 while a fixed reference voltage v ref — fixed is coupled to its negative input . when the waveform is below the reference voltage , the comparator outputs a low , and when it is above the reference voltage , the comparator outputs a high . thus , a bit stream is generated with a frequency corresponding to the frequency of the waveform . its duty cycle depends on the offset position of the waveform relative to the reference voltage . by appropriately controlling the control input to the waveform generator , the waveform can be shifted upward or downward , relative to the reference voltage , to either increase or decrease the amount of time per cycle that the waveform is below ( or above ) the fixed reference voltage . in this way , the bit stream duty cycle can be adjusted accordingly , corresponding to the percentage of time during each cycle that it is above the reference level . ( alternatively , the variable waveform &# 39 ; s amplitude could be adjusted to adjust the bit stream duty cycle .) fig7 shows a portion of a fixed comparator pwm using a dual rail generator . the dual rail generator 201 provides adjustable high and low rails , v h and v l to the triangular waveform generator , which works in cooperation with the dual rail generator to generate a triangular waveform cycling between the low and high rails . in some embodiments , the fixed reference ( v ref — fixed ) corresponds to the reference voltage ( v ref ) used in the dual rail generator 201 . the positions of the high and low rails , which are controlled by the amplitude and offset controls , determines the height and offset of the triangle wave signal relative to the reference voltage . therefore , they can be used to control the duty cycle of the output bit stream . in some embodiments , the amplitude may initially be set ( e . g ., at start - up or via periodic calibration ), and the offset control can then be used by the pwm controller to control the duty cycle of the bit stream . ( for information on a waveform generator working in cooperation with a dual rail generator to generate a variable waveform , reference is made to co - pending , commonly owned us patent application titled , signal generating circuit , filed on dec . 19 , 2006 , which is incorporated by reference into the present application .) fig8 shows the pwm portion of fig7 with an inverter used as the fixed reference comparator . in some embodiments , it &# 39 ; s designed to have a trip - point that corresponds to the reference voltage ( v ref ) of the dual rail generator 201 . in some embodiments where a dual rail generator such as is shown in fig4 is used , the trip - point may be designed to correspond to the trip points of inverters in the dual rail generator used to set the reference voltage ( v ref ). with reference to fig9 , one example of a computer system is shown . the depicted system generally comprises a processor 902 that is coupled to a voltage regulator 501 ( as described with reference to fig5 ), a wireless interface 908 , and to memory 906 . it is coupled to the voltage regulator 501 , which in turn is coupled to a power supply 904 , to receive from the voltage regulator at least one regulated voltage supply , derived from power supply 904 . the wireless interface 908 is coupled to an antenna 910 to communicatively link the processor through the wireless interface 908 to a wireless network ( not shown ). it should be noted that the depicted system could be implemented in different forms . that is , it could be implemented on a circuit board , or a chassis having multiple circuit boards . similarly , it could constitute one or more complete computers or alternatively , it could constitute a component useful within a computing system . the invention is not limited to the embodiments described , but can be practiced with modification and alteration within the spirit and scope of the appended claims . for example , it should be appreciated that the present invention is applicable for use with all types of semiconductor integrated circuit (“ ic ”) chips . examples of these ic chips include but are not limited to processors , controllers , chip set components , programmable logic arrays ( pla ), memory chips , network chips , and the like . moreover , it should be appreciated that example sizes / models / values / ranges may have been given , although the present invention is not limited to the same . as manufacturing techniques ( e . g ., photolithography ) mature over time , it is expected that devices of smaller size could be manufactured . in addition , well known power / ground connections to ic chips and other components may or may not be shown within the figs . for simplicity of illustration and discussion , and so as not to obscure the invention . further , arrangements may be shown in block diagram form in order to avoid obscuring the invention , and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present invention is to be implemented , i . e ., such specifics should be well within purview of one skilled in the art . where specific details ( e . g ., circuits ) are set forth in order to describe example embodiments of the invention , it should be apparent to one skilled in the art that the invention can be practiced without , or with variation of , these specific details . the description is thus to be regarded as illustrative instead of limiting .