referring now to the figures of the drawings in detail , there is shown , in the top right of the figures , a schematic illustration of a memory matrix 50 containing m = 2 z regular rows zm ( 1 ) to zm ( m ), p = 2 k additional rows zp ( 1 ) to zp ( p ), n = 2 s regular columns sn ( 1 ) to sn ( n ) and q = 2 l additional columns sq ( 1 ) to sq ( q ). the names used here for the rows and columns are entered against the respectively associated row and column lines in the drawing . the numbers z , k , s , l are integers , where k ≦ z − 2 and l ≦ s − 2 . the m regular rows and the n regular columns define a first region a of the memory matrix . the p additional rows and the n regular columns define a second region b of the memory matrix . the m regular rows and the q additional columns define a third region c of the memory matrix . the p additional rows and the q additional columns define a fourth region d of the memory matrix . in the case illustrated , each region is a cohesive block in the matrix . this also simplifies the illustration in the drawing . alternatively , the regions can be disposed with physical interleaving . the bundle 51 of the m regular row lines is connected to a first group 41 a of m outputs of a row address decoder 41 , and the bundle 52 of the p additional row lines is connected to a second group 41 b of p outputs of the row address decoder 41 . in a similar way , the bundle 53 of the n regular column lines is connected to a first group 42 a of n outputs of a column address decoder 42 , and the bundle 54 of the q additional column lines is connected to a second group 42 b of q outputs of the column address decoder 42 . the row address decoder 41 has z address inputs ez ( 1 ) to ez ( z ) for receiving z address bits sufficient for addressing the m = 2 z regular rows . the decoder 41 also has a control input cz for receiving a first binary control signal u 1 from a line 35 . the decoder 41 is configured to alternate between two column decoding specifications ( which are described further below ) based upon the control signal u 1 . the column address decoder 42 has s address inputs es ( 1 ) to es ( s ) for receiving s address bits sufficient for addressing the n = 2 s regular columns . the decoder 42 also has a control input cs for receiving a second binary control signal u 2 from a line 36 . the decoder 42 is configured to alternate between two row decoding specifications ( which are described further below ) based upon the control signal u 2 . there is also a first set 11 of z address connection contacts az ( 1 ) to az ( z ), the first z − 1 instances az ( 1 ) to az ( z − 1 ) of which are hardwired to the first z − 1 instances ez ( 1 ) to ez ( z − 1 ) of the address inputs of the row address decoder 41 . in a similar manner , there is a second set 12 of s address connection contacts as ( 1 ) to as ( s ), the first s − 1 instances as ( 1 ) to as ( s − 1 ) of which are hardwired to the first s − 1 instances es ( 1 ) to es ( s − 1 ) of the address inputs of the column address decoder 42 . the last address input ez ( z ) of the row address decoder 41 can be selectively connected either to the last contact az ( z ) in the first set 11 of address connection contacts or to the second to last contact as ( s − 1 ) in the second set 12 of address connection contacts by an electronically controlled first changeover switch ( multiplexer ) 31 . the switching state of the changeover switch 31 is controlled by the second binary control signal u 2 , which appears on the line 36 . in a similar manner , the last address input es ( s ) of the column address decoder 42 can be selectively connected either to the last contact as ( s ) in the second set 12 of address connection contacts or to the second to last contact az ( z − 1 ) in the first set 11 of address connection contacts by an electronically controlled second changeover switch ( multiplexer ) 32 . the switching state of the changeover switch 32 is controlled by the first binary control signal u 1 , which appears on the line 35 . for generating the two control signals u 1 and u 2 , a separate connection contact 13 in the form of a control bit connection ac for externally applying a first control bit c 1 , and a combinational logic circuit having two and gates 33 and 34 , each of which can be formed by a nand gate with a downstream inverter , for example , are provided . the input side of the first and gate 33 is connected to the control bit connection contact ac and to the last contact az ( z ) in the first set 11 of address connection contacts , and the output side of the and gate 33 puts the control signal u 1 onto the line 35 . the input side of the second and gate 34 is connected to the control bit connection contact ac and to the last contact as ( s ) in the second set 12 of address connection contacts , and the output side of the and gate 34 puts the control signal u 2 onto the line 36 . the whole of the circuit configuration described above is preferably in the form of an integrated circuit on a single chip . the way in which the circuit works for addressing the various regions a , b , c , and d of the matrix 50 will now be explained with reference to fig1 to 4 . to address the m regular rows and n regular columns that define the region a of the memory matrix 50 , the binary value “ 0 ” is applied to the control bit connection contact ac to set a first operating state , which is shown in fig1 . the “ 0 ” of the “ first control bit ” c 1 on the contact ac sets the first control signal u 1 to “ 0 ” through the first and gate 33 and sets the second control signal likewise to “ 0 ” through the second and gate 34 . in response to the binary value “ 0 ” of the second control signal u 2 , the first changeover switch 31 connects the last address input ez ( z ) of the row address decoder 41 to the last address connection contact az ( z ) in the set 11 , and , in response to the binary value “ 0 ” of the first control signal u 1 , the row address decoder 41 is set to a first row “ decoding specification ” ( through its input cz ). this means that , in such a setting , the decoder 41 uses all z bits applied to its address inputs ez ( 1 ) to ez ( z ) for addressing the m regular rows zm ( 1 ) to zm ( m ) of the memory matrix 50 . in a similar manner , in response to the binary value “ 0 ” of the first control signal u 1 , the second changeover switch 32 connects the last address input es ( s ) of the column address decoder 42 to the last address connection contact as ( s ) in the set 12 , and , in response to the binary value “ 0 ” of the second control signal u 2 , the column address decoder 42 is set to a first column decoding specification ( through its input cs ). in such a setting , the decoder 42 uses all s bits applied to its address inputs es ( 1 ) to es ( s ) for addressing the n regular columns zn ( 1 ) to zn ( n ) of the memory matrix 50 . in the circuit configuration &# 39 ; s first operating state , as so defined , the row address bits z ( 1 ) to z ( z ) required for addressing the m regular rows are applied to the address connection contacts az ( 1 ) to az ( z ) in the first set 11 , and the column address bits s ( 1 ) to s ( s ) required for addressing the n regular columns are applied to the address connection contacts as ( 1 ) to as ( s ) in the second set 12 . to address the p additional rows and n regular columns that define the region b of the memory matrix 50 , a second operating state as shown in fig2 is set by setting the first control bit c 1 on the contact ac to the binary value “ 1 ”, applying a “ 1 ” as second control bit to the last address connection contact az ( z ) in the first set 11 , and applying a “ 0 ” as third control bit to the last address connection contact as ( s ) in the second set 12 . in such a case , the first and gate 33 receives a “ 1 ” at both inputs , which means that the first control signal u 1 is set to “ 1 ”. the second control signal u 2 is set to “ o ”, because the and gate receives a “ 0 ” at one input . in response to the binary value “ 0 ” of the second control signal u 2 , the first changeover switch 31 connects the last address input ez ( z ) of the row address decoder 41 to the last address connection contact az ( z ) in the set 11 ( this connection is not actually needed in the second operating state of the circuit configuration , but its appearance can be attributed to the nature of the changeover switch used ). in response to the binary value “ 1 ” of the first control signal u 1 , the row address decoder 41 is set to a second row decoding specification ( through its input cz ). in such a setting , the decoder 41 uses only k ≦ z − 2 bits applied to its address inputs ez ( 1 ) to ez ( k ) for addressing the p additional rows zp ( 1 ) to zp ( p ) of the memory matrix 50 . in response to the binary value “ 1 ” of the first control signal u 1 , the second changeover switch 32 connects the last address input es ( s ) of the column address decoder 42 to the second to last address connection contact az ( z − 1 ) in the set 11 , and , in response to the binary value “ 0 ” of the second control signal u 2 , the column address decoder 42 is set to the first column decoding specification ( through its input cs ). in such a setting , the decoder 42 uses , as mentioned , all s bits applied to its address inputs es ( 1 ) to es ( s ) for addressing the n regular columns zn ( 1 ) to zn ( n ) of the memory matrix 50 . in the circuit configuration &# 39 ; s second operating state , as so defined , the k row address bits z ( 1 ) to z ( k ) required for addressing the p additional rows are applied to the address connection contacts az ( 1 ) to az ( k ) in the first set 11 , and the s row address bits s ( 1 ) to s ( s ) required for addressing the n regular columns are applied to the address connection contacts as ( 1 ) to as ( s − 1 ) in the second set 12 and to the second to last address connection contact az ( z − 1 ) in the first set . to address the m regular rows and the q additional columns that define the region c of the memory matrix 50 , a third operating state as shown in fig3 is set by setting the first control bit c 1 on the contact ac to the binary value “ 1 ”, applying a “ 0 ” as second control bit to the last address connection contact az ( z ) in the first set 11 , and applying a “ 1 ” as third control bit to the last address connection contact as ( s ) in the second set 12 . in such a case , the first and gate 33 receives a “ 0 ” at one input , which means that the first control signal u 1 is set to “ 0 ”. the second control signal u 2 is set to “ 1 ”, because the second and gate 34 receives a “ 1 ” at both inputs . in response to the binary value “ 1 ” of the second control signal u 2 , the first changeover switch 31 connects the last address input ez ( z ) of the row address decoder 41 to the second to last address connection contact as ( s − 1 ) in the set 12 , and , in response to the binary value “ 0 ” of the first control signal u 1 , the row address decoder 41 is set to the first row decoding specification ( through its input cz ). in such a setting , the decoder 41 uses , as mentioned , all z bits applied to its address inputs ez ( 1 ) to ez ( z ) for addressing the m regular rows zm ( 1 ) to zm ( m ) of the memory matrix 50 . in response to the binary value “ 0 ” of the first control signal u 1 , the second changeover switch 32 connects the last address input es ( s ) of the column address decoder 42 to the last address connection contact as ( s ) in the set 12 ( this connection is not actually needed in the third operating state of the circuit configuration , but its appearance can be attributed to the nature of the changeover switch used ). in response to the binary value “ 1 ” of the second control signal u 2 , the column address decoder 42 is set to a second column decoding specification ( through its input cs ). in such a setting , the decoder 42 uses only the l ≦ s − 2 bits applied to its address inputs es ( 1 ) to es ( l ) for addressing the q additional columns sq ( 1 ) to aq ( q ) of the memory matrix 50 . in the circuit configuration &# 39 ; s third operating state , as so defined , the l row address bits z ( 1 ) to s ( l ) required for addressing the q additional columns are applied to the l address connection contacts as ( 1 ) to as ( l ) in the second set 12 , and the z row address bits z ( 1 ) to z ( z ) required for addressing the m regular rows are applied to the address connection contacts az ( 1 ) to az ( z − 1 ) in the first set 11 and to the second to last address connection contact as ( s − 1 ) in the second set 12 . to address the p additional rows and the q additional columns that define the region d of the memory matrix 50 , a fourth operating state as shown in fig4 is set by setting the first control bit cl on the contact ac to the binary value “ 1 ”, applying a “ 1 ” as second control bit to the last address connection contact az ( z ) in the first set 11 , and applying a “ 1 ” as third control bit to the last address connection contact as ( s ) in the second set 12 . in such a case , the first and gate 33 receives a “ 1 ” at both inputs , which means that the first control signal u 1 is set to “ 1 ”. the second control signal u 2 is , likewise , set to “ 1 ” because the and gate 34 also receives a “ 1 ” at both inputs . in response to the binary value “ 1 ” of the second control signal u 2 , the first changeover switch 31 naturally connects the last address input ez ( z ) of the row address decoder 41 to the second to last address connection contact as ( s − 1 ) in the set 12 ( although this connection is not needed in this case ). in response to the binary value “ 1 ” of the first control signal u 1 , the row address decoder 41 is set to the second row decoding specification ( through its input cz ). in such a setting , the decoder 41 uses , as mentioned , only k bits applied to its k address inputs ez ( 1 ) to ez ( k ) for addressing the p additional rows zp ( 1 ) to zp ( p ) of the memory matrix 50 . in response to the binary value “ 1 ” of the first control signal u 1 , the second changeover switch 32 naturally connects the last address input es ( s ) of the column address decoder 42 to the second to last address connection contact az ( z − 1 ) in the set 11 ( although this connection is also not needed in this case ). in response to the binary value “ 1 ” of the second control signal u 2 , the column address decoder 42 is set to the second column decoding specification ( through its input cs ). in such a setting , the decoder 42 uses , as mentioned , only l bits applied to its address inputs es ( 1 ) to es ( l ) for addressing the q additional columns sq ( 1 ) to aq ( q ) of the column matrix 50 . in the circuit configuration &# 39 ; s fourth operating state , as so defined , the k row address bits z ( 1 ) to z ( k ) required for addressing the p additional rows are applied to the address connection contacts az ( 1 ) to az ( k ) in the first set 11 , and the l row address bits z ( 1 ) to s ( l ) required for addressing the q additional columns are applied to the l address connection contacts as ( 1 ) to as ( l ) in the second set 12 . the ordinate numbers used in the above description and in the figures and also indicated in brackets for the various address bits , address connection contacts , and decoding inputs , preferably ( even though not necessarily ) correspond to the respective ordinate number for the place value of the bits in question . that is to say , that “ first ” is associated with the lowest bit place value , and “ last ” is associated with the highest bit place value . as can be seen from the description above and from the figures of the drawing , the way in which the address bits of the regular rows and columns are distributed over the address connection contacts changes for different operating states . the additional involvement for the relevant reordering of the address bits can be moved to the external assembly , which is connected upstream of the address connection contacts during operation and can be configured to perform suitable address scrambling . following testing of the memory cells in all the matrix regions by setting the four operating states described above and following programming of the fuse banks for replacing faulty instances of the regular rows / columns with fault - free instances of the additional rows / columns , the circuit configuration can be used normally as a memory circuit with a fault - free m - times - n matrix , specifically , in the first operating state as shown in fig1 where the control bit connection contact is permanently held at “ 0 ”. alternatively , a further subsequent processing operation on the chip can also be used to provide for the changeover device to be completely isolated in terms of its function and for a permanent state to be set up instead , in which the switched connections shown in fig1 exist between the address connection contacts and the decoder inputs and in which the decoders are set to their respective first decoding specification ( as shown in fig1 ). this has the advantage that the control bit connection contact can subsequently be wired for other purposes on the chip so that it may be possible to dispense with a wide “ pad ” that would otherwise need to be available for such further purposes . on the other hand , however , it can be useful to retain the changeover device &# 39 ; s operability while the memory circuit is being used as well . it is , thus , possible , by accessing the control bit connection contact , to write and read additional information to / from memory cells in ( fault - free ) instances of the additional rows and columns of the memory matrix . such information can be , by way of example , security information that is intended to be available only to those users for whom access to the control bit connection contact is specifically possible .