reference will now be made in detail to embodiments of the present invention , examples of which are illustrated in the accompanying drawings , wherein like reference numerals refer to the like elements throughout . the embodiments are described below to explain the present invention by referring to the figures . the term switch as used herein refers to any of : silicon controlled rectifier ( scr ), insulated gate bipolar junction transistor ( igbt ), bipolar junction transistor ( bjt ), field effect transistor ( fet ), junction field effect transistor ( jfet ), switching diode , mechanically operated single pole double pole switch ( spdt ), spdt electrical relay , spdt reed relay , spdt solid state relay , insulated gate field effect transistor ( igfet ), diode for alternating current ( diac ), and triode for alternating current ( triac ). the term “ zero current switching ” ( or “ zcs ”) as used herein is when the current through a switch is reduced to significantly zero amperes prior to when the switch is being turned either on or off . the term “ power converter ” as used herein applies to dc - to - dc converters , ac - to - dc converters , dc - to - ac inverters , buck converters , boost converters , buck - boost converters , full - bridge converters and half - bridge converters or any other type of electrical power conversion / inversion known in the art . the term “ zero voltage switching ” ( or “ zvs ”) as used herein is that the peak voltage across a switch , is reduced to substantially zero volts when the switch is being turned either on or off . the term “ cycle ” or “ commutation cycle ” refers to the periodicity of main switch positions in a circuit which performs a process of electrical power conversion or inversion . the term “ non - resonant ” as used herein to exclude resonant and quasi - resonant circuits used in the prior art for zero current switching . resonant switching implies that the switching frequencies are similar to a resonant frequency of a resonant tank circuit in the switching converter . the terms “ charging ” and “ discharging ” in the context of the present invention in reference to charging and discharging a capacitor , are used herein interchangeably except that current flow while charging and discharging is usually in the opposite direction . reference is now made to fig3 ( including fig3 a - 3 e ) showing a buck - boost dc - to - dc converter 30 according to an embodiment of the present invention . a buck circuit 32 of buck - boost dc - to - dc converter 30 has an input voltage v in with an input capacitor c 1 connected in parallel across v in . two switches q 1 and q 2 are connected in series at node a by connecting the source of q 1 to the drain of q 2 . the drain of q 1 and the source of q 2 are placed in parallel across capacitor c 1 . the source of q 2 is connected to ground . the other end of inductor 106 is connected in the present example to a boost circuit 34 of buck boost dc - to - dc converter 30 at node b . a zero - voltage switching feature according to embodiments of the present invention is provided using switch module 300 . switch module 300 has a switch q 5 , the drain of q 5 is connected to node a of buck circuit 32 via link 308 . the source of q 5 connects to one end of an auxiliary inductor 302 to form a node e . a cathode of discharge diode d 1 connects to node e and the anode of discharge d 1 connects to ground . the other end of auxiliary inductor 302 connects to the source of switch q 6 . the drain of q 6 connects to node b of boost circuit 34 via a link 310 . reference is still made to buck - boost dc - to - dc converter 30 shown in fig3 a - 3 e which illustrate operation of buck - boost dc - to - dc converter 30 and fig4 showing a flow diagram of a method for zero current switching , for zero current switching in boost and / or buck topologies running in continuous mode during the turn on of main switch q 3 and / or q 1 according to embodiments of the present invention . throughout the following illustration using fig3 a - 3 e , an electrical property of an inductor is relied upon ; namely that when a voltage v is applied across an inductor , the initial current through the inductor is zero and after a certain time period inductor current i l builds up linearly . in fig3 a - 3 e , current flow in buck circuit 32 , boost circuit 34 and switch module 300 is indicated by arrow markings and gray shaded lines . a . reference is now made to fig3 a which illustrates the state of dc - to - dc converter 30 prior to buck turn on . switch q 2 is on . switches q 1 , q 5 and q 6 are off . current flows through inductor 106 from node a to node b and switch q 2 . switch q 2 turns off and current continues to flow through the parasitic diode of switch q 2 . b . reference is now made to fig3 b which continuous to illustrate the state of dc - to - dc converter 30 prior to buck leg turn on . switches q 5 and q 6 turn on at zero current at i aux . current i aux through auxiliary conductor and switches q 5 and q 6 increases linearly as auxiliary inductor 302 is charged by output voltage v out . the direction of current i aux opposes current i p through main inductor 106 and flows from node b to node a . switches q 1 , and q 2 , are off but current i p flows through inductor 106 from node a to node b through the parasitic diode of switch q 2 . c . reference is now made to fig3 c which illustrates the state of dc - to - dc converter 30 as buck leg turns on . when current i aux equals current i p through inductor 106 plus q 2 diode recovery current , the voltage v buck across q 2 starts to rise . switch q 1 then turns on at zero current . switch q 2 remains off . switches q 5 and q 6 remain on and i aux begins to decrease discharging from v in to v out . d . reference is now made to fig3 d which continues to illustrate the state of dc - to - dc converter 30 as buck leg turns on ; q 5 turns off when current through i aux gets low ( i . e . substantially zero current switching ), the current i aux flows through q 5 parasitic diode . the current i aux reverses because of q 5 reverse recovery current . this reverse recovery current discharges through the discharge diode d 1 and q 6 . e . reference is now made to fig3 e which illustrates the state of dc - to - dc converter 30 after buck leg turns on . current i p flows through switch q 1 through inductor 106 and through boost circuit 34 . current i aux falls to zero and switch q 6 is turned off . fig4 shows a simplified flow diagram of a method for zero current switching according to an embodiment of the present invention . still referring to the embodiment of fig3 , in step 41 , auxiliary inductor 302 is connected to main inductor 106 in parallel by auxiliary switches q 5 and q 6 . when the total current is substantially zero in decision box 43 , main switch q 1 is switched on ( step 45 ) at zero current . a preferred method of determining when the total current reached is zero is to use a zero current sensing circuit or to turn q 1 on at a time according to the timing transients of either auxiliary inductor 302 or inductor 106 . when the current in auxiliary inductor 302 is substantially zero in decision box 47 , auxiliary switch q 6 is switched off ( step 49 ) at zero current and inductor 302 is disconnected across inductor 106 . a preferred method of determining when the current in auxiliary inductor 302 approaches zero current , is to use a zero current sensing circuit or to turn q 6 off at a time according to the timing transients of either auxiliary inductor 302 or inductor 106 . fig5 shows a further embodiment of present invention as applied to a full bridge dc to dc converter 50 . full bridge dc to dc converter 50 has four main switches s m , 1 , s m , 2 , s m , 3 and s m , 4 connected together in a full bridge configuration . each of four main switches ( s m , 1 , s m , 2 , s m , 3 and s m , 4 ) have respective diode shunts connected in parallel thereto . the diodes placed across switches s m , 1 and s m , 2 are in both the same direction similarly the diodes of s m , 3 and s m , 4 are both in the same direction . all diodes connected across switches s m , 1 , s m , 2 , s m , 3 and s m , 4 are reverse biased with respect to the input voltage v in . an input voltage ( v in − ) of full bridge dc - to - dc converter 50 is connected across the node between switches s m , 2 and s m , 4 and an input voltage ( v in + ) is connected at the node between switches s m , 1 and s m , 3 . an output voltage ( v out − ) of full bridge dc - to - dc converter 50 is connected across the node ( m ) between switches s m , 1 and s m , 2 connected through a split inductor 500 a and output voltage v out + is connected at the node ( l ) between switches s m , 3 and s m , 4 through a split inductor 500 b . an auxiliary switch s a , 1 is connected between nodes m and k . a diode is placed across in parallel with s a , 1 with the cathode of the diode connected to node m and the anode of the diode connected to node k . a discharge diode d 1 is connected between node k and v in − with the anode of d 1 connected to v in − and the cathode of d 1 connected to node k . one end of an auxiliary inductor 502 connects to node k . the other end of auxiliary inductor 502 connects to node j . a discharge diode d 2 is connected between node j and v in − with the anode of d 2 connected to v in − and the cathode of d 2 connected to node j . an auxiliary switch s a , 2 is connected between nodes j and l . a diode is placed across in parallel with s a , 2 with the cathode of the diode connected to node l and the anode of the diode connected to node j . the operation of full bridge circuit 50 , according to a feature of the present invention is illustrated with reference also to fig5 a - 5 e and fig6 which shows a timing diagram of selected voltages and currents for steps v to z is as follows : fig5 a - 5 e illustrate current flow is indicated by arrow markings and gray shaded lines . v ) referring now specifically to fig5 a : main switches s m , 1 and s m , 4 are turned on , all other switches are off . current i p flows from v out − to v in + through inductor 500 a , and through main switch s m , 1 . current flows from v in − to v out + through main switch s m , 4 and through inductor 500 b . w ) referring now specifically to fig5 b ; switches s m , 1 and s m , 4 are turned off . switches s a , 1 and s a , 2 are turned on . current i aux begins at zero current and increases linearly , current i aux flowing between nodes m and l . because the current i aux is initially zero , the switching on of switches s a , 1 and s a , 2 , occurs with zero current . current flows from v out − to v in + through inductor 500 a , and through the diode of main switch s m , 1 current flows from v in − to v out + through the diode of main switch s m , 4 and through inductor 500 b . x ) referring now specifically to fig5 c ; once the auxiliary current i aux reaches a peak value , equaling to i p , main switches s m , 2 and s m , 3 are turned on with zero current since kirchhoff &# 39 ; s current equation at node m shows current through main switch s m , 2 : is m , 2 = i p − i aux = 0 and kirchhoff &# 39 ; s current equation at node l shows is m , 3 = i p − i aux = 0 . current flows from v in + to v out + through main switch s m , 3 , and through inductor 500 b . current now flows from v out − to v in − through inductor 500 a and through main switch s m , 2 . y ) referring now specifically to fig5 d ; auxiliary switch s a , 2 is now turned off as current i aux has reduced to substantially zero in the direction of node m to node l . diode d 2 takes any reverse recovery current from switch s a , 2 . current flows into v out + from v in + through inductor 500 b , and through main switch s m , 3 current now flows into v in − from v out − through main switch s m , 2 and through inductor 500 a . z ) referring now specifically to fig5 e ; auxiliary switch s a , 1 is now turned off with zero current i aux . current flows into v out + from v in + through inductor 500 b , and through main switch s m , 3 current now flows into v in − from v out − to through main switch s m , 2 and through inductor 500 a . similar switching steps occur when the current at the main inductor 500 is reverse in polarity . switch pairs ( s m , 1 , s m , 2 ), ( s m , 4 , s m , 3 ), ( s a , 1 , s a , 2 ) and diodes ( d 2 , d 1 ) are swapped at the above description to accomplish this symmetrical case . the definite articles “ a ”, “ an ” is used herein , such as “ a converter ”, “ a switch ” have the meaning of “ one or more ” that is “ one or more converters ” or “ one or more switches ”. although selected embodiments of the present invention have been shown and described , it is to be understood the present invention is not limited to the described embodiments . instead , it is to be appreciated that changes may be made to these embodiments without departing from the principles and spirit of the invention , the scope of which is defined by the claims and the equivalents thereof .