aside from the preferred embodiment or embodiments disclosed below , this invention is capable of other embodiments and of being practiced or being carried out in various ways . thus , it is to be understood that the invention is not limited in its application to the details of construction and the arrangements of components set forth in the following description or illustrated in the drawings . if only one embodiment is described herein , the claims hereof are not to be limited to that embodiment . moreover , the claims hereof are not to be read restrictively unless there is clear and convincing evidence manifesting a certain exclusion , restriction , or disclaimer . there is shown in fig1 an automatic power saving system 10 according to this invention and a signal processor 12 . signal processor 12 includes a digital state machine 14 , some predetermined power consuming circuits 16 and other power consuming circuits 18 as well as a communications interface 20 . predetermined power consuming circuit 16 consumes substantial power while other power consuming circuits 18 consumes lower amounts of power . both gather and / or process information in conjunction with digital state machine 14 . the final output data is delivered to further processors or displays by communication interface 20 . signal processor 12 typically also includes a clock 22 which normally operates digital state machine 14 , predetermined power consuming circuits 16 and other power consuming circuits 18 . in accordance with this invention the automatic power saving system 10 includes supply monitor 24 , an electromagnetic interference ( emi ) response control 26 and clock gate circuit 28 . when the power supply voltage vdd drops to some preselected level supply monitor 24 senses that level and provides a signal to emi response control 26 . it in turn operates clock gate circuit 28 to halt the clock signals from clock 22 to at least predetermined power consuming circuits 16 . it may also halt the clock signals to other power consuming circuits 18 and even digital state machine 14 . digital state machine 14 may be halted in this manner because supply monitor 24 and emi response control 26 operate their decision making process independent of digital state machine 14 . digital state machine 14 and other power consuming circuits 18 may receive their clock signals directly from clock 22 and not under control of clock gate circuit 28 . when , then , supply monitor 24 senses a sufficient drop in supply voltage vdd to trigger emi response control 26 operation , clock gate circuit 28 halts clock signals to predetermined power consuming circuits 16 in order to save power so that at least for some specified period the system conserves power . however , even though predetermined power consuming circuit 16 and even other power consuming circuits 18 and digital state machine 14 may be denied operation due to disablement of the clock signal , communication interface 20 is not . therefore , communication interface 20 operates continuously and gives the appearance of full operation even though the information gathering and processing operations of circuits 16 and 18 and even digital state machine 14 may be inoperative . a more specific embodiment of the invention in a vehicle application is shown in fig2 where like parts have been given like numbers accompanied by a lower case a . there it can be seen that clock gate circuit 28 a actually includes two clock gates clock gate one , 30 and clock gate two , 32 . predetermined power consuming circuits 16 a are represented in this case by one circuit : transducer signal channel 34 , although two or many more circuits could be included . transducer signal channel 34 contains a number of digital and analog circuits to produce an ultrasonic pulse and listen to the returning echo . the other power consuming circuits 18 a may include for example a temperature sensor 36 and a low frequency oscillator 38 which drives a watch dog circuit 40 . digital state machine 14 may include a microprocessor controller 14 a which may have a microprocessor 42 , read only memory 44 , static random access memory 46 and one time programmable memory 48 . a power - on reset 50 may be provided for when a complete restart is required . microprocessor controller 14 a may include a non - volatile multi - time programmable memory ( nvmtpm ) such as , but not limited to eeprom , flash memory , feram . signal processor 12 a may be formed of conventional devices . for example temperature sensor 36 may contain an analog to digital converter which provides a digital code representing temperature . low frequency oscillator 38 may provide an approximately 130 khz signal for timing the watchdog timer . the watchdog timer 40 can reset the part if it does not periodically receive the correct sequence from the microprocessor . digital communications interface 20 a communicates with the rest of the vehicle through a serial digital interface . there are three formats available : pulse width modulation ( pwm ), local interconnect network ( lin ), and signal edge nibble transmission ( sent ). transducer signal channel 16 a typically contains a number of digital and analog circuits to produce an ultrasonic pulse and listen to the returning echo which it relays to microprocessor controller 14 a . high frequency oscillator 22 a typically supplies a 20 mhz signal for clocking the digital system , in most cases this may be divided down to 2 . 5 mhz before being used . supply monitor 24 a provides a signal when the power supply falls before 8 volts for example . this signal is then acted on by emi response controller 26 a which then takes measures to conserve power . it does so by operating clock gates 30 and 32 included in clock gate circuit 28 a . clock gate one , 30 , halts the clock signal to transducer signal channel 34 ; clock gate two , 32 , may be provided to actually halt clock signals to microprocessor controller 14 a . both the automatic power saving system 10 a and signal processor 12 a are driven by a 3 . 3 volt supply from low drop out regulator ( ldo ) 60 which regulates the automobile battery voltage from 12 volts to 3 . 3 volts . it is connected to the power supply terminal 62 . it should be understood that in the example of this embodiment the application of the invention is for an automobile and so the power supply is the automobile battery , but this is an example only and in no way limits the invention : the power supply is not limited to a battery or any of the specifics shown here . also included is a digital communications physical circuit 64 which translates the 0 to 3 . 3 volt logical level output of digital comms 20 a to the 0 to 12 volt level in the remainder of the circuit . digital communications physical 64 is connected to communications terminal 66 . there is also a ground terminal 68 . transducer signal channel 34 provides transmission pulses to and receives return pulses from h bridge driver 70 , which through transducer terminals 72 and 74 connect to a transducer such as an acoustic transducer 76 . h bridge driver 70 contains high voltage switches to apply a high amplitude ultrasonic pulse onto the ultrasonic transducer 76 . transducer 76 when receiving a transmission pulse produces an acoustic pulse which reflects off a surface or object of interest and returns through transducer terminal 72 , 74 back to h bridge circuit 70 where the return pulse causes transducer signal channel 34 to respond to microprocessor controller 14 a . all of these elements plus signal processor 12 a and automatic power saving system 10 a are included in a vehicle application module which has a power supply pin 82 , ground pin 84 and a communications pin 86 . the battery voltage vbat is delivered through reverse bias diode 88 to the power supply terminal vdd 62 . also connected to terminal 62 is decoupling capacitor 90 and zener diode 92 . reverse bias diode 88 prevents the charge on coupling capacitor 90 being drawn down when vbat decreases . the reverse bias diode 88 may also be implemented using a diode connected mosfet . decoupling capacitor 90 , typically 100 nf , smoothes out disturbances on the external supply . due to space restrictions within the module in some applications the size of this capacitor cannot be increased . zener diode 92 prevents the voltage on decoupling capacitor 90 from exceeding the zener voltage , for example 24 volts . there is an interconnection shown between emi response controller 26 a and microprocessor controller 14 a in fig2 . this is so that the microprocessor controller 14 a can monitor the occurrence of emi interruptions . thus microprocessor controller 14 a operates in the following fashion as shown in fig2 a . it initiates by beginning a time sensitive operation 200 and then it waits for that activity to be completed . if in the interim there was an emi interruption this is detected at 204 and the time sensitive operation is repeated after the power supply recovers . the microprocessor may wait a short period of time before repeating the operation , for example , if the previous operation involved an ultra sonic pulse the microprocessor may wait until return echos , have ceased . if there was no emi interruption then the results , for example , the output of transducer signal channel 34 , are processed 206 and the results 208 are delivered to the digital communications circuit 20 a . the efficacy of this invention can be better understood with reference to the examples shown in fig3 and 4 which show the variation of the voltage on the capacitor ( 90 vdd ) not to be confused with the external supply ( 82 , vbat ) which is being interrupted . time of the power supply interruption is specified as a maximum of 50 microseconds . there are three states shown . state a which is the normal state and covers the voltage range from approximately 12 volts down to 4 . 2 . state b is the range from 4 . 2 volts to 2 . 4 volts : here below the approximately 4 . 2 volt minimum the system will continue to function but with degraded performance and with no loss of memory so that whatever processing was being performed when the clock signal was halted will be resumed . state c is the range from 2 . 4 volts to 0 volts , here there is no operation and memory is lost so that the system would have to be reset . in fig3 an acoustic pulse occurs simultaneously with an interruption in the power supply . there the voltage 100 drops sharply within 7 or 8 microseconds from 12 volts down to roughly six volts . if nothing is done , then , as shown at line 102 , the system enters state b , at about 15 microseconds and has completely discharged the decoupling capacitor 90 in little more than 35 microseconds . however , with this invention shutting down the predetermined power consuming circuits 16 , e . g . transducer signal channel 34 , the discharge path shallows out as shown at 104 and at 50 microseconds has barely reached 4 . 2 volts . that is , it is on the border between normal state , state a and state b . in fig4 the acoustic pulse occurs during power supply interruption and there is a similar improvement in operation . here capacitor 90 ( voltage vdd 62 ) is discharging , 100 a , then the supply monitor 24 a operates , 106 , at the 8 volt level and the voltage begins to drop abruptly 108 . within two microseconds emi response control 26 a operates at least clock gate one , 30 , and the shallower slope of discharge 110 is returned to so that at 50 microseconds the voltage is only dropped to approximately 4 . 5 volts . application module 80 , fig5 , has its pins 82 , 86 and 84 connected through a wiring harness 120 to an engine control unit 122 conventionally contained in a vehicle . also contained in a vehicle is a 12 volt battery 124 as the power supply . the engine control unit , as is well known , monitors and controls activities in the car engine and communicates with the application module 80 over the communications line on pin 86 . when an electromagnetic interference event occurs , the engine control unit 122 must not be able to detect any problems with the application module 80 . from the engine control unit 122 point of view there are three operating modes of the applications module as explained previously . in state a all functions are correct and within expected limits ; in state b there is degradation of functions but no loss of stored memory data ; in state c there is no damage to the applications module but complete or partial loss of stored memory occurs and the applications module can return to normal operation after the electromagnetic interference event . an electromagnetic interference event may occur through the wiring harness , e . g . from the car starter motor , alternator malfunction , or the automobile passing through radar installation near an airport , cellular phones . the electromagnetic event as explained in this particular embodiment is shown in the graphical illustration in fig5 , where the power supply is at 12 volts , 125 , but can drop as much as 50 volts as at 126 for as long as 50 microseconds as shown at 128 before recovery occurs . the voltage levels and the times may vary in which case the parameters of the embodiment would change accordingly . supply monitor 24 a may include a comparator circuit 130 , fig6 , and a voltage reference source 132 . in this case the reference voltage is 8 volts as indicated previously , so when comparator circuit 130 senses that the supply voltage vdd has dropped below 8 volts , it provides a signal to emi response control 26 a which then disables clock gate one , 30 which halts the signal on line 134 to transducer signal channel 34 and also halts the clock signal on line 136 from clock gate two , 32 , to microprocessor 42 . transducer signal channel 34 in fig6 is shown as having a digital section 140 and an analog section 142 . in the usual manner the digital section 140 requests that the analog signal activate and send a pulse to the transducer 76 and also process the return pulse . however , in accordance with this invention digital section 140 does not directly operate the analog section 142 , rather analog section 142 is operated by the output from logic gate 144 . logic gate 144 provides an output as long as it receives an enabling input at pin 146 from emi response control 26 a indicating that the power supply is still operating properly , that is , above 8 volts and that the digital section 140 has called for analog operation . only then will the analog section communicate a pulse to transducer 76 and respond to the return pulse . only when transducer signal channel 34 receives the return pulse and has processed it will it be transferred to microprocessor controller 14 a . if before the processing in transducer signal channel 34 is complete , the clock signal to it has been halted , there will be pulse information returned to the microprocessor controller , however it will be invalid and unusable due the interruption in processing caused by the power interruption and when the power supply returns to normal operation range the microprocessor controller will begin again by repeating that operation . in order to accommodate the supply monitor 24 b , fig7 , so that it can monitor a 12 volt power supply while being operated from only a 3 . 3 volt power supply . a pair of voltage dividers 150 and 152 are included to step down the power supply level and the 3 . 3 volt supply level reference at the input of comparator circuit 130 a to levels which are proportional to 12 volts and proportional to 8 volts , respectively . the method of this invention is shown in fig8 and begins simply with the inquiry as to whether a power supply interruption has been sensed 160 , if it has not the clock pulses to all circuits are continued 162 . if the response is affirmative , then the clock signals to predetermined power consuming circuits are halted , 164 , but the clock signals to the communications interface 166 are continued and the system loops back to inquire once again is there a power supply interruption . although specific features of the invention are shown in some drawings and not in others , this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention . the words “ including ”, “ comprising ”, “ having ”, and “ with ” as used herein are to be interpreted broadly and comprehensively and are not limited to any physical interconnection . moreover , any embodiments disclosed in the subject application are not to be taken as the only possible embodiments . in addition , any amendment presented during the prosecution of the patent application for this patent is not a disclaimer of any claim element presented in the application as filed : those skilled in the art cannot reasonably be expected to draft a claim that would literally encompass all possible equivalents , many equivalents will be unforeseeable at the time of the amendment and are beyond a fair interpretation of what is to be surrendered ( if anything ), the rationale underlying the amendment may bear no more than a tangential relation to many equivalents , and / or there are many other reasons the applicant can not be expected to describe certain insubstantial substitutes for any claim element amended . other embodiments will occur to those skilled in the art and are within the following claims .