referring specifically to the figure , the number 10 designates a main antenna , which may be for example a directional type antenna . the antenna 10 is connected through a bandpass filter 11 and other circuitry ( not shown ) to one input of a summing device 15 . the broken line between the bandpass filter 11 and summing device 15 indicates that apparatus not pertinent to this invention is omitted therefrom . generally , this omitted apparatus is referred to as a receiver and may be , for example , apparatus for converting the signal to an intermediate frequency signal , amplifying devices , etc . the number 16 indicates an auxiliary antenna , which generally will be an omnidirectional antenna . also , in sidelobe cancelling circuitry of this type it will be understood by those skilled in the art that additional auxiliary antennas may be utilized since it is generally well known that an auxiliary antenna and the associated sidelobe cancelling circuitry is required for each interference signal to be cancelled . however , in the present embodiment only one auxiliary antenna 16 is illustrated for convenience and a complete sidelobe interference cancelling system is described therewith . the auxiliary antenna 16 is connected through a bandpass filter 17 to a delay 19 , a 90 ° phase shifting network 20 and a mixer or weighting device 21 . the output of the phase shifting device 20 is connected to an input of a second mixer or weighting device 22 . the outputs of the weighting devices 21 and 22 are connected to two more inputs of the summing device 15 ( the broken lines indicating that additional equipment such as receivers have been eliminated because it does not form a portion of this invention or in any way effect the operation thereof ). the output of the summing device 15 is connected to a clutter compensating circuit , generally designated 25 ( enclosed within dotted lines ) and to a delay 26 . an output of the clutter compensating circuit 25 is connected to a negative input of a summing device 30 and the output of the delay circuit 26 is connected to a positive input of the summing device 30 . an output of the summing device 30 is applied to an output terminal 31 , which serves as an output for the system and , as illustrated , may apply the output signals to , for example , an mti processor . the output of the summing device 30 is also connected to inputs of a pair of mixers or correlation circuits 35 and 36 . the output of the delay circuit 19 is connected to a second input of the correlation circuit 36 and through a 90 ° phase shift circuit 37 to a second input of the correlation circuit 35 . the correlation circuits 35 and 36 each compare signals at the two inputs thereof and provide an output signal which is indicative of correlation between the two input signals . the outputs of the correlation circuits 35 and 36 are connected through integrater amplifiers 38 and 39 , respectively , to inputs of mixers or weighting circuits 22 and 21 , respectively . the output signals of the integrator amplifiers 38 and 39 are essentially weighting control signals which adjust the weighting devices 22 and 21 to minimize the control signals or minimize correlation between signals applied to the correlation circuits 35 and 36 . the phase and amplitude ( weighting ) of the signals applied to the summing device 15 from the weighting devices 21 and 22 will be such as to cause cancellation of a portion of the signal from the main antenna 10 which is received by the auxiliary antenna 16 and which is correlated with the clutter compensated signal appearing at the output of terminal 31 . the combined signal at the output of the summing device 15 and present at the input of the clutter compensating circuit 25 is applied to inputs of a pair of mixers 40 and 41 . a local oscillator 45 applies a second signal to the mixer 40 and applied a second signal through a phase shifting circuit 46 to the mixer 41 . the combined signal at the output of the summing device 15 is generally at an intermediate frequency and the clutter compensating circuit 25 , as disclosed in this embodiment , operates at the base band frequency so that the local oscillator 45 and mixers 40 and 41 are used to convert the intermediate frequency combined signal to in - phase and quadrature components of the combined signal at baseband frequency . the output of the mixer 40 which is the in - phase component of the combined signal , is connected through a low pass filter 50 to a positive terminal of a summing circuit 51 . the output of the summing circuit 51 is applied through an amplifier 53 , which supplies an amplification factor of a to a positive input of a second summing circuit 55 . the output of the summing circuit 55 is connected to an input of a clocked memory or storage device 60 , which may be for example a capacitive coupled device ( ccd ) or a shift register or the like . an output of the storage device 60 is connected to a negative input of the summing circuit 51 , a positive input of the summing circuit 55 and an input of a mixer 61 . the output of the local oscillator 45 is connected to a second input of the mixer 61 and the output thereof is connected to a positive terminal of a summing circuit 65 . the quadrature component of the combined signal at the output of the mixer 41 passes through a low pass filter 67 , a summing circuit 68 , and amplifier 69 having an amplification factor of a , a second summing circuit 70 , a storage device 71 and a mixer 73 , all of which are connected as described in conjuction with the in - phase component of the combined signal . in the operation of the clutter compensating circuit 25 and referring to the in - phase component of the combined signal as an example , the low pass filter 50 removes un - wanted high frequency noise and the summing circuit 51 compares the difference between the stored signal in the storing device 60 and the next portion or current signal from the summing device 15 . assuming that the communications system disclosed is a pulsed radar with range bins ( the operation of which is well known in the art ) the storage device 60 has sufficient elements therein to store the data in each range bin in a separate element . the clocking of the storage device 60 is sufficiently high to circulate all of the data in all of the elements once per radar pulse ( between the actual transmitted pulses ). thus , the data stored in the first element , designated by the number 80 , will always be compared to the first range bin of the return pulse in the summing device 51 and the last element , designated 81 , will always be compared with the final range bin in the radar return by the summing device 51 . the summing device 51 provides a signal indicative of the difference between the two signals applied to the inputs thereof and the amplifier 53 supplies an amplification factor of a to the signal . in general , the amplification factor a will be between 0 and 1 and should be relatively high ( near unity ) for fast changing back ground scenes and near 0 for slow changing scenes . the amplifier 53 may have an automatically varying amplification factor , it may be adjusted manually by an operator or it may be fixed at some convenient level depending upon the expected background . in essence , the amplifier 53 selects only a portion of the output of the summing device 51 and couples it to the summing device 55 . the summing device 55 also receives the output of the storage device 60 directly so that it periodically updates the estimate of clutter stored in the storage device 60 . the output of the storage device 60 is again converted to an appropriate intermediate frequency by the mixer 61 and recombined with the quadrature component , which is operated upon as described in conjunction with the in - phase component . the output of the summing device 65 , which is an updated estimate of clutter , is applied to the summing device 30 where it is subtracted from the combined signal after the combined signal is delayed in the delay 26 sufficiently to provide a proper time sequence . generally , the delay 26 may be a ccd or a shift register equivalent to the devices 60 or 71 so as to delay the combined signal an amount equal to the delay of the signal passing through the clutter compensating circuit 25 . because the output of the summing device 30 is correlated with the signal from the auxiliary antenna 16 in correlators 35 and 36 , the delay 19 ( similar to the delay 26 ) must be included in the connection from the auxiliary antenna 16 to bring the signals into the proper time sequence . in general , the intent of this disclosure is to define an efficient recursive estimation circuit , based on principles of kalman filtering ( kalman , r . e . and bucy , r . s . : &# 34 ; new results in linear filtering and prediction theory &# 34 ; j . basic engineering march 1961 ) for compensating a sidelobe cancellation system against the deleterious effects of clutter . essentially this circuit takes into account the a priori statistical properties of the clutter signal such as correlation over time , defines an optimal estimate of the clutter signal component , and removes this clutter signal component from the signal entering the sidelobe cancelling circuitry ( at mixers 35 and 36 ). control of the gain a ( 53 and 69 ) may be varying with time over a finite record of samples and would be selected to define the optimal estimate of clutter , given the finite number of samples collected . while i have shown and described a specific embodiment of this invention , further modifications and improvements will occur to those skilled in the art . i desire it to be understood , therefore , that this invention is not limited to the particular form shown and i intend in the appended claims to cover all modifications which do not depart from the spirit and scope of this invention .