embodiments of the present invention will be described hereinafter with reference to the accompanying drawings . however , the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention . referring to fig2 , a semiconductor system according to an embodiment of the present invention may include a controller 1 and a semiconductor memory device 2 . the controller 1 may generate a first command signal mrr , first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ;, first to fourth background control signals dc 2 & lt ; 1 : 4 & gt ; and a second command signal mrw . the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ;, first to fourth background control signals dc 2 & lt ; 1 : 4 & gt ; and a second command signal mrw may be generated by first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; provided from the semiconductor memory device 2 . the semiconductor memory device 2 may be configured to output the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; and the first to fourth background data dq 2 & lt ; 1 : 4 & gt ; in response to the first command signal mrr . further , the semiconductor memory device 2 may be configured to store the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; and the first to fourth background control signals dc 2 & lt ; 1 : 4 & gt ; therein in response to the second command signal mrw . moreover , the semiconductor memory device 2 may be configured to control drivabilities of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; and the first to fourth background data dq 2 & lt ; 1 : 4 & gt ; according to a level combination of the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; and the first to fourth background control signals dc 2 & lt ; 1 : 4 & gt ;. the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; may control the drivability of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; and the first to fourth background control signals dc 2 & lt ; 1 : 4 & gt ; may control the drivability of the first to fourth background data dq 2 & lt ; 1 : 4 & gt ;. as shown in fig3 , the controller 1 may include a command generator 11 , a selection signal generator 12 , a comparison signal generator 13 and a control signal generator 14 . the command generator 11 may be configured to generate a pulse of the first command signal mrr in response to a test enable signal tmen enabled when a test mode starts . further the command generator 11 may be also configured to generate a pulse of the first command signal mrr even when a level combination of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; or the first to fourth background data dq 2 & lt ; 1 : 4 & gt ; is different from a predetermined level combination . further , the command generator 11 may be configured to generate a pulse of the second command signal mrw when the level combination of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; or the first to fourth background data dq 2 & lt ; 1 : 4 & gt ; is identical to the predetermined level combination . the selection signal generator 12 may be configured to generate a selection signal sel having a first level and a second level which is opposite to the first level . the selection signal may become the first level ( e . g ., a logic “ low ” level ) if a pulse of a read latency signal rdout is inputted after a predetermined time elapses from a time that the pulse of the first command signal mrr is generated . further , the selection signal sel may become the second level ( e . g ., a logic “ high ” level ) if the level combination of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; or the first to fourth background data dq 2 & lt ; 1 : 4 & gt ; is identical to the predetermined level combination after the pulse of the read latency signal rdout is inputted . the read latency signal rdout may correspond to a signal which is enabled after the semiconductor memory device 2 outputs data in response to the first command signal mrr . the comparison signal generator 13 may include a multiplexer 131 , a comparison code generator 132 and a comparator 133 . the multiplexer 131 may be configured to output the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; as first to fourth selection data sd & lt ; 1 : 4 & gt ; when the selection signal sel has the first level ( e . g ., a logic “ low ” level ) and output the first to fourth background data dq 2 & lt ; 1 : 4 & gt ; as the first to fourth selection data sd & lt ; 1 : 4 & gt ; when the selection signal sel has the second level ( e . g ., a logic “ high ” level ). the comparison code generator 132 may be configured to generate first and second comparison codes s & lt ; 1 : 2 & gt ; whose level combination is determined according to a level combination of the first to fourth selection data sd & lt ; 1 : 4 & gt ;. the comparator 133 may be configured to generate a pulse of a comparison signal comp when a level combination of the first and second comparison codes s & lt ; 1 : 2 & gt ; is different from a level combination of first and second test codes t & lt ; 1 : 2 & gt ; having a predetermined level combination . for example , the comparison signal generator 13 may generate a pulse of the comparison signal comp when the selection signal sel has the first level ( e . g ., a logic “ low ” level ) and the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; have a level combination which is different from the predetermined level combination . further , the comparison signal generator 13 may also generate a pulse of the comparison signal comp even when the selection signal sel has the second level ( e . g ., a logic “ high ” level ) and the first to fourth background data dq 2 & lt ; 1 : 4 & gt ; has a level combination which is different from the predetermined level combination . a level combination of the first and second comparison codes s & lt ; 1 : 2 & gt ; may vary according to the number of bits having a logic “ high ” level among the bits of the first to fourth selection data sd & lt ; 1 : 4 & gt ;. in addition , the predetermined level combination of the first and second test codes t & lt ; 1 : 2 & gt ; may be set such that the first test code t & lt ; 1 & gt ; has a logic “ high ” level and the second test code t & lt ; 2 & gt ; has a logic “ low ” level . however , the predetermined level combination of the first and second test codes t & lt ; 1 : 2 & gt ; may be set to be different according to the embodiments . further , the comparison code generator 132 and the comparator 133 may be received the first command signal mrr , as a control signal . the level combination of the first and second comparison codes s & lt ; 1 : 2 & gt ; according to the number of the bits having a logic “ high ” level among the bits of the first to fourth selection data sd & lt ; 1 : 4 & gt ; may be summarized as described in the following table 1 . the control signal generator 14 may include a counter 141 and a decoder 142 . the counter 141 may be configured to output first and second count signals cnt & lt ; 1 : 2 & gt ;. the first and second count signals cnt & lt ; 1 : 2 & gt ; may be counted when a pulse of the comparison signal comp is inputted . when the selection signal sel has the first level ( e . g ., a logic “ low ” level ), the decoder 142 may decode the first and second count signals cnt & lt ; 1 : 2 & gt ; to generate first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ;. further , when the selection signal sel has the second level ( e . g ., a logic “ high ” level ), the decoder 142 may decode the first and second count signals cnt & lt ; 1 : 2 & gt ; to generate first to fourth background control signals dc 2 & lt ; 1 : 4 & gt ;. that is , the control signal generator 14 may be configured to generate the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; whose level combination changes when the selection signal sel has the first level ( e . g ., a logic “ low ” level ) and a pulse of the comparison signal comp is inputted . further , the control signal generator 14 may be configured to generate the first to fourth background control signals dc 2 & lt ; 1 : 4 & gt ; whose level combination changes when the selection signal sel has the second level ( e . g ., a logic “ high ” level ) and a pulse of the comparison signal comp is inputted . for example , a level combination of the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; according to a level combination of the first and second count signals cnt & lt ; 1 : 2 & gt ; may be summarized as described in the following table 2 . for example , a level combination of the first to fourth background control signals dc 2 & lt ; 1 : 4 & gt ; according to a level combination of the first and second count signals cnt & lt ; 1 : 2 & gt ; may be summarized as described in the following table 3 . the drive signal generator 21 may include an input buffer 211 , a signal storage unit 212 and a data input / output ( i / o ) controller 213 . the input buffer 211 may be configured to buffer the first command signal mrr and the second command signal mrw to generate a first internal command signal ird and a second internal command signal iwt , respectively . the signal storage unit 212 may be configured to output the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; as first to fourth foreground drive signals drv 1 & lt ; 1 : 4 & gt ; and may output the first to fourth background control signals dc 2 & lt ; 1 : 4 & gt ; as first to fourth background drive signals drv 2 & lt ; 1 : 4 & gt ; when the first internal command signal ird is inputted . further , the signal storage unit 212 may be configured to store the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; and the first to fourth background control signals dc 2 & lt ; 1 : 4 & gt ; therein when the second internal command signal iwt is inputted . moreover , the signal storage unit 212 may be configured to output first to fourth pattern data pd & lt ; 1 : 4 & gt ; having a predetermined level combination in response to the first internal command signal ird . the data i / o controller 213 may load the first to fourth pattern data pd & lt ; 1 : 4 & gt ; on first to fourth foreground i / o lines gio 1 & lt ; 1 : 4 & gt ; and on first to fourth background i / o lines gio 2 & lt ; 1 : 4 & gt ;, respectively , when the test enable signal tmen is enabled . further , the data i / o controller 213 may load first to fourth foreground internal data id 1 & lt ; 1 : 4 & gt ; stored in memory cells on the first to fourth foreground i / o lines gio 1 & lt ; 1 : 4 & gt ; and may load first to fourth background internal data id 2 & lt ; 1 : 4 & gt ; stored in memory cells on the first to fourth background i / o lines gio 2 & lt ; 1 : 4 & gt ; when the test enable signal tmen is disabled . for example , the predetermined level combination of the first to fourth pattern data pd & lt ; 1 : 4 & gt ; may be set such that the first and third pattern data pd & lt ; 1 & gt ; and pd & lt ; 3 & gt ; have a logic “ low ” level and the second and fourth pattern data pd & lt ; 2 & gt ; and pd & lt ; 4 & gt ; have a logic “ high ” level . however , the predetermined level combination of the first to fourth pattern data pd & lt ; 1 : 4 & gt ; may be set to be different according to the embodiment . the output buffer 22 may be configured to control the drivability of the first to fourth foreground i / o lines gio 1 & lt ; 1 : 4 & gt ; according to a level combination of the first to fourth foreground drive signals drv 1 & lt ; 1 : 4 & gt ; to generate the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ;. further , the output buffer 22 may be control the drivability of the first to fourth background i / o lines gio 2 & lt ; 1 : 4 & gt ; according to a level combination of the first to fourth background drive signals drv 2 & lt ; 1 : 4 & gt ; to generate the first to fourth background data dq 2 & lt ; 1 : 4 & gt ;. referring to fig5 , the output buffer 22 may include a first output buffer 23 and a second output buffer 25 . the first output buffer 23 may include a first pre - driver 231 and a first driver 232 . the first pre - driver 231 may be configured to control the drivability of the first to fourth foreground i / o lines gio 1 & lt ; 1 : 4 & gt ; according to a level combination of the first to fourth foreground drive signals drv 1 & lt ; 1 : 4 & gt ; to generate first to fourth pre - foreground data pre_dq 1 & lt ; 1 : 4 & gt ;. the first driver 232 may be configured to buffer the first to fourth pre - foreground data pre_dq 1 & lt ; 1 : 4 & gt ; to output the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; through a first pad 24 . the second output buffer 25 may include a second pre - driver 251 and a second driver 252 . the second pre - driver 251 may be configured to control the drivability of the first to fourth background i / o lines gio 2 & lt ; 1 : 4 & gt ; according to a level combination of the first to fourth background drive signals drv 2 & lt ; 1 : 4 & gt ; to generate first to fourth pre - background data pre_dq 2 & lt ; 1 : 4 & gt ;. the second driver 252 may be configured to buffer the first to fourth pre - background data pre_dq 2 & lt ; 1 : 4 & gt ; to output the first to fourth background data dq 2 & lt ; 1 : 4 & gt ; through a second pad 26 . referring to fig6 , the first pre - driver 231 may be configured to include a first buffering unit 2310 , a first inverter iv 20 , a first driving unit 2311 , a second driving unit 2312 , a third driving unit 2313 and a fourth driving unit 2314 . the first buffering unit 2310 may be configured to buffer signals loaded on the first to fourth foreground i / o lines gio 1 & lt ; 1 : 4 & gt ; in response to a read enable signal endq enabled to have a logic “ high ” level when the first command signal mrr is inputted , thereby outputting the buffered signals through a first node nd 21 . for example , the first buffering unit 2310 may include a nand gate nd 20 . the first inverter iv 20 may inversely buffer a signal on the first node nd 21 to output the inversely buffered signal through a second node nd 22 . the first driving unit 2311 may receive the first foreground drive signal drv 1 & lt ; 1 & gt ; and a first complementary foreground drive signal drvb 1 & lt ; 1 & gt ; to drive the second node nd 22 . the second driving unit 2312 may receive the second foreground drive signal drv 1 & lt ; 2 & gt ; and a second complementary foreground drive signal drvb 1 & lt ; 2 & gt ; to drive the second node nd 22 . the third driving unit 2313 may receive the third foreground drive signal drv 1 & lt ; 3 & gt ; and a third complementary foreground drive signal drvb 1 & lt ; 3 & gt ; to drive the second node nd 22 . the fourth driving unit 2314 may receive the fourth foreground drive signal drv 1 & lt ; 4 & gt ; and a fourth complementary foreground drive signal drvb 1 & lt ; 4 & gt ; to drive the second node nd 22 . that is , the first pre - driver 231 may generate the first to fourth pre - foreground data pre_dq 1 & lt ; 1 : 4 & gt ; whose drivabilities are controlled according to a level combination of the first to fourth foreground drive signals drv 1 & lt ; 1 : 4 & gt ;. the first to fourth complementary foreground drive signals drvb 1 & lt ; 1 : 4 & gt ; may correspond to inverted signals of the first to fourth foreground drive signals drv 1 & lt ; 1 : 4 & gt ;, respectively . referring to fig7 , the second pre - driver 251 may be configured to include a second buffering unit 2510 , a second inverter iv 21 , a fifth driving unit 2511 , a sixth driving unit 2512 , a seventh driving unit 2513 and a eighth driving unit 2514 . the second buffering unit 2510 may be configured to buffer signals loaded on the first to fourth background i / o lines gio 2 & lt ; 1 : 4 & gt ; in response to the read enable signal endq enabled to have a logic “ high ” level when the first command signal mrr is inputted , thereby outputting the buffered signals through a third node nd 23 . for example , the second buffering unit 2510 may include nand gate nd 21 . the second inverter iv 21 may inversely buffer a signal on the third node nd 23 to output the inversely buffered signal through a fourth node nd 24 . the fifth driving unit 2511 may receive the first background drive signal drv 2 & lt ; 1 & gt ; and a first complementary background drive signal drvb 2 & lt ; 1 & gt ; to drive the fourth node nd 24 . the sixth driving unit 2512 may receive the second background drive signal drv 2 & lt ; 2 & gt ; and a second complementary background drive signal drvb 2 & lt ; 2 & gt ; to drive the second node nd 22 . the seventh driving unit 2513 may receive the third background drive signal drv 2 & lt ; 3 & gt ; and a third complementary background drive signal drvb 2 & lt ; 3 & gt ; to drive the second node nd 22 . the eighth driving unit 2514 may receive the fourth background drive signal drv 2 & lt ; 4 & gt ; and a fourth complementary background drive signal drvb 2 & lt ; 4 & gt ; to drive the second node nd 22 . that is , the second pre - driver 251 may generate the first to fourth pre - background data pre_dq 2 & lt ; 1 : 4 & gt ; whose drivabilities are controlled according to a level combination of the first to fourth background drive signals drv 2 & lt ; 1 : 4 & gt ;. the first to fourth complementary background drive signals drvb 2 & lt ; 1 : 4 & gt ; may correspond to inverted signals of the first to fourth background drive signals drv 2 & lt ; 1 : 4 & gt ;, respectively . operations of the semiconductor system as set forth above will be described hereinafter with reference to fig2 to 7 in conjunction with an example that drivabilities of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; are controlled when delay times of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; are greater than a normal delay time . the following description will be developed in conjunction with an example that the first to fourth pattern data pd & lt ; 1 : 4 & gt ; are set to have a level combination of ‘ l , h , l , h ’ and the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; are set to have a level combination of ‘ l , l , l , h ’. the command generator 11 of the controller 1 may generate a pulse of a first command signal mrr in response to a test enable signal tmen enabled when a test mode starts . the selection signal generator 12 may generate a selection signal sel having a first level ( e . g ., a logic “ low ” level ) if a pulse of a read latency signal rdout is inputted after a predetermined time elapses from a time that the pulse of the first command signal mrr is generated . in the semiconductor memory device 2 , the input buffer 211 of the drive signal generator 21 may buffer the pulse of the first command signal mrr to generate a first internal command signal ird . the signal storage unit 212 may receive the first internal command signal ird provided from the input buffer 211 to output first to fourth pattern data pd & lt ; 1 : 4 & gt ; having a level combination of ‘ l , h , l , h ’. the data i / o controller 213 may receive the first internal command signal ird provided from the input buffer 211 , to load the first to fourth pattern data pd & lt ; 1 : 4 & gt ; having the level combination of ‘ l , h , l , h ’ on the first to fourth foreground i / o lines gio 1 & lt ; 1 : 4 & gt ;. the first output buffer 23 may buffer signals loaded on the first to fourth foreground i / o lines gio 1 & lt ; 1 : 4 & gt ; to generate first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ;. in such a case , because the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; have a level combination of ‘ l , l , l , h ’, the first to fourth foreground drive signals drv 1 & lt ; 1 : 4 & gt ; may also have a level combination of ‘ l , l , l , h ’. that is , only the first foreground drive signal drv 1 & lt ; 1 & gt ; among the first to fourth foreground drive signals drv 1 & lt ; 1 : 4 & gt ; may have a logic “ high ” level . thus , only the first driving unit 2311 among the first to fourth driving units 2311 , 2312 , 2313 and 2314 constituting the first pre - driver 231 may operate to drive the second node nd 22 . the multiplexer 131 of the comparison signal generator 13 may receive the selection signal sel having the first level ( e . g ., a logic “ low ” level ) to output the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; as first to fourth selection data sd & lt ; 1 : 4 & gt ;. the comparison code generator 132 may generate first and second comparison codes s & lt ; 1 : 2 & gt ; whose level combination is determined according to a level combination of the first to fourth selection data sd & lt ; 1 : 4 & gt ;. for example , if the delay times of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; are greater than a normal delay time , levels of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; may change at a rising edge and a falling edge of a clock signal . thus , the comparison code generator 132 does not generate the first and second comparison codes s & lt ; 1 : 2 & gt ; having a level combination of ‘ h , l ’. the comparator 133 may compare the first and second comparison codes s & lt ; 1 : 2 & gt ; with first and second test codes t & lt ; 1 : 2 & gt ; having a level combination of ‘ h , l ’ to generate a pulse of a comparison signal comp . that is , since the first and second comparison codes s & lt ; 1 : 2 & gt ; does not have the level combination of ‘ h , l ’, the first and second comparison codes s & lt ; 1 : 2 & gt ; are not identified to the first and second test codes t & lt ; 1 : 2 & gt ; so that the comparator 133 may generate the comparison signal comp . the level combination ‘ h , l ’ of the first and second test codes t & lt ; 1 : 2 & gt ; means that the first test code t & lt ; 1 & gt ; has a logic “ low ” level and the second test code t & lt ; 2 & gt ; has a logic “ high ” level . in addition , because the number of bits having a logic “ high ” level among the bits of the first to fourth pattern data pd & lt ; 1 : 4 & gt ; is two , the first and second test codes t & lt ; 1 : 2 & gt ; may be set to have a level combination of ‘ h , l ’. the counter 141 of the control signal generator 14 may count first and second count signals cnt & lt ; 1 : 2 & gt ; in response to a pulse of the comparison signal comp to generate the first and second count signals cnt & lt ; 1 : 2 & gt ; having a level combination of ‘ l , h ’. the level combination ‘ l , h ’ of the first and second count signals cnt & lt ; 1 : 2 & gt ; means that the first count signal cnt & lt ; 1 & gt ; has a logic “ high ” level and the second count signal cnt & lt ; 2 & gt ; has a logic “ low ” level . the decoder 142 may decode the first and second count signals cnt & lt ; 1 : 2 & gt ; in response to the selection signal sel . since the selection signal sel has the first level ( e . g ., a logic “ low ” level ), the decoder 142 may output the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; having a level combination of ‘ l , l , h , h ’, as an output signals thereof . the command generator 11 may receive the pulse of a comparison signal comp provided from the comparator 133 to generate a pulse of the first command signal mrr . the selection signal generator 12 may generate the selection signal sel having the first level ( e . g ., a logic “ low ” level ) in response to the read latency signal rdout enabled after a predetermined time elapses from a of time that the pulse of the first command signal mrr is generated and the comparison signal comp . the input buffer 211 of the semiconductor memory device 2 may buffer the pulse of the first command signal mrr provided from the command generator 11 of the controller 1 to generate the first internal command signal ird . the signal storage unit 212 may receive the first internal command signal ird to output first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; as the first to fourth foreground drive signals drv 1 & lt ; 1 : 4 & gt ; and to output the first to fourth pattern data pd & lt ; 1 : 4 & gt ; having a level combination of ‘ l , h , l , h ’. the data i / o controller 213 may receive the first internal command signal ird to load the first to fourth pattern data pd & lt ; 1 : 4 & gt ; having the level combination of ‘ l , h , l , h ’ on the first to fourth foreground i / o lines gio 1 & lt ; 1 : 4 & gt ;. the first output buffer 23 of the output buffer 22 may buffer signals loaded on the first to fourth foreground i / o lines gio 1 & lt ; 1 : 4 & gt ; in response to the first to fourth foreground drive signals drv 1 & lt ; 1 : 4 & gt ; having a level combination of ‘ l , l , h , h ’ to generate the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; whose drivabilities are increased . in such a case , because the first to fourth foreground drive signals drv 1 & lt ; 1 : 4 & gt ; have a level combination of ‘ l , l , h , h ’, the first and second driving units 2311 and 2312 among the first to fourth driving units 2311 , 2312 , 2313 and 2314 constituting the first pre - driver 231 may operate to increase the drivabilities of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ;. the multiplexer 131 of the comparison signal generator 13 may receive the selection signal sel having the first level ( e . g ., a logic “ low ” level ) to output the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; as the first to fourth selection data sd & lt ; 1 : 4 & gt ;. the comparison code generator 132 may generate the first and second comparison codes s & lt ; 1 : 2 & gt ; whose level combination varies according to a level combination of the first to fourth selection data sd & lt ; 1 : 4 & gt ;. in such a case , because the drivabilities of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; have been increased , level transition periods of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; may become shorter . thus , the rising edge and the falling edge of the clock signal may occurs after the level transition periods of the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ;. as a result , the first and second comparison codes s & lt ; 1 : 2 & gt ; may be generated to have a level combination of ‘ h , l ’. the comparator 133 may compare the first and second comparison codes s & lt ; 1 : 2 & gt ; with first and second test codes t & lt ; 1 : 2 & gt ; having a level combination of ‘ h , l ’ not to generate a pulse of the comparison signal comp . the counter 141 of the control signal generator 14 does not count the first and second count signals cnt & lt ; 1 : 2 & gt ;. the decoder 142 may decode the first and second count signals cnt & lt ; 1 : 2 & gt ; to generate the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; having a level combination of ‘ l , l , h , h ’ because the selection signal sel has the first level ( e . g ., a logic “ low ” level ). the selection signal generator 12 may generate the selection signal sel having a second level ( e . g ., a logic “ high ” level ) because the pulse of the read latency signal rdout is inputted but no pulse of the comparison signal comp is inputted after a predetermined time elapses from a time that the pulse of the first command signal mrr is generated . thus , the command generator 11 may generate a pulse of a second command signal mrw because the selection signal sel having the second level is inputted but no pulse of the comparison signal comp is inputted . the input buffer 211 of the semiconductor memory device 2 may buffer the pulse of the second command signal mrw to generate a second internal command signal iwt . the signal storage unit 212 may receive the second internal command signal iwt to store the first to fourth foreground control signals dc 1 & lt ; 1 : 4 & gt ; therein . after the test mode terminates , the data i / o controller 213 may load first to fourth foreground internal data id 1 & lt ; 1 : 4 & gt ; stored in memory cells on the first to fourth foreground i / o lines gio 1 & lt ; 1 : 4 & gt ;. the first output buffer 23 may output the first to fourth foreground data dq 1 & lt ; 1 : 4 & gt ; whose drivabilities are increased according to a level combination ‘ l , l , h , h ’ of the first to fourth foreground drive signals drv 1 & lt ; 1 : 4 & gt ;. the semiconductor system described above may control drivabilities of i / o lines to change level transition periods of data even though delay times of the data vary according to process / voltage / temperature ( pvt ) conditions . as a result , reliability of the data may be improved . while certain embodiments have been described above , it will be understood to those skilled in the art that the embodiments described are by way of example only . accordingly , the semiconductor integrated circuit described herein should not be limited based on the described embodiments . rather , the semiconductor integrated circuit described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings .