a preferred embodiment of the present invention is now described with reference to the figures where like reference numbers indicate identical or functionally similar elements . also in the figures , the left most digit of each reference number corresponds to the figure in which the reference number is first used . fig1 is an illustration of a computer environment in which a preferred embodiment of the present invention resides . a conventional memory unit 104 and conventional input / output ( i / o ) devices 106 communicate with a data processor 102 . in the preferred embodiment the processor is a hal r1 processor developed by hal computer systems , campbell , calif . the hal r1 processor implements the sparc v9 64 bit instruction set architecture developed by sparc international , inc ., menlo park , calif . the processor 102 includes a superscalar cpu 108 , a memory management unit ( mmu ), and four cache memory units 110 , 112 . the cache memory units 110 , 112 preferably include two 64 kilobyte ( kb ) conventional data caches and two 64 kb conventional instruction caches . the data caches 110 provide data to the superscalar cpu 108 and the mmu 114 . both sets of cache memory units 110 , 112 are virtually indexed and tagged . each cache chip 110 , 112 contains 64 kb of data storage , organized as four sets . each 64 kb cache chip 110 , 112 , can service two independent requests from the superscalar cpu 108 . the interface between the superscalar cpu 108 and the caches 110 , 112 is non - blocking in that the superscalar cpu 108 can access the cache 110 , 112 , at the same time a cache line is being refilled or flushed . additional detail concerning the cache memory units 110 , 112 is set forth in chen , chien , y . lu , a . wond ; the microarchitecture of the hal cache , compcon proceedings 1995 , which is incorporated herein by reference in its entirety . the function of the mmu 114 includes controlling memory management and data coherence , interfacing to memory 104 and i / o devices 106 , and error handling , for the processor 102 . the mmu 114 includes three levels of address spaces : ( 1 ) a virtual address space for the processor 102 , ( 2 ) a logical address space for i / o devices 106 and a diagnostic processor , and ( 3 ) a physical address space for memory 104 . these hierarchical address spaces provide an efficient mechanism for managing the large address space . a more detailed description of the mmu 114 used in the preferred embodiment is described in david chang , d . lyon , c . chen , l . peng , m . massoumi , m . hakimi , s . iyengar , e . li , r . remedios , microarchitecture of hal &# 39 ; s memory management unit , compcon proceedings 1995 , which is incorporated herein by reference in its entirety . fig2 is a more detailed illustration of a superscalar cpu 108 of the preferred embodiment of the present invention . the processor 102 implements a four - stage pipeline for fixed - point instructions and a six - stage pipeline for &# 34 ; load &# 34 ; instructions . the superscalar cpu 108 includes an instruction fetch unit 202 , a programmable instruction trap unit 204 , an instruction issue unit 206 , an instruction execution unit 218 , a precise state unit 220 , a branch history table 208 , a return prediction table 210 , a prefetch buffer 212 , a recoded instruction cache 214 and a branch unit 216 . the fetch unit 202 requests and receives four instructions from either the off - chip 64 kb instruction cache 112 , shown as data lines 201 in fig2 a prefetch buffer 212 , or a recoded instruction cache 214 . four instructions are then sent to a programmable instruction trap unit 204 to determine if any of the instructions should be trapped . the programmable instruction trap unit 204 is described in greater detail below with reference to fig3 - 8 . the branch history table 208 contains a plurality of counters that are used to predict the direction of execution branches . the return prediction table 210 is used to predict the return address of executed instructions . the branch unit 216 uses information from the issue unit 206 , the branch history table 208 , and the return prediction table 210 , to determine if a control transfer instruction is within the current issue window , and further modifies the program counter if the control transfer instruction is taken . the issue unit 206 determines the available computer resources and issue constraints , e . g ., should an instruction be synchronized . all instructions are issued by the issue unit 206 in the order they would have issued in a traditional serial processor and are sent to the instruction execution unit 218 . the instruction execution unit 218 executes the instructions , although not necessarily in the order in which they were issued . the instruction execution unit 218 outputs the results of the instruction execution on data bus 222 . a more detailed description of the superscalar cpu 108 of the preferred embodiment is described in niteen patkar , a . katsuno , s . li , t . maruyama , s . savkar , m . simone , g . shen , r . swami , d . tovey , microarchitecture of the hal pm1 cpu , compcon proceedings 1995 . the present invention lies in the programmable instruction trap unit 204 which is herein described . fig3 is a more detailed illustration of a programmable instruction trap unit 204 according to the preferred embodiment of the present invention . the programmable instruction trap unit 204 preferably receives four instructions from the fetch unit 202 . the instructions are shown on fig3 as inst00 , inst01 , inst10 , inst11 . each instruction is sent to an instruction trap logic unit ( itlu ) 302 . the instruction trap logic unit also receives signals from preferably four instruction trap register &# 39 ; s ( itrv ) 304 , four instruction trap register masks ( itrm ) 306 , and four control registers ( cr ) 308 . a more detailed description of the instruction trap logic unit 302 , itrm 304 , itrm 306 and cr 308 are set forth below with respect to fig4 - 8 . fig4 is a more detailed illustration of a programmable instruction trap unit according to the preferred embodiment of the present invention . the instruction trap logic unit 302 preferably includes four exclusive nor logic devices 404a - d , where one exclusive nor is associated with each itrv 304 . each exclusive nor device 404 compares each inverted bit of the instruction with a corresponding bit from the associated itrv , e . g ., itrv0 410 , and for each bit the nor device 404 outputs a value indicating whether a match has occurred . it is envisioned that other techniques can be used to compare each bit of the instruction , inst00 , with each bit in an itrv 304 . the method for performing this comparison is described in greater detail below with respect to fig7 - 8 . the instruction trap logic unit 302 preferably includes four devices 406a - d that compare each bit output by an associated exclusive nor device 404 with a bit value in an itrm 306 . each itrm 306 contains a plurality of bits containing a &# 34 ; care &# 34 ; or &# 34 ; don &# 39 ; t care &# 34 ; value . each of the four devices 406a - d compares a bit that is output by its associated exclusive nor device and a bit in its associated itrm 306 . each device 406 outputs a one bit value representing whether all of the instruction bits match the associated itrv - itrm register pair . preferably , each device 406 is an ao32 × 2 device . this device has two sets of 32 bit inputs , one set coupled to each bit line of the associated exclusive nor 404 output , the other set coupled to the associated itrm 306 . the ao32 × 2 includes 32 logical and gates whose outputs are input into a logical or gate . the method for performing this comparison is described in greater detail below with respect to fig7 - 8 . the cr &# 39 ; s 308 are associated with a single itrv - itrm pair . for example , cr0 is associated with itrv0 and itrm0 . each cr contains data representing the action that is to be taken if the instruction matches its associated itrv - itrm register pair . although each control register can contain any number of bits , in the preferred embodiment each cr 308 contains two bits . one bit represents a synchronization action , the other bit represents an instruction trap . that is , if the bits in a control register are &# 34 ; 00 &# 34 ; and if the instruction matches the associated itrv - itrm register pair 304 , 306 , then no special action is taken . if the bits in a control register are &# 34 ; 01 &# 34 ; and if the instruction matches the associated itrv - itrm register pair 304 , 306 , then the programmable instruction trap unit 204 will output a signal that causes the matched instruction to execute synchronously , i . e ., all instructions that are issued before the matched instruction will have completed execution and the machine will be in a committed , i . e ., known , state before the matched instruction executes . in addition , a synchronization instruction is issued , executed , completed and committed before any subsequent instructions are issued . if the bits in a control register are &# 34 ; 10 &# 34 ; and if the instruction matches the associated itrv - itrm register pair 304 , 306 , then the programmable instruction trap unit 204 will generate a non - synchronizing instruction issue trap , i . e ., the instruction will take on the semantics of an instruction trap . if the bits in a control register are &# 34 ; 11 &# 34 ; and if the instruction matches the associated itrv - itrm register pair 304 , 306 , then the programmable instruction trap unit 204 will generate a synchronizing instruction issue trap , i . e ., the instruction will be trapped and executed synchronously . the instruction trap logic unit 302 includes a device for generating the values stored in the cr 308 associated with an itrv - itrm register pair 304 , 306 that matches the received instruction , e . g ., inst00 . a variety of techniques can be utilized to generate this value . preferably , two sets of four logical or gates ( one associated with each cr 308 ) receive an input from the cr 308 . each or gate of the first set of or gates receives two inputs : ( 1 ) the first bit of a cr 308 , e . g ., cr0 , and ( 2 ) the one bit output from the ao32 × 2 associated with the cr 308 . similarly , each or gate of the second set of or gates receives two inputs : ( 1 ) the second bit of a cr 308 , e . g ., cr0 , and ( 2 ) the one bit output from the ao32 × 2 associated with the cr 308 . the output of all of the or gates for each set of or gates is supplied to a logical nand gate , 408a - b . the method for generating the outputs of the instruction trap logic unit 302 is described in greater detail below with respect to fig7 - 8 . the values in the itrv &# 39 ; s 304 , the itrm &# 39 ; s 306 , and the cr &# 39 ; s 308 are programmable . these values can be programmed by a user to trap instructions and cause certain instructions to be executed synchronously , as described above . the programmability feature of the present invention provides an efficient technique for trapping and synchronizing instructions in order to correct functional errors in processor instructions and ensure the proper operation of application programs by executing certain instructions synchronously , i . e ., those instructions stored in the itrv 304 , itrm 306 . a variety of techniques can be used to program the itrv &# 39 ; s 304 , the itrm &# 39 ; s 306 , and the cr &# 39 ; s 308 ( collectively called the programmable registers ). for example , the programmable registers can be coupled to a data bus and to control logic that permits the programmable registers to receive data from the data bus . in the preferred embodiment the data is &# 34 ; scanned - in &# 34 ; during the computer boot - up operation . the programmable registers are programmed using a technique similar to shift registers . fig5 is a more detailed illustration of an itrv 304 and itrm 306 according to the preferred embodiment of the present invention . each programmable register 410 contains a plurality of bit registers 502 . preferably , each itrv 304 and each itrm 306 include 27 bit registers 502 while each cr 306 includes 2 bit registers 502 . fig5 is a representative itrv 304 or an itrm 306 . the cr &# 39 ; s 308 operate in the same manner with the exception that each cr 308 preferably includes two bit registers 502 as opposed to 27 bit registers 502 , as discussed above . each programmable register 410 receives a scan clock ( sc ) signal , a scan - enable ( se ) signal , and scan - input ( si ) signal , and generates a scan - output ( so ) signal and a q output signal . fig6 is a more detailed illustration of a bit register 502 according to the preferred embodiment of the present invention . a signal containing a bit value is received on the si line . when the sc and se signals are high , i . e ., the signal represents a binary &# 34 ; 1 &# 34 ; value , the logical and gate 602 generates a high signal . this signal is coupled to the gate of transistor 604 . as a result , transistor 604 conducts thereby enabling the signal on the si line to pass through the transistor 604 and have its logic value be maintained by two inverters 606 . when the sc goes low while the se signal remains high transistor 604 turns off and the logical and gate 608 generates a high signal . the and gate 608 is coupled to the gate of transistor 610 . as a result , transistor 612 conducts and the inverted si signal is again inverted by one of the inverters 610 and is output on the so line . the signal is also output on the q line that is coupled to either device 404a if the bit register is part of an itrv 304 , an inverter and device 406a if the bit register is part of an itrm 306 , or an inverter and an or gate if the bit register is part of a cr 308 . the so line is coupled to the next bit register si line . the so line of the last bit register of itrv 304 is coupled to the first bit register of the first itrm 306 . the last bit register of itrm 306 is coupled to the first bit register of the first cr 308 . during the computer initialization process data representing the programmable register values are systematically input into the first si line 412 and shifted through all of the bit registers until each programmable register contains the desired values , i . e ., the bit register values are scanned - in . the method of the present invention will now be described . fig7 is a flow diagram describing the method of trapping an instruction according to the preferred embodiment of the present invention . initially , the itrv &# 39 ; s 304 , the itrm &# 39 ; s 306 , and the cr &# 39 ; s 308 are programmed . as described above , these programmable registers can be programmed individually 704 , 706 , 708 , using a data bus and control signals . preferably , the programmable registers are programmed during computer initialization using the scan - in , i . e ., bit shifting , technique described above with reference to fig5 - 6 . after the programmable registers are programmed 702 instructions are tested 710 . the method for testing instructions is set forth below with respect to fig8 . fig8 is a flow diagram describing the method of testing an instruction according to the preferred embodiment of the present invention . preferably four instructions are received 802 by the programmable instruction trap unit 204 from the fetch unit 202 , as illustrated in fig2 . each instruction is sent to a separate instruction trap logic unit 302 . for example , instruction inst00 is sent to instruction trap logic unit 302a . the instruction trap logic unit 302a inverts each bit in the instruction using inverter 402 . the inverted instruction bits are received by four exclusive nor device 404a - d , described above with reference to fig4 . each exclusive nor device 404 compares 804 each inverted instruction bit with a corresponding bit in one of the itrv &# 39 ; s 304 that was previously programmed . for example , the exclusive nor device 404a , compares instruction bit 0 with bit register 0 of itrv0 , as illustrated in fig4 - 6 . if the inverted instruction bit matches the associated bit in one of the itrv &# 39 ; s 304 then the exclusive nor generates a signal representing a logical &# 34 ; 1 &# 34 ;. otherwise , the exclusive nor generates a signal representing a logical &# 34 ; 0 &# 34 ;. since the exclusive nor device is comparing the associated itrv bit register 502 and an inverted bit of the instruction , if the exclusive nor generates a signal representing a logical &# 34 ; 0 &# 34 ; then the itrv bit matches the instruction bit . each inverted bit of the instruction , inst00 , is compared to each associated bit of each itrv 304 . preferably , the result of these comparisons is four 27 - bit signals representing the result of the exclusive nor comparison of devices 404a - d . preferably , each bit in each set of 27 - bit signals is compared 806 with a bit register 502 in an associated itrm 306 using an ao32 × 2 device 406a - d . each ao32 × 2 device 406a - d consists of at least 27 logical and gates whose outputs are input into a logical or gate . for example , the least significant bit , or the zero bit , that is output from device 404a is input into an and gate along with the inverted zero bit register of itrm0 . the itrm &# 39 ; s 306 are a mask . sometimes it is desirable to compare each instruction with a set of related instruction patterns . for example , it may be desirable to match all instructions having a certain combination of bits 5 - 9 . in this situation the remaining bits , e . g ., bits 0 - 4 and 10 - 26 , should be masked because their value is irrelevant for this particular match . this matching is accomplished by placing a &# 34 ; don &# 39 ; t care &# 34 ; value in the proper itrm bit register . in the present invention , the &# 34 ; don &# 39 ; t care &# 34 ; value is a logical &# 34 ; 1 &# 34 ;. as illustrated in fig4 the itrm values are inverted before they are received by the ao32 × 2 . accordingly , if a bit from device 404a is either zero , because the instruction bit matched the associated itrv bit register , the output of the associated and gate in the ao32 × 2 406a will be zero . similarly , if a bit from device 404a is a logical one , then the output of the and will be zero only if the associated bit register in itrm0 is masked , i . e ., it &# 39 ; s inverted value is equal to zero . as discussed above , all of the and gate outputs are coupled to an or gate . if any and gate output is a logical one then the output of the or gate is a logical one . the output of the or gate is the output of the ao32 × 2 406 . therefore , the ao32 × 2 406 generates an instruction match value ( imv ) signal that represents a logical zero only if all of the bits from the instruction inst00 either match the associated itrv bits or are masked , i . e ., if the instruction inst00 matches the itrv - itrm 304 , 306 register pair . the programmable instruction trap unit 204 then determines 810 if any matches have occurred and if so it generates 812 the value in the associated cr 308 . the process for achieving this is now described . the output from each ao32 × 2 device 406 is received by two logical or gates , e . g ., or gates 418 , 420 , as illustrated in fig4 . the second input to the first or gate 418 is the value of the first bit register of the associated cr 308 . the second input to the second or gate 420 is the value of the second bit register of the associated cr 308 . for example , if instruction inst00 only matches the register pair itrv0 - itrm0 then ao32 × 2 406a generates a signal representing a logical zero at its output and the remaining ao32 × 2 406b - d generate a signal representing a logical one at its output . the three or gates associated with ao32 × 2 &# 39 ; s 406b - d receive a binary one as one of its inputs . accordingly , these three or gates will output a signal representing a binary one . nand gate 408a will generate a logical zero output only if the output of or gate 418 generates a logical one . since the output of device 406a is a logical zero , the output of or gate 418 is a logical one only if the first bit register of cr0 contains a logical zero . each set of four or gates and one nand gate 408 result in either ( 1 ) the value of the cr 308 associated with a matching register pair to be output by the nand gates 408a - b , or ( 2 ) if the instruction inst00 does not match any register pair , the nand gates 408a - b output a &# 34 ; 00 &# 34 ; value representing that no special action is to be taken , as described above . all four received instructions , i . e ., inst00 , inst01 , inst10 , and inst11 are similarly compared to each of the four itrv registers and the itrm registers . it is possible for more than one register pair to match a single instruction . for example , both the register pair itrv1 - itrm1 and the register pair itrv2 - itrm2 can match a particular instruction , e . g ., inst00 . in such a circumstance a bit value of &# 34 ; 1 &# 34 ; in a cr bit register for one cr , e . g ., cr2 , will result in the associated nand gate generating a signal representing a logical one . after all four instructions are concurrently tested the method continues 814 . if more instructions are received 712 the process repeats . after all instructions have been tested new values for the itrv &# 39 ; s 304 , itrm &# 39 ; s 306 , and cr &# 39 ; s 308 can be programmed 714 in using a data bus or preferably by rebooting the computer and scanning in new programmable register values , as described above , and then the process 702 - 714 repeats . while the invention has been particularly shown and described with reference to a preferred embodiment and several alternate embodiments thereof , it will be understood by persons skilled in the relevant art that various change in form and details can be made therein without departing from the spirit and scope of the invention .