various illustrative embodiments of the invention are described below . in the interest of clarity , not all features of an actual implementation are described in this specification . it will of course be appreciated that in the development of any such actual embodiment , numerous implementation - specific decisions must be made to achieve the developers &# 39 ; specific goals , such as compliance with system - related and business - related constraints , which will vary from one implementation to another . moreover , it will be appreciated that such a development effort might be complex and time - consuming , but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure . the present subject matter will be described with reference to the attached figures . various structures , systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art . nevertheless , the attached drawings are included to describe and explain illustrative examples of the present disclosure . the words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art . no special definition of a term or phrase , i . e ., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art , is intended to be implied by consistent usage of the term or phrase herein . to the extent that a term or phrase is intended to have a special meaning , i . e ., a meaning other than that understood by skilled artisans , such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase . the present disclosure is directed to various methods of controlling the height of various structures used in forming integrated circuit devices or in a semiconducting substrate . as will be readily apparent to those skilled in the art upon a complete reading of the present application , the present method is applicable to a variety of devices , including , but not limited to , asics , logic devices , memory devices , etc . moreover , the present invention may be employed in forming any of a variety of different types of features formed on an integrated circuit product , such as lines , trenches , gate electrode structures , fins for finfet devices , contact structures , back - end - of - line ( beol ) structures , etc . portions of the finfet device structure are formed using well - known techniques and process steps ( e . g ., techniques and steps related to doping , photolithography and patterning , etching , material growth , material deposition , surface planarization and the like ) that will not be described in detail here . moreover , the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein . in particular , various steps in the manufacture of semiconductor - based transistors are well known and so , in the interest of brevity , many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well - known process details . the techniques and technologies described herein may be utilized to fabricate mos transistor devices , including nmos transistor devices , pmos transistor devices and cmos transistor devices . in particular , the process steps described herein can be utilized in conjunction with any semiconductor device fabrication process that forms gate structures for transistors . although the term “ mos device ” properly refers to a device having a metal gate electrode and an oxide gate insulator , that term may be used to refer to any semiconductor device that includes a conductive gate electrode ( whether metal or other conductive material ) that is positioned over a gate insulator ( whether oxide or other insulator ) which , in turn , is positioned over a semiconductor substrate . certain terminology may also be used in the following description for the purpose of reference only , and thus are not intended to be limiting . for example , terms such as “ upper ,” “ lower ,” “ above ” and “ below ” refer to directions in the drawings to which reference is made . terms such as “ front ,” “ back ,” “ rear ,” “ side ,” “ outboard ” and “ inboard ” describe the orientation and / or location of portions of a feature or element within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the item under discussion . such terminology may include the words specifically mentioned above , derivatives thereof , and words of similar import . similarly , the terms “ first ,” “ second ” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context . with reference to the attached drawings , various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail . the figures illustrate versions where height is controlled by local isolation recess and where height is controlled by epitaxial growth height . it also depicts the use of a continuous common channel material and isolated common channel material . the present disclosure is directed to various methods of finfet fabrication , and to finfet devices . as will be readily apparent to those skilled in the art upon a complete reading of the present application , the present method is applicable to a variety of technologies , e . g ., nmos , pmos , cmos , etc ., and is readily applicable to a variety of devices , including , but not limited to , logic devices , memory devices , etc . with reference to fig1 - 54 , various illustrative embodiments of the methods disclosed herein will now be described in more detail . additionally , the term “ substrate ” as used herein is intended to be very broad in nature and cover any type or structure or form of a channel region of a transistor that is commonly in contact with or positioned below a gate insulation layer , such as a layer of silicon / germanium that is commonly found in pmos devices . the term “ substrate ” should also be understood to cover any of a variety of different semiconductor materials , such as silicon , silicon / germanium , gallium arsenide , etc . instead of a silicon substrate , an inp buffer could be used as the substrate . fig1 - 12 show cross - sectional views of a structure 100 going through fabrication steps of an improved finfet fabrication process , in accordance with embodiments of the present invention . more specifically , fig1 , in one embodiment , shows a cross - sectional view of a semiconductor device 100 in an early manufacturing stage . with reference to fig1 , the improved finfet process may start out with providing a semiconductor substrate 106 . the substrate 106 may have a variety of configurations , such as the depicted bulk silicon configuration . the substrate may also have a silicon - on - insulator ( soi ) configuration that includes a bulk silicon layer , a buried insulation layer and an active layer , wherein semiconductor devices are formed in and above the active layer . thus , the terms substrate or semiconductor substrate should be understood to cover all forms of semiconductor structures . the substrate may also be made of materials other than silicon . the substrate material 106 is preferably a silicon material as typically used in the semiconductor industry , e . g ., relatively pure silicon , as well as silicon admixed with other elements , such as germanium , carbon and the like . next , with reference to fig2 , a material layer 108 is formed over the top of the substrate 106 . in one embodiment , the material layer 108 is an insulator . the material layer 108 may be oxide , such as sio 2 , and may be formed by plasma enhanced atomic layer deposition ( peald ), low pressure chemical vapor deposition ( lpcvd ), chemical vapor deposition ( cvd ), thermally grown or deposited with other methods . next , with reference to fig3 , patterning of the material layer 108 ( fig2 ) into at least one patterned material structure 110 is performed . the patterning may be performed by etching to define at least one trench 114 and a substrate top surface 112 . in one embodiment , the etching may be performed by plasma - based etching , leaving the at least one patterned material structure 110 , defining a trench width from 5 - 25 nm . next , with reference to fig4 , a common stack material 118 is formed in the at least one trench 114 over the substrate top surface 112 . in one embodiment , the common stack material 118 may be formed by epitaxially growing the common stack material 118 . the common stack material 118 may be si — c , in the case of si or sige channels , or could be inp in the case of group iii - v semiconductor material channels . in one embodiment , the common stack material 118 may be 5 - 20 nm thick . next , with reference to fig5 , a first masking material 120 is formed on a first portion of the common stack material 118 and a first portion of the at least one patterned material structure 110 proximate to the first portion of the common stack 118 . in one embodiment , the first masking material 120 may be deposited . the first masking material 120 may be pfet masking material , such as si 3 n 4 , tin , sio 2 , etc . the first portion of the common stack material 118 and the first portion of the at least one patterned material structure 110 proximate to the first portion of the common stack material may define a cell library . next , with reference to fig6 , a first channel material 122 is formed on a second portion of the common stack material 118 . in one embodiment , the first channel material 122 may be formed by epitaxially growing the first channel material 122 . the first channel material 122 may be nfet channel material , such as si , or group iii - v semiconductor material . in one embodiment , the first channel material 122 may be 20 - 100 nm thick . next , with reference to fig7 , removal of the first masking material 120 is performed . in one embodiment , the removal of the first masking material 120 may be performed by plasma - based processing or “ wet ” chemical methods . next , with reference to fig8 , a second masking material 124 is formed on the first channel material 122 and a second portion of the at least one patterned material structure 110 proximate to the first channel material 122 . in one embodiment , the second masking material 124 may be formed by depositing the second masking material 124 . in one embodiment , the second masking material 124 may be nfet masking material , such as si 3 n 4 , tin , sio 2 , etc . the first channel material 122 and the portion of the at least one patterned material structure 110 proximate to the first channel material 122 may define a cell library . next , with reference to fig9 , a second channel material 126 is formed on the first portion of the common stack material 118 . in one embodiment , the second channel material 126 may be epitaxially grown . the second channel material 126 may be pfet channel material and as such may have a germanium ( ge ) content , ranging from 25 - 100 % and ranging from 20 - 100 nm thick . next , with reference to fig1 , a portion of the unmasked material is removed 136 , thereby producing an asymmetry between the various structure heights . the material removal may be performed by conventional plasma or wet etching methods . next , with reference to fig1 , removal of the second masking material 124 is performed . in one embodiment , the removal of the second masking material 124 may be performed by plasma - based processing or “ wet ” chemical methods . next , with reference to fig1 , recessing the at least one patterned material structure 110 is performed to produce recessed structure 130 , thereby producing an asymmetry between various recessed structure 130 heights 138 , 140 . in one embodiment , the recessing may be performed by conventional plasma or wet etching methods . in one embodiment , the recessed structure 130 may result from having been recessed to a depth range of 5 - 40 nm . fig1 - 24 show cross - sectional views of a structure 200 going through fabrication steps of an improved finfet fabrication process , in accordance with embodiments of the present invention . more specifically , fig1 , in one embodiment , shows a cross - sectional view of a semiconductor device 200 in an early manufacturing stage . with reference to fig1 , the improved finfet process may start out with providing a semiconductor substrate 206 . next , with reference to fig1 , a common stack layer 204 is formed over the substrate 206 . in one embodiment , the common stack layer 204 may be sic in the case of si or sige channels , or could be inp in the case of group iii - v material channels , and may be formed by epitaxial growth or other deposition methods . in one embodiment , the common stack layer 204 may be 5 - 20 nm thick . next , with reference to fig1 , a material layer 208 is formed over the common stack layer 204 . in one embodiment , the material layer 208 may be silicon oxide or silicon nitride and may be formed by various depositing or growth methods . next , with reference to fig1 , patterning of the material layer 208 is performed to produce at least one patterned material structure 210 . the patterning may be performed by etching material layer 208 to define at least one trench 214 and a channel layer top surface 212 . in one embodiment , the etching may be performed by plasma - based processing , leaving the at least one patterned material 210 . next , with reference to fig1 , a first masking material 220 is formed on a first portion of the channel layer 204 and a first portion of the at least one patterned material structure 210 . in one embodiment , forming the first masking material 220 may be by depositing and patterning the first masking material 220 . the first masking material 220 may be pfet masking material , such as si 3 n 4 , tin , sio 2 , etc . next , with reference to fig1 , a first channel material 222 is formed on a second portion of the common stack layer 204 . in one embodiment the first channel material 222 may be formed by epitaxially growing the first channel material 222 . the first channel material 222 may be nfet channel material , such as si , or group iii - v semiconductor material . in one embodiment , the first channel material 222 may be 20 - 100 nm thick . next , with reference to fig1 , removal of the first masking material 220 is performed . in one embodiment , removal of the first masking material 220 may be performed by “ wet ” chemical removal . next , with reference to fig2 , a second masking material 224 is formed on the first channel material 222 and a second portion of the at least one patterned material structure 210 proximate to the first channel material 222 . in one embodiment , the second masking material 224 is formed by depositing the second masking material 224 . in one embodiment , the second masking material 224 may be nfet masking material such as si 3 n 4 , tin , sio 2 , etc . next , with reference to fig2 , a second channel material 226 is formed on the first portion of the common stack layer 204 . in one embodiment , the second channel material 226 may be epitaxially grown . the second channel material 226 may be pfet channel material and as such have a ge content ranging from 25 - 100 %. in one embodiment , the second channel material 226 may be 15 - 35 nm thick . next , with reference to fig2 , a portion of the unmasked material is removed , thereby producing an asymmetry between the various structure heights 236 . the material removal may be performed by conventional plasma or wet etching methods . next , with reference to fig2 , removal of the second masking material 224 is performed . in one embodiment , the removal of the second masking material 224 may be performed by “ wet ” chemical removal . next , with reference to fig2 , recessing of the at least one patterned material structure 210 is performed to produce recessed structure 230 , thereby producing an asymmetry between various recessed structure 230 heights 238 , 240 . in one embodiment , the recessing may be performed by conventional plasma or wet etching methods . in one embodiment , the recessed structure may be produced by recessing the patterned material 210 to a depth range of 5 - 40 nm . fig2 - 32 show cross - sectional views of a structure 300 going through fabrication steps of an improved finfet fabrication process , in accordance with embodiments of the present invention . more specifically , fig2 , in one embodiment , shows a cross - sectional view of a semiconductor device 300 in an early manufacturing stage . with reference to fig2 , the improved finfet process may start out with providing a semiconductor substrate 306 . next , with reference to fig2 , one or more fins 310 are formed in the substrate 306 . the fins 310 may be formed by patterning and etching the substrate 306 . a first masking material 318 is formed and patterned on the substrate 306 and remains on the fins 310 after fin formation . at least one trench 314 is defined when forming the fins 310 . in one embodiment , the first masking material 318 may be si 3 n 4 , sio2 or any dielectric with good etch contrast to the channel material ( si , sige , iii - v , etc .). next , with reference to fig2 , a material layer 320 is formed in the at least one trench 314 . the material layer 320 may be formed above 336 the first masking material 318 and in one embodiment to a height of 0 ( bottom up fill ) to 50 nm . in one embodiment , the material layer 320 may be formed by ald , cvd , spin - on , etc . and may be an insulator , with sio 2 preferred . next , with reference to fig2 , a second masking material 324 is formed on a first portion of the material layer 320 . in one embodiment , the second masking material 324 may be formed by depositing and patterning the second mask material 324 . the second masking material 324 may be tin , sin , photoresist , organic planarizing layer ( opl ), ac , or sio 2 . next , with reference to fig2 , a portion of the material layer 320 that is not covered by the second masking material 324 is removed , thereby producing an asymmetry across the height 338 of the material layer 320 . the material removal may be performed by conventional plasma or wet etching methods . next , with reference to fig3 , removal of the second masking material 324 is performed . in one embodiment , the removal of the second masking material 324 may be performed by conventional plasma or wet etching . next , with reference to fig3 , recessing the material layer 320 is performed to produce recessed structure 330 , thereby producing an asymmetry between various recessed structure 330 heights 340 , 342 . in one embodiment , the recessing may be performed by conventional plasma or wet etching methods . in one embodiment , the recessed structure height may be the result of recessing by 10 - 50 nm . next , with reference to fig3 , removal of the first masking material 318 is performed . in one embodiment , the removal of the first masking material 318 may be performed by conventional plasma or wet etching methods . fig3 - 43 show cross - sectional views of a structure 400 going through fabrication steps of an improved finfet fabrication process , in accordance with embodiments of the present invention . more specifically , fig3 , in one embodiment , shows a cross - sectional view of a semiconductor device 400 in an early manufacturing stage . with reference to fig3 , the improved finfet process may start out with providing a semiconductor substrate 406 . next , with reference to fig3 , a material layer 408 is formed over the substrate 406 . in one embodiment , the material layer 408 may be insulator , such as an oxide , sio 2 , and may be formed by deposition or thermal oxidation methods . next , with reference to fig3 , patterning the material layer 408 into at least one patterned material structure 410 is performed . patterning the material layer 408 may be performed by etching material layer 408 to define at least one trench 414 . in one embodiment , the etching may be performed by plasma - based processing , leaving the at least one patterned material structure 410 . next , with reference to fig3 , a common stack material 418 is formed in the at least one trench 414 . in one embodiment , the common stack material 418 may be sic , uniquely doped si , etc ., and may be formed by deposition techniques or epitaxially grown . in one embodiment , the common stack material 418 may be 5 - 20 nm thick . next , with reference to fig3 , a first masking material 420 is formed on a first portion of the channel material 418 and a first portion of the at least one patterned material structure 410 . in one embodiment , forming the first masking material 420 may include depositing and patterning the first masking material 420 . the first masking material 420 can be a pfet masking material , such as si 3 n 4 , tin , sio 2 , etc . next , with reference to fig3 , a first channel material 422 is formed on a second portion of the common stack material 418 . in one embodiment , the first channel material 422 may be formed by epitaxially growing the first channel material 422 . the first channel material 422 may be an nfet channel material , such as si , uniquely doped si , etc . in one embodiment , the first channel material 422 may be 40 - 60 nm thick . next , with reference to fig3 , removal of the first masking material 420 is performed . in one embodiment , the removal may be performed by “ wet ” chemical removal methods . next , with reference to fig4 , a second masking material 424 is formed on the first channel material 422 and a second portion of the at least one patterned material structure 410 proximate to the first channel material 422 . in one embodiment , forming the second masking material 424 may be performed by depositing and patterning the second masking material 424 . in one embodiment , the second masking material 424 may be nfet masking material such as si 3 n 4 , tin , sio 2 , etc . next , with reference to fig4 , a second channel material 426 is formed on the first portion of the common stack material 418 and the second channel material 426 is formed to a height different than the height of the first channel material 422 . in one embodiment , the second channel material 426 may be epitaxially grown . the second channel material 426 may be a pfet channel material and have a ge content ranging from 25 - 100 %. in one embodiment , the second channel material 426 may be 40 - 60 nm thick . next , with reference to fig4 , removal of the second masking material 424 is performed . in one embodiment , the removal of the second masking material 424 may be performed by “ wet ” chemical etching methods . next , with reference to fig4 , recessing of the at least one patterned material structure 410 is performed to produce recessed structure 430 . in one embodiment , the recessing may be performed by plasma - based processing , sublimation - based methods or “ wet ” chemical etching methods . in one embodiment , the recessed structure 430 may be produced by recessing the at least one patterned material structure 410 to a depth range of 25 - 40 nm . fig4 - 54 show cross - sectional views of a structure 500 going through fabrication steps of an improved finfet fabrication process , in accordance with embodiments of the present invention . more specifically , fig4 , in one embodiment , shows a cross - sectional view of a semiconductor device 500 in an early manufacturing stage . with reference to fig4 , the improved finfet process may start out with providing a semiconductor substrate 506 . next , with reference to fig4 , a common stack layer 504 is formed over the substrate 506 . in one embodiment , the common stack layer 504 may be sic , uniquely doped si , etc ., and may be formed by deposition techniques or epitaxially grown . in one embodiment , the common stack layer 504 may be 5 - 20 nm thick . next , with reference to fig4 , a material layer 508 is formed over the common stack layer 504 . in one embodiment , the material layer 508 may be oxide , nitride , etc ., and may be formed by deposition methods . next , with reference to fig4 , patterning the material layer 508 into at least one patterned material structure 510 is performed . the patterning may be performed by etching material layer 508 to define at least one trench 514 and a channel layer top surface 512 . in one embodiment , the etching may be performed by plasma - based processing , leaving the patterned material 510 . next , with reference to fig4 , a first masking material 520 is formed on a first portion of the common stack layer 504 and a first portion of the at least one patterned material structure 510 proximate the first portion of the common stack layer 504 . in one embodiment , forming of the first masking material 520 may include depositing and patterning the first masking material 520 . the first masking material 520 may be a pfet masking material , for example si 3 n 4 , tin , sio 2 , etc . next , with reference to fig4 , a first channel material 522 is formed on a second portion of the common stack layer 504 . in one embodiment , the first channel material 522 may be formed by epitaxially growing the first channel material 522 . the first channel material 522 may be an nfet channel material , for example si , uniquely doped si , etc . in one embodiment , the first channel material 522 may be 40 - 60 nm thick . next , with reference to fig5 , removal of the first masking material 520 is performed . in one embodiment , removal may be performed by “ wet ” chemical methods . next , with reference to fig5 , a second masking material 524 is formed on the first channel material 522 and a second portion of the at least one patterned material structure 510 proximate to the first channel material 522 . in one embodiment , forming the second masking material 524 may be performed by depositing and patterning the second masking material 524 . in one embodiment , the masking material 524 may be an nfet masking material , such as si 3 n 4 , tin , sio 2 , etc . next , with reference to fig5 , a second channel material 526 is formed on the first portion of the common stack layer 504 . the second channel material 526 is formed to a height different from that of the first channel material 522 . in one embodiment , forming the second channel material 526 may be performed by epitaxially growing the second channel material 526 . the second channel material 526 may be a pfet channel material and , for example , have a ge content in the range of 25 - 100 %. in one embodiment , the second channel material 526 may be 40 - 60 nm thick . next , with reference to fig5 , removal of the second masking material 524 is performed . in one embodiment , removal of the second masking material 524 may be performed by “ wet ” chemical etching methods . next , with reference to fig5 , recessing the at least one patterned material structure 510 is performed to produce recessed structure 530 , thereby producing an asymmetry between various recessed structure 526 and 522 heights 540 . in one embodiment , the recessing may be performed by conventional plasma or wet etching methods . in one embodiment , recessed structure 530 may be produced by recessing the patterned material 510 to a depth range of 25 - 40 nm . the particular embodiments disclosed above are illustrative only , as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein . for example , the process steps set forth above may be performed in a different order . furthermore , no limitations are intended to the details of construction or design herein shown , other than as described in the claims below . it is , therefore , evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention . while at least one exemplary embodiment has been presented in the foregoing detailed description , it should be appreciated that a vast number of variations exist . it should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope , applicability or configuration of the claimed subject matter in any way . rather , the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments . it should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims , which includes known equivalents and foreseeable equivalents at the time of filing this patent application . accordingly , the protection sought herein is as set forth in the claims below .