please refer to fig2 a , which is a schematic diagram of a source driving circuit 20 . the source driving circuit 20 includes a gamma circuit 200 , a digital - to - analog converter 210 and an interpolation circuit 220 . the gamma circuit 200 is utilized for providing m + 1 reference voltages vr 0 , vr 1 , . . . , vrm between a high voltage vdd and a low voltage vss , e . g . 5v = vdd & gt ;= vr 0 & gt ; vr 1 & gt ; . . . & gt ; vrm & gt ;= vss = 0v , which are candidates for a source driving voltage . based upon chromatic needs , the reference voltages vr 0 , vr 1 , . . . , vrm are arranged to depict a non - linear curve , as illustrated in fig2 b . according to an alternative embodiment , the reference voltages vr 0 , vr 1 . . . vrm could be negative , i . e . 0v = vss & gt ;= vrm & gt ; . . . & gt ; vr 1 & gt ; vr 0 & gt ;= vcl =− 5v , where vcl denotes another low voltage , as illustrated in fig2 c . in such an arrangement , the reference voltages vr 0 , vr 1 , . . . , vrm depict another non - linear curve shown in fig2 d . the gamma circuit 200 could be implemented by resistors connected in series . the digital - to - analog converter 210 is utilized for selecting two reference voltages from the reference voltages vr 0 , vr 1 , . . . , vrm according to an n - bit digital signal dig 1 to be a first analog signal vh and a second analog signal vl . the interpolation circuit 220 is utilized for providing an interpolation voltage of the first analog signal vh and the second analog signal vl according to a 2 - bit second digital signal dig 2 to be a source driving signal sr . note that , the first analog signal vh and the second analog signal vl are two adjacent reference voltages . for example , if the source driving circuit 20 can provide 2 8 candidate voltages to be the source driving signal sr , the digital - to analog converter 210 would be a 6 - bit digital - to - analog converter 310 as illustrated in fig3 a and fig3 b . in fig3 a and fig3 b , there are 65 reference voltages ( m = 64 ), and the digital signal dig 1 includes six bits d 0 , d 1 , d 2 , d 3 , d 4 , d 5 . the digital - to - analog converter 310 selects two adjacent reference voltages from the reference voltage vr 0 , vr 1 , . . . , vr 64 according to the bits d 0 , d 1 , d 2 , d 3 , d 4 , d 5 to be the first analog signal vh and the second analog signal vl . further , the interpolation circuit 220 inserts four voltages between the first analog signal vh and the second analog signal vl and selects one from the four voltages according to the 2 - bit second digital signal dig 2 to be the source driving signal sr . as a result , the source driving circuit 20 can generates 2 6 * 2 2 = 2 8 possible voltage levels for the source driving signal sr . note that , the digital - to - analog converter 310 requires 126 switches . if each of the 126 switches is implemented by two transistors , 252 transistors are totally required . therefore , the present invention further provides another digital - to - analog converter , which requires fewer transistors than the digital - to - analog converter 310 . please refer to fig4 a and fig4 b , which is a schematic diagram of an n - bit ( n = 6 ) digital - to - analog converter 410 according to an embodiment of the present invention . the digital - to - analog converter 410 is utilized for converting a digital signal dig 1 into a first analog signal vh and a second analog signal vl . the digital signal dig 1 includes n bits d 0 , d 1 . . . dn − 1 , where n denotes a positive integer . the digital - to - analog converter 410 includes multiple first input ends 412 , multiple second input ends 414 , multiple first switches 416 and at least n second switches 418 . the first input ends 412 are respectively utilized for receiving the bits dn - 1 , dn - 2 . . . d 1 , d 0 ( contrary to the receiving order of the digital - to - analog converter 310 ). the second input ends 414 are respectively utilized for receiving multiple reference voltages vr 0 − vr 2 n arranged in a best order shown in fig4 a and fig4 b . in order to narrate the present invention more easily , the reference voltages vr 0 − vr 2 n ordered by magnitude ( vr 0 & gt ; vr 1 & gt ; . . . & gt ; vr 2 n ) determines an original order ( vr 0 → vr 1 → . . . → vr 2 n ), and the original order is performed with ( n − 1 ) reorder processes to determine the best order ( vr 0 → vr 32 → vr 16 → . . . → vr 2 n ). the first switches 416 are electrically coupled to each other in a tree structure , and include n stages , each for selecting one of the reference voltages vr 0 − vr 2 n according to one of the n bits to generate a first selection result . each of the second switches 418 _ 1 - 418 _ 6 is utilized for selecting a second selection result of a previous second switch ( 418 _ 1 - 418 _ 5 ) of the second switch or the first selection result of the corresponding first switch according to one of the n bits dn − 1 , d 1 , d 0 , to generate the second selection result . for n & gt ;= 2 , the nth second switch 418 _n is utilized for receiving the first selection result generated by the second first switch of the ( n − 1 ) th stage . finally , through the switching operations of n stages , the first selection result generated by the first switch 416 of the nth stage is the first analog signal vh , and the second selection result generated by the last second switch 418 _ 6 is the second analog signal vl . note that , the n stages of the first switches 416 correspond to the n bits d 0 , d 1 , . . . , dn − 1 according to a reverse order , which means that the first switches 416 of the first stage are controlled by the bit dn − 1 , the first switches 416 of the second stage are controlled by the bit and the first switch 416 of the nth stage is controlled by the bit d 0 . similarly , similarly , the second switches 418 also correspond to the n bits d 0 , d 1 , . . . , dn − 1 according to the reverse order , which means that the first second switch 418 _ 1 is controlled by the bit dn − 1 , the second second switch 418 _ 2 is controlled by the bit dn - 2 , . . . , and the nth second switch 418 _n is controlled by the bit d 0 . in comparison with the digital - to - analog converter 310 requiring 252 transistors , the digital - to - analog converter 410 of fig4 a and fig4 b merely requires 138 transistors , but can generate the same first analog signal vh and the second analog signal vl . therefore , the digital - to - analog converter 410 requires less circuit layout area and causes less parasitic capacitance than the digital - to - analog converter 310 . in other words , the digital - to - analog converter 410 arranges the input order of the reference voltages vr 0 − vr 2 n , such that the second switches 418 can use a part of the first selection result of the first switches 416 , so as to reduce the number of the second switches 418 . how the reference voltages vr 0 − vr 2 n are reordered is illustrated in fig5 , in which the reference voltages vr 0 − vr 15 are reordered for example . in the embodiment of fig5 , n = 4 , and the reference voltages vr 0 − vr 15 are performed with n − 1 = 3 reorder processes . during the first reorder process , odd components { vr 0 , vr 2 , vr 4 . . . vr 14 } of an original sequence seq 0 ={ vr 0 − vr 15 } are acquired to form a first half part of a new first sequence , and even components { vr 1 , vr 3 , vr 5 . . . vr 15 } of the original sequence seq 0 are acquired to form a second half part of the first sequence , i . e . seq 1 ={ vr 0 , vr 2 , vr 4 , vr 6 , vr 8 , vr 10 , vr 12 , vr 14 , vr 1 , vr 3 , vr 5 , vr 7 , vr 9 , vr 11 , vr 13 , vr 15 }. during the second reorder process : ( 1 ) the first sequence is divided into two sub - sequences seq 11 ={ vr 0 , vr 2 , vr 4 , vr 6 , vr 8 , vr 10 , vr 12 , vr 14 } and seq 12 ={ vr 1 , vr 3 , vr 5 , vr 7 , vr 9 , vr 11 , vr 13 , vr 15 }; ( 2 ) odd components { vr 0 , vr 4 , vr 8 , vr 12 } of the first sub - sequence seq 11 of the sub - sequences seq 11 , seq 12 are acquired to form a 1 / 2 2 part of a second sequence seq 2 ; ( 3 ) even components { vr 2 , vr 6 , vr 10 , vr 14 } of the first sub - sequence seq 11 of the sub - sequences seq 11 , seq 12 are acquired to form a 2 / 2 2 part of the second sequence seq 2 ; ( 4 ) odd components { vr 1 , vr 5 , vr 9 , vr 13 } of the second sub - sequence seq 12 of the sub - sequences seq 11 , seq 12 are acquired to form a 3 / 2 2 part of the second sequence seq 2 ; and ( 5 ) even components { vr 3 , vr 7 , vr 11 , vr 15 } of the second sub - sequence seq 12 of the sub - sequences seq 11 , seq 12 are acquired to form a 4 / 2 2 part of the second sequence seq 2 . therefore , the whole second sequence seq 2 is { vr 0 , vr 4 , vr 8 , vr 12 , vr 2 , vr 6 , vr 10 , vr 14 , vr 1 , vr 5 , vr 9 , vr 13 , vr 3 , vr 7 , vr 11 , vr 15 }. similarly , during the third reorder process : ( 1 ) the second sequence is divided into 2 2 sub - sequences seq 21 ={ vr 0 , vr 4 , vr 8 , vr 12 }, seq 22 ={ vr 2 , vr 6 , vr 10 , vr 14 }, seq 23 ={ vr 1 , vr 5 , vr 9 , vr 13 } and seq 24 ={ vr 3 , vr 7 , vr 11 , vr 15 }; ( 2 ) odd components of the sub - sequences seq 21 , seq 22 , seq 23 , seq 24 are respectively acquired to form 1 / 2 3 , 3 / 2 3 , 5 / 2 3 , 7 / 2 3 parts of a third sequence seq 3 ; and ( 3 ) even components of the sub - sequences seq 21 , seq 22 , seq 23 , seq 24 are respectively acquired to form 2 / 2 3 , 4 / 2 3 , 6 / 2 3 , 8 / 2 3 parts of the third sequence seq 3 . as a result , the whole third sequence seq 3 is { vr 0 , vr 8 , vr 4 , vr 12 , vr 2 , vr 10 , vr 6 , vr 14 , vr 1 , vr 9 , vr 5 , vr 13 , vr 3 , vr 11 , vr 7 , vr 15 }. the above first to third reorder processes can be summarized into a general rule , so as to derive the ( n − 1 ) th reorder process , which includes the following steps : ( 1 ) dividing an ( n − 2 ) th sequence into 2 n − 2 sub - sequences seq ( n − 2 ) 1 − seq ( n − 2 ) 2 n − 2 ; ( 2 ) acquiring odd components of k ( k = 1 − 2 n − 2 ) sub - sequences seq ( n − 2 ) 1 − seq ( n − 2 ) 2 n − 2 to form a ( 2k − 1 )/ 2 n − 1 part of an ( n − 1 ) th sequence ; and ( 3 ) acquiring even components of k ( k = 1 − 2 n − 2 ) sub - sequences seq ( n − 2 ) 1 − seq ( n − 2 ) 2 n − 2 to form a 2k / 2 n − 1 part of the ( n − 1 ) th sequence . for example , the order of the reference voltages of fig4 a and fig4 b is the result of n - 1 = 5 reorder processes . details of the five reorder processes can be acquired by setting k = n − 1 = 1 , 2 , 3 , 4 or 5 in the above steps . note that , the digital signal dig 1 has to be received according to the reverse order in the digital - to - analog converter 410 , such that the first analog signal vh and the second analog signal vl of the digital - to - analog converter 410 can be the same as the first analog signal vh and the second analog signal vl of the digital - to - analog converter 310 . particularly , the reverse order is defined herein to be a reversed bit order of the digital signal dig 1 . for example , according to the embodiment of fig4 a and fig4 b , the original bit order is { d 0 , d 1 , d 2 , d 3 , d 4 , d 5 }, and the reverse order is { d 5 , d 4 , d 3 , d 2 , d 1 , d 0 }. in addition , a special case is that there is no previous second switch for the first second switch 418 _ 1 according to fig4 a and fig4 b . in such a case , the first second switch 418 _ 1 selects the ( 2 ( n − 1 ) + 1 = 33 ) th reference voltage vr 32 numbered by the original order or the ( 2 n + 1 = 65 ) th reference voltage vr 64 numbered by the original order according to the ( n = 6 ) th bit d 5 . according to an embodiment , the first switches 416 and the second switches 418 could be implemented by transistor switches . notably , although n − 1 = 5 reorder processes are performed according to the embodiment of fig4 a and fig4 b , a second best order can be formed for the reference voltages vr 0 , vr 1 . . . vrm if only n − 2 reorder processes are performed . for example , if n = 3 , and the reference voltages vr 0 − vr 8 are received according to the original order , a 3 - bit digital - to - analog converter 610 requires 28 transistors , as illustrated in fig6 a . if the reference voltages vr 0 − vr 8 are performed with n − 2 = 1 reorder process , and are received according to the second best order , a 3 - bit digital - to - analog converter 620 requires 22 transistors , as illustrated in fig6 b . if the reference voltages vr 0 − vr 8 are performed with n − 1 = 2 reorder processes , and are received according to the best order , a 3 - bit digital - to - analog converter 630 requires 20 transistors , as illustrated in fig6 c . therefore , receiving the reference voltages according to the second best order also can reduce the required transistors . according to fig6 b and fig6 c , the circuits of the best order and the second best order differ in receiving orders for the bits d 0 - d 2 and the reference voltages vr 0 − vr 8 , and differ in connections of the second switches 628 , 638 . specifically , first input ends 622 receive the bits d 0 - d 2 according to a semi - reverse order ( d 1 → d 2 → d 0 ), second input ends 624 receive the reference voltages vr 0 − vr 7 according to the second best order ( vr 0 → vr 2 → vr 4 → vr 6 → vr 1 → vr 3 → vr 5 → vr 7 ), and the second switches 628 _ 1 - 628 _ 3 of the first and second stages are specially connected . other than the different parts , the remaining part of the second best order circuit is identical to the best order circuit , which can be referred to the digital - to analog converter 410 in the above and is not further narrated herein . as mentioned before , the second best order is the result of performing n − 2 reorder processes on the original order , and the n − 2 reorder processes are identical to those for acquiring the best order . for example , the ( n − 2 ) th reorder process includes the following steps : ( 1 ) dividing the ( n − 3 ) th sequence into 2 n − 3 sub - sequences seq ( n − 3 ) 1 − seq ( n − 3 ) 2 n − 3 ; ( 2 ) acquiring odd components of k ( k = 1 − 2 n − 3 ) sub - sequences seq ( n − 3 ) 1 − seq ( n − 3 ) 2 n − 3 to form a ( 2k − 1 )/ 2 n − 2 part of a ( n − 2 ) th sequence ; and ( 3 ) acquiring even components of k ( k = 1 − 2 n − 3 ) sub - sequences seq ( n − 3 ) 1 − seq ( n − 3 ) 2 n − 3 to form a 2k / 2 n − 2 part of the ( n − 2 ) th sequence . ( 1 ) reversing a bit order of the digital signal dig 1 to be the semi - reverse order , i . e . d 0 → d 1 → d 2 ; ( 2 ) determining a second highest bit d 1 of the bit order to be a lowest bit of the semi - reverse order ; and ( 3 ) determining a highest bit d 2 of the bit order to be a second lowest bit of the semi - reverse order . for example , the semi - reverse order is d 1 → d 2 → d 0 in the embodiment of fig6 b . finally , the first second switch 628 _ 1 selects the ( 2 ( n − 1 ) − 1 = 3 ) th reference voltage vr 2 numbered by the original order or the ( 2 ( n − 1 ) + 1 = 5 ) th reference voltage vr 4 numbered by the original order according to the ( n = 3 ) th bit d 2 . the second second switch 628 _ 2 selects the ( 2 n − 1 = 7 ) th reference voltage vr 6 numbered by the original order or the ( 2 n + 1 = 9 ) th reference voltage vr 8 numbered by the original order according to the ( n = 3 ) th bit d 2 . the third second switch 628 _ 3 selects the second selection result of the first second switch 628 _ 1 or the second selection result of the second second switch 628 _ 2 according to the ( n − 1 = 2 ) th bit d 1 . therefore , regardless of the digital - to analog converters 410 , 630 applying the best order or the digital - to analog converter 620 applying the second best order , node voltages within the generation process of the first analog signal vh are further utilized for generating the second analog signal vl since the first analog signal vh and the second analog signal vl are two adjacent reference voltages , so as to reduce employed transistors . to sum up , the present invention shares switches based on the relation between the output analog signals to employ fewer transistors for the digital - to - analog converter , so as to minimize circuit layout area and parasitic resistance . those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention . accordingly , the above disclosure should be construed as limited only by the metes and bounds of the appended claims .