fig1 illustrates the top view of a wafer probe card 10 having a series of pins 12 extending from two sides of the wafer probe card 10 . in order to test a particular die 14 on a wafer , this wafer probe card 10 is placed over the die 14 . the die 14 includes a plurality of contact pads 16 . for purposes of this application , a contact pad is defined to include any conductive surface configured to permit temporary or permanent electrical communication with a circuit or node . during testing , the pins 12 of the wafer probe card 10 are in communication with nearby contact pads 16 . given the configuration of the wafer probe card 10 , however , the pins 12 may not be able to reach contact pads 16 on certain areas of the die 14 . fig2 demonstrates the solution in the prior art for this problem . if the contact pad 16 for a logic circuit 18 cannot be accessed by the wafer probe card 10 , then a redundant contact pad 20 is provided in a more accessible location and coupled to the logic circuit 18 . after testing , the original contact pad 16 is once again used to access the logic circuit 18 . the redundant contact pad 20 , however , also remains coupled to the logic circuit 18 and , as described above , may adversely affect the performance of the logic circuit in particular and the entire die in general . fig3 illustrates one embodiment of the current invention that solves the problem remaining in the prior art solution . an isolation circuit 22 is electrically interposed between the redundant contact pad 20 and the logic circuit 18 in order to regulate electrical communication therebetween . the isolation circuit 22 in this embodiment comprises a p - channel long l device 24 having a source coupled to a potential node 26 . the potential node 26 is configured to accept a voltage source . the p - channel long l device 24 also has a drain coupled to a signal node 28 . the gate of the long l device 24 is bled to ground , thereby allowing signal node 28 to constantly receive a voltage signal from the potential node 26 . the signal node 28 carries the voltage signal through a pathway leading to ground , but that pathway is interrupted by a fuse 30 . moreover , the signal node 28 is coupled to a first inverter 32 . the output of the first inverter 32 connects to the gate of an n - channel transistor q 1 , which is a component of a multiplexer 80 electrically interposed between the redundant contact pad 20 and the logic circuit 18 . in addition , the output of the first inverter 32 serves as the input for a second inverter 34 . this second inverter 34 connects to the gate of a p - channel transistor q 2 , which is another component of the multiplexer 80 . in operation , the potential node 26 , the p - channel long l device 24 , the signal node 28 , and the fuse 30 cooperate to determine the drive state of the multiplexer 80 . the fuse 30 is initially intact and provides grounding communication for the signal node 28 . because the signal node 28 is grounded , a low voltage signal , or “ logic 0 ,” is generated and carried to the first inverter 32 . accordingly , the first inverter outputs a high voltage signal , or “ logic 1 .” the high signal drives the n - channel transistor q 1 . the high signal also serves as input to the second inverter 34 , and the resulting low signal drives the p - channel transistor q 2 . with transistors q 1 and q 2 on , a range of signals may be transmitted between the redundant contact pad 20 and the logic circuit 18 . the redundant contact pad 20 can then be isolated by programming or “ blowing ” the fuse 30 . with fuse 30 blown , the signal node 28 no longer has a direct path to ground . as a result , a high signal is sent in a new direction — to the first inverter 32 . the resulting low signal turns off the n - channel transistor q 1 . further , the low signal is changed by the second inverter 34 to a high signal that turns off the p - channel transistor q 2 . with both transistors q 1 and q 2 off , electrical communication between the redundant contact pad 20 and the logic circuit 18 is prevented . moreover , the potential node 26 / signal node 28 / fuse 30 configuration , hereinafter referred to as a “ program circuit ,” is not limited to driving only one multiplexer . as seen in fig4 , first inverter 32 and second inverter 34 can also be coupled to transistors q 1 ′ and q 2 ′ of a second multiplexer 80 ′, wherein the second multiplexer 80 ′ is electrically interposed between another logic circuit 18 ′ and another redundant contact pad 20 ′. as a result , this embodiment provides for the electrical isolation of two redundant contact pads by blowing only one fuse . contact pads 16 and 16 ′ maintain electrical communication with their respective logic circuits 18 and 18 ′. it follows that additional logic circuits could be similarly accommodated . in yet another embodiment illustrated in fig5 , a multiplexer 81 is electrically interposed between contact pad 16 and the logic circuit 18 . as with multiplexer 80 , multiplexer 81 is comprises a p - channel transistor q 3 and an n - channel transistor q 4 . however , whereas the first inverter 32 is coupled to the n - channel transistor q 1 of multiplexer 80 , the first inverter 32 is instead coupled to the p - channel transistor q 3 of multiplexer 81 . similarly , the second inverter 34 connects to the p - channel transistor q 2 in multiplexer 80 but drives the n - channel transistor q 4 in multiplexer 81 . by switching the driving signals in this fashion , the initial signals that serve to turn on multiplexer 80 also turn off multiplexer 81 . conversely , blowing the fuse , which turns off multiplexer 80 , serves to turn on multiplexer 81 . further , the embodiments depicted in fig4 and 5 could be combined so that blowing one fuse 30 switches the communication arrangement for two or more logic circuits . thus , as demonstrated in fig6 , multiplexers 80 ′ and 81 ′ are driven by the program circuit to allow electrical communication between logic circuit 18 ′ and redundant contact pad 20 ′, while at the same time electrically isolating contact pad 16 ′. meanwhile , the same program circuit allows for electrical communication between logic circuit 18 and redundant contact pad 20 and electrically isolates contact pad 16 . blowing fuse 30 switches the electrical communication pathways for both logic circuits 18 and 18 ′. fig7 demonstrates another embodiment of the current invention . the isolation circuit 22 has a similar configuration to the one in fig3 except that ( 1 ) the fuse 30 has been replaced with an anti - fuse 36 ; ( 2 ) the second inverter 34 now drives the n - channel transistor q 1 ; and ( 3 ) the first inverter 32 directly drives the p - channel transistor q 2 . given this configuration , the direct path from the signal node 28 to ground is initially barred by the anti - fuse 36 . consequently , a high signal is transmitted to the first inverter 32 . the low signal output drives the p - channel transistor q 2 . the second inverter 34 turns this low signal into a high signal in order to drive the n - channel transistor q 1 . with both transistors q 1 and q 2 on , the redundant contact pad is fully coupled to the logic circuit . once the anti - fuse is programmed , however , the signal node 28 becomes grounded and a low signal is transmitted to the first inverter 32 , which sends a high turn - off signal to the p - channel transistor q 2 . moreover , this high signal is altered by the second inverter 34 so that a low signal turns off the n - channel transistor q 1 . with both transistors q 1 and q 2 off , the redundant contact pad 20 is no longer in electrical communication with logic circuit 18 . it can be appreciated that an anti - fuse 36 could replace the fuse many of the embodiments of this invention . accordingly the “ program circuit ” could include an anti - fuse . an embodiment illustrated in fig8 demonstrates that the isolation circuit 22 can comprise the fuse 30 directly interposed between the redundant contact pad 20 and the logic circuit 18 , wherein programming the fuse isolates the redundant contact pad 20 . programming can occur at the completion of testing or at a stage in any other application where isolation of a contact pad is beneficial . it should be noted that , while this embodiment conserves die space , embodiments such as those in fig3 through 7 are better at preventing accidental programming due to an esd event . if wafer testing indicates a likelihood that the wafer has a yield of good quality dies , the dies are separated from the wafer and undergo a packaging process . many such processes involve attaching a die 14 to a lead frame 42 , such as one shown in fig9 , and using bond wires 44 to connect the contact pads 16 to the conductive leads 46 of the lead frame 42 . the die / lead frame assembly may then be encased , with the outer ends of the conductive leads 46 remaining exposed to allow communication with external devices . however , some conductive leads may not be connected to the contact pads of a die . such a conductive lead is designated as a “ no - connect ” or “ nc ” pin , as demonstrated in the pin - out diagram of fig1 a . after assembly , a packaged device may then be subjected to further testing . fig1 b depicts an embodiment of the current invention that makes use of the no - connect pin 38 of the packaged die 14 for such testing . prior to assembly , the die 14 is configured to include a redundant contact pad 20 coupled to a logic circuit 18 through an isolation circuit 22 . further , the no - connect pin 38 is connected to the redundant contact pad 20 by a bond wire 44 . as a result , communication with the logic circuit 18 may be accomplished during testing of the device through the no - connect pin 38 . once testing is complete , the isolation circuit 22 , which may comprise one of the configurations described above , is programmed , thereby halting communication between the no - connect pin and the logic circuit . moreover , other embodiments of the current invention allow for isolating an additional contact pad that is not necessarily a test - mode pad . as shown in fig1 , isolation circuits can be used to allow a die to adapt to more than one lead frame configuration . fig1 shows eight logic circuits 48 , 50 , 52 , 54 , 56 , 58 , 60 , and 62 coupled to a first group of contact pads 64 located on opposing sides 68 , 70 of a die 14 . these eight logic circuits are also coupled to a second group of contact pads 66 extending along a center axis 76 of the die 14 between the between the opposing sides 68 , 70 . an isolation circuit 22 is also provided . in this embodiment , the isolation circuit 22 resembles the one depicted in fig6 , where the isolation circuit 22 not only services more than one logic circuit but also enables exclusive electrical communication within a logic circuit to be switched between two contact pads . fig1 further demonstrates that the first group of contact pads 64 is configured to accommodate a lead frame having conductive leads 72 that address the opposing sides 68 and 70 of the die 14 . the second group of contact pads 66 will favorably receive a lead frame having conductive leads 74 addressing internal portions of the die , such as those near the center axis 76 . thus , depending on the lead frame ultimately chosen , the current invention allows for particular contact pads to be isolated accordingly . as in fig6 , the isolation circuit in fig1 is assumed to be configured to turn on the transistors in multiplexers 80 when the fuse is intact . it should also be noted that multiplexers 80 are interposed between the first group of contact pads 64 and their respective logic circuit . further , multiplexers 81 are interposed between the second group of contact pads 66 and their respective logic circuit . thus , if the fuse 30 is not blown , then electrical communication with the logic circuits 48 , 50 , 52 , 54 , 56 , 58 , 60 , and 62 is achieved solely through the first group of contact pads 64 . should it be determined to package the die 14 with a lead frame having conductive leads 72 , the fuse remains unprogrammed , the conductive leads 72 are wire bonded to that group , and the second group of contact pads 66 remain isolated . if , however , a lead frame including conductive leads 74 is to be packaged with the die 14 , then by programming a single fuse 30 , the second group of contact pads will be in electrical communication with the logic circuits 48 , 50 , 52 , 54 , 56 , 58 , 60 , and 62 . moreover , the first group of contact pads 64 , having been isolated due to blowing the fuse , will not contribute additional capacitance to the circuit operations . the embodiment illustrated in fig1 can accommodate still other lead frames , wherein only some of the contact pads of a group need to be isolated . while the logic circuit / contact pad layout in fig1 is similar to the configuration in fig1 , the isolation circuitry is preferably more like the arrangement in fig5 . furthermore , it would be beneficial in this embodiment to use a plurality of isolation circuits 22 in order to provide one fuse 30 for every contact pad pair associated with a logic circuit . given this configuration , each fuse 30 can be programmed as needed to accommodate the lead frame . for example , the lead frame in fig1 has some conductive leads 74 addressing internal portions of the die near the center axis 76 , and the lead frame has other conductive leads 72 that address opposing sides 68 and 70 of the die 14 . therefore , only some of the contact pads in the first group 64 should be isolated , as should some of the contact pads in the second group 66 . the embodiment in fig1 allows this selectivity . it would be a further benefit to associate a particular group of contact pads with multiplexers having the same initial state . for example , assuming that each contact pad in the first group 64 is respectively coupled to the multiplexer 80 of each isolation circuit 22 , it follows that the entire first group 64 is initially in electrical communication with the logic circuits 48 , 50 , 52 , 54 , 56 , 58 , 60 , and 62 . it also follows that the entire second group 66 is associated with the multiplexers 81 of the isolation circuits 22 and are therefore isolated . in order to accommodate the conductive leads 72 , 74 illustrated in fig1 , it is relatively easy , given contact pad / isolation circuit association , to determine that only the fuses 30 corresponding to logic circuits 50 , 52 , 58 , and 60 need to be blown . in addition , one can appreciate that other lead frame adapter embodiments could use isolation circuits similar to those depicted in fig3 , 7 , and 8 . finally , one of ordinary skill can appreciate that , although specific embodiments of this invention has been described for purposes of illustration , various modifications can be made without departing from the spirit and scope of the invention . for example , concerning the embodiments discussed above that use a fuse , such a fuse could comprise one of various types of fuses , including a link fuse or a laser fuse . alternatively , the fuse could be replaced by an anti - fuse with minor configuration changes . moreover , embodiments such as those in fig3 through 7 using both a p - channel and an n - channel transistor as a link could be modified to use only one of the transistors . accordingly , the invention is not limited except as stated in the claims .