reference will now be made in detail to the preferred embodiments of the present invention , examples of which are illustrated in the accompanying drawings . fig1 is a circuit diagram of an exemplary shift register of an lcd panel according to the present invention . in fig1 , a gate or data start pulse vst , four clock signals clk 1 – clk 4 each having different phases , and power drain voltages vdd and vss may be input to a shift register . in addition , the shift register may have five blocks of transistor each having similar structures . each of the five blocks may include first , second , third , fourth , fifth , sixth , seventh , eight , and ninth p - mos transistor tft 1 – tft 9 . in particular , the first transistor tft 1 may have drain and gate terminals to which the start pulse vst is supplied or connected to an output terminal of the previous block . for example , in the , first block , the drain and gate terminals of the first transistor tft 1 may be connected to receive the start pulse vst , and in the second block , the drain and gate terminals of the first transistor tft 1 may be connected to the first output terminal output 1 . the second transistor tft 2 may have a drain terminal connected to a source terminal of the first transistor tft 1 , and a gate terminal to which one of the four clock signals clk 1 – clk 4 may be supplied . for example , in the first block , the fourth clock signal clk 4 may be supplied , and in the second block , the first clock signal clk 1 may be supplied . in addition , the third transistor tft 3 may have a source terminal connected to a source terminal of the second transistor tft 2 , and a drain terminal connected to the vss terminal . the fourth transistor tft 4 may have a drain terminal connected to the vdd terminal , a gate terminal to which one of the four clock signals clk 1 – clk 4 is supplied , and a source terminal connected at a node qb to a gate terminal of the third transistor tft 3 . for example , in the first block , the third clock signal clk 3 may be supplied , and in the second block , the fourth clock signal clk 4 may be supplied . the fifth transistor tft 5 may have a drain terminal connected at the node qb to the source terminal of the fourth transistor tft 4 , a gate terminal connected to a contact node q between the source terminal of the second transistor tft 2 and the source terminal of the third transistor tft 3 , and a source terminal connected to the vss terminal . further , the sixth transistor tft 6 may have a drain terminal to which one of the four clock signals clk 1 – clk 4 is supplied , a gate terminal connected at the node q to the source terminal of the second transistor tft 2 , and a source terminal connected to a corresponding output terminal . for example , in the first block , the first clock signal clk 1 may be supplied , and in the second block , the second clock signal clk 2 may be supplied . in addition , in the first block , the source terminal of the sixth transistor tft 6 may be connected to the first output terminal output 1 , and in the second block , the source terminal of the sixth transistor tft 6 may be connected to the second output terminal output 2 . the seventh transistor tft 7 may have a drain terminal connected to the corresponding output terminal as the source terminal of the sixth transistor tft 6 , a gate terminal connected at the node qb to the source terminal of the fourth transistor tft 4 and the gate terminal of the third transistor tft 3 , and a source terminal connected to the vss terminal . the eighth transistor tft 8 may have drain and gate terminals connected to an output terminal of the next block . for example , in the first block , the drain and gate terminal of the eighth transistor tft 8 may be connected to the second output terminal output 2 . moreover , in the fifth block , the drain and gate terminals of the eight transistor tft 8 may instead receive the start pulse vst . the ninth transistor tft 9 may have a source terminal connected to a source terminal of the eighth transistor tft 8 , a gate terminal to which one of the four clock signals clk 1 – clk 4 is supplied , and a drain terminal connected at the node q to the source terminal of the second transistor tft 2 and the gate terminal of the sixth transistor tft 6 . for example , in the first block , the second clock signal clk 2 may be supplied , and in the second block , the third clock signal clk 3 may be supplied . moreover , a first capacitor may connect the gate terminal of the sixth transistor tft 6 to the vss terminal . a second capacitor c 2 may connect between the gate and source terminals of the sixth transistor tft 6 . in addition , a third capacitor c 3 may connect the gate terminal of the seventh transistor tft 7 to the vss terminal . accordingly , the first clock signal clk 1 may be supplied to the drain terminal of the sixth transistor tft 6 in the first and the fifth blocks , the gate terminal of the second transistor tft 2 in the second block , the gate terminal of the fourth transistor tft 4 in the third block , and the gate terminal of the ninth transistor tft 9 in the fourth block . the second clock signal clk 2 may be supplied to the gate terminal of the ninth transistor tft 9 in the first and fifth blocks , the drain terminal of the sixth transistor tft 6 in the second block , the gate terminal of the second transistor tft 2 in the third block , and the gate terminal of the fourth transistor tft 4 in the fourth block . in addition , the third clock signal clk 3 may be supplied to the gate terminal of the fourth transistor tft 4 in the first and fifth blocks , the gate terminal of the ninth transistor tft 9 in the second block , the drain terminal of the sixth transistor tft 6 in the third block , and the gate terminal of the second transistor tft 2 in the fourth block . the fourth clock signal clk 4 may be supplied to the gate terminal of the second transistor tft 2 in the first and fifth blocks , the gate terminal of the fourth transistor tft 4 in the second block , the gate terminal of the ninth transistor tft 9 in the third block , the drain terminal of the sixth transistor tft 6 in the fourth block . although not shown , if the driving circuit includes eight blocks , the clock signal may be equally supplied to each block of transistors . fig1 illustrates forward input and output waveforms of the exemplary shift register of the lcd panel of fig1 according to the present invention . in fig1 , the four clock signals may be low in sequence . for example , during a first time period , about 0 s – 20 μs , the start pulse may be set low ( 0v ), thereby turning the first transistor tft 1 ( of the first block in fig1 ) on . also , the fourth clock signal clk 4 may be low , thereby turning the second transistor tft 2 ( in fig1 ) on . as a result , the node q ( in fig1 ) may become low . accordingly , the sixth transistor tft 6 ( in fig1 ) may be turned on , thereby supplying the first clock signal clk 1 to the first output terminal output 1 ( in fig1 ). in addition , since the second transistor tft 2 ( in fig1 ) may be on , the fifth transistor tft 5 ( in fig1 ) may also be turned on , thereby setting the node qb high ( 10v ) as the vss voltage . thus , the seventh transistor tft 7 ( in fig1 ) may be turned off , and the vss voltage may not be supplied to the first output terminal output 1 ( in fig1 ). during a second time period , about 20 μs – 40 μs , the first clock signal may be low , which may be supplied through the first output terminal output 1 ( in fig1 ) to the gate terminal of the first transistor tft 1 ( of the second block in fig1 ), and may be directly supplied to the gate terminal of the second transistor tft 2 ( in the second clock in fig1 ). thus , the first and second transistors tft 1 and tft 2 ( in fig1 ) may be on , thereby turning the sixth transistor tft 6 ( in fig1 ) on . accordingly , the second clock signal clk 2 may be supplied to the second output terminal output 2 ( in fig1 ). turning to the fifth block ( in fig1 ), during the first time period when the start pulse vst is set low , the second clock signal clk 2 may be set high , thereby turning the ninth transistor tft 9 off , even though the eighth transistor tft 8 may be turned on . since the ninth transistor tft 9 may be turned off , the node q may be high . thus , the sixth transistor tft 6 may be off and may not output the first clock signal clk 1 to the fifth output terminal output 5 . accordingly , in the fifth block , an output may be generated only when an output of a previous block is supplied in a switch - on state to the first transistor tft 1 , and not when the start pulse vst is set low . accordingly , the start pulse vst may be initially synchronized with the fourth clock signal clk 4 , and the first to third clock signals clk 1 to clk 3 may be sequentially generated , thereby sequentially supplying the four clock signals in a sequence . fig1 illustrates backward input and output waveforms of the exemplary shift register of the lcd panel of fig1 according to the present invention . in fig1 , the four clock signals may be set low in a reverse sequence . for example , in a first time period , about 0 s – 20 μs , the start pulse vst and the second clock signal may be set low . thus , in the first block ( in fig1 ), the first transistor tft 1 may be turned on , the second transistor tft 2 may be turned off , thereby turning the sixth transistor tft 6 off . as a result , the first block may not supply the first clock signal clk 1 to the first output terminal output 1 ( in fig1 ). however , in the fifth block ( in fig1 ), the eighth transistor tft 8 and the ninth transistor tft 9 may be turned on , thereby turning the sixth transistor tft 6 on . as a result , the first clock signal clk 1 may be supplied to the fifth input terminal output 5 ( in fig1 ). in addition , during a second time period , about 20 μs – 40 μs , the signal supplied from the fifth output terminal output 5 may then be supplied to the eighth transistor tft 8 in the fourth block ( in fig1 ). also , the first clock signal clk 1 may become low , thereby turning the eighth and ninth transistors tft 8 and tft 9 in the fourth block ( in fig1 ) on . as a result , the sixth transistor tft 6 ( in fig1 ) may also be turned on , thereby supplying the fourth clock signal clk 4 to the fourth output terminal output 4 ( in fig1 ). hence , the start pulse vst may be initially synchronized with the second clock signal clk 2 , and the first to fourth and third clock signals clk 1 to clk 4 and clk 3 may be sequentially generated , thereby repeatedly supplying the four clock signals in a reverse sequence . accordingly , the shift register may be driven bi - directionally , such that an lcd panel may operate regardless of panel orientation . in addition , the shift register may be driven without error regardless of how many blocks of transistors it may have . it will be apparent to those skilled in the art that various modifications and variations can be made in the bi - direction driving circuit and the bi - direction driving method of a liquid crystal display pane of the present invention . thus , it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents .