referring initially to fig1 ( a ), there is shown a cross - sectional view of a semiconductor device structure 100 , in which an active device area 102 is adjacent an sti region 104 . a substrate corresponding to the active device area 102 may include any suitable semiconducting material such as , but not limited to : silicon ( si ), germanium ( ge ), silicon germanium ( sige ), silicon carbide ( sic ), silicon germanium carbide ( sigec ), gallium arsenide ( gaas ), gallium nitride ( gan ), indium arsenide ( inas ), indium phosphide ( inp ) and all other iii / v or ii / vi compound semiconductors . the semiconductor substrate may also comprise an organic semiconductor or a layered semiconductor such as si / sige , a silicon - on - insulator ( soi ), a sige - on - insulator ( sgoi ) or germanium - on - insulator ( goi ). as further shown in fig1 ( a ), a plurality of hkmg stacks 106 are formed over the active area , and include a high - k dielectric layer 108 ( e . g ., hafnium silicate , zirconium silicate , hafnium dioxide , zirconium dioxide , etc .) one or metal layers 110 ( e . g ., titanium nitride ( tin )) formed over the high - k dielectric layer 108 , and a polysilicon layer 112 formed over the metal layer ( s ) 110 . in this instance , it will be noted that the active area gate stack 106 located adjacent the sti region 104 partially extends over to the sti region 104 , thus leading to formation of a metal foot 114 on the sti region 104 . in the formation of fet gate devices , insulating spacers 116 are formed on sidewalls of the gate stacks , as shown in fig1 ( b ). where a step height , x , between a recessed sti region 104 and active area substrate 102 exceeds a thickness , z , of the metal layer 110 in the hkmg stack , the result may be an asymmetric extrusion of the metal foot 114 by a width , y . if this dimension y is great enough so as to equal or exceed a thickness , δ , of the sidewall spacer 116 , then at least a portion of the metal foot 114 will be left unprotected by the sidewall spacer 116 . as a result , the gate metal is vulnerable to wet etch chemistries during subsequent processing steps , which in turn may result in gate liftoff . by way of further illustration , fig2 is a scanning electron microscopy ( sem ) image of a semiconductor device structure with hkmg stacks such as shown in fig1 ( a ) and 1 ( b ). in particular , it will be seen that the outermost gate stacks partially extend down into a recess between the active area the adjacent sti region . a similar issue may exist in the case of a so - called dummy gate stack formed over the sti region , but very close to the active area region . for example , fig3 ( a ) is a cross - sectional view of a semiconductor device structure 300 with hkmg stacks where a dummy gate stack 306 formed on an sti region adjacent an active area is formed with excess metal thickness at the sti / active area border . this excess metal thickness results from both the step height between the active area 102 and sti region 104 , and the proximity of the gate stack 306 to the active area 102 . as shown in fig3 ( b ), the formation of the sidewall spacers 116 does not completely protect the gate metal 110 from subsequent processing , as shown at region 308 . by way of further illustration , fig4 is sem image of a semiconductor device structure with hkmg stacks such as shown in fig1 ( a ) and 1 ( b ). in particular , it will be seen that the outermost gate stacks partially extend down into a recess between the active area the adjacent sti region . still another example of the effects of sti divoting on metal gate structures is shown in fig5 , which is a top view of a semiconductor device structure 500 illustrating metal divot formation due to overlap of a gate structure with an sti divot . specifically , the dashed lines in fig5 represent gate structures that overlap a ( rectangular ) sti divot region . on the left portion of fig5 , the gate structures slightly overlap the sti divot . however , on the right portion of fig5 , the gate structures extend and overlap the sti divot orthogonally , which again leads to the spacer material floating above protruding gate metal and failing to encapsulate the metal gate . fig6 is an sem image of a semiconductor device structure with a metal divot protrusion such as shown in fig5 . accordingly , fig7 ( a ) through 7 ( e ) are a sequence of cross - sectional views illustrating an exemplary embodiment of a method of protecting exposed metal gate structures from etching processes during integrated circuit manufacturing . in particular , fig7 ( a ) illustrates a semiconductor device structure 700 with hkmg stacks where an active area gate stack 706 formed adjacent an sti region partially extends over to the sti region 704 , leading to formation of a metal foot 714 on the sti region 704 . in fig7 ( b ), the formation of a first set of spacers 716 on the gate sidewalls fails to completely encapsulate the metal foot 714 . then , as shown in fig7 ( c ), an isotropic etch is performed to remove the metal foot portion of the gate stack metal layer , while still preserving the planar portion of the metal layer 710 formed atop the high - k gate dielectric layer 708 . suitable isotropic etch conditions may include , for example , an inductive plasma etch operating at about 5 millitorr ( mt ) to about 30 mt , with an etch chemistry comprising about 20 %- 70 % by volume bcl 3 , about 0 - 20 % by volume cl 2 , with the balance thereof being ar , and at wafer temperature of about 100 ° c . to about 400 ° c . in a more specific embodiment , isotropic etch conditions may include , for example , an inductive plasma etch operating at about 5 - 10 mt , with an etch chemistry comprising about 40 %- 60 % by volume bcl 3 , about 5 %- 10 % by volume cl 2 , with the balance thereof being ar , and at wafer temperature of about 180 ° c . to about 280 ° c . by performing an isotropic etch of the metal , the bottom of the spacer layer 716 that was initially formed atop the foot is undercut . in the embodiment depicted , the first set of spacers 716 comprises sacrificial spacers , in that they are removed following the isotropic etch , as shown in fig7 ( d ). however , in other embodiments , the first set of spacers may remain . as then shown in fig7 ( e ), a second set of spacers 720 is formed in a manner similar to the first set of spacers . here , however , the second set of spacers completely covers the exposed gate metal due to the isotropic etching . a small void 722 may be formed as a result , but since the spacer material extends all the way to the top of the sti region 704 , the gate stack metal is encapsulated . processing in accordance with known techniques may proceed thereafter . as stated above , the first set of spacers may remain upon the gate stack following the isotropic etch of the metal protrusion . this variation is depicted in the alternative embodiment of fig8 ( a ) through 8 ( d ). in this embodiment , the processing of fig8 ( a ) through 8 ( c ) is the same as in fig7 ( a ) through 7 ( c ). instead of removing the first set of spacers 716 following the isotropic etch of the metal protrusion / foot , the spacers 716 remain on the gate stacks , followed by formation of a second set of spacers 820 , as shown in fig8 ( d ). since the second set of spacers 820 extends all the way to the top of the sti region 104 , the gate metal is completely encapsulated for further device processing , with a small void 822 possibly resulting . finally , fig9 ( a ) through 9 ( d ) are a sequence of cross - sectional views illustrating a method of protecting exposed metal gate structures from etching processes during integrated circuit manufacturing , in accordance with another exemplary embodiment . in this example , fig9 ( a ) illustrates a semiconductor device structure 900 with hkmg stacks where a dummy gate 906 formed on an sti region 904 adjacent an active area 902 is formed with excess metal thickness at the sti / active area border . in fig9 ( b ), a first set of spacers 916 is formed over the hkmg stacks of fig9 ( a ). as can be seen , the width of the spacers 916 is insufficient to completely encapsulate the excess metal 910 between the gate stack 906 and the active area step height . as shown in fig9 ( c ), both the excess metal 910 and high - k gate dielectric 908 are isotropically etched , vertically and horizontally , so as to undercut the short side spacer 916 . thus , upon formation of a second set of spacers 920 in fig9 ( d ), the metal gate material 910 is completely encapsulated . as will thus be appreciated , through the use of an isotropic metal etch following a first spacer formation , a subsequently formed second set of spacers is able to completely protect an hkmg stack from middle - of - line ( mol ) wet etch processes . this avoids the need , for example , to overetch the metal during the initial gate stack formation and unnecessarily undercutting the device gates . while the invention has been described with reference to a preferred embodiment or embodiments , it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention . in addition , many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof . therefore , it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention , but that the invention will include all embodiments falling within the scope of the appended claims .