referring now to fig2 , this shows a dual loop clock synchroniser embodying the invention . this synchroniser comprises two blocks : an analogue phase locked loop 2 ( apll ) which generates a low jitter local clock lck ; and a control circuit 3 . the apll synthesises the local clock , of frequency f lck , from a reference signal 10 , of frequency f ref , generated by the reference oscillator 1 , which incorporates the local crystal 11 and oscillator circuitry 12 . the apll includes a controllable divider circuit in the feedback path from its output clock to its input phase detector which sets the ratio of f ref to f lck according to f lck = f ref * n where n is the divider ratio . the control circuit 3 includes a clock comparison circuit 5 which compares a received clock rck and the local clock lck and generates a digital signal 7 indicative of any asynchronism between them , and a control link 6 which conditions this indicative asynchronism signal 7 to provide a digital control signal 4 to the apll . this digital control signal 4 is applied to a controllable divider in the apll , which is arranged to adjust the division ratio n in the feedback path of the apll to adjust f lck , so as to bring the frequencies of the clock signals lck and rck together . as regards the apll , it is often desirable to have the vco frequency running faster than needed and dividing that clock down to the desired rate to achieve a low phase noise . for r . f . applications the divider ratio is often large , and adequate frequency resolution may be obtained with an integer divider ratio . but more commonly , a non - integer divider ratio is needed to provide adequate frequency resolution . thus , certain embodiments of the present invention use a fractional - n pll so that the output frequency of the pll can be adjusted to the resolution to which n can be specified . for example a resolution of 22 bits for n will allow the frequency to be adjusted to 1 part in 2 ̂ 24 , corresponding to a beat frequency of once every 92 minutes for a 48 khz clock . in practice the frequency will tend to hunt between the two ( or maybe a few ) closest increments in n : the resolution of n should be high enough so that the resulting jitter is small compared to the output jitter due to other sources . the combination of divider control circuit 3 ( i . e . clock comparison circuit and control link ) and apll 2 may be considered to implement a digital frequency - locked loop ( dfll ). to prevent jitter passing from the remote clock to the local clock the dfll is designed with a low loop bandwidth . input jitter components within this bandwidth will pass through the dfll , as will long - term clock frequency variations . however , jitter components above a certain frequency are attenuated . for audio applications this corner frequency is arranged to be below 200 hz , to prevent clock jitter components in the audio band from producing signal distortion when used to reconstruct the analogue audio signal in a dac , for example . the low loop bandwidth of the dfll is achieved using digital filtering in the loop instead of the large off chip filter components a dual analogue pll approach would use . the physical size of these components is a problem especially in portable systems . the use of digital techniques also allows the frequency above which jitter is attenuated to be pushed significantly lower than would be practical using off chip components . component values would be constrained by on - and off - chip leakage currents compared to the low - value on - chip current sources , and the thermal noise of high - impedance components contributing to pll output noise / jitter . in cost sensitive designs the cost reduction of not using off chip components and improving performance is a significant advantage over traditional approaches . from the above description of fig2 , it will be apparent that in certain embodiments of the invention the control circuit comprises a clock comparison circuit controlling the apll divider with a suitably arranged control link . the clock comparison circuit in certain embodiments comprises a period detection circuit . in other embodiments it may comprise a frequency detector , or a phase detector . different filtering is required to obtain loop stability and to define the desired low loop bandwidth to provide jitter attenuation for each case . as analysed later , this control circuit block eventually typically delivers an output which is indicative ( albeit loosely in some examples ) of the accumulated slippage between the two clocks , rather than the instantaneous frequency , period or phase difference between the local and received clocks . this accumulated slippage or asynchronism may also be regarded as a measure of jitter between the most recent corresponding chosen edges of the two clocks . preferably this measure is not subject to any frequency weighting or attenuation : it is the loop gain of the whole loop which provides attenuation of medium and high frequency jitter between the received clock and the local clock . fig3 shows another embodiment of the invention . this clock synchroniser comprises a clock comparison circuit 31 which compares the locally generated clock lck with the received clock rck . the clock comparison circuit 31 can be implemented in a variety of ways to give different measures of asynchronism . a possible implementation is shown in fig7 . this circuit is a period detector . this circuit uses two counters 35 , 36 that hold their maximum value when the clear signal is asserted . these counters can be clocked by a clock pck from the apll , or some other convenient source . the counter values each represent the duration , in units of pck period , t pck , of the respective input clock , and are compared by a comparator 37 which outputs a digital signal 311 indicative of the relative pulse lengths of the rck and lck signals , and hence also indicative of a period difference between the local and remote clocks . looking at the circuits of fig7 and fig3 , this generates a positive output 311 if the received clock is running faster and a negative output if the local clock is running faster . this output signal 311 can be regarded as a measure of the period error of the two clocks . the signal 311 is scaled by a gain block 32 of gain g 1 and input to an integrator 33 integrating the detected period difference to give a digital number δn representing the slippage between the clocks in units of t pck / g 1 . in the circuit of fig3 , this digital number is supplied direct to the divider , as a digital control signal δn . in other embodiments , such as that shown in fig4 , the digital number from the integrator 33 may be scaled by another gain block 34 with associated gain g 2 ( typically dividing by a power of two , i . e . a bit - shift , for hardware simplicity ) to give a number δn which is then added ( using an adder 41 ) to the nominal divider value , n , for the pll . this system has a transfer function , t , from the input to n which can be derived in the following manner : where f ref is the frequency of the reference clock , in this case that of the crystal oscillator 12 . so to first order , the small - signal transfer function of the apll is it is assumed that the dominant pole in the apll is at least one decade higher than the open loop unity gain frequency of the overall dfll to ensure stability the period detector determines the period difference : if f lck is approximately equal to f rck , and f pck / f lck = m , say , this approximates to where t fd = m / f lck can be considered a small - signal transfer function δδn / δf lck of this block and the digital filter , in this case a simple integrator , operates upon δn ( possibly gained by a value g1 ) to give a number δn ( representing the clock slippage or the jitter between corresponding clock edges ): hence we can define the transfer function of the digital filter as : which leads to the closed loop transfer function from rck to lck of g1 can be used to dynamically adjust the bandwidth . for this system the cut - off frequency of the control loop is approximately given by where t pck is the period of pck . for a pck of 48 khz , m / n = 1 , and a g1 of note the loop bandwidth gain can be temporarily increased , to increase the loop bandwidth and hence reduce lock times , on start - up or re - acquisition , by increasing the gain term g 1 . although the circuit of fig3 employed a clock comparison circuit in the form of a period detector , giving a multi - bit digital output , other implementations are possible for the detector . one additional form of clock comparison circuit is shown in fig8 and represents a variant of that shown in fig7 . the circuit of fig8 outputs a digital signal 311 which represents the difference between the two counters as just 1 , 0 or − 1 rather than a multi - bit word . in this case the integrator 33 can be replaced by a simple counter , which is incremented , unchanged , or decremented according to whether the output is + 1 , 0 , or − 1 respectively . this implementation provides adequate performance with significantly less hardware or calculation complexity . another suitable clock comparison circuit is shown in fig9 . this circuit counts the number of lck and rck cycles during each cycle of a relatively low frequency pck and thus acts as a frequency detector . this could be followed within the frequency detection circuit by a simple integrator , or more complex filter if desired . another clock comparison circuit for use in embodiments of the invention is shown in fig6 . this is the well known phase and frequency detector ( pfd ) circuit widely used in modern apll designs . in this case the phase detection already implies an integration of the input frequency difference in the loop , so the digital filter included in the whole frequency detection circuit would typically include one pole and one zero , rather than being a pure integrator . the pole would smooth high - frequency ripple , the zero would ensure stability near the low closed - loop frequency . implementations using these alternative clock comparison circuits can be analysed mathematically similarly to the above . in principle , by increasing the resolution of n , an arbitrarily exact clock synchronisation could be achieved . however the apll will itself introduce some jitter to the local clock through noise and other imperfections . apll jitter components of frequency less than the dfll loop bandwidth will be attenuated in the same way as remote clock jitter . but if the jitter of the apll , measured over interval of less than the order of the dfll time - constant , is of the order of a clock period , then this apll short term jitter will negate any advantages of the dfll control loop , i . e . edges of the local clock may still slip past edges of the remote clock . in other words the apll loop must be designed so that where s θ is the power spectral density of the apll output , bw is the bandwidth of the dfll and t lck is the local clock period . in practice bw is small , so the integral approximates the integral from 0 to infinity , i . e . the full integrated jitter of the apll . plls can easily be designed to give long term jitter will be less than ins . this easily satisfies the above constraint for audio applications , where the clock frequency will be a few mhz at most , but may be a limit for higher - data - rate links , where more care and expertise would be required in the pll design . fig4 illustrates some further features of a possible implementation of the inventive clock synchroniser . the output from the integrator 33 is scaled as appropriate by g 2 ( by gain block 34 ) and added to the nominal divide ratio using an adder 41 . the adder output ( the sum of the two digital signals ) is typically input to a sigma delta modulator ( sdm ) 42 inside the apll 2 to use noise shaping to achieve a fractional frequency multiplication with low apll output jitter . also the apll vco 23 will typically run at a high frequency to allow low phase noise . as shown , the output system clock lck will typically be divided down independently , using divider 5 as shown , for maximum resolution in frequency . to reduce hardware some of the stages of divider 5 and the feedback divider could be shared . but this would be equivalent to just having a reduced - frequency vco which is undesirable as limiting resolution of the feedback divider . although we are referring to the plls 2 in fig4 and 5 as analogue plls , they do incorporate digital phase detectors in the form of pfds 21 . these generate digital outputs . the digital phase detector outputs are used to control a charge pump ( or pumps ) 24 , which in turn supply charge ( current ) to a loop filter 25 . the loop filter integrates the supplied current and provides a control voltage to the vco . the filter voltage , controlling the vco , is thus a continuous ( i . e . non - digital ) control parameter , and it is for this reason that the circuits are referred to as aplls . extension of the above algebraic analysis to fig4 is straightforward to one versed in the art . fig5 shows another embodiment , representing one possible implementation suitable for a system where the nominal clock frequency is uncertain , e . g . in digital audio systems where the input clock can be related to a base frequency of either 48 khz or 44 . 1 khz . a sample rate detector 43 , incorporating a counter clocked from the known crystal frequency , provides a crude estimate of the input frequency ( i . e . the received clock rck frequency , and hence the remote clock frequency ). this counter output is used by the control link circuitry to choose an approximate estimate for the nominal apll divider ratio n , in this example by means of a memory ( rom 44 ) storing a set of appropriate values for anticipated possible input clock frequencies . this arrangement greatly reduces lock time , as well as allowing ( and accommodating ) abrupt changes in transmission clock frequency . the control circuitry is arranged such that the sample rate detector will usually only be used initially after a system reset , and the dfll will track any subsequent frequency changes . the accuracy to which this system can synchronise the clock is limited to the digital accuracy to which n can be specified . hence the local clock frequency will hunt between the two closest possibilities . this will not result in data loss as long as the frequency difference is not enough to cause the local clock to jump between samples of the data it will be apparent that clock synchroniser circuits embodying the present invention can provide the following advantages : they can generate clean local clock signal , suitable for low - distortion dacs , for example ; they can attenuate jitter on an incoming clock to very low frequency ; they can provide the above advantages without the need for large off chip filter components ( reducing cost , and providing performance that is less sensitive to ground bounce etc ); the circuits can be implemented in small silicon areas in comparison to prior art circuits incorporating elastic buffers and large analogue components needed to achieve the same loop bandwidth ; and unlike elastic buffer systems ( requiring a large elastic buffer for each channel ), only one clock synchroniser embodying the invention is required for a multiple channel application . the skilled person will also appreciate that the various embodiments and specific features described with respect to them could be freely combined with the other embodiments or their specifically described features in general accordance with the above teaching . the skilled person will also recognise that various alterations and modifications can be made to specific examples described without departing from the scope of the appended claims .