fig1 is an illustrative block diagram of a system 100 including an lcd 110 that was tested and calibrated by a testing platform ( e . g ., as shown in a later fig .) in accordance with an embodiment of the invention . as shown , lcd 110 may have lcd driver 112 mounted thereon . lcd driver 112 may be connected to connector 114 via a flex ( connection outlined by the dotted lines between elements 112 and 114 ). the combination of lcd 110 , driver 112 , and connector 114 may be a subassembly ( denoted by dashed box 116 ) that is tested by a testing platform according to the invention prior to assembly of system 100 . connector 114 may be electrically coupled to processor 120 via communications paths 118 . communications paths 118 may be any suitable path for transmitting data signals . for example , communications paths 118 may be a wired link or a fiber optic link . processor or cpu 120 may transmit and / or receive data according to a particular protocol . in one embodiment , the protocol may be a mipi protocol , which is a differential - ended , high - speed , serial interface ( hssi ) used to interface processor 120 and lcd 110 . structurally , mipi uses a pair of wires for each lane being used to transmit data . for example , in one embodiment , a clock lane and at least one data lane may be used to transmit information to lcd 110 . the data may be transmitted in packets . for example , a packet may include header information and data . the header information may specify if the data is control information ( which may be used to control , for example , workflow ) or image information ( which may be used to generate red / green / blue values for pixels in the display ). advantages of using mipi include reduced number of wires , faster charge / discharge of parasitic capacitance , reduced voltage swing , reduced number of pins , and increased signal integrity . to achieve optimal performance , various portions of the peripheral interfacing with the processor using mipi ( e . g ., lcd driver 112 ) may require customization . these customized parts may require custom programming , which is provided using a testing system in accordance with embodiments of this invention . as also shown in fig1 , system 100 can include volatile memory 130 ( e . g ., ram or ddr ) and non - volatile memory 140 ( e . g ., flash or a hard - disk ). processor 120 can communicate with memories 130 and 140 to obtain data as needed and provide it , for example , to a peripheral . for example , when system 100 displays content on lcd 110 , processor 120 may obtain content from non - volatile memory 140 , buffer a frame of content in volatile memory 130 , and provide the buffered content to lcd 110 over path 118 , according to the mipi protocol , for display . using the mipi protocol , processor 120 can substantially directly communicate with lcd driver 112 . that is , there is no need for bridge circuitry , which is used in connection with mpl ( i . e ., single - ended hssi ) protocol systems , to be disposed between processor 120 and connector 114 . ( mpl is the acronym for the mobile pixel link communications protocol .) the mipi protocol offers substantial advantages over its mpl counterpart in terms of performance and system integration . in terms of integration , processor 120 can process data retrieved from memory 130 or 140 according to the mipi protocol and provide it to lcd 110 . thus , because processor 120 is processing data according to the mipi protocol , peripherals ( such as lcd 110 ) interfacing with processor 120 may need to be tested and / or calibrated to ensure optimal operation . for example , it may be necessary to test whether a peripheral is properly receiving or processing data according to the mipi protocol . in another example , a test may need to be run to determine if the peripheral is operating according to predetermined criteria . fig2 shows an illustrative test system 200 according to an embodiment of the invention . test system 200 can include test computer 210 , test module 220 , and lcd subassembly 116 . module 220 can include test processor 120 , dock 222 , dock 224 , interface 226 , and daughter - board 230 . test processor 120 may be another instance of the same processor as that shown in fig1 . using the same processor ( i . e ., processor 120 ) in test system 200 that is used in end - use system 100 advantageously promotes testing and calibration of lcd subassembly 116 . ( the phrase “ end - use ” just refers to the final hook - ups or connections to peripheral 116 per se .) it will be understood that the term “ same processor ” refers to the same make and model processor , both instances of which may be operating according to the same firmware instruction set ( stored , e . g ., in memory 221 ). if it is desired to update the firmware or other software of test system 200 , test computer 210 may provide such updates via dock 224 . test computer 210 may be electrically coupled to test processor 120 via path 212 and dock 222 . through path 212 , test computer 210 may control processor 120 to test a peripheral ( shown as lcd subassembly 116 ) attached to module 220 . commands and data provided by test computer 210 may be processed by processor 120 and provided to interface 226 , which routes the commands and data through daughter - board 230 to connector 114 . after test computer 210 finishes testing and / or calibrating subassembly 116 , subassembly 116 may be removed and a new one put in its place . test computer 210 may include software ( e . g ., a control application ) 211 to control test module 220 and test a peripheral ( shown as lcd subassembly 116 ) attached to test module 220 . the software 211 may test any number of parameters related to the peripheral 116 or the system ( e . g ., processor ). for example , in an embodiment where the peripheral is an lcd subassembly , the test computer 210 may test display 110 for flicker and gamma performance , test the system for serial interface link performance , and test the system for optical performance . in addition , test computer 210 may be able to adjust various parameters affiliated with the peripheral . in the lcd subassembly 116 embodiment , adjustments may be made for flicker and gamma values . the adjustments may be made at the direction of a user who manually directs the adjustments though test computer 210 , or adjustments may be performed automatically by test computer 210 . automatic adjustments may be performed , for example , by having a camera ( not shown ) monitor the lcd screen and feed back data ( e . g ., flicker and gamma values ) to test computer 210 , which uses that data to make adjustments as necessary . test computer 210 may also be able to program peripherals attached to module 220 . for example , after test computer 210 determines the appropriate flicker and gamma values for subassembly 116 , test computer 210 may program an eeprom ( not shown separately ) located in lcd driver 112 so that it operates according to the flicker and gamma values determined to work best for this particular subassembly 116 . one of the advantages of test system 200 is that it permits test computer 210 to directly access and control mipi protocol commands in processor 120 . fig3 is a flow chart of illustrative steps that may be performed by a test system ( e . g ., as in fig2 ) in accordance with an embodiment of the invention . starting at step 310 , a peripheral ( e . g ., an lcd subassembly 116 ) is connected to a testing system ( e . g ., daughter - board 230 of fig2 ). at step 320 , tests may be performed on the peripheral using a test processor ( e . g ., 120 ) processing data and commands supplied by a test computer ( e . g ., 120 ). if desired , tests may be performed to evaluate the communications link ( e . g ., 112 , 114 , etc .) between the test processor ( e . g ., 120 ) and the peripheral ( e . g ., 116 ). at step 330 , at least one parameter associated with the peripheral ( e . g ., 116 ) is adjusted to determine an optimal parameter setting for such parameter ( s ). it will be understood that steps 320 and 330 may be performed in conjunction with each other . the parameter adjustments may be performed by the test processor ( e . g ., 120 ) under the direction of the test computer ( e . g ., 210 ). after all adjustable parameters have been found , the optimal parameter settings ( s ) may be saved on the peripheral ( e . g ., 116 ), as indicated by step 340 . the test processor ( e . g ., 120 ) may save the settings in on - board memory mounted to the peripheral ( e . g ., 116 ). it will be appreciated that these steps are merely illustrative , and that additional steps may be included or existing steps may be omitted . for example , a step may be added to account for manual input of parameter adjustments by a test system user . the foregoing describes systems and methods for testing peripherals that interface with a processor using a mipi protocol . those skilled in the art will appreciate that the invention can be practiced by other than the described embodiments , which are presented for the purpose of illustration rather than of limitation , and the invention is limited only by the claims which follow .