the present invention is described below in the context of a “ band pass filter .” the reference to “ band pass filter ” is intended to refer to a use of a difference of an input signal and a time shift version of the input signal to extract a desired frequency band from the input signal . many advantages can be identified by the use of the present invention to build a band pass filter . for instance , the power consumption , the complexity , the costs , and the device area required for a regular band pass filter are greatly reduced by use of the band pass filter architecture of the present invention . from a consumption of device area point of view , it is well known by those of ordinary skill in the art that the area and the number of logic gates required for an adder or a subtracter is much less than a multiplier required . a wide range of band pass filters is built upon iir or fir band pass filter architectures that use not only adders and multipliers but also a set of coefficients to achieve a frequency band extracting functions . both input lines for coefficients and hardware layout for adders and multipliers increase complexity and power consumption of a band pass filter . as a consequence , a built up heat due to power consumption of the band pass filter also causes more possible hardware failures during the hardware operation . on the other hand , as a contrast , to implement the present invention in hardware , a shift register with a predetermined length and an arithmetic subtracter are enough to achieve a functionality of a band pass filter . the present invention is also feasible for software implementation . by use of the present invention in software , less coding , less variables , and less software overhead bring up the performance of a software band pass filter application . the present invention can be realized not only in computer hardware or computer software but also in an analog circuit as a user wishes . there are three preferred embodiments of the present invention are addressed as follows ; however , the present invention is not limited to these preferred embodiments . the first preferred embodiment of the present invention uses a shift register and an arithmetic subtracter to form a band pass filter 100 as depicted in fig1 . the shift register 101 is constructed by a plurality of registers coupled in cascade ; therefore , a data entrance end 104 and a data exit end 106 of the shift register is provided . the arithmetic subtracter 110 subtracts a value holding in the exit end 106 register from a value holding in the entrance end 104 register to produce an output of the band pass filter 140 . a detail of the band pass filter functions as follows . at the beginning , zeros are preset to all registers in the shift register before the system is ready to do its job . an input signal that is represented by a sequence of data stream is fed to an input terminal 130 of the band pass filter 100 . by responding to a synchronization clock that is connected to the shift register 101 , the input signal is shifted into the shift register 101 from the entrance end 104 . as time goes by , the input signal is moving through the shift register 101 , and leaving the shift register 101 via the exit end 106 . note that the shift register 101 always keeps a segment of the input signal as the input signal sliding through , and as time goes by , the exit end 106 register is holding a delayed copy of data in the entrance - end register 104 . by carefully choosing the length of the shift register 101 , thereby the delayed time period of the input signal occurring between the entrance end 104 and the exit end 106 of the shift register 101 , a desired frequency band is extracted from the input signal by subtracting the delayed input signal from the input signal . as a result , as depicted in fig1 an output 140 of the band pass filter 100 is obtained . the delayed time period of the input signal can be determined by the following formula : delayed time period = fs / 2fo , ( eqn . 1 ) where : fs is a sampling rate of the input signal ; and fo is a desired frequency band that needs to be extracted from the input signal . while the length of the shift register can be determined by the following formula : the number of registers need =[ fs / 2fo ]+ 1 , ( eqn . 2 ) same as in eqn . 1 , where fs , and fo represent an input signal sampling rate , and a desired frequency band respectively . note that one is added to the integer part of the ratio of fs / 2fo ; however , the number of time unit delayed between the data holding in the first and the last registers of the shift register is never changed . the delayed time units are exactly equal to the integer part of the ratio of the input signal sampling rate to two times of the target desired frequency . the delayed time units are measured by and in accordance with the shift register synchronization clock . an exercise of the first preferred embodiment of the present invention is as follows . an input signal sampling rate of 100 khz data stream is fed into the input terminal 130 of the band pass filter 100 depicted in fig1 . a desired frequency band for example centered at 12 . 5 khz is aimed to be extracted from the 100 khz sampling rate data stream . according to eqn . 2 , the number of registers need to achieve the goal is 100 khz divided by 2 ( 12 . 5 khz ) plus 1 that gives 5 registers . a shift register of 5 - register length and an arithmetic subtracter are configured as a band pass filter as demonstrated in fig1 to accomplish a band pass filter function on an input signal of 100 khz sampling rate data stream to have output results depicted in fig4 and fig5 . in fig4 the horizontal axis represents a normalized frequency band from 0 to 1 , and the vertical axis represents a magnitude of the output data in db unit . in fig4 along the horizontal axis , 1 represents a 50 khz signal that has a sampling rate of 100 khz . clearly , the target frequency 12 . 5 khz is located at 0 . 25 scale as depicted by an upright arrow in fig4 where is the passing frequency centered . the other passing frequency centered at 0 . 75 scale that is where 37 . 5 khz signal resides . instead of a single frequency band , the band pass filter extracts two frequency bands from the input signal ; one is the target frequency band , and the other is a mirror of the target frequency band . so long as an input signal doesn &# 39 ; t contain a signal frequency in a mirror of the target frequency band , the band pass filter will extract exactly a user desired frequency band from the input signal . fig5 is the band pass filter output phase diagram . [ 0034 ] fig6 and fig7 represent an output result of an iir based band pass filter depicted in fig3 . the same input signal data stream ( 100 khz sampling rate ) and the same target frequency ( 12 . 5 khz ) are applied to the iir based band pass filter . note that to a compatible result , the iir based band pass filter uses 4 multipliers , 4 adders , 2 registers , and a set of coefficients , b0 , a1 , a2 , and b2 . the values that assigned to the coefficients are b0 = 0 . 24523727525279 , a1 = 0 . 93293803467052 , a2 =− 0 . 50952544949443 , and b2 =− 0 . 24523727525279 . comparing to the compatible results , the band pass filter of the preferred embodiment of the present invention uses only a shift register of 5 - registe length , a subtracter , and no input coefficients that greatly reduces the complexity , costs , power consumption , and space required in the iir based band pass filter . there will fall into a similar case if fir based band pass filter is used as depicted in fig2 . a set of coefficients and multipliers 220 , and a set of adders 210 are not avoidable in a fir based band pass filter design . the second preferred embodiment of the present invention presents a method of obtaining a desired frequency band from an input signal as depicted in fig8 . in fig8 the method is demonstrated by a flow chart diagram ( 800 ). the method first receives the input signal based on a time frame ( 810 ). then , the method marks currently received data as a present reference ( 820 ) and records a segment of the input signal starting from the present reference and on as the input signal and time go by ( 830 ); thereby , the sequence of the recorded input signal segment provides a starting end and an ending end of the segment . finally , the method sequentially reports a difference between the starting end and the ending end of the recorded input signal segment to obtain an output of the method based on the time frame ( 840 ). the method addressed above , a length of the recorded input data segment is determined by a ratio of a half of a sampling rate of the input signal to a target desired frequency of the method . also , at a boundary condition of the method , a beginning or an ending of the method , zeros are inserted to both ends of the input data sequence . the third preferred embodiment of the present invention presents another method of obtaining a desired frequency band from an input signal . the method is depicted in a flow chat diagram as presented in fig9 . first , the method provides a number of registers coupled in cascade to form a shift register ( 910 ); thereby , a first register and a last register are identified at a data entrance end and a data exit of the shift register ( 920 ). each register has a storage capacity of at least one bit of digital data . finally , the method computes a difference of contents stored in the first register and the last register to form an output of the method in a clock frame ( 930 ). in the method addressed in the last preferred embodiment of the present invention , the number of registers is determined by adding one to an integer part of a ratio of a half of the input signal sampling rate to a target desired frequency of the method . the difference of contents stored in the first and last registers is calculated by adding a content of the first register and a negative content of the last register to form an output of the method in the clock frame . also , a register in the shift register of the method can be use to store digital data or numeric data . note that the method is feasible to be implemented by computer hardware or computer software , and the clock frame in the method is a shift register synchronization clock . it will be apparent to those skilled in the art that various modifications and variations can be made to the structure or to the methods of the present invention without departing from the scope or spirit of the invention . in view of the foregoing , it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents .