with reference to the accompanying drawings , fig1 - 3 illustrate schematic cross - sectional representations of methods of cleaning and passivating the cu surface and depositing a refractory liner with a low contact resistance in at least one via of a semiconductor device according to the invention . as shown in fig1 , there is provided a substrate 10 which may be a bulk semiconductor including , for example , si , sige , sic , sigec , gaas , inp , inas and other semiconductors , or layered semiconductors such as silicon - on - insulators ( soi ), sic - on - insulator ( sicoi ) or silicon germanium - on - insulators ( sgoi ). when the layered semiconductors are employed , the top layer of those substrates represent the top layer 10 shown in fig1 . formed on substrate 10 is a representative metal layer ( m 1 ) layer 12 which may be a patterned wiring level of conducting material such as cu , al , or alloys thereof . atop of the metal layer is a subsequently formed bottom dielectric capping layer 14 which may comprise silicon nitride ( sin ) or silicon carbide ( sic ). the formed dielectric bottom cap layer 14 may act as cu diffusion barrier layer and also an rie mask and cmp ( chemical - mechanical polishing ) polish stop layer . atop the bottom capping layer is a low - k organic or inorganic interlevel dielectric layer ( ild ) 16 of low - k dielectric material which may be deposited by any of number of well known techniques such as sputtering , spin - on , or pecvd . on top of the low - k dielectric layer is formed a top dielectric cap layer 18 comprising , for example , a hard mask layer of blok ® ( trademark of applied materials inc .) and silicon nitride , to act as a moisture barrier . blok ® is a pecvd deposited silicon carbide film . each layer may include any now known or later developed material used for the layer &# 39 ; s respective purpose . in one embodiment , for example , inorganic ild layer 16 may include a single layered low - k interlevel dielectric or multilayer dielectric structure . when a multilayered dielectric is employed as the interlevel dielectric , a buried etch stop layer may optionally be formed between the multilayered dielectrics . notwithstanding whether the interlevel dielectric is composed of a single layered dielectric or a multilayered dielectric , the interlevel dielectric employed may include a conventional spun - on organic dielectrics , spun - on inorganic dielectrics or combinations thereof which have a dielectric constant of about 3 . 5 or less . suitable organic dielectrics that can be employed in the present invention include dielectrics that comprise c , o and h . examples of some types of organic dielectrics that can be employed in the present invention include , but are not limited to : aromatic thermosetting polymeric resins , for example , resins sold by dow chemical company under the tradename silk ®, honeywell under the tradename flare @, and similar resins from other suppliers , and other like organic dielectrics . the organic dielectric employed as interlevel dielectric 16 may or may not be porous , with porous organic dielectric layers being highly preferred due to the reduced k value . when porous organic dielectrics are employed as the interlevel dielectric , the pore size of the organic dielectric is typically of from about 1 to about 50 nm at a volume percent porosity of from about 5 to about 35 %. when inorganic dielectrics are employed as the interlevel dielectric , the inorganic dielectrics typically comprise si , o and h , and optionally c , e . g ., sicoh , sioch , carbon - doped oxides ( cdo ), silicon - oxicarbides , organosilicate glasses ( osg ) deposited by plasma enhanced chemical vapor deposition ( cvd ) techniques . illustrative examples of some types of inorganic dielectrics that can be employed in the present invention include , but are not limited to : the silsesquioxane hosp ( sold by honeywell ), methylsilsesquioxane ( msq ), hydrido silsesquioxane ( hsq ), msq - hsq copolymers , tetraethylorthosilicate ( teos ), organosilanes and any other si - containing material . in the present invention , porous or non - porous inorganic dielectrics can be used as the interlevel dielectric , with porous inorganic dielectrics being more highly preferred . it should be recognized that the cap layers 14 and / or 18 may or may not be used . it should also be recognized that the material makeup of the layers may vary and not depart from the scope of the invention . in the method depicted in fig1 , a via opening pattern is defined atop cap layer 18 followed by sequential etching of a hole or trench through the top cap layer 18 , the inorganic low - k dielectric layer 16 and the bottom cap layer 14 to expose the underlying metal layer 12 to further processing ( the described embodiment assumes the case of a via formed at a hole , however , it is understood that the invention is applicable for via formation at a trench or at both a hole and trench ). such steps may include first forming a mask structure and conducting a reactive ion etch ( rie ) that provides superior interconnect depth control . then , referring to fig2 , a next step includes the implantation of nitrogen ions 22 into the via opening 20 to form a thin nitrogen implanted layer 24 in the top surface of the metal conducting layer 12 . in one embodiment , the energy used to implant the nitrogen 22 is less than 1 kev and the thickness of the resulting implanted layer 24 is less than about 5 nm . while a thin cun layer 24 is formed as a result of implanting nitrogen , it is should be understood that nitrogen may be ion implanted from a gas mixture including other atoms such as argon or helium . it is understood that conventional ion implantation techniques may be performed to implant the nitrogen ions , however other techniques such as providing a plasma of a gas mixture of nitrogen with argon or helium , or with a combination of argon and helium , or , by ion implanting performed by a plasma with rf bias or ion enhanced plasma with rf bias of between about 0 watts and about 500 watts is additionally contemplated . referring to fig3 , the next step includes the deposition of a refractory metal liner which creates a thin layer on top on the thin nitrogen implanted layer 24 , on the sidewalls of the etched via opening 20 and top of the cap layer 18 or the interlevel dielectric 20 if there is no cap layer 18 present . in one embodiment , the refractory metal liner 28 comprises a refractory material , e . g ., tantalum , tantalum nitride , chromium / chromium oxide , titanium , titanium nitride , tungsten , tungsten silicide , or the like , deposited using any of the known deposition methods , such as , for example , cvd , hollow cathode magnetron sputtering , deposit - etch ( dep .- etch ) process , or any combination of these or , other similar methods . for example , the liner material 28 may comprise a single structural compound such as tin or tan and deposited to a thickness of less than about 400 å . in an alternate embodiment , the refractory metal liner ( s ) 28 may comprise two different structural compounds such as ta / tan with thicknesses of less than about 400 å . it should be recognized that the material makeup of the metal liners 28 may vary and not depart from the scope of the invention . for example , optional liner material employed in the present invention may include any material which would prevent the diffusion of cu into the dielectric layers . some examples of such liners include , but are not limited to : tin , tan , ti , ta , w , wn , cr , nb and other like materials . the present invention also contemplates multilayer combinations of such liners . the liner material may be formed in the via utilizing conventional deposition processes well known to those skilled in the art , including : cvd , plasma - assisted cvd , sputtering , plating and chemical solution deposition . further , as known to skilled artisans , subsequent to the formation of the liner is the deposition of a plug ( usually by chemical vapor deposition or electroplating ) of conductive material , e . g ., copper or tungsten ( or alloys thereof ). the implanting of low energy nitrogen according to the invention results in the formation of a thin cun layer at the bottom of via opening 20 . the thin formed cun protects the cu via surface from undesirable contaminants such as oxygen , o , and carbon , c . it additionally improves contact via resistance and adhesion at the bottom of the via , and , further , results in a low resistance phase alpha - ta on nitride implanted cu surface without additional nitride ( such as tan or tin ) barrier layer . for instance , as demonstrated by the auger chemical depth profile analysis of an example device as shown with respect to fig4 ( a ) and 4 ( b ), the implantation of nitrogen into the metal conducting line 12 results in a cleaner metal liner 28 / metal conducting line 12 interface . the auger chemical depth profile analysis 30 depicted in fig4 ( a ) is obtained at the metal liner / metal surface interface of the contact region without the formed nitrogen implant and illustrates the resulting concentrations of c and o contamination 31 , 32 respectively , resulting from the interlevel contact formation process . this is compared to the auger chemical depth profile analysis 40 depicted in fig4 ( b ) is obtained at the metal liner / metal surface interface of the contact region with the formed cun layer and illustrates resulting concentrations of c and o contamination 41 , 42 respectively , of significantly reduced concentrations ( no peaks shown , i . e . the amount of contamination is under auger detection limit ). thus , there is manifest a lower via 20 contact resistance 50 as exemplified in fig5 for the nitrogen implanted surface of the metal conducting line 12 as compared to the via contact resistance 60 without the n implant . moreover , as a result of the passivation of the metal surface according to the invention , a lower resistance alpha phase ta ( α - ta ) is preferably formed in the metal liner 28 that increases the reliability performance of the formed interconnection structure . as known , α - ta has a body centered cubic crystal structure as compared to a beta phase ta β - ta possessing a tetragonal crystal structure and exhibiting roughly ten ( 10 ) times more sheet resistivity . thus , as shown in fig6 , there is depicted the crystalline structures 70 of a tantalum metal liner formed on the cun metal layer surface having an increased α - ta phase 75 according to the present invention as compared to a tantalum liner formed on the cu metal layer surface having a reduced α - ta phase 78 according to the prior art e . g ., implementing an argon sputter clean . as is shown in fig6 , the nitrogen enriched metal conductor cun surface enables the formation of a tantalum layer in the desired low - resistivity alpha phase , thus minimizing the resistivity of the contact . while there has been shown and described what is considered to be preferred embodiments of the invention , it will , of course , be understood that various modifications and changes in form or detail could readily be made without departing from the spirit of the invention . it is therefore intended that the invention be not limited to the exact forms described and illustrated , but should be constructed to cover all modifications that may fall within the scope of the appended claims .