fig1 is a schematic plan view of a semiconductor ic not yet packaged . in fig1 reference numeral 10 represents a chip . in and on the chip 10 , a first semiconductor ic i ( corresponding to a main - semiconductor circuit ) and a second semiconductor ic ii ( corresponding to a sub - semiconductor circuit ) are fabricated . many pads a through m , v cc , v cc * and v ss , used for the power supply , communication of i / o signals , and so on , are distributed thereon . wire bonding is performed between the pads and corresponding external pins . usually , there are 16 pins . in fig1 however , all the pins and wire bondings are not illustrated . of these members , the pads v cc and v cc * are particularly relevant to the embodiment of the present invention . the pad v cc constitutes a first power source with ground level pad v ss . the pad v cc * constitutes a second power source with ground level pad v ss . the first and second power sources drive the first and second semiconductor ic &# 39 ; s i and ii , respectively . in this case , the pads v cc and v cc * are commonly connected , through wire bondings 12 and 13 , respectively , to a single pin 11 connected to an external power source ( not shown ). the common pin is preferable in view of economical use of the fixed number of pins . the wire bonding 12 is always provided . the wire bonding 13 is provided in accordance with individual user needs , as previously mentioned . incidentally it should be understood that , in fig1 illustration of wirings between the pad v cc and the first semiconductor ic i and also wiring between the pad v cc *, is omitted for brevity . below , it will be explained how the embodiment of the present invention enables external detection of the wire bonding after the semiconductor chip is packaged . fig2 is a circuit diagram of a semiconductor circuit having a test circuit according to an embodiment of the present invention . in fig2 parts the same as fig1 are represented by the same reference numerals or characters in fig2 a block 20 indicated by chain - dotted lines represents a test circuit , a particularly important part of the present invention . the test circuit 20 is connected to the pad a , the pad v cc * and the pad v ss via newly employed lines 21 , 22 , and 23 , respectively . the pad a is just an example ; any other pad may be used instead . the pad a is connected to an external i / o pin 14 . the test circuit 20 comprises a series - connected mis transistor 24 and an mis diode 25 . the gate of the mis transistor 24 is connected to the line 22 . it should be noted that in the embodiment of the present invention , the test circuit 20 functions to detect the existence of the wire bonding 13 . from the viewpoint of the general purpose application of the present invention , however , the test circuit 20 funtions to detect the level at an internal node n under testing , in which either ground level ( v ss ) or the power source level ( v cc ) occurs at the pad v cc * ( or at the internal node n to be tested ). fig3 a is an equivalent circuit diagram of the test circuit created under a mode where the second semiconductor ic ii is active . fig3 b is an equivalent circuit diagram of the test circuit created under a mode where the second semiconductor ic ii is not active . as previously , mentioned , according to the embodiment of the present invention , the existence of the wire bonding 13 shown in fig1 is detected by way of an external i / o pin . similarly , from a general purpose point of view , the power source level or ground level occuring at the internal node n is dectected by way of the external i / o pin 14 . when the wire bonding 13 exists in the chip , the pad v cc * is activated , thereby turning on the mis transistor 24 via the line 22 . similarly , when the node n is activated at the power soruce level , the mis transistor 24 is turned on . such a mode corresponds to the equivalent circuit diagram of the test circuit shown in fig3 a . on the other hand , when the wire bonding 13 does not exist in the chip , the pad v cc * is not activated . at this time , since the pad v cc * is also connected , via a resistor having high resistance ( not shown ) to ground , the pad v cc * is set at ground level . therefore , the level of the second power source for the second semiconductor ic ii is set at ground level . accordingly , ground level is applied to the gate of the mis transistor 24 . similarly , when the node n is set at ground level , ground level is applied to the gate of the mis transistor 24 . such a mode corresponds to the equivalent circuit diagram of the test circuit shown in fig3 b . that is , the mis transistor 24 substantially forms a conductive path if the internal node n is at the power source level and substantially forms a transistor in which the gate ( g ) and drain ( d ) thereof are electrically shorted if the internal node is at ground level . the symbol s denotes a source of the mis transistor 24 . thus , the existence of the wire bonding 13 , similarly the power source level or ground level at the internal node n , can be determined by investigating whether the equivalent circuit diagram of fig3 a or fig3 b exists . the circuit modes of fig3 a and fig3 b can be distinguished by observation from the pad a . in practice , such observation is achieved via the external i / o pin 14 connected to the pad a inside of the chip . it should be noted that the pin 14 works as a test pin during a test mode , but as an i / o signal pin during a normal operation mode . in carrying out the test mode , a current is drawn from the external i / o pin 14 . under the circuit mode of fig3 a , i . e , with the wire bonding 13 or with application of the power source level to the internal node n , to draw a current requires application of a first voltage level lower than the threshold voltage v th of the mis diode 25 , to the pin 14 . thus , if a level of - v th is applied to the pin 14 and a current flows through the pin 14 , one may conclude that the circuit mode of fig3 a is created in the chip . however , under the circuit mode of fig3 b , i . e ., with no wire bonding 13 or with application of ground level to the internal node n , to draw a current requires application of a second voltage level , lower than the sum of the threshold voltages v th of the mis diode 25 and mis transistor 24 , to the pin 14 . thus , if a level of - 2v th is applied to the pin 14 and a current flows through the pin 14 , one may conclude that the circuit mode of fig3 b is created in the chip . thus , the existence of the wire bonding 13 , similarly the power source level or ground level at the internal node n , can easily be distinguished by the voltage level (- v th or - 2v th ) applied to the pin 14 . in this case , the mis diode 25 functions as a diode for preventing a flow of a reverse current to the test circuit 20 during a normal operation mode . that is , the mis diode 25 is set to a reverse biasing state during application of an ordinary i / o signal sig , indicated by a broken line arrow in fig2 from the pin 14 . as explained above , the power source level or ground level occurring at an internal node in the semiconductor ic chip can be correctly externally distinguished via the external i / o pin .