positive logic and a positive ground are utilized throughout the descriptions of fig1 , 3 , and 4 . thus a binary one is represented by ground potential and a binary zero is represented by a negative potential . referring to fig1 there is shown a phase - locked loop 10 for producing an output signal , v out , having a phase ( and therefore frequency ) locked to the phase of an input signal , v in . v out is produced by a voltage - controlled oscillator 12 wherein the frequency and phase of v out are determined by a control voltage applied to an input terminal 13 of the voltage - controlled oscillator 12 . the control voltage is provided by the selective operation of one of two feedback loops : a primary feedback loop , consisting of a first phase detector 14 , and an initialization feedback loop , consisting of a second phase detector 28 . in response to an off - frequency detector 32 which is responsive to the second phase detector 28 , a switch 34 determines which of the two feedback loops is operative to control the voltage - controlled oscillator 12 at the input terminal 13 thereof . the initialization feedback loop operates when the frequency difference between v out and v in is above a predetermined limit . the initialization feedback loop has a wide bandwidth to provide a broad capture range , i . e ., the range of frequencies over which v out can be locked to a reference frequency approximating v in . the primary feedback loop has a narrow bandwidth to provide improved noise rejection for the phase - locked loop 10 and operates when the frequency difference between v out and v in is below the predetermined limit . as can be seen in fig1 in the primary feedback loop v out is input to the first phase detector 14 . the first phase detector 14 is also responsive to v in to detect a phase difference between v out and v in . the first phase detector 14 produces a difference signal in response to the phase difference ; the difference signal is selectively input to the voltage - controlled oscillator 12 at the input terminal 13 , via the switch 34 , for controlling the frequency and phase of v out only when the difference between the frequency of v out and the frequency of v in is below the predetermined limit . operation of the switch 34 will be discussed in greater detail hereinafter . in the initialization feedback loop v out is input to the second phase detector 28 . within the second phase detector 28 , v out is input to a first mixer 16 and a delay circuit 18 . a second mixer 20 is responsive to the delay circuit 18 . the first mixer 16 and the second mixer 20 are also responsive to a first reference signal designated v ref1 . the first mixer 16 , the delay circuit 18 , and the second mixer 20 constitute the second phase detector 28 . the second phase detector 28 detects a phase difference between v out and v ref1 ; the frequency of v ref1 is approximately equal to the frequency of v in . the second phase detector 28 produces a signal v e1 ( see fig1 ) representative of the difference between the frequency of v ref1 and the frequency of v out . v e1 is selectively input to the voltage - controlled oscillator 12 at the input terminal 13 , via the switch 34 , for controlling the frequency and phase of v out when the disparity between the frequency of v out and the frequency of v ref1 is above the predetermined limit . the operation of the second phase detector 28 is as follows . the first mixer 16 determines the frequency difference between v ref1 and v out and produces the first error signal , v e1 , representative of the frequency difference between the mixed signals . the delay circuit 18 , which is responsive to v out , slightly delays and inverts v out . the delayed and inverted v out signal and v ref1 are mixed in the second mixer 20 producing a second error signal , v e2 , representative of the frequency difference between the mixed signals . the signals v e1 and v e2 are both low frequency slightly distorted sine waves representative of the frequency difference between v ref1 and v out . v e2 is approximately 180 degrees out of phase with v e1 . v e1 and v e2 are illustrated in fig3 . in one embodiment of the present invention v in has a frequency close to 5 . 2 mhz ; v ref1 has an extremely precise frequency of 5 . 2 mhz . also , note that the delay circuit 18 functions solely to impart a phase difference and inversion between v e1 and v e2 . therefore , in another embodiment the delay circuit 18 can be repositioned such that v ref1 is input thereto and the first mixer 16 is responsive to the output of the delay circuit 18 . in this embodiment the second mixer 20 is responsive to v out . continuing with a description of the off - frequency detector 32 in fig1 a level detector 36 is responsive to v e1 and produces a square wave signal v sq1 ; a level detector 38 is responsive to v e2 and produces a square wave signal v sq2 . v sq1 and v sq2 are combined in a logic circuit 40 which produces two output signals , v l1 and v l2 . the level detectors 36 and 38 and the logic circuit 40 constitute a logic means 41 . an inverting set input terminal of a flip - flop 42 is responsive to v l1 ; an inverting reset input terminal of the flip - flop 42 is responsive to v l2 . the flip - flop 42 produces a square wave designated v ff . v ff is input to a differentiator / rectifier 43 . an integrator 44 is responsive to an output terminal of the differentiator / rectifier 43 , and a schmitt trigger 46 is responsive to an output terminal of the integrator 44 . the schmitt trigger 46 produces the switching signal , v sw , for controlling the switch 34 . the differentiator / rectifier 43 and the integrator 44 constitute a frequency detector 45 . the level detectors 36 and 38 , the logic circuit 40 , the flip - flop 42 , the differentiator / rectifier 43 , the integrator 44 , and the schmitt trigger 42 constitute the off - frequency detector 32 . operation of the off - frequency detector 32 is as follows . the level detector 36 converts the sine wave signal v e1 to a square wave signal v sq1 . v sq1 may have chatter on the leading and trailing edges of each pulse if v out is distorted by phase jitter . the phase jitter is present when v in is noisy . both signals v e1 and v sq1 are illustrated in fig3 . the level detector 38 produces a square wave signal v sq2 in response to v e2 . like v sq1 , v sq2 may have jitter on the leading and trailing edges of each pulse ; v sq2 is also shown in the fig3 timing diagram . the phase difference between v e1 and v e2 in maintained in processing through the level detectors 36 and 38 , but the inverse relationship is lost . therefore , v sq1 is only slightly out of phase with v sq2 . as discussed above , the chatter associated with the pulses of v sq1 and v sq2 can cause improper operation of the off - frequency detector 32 by causing the switching signal v sw to change states incorrectly . for example , the chatter can cause activation of the initialization loop , and deactivation of the primary loop when v out is already synchronized with v in . the logic circuit 40 and the flip - flop 40 eliminate this problem . within the logic circuit 40 , v l1 and v l2 are produced by arithmetic operations on v sq1 and v sq2 . v l1 is the logical sum of v sq2 and the inverse of v sq1 . v l1 is present at the first output terminal of logic circuit 40 and input to the inverting set input terminal of the flip - flop 42 . v l2 is the logical sum of v sq1 and the inverse of v sq2 . v l2 is provided at the second output terminal of logic circuit 40 and input to the inverting reset terminal of the flip - flop 42 . both v l1 and v l2 are shown in fig3 . through the action of the flip - flop 42 , v l1 and v l2 are converted to a square wave signal ( v ff ) having no chatter on either the leading or the trailing edges . see fig3 . once a transition of v ff has occurred , v ff cannot make a subsequent transition unless v out undergoes an additional 180 ° phase shift ( either plus or minus ). phase jitter on v out , induced by leading - edge and trailing - edge chatter in v sq1 and v sq2 has , therefore , been eliminated because it is unlikely v out will contain jitter components with magnitude sufficient to cause a 180 ° phase shift . the frequency of v ff represents the difference between the frequency of v out and the frequency of v ref1 . in response to v ff the differentiator / rectifier 43 produces a current pulse for each positive transition of v ff ; the integrator 44 integrates the current pulses . the integrator 44 is a frequency - to - voltage converter circuit that is insensitive to noise because the integrator 44 integrates over a long period . occasional false transitions in v ff do not significantly contribute to the long - term average and will therefore not cause erroneous state changes in v sw . an output signal of the integrator 44 is input to the schmitt trigger 46 . when the output signal of the integrator 44 exceeds the trip voltage threshold of the schmitt trigger 46 v sw goes high . when the frequency of v out is made equal to the frequency of v ref1 the output signal of the integrator 44 is below the trip threshold of the schmitt trigger 46 and v sw will fall to a low state . a first input terminal of the switch 34 is responsive to v e1 . a second input terminal of the switch 34 is responsive to the output signal from the first phase detector 14 . an output terminal of the switch 34 is selectively responsive to v e1 and the output signal from the first phase detector 14 . the input terminal 13 of the voltage - controlled oscillator 12 is responsive to the output terminal of the switch 34 . the switching signal , v sw , produced by the off - frequency detector 32 and input to the switch 34 at a third input terminal thereof determines which of the two input signals to the switch 34 is connected to the output terminal thereof . when v sw is in the high state the first input terminal ( i . e ., v e1 ) of the switch 34 is connected to the output terminal thereof . the high state of v sw indicates a divergence between the frequency of v out and the frequency of v ref1 in excess of the predetermined limit . this causes the initialization feedback loop to be operative . in this mode v e1 is input to the voltage controlled oscillator 12 , via the switch 34 , to equalize the frequency of v out to the frequency of v ref1 . when v sw is in the low state the second input terminal ( i . e ., the output signal from the first phase detector 14 ) of the switch 34 is connected to the output terminal thereof . the low state of v sw indicates that the frequency of v out equals the frequency of v ref1 such that the primary feedback loop can be activated to precisely synchronize v out with v in . now , the output signal from the first phase detector 14 is input to the voltage - controlled oscillator 12 , via the switch 34 , to perform the synchronization of v out with v in . in another embodiment of the present invention the output signal of the first phase detector 14 can be permanently connected to the voltage - controlled oscillator 12 . because the output signal of the first phase detector 14 is at a lower level than v e1 , the former does not interfere with the initialization process . in this embodiment the switch 34 is utilized only to connect and disconnect v e1 from the input terminal 13 of the voltage - controlled oscillator 12 . turning to fig2 there is shown a second embodiment of a phase - locked loop 10 constructed according to the teachings of the present invention . the components of fig2 are identical in structure and function to the components bearing identical reference characters in fig1 . the embodiment of fig2 includes a signal processing circuit 15 disposed between the voltage controlled oscillator 12 and the first mixer 16 . a third mixer 22 is disposed between the first mixer 16 and the level detector 36 ; a fourth mixer 24 is disposed between the second mixer 20 and the level detector 38 . a frequency divider 26 is also responsive to v ref1 for producing a second reference signal designated v ref2 . in the embodiment of fig2 the signal processing circuit 15 , the first mixer 16 , the third mixer 22 , the delay circuit 18 , the second mixer 20 , the fourth mixer 24 , and the frequency divider 26 constitute the second phase detector 28 . the second phase detector 28 detects a phase difference between v out and v ref1 plus v ref2 ; the frequency of v ref1 plus the frequency of v ref2 is approximately equal to the frequency of v in . the second phase detector 28 produces the signal v e1 representative of the difference between the frequency of v ref1 l plus the frequency of v ref2 and the frequency of v out . like the embodiment of fig1 signal v e1 is selectively input to the voltage - controlled oscillator 12 at the input terminal 13 , via the switch 34 , for controlling the frequency and phase of v out when the disparity between the frequency of v out and the frequency of v ref1 plus the frequency of v ref2 is above the predetermined limit . note that the embodiment of fig2 utilizes four mixers , rather than two mixers as shown in the fig1 embodiment . this is due to the availability of an extremely precise frequency of 5 mhz for v ref1 when v in is approximately 5 . 2 mhz . v ref2 is obtained by dividing v ref1 by twenty - five ( in the frequency divider 26 ) producing v ref2 with a frequency of 200 khz . thus , the frequency of v ref1 plus v ref2 equals v in . the mixing of v out and the reference signal is performed in two stages ( i . e ., the first stage consisting of the first mixer 16 and the second mixer 20 , the second stage consisting of the third mixer 26 and the fourth mixer 24 ) due to the availability of an extremely accurate 5 mhz source . the result obtained is identical to mixing v in with a signal of 5 . 2 mhz in a single mixing stage . in other embodiments , more than two mixing stages or a single mixing stage ( see fig1 ) may be used depending on the frequencies involved and the availability of accurate frequency sources . the operation of the second phase detector 28 , as depicted in fig2 is as follows . note first that the frequency of v ref1 is divided by the frequency divider 26 to produce v ref2 . the first mixer 16 determines the frequency difference between v ref1 and v out and produces an output signal representative thereof . in the third mixer 22 , v ref2 and the output signal from the first mixer 16 are mixed to produce the first error signal , v e1 , representative of the frequency difference between the mixed signals . the delay circuit 18 , slightly delays and inverts v out . the delayed and inverted v out signal and v ref1 are mixed in the second mixer 20 producing an output signal representative of the frequency difference between the mixed signals . the fourth mixer 24 produces a second error signal , v e2 , representative of the difference between the frequency of the signal from the second mixer 20 and v ref2 . the signals v e1 and v e2 are both low frequencies slightly distorted sine waves representative of the frequency difference between v ref1 pus v . sub . ref2 and v out . v e2 is approximately 180 ° out of phase with v e1 . v e1 and v e2 are illustrated in fig3 . from this point , operation of the phase - locked loop 10 of fig2 is identical to that described in conjunction with fig1 . turning now to fig4 there is shown a schematic diagram of the second phase detector 28 ( as illustrated in fig2 ) and the off - frequency detector 32 . a first terminal of a capacitor 48 is responsive to v out ; a second terminal of the capacitor 48 is connected to an input terminal of an inverter 50 . an output terminal of the inverter 50 is connected to an input terminal of an inverter 56 via a capacitor 54 . the output terminal of the inverter 50 is also connected to the input terminal thereof via a resistor 52 . an output terminal of the inverter 56 is connected to an input terminal of an inverter 60 . the output terminal of the inverter 56 is also connected to the input terminal thereof via a resistor 58 . the inverters 50 , 56 and 60 , and the associated resistors and capacitors constitute the signal processing circuit 15 of the second phase detector 28 . the signal processing circuit 15 converts the analog signal v out to a digital signal suitable for processing through the digital circuitry of the phase - locked loop 10 . an output terminal of the inverter 60 is connected to an input terminal of an inverter 62 . the inverter 62 , which constitutes the delay circuit 18 , not only delays v out , but also inverts v out . the result , as previously noted , is that v e2 is approximately 180 degrees out of phase with v e1 . as will be explained subsequently , a re - invention occurs within the level detector 38 to impart the proper polarity relationship to v sq1 and v sq2 . the output terminal of the inverter 60 is connected to a first input terminal of an exclusive or gate 64 . a second input terminal of the exclusive or gate 64 is responsive to the first reference signal v ref1 . the exclusive or gate 64 constitutes the first mixer 16 . an output terminal of the inverter 62 is connected to a first input terminal of an exclusive or gate 66 ; a second input terminal of the exclusive or gate 66 is responsive to v ref1 . the exclusive or gate 66 constitutes the second mixer 20 of the second phase detector 28 . since the output signal of an exclusive or gate is a binary one only if the input signals are unequal , an exclusive or gate can be utilized as a detector whereby the exclusive or gate output signal &# 39 ; s frequency equals the difference between the frequencies of the signals at the input terminals thereof . exclusive or gates 64 and 66 are used in this manner . an output terminal of the exclusive or gate 64 is connected to a first input terminal of an exclusive or gate 68 . a second input terminal of the exclusive or gate 68 is responsive to v ref2 , produced by the frequency divider 26 . an output terminal of the exclusive or gate 66 is connected to a first input terminal of an exclusive or gate 70 . a second input terminal of the exclusive or gate 70 is responsive to v ref2 . exclusive or gates 68 and 70 also function as frequency detectors . an output terminal of the exclusive or gate 68 is connected to a non - inverting input terminal of an operational amplifier 88 via a series combination of a resistor 72 and a resistor 74 . an output terminal of the excusive or gate 70 is connected to an inverting input terminal of an operational amplifier 90 via a series combination of a resistor 84 and a resistor 86 . the junction between the resistor 72 and the resistor 74 is connected to ground via a capacitor 76 ; the junction between the resistor 84 and the resistor 86 is also connected to ground via a capacitor 80 . the junction between resistor 74 and the non - inverting input terminal of the operational amplifier 88 is connected to ground via a capacitor 78 ; the junction between the resistor 86 and the inverting input terminal of the operational amplifier 90 is connected to ground via a capacitor 82 . the exclusive or gate 68 and the resistors and capacitors associated therewith constitute the third mixer 22 . the exclusive or gate 70 with the associated resistors and capacitors constitute the fourth mixer 24 . note that the signal supplied to the non - inverting input terminal of the operational amplifier 88 is v e1 discussed in conjunction with fig1 and 2 , and the signal applied to the inverting input terminal of the operational amplifier 90 is v e2 discussed in conjunction with fig1 and 2 . since v e2 is applied to the inverting input terminal of the operational amplifier 90 and v e1 is applied to the non - inverting input terminal of the operational amplifier 88 , v e2 is inverted with respect to v e1 . this inversion compensates for the previously discussed inversion associated with the inverter 62 ( i . e ., the delay circuit 18 ). an inverting input terminal of the operational amplifier 88 is connected to a power supply voltage v s via a resistor 92 and connected to ground via a resistor 94 . the junction between the resistor 94 and the inverting input terminal of the operational amplifier 88 is connected to a non - inverting input terminal of the operational amplifier 90 . the operational amplifier 88 and the resistor associated therewith constitute the level detector 36 . the level detector 38 is comprised of the operational amplifier 90 and the resistor 94 . the signal v sq1 is present at an output terminal of the operational amplifier 88 ; a first input terminal of a nand gate 96 is responsive to v sq1 . a second input terminal of the nand gate 96 is connected to ground . the first input terminal of the nand gate 96 is also connected to ground via a resistor 100 and is connected to an anode terminal of a diode 108 . the operational amplifier 90 produces a signal v sq2 at an output terminal thereof . a first input terminal of a nand gate 98 is responsive to v sq2 . a second input terminal of the nand gate 98 is connected to ground . the first input terminal of the nand gate 98 is also connected to ground via a resistor 102 and is connected to an anode terminal of a diode 106 . an output terminal of the nand gate 96 is connected to an anode terminal of a diode 104 ; a cathode terminal of the diode 104 is connected to a cathode terminal of the diode 106 . an output terminal of the nand gate 98 is connected to an anode terminal of a diode 110 ; a cathode terminal of the diode 110 is connected to a cathode terminal of the diode 108 . the junction between the diodes 104 and 106 is connected to the power supply voltage v s via a resistor 112 . a junction between the diodes 108 and 110 is connected to the power supply voltage v s via a resistor 114 . the nand gates 96 and 98 , the diodes 104 , 106 , 108 , and 110 , and the associated resistors constitute the logic circuit 40 of the off - frequency detector 32 . the signal at the junction between the diodes 104 and 106 is referred to as v l1 in fig1 and 2 . the signal at the junction between the diodes 108 and 110 is referred to as v l2 in fig1 and 2 . a first input terminal of a nand gate 116 is responsive to v l1 , and a first input terminal of a nand gate 118 is responsive to v l2 . a second input terminal of the nand gate 116 is connected to an output terminal of the nand gate 118 . a second input terminal of the nand gate 118 is connected to an output terminal of the nand gate 116 . the nand gates 116 and 118 constitute the flip - flop 42 of the off - frequency detector 32 . the first input terminal of the nand gate 116 is referred to as the inverting set input terminal of the flip - flop 42 in fig1 and 2 ; the first input terminal of the nand gate 118 is referred to as the inverting reset input terminal of the flip - flop 42 in fig1 and 2 . the signal at the output terminal of the nand gate 116 is designated v ff in fig1 and 2 . a first terminal of capacitor 120 is responsive to v ff . a second terminal of the capacitor 120 is connected to the power supply voltage v s via a parallel combination of a resistor 122 and a diode 124 such that the cathode terminal of the diode 124 is connected to the power supply voltage v s . the second terminal of the capacitor 120 is also connected to a base terminal of a transistor 126 . a collector terminal of the transistor 126 is connected to the power supply voltage v s via a resistor 128 . an emitter terminal of the transistor 126 is connected to ground via a parallel combination of a capacitor 130 and a resistor 132 . the capacitor 120 , the resistor 122 and the diode 124 constitute the differentiator / rectifier 43 ; the transistor 126 and the associated resistors and capacitor constitute the integrator 44 . the emitter terminal of the transistor 126 is also connected to an inverting input terminal of an operational amplifier 134 . a non - inverting input terminal of the operational amplifier 134 is connected to ground via a resistor 140 and is connected to the power supply voltage v s via a resistor 136 . an output terminal of the operational amplifier 134 is connected to the non - inverting input terminal thereof via a resistor 138 . the switching signal v sw discussed in detail in conjunction with fig1 and 2 is provided at the output terminal of the operational amplifier 134 . the schmitt trigger 46 of the off - frequency detector 32 comprises the operational amplifier 134 and the associated resistors . as discussed in conjunction with fig2 when the output terminal of the operational amplifier 134 is in a high state , the initialization feedback loop is operative to equalize the frequency of v out to the sum of the frequencies of v ref1 plus v ref2 . when the output terminal of the operational amplifier 134 is in a low state , the primary feedback loop will be operative to precisely synchronize the phase of v out to the phase of v in .