referring to fig1 the amplifier is designed for driving a horizontal deflection yoke . the circuit includes an input network 2 , an amplifier 4 , a semiconductor switch 6 , a current feedback network 8 and a damping network 10 . the input network 2 conducts current signals from input terminal a to the summing junction 12 of amplifier 4 . resistor r1 conducts a ± d . c . reference to adjust the d . c . bias current in the load . resistor r2 and a capacitor c1 conduct the deflection signal from the deflection signal generator to the summing junctions of the amplifier . the deflection signal , in the case of a crt circuit , is the horizontal deflection signal for a television monitor . any desired correction terms , for example , to correct for geometric distortion in the display tube , can be included in the input signal . if the input signal contains no unwanted d . c . bias voltages , capacitor c1 can be eliminated , and resistor r2 connected directly to the input signal . the amplifier 4 provides both current and voltage gain to the load in response to the current conducted through the input network , and controlled by the current from the load current feedback network and the damping network . the input signal current is applied to the inverting input 14 of integrated amplifier a 1 . integrated amplifier a 1 is an integrated circuit , wide band , amplifier which provides high open loop voltage gain such as model no . nh0024 by national semiconductor or model no . ha2520 by harris semiconductor . the noninverting input 16 of integrated amplifier a 1 is connected to signal ground through resistor r5 , providing a d . c . reference for the amplifier . the + 15v and - 15v power for the amplifier is filtered by conventional means ( not shown ). further filtering is provided by capacitor c2 and capacitor c3 which are connected to the power supply at integrated circuit a 1 . capacitor c8 is used to stabilize integrated circuit a 1 , and is adjusted to prevent oscillation . the output of integrated circuit a 1 is coupled to a unity gain noninverting power stage consisting of transistors q1 , q2 , q3 , q4 and q5 . the output of the power amplifier is coupled through junction 18 to the semiconductor switch 6 . the semiconductor switch 6 consists of high voltage transistors q7 and q8 , base bias resistor r11 , coupling capacitor c6 and inductor l2 . the a . c . component of the output signal is coupled through capacitor c6 , while the d . c . bias current is coupled through inductor l2 . the voltage reference 20 consists of a 12 volt zener diode , vr 1 , resistor r10 and diode cr4 and transistor q6 . the output of voltage reference 20 is a nominal 11 . 4 volts , but is not critical as long as transistors q7 and q8 can be reverse - biased by the amplifier and the reverse base - emitter voltage rating of q7 and q8 is not exceeded . the diode cr4 permits rapid charge removal from the bases of transistors q7 and q8 . the inductor l3 provides the stored energy to reverse the load current during the retrace time . the resistor r12 is a necessary part of the circuit , since the current in inductor l3 does not go to zero . the d . c . component of current results in a voltage drop across resistor r12 . the voltage applied to resistor r12 can be adjusted for the most optimum level . too little voltage will not provide enough current through inductor l3 to reverse the load current in load l1 during retrace . too much voltage will not affect circuit operation , but will result in excessive power loss in resistor r12 . the load l1 is any desired inductive element , for example , a deflection yoke for a crt tube . the inductance of inductance l3 is small compared with the inductance of inductor l2 but large compared with the inductance of load l1 . the current feedback path consists of a sensing resistor , r15 , which develops a voltage drop , and resistor r14 which couples the current back to the summing junction 14 of the amplifier . capacitor c5 provides stability . the damping network consists of diode cr5 , potentiometer r16 , capacitor c7 and resistor r13 . only enough damping current is fed back to the summing junction to prevent instability . the diode cr5 , blocks the damping feedback voltage during retrace but conducts during the active scan time since the amplifier output is positive during retrace and negative during the active scan time . the d . c . term is coupled through the amplifier 4 , through inductor l2 and is monitored across resistor r15 . the a . c . input term shown in fig2 a consists of a long linear ramp ( scan time ) and a relatively short voltage ramp ( retrace time ). since the amplifier is an inverting amplifier , the a . c . term monitored by resistor r15 , as shown in fig2 d is the inverse of the input term . at time t o , the input voltage signal from input network 2 to the summing junction 12 of amplifier 4 switches from a positive going ramp to a negative going ramp . this causes the output of amplifier 4 at terminal 18 , shown in fig2 b , to go positive almost instantaneously to the value determined by the threashold voltage of transistor q7 and q5 . current is conducted to the output terminal 18 of amplifier 4 by two paths . the first path is from the plus terminal through resistor r12 , inductor l3 , transistor q7 and transistor q8 to terminal 18 . in the second path , the d . c . component is conducted from the ground terminal through resistor r15 , inductor l1 and inductor l2 to terminal 18 of the amplifier while the a . c . component is conducted from the ground terminal through resistor r15 , inductor l1 , capacitor c6 , transistor q7 and transistor q8 to terminal 18 of the amplifier . the output voltage of amplifier 4 continues to rise slowly until it is equal to the constant voltage applied to the bases of transistors q7 and q8 minus the internal voltage drop of these transistors . when this occurs , at time t 1 , transistor q7 and q8 are turned off , thus blocking the two current paths to terminal 18 of amplifier 4 . this causes inductor l3 to generate an inductive voltage surge of several hundred volts . the load l1 also attempts to generate a voltage surge but this voltage surge is overcome and reversed by the voltage surge of inductor l3 because the inductance of inductor l3 is very large compared to the inductance of load l1 . the resulting voltage at terminal 19 is shown in fig2 c . the induced voltage of inductor l3 decays until it reaches zero volts at time t 2 . since the amplifier 4 is still attempting to maintain a constant rate of change of current through load l1 and resistor 15 , the output of amplifier 4 almost instantaneously goes negative at time t 2 . the output of amplifier 4 stays negative until time t 3 when the cycle is repeated . fig2 e shows the resulting voltage load l1 during times t 2 to t 3 with a linear scan input . the applied voltage slope changes to maintain a constant rate of current change as the inductance of l1 varies during the cycle . in the foregoing description it will be seen that the present invention provides an improved closed loop horizontal deflection amplifier . as will be appreciated by those skilled in the art , various modifications , omissions and additions may be used in the present invention without departing from the scope thereof . accordingly , it is to be understood that the invention shall be limited only by the following claims .