the detailed description of this invention is given in the context of a data transfer system that supports both non - isochronous and isochronous communication . the description provided herein therefore enables a discussion of the invention in network systems employed for : 1 ) transfers between a non - isochronous source and non - isochronous sink connected to the same hub ; and 2 ) transfers between an isochronous source and an isochronous sink connected to the same hub . the description therefore illustrates several of the more common situations in which the invention might be used . pending application ser . no . 07 / 969 , 916 , attorney docket no . 8332 - 314 / ns2023 , titled &# 34 ; network for data communication with isochronous capability &# 34 ;, filed the same day herein and incorporated by reference , describes a data communication system for isochronous data that can be configured in a star - topology and interconnected in a ring or tree topology . such a system is shown in fig2 a , 2b or 2c . in the configuration depicted in fig2 a , the hubs are connected in a ring - topology with first hub 44a sending data to the second hub 44b , the second hub 44b sending data to the third hub 44c , the third hub sending data back to the first hub 44a via a cycle generator and latency adjustment circuitry . the inter - hub connections over a time slot interchange ( tsi ) ring 58f . in one embodiment , an fddi - ii system can be used as the tsi ring 58f . fig2 b shows hubs 44a , 44b and 44c arranged in a star and ring topology having multiple isochronous circuitry within a single hub . fig2 c shows a tree topology communication system . the parent hub 44a connects to a high bandwidth backbone . hub 44b operates as a child hub of parent hub 44a and is attached at port 2 of hub 44a . child hub 44a cascades from child hub 44b . the star and ring topology includes a plurality of nodes 42a , 42b , 42c attached to a single hub operating on the high bandwidth bus . the exact number of nodes varies depending on the data transmission needs and objectives of the system . each of the nodes 42a - 42c can include various types of sources and sinks such as strictly isochronous sources and sinks , strictly non - isochronous sources / sinks or both isochronous and non - isochronous sources and sinks . data links comprising physical data transmission media , such as one - way twisted pair wires 46 , couple each node to one of hubs 44a - 44c . fig3 shows hub 44a and associated nodes 42a - 42c in greater detail . fig3 may , by itself , form a complete star topology system . each node 42a , 42b , 42c includes circuitry 50a , 50b , 50c . circuitry 50a - c receives data , for conversion to a form suitable for transmission onto the physical media 46a , 46c , 46e ; and receives signals from the physical media 46b , 46d , 46f for conversion to a form suitable for use by the data sinks . hub 44a includes circuitry 54a , 54b , 54c for receiving data from the physical media 46a , 46c , 46e ; separating the isochronous - sourced data from the non - isochronous - sourced data and the d channel and maintenance channel data ; and converting separated data into a form suitable for handling by downstream hub circuitry 56 . in the depicted embodiment the separated isochronous - sourced data is provided to isochronous switching circuitry such as a time slot interchange controller 58 for placing the data on a tsi bus so that it can be transported to and retrieved by other equivalent circuitry 54a - 54c in the hub for transmission to various destination nodes 42a - 42c to other hubs . the separated non - isochronous data is provided to circuitry 60 configured to convey the non - isochronous data for transmission to destination nodes 42a , 42b , 42c . in an embodiment in which non - isochronous - sourced data includes ethernet data , the hub circuitry 60 can be a standard ethernet repeater processor . in this way , the system can be at least partially backwards - compatible with previous ethernet hub systems . the d channel and maintenance data is provided to a signaling processor 62 . signaling processor 62 performs various maintenance and control functions such as identifying and alerting users of error conditions , and setting up requested connections , i . e . source / destination paths e . g . by communicating with the isochronous and non - isochronous controllers 58 , 60 , e . g . over data path 64 . the operation of the components described above may be understood by describing the transfer of data from video camera , isochronous source , 48d to isochronous sink 48b and from ethernet mac , non - isochronous source 48c to non - isochronous sink 48g . data sent from isochronous device 48d is a continuous stream of digitized data having , for example , a rate equal to the american &# 34 ; t1 &# 34 ; standard of 1 . 544m6ps . data output from the ethernet mac 48c is provided at the standard 10base - t ethernet rate of 10 mb / sec . d channel information is provided from a d channel data stream source preferably contained in a mac or other circuitry in the system , or for example , from the virtual key pad 48f at a variable data rate , such as a rate not exceeding about 64 kb / sec . lines 66a , 66b , 66c carry the data streams from sources 48d and 48c to node circuitry 50b . fig4 shows circuitry 50b in greater detail . node circuitry 50b comprises hardware that operates on the incoming data stream to enable efficient , compatible transmission between the data source and destination . a multiplexer 70 time - division multiplexes the incoming data on a four - bit basis using a repeating series of frames or templates . in this embodiment , the frames are repeated every 125 micro seconds . table i tabulates a scheme for time division multiplexing the various data streams , additional data and control bytes . each symbol in table i represents four bits of data and therefore every group of two symbols represents one 8 - bit byte of data . in table i , e represents four bits of data from the ethernet stream 66a , b designates four bits of data from the isochronous stream 66b and d represents four bits of data from the d channel stream 66c . m represents m channel data , which preferably is provided by circuitry 50b . in addition , certain byte - length patterns are provided . jk represents a frame synchronization pattern and em ( the first two bytes of block three in table i ) represents an ethernet &# 34 ; pad &# 34 ; followed by a maintenance byte . as seen in table i , each frame contains 256 bytes which can be considered in thirty - two groups of eight bytes each , or four blocks of sixty - four bytes each . for a data rate output from the isochronous source 48d of 1 . 544 mb / sec . the frame structure described provides an isochronous bandwidth capability of 6 . 144 mb / sec . thus , the single isochronous source 48b in the present example can be entirely accommodated using only 48 of the 192 &# 34 ; b &# 34 ; symbols per frame . a basic rate isdn channel could be supported by using three 64 kb / s slots within the isochronous channel . thus , a variety of isochronous sources may be allocated among the available isochronous bandwidth . the frame structure is described more thoroughly in commonly - assigned application ser . no . 07 / 969 , 911 ( attorney file no . 8332 - 315 / ns - 2024 ), titled &# 34 ; network for transmitting isochronous - source data with a frame structure &# 34 ; filed on even date herewith and incorporated herein by reference . frame structures other than that described could be used to provide an allocation of bandwidth suited for the particular purpose . the time - multiplexed data is then encoded by an encoder 72 to maintain the ac balance of the cable which can be potentially upset by an extended string of binary zeros . in the depicted embodiment , the encoder performs four / five encoding . one particular form of four / five encoding , conforming partially to the ansii x3t9 . 5 standard , is described by table ii . these patterns , when properly combined , have a maximum of three bit times with no transition . the encoding scheme depicted in table ii is described in greater detail in commonly - assigned application ser . no . 07 / 970 , 329 ( attorney file no . 8332 - 316 / ns - 2022 ), titled &# 34 ; frame - based transmission of data &# 34 ; filed on even date herewith and incorporated herein by reference . the results of the four / five encoding is then further encoded by encoder 74 of fig4 using a non - return to zero , inverted ( nrzi ) scheme . the four / five - nrzi encoding is particularly useful in networks in which a non - isochronous source is a 10base - t ethernet source because the encoding provides for transmission at a signaling rate substantially compatible with the data rates provided and expected by the ethernet mac . other types of encoding or decoding , however , can also be used such as a scheme encoding 8 bits into 10 bits . after encoding , the data is sent to pre - emphasis circuitry 76 and to a transmitter or driver 78b . pre - emphasis circuitry 76 compensates the signal transmitted onto the physical medium to reduce jitter . the signal is then transmitted over the physical medium 46c to hub 44a which can include twisted pair , coaxial or fiber optic cable . hub 44a as seen in fig3 comprises a plurality of circuit devices 54a , 54b , 54c , each one coupled to one of nodes 42a , 42b , 42c by physical media 46 . as depicted in fig5 the data transmitted over the physical media 46 arrives serially at a de - serializer / decoder 80 . de - serializer / decoder 80 includes circuitry which is functionally an inverse of the multiplexing / encoding circuitry described above and operates to decode the four / five nrzi encoding and to separate the isochronous and non - isochronous sourced data . de - serializer / decoder 80 also outputs a synchronization signal , derived from the jk frame synchronization symbols 96 for use by a framing timing generator 98 . link detect circuitry 82 also receives the data from the physical media 46 for detection of the mode in which the node is operating ( e . g . 10base - t , isochronous ethernet or isochronous ) and outputting a mode select signal , as described more fully in commonly - assigned application ser . no . 07 / 971 , 018 ( attorney file no . 8332 - 319 / ns - 2027 , titled &# 34 ; network link endpoint capability detection ,&# 34 ; filed on even date herewith and incorporated herein by reference .) both the non - isochronous - sourced data 94b and the isochronous - sourced data 94a are made available to the various hub circuitry components 54a , 54b , 54c , as needed for transmission to destination nodes . in one embodiment , the separated isochronous data 94a and non - isochronous data 94b are reconfigured by the respective interfaces 58 , 60 to provide isochronous output 102 and non - isochronous output 104 in a form suitable for transmission to the destination nodes . in one embodiment , the non - isochronous data 94b is configured by the e interface 60 so that the output data 104 can be processed by a repeater device for provision to hub circuitry 54 and eventual transmission to destination nodes . as an alternative to using a repeater for the non - isochronous data , packet connections may be linked through media access control layer bridges . fig6 depicts one implementation of an e interface 59 of a type which will receive the non - isochronous data 94b and provide outputs 106 , 108 of a type that can be processed by previously - available repeater circuitry 60 . the non - isochronous data is received in a first - in - first - out ( fifo ) buffer 112 to smooth out data rates . circuitry 114 detects &# 34 ; no carrier &# 34 ; symbols , provided to emulate ethernet data packets , used by logic circuitry or state machine 116 to output carrier detect signals . the output 118 from fifo 112 is provided to a multiplexer 120 and a de - serializer 122 to produce data output 106 . multiplexer 120 can receive a preamble stream 124 to provide the proper preamble bits in the output data 106 . output 118 from fifo 112 is also provided to decode circuitry 128 to recognize data collision and alignment error symbols and output appropriate signals 130 , 132 to state machine 116 . operation and components of the receive interface 59 are described more thoroughly in application ser . no . 07 / 970 , 329 ( attorney file no . 8332 - 316 / ns - 2022 ), titled &# 34 ; frame - based transmission of data &# 34 ;. for purposes of the present example , data from isochronous - source 48d ( fig7 ) is assumed transmitted in the first 24 isochronous bytes of each frame represented by the &# 34 ; b &# 34 ; symbols in block 0 of table i ( i . e . the first forty - eight &# 34 ; b &# 34 ; symbols in the frame structure ). fig5 depicts a b interface 58 according to one embodiment of the invention . in the embodiment of fig7 the separated isochronous data 94a is stored in one of two buffers 132a , 132b . the timing of storage in the buffers 132a , 132b is coordinated with the 125 microsecond frame transmission timing so that data 94a from a first frame will be stored in the first buffer 132a during a first period of 125 microseconds and , during the next 125 microsecond period , the isochronous data 94a from the next frame will be stored in the second buffer 132b . in one embodiment , the data can be stored in the buffer 132 in the same order it is received , such that the eight bits represented by the first two &# 34 ; b &# 34 ; symbols in table i is stored in the first storage location of buffer 132a , that corresponding to the second two &# 34 ; b &# 34 ; symbols in table i is stored in the second location of buffer 132a and so on . since the frame structure depicted in table i contains 96 bytes of isochronous data per frame , each of the buffers 132a , 132b has the capacity to store 96 bytes of data per node supported . after isochronous data from a first frame is stored in buffer 132 , during the next 125 microsecond period ( while the data from the next frame is being stored in the second buffer 132b ) data which was stored in the first buffer 132a may be transmitted onto a high bandwidth bus 134 . the loading and ordering of the buffer 132 is dependent upon the number of nodes supported by hub 44a . bus 134 has sufficient bandwidth to carry the isochronous data output from a plurality of nodes which are connected to the hub 44a . in an embodiment in which the hub 44a is connected to 16 nodes , the bandwidth of the bus 134 must be sufficient to receive 1 . 536 bytes of data ( i . e . 16 nodes × 96 bytes per node ) every 125 microseconds ( i . e . every frame ). this corresponds to a bandwidth of about 98304 kb / sec . depending upon aspects of the system configuration , such as the number of nodes attached to a hub and the bandwidth dedicated to isochronous data , other embodiments of the invention could be provided with other bandwidths in place of the tsi bus 134 . however , the 98304 kb / sec bandwidth is particularly useful because it substantially matches the bandwidth employed in fddi - ii , making it particularly easy to port the data on the tsi bus 134 to a tsi ring 58 ( fig3 ) in configurations where the tsi ring 58 is an fddi - ii system . according to one embodiment , the data is conveyed from the buffer 132 into a time slot on the bus 134 in a time slot interchange fashion . data carried on tsi bus 134 is transmitted in 125 microsecond time frames divided into 1 . 536 time slots , each of which has a duration of about 0 . 08138 microseconds . each time slot has data and associated control and parity . thus a byte could represent 10 bits of time slot information . thus , data from buffer 132a may be placed onto tsi bus 134 , by transmitting a given one of the 1 . 536 bytes stored in 132a on tsi bus 134 at the proper one of the 1 . 536 time slots of the 125 microsecond frame . which of the time slots is &# 34 ; proper &# 34 ; depends on the use which is to be made of the data and , in particular , the destination for the data as predetermined in the connection set - up via the d channel . the destination for data , in the depicted embodiment , has been pre - established using the d channel information . the d channel information is sent to a signaling processor 138 . the d channel information , which includes source , destination , and other needed information , is used to store values in preferably a switch table 140 . in one example , switch table 140 may be divided into sixteen sections 142a - 142p corresponding to the sixteen nodes associated with the hub circuitry 58 of this example . each section 142 contains 1 . 536 bits , corresponding to the 1 . 536 time slots in a tsi bus time frame . these bits can be used as a control 144 for a multiplexer 146 . in the present example , the twenty - four bytes of data from 48d per 125 microsecond frame are conveyed in the first twenty - four b slots of each 48d frame . thus , the data from source 48d will be stored in the isochronous data buffer 132 . the destination for the isochronous data of this example is monitor 48b . thus , the 24 b slots of data will be transferred to data buffer 154a and then on the next frame transmitted to 48b in its corresponding first 24 b slots . the 24 b slots could have been destined for the tsi bus in which case the 24 b slots in 132 would have been switched onto the tsi bus . a bit of the contents of the switch table would have controlled line 150 to control the multiplexer 146 at a rate of one bit for every tsi time slot ( i . e ., one bit every 0 . 080 microseconds ). assuming the first 10 time slots of the tsi bus do not receive the b data which is destined for a nodes attached to another hub , during the first tsi time slot , the multiplexer control 144 will be &# 34 ; 0 &# 34 ; and no data will be output from the buffer 132 onto bus 134 . the multiplexer 146 will merely convey along the tsi bus 134 whatever data was already on the tsi bus in the first time slot . this continues until the 11th time slot of the tsi bus , at which time the b data destined for a node attached to another hub begins to be output onto the tsi bus . during each of the next 24 tsi bus time slots , the control signal for multiplexer 146 will be &# 34 ; 1 &# 34 ; and a byte of data stored in the appropriate data location of buffer 132 will be output through multiplexer 146 onto the bus 134 . which data location of the buffer 132 is &# 34 ; appropriate &# 34 ; can be determined by a read pointer contained in the switch table . preferably , buffer 132 is a read access memory ram and the read pointer will be determined according to the contents of the switch table , on representing the tsi slot time . after completion of conveying the 24 bytes onto the tsi bus , there will be no output from the buffer 132a during subsequent time slots of this tsi frame since in this example no other connections were established . in this way , time slots 11 through 35 for a frame on the tsi bus will be filled with data stored in the buffer 132a , i . e . the 24 bytes of data output by the isochronous source 48d . fig7 also depicts transmission of the isochronous data retrieved from tsi bus 134 to a destination node . the present example requires hub 44a to retrieve the twenty - four bytes of data stored in the first twenty - four even - numbered time slots of the transmitted frame . data from the tsi ring is retrieved by the b interface 58 associated with sink 48b . retrieval from the tsi ring is achieved by a multiplexer 156 controlled by a control signal 158 output over line 160 from the signal processor 138 , relying on a table 162 in a fashion similar to that described for control of multiplexer 146 . the e interface 60 of hub 44a retrieves the non isochronous data ( source 48c ) from repeater 60 intended for the non - isochronous sink 48g . an example of an e transmit interface 168 is depicted in fig8 . the transmit interface depicted in fig8 is in general , the functional inverse of the e receive interface 60 depicted in fig6 . the data 166 is de - serialized and is then combined with any necessary alignment error bits 172 in a multiplexer 174 , the output of which is conveyed to a fifo 176 . a parallel interface could also be provided , without the need for the fifo when in mac . a sync detect circuit 178 extracts synchronization information from the repeater output 166 for conveying to a state machine 180 . state machine 180 also receives carrier detect information 184 , framing counter information 186 , and provides control signals 188 to fifo 176 . the data output from fifo 176 is multiplexed with preamble bits 190 , and &# 34 ; null carrier &# 34 ; bits 194 by a multiplexer 196 . operation of the e transmit interface is described more thoroughly in the application ser . no . 07 / 970 , 329 ( attorney file no . 8332 - 316 / ns - 2022 ), titled &# 34 ; frame - based transmission of data &# 34 ;. the data 198 output from e transmit interface 168 is provided along with isochronous data output 164 and m channel and d channel data 170 to encoder serializer circuitry 202 , as depicted in fig9 . encoder / serializer 202 is configured substantially like the encoding circuitry depicted in fig4 . specifically , encoder / serializer 202 provides a multiplexer for combining the three streams of data 198 , 170 , 164 , a four / five encoder , an nrzi encoder , and pre - emphasis circuitry . the timing of transmission is controlled by transmit timing circuitry 204 . output 206 from the encoder / serializer is selectively combined with link beats from a link beat generator 208 by multiplexer 210 for purposes of link end point detection , as described more thoroughly in application ser . no . 07 / 971 , 018 ( attorney file no . 8332 - 319 / ns - 2027 ). both isochronous and non - isochronous data sent from hub 44a to the nodes 42 is sent in a frame format which is preferably substantially the same as the frame format used for the data sent from the nodes 48 to the hub 44a as described above . at the nodes 42 , the circuitry 50 includes devices ( fig4 ) for decoding and de - multiplexing data , similar to that described for performing these functions in the hub , mainly a phase lock decode 86 , and nrzi decode 88 , a four / five decode 90 , and a de - multiplexer 92 . decoded and de - multiplexed data is then delivered to the various data sinks in the nodes 42 . fig1 depicts a timing scheme to reduce delay and jitter to enable the buffering operation described in the paragraphs above . as shown in fig1 , the timing can be synchronized with a 125 microsecond reference clock signal 214 that provides an ascending clock edge every 125 microseconds . the reference signal can be provided by any of a number of sources , including by synchronization to an external clock reference , such as a reference signal from a wide area network or from a fddi - ii ring or a telephone source , such as a t1 ( 1 . 544 mb / s ) link provided by a local telephone company . at the beginning of a cycle , hub 44 begins to transmit a frame to the node , as indicated by the timing marks on time line 216 . because of the line delays in the physical media , the time at which the nodes receive the frame transmitted by the hub lags the time when the frame was sent from the hub as shown by time line 218 . a delay 220 is therefore introduced before the node begins transmission of the next frame to hub 222 . delay 220 accounts for the latency introduced by transmission over physical media 46 and encoding delays introduced by the hub and node , such that the hub begins receiving the transmitted frame at times 224 approximately coinciding with the rising edges of the clock signals 214 . the hub makes a measurement of the amount of adjustment to be made to the nodes cycle delay . this can be done by timing the delay between the transmission of the cycle start and the arrival of the received cycle start . this adjustment can then be sent to the node as a bit serial stream . the arrival value would be added to the current value , with the modified value to be used as the cycle delay . another scheme for adjusting delay transmits a signal to the node which indicates that the cycle delay is to be increased . every cycle that this increase parameter is received , the node increases the cycle delay . the advantage is in the use of a counter to hold the cycle delay value but requires multiple cycles to correct the skew . fig1 is a block diagram of delay circuitry useful for aligning the transmitted and received data to compensate for line delays . the delay circuitry of fig1 comprises a data control circuit 226 . control circuit 226 may comprise a finite state machine and adder and / or register circuitry . circuit 226 may store a known , fixed initial value of delay for each of the nodes coupled to the hub 44 . latch 236 could also be initialized to a known fixed delay . for cable lengths under 100m , this and the small fifo proves suitable . an adjustable delay accommodates longer lengths , such as with fiber optics . the adjustable delay value is output as a stream of control bits , together with the cycle reference frame , by hub transmitter 228 over physical media 46 to node receiver 230 . the cycle reference frame can be supplied by any of a number of possible sources as described above . at node receiver 230 , the cycle reference is extracted and provided to node delay circuit 232 . the delay control bits are provided to node data control circuit 234 . node data control circuit 234 may also comprise a state machine , and registers , and / or counter circuits . the output of node control circuit 234 controls circuit 236 . according to one embodiment of the present invention circuit 236 is a memory or counter device that stores the current delay value and outputs this value to delay circuit 232 . delay circuit 232 then waits a period of time , t , as given by the output of circuit 236 before transmitting the cycle reference frame to the node transmitter circuit 238 . data from node transmitter 238 is transmitted in phase with the cycle reference frame . data transmitted by node transmitter 238 is received by hub receiver 240 over physical media 46 . hub receiver 240 extracts the transmitted cycle reference and outputs this data to delay measurement circuit 244 . delay measurement circuit 244 compares the cycle reference received from the node to the external cycle reference to obtain an offset value 246 . offset value 246 is provided to hub data control circuit 226 . offset value 246 indicates the delay required to align the received and transmitted data . when the offset value is zero , the received and transmitted frames are in phase . the offset value may be used to increment the initial delay value stored in circuit 226 , or be added to the current delay value stored in circuit 226 to obtain a new current delay value for output to the node . the delay circuitry of the present invention accommodates all lengths of cable up to a cycle reference length of delay . other delays can also be accommodated so long as the sum of delays is an integral number of frame cycles . because the data is multiplexed , the delay circuit of the present invention also has the advantage of accommodating the delays of the many individual isochronous sources coupled to the node . the timing scheme described above guarantees that the cycle received from the node arrives slightly sooner than the next cycle transmitted from the hub . a small fifo can be inserted into the hub &# 39 ; s received data stream to accurately align the arrival of the cycle . a similar fifo structure may be used in the node to synchronize data with the received cycle reference until it is to be transmitted . provision of these fifos is described in more detail in commonly - assigned application ser . no . 07 / 969 , 917 ( attorney file no . 8332 - 320 / ns - 2028 ), titled &# 34 ; apparatus and method for accommodating cable length delays using isochronous fifoing &# 34 ;, filed on even date herewith and incorporated herein by reference . although the present invention has been described by way of preferred embodiments and certain variations and modifications , other variations and modifications can also be used , the invention being defined by the following claims . table i__________________________________________________________________________block 0 : j k e b e b e b e b e b e b e e group 0e e e b e b e b e b e b e b e e group 1e e e b e b e b e b e b e b e e group 2e e e b e b e b e b e b e b e e group 3e e e b e b e b e b e b e b e e group 4e e e b e b e b e b e b e b e e group 5e e e b e b e b e b e b e b e e group 6e e e b e b e b e b e b e b e e group 7block 1 : m m e b e b e b e b e b e b e e group 8e e e b e b e b e b e b e b e e group 9e e e b e b e b e b e b e b e e group 10e e e b e b e b e b e b e b e e group 11e e e b e b e b e b e b e b e e group 12e e e b e b e b e b e b e b e e group 13e e e b e b e b e b e b e b e e group 14e e e b e b e b e b e b e b e e group 15block 2 : d d e b e b e b e b e b e b e e group 16e e e b e b b b e b e b e b e e group 17e e e b e b e b e b e b e b e e group 18e e e b e b e b e b e b e b e e group 19e e e b e b e b e b e b e b e e group 20e e e b e b e b e b e b e b e e group 21e e e b e b e b e b e b e b e e group 22e e e b e b e b e b e b e b e e group 23block 3 : e m e b e b e b e b e b e b e e group 24e e e b e b e b e b e b e b e e group 25e e e b e b e b e b e b e b e e group 26e e e b e b e b e b e b e b e e group 27e e e b e b e b e b e b e b e e group 28e e e b e b e b e b e b e b e e group 29e e e b e b e b e b e b e b e e group 30e e e b e b e b e b e b e b e e group 31__________________________________________________________________________ jk = frame synchronization pattern em = ethernet pad & amp ; 4 maintenance bits mm = 8 maintenance bits e = ethernet packet channel d = d channel b = isochronous channel table ii______________________________________symbol encoded ( 5 bit ) decoded ( 4 bit ) description______________________________________0 11110 0000 data 01 01001 0001 data 12 10100 0010 data 23 10101 0011 data 34 01010 0100 data 45 01011 0101 data 56 01110 0110 data 67 01111 0111 data 78 10010 1000 data 89 10011 1001 data 9a 10110 1010 data ab 10111 1011 data bc 11010 1100 data cd 11011 1101 data de 11100 1110 data ef 11101 1111 data fi 11111 1010 no ethernet carriers 11001 0111 no ethernet datav 01100 0010 unaligned datat 01101 0101 unassignedj 11000 1101 frame sync part 1k 10001 1101 frame sync part 2q 00000 0010 invalidh 00100 0001 invalidr 00111 0110 invalidv 00001 0110 invalidv 00010 0010 invalidv 00011 0010 invalidv 00101 0010 invalidv 00110 0010 invalidv 01000 0010 invalidv 10000 0010 invalid______________________________________