a preferred embodiment of a switched mode power supply circuit will now be thoroughly described with reference to fig2 . for clarity purposes , in fig2 same elements as in fig1 keep same reference numbers . as will be seen , the circuit is particularly adapted for designing a feeding circuit for a new generation cellular phone . a modern cellular phone generally comprises a digital signal processing ( d . s . p .) unit which consumes a lot of current in active mode and which is associated with a microcontroller for managing keyboard , screen , user interface etc ., . . . which requires much less power . thus , in suspend mode , the phone can operate with very low feeding current whereas in active operating mode — when the user is using his / her phone — the d . s . p unit features are fully used in the apparatus , thus substantially increasing the current consumed by the phone . thus the switched mode power supply circuit is particularly adapted to power supplies for cellular phones that operate in these two quite different operating modes , because it allows operation even with very low cyclic ratio values . it is however clear that people qualified in the art will be able to adapt teachings of this invention to any other mobile electronic device . a circuit comprising a pmos - type power transistor will also be described , it being understood that people qualified in the art could readily adapt the circuit to a reverse polarity power transistor . thus , fig2 shows a pmos transistor 101 with a source connected to a non - regulated voltage source , which is in general supplied by a battery , for example an ion - lithium - type battery . as is known , the nominal voltages of this type of battery are of several volts and it is appropriate to reduce the output voltage to prescribed values that are compatible with the semiconductor technology used , for example between 0 . 9 and 1 . 2 volts . the pmos transistor drain is connected to ground via a recovery diode 105 and is also connected to a first choke electrode 102 in serial connection with a capacitor 103 . the regulated output voltage vout is delivered on terminals of the capacitor 103 and can be used as supply voltage for a given load ( not represented ). the control device of the pmos transistor 101 will now be more particularly described . this control device comprises an operational amplifier ( op . amp .) 106 , the positive input of the op amp receives a reference voltage filtered by a capacitor 113 . op amp 106 is assembled as a linear amplifier with a feedback loop , which is comprised of a resistor 107 and a capacitor 108 which are assembled in parallel and this assembly allows to generate an error signal representative of a difference between the regulated voltage vout and the reference voltage vref . the error signal output from op amp 106 is transmitted to a positive input of a second op amp 109 , assembled as a comparator circuit , and the negative input of op amp 109 receives a ramp voltage generated by a ramp generation circuit based on a transistor 114 associated with a capacitor 115 . the output of op amp 109 is transmitted via a toggling circuit 110 ( for example a d - type toggling circuit ) and a reversing switch 116 to a grid input to the pmos power transistor 101 , via a delay element 100 . delay element 100 is designed so as to introduce a predetermined delay on falling edges of the grid signal of pmos transistor 101 , i . e ., a delay at the setting to conduction . for the system to operate in a satisfactory way , i . e ., compensating for the delays inherent to the comparator 109 or toggling circuit 110 , the delay element 100 must introduce a delay on switch - on but not on switch - off . this element can be implemented in a simple way as will be seen hereafter in the description of the preferred embodiment of fig3 . introducing a delay to the setting to conduction of power transistor 101 , allows to introduce a local desynchronization by making generation of the ramp start before the power transistor 101 is set to conduction , whereby all switching delays in the chain can be compensated for . this is simple to realize by directly connecting the output of the reversing switch 116 to the grid input of transistor 114 thus resetting the ramp generation circuit . on the other hand , transistor 101 — the grid of which is connected to the output of the delay element — is set to conduction only after the preset delay time has elapsed . as can thus be seen , as illustrated by the timing diagrams in fig2 the width of pulse ton can be reduced by the delay value . in order to reach particularly small values of the cyclic ratio , without using a fast comparator circuit , it is advantageous to use capacitor pairing techniques and current mirroring techniques that are well - known to people qualified in the art , which will allow to precisely adjust the delay of element 100 so that the switched mode power supply operates within a broad range of output currents , and in particular for the lowest values . a substantial advantage results . in addition to allowing the switched mode power supply circuit to operate at very small values of the cyclic ratio ton / t , the comparator 109 can also be switched off upon completion of the comparison . this further reduces the overall consumption of the circuit , which result could not be obtained with other techniques , in particular the technique based on using of a dual rising - falling ramp and switching the comparator twice per clock cycle . [ 0043 ] fig3 shows a preferred embodiment of a desynchronization circuit comprising a first toggling circuit 202 and a second toggling circuit 203 . both toggling circuits 202 and 203 have an input d and an input sd that are connected to a positive supply voltage . an input cp receives a clock signal clk 205 allowing to clock the ramp generation , the representative timing diagrams of which are illustrated in fig6 b . toggling circuits 202 and 203 are reset by means of a signal received by input cd , which is connected to the output of comparator 109 . the first toggling circuit 202 has an output q that is connected to an input of a delay element 297 , the output delay element 297 is connected to a first input of an and gate 201 . the second toggling circuit 203 has an output q that is connected to a second input of the and gate 201 , but is also used as a the ramp generator control circuit 204 comprising a transistor 114 , a capacitor 115 and a power source 117 . with an aim to illustrate the great variety of all possible ways the invention can be implemented , this time , the ramp generation circuit output is connected to the circuit comparator 109 positive input , contrary to what is illustrated in fig2 . the output of the comparator is then connected directly to two cd inputs of toggling circuits 202 and 203 and is thus used to reset both toggling circuits . the and gate 201 provides an output voltage 206 for controlling the setting to conduction of the mos power transistor 101 , illustrated in fig1 . if needed , an adequate buffer - type circuit ( not represented ) may be added . the desynchronization circuit operates as follows . the power transistor is supposed to be non - conducting . on the rising edge of the clock signal clk , present on electrode 205 , the output q of both toggling circuits goes to a high state . this high state is immediately transmitted to the and gate second input and also controls enabling of the ramp generator via circuit 204 . however , it is only when the high state is transmitted to the first input of and gate 201 by the delay element 207 that the output of and gate 201 switches , whereby setting the mos power transistor to conduction . there is indeed an offset between the setting to conduction of this transistor and the enabling of the ramp generator , which is controlled as soon as both toggling devices switch . examining now how the same transistor is set not to conduct , it can be noted that as soon as the ramp voltage reaches the value of the error voltage at the comparator input , the comparator switches , thus causing both toggling circuits 202 and 203 to reset . instantaneously , both toggling circuits change states , and the low state of output q 204 of the second toggling circuit then immediately locks the and gate 201 , causing the mos transistor 101 to immediately switch off . thus it can be observed that there is indeed a delay — from element 207 — for setting the power transistor to conduction , but switching it off is instantaneous . this effect is obtained by the ramp generation circuit being controlled by the second toggling circuit output , while the first toggling circuit output is only transmitted to the input of and gate 201 after a time delay . thus the intrinsic delay of the comparator is compensated for , as well as all delays in the switching chain , and the switched mode power supply can thus operate for very low current drain values , while avoiding pulse skipping mode . [ 0053 ] fig4 a - 4 e and 5 a - 5 d illustrate timing diagrams of a simulation of various voltages existing in the feeding circuit when the resetting of the ramp generation circuit and the setting to conduction of the power transistor are synchronous . more particularly , fig4 a illustrates the shape of the charging current . [ 0056 ] fig4 c shows the output signal q of the second toggling circuit , which controls resetting of the ramp generator circuit . [ 0057 ] fig4 d illustrates the output voltage 206 of the and gate 201 , which is used to control the setting to conduction of power transistor 101 . [ 0058 ] fig4 e shows voltage vout on the terminals of the load . [ 0059 ] fig5 a illustrates the input signal of comparator 109 in detail . [ 0060 ] fig5 b illustrates the output signal q 204 of the second toggling circuit in detail , which controls the resetting of the ramp generator circuit . [ 0061 ] fig5 c illustrates in detail the output voltage 206 of and gate 201 , which is used to control the setting to conduction of power transistor 101 . [ 0062 ] fig5 d shows details of voltage vout on the terminals of the load . [ 0063 ] fig6 a - 6 e and 7 a - d illustrate timing diagrams representative of the same voltages when the beginning of the ramp and the setting to conduction of power transistor 101 are desynchronized . more particularly , fig6 a illustrates the shape of the charging current . the fig6 c shows the output signal q of the second toggling circuit 203 , which controls the resetting of the ramp generator circuit . the fig6 d illustrates the output voltage 206 of the and gate 201 , which is used to control the setting to conduction of the power transistor 101 . [ 0068 ] fig6 e shows the voltage vout on terminals of the load . [ 0069 ] fig7 a illustrates the input signal of the comparator 109 , in detail . [ 0070 ] fig7 b illustrates the output signal q 204 of the second toggling circuit in detail , which controls the resetting of the ramp generator circuit . [ 0071 ] fig7 c illustrates in detail the output voltage 206 of the and gate 201 , which is used to control the setting to conduction of power transistor 101 . [ 0072 ] fig7 d shows details of the voltage vout on terminals of the load . comparing fig5 c and 7 c , it can be particularly noted that desynchronization allows to substantially reduce duration of the setting to conduction of the power transistor , and without using a faster comparator 109 . all of the above u . s . patents , u . s . patent application publications , u . s . patent applications , foreign patents , foreign patent applications and non - patent publications referred to in this specification and / or listed in the application data sheet , are incorporated herein by reference , in their entirety . from the foregoing it will be appreciated that , although specific embodiments of the invention have been described herein for purposes of illustration , various modifications may be made without deviating from the spirit and scope of the invention . accordingly , the invention is not limited except as by the appended claims .