an interface apparatus of the present invention will be described below in detail with reference to the accompanying drawings . fig2 is a schematic block diagram illustrating the structure of an interface apparatus according to a first embodiment of the present invention . referring to fig2 the interface apparatus 51 according to the first embodiment is connected to a control unit ( cpu ) 52 via a host bus 57 and to an ic card 50 with external terminals . the interface apparatus 51 is composed of a clock signal adjusting unit 1 , a stand - by signal generating circuit 53 , and a serial / parallel converter 54 . the serial / parallel converter 54 converts a transfer data transmitted / received between the control unit 52 and the ic card 50 via the host bus 57 from a serial form into a parallel form or from the parallel form into the serial form . the stand - by signal generating circuit 53 inputs therein the serial transfer data outputted from the serial / parallel converter 54 to the ic card 50 and detects start / end timing of the data transfer operation to thereby generate the stand - by signal sb . the clock signal adjusting unit 1 inputs therein the stand - by signal sb under control of the control unit 52 and generates a card operation clock signal cclk and a data transfer clock signal tclk from the source clock signal based on the stand - by signal sb . this card operation clock signal cclk is supplied to the ic card 50 , whereas the data transfer clock signal tclk is supplied to the serial / parallel converter 54 . fig3 is a schematic block diagram illustrating the structure of the clock signal adjusting unit 1 of the interface apparatus according to the first embodiment of the present invention . referring to fig3 the clock signal adjusting unit 1 according to the first embodiment is composed of an internal clock signal generating section 3 , a card operation clock signal generating section 4 , and a data transfer clock signal generating section 2 . the internal clock signal generating section 3 is a programmable frequency dividing circuit . the internal clock signal generating section 3 is composed of a register 20 for storing data for designating a frequency division ratio and an internal clock signal generating unit 21 for generating an internal clock signal iclk for the interface apparatus based on the frequency division ratio designating data . the card operation clock signal generating section 4 is a programmable frequency dividing circuit and is composed of a register 22 for storing data for designating a frequency division ratio and a card operation clock signal generating unit 23 for generating the card operation clock signal cclk for the ic card 50 at an instructed frequency division ratio , based on the frequency division ratio designating data . the data transfer clock signal generating section 2 generates the data transfer clock signal tclk from the internal clock signal iclk generated by the internal clock signal generating unit 21 in accordance with the predetermined frequency division ratio . the data transfer clock signal generating section 2 controls the generation timing of the data transfer clock signal tclk to supply the controlled data transfer clock signal tclk to the serial / parallel converter 54 . the data transfer clock signal tclk generating section 2 is composed of an adjusted period designating data register 24 , a shift register 25 , an internal counter value register 26 , a down counter 27 , a comparator 28 , a multiplexer 29 , a d - type flip - flop ( d - f / f ) 30 , a t - type flip - flop ( t - f / f ) 31 , an and gate 32 , an or gate 33 , and an exclusive or gate 34 . the d - type flip - flop ( d - f / f ) 30 inputs the internal clock signal iclk at a clock terminal c and an output of the multiplexer 29 at a data terminal d . also , the d - type flip - flop 30 outputs a previous stage data transfer clock signal ptclk divided in frequency in accordance with a predetermined frequency division ratio , and having periods controlled based on the output of the multiplexer 29 . the t - type flip - flop ( t - f / f ) 31 inputs the inverted output of the previous stage data transfer clock signal ptclk from the d - type flip - flop 30 at the clock terminal c . the t - type flip - flop ( t - f / f ) 31 divides the inverted previous stage data transfer clock signal by 2 in frequency in a toggled manner to thereby generate the data transfer clock signal tclk . the inverted signal btclk of the data transfer signal tclk is supplied to the and gate 32 . the down counter 27 inputs a predetermined internal counter value from the register 26 and counts down the internal counter value in response to an inverted signal biclk of the internal clock signal iclk . the predetermined internal counter value is a value indicative of a half of one period of the data transfer clock signal tclk . the down counter 27 outputs the count value to the comparator 28 . the or gate 33 inputs the stand - by signal sb and the previous stage data transfer clock signal ptclk to generate a counter initialize signal ci . the down counter 27 is reset in response to the counter initialize signal ci from the or gate 33 . the shift register 25 is activated in response to the stand - by signal sb . in the active state , the shift register 25 inputs an adjusted period designating data adj of 12 bits from the register 24 and shifts the adjusted period designating data apd one bit by one bit in response to the data transfer clock signal tclk . each bit of the adjusted period designating data apd corresponds to one of the 12 periods of the data transfer clock signal tclk , and indicates whether adjustment of period length should be performed in the corresponding period . then , the shift register 25 outputs the shifted value as a period adjustment designation bit signal adj for the data transfer clock signal tclk within one character . a logical product of the period adjustment designation bit signal adj and the inverted data transfer clock signal btclk is calculated by the and gate 32 . an adjustment direction designating data adir indicating whether each of periods of the data transfer clock signal tclk is to be extended or shortened is set in the adjustment direction designating register 35 . the exclusive or gate 34 inputs the output of the and gate 32 and the adjustment direction designating data adir from the register 24 and calculates a logical exclusive sum to output the calculating result as a selection signal sel . the comparator 28 outputs either an internal signal &# 34 ; 1 &# 34 ; or &# 34 ; 0 &# 34 ; in response to the output of the down counter 27 . the multiplexer 29 enters therein the output signals from the comparator 28 at the terminals &# 34 ; 0 &# 34 ; and &# 34 ; 1 &# 34 ;. then , the multiplexer 29 outputs the internal signal of either &# 34 ; 1 &# 34 ; or &# 34 ; 0 &# 34 ; to the d - type flip - flop 30 based on the selection signal sel from the exclusive or gate 34 . it should be noted that in fig3 there is shown the comparator 28 arranged by a first comparator 28x and a second comparator 28y . the first comparator 28x outputs the internal signal of &# 34 ; 1 &# 34 ; when the count value outputted from the 16 - bit down counter 27 is &# 34 ; 1 &# 34 ;, and the second comparator 28y outputs the internal signal of &# 34 ; 0 &# 34 ; when the count value outputted from the down counter 27 is &# 34 ; 0 &# 34 ;. alternatively , this comparator 28 may be formed a single comparator . fig4 is an example of the comparator 28 . this comparator 28 is composed of a nor gate 41 , an inverter 40 , and and gates 42 and 43 . the nor gate 41 outputs an inverted logical sum of all bits of the counter output except for the least significant bit ( lsb ). the inverter 40 inverts the least significant bit of the counter output to output the inverted lsb signal . the and gate 42 calculates a logical product of the least significant bit of the counter output and the output of the nor gate 41 to output the internal signal of &# 34 ; 1 &# 34 ;. the and gate 43 calculates a logical product of the output of the inverter 40 and the output of the nor gate 41 to output the internal signal of &# 34 ; 0 &# 34 ;. that is , the comparator 28 outputs the internal signal of &# 34 ; 1 &# 34 ; or &# 34 ; 0 &# 34 ; based on the lsb of the internal counter value from the register 26 when the last bit of a half of each period of the data transfer clock signal tclk is counted down . also , fig5 shows an example of the 12 - bit shift register 25 . the shift register 25 is composed of 12 register cells 46 ( 46a , 46b , 46c , . . . ). in each of these register cells 46 , an output of a previous stage register cell as an si signal is inputted to an si input terminal . the stand - by signal sb is inputted to a stand - by input terminal and the data transfer clock signal tclk is inputted to a clk input terminal . the period adjustment designation bit signals adji ( i is an integer in a range of 0 to 11 ) are inputted from the 12 - bit shift register 24 . an so output terminal outputs data to the next stage register cell . furthermore , each of these register cells 46 is composed of a d - type flip - flop 44 having both a set function and a reset function , and and gates 45 and 47 . in this d - type flip - flop 44 , the si signal is supplied to a data terminal d . the data transfer clock signal tclk is inputted into a clock terminal c . the output derived from the and gate 45 for calculating a logical product of the stand - by signal sb and the adji signal is entered into a set terminal s . the output derived from the and gate 47 for calculating a logical product of the stand - by signal sb and the inverted adji signal is supplied to a reset terminal r . in other words , the register cells 46 constitutes a 1 - bit shift register . the register cell operates in such a manner that the output so of the d - type flip - flop 44 is initialized to have the value of the adji signal when the stand - by signal sb becomes &# 34 ; 1 &# 34 ;. also , the register cell operates to shift the si signal input to the so signal output at a rising edge of the data transfer clock signal tclk signal when the stand - by signal sb becomes &# 34 ; 0 &# 34 ;. various kinds of values set in the clock signal adjusting unit 1 may be calculated in the below - mentioned methods . these values are the period adjustment designating data ( apd ) to be set in the shift register 25 , a 1 - bit adjustment direction designating data ( adir ) indicative of an increase / decrease direction of the period adjustment , and an initial counter value ( cnt ) to be set in the down counter 27 . fig6 is a flow chart illustrating the methods . the above values are determined in correspondence with the ratio ( rat ) of data transfer clock signal period to card operation clock signal period for every serial number in the above table 1 . first , the 1 - bit adjustment direction designating data adir and the 16 - bit internal counter value cnt are calculated as follows : in a step s2 , one of the ratios rats is read from the above table 1 and initial values are set . in a step s4 , it is determined whether an integer portion ( ratint ) of the ratio rat except for a fractional portion is an odd number or an even number . when the integer portion ( ratint ) is an even number , a step s8 is executed , whereas when the integer portion ( ratint ) is an odd number , a step s6 is executed . in the step s6 , it is set that adir = 1 and cnt =( ratint + 1 )/ 2 - 1 . on the other hand , in the step s8 , it is set that adir = 0 and cnt =( ratint )/ 2 - 1 . next , in the following steps , the 12 - bit period adjustment designating data apd will be successively calculated from the least significant bit ( lsb ) one bit by one bit . in the following description , the bit values adj of the period adjustment designating data apd are expressed as adj ( i ) ( note i = 0 to 11 ), and a summation of ratio rat up to ith - bit is expressed as σrat ( i ) in the description . also , a summation of counted values of the internal clock signal iclk up to ith - bit is expressed as σclk ( i ) in the description . first , in a step s10 , a summation of σrat ( i - 1 ) and the ratio rat is calculated as σrat ( i ), and σclk ( i ) is recognized as a summation of ( cnt + 1 )× 2 and σclk ( i - 1 ). in the case of the least significant adj ( 0 ), the ratio rat is substituted for σrat ( 0 ), and σclk ( 0 ) is recognized as ( cnt + 1 )× 2 . next , in a step s12 , if the adjustment direction data adir is equal to 1 , then σclk1 = σclk ( i )+ 1 . on the other hand , in a step s14 , if the adjustment direction data adir is equal to 0 , then σclk1 = σclk ( i )- 1 . thereafter , in a step s16 , σclk1 and σclk ( i ) are compared with σrat ( i ) to calculate absolute values d0 and d1 of the differences , respectively . next , in a step s18 , a selection is made whether σclk1 and σclk ( i ) is closer to σrat ( i ). next , in a step s20 , if σclk ( i ) is selected , then adj ( i )= 0 . if σclk1 is selected , then adj ( i )= 1 in a step s22 . next , in a step s24 , whether the processing is completed to all the 12 bits is determined . if the processing not completed , the processing of the step s6 or s8 is executed again . in this manner , as explained above , the period adjustment designating data apd , the 1 - bit adjustment direction designating data ( adir ), and the internal counter values ( cnt ) are calculated for each of the ratios rat from the serial number 1 to the serial number 83 listed in the table 1 . these calculated values are listed in the following table 2 to table 84 . table 2__________________________________________________________________________1 in case of clock period ratio ( rat ) of 11 . 62500adir = 1 , cnt = 5 ( 0005h ), adj = 001001010010b ( 252h ) summation of count of transfer deviationbit internal clock rate / etu ( σclk ( i ) - no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) error / etu__________________________________________________________________________1 0 12 . 0000 11 . 6250 0 . 3750 0 . 03232 1 23 . 0000 23 . 2500 - 0 . 2500 - 0 . 02153 0 35 . 0000 34 . 8750 0 . 1250 0 . 01084 0 47 . 0000 46 . 5000 0 . 5000 0 . 04305 1 58 . 0000 58 . 1250 - 0 . 1250 - 0 . 01086 0 70 . 0000 69 . 7500 0 . 2500 0 . 02157 1 81 . 0000 81 . 3750 - 0 . 3750 - 0 . 03238 0 93 . 0000 93 . 0000 0 . 0000 0 . 00009 0 105 . 0000 104 . 6250 0 . 3750 0 . 032310 1 116 . 0000 116 . 2500 - 0 . 2500 - 0 . 021511 0 128 . 0000 127 . 8750 0 . 1250 0 . 010812 0 140 . 0000 139 . 5000 0 . 5000 0 . 0430__________________________________________________________________________ table 3__________________________________________________________________________2 in case of clock period ratio ( rat ) of 16 . 0000adir = 0 , cnt = 7 ( 0007h ), adj = 000000000000b ( 000h ) summation of count of transfer deviationbit internal clock rate / etu ( σclk ( i ) - no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) error / etu__________________________________________________________________________1 0 16 . 0000 16 . 0000 0 . 0000 0 . 00002 0 32 . 0000 32 . 0000 0 . 0000 0 . 00003 0 48 . 0000 48 . 0000 0 . 0000 0 . 00004 0 64 . 0000 64 . 0000 0 . 0000 0 . 00005 0 80 . 0000 80 . 0000 0 . 0000 0 . 00006 0 96 . 0000 96 . 0000 0 . 0000 0 . 00007 0 112 . 0000 112 . 0000 0 . 0000 0 . 00008 0 128 . 0000 128 . 0000 0 . 0000 0 . 00009 0 144 . 0000 144 . 0000 0 . 0000 0 . 000010 0 160 . 0000 160 . 0000 0 . 0000 0 . 000011 0 176 . 0000 176 . 0000 0 . 0000 0 . 000012 0 192 . 0000 192 . 0000 0 . 0000 0 . 0000__________________________________________________________________________ table 4__________________________________________________________________________3 in case of clock period ratio ( rat ) of 17 . 43750adir = 1 , cnt = 8 ( 0008h ), adj = 101101010101b ( b55h ) summation of count of transfer deviationbit internal clock rate / etu ( σclk ( i ) - no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) error / etu__________________________________________________________________________1 1 17 . 0000 17 . 4375 - 0 . 4375 - 0 . 02512 0 35 . 0000 34 . 8750 0 . 1250 0 . 00723 1 52 . 0000 52 . 3125 - 0 . 3125 - 0 . 01794 0 70 . 0000 69 . 7500 0 . 2500 0 . 01435 1 87 . 0000 87 . 1875 - 0 . 1875 - 0 . 01086 0 105 . 0000 104 . 6250 0 . 3750 0 . 02157 1 122 . 0000 122 . 0625 - 0 . 0625 - 0 . 00368 0 140 . 0000 139 . 5000 0 . 5000 0 . 02879 1 157 . 0000 156 . 9375 0 . 0625 0 . 003610 1 174 . 0000 174 . 3750 - 0 . 3750 - 0 . 021511 0 192 . 0000 191 . 8125 0 . 1875 0 . 010812 1 209 . 0000 209 . 2500 - 0 . 2500 - 0 . 0143__________________________________________________________________________ table 5__________________________________________________________________________4 in case of clock period ratio ( rat ) of 18 . 60000adir = 0 , cnt = 8 ( 0008h ), adj = 011010110101b ( 6b5h ) summation of count of transfer deviationbit internal clock rate / etu ( σclk ( i ) - no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) error / etu__________________________________________________________________________1 1 19 . 0000 18 . 6000 0 . 4000 0 . 02152 0 37 . 0000 37 . 2000 - 0 . 2000 - 0 . 01083 1 56 . 0000 55 . 8000 0 . 2000 0 . 01084 0 74 . 0000 74 . 4000 - 0 . 4000 - 0 . 02155 1 93 . 0000 93 . 0000 0 . 0000 0 . 00006 1 112 . 0000 111 . 6000 0 . 4000 0 . 02157 0 130 . 0000 130 . 2000 - 0 . 2000 - 0 . 01088 1 149 . 0000 148 . 8000 0 . 2000 0 . 01089 0 167 . 0000 167 . 4000 - 0 . 4000 - 0 . 021510 1 186 . 0000 186 . 0000 0 . 0000 0 . 000011 1 205 . 0000 204 . 6000 0 . 4000 0 . 021512 0 223 . 0000 223 . 2000 - 0 . 2000 - 0 . 0108__________________________________________________________________________ table 6__________________________________________________________________________5 in case of clock period ratio ( rat ) of 23 . 25000adir = 1 , cnt = 11 ( 000bh ), adj = 110111011101b ( dddh ) summation of count of transfer deviationbit internal clock rate / etu ( σclk ( i ) - no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) error / etu__________________________________________________________________________1 1 23 . 0000 23 . 2500 - 0 . 2500 - 0 . 01082 0 47 . 0000 46 . 5000 0 . 5000 0 . 02153 1 70 . 0000 69 . 7500 0 . 2500 0 . 01084 1 93 . 0000 93 . 0000 0 . 0000 0 . 00005 1 116 . 0000 116 . 2500 - 0 . 2500 - 0 . 01086 0 140 . 0000 139 . 5000 0 . 5000 0 . 02157 i 163 . 0000 162 . 7500 0 . 2500 0 . 01088 1 186 . 0000 186 . 0000 0 . 0000 0 . 00009 1 209 . 0000 209 . 2500 - 0 . 2500 - 0 . 010810 0 233 . 0000 232 . 5000 0 . 5000 0 . 021511 1 256 . 0000 255 . 7500 0 . 2500 0 . 010812 1 279 . 0000 279 . 0000 0 . 0000 0 . 0000__________________________________________________________________________ table 7__________________________________________________________________________6 in case of clock period ratio ( rat ) of 24 . 00000adir = 0 , cnt = 11 ( 000bh ), adj = 000000000000 ( 000h ) summation of count of transfer deviation internal clock rate / etu ( σclk ( i )- bit no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) error / etu__________________________________________________________________________1 0 24 . 0000 24 . 0000 0 . 0000 0 . 00002 0 48 . 0000 48 . 0000 0 . 0000 0 . 00003 0 72 . 0000 72 . 0000 0 . 0000 0 . 00004 0 96 . 0000 96 . 0000 0 . 0000 0 . 00005 0 120 . 0000 120 . 0000 0 . 0000 0 . 00006 0 144 . 0000 144 . 0000 0 . 0000 0 . 00007 0 168 . 0000 168 . 0000 0 . 0000 0 . 00008 0 192 . 0000 192 . 0000 0 . 0000 0 . 00009 0 216 . 0000 216 . 0000 0 . 0000 0 . 000010 0 240 . 0000 240 . 0000 0 . 0000 0 . 000011 0 264 . 0000 264 . 0000 0 . 0000 0 . 000012 0 288 . 0000 288 . 0000 0 . 0000 0 . 0000__________________________________________________________________________ table 8__________________________________________________________________________7 in case of clock period ratio ( rat ) of 25 . 60000adir = 1 , cnt = 12 ( 000ch ), adj = 100101001010b ( 94ah ) summation of count of transfer deviation internal clock rate / etu ( σclk ( i )- bit no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) error / etu__________________________________________________________________________1 0 26 . 0000 25 . 6000 0 . 4000 0 . 01562 1 51 . 0000 51 . 2000 - 0 . 2000 - 0 . 00783 0 77 . 0000 76 . 8000 0 . 2000 0 . 00784 1 102 . 0000 102 . 4000 - 0 . 4000 - 0 . 01565 0 128 . 0000 128 . 0000 0 . 0000 0 . 00006 0 154 . 0000 153 . 6000 0 . 4000 0 . 01567 1 179 . 0000 179 . 2000 - 0 . 2000 - 0 . 00788 0 205 . 0000 204 . 8000 0 . 2000 0 . 00789 1 230 . 0000 230 . 4000 - 0 . 4000 - 0 . 015610 0 256 . 0000 256 . 0000 0 . 0000 0 . 000011 0 282 . 0000 281 . 6000 0 . 4000 0 . 015612 1 307 . 0000 307 . 2000 - 0 . 2000 - 0 . 0078__________________________________________________________________________ table 9__________________________________________________________________________8 in case of clock period ratio ( rat ) of 27 . 90000adir = 1 , cnt = 13 ( 000dh ), adj = 000000100000b ( 020h ) summation of count of transfer deviation internal clock rate / etu ( σclk ( i )- bit no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) error / etu__________________________________________________________________________1 0 28 . 0000 27 . 9000 0 . 1000 0 . 00362 0 56 . 0000 55 . 8000 0 . 2000 0 . 00723 0 84 . 0000 83 . 7000 0 . 3000 0 . 01084 0 112 . 0000 111 . 6000 0 . 4000 0 . 01435 0 140 . 0000 139 . 5000 0 . 5000 0 . 01796 1 167 . 0000 167 . 4000 - 0 . 4000 - 0 . 01437 0 195 . 0000 195 . 3000 - 0 . 3000 - 0 . 01088 0 223 . 0000 223 . 2000 - 0 . 2000 - 0 . 00729 0 251 . 0000 251 . 1000 - 0 . 1000 - 0 . 003610 0 279 . 0000 279 . 0000 0 . 0000 0 . 000011 0 307 . 0000 306 . 9000 0 . 1000 0 . 003612 0 335 . 0000 334 . 8000 0 . 2000 0 . 0072__________________________________________________________________________ table 10__________________________________________________________________________9 in case of clock period ( rat ) of 31 . 00000adir = 1 , cnt = 15 ( 000fh ), adj = 111111111111b ( fffh ) summation of count of transfer deviation internal clock rate / etu ( σclk ( i )- bit no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) error / etu__________________________________________________________________________1 1 31 . 0000 31 . 0000 0 . 0000 0 . 00002 1 62 . 0000 62 . 0000 0 . 0000 0 . 00003 1 93 . 0000 93 . 0000 0 . 0000 0 . 00004 1 124 . 0000 124 . 0000 0 . 0000 0 . 00005 1 155 . 0000 155 . 0000 0 . 0000 0 . 00006 1 186 . 0000 186 . 0000 0 . 0000 0 . 00007 1 217 . 0000 217 . 0000 0 . 0000 0 . 00008 1 248 . 0000 248 . 0000 0 . 0000 0 . 00009 1 279 . 0000 279 . 0000 0 . 0000 0 . 000010 1 310 . 0006 310 . 0000 0 . 0000 0 . 000011 1 341 . 0000 341 . 0000 0 . 0000 0 . 000012 1 372 . 0000 372 . 0000 0 . 0000 0 . 0000__________________________________________________________________________ table 11__________________________________________________________________________10 in case of clock period ratio ( rat ) of 32 . 00000adir = 0 , cnt = 15 ( 000fh ), adj = 000000000000b ( 000h ) summation of count of transfer deviation internal clock rate / etu ( σclk ( i )- bit no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) error / etu__________________________________________________________________________1 0 32 . 0000 32 . 0000 0 . 0000 0 . 00002 0 64 . 0000 64 . 0000 0 . 0000 0 . 00003 0 96 . 0000 96 . 0000 0 . 0000 0 . 00004 0 128 . 0000 128 . 0000 0 . 0000 0 . 00005 0 160 . 0000 160 . 0000 0 . 0000 0 . 00006 0 192 . 0000 192 . 0000 0 . 0000 0 . 00007 0 224 . 0000 224 . 0000 0 . 0000 0 . 00008 0 256 . 0000 256 . 0000 0 . 0000 0 . 00009 0 288 . 0000 288 . 0000 0 . 0000 0 . 000010 0 320 . 0000 320 . 0000 0 . 0000 0 . 000011 0 352 . 0000 352 . 0000 0 . 0000 0 . 000012 0 384 . 0000 384 . 0000 0 . 0000 0 . 0000__________________________________________________________________________ table 12__________________________________________________________________________11 in case of clock period ratio ( rat ) of 34 . 87500adir = 0 , cnt = 16 ( 0010h ), adj = 011111110111b ( 7f7h ) summation of count of transfer deviation internal clock rate / etu ( σclk ( i )- bit no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) error / etu__________________________________________________________________________1 1 35 . 0000 34 . 8750 0 . 1250 0 . 00362 1 70 . 0000 69 . 7500 0 . 2500 0 . 00723 1 105 . 0000 104 . 6250 0 . 3750 0 . 01084 0 139 . 0000 139 . 5000 - 0 . 5000 - 0 . 01435 1 174 . 0000 174 . 3750 - 0 . 3750 - 0 . 01086 1 209 . 0000 209 . 2500 - 0 . 2500 - 0 . 00727 1 244 . 0000 244 . 1250 - 0 . 1250 - 0 . 00368 1 279 . 0000 279 . 0000 0 . 0000 0 . 00009 1 314 . 0000 313 . 8750 0 . 1250 0 . 003610 1 349 . 0000 348 . 7500 0 . 2500 0 . 007211 1 384 . 0000 383 . 6250 0 . 3750 0 . 010812 0 418 . 0000 418 . 5000 - 0 . 5000 - 0 . 0143__________________________________________________________________________ table 13______________________________________12 in case of clock period ratio ( rat ) of 37 . 20000adir = 1 , cnt = 18 ( 0012h ), adj = 111101111011b ( f7bh ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 1 37 . 0000 37 . 2000 - 0 . 2000 - 0 . 00542 1 74 . 0000 74 . 4000 - 0 . 4000 - 0 . 01083 0 112 . 0000 111 . 6000 0 . 4000 0 . 01084 1 149 . 0000 148 . 8000 0 . 2000 0 . 00545 1 186 . 0000 186 . 0000 0 . 0000 0 . 00006 1 223 . 0000 223 . 2000 - 0 . 2000 - 0 . 00547 1 260 . 0000 260 . 4000 - 0 . 4000 - 0 . 01088 0 298 . 0000 297 . 6000 0 . 4000 0 . 01089 1 335 . 0000 334 . 8000 0 . 2000 0 . 005410 1 372 . 0000 372 . 0000 0 . 0000 0 . 000011 1 409 . 0000 409 . 2000 - 0 . 2000 - 0 . 005412 1 446 . 0000 446 . 4000 - 0 . 4000 - 0 . 0108______________________________________ table 14______________________________________13 in case of clock period ratio ( rat ) of 38 . 40000adir = 0 , cnt = 18 ( 0012h ), adj = 100101001010b ( 94ah ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 38 . 0000 38 . 4000 - 0 . 4000 - 0 . 01042 1 77 . 0000 76 . 8000 0 . 2000 0 . 00523 0 115 . 0000 115 . 2000 - 0 . 2000 - 0 . 00524 1 154 . 0000 153 . 6000 0 . 4000 0 . 01045 0 192 . 0000 192 . 0000 0 . 0000 0 . 00006 0 230 . 0000 230 . 4000 - 0 . 4000 - 0 . 01047 1 269 . 0000 268 . 8000 0 . 2000 0 . 00528 0 307 . 0000 307 . 2000 - 0 . 2000 - 0 . 00529 1 346 . 0000 345 . 6000 0 . 4000 0 . 010410 0 384 . 0000 384 . 0000 0 . 0000 0 . 000011 0 422 . 0000 422 . 4000 - 0 . 4000 - 0 . 010412 1 461 . 0000 460 . 8000 0 . 2000 0 . 0052______________________________________ table 15______________________________________14 in case of clock period ratio ( rat ) of 42 . 66667adir = 0 , cnt = 20 ( 0014h ), adj = 101101101101b ( b6dh ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 1 43 . 0000 42 . 6667 0 . 3333 0 . 00782 0 85 . 0000 85 . 3333 - 0 . 3333 - 0 . 00783 1 128 . 0000 128 . 0000 0 . 0000 0 . 00004 1 171 . 0000 170 . 6667 0 . 3333 0 . 00785 0 213 . 0000 213 . 3333 - 0 . 3333 - 0 . 00786 1 256 . 0000 256 . 0000 0 . 0000 0 . 00007 1 299 . 0000 298 . 6667 0 . 3333 0 . 00788 0 341 . 0000 341 . 3333 - 0 . 3333 - 0 . 00789 1 384 . 0000 384 . 0000 0 . 0000 0 . 000010 1 427 . 0000 426 . 6667 0 . 3333 0 . 007811 0 469 . 0000 469 . 3333 - 0 . 3333 - 0 . 007812 1 512 . 0000 512 . 0000 0 . 0000 0 . 0000______________________________________ table 16______________________________________15 in case of clock period ratio ( rat ) of 46 . 50000adir = 0 , cnt = 22 ( 0016h ), adj = 101010101010b ( aaah ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 46 . 0000 46 . 5000 - 0 . 5000 - 0 . 01082 1 93 . 0000 93 . 0000 0 . 0000 0 . 00003 0 139 . 0000 139 . 5000 - 0 . 5000 - 0 . 01084 1 186 . 0000 186 . 0000 0 . 0000 0 . 00005 0 232 . 0000 232 . 5000 - 0 . 5000 - 0 . 01086 1 279 . 0000 279 . 0000 0 . 0000 0 . 00007 0 325 . 0000 325 . 5000 - 0 . 5000 - 0 . 01088 1 372 . 0000 372 . 0000 0 . 0000 0 . 00009 0 418 . 0000 418 . 5000 - 0 . 5000 - 0 . 010810 1 465 . 0000 465 . 0000 0 . 0000 0 . 000011 0 511 . 0000 511 . 5000 - 0 . 5000 - 0 . 010812 1 558 . 0000 558 . 0000 0 . 0000 0 . 0000______________________________________ table 17______________________________________16 in case of clock period ratio ( rat ) of 48 . 00000adir = 0 , cnt = 23 ( 0017h ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 48 . 0000 48 . 0000 0 . 0000 0 . 00002 0 96 . 0000 96 . 0000 0 . 0000 0 . 00003 0 144 . 0000 144 . 0000 0 . 0000 0 . 00004 0 192 . 0000 192 . 0000 0 . 0000 0 . 00005 0 240 . 0000 240 . 0000 0 . 0000 0 . 00006 0 288 . 0000 288 . 0000 0 . 0000 0 . 00007 0 336 . 0000 336 . 0000 0 . 0000 0 . 00008 0 384 . 0000 384 . 0000 0 . 0000 0 . 00009 0 432 . 0000 432 . 0000 0 . 0000 0 . 000010 0 480 . 0000 480 . 0000 0 . 0000 0 . 000011 0 528 . 0000 528 . 0000 0 . 0000 0 . 000012 0 576 . 0000 576 . 0000 0 . 0000 0 . 0000______________________________________ table 18______________________________________17 in case of clock period ratio ( rat ) of 51 . 20000adir = 1 , cnt = 25 ( 0019h ), adj = 111101111011b ( f7bh ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 1 51 . 0000 51 . 2000 - 0 . 2000 - 0 . 00392 1 102 . 0000 102 . 4000 - 0 . 4000 - 0 . 00783 0 154 . 0000 153 . 6000 0 . 4000 0 . 00784 1 205 . 0000 204 . 8000 0 . 2000 0 . 00395 1 256 . 0000 256 . 0000 0 . 0000 0 . 00006 1 307 . 0000 307 . 2000 - 0 . 2000 - 0 . 00397 1 358 . 0000 358 . 4000 - 0 . 4000 - 0 . 00788 0 410 . 0000 409 . 6000 0 . 4000 0 . 00789 1 461 . 0000 460 . 8000 0 . 2000 0 . 003910 1 512 . 0000 512 . 0000 0 . 0000 0 . 000011 1 563 . 0000 563 . 2000 - 0 . 2000 - 0 . 003912 1 614 . 0000 614 . 4000 - 0 . 4000 - 0 . 0078______________________________________ table 19______________________________________18 in case of clock period ratio ( rat ) of 55 . 80000adir = 1 , cnt = 27 ( 001bh ), adj = 000010000100b ( 084h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 56 . 0000 55 . 8000 0 . 2000 0 . 00362 0 112 . 0000 111 . 6000 0 . 4000 0 . 00723 1 167 . 0000 167 . 4000 - 0 . 4000 - 0 . 00724 0 223 . 0000 223 . 2000 - 0 . 2000 - 0 . 00365 0 279 . 0000 279 . 0000 0 . 0000 0 . 00006 0 335 . 0000 334 . 8000 0 . 2000 0 . 00367 0 391 . 0000 390 . 6000 0 . 4000 0 . 00728 1 446 . 0000 446 . 4000 - 0 . 4000 - 0 . 00729 0 502 . 0000 502 . 2000 - 0 . 2000 - 0 . 003610 0 558 . 0000 558 . 0000 0 . 0000 0 . 000011 0 614 . 0000 613 . 8000 0 . 2000 0 . 003612 0 670 . 0000 669 . 6000 0 . 4000 0 . 0072______________________________________ table 20______________________________________19 in case of clock period ratio ( rat ) of 58 . 12500adir = 0 , cnt = 28 ( 001ch ), adj = 000000010000b ( 010h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 58 . 0000 58 . 1250 - 0 . 1250 - 0 . 00222 0 116 . 0000 116 . 2500 - 0 . 2500 - 0 . 00433 0 174 . 0000 174 . 3750 - 0 . 3750 - 0 . 00654 0 232 . 0000 232 . 5000 - 0 . 5000 - 0 . 00865 1 291 . 0000 290 . 6250 0 . 3750 0 . 00656 0 349 . 0000 348 . 7500 0 . 2500 0 . 00437 0 407 . 0000 406 . 8750 0 . 1250 0 . 00228 0 465 . 0000 465 . 0000 0 . 0000 0 . 00009 0 523 . 0000 523 . 1250 - 0 . 1250 - 0 . 002210 0 581 . 0000 581 . 2500 - 0 . 2500 - 0 . 004311 0 639 . 0000 639 . 3750 - 0 . 3750 - 0 . 006512 0 697 . 0000 697 . 5000 - 0 . 5000 - 0 . 0086______________________________________ table 21______________________________________20 in case of clock period ratio ( rat ) of 62 . 00000adir = 0 , cnt = 30 ( 001eh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 62 . 0000 62 . 0000 0 . 0000 0 . 00002 0 124 . 0000 124 . 0000 0 . 0000 0 . 00003 0 186 . 0000 186 . 0000 0 . 0000 0 . 00004 0 248 . 0000 248 . 0000 0 . 0000 0 . 00005 0 310 . 0000 310 . 0000 0 . 0000 0 . 00006 0 372 . 0000 372 . 0000 0 . 0000 0 . 00007 0 434 . 0000 434 . 0000 0 . 0000 0 . 00008 0 496 . 0000 496 . 0000 0 . 0000 0 . 00009 0 558 . 0000 558 . 0000 0 . 0000 0 . 000010 0 620 . 0000 620 . 0000 0 . 0000 0 . 000011 0 682 . 0000 682 . 0000 0 . 0000 0 . 000012 0 744 . 0000 744 . 0000 0 . 0000 0 . 0000______________________________________ table 22______________________________________21 in case of clock period ratio ( rat ) of 64 . 00000adir = 0 , cnt = 31 ( 001fh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 64 . 0000 64 . 0000 0 . 0000 0 . 00002 0 128 . 0000 128 . 0000 0 . 0000 0 . 00003 0 192 . 0000 192 . 0000 0 . 0000 0 . 00004 0 256 . 0000 256 . 0000 0 . 0000 0 . 00005 0 320 . 0000 320 . 0000 0 . 0000 0 . 00006 0 384 . 0000 384 . 0000 0 . 0000 0 . 00007 0 448 . 0000 448 . 0000 0 . 0000 0 . 00008 0 512 . 0000 512 . 0000 0 . 0000 0 . 00009 0 576 . 0000 576 . 0000 0 . 0000 0 . 000010 0 640 . 0000 640 . 0000 0 . 0000 0 . 000011 0 704 . 0000 704 . 0000 0 . 0000 0 . 000012 0 768 . 0000 768 . 0000 0 . 0000 0 . 0000______________________________________ table 23______________________________________22 in case of clock period ratio ( rat ) of 69 . 75000adir = 1 , cnt = 34 ( 0022h ), adj = 010001000100b ( 444h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 70 . 0000 69 . 7500 0 . 2500 0 . 00362 0 140 . 0000 139 . 5000 0 . 5000 0 . 00723 1 209 . 0000 209 . 2500 - 0 . 2500 - 0 . 00364 0 279 . 0000 279 . 0000 0 . 0000 0 . 00005 0 349 . 0000 348 . 7500 0 . 2500 0 . 00366 0 419 . 0000 418 . 5000 0 . 5000 0 . 00727 1 488 . 0000 488 . 2500 - 0 . 2500 - 0 . 00368 0 558 . 0000 558 . 0000 0 . 0000 0 . 00009 0 628 . 0000 627 . 7500 0 . 2500 0 . 003610 0 698 . 0000 697 . 5000 0 . 5000 0 . 007211 1 767 . 0000 767 . 2500 - 0 . 2500 - 0 . 003612 0 837 . 0000 837 . 0000 0 . 0000 0 . 0000______________________________________ table 24______________________________________23 in case of clock period ratio ( rat ) of 74 . 40000adir = 0 , cnt = 36 ( 0024h ), adj = 100101001010b ( 94ah ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 74 . 0000 74 . 4000 - 0 . 4000 - 0 . 00542 1 149 . 0000 148 . 8000 0 . 2000 0 . 00273 0 223 . 0000 223 . 2000 - 0 . 2000 - 0 . 00274 1 298 . 0000 297 . 6000 0 . 4000 0 . 00545 0 372 . 0000 372 . 0000 0 . 0000 0 . 00006 0 446 . 0000 446 . 4000 - 0 . 4000 - 0 . 00547 1 521 . 0000 520 . 8000 0 . 2000 0 . 00278 0 595 . 0000 595 . 2000 - 0 . 2000 - 0 . 00279 1 670 . 0000 669 . 6000 0 . 4000 0 . 005410 0 744 . 0000 744 . 0000 0 . 0000 0 . 000011 0 818 . 0000 818 . 4000 - 0 . 4000 - 0 . 005412 1 893 . 0000 892 . 8000 0 . 2000 0 . 0027______________________________________ table 25______________________________________24 in case of clock period ratio ( rat ) of 76 . 80000adir = 0 , cnt = 37 ( 0025h ), adj = 111101111011b ( f7bh ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 1 77 . 0000 76 . 8000 0 . 2000 0 . 00262 1 154 . 0000 153 . 6000 0 . 4000 0 . 00523 0 230 . 0000 230 . 4000 - 0 . 4000 - 0 . 00524 1 307 . 0000 307 . 2000 - 0 . 2000 - 0 . 00265 1 384 . 0000 384 . 0000 0 . 0000 0 . 00006 1 461 . 0000 460 . 8000 0 . 2000 0 . 00267 1 538 . 0000 537 . 6000 0 . 4000 0 . 00528 0 614 . 0000 614 . 4000 - 0 . 4000 - 0 . 00529 1 691 . 0000 691 . 2000 - 0 . 2000 - 0 . 002610 1 768 . 0000 768 . 0000 0 . 0000 0 . 000011 1 845 . 0000 844 . 8000 0 . 2000 0 . 002612 1 922 . 0000 921 . 6000 0 . 4000 0 . 0052______________________________________ table 26______________________________________25 in case of clock period ratio ( rat ) of 85 . 33333adir = 1 , cnt = 42 ( 002ah ), adj = 101101101101b ( b6dh ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 1 85 . 0000 85 . 3333 - 0 . 3333 - 0 . 00392 0 171 . 0000 170 . 6667 0 . 3333 0 . 00393 1 256 . 0000 256 . 0000 0 . 0000 0 . 00004 1 341 . 0000 341 . 3333 - 0 . 3333 - 0 . 00395 0 427 . 0000 426 . 6667 0 . 3333 0 . 00396 1 512 . 0000 512 . 0000 0 . 0000 0 . 00007 1 597 . 0000 597 . 3333 - 0 . 3333 - 0 . 00398 0 683 . 0000 682 . 6667 0 . 3333 0 . 00399 1 768 . 0000 768 . 0000 0 . 0000 0 . 000010 1 853 . 0000 853 . 3333 - 0 . 3333 - 0 . 003911 0 939 . 0000 938 . 6667 0 . 3333 0 . 003912 1 1024 . 0000 1024 . 0000 0 . 0000 0 . 0000______________________________________ table 27______________________________________26 in case of clock period ratio ( rat ) of 93 . 00000adir = 1 , cnt = 46 ( 002eh ), adj = 111111111111b ( fffh ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 1 93 . 0000 93 . 0000 0 . 0000 0 . 00002 1 186 . 0000 186 . 0000 0 . 0000 0 . 00003 1 279 . 0000 279 . 0000 0 . 0000 0 . 00004 1 372 . 0000 372 . 0000 0 . 0000 0 . 00005 1 465 . 0000 465 . 0000 0 . 0000 0 . 00006 1 558 . 0000 558 . 0000 0 . 0000 0 . 00007 1 651 . 0000 651 . 0000 0 . 0000 0 . 00008 1 744 . 0000 744 . 0000 0 . 0000 0 . 00009 1 837 . 0000 837 . 0000 0 . 0000 0 . 000010 1 930 . 0000 930 . 0000 0 . 0000 0 . 000011 1 1023 . 0000 1023 . 0000 0 . 0000 0 . 000012 1 1116 . 0000 1116 . 0000 0 . 0000 0 . 0000______________________________________ table 28______________________________________27 in case of clock period ratio ( rat ) of 96 . 00000adir = 0 , cnt = 47 ( 002fh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 96 . 0000 96 . 0000 0 . 0000 0 . 00002 0 192 . 0000 192 . 0000 0 . 0000 0 . 00003 0 288 . 0000 288 . 0000 0 . 0000 0 . 00004 0 384 . 0000 384 . 0000 0 . 0000 0 . 00005 0 480 . 0000 480 . 0000 0 . 0000 0 . 00006 0 576 . 0000 576 . 0000 0 . 0000 0 . 00007 0 672 . 0000 672 . 0000 0 . 0000 0 . 00008 0 768 . 0000 768 . 0000 0 . 0000 0 . 00009 0 864 . 0000 864 . 0000 0 . 0000 0 . 000010 0 960 . 0000 960 . 0000 0 . 0000 0 . 000011 0 1056 . 0000 1056 . 0000 0 . 0000 0 . 000012 0 1152 . 0000 1152 . 0000 0 . 0000 0 . 0000______________________________________ table 29______________________________________28 in case of clock period ratio ( rat ) of 102 . 40000adir = 0 , cnt = 50 ( 0032h ), adj = 100101001010b ( 94ah ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 102 . 0000 102 . 4000 - 0 . 4000 - 0 . 00392 1 205 . 0000 204 . 8000 0 . 2000 0 . 00203 0 307 . 0000 307 . 2000 - 0 . 2000 - 0 . 00204 1 410 . 0000 409 . 6000 0 . 4000 0 . 00395 0 512 . 0000 512 . 0000 0 . 0000 0 . 00006 0 614 . 0000 614 . 4000 - 0 . 4000 - 0 . 00397 1 717 . 0000 716 . 8000 0 . 2000 0 . 00208 0 819 . 0000 819 . 2000 - 0 . 2000 - 0 . 00209 1 922 . 0000 921 . 6000 0 . 4000 0 . 003910 0 1024 . 0000 1024 . 0000 0 . 0000 0 . 000011 0 1126 . 0000 1126 . 4000 - 0 . 4000 - 0 . 003912 1 1229 . 0000 1228 . 8000 0 . 2000 0 . 0020______________________________________ table 30______________________________________29 in case of clock period ratio ( rat ) of 116 . 25000adir = 0 , cnt = 57 ( 0039h ), adj = 010001000100b ( 444h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 116 . 0000 116 . 2500 - 0 . 2500 - 0 . 00222 0 232 . 0000 232 . 5000 - 0 . 5000 - 0 . 00433 1 349 . 0000 348 . 7500 0 . 2500 0 . 00224 0 465 . 0000 465 . 0000 0 . 0000 0 . 00005 0 581 . 0000 581 . 2500 - 0 . 2500 - 0 . 00226 0 697 . 0000 697 . 5000 - 0 . 5000 - 0 . 00437 1 814 . 0000 813 . 7500 0 . 2500 0 . 00228 0 930 . 0000 930 . 0000 0 . 0000 0 . 00009 0 1046 . 0000 1046 . 2500 - 0 . 2500 - 0 . 002210 0 1162 . 0000 1162 . 5000 - 0 . 5000 - 0 . 004311 1 1279 . 0000 1278 . 7500 0 . 2500 0 . 002212 0 1395 . 0000 1395 . 0000 0 . 0000 0 . 0000______________________________________ table 31______________________________________30 in case of clock period ratio ( rat ) of 124 . 00000adir = 0 , cnt = 61 ( 003dh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 124 . 0000 124 . 0000 0 . 0000 0 . 00002 0 248 . 0000 248 . 0000 0 . 0000 0 . 00003 0 372 . 0000 372 . 0000 0 . 0000 0 . 00004 0 496 . 0000 496 . 0000 0 . 0000 0 . 00005 0 620 . 0000 620 . 0000 0 . 0000 0 . 00006 0 744 . 0000 744 . 0000 0 . 0000 0 . 00007 0 868 . 0000 868 . 0000 0 . 0000 0 . 00008 0 992 . 0000 992 . 0000 0 . 0000 0 . 00009 0 1116 . 0000 1116 . 0000 0 . 0000 0 . 000010 0 1240 . 0000 1240 . 0000 0 . 0000 0 . 000011 0 1364 . 0000 1364 . 0000 0 . 0000 0 . 000012 0 1488 . 0000 1488 . 0000 0 . 0000 0 . 0000______________________________________ table 32______________________________________31 in case of clock period ratio ( rat ) of 128 . 00000adir = 0 , cnt = 63 ( 003fh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 128 . 0000 128 . 0000 0 . 0000 0 . 00002 0 256 . 0000 256 . 0000 0 . 0000 0 . 00003 0 384 . 0000 384 . 0000 0 . 0000 0 . 00004 0 512 . 0000 512 . 0000 0 . 0000 0 . 00005 0 640 . 0000 640 . 0000 0 . 0000 0 . 00006 0 768 . 0000 768 . 0000 0 . 0000 0 . 00007 0 896 . 0000 896 . 0000 0 . 0000 0 . 00008 0 1024 . 0000 1024 . 0000 0 . 0000 0 . 00009 0 1152 . 0000 1152 . 0000 0 . 0000 0 . 000010 0 1280 . 0000 1280 . 0000 0 . 0000 0 . 000011 0 1408 . 0000 1408 . 0000 0 . 0000 0 . 000012 0 1536 . 0000 1536 . 0000 0 . 0000 0 . 0000______________________________________ table 33______________________________________32 in case of clock period ratio ( rat ) of 139 . 50000adir = 1 , cnt = 69 ( 0045h ), adj = 101010101010b ( aaah ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 140 . 0000 139 . 5000 0 . 5000 0 . 00362 1 279 . 0000 279 . 0000 0 . 0000 0 . 00003 0 419 . 0000 418 . 5000 0 . 5000 0 . 00364 1 558 . 0000 558 . 0000 0 . 0000 0 . 00005 0 698 . 0000 697 . 5000 0 . 5000 0 . 00366 1 837 . 0000 837 . 0000 0 . 0000 0 . 00007 0 977 . 0000 976 . 5000 0 . 5000 0 . 00368 1 1116 . 0000 1116 . 0000 0 . 0000 0 . 00009 0 1256 . 0000 1255 . 5000 0 . 5000 0 . 003610 1 1395 . 0000 1395 . 0000 0 . 0000 0 . 000011 0 1535 . 0000 1534 . 5000 0 . 5000 0 . 003612 1 1674 . 0000 1674 . 0000 0 . 0000 0 . 0000______________________________________ table 34______________________________________33 in case of clock period ratio ( rat ) of 155 . 00000adir = 1 , cnt = 77 ( 004dh ), adj = 111111111111b ( fffh ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 1 155 . 0000 155 . 0000 0 . 0000 0 . 00002 1 310 . 0000 310 . 0000 0 . 0000 0 . 00003 1 465 . 0000 465 . 0000 0 . 0000 0 . 00004 1 620 . 0000 620 . 0000 0 . 0000 0 . 00005 1 775 . 0000 775 . 0000 0 . 0000 0 . 00006 1 930 . 0000 930 . 0000 0 . 0000 0 . 00007 1 1085 . 0000 1085 . 0000 0 . 0000 0 . 00008 1 1240 . 0000 1240 . 0000 0 . 0000 0 . 00009 1 1395 . 0000 1395 . 0000 0 . 0000 0 . 000010 1 1550 . 0000 1550 . 0000 0 . 0000 0 . 000011 1 1705 . 0000 1705 . 0000 0 . 0000 0 . 000012 1 1860 . 0000 1860 . 0000 0 . 0000 0 . 0000______________________________________ table 35______________________________________34 in case of clock period ratio ( rat ) of 170 . 66667adir = 0 , cnt = 84 ( 0054h ), adj = 101101101101b ( b6dh ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 1 171 . 0000 170 . 6667 0 . 3333 0 . 00202 0 341 . 0000 341 . 3333 - 0 . 3333 - 0 . 00203 1 512 . 0000 512 . 0000 0 . 0000 0 . 00004 1 683 . 0000 682 . 6667 0 . 3333 0 . 00205 0 853 . 0000 853 . 3333 - 0 . 3333 - 0 . 00206 1 1024 . 0000 1024 . 0000 0 . 0000 0 . 00007 1 1195 . 0000 1194 . 6667 0 . 3333 0 . 00208 0 1365 . 0000 1365 . 3333 - 0 . 3333 - 0 . 00209 1 1536 . 0000 1536 . 0000 0 . 0000 0 . 000010 1 1707 . 0000 1706 . 6667 0 . 3333 0 . 002011 0 1877 . 0000 1877 . 3333 - 0 . 3333 - 0 . 002012 1 2048 . 0000 2048 . 0000 0 . 0000 0 . 0000______________________________________ table 36______________________________________35 in case of clock period ratio ( rat ) of 186 . 00000adir = 0 , cnt = 92 ( 005ch ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclki ) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 186 . 0000 186 . 0000 0 . 0000 0 . 00002 0 372 . 0000 372 . 0000 0 . 0000 0 . 00003 0 558 . 0000 558 . 0000 0 . 0000 0 . 00004 0 744 . 0000 744 . 0000 0 . 0000 0 . 00005 0 930 . 0000 930 . 0000 0 . 0000 0 . 00006 0 1116 . 0000 1116 . 0000 0 . 0000 0 . 00007 0 1302 . 0000 1302 . 0000 0 . 0000 0 . 00008 0 1488 . 0000 1488 . 0000 0 . 0000 0 . 00009 0 1674 . 0000 1674 . 0000 0 . 0000 0 . 000010 0 1860 . 0000 1860 . 0000 0 . 0000 0 . 000011 0 2046 . 0000 2046 . 0000 0 . 0000 0 . 000012 0 2232 . 0000 2232 . 0000 0 . 0000 0 . 0000______________________________________ table 37______________________________________36 in case of clock period ratio ( rat ) of 192 . 00000adir = 0 , cnt = 95 ( 005fh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 192 . 0000 192 . 0000 0 . 0000 0 . 00002 0 384 . 0000 384 . 0000 0 . 0000 0 . 00003 0 576 . 0000 576 . 0000 0 . 0000 0 . 00004 0 768 . 0000 768 . 0000 0 . 0000 0 . 00005 0 960 . 0000 960 . 0000 0 . 0000 0 . 00006 0 1152 . 0000 1152 . 0000 0 . 0000 0 . 00007 0 1344 . 0000 1344 . 0000 0 . 0000 0 . 00008 0 1536 . 0000 1536 . 0000 0 . 0000 0 . 00009 0 1728 . 0000 1728 . 0000 0 . 0000 0 . 000010 0 1920 . 0000 1920 . 0000 0 . 0000 0 . 000011 0 2112 . 0000 2112 . 0000 0 . 0000 0 . 000012 0 2304 . 0000 2304 . 0000 0 . 0000 0 . 0000______________________________________ table 38______________________________________37 in case of clock period ratio ( rat ) of 232 . 50000adir = 0 , cnt = 115 ( 0073h ), adj = 101010101010b ( aaah ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 232 . 0000 232 . 5000 - 0 . 5000 - 0 . 00222 1 465 . 0000 465 . 0000 0 . 0000 0 . 00003 0 697 . 0000 697 . 5000 - 0 . 5000 - 0 . 00224 1 930 . 0000 930 . 0000 0 . 0000 0 . 00005 0 1162 . 0000 1162 . 5000 - 0 . 5000 - 0 . 00226 1 1395 . 0000 1395 . 0000 0 . 0000 0 . 00007 0 1627 . 0000 1627 . 5000 - 0 . 5000 - 0 . 00228 1 1860 . 0000 1860 . 0000 0 . 0000 0 . 00009 0 2092 . 0000 2092 . 5000 - 0 . 5000 - 0 . 002210 1 2325 . 0000 2325 . 0000 0 . 0000 0 . 000011 0 2557 . 0000 2557 . 5000 - 0 . 5000 - 0 . 002212 1 2790 . 0000 2790 . 0000 0 . 0000 0 . 0000______________________________________ table 39______________________________________38 in case of clock period ratio ( rat ) of 256 . 00000adir = 0 , cnt = 127 ( 007fh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 256 . 0000 256 . 0000 0 . 0000 0 . 00002 0 512 . 0000 512 . 0000 0 . 0000 0 . 00003 0 768 . 0000 768 . 0000 0 . 0000 0 . 00004 0 1024 . 0000 1024 . 0000 0 . 0000 0 . 00005 0 1280 . 0000 1280 . 0000 0 . 0000 0 . 00006 0 1536 . 0000 1536 . 0000 0 . 0000 0 . 00007 0 1792 . 0000 1792 . 0000 0 . 0000 0 . 00008 0 2048 . 0000 2048 . 0000 0 . 0000 0 . 00009 0 2304 . 0000 2304 . 0000 0 . 0000 0 . 000010 0 2560 . 0000 2560 . 0000 0 . 0000 0 . 000011 0 2816 . 0000 2816 . 0000 0 . 0000 0 . 000012 0 3072 . 0000 3072 . 0000 0 . 0000 0 . 0000______________________________________ table 40______________________________________39 in case of clock period ratio ( rat ) of 279 . 00000adir = 1 , cnt = 139 ( 008bh ), adj = 111111111111b ( fffh ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 1 279 . 0000 279 . 0000 0 . 0000 0 . 00002 1 558 . 0000 558 . 0000 0 . 0000 0 . 00003 1 837 . 0000 837 . 0000 0 . 0000 0 . 00004 1 1116 . 0000 1116 . 0000 0 . 0000 0 . 00005 1 1395 . 0000 1395 . 0000 0 . 0000 0 . 00006 1 1674 . 0000 1674 . 0000 0 . 0000 0 . 00007 1 1953 . 0000 1953 . 0000 0 . 0000 0 . 00008 1 2232 . 0000 2232 . 0000 0 . 0000 0 . 00009 1 2511 . 0000 2511 . 0000 0 . 0000 0 . 000010 1 2790 . 0000 2790 . 0000 0 . 0000 0 . 000011 1 3069 . 0000 3069 . 0000 0 . 0000 0 . 000012 1 3348 . 0000 3348 . 0000 0 . 0000 0 . 0000______________________________________ table 41______________________________________40 in case of clock period ratio ( rat ) of 372 . 00000adir = 0 , cnt = 185 ( 00b9h ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 372 . 0000 372 . 0000 0 . 0000 0 . 00002 0 744 . 0000 744 . 0000 0 . 0000 0 . 00003 0 1116 . 0000 1116 . 0000 0 . 0000 0 . 00004 0 1488 . 0000 1488 . 0000 0 . 0000 0 . 00005 0 1860 . 0000 1860 . 0000 0 . 0000 0 . 00006 0 2232 . 0000 2232 . 0000 0 . 0000 0 . 00007 0 2604 . 0000 2604 . 0000 0 . 0000 0 . 00008 0 2976 . 0000 2976 . 0000 0 . 0000 0 . 00009 0 3348 . 0000 3348 . 0000 0 . 0000 0 . 000010 0 3720 . 0000 3720 . 0000 0 . 0000 0 . 000011 0 4092 . 0000 4092 . 0000 0 . 0000 0 . 000012 0 4464 . 0000 4464 . 0000 0 . 0000 0 . 0000______________________________________ table 42______________________________________41 in case of clock period ratio ( rat ) of 384 . 00000adir = 0 , cnt = 191 ( 00bfh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 384 . 0000 384 . 0000 0 . 0000 0 . 00002 0 768 . 0000 768 . 0000 0 . 0000 0 . 00003 0 1152 . 0000 1152 . 0000 0 . 0000 0 . 00004 0 1536 . 0000 1536 . 0000 0 . 0000 0 . 00005 0 1920 . 0000 1920 . 0000 0 . 0000 0 . 00006 0 2304 . 0000 2304 . 0000 0 . 0000 0 . 00007 0 2688 . 0000 2688 . 0000 0 . 0000 0 . 00008 0 3072 . 0000 3072 . 0000 0 . 0000 0 . 00009 0 3456 . 0000 3456 . 0000 0 . 0000 0 . 000010 0 3840 . 0000 3840 . 0000 0 . 0000 0 . 000011 0 4224 . 0000 4224 . 0000 0 . 0000 0 . 000012 0 4608 . 0000 4608 . 0000 0 . 0000 0 . 0000______________________________________ table 43______________________________________42 in case of clock period ratio ( rat ) of 465 . 00000adir = 1 , cnt = 232 ( 00e8h ), adj = 111111111111b ( fffh ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 1 465 . 0000 465 . 0000 0 . 0000 0 . 00002 1 930 . 0000 930 . 0000 0 . 0000 0 . 00003 1 1395 . 0000 1395 . 0000 0 . 0000 0 . 00004 1 1860 . 0000 1860 . 0000 0 . 0000 0 . 00005 1 2325 . 0000 2325 . 0000 0 . 0000 0 . 00006 1 2790 . 0000 2790 . 0000 0 . 0000 0 . 00007 1 3255 . 0000 3255 . 0000 0 . 0000 0 . 00008 1 3720 . 0000 3720 . 0000 0 . 0000 0 . 00009 1 4185 . 0000 4185 . 0000 0 . 0000 0 . 000010 1 4650 . 0000 4650 . 0000 0 . 0000 0 . 000011 1 5115 . 0000 5115 . 0000 0 . 0000 0 . 000012 1 5580 . 0000 5580 . 0000 0 . 0000 0 . 0000______________________________________ table 44______________________________________43 in case of clock period ratio ( rat ) of 512 . 00000adir = 0 , cnt = 255 ( 00ffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 512 . 0000 512 . 0000 0 . 0000 0 . 00002 0 1024 . 0000 1024 . 0000 0 . 0000 0 . 00003 0 1536 . 0000 1536 . 0000 0 . 0000 0 . 00004 0 2048 . 0000 2048 . 0000 0 . 0000 0 . 00005 0 2560 . 0000 2560 . 0000 0 . 0000 0 . 00006 0 3072 . 0000 3072 . 0000 0 . 0000 0 . 00007 0 3584 . 0000 3584 . 0000 0 . 0000 0 . 00008 0 4096 . 0000 4096 . 0000 0 . 0000 0 . 00009 0 4608 . 0000 4608 . 0000 0 . 0000 0 . 000010 0 5120 . 0000 5120 . 0000 0 . 0000 0 . 000011 0 5632 . 0000 5632 . 0000 0 . 0000 0 . 000012 0 6144 . 0000 6144 . 0000 0 . 0000 0 . 0000______________________________________ table 45______________________________________44 in case of clock period ratio ( rat ) of 558 . 00000adir = 0 , cnt = 278 ( 0116h ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 558 . 0000 558 . 0000 0 . 0000 0 . 00002 0 1116 . 0000 1116 . 0000 0 . 0000 0 . 00003 0 1674 . 0000 1674 . 0000 0 . 0000 0 . 00004 0 2232 . 0000 2232 . 0000 0 . 0000 0 . 00005 0 2790 . 0000 2790 . 0000 0 . 0000 0 . 00006 0 3348 . 0000 3348 . 0000 0 . 0000 0 . 00007 0 3906 . 0000 3906 . 0000 0 . 0000 0 . 00008 0 4464 . 0000 4464 . 0000 0 . 0000 0 . 00009 0 5022 . 0000 5022 . 0000 0 . 0000 0 . 000010 0 5580 . 0000 5580 . 0000 0 . 0000 0 . 000011 0 6138 . 0000 6138 . 0000 0 . 0000 0 . 000012 0 6696 . 0000 6696 . 0000 0 . 0000 0 . 0000______________________________________ table 46______________________________________45 in case of clock period ratio ( rat ) of 744 . 00000adir = 0 , cnt = 371 ( 0173h ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 744 . 0000 744 . 0000 0 . 0000 0 . 00002 0 1488 . 0000 1488 . 0000 0 . 0000 0 . 00003 0 2232 . 0000 2232 . 0000 0 . 0000 0 . 00004 0 2976 . 0000 2976 . 0000 0 . 0000 0 . 00005 0 3720 . 0000 3720 . 0000 0 . 0000 0 . 00006 0 4464 . 0000 4464 . 0000 0 . 0000 0 . 00007 0 5208 . 0000 5208 . 0000 0 . 0000 0 . 00008 0 5952 . 0000 5952 . 0000 0 . 0000 0 . 00009 0 6696 . 0000 6696 . 0000 0 . 0000 0 . 000010 0 7440 . 0000 7440 . 0000 0 . 0000 0 . 000011 0 8184 . 0000 8184 . 0000 0 . 0000 0 . 000012 0 8928 . 0000 8928 . 0000 0 . 0000 0 . 0000______________________________________ table 47______________________________________46 in case of clock period ratio ( rat ) of 768 . 00000adir = 0 , cnt = 383 ( 017fh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 768 . 0000 768 . 0000 0 . 0000 0 . 00002 0 1536 . 0000 1536 . 0000 0 . 0000 0 . 00003 0 2304 . 0000 2304 . 0000 0 . 0000 0 . 00004 0 3072 . 0000 3072 . 0000 0 . 0000 0 . 00005 0 3840 . 0000 3840 . 0000 0 . 0000 0 . 00006 0 4608 . 0000 4608 . 0000 0 . 0000 0 . 00007 0 5376 . 0000 5376 . 0000 0 . 0000 0 . 00008 0 6144 . 0000 6144 . 0000 0 . 0000 0 . 00009 0 6912 . 0000 6912 . 0000 0 . 0000 0 . 000010 0 7680 . 0000 7680 . 0000 0 . 0000 0 . 000011 0 8448 . 0000 8448 . 0000 0 . 0000 0 . 000012 0 9216 . 0000 9216 . 0000 0 . 0000 0 . 0000______________________________________ table 48______________________________________47 in case of clock period ratio ( rat ) of 930 . 00000adir = 0 , cnt = 464 ( 01d0h ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 930 . 0000 930 . 0000 0 . 0000 0 . 00002 0 1860 . 0000 1860 . 0000 0 . 0000 0 . 00003 0 2790 . 0000 2790 . 0000 0 . 0000 0 . 00004 0 3720 . 0000 3720 . 0000 0 . 0000 0 . 00005 0 4650 . 0000 4650 . 0000 0 . 0000 0 . 00006 0 5580 . 0000 5580 . 0000 0 . 0000 0 . 00007 0 6510 . 0000 6510 . 0000 0 . 0000 0 . 00008 0 7440 . 0000 7440 . 0000 0 . 0000 0 . 00009 0 8370 . 0000 8370 . 0000 0 . 0000 0 . 000010 0 9300 . 0000 9300 . 0000 0 . 0000 0 . 000011 0 10230 . 0000 10230 . 0000 0 . 0000 0 . 000012 0 11160 . 0000 11160 . 0000 0 . 0000 0 . 0000______________________________________ table 49______________________________________48 in case of clock period ratio ( rat ) of 1024 . 00000adir = 0 , cnt = 511 ( 01ffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 1024 . 0000 1024 . 0000 0 . 0000 0 . 00002 0 2048 . 0000 2048 . 0000 0 . 0000 0 . 00003 0 3072 . 0000 3072 . 0000 0 . 0000 0 . 00004 0 4096 . 0000 4096 . 0000 0 . 0000 0 . 00005 0 5120 . 0000 5120 . 0000 0 . 0000 0 . 00006 0 6144 . 0000 6144 . 0000 0 . 0000 0 . 00007 0 7168 . 0000 7168 . 0000 0 . 0000 0 . 00008 0 8192 . 0000 8192 . 0000 0 . 0000 0 . 00009 0 9216 . 0000 9216 . 0000 0 . 0000 0 . 000010 0 10240 . 0000 10240 . 0000 0 . 0000 0 . 000011 0 11264 . 0000 11264 . 0000 0 . 0000 0 . 000012 0 12288 . 0000 12288 . 0000 0 . 0000 0 . 0000______________________________________ table 50______________________________________49 in case of clock period ratio ( rat ) of 1116 . 00000adir = 0 , cnt = 557 ( 022dh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 1116 . 0000 1116 . 0000 0 . 0000 0 . 00002 0 2232 . 0000 2232 . 0000 0 . 0000 0 . 00003 0 3348 . 0000 3348 . 0000 0 . 0000 0 . 00004 0 4464 . 0000 4464 . 0000 0 . 0000 0 . 00005 0 5580 . 0000 5580 . 0000 0 . 0000 0 . 00006 0 6696 . 0000 6696 . 0000 0 . 0000 0 . 00007 0 7812 . 0000 7812 . 0000 0 . 0000 0 . 00008 0 8928 . 0000 8928 . 0000 0 . 0000 0 . 00009 0 10044 . 0000 10044 . 0000 0 . 0000 0 . 000010 0 11160 . 0000 11160 . 0000 0 . 0000 0 . 000011 0 12276 . 0000 12276 . 0000 0 . 0000 0 . 000012 0 13392 . 0000 13392 . 0000 0 . 0000 0 . 0000______________________________________ table 51______________________________________50 in case of clock period ratio ( rat ) of 1488 . 00000adir = 0 , cnt = 743 ( 02e7h ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 1488 . 0000 1488 . 0000 0 . 0000 0 . 00002 0 2976 . 0000 2976 . 0000 0 . 0000 0 . 00003 0 4464 . 0000 4464 . 0000 0 . 0000 0 . 00004 0 5952 . 0000 5952 . 0000 0 . 0000 0 . 00005 0 7440 . 0000 7440 . 0000 0 . 0000 0 . 00006 0 8928 . 0000 8928 . 0000 0 . 0000 0 . 00007 0 10416 . 0000 10416 . 0000 0 . 0000 0 . 00008 0 11904 . 0000 11904 . 0000 0 . 0000 0 . 00009 0 13392 . 0000 13392 . 0000 0 . 0000 0 . 000010 0 14880 . 0000 14880 . 0000 0 . 0000 0 . 000011 0 16368 . 0000 16368 . 0000 0 . 0000 0 . 000012 0 17856 . 0000 17856 . 0000 0 . 0000 0 . 0000______________________________________ table 52______________________________________51 in case of clock period ratio ( rat ) of 1536 . 00000adir = 0 , cnt = 767 ( 02ffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 1536 . 0000 1536 . 0000 0 . 0000 0 . 00002 0 3072 . 0000 3072 . 0000 0 . 0000 0 . 00003 0 4608 . 0000 4608 . 0000 0 . 0000 0 . 00004 0 6144 . 0000 6144 . 0000 0 . 0000 0 . 00005 0 7680 . 0000 7680 . 0000 0 . 0000 0 . 00006 0 9216 . 0000 9216 . 0000 0 . 0000 0 . 00007 0 10752 . 0000 10752 . 0000 0 . 0000 0 . 00008 0 12288 . 0000 12288 . 0000 0 . 0000 0 . 00009 0 13824 . 0000 13824 . 0000 0 . 0000 0 . 000010 0 15360 . 0000 15360 . 0000 0 . 0000 0 . 000011 0 16896 . 0000 16896 . 0000 0 . 0000 0 . 000012 0 18432 . 0000 18432 . 0000 0 . 0000 0 . 0000______________________________________ table 53______________________________________52 in case of clock period ratio ( rat ) of 1860 . 00000adir = 0 , cnt = 929 ( 03a1h ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 1860 . 0000 1860 . 0000 0 . 0000 0 . 00002 0 3720 . 0000 3720 . 0000 0 . 0000 0 . 00003 0 5580 . 0000 5580 . 0000 0 . 0000 0 . 00004 0 7440 . 0000 7440 . 0000 0 . 0000 0 . 00005 0 9300 . 0000 9300 . 0000 0 . 0000 0 . 00006 0 11160 . 0000 11160 . 0000 0 . 0000 0 . 00007 0 13020 . 0000 13020 . 0000 0 . 0000 0 . 00008 0 14880 . 0000 14880 . 0000 0 . 0000 0 . 00009 0 16740 . 0000 16740 . 0000 0 . 0000 0 . 000010 0 18600 . 0000 18600 . 0000 0 . 0000 0 . 000011 0 20460 . 0000 20460 . 0000 0 . 0000 0 . 000012 0 22320 . 0000 22320 . 0000 0 . 0000 0 . 0000______________________________________ table 54______________________________________53 in case of clock period ratio ( rat ) of 2048 . 00000adir = 0 , cnt = 1023 ( 03ffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 2048 . 0000 2048 . 0000 0 . 0000 0 . 00002 0 4096 . 0000 4096 . 0000 0 . 0000 0 . 00003 0 6144 . 0000 6144 . 0000 0 . 0000 0 . 00004 0 8192 . 0000 8192 . 0000 0 . 0000 0 . 00005 0 10240 . 0000 10240 . 0000 0 . 0000 0 . 00006 0 12288 . 0000 12288 . 0000 0 . 0000 0 . 00007 0 14336 . 0000 14336 . 0000 0 . 0000 0 . 00008 0 16384 . 0000 16384 . 0000 0 . 0000 0 . 00009 0 18432 . 0000 18432 . 0000 0 . 0000 0 . 000010 0 20480 . 0000 20480 . 0000 0 . 0000 0 . 000011 0 22528 . 0000 22528 . 0000 0 . 0000 0 . 000012 0 24576 . 0000 24576 . 0000 0 . 0000 0 . 0000______________________________________ table 55______________________________________54 in case of clock period ratio ( rat ) of 2232 . 00000adir = 0 , cnt = 1115 ( 045bh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 2232 . 0000 2232 . 0000 0 . 0000 0 . 00002 0 4464 . 0000 4464 . 0000 0 . 0000 0 . 00003 0 6696 . 0000 6696 . 0000 0 . 0000 0 . 00004 0 8928 . 0000 8928 . 0000 0 . 0000 0 . 00005 0 11160 . 0000 11160 . 0000 0 . 0000 0 . 00006 0 13392 . 0000 13392 . 0000 0 . 0000 0 . 00007 0 15624 . 0000 15624 . 0000 0 . 0000 0 . 00008 0 17856 . 0000 17856 . 0000 0 . 0000 0 . 00009 0 20088 . 0000 20088 . 0000 0 . 0000 0 . 000010 0 22320 . 0000 22320 . 0000 0 . 0000 0 . 000011 0 24552 . 0000 24552 . 0000 0 . 0000 0 . 000012 0 26784 . 0000 26784 . 0000 0 . 0000 0 . 0000______________________________________ table 56______________________________________55 in case of clock period ratio ( rat ) of 2976 . 00000adir = 0 , cnt = 1487 ( 05cfh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 2976 . 0000 2976 . 0000 0 . 0000 0 . 00002 0 5952 . 0000 5952 . 0000 0 . 0000 0 . 00003 0 8928 . 0000 8928 . 0000 0 . 0000 0 . 00004 0 11904 . 0000 11904 . 0000 0 . 0000 0 . 00005 0 14880 . 0000 14880 . 0000 0 . 0000 0 . 00006 0 17856 . 0000 17856 . 0000 0 . 0000 0 . 00007 0 20832 . 0000 20832 . 0000 0 . 0000 0 . 00008 0 23808 . 0000 23808 . 0000 0 . 0000 0 . 00009 0 26784 . 0000 26784 . 0000 0 . 0000 0 . 000010 0 29760 . 0000 29760 . 0000 0 . 0000 0 . 000011 0 32736 . 0000 32736 . 0000 0 . 0000 0 . 000012 0 35712 . 0000 35712 . 0000 0 . 0000 0 . 0000______________________________________ table 57______________________________________56 in case of clock period ratio ( rat ) of 3072 . 00000adir = 0 , cnt = 1535 ( 05ffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 3072 . 0000 3072 . 0000 0 . 0000 0 . 00002 0 6144 . 0000 6144 . 0000 0 . 0000 0 . 00003 0 9216 . 0000 9216 . 0000 0 . 0000 0 . 00004 0 12288 . 0000 12288 . 0000 0 . 0000 0 . 00005 0 15360 . 0000 15360 . 0000 0 . 0000 0 . 00006 0 18432 . 0000 18432 . 0000 0 . 0000 0 . 00007 0 21504 . 0000 21504 . 0000 0 . 0000 0 . 00008 0 24576 . 0000 24576 . 0000 0 . 0000 0 . 00009 0 27648 . 0000 27648 . 0000 0 . 0000 0 . 000010 0 30720 . 0000 30720 . 0000 0 . 0000 0 . 000011 0 33792 . 0000 33792 . 0000 0 . 0000 0 . 000012 0 36864 . 0000 36864 . 0000 0 . 0000 0 . 0000______________________________________ table 58______________________________________57 in case of clock period ratio ( rat ) of 3720 . 00000adir = 0 , cnt = 1859 ( 0743h ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 3720 . 0000 3720 . 0000 0 . 0000 0 . 00002 0 7440 . 0000 7440 . 0000 0 . 0000 0 . 00003 0 11160 . 0000 11160 . 0000 0 . 0000 0 . 00004 0 14880 . 0000 14880 . 0000 0 . 0000 0 . 00005 0 18600 . 0000 18600 . 0000 0 . 0000 0 . 00006 0 22320 . 0000 22320 . 0000 0 . 0000 0 . 00007 0 26040 . 0000 26040 . 0000 0 . 0000 0 . 00008 0 29760 . 0000 29760 . 0000 0 . 0000 0 . 00009 0 33480 . 0000 33480 . 0000 0 . 0000 0 . 000010 0 37200 . 0000 37200 . 0000 0 . 0000 0 . 000011 0 40920 . 0000 40920 . 0000 0 . 0000 0 . 000012 0 44640 . 0000 44640 . 0000 0 . 0000 0 . 0000______________________________________ table 59______________________________________58 in case of clock period ratio ( rat ) of 4096 . 00000adir = 0 , cnt = 2047 ( 07ffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 4096 . 0000 4096 . 0000 0 . 0000 0 . 00002 0 8192 . 0000 8192 . 0000 0 . 0000 0 . 00003 0 12288 . 0000 12288 . 0000 0 . 0000 0 . 00004 0 16384 . 0000 16384 . 0000 0 . 0000 0 . 00005 0 20480 . 0000 20480 . 0000 0 . 0000 0 . 00006 0 24576 . 0000 24576 . 0000 0 . 0000 0 . 00007 0 28672 . 0000 28672 . 0000 0 . 0000 0 . 00008 0 32768 . 0000 32768 . 0000 0 . 0000 0 . 00009 0 36864 . 0000 36864 . 0000 0 . 0000 0 . 000010 0 40960 . 0000 40960 . 0000 0 . 0000 0 . 000011 0 45056 . 0000 45056 . 0000 0 . 0000 0 . 000012 0 49152 . 0000 49152 . 0000 0 . 0000 0 . 0000______________________________________ table 60______________________________________59 in case of clock period ratio ( rat ) of 4464 . 00000adir = 0 , cnt = 2231 ( 08b7h ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 4464 . 0000 4464 . 0000 0 . 0000 0 . 00002 0 8928 . 0000 8928 . 0000 0 . 0000 0 . 00003 0 13392 . 0000 13392 . 0000 0 . 0000 0 . 00004 0 17856 . 0000 17856 . 0000 0 . 0000 0 . 00005 0 22320 . 0000 22320 . 0000 0 . 0000 0 . 00006 0 26784 . 0000 26784 . 0000 0 . 0000 0 . 00007 0 31248 . 0000 31248 . 0000 0 . 0000 0 . 00008 0 35712 . 0000 35712 . 0000 0 . 0000 0 . 00009 0 40176 . 0000 40176 . 0000 0 . 0000 0 . 000010 0 44640 . 0000 44640 . 0000 0 . 0000 0 . 000011 0 49104 . 0000 49104 . 0000 0 . 0000 0 . 000012 0 53568 . 0000 53568 . 0000 0 . 0000 0 . 0000______________________________________ table 61______________________________________60 in case of clock period ratio ( rat ) of 5952 . 00000adir = 0 , cnt = 2975 ( 0b9fh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 5952 . 0000 5952 . 0000 0 . 0000 0 . 00002 0 11904 . 0000 11904 . 0000 0 . 0000 0 . 00003 0 17856 . 0000 17856 . 0000 0 . 0000 0 . 00004 0 23808 . 0000 23808 . 0000 0 . 0000 0 . 00005 0 29760 . 0000 29760 . 0000 0 . 0000 0 . 00006 0 35712 . 0000 35712 . 0000 0 . 0000 0 . 00007 0 41664 . 0000 41664 . 0000 0 . 0000 0 . 00008 0 47616 . 0000 47616 . 0000 0 . 0000 0 . 00009 0 53568 . 0000 53568 . 0000 0 . 0000 0 . 000010 0 59520 . 0000 59520 . 0000 0 . 0000 0 . 000011 0 65472 . 0000 65472 . 0000 0 . 0000 0 . 000012 0 71424 . 0000 71424 . 0000 0 . 0000 0 . 0000______________________________________ table 62______________________________________61 in case of clock period ratio ( rat ) of 6144 . 00000adir = 0 , cnt = 3071 ( 0bffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 6144 . 0000 6144 . 0000 0 . 0000 0 . 00002 0 12288 . 0000 12288 . 0000 0 . 0000 0 . 00003 0 18432 . 0000 18432 . 0000 0 . 0000 0 . 00004 0 24576 . 0000 24576 . 0000 0 . 0000 0 . 00005 0 30720 . 0000 30720 . 0000 0 . 0000 0 . 00006 0 36864 . 0000 36864 . 0000 0 . 0000 0 . 00007 0 43008 . 0000 43008 . 0000 0 . 0000 0 . 00008 0 49152 . 0000 49152 . 0000 0 . 0000 0 . 00009 0 55296 . 0000 55296 . 0000 0 . 0000 0 . 000010 0 61440 . 0000 61440 . 0000 0 . 0000 0 . 000011 0 67584 . 0000 67584 . 0000 0 . 0000 0 . 000012 0 73728 . 0000 73728 . 0000 0 . 0000 0 . 0000______________________________________ table 63______________________________________62 in case of clock period ratio ( rat ) of 7440 . 00000adir = 0 , cnt = 3719 ( 0e87h ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 7440 . 0000 7440 . 0000 0 . 0000 0 . 00002 0 14880 . 0000 14880 . 0000 0 . 0000 0 . 00003 0 22320 . 0000 22320 . 0000 0 . 0000 0 . 00004 0 29760 . 0000 29760 . 0000 0 . 0000 0 . 00005 0 37200 . 0000 37200 . 0000 0 . 0000 0 . 00006 0 44640 . 0000 44640 . 0000 0 . 0000 0 . 00007 0 52080 . 0000 52080 . 0000 0 . 0000 0 . 00008 0 59520 . 0000 59520 . 0000 0 . 0000 0 . 00009 0 66960 . 0000 66960 . 0000 0 . 0000 0 . 000010 0 74400 . 0000 74400 . 0000 0 . 0000 0 . 000011 0 81840 . 0000 81840 . 0000 0 . 0000 0 . 000012 0 89280 . 0000 89280 . 0000 0 . 0000 0 . 0000______________________________________ table 64______________________________________63 in case of clock period ratio ( rat ) of 8192 . 00000adir = 0 , cnt = 4095 ( 0fffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 8192 . 0000 8192 . 0000 0 . 0000 0 . 00002 0 16384 . 0000 16384 . 0000 0 . 0000 0 . 00003 0 24576 . 0000 24576 . 0000 0 . 0000 0 . 00004 0 32768 . 0000 32768 . 0000 0 . 0000 0 . 00005 0 40960 . 0000 40960 . 0000 0 . 0000 0 . 00006 0 49152 . 0000 49152 . 0000 0 . 0000 0 . 00007 0 57344 . 0000 57344 . 0000 0 . 0000 0 . 00008 0 65536 . 0000 65536 . 0000 0 . 0000 0 . 00009 0 73728 . 0000 73728 . 0000 0 . 0000 0 . 000010 0 81920 . 0000 81920 . 0000 0 . 0000 0 . 000011 0 90112 . 0000 90112 . 0000 0 . 0000 0 . 000012 0 98304 . 0000 98304 . 0000 0 . 0000 0 . 0000______________________________________ table 65______________________________________64 in case of clock period ratio ( rat ) of 8928 . 00000adir = 0 , cnt = 4463 ( 116fh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 8928 . 0000 8928 . 0000 0 . 0000 0 . 00002 0 17856 . 0000 17856 . 0000 0 . 0000 0 . 00003 0 26784 . 0000 26784 . 0000 0 . 0000 0 . 00004 0 35712 . 0000 35712 . 0000 0 . 0000 0 . 00005 0 44640 . 0000 44640 . 0000 0 . 0000 0 . 00006 0 53568 . 0000 53568 . 0000 0 . 0000 0 . 00007 0 62496 . 0000 62496 . 0000 0 . 0000 0 . 00008 0 71424 . 0000 71424 . 0000 0 . 0000 0 . 00009 0 80352 . 0000 80352 . 0000 0 . 0000 0 . 000010 0 89280 . 0000 89280 . 0000 0 . 0000 0 . 000011 0 98208 . 0000 98208 . 0000 0 . 0000 0 . 000012 0 107136 . 0000 107136 . 0000 0 . 0000 0 . 0000______________________________________ table 66______________________________________65 in case of clock period ratio ( rat ) of 11904 . 00000adir = 0 , cnt = 5951 ( 173fh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 11904 . 0000 11904 . 0000 0 . 0000 0 . 00002 0 23808 . 0000 23808 . 0000 0 . 0000 0 . 00003 0 35712 . 0000 35712 . 0000 0 . 0000 0 . 00004 0 47616 . 0000 47616 . 0000 0 . 0000 0 . 00005 0 59520 . 0000 59520 . 0000 0 . 0000 0 . 00006 0 71424 . 0000 71424 . 0000 0 . 0000 0 . 00007 0 83328 . 0000 83328 . 0000 0 . 0000 0 . 00008 0 95232 . 0000 95232 . 0000 0 . 0000 0 . 00009 0 107136 . 0000 107136 . 0000 0 . 0000 0 . 000010 0 119040 . 0000 119040 . 0000 0 . 0000 0 . 000011 0 130944 . 0000 130944 . 0000 0 . 0000 0 . 000012 0 142848 . 0000 142848 . 0000 0 . 0000 0 . 0000______________________________________ table 67______________________________________66 in case of clock period ratio ( rat ) of 12288 . 00000adir = 0 , cnt = 6143 ( 17ffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 12288 . 0000 12288 . 0000 0 . 0000 0 . 00002 0 24576 . 0000 24576 . 0000 0 . 0000 0 . 00003 0 36864 . 0000 36864 . 0000 0 . 0000 0 . 00004 0 49152 . 0000 49152 . 0000 0 . 0000 0 . 00005 0 61440 . 0000 61440 . 0000 0 . 0000 0 . 00006 0 73728 . 0000 73728 . 0000 0 . 0000 0 . 00007 0 86016 . 0000 86016 . 0000 0 . 0000 0 . 00008 0 98304 . 0000 98304 . 0000 0 . 0000 0 . 00009 0 110592 . 0000 110592 . 0000 0 . 0000 0 . 000010 0 122880 . 0000 122880 . 0000 0 . 0000 0 . 000011 0 135168 . 0000 135168 . 0000 0 . 0000 0 . 000012 0 147456 . 0000 147456 . 0000 0 . 0000 0 . 0000______________________________________ table 68______________________________________67 in case of clock period ratio ( rat ) of 14880 . 00000adir = 0 , cnt = 7439 ( 1d0fh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 14880 . 0000 14880 . 0000 0 . 0000 0 . 00002 0 29760 . 0000 29760 . 0000 0 . 0000 0 . 00003 0 44640 . 0000 44640 . 0000 0 . 0000 0 . 00004 0 59520 . 0000 59520 . 0000 0 . 0000 0 . 00005 0 74400 . 0000 74400 . 0000 0 . 0000 0 . 00006 0 89280 . 0000 89280 . 0000 0 . 0000 0 . 00007 0 104160 . 0000 104160 . 0000 0 . 0000 0 . 00008 0 119040 . 0000 119040 . 0000 0 . 0000 0 . 00009 0 133920 . 0000 133920 . 0000 0 . 0000 0 . 000010 0 148800 . 0000 148800 . 0000 0 . 0000 0 . 000011 0 163680 . 0000 163680 . 0000 0 . 0000 0 . 000012 0 178560 . 0000 178560 . 0000 0 . 0000 0 . 0000______________________________________ table 69______________________________________68 in case of clock period ratio ( rat ) of 16384 . 00000adir = 0 , cnt = 8191 ( 1fffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 16384 . 0000 16384 . 0000 0 . 0000 0 . 00002 0 32768 . 0000 32768 . 0000 0 . 0000 0 . 00003 0 49152 . 0000 49152 . 0000 0 . 0000 0 . 00004 0 65536 . 0000 65536 . 0000 0 . 0000 0 . 00005 0 81920 . 0000 81920 . 0000 0 . 0000 0 . 00006 0 98304 . 0000 98304 . 0000 0 . 0000 0 . 00007 0 114688 . 0000 114688 . 0000 0 . 0000 0 . 00008 0 131072 . 0000 131072 . 0000 0 . 0000 0 . 00009 0 147456 . 0000 147456 . 0000 0 . 0000 0 . 000010 0 163840 . 0000 163840 . 0000 0 . 0000 0 . 000011 0 180224 . 0000 180224 . 0000 0 . 0000 0 . 000012 0 196608 . 0000 196608 . 0000 0 . 0000 0 . 0000______________________________________ table 70______________________________________69 in case of clock period ratio ( rat ) of 17856 . 00000adir = 0 , cnt = 8927 ( 22dfh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 17856 . 0000 17856 . 0000 0 . 0000 0 . 00002 0 35712 . 0000 35712 . 0000 0 . 0000 0 . 00003 0 53568 . 0000 53568 . 0000 0 . 0000 0 . 00004 0 71424 . 0000 71424 . 0000 0 . 0000 0 . 00005 0 89280 . 0000 89280 . 0000 0 . 0000 0 . 00006 0 107136 . 0000 107136 . 0000 0 . 0000 0 . 00007 0 124992 . 0000 124992 . 0000 0 . 0000 0 . 00008 0 142848 . 0000 142848 . 0000 0 . 0000 0 . 00009 0 160704 . 0000 160704 . 0000 0 . 0000 0 . 000010 0 178560 . 0000 178560 . 0000 0 . 0000 0 . 000011 0 196416 . 0000 196416 . 0000 0 . 0000 0 . 000012 0 214272 . 0000 214272 . 0000 0 . 0000 0 . 0000______________________________________ table 71______________________________________70 in case of clock period ratio ( rat ) of 23808 . 00000adir = 0 , cnt = 11903 ( 2e7fh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 23808 . 0000 23808 . 0000 0 . 0000 0 . 00002 0 47616 . 0000 47616 . 0000 0 . 0000 0 . 00003 0 71424 . 0000 71424 . 0000 0 . 0000 0 . 00004 0 95232 . 0000 95232 . 0000 0 . 0000 0 . 00005 0 119040 . 0000 119040 . 0000 0 . 0000 0 . 00006 0 142848 . 0000 142848 . 0000 0 . 0000 0 . 00007 0 166656 . 0000 166656 . 0000 0 . 0000 0 . 00008 0 190464 . 0000 190464 . 0000 0 . 0000 0 . 00009 0 214272 . 0000 214272 . 0000 0 . 0000 0 . 000010 0 238080 . 0000 238080 . 0000 0 . 0000 0 . 000011 0 261888 . 0000 261888 . 0000 0 . 0000 0 . 000012 0 285696 . 0000 285696 . 0000 0 . 0000 0 . 0000______________________________________ table 72______________________________________71 in case of clock period ratio ( rat ) of 24576 . 00000adir = 0 , cnt = 12287 ( 2fffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 24576 . 0000 24576 . 0000 0 . 0000 0 . 00002 0 49152 . 0000 49152 . 0000 0 . 0000 0 . 00003 0 73728 . 0000 73728 . 0000 0 . 0000 0 . 00004 0 98304 . 0000 98304 . 0000 0 . 0000 0 . 00005 0 122880 . 0000 122880 . 0000 0 . 0000 0 . 00006 0 147456 . 0000 147456 . 0000 0 . 0000 0 . 00007 0 172032 . 0000 172032 . 0000 0 . 0000 0 . 00008 0 196608 . 0000 196608 . 0000 0 . 0000 0 . 00009 0 221184 . 0000 221184 . 0000 0 . 0000 0 . 000010 0 245760 . 0000 245760 . 0000 0 . 0000 0 . 000011 0 270336 . 0000 270336 . 0000 0 . 0000 0 . 000012 0 294912 . 0000 294912 . 0000 0 . 0000 0 . 0000______________________________________ table 73______________________________________72 in case of clock period ratio ( rat ) of 29760 . 00000adir = 0 , cnt = 14879 ( 3a1fh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 29760 . 0000 29760 . 0000 0 . 0000 0 . 00002 0 59520 . 0000 59520 . 0000 0 . 0000 0 . 00003 0 89280 . 0000 89280 . 0000 0 . 0000 0 . 00004 0 119040 . 0000 119040 . 0000 0 . 0000 0 . 00005 0 148800 . 0000 148800 . 0000 0 . 0000 0 . 00006 0 178560 . 0000 178560 . 0000 0 . 0000 0 . 00007 0 208320 . 0000 208320 . 0000 0 . 0000 0 . 00008 0 238080 . 0000 238080 . 0000 0 . 0000 0 . 00009 0 267840 . 0000 267840 . 0000 0 . 0000 0 . 000010 0 297600 . 0000 297600 . 0000 0 . 0000 0 . 000011 0 327360 . 0000 327360 . 0000 0 . 0000 0 . 000012 0 357120 . 0000 357120 . 0000 0 . 0000 0 . 0000______________________________________ table 74______________________________________73 in case of clock period ratio ( rat ) of 32768 . 00000adir = 0 , cnt = 16383 ( 3fffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 32768 . 0000 32768 . 0000 0 . 0000 0 . 00002 0 65536 . 0000 65536 . 0000 0 . 0000 0 . 00003 0 98304 . 0000 98304 . 0000 0 . 0000 0 . 00004 0 131072 . 0000 131072 . 0000 0 . 0000 0 . 00005 0 163840 . 0000 163840 . 0000 0 . 0000 0 . 00006 0 196608 . 0000 196608 . 0000 0 . 0000 0 . 00007 0 229376 . 0000 229376 . 0000 0 . 0000 0 . 00008 0 262144 . 0000 262144 . 0000 0 . 0000 0 . 00009 0 294912 . 0000 294912 . 0000 0 . 0000 0 . 000010 0 327680 . 0000 327680 . 0000 0 . 0000 0 . 000011 0 360448 . 0000 360448 . 0000 0 . 0000 0 . 000012 0 393216 . 0000 393216 . 0000 0 . 0000 0 . 0000______________________________________ table 75______________________________________74 in case of clock period ratio ( rat ) of 35712 . 00000adir = 0 , cnt = 17855 ( 45bfh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 35712 . 0000 35712 . 0000 0 . 0000 0 . 00002 0 71424 . 0000 71424 . 0000 0 . 0000 0 . 00003 0 107136 . 0000 107136 . 0000 0 . 0000 0 . 00004 0 142848 . 0000 142848 . 0000 0 . 0000 0 . 00005 0 178560 . 0000 178560 . 0000 0 . 0000 0 . 00006 0 214272 . 0000 214272 . 0000 0 . 0000 0 . 00007 0 249984 . 0000 249984 . 0000 0 . 0000 0 . 00008 0 285696 . 0000 285696 . 0000 0 . 0000 0 . 00009 0 321408 . 0000 321408 . 0000 0 . 0000 0 . 000010 0 357120 . 0000 357120 . 0000 0 . 0000 0 . 000011 0 392832 . 0000 392832 . 0000 0 . 0000 0 . 000012 0 428544 . 0000 428544 . 0000 0 . 0000 0 . 0000______________________________________ table 76______________________________________75 in case of clock period ratio ( rat ) of 47616 . 00000adir = 0 , cnt = 23807 ( 5cffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 47616 . 0000 47616 . 0000 0 . 0000 0 . 00002 0 95232 . 0000 95232 . 0000 0 . 0000 0 . 00003 0 142848 . 0000 142848 . 0000 0 . 0000 0 . 00004 0 190464 . 0000 190464 . 0000 0 . 0000 0 . 00005 0 238080 . 0000 238080 . 0000 0 . 0000 0 . 00006 0 285696 . 0000 285696 . 0000 0 . 0000 0 . 00007 0 333312 . 0000 333312 . 0000 0 . 0000 0 . 00008 0 380928 . 0000 380928 . 0000 0 . 0000 0 . 00009 0 428544 . 0000 428544 . 0000 0 . 0000 0 . 000010 0 476160 . 0000 476160 . 0000 0 . 0000 0 . 000011 0 523776 . 0000 523776 . 0000 0 . 0000 0 . 000012 0 571392 . 0000 571392 . 0000 0 . 0000 0 . 0000______________________________________ table 77______________________________________76 in case of clock period ratio ( rat ) of 49152 . 00000adir = 0 , cnt = 24575 ( 5fffh ), adj = 000000000000b ( 000h ) summation count of of internal transfer deviationbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 49152 . 0000 49152 . 0000 0 . 0000 0 . 00002 0 98304 . 0000 98304 . 0000 0 . 0000 0 . 00003 0 147456 . 0000 147456 . 0000 0 . 0000 0 . 00004 0 196608 . 0000 196608 . 0000 0 . 0000 0 . 00005 0 245760 . 0000 245760 . 0000 0 . 0000 0 . 00006 0 294912 . 0000 294912 . 0000 0 . 0000 0 . 00007 0 344064 . 0000 344064 . 0000 0 . 0000 0 . 00008 0 393216 . 0000 393216 . 0000 0 . 0000 0 . 00009 0 442368 . 0000 442368 . 0000 0 . 0000 0 . 000010 0 491520 . 0000 491520 . 0000 0 . 0000 0 . 000011 0 540672 . 0000 540672 . 0000 0 . 0000 0 . 000012 0 589824 . 0000 589824 . 0000 0 . 0000 0 . 0000______________________________________ table 78______________________________________77 in case of clock period ratio ( rat ) of 59520 . 00000adir = 0 , cnt = 29759 ( 743fh ), adj = 000000000000b ( 000h ) summation count of of devia - internal transfer tionbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 59520 . 0000 59520 . 0000 0 . 0000 0 . 00002 0 119040 . 0000 119040 . 0000 0 . 0000 0 . 00003 0 178560 . 0000 178560 . 0000 0 . 0000 0 . 00004 0 238080 . 0000 238080 . 0000 0 . 0000 0 . 00005 0 297600 . 0000 297600 . 0000 0 . 0000 0 . 00006 0 357120 . 0000 357120 . 0000 0 . 0000 0 . 00007 0 416640 . 0000 416640 . 0000 0 . 0000 0 . 00008 0 476160 . 0000 476160 . 0000 0 . 0000 0 . 00009 0 535680 . 0000 535680 . 0000 0 . 0000 0 . 000010 0 595200 . 0000 595200 . 0000 0 . 0000 0 . 000011 0 654720 . 0000 654720 . 0000 0 . 0000 0 . 000012 0 714240 . 0000 714240 . 0000 0 . 0000 0 . 0000______________________________________ table 79______________________________________78 in case of clock period ratio ( rat ) of 65536 . 00000adir = 0 , cnt = 32767 ( 7fffh ), adj = 000000000000b ( 000h ) summation count of of devia - internal transfer tionbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 65536 . 0000 65536 . 0000 0 . 0000 0 . 00002 0 131072 . 0000 131072 . 0000 0 . 0000 0 . 00003 0 196608 . 0000 196608 . 0000 0 . 0000 0 . 00004 0 262144 . 0000 262144 . 0000 0 . 0000 0 . 00005 0 327680 . 0000 327680 . 0000 0 . 0000 0 . 00006 0 393216 . 0000 393216 . 0000 0 . 0000 0 . 00007 0 458752 . 0000 458752 . 0000 0 . 0000 0 . 00008 0 524288 . 0000 524288 . 0000 0 . 0000 0 . 00009 0 589824 . 0000 589824 . 0000 0 . 0000 0 . 000010 0 655360 . 0000 655360 . 0000 0 . 0000 0 . 000011 0 720896 . 0000 720896 . 0000 0 . 0000 0 . 000012 0 786432 . 0000 786432 . 0000 0 . 0000 0 . 0000______________________________________ table 80______________________________________79 in case of clock period ratio ( rat ) of 71424 . 00000adir = 0 , cnt = 35711 ( 8b7fh ), adj = 000000000000b ( 000h ) summation count of of devia - internal transfer tionbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 71424 . 0000 71424 . 0000 0 . 0000 0 . 00002 0 142848 . 0000 142848 . 0000 0 . 0000 0 . 00003 0 214272 . 0000 214272 . 0000 0 . 0000 0 . 00004 0 285696 . 0000 285696 . 0000 0 . 0000 0 . 00005 0 357120 . 0000 357120 . 0000 0 . 0000 0 . 00006 0 428544 . 0000 428544 . 0000 0 . 0000 0 . 00007 0 499968 . 0000 499968 . 0000 0 . 0000 0 . 00008 0 571392 . 0000 571392 . 0000 0 . 0000 0 . 00009 0 642816 . 0000 642816 . 0000 0 . 0000 0 . 000010 0 714240 . 0000 714240 . 0000 0 . 0000 0 . 000011 0 785664 . 0000 785664 . 0000 0 . 0000 0 . 000012 0 857088 . 0000 857088 . 0000 0 . 0000 0 . 0000______________________________________ table 81______________________________________80 in case of clock period ratio ( rat ) of 95232 . 00000adir = 0 , cnt = 47615 ( b9ffh ), adj = 000000000000b ( 000h ) summation count of of devia - internal transfer tionbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 95232 . 0000 95232 . 0000 0 . 0000 0 . 00002 0 190464 . 0000 190464 . 0000 0 . 0000 0 . 00003 0 285696 . 0000 285696 . 0000 0 . 0000 0 . 00004 0 380928 . 0000 380928 . 0000 0 . 0000 0 . 00005 0 476160 . 0000 476160 . 0000 0 . 0000 0 . 00006 0 571392 . 0000 571392 . 0000 0 . 0000 0 . 00007 0 666624 . 0000 666624 . 0000 0 . 0000 0 . 00008 0 761856 . 0000 761856 . 0000 0 . 0000 0 . 00009 0 857088 . 0000 857088 . 0000 0 . 0000 0 . 000010 0 952320 . 0000 952320 . 0000 0 . 0000 0 . 000011 0 1047552 . 0000 1047552 . 0000 0 . 0000 0 . 000012 0 1142784 . 0000 1142784 . 0000 0 . 0000 0 . 0000______________________________________ table 82______________________________________81 in case of clock period ratio ( rat ) of 98304 . 00000adir = 0 , cnt = 49151 ( bfffh ), adj = 000000000000b ( 000h ) summation count of of devia - internal transfer tionbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 98304 . 0000 98304 . 0000 0 . 0000 0 . 00002 0 196608 . 0000 196608 . 0000 0 . 0000 0 . 00003 0 294912 . 0000 294912 . 0000 0 . 0000 0 . 00004 0 393216 . 0000 393216 . 0000 0 . 0000 0 . 00005 0 491520 . 0000 491520 . 0000 0 . 0000 0 . 00006 0 589824 . 0000 589824 . 0000 0 . 0000 0 . 00007 0 688128 . 0000 688128 . 0000 0 . 0000 0 . 00008 0 786432 . 0000 786432 . 0000 0 . 0000 0 . 00009 0 884736 . 0000 884736 . 0000 0 . 0000 0 . 000010 0 983040 . 0000 983040 . 0000 0 . 0000 0 . 000011 0 1081344 . 0000 1081344 . 0000 0 . 0000 0 . 000012 0 1179648 . 0000 1179648 . 0000 0 . 0000 0 . 0000______________________________________ table 83______________________________________82 in case of clock period ratio ( rat ) of 119040 . 00000adir = 0 , cnt = 59519 ( e87fh ), adj = 000000000000b ( 000h ) summation count of of devia - internal transfer tionbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 119040 . 0000 119040 . 0000 0 . 0000 0 . 00002 0 238080 . 0000 238080 . 0000 0 . 0000 0 . 00003 0 357120 . 0000 357120 . 0000 0 . 0000 0 . 00004 0 476160 . 0000 476160 . 0000 0 . 0000 0 . 00005 0 595200 . 0000 595200 . 0000 0 . 0000 0 . 00006 0 714240 . 0000 714240 . 0000 0 . 0000 0 . 00007 0 833280 . 0000 833280 . 0000 0 . 0000 0 . 00008 0 952320 . 0000 952320 . 0000 0 . 0000 0 . 00009 0 1071360 . 0000 1071360 . 0000 0 . 0000 0 . 000010 0 1190400 . 0000 1190400 . 0000 0 . 0000 0 . 000011 0 1309440 . 0000 1309440 . 0000 0 . 0000 0 . 000012 0 1428480 . 0000 1428480 . 0000 0 . 0000 0 . 0000______________________________________ table 84______________________________________83 in case of clock period ratio ( rat ) of 131072 . 00000adir = 0 , cnt = 65535 ( ffffh ), adj = 000000000000b ( 000h ) summation count of of devia - internal transfer tionbit clock rate / etu ( σclk ( i ) - error / no . adj ( σclk ( i )) ( σrat ( i )) σrat ( i )) etu______________________________________1 0 131072 . 0000 131072 . 0000 0 . 0000 0 . 00002 0 262144 . 0000 262144 . 0000 0 . 0000 0 . 00003 0 393216 . 0000 393216 . 0000 0 . 0000 0 . 00004 0 524288 . 0000 524288 . 0000 0 . 0000 0 . 00005 0 655360 . 0000 655360 . 0000 0 . 0000 0 . 00006 0 786432 . 0000 786432 . 0000 0 . 0000 0 . 00007 0 917504 . 0000 917504 . 0000 0 . 0000 0 . 00008 0 1048576 . 0000 1048576 . 0000 0 . 0000 0 . 00009 0 1179648 . 0000 1179648 . 0000 0 . 0000 0 . 000010 0 1310720 . 0000 1310720 . 0000 0 . 0000 0 . 000011 0 1441792 . 0000 1441792 . 0000 0 . 0000 0 . 000012 0 1572864 . 0000 1572864 . 0000 0 . 0000 0 . 0000______________________________________ next , the operation of the interface apparatus 51 employing the clock signal adjusting unit 1 according to the first embodiment of the present invention will be described below . first , the control unit 52 sets a frequency division ratio for the internal clock signal iclk in the register 20 , a frequency division ratio for the card operation clock signal cclk in the register 22 . also , the control unit 52 sets the adjusted period designating data apd in the register 24 , and the 1 - bit adjustment direction designating data adir in the register 35 . further , the control unit 52 sets the internal counter value cnt for the down counter 27 into the register 26 . these values are determined based on an externally input designation or the ratio of data transfer clock signal period to card operation clock signal period , obtained in the initial response . assuming now such a combination that adir = 0 , adj = 010001000100b , and cnt = 5 , the operation of the interface apparatus 51 when one character is transferred will be described with reference to fig2 and fig7 a to 7e . in this example , if the internal clock signal iclk is counted simply 5 periods by 5 periods to generate the data transfer clock signal tclk , the errors are gradually accumulated proceeding to the last bit ( t2 ) of the one character . as a result , there would be a case that transmission / reception of data fail . this is because the frequency of the generated data transfer clock signal tclk is slightly larger than an expected frequency of the data transfer clock signal for the ic card 50 . in a data transfer operation between the ic card 50 and the interface apparatus 51 , a parity bit must be received within a time period of 9 . 5 etu ± 0 . 2 etu from a head of a start bit such that the parity check can be performed . when an error is detected based on the parity bit , &# 34 ; 0 &# 34 ; must be output to a data line between this ic card 50 and the interface apparatus 51 within a time period of 1 to 2 etu after 10 . 5 etu from the head of the start bit . as a consequence , accumulation of the errors must be prevented for the data transfer clock signal tclk within a time period defined from the head of the start bit to 12 etu . in accordance with this embodiment , the period count value of the internal clock signal iclk is increased by &# 34 ; 1 &# 34 ; to extend &# 34 ; etu &# 34 ; in proper periods , by which the error accumulation can be avoided . in the case that the adjusted period designating data apd of 12 bits is sequentially outputted as the adjusted period designating bit signal adj from the least significant bit as shown in fig7 c . when the adjusted period designating bit signal adj is &# 34 ; 1 &# 34 ; and further the data transfer clock signal tclk is &# 34 ; 0 &# 34 ;, the extra counting of the internal clock signal iclk is carried out , as shown in fig7 e by a range a . in other words , at the same time when the start bit of a reception data , or writing of a transmission data is detected , the stand - by signal sb is reset as shown in fig7 b . at this time ( t0 ), the shift register 25 is set to the shift operation enable state . also , the down counter 27 starts to count down the value , i . e ., &# 34 ; 5 &# 34 ; set in the counter 27 from the register 26 . the down counter 27 counts by - 1 every time the falling edge of the internal clock signal iclk , namely executes the count down operation . the output of the eor gate 34 as the selection signal sel is &# 34 ; 0 &# 34 ;, unless the data transfer clock signal tclk is &# 34 ; 0 &# 34 ; and also the adjusted period designating bit signal adj outputted from the shift register 25 is &# 34 ; 1 &# 34 ;. in addition , one of the internal data bits of &# 34 ; 0 &# 34 ; and &# 34 ; 1 &# 34 ; entered from the comparator 28x is selected as the output from the multiplexer 29 in accordance with the selection signal sel . therefore , the previous stage data transfer clock signal ptclk is outputted at the rising edge of the internal clock signal iclk immediately after the output of the counter 27 becomes &# 34 ; 1 &# 34 ;. as a result , the content of the counter 27 is initialized in response to the clock signal ptclk . in other words , the value &# 34 ; 5 &# 34 ; set in the register 26 for the down counter 27 is loaded on the down counter 27 , so that the subsequent count down operation is commenced ( t1 ). fig8 a to 8i are timing charts illustrating the period adjusting operation shown as the range &# 34 ; a &# 34 ; in fig7 e . the content of the shift register 25 is shifted by one bit at a rising edge ( t3 ) of the data transfer clock signal tclk shown in fig8 f so that the adjusted period designating signal adj becomes &# 34 ; 1 &# 34 ; as shown in fig8 g . since the data transfer clock signal tclk is &# 34 ; 1 &# 34 ;, the adjusted period designating bit signal adj is masked by the and gate 32 . accordingly , the counting - down operation of the down counter 27 is advanced to &# 34 ; 1 &# 34 ; ( t4 ) as shown in fig8 b , and the previous stage data transfer clock signal ptclk is raised at a rising edge ( t5 ) of the next internal clock signal iclk shown in fig8 a . as a result , the counter initialize signal ci is set to &# 34 ; 1 &# 34 ; and the down counter 27 is initialized in response to the clock signal ptclk . in this manner , the initialization of the counter 27 is performed and then the counting - down operation of the down counter 27 is again commenced from &# 34 ; 5 &# 34 ;. as a subsequent rising edge ( t6 ) of the internal clock signal iclk shown in fig8 a , the previous stage data transfer clock signal tclk falls down , as shown in fig8 f . subsequently , the data transfer clock signal tclk is toggled between &# 34 ; 0 &# 34 ; and &# 34 ; 1 &# 34 ;. as a result , the output of the and gate 32 becomes &# 34 ; 1 &# 34 ; when the data transfer clock signal tclk is &# 34 ; 1 &# 34 ; because the adjusted period designation signal adj is also &# 34 ; 1 &# 34 ;. since the output adir from the adjustment direction designating data register 35 is equal to &# 34 ; 0 &# 34 ;, the eor gate 34 outputs &# 34 ; 1 &# 34 ; as the selection signal sel , as shown in fig8 h . for this reason , the multiplexer 29 selects the input on the &# 34 ; 1 &# 34 ; side , namely , the output of &# 34 ; 0 &# 34 ; from the comparator 28 shown in fig8 d . as a result , the counting - down operation by the down counter 27 is advanced to &# 34 ; 0 &# 34 ; ( t7 ), as shown in fig8 b . that is , the down counter 27 counts down more by 1 than in a case that the selection signal sel is &# 34 ; 0 &# 34 ;. when the count output of the down counter 27 becomes &# 34 ; 0 &# 34 ;, as shown in fig8 b , the previous stage data transfer clock signal tclk is raised at the next rising edge ( t8 ) of the internal clock signal iclk . therefore , the down counter 27 is initialized in response to the clock signal ptclk in such a manner that the counting - down operation is again commenced from &# 34 ; 5 &# 34 ;, as shown in fig8 a . at a subsequent rising edge ( t9 ) of the internal clock signal iclk shown in fig8 a , the previous stage data transfer clock signal ptclk falls down as shown in fig8 e . as a result , the counter initialize signal ci , i . e ., the output of the or gate 33 becomes &# 34 ; 0 &# 34 ; as shown in fig8 i , so that the counting down operation by the down counter 27 is commenced . at the same time , the data transfer clock signal is toggled to become &# 34 ; 1 &# 34 ;. as a result , the adjustment period designating data apd of the shift register 25 is shifted by one bit , and the adjusted period designating bit signal adj is returned to &# 34 ; 0 &# 34 ;, as shown in fig8 g . thus , the generating operation of the data transfer clock signal tclk for one time period is accomplished in a case that the adjusted period designating bit signal adj becomes &# 34 ; 1 &# 34 ;. in this case , one time period of the data transfer clock signal tclk becomes 11 (= 5 + 6 ) time periods of the internal clock signal iclk . in this case , the adjusted period designating bit signal adj becomes &# 34 ; 0 &# 34 ; and the counting - down operation of the down counter 27 is ended at the value of &# 34 ; 1 &# 34 ;. therefore , in the generating operation of the data transfer clock signal tclk for the next time period , the next time period of the data transfer clock signal tclk is equal to ( 5 + 5 ) time periods of the internal clock signal . next , the operation of the interface apparatus 51 when adir = 1 , adj = 010001000100b , and cnt = 5 , will now be explained with reference to fig9 a to 9e . in this example , if the internal clock signal iclk is simply counted every 6 periods such that the data transfer clock signal tclk is generated , the errors are accumulated near the last ( t2 ) of 1 character , because the data transfer clock signal tclk is delayed . thus , there are some possibilities that the data transmission / reception may fail . as a consequence , the counter value of the internal clock signal iclk by the down counter 27 is shortened by one in proper periods in order to avoid the error accumulation . that is , while the adjusted period designating data apd of 12 bits is sequentially outputted from the least significant bit one bit by one bit as the adjusted period designating bit signal adj . when the adjusted period designating bit signal adj becomes &# 34 ; 1 &# 34 ; and also the data transfer clock signal tclk becomes &# 34 ; 0 &# 34 ;, the count value of internal clock signal periods is shortened . the stand - by signal sb is reset as shown in fig9 b when the data transfer operation of one character is started . in response to the stand - by signal sb of the low level , the down counter 27 receives the internal counter value cnt of &# 34 ; 5 &# 34 ; from the register 26 and commences the counting - down operation from the internal counter value of &# 34 ; 5 &# 34 ; ( t0 ). the down counter 27 is counted by + 1 every time the falling edge of the internal clock signal appears . unless the data transfer clock signal tclk is &# 34 ; 0 &# 34 ; and also the adjusted period designating signal adj is &# 34 ; 1 &# 34 ;, the selection signal sel is &# 34 ; 1 &# 34 ;. for this reason , the output of &# 34 ; 0 &# 34 ; from the comparator 28 is selected by the multiplexer 29 . the previous stage data transfer clock signal ptclk rises at the rising edge of the internal clock signal immediately after the output of the counter 27 becomes &# 34 ; 0 &# 34 ;. thus , the counter initialize signal ci becomes active so that the down counter 27 is initialized . in other words , the value &# 34 ; 5 &# 34 ; set in the register 26 for the counter 27 is loaded on the down counter 27 , so that the subsequent counting - down operation is commenced ( t1 ). fig1 a to 10i are timing charts illustrating the operation of the interface apparatus 51 in a range b shown in fig9 e . as shown in fig1 g , the adjusted period designating data apd of the shift register 25 is shifted by &# 34 ; 1 &# 34 ; bit at a rising edge ( t3 ) of the internal clock signal iclk shown in fig1 a . as a result , adjusted period designating bit signal adj becomes &# 34 ; 1 &# 34 ; in this example . when the data transfer clock signal tclk becomes &# 34 ; 1 &# 34 ;, the adjusted period designating bit signal adj is masked by the and gate 32 . accordingly , the counting - down operation of the down counter 27 is advanced to &# 34 ; 0 &# 34 ; ( t4 ). then , the previous stage data transfer clock signal ptclk is raised at a rising edge ( t5 ) of the next internal clock signal iclk , as shown in fig1 e , and the counter initialize signal ci becomes &# 34 ; 1 &# 34 ;, as shown in fig1 i . as a consequence , the initialization of the down counter 27 is performed so that the counting - down operation of the down counter 27 is again commenced from 5 . at a subsequent rising edge ( t6 ) of the internal clock signal iclk , the previous stage data transfer clock signal ptclk falls down , as shown in fig1 e . in this way , the data transfer clock signal tclk is changed from &# 34 ; 1 &# 34 ; to &# 34 ; 0 &# 34 ;, as shown in fig1 f , so that the output of the and gate 32 becomes &# 34 ; 1 &# 34 ;. as a result , the output from the adjustment direction designating data register 35 , namely the adjustment direction designating signal adir is equal to &# 34 ; 1 &# 34 ;. therefore , the eor gate 34 outputs &# 34 ; 0 &# 34 ; as the selection signal sel , as shown in fig1 h . then , the multiplexer 29 selects the output of &# 34 ; 1 &# 34 ; on the &# 34 ; 0 &# 34 ; side in the comparator 28 in response to the selection signal sel , as shown in fig1 c , so that the countdown operation by the down counter 27 is advanced to &# 34 ; 1 &# 34 ; ( t7 ). at the next rising edge ( t8 ) of the internal clock signal iclk , the previous stage data transfer clock signal ptclk is raised , as shown in fig1 e . thus , the counter initialize signal ci becomes &# 34 ; 1 &# 34 ;. accordingly , the content of the down counter 27 is initialized in response to the counter initialize signal ci in such a manner that the counting - down operation is again commenced from &# 34 ; 5 &# 34 ;, as shown in fig1 b . in other words , the counting - down operation of the down counter 27 is accomplished to have a count value smaller by &# 34 ; 1 &# 34 ; than in a case that the selection signal sel becomes &# 34 ; 1 &# 34 ;. at a subsequent rising edge ( t9 ) of the internal clock signal iclk shown in fig1 a , the previous stage data transfer clock signal ptclk falls down as shown in fig1 e , and the counter initialize signal ci also becomes &# 34 ; 0 &# 34 ; as shown in fig1 i . as a result , the counting - down operation by the down counter 27 is commenced , and at the same time , the data transfer clock signal is changed to &# 34 ; 1 &# 34 ; as shown in fig1 f . the content of the shift register 25 is shifted by 1 bit , and the adjusted period designating signal is returned to &# 34 ; 0 &# 34 ; as shown in fig1 g . thus , the generating operation of the data transfer clock signal tclk for 1 time period in a case that the adjusted period designating signal becomes &# 34 ; 1 &# 34 ; is accomplished . in this case , one time period of the data transfer clock signal tclk becomes 11 (= 6 + 5 ) periods of the internal clock signal iclk . in the generating operation of the data transfer clock signal tclk for the next 1 time period , the adjusted period designating bit signal adj becomes &# 34 ; 0 &# 34 ; as shown in fig1 g . also , the counting - down operation of the down counter 27 is advanced to 0 , as shown in fig1 b . therefore , 1 time period for the data transfer clock signal tclk is equal to 12 (= 6 + 6 ) period of the internal clock signal in this case . fig1 is a block diagram illustrating the clock signal adjusting unit according to the second embodiment of the present invention . referring now to fig1 , the clock signal adjusting unit will be described . in accordance with the second embodiment , the adjusted period designating bit signal adj is outputted by an n - bit cyclic shift register 125 . when the stand - by signal sb is &# 34 ; 1 &# 34 ;, an n - bit adjusted period designating data is set from the cyclic shift register 124 and functions an initial value of the cyclic shift register 125 . fig1 shows an embodiment of the n - bit cyclic shift register 125 . referring to fig1 , this n - bit cyclic shift register 125 has the structural different point from the above - explained 12 - bit shift register 25 in the first embodiment . that is , the adjusted period designating signal is fed back to an input of the most significant bit ( msb ) register . in a case that &# 34 ; n &# 34 ; is selected to be smaller than , or equal to 11 , when one character , namely data of 12 etu is transferred , the same value is used more than two times as the value of the adjusted period designating data . for example , in the case that &# 34 ; n &# 34 ; is equal to &# 34 ; 4 &# 34 ;, the 4 - bit adjusted period designating bit data adj in the register 125 is repeatedly used three times while one character , namely data of 12 etu is transferred . 2 to 12 may be selected for possible values of &# 34 ; n &# 34 ;. the larger this &# 34 ; n &# 34 ; value becomes , the more precisely the communication time period can be controlled . to the contrary , the more precisely the communication time period is controlled , the larger the circuit scale becomes . for example , it is supposed that this &# 34 ; n &# 34 ; value is larger than &# 34 ; 8 &# 34 ; in a case that the connection to the control unit 52 such as the cpu is realized by a data bus having an 8 - bit width . in this case , the data access operation to the control unit 52 must be carried out at least two times in order to set the adjusted period designating data in the cyclic shift register 125 . as a consequence , if this &# 34 ; n &# 34 ; value is selected to be smaller than 8 , then there is an effect that the access time to the control unit 52 such as the cpu can be reduced . also , when this &# 34 ; n &# 34 ; value is equal to 12 , the same effect as that of the first embodiment can be achieved . therefore , this second embodiment may be considered as the generic mode of the first embodiment . it should also be noted that the adjusted period designating data set to the n - bit register 124 can be conducted by repeatedly performing the processing shown in fig6 in a similar case that n = 12 , namely the first embodiment &# 34 ; m (= 12 / n )&# 34 ; times . next , a clock signal adjusting unit according to a third embodiment of the present invention will now be explained with reference to fig1 . in fig1 , an address is designated by a rom address designating register 226 and an output from a rom table 224 , namely the data output of the rom table 224 from the designated address may determine the adjusted period designating data apd for the n - bit cyclic shift register 125 and the adjustment direction designating data adir . in this example , the control unit 52 does not calculate any value for the cyclic shift register 125 , but simply enters the ratio of data transfer clock signal period to card operation clock signal period , which is obtained in the initial response , into the rom address register 226 . as a consequence , there is a merit that the calculation workload by the control unit 52 can be reduced . also , in the third embodiment of the present invention , the present invention is not limited to the case of the interface apparatus for the ic card equipped with external terminals , but may be modified . for instance , the adjustment period designating data is previously set to all bits of the character of the transfer data , so that a clock signal having the bit length other then 12 - bit length can be generated from the internal clock signal , and may be controlled in a similar manner to that of the above - described embodiment . as described above , according to the present invention , each of period s of the data transfer clock signal period is controlled based upon the ratio of data transfer clock signal period to card operation clock signal period . accordingly , it is possible to prevent the data from being erroneously transferred due to the accumulated errors in the data transfer clock signal tclk . as a result , it is possible to use the clock signal source having a low frequency which is not equal to a frequency integer times higher than the data transfer rate . therefore , there are advantages that the selectable range of the clock signal source can be enlarged , and also the electromagnetic interference to external appliances can be reduced . also , since each of the periods of the clock signal periods of the data transfer are controlled , the circuit arrangement can be digitalized . as a consequence , there are further merits that the power consumption can be reduced , and the interface apparatus can be made compact and also can be highly integrated .