fig3 depicts a divide - by - five circuit 300 that divides a pair of complimentary clock signals c and cb by five . like circuit 100 of fig1 circuit 300 employs differential signaling to improve performance . circuit 300 differs from circuit 100 , however , in that the logic associated with nor gates 105 of fig1 is incorporated into a single flip - flop 305 adapted to receive two pairs of complimentary inputs d 0 , d 0 b and d 1 , d 1 b . the operation of an embodiment of flip - flop 305 is detailed below in connection with fig6 . circuit 300 also includes a number of flip - flops 310 that are modified in accordance with the invention to improve speed performance . finally , circuit 300 includes a differential to single - ended converter 315 . flip - flops 310 and converter 315 are described below in connection with fig4 , and 7 . fig4 depicts a flip - flop 400 that is an embodiment of flip - flop 310 of fig3 . flip - flop 400 includes an input stage ( left ) and an output stage ( right ). the input stage includes a pair of differential transistors 400 and 405 , the control inputs of which are connected to respective complementary data inputs d and db . the output terminals x 1 and x 2 of the input stage connect to respective control terminals of a pair of differential transistors 410 and 415 in the output stage . the input and output stages include respective cross - coupled pmos transistor loads 420 and 425 . the input stage includes an nmos transistor 430 x having one current handling terminal connected to output terminal x 1 and the other connected to output terminal x 2 . the control input ( gate ) of transistor 430 is connected to the clock signal cb . the output stage likewise includes a transistor 435 , one current - handling terminal of which is connected to output terminal q , the other current - handling terminal to output terminal qb . the control terminal of transistor 435 is connected to clock signal c . in another embodiment , one of transistors 430 and 435 is substituted with a pmos transistor , allowing both control terminals associated with transistors 430 and 435 to be controlled by the same clock signal . fig5 is a waveform diagram 500 depicting exemplary signals associated with the operation of flip - flop 400 of fig4 . diagram 500 depicts complimentary clock signals c and cb , data signals d and db , input - stage output signals x 1 and x 2 , and output terminals q and qb . the various node labels refer to both the signal and the corresponding circuit node . whether a given designation refers to a node or a signal will be clear from the context . prior to time t0 , clock signal cb is high , so transistor 430 connects output terminals x 1 and x 2 of the input stage of flip - flop 400 . the logic 0 input on the differential terminals d and db consequently produces only a relatively small voltage difference across terminals x 1 and x 2 . though limited by the on resistance of transistor 430 , the voltage across terminals x 1 and x 2 does reflect a logic 0 ( i . e ., x 1 & gt ; x 2 ). at time t0 , clock signal cb goes low , turning off transistor 430 to disconnect terminals x 1 and x 2 . the voltage between terminals x 1 and x 2 thus increases , better representing the difference between input signals on terminals d and db . also at time t0 , clock signal c goes high , causing transistor 435 to connect output terminals q and qb . the voltage difference between signals q and qb therefore diminishes . though limited by the on resistance of transistor 435 , the voltage across terminals q and qb continues to reflect a logic 0 ( i . e ., q & lt ; qb ). next , at time t1 , clock signal c returns low and complimentary clock signal cb returns high . respective transistors 430 and 435 consequently change states , so that terminals x 1 and x 2 are once again connected and terminals q and qb are disconnected . in this new state , terminals x 1 and x 2 begin to approach one another and output terminals q and qb swing away from one another to reflect the differential input signals to transistors 410 and 415 . before the receipt of a new data bit on differential input terminals d and db , the pairs of output terminals x 1 , x 2 and q , qb approach one another to limit the maximum amount of voltage swing required to move the differential output signal to the next logic bit . for example , the logic level expressed on output terminals q and qb from time t2 to time t4 switches from a logic 0 to a logic 1 , and therefore requires a maximum voltage swing for each of output terminals q and qb . the present invention expedites the time required to make this transition by beginning to bring qb low and q high prior to receipt of the data signal indicating the logic transition . the resulting reduction in the maximum voltage swing required to change the logic level expressed on terminals q and qb reduces the maximum amount of time required to make logic transitions on terminals q and qb . this embodiment of the invention thus speeds the logic transitions on the outputs of flip - flop 310 . as illustrated between times t4 and t6 , the voltage difference between terminals q and qb is reduced even if the next data bit turns out to be the same logic level as the one presently represented . this is because flip - flop 400 cannot anticipate the next logic level , and consequently must prepare for either of the two alternatives . flip - flop 400 therefore requires some amount of time to “ transition ” between two logic zeroes or two logic ones . the overall speed of flip - flop 400 increases because the time required to transition between different logic levels is reduced . reducing the time required for flip - flop 400 to transition between different logic levels translates directly into improved speed performance . moreover , as compared with flip - flop 110 ( fig2 ), flip - flop 400 has far fewer transistors , and can therefore be implemented using less die area . these changes also result in significantly reduced power consumption for a given level of speed performance . fig6 depicts a flip - flop 600 that may be used in place of flip - flop 305 ( fig3 ) in one embodiment of the invention . flip - flop 600 is largely similar to flip - flop 310 of fig4 like numbered features being identical . due to the similarities of flip - flop 600 and flip - flop 310 , a detailed description of flip - flop 600 is omitted for brevity . flip - flop 600 is modified in accordance with an embodiment of the invention to receive two pairs of differential inputs d 0 , d 0 b and d 1 , d 1 b . as noted above in connection with fig1 nor gates 105 impose some delay that slows the maximum operating speed of circuit 100 of fig1 . flip - flop 600 incorporates a pair of logic gates 605 and 610 that eliminate the need for nor gates 105 , and therefore speed up divide - by - five circuit 300 of fig3 . gate 605 , composed of a pair of transistors 615 and 620 , performs a nor function of inputs d 0 and d 1 ; a pair of serial - connected transistors 625 and 630 within gate 610 performs a nand function of input signals d 0 b and d 1 b . as shown in fig5 the data output on complimentary output terminals q and qb fluctuates even when the data signal does not . fig7 depicts a differential circuit that can be used as circuit 315 of fig3 to convert the differential signal on terminals q and qb of the last flip - flop 310 in circuit 300 into full - swing , stable differential output signals . while the present invention has been described in connection with specific embodiments , variations of these embodiments will be obvious to those of ordinary skill in the art . for example , the invention can be adapted for use with other types of sequential logic elements , such as single - stage latches , toggle flip - flops , a j - k flip - flops , and - input flip - flops , or xor - input flip - flops . moreover , some components are shown directly connected to one another while others are shown connected via intermediate components . in each instance , the method of interconnection establishes some desired electrical communication between two or more circuit nodes , or terminals . such communication may often be accomplished using a number of circuit configurations , as will be understood by those of skill in the art . therefore , the spirit and scope of the appended claims should not be limited to the foregoing description .