with reference in particular to fig1 , a non - volatile memory device 100 ( for example , consisting of a flash e 2 prom ) is illustrated . the memory device 100 is integrated in a chip of semiconductor material , and includes a matrix 105 of memory cells mc . each memory cell mc includes a floating gate mos transistor with a programmable threshold voltage vthc . the memory cell mc in a non - programmed ( or erased ) condition exhibits a low threshold voltage . the memory cell mc is programmed by injecting electric charge into its floating gate ; the memory cell mc can be programmed to multiple levels , each one associated with a corresponding range of its threshold voltage vthc . each level represents a different logical value ; for example , the memory device 100 operates at 4 levels , so that each memory cell mc stores a logical value consisting of 2 bits of information ( 11 , 10 , 01 and 00 for increasing threshold voltages vthc ). the matrix 105 includes one or more sectors ( only one shown in the figure ), which can be erased individually . each sector is associated with three reference cells mr 0 , mr 1 and mr 2 that are used for discriminating the logical values stored in the memory cells mc . for this purpose , the threshold voltages of the reference cells mr 0 , mr 1 and mr 2 ( denoted with vthr 0 , vthr 1 and vthr 2 ) are set to predefined values between the levels of the logical values 11 - 10 , 10 - 01 and 01 - 00 , respectively . in the example at issue , the matrix 105 has a so - called nor architecture . particularly , the drain terminals of the memory cells mc of each column are connected to a corresponding bit line bl , whereas the control gate terminals of the memory cells mc of each row are connected to a corresponding word line wl ; the source terminals of all the memory cells mc are connected to a common terminal providing a reference voltage ( or ground ). the memory device 100 simultaneously processes a word ( for example , consisting of 16 bits ). the bits of each word are stored in a page of memory cells mc ( 16 / 2 = 8 in the example at issue ), which are associated with a single word line wl ; the bit lines bl of the matrix 105 are grouped into 8 sub - sets , each one for a memory cell mc of the different pages . likewise , the drain terminals of the reference cells mr 0 , mr 1 and mr 2 are connected to a bit line blr 0 , blr 1 and blr 2 , respectively . the control gate terminals of all the reference cells mr 0 - mr 2 are connected to a common word line wlr , whereas their source terminals are connected to the ground terminal . the memory device 100 receives an address adr for accessing a corresponding page . a portion of the address adr is supplied to a row decoder 110 r , which selects the desired word line wl . another portion of the address adr is supplied to a column decoder 110 c , which selects the desired bit line bl in each sub - set . the memory device 100 further includes a counter 115 , which is continuously incremented with a predefined frequency ( after being reset at the beginning of every operation on the memory device 100 ); the value in the counter 115 is supplied to a digital - to - analog converter ( dac ) 120 , which outputs a biasing voltage having a ramp - like pattern ( i . e ., with its value that increases linearly over time according to a constant slope ). the row decoder 110 r couples the selected word line wl with the dac 120 , so as to apply the biasing voltage to the control gate terminals of the selected memory cells mc . the same biasing voltage is also applied to the word line wlr ( and then to the control gate terminals of the reference cells mr 0 - mr 2 ) through a driver 125 . the column decoder 110 c connects the selected bit lines bl to a bank of sense amplifiers 130 . the sense amplifiers 130 are also connected to the bit lines blr 0 , blr 1 and blr 2 through switches 135 0 , 135 1 and 135 2 , respectively . moreover , the sense amplifiers 130 receive a comparison current icomp ; the comparison current icomp is provided by a direct current generator 140 , and has a value lower than the current flowing through every ( memory or reference ) cell mc , mr 0 - mr 2 when conductive ( for example , about 5 - 20 μa ). as described in detail in the following , the sense amplifiers 130 compare the currents provided by the selected memory cells mc and by the reference cells mr 0 - mr 2 with the current icomp , so as to detect their turning on . this information is supplied to a logic unit 145 , which determines the condition of each selected memory cell mc according to the temporal relation of the relevant turning on times . considering now fig2 a , in an embodiment of the invention the sense amplifiers 130 include the same structure for each selected memory cell ; particularly , this structure is formed by a comparator 205 c for the memory cell and three comparators 205 r 0 , 205 r 1 and 205 r 2 for the reference cells . particularly , the non - inverting input terminal of the comparator 205 c receives a cell current ic flowing through the selected bit line bl ( and then through the selected memory cell ); on the other hand , the non - inverting input terminals of the comparators 205 r 0 , 205 r 1 , and 205 r 2 receive a reference current ir 0 , ir 1 and ir 2 flowing through the bit lines blr 0 , blr 1 and blr 2 , respectively ( and then through the corresponding reference cells ). the inverting input terminals of all the comparators 205 c , 205 r 0 - 205 r 2 instead receive the comparison current icomp . the output terminals of the comparators 205 c , 205 r 0 , 205 r 1 and 205 r 2 provide a bit sc , sr 0 , sr 1 and sr 2 , respectively ; the bits sc , sr 0 - sr 2 are asserted ( for example , at the logical value 1 ) when the corresponding currents ic , ir 0 - ir 2 exceed the comparison current icomp . the output terminals of the comparators 205 r 0 , 205 r 1 and 205 r 2 are connected to corresponding latches 210 r 0 , 210 r , and 210 r 2 through switches 215 0 , 215 1 and 215 2 , respectively . alternatively , the same output terminals are connected to the latches 210 r 0 , 210 r 1 and 210 r 2 by means of identical delay blocks 220 through further switches 225 0 , 225 1 and 225 2 , respectively . the blocks 220 delay the application of the bits sr 0 - sr 2 to the latches 210 r 0 - 210 r 2 by a predetermined value & lt ; t ; preferably , trimming elements ( not shown in the figure ) are used to regulate the delay & lt ; t to the desired value . for example , the delay & lt ; t can be of about 0 . 2 - 2 ns ; as it will be apparent in the following , this value corresponds to a voltage difference along the ramp of the biasing voltage of 20 - 200 mv ( assuming a slope of 100 * 10 6 v / s ). all the switches 225 0 - 225 2 are controlled by an enabling signal en , while all the switches 215 0 - 215 2 are controlled by its negated value en . on the other hand , the latches 210 r 0 - 210 r 2 are controlled by the bit sc provided by the comparator 205 c . the bits sr 0 - sr 2 stored in the latches 210 r 0 - 210 r 2 are then supplied to the logic unit 145 . considering now fig2 a and 2 b together , the biasing voltage ( v ) increases over time ( t ) from the value 0v to a maximum value higher than the threshold voltage vthr 2 ( of the last reference cell ). during a read operation , the enabling signal en is deasserted ; therefore , the switches 215 0 - 215 2 are closed and the switches 225 0 - 225 2 are open . in this condition , when the biasing voltage reaches the threshold voltage vthr 0 at the time tr 0 , the first reference cell turns on ; therefore , as soon as the corresponding reference current ir 0 reaches the comparison current icomp , its bit sr 0 is asserted . the other bits sr 1 and sr 2 are asserted in succession when the biasing voltage reaches the threshold voltage vthr 1 at the time tr 1 and the threshold voltage vthr 2 at the time tr 2 , respectively . likewise , the bit sc is asserted when the biasing voltage reaches the threshold voltage vthc of the memory cell to be read at the time tc . as a result , the current values of the bits sr 0 - sr 2 are stored into the corresponding latches 210 r 0 - 210 r 2 ; the conditions of the latches 210 r 0 - 210 r 2 when the bit sc is asserted uniquely identify the logical value stored in the memory cell . particularly , if the time tc precedes the time tr 0 all the values in the latches 210 r 0 - 210 r 2 are deasserted ; this means that the threshold voltage vthc is lower than the threshold voltage vthr 0 and the memory cell stores the logical value 11 . in a similar manner , if the time tc is comprised between the times tr 0 - tr 1 ( value in the latch 210 r 0 asserted and values in the latches 210 r 1 - 210 r 2 deasserted ) or the times tr 1 - tr 2 ( values in the latches 210 r 0 - 210 r 1 asserted and value in the latch 210 r 2 deasserted ) the memory cell stores the logical values 10 or 01 , respectively . if the time tc follows the time tr 2 ( all the values in the latches 210 r 0 - 210 r 2 asserted ) or the bit sc is not asserted when the biasing voltage reaches its maximum value ( higher than the threshold voltage vthr 2 ), the memory cell stores the logical value 00 . it should be noted that once the bit sc has switched ( and the values of the bits sr 0 - sr 2 have been stored into the corresponding latches 210 r 0 - 210 r 2 ), the memory and reference cells can be turned off by means of the column decoder and the associated switches , respectively ( so as to reduce the power consumption of the memory device and any noise caused by the current drained from the common ground terminal ). similar considerations apply if the bit sr is stored into all the latches 210 r 0 - 210 r 2 in response to the respective bits sr 0 - sr 2 . with reference instead to fig2 a with fig2 c , let us consider a program - verify operation relating to a specific logical value ( for example , the one corresponding to the reference cell with the threshold voltage vthr 1 ). in this condition , only this reference cell is taken into consideration ; at the same time , the enabling signal en is now asserted , so that the switch 225 1 is closed and the switch 215 1 is open . as in the preceding case , the bit sr 1 is asserted at the time tr 1 when the biasing voltage reaches the threshold voltage vthr 1 . however , the bit sr 1 now reaches the latch 210 r 1 after the delay & lt ; t introduced by the block 220 . the assertion of the bit sr 1 can thus be stored into the latch 210 r 1 ( in response to the bit sc ) only after the time tv 1 = tr 1 +& lt ; t . as clearly shown in the figure , this delay & lt ; t is equivalent to a corresponding increase of the threshold voltage of the reference cell ; therefore , the ( delayed ) bit sr 1 emulates a further reference cell with a different threshold voltage ( denoted with vthv 1 ); particularly , the threshold voltage vthv 1 is equal to the threshold voltage vthr 1 with a margin that is always positive . a different embodiment of the invention is illustrated in fig3 ( in the following , the elements corresponding to the ones shown in the preceding figures will be denoted with the same references and their explanation will be omitted for the sake of brevity ). in this case , the value in the counter 115 ( which is used to generate the ramp - like biasing voltage ) is supplied to a buffer 310 c for each selected memory cell ( only one shown in the figure ) and to three buffers 310 r 0 , 310 r 1 and 310 r 2 for the reference cells . the bit sc enables the buffer 310 c to store the value in the counter 115 ; the bits sr 0 - sr 2 control the corresponding buffers 310 r 0 - 310 r 2 in a similar way . the buffer 310 c is directly connected to the logic unit 145 . on the other hand , the buffers 310 r 0 , 310 r 1 and 310 r 2 are connected to the logic unit 145 through switches 315 0 , 315 1 and 315 2 , respectively . the same buffers 310 r 0 , 310 r 1 and 310 r 2 are also connected to an input terminal of corresponding adders 320 r 0 , 320 r 1 and 320 r 2 ; another input terminal of the adders 320 r 0 - 320 r 2 receives an offset & lt ; c from a common register 322 , which offset & lt ; c can be customized to the desired value ( either positive or negative ). the adders 320 r 0 , 320 r 1 and 320 r 2 are connected to the logic unit 145 through further switches 325 0 , 325 1 and 325 2 , respectively . all the switches 325 i are controlled by the same enabling signal en , while all the switches 315 i are controlled by its negated value en . as in the preceding case , during a read operation the enabling signal en is deasserted ; therefore , the switches 315 i are closed and the switches 325 i are open . in this condition , when the bits sr 0 , sr 1 and sr 2 are asserted at the times tr 0 , tr 1 and tr 2 , respectively , the corresponding values in the counter 115 ( denoted with cr 0 , cr 1 and cr 2 ) are stored into the buffers 310 r 0 , 310 r 1 and 310 r 2 , respectively . likewise , when the bit sc is asserted at the time tc the corresponding value in the counter 155 ( denoted with cc ) is stored into the buffer 310 c . therefore , if the value cc is lower than the value cr 0 , the memory cell stores the logical value 11 , if the value cc is comprised between the values cr 0 - cr 1 or cr 1 - cr 2 the memory cell stores the logical values 10 or 01 , respectively , and if the value cc is higher than the value cr 2 the memory cell stores the logical value 00 . conversely , during a program - verify operation ( relating to the same reference cell as in the preceding case ) the enabling signal en is asserted , so that the switch 225 , is close and the switch 215 , is open . in this case , the value cr 1 that is stored in the buffer 310 r 1 is now updated ( i . e ., increased or decreased ) according to the offset & lt ; c . therefore , the logic unit 145 will receive a value cv 1 = cr 1 +& lt ; c . this offset & lt ; c is equivalent to a corresponding change in the threshold voltage of the reference cell ( i . e ., an increase for a positive offset & lt ; c or a decrease for a negative offset & lt ; c ); it should be noted that in this embodiment it is now possible to emulate a further reference cell having a threshold voltage with either a positive margin or a negative margin . as shown in fig4 , a memory device 400 according to a different embodiment of the invention is illustrated . in this case , each sector of the memory device 400 is associated with a structure being equivalent to a single reference cell ( denoted with mr ). the reference cell mr includes multiple basic elements br i ( with i = 0 . . . n , for example , n = 3 - 10 ), each one consisting of a floating gate mos transistor . the drain terminals of the basic elements br i are connected to a common bit line blr ( which is coupled with the sense amplifiers 130 through a switch 135 ). the control gate terminals of all the basic elements br i are connected to the word line wlr , whereas their source terminals are connected to the ground terminal . considering now fig5 a , in an embodiment of the invention based on the delays , each basic element of the reference cell is set to the lowest threshold voltage ( denoted with vthr ) that is required for the operation of the memory device ; typically , the threshold voltage vthr consists of the value that is used during a depletion - verify operation ( for example , 0 - 2v ). for each selected memory cell , the sense amplifiers 130 now include a single comparator 205 r for the reference cell ( in addition to the comparator 205 c for the memory cell ). particularly , the non - inverting input terminal of the comparator 205 r receives a reference current flowing through the bit line blr ( and then through the reference cell ). the reference current is given by the sum of the currents that flow through the corresponding basic elements ; denoting with ib the common value of these basic currents , the reference current is then equal to n * ib . moreover , the comparison current icomp is now provided to the sense amplifiers 130 through a current mirror 505 . the current mirror 505 includes an input leg that is formed by an nmos transistor mi . the transistor mi has the drain terminal connected to the current generator 140 ( for receiving the comparison current icomp ); the transistor mi has the gate terminal short - circuited to its drain terminal , and the source terminal connected to the ground terminal . for each selected memory cell , the current mirror 505 further includes a cell output leg ( for the memory cell ) and a reference output leg ( for the reference cell ). particularly , the cell output leg and the reference output leg are formed by an nmos transistor moc and an nmos transistor mor , respectively . the transistors moc , mor have the gate terminals connected to the gate terminal of the transistor mi and the source terminals connected to the ground terminal . the drain terminal of the transistor moc is connected to the inverting input terminal of the comparator 205 c , and the drain terminal of the transistor mor is connected to the inverting input terminal of the comparator 205 r . the transistors mi and moc are dimensioned so that a mirroring factor between the input leg and the cell output leg is equal to 1 . therefore , the comparator 205 c will receive the same comparison current icomp . conversely , the transistors mi and mor are dimensioned so that a mirroring factor between the input leg and the reference output leg is equal to n . therefore , the comparator 205 r will receive a multiplied comparison current equal to n * icomp . the output terminal of the comparator 205 r is now connected to multiples latches . particularly , the output terminal of the comparator 205 r , providing a bit sr , is directly connected to a latch 510 r . the same output terminal is instead connected to further latches 510 d j ( with j = 0 . . . m , for example , m = 2 - 15 ) through corresponding delay blocks 520 j . each delay block 520 j applies a corresponding bit sd j to the latch 510 dj . the bit sd j is delayed with respect to the bit sr by a value & lt ; t j ; preferably , the delays & lt ; t j can be trimmed to the desired values either individually or as a whole ( for example , proportionally to their values ). for example , the delays & lt ; t j can be in the range from 0 . 2 ns to 60 ns , for a voltage difference along the ramp of the biasing voltage between 20 mv and 6v ( again assuming a slope of 100 * 10 6 v / s of the ramp ). as in the preceding case , all the latches 510 r , 510 dj are controlled by the bit sc provided by the comparator 205 c . considering now fig5 a and 5 b together , when the biasing voltage reaches the threshold voltage vthr at the time tr , the basic elements of the reference cell turn on ; therefore , as soon as the corresponding reference current n * ib reaches the multiplied comparison current n * icomp , the bit sr is asserted . the other bits sd j are asserted in succession at the times td j = tr +& lt ; t j . when the bit sc is asserted , the current values of the bits sr , sd j are stored into the corresponding latches 510 r , 510 d j . as clearly shown in the figure , each delay & lt ; t j is then equivalent to a corresponding increase of the threshold voltage of the reference cell . therefore , the ( delayed ) bits sd j emulate further reference cells with different threshold voltages ( denoted with vthd j ). the threshold voltages vthd j can be set to any desired value higher than vthr ( for example , for the erase - verify operation , the read operation , the program - verify operation , and the refresh operation ); naturally , the logic unit of the memory device will exploit one or more of the available bits sr , sd j at any time , according to the operation in progress . with reference instead to fig6 , in a different embodiment of the invention based on the offsets , each basic element of the single reference cell is preferably in the erased , or ultra - violet ( uv ), condition ( i . e ., without any charge in its floating gate and then with a threshold voltage of about 3 . 0 - 4 . 0 v ). the sense amplifiers 130 now include a single buffer 310 r for the reference cell ( in addition to the buffer 310 c for each selected memory cell ); the bit sr ( provided by the comparator 205 r ) enables the buffer 310 r to store the value in the counter 115 ( while the bit sc controls the buffer 310 c as above ). both the buffer 310 c ( providing the value cc ) and the buffer 310 r ( providing a value denoted with cr ) are directly connected to the logic unit 145 . the buffer 310 r is also connected to an input terminal of a plurality of adders 620 j ; another input terminal of each adder 620 j receives an offset & lt ; c j from a corresponding register 622 j , which offset & lt ; c j can be customized to the desired value ( either positive or negative ). each adder 620 j supplies a corresponding value cd j = cr +& lt ; c j to the logic unit 145 . as in the preceding case , as soon as the bit sr is asserted ( when the biasing voltage reaches the threshold voltage of the basic elements of the reference cell ), the corresponding value cr in the counter 115 is stored into the buffers 310 r . at the same time , the adders 620 j calculate the other values cd j by adding the respective offsets & lt ; c j to the value cr . the values cd j are equivalent to corresponding increments or decrements of the threshold voltage of the reference cell ; therefore , they emulate further reference cells with different threshold voltages ( which are selectively exploited by the logic unit of the memory device according to the operation in progress ). naturally , in order to satisfy local and specific requirements , a person skilled in the art may apply to the solution described above many modifications and alterations . particularly , although the present invention has been described with a certain degree of particularity with reference to preferred embodiments thereof , it should be understood that various omissions , substitutions and changes in the form and details as well as other embodiments are possible ; moreover , it is expressly intended that specific elements and / or method steps described in connection with any disclosed embodiment of the invention may be incorporated in any other embodiment as a general matter of design choice . for example , similar considerations apply if the memory device has a different structure or includes equivalent components . in addition , the application of the proposed solution to different non - volatile memory devices ( such as e 2 proms , flash memories with nand architecture , phase - change memories ), or even to other memory devices ( such as drams ) is contemplated ; in any case , the principles of the invention should not be limited to a multi - level memory device ( but they also apply to standard memory devices wherein each memory cell stores a single bit ). moreover , the numerical examples described above are merely illustrative and must not be interpreted in a limitative manner . alternatively , the ramp - like biasing voltage can be generated in another way ( for example , by means of an analog generator or by applying a direct current to the selected memory cells and to the reference cells ); similar considerations apply if the biasing voltage has a different monotone time pattern ( either increasing or decreasing over time ). alternatively , the values stored in the memory cells can be determined with equivalent techniques based on the temporal order of their turning on with respect to the ones of the reference cells ( for example , with a single latch for each reference cell and the addition of a further latch for each memory cell ). in any case , the solution according to the present invention lends itself to be implemented with any equivalent means for delaying the provision of the relevant bit ( s ) to the logic unit . in a different embodiment of the invention , the time required by the reference current ( s ) to reach the comparison current is measured in a different way ( for example , by using a dedicated counter controlled by an oscillator , which counter is reset at the enabling of the ramp generator ); moreover , the adder ( s ) can be replaced with an equivalent structure ( for example , by implementing the same operations in the logic unit directly ). in both cases , different delays / offsets can be provided for each reference cell ( even with those delays / offsets that are set dynamically to different values according to the desired reference thresholds ); in this way , for example , it is possible to compensate any intrinsic difference among the sense amplifiers ( such as due to any asymmetry in the routing of the corresponding signals ). the enabling / disabling of the proposed structure with equivalent solutions is contemplated . moreover , the above - described implementations of the invention based on a single delay / offset for each reference cell are also applicable to a refresh - operation , or more generally to any other read operation with a ( positive and / or negative ) margin . similar considerations apply when the basic elements of the single reference cell are set to a different threshold voltage . particularly , in the embodiment based on the delays the threshold voltage can consist of the value that is used during the erase - verify operation , or more generally to the required threshold voltage ( either the lowest one or the highest one ) that is closest to a starting value of the biasing voltage . without departing from the principles of the invention , the basic currents can be combined in a different way into the corresponding reference current ; likewise , alternative solutions are tenable for scaling the reference current and / or the comparison current in order to allow their comparison ( for example , by diving the reference current instead of multiplying the comparison current ). moreover , it will be apparent to those skilled in the art that the additional features providing further advantages are not essential for carrying out the invention , and may be omitted or replaced with different features . for example , the application of the proposed solution to the cell currents is not excluded ( even if this implementation is less advantageous , since it requires the replica of the same structure for the number of memory cells that are processed simultaneously ). in any case , the principles of the invention should not be limited to the above - described embodiments based on the delays and on the offsets ; more generally , it is possible to use any suitable means for time shifting the detections ( of the reaching of the comparison current by the reference currents ) to emulate the comparison with one or more further reference cells . moreover , it is possible to emulate any other reference cell from the ones relating to the read operation ( such as the reference cells for the depletion - verify and / or the erase - verify operation from the one relating to the logical value 11 ). in a different embodiment of the invention , all of the reference cells of the memory device are emulated from two or more reference cells available ( either in the solution based on the delays or in the solution based on the offsets ); for example , it is possible to have a reference cell with the lowest threshold voltage ( for example , 2v ) and another reference cell with the highest threshold voltage ( for example , 6v ) for operation of the memory device . alternatively , the setting of the threshold voltage of the single reference cell to the value corresponding to any other operation is contemplated . at the end , nothing prevents the implementation of the single reference cell with one transistor only .