fig1 shows an exemplary voltage comparator 2 constructed in accordance with one embodiment of the present invention . the input voltages v 1 and v 2 that are to be compared are selectively coupled to the gate of a first mos transistor 3 via switches 4 and 5 , respectively . that is , the input voltages v 1 and v 2 may be sequentially directed to the gate of the first transistor 3 by alternately closing and opening the switches 4 and 5 . the first mos transistor 3 has its source terminal connected to a first voltage supply v ss that is , for example , at ground potential . the drain of the first transistor 3 is coupled to the drain of a second mos transistor 6 . the source of the second mos transistor 6 is connected to a second voltage supply v dd that is maintained at a higher potential than the first voltage supply v ss . the output terminal 9 of the voltage comparator 2 is connected to a node located intermediate to the drains of the first and second transistors 3 and 6 . the gate of the second mos transistor 6 is selectively coupled to the output terminal 9 via a switch 7 . as one of ordinary skill in the an will recognize , when switch 7 is closed , the second mos transistor is in a diode mounted configuration . the gate of the second mos transistor 6 also may be optionally connected to a capacitor 8 that is in turn connected to a constant reference voltage such as the second voltage supply v dd , for example . the capacitor 8 may be advantageously employed when the parasitic or inherent gate - source capacitance of the second mos transistor 6 is insufficient to maintain the voltage at the gate of the second transistor 6 . the capacitor 8 may be a charge storage device such as a conventional capacitor or a mos transistor in which the capacitance arises between the gate and transistor substrate . the first and second mos transistors 3 and 6 should have opposite polarities . thus , in the exemplary embodiment of the invention shown in fig1 the first mos transistor 3 is an n - mos transistor and the second mos transistor 6 is a p - mos transistor . alternatively , the first mos transistor 3 may be a p - mos transistor and the second mos transistor 6 may be an n - mos transistor . in this latter case the first voltage supply v ss should be at a higher potential than the second voltage supply v dd . in operation , the switches 4 , 5 , and 7 are initially in their open state . switches 4 and 7 are then closed , applying the first input voltage v 1 to the gate of the first transistor 3 . in a mos transistor , the drain - source current i ds depends on the applied gate - source voltage v gs . thus , the input voltage v 1 is in effect transformed into a current i ds ( v 1 ) that flows through the source - drain path of the first transistor 3 . since the first and second transistors 3 and 6 are serially connected , the current i ds ( v 1 ) flowing through the first transistor 3 also flows through the second transistor 6 . the current i ds ( v 1 ) flowing through the second transistor 6 causes a voltage v gs to appear between the gate and source of the second transistor 6 since the second transistor 6 is diode mounted when switch 7 is closed . this voltage is maintained or stored in the second transistor 6 by the parasitic gate - source capacitance of the transistor , and possibly by the capacitor 8 as well , if employed . switch 7 may now be opened and the current i ds ( v 1 ) flowing through the second transistor 6 will be maintained by the stored voltage . in the next operational step , switch 4 is opened and switch 5 is closed so that the second input voltage v 2 is applied to the gate of the first transistor 3 . similar to the step previously described in which the first input voltage v 1 was transformed into a current flowing through the first transistor 3 , the second input voltage v 2 now gives rise to a current i ds ( v 2 ) flowing through the first transistor 3 . thus , a current i ds ( v 1 ) now flows through the second transistor 6 while a current i ds ( v 2 ) flows through the first transistor 3 . if the currents i ds ( v 1 ) and i ds ( v 2 ) are not identical , a difference current will be generated at the output terminal 9 of the comparator 2 . the difference current will bring the unloaded output of the comparator 2 into saturation . that is , the comparator output terminal 9 will provide a voltage equal to one of the supply voltages v ss or v dd when the currents i ds ( v 1 ) and i ds ( v 2 ) are unequal . more particularly , if the current i ds ( v 1 ) is greater than the current i ds ( v 2 ) the comparator output terminal 9 will be at a voltage v dd . if the current i ds ( v 1 ) is less than the current i ds ( v 2 ), the comparator output terminal 9 will be at a voltage v ss . thus , the voltage appearing at the comparator output terminal 9 indicates whether the first input voltage v 1 is greater or less than the second input voltage v 2 . in summary , the comparator undergoes two distinct periods during its operation . in a first period denoted a transfer period , the first input voltage is applied to the comparator , transferred to the second transistor 6 and stored in a capacitor . in a subsequent period denoted a compare period , the second input voltage is applied to the comparator and the comparator generates an output voltage indicating the larger of the first and second input voltages . the comparator 2 may be operated in a variety of modes . in one mode an input voltage , say the first input voltage v 1 , has a constant value over time . in this mode the second input voltage may be continuously applied to the comparator by leaving switch 5 in its closed state after the constant input voltage v 1 has been transferred to the second transistor 6 by first closing and then reopening switches 4 and 7 . in this manner the comparator remains in its compare period so that the second input voltage v 2 is continuously compared to the constant input voltage v 1 . in a second mode of operation the input voltages are variable . in this mode the switches 4 and 7 , operated in unison , must be alternately opened and closed with switch 5 each time a comparison is to be performed so that the comparator 2 alternates between its transfer and compare periods . as a result , new values of the input voltages v 1 and v 2 will be input and compared after the completion of each compare period . the first mode of operation is advantageously employed whenever only one of the input voltages is variable because the dynamic power requirements are less in this mode of operation and because continual switching generates noise . fig2 shows an alternative embodiment of the invention similar to that shown in fig1 except that a source follower comprising serially connected transistors 40 and 41 is inserted between the gate of the first transistor 43 and the switches 44 and 45 . the source follower is used to reduce noise from the first voltage supply v ss , which may occur whenever current is injected into a supply rail with non - zero resistivity . this noise reduction is achieved by applying to the gate of transistor 40 a reference voltage v ref that is immune to noise . the reference voltage v ref may be more readily immunized from noise than the voltage supply v ss because , unlike v ss , the reference voltage v ref only supplies a voltage and does not draw current . as seen in fig2 the source of transistor 40 is connected to the first supply voltage v ss and the drain of the transistor 41 is connected to the second supply voltage v dd . the drain of the transistor 40 is connected to the source of transistor 41 . a reference voltage is supplied to the gate of the transistor 40 and the input voltages v 1 and v 2 undergoing comparison are selectively input to the gate of the transistor 41 via switches 44 and 45 , respectively . the transistors 40 and 41 should be of the same dimensions so that they have the same operational characteristics . the gate of the first transistor 43 is connected to a node located between the drain of transistor 40 and the source of transistor 41 . the following discussion will explain how the comparator shown in fig2 is immunized from noise by the source follower . the voltage at the gate of the first transistor 43 is equal to v in -( v ref - v ss ), where v in is equal to either v 1 or v 2 , depending on whether switch 44 or switch 45 is closed . the voltage at the source of the first transistor 43 is equal to v ss . accordingly , the voltage v gs43 between the gate and source of the first transistor 43 is equal to v in - v ref and thus the input voltage to the first transistor 43 is independent of the supply voltage v ss . the reference voltage should be selected so that it is equal to or greater than the threshold voltage of the transistor 40 so that the transistor 40 remains on . however , as explained below , when the reference voltage increases the range of voltages that may be compared by the comparator decreases . therefore , a reference voltage should be selected that is not much larger than the threshold voltage to maximize the input dynamic range ( i . e ., the lower bound of the voltage v in ) of the comparator . the analysis presented below will explain why the input dynamic range decreases as the reference voltage increases . where v gs41 and v gs43 are the gate - source voltages of transistors 41 and 43 , respectively , and the remaining voltages have been previously defined . the gate - source voltage of transistor 43 must be larger than the threshold voltage so that the transistor does not turn off . that is , rewriting equation ( 3 ) using equations ( 4 ) and ( 5 ) to eliminate v gs41 results in equation ( 6 ) shows that the lowest acceptable value for the input voltages v 1 and v 2 for the comparator shown in fig2 is v ref + v th . therefore , as previously noted , the reference voltage v ref should be minimized to maximize the input dynamic range . in practice of course , the comparator output is loaded and as a result the output voltage will not reach either v dd or v ss when the difference current representing the difference between i ds ( v 2 ) and i ds ( v 1 ) is small . thus , in order to increase the gain and as a consequence the sensitivity of the comparator a cascaded structure such as shown in fig3 may be used . while fig3 shows a two - stage comparator in which two of the fig1 comparators are cascaded together , one of ordinary skill in the art will recognize that in general an n - stage comparator may be used , where n is any desired number of individual comparators which are cascaded together . the comparators shown in fig3 are cascaded together by coupling the output terminal 32 of the first comparator 30 to the gate of the first transistor 34 in the second comparator 31 . the cascaded comparator operates in the same manner as the single stage comparator shown in fig1 except that the switches 35 and 36 respectively connecting the gates of the second transistors in the first and second comparators 30 and 31 to the output terminals 32 and 37 must both be operated in synchronism . the gain of the n - stage comparator equals a 1 a 2 a 3 , . . . a n , where a k is the voltage gain of stage k . the voltage gain a k of stage k is defined as the voltage change that appears at the output of stage k for a given voltage change appearing at the input of stage k ( i . e ., at the gate of the first transistor in stage k ). fig4 shows an alternative embodiment of the invention which employs an operational amplifier 20 . operational amplifiers are well known devices that provide high open loop gain , high input impedance and low output impedance . additional details concerning the characteristics and structure of operational amplifiers are not a pan of this invention and hence will not be discussed further . as seen in fig4 the operational amplifier is coupled to supply voltages v ss and v dd . in contrast to the previous embodiments of the invention , the output of the operational amplifier can swing between almost completely between v ss and v dd . the input voltages v 1 and v 2 are selectively applied to the noninverting input terminal 21 of the operational amplifier 20 via switches 22 and 23 , respectively . the inverting input terminal 24 of the operational amplifier 20 is connected to a capacitor 25 . the capacitor 25 may be a charge storage device such as a conventional capacitor or a mos transistor in which the capacitance arises between the gate and transistor substrate . the capacitor 25 is in turn connected to a constant voltage source , which as illustrated in fig4 may be at ground potential . the inverting input terminal 24 of the operational amplifier 20 is also selectively connectable to the output 26 of the operational amplifier 20 via a switch 27 . the output 26 of the operational amplifier 20 serves as the output of the voltage comparator . the operation of the comparator shown in fig4 is similar to that of the comparator shown in fig1 . that is , the comparator shown in fig4 undergoes both a transfer period and a compare period during its operation . in the transfer period , switches 22 and 27 are both closed . as one of ordinary skill will recognize , the output voltage v out appearing at the output terminal 26 of an operational amplifier may be expressed as follows : where a is an appropriate proportionality constant , v + is the voltage at the noninverting input , v - is the voltage at the inverting input , and v off is an offset voltage inherent in the operational amplifier due to the mismatch between the input transistors . when switches 22 and 27 are closed so that v + = v 1 and v -= v out , this equation reduces to : since a is infinite for an ideal operational amplifier , this equation can be approximated as : as equation ( 9 ) indicates , when switches 22 and 27 are both closed the voltage at the inverting input terminal 24 equals the first input voltage v 1 offset by the voltage v off . this voltage at the inverting input will appear across the capacitor 25 . in the second pan of the transfer period switch 27 is opened so that the voltage v 1 + v off is stored across the capacitor 25 . in the compare period of operation switch 22 is opened and switch 23 is closed so that the second input voltage v 2 appears at the noninverting input terminal v + . substituting into equation 7 the voltages presently appearing at the positive and negative input terminals yields : accordingly , the output voltage v out is independent of the offset voltage v off and the sign of the output voltage v out indicates the larger of the two input voltages . more particularly , as with the first embodiment of the invention , the output voltage v out will equal one of the supply voltages v ss or v dd supplied to the operational amplifier depending on whether v 1 or v 2 is the larger voltage . an n - stage comparator may be formed by cascading together two or more of the single stage comparators shown in fig4 in the same manner shown in fig3 . that is , the output of each operational amplifier is coupled to the noninverting input of the succeeding operational amplifier as shown in fig5 . the embodiments of the invention shown in fig1 - 3 may be fabricated from discrete mos transistors . alteratively , these embodiments may be fabricated as a monolithic device using a conventional digital complementary metal oxide semiconductor ( cmos ) process . the embodiment of the invention shown in fig4 employing an operational amplifier may be fabricated by any conventional process , including bipolar or cmos processes , or a combination thereof .