as described above , if a programmable logic device includes a specialized functional circuit that in turn includes elements that may or may not be used , then if those elements are not used , even though the specialized functional circuit is used , changing signals within the specialized functional circuit may cause components of the unused elements to charge and discharge , consuming power . moreover , those components may generate signals that cause other circuit elements in the specialized functional circuit to change state and consume power . the present invention overcomes the aforementioned disadvantage by turning off components of unused circuit elements , or by forcing the output of an unused circuit element into a particular state , so that it does not cause switching of components of other unused circuit elements , which might cause unnecessary switching , and therefore unnecessary power consumption , in the programmable logic device . in the case of turning off a component , that might be accomplished as simply as by interrupting the component &# 39 ; s power supply . similarly , in the case of forcing an output into a particular state , that might be accomplished by replacing a gate with a slightly modified gate that can accept an extra input to force a particular output . fig1 shows a portion of a programmable logic device 10 incorporating the claimed invention . programmable logic device 10 preferably includes a plurality of regions 11 , 12 of programmable logic , and a specialized functional region 13 . preferably , outputs of programmable logic region 11 are inputs to specialized functional region 13 , while outputs of specialized functional region 13 are inputs to programmable logic region 12 . however , other configurations are possible in which specialized functional region 13 either accepts inputs directly from input pins ( not shown ) of programmable logic device 10 or generates outputs that connect directly to output pins ( not shown ) of programmable logic device 10 . as shown in fig2 in a preferred embodiment , specialized functional region 13 is a multiplier / accumulator region preferably capable of performing addition , subtraction , multiplication , and accumulation of the results of those operations . such a specialized function region may be referred to as a multiplier - accumulator (“ mac ”) block because the results of several multiplications 20 may be accumulated by adders 21 , or as a “ dsp ” block because it is useful for digital signal processing . the provision of such blocks is described in more detail in copending , commonly - assigned application ser . no . 09 / 955 , 645 , filed concurrently herewith , which is hereby incorporated by reference herein in its entirety . as seen in fig3 which shows more detail of mac block 13 , it is possible using multiplexers 34 to select the output of one of multipliers 30 as the output of block 13 , in which case all of adders 31 , 32 , 33 would remain unused , but would still receive inputs and consume power . alternatively , it is possible using multiplexers 35 to select the output or outputs of one or both of adders 31 , 32 as the output of mac block 13 , in which case adder 33 would remain unused , but would still receive inputs and consume power . either way , one or more of adders 31 - 33 would be consuming power . in the preferred embodiments shown , mac block 13 accepts multiple - bit inputs . accordingly , as shown in fig4 a representative one 40 of adders 31 - 33 actually includes a plurality of adder stages 41 . in such an arrangement , if the first one 410 of adder stages 41 could be disconnected or turned off , the subsequent adder stages 41 would not receive input signals , and therefore would not switch or consume significant power . a preferred embodiment of adder stage 410 is shown in more detail in fig5 . adder stage 410 accepts two data inputs a , b on input terminals 50 , as well as carry signals c in and c out ( generated in another stage ) on carry terminals 51 , 52 , and generates an output sum signal 53 . because adder stage 410 preferably is a carry / look - ahead adder , it preferably also operates on data signals a , b , using nand gate 54 and inverter 55 , and nor gate 56 and inverter 57 , to respectively provide a gen ( i . e ., “ generate ”) signal 58 and a prop ( i . e ., “ propagate ”) signal 59 as carry / look - ahead signals that are used to derive the signals c in and c out for use by a subsequent adder stage 41 . in accordance with the present invention , adder stage 410 has two additional inputs psave and { overscore ( psave )} on terminals 500 , 501 respectively , which are used to put adder stage 410 in low - power mode . psave and { overscore ( psave )} could be provided as a single signal , appropriately inverted where necessary . as seen in fig5 when psave is asserted high and { overscore ( psave )} is asserted low to enter low - power mode , nmos transistor 502 is turned off , disconnecting the current path through functional components 503 , effectively turning them off and preventing them from switching . at the same time , pmos transistor 504 is turned on , pulling node 505 high , forcing output sum signal 53 low , so that no signal is input as data to subsequent stages 41 . in a previously known carry / look - ahead circuit , nand gate 54 and nor gate 56 would have two inputs each . however , in preferred adder stage 410 , each has three inputs . when psave is asserted high , the input of psave to nor gate 56 forces the output of nor gate 56 low , so that propagate signal 59 is a constant high that does not switch . similarly , when { overscore ( psave )} is asserted low , the input of { overscore ( psave )} to nand gate 54 forces the output of nand gate 54 high , so that generate signal 58 is a constant low that does not switch . thus , the generate and propagate look - ahead signals do not switch , and do not cause subsequent stages 41 to switch . programmable logic device 10 incorporating low - power adder circuit 40 may be used as part of a data processing system 900 shown in fig6 . the state of low - power signals psave and { overscore ( psave )} may be controlled by the setting of a configuration bit in device 10 . data processing system 900 may include one or more of the following components : a processor 901 ; memory 902 ; i / o circuitry 903 ; and peripheral devices 904 . these components are coupled together by a system bus 905 and are populated on a circuit board 906 which is contained in an end - user system 907 . system 900 can be used in a wide variety of applications , such as computer networking , data networking , instrumentation , video processing , digital signal processing , or any other application where the advantage of using programmable or reprogrammable logic is desirable . programmable logic device 10 can be used to perform a variety of different logic functions . for example , programmable logic device 10 can be configured as a processor or controller that works in cooperation with processor 901 . programmable logic device 10 may also be used as an arbiter for arbitrating access to a shared resource in system 900 . in yet another example , programmable logic device 10 can be configured as an interface between processor 901 and one of the other components in system 900 . it should be noted that system 900 is only exemplary , and that the true scope and spirit of the invention should be indicated by the following claims . various technologies can be used to implement programmable logic devices 10 employing low - power adders 40 as described above according to this invention . moreover , this invention is applicable to both one - time - only programmable and reprogrammable devices . it will be understood that the foregoing is only illustrative of the principles of the invention , and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention , and the present invention is limited only by the claims that follow .