the self - electrooptic effect device ( seed ), the symmetric self - electrooptic effect device ( s - seed ), and the fabrication techniques applicable to both have been fully described in u . s . pat . re . nos . 32 , 893 ; 4 , 546 , 244 ; 4 , 751 , 378 ; and 4 , 754 , 132 as well as in the following technical references : d . a . b . miller et al ., appl . phys . lett ., 45 ( 1 ), pp . 13 - 15 ( 1984 ) and a . . lentine et al ., appl . phys . lett ., 52 ( 17 ), pp . 1419 - 21 ( 1988 ). the references cited above and their teachings are expressly incorporated herein by reference . the s - seed is a four port device having an least two inputs and two outputs as shown in fig1 . this device is formed by electrically interconnecting multiple quantum well p - i - n diode 101 in series with multiple quantum well p - i - n diode 102 via lead 104 . the diodes are subject to a reverse bias potential , v . when the diodes are connected in this manner , they provide complementary outputs ( q and q ) because one of the diodes is on when the other is off . more precisely , it is understood that one of the diodes is in an absorbing state when the other diode is in a transmissive state . state changes for the s - seed are known to occur as a function of the ratio of the powers of the inputs signals and not as a function of the absolute intensity of the input signal . a state change is observed from outputs changing levels such as q changing from 0 to 1 or vice versa . in operation , optical signal beams 110 , 111 , 113 , and 114 are incident on the s - seed . the optical signal beams are grouped to be incident on the specific diodes as follows : optical signal beams 110 and 111 representing data a and the clock signals , respectively , are incident on diode 101 and optical signal beams 113 and 114 representing the clock signal and data signal b are incident on diode 102 . optical signal beams 110 and 114 can effect a change of output state of the s - seed . the amplitude of these optical signal beams is choses to have suficient contrast between a signal 0 and a logical 1 level to insure that the s - seed is not forced into a bistable region wherein the output level is ambiguous . an exemplary contrast of 2 : 1 has been found to satisfy the above criteria . it is understood that the optical signal beams corresponding to the clock signals have substantially equal intensities which are intially low when to the data signal intensities . since the output state of the s - seed is determined by the ratio of the incident signal powers on the diodes , the presence of a clock signal simultaneously with the data signals tends to degrade the constrast ratio of the input beams possible resulting in the failure of the s - seed to switch states . while it is understood that the clock signals are generally applied to read out the state of the s - seed via complementary output signal beams 115 and 116 ( q and q , respectively ), it is desirable to maintain a relatively small difference between the intensities of optical signal beams 111 and 113 as well as a sufficient intensity so that the state of the s - seed is read without interference or alteration . for most s - seed , it has a been determined that a ratio of powers for data signal a to data signal b exceeding 1 . 3 or falling below 0 . 7 causes switching of the s - seed wherein it is understood that the optical hysteresis loop is centered about a point where the powers of both data signals are substantially equal . to understand the programmable optical logic device , it is necessary to explain that fig1 has been simplified to permit the description of the basic s - seed given above . optical signal beams 110 and 114 individually comprise the data signals on which the boolean functions are to be performed . see , for example , fig2 and 3 . as shown , optical signal beam 110 includes the combination of individual data signals x and y whereas optical signal beam 114 includes the combination of the complements of the individual data signals x and y . when performing a boolean function , the programmable optical logic device performs it on the individual data signals x and y as combined to form signal a or on complementary individual data signals x and y as combined to form signal b . that is , the programmable optical logic device performs an and function as f ( x , y )= x · y and an or function as f ( x , y )= x + y . as shown in fig1 the embodiment of the present invention also includes logic control 103 in combination with the s - seed which comprises series connected multiple quantum well p - i - n diodes . logic control 103 generates complementary optical signal beams 117 and 118 for presetting the s - seed to operate deterministically through the bistable region for the basic s - seed so that ambiguities are eliminated and so that the device may perform various boolean functions on command . in fig1 optical signal beam 118 from logic control 103 is directed to be incident on diode 101 and optical signal beam 117 from logic control 103 is directed to be incident on diode 102 . in an alternative embodiment , logic control 103 generates only one of the optical signal beams 117 and 118 at a time . in the latter embodiment , one preset beam would be off while the other beam would be on . logic control 103 through its application of complementary optical signal beams 117 and 118 ( preset signal a and b ) causes the s - seed to respond to subsequent data signals as either an and / nand gate or an or / nor gate . logic control 103 effectively programs a particular boolean function so that the entire combination of the s - seed and logic control 103 acts as a programmable optical logic device according to the desire boolean function rules . in order to understand the programmable operation of this device , attention should be directed to fig2 and 3 . a description of the operation for noninverting logic functions , and and or , follows below . for a boolean and operation , preset signal b ( optical beam 117 ) is generated at a high level by logic control 103 . this results in diode 102 becoming highly absorbing which causes the data signal b ( x , y ) to be absorbed by diode 102 causing , in turn , output optical signal beam 116 to be in a low state ( q = 0 ) relative to output optical signal beam 115 which is set to a high state ( q = 1 ) because diode 101 is highly transmissive for data signal a ( x , y ). preset signal b is generated as a pulse to impinge on diode 102 for a short time period preceding the arrival of the data signals . the wavelength , duration and intensity of the preset signal is determined to permit sufficient energy transfer to diodes 101 and 102 for establishing an initial output state for the diode pair . while staggering of the preset and data signals is preferred , it is understood that the preset signal may be applied concurrent with the leading edge of the data signals . when x and y are at a zero level , x and y are both at a one level so that the diode pair remains in the preset condition with q = 0 . when either x or y is at one lever , x or y is at a one level so that data signal a and b are substantially equal causing the diode pair to remain in the state set by preset signal b wherein q = 0 . finally when x and y are at a one lever , x and y are both in the zero state causing the diode pair to switch from the preset state to a state where q = 1 . thus , the boolean and function is achieved by proper use of presetting as developed by logic control 103 . for a boolean or operation , preset signal a ( optical beam 118 ) is generated at a high level by logic control 103 . this result in diode 101 becoming highly absorbing which causes the data signal a ( x , y ) to be absorbed by diode 101 causing , in turn , output optical signal beam 116 to be in a high state ( q = 1 ) relative to output optical signal beam 115 which is set to a high state ( q = 0 ) because diode 102 is highly transmissive for data signal b ( x , y ). preset signal a is generated as a pulse to impinge on diode 101 for a short time period preceding the arrival of the data signals . when x and y are at a zero level , x and y are both in the one state causing the diode pair to switch from the preset state to a state where q = 0 . when either x or y is at a one level , x or y is also at a one level so that data signals a and b are substantially equal causing the diode pair to remain in the state set by preset signal b wherein q = 1 . finally when x and y are at one lever , x and y are both at a zero level so that the diode pair remains in the preset condition with q = 1 . thus , the boolean or function is achieved by proper use of presetting as developed by logic control 103 . it should be clear to those skilled in the art that the inverting boolean functions are simultaneously available on the complementary output rail or beam ( q ). that is , when the q output ( output beam 116 ) is the primary or active rail during an and or or operation , the q output ( output beam 115 ) corresponds to a nand or nor output , respectively . as shown in fig3 a preset signal b ( beam 117 shown as signal 302 ) from logic control 103 impinges on diode 102 from time t 1 to time t 2 . this causes the programmable optical logic device to behave as an and / nand gate based upon which output is active . data signals x , y , x , y ( shown individually as exemplary signal 303 ) impinging on the diodes are anded or nanded together to generate new output signal beams . at time t 3 , the data signals subside and the clock signals ( shown individually as signal 305 ) are applied to read the outputs beginning at time t 4 . see exemplary output signals 304 . the clock signals are turned off to cease reading at time t 5 . at time t 6 , preset signal a ( beam 118 shown as signal 301 ) form logic control 103 impinges on diode 101 from time t 6 to time t 7 . this causes the programmable optical logic device to behave as an or / nor gate based upon which output is active . data signals x , y , x , y impinging on the diodes are ored or nored together to generate new output signal beams . at time t 8 , the data signals subside and the clock signal are applied to read the outputs beginning at time t g . see exemplary output signals 304 . the clock signals are turned off to cause reading of the or logic . in one example for experimental practice , preset signals were generated by a standard acousto - optic modulated hene laser at 633 nm using peak power levels from approximately 6 μw to approximately 100 μw at a 12 . 5 % duty cycle . clearly any wavelength that is significantly absorbed by the diodes can be used . in theory , a short pulse from a modelocked laser can be used to preset the s - seed very quickly provided that the pulse contains sufficient energy . in the particular example cited above , the s - seed comprises quantum well p - i - n diodes with algaas / gaas quantum well intrinsic regions ( nominally 850 nm ). exemplary data signal levels incident on the logic gate have been estimated at approximately 4 . 8 μw and 2 . 4 μw for the complementary input beams . from the description above , it should be clear to those skilled in the art that the programmable optical logic device described herein either may be operated as a dedicated logic gate or may be operated in a programmable mode wherein the logic function perform may vary from time period to time period . in addition to the benefits described above , other benefits derived from the programmable optical logic device are time sequential gain without critical biasing , high gain ( low power in vs . high power out ), and large fanout . while the presetting function has been shown to be performed primarily with optical signals , it should be clear now to those skilled in the art that electrical signals may be used to preset the diode pair to an initial state . for example , a source potential v or ground potential may be switchably applied to lead 104 . application of source potential v would cause diode 102 to become highly absorbent whereas application of the ground potential would cause diode 101 to become highly absorbent . it should also be noted that an alternative embodiment of the diode pair is contemplated herein . for example , either diode 101 or diode 102 may be replaced by a standard p - i - n diode which does not employ a quantum well intrinsic region . as such , the remaining diode would be required to be a quantum well p - i - n diode so that the resulting arrangement would be a self electro - optic effect device having a p - i - n diode as its load . in such an arrangement , the active output and , in fact , the only output would be derived from the output of the quantum well p - i - n diode .