a detailed description of embodiments of the present invention is presented below . while the disclosure will be described in connection with these drawings , there is no intent to limit it to the embodiment or embodiments disclosed herein . on the contrary , the intent is to cover all alternatives , modifications and equivalents included within the spirit and scope of the disclosure as defined by the appended claims . in a rate converter the discrete low pass filter should have a bandwidth 1 / r where r is typically the larger of the upsampling factor l and downsampling factor m . one implementation of the low pass filter has an impulse response of where w [ n ] is a impulse response of a window function . when this is split into poly - phase filter components where m is an index based on the output samples and k is an index based on the input samples . furthermore , the arithmetic inside the brackets of h [ ] and w [ ] is performed modulo m . the standard rate converter shown in fig5 and with the specific example in fig4 is not flexible . they are designed for a specific input sampling rate and a specific output sampling rate . embodiments of the present invention employ poly - phase design similar to the rate converter 500 , but extend the architecture to a more generalized input rate . returning to the simplified example of fig4 , suppose rather than the rate conversion from an input sampling rate 2f to an output sampling rate of 3f , an input sampling rate of 2 . 2f is desired . for the sake of nomenclature , the input sampling rate for which the poly - phase filter was originally designed is referred to as the nominal input sampling rate . if the input sampling rate of rate converter 400 is changed from the nominal input sampling rate of 2f to an input sampling rate of 2 . 2f , delay line 402 would operate at 2 . 2f , but the poly - phase filter coefficients would not work since the input signal is out of phase with the nominal input sampling rate . however , equation ( 7 ), the poly - phase filter coefficients are essentially sampling the impulse response of a filter . by the same token , filter coefficients could be derived for other sampling rates . the difficulty in using this equation is that either a lot of values need to be precalculated or they need to be computed on the fly . the former alternative could require a lot of storage especially if the input and output sampling rates are incommensurate or have a very large least common multiple and the latter alternative could require a lot of computational capability . fig7 shows a generalize poly - phase architecture for arbitrary rate conversion . rate converter 700 comprises a plurality of delay units configured in a delay line , presented by delay units 702 , 704 , and 706 , operating at the input sampling rate , a plurality of scaling elements that change with the output sampling rate , and one or more adders , represented here by adders 722 , 724 , and 726 . unlike the filter coefficients apply by scaling elements 512 , 514 , 516 and 518 , the plurality of scaling elements represented by scaling elements 712 , 714 , 716 , and 718 , apply filter coefficients h q [ k ] which are not indexed by an integer value i , but by an “ index ” that on any real value q . for convenience , this real “ index ’ is referred to as a phase offset as opposed to the integer value which is referred to as a phase index . while in general the h q [ k ] can be calculated on the fly or precalculated from equation ( 7 ). this is not computationally or storage efficient . instead , the filter coefficients h i [ k ] are calculated in the same fashion as for rate converter 500 at the nominal input sampling rate . the key difference between rate converter 500 and rate converter 700 is that the input sampling rate and the nominal input sampling rate are different for rate converter 700 , while they are the same for converter 500 . with regard to a poly - phase rate converter , by design there is an nominal input sampling rate which is upsampled to an intermediate high sampling rate which a common multiple of the nominal input sampling rate and the output sampling rate . the least common multiple is typically chosen . implicit in the poly - phase rate converter there is an upsampling factor from the nominal input sampling rate to the intermediate high sampling rate and a downsampling factor from the intermediate high sampling rate and the output sampling rate . in a traditional fir filter many components would require operating at the intermediate high rate , but the poly - phase implementation eliminates the actual need however in the derivation , there is an implicit upsampling to the intermediate high sampling rate back down to the output sampling rate . in a typical poly - phase filter the upsampling factor is equal to the number of phases . when an input sampling rate different than the nominal input sampling rate is used , there is an implicit upsampling factor from the input sampling rate to the intermediate high sampling rate but it is not tied to the number of phases . mathematically , a given poly - phase structure the nominal input sampling rate , the output sampling rate and the intermediate high sampling rate arc relative . because of this by changing the rate at which the components operate , the output sampling rate can be adjusted . if the output sampling rate is adjusted the intermediate high sampling rate and the nominal sampling rate are changed . for example , given the rate converter in fig4 , if the output sampling rate is changed to 2 . 7f , then the intermediate high frequency would be 5 . 4f and the nominal input sampling rate would be changed to 1 . 8f . if the input sampling rate remains unchanged for the rate converter , the input sampling rate of 2f is now out of phase with the poly - phase filter coefficients . therefore , for the rate converter of fig7 the input sampling rate and the output sampling rate are completely flexible . the performance is limited generally by the number of filter coefficients used , that is for example , the number of coefficients used to perform the 2 to 6 to 3 in our example would likely be totally insufficient to handle the 44 . 1 to 7068 to 48 audio rate conversion . fig8 illustrate the derivation of the phase offset q . graph 802 shows samples at the input sampling rates . graph 804 shows the filter samples for which are determined at the nominal input sampling rate . for example , returning the example of fig2 , the poly - phase rate converter may store h i [ 1 ] as { h [ 3 ], h [ 5 ], h [ 4 ]}, and h i [ 0 ] as δh [ 0 ], h [ 2 ], h [ 1 ])}. in this example , the nominal input sampling rate of graph 804 is 2f . however , if the input sampling rate is then changed to 2 . 2f , the input samples no longer align to appropriate filter coefficients . in fig8 , sample 806 falls at q which is between filter samples at i and i + 1 . the fractional portion is indicated by d . it should be noted that the samples used here are merely to delineate the timing and the scale is not necessarily representative of real samples . embodiments of the present invention use interpolation based on stored coefficients h i [ k ], which offer a fast method for deriving the h q [ k ]&# 39 ; s . fig9 a illustrates deriving h q [ k ] using linear interpolation between the two nearest h i [ k ]&# 39 ; s . since q falls between i and i + 1 , scaling element 902 and 904 apply filter coefficients h i [ k ], and h i + 1 [ k ], respectively to the common input and are complementarily scaled by scaling elements 912 and 914 according to the proximity of q to i and i + 1 , respectively , that is by d and 1 − d . the results are combined by adder 934 . the approximation can be summed up mathematically as h q [ k ]≦( 1 − d ) h i [ k ]+ dh i + 1 [ k ]. ( 8 ) fig9 b illustrates deriving h q [ k ] using cubic interpolation between the four nearest h i [ k ]&# 39 ; s . since q falls between i and i + 1 , scaling element 902 and 904 apply filter coefficients h i [ k ], and h i + 1 [ k ]. additionally , scaling elements 906 and 908 apply filter coefficients filter coefficients h i − 1 [ k ], and h i + 2 [ k ]. scaling elements 916 , 918 , 920 , and 922 , apply scale factors p 0 ( d ), p 1 ( d ), p 2 ( d ) and p 3 ( d ), respectively . to h i − 1 [ k ], h i [ k ], h i + 1 [ k ] and h i + 2 [ k ], in accordance to a cubic interpolation . the results arc combined by adder 934 the approximation can be summed up mathematically as h q [ k ]= p 0 ( d ) h i − 1 [ k ]+ p 1 ( d ) h i [ k ]+ p 2 ( d ) h 1 + 1 [ k ]+ p 3 ( d ) h 1 + 2 [ k ]. ( 9 ) it should be noted that there are various forms of cubic interpolation including spline cubic and hermite cubic . also , other interpolation techniques known in the art can also be used to approximate h q [ k ]. it is a tradeoff between accuracy of interpolation and computational efficiency . fig1 illustrates a rate converter employing the linear interpolation of fig9 a . rate converter 1000 is like rate converter 700 with a plurality of delay elements and one or more adders operating similarly to their counterparts in rate converter 700 . scaling elements 712 , 714 , 716 , and 718 arc replaced by the interpolation module shown in fig9 a . the first module comprises scaling elements 1002 , 1004 , 1022 , and 1024 which operate in a similar fashion as described for scaling elements 902 , 904 , 912 and 914 . likewise , scaling elements 1006 , 1008 , 1010 , 1012 , 1014 , and 1016 in the second , third and fourth module shown operate similarly to their counterparts 902 and 904 in fig9 a . adders 1032 , 1034 , 1036 and 1038 operate similarly to adder 922 . fig1 shows an alternate architecture for a rate converter employing linear interpolation . because each interpolation module in fig1 comprises the same scale factors for the various instances of scaling element 1022 and 1024 , respectively . they can be factored out , after the summation represented by adders 722 , 724 and 726 of fig1 . scaling elements 1002 , 1004 , 1006 , 1008 , 1010 , 1012 , 1014 , and 1016 function similarly to that described in fig1 . the various instances of scaling elements 1022 and 1024 have been eliminated in favor of one instance of each after the summation shown by adders 1102 , 1104 , 1106 , 1108 , 1110 , and 1112 . under this arrangement , it can be seen the components shown inside 1150 correspond to an instance of rate converter 500 from fig5 at index i and the components shown inside 1160 correspond to an instance of rate converter 500 at index i + 1 . fig1 shows a rate converter 1200 but in block diagram at the filter level . filter 1150 is a single phase of the poly - phase implementation of a rate converter at index i , and filter 1160 is single phase of the poly - phase implementation of a rate converter at index i + 1 . for the sake of simplifying notation , each phase at a given index j , of the poly - phase filter is given by the transfer function h j ( z ). this is particularly useful in a software implementation of a poly - phase rate converter because the same code could be re - used to calculate h i ( z ) and h i + 1 ( z ). the same principle applies to other interpolation methods such as the cubic interpolation . fig1 shows a rate converter using cubic interpolation . in addition to blocks 1150 and 1160 , blocks 1302 and 1304 using the transfer functions h i − 1 ( z ) and h i + 2 ( z ), respectively . scaling elements 916 , 918 , 920 and 922 operate similarly to that described in fig9 b . the interpolation is completed by combiner 1322 . one drawback of the interpolation technique is that the number of multiplications and additions is at least doubled for linear interpolation and quadrupled for cubic interpolation . if the fractional portion is close to 0 , then the contribution of the dh i + 1 [ n ] term in equation ( 8 ) is small and can be neglected . fig1 a shows an interpolation for h q [ n ] where if d is small only the scale factor of h i [ k ] is applied by scaling element 902 . functionally this is controlled by selector 1402 , which selects between using functional block 1410 which scales the input by h i [ k ] or functional block 1420 which uses a linear approximation for h q [ k ], based on the value of d . selector 1402 chooses which functional block should execute . in the case of a software implementation , selector 1402 chooses between two functions , one which uses linear interpolation , or one which uses the approximation h q [ n ]≈ h i [ n ], is used instead . in this fashion , resources are saved by not executing the unselected alternative , in particular the interpolation . mathematically , equation ( 8 ) becomes where t 1 is a threshold used for determining whether d is small . because the diagram shown in fig1 a is somewhat cumbersome , fig1 b shows the same diagram as in fig1 a except that the notation is simplified . even though it appears that two function blocks exist simultaneously , this is not intended to be a physical implementation . as explained above , for practical purposes , typically only one alternative functional block is performed at a time . also it should be noted that scaling element 902 appears twice in the diagram , in actuality either hardware or as a software functional block , scaling clement 902 could be the same scaling clement be it hardware or code . therefore in this and subsequent figure , it should be understood that alternate functional blocks are selected by the selector in each figure . likewise , fig1 shows a similar approximation when cubic interpolation is used . when d is small then the following approximations can be made to the interpolation of equation ( 9 ), p 0 ( d )≈ 0 , p 1 ( d )≈ 1 , p 2 ( d )≈ 0 and p 3 ( d )≈ 0 . this is controlled in fig1 by the addition of selector 1502 which selects between h i [ k ] and a cubic approximation for h q [ k ]. rather than interpolate or approximate each h q [ k ], a selection can be made between an interpolation based on the h j ( z ) for nearby , j &# 39 ; s or to use h i ( z ) if d is small . fig1 shows a rate converter selectively employing linear interpolation . rate converter 1600 essentially selects between rate converter 1200 of fig1 or conventional poly - phase rate converter 500 of fig5 depending on whether the fractional value is close to zero . when d is small , the filter h i ( z ) is used . otherwise , the output is a linear combination of the output of filters h i ( z ) and h i + 1 ( z ). this selection is shown functionally as performed by selector 1602 . fig1 shows a rate converter selectively employing cubic interpolation . rate converter 1700 essentially selects between rate converter 1300 of fig1 or conventional poly - phase rate converter 500 of fig5 depending on whether the fractional value is small . when d is small , the filter h i ( z ) is used . otherwise , the output is a cubic interpolated the output of filters h i − 1 ( z ), h i ( z ), h i + 1 ( z ) and h i + 2 ( z ). this selection is shown functionally as performed by selector 1702 . in general , any interpolation technique can be used . for notational simplicity , h ′ q [ k ] represents an approximation of h q [ k ] obtained through interpolation of h j [ k ] for indices j near q and h ′ q ( z ) represents the filter structures derived from those approximations . fig1 shows an example of using an approximation for small fractional parts in a block diagram . here h q [ k ] is approximated by h i [ k ] when d is small and otherwise by h ′ q [ k ], shown as interpolated scaling element 1802 . the selection is shown functionally as performed by selector 1804 . if the linear interpolation of fig9 a is used to derive h ′ q [ k ], then rate converter 1800 is essentially rate converter 1400 . if the cubic interpolation of fig9 b is used to derive h ′ q [ k ] then rate converter 1800 is essentially rate converter 1500 . fig1 shows an example of using an approximation for small fractional parts at the filter level . rate converter 1900 essentially functions as filter 1150 when d is small and functions filter 1902 otherwise , where filter 1902 is a filter structure derived from interpolation approximations . for example , if the filter structure of rate converter 1200 using linear interpolation is used for h ′ q ( z ), then rate converter 1900 is essentially rate converter 1600 . if the filter structure of rate converter 1300 , using cubic interpolation is used for h ′ q ( z ), then rate converter 1900 is essentially rate converter 1700 . fig2 shows another scaling clement for scaling by an approximation to h q [ k ]. the scaling element comprises interpolated scaling element 1802 similar to that described for fig1 . much like in fig1 , when d is small , selector 2002 selects scaling element 902 to apply h i [ k ] to the input . in addition when d ≈ 1 , selector 2002 selects scaling element 904 to apply h i [ k ] to the input . otherwise , selector 2002 uses interpolated scaling element 1802 . mathematically , this architecture can be described as where t 2 is a threshold used to determine the closeness of d to 1 . similarly , fig2 shows another rate converter . rate converter 2100 comprises selector 2102 which selects filter 1150 when d is small , filter 1160 when d is close to i and filter 1902 which uses a filter structure employing interpolation , otherwise . fig2 shows a scaling element for scaling by an approximation to h q [ k ], when the linear interpolated scaling clement of fig9 a is used . fig2 shows an implementation of rate converter 2100 when the linear interpolated filter structure of rate converter 1200 is used . fig2 shows a scaling element for scaling by an approximation to h q [ k ], when the cubic interpolated scaling element of fig9 b is used . fig2 shows an implementation of rate converter 2100 when the cubic interpolated filter structure of rate converter 1300 is used . when the input sampling rate is higher than the output sampling rate , the input samples flow into a delay line and may move down more than one delay element before an output is generated . for example , if the input sampling rate is twice the output sampling rate . input samples flow down two delay elements for every output period when the output samples are calculated . this results in unnecessary processing of the delay lines every input sample period when processing the delay line every output sample period is all that is needed . therefore , in order to receive the input samples , but not to advance them in a delay line until they are needed . multiple delay lines can be used . fig2 shows a poly - phase rate converter where multiple delay lines arc used . by mathematically rearranging the operations in a rate converter such as rate converter 700 in fig7 , rate converter 2600 can be derived . approximately , the same number of delay elements , scaling elements and adders are used . the number may not be exact for example , if the original rate converter had an odd number of delay elements and rate converter 2600 had uses two delay lines . there also may be additional elements required for overhead such as adder 2630 . in addition the poly - phase coefficients are shuffled . additionally , the separation into poly - phase subfilters can lead to additional optimization . for example , it is not uncommon that for certain rate conversions that h kq k [ n ] is 1 for a given value of n say n 0 and zero for all other values of n . the zeroes in the filter coefficients make the design of the kth subfilter much simpler , and the delay line does not need to extend beyond the n 0 element . as a result , delay elements 2602 , 2604 , and 2606 , scaling elements 2612 , 2614 , 2616 , and 2618 , and adders 2622 , 2624 , and 2626 , form essentially one poly - phase filter and delay elements 2652 , 2654 , and 2656 , scaling elements 2662 , 2664 , 2666 and 2668 and adders 2672 , 2674 and 2676 , form essentially another poly - phase filter . the outputs are combined by adder 2630 . mathematically rate converter 2600 and rate converter 700 are the same provided that they share the same parameters , ( i . e ., size and coefficients ). however , in this arrangement , the two delay lines operate at the slower output sampling rate . in this fashion , the rate converter 2600 has been factored into two poly - phase subfilters . it should be noted that the multiplication by the scaling elements are now indexed differently each scaling element is now represented by h kq k [ n ], where k k represents the kth subfilter . the second “ index ” q k is similar to the “ index ” q in fig7 except it may be different than the for each subfilter hence they are indexed by k . they may differ because each poly - phase subfilter is represents a different phase with respect to the slower output sampling rate . though only two subfilters are shown , clearly , this architecture can be generalized to arbitrary multiple delay lines and subfilters . fig2 shows a rate converter employing d poly - phase subfilters . in particular it shows a particular instance of the rate converter . when the input sample x [ n ] is received it actually goes into only one of the poly - phase subfilters , but at this time the “ index ” is adjusted in all the subfilters to the appropriately determined q k . hence at that instance each subfilter is represented by the notation h kq k where k indexes all the subfilters , here ranging from 0 to d - 1 . depicted in fig2 are representative subfilters , where subfilter 2702 is notated by h 0q 0 , subfilter 2704 is notated by h 1q 1 and subfilter 2706 is notated by h ( d - 1 ) q ( d - 1 ) . the results of all subfilters are summed up by one or more adders represented here by adders 2712 and 2714 . each subfilter can be approximated by using interpolation and the approximation techniques described above . for example , each subfilter can employ scaling elements such as shown in fig1 b , 15 , 18 , 20 , 22 and 24 . or the interpolation and approximation can be factored outside each subfilter such as shown in fig1 , 17 , 19 , 21 , 23 and 25 . fig2 shows an approximation using both interpolation and approximation techniques when q is close to an integer . in fig2 , each subfilter uses the approximation structure of fig2 . in particular , h ′ kq k ( z ), represented by subfilters 2812 , 2818 , and 2824 is an approximation of h kq k ( z ) using any one of the interpolation techniques described above . for each subfilter , an index i k and fractional part d k is determined from q k . if d k is near zero then the subfilter h ki k ( z ), represented by subfilters 2814 , 2820 and 2826 , is applied . if d k is near one then the subfilter h k ( i k + 1 )( z ), represented by subfilters 2816 , 2822 and 2828 . for each approximation a selector , represented in fig2 by selectors 2802 , 2804 and 2806 , can be used to select which calculation or subfilter to apply . 1087 ] fig2 shows a flow chart of an implementation of a traditional rate converter using multiple poly - phase subfilters . at step 2902 , the system is initialized . at step 2904 , an output accumulator y 0 is initialized to zero as is k which indexes the subfilters which sets the current subfilter to the kth subfilter . at step 2906 , the phase index i for the current subfilter is determined . for a traditional rate converter q k for each subfilter will fall on an integer . at step 2908 , the delay lines arc advanced if necessary . the advancement of the delay line in each subfilter is advanced at the appropriate time . the advancement can be based on the time when a new output sample is calculated or can be based on when an input sample is received . for example , the first input sample goes into the delay line of the first subfilter and that delay line is advanced . the second input sample goes into the delay line of the second subfilter and so forth . when all the input samples needed to calculate the next output sample are available , the next output sample is calculated . another method makes use of an input buffer . input samples are buffered for example in a first - in first - out ( fifo ) buffer . each time an output sample is ready to be computed ( i . e ., one output sample period ) the necessary input samples are read from the fifo and entered into the delay lines of the subfilters . for example , if the input sample rate is three times the output sample rate and there are three subfilters . every sample period , three samples arc read from the ftfo and entered into each delay line for the three subfilters . in this way , input samples need only be accessed every time an output value needs to be generated . during each advancement step , each subfilters delay line may receive zero , one or many input samples depending on the input and output sampling rates . when upsampling , it is even possible that for a given output sample , no delay lines are advanced . therefore , each subfilter receives input samples if available . if one or more samples are available the delay lines arc advanced ( i . e . oldest samples are discarded and newly received samples are added ). h i are the filter coefficients for the current subfilter , and c is the number of filter coefficients for the subfilter , is calculated . at step 2912 , the sum is added to y 0 and k is incremented . at step 2914 , a determination is made as to whether all subfilters have been applied ( i . e ., k = d ). if not , the process returns to step 2908 and repeats until all subfilters have been applied . if so , the value of y 0 is output as the current output sample at step 2916 and the process returns to step 2904 for the next output sample . fig3 a flow chart of an implementation of a rate converter using multiple poly - phase subfilters using interpolation . at step 3002 , the system initialized . at step 3004 , an output accumulator y 0 is initialized to zero as is k which indexes the subfilters which sets the current subfilter to the kth subfilter . at step 3006 , the phase offset q the phase index i and fractional part d for the current subfilter is determined . at step 3008 , the delay line in each subfilter is appropriately advanced as describe above for step 2908 . at step 3010 , the sums are calculated for values of l near q . the number of sums calculated is dictated by the type of interpolation algorithm used . for linear only the two nearest values to q , i and i + 1 are used . for cubic interpolation the nearest four values arc required . at step 3012 , an interpolation between sums is performed . in the case of linear interpolation , the result of the interpolation looks like : at step 3014 , the result is added to y 0 and k is incremented . at step 3016 , a determination is made as to whether all subfilters have been applied . if not , the process returns to step 3008 and repeats until all subfilters have been applied . if so , the value of y 0 is output as the current output sample at step 3018 and the process returns to step 3004 for the next output sample . fig3 a flow chart of an implementation of a rate converter using multiple poly - phase subfilters using interpolation and small fraction approximation . at step 3102 , the system initialized . at step 3104 , an output accumulator y 0 is initialized to zero as is k which indexes the subfilters which sets the current subfilter to the kth subfilter . at step 3106 , the phase offset q the phase index i and fractional part d for the kth subfilter is determined . at step 3108 , the delay line in each subfilter is appropriately advanced as describe above for step 2908 . at step 3110 , a determination is made as to whether d is closed to zero ( i . e ., d & lt ; t 1 ) if so , the sum is calculated at step 3114 . if not , at step 3112 a determination is made as to whether d is closed to one ( i . e ., d & gt ; t 2 , it should also be noted that if symmetry is important t 2 could be set equal to 1 − t 1 .) if so , the sum are calculated for values of l near q at step 3118 . again , the number of sums calculated is dictated by the type of interpolation algorithm used . for linear only the two nearest values to q , i and i + 1 are used . for cubic interpolation the nearest four values are required . at step 3120 , an interpolation between sums is performed . in the case of linear interpolation , the result of the interpolation looks like : at step 3122 , the result of steps 3114 , 3116 or 3020 is added to y 0 and k is incremented . in the case of linear interpolation used , the result look like at step 3124 , a determination is made as to whether all subfilters have been applied . if not , the process returns to step 3108 and repeats until all subfilters have been applied . if so , the value of y 0 is output as the current output sample at step 3126 and the process returns to step 3104 for the next output sample . the preceding flowcharts show how flexible rate converters using a single or multiple poly - phase filter architecture can be used to efficiently implemented in software . in particular the use of small fraction approximation can reduce the amount of calculations need to be performed . in addition to adding flexibility to the sampling rates that can be accommodated by the above described rate converters . the ability to interpolate and approximate using the techniques above also allows for the trade - off between storing filter coefficients and interpolating them . for example , if h i [ k ] is not available due to memory constraints , h i [ k ] could , for instance , be approximated by interpolating between h i − 1 [ k ] and h i + 1 [ k ]. since in the example of 44 . 1 khz to 48 khz rate conversion 5000 to 10000 coefficients need to be stored , the number could be reduced in exchange for increased computation . this enables the filter designer to trade off between memory and computational complexity . in addition to upsampling and downsampling , the flexible rate conversion architectures can be employed to for synchronization . the need for synchronization arises when the precise input sampling rate is no known . in the simplest example , the input sampling rate is expected to be approximately the same as the output sampling rate , but due to slight differences in hardware between the device supplying the input and the rate converter , the precise rate is not known and does not exactly match the output sampling rate . in a more generalized example , the rate converter expects the input at the nominal input sampling rate , but can be adjusted to determine the precise input sampling rate . fig3 illustrates a system for rate conversion which can determine the input sampling rate . rate conversion system 3200 comprises first - in - first - out ( fifo ) buffer 3202 , flexible rate converter 3204 and controller 3206 . flexible rate converter 3204 can be any of the architectures described above for flexible rate conversion . in addition , the input sampling rate of flexible rate converter 3204 can be adjusted . controller 3206 receives status information from fifo buffer 3202 . this status information comprises an indication of how full the fifo . nominally , the fifo is half full , if the input sampling rate set for the rate converter is less than the actual input sampling rate , the fifo will fill up . in this situation , controller 3206 will receive an indication that the fifo is filling up or near full . upon receiving the indication , controller 3206 increases the input sampling rate of the rate converter . similarly , if the input sampling rate set for the rate converter is greater than the actual input sampling rate , the fifo will drain . in this situation , controller 3206 will receive an indication that the fifo is depleting or near empty . upon receiving the indication , controller 3206 decreases the input sampling rate of the rate converter . one method of determining the near full and near empty condition is to set thresholds within the fifo . fig3 is a diagram of a fifo used in an embodiment of the rate conversion system depicted in fig3 . nominally , fifo 3300 operates at point 3302 , the half empty point . if fifo 3300 reaches point 3304 a near full indication is sent to the controller . if fifo 3300 reaches point 3306 a near empty indication is sent to the controller . because as described about , the flexible rate conversion systems described throughout can applied to adjustable output sampling rates as well as input sampling rates , a flexible rate conversion system can be used also to a synchronizing rate converter when the output rate is unknown . fig3 illustrates a rate conversion system which can determine the output sampling rate . rate conversion system 3400 first - in - first - out ( fifo ) buffer 3404 , flexible rate converter 3402 and controller 3406 . flexible rate converter 3402 can be any of the architectures described above for flexible rate conversion . in addition , the output sampling rate of flexible rate converter 3402 can be adjusted . very much like the synchronization to an unknown input sampling rate , controller 3406 receives status information from fifo buffer 3402 . this status information comprises an indication of how full the fifo . nominally , the fifo is half full , if the output sampling rate set for the rate converter is greater than the actual output sampling rate , the fifo will fill up . in this situation , controller 3406 will receive an indication that the fifo is filling up or near full . upon receiving the indication , controller 3406 decrease the output sampling rate of the rate converter . similarly , if the output sampling rate set for the rate converter is less than the actual output sampling rate , the fifo will drain . in this situation , controller 3406 will receive an indication that the fifo is depleting or near empty . upon receiving the indication , controller 3406 increase the output sampling rate of the rate converter . both the input synchronization described in fig3 and the output synchronization described in fig3 could be combined into a synchronizing rate converter where neither the input sampling rate nor the output sampling rate are precisely known . specifically , both an input fifo and an output fifo would indicate overflow or underflow conditions to a controller which would adjust the input sampling rate and the output sampling rate of the rate converter . finally , the technique for determining rates could be applied to other architectures for variable rate converters . fig3 shows a variable rate conversion system using linear interpolation of the input signal . rather than interpolating between phases in the poly - phase filter , the interpolation takes place between input samples . in general interpolation , especially linear interpolation , is not used for rate conversion due to unintended spectral effects . however , in this limited case , the linear interpolation is used to adjust for differences between the input sampling rate and the nominal input sampling rate of poly - phase rate converter 1150 . if the poly - phase rate converter is expecting a sample at corresponding to x [ q ] where q lies between n and n − 1 , then x [ q ] is approximated by ( 1 − d ) x [ n ]+ dx [ n − 1 ] where d = q − n − 1 . the interpolation is performed by scaling elements 3502 and 3504 and adder 3506 . small fraction approximation could also be used here to reduce complexity so that x [ q ]≈ x [ n − 1 ] when d ≈ 0 and x [ q ]≈ x [ n ] when d ≈ 1 . when interpolation is done on the input signal , it must be done with special care to avoid aliasing effects . this is particularly an issue when the interpolation at the input results in sampling rate reduction . in combination of the rate determining system described in fig3 , 33 , and / or 34 the variable rate converter 3500 can be used for synchronization of an unknown input signal . it should be noted that for simplicity of language all indexing uses regular arithmetic terms . however , it should be noted that all arithmetic relating to the phase offset and phase indices are practically performed modulo p , where p is the number of phases . so for instance if i = p − 1 then i + 1 = 0 . in practical terms to deal with the wraparound values , filter coefficients are often shifted duplicas such that h p [ n ]= h 0 [ n − 1 ] and h p + 1 [ n ]= h 1 [ n − 1 ]. it should be emphasized that the above - described embodiments are merely examples of possible implementations . many variations and modifications may be made to the above - described embodiments without departing from the principles of the present disclosure . all such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims .