referring to fig1 the block diagram of the circuit of the invention is shown in box 1 formed of dashed lines . the signal from antenna 2 is received on terminals 10 and 11 by differential amplifier circuit 3 . a phase adjustment 4 is provided to compensate for phase mismatch between individual differential amplifiers in different units . buffer driver stage 5 provides isolation and a constant output impedance . gain adjustment 6 is provided to compensate for gain mismatch between units . load 7 has a constant impedance such as 50 ohms . referring to fig2 resistors r1 and r2 terminate the antenna transmission line . the signal is coupled to the differential amplifier 30 through capacitors c3 and c4 and through spurious oscillation suppression resistors r3 and r4 . resistors r5 and r6 are of equal value and form a voltage divider so that the potential at the junction of r1 and r2 is one half the applied potential . amplifier 30 is a differential amplifier having a flat gain characteristic over a wide band of frequencies such as a fairchild μa733ic broadband video amplifier with a frequency response from dc to 100 mhz . it is temperature compensated and has an internally preset fixed gain . to attain an output impedance which is independent of input impedance it is necessary to have a negligible reverse signal transfer function ; therefore , a closed loop feedback system can not be used . emitter feedback in the μa733 provides feedback without closing the loop between input and output . this feedback technique , plus additional isolation provided by the buffer driver , allows maximum isolation of reverse signal transfer . variable capacitor c1 provides a phase adjustment to allow for phase mismatch between amplifiers . the fairchild μa733 has maximum phase mismatch of 7 ° at 30 mhz ; therefore , 14 ° of variable phase correction is provided to allow exact alignment for worst case deviations . the buffer driver 5 is a complementary emitter follower operating in class a mode . npn transistor q1 , pnp transistor q2 , emitter resistors r9 and r10 , bias resistors r11 and r12 and diode d1 form the buffer driver . diode d1 enables the buffer driver to operate in class a mode . q1 may be a 2n8101 , q3 a 2n8301 and d1 a in4157 . alternatively , an integrated circuit such as a nh002 , a complementary emitter follower made by national semiconductor , may be used . a complementary emitter follower is used so that the output impedance will be the same on both the positive and the negative swings of the input wave . the buffer stage must have a large gain bandwidth product to insure small propogation delay and , therefore , precise phase matching . the buffer stage of fig2 has a gain bandwidth product of 800 mhz . if the output impedance of the buffer driver is smaller than the desired output impedance , a fixed resistor r7 is disposed between the buffer and the output terminals , providing a constant output impedance composed primarily of the fixed resistance in series with the output impedance of the buffer . in the event that the output impedance of the buffer stage is somewhat frequency dependent , reactive compensation ( shown as z o comp . in fig2 ) is added . the disclosed buffer stage has a flat output impedance characteristic from 1 to 20 mhz but the impedance increases above 20 mhz . therefore a capacitor c2 , whose impedance decreases with frequency is used for compensation . variable resistor r8 provides gain adjustment so that the gain of individual units can be matched . since there is only a 1 / 2 dbm gain mismatch between amplifiers , a 1 dbm adjustment is used in the disclosed embodiment . the variable resistor has a large value of resistance compared to fixed resistance r7 so that the gain setting has an insignificant effect on output impedance . although the preferred embodiment relates to an antenna lead in system , it is obvious that the invention applies to any system which requires the connection of a source of variable impedance to a load of fixed impedance . obviously , many modification and variations of the present invention are possible in light of the above teachings . it is therefore to be understood that , within the scope of the appended claims , the invention may be practiced otherwise than as specifically described .