the various aspects of the present invention may be implemented in software , hardware , application logic , or a combination of software , hardware , and application logic . the software , application logic and / or hardware may reside on a server , an electronic device , or a service . if desired , part of the software , application logic and / or hardware may reside on an electronic device , part of the software , application logic and / or hardware may reside on a server . referring now to fig1 , a transaction interface according to the present invention is shown . the interface includes a request channel and a response channel . request channel signals are named with the prefix “ req ” and response channel signals are named with the prefix “ rsp ”. a transaction is initiated when the slave asserts reqrdy and the master asserts reqvld in the same clock cycle . the opcode ( type of transaction ) is indicated by the master with the reqopc signal . conventionally , read and write are possible opcodes . according to an aspect of the present invention , an urgency change is another type of opcode . the address of the transaction is indicated by the master with the reqaddr signal . the urgency of the transaction is indicated by the master with the requrg signal . according to an aspect of an embodiment of the present invention , the master uses the requrg signal to indicate a new urgency value for the slave to apply to zero or more pending transactions . the data to be written , if the transaction has a write opcode , is indicated by the master with the reqdata signal . according to an aspect of the present invention , a transaction identifier ( id ) is indicated for each transaction request by the master with the reqtrld signal . in accordance with some aspects , the transaction id signal is unique for each transaction . according to aspects of the present invention shown in fig1 , the interface supports more than one pending transaction and the master indicates , with the requrgchangemask signal , for an urgency change operation , which pending transaction &# 39 ; s urgency to change . the requrgchangemask signal has one bit for each possible value of trid . the urgency of all transactions pending in the slave ip with a trid value matching the equivalent bit asserted in the requrgchangemask signal is changed . in accordance with some aspects of the present invention , the requrgchangemask signal is not present and an urgency change operation causes the slave to changes the urgency of all pending transactions . in accordance with some aspects of the present invention , the requrgchangemask signal is not present and the reqaddress signal represents the value otherwise presented requrgchangemask . in other aspects of the present invention , the requrgchangemask signal is not present and the req data signal represents the value otherwise presented requrgchangemask . a transaction is completed by a response on the response channel . a response occurs when the master asserts rsprdy and the slave asserts rspvld in the same cycle . the read data , if the transaction had a read opcode , is indicated by the slave with the rspdata signal . the transaction identifier is indicated for each transaction response by the slave with the rsptrld signal . whereas a transaction interface , according to the present invention , can cause a set of pending transactions to change urgency , the change in urgency is most beneficial if it causes transactions blocked within an ip , such as a noc , to make forward progress . this is done with a forward - going pressure signal . where pressure is used within a master ip and a slave ip , it is useful to have a sideband pressure signal . this is distinguished in that it is out - of - band ( not associated with any particular transaction ) whereas the mechanism for promoting the urgency of transactions is in - band ( associated to one or more particular transactions ). according to various aspects of the present invention , the request to change the urgency of a set of pending transactions is carried on the request channel and , thus , subject to slave back - pressure . according to another aspect of the present invention , the master may use a forward - pressure signal on the request channel to accelerate the notification to the slave of such a change of urgency , in the same way it would have done to accelerate the notification to the slave of an urgent request . one aspect of the present invention , as exemplified in one embodiment , discloses a transaction request with an urgency change opcode that causes an incrementing of the urgency of all transactions pending for that transaction interface . such a transaction request receives no response . in accordance with another aspect , a transaction request with an urgency change opcode causes the urgency of all transactions pending for that transaction interface to be assigned the value of requrg . such a transaction request receives no response . in accordance with another aspect , a transaction request with an urgency change opcode causes the urgency of all transactions pending for that transaction interface to be assigned the value of requrg , but only if the value of requrg is greater than the existing urgency value . such a transaction request receives no response . in accordance with another aspect , an interface supports 32 pending transactions , each with a transaction id value and an urgency value . a bit of the address signal corresponds to each transaction id value . address bit 0 corresponds to transaction id with binary value 00000 . address bit 1 corresponds to transaction id with binary value 00001 . address bit 2 corresponds to binary transaction id 00010 , etc ., such that address bit 31 corresponds to transaction id with binary value 11111 . a transaction request with an urgency change opcode causes the urgency of all transactions pending for that transaction interface to be assigned the value of requrg . such a transaction request receives no response . in accordance with another aspect , an interface supports 32 pending transactions , each with a transaction id value and an urgency value . a bit of the address signal corresponds to each transaction id value as described above . each pending transaction has a unique transaction id value . a transaction request with an urgency change opcode causes the urgency of all transactions pending for that transaction interface to be assigned the value of requrg . such a transaction request receives no response . in accordance with another aspect , an interface supports 32 pending transactions , each with a transaction id value and an urgency value . a bit of the address signal corresponds to each transaction id value as described above . each pending transaction has a unique transaction id value . a transaction request with an urgency change opcode causes the urgency of all transactions pending for that transaction interface to be assigned the value of requrg . such a transaction receives a response after the slave ip has processed the change of urgency . in accordance with another aspect , an interface supports 16 pending transactions , each with a transaction id value and an urgency value . a requrgchangemask signal has 16 bits . each corresponds to a transaction id value as described above . each pending transaction has a unique transaction id value . a transaction request with an urgency change opcode causes the urgency of all transactions pending for that transaction interface to be assigned the value of requrg . such a transaction receives a response after the slave ip has processed the change of urgency . in accordance with another aspect , an interface comprises a sideband signal indicating a pressure level . pressure is used within the slave ip to force forward progress of queued transactions . as will be apparent to those of skill in the art upon reading this disclosure , each of the aspects described and illustrated herein has discrete components and features which may be readily separated from or combined with the features and aspects to form embodiments , without departing from the scope or spirit of the present invention . any recited method can be carried out in the order of events recited or in any other order which is logically possible . unless defined otherwise , all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs . although any methods and materials similar or equivalent to those described herein can also be used in the practice or testing of the present invention , representative illustrative methods and materials are now described . all publications and patents cited in this specification are herein incorporated by reference as if each individual publication or patent were specifically and individually indicated to be incorporated by reference and are incorporated herein by reference to disclose and describe the methods and / or system in connection with which the publications are cited . the citation of any publication is for its disclosure prior to the filing date and should not be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention . further , the dates of publication provided may be different from the actual publication dates which may need to be independently confirmed . additionally , it is intended that such equivalents include both currently known equivalents and equivalents developed in the future , i . e ., any elements developed that perform the same function , regardless of structure . the scope of the present invention , therefore , is not intended to be limited to the exemplary embodiments shown and described herein . in accordance with the teaching of the present invention a computer and a computing device are articles of manufacture . other examples of an article of manufacture include : an electronic component residing on a mother board , a server , a mainframe computer , or other special purpose computer each having one or more processors ( e . g ., a central processing unit , a graphical processing unit , or a microprocessor ) that is configured to execute a computer readable program code ( e . g ., an algorithm , hardware , firmware , and / or software ) to receive data , transmit data , store data , or perform methods . the article of manufacture ( e . g ., computer or computing device ) includes a non - transitory computer readable medium or storage that includes a series of instructions , such as computer readable program steps or code encoded therein . in certain aspects of the present invention , the non - transitory computer readable medium includes one or more data repositories . thus , in certain embodiments that are in accordance with any aspect of the present invention , computer readable program code ( or code ) is encoded in a non - transitory computer readable medium of the computing device . the processor , in turn , executes the computer readable program code to create or amend an existing computer - aided design using a tool . in other aspects of the embodiments , the creation or amendment of the computer - aided design is implemented as a web - based software application in which portions of the data related to the computer - aided design or the tool or the computer readable program code are received or transmitted to a computing device of a host . an article of manufacture or system , in accordance with various aspects of the present invention , is implemented in a variety of ways : with one or more distinct processors or microprocessors , volatile and / or non - volatile memory and peripherals or peripheral controllers ; with an integrated microcontroller , which has a processor , local volatile and non - volatile memory , peripherals and input / output pins ; discrete logic which implements a fixed version of the article of manufacture or system ; and programmable logic which implements a version of the article of manufacture or system which can be reprogrammed either through a local or remote interface . such logic could implement either a control system either in logic or via a set of commands executed by a soft - processor . accordingly , the preceding merely illustrates the various aspects and principles of the present invention . it will be appreciated that those skilled in the art will be able to devise various arrangements which , although not explicitly described or shown herein , embody the principles of the invention and are included within its spirit and scope . furthermore , all examples and conditional language recited herein are principally intended to aid the reader in understanding the principles of the invention and the concepts contributed by the inventors to furthering the art , and are to be construed as being without limitation to such specifically recited examples and conditions . moreover , all statements herein reciting principles , aspects , and embodiments of the invention as well as specific examples thereof , are intended to encompass both structural and functional equivalents thereof . additionally , it is intended that such equivalents include both currently known equivalents and equivalents developed in the future , i . e ., any elements developed that perform the same function , regardless of structure . the scope of the present invention , therefore , is not intended to be limited to the various aspects discussed and described herein . rather , the scope and spirit of present invention is embodied by the appended claims .