the accuracy of the amplification of a sample by circulation is limited by defects peculiar to the amplifiers and sampling circuits . the values of the offset voltages of the amplifiers and memory errors are , in the present state of the art , much higher than the mean value of the thermal noise and may attain one hundred times the value of the latter . amplification circuits embodying the invention enable the offset voltages and memory errors to be eliminated or greatly reduced , which in turn enables the possibilities of the recirculatory amplification circuits described in the abovementioned patent application to be utilized to the full . thus amplification accuracy will only be limited by the noise . in the abovementioned patent application a description is given of the amplifier circuits followed by digitising circuits . the offset voltages and memory error voltages may be limited in practice to values sufficiently low for the digitising result to remain unaffected . thus the present invention is aimed at compensating only those errors produced during the amplification phase . the circuit diagrams are restricted to the amplification circuits without regard to the digitising circuits or to the comparison circuits which arrest the circulation of a sample by comparing with a predetermined threshold level . for a description thereof reference should be made to the aforementioned application ser . no . 322 , 333 . the offset and memory error voltages are in practice invariable at a constant temperature . it will therefore be possible to eliminate these errors if one considers that the temperature variation of the circuits is negligible during the course of one amplification . since in practice the duration of the amplification can be reduced to a fraction of a millisecond , it is reasonable to assume that the temperature remains constant throughout the amplification of one sample . it may therefore be assumed that the offset and memory error voltages are constant during an amplification phase . fig1 shows in diagrammatic form a differential amplification circuit comprising a negative feedback differential amplifier a 113 . the non - inverting input of this amplifier is connected to the circuit input by a controlled switch s 150 . the negative feedback circuit of this amplifier consists of a resistor r 114 connected between the output and the inverting input of the amplifier and a resistor r 115 connected to the inverting input of the amplifier and grounded by a controlled switch s 116 . connected in parallel with this second resistor is a resistor r 1 grounded by means of controlled switch s 1 . a controlled switch s 2 enables the non - inverting input of amplifier a 113 to be grounded . a delay memory circuit is connected between the output of amplifier a 113 and its non - inverting input and is not shown , but part of it can be connected to the inverting input of amplifier a 113 by a controlled switch s 3 and a resistor r 3 . this diagram shows the various components of the general diagram of a circulation amplifier described in the abovementioned patent application with the exception of resistors r 1 and r 3 and controlled switches s 1 , s 2 and s 3 , these different components modifying the amplifying circuit to enable the offset and memory errors to be compensated . in accordance with the invention a zero input signal circulates once by closing switch s2 . assuming amplifier a113 to have an error - determining gain g p , the value of this gain is obtained by opening switch s116 and closing switch s 1 . since the amplifier input signal is zero , its output signal is equal to the offset voltage eo of the amplifier multiplied by the gain gp . after circulation the memory error in the delay memory circuit is added to this error . the resulting signal is transmitted to the inverting input of amplifier a 113 by closing switch s 3 at the same time as the sample is applied to the non - inverting input by closing switch s 150 after having previously opened switches s 1 and s 2 . the output signal from amplifier a 113 will then be the sample signal subjected to a gain ge to which will be added the offset voltage subjected to the same gain and from which will be deducted the error compensation voltage applied to the inverting input of the amplifier , this voltage being subject to the gain gc . the signal obtained is then amplified by circulation in the same way as described in the abovementioned patent application . the values of the resistances r 1 and r 2 are fixed so that the offset and memory errors can be eliminated for a given number of circulation cycles . it will therefore be seen that a circulation amplification with error compensation requires one circulation cycle before sampling . since the duration of this cycle is constant , all the samples will be put back by this same duration and this does not , therefore , present any difficulty . the first embodiment will now be described with reference to fig2 with a detailed description for this embodiment of the operation of the circulation amplification circuit with error compensation together with the detailed calculation for determining resistances r 1 and r 3 . the circuit for the first embodiment is similar to that shown in fig1 with a delay memory circuit composed of a first static memory m 124 , whose input is connected to the output of amplifier a 113 by a controlled switch s 123 . the output of this first static memory is connected to the input of an amplifier a 125 of unitary gain , whose output is connected to the input of a second static memory m 127 by a controlled switch s 126 . the output of this second memory is connected to the non - inverting input of amplifier a 113 by a controlled switch s 140 and to the inverting input by means of switch s 3 and resistor r 3 . since the gain of amplifier a 125 is constant and equal to unity , its offset voltage is also constant , whatever the signal to be amplified . the total error due to memories m 124 and m 127 and amplifier a 125 is therefore constant and the voltage e 1 of this error will be noted . error voltages vp , ve , va1 , va2 , . . . van supplied by memory m 127 will be noted at the end of the following stages respectively : in a first phase which we shall designate &# 34 ; error determination &# 34 ; the non - inverting input of amplifier a 113 is earthed by closing switch s 2 . switches s 1 and s 123 are also closed and all the other switches are opened . the output signal of amplifier a 113 , equal to g p × e o where ## equ1 ## is transferred to the memory m 124 . switch s 123 is then opened , and switch s 126 closed . the error signal to the output of memory m 127 is then : in the second phase , which is the &# 34 ; sampling phase &# 34 ;, switches s 150 , s 123 and s 3 are closed after opening switches s 2 , s 1 and s 126 . switch s 123 is then open and switch s 126 closed , and the output signal of the amplifier a 125 to which are added the memory errors , is transferred to memory m 127 . the error voltage at the output of memory m 127 is then : where ## equ2 ## voltage ve only symbolizes the error voltage at the output of m 127 , without including the voltage of the sampled signal which of course is amplified according to the operation described in the abovementioned patent application . the third phase is the first amplification phase . to carry out this phase , only switches s 116 , s 123 and s 140 are closed . the signal is amplified by amplifier a 113 with gain g , transferred to memory m 124 , then to memory m 127 , by closing switch s 126 and opening switch s 123 . the error voltage at the output of m 127 is then : where ## equ3 ## the second amplification is carried out under the same conditions as the first , i . e . : by grouping together the terms in eo and in e 1 in the expression for voltage van , and by cancelling out their coefficients , the values for gp and ge are calculated as functions of g . these values enable the errors to be eliminated after n amplification cycles . thus the values for r 1 and r 3 in terms of the value of r 114 and g may be deduced from the results . the detailed calculation of resistances r 1 and r 3 , the principle of which was given above , will now be described , i . e . by calculating the error voltages phase by phase : ∴ ve = [ ge - gp ( ge - 1 )] eo + [ 1 - ( ge - 1 )] e 1 ∴ va 1 = g . [ 1 + ge - ( ge - 1 ) gp ] eo + [ 1 + g - ( ge - 1 ) g ] e 1 . ∴ va 2 = g . sup . 2 . [ 1 + g . sup .-. sup . 1 + ge - ( ge - 1 ) gp ] eo + g . sup . 2 . [ 1 + g . sup .-. sup . 1 + g . sup .. sup .- 2 - ( ge - 1 )] e 1 van = g . eo + e 1 + g . va ( n - 1 ) ∴ van = g . sup . n . [ 1 + g . sup .-. sup . 1 + g . sup .-. sup . 2 + . . . + g . sup . 1 . sup .- n + ge - ( ge - 1 ) gp ] eo + g . sup . n . [ 1 + g . sup .-. sup . 1 + g . sup .-. sup . 2 + . . . + g . sup .-. sup . n - ( ge - 1 )]. e 1 for a given number n of amplification cycles , the coefficients of eo and e 1 may be cancelled , which enables the values to be determined for ge and gp as functions of g , values which eliminate the errors after n amplification cycles . the values of r 1 and r 3 are then deduced from the following relations : ## equ4 ## may be replaced , without appreciable error , by the sum of the terms of the same progressions with an infinite number of terms : ## equ5 ## the following is then obtained : ## equ6 ## to ensure that the error voltage is zero after n amplification cycles , it is necessary and sufficient for the coefficients of eo and e 1 to be zero at the same time . the following is then obtained : ## equ7 ## which allows the following to be obtained : ## equ8 ## by giving r 1 and r 3 the above defined values the error voltage would be strictly zero for an infinite number of amplification cycles , but with the approximations made it may be assumed that it is also zero for a finite number of amplification cycles . this approximation will be explained in more detail later . the second embodiment shown in fig3 will now be described . this embodiment differs from the first embodiment only in that amplifier a 125 of unitary gain is replaced by an amplifier a 163 of the same gain as amplifier a113 . the various operational phases are similar to those for the operation of the first embodiment , with the exception that in the amplification phases the two amplifiers a 113 and a 163 play the same role and the signal can be extracted from the amplification circuit at the output of either of these two amplifiers . an amplification cycle is therefore determined by the passage of the signal in one of the two amplifiers a 113 and a 163 . since the signal can only be extracted from the circuit at the output of the two amplifiers , if this signal is memorized in m 124 , it will be amplified by a 163 when the output of the latter is connected to m 127 or to a suitable mechanism . similarly , if the signal is memorized in m 127 , it will be amplified by a 113 . thus we shall call the &# 34 ; amplification cycle &# 34 ; the circulation in either memory m 127 and amplifier a 113 or in m 124 and a 163 . each cycle commences on opening the switch upstream from the memory and ends when the signal leaves the amplifier . thus the memory error voltages of m 124 and offset voltages of a 163 may be grouped together in a single error voltage designated e 1 . as in the first error - determining phase , amplifier a 113 operates on the basis of a signal which is not extracted from m 127 and , a distinction will be made between offset voltage eo of a 113 and memory error voltage e 2 of memory m 127 . the gain and voltage notations are similar to those of the first embodiment and the operational phases are also the same . the various stages in determining resistances r 1 and r 2 are given briefly below , this determination being carried out by a similar method to that in the preceding embodiment . by the same method as before , and with the same approximation , the following is obtained : ## equ9 ## the coefficients of e 1 and e 2 are similar , hence the cancellation of the coefficients eo , e 1 and e 2 is reduced to two equations and the following is obtained : ## equ10 ## finally the following is obtained : ## equ11 ## the third embodiment shown in fig4 will now be described . only the delay memory circuit is different from the two preceding embodiments . this circuit comprises two static memories m 124 and m 127 connected in parallel , and each being connected to the output of amplifier a 113 by controlled switches s 123 and s 126 respectively , and also connected to the non - inverting input of the same amplifier by controlled switches s 128 and s 129 respectively . the output of one of the two memories , m 127 in this example , is connected to the inverting input of amplifier a 113 by controlled switch s 3 and resistor r 3 . the recirculating signal is memorized at the output of amplifier a 113 or alternatively in memory m 124 and in memory m 127 . an amplification phase is determined by the passage of the signal in amplifier a 113 and its memorization in one of the two memories . in the course of the error determining phase , the zero input signal circulates in the two memories and therefore passes twice into amplifier a 113 . the notations of the gains and voltages are similar to those of the preceding embodiments and the operational phases are also the same . e 1 is the memory error of m 124 and e 2 that of m 127 . the stages in determining resistances r 1 and r 3 will be given briefly below , the principle of this determination being similar to that of the preceding embodiments . 2nd phase : memorization in m 127 with s 2 opened and s 116 closed : ve = ge . eo + e 1 - ( ge - 1 ) vp van = g . va ( n - 1 ) + g . eo + e 1 if n is even van = g . va ( n - 1 ) + g . eo + e 2 if n is odd . in the same way as previously , and with the same approximation , the following is obtained : ## equ12 ## the coefficients of e 1 and e 2 cancel for : ## equ13 ## and the coefficient of eo then cancels for : ## equ14 ## the following is then obtained : ## equ15 ## it should be noted that these values for r 1 and r 3 are the same as those obtained in the second embodiment . the fourth embodiment shown in fig5 will now be described . only the delay memory circuit differs from the preceding embodiments . this circuit comprises a delay line 120b , introducing a delay τ , and an amplifier 120a , connected in series . the input of the delay line is connected directly to the output of amplifier a 113 and the output of the delay line is connected to the non - inverting and inverting inputs of amplifier a 113 by controlled switch s 140 , and by controlled switch s 3 , ( through resistor r 3 ) respectively . the delay line does not bring about a voltage offset but causes a loss in the level of the signals which traverse it . amplifier 120a is designed to compensate for this loss of signal level , which is essential for amplification , but it introduces an offset voltage e 1 . it may therefore be assumed that the delay memory circuit introduces a total error e 1 and it is clear that determination of resistances r 1 and r 3 is carried out in exactly the same way as the first embodiment with the same results , namely : ## equ16 ## in the case of a constant gain amplification , all the samples complete the same number of amplification cycles and hence the same number of circulation cycles . in this case , error compensation can be accurate . in fact is is possible to calculate the exact value of the two sums 1 + g - 1 + g - 2 + . . . g - n and g - 1 + g - 3 + . . . g - n since these values have a limited number of terms . however , it should be noted that in the second and third embodiments the error compensation may only be accurate where the number of amplification cycles is odd . in fact , it is only in this case that the coefficients of e 1 and e 2 are equal . in the case of a variable gain amplification , the number of amplification cycles is variable according to the level of the sample . however , a maximum number of amplification cycles may be fixed which no sample is likely to exceed . r 1 and r 3 may then be determined for this number of amplification cycles and error compensation will only be perfectly accurate where the sample is actually subjected to this number of amplification cycles . if the resistances r 1 and r 3 are determined by means of the simplified formulae obtained above , by replacing the geometrical progressions with a limited number of terms by progressions with an infinite number of terms , the error introduced by this approximation is still acceptable . in fact , for each of the embodiments the gains ge and gp are replaced by their value as a function of g , obtained after approximation in the error voltage expressions ve , va1 , va2 , . . . van , in order to determine the errors produced after the sampling phase and each amplification cycle , the following is obtained : it will be observed that in the four embodiments the errors are not amplified , hence the relative total error in relation to the sampled voltage is practically independent of the size of this voltage . the error introduced by the approximation of a series with a limited number of terms by a series with an infinite number of terms is therefore completely acceptable . the principal error introduced by the method is due to the difference between the number of amplification cycles actually completed and the number of cycles for which resistances r 1 and r 3 have been determined . the most unfavorable case for inaccuracy of the error compensation is the case of a sample which is not to be amplified and is extracted from the circuit after its passage in the differential amplifier , and hence not passing with amplification into the delay memory circuit . in fact , in this case , if the amplification circuit did not include any error compensation , the errors introduced to the sample would be equal to the sum of the errors of the various components . normally the error is limited to the input of the main amplifier , i . e . the error voltage to be added to the input signal of the circuit will be determined to obtain the same error at the output , and assuming that none of these components introduces any error voltage . in order to do this it is sufficient to determine the ratio of the sampling voltage to the sampling gain . in the first , second and fourth embodiments the error is less than that which would be caused by the various components without error compensation . in fact , without error compensation the error would be equal to the sum of the errors caused by each of the components of the circuit when these embodiments , the coefficients of eo , e 1 and e 2 being lower than unity , the error is less than the sum of the errors produced by each of the components in the circuit . in the third embodiment , the coefficient of eo is higher than unity but , because the gain g is always greater than 2 , this coefficient is only slightly greater than unity . determination of the resistances r 1 and r 3 for automatic variable gain operation by means of the simplified formulae therefore enables an error compensation to be made , which even in the most unfavorable cases improves the accuracy of the sample amplification . of course the four embodiments described are only preferred and it is possible to apply the principle of error compensation to other recirculatory amplification circuits without departing from the scope of the present invention .