embodiments of the invention will be described with reference to the attached drawings . the first embodiment , shown in fig1 , comprises a first device 1 having a transmitting section 10 and a receiving section 20 , a second device 6 having a receiving section 60 and a transmitting section 70 , and a bi - directional communication channel 300 linking the first device 1 and second device 6 . the transmitting section 10 comprises an encryption circuit 11 , a transmitting circuit 12 , an encryption key generator 13 , and a memory 14 . the transmitting section 10 receives a transmit signal a comprising successive packets , which arrive intermittently and are supplied to the encryption circuit 11 and encryption key generator 13 . from the transmit signal a , the encryption key generator 13 generates an encryption key ka . the encryption key ka is a signal similar to the transmit signal a , divided into packets . the encryption key ka is stored in the memory 14 and thereby delayed . the encryption circuit 11 reads the delayed encryption key dka from the memory 14 and uses it to encrypt the transmit signal a . the transmitting circuit 12 receives the encrypted signal ca and converts it to a modulated signal mca for transmission on the communication channel 300 . the receiving section 20 comprises a receiving circuit 21 , a decryption circuit 22 , a decryption key generator 23 , and a memory 24 . the receiving circuit 21 receives a modulated signal mcb from the communication channel 300 and demodulates it . the resulting demodulated signal is an encrypted signal cb , which comprises successive packets that are received intermittently . the decryption circuit 22 decrypts the encrypted signal cb by use of a delayed decryption key dkb read from the memory 24 , and outputs the decrypted signal as a receive signal b ′. from the receive signal b ′, the decryption key generator 23 generates a decryption key kb . the memory 24 stores and thereby delays the decryption key kb , which becomes the delayed decryption key dkb . the receiving section 60 in the second device 6 comprises a receiving circuit 61 , a decryption circuit 62 , a decryption key generator 63 , and a memory 64 , which are similar to the corresponding elements in the receiving section 20 of the first device 1 . the receiving circuit 61 receives the modulated signal mca and outputs an encrypted signal ca , which is decrypted by the decryption circuit 62 to obtain a receive signal a ′. the decryption key generator 63 generates an encryption key ka from the receive signal a ′, and the memory 64 stores the encryption key ka , supplying a delayed encryption key dka to the decryption circuit 62 . the transmitting section 70 comprises an encryption circuit 71 , a transmitting circuit 72 , an encryption key generator 73 , and a memory 74 , which are similar to the corresponding elements in the transmitting section 10 of the first device 1 . the encryption circuit 71 encrypts a transmit signal b , which comprises intermittent packets . the transmitting circuit 72 modulates the signal mcb according to the encrypted signal cb . the encryption key generator 73 converts the transmit signal b to an encryption key kb , which is stored in the memory 74 and supplied to the encryption circuit 71 as a delayed encryption key dkb . various encryption methods can be employed , such as the exclusive logical or method mentioned above , or another method involving reversible arithmetic and logic operations . signals a and b may be encrypted by different methods . various methods can be used to generate encryption and decryption keys from the transmit and receive signals . for example , the order of bits in the transmit and receive signals can be permuted according to a fixed rule to generate the encryption and decryption keys . the transmission and reception of signal a are independent of the transmission and reception of signal b . if the receiving section 20 and transmitting section 70 are eliminated , as shown in fig2 , the resulting system is still capable of transmitting signal a in encrypted form from the first device 1 to the second device 6 . the following description will be confined to the simplified uni - directional system shown in fig2 , but the description applies equally to the transmission of signal b in fig1 . initially , the memories 14 , 64 store predetermined initial key values , such as all - zero values . upon receiving the first packet of a transmission , the encryption circuit 11 reads the initial key value from the memory 14 and uses it to generate the first encrypted packet . at the same time , the encryption key generator 13 uses the first packet to generate a new encryption key , which is then stored in the memory 14 . the first encrypted packet is transmitted to the second device 6 and decrypted by use of the initial key stored in memory 64 . the decryption key generator 63 generates a new decryption key from the decrypted packet , and stores it in memory 64 . this process continues . fig3 a illustrates four successive packets a ( n − 2 ), a ( n − 1 ), a ( n ), a ( n + 1 ) of transmit signal a , where n is an arbitrary integer equal to or greater than three . as shown , the packets may be separated by unequal gaps of arbitrary length . fig3 b illustrates the corresponding encrypted packets ca ( n − 2 ) to ca ( n + 1 ); fig3 c illustrates the corresponding received packets a ′( n − 2 ) to a ′( n + 1 ). when the encryption circuit 11 receives packet a ( n − 2 ), it uses the key currently stored in memory 14 as an encryption key to generate an encrypted signal ca ( n − 2 ). at the same time , the encryption key generator 13 uses packet a ( n − 2 ) to generate a new encryption key ka ( n − 2 ). next , this encryption key ka ( n − 2 ) is stored in the memory 14 , and the transmitting circuit 12 converts the encrypted signal ca ( n − 2 ) to a modulated signal mca ( n − 2 ). in the second device 6 , the receiving circuit 61 demodulates the modulated signal mca ( n − 2 ) to obtain the encrypted signal ca ( n − 2 ). the key currently stored in memory 64 matches the key that was read from memory 14 during the encryption of signal a ( n − 2 ). the decryption circuit 62 uses this key to decrypt the encrypted signal ca ( n − 2 ), obtaining a receive packet a ′( n − 2 ) identical to the transmit packet a ( n − 2 ). the decryption key generator 63 generates a decryption key ka ( n − 2 ) from the receive signal a ′( n − 2 ), and stores it in memory 64 . the decryption key ka ( n − 2 ) is identical to the encryption key ka ( n − 2 ) generated by the encryption key generator 13 in the first device 1 . when the encryption circuit 11 receives the next packet a ( n − 1 ), it uses the key now stored in memory 14 as an encryption key to generate an encrypted signal ca ( n − 1 ). this key is denoted dka ( n − 2 ) in fig3 a and 3b , although it is identical to the key ka ( n − 2 ) written previously by the encryption key generator 13 . the corresponding modulated signal mca ( n − 1 ) is transmitted on the communication channel 300 to the second device 6 , and demodulated by the receiving circuit 61 , which outputs the encrypted signal ca ( n − 1 ). the decryption circuit 62 uses the key now stored in memory 64 , denoted dka ( n − 2 ) but identical to the key ka ( n − 2 ) written previously by the decryption key generator 63 , to decrypt the encrypted signal ca ( n − 1 ) and obtain the next receive packet a ′( n − 1 ). in the meantime , the encryption key generator 13 in the first device 1 generates the next encryption key ka ( n − 1 ) from packet a ( n − 1 ) and stores it in memory 14 . the decryption key generator 63 in the second device 6 generates an identical decryption key ka ( n − 1 ) from the receive packet a ′( n − 1 ) and stores it in memory 64 . packet a ( n ) is now encrypted by use of delayed key dka ( n − 1 ), identical to ka ( n − 1 ), and the encrypted signal ca ( n ) is decrypted by use of the same delayed key dka ( n − 1 ) to obtain receive packet a ′( n ). new keys ka ( n ) are generated from a ( n ) and a ′( n ) and stored in the memories 14 , 64 . then packet a ( n + 1 ) is encrypted by use of delayed key dka ( n ), identical to ka ( n ), and the encrypted signal ca ( n + 1 ) is decrypted by use of the same delayed key dka ( n ) to obtain receive packet a ′( n + 1 ). in other words , after the first packet , each packet is encrypted and decrypted by use of a key generated from the preceding packet . this system is simple because it generates key information from the transmit and receive signals , and therefore does not require circuitry to generate random patterns . the system is secure in that the key is constantly changing . moreover , the system enables a signal transmitted from the first device 1 to the second device 6 to be encrypted and decrypted without reliance on a signal transmitted from the second device 6 to the first device 1 , so it is particularly useful in packet transmission systems and other intermittent transmission systems . as a second embodiment of the invention , fig4 shows a system comprising a first device 2 having a transmitting section 30 and a receiving section 40 , and a second device 7 having a receiving section 80 and a transmitting section 90 . these sections and their constituent elements are equivalent to the corresponding elements in the first embodiment , but with additional functions and elements for detecting transmission errors and sending and receiving initialization command , control , and reply signals . the transmitting section 30 in the first device 2 has an encryption circuit 31 , a transmitting circuit 32 , an encryption key generator 33 , a memory 34 , and an initialization control signal generator 35 . the initialization control signal generator 35 receives an error detection signal edb from the receiving section 40 , and supplies a corresponding initialization control signal ipb to the transmitting circuit 32 for transmission on the communication channel 300 . ipb is supplied and transmitted as a packet . the initialization control signal generator 35 also receives a report - of - initialization signal ( ria ) from the receiving section 40 , and supplies a corresponding initialization reply signal ( ira ) to the transmitting circuit 32 for transmission as a packet on the communication channel 300 . the receiving section 40 has a receiving circuit 41 , a decryption circuit 42 , a decryption key generator 43 , and a memory 44 . the receiving circuit 41 tests the validity of a frame check sequence ( fcs ) included in each packet to detect transmission errors , and generates the error detection signal edb when an invalid fcs is detected . if the receiving circuit 41 receives an initialization control packet ipa from the second device 7 , it sends an initialization command ica to the encryption circuit 31 , encryption key generator 33 , and memory 34 in the transmitting section 30 . if the receiving circuit 41 receives an initialization reply signal ( irb ) from the second device 7 , it sends an initialization command rcb to the decryption circuit 42 , decryption key generator 43 , and memory 44 . the receiving section 80 in the second device 7 has a receiving circuit 81 , decryption circuit 82 , decryption key generator 83 , and memory 84 , which are similar to the corresponding elements in the receiving section 40 in the first device 2 . the transmitting section 90 in the second device 7 has an encryption circuit 91 , a transmitting circuit 92 , an encryption key generator 93 , a memory 94 , and an initialization control signal generator 95 which are similar to the corresponding elements in the transmitting section 30 in the first device 2 . the receiving circuit 81 generates an error detection signal eda , a report - of - initialization signal ( rib ), and initialization command signals rca and icb . the initialization control signal generator 95 generates an initialization control signal ipa and an initialization reply signal ( irb ). the system in fig4 is bi - directional , transmitting a signal a from the first device 2 to the second device 7 , and a signal b from the second device 7 to the first device 2 . fig5 shows a variation of the second embodiment adapted for transmission of signal a without transmission of signal b . the first device 2 includes the encryption circuit 31 , transmitting circuit 32 , encryption key generator 33 , memory 34 , initialization control signal generator 35 , and receiving circuit 41 of fig4 , the initialization control signal generator 35 now being external to the transmitting section 30 . the second device 7 includes the receiving section 80 , transmitting circuit 92 , and initialization control signal generator 95 of fig4 . the operation of the second embodiment will be described in relation to the variation in fig5 , but similar operations take place when signal b is transmitted in fig4 . fig6 depicts the operation from a point at which a packet a ( m ) is encrypted in the first device 2 , using a key generated from the preceding packet a ( m − 1 ) as described in the first embodiment ( step s 1 ). the encrypted packet ca ( m ) is transmitted as a modulated signal mca ( m ) to the second device 7 and decrypted using the same key , which is generated from the preceding received packet a ′( m − 1 ), as also described in the first embodiment ( step s 2 ). this process continues as long as no transmission errors are detected . if at some point a packet a ( n ) encrypted by the first device 2 ( step 11 ) is corrupted in transmission , the error is detected by the fcs check performed by the receiving circuit 81 in the second device 7 ( step s 12 ). the receiving circuit 81 then sends an error detection signal eda to the initialization control signal generator 95 . the initialization control signal generator 95 generates an initialization control signal ipa and supplies it as a maintenance packet to the transmitting circuit 92 ( step 13 ). the transmitting circuit 92 transmits this ipa packet to the first device 2 . if the ipa packet is received without error , the receiving circuit 41 in the first device 2 sends an initialization command signal ica to the encryption circuit 31 , encryption key generator 33 , and memory 34 , thereby initializing the transmitting section 30 ( step s 14 ). at the same time , the receiving circuit 41 reports the reception of the ipa packet by sending a report - of - initialization signal ria to the initialization control signal generator 35 , which generates an initialization reply signal ira and supplies it as a maintenance packet to the transmitting circuit 32 . the transmitting circuit 32 transmits this ira packet to the second device 7 . if the ira packet is received without error , the receiving circuit 81 in the second device 7 sends an initialization command signal rca to the decryption circuit 82 , decryption key generator 83 , and memory 84 , thereby initializing the receiving section 80 ( step s 15 ). thus ipa is the trigger for initialization of the transmitting section 30 , while ira is the trigger for initialization of the receiving section 80 . after this initialization , both memories 34 , 84 hold the same initial key value , such as an all - zero value . the encryption circuit 31 in the first device 2 now encodes the next packet a ( n + 1 ), using the initial key ( step s 16 ). the encrypted packet ca ( n + 1 ) is transmitted as a modulated signal mca ( n + 1 ) to the second device 7 and decrypted , using the same initial key ( step s 17 ). the next packet a ( n + 2 ) is encrypted in the normal way in the first device 2 , using a key generated from the preceding packet a ( n + 1 ) ( step s 18 ). in the second device 7 , the encrypted packet ca ( n + 2 ) is decrypted by use of a key generated from the preceding received packet a ′( n + 1 ) ( step s 19 ). the second embodiment provides a way to recover from transmission errors without retransmitting the erroneous packet . the second embodiment is particularly useful in systems that must operate in real time and cannot afford to retransmit erroneous packets . if the system provides for retransmission of erroneous packets , either the first or the second embodiment can be employed . in a variation of the second embodiment , the receiving circuit 81 also detects missing packets , by use of packet serial numbers , for example , and generates an error detection signal eda when a packet is either corrupted or missing . as a third embodiment of the invention , fig7 shows a uni - directional transmission system comprising a first device 3 having a transmitting section 50 , and a second device 8 having a receiving section 100 . the transmitting section 50 comprises an encryption circuit 51 , a transmitting circuit 52 , an encryption key generator 53 , and a memory 54 , which are similar to the corresponding elements in the first embodiment , and a pseudo - random pattern generating circuit 55 and scrambling circuit 56 . the receiving section 100 comprises a receiving circuit 101 , a decryption circuit 102 , a decryption key generator 103 , and a memory 104 , which are similar to the corresponding elements in the first embodiment , and a pseudo - random pattern generating circuit 105 and descrambling circuit 106 . the two pseudo - random pattern generating circuits 55 , 105 generate identical pseudo - random patterns ra . the transmit signal a received by the transmitting section 50 is first scrambled by the scrambling circuit 56 , using the pseudo - random pattern ra supplied by the pseudo - random pattern generating circuit 55 . various well - known scrambling methods can be used , such as the exclusive logical or method described above . the resulting scrambled signal sa is then encrypted by the encryption circuit 51 , using a delayed encryption key dksa read from the memory 54 . the transmitting circuit 52 converts the encrypted signal csa to a modulated signal mcsa for transmission to the second device 8 . the encryption key generator 53 generates a new key ksa from the scrambled signal sa , and stores the new key in the memory 54 , from which it will be read as the delayed encryption key dksa for the next scrambled packet . in the second device 8 , the receiving circuit 101 demodulates the modulated signal mcsa to obtain the encrypted signal csa , which is decrypted by the decryption circuit 102 , using a delayed decryption key dksa read from the memory 104 . the decrypted signal is the scrambled signal sa , from which the decryption key generator 103 generates a new decryption key ksa . the new decryption key ksa is stored in the memory 104 , from which it will be read as the next delayed decryption key . the scrambled signal sa is descrambled by the descrambling circuit 106 , using the pseudo - random pattern ra supplied by the pseudo - random pattern generating circuit 105 , to obtain the receive signal a ′. in the first and second embodiments , a party intercepting the communication between the first device and the second device may attempt to decrypt each packet on the assumption that it was encrypted with the initial key value . in this way , the intercepting party may succeed in decrypting the first packet transmitted in the first embodiment , or a packet transmitted after a transmission error in the second embodiment . if the decrypted packet includes a text message , for example , the intercepting party will know that he has decrypted the packet successfully because the decrypted message will be in plain text . the intercepting party may then be able to determine how the key is generated and decrypt the succeeding packets as well . in the third embodiment , even if an intercepted packet is correctly decrypted , the intercepting party obtains only a scrambled message , and cannot easily recognize that the packet has been decrypted correctly . this makes it extremely difficult for the intercepting party to determine how the key is generated , and how the packets have been scrambled . the third embodiment accordingly provides a higher level of security than the first and second embodiments . this higher level of security can moreover be obtained with a comparatively short pseudo - random pattern , because the key changes from packet to packet , so that even if two packets are scrambled in the same way , they will not be encrypted in the same way . differing from the prior art , the third embodiment does not require long pseudo - random patterns or complex and expensive pseudo - random pattern generating circuits in order to protect the privacy of communications . the third embodiment can be modified for bi - directional communication , by adding a receiving section to the first device 3 and a transmitting section to the second device 8 . the third embodiment can also be varied by providing for initialization in case of transmission errors , as in the second embodiment . in the description of the first embodiment , the delay of the encryption and decryption keys in the memories 14 , 64 was assumed to be equal to the length of one packet , but this is not a requirement . the delay can have any fixed value , expressed as a fixed number of bits with respect to the transmit and receive signals . in the description of the first embodiment , the packets were implicitly assumed to be of equal length , but this is not a requirement either . the packets may have variable length . the encryption key used to encrypt the transmit signal need not be identical to the decryption key used to decrypt the encrypted signal . the decryption key may be complementary to the encryption key , for example . any of the preceding embodiments can be modified for communication among more than two devices . the invention can be used in a packet - switching network , for example . the invention can also be used in systems that transmit signals continuously , instead of intermittently . the invention is particularly useful in uni - directional systems , as illustrated in fig2 and 5 . those skilled in the art will recognize that further variations are possible within the scope claimed below .