an on - chip in - circuit - emulator system that provides debug memory mapping and breakpoints is disclosed . in the following description , for purposes of explanation , specific nomenclature is set forth to provide a thorough understanding of the present invention . however , it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention . furthermore , well known circuits and devices are shown in block diagram form in order not to obscure the present invention unnecessarily . fig1 illustrates a prior art computer system comprising a central processing unit ( cpu ) 110 , a main memory 150 , and an i / o device 140 . the central processing unit ( cpu ) 110 is coupled to an i / o device 140 by an i / o system bus 105 . the central processing unit ( cpu ) 110 is also coupled to a main memory 150 by a memory bus 115 . while developing the computer system , the main memory 150 and i / o device 140 may not operate properly and require debugging . to help debug the computer system , an in - circuit - emulator ( ice ) system is used . the in - circuit - emulator monitors and controls transactions on the buses using an in - circuit - emulator bus controller 120 to help the user debug the computer system . an in - circuit - emulator usually contains a memory address space that can be used to supply information to the computer system being developed . fig1 also illustrates a debug memory 130 that comprises the memory address space for an in - circuit - emulator . to access the debug memory 130 , an in - circuit - emulator bus controller 120 monitors the memory bus for special addresses . when the in - circuit - emulator bus controller 120 detects a bus cycle on the memory bus 115 containing one of the special addresses , the in - circuit - emulator bus controller 120 directs the bus cycle to the debug memory 130 . the in - circuit - emulator system depicted in fig1 is typical of the prior art . such prior art in - circuit - emulator systems limit the speed at which the central processing unit 110 can operate since the in - circuit - emulator bus controller 120 introduces propagation delays into the computer system . the present invention proposes an in - circuit - emulator memory mapping system that is contained on the microprocessor silicon die itself . by placing the in - circuit - emulator memory mapping system on the microprocessor silicon die , significantly less propagation delay is introduced into the computer system by the in - circuit - emulator . fig2 illustrates a computer system equipped with the ice memory mapping system of the present invention . note that in the ice memory mapping system of the present invention there is no bus controller that splits either of the external buses thus eliminating the propagation delays introduced into the system by the prior art . referring to fig2 the debug memory 240 is coupled to the memory bus 217 just like the main memory 230 . however , one special line , called the ice address data strobe ( iads ) 250 , couples an ice module 330 in the central processing unit 210 to the debug memory 240 . the central processing unit 210 asserts the ice address data strobe ( iads ) 250 line when a bus cycle should be directed to the debug memory 240 instead of the main memory 230 . fig3 illustrates an internal block diagram of the central processing unit 210 . the central processing unit 210 contains a central processing unit core 310 that performs the actual computer processing . coupled to the central processing unit core 310 is an internal bus referred to as the h bus 315 . the h bus 315 is further coupled to an internal bus controller 320 . the internal bus controller 320 functions as a bus transceiver for an isa / pi bus controller 340 and a memory controller 350 . to direct bus cycles to the debug memory 240 illustrated in fig2 the central processing unit 210 contains an internal ice memory mapping module 330 . referring back to fig3 the internal ice memory mapping module 330 is coupled to the fi bus 315 and to the internal bus controller 320 . the internal bus controller 320 contains a pair of match registers ( user address registers 322 and 324 ) that are used to activate the internal ice memory mapping module 330 when a match occurs . a user sets user address registers 322 and 324 to address values that the user desires to have mapped into the debug memory 240 address space . when the internal bus controller 320 detects a match between the h bus 315 and one of the user address registers , the internal bus controller 320 activates the internal ice memory mapping module 330 . the internal ice memory mapping module 330 then generates a physical address using a pair of registers , asserts the ice address data strobe ( iads ) line 250 , and routes the generated physical address to the debug memory 240 . fig4 illustrates a block diagram of the internal bus controller 320 and the ice memory mapping module 330 . at the top of fig4 the incoming h bus address is illustrated . the upper 16 bits of the h bus address are directed into a comparator 410 . the comparator 410 compares the upper 16 bits of the h bus address with 16 bits provided by the user in the user address registers 322 and 324 . if the address on the upper 16 bits of the h bus address matches the 16 bits in either of the user address registers 322 and 324 , the ice memory mapping module 330 directs the bus cycle to the debug memory 240 by generating a physical address and asserting the ice address data strobe ( iads ) line 250 . to generate a physical address for the debug memory 240 , the ice memory mapping module 330 first encodes the four byte enable bits ( be3 - be0 ) into low address bits ( a1 and a0 ) and a byte high enable bit using encoder 430 . the next fourteen address bits are taken directly from the h bus address and passed through unmodified . finally , for the upper 8 bits , the ice memory mapping module 330 uses bits from the value stored in a pair of 8 bit long ice address registers 422 and 424 . if the value on the h bus matches the value in the first user address register 322 , then the 8 bits in the first ice address register 422 are used . otherwise , if the value on the h bus matches the value in the second user address register 324 , then the 8 bits in the second ice address register 424 are used . a multiplexor 420 controlled by comparator 410 directs the proper ice address register into the upper 8 bits of the ice physical ddress . to operate the internal ice memory mapping module 330 , the central processing unit 210 must be reset while asserting a special ice input pin ( not shown ) high . the user then sets address ranges to be mapped into the debug memory 240 address space by setting the user address registers 322 and 324 in the internal bus controller 320 . a user sets the user address registers by executing an i / o write instruction to reserved i / o address . the user will only be able to execute the i / o write instruction to the reserved i / o address if the central processing unit 210 was reset while asserting the special ice input pin . fig5 illustrates the components of a user address register . the least significant 16 bits of a user address register are matched against the most significant 16 bits of the h bus value . the number of bits compared depends upon the granularity setting in bits 28 - 30 of the user address register . to map 64k of memory into the debug memory , the users sets the granularity bits such that all 16 bits are compared during the comparison . if the user wants to map more memory , the user changes the granularity bits to specify that less bits be compared , down to a minimum of 12 bits such that 1 meg of memory is mapped . finally , two control bits in the user address register specify how the mapping system should treat the system memory mode ( smm ). if bit 27 of a user address register is set , then ice memory mapping is only enabled when the central processing unit is in the smm mode . alternatively , if bit 31 is set , then ice memory mapping is only enabled when the central processing unit is not in smm mode . however , if both bit 27 and bit 31 of the user address register are set , then ice memory mapping is disabled such that no ice memory mapping occurs . most in - circuit - emulators commonly offer a breakpoint system that allows a user to set certain conditions that will cause the central processing trait to halt execution . for example , a user can set the in - circuit - emulator to halt when the central processing unit accesses a particular address on an external bus . in prior art in - circuit - emulators , the in - circuit - emulator monitors an external bus to detect when the central processing unit accesses a particular address . some highly integrated central processing units have more than one external bus upon which a bus cycle may occur . thus , in such systems the in - circuit - emulator must monitor all the different external buses . for example , referring again to fig1 a computer system with a prior art in - circuit - emulator system is illustrated . in the prior art in - circuit - emulator system illustrated in fig1 the in - circuit - emulator system must monitor both the i / o bus 105 and the memory bus 115 coupled to the central processing unit 110 . monitoring multiple external buses increases the complexity and cost of the in - circuit - emulator system . furthermore , the ice external bus controller introduces propagation delays into the computer system as explained in the previous section . the present invention proposes a on - chip breakpoint system that monitors only a single internal bus even if multiple external buses exist . the on - chip breakpoint system also monitors an internal bus controller that specifies which external bus , if any , each bus cycle is for . referring to fig6 an internal block diagram of a central processing unit 210 containing the internal ice breakpoint module of the present invention . the central processing unit 110 contains a central processing unit core 310 that performs the processing . coupled to the central processing unit core 310 is an internal bus referred to as the h bus 315 . the h bus 315 is further coupled to an internal bus controller 320 . the internal bus controller 320 functions as bus transceiver for an isa / pi bus controller 340 and an external memory controller 350 . the isa / pi bus controller 340 and the external memory controller 350 each control external buses . in the present invention as illustrated in fig6 an ice breakpoint module 610 is coupled to the internal h bus 315 of the central processing unit 210 . the ice breakpoint module 610 is also coupled to the internal bus controller 320 such that the ice breakpoint module 610 receives certain control signals from the internal bus controller 320 . specifically , the control signals from the internal bus controller 320 inform the ice breakpoint module 610 which external bus , if any , each bus cycle is for . the ice breakpoint module 610 monitors the internal h bus 315 and the control signals from the internal bus controller 320 to detect certain conditions set by a user in a set of breakpoint registers 615 . the user sets the breakpoint conditions by setting the breakpoint registers 615 in the ice breakpoint module 610 . fig7 provides a detailed illustration of the set of breakpoint registers . the breakpoint registers comprise two physical address match registers , two data match registers , and two control registers . the physical address match registers are used to look for particular physical addresses on the h bus 315 . the data match registers are used to look for particular data values on the h bus 315 . the two control registers are used to set specific conditions to look for . the following list provides the set of control bits available within the breakpoint two control registers : smm [ i ]: smm space enable ( 00 = disable breakpoints , 01 = smm mode , 10 -- non -- smm mode , 11 -- either mode ) iio [ i ]: internal io breakpoints ( 0 = external or internal bus cycle , 1 = internal bus cycle only ) rw [ i ]: read / write cycle bits ( 00 = reserved , 01 = data write , 10 = data read , 11 = data read or write ) len [ i ]: breakpoint field width encoding ( 00 = 1 byte , 01 = 2 bytes , and 11 = 4 bytes ) to modify the comparison parameters of the ice breakpoint module 610 , the user simply sets the control bits in the control registers as desired . for example , if a user desires to have the central processing unit 210 halt when a particular physical address on the external peripheral interface ( pi ) bus is accessed , the user stores the physical address into one of the breakpoint physical address match registers and sets the pi control bit in the control register . when an access to the external peripheral interface ( pi ) bus occurs with the specified physical address , the ice breakpoint module will halt the central processing unit core 310 . in the foregoing specification , the invention has been described with reference to specific exemplary embodiments thereof . however , it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the following claims . accordingly , the specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense .