referring to fig1 a method of processing a computer representation of design elements of a semiconductor device is illustrated . the method includes determination ( 102 ) of particular design instances of standard threshold voltage ( standard v t ) logic cells to swap for low threshold voltage ( low v t ) instances . after determining the particular cell instances for substitution , the particular cell instances are swapped by substituting ( 104 ) information corresponding to low v t physical files , low v t schematic representations , and low v t timing files for that associated with respective standard v t cells . in a particular implementation , two substantially co - extensive cell libraries may be provided . for example , a standard v t library may be provided that includes standard v t type transistors , circuit and gate configurations implementing cells of the library , while a low v t library includes low v t type transistors , circuit and gate configurations implementing corresponding cells . in such an implementation , swapping a particular cell instance from standard v t to low v t simply involves substituting information for a corresponding cell from a different library . after the selected cells of the design have been substituted from standard v t to low v t cells , design verification tests , such as noise tests , minimum timing tests , and physical verification tests , may be re - executed ( 106 ) to verify the new design that includes the substituted low v t cells . an advantageous characteristic of low v t cells is reduced delay as compared to corresponding standard v t cells . as a result , use of a low v t cell instance in substitution for a cell instance that contributes to a max - time violation in a timing path may allow an integrated circuit design to operate at a higher frequency . indeed , use of low v t transistors may improve cycle time by 15 % in certain gate - dominated delay paths . if low v t cell substitutions are prioritized and applied in a way that does not unacceptably degrade other characteristics of a semiconductor device , such as noise susceptibility , margins and / or overall leakage current , improved device performance and / or yield at grade can be achieved . preferably , substitutions made during a design phase can be constrained to obviate a full - battery of post - substitution timing analysis . improved performance can be particularly desirable in integrated circuits , such as microprocessor integrated circuits , where high - speed - grade parts demand a substantial premium in the marketplace . fig2 demonstrates an exemplary reduction in speed - grade limiting timing violations resulting from the techniques described herein to a microprocessor design . by selectively substituting low v t cells , critical timing violations are eliminated , as evidenced by the shifting of the tail of the illustrated histogram , and resulting microprocessor integrated circuits can be expected to operate at a higher frequency . while low v t cells offer reduced delay , they also tend to exhibit a higher leakage current than standard v t cells . many applications for high - speed processors also require low current and power usage . accordingly , while such applications can benefit from substitution of many cells with low v t cells , wholesale substitution of all cells is generally not acceptable since such substitution tends to result in leakage current and noise levels that exceed design requirements . in addition , low v t transistors are generally more sensitive to voltage variations at their input gates . accordingly , certain otherwise desirable substitution opportunities may be undesirable when particular electrical characteristics of input nets are considered . [ 0017 ] fig3 illustrates in further detail a method of processing design files for a semiconductor device . a portion of a design file for a semiconductor device that contains max - time violating circuit paths is received or accessed at 302 . each of the max - time violating circuit paths , i . e ., those circuit paths having a signal propagation delay that exceeds a desired end - to - end timing requirement , typically contain multiple circuit elements , cells , transistors , or more generally , gate instances , for which substitution with a low v t instance may be possible . for example , in a circuit path characterized primarily by logic delays through standard cell implementations of logic gates , substitutable gate instances may implement logic gate such as a logic “ and ” or a logic “ or ” function , while in others , substitutable gate instances may correspond to larger or smaller aggregations of circuit features , including circuit blocks or individual transistor gate instances . of course , as previously described , an appropriate level of aggregation for gate instances may vary from exploitation to exploitation , and indeed , even within a given exploitation . accordingly , as before , persons of ordinary skill in the art will appreciate a suitable range of exploitations based on the description herein . a set of gate instances is prioritized based on a metric that tends to emphasize those gate instances that contribute significantly to larger numbers of those time violating circuit paths that exhibit the greatest violations . while any of a variety of metrics may be suitable , and may fall within the scope of claims that follow , a particular metric is illustrative . fom i = ∑ j = 1 count i  violation j × delay i , where violation j is a measure of timing violation for path j of count i maximum time violating paths through gate instance i and delay i is a weighting factor based on delay through gate instance i . in calculating such a metric , fom , it may be desirable to eliminate or skip those gate instances for which substitution may not be appropriate . for example , in some realizations , a low v t instance may not exist for certain design features and prioritization can be forgone . similarly , in some realizations , certain gate instances may not be considered for substitution . for example , flops or more generally gate instances or cells with min - time design requirements may be eliminated from consideration or skipped . whatever the appropriate set or subset of gate instances , they are prioritized based on a metric that incorporates contributions for multiple time violating paths therethrough . referring to fig3 a metric may include contributions corresponding to each time violating circuit path that includes a gate instance and which is weighted based on the gate delay for the particular gate instance ( see 306 ). a prioritized set of the gate instances is created . based in part on a leakage current budget , a subset of the gate instances from the prioritized list are selected ( 308 ) for low v t substitution . for example , for each of the selected gate instances , a standard cell may be substituted with low v t version of the cell and a design file , referred to as a second design file , is created at 310 . whether the second is a new design file , a revised version of a first design file , or set of overrides is generally a matter of design preference . in any case , the second design file encodes ( either in whole or in part ) representations for the low v t substituted cells . a resulting design that includes the low v t substituted cells is then tested at 312 . such testing may include design rule tests , noise tests , and for minimum timing tests . such tests are typically performed using computer - based software tools . after testing the second design , the second design may then be used to create masks for fabricating a semiconductor device to be constructed in accordance with the second design . the semiconductor device may then be fabricated at 314 . in general , any of a variety of suitable fabrication methods may be employed . referring to fig4 a and 4b , another representation of a method of processing a design file for a semiconductor device is shown . a timing report for a microprocessor design that shows time violating circuit paths is received or accessed at 402 . by evaluating this first input file , which may be a pearl timing report , an analysis of each timing path violation may be conducted . in a typical realization , the timing path violation report lists the devices ( including gates that are in the timing path ) and separates the delay into two components : wire delay and gate delay . the method flow then parses the time report to identify timing paths in the report and creates a database for each gate instance in the design . that is , for each gate instance the method determines ( 1 ) the number of times that such gate instance is part of a violating timing path ; and ( 2 ) calculates the summation , over each of these instances , of the path timing violation multiplied by the gate delay . this calculation provides a weighted metric that represents a benefit from swapping this particular gate instance to a low v t cell . then , this set of gate instance entries may be sorted in priority order according to those gates that would have the most impact on cycle - time . logically , the gate instances with larger intrinsic delays that are located inside of relatively more violating timing paths would be near the top of this prioritized list . this summation and weighted contribution can be denoted as : it should be noted that the database created is based on gate instances , not based on merely the cell name . since instances of a particular cell may be using in an integrated circuit design at many locations , there are typically many gate instances that correspond to a particular standard cell design . the design is analyzed to identify those instances can be swapped for low v t variants to improve performance of the integrated circuit design . for example , a particular standard cell design for a particular n - input logic gate may be used 250 times in an integrated circuit design . accordingly , the integrated circuit design includes 250 gate instances corresponding to the standard cell . however , each instance plays a different role in performance of the integrated circuit design . for example , some instances may not be part of any max - time violating circuit path . on the other hand , a single one of the 250 instances may be part of 63 different max - time violating paths . also , this one gate instance may exhibit a delay of 59 ps and may be the single greatest contributor to violations in the 63 timing paths . if a low v t instance of the n - input logic gate is 8 ps faster than a standard v t instance , then the substitution of just one gate instance for a low v t variant could improve the cycle - time of each of 63 different timing paths by approximately 8 ps . accordingly , using techniques such as described above , at least a subset of gate instances is prioritized for a given integrated circuit design . while some realizations may result in an absolute ordering , partial orderings or a simple selection of a subset of worst offender gate instances may be sufficient prioritization in some realizations . based on the description herein , persons of ordinary skill in the art will appreciate suitable prioritizations for a given design and / or computational environment and the claims that follow may be understood to encompass a variety of such prioritizations . given such a prioritization , selection of particular gate instances for substitution is now described . in general , any of a variety of substitution constraints can be applied in various realizations of present invention . for example , in one realization , a leakage current budget constraint and two noise - related constraints are applied in the selection of gate instances from the prioritized set . other realizations may employ these or other similar constraints , depending on implementation - specific design considerations . nonetheless , aspects of the present invention will be understood in the context of the following exemplary substitution constraints : a limit on capacitance at inputs of a substitution candidate , a limit on rc delay leading into inputs of a substitution candidate , and a total leakage current limit , or budget , expended incrementally as candidate gate instances are substituted for low v t variants . embodiments of the present invention may exploit some or all of these or other similar constraints . we now focus on exemplary noise - related constraints , referring to fig4 a and 4b . one factor in determining whether a particular gate instance is a good candidate for a low v t substitution is capacitance at inputs of a substitution candidate . for example , a capacitance value for an input ( or inputs ) of a particular gate instance is compared to a maximum capacitance value for such input at 412 . in the particular design process of fig4 a , if the capacitance at an input to the particular gate instance is greater than the maximum capacitance value , then the gate instance is discarded as a low v t substitution candidate and evaluation of candidates continues at 410 . if the capacitance value for the gate instance does not exceed the maximum capacitance value , other noise related constraints may be evaluated . ordering of such evaluations is somewhat arbitrary although evaluations that involve simpler computations may be computed first in some realizations . in some realizations , a flattened rc interconnect netlist may be accessed to determine capacitance at inputs to particular gate instances . since a low v t transistor ( or more generally , a gate instance that includes one or more low v t transistors ) is , in general , more sensitive to voltage variations on its input gate ( s ), a capacitance constraint helps to ensure that a standard v t instance is not swapped for a low v t instance if its input ( s ) is ( are ) coupled to highly capacitive ( i . e ., noisy ) nets . although a suitable maximum capacitance value is , in general , design specific , a 0 . 30 pf capacitance limit has been found to be suitable for some designs . another factor in determining whether a particular gate instance is a good candidate for a low v t substitution is rc delay leading into inputs of a substitution candidate . in this case , we are checking not just the capacitance of the net , but the rc component connected to the input of the gate instance . in some realizations , an rc delay file may be consulted for suitable characterizations at inputs of particular candidate gate instances . the rc delay value leading to the input of the particular gate instance is compared to a standard delay format ( sdf ) rc limit threshold at 414 . if the rc delay value exceeds this rc delay threshold , then the particular gate instance is discarded as a low v t substitution candidate and evaluation of candidates continues at 410 . if the rc delay value does not exceed the rc limit threshold , then the substitution constraint evaluation proceeds . although a suitable maximum rc delay limit is , in general , design specific , a 20 ps delay limit has been found to be suitable for some designs . each low v t substitution incrementally contributes to an increase in overall leakage current . accordingly , at decision step 416 , an accumulation of the extra leakage current ( including the contribution associated with the low v t substitution candidate ) is compared to a maximum leakage current threshold . if the accumulated sum of extra leakage current is less than or equal to the maximum leakage threshold at 416 , then the particular gate instance is added to a master low v t substitute swaplist at 418 . next , a decision check is performed to determine if the gate instance is the last gate instance on the priority list at 420 . if the evaluated gate instance is the last instance on the list , then the gate instance evaluation loop is exited and processing continues to step 422 . however , if the gate instance is not the last gate instance on the list , then processing continues back at step 410 for the next gate instance candidate . after processing all gate instances on the priority list , as determined at decision step 420 , or after expending the maximum leakage current budget at 416 , processing of the method continues at step 422 . at this point in the process , all gate instances that are on the master swaplist are then substituted for low v t cell types . referring to fig5 an illustrative semiconductor device 500 constructed in accordance with the method described herein and with substituted low v t gate instances is shown . the semiconductor device 500 includes input / output interconnects 502 and interconnected circuit and logic gate portion 504 . any of a variety of integrated circuit designs may be appropriate ; however , the circuit and logic gate portion 504 of the semiconductor device includes both standard v t threshold gate instances 506 and substituted low v t gate instances 508 . by providing low v t gate instances 508 , operating frequency for the particular semiconductor device 500 is increased and performance is improved . in addition , by using the illustrated methodology , an overall current leakage budget is maintained such that the semiconductor device 500 is within the suitable current leakage requirements . in some realizations , the actual swapping for cell instances from instances based on the standard v t library to the low v t library can be performed at the control logic standard cell place & amp ; route blocks and datapath blocks . for a block level low v t swapping phase there are , in general , two types of swapping : netlist swaps and opus view swaps . opus view swaps are done on layout and schematics . in the layout view of the software tool executed on an appropriate type of computer system or engineering workstation , a skill routine is used to swap the standard v t cell instances to low v t cell instances . for modification of the schematic , the user may take the low v t . vl netlist and perform verilogin in opus to create the schematic . in general , it can be difficult to take hierarchical data path block schematics that have dpmacros and swap specific instances because the dpmacros are arrayed instances of cells . since the low v t flow is designed to swap specific instances , it would be difficult to swap entire arrays of instances described by dpmacros . so instead , a verilogin operation may be performed for both place & amp ; route and datapath schematics , which creates a flat schematic with symbols connected “ by name .” a schematic that is connected “ by name ” means that it derives its connectivity by the names of the pins on the symbols , rather than drawing thousands of nets to connect the flat schematic symbols . an added benefit of using verilogin is that the schematic has the same connectivity as the . vl netlist for the design . during an engineering change order ( eco ) mode , an error may have occurred if the . vl netlist and the schematic were edited out of sync . so , if the low v t block is layout versus schematic ( lvs ) clean after schematic generation , then the . vl file and layout are synchronized . once all the netlists , layouts and schematics have been swapped to low v t , then minimum - timing regression tests can be run on each block to make sure that paths were not sped up to the point of causing min - time violations . referring again to fig4 a minimum timing regression test for a cpu level and at each block level for the new design with the substituted low v t gates is then executed at 424 . a noise regression test at the cpu and at the block level is performed at 426 , and a final maximum timing test is executed to determine a new frequency for the processor device design at 428 . a physical verification design rule test is performed at 430 , and , upon completion of the testing , a semiconductor device with the new design is then fabricated at 432 . other post substitution design qualifications may be performed in other realizations . an automated computer software semiconductor design tool , such as the commercially available design framework ii ( opus ) software tools available from cadence design systems , inc . may be used to process the design files and to implement the particular methodology disclosed in this application . in addition , design tools that support verilog or other hardware description languages may be employed . on the other hand , based on the description herein , persons of ordinary skill in the art will appreciate a variety of other implementations suitable for this and other design environments and languages . terminology used herein , which is particular to the above - identified design environments or languages , is meant to be illustrative and modifications , extensions and analogs suitable for other design environments will be appreciated based on the description herein . such modifications , extensions and analogs may fall within the scope of claims that follow . the above - disclosed subject matter is to be considered illustrative , not restrictive , and the appended claims are intended to cover all modifications and other embodiments which fall within the true spirit and scope of the present invention . thus , to the maximum extent allowed by law , the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents , and shall not be restricted or limited by the foregoing detailed description .