referring now to the drawings and , more particularly , to fig1 thereof , there is shown an overly simplified version of circuit means , generally designated 10 , constructed in accordance with the teachings of the present invention . from fig1 it can be seen that circuit means 10 basically consists of four switches , generally designated 11 - 14 , connected in a bridge configuration between a pair of input terminals 15 and 16 and a pair of output terminals 17 and 18 . for a positive polarity input signal v in ( input terminal 15 is positive and input terminal 16 is negative ), switches 11 and 14 would be closed , as shown , connecting output terminal 17 to input terminal 15 and output terminal 18 to input terminal 16 . at this time , switches 12 and 13 would be open , also as shown . in this manner , the output voltage v out will be equal to the input voltage v in and have the same polarity . if , on the other hand , the polarity of input signal v in is reversed so that input terminal 15 is negative and input terminal 16 is positive , switches 12 and 13 would be closed and switches 11 and 14 would be open . with this switch configuration , output terminal 17 is connected to input terminal 16 and output terminal 18 is connected to input terminal 15 . the magnitude of output voltage v out will remain the same , as will the polarity . accordingly , with such a simplified circuit , the output voltage polarity will remain coherent , i . e . output terminal 17 will always be biased positively with respect to output terminal 18 . according to the present invention , switches 11 - 14 are replaced by active semiconductor devices . while various active devices can be used , such as bipolar transistors , junction field - effect transistors and the like , in most applications , the characteristics of mos transistors are preferable since the controlling gate is isolated from the other device terminals and thus draws no current and can be connected to a wide range of voltages . the present invention will , therefore , be described hereinafter with reference to mos transistors . referring now to fig2 there is shown circuit means , generally designated 20 , which is similar to circuit means 10 , except that switches 11 - 14 have been replaced by active mos transistors , generally designated 21 - 24 . the source and drain of transistor 21 are connected between input terminal 15 and output terminal 17 , the source and drain of transistor 22 are connected between input terminal 16 and output terminal 17 , the source and drain of transistor 23 are connected between input terminal 15 and output terminal 18 , and the source and drain of transistor 24 are connected between input terminal 16 and output terminal 18 . each of transistors 21 - 24 has a gate , the gates of transistors 21 and 23 being connected to input terminal 16 and the gates of transistors 22 and 24 being connected to input terminal 15 . in the example shown , transistors 21 and 22 are p - channel mos transistors , while transistors 23 and 24 are n - channel mos transistors . in this initial simplification of circuit 20 , it is assumed that the effect of the substrates of transistors 21 - 24 may be ignored and that transistors 21 - 24 are enhancement types such that no drain - to - source current can flow in any transistor with the gate thereof connected to its respective source . for current to be able to flow , the gates of the p - channel transistors must be biased slightly negatively with respect to their sources and for the n - channel transistors , the gates must be biased slightly positively with respect to their sources . in operation , with an input voltage v in of greater than about + 0 . 5 volts between input terminals 15 and 16 , transistor 21 is turned or since its gate ( which is connected to input terminal 16 ) is negatively biased with respect to its source ( which is connected to input terminal 15 ). thus , terminal 15 is connected to terminal 17 . similarly , transistor 24 connects input terminal 16 to output terminal 18 while transistors 22 and 23 are open . by reversing the polarity of v in , it can be shown by similar reasoning that transistors 22 and 23 are closed and transistors 21 and 24 are open . in reality , mos transistors are truly four terminal devices , there beng a substrate gate in addition to the regular metal ( or silicon ) top - side gate . in some instances , it may be possible to leave the substrate gate as an open circuit , as in the case of silicon - on - sapphire ( sos ) technologies . however , using regular junction , isolated , complementary mos technologies ( cmos ), it is not possible to ignore the substrate gates since in integrated structures , substrates may be common to more than one transistor . in cmos technologies , where both p - and n - channel transistors can be integrated onto a single chip , in most instances , it is necessary to have circuitry that detects polarities between the substrates and the transistor drain / sources ( drain and sources are often symmetrical and interchangeable ) and connects the substrates to sources so that the intrinsic pn diodes formed by the sources and substrates are not forward - biased . if a source - substrate diode is forward - biased , operation of the mos transistor is modified and , furthermore , the characteristics of adjacent mos transistors may also be modified ( through minority carrier injection into the substrate caused by the forward - biasing of a source - to - substrate pn diode ). in order to eliminate this problem , circuit means 20 is modified , as shown in fig3 to provide circuit means 30 including four extra transistors , generally designated 31 - 34 , which are used solely to steer the substrate connections of all transistors to the correct points so that substrate - to - source diodes are not forward - biased . referring now to fig3 transistors 21 , 31 , 22 and 32 are all p - channel transistors , all of the substrates thereof being connected together at 35 . transistors 23 , 33 , 24 and 34 are all n - channel transistors , the substrates of which are all connected together at 36 . transistors 31 - 34 are connected across transistors 21 - 24 , respectively , as shown , and are used solely to sense the polarity of the input voltage and to connect the two common substrate points 35 and 36 to either terminal 15 or 16 , so that under all circumstances , points 35 and 36 will be respectively connected to the positive and negative terminals of the steering network . in operation , assume a voltage applied to terminal 15 which is at least a few tenths of a volt more positive than the voltage applied to terminal 16 . under such circumstances , transistors 21 , 31 , 24 and 34 will be turned on and transistors 22 , 32 , 23 and 33 will be turned off . transistor 31 will connect the common p - channel substrate point 35 to input terminal 15 and transistor 34 will connect the common n - channel substrate point 36 to input terminal 16 . thus , under all circumstances , the substrates will be connected to the positive ( p - channel substrates ) or negative ( n - channel substrates ) voltage points . the operation of transistors 21 - 24 is as described previously . in practice , of course , transistors 21 - 24 are not ideal switches . depending on the transistor configuration and sizes , each will have a finite on resistance ( approximately inversely proportional to the input voltage for low - threshold transistors ) and will have breakdown voltages which may range from a few volts to a few tens of volts . transistors 31 - 34 will often be much smaller than transistors 21 - 24 , since they do not have to carry large continuous currents . it can therefore be seen that according to the present invention , there is provided circuit means that accepts an input signal of either positive or negative polarity and produces an output signal having an open circuit voltage which is similar in amplitude to the input signal amplitude but has a defined polarity . such a circuit is useful in protecting electronic components from battery or power supply reversal . furthermore , in many applications , such a circuit would not cause a significant reduction in the applied output voltage as would be the case with a bridge rectifier . for many applications , the present invention would be a separate component in the system . on the other hand , it could readily be integrated onto a single monolithic integrated circuit containing additional functions without significantly increasing the cost thereof , making the present invention cost effective and an ideal solution for future integrated circuit designs . while the invention has been described with respect to the preferred physical embodiments constructed in accordance therewith , it will be apparent to those skilled in the art that various modifications and improvements may be made without departing from the scope and spirit of the invention . accordingly , it is to be understood that the invention is not to be limited by the specific illustrative embodiments , but only by the scope of the appended claims .