in accordance with embodiments of the present invention , circuits and methods to protect the 1 - hot vectors used in the tag cache are described herein . as a way of illustration only , two embodiments of the present invention are described : a 1 - hot plus valid bit and a 2 - hot vector scheme , however , these two embodiments should not be taken to limit any alternative embodiments , which fall within the spirit and scope of the appended claims . in general , a cache that stores 1 - hot vectors as tags is referred to as a 1 - hot tag cache and a cache that stores 2 - hot vectors as tags is referred to as a 2 - hot tag cache . a 1 - hot vector is an n - bit string that contains a single “ 1 ” and n − 1 “ 0 &# 39 ; s ”, for example , “ 00001000 ” is an eight - bit 1 - hot vector . similarly , a 2 - hot vector is an n - bit string that contains two consecutive “ 1 &# 39 ; s ” and n − 2 “ 0 &# 39 ; s ”, for example , “ 00011000 ” is an eight - bit 2 - hot vector . the right most “ 1 ” bit in a 2 - hot vector is called a primary bit and a left neighbor “ 1 ” bit of the primary bit is called an aux ( auxiliary ) bit . fig1 is a logic block diagram of a known implementation of a 1 - hot tag cache 119 . the 1 - hot tag cache 119 shown in fig1 is a 4 - way set associative cache , which means that four tags are stored for any given set ( row ) in the cache . in fig1 , the 1 - hot tag cache 119 is coupled to a tlb 109 , which includes a tlb virtual address array 110 . the 1 - hot tag cache 119 includes a 1 - hot tag array 120 , a cache data array 125 , comparators 130 - 133 , a first multiplexer 140 , and a second multiplexer 150 . in fig1 , during a read request , the tlb virtual address array 110 , receives a tag 102 from an incoming tag cache access address request 100 that specifies the desired tag in the tlb virtual address array 110 and , based on the virtual address stored in the specified tag , outputs an n - bit 1 - hot vector 112 , where the number of bits , n , in the 1 - hot vector is equal to the size of the tlb , that is , the number of tags in the tlb . at generally about the same time that the tlb virtual address array 110 receives the tag 102 , the 1 - hot tag array 120 receives an index address 104 that specifies which set , that is , row , in the 1 - hot tag array 120 to read out and , then , the 1 - hot tag array 120 reads out the tags from the memory cells in the specified set . the comparators 130 - 133 each receive one of the tags read out from the 1 - hot tag array 120 and the 1 - hot vector 112 from the tlb . each of the comparators 130 - 133 , then compares the 1 - hot vector 112 with the tag it received from the 1 - hot tag array 120 to determine if the received tag is the desired tag from the set . each of the comparators 130 - 133 , outputs a value representing whether the desired tag was located in that specific comparator to a first multiplexer 140 . the first multiplexer 140 also receives four - way data from the data cache array 125 as specified in the index address 104 and , then , based on the values of the comparators 130 - 133 , determines which one way of the four - way data to read out . if there is a match between the desired tag value and one of the four - way data values , the way that matched is read out of the first multiplexer 140 . the second multiplexer 150 receives the read - out data and a byte select value 106 from the incoming tag cache access address request 100 and , then , based on the byte select value 106 , the second multiplexer 150 outputs the desired data . fig2 is a circuit schematic diagram of a known 1 - hot tag memory cell architecture , illustrating how the 1 - hot tag cache can operate with no interaction between the memory bit circuits in the 1 - hot tag memory cell . in fig2 , the 1 - hot tag memory cell is shown to include word lines w 10 , w 11 and w 12 that are coupled to memory bit circuits 210 , 220 and 230 . the memory bit circuits 210 , 220 and 230 are coupled together with a plurality of other memory bit circuits to form an n - bit memory cell . in fig2 , for ease of illustration , only the memory bit circuits 210 , 220 and 230 are shown , the remainder being generally indicated by the dotting to the left of memory bit circuit 210 and to the right of memory bit circuit 230 . each of the memory bit circuits 210 , 220 and 230 include bit lines b 10 , b 11 and b 12 . the bit lines b 10 and b 11 can be used to read out the content of the memory bit circuits and b 12 can be used to write data to the memory bit circuits 210 , 220 and 230 . operation of the 1 - hot tag array . in fig2 , the 1 - hot tag array has two read ports . for a read operation in the 1 - hot tag array , either w 10 or w 11 can be asserted to read out a bit from each memory bit circuit 210 , 220 and 230 on the memory bit circuit &# 39 ; s b 10 or b 11 , respectively . in fig2 , performing a write operation in the 1 - hot tag memory cell requires two phases . in the first phase , in each memory bit circuit 210 , 220 and 230 , one or both of the bit lines b 10 and b 11 can be grounded to “ 0 ” and one or both of the word lines w 10 and w 11 can be asserted , to write a “ 0 ” into each memory bit circuit 210 , 220 and 230 . in the second phase , w 12 can be asserted and the data indicated on the b 12 line is a blind clear ( bc ) signal in an inverted form , which is the inverse of the data to be written to the 1 - hot array . that is , in the inverted form of the bc signal , in all of the memory bit circuits where a “ 1 ” is to be written the b 12 will have a value equal to “ 0 ” and in all memory bit circuits where a “ 0 ” is to be written the b 12 will have a value equal to “ 1 ”. in this way , the inverse of the 1 - hot vector is written into the memory cell , for example , if an 8 - bit 1 - hot vector value is “ 00010000 ” then an inverse 8 - bit bc signal , which will be written into the memory cell , is “ 11101111 ”. the bit values will be inverted when they are read out of the array , thus , producing the desired 1 - hot vector . in fig2 , to perform a blind invalidate in the 1 - hot tag memory cell , the w 12 line of all rows are asserted and each b 12 contains the non - inverted version of the 1 - hot vector bit , which clears the content of all of the memory bit circuits in the 1 - hot memory cell indicated by the 1 - hot vector . in accordance with an embodiment of the present invention , a 1 - hot plus valid bit scheme involves adding one bit to each 1 - hot vector to serve as a valid identification ( v id ) bit . in the 1 - hot plus valid bit scheme , while conceptually simple , a multi - cycle read - modify operation can be used to update the valid bit to avoid the timing impact . in addition , in accordance with an embodiment of the present invention , in the 1 - hot plus valid bit scheme an additional word line is used to read out the content of the 1 - hot column . therefore , in accordance with an embodiment of the present invention , in this scheme , a single bit is appended at the end of each 1 - hot vector to serve as the v id bit . fig3 is a circuit schematic diagram of a 1 - hot tag plus valid bit memory cell , illustrating the interaction between the memory bit circuits in the 1 - hot tag plus valid bit memory cell , in accordance with an embodiment of the present invention . in the circuit illustrated in fig3 , the v id bit memory bit circuit 340 is shown as an extra bit circuit coupled at the end of the plurality of memory bit circuits that make up the 1 - hot memory cell of fig2 . for the sake of clarity , an analogous memory bit circuit for the memory bit circuit 210 of fig2 has been omitted from fig3 . in fig3 , the structure of the v id bit memory bit circuit 340 is different than the memory bit circuits 320 and 330 in the 1 - hot memory cell in that the v id bit memory bit circuit 340 does not have the b 12 bit line . in place of the b 12 line is the output of a latch 344 . furthermore , the gate of transistor 300 , which , when turned on , can cause the value at the output of the latch 344 to affect the value stored in the v id bit memory bit circuit 340 , which is coupled to a bit enable line 348 . the embodiment in fig3 also has an additional word line w 13 , which is the input to the latch 344 . the w 13 word line also is coupled to transistors 322 and 332 , each of which is coupled to the b 12 bit line in each of the memory bit circuits 320 and 330 , respectively . furthermore , each of memory bit circuits 320 , 330 , etc . have an additional transistor 302 , which is coupled to the b 12 bit line in the respective memory bit circuits 320 and 330 . the latch 344 is also coupled to a clock output 346 . in accordance with embodiments of the present invention , on a read operation in the 1 - hot plus valid bit scheme , the v id bit is accessed at the same time as the 1 - hot vector and , if the v id bit is set , the 1 - hot vector is considered valid , otherwise , the 1 - hot vector is considered invalid by external processor logic ( not shown ). the v id bit is cleared on a blind invalidate just as for the 1 - hot tag array . the detailed operation of the 1 - hot plus v id bit is described below . it should be noted that the 1 - hot plus v id bit scheme is somewhat slower than the 1 - hot tag memory cell due to the added read port via w 13 being slower than w 10 and w 11 . operation of the 1 - hot plus valid bit . in fig3 , in accordance with an embodiment of the present invention , for a read operation in the 1 - hot tag plus valid bit memory cell , either w 10 or w 11 is asserted to read out the content of the bits in the array on b 10 or b 11 , respectively . similarly , the valid bit is read at the same time as the 1 - hot vector bits . a 1 - hot vector that does not have the valid bit set is considered an error , which causes the processor to vector into the error recovery firmware ( fw ) code . this fw code will flush the entire cache to correct the error . in accordance with an embodiment of the present invention , in fig3 , a write operation in the 1 - hot tag plus valid bit memory cell is performed in two phases in the same manner as described above for the write operation in the 1 - hot tag memory cell . in the first phase of a clock cycle ( each clock has a high phase and a low phase ), in each memory bit circuit 320 and 330 , one or both of the bit lines b 10 and b 11 are grounded to “ 0 ” and one or both of the word lines w 10 and w 11 are asserted , to write a “ 0 ” into each memory cell 320 and 330 . in the second phase , w 12 is asserted and the data indicated on the b 12 lines is a blind clear ( bc ) signal in an inverted form , which is the inverse of the data to be written to the 1 - hot array . that is , in the inverted form of the bc signal , in all of the memory bit circuits where a “ 1 ” is to be written the b 12 will have a value equal to “ 0 ” and in all of the memory bit circuits where a “ 0 ” is to be written the b 12 will have a value equal to “ 1 ”. in this way , the inverse of the 1 - hot vector is written into the memory cell , for example , if the 8 - bit 1 - hot vector value is “ 00010000 ” then the inverse 8 - bit bc signal , which will be written into the cell , is “ 11101111 ”. the bit values will be inverted when they are read out of the array , thus , producing the desired 1 - hot vector . in accordance with an embodiment of the present invention , in fig3 , a blind invalidate is performed in 2 clock cycles in the 1 - hot tag array . in the first clock cycle , the 1 - hot vector bit values can be indicated by the n b 12 bit lines and w 12 word lines of all rows are asserted . as a result , all rows that are indicated by the 1 - hot vector will be cleared , that is , invalidated . in addition , if any of the bits of a cleared cell in the rows contain a “ 1 ”, then the latch 344 can be set via w 13 . in the second clock cycle the enable bit line 348 can be asserted and the valid bit can be cleared as well . 2 - hot vector protection scheme . in accordance with an embodiment of the present invention , in the 2 - hot vector scheme , the 1 - hot vector is converted to a 2 hot vector . this is accomplished by local logic prior to the cache tag during the write operation of the 1 - hot vector into the tag . during the read out , the 2 - hot vector is automatically converted back to a 1 - hot vector by local logic subsequent to the cache tag . in this way , the accesses of the cache work identically to the 1 - hot tag cache described above . in accordance with an embodiment of the present invention , while the 2 - hot vector scheme is more complicated , it does not require the multi - cycle operation of the 1 - hot plus valid bit scheme . in addition , in accordance with an embodiment of the present invention , the 2 - hot scheme does not require additional bit lines or word lines . fig4 is a logic block diagram of a 2 - hot tag cache 419 based on the 1 - hot tag cache in fig1 , in accordance with an embodiment of the present invention . in fig4 , the 2 - hot tag cache 419 works in a similar way as the 1 - hot cache 119 in fig1 except that , in fig4 , the 1 - hot vector tag is converted to a 2 - hot vector and then stored in the 2 - hot tag array 420 . in fig4 , the numbering convention used in fig1 has been continued in fig4 for those elements that remain unchanged from fig1 . in fig4 , a convert to 2 - hot vector block 418 is coupled to the write data path of the 2 - hot tag array 420 and the convert to 2 - hot vector block 418 receives the incoming 1 - hot vector data and then converts the 1 - hot vector to the 2 - hot vector . the 2 - hot vector is then stored in the 2 - hot tag array 420 . an output of the 2 - hot tag array 420 is coupled to a convert to 1 - hot vector block 422 , which converts the 2 - hot vectors from the 2 - hot tag array 420 back to 1 - hot vectors , which are then input into the comparators 130 - 133 and the operation continues as described above for the 1 - hot tag cache of fig1 . fig5 is a circuit schematic diagram of a 2 - hot tag memory cell , illustrating the interaction between the memory bit circuits in the 2 - hot tag memory cell , in accordance with an embodiment of the present invention . in fig5 , the 1 - hot tag memory cell shown in fig2 , is illustrated with modifications that convert the 1 - hot tag memory cell to a 2 - hot tag memory cell , in accordance with an embodiment of the present invention . in fig5 , each memory bit circuit 510 , 520 and 530 in the 2 - hot tag memory cell is implemented with a primary clear bit line b 13 that is coupled to a primary clear circuit 519 , which is coupled to each memory bit circuit 510 , 520 and 530 to clear the bit in that memory bit circuit . in accordance with an embodiment of the present invention , an auxiliary clear circuit 517 is coupled to a primary clear circuit 519 in memory bit circuit 510 and clears the aux bit in the memory cell to the right of the memory cell that contains the primary bit . similar auxiliary clear and primary clear circuits are implemented in each of the memory bit circuits in the 2 - hot tag memory cell . operation of the 2 - hot tag cache . in fig5 , in accordance with an embodiment of the present invention , the read operation is the same as the read operation in the 1 - hot tag memory cell in fig2 , in which a 1 - hot vector is read out . specifically , for the read operation either w 10 or w 11 can be asserted to read out the content of the bits in the memory cell on b 10 or b 11 , respectively . when this occurs , the 2 - hot vector data stored in the 2 - hot tag array can be read out and converted back to a 1 - hot vector by the convert to 1 - hot vector block 422 of fig4 ( not shown in fig5 ). before the conversion from a 2 - hot to a 1 - hot vector , the 1 - hot vector coming from the 2 - hot cache tag can be considered an error and can cause the processor to vector to the fw code for proper error recovery . in accordance with an embodiment of the present invention , in fig5 , for a write operation in the 2 - hot tag memory cell , the write operation is performed in the same manner as described above for the 1 - hot tag memory cell in fig2 , except that the data is stored as a 2 - hot vector . in accordance with an embodiment of the present invention , in fig5 , a blind invalidate is performed by asserting the b 13 bit lines to cause each memory bit circuit to look at the memory bit circuit &# 39 ; s right neighbor blind clear signal ( bc ) and the memory bit circuit &# 39 ; s left and right neighboring memory bit circuits . specifically , the bits to be invalidated will be indicated by the b 13 lines in a 1 - bit format . the aux bit is cleared if and only if the aux bit &# 39 ; s primary b 13 bit line is asserted and its left neighbor bit is a “ 0 ”. the primary bit is cleared if the primary bit &# 39 ; s b 13 bit line is asserted and the left neighbor of the primary bit is a “ 0 ”. while the aux bit has been described located in the bit just to the right of the primary bit , in an alternate embodiment of the present invention , the aux bit can be located in any bit position within the 2 - hot vector . however , embodiments in which the aux bit is located closer to the primary bit , in general , perform better than those embodiments in which the aux bit is located farther away from the primary bit . fig6 is a circuit schematic diagram of a known alternative 1 - hot tag memory cell , which also illustrates how the 1 - hot tag cache operates with no interaction between the memory bit circuits in the alternative 1 - hot tag memory cell . in fig6 , the read operation is performed in the same manner as described above for the read operation in the 1 - hot tag memory cell in fig2 . specifically , in fig6 , for the read operation either w 10 or w 11 can be asserted to read out the content of the bits in the 1 - hot tag memory cell on b 10 or b 11 , respectively . in accordance with an embodiment of the present invention , in fig6 , to perform a write operation , in the 1 - hot tag memory cell , w 10 and w 11 can be selected . the data can be indicated on bit lines b 10 and b 11 . the data on the b 11 bit line can be the inverted version of the data on the b 10 bit line in each memory bit circuit . in this way , differential writes can be implemented . in accordance with an embodiment of the present invention , in fig6 , to perform a blind invalidate in the 1 - hot tag memory cell the b 12 line can be asserted , which causes each of the bit circuits to be discharged and a “ 0 ” to be written into each of the bit circuits . fig7 is a circuit schematic diagram of an alternative 2 - hot tag memory cell , implemented from the 1 - hot tag array cell in fig6 , illustrating the interaction between the memory bit circuits in the 1 - hot tag memory cell , in accordance with an embodiment of the present invention . in fig7 , the interaction between the primary bit and the left and right neighbor bits of the primary bit are illustrated . in fig7 , in accordance with an embodiment of the present invention , the read operation is performed in the same manner as described above for the read operation in the 1 - hot tag memory cell in fig6 . specifically , for the read operation either w 10 or w 11 can be asserted to read out the content of the bits in the 2 - hot tag memory cell on b 10 or b 11 , respectively . in accordance with an embodiment of the present invention , in fig7 , for a write operation in the 2 - hot tag memory cell , the write operation can be performed in the same manner as described above for the 1 - hot tag memory cell in fig6 , except that the data to be stored is a 2 - hot vector . in accordance with an embodiment of the present invention , in fig7 , a blind invalidate can be performed by asserting the b 12 bit lines to cause each bit to look at the bit &# 39 ; s right neighbor blind clear signal ( bc ) and the bit &# 39 ; s left and right neighboring bits . specifically , the bits to be invalidated can be indicated by the b 12 lines in a 1 - bit format . the aux bit can be cleared if and only if the aux bit &# 39 ; s primary b 12 bit line is asserted and its left neighbor bit is a “ 0 ”. the primary bit can be cleared if the primary bit &# 39 ; s b 12 bit line is asserted and the left neighbor of the primary bit is a “ 0 ”. in the blind invalidate the data can be a 1 - hot vector and the aux and primary bits can be invalidated in the same cycle . while the embodiments described above relate to the 1 - hot plus valid bit and 2 - hot vector embodiments , they are not intended to limit the scope or coverage of the present invention . in fact , for example , the 2 - hot scheme described above can be extended to a 3 - hot vector to protect errors in 2 consecutive bits or to a 4 - hot or higher vector to protect errors in 3 and higher consecutive bits , respectively . similarly , other bit patterns other than the 2 - hot scheme may be used depending on the type of the errors , such as , for example , double bit errors , that a designer is trying to protect against . in addition , the 1 - hot plus valid bit scheme is , generally , good for microprocessor designs that are not wire congested in the physical layout and , thus , have available area for the additional read line . likewise , the 2 - hot scheme is good for microprocessor designs that are , generally , wire congested in the physical layout and , thus , do not have much available area for the additional hardware that is associated with the 1 - hot plus valid bit scheme . the 2 - hot scheme described above minimizes global routing at the expense of local interconnect and transistors . other 2 - hot schemes can use a multiple clock blind invalidation scheme by using a different signal for invalidating the aux bit . both the 1 - hot plus valid bit and 2 - hot vector protection schemes can be implemented in high performance microprocessors and high performance multi - processors on a single chip . it should , of course , be understood that while the present invention has been described mainly in terms of microprocessor - and multi - processor - based personal computer systems , those skilled in the art will recognize that the principles of the invention may be used advantageously with alternative embodiments involving other integrated processor chips and computer systems . accordingly , all such implementations which fall within the spirit and the broad scope of the appended claims will be embraced by the principles of the present invention .