referring now to fig1 a data processing system 10 in which the present invention is embodied will be described . data processing system 10 includes a storage controller 12 , a plurality of host processors 14 , 16 , 18 and 20 and a plurality of direct access storage devices ( dasd &# 39 ; s ) 22 , 24 , 26 , 28 , 30 and 32 . dasds are generally magnetic storage units such as disk drives . in this embodiment , the dasds 22 - 32 are connected to the storage controller 12 for selective connection to any or all of the host processors 14 - 20 . the storage controller 12 is preferably an ibm 3990 model 3 or an enhanced version of the same . the enhanced version and its associated features will be discussed below . host processors 14 - 20 are typically main frame systems such as the ibm 3090 , the es9000 model computer , or comparable systems . the host processors 14 - 20 are connected to storage controller 12 through either 4 , 8 , 12 , or 16 system adapters ( sas ). there are two types of sas : parallel and escon . parallel sas provide attachment to channels via a parallel i / o interface . escon sas provide channel attachment via the escon i / o interface . various sa configurations can be used with a minimum of four and a maximum of sixteen sa &# 39 ; s connected to the storage controller 12 . each parallel sa attaches to one host channel while an escon sa can attach to multiple host channels . each sa , in turn , contains a number of channels which results in the ability to provide up to 128 channels in communication with the storage controller 12 when using escon sas . while it is necessary to understand , generally , that channels connect to the storage controller 12 , a discussion of the various channel configurations is beyond the scope of this specification . fig2 illustrates , through a block diagram , the general architecture of the storage controller 12 embodying this invention . it can be seen that each cluster is configured with two storage paths ( sps ) 60 , 62 , 64 and 66 . each storage path contains a microcontroller capable of interpreting channel commands from the host and controlling the attached dasds . further , each cage contains shared control array ( sca ) storage 42 and 44 . the sca stores local status information as well as status information shared with the sca located in the other cage within the storage controller 12 . typical shared data includes device status and reconnection data as well as a variety of external registers used by the microcontrollers contained in each of the storage paths 60 , 62 , 64 , and 66 . sca data is accessible to all four storage paths 60 , 62 , 64 , and 66 . this access is 14 over fault independent paths so that in the case of a power failure in , for example , cage 1 , storage path 0 ( located in cluster 0 ) would continue to have access to the sca of cage 0 . fig3 shows the one of the four storage paths 60 in the storage controller 12 in a block diagram schematic . all four storage paths being identical , only one will be described herein . storage path 60 is connected to 8 × 2 switch 115 by an upper port 110 and to a plurality of dasds by a lower port 112 . data transfer between the 8 × 2 switch 115 and one of the dasds during direct dasd operations occurs via an automatic data transfer circuit ( adt ) 174 supported by a rate change buffer 176 , if required . rate change buffer 176 compensates for differences between the speed of data transference by dasd and that of channel to host communications . channel transfers typically occur at a much higher rate than dasd to controller transfers . the storage path 60 also contains a microcontroller 170 which functions to control all operations taking place on the storage path 60 . the microcontroller 170 executes microinstructions which are loaded into a control store ( cs ) 182 through an external / support facility . the microcontroller 170 used in the preferred embodiment , in addition to having internal registers , is capable of addressing up to 256 external registers located on the storage path card . there is also provision for addressing locations external to the storage path 60 such as both cache elements and both nvss using an indirect register interface . a port adapter ( pa ) 172 provides control and data paths for the transfer of data between cache 70 and 72 , nonvolatile storage 74 and 76 , microcontroller 170 and upper and lower ports . it also allows for the microcontroller 170 to perform indirect addressing to cache and nvs , using the ira and ird registers . the adt 174 transfers data among the sa , the upper port , the lower port and the device connection . all transfers through the adt can take place at up to 18 mb per second . automatic data transfer through the adt 174 is set up and initiated by microcode located within the control store 182 . after initiation , no further microcode intervention is required until after the transfer is complete . caches 70 and 72 each contain two ports ( upper and lower ) to allow for two simultaneous data transfers to and / or from each cache element . by way of example , data may be transferred from cache and channel while also transferring data to cache from dasd . data transfer is typically set up by microcontroller 170 and then taken over by the automatic data transfer 174 function without microcontroller intervention until transfer termination . a typical track format for data recordation on dasd is now described with reference to fig4 . the most widely used arrangement is referred to as count - key - data format ( ckd ). ckd is used with the ibm 3990 model 3 storage controller and the various dasd devices that it supports . the primary advantage of ckd is the flexibility it provides in allowing records to be of variable length . the ckd format , although well known in the art , will now be described briefly . the basic ckd record format includes a count field , an optional and variable length key field and a variable length data field . the count field is fixed in length and specifies the record identification and the respective lengths of the key and data fields . the optional key field , if used , is of variable length and may be used to rapidly identify particular records which have been stored under a classification scheme based upon the key fields . on each track there is an index which defines the physical radial location of the track on the disk . following the index is a home address ( ha ) which contains information about the condition of the track , including the location and length of any defects on the track . following ha is a track descriptor record ( ro ) which can be used to point to an alternate track , if the primary track is defective . following the ro record are the data records r1 to rn , which are in conventional ckd format as described above . physical gaps within and between the data records , represented as &# 34 ; g &# 34 ; in fig4 separate the recorded areas on the track . the length of the gaps varies with the particular track format and the location of the gap . the gaps are required between the fields to perform various hardware functions , including the encoding and decoding of data and the padding of variable length fields . fig5 illustrates the format of the track records that are used in the first preferred embodiment of this invention . it should be noted that this record includes field status data denoted fs . although fig5 represents the data format as stored on dasd , the field status data also travels with the data fields throughout the storage controller 12 . the field status data , wherever located , indicates the validity of the attached data field . the primary purpose of field status is to increase data integrity during data transfers including data transfers within the storage controller 12 . the table in fig6 describes bit assignments for the field status area . as required by the first preferred embodiment of the instant invention , field status is a two byte object that travels with various data fields through the data fields and indicates the validity of the attached data field . the adt 174 appends field status to fields coming from the sa and strips field status from data fields going to the sa . this is because the sas ( both parallel and escon ) do not maintain or support field status . the first preferred embodiment provides a method for the storage controller 12 to maintain data sufficient to notify the host of any data integrity problems as a result of channel errors during data transfers . this is accomplished in four broad steps . the storage controller 12 must first identify the exception condition occurring during the data transfer . it must then mark the data as bad . later , when the data is accessed , the indication of damaged data must be detected . finally , the host must be signalled that the data was damaged when it was written but that the subsystem is operating correctly and is not in need of repair . each of these steps will now be discussed in detail . the storage controller 12 will detect two types of error conditions . the first type comprises a halt i / o , selective reset or system reset . these are specific sequences on a parallel channel or frames for an escon channel and are well known in the art . should one of these three events occur and cause truncation of a data transfer from the channel to the storage controller 12 , the sa will raise a signal or a discrete wire to the adt 174 . the adt 174 will set bit 12 in a field status register within the adt 174 . at the end of the data transfer the adt 174 places field status in the data stream either to the rate change buffer 176 or a cache 70 or 72 . the second type of fault detected is a general fault in data transfer . faults in data transfer set bits in check registers . the output of these bits are then combined into summary bits in other check registers . the output of these bits are eventually combined in a check - 2 bit within the adt 174 . when check - 2 is set the adt 174 will cause bit 9 of field status to be set . once an exception condition has occurred , the next step is to mark the data as bad . the method by which this is done in the instant invention is to tag any damaged field in the field status area with an indication of bad data . the field status area is a two byte field with the first byte ( bits 0 - 7 ) of this field used to flag exceptions detected by the dasd 22 - 32 and the second byte ( bits 8 - 15 ) used to flag exceptions detected by the storage controller 12 . the instant invention is limited to the second byte and uses three bits of the second byte to flag errors detected during channel transfers . referring again to fig6 it is seen that bit 9 is set when a channel error due to a halt i / o ccw , selective reset ccw or system reset ccw occurs . this typically causes truncation of the data with zero padding written over the damaged fields . this bit is set by the storage controller hardware . the second bit used is bit 12 which is used to indicate a sa problem or an adt check - 2 situation . as a result a check condition has occurred within the subsystem and there has been some degree of data corruption . this bit is also set by storage controller hardware . bit 8 is used to indicate that the field could not be read without error from the primary of a duplex pair during a dual copy operation under error . this bit is set by the storage controller hardware . field status , in addition to being kept within the storage controller 12 , is sent to the dasd in the track format described above only if the particular dasd device supports the track format including field status . this is illustrated in fig7 . the dasd units receive field status , update it if necessary , and store it on the disk . when the field is subsequently read , the field status is transferred back to the storage controller 12 . when data records are received from the channel and through the sas , the adt 174 first appends all zeros as field status data to the associated data field . if the sa has indicated a halt i / o , selective reset or system reset condition , the adt sets bit 9 of field status . bit 12 of field status is set in the sa has detected a check - 2 condition . bad field status is field status that indicates that an error occurred during the write operation of that field . any operation that either uses a count field with bad field status , transfers a field with bad field status to a channel or uses a field with bad field status in a search operation ( either for a search command , or a locate record ) will be terminated and cause a check condition to occur . because the controller 12 can not always tell when the key field ends and the data field begins , it always stores the key and data fields as one field in the adt buffer during write operations . this means that there will be a single field status for the key and data fields while in the adt buffer . the errors recorded in this field status are tagged to the data field . therefore , should an error occur while writing the key field , it is possible that the error will be flagged in field status against the data field and not against the key field . this condition may allow some search key chains to operate as a bad key field without being notified , however , a key field can never be read without also reading the associated data field and the error will be detected when the data field is later read . the indication of damaged data within the data storage subsystem is detected by the hardware in two places . the first detection point is on the director - device connection ( ddc ) when the data is read from dasd . the ddc is a microcode controlled interface that provides the means for attaching dasd to the storage controller 12 . command and status transfer between the storage paths 60 - 66 and the dasd is controlled by microcontroller 170 . data transfer is controlled by the hardware after being set up by the microcode for an automatic data transfer through the adt 174 . the indication on the ddc interface is a status bit . this bit must be a status bit rather than a check bit . if a check bit were used , it would have to be processed every time that it was set . this would cause timing critical code to examine and reset the bit for key and data fields . the extra overhead introduced in this instance would be unacceptable . a status bit , on the other hand , permits checking the bit or ignoring it as conditions dictate . a second indication of damaged data occurs on the channel interface when data is transferred to the channel or used to satisfy a channel search . this causes a check condition to be recognized because the channel has accessed damaged data . finally , the controller 12 must have some way of signalling the host processor that data that is sent to the host processor is invalid . this is accomplished by using a special exception class which is sent from the controller 12 to the host . the exception is reported as a data check since the data is bad and there is no storage subsystem malfunction . the host is also notified that the problem is not due to media but is instead a problem that occurred while the data was being written and was not recovered . as discussed above , the first preferred embodiment of the instant invention requires a hardware modification due to the reformatting of tracks on the dasd . a second preferred embodiment of the instant invention which does not require this hardware modification or reformatting of data tracks is now described . it should first be noted that the second preferred embodiment of this invention requires no hardware modification because the solution to the above described problem is addressed only through microcode changes located within the storage controller 12 . this preferred embodiment does not require marking of data as invalid but instead uses the asynchronous capability of existing dasd storage controllers to maintain data integrity such that no invalid data records are ever stored within the storage controller 12 or the dasd devices 22 - 32 . the operation of the storage controller 12 in an asynchronous fashion , which is required under this embodiment , will now be described . the asynchronous operation enables the channel and the device to transfer data independently of each other . this is accomplished by inserting a buffer in the data path between the device and the channel with separate data paths for the channel and the device , each under the control of separate processors . in this manner , the device processor can access records in one portion of the buffer while another portion of the buffer is being used by the channel processor . channel programs can be executed such that the channel and storage control activities required to end execution of one command and advance to the next do not have to occur during the inter - record gap between two adjacent fields . this procedure has the further and more important advantage of allowing data records that are corrupted because of a channel error to be discarded instead of written over previously valid data . this can not be accomplished in a synchronous environment . in a synchronous environment , the channel and device must perform data transfer in lock - step . as write data is being transferred from the channel to the control unit , the data is simultaneously transferred to dasd . as a result , if a channel error occurs while performing a write operation , the previous version of the record on disk is concurrently being overlaid with the invalid data from the channel . with an asynchronous environment , the previous valid version of the record can be preserved until the channel data transfer has been completed successfully . operations , thus , do not need to be performed in lock - step . write data can be transferred from the channel to the storage controller 12 first , and then transferred from the controller 12 to the dasd only when the first step has completed without a channel error or some other fault as described above . the processing under the second preferred embodiment will now be described . all processing described herein refers to storage control processing in a cached environment , the typical configuration of the storage controller 12 of the preferred embodiments . in a caching environment , two situations must be addressed . the first is a normal write and the second is a dasd fast write . both write operations will be described now as a preliminary matter , before the discussion of the treatment of each operation within the storage controller 12 . it is important to note that the following discussion of write operations are described with reference to synchronous processing . the method of the invention modifies the write operations to remedy the above described data integrity problem . a normal write is the basic cache writing operation in the storage controller 12 . if a copy of the requested data is in the cache storage when the channel initiates a write request , a &# 34 ; write hit &# 34 ; occurs . the controller 12 then writes the data directly from the channel to dasd , and , at the same time , updates the data in cache storage . this approach . assures that the data in the cache storage is current when it is accessed again for 8 read operation . data is simultaneously written to the cache storage and to dasd with a device end signal returned at completion . it is important to note that a device end can not be returned until data is written successfully to dasd . the second cache operation of importance to the invention herein is a &# 34 ; dasd fast write &# 34 ;. as with any cached write operation , dasd fast write requires an nvs backup , associated with the cache memory to prevent data loss in the event of a power failure . dasd fast write allows for faster write operation processing in that access to the dasd device is not necessary if the data is present in cache . if it so happens that the data to be written is present in the cache , instead of writing the data update to dasd , the storage director copies the data received from the channel into cache and nvs . once this is done , the storage director can return channel end and device end status . in this manner host processing can continue without waiting for the data to be placed on dasd . the data is not actually written to dasd until it is necessary to free space in the cache or nvs . if the data is not present in the cache , then a &# 34 ; write miss &# 34 ; occurs and the data is written to dasd and to cache simultaneously and immediately . in addition , the remainder of the track containing the record to be written is staged to cache for future anticipated use . now , turning to fig8 it will be described how a storage controller operating under this invention will treat data under a normal write situation so that invalid data is prevented from being stored within the storage subsystem . the typical subsystem action which occurs during one of the above mentioned exceptions is to record a good block of data , replacing damaged or missing data with zeros ( padding ) and including the usual error checking codes ( ecc ) to validate the zeros as good data stored . the invention herein recognizes the undesirability of current subsystem processing and provides a method to solve the resulting data integrity problem with only a microcode change . as can be seen in block 710 asynchronous mode is first established . asynchronous mode is established by the controller 12 when it receives the first ccw from the channel program asynchronous mode is always established with escon and is established in a parallel adapter environment with eckd . once asynchronous mode has been established the sector lead is increased as shown in block 720 . this allows the record being transferred to be entirely captured in the adt 174 before being written to dasd 22 - 32 or discarded , as the case may be . the channel then transfers the selected records into the storage controller adt buffer 730 . records which have been padded with zeros as a result of a channel or host errors are detected as invalid at this point . if data is determined at block 740 to be invalid then the data is discarded at block 760 . otherwise , data is transferred from the adt to the selected dasd device 750 only after successful completion of the channel to adt transfer . the processing ends at block 770 . fig9 illustrates storage controller processing in the dasd fast write mode according to the second preferred embodiment of this invention . processing is initiated for a write operation at block 810 . as with normal writes , the controller 12 is placed in asynchronous mode at block 820 . it is then determined whether or not the record to be written is contained on a track currently residing in cache at block 840 . if not , processing as treated in the same manner as if a normal write operation was taking place . this procedure includes blocks 830 , 840 , 850 , 850 and 870 . a description of the same series of process steps can be found above with respect to normal write operations and will , therefore , not be repeated here . if the track containing the record to be written is in cache , it will be determined , at block 880 , if a format write or update write is taking place . a format write command establishes count areas of the track and formats the key and data areas of the track or tracks . in a format write with dasd fast write , the new record is written , and the rest of the track is formatted for new data . there is no need to verify the data on the track before allowing the cache write . an update write , on the other hand , changes the key and data areas of existing records without affecting other areas of the record or other records on the same track . update writes are the most common form of write operations taking place in the storage controller 12 . if the write operation is a format write , then old nvs blocks corresponding to the track containing the record to be written are deallocated 890 and new nvs blocks are allocated 895 . the padded records are detected as channel data arrives into cache and nvs . the format write is converted into an erase . the erase command is a format write that erase the track starting with the record referenced . for example , a format write of record 3 would write record 3 and erase the rest of the track . erase record 3 would erase record 3 and the rest of the track . therefore , if a channel exception occurs during a format write , the record is erased and so is the rest of the track . if the write operation is an update write , it must first be determined , at block 835 , whether it is a first update write or a subsequent update write . in the case of a first update write the track containing the record to be written will be in cache but no nvs block will have been allocated for this record . processing for a first update write is as follows : padded / invalid records are detected as channel data arrives into cache and nvs . the nvs block for this record is discarded 855 , the cache track slot is invalidated 856 and all remaining records for the track are destaged 857 from nvs to dasd . while the destage occurs and until it is completed , the track is in &# 34 ; pinned nvs only &# 34 ; state . finally , all nvs space for this track is deallocated 858 . in the case of an update write that is a subsequent update to a record , the track will be in cache and an nvs block will already be allocated for this record . at this point it must be determined 871 if the same fields as in a previous update write are to be updated or if it is a new field to be updated . if an update is to occur on a field previously updated then new nvs space is allocated and the previous nvs block is deallocated after a successful write operation . again , padded / invalid records are detected as channel data arrives into the cache and newly allocated nvs storage . the new nvs block for this record is then discarded 881 and the cache track slot is invalidated 882 . next , the earlier version of the record to be written and all other records residing on its track are destaged 883 from nvs to dasd . the track is in &# 34 ; pinned nvs only &# 34 ; state until the destage completes successfully . finally , all nvs space for the track is deallocated 884 . if the subsequent update write is directed to different fields from those updated previously , then the track is destaged 892 from cache to dasd and all nvs space for the track is deallocated 893 . next , the nvs block for this record is discarded 855 , the cache track slot is invalidated 856 and all remaining records for the track are destaged 857 from nvs to dasd . while the destage occurs and until it is completed , the track is in &# 34 ; pinned nvs only &# 34 ; state . finally , all nvs space for this track is deallocated 858 . if a redundancy check occurs in the nvs during emergency nvs destage at power up , the nvs block is discarded . if two nvs blocks exist for the same record , both blocks are destaged to dasd in order upon power up . if a storage controller power loss occurs before a padded nvs block is deallocated , then the padded nvs block is destaged to dasd upon power up . while the invention has been particularly shown and described with reference to the preferred embodiments thereof , it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention .