the detailed description sets forth specific embodiments that are described in sufficient detail to enable those skilled in the art to practice the present invention . it should be apparent to those skilled in the art that other embodiments may be utilized , and that logical , mechanical , and electrical changes may be made , while remaining within the scope of the present invention . the following detailed description is , therefore , not to be taken in a limiting sense , and the scope of the invention is defined only by the appended claims . fig1 is a simplified diagram of a temperature measurement module 4 according to one embodiment . the temperature measurement module 4 includes a cmos temperature sensor 42 , a sigma - delta converter 44 , a counter 46 , and a controller 48 , among others . the temperature measurement module 4 converts an analog temperature reading ( i . e ., from the temperature sensor 42 ) into a digital output . in the current embodiment , the temperature sensor 42 includes a vertical bipolar transistor . it should be apparent to one skilled in the art , however , that other types of devices might be used ( for example , a cmos transistor operating in weak inversion , a lateral bipolar transistor , schottky diodes , etc .) while remaining within the scope of the present invention . temperature sensor 42 produces a current proportional to absolute temperature ( i ptat ), a current complementary to absolute temperature ( i ctat ), and a voltage complementary to absolute temperature ( v ctat ), each of which are provided to converter 44 . fig1 a and 1b are simplified diagrams of circuits for producing i ptat and i ctat , respectively , according to one embodiment . referring briefly to fig1 a , current generator 60 includes an op amp 62 , pmos transistors 64 a , 64 b , 64 c , resistor 66 , and diodes 68 a , 68 b . in the current embodiment , diodes 68 a , 68 b are vertical p - n - p diodes . the non - inverting input of op - amp 62 is connected to a node located between pmos transistor 64 b and resistor 66 such that the voltage produced across resistor 66 is applied to the non - inverting input . the inverting input of op - amp 62 is connected to a node between pmos transistor 64 a and diode 68 a such that the voltage ( v diode ) produced across diode 68 a is applied to the inverting input . the output of op amp 62 is applied to the gates of pmos transistors 64 a , 64 b , 64 c . in the current embodiment , pmos transistors 64 a , 64 b , 64 c act as current sources . the output of pmos transistor 64 c is i ptat . for clarity , the transistors 64 a , 64 b , 64 c illustrated in fig1 a are single pmos transistors , however , it should be apparent to one skilled in the art that other types of transistors may be used while remaining within the scope of the present invention . for example , cascaded pmos transistors may be used for pmos transistors 64 a , 64 b , 64 c while remaining within the scope of the present invention . referring briefly to fig1 b , current generator 70 includes an op amp 72 , pmos transistors 74 a , 74 b , and resistor 76 . the non - inverting input of op - amp 62 is connected to a node located between pmos transistor 74 a and resistor 76 such that the voltage produced across resistor 76 is applied to the non - inverting input . the inverting input of op - amp 62 is connected to the voltage ( v diode ) that is produced as discussed above . the output of op amp 72 is applied to the gates of pmos transistors 74 a , 74 b . in the current embodiment , pmos transistors 74 a , 74 b act as current sources . the output of pmos transistor 64 b is i ctat . for clarity , the transistors 74 a , 74 b illustrated in fig1 a are single pmos transistors , however , it should be apparent to one skilled in the art that other types of transistors may be used while remaining within the scope of the present invention . for example , cascaded pmos transistors may be used for pmos transistors 74 a , 74 b for better power supply rejection and other performance parameters while remaining within the scope of the present invention . returning to fig1 , converter 44 uses i ptat , i ctat , and v ctat , to produce a bitstream that is provided to counter 46 . counter 46 uses the bitstream output to produce a digital output representing the temperature reading . controller 48 regulates the temperature sensor 42 , converter 44 , and counter 46 in the current embodiment . for example , controller 48 issues “ clock ” and “ enable ” signals ( among others ) to the temperature sensor 42 , converter 44 , and counter 46 . the temperature measurement module 4 illustrated in fig1 employs a single temperature sensor . in an alternative embodiment , the temperature measurement module 4 may employ a plurality of temperature sensors while remaining within the scope of the present invention . fig2 illustrates a temperature measurement module 4 having a plurality of temperature sensors 42 according to one embodiment . as seen in fig2 , each temperature sensor 42 is connected to a multiplexer 43 . in the current embodiment , controller 48 issues a “ select ” command to the multiplexer 43 such that multiplexer 43 passes the output from the selected temperature sensor 42 to the converter 44 . once the particular temperature sensor 42 is selected , the temperature measurement module 4 shown in fig2 functions the same way as the temperature measurement module 4 shown in fig1 . it should be noted that the criteria used to select a particular temperature sensor 42 may vary according to certain design choices . for example , depending upon their locations within an integrated circuit , a first temperature sensor 42 may be selected twice as often as a second temperature sensor 42 . fig3 is a simplified diagram of a portion of the temperature measurement module 4 of fig1 and / or fig2 according to one embodiment . more specifically , fig3 illustrates a more detailed view of the sigma - delta converter 44 in combination with the counter 46 . the converter 44 includes a capacitor 56 , a clocked comparator 52 , and a transistor 54 . the capacitor 56 acts as a signal integrator . it should be apparent to one skilled in the art that other types of integrators may be used while remaining within the scope of the present invention . additionally , as previously discussed , a “ clocked comparator ” refers to a comparator that compares two inputs and asserts the output signal once every clock cycle ( e . g ., a comparator whose output changes only once per clock cycle ). in operation , i ptat from temperature sensor 42 ( as shown in fig1 ) or from the selected temperature sensor 42 ( as shown in fig2 ) causes a voltage (“ sigma ”) to develop across capacitor 56 at node a . this voltage , which may also be referred to as v cap , is provided to the non - inverting input of comparator 52 . when v cap exceeds v ctat , the comparator output ( i . e ., the bitstream ) goes high causing transistor 54 to conduct . when activated , transistor 54 sinks i ctat ( i . e ., “ delta ”), thus discharging capacitor 56 and causing v cap to decrease . when v cap falls below v ctat , the comparator output goes low , thus de - activating transistor 54 . as seen in fig3 , the comparator output is also connected to an input of counter 46 . counter 46 counts the number of “ 1 ” decisions made by the comparator 52 and produces a digital output representing the temperature as sensed by the temperature sensor 42 ( i . e ., counter 46 counts the number of times the comparator output goes high within a predetermined time period , such as 100 clock cycles ). fig4 a is a simplified diagram illustrating the relationship between i ptat and temperature for the temperature measurement module 4 according to one embodiment . as seen in fig4 a , i ptat is directly proportional to temperature ( i . e ., as temperature increases , i ptat increases ). fig4 b and 4c are simplified diagrams illustrating the relationship between i ctat and temperature and between v ctat and temperature , respectively , for the temperature measurement module 4 according to one embodiment . as seen in fig4 b and 4c , i ctat and v ctat are inversely proportional to temperature ( i . e ., as temperature increases , i ctat and v ctat each decrease ). the use of i ctat ( i . e ., as the delta current source ) in combination with a reference voltage enables increased resolution for the temperature measurement module 4 . additionally , using a capacitor as an integrator instead of an op - amp based integrator removes complexities associated with designing low voltage op - amps . in the current embodiment , for example , using i ctat ( i . e ., as the delta current source ) and v ctat ( i . e ., as the reference in the comparator ) in contrast to i ref and v ref , respectively , increases the effective resolution of the temperature measurement module 4 without using precision analog components as required by the prior art . with increasing temperature , i ptat increases while i ctat decreases . this improves the resolution of the temperature sensor 42 . for example , when the comparator 52 is sampled 100 times , the counter range goes from about 15 when using i ref and v ref ( as discussed above in conjunction with the prior art temperature measurement system ) to approximately 55 when using i ctat and v ctat ( e . g ., for a temperature range between approximately − 40 ° c . and 110 ° c .). it should be noted that another reference voltage may be used as the reference for the comparator while remaining within the scope of the present invention . it should further be noted that the reference voltage need not have the same properties as v ctat ( e . g ., as temperature increases , the reference voltage need not decrease ) to remain within the scope of the present invention . additionally , the use of i ctat and v ctat ensures adequate operation at lower voltages ( e . g ., 1 . 2 v and below ) and eliminates the precision band - gap type tuning required to generate a fixed v ref by the prior art circuits . fig5 is a simplified block diagram of a memory system 1 according to one embodiment . the memory system 1 includes a memory controller 2 , two ( 2 ) dual - inline - memory - modules 3 ( i . e ., dimm - 0 , dimm - 1 ), and one or more temperature measurement modules 4 ( as illustrated in fig1 and / or fig2 ). each memory module 3 is divided into two ( 2 ) ranks ( rank - 0 , rank - 1 ), each rank being comprised of nine ( 9 ) synchronous dynamic random access memory ( sdram ) devices 10 . the memory system 1 may be utilized as a component within a larger system , for example , within a computer system having a processor , a storage device , a display , etc . the memory controller 2 and memory modules 3 communicate via a system bus 5 . in the current embodiment , the system bus 5 carries command signals , address signals , and data signals , among others . the system bus 5 may be sub - divided into two or more buses , for example a command bus , an address bus , and a data bus . the command bus may carry the row address strobe ( ras #), column address strobe ( cas #), and write enable ( we #) command signals , among others . the address bus may carry bank address ( ba 0 , ba 1 ) and address input ( a 0 - a 12 ) signals , among others . the data bus may carry data input / output signals ( dq 0 - dq 15 ), data strobe signals ( ldqs , ldqs #, udqs , udqs #), and data mask signals ( ldm , udm ), among others . additionally , rank specific command signals , such as the chip select ( cs #), clock enable ( cke ), and on - die termination ( odt ) signals may be carried by another portion of the system bus 5 . it should be apparent to one skilled in the art that the topology of the system bus 5 ( and its component parts ) may be varied while remaining within the scope of the present invention . the temperature measurement modules 4 may be distributed throughout the memory system 1 . for example as shown in fig5 , temperature memory modules 4 are shown located within the memory controller 2 , within each rank of each memory module 3 , and within the unused die space of the memory system 1 . temperature memory modules 4 may also be incorporated into one or more of the sdrams 10 ( not shown in fig5 ). accordingly , the temperature memory modules 4 may be employed to protect the memory system 1 and / or its components against overcurrent damage , to compensate for cross sensitivity of other sensors , to reduce errors caused by self - heating , and to provide process data input , among others . for example , the output of one or more of the temperature measurement modules 4 may be used by the memory controller 2 and / or a microprocessor ( not shown ) to regulate power supplied to the memory device 1 and to prevent overheating , among others . it should be apparent to one skilled in the art the number of temperature measurement modules 4 employed and / or their location ( s ) within the memory system 1 may be varied while remaining within the scope of the present invention . additionally , it should be apparent to one skilled in the art that a single temperature measurement module 4 having a plurality of temperature sensors ( for example , as best illustrated in fig2 ) may be employed while remaining within the scope of the present invention . it should further be apparent to one skilled in the art that the use of the temperature measurement module 4 within a memory device is for exemplary purposes only and is not intended , in any manner , to limit the scope of the present invention . the temperature measurement module 4 may be used with other types of devices may be used while remaining within the scope of the present invention . fig6 illustrates a simplified functional block diagram of an architecture for an sdram 10 of fig5 according to one embodiment . the sdram 10 may include a temperature measurement module 4 for measuring the temperature within the sdram 10 . the sdram 10 includes control logic 11 responsive to a plurality of command signals ( e . g ., cs #, ras #, cas #, we #, cke , ck , ck #, adr , ba , etc .) from a command bus 12 . the control logic 11 includes a command decode circuit 13 and mode register circuits 14 , among others . table 1 illustrates a truth table for the command coding of the sdram 10 according to the one embodiment . referring to table 1 for example , when the memory controller 2 sets cs #= l , ras #= h , cas #= l and we #= l , the command decode circuit 13 decodes the signals as a write command function . it should be apparent to those skilled in the art that different and / or additional signals ( e . g ., ba , adr , etc .) may be used to encode each command function . it should further be apparent to one skilled in the art that the specific state of each command signal ( i . e ., cs #, ras #, etc .) used to define each command function ( i . e ., write , read , etc .) may be altered while remaining within the scope of the present invention . the sdram 10 also includes an address register 15 responsive to an address bus 16 that carries a plurality of address signals ( e . g ., a 0 - a 12 , ba 0 , ba 1 , etc .). the control 9 logic 11 and the address register 15 communicate with each other , and with a row address multiplexer circuit 17 , a bank control logic circuit 18 , and a column address counter / latch circuit 19 , via an internal bus 20 . the bank control logic 18 is responsive to the control logic 11 , the address register 15 , and a refresh counter 38 . the row address multiplexer 17 is also responsive to the control logic 11 , the address register 15 , and the refresh counter 38 . a series of row latch / decoders 21 are responsive to the bank control logic 18 and the row address multiplexer 17 . one row latch / decoder 21 is provided for each memory array 22 . each memory array 22 is comprised of a plurality of memory cells each operable to store one bit of information . four memory arrays 22 , labeled bank 0 through bank 3 , are illustrated in fig6 . accordingly , there are four row latch / decoder circuits 21 , one each for controlling bank 0 through bank 3 . the column address counter / latch circuit 19 is responsive to the control logic 11 and the address register 15 . a series of column decoders 23 are responsive to the bank control logic 18 and the column address counter / latch 19 . one column decoder 23 is provided for each memory array 22 . as discussed above , sdram 10 includes four memory arrays 22 labeled bank 0 through bank 3 . accordingly , there are four column decoder circuits 23 , one each for controlling bank 0 through bank 3 . an i / o gating circuit 24 is responsive to the column decoder circuits 23 for controlling sense amplifiers 40 within each of the memory arrays 22 . the sdram 10 may be accessed through a plurality of data pads 25 for either a write operation or a read operation . for a write operation , data on data pads 25 is received by receivers 26 and passed to input registers 27 . a write buffer / driver circuit 28 buffers the received data which is then input to the memory arrays 22 through the i / o gating circuit 24 . data that is to be read from the memory arrays 22 is output through the i / o gating circuit 24 to a read latch 29 . from the read latch 29 , the information is input to a multiplexer circuit 30 , which outputs the data onto the data pads 25 through drivers 31 . the drivers 31 are responsive to a data strobe generator 32 and to a delay locked loop circuit 33 . the data strobe generator 32 is operable to produce data strobes for upper and lower bytes ( i . e ., udqs , udqs #, ldqs , and ldqs #) as is known in the art . the data strobes are also provided to data strobe output pads 34 , input registers 27 , and to the write buffer / driver 28 , among others . the sdram 10 also includes input data mask pads 35 for receiving upper data mask signals ( udm ) and lower data mask signals ( ldm ) for the upper bytes ( dq 8 - dq 15 ) and lower bytes ( dq 0 - dq 7 ), respectively . the data pads 25 , data strobe output pads 34 , and data mask pads 35 may be part of a data bus 37 . the sdram 10 includes an on - die termination ( odt ) circuit 36 that is operable to apply an effective resistance rtt ( e . g ., ri or r 2 ) to the data pads 25 , data strobe output pads 34 , and input data mask pads 35 ( or to another portion of the data bus ). an odt activation circuit 39 is used to control whether the odt circuit 36 is enabled / disabled , and thus whether rtt is applied . in the embodiment illustrated in fig6 , the odt activation circuit 39 receives the we # and cs # signals which are sent by the system controller 2 to the dimms 3 and to each sdram 10 . these signals may be rank specific ( e . g ., weo # and cs # 0 for rank - 0 , we # 1 and cs # 1 for rank - 1 , etc .). it should be apparent to one skilled in the art that the position of the temperature measurement module 4 within the sdram 10 ( as illustrated in fig6 ) may be altered while remaining within the scope of the present invention . the positioning may be dependent upon the purpose to be served by the temperature measurement module 4 ( e . g ., to protect against overcurrent damage , to compensate for cross sensitivity of other sensors , to reduce errors caused by self - heating , to provide process data input , etc .). it should further be apparent to one skilled in the art that the use of sdram 10 is for exemplary purposes only and that other types of memory devices may be used while remaining within the scope of the present invention . it should be apparent to those of ordinary skill in the art that equivalent logic or physical circuits may be constructed using alternate logic elements while remaining within the scope of the present invention . it should further be recognized that the above - described embodiments of the invention are intended to be illustrative only . those skilled in the art may devise numerous alternative embodiments without departing from the scope of the following claims .