fig1 a - 1g are cross - section views of an array substrate of a transflective lcd in process steps according to the first embodiment of the present invention . in fig1 a , regions from left to right are a thin film transistor ( tft ) region a , a pixel region b , a storage capacitance region c and a gate pad region d , respectively . first , a transparent conductive layer 110 and a fist metal layer 120 are formed sequentially on a substrate 100 . then , a first half - tone photo - mask is used to define the first metal layer 120 and the transparent conductive layer 110 simultaneously . the first metal layer 120 is defined to form complementary patterns 120 a , 120 c and 120 d and a reflective layer 120 b , which is on a penetrating portion of the pixel region b . the complementary patterns 120 a , 120 c and 120 d are the complementary patterns of a gate electrode , a capacitance line and a gate pad , respectively . a complementary pattern of a scan line is also formed in the first metal layer 120 but not shown in fig1 a . the transparent conductive layer 110 is defined to form a pixel electrode . the first metal layer 120 with complementary patterns of the gate electrode 120 a , the capacitance line 120 c , the scan line ( not shown ) and the gate pad 120 d is used as a photo - mask for the following backward exposure process . the reflective layer 120 b on the penetrating portion of the pixel region b is used to reflect external light which enters into the lcd . in fig1 b , a passivation layer 130 and a second metal layer 140 are sequentially formed on the substrate 100 . then , the first metal layer 120 with complementary patterns is used as a photo - mask to define the second metal layer 140 by means of a backward exposure . therefore , the second metal layer 140 is defined to form a gate electrode 140 a , a capacitance line 140 c , a scan line ( not shown ) and a gate pad 140 d . at the same time , a sacrifice metal layer 140 b is formed on the penetrating portion of the pixel region b in the second metal layer 140 . the capacitance line 140 c , the underlying first passivation layer 130 and transparent conductive layer 110 constitute a first storage capacitance 141 . in fig1 c , a dielectric layer 150 is formed on the substrate 100 . in fig1 d , a second photo - mask is used to define the dielectric layer 150 , the second metal layer 140 and the first passivation layer 130 simultaneously . the second photo - mask is a half - tone photo - mask . because different regions of the half - tone photo - mask have different light transmittances , photo resist with different thicknesses on different regions is formed after exposure and development processes . after an etching process , several layers underlying the photo resist can be defined simultaneously . in the first embodiment , the photo resist has the highest thickness on a reflective portion of the pixel region b and regions outside the gate pad region d , second highest thickness on the gate pad 140 d , and zero thickness on the penetrating portion of the pixel region b and regions surrounding the gate pad 140 d . because no photo resist is on the penetrating portion of the pixel region b and regions surrounding the gate pad 104 d , the sacrifice metal layer 140 b on the penetrating region of the pixel region b and a portion of the first passivation layer 130 surrounding the sacrifice metal layer are removed in the etching process , at the same time , the dielectric layer 150 and the first passivation layer 130 surrounding the gate pad 140 d are also removed to expose the gate pad 140 d . after the etching process , the dielectric layer 150 on the gate electrode 140 a can be used as the gate isolation layer 150 a . the dielectric layer 150 on the capacitance line 140 c and the scan line ( not shown ) can be used to protect conducting wires and to provide electrical isolation for conducting wires . in fig1 e , a semiconductor layer is formed on the substrate 100 , and then a third photo - mask is used to define the semiconductor layer to form a channel region 160 a on the dielectric layer 150 on the gate electrode 140 a . in a preferred embodiment , the semiconductor layer comprises an amorphous silicon layer and an n - type doped amorphous silicon layer thereon . the second photo - mask of fig1 d and the third photo - mask of fig1 e can be combined as a single half - tone photo - mask . first , a dielectric layer 150 and a semiconductor layer 160 are sequentially formed on the substrate 100 . then , a half - tone photo - mask is used to define the semiconductor layer 160 , the dielectric layer 150 , the second metal layer 140 and the first passivation layer 130 simultaneously . therefore , the number of the photo - masks used in manufacturing the array substrate of a transflective lcd can further be reduced . after exposure and development processes , the photo resist has the highest thickness on the channel region 160 a , second highest thickness on the gate pad 140 d , zero thickness on the penetrating portion of the pixel region b and regions surrounding the gate pad 140 d , and the photo resist on other regions has thickness between the thickness on the channel region 160 a and the thickness on the gate pad 140 d . in fig1 f , a third metal layer 170 is formed on the substrate 100 . then , a fourth photo - mask is used to define the third metal layer 170 to form a source electrode 170 a , a drain electrode 171 a , an expanded gate pad 170 d , a signal line ( not shown ) and a signal pad ( not shown ). the source electrode 170 a and the drain electrode 171 a are on two sides of the channel region 160 a . the drain electrode 171 a is electrically connected to the transparent conductive layer 110 . the expanded gate pad 170 d is directly connected to the gate pad 140 d to reduce impedance of the gate pad 140 d . the structure of the expanded gate pad 170 d is similar to the structure of the signal pad . therefore , an expanded signal pad with a structure similar to the gate pad 140 d can be selectively formed under the signal pad to reduce impedance of the signal pad . in fig1 g , a second passivation layer 180 is formed on the substrate 100 . then , the second passivation layer 180 is defined by back exposure to remove the second passivation layer 180 and the first passivation layer 130 on the penetrating portion of the pixel region b . fig2 a - 2d are cross - section views of an array substrate of a transflective lcd in process steps according to the second embodiment . from the process step of forming the transparent conductive layer 110 to the process step of forming the dielectric layer 150 , the second embodiment is the same as the first embodiment . therefore , the description about these process steps can be directly referred to the first embodiment . in fig2 a , a second photo - mask is used to define the dielectric layer 150 , the second metal layer 140 and the first passivation layer 130 after forming the dielectric layer 150 . in this process step , the sacrifice metal layer 140 b on the penetrating portion of the pixel region b and the dielectric layer 150 thereon are removed , at the same time , the dielectric layer 150 and the first passivation layer 130 on a side of the first storage capacitance 141 is removed to form a contact window 151 . moreover , the dielectric layer 150 and the first passivation layer 130 surrounding the gate pad 140 d are removed to expose the gate pad 140 d at the same time . in fig2 b , a semiconductor layer is formed after forming the contact window 151 . a third photo - mask is used to define the semiconductor layer to form a channel region 160 a on the dielectric layer 150 on the gate electrode 140 a . the same as the first embodiment , the second photo - mask of fig2 a and the third photo - mask of fig2 b can be combined as a single half - tone photo - mask . the half - tone photo - mask used here is very similar to the half - tone photo - mask in the first embodiment except the photo - mask of the second embodiment has a contact window pattern thereon . in fig2 c , a third metal layer 170 is formed on the substrate 100 . a fourth photo - mask is used to define the third metal layer 170 to form a source electrode 170 a , a drain electrode 171 a , an expanded capacitance 170 c , an expanded gate pad 170 d , a signal line ( not shown ) and a signal pad ( not shown ). the source electrode 170 a and the drain electrode 171 a are on two sides of the channel region 160 a . the drain electrode 171 a is electrically connected to the transparent conductive layer 110 . the expanded capacitance line 170 c is on the dielectric layer 150 on the capacitance line 140 c . the expanded capacitance line 170 c is electrically connected to the transparent conductive layer 110 through the contact window 151 . the expanded capacitance 170 c , the underlying dielectric layer 150 and capacitance line 140 c constitute a second storage capacitance 171 . the second storage capacitance 171 and the first capacitance 141 connect in series , not only the capacitance value per unit of area can be increased but also the overall area on the substrate occupied by the storage capacitance can be reduced . moreover , the aperture rate of the penetrating region of the pixel region and the brightness of the lcd are increased . as shown in fig2 d , a second passivation layer 180 on the substrate 100 is formed . the second passivation layer 180 is defined by means of back exposure , and at the same time the second passivation layer 180 and the first passivation layer 130 on the penetrating region of the pixel region b are removed . accordingly , the present invention , as shown and described , has at least the following advantages . ( 1 ) in preferred embodiments , only three to four photo - masks are needed to manufacture a transflective lcd . therefore , not only the production cost can be greatly reduced but also the production volume can be increased . ( 2 ) the gate pad and the expanded gate pad are directly connected to reduce impedance of the gate pad . ( 3 ) the storage capacitances connect in series , not only the capacitance value per unit of area can be increased but also the overall area on the substrate occupied by the storage capacitance can be reduced . moreover , the aperture rate of the penetrating region of the pixel region and the brightness of the lcd are increased . the preferred embodiments of the present invention described above should not be regarded as limitations to the present invention . it will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the scope or spirit of the invention , as defined in the appended claims .