referring to fig1 a schematic block diagram of a processor architecture using active power management is shown . for clarity certain elements of fig1 are presented as separate blocks in the block diagram denoted by function . it will readily be appreciated that these elements may in fact be software applications run on one or more processors in the architecture . an active power management application ( apm ) 10 runs on a first processor dxp 0 12 . the apm 10 is configured to receive operating cycle information in the form of mips from processor dxp 0 12 . apm 10 is also configured to receive parameters defining an execution profile . in particular embodiments of the invention the execution profile data is supplied to apm 10 by applications running on processor dxp 0 12 . a further processor dxp 1 14 is also illustrated . the processor dxp 1 14 has no execution profile — it is assumed to operate as a general purpose processor , and can request a required operating frequency ( referred to herein a mhz ) on demand . the processor dxp 0 12 , however , handles real - time applications of a “ periodic ” nature . its clock demands are discussed in the following . a clock frequency control output 15 from apm 10 controls a processor clock ( clk ) 16 . the clock 16 generates a clock signal for processor dxp 0 12 and processor dxp 1 14 at a frequency controlled by the apm 10 . a voltage control output 17 from apm 10 controls a function 20 within an avs ( automatic voltage supply ) function 18 which selects a supply voltage from first and second preset levels , vdd 1 , vdd 2 . the selected setting , vdd 1 or vdd 2 sets the supply voltage of processors dxp 0 12 and dxp 1 14 . the avs 18 has a function 22 ( full path function ) which sets the levels of vdd 1 and vdd 2 , for example to track temperature , in addition to the select ( fast path ) function 20 for selecting between the individual settings . in operation execution profile data is supplied to apm 10 . the execution profile data may be supplied to apm 10 by processor dxp 0 12 . execution profiles define how the need for clock frequency ( mhz ) of processor dxp 0 12 changes over the entire profile timespan . the behaviour of processor dxp 0 12 is assumed to be periodic . in this context a period is a time during which intense processing activity is required , followed by a lull . an example is a umts slot of data in a wireless communication system , a umts slot being 666 microseconds long . the period is assumed to be “ short ”, which means it is not possible to change supply voltage vdd 18 many times in a period because of the change latency and apm overhead . execution profiles are mode - specific . consequently there may be separate profiles for e . g . umts and gsm modes . the software of apm 10 allows the active profile to be changed when the wireless modem mode changes ( e . g . umts / gsm , but also umts voice / umts high speed data . according to the described embodiment , an execution profile is composed of two parts only : high speed ( high frequency ) and low speed ( low frequency ) intervals . it is recognized that the needs of apm 10 may not be easily expressed in terms of such a simple model , so additional flexibility is allowed : the application may ask to shorten the low frequency interval in each profile period as shown in fig3 and discussed below . an execution profile includes the following information , which may be provided to apm 10 in the form of parameters : the requested clock frequency for the high frequency interval ; the minimum length of the high frequency interval in microseconds ; the length of the entire execution profile period ; and the average clock frequency the application needs . the apm 10 is then able to derive further information for each execution profile based on the execution profile data supplied to it . the derived data may include : the granted clock frequency for the high frequency interval ; the granted clock frequency for the low frequency interval ; and the nominal high frequency interval length . in the process of selecting “ granted ” frequencies , required mips from the processor dxp 1 14 can be requested ( in addition to the parameters from the profile ) is taken into account ; in this way dxp 1 can modulate a profile - based “ granting procedure ”. the granted mhz for the high frequency interval will usually , i . e . under normal operating conditions , be higher than the requested mhz . this is due to the granularity of the clock 16 . in the described embodiment , the clock signal is generated by a phase locked loop ( pll ) with the frequency controlled by a divisor . the granted mhz for the low frequency interval and the actual nominal high frequency interval length may be selected to satisfy an average mhz request . they may also take into account the granularity of the clock 16 . the granted mhz for the high and low frequency intervals remain constant for a given mode . the avs function 18 receives the granted mhz on line 15 and uses them as a reference mhz to adapt two vdd settings , vdd 1 and vdd 2 . this is explained further below . the granted mhz for the low frequency interval cannot be higher than the granted mhz for the high frequency interval . they are allowed to be the same . this is guaranteed by the clock frequency granting procedure . the length of the low frequency interval can be modified in dependence on the application ( modem software ) executing on the processor dxp 0 12 . that is , because the mips required by processor dxp 0 12 for the low frequency interval may differ on period by period basis , the modem software is configured to allow the passing of this information to apm 10 at the commencement of each period ( actually on every high frequency to low frequency transition ). the apm 10 may then decide , if necessary , to bring forward the subsequent low frequency to high frequency transition , or to suppress the low interval completely for the current period , to give the modem software more mips . this feature can be viewed as a type of pwm ( pulse width modulation ), enhancing the basic two - interval periodicity . profile interval switches , i . e . switches from high frequency interval to low frequency interval and vice - versa , involve modifying the clock frequency and selecting the supply voltage between vdd 1 / vdd 2 . the clock frequency is modified by changing the clock divisors sent from apm 10 to clk 16 . this configuration requires no reprogramming of the phase lock loop used to generate clk 16 , and is therefore very fast . voltage change is implemented herein by programming two vdd settings for the core voltage ( full path ) and switching between them using a dedicated input signal 17 ( fast path ). actual programming of two vdd settings can be done by the avs application running on processor dxp 1 14 , while apm 10 just selects one of two settings using fast toggling of a dedicated hardware signal . there is latency between when select function 20 that controls the output of avs 18 is switched and when the selected vdd reaches the desired voltage level . because of the vdd latency , change events of vdd 18 are scheduled before a frequency change when changing to higher frequency and voltage to ensure that the vdd is suitable for a higher frequency . there are two cases to consider when transitioning between intervals during an execution period : low frequency → high frequency interval switch . first vdd 18 must be increased and only after sufficient delay clk 16 may be increased . this may be performed as a two - step operation , unlike reducing vdd / frequency . voltage change will be scheduled to occur before switching to the high frequency interval . clock frequency switch will be scheduled to occur exactly when required . high frequency → low frequency interval switch . first clk 16 should be reduced and then vdd 18 can be decreased . this may be done on demand , i . e . when the modem software signals that the high interval has been completed . referring to fig2 , a schematic flow chart is shown outlining a sequence of steps for active power management of a processor . an execution profile is supplied to apm 10 at step 22 . the execution profile comprises parameters as discussed above , and defines high frequency and low frequency operating intervals for an active period . based on the execution profile supplied , apm 10 determines the granted high frequency clock ( step 24 ) and the granted low frequency clock ( step 26 ), taking into account mhz requirements of dxp 0 14 and clock granularity . in step 28 , apm passes granted clocks to avs . at step 30 there is also supplied to apm 10 , at the commencement of a period , an operating cycle requirement for the period , determined by the modem software . the operating cycle requirement may be provided by processor dxp 0 12 . exemplary operating cycle requirements may be in the form of required mips . the length of the low frequency interval may be calculated based on the operating cycle requirement by apm 10 at step 32 . calculation of the length of the low frequency interval is undertaken following an assessment of whether the high frequency interval has undergone a “ jittery ” transition . apm 10 determines the length of the low interval every period based on the mips required in this period and the actual time of the “ jittery ” high to low transition . for effective , integrated power management , in the described embodiment of the invention the granted high frequency and low frequency clocks are supplied to the avs function 18 . the avs may use this clock information to adapt the settings of vdd 1 and vdd 2 as described above . at step 34 apm 10 controls clk 16 by providing divisors to divide the clock signal provided to the phase lock loop that generates the processor clock signal . vdd is controlled as explained above . steps 30 , 32 , 34 are performed repeatedly in a loop . the following is a possible algorithm which may be used to implement the invention : the above algorithm above is capable of reducing the low interval length but cannot extend it . however , alternatives are possible where the low interval length is extended . the algorithm is included for illustration purposes only . the scope of the invention is intended to cover the use of alternative algorithms that implement the invention as described in the accompanying claims . alternative algorithms may accommodate additional factors . the apm 10 user may request dynamically ( on a period by period basis ) that the low frequency interval length is extended or shortened ( if possible ) from its nominal value depending on the estimation of its momentary clock frequency needs . referring to fig3 an exemplary schematic for an execution profile is shown . time is shown on the horizontal axis . the high frequency interval 38 and the low frequency interval 40 are clearly shown as comprising the entire profile period 42 . fig3 also shows the requested clock frequency 44 for the high and low frequency intervals , and the granted clock frequencies 46 for the high frequency and low frequency intervals . the vdd trace 48 is also shown and demonstrates the vdd latency 50 during transition from high frequency interval to low frequency interval , and the vdd latency 52 during transmission from the low frequency interval to the high frequency interval . the start 54 of the profile period 42 and the end 56 of the profile period 42 are fixed , as already stated above . however , the transition from high frequency interval to low frequency interval may suffer from jitter 58 . it can therefore be seen in fig3 that the length of the low frequency interval 40 may be altered 60 , 62 to accommodate this and improve power efficiency by extending the low interval . it will be appreciated that the active power management described above is particularly suited to “ periodic ” software , that is for example processing slot - based data in a wireless communication system , or in other situations where the data processing is “ bursty ”. in other circumstances , the processor dxp 0 12 should be allowed to request mhz in a normal manner , as the processor dxp 1 14 . the architecture can be setup so that if an execution profile is selected , any direct request from the processor dxp 0 12 for mhz is ignored . the processor dxp 0 12 could be told to “ unselect ” the execution profile , in which case the direct mhz request becomes valid . if no profile is selected , and neither of the processors request mhz , a minimum mhz will be selected . mhz requests by the processors dxp 1 14 and dxp 0 12 ( either direct or profile - based ) are combined in the apm 10 and passed to the avs function 18 , which tracks the supply voltage vdd for the combined mhz request . while in the above described embodiment only the length of the low frequency interval is modified based on the mips requirement received at the commencement of a period , it would be possible also to tune the granted clock frequencies at that point .