embodiments of this invention will now be described with reference to the accompanying drawing . fig1 shows an ic tester in accordance with an embodiment of this invention . the ic tester shown has a prime oscillator 21 for generating reference signals and a common timing circuit 22 connected to this prime oscillator 21 . the common timing circuit 22 includes a plurality of clock circuits 23 and a plurality of strobing circuits 24 . the clock circuits 23 are connected to a plurality of selectors 26a and 26b through a distribution line 25 , the selectors 26a and 26b being connected to respective drivers 27a and 27b . the strobing circuits 24 of the common timing circuit 22 are connected to a plurality of selectors 28a and 28b through the distribution line 25 , the selectors 28a and 28b being connected to respective comparators 29a and 29b . further , connected to the prime oscillator 21 are a dedicated clock circuit 31a and a dedicated strobing circuit 32a , which are dedicated to one ic 20a to be tested , as well as a dedicated clock circuit 31b and a dedicated strobing circuit 32b , which are dedicated to the other ic 20b to be tested . drivers 33a and 33b are connected to the dedicated clock circuits 31a and 31b , respectively , and comparators 34a and 34b are connected to the dedicated strobing circuits 32a and 32b , respectively . tester pins 35 are connected to the drivers 27a , 27b , 33a and 33b , as well as the comparators 29a , 29b , 34a and 34b , respectively . in the illustrated embodiment the prime oscillator 21 , the common timing circuit 22 , the dedicated clock circuits 31a and 31b , and the dedicated strobing circuits 32a and 32b constitute a timing generating means . further , a cpu 36 , which constitutes the control means , is connected to the respective circuits constituting the timing generating means as well as to the respective selectors , the respective drivers , and the respective comparators . in fig1 the respective connecting lines which connect the cpu 36 to the selectors 26b and 28b , to the drivers 27a , 27b and 33b , and to the comparators 29a , 29b and 34b , are omitted . next , the operation of the ic tester of this embodiment when testing two ics simultaneously will be described . like the ic 15 shown in fig4 a , the ic 20a to be tested is equipped with an internal - clock generating circuit and an internal circuit which operates by internal clocks generated by the internal clock generating circuit . the ic 20a is further equipped with an input terminal t1 and an output terminal t2 which are connected to the above - mentioned internal circuit as well as an input terminal t3 and an output terminal t4 which are not connected to the internal circuit and which deal with signals not depending on the internal clocks . the input terminal t1 , the output terminal t2 , the input terminal t3 , and the output terminal t4 , of this ic 20a to be tested , are connected to the driver 33a , the comparator 34a , the driver 27a , and the comparator 29a , respectively , by means of respective tester pins 35 . the other ic 20b to be tested has a construction similar to that of the above - described ic 20a and is equipped with input terminals t1 , t3 and output terminals t2 , t4 . the input terminal t1 and the output terminal t2 , which are connected to the internal circuit of this ic 20b , are respectively connected to the driver 33b and the comparator 34b , and the input terminal t3 and the output terminal t4 , which are not connected to the above internal circuit , are respectively connected to the driver 27b and the comparator 29b . the cpu 36 supplies the prime oscillator 21 with instruction signals designating the periods of the reference signals to be emitted therefrom . thus , the prime oscillator 21 generates reference signals having periods which are in conformity with these instructions and supplies these reference signals to the dedicated clock circuits 31a , 31b and the dedicated strobing circuits 32a , 32b . the dedicated clock circuits 31a and 31b generate predetermined timing signals and supply them to the drivers 33a and 33b , and clock signals which are based on these timing signals , are supplied from the drivers 33a and 33b to the respective input terminals t1 of the ics 20a and 20b . based on the clock signals thus supplied , signals are emitted through the respective output terminals t2 of the ics 20a an 20b and are supplied to the dedicated strobing circuits 32a and 32b through the comparators 34 and 34b , respectively . the dedicated strobing circuits 32a and 32b measure the differences in timing between the clock signals and the output signals in the respective ics 20a and 20b , respectively . on the basis of the timing differences thus measured by the dedicated strobing circuits 32a and 32b , the cpu 36 provides the dedicated clock circuits 31a and 31b with timings which are independent of each other in such a manner that the respective timings of the output signals from the ics 20a and 20b , i . e ., the respective timings of the internal clocks of these ics , coincide with each other . afterwards , the dedicated clock circuits 31a and 31b generate input timing signals having the mutually independent timings set by the cpu 36 and supply them to the drivers 33a and 33b , respectively , and the dedicated strobing circuits 32a and 32b generate judgment timing signals and supply them to comparators 34a and 34b , respectively . the drivers 33a and 33b generate testing signals on the basis of the input timing signals supplied thereto and supply them to the respective input terminals t1 of the ics 20a and 20b . the reference signals from the prime oscillator 21 are also supplied to the clock circuits 23 and the strobing circuits 24 of the common timing circuit 22 . the clock circuits 23 generate input timing signals having mutually different timings and supply them to the selectors 26a and 26b . the strobing circuits 24 generate judgment timing signals having mutually different timings and supply them to the selectors 28a and 28b . the selectors 26a and 26b respectively select the requisite input timing signals in accordance with the instructions from the cpu 36 and supply them to the corresponding drivers 27a and 27b . the drivers 27a and 27b generate testing signals on the basis of the input timing signals supplied thereto and supply them to the respective input terminals t3 of the ics 20a and 20b through the respective tester pins 35 . thus , the two ics 20a and 20b operate in accordance with the testing signals supplied through the respective input terminals t1 and t3 and emit output signals through the respective output terminals t2 and t4 . the output signals emitted through the respective output terminals t2 are supplied through the respective tester pins 35 to the corresponding comparators 34a and 34b , where the output signals are judged on the basis of the judgment timing signals supplied from the dedicated strobing circuits 32a and 32b . the output signals emitted through the respective output terminals t4 of the ics 20a and 20b are supplied to the corresponding comparators 29a and 29b through the respective tester pins 35 . at this time , instructions from the cpu 36 have already been supplied to the respective selectors 28a and 28b . in accordance with these instructions , the selectors 28a and 28b select the requisite judgment timing signals and supply them to the corresponding comparators 29a and 29b . the comparators 29a and 29b make a judgment on the output signals from the respective output terminals t4 of the ics 20a and 20b . the cpu decides whether the ic 20a is good or defective in accordance with the judgment results obtained by the comparators 29a and 34a , and decides whether the ic 20b is good or defective in accordance with the judgment results obtained by the comparators 29b and 34b . thus , in accordance with this embodiment , the respective operational timings of the two ics 20a and 20b , which operate by respective internal clocks peculiar to them , are made to coincide with each other by using the dedicated clock circuits 31a , 31b and the dedicated strobing circuits 32a , 32b , thereby making it possible to perform the multi - testing of these two ics 20a and 20b . although the embodiment described above employs a common timing circuit 22 which is common to the two ics 20a and 20b , it is also possible to connect dedicated clock circuits or dedicated strobing circuits which are independent of each other to all the terminals of the ics to be tested . further , while in the above embodiment the multi - testing of two ics is performed , it is also possible to perform the multi - testing of three or more ics by providing a number of dedicated clock circuits and dedicated strobing circuits .