with reference to the following detailed description , the accompanying schematic is divided into east and west terminals with like elements having the same reference numerals followed by reference characters e or w to designate the appropriate location . only the reference numeral will be referred to unless specific reference to one or the other is required . also , both terminals are basically the same . hence only the east terminal is shown in detail . each of the east - west station terminals comprises a telephone set 10 connected via a two - wire transmission path 11 to a hybrid network 12 . analog transmit and receive signals are coupled from the network 12 to a digital transmit 13 and a receive 14 four - wire transmission path via analog - digital ( a / d ) 15 and digital - analog ( d / a ) 16 converters . the converters 15 and 16 are in turn coupled to a digital switching system 17 . it will be evident that the switching system 17 may be a local pbx , one or more central offices connected in tandem via inter - office trunks , or any combination of these . in addition , one of the two central switching offices may operate on two - wire analog signals in which case the signals will be converted from digital to analog at the output of the other office . each of the voice controlled digital echo attenuation circuits comprises a control logic circuit generally 18 , which controls the insertion of a 6db attenuator pad generally 19 , in the receive path in response to the relative magnitude of the transmit and receive signals . when the input to the circuit 18 is prior to the 6db pad 19 in the receive path , each of the two control logic circuits 18 receive information of the same relative magnitude for comparison purposes . consequently , there will be a minimum amount of hysteresis or overlap between the insertion of one digital pad ( say 19e ) and the removal of the other ( 19w ). however , when the signal sample in the receive path 14 is obtained after the pad 19 , the one attenuator pad ( say 19e ) will be inserted well before the removal of the other ( 19w ), so as to provide a greater hysteresis around the loop . in the following description , a standard pcm format for transmission of voice signals will be assumed in which an 8 - bit code comprising a single polarity or sign bit and seven magnitude bits are used to transmit a voice signal sampled at an 8 khz rate . the analog signals are encoded using a μ - 255 or a - law so that the binary value of the magnitude bits is roughly proportional to the logarithm of the encoded signal amplitude . both digital signals on the transmit and receive paths 13 and 14 are coupled to separate serial - to parallel converters 20 and 21 respectively . during each sample , the n = 4 most - significant bits of the m = 7 magnitude bits from the output of each of the converters 20 and 21 are fed to an 8 khz rate or every 125 μsec to a four - bit x - y comparator 22 . when the transmit signal x is equal to or greater than the receive signal y , an output will be obtained from the comparator 22 which increments an l = 8 - bit up / down counter or accumulator 23 by one . on the other hand , when the receive signal y is greater than the transmit signal x , the counter is decremented by one . the counter 23 includes a conditional overflow halt control which prevents the counter from recycling once it is filled or empty . the contents of the counter 23 therefore can vary anywhere between 0 and a maximum of ( 2 l - 1 ) = 2 8 - 1 = 255 . when the counter is more than half - full , i . e . a ( n ) ≧ 128 , an output is obtained on the most - significant bit lead 24 which opens and closes and gates 25 and 26 respectively so as to connect a 6db digital attenuator 27 in series with the receive path 14 . comparing only the four most - significant bits results in an output x = y from the comparator 22 for small amplitude differences of less than about 3db . as a result the counter 23 at both east and west terminals is continually being incremented during no signal periods . this biases the control logic 18 so that both pads 19 tend to remain in the four - wire path except when a signal is present on one of the receive paths 14 . in the above - described embodiment , various units are synchronized by a recovered clock signal ( clk ) in a well known manner . in addition , the output of each of the serial - to - parallel converters 20 and 21 is truncated so that only the four out of seven most - significant bits are compared in the comparator 22 . in addition , the output of the comparator 22 is also truncated so that the counter 23 is only augmented up or down a single bit after each comparison . it will be evident that various other configurations could be utilized and that the amount of delay encountered in switching the pads 19 in and out can be readily altered by changing the capacity and / or threshold point of the counter 23 . in addition , it has been found that 6db attenuation of the digital signals in the attenuators 27 provides sufficent margin to prevent severe distortion of the signals being propagated around the four - wire path without noticeably affecting the level of the listening path . consequently , should a double - talking condition occur , both parties will hear the other without undue attenuation even though one or possibly both of the 6db attenuator pads 19 are in . as illustrated , the received digital signal fed to the serial - to - parallel converter 21 is obtained prior to the attenuator 27 . if a more pronounced hysteresis or overlap between the insertion of one pad ( say 19e ) and the removal of the other ( 19w ) is required , the input to the serial - to - parallel converter 21 can be obtained from the output of and gates 25 and 26 by altering the position of switch 28 . as a result , once the pad 27 is in the circuit , the y signals will be automatically attenuated by 6db thereby tending to retain the attenuator 27 in the receive path 14e until a strong signal is received from telephone 10w . the embodiment described above utilizes a single control logic circuit 18 per line . it will be evident that as with many digital transmission systems , some of the circuitry can be used on a time - shared basis . for instance , if a pcm signal utilizing the standard 24 channel t1 format ( see transmission systems for communication by bell telephone laboratories , inc . fourth edition , pp . 556 et seq .) were transmitted and received along the four - wire path the control logic could be readily arranged by the use of additional storage , memory and recall circuitry to sequentially insert or remove the 6db pads 19 from the line depending upon the various conditions in each of the 24 channels . the circuit can be readily implemented using standard logic elements . one suitable form of digital attenuator is described in u . s . pat . no . 4 , 021 , 652 issued may 3 , 1977 and invented by ernst a . munter . in addition to the alternate circuit configurations shown in the drawing obtained by actuating the switch 28 , a third configuration can be realized by placing the attenuator rods 19 in the transmit legs 13 rather than the receive legs 14 of the four - wire path . with this configuration the serial - to - parallel converter 20 must be connected prior to the input to the pad 19 otherwise the circuit will tend to insert the attenuation in the talking rather than the listening path except under very strong signal conditions . in addition the output of the comparator 22 must be inverted so that the pads 19 are inserted in the transmit path 13 only when the signal on the receive path 14 is stronger . this configuration also has the added disadvantage that in a mixed network , the levels on the analog facilities would be 6db lower when the pads are in , thereby decreasing the signal - to - noise ratio .