turning to fig5 a through 5d , we see the schematic cross section of the device fabrication of a buried crescent heterostructure eled preferably employed to fabricate the present invention . the device is fabricated as follows . first we see in fig5 a , a substrate 51 which is preferably n - inp wafer that is doped to a degree that it is conductive , for preferably having doping levels of approximately 10 17 to 10 19 cm - 1 . a layer of high thermal conductivity semi - insulating material 52 ( for example fe doped inp ) is epitaxially grown on the substrate 51 preferably by metal oxide chemical vapor deposition ( mocvd ), however techniques such as liquid phase epitaxy ( lpe ), molecular beam epitaxy ( mbe ) and chemical beam epitaxy ( cbe ) are also possible techniques . turning now to fig5 b , we see the etched layers of the semi - insulating layer in order to effect the groove structure which advantageously divides the device into first and second regions with attendant advantages . the etching of the semi - insulating layer and the substrate as shown in fig5 b is effected preferably by masking with an appropriate mask such as sio 2 or silicon nitride followed by wet chemical etchant , however a dry etching method such as reactive ion etching ( rie ) is within the purview of the present invention . the epitaxial materials are grown first in a planar structure and then masked with dielectric or photoresist . the mask is patterned and partially removed . the exposed area is then etched by an isotropical etchant to leave a groove structure of the semi - insulating layer and substrate . the unetched semi - insulating portion 53 divides the device into a first and second region for discussion purposes . in any event , the grooves 54 are preferably in the dimension of a few microns in depth and a few hundred microns in length . it is critical that in the lateral dimension ( the width ) the grooves have an arrowhead or v - shape as at 55 to pinch off the active region in the ensuing regrowth . in the longitudinal direction the v - shape of the grooves facilitates the light diffusion as at 56 . the desired orientations of the arrowhead 55 and the light diffusion surface 56 are effected by etching to reveal selected crystalline planes of the monocrystalline layers of the semi - insulating and substrate layers . by way of example , by choosing a ( 001 ) substrate , a 54 . 7 degree angle relative to the substrate is achieved with a ( 111 ) surface etch of the face 56 in the semi - insulating layer . the orientations described are merely exemplary , and it is clearly understood that other materials with other crystalline orientations are considered within the purview of the skilled artisan . details of selective crystalline etching are found in u . s . pat . no . 4 , 210 , 923 to north , et al ., the disclosure of which is specifically incorporated herein by reference . the buried crescent heterostructure as shown in fig5 c is fabricated preferably as follows . the first cladding layer 57 which is preferably of inp is grown by preferably lpe and effects a concave surface in the region of the etched grooves at an increased growth rate over that of convex growth . accordingly , the lpe is carried out for preferably 10 - 90 seconds along with the growth of the active / absorption layer 58 of n - ingaasp in the first and second regions 511 and 512 , of the device respectively , to form a concave structure as shown in a single high growth rate step . at this point , the second cladding layer of inp 59 is grown by a long lpe step , generally of a few minutes . this enables relatively planar growth of this layer 510 as is desired . finally , a cap layer of n - ingaasp is grown in a relatively fast planar growth step of about 20 - 30 seconds of lpe to form the planar layer as shown . it is of course possible to have differently doped materials for the differing materials . as the important factor being that the basic physics of an eled be employed , it is considered within the purview of the skilled artisan to effect a device by differently doped materials as well as different iii - v compounds . finally , turning to fig5 d , we see the final version of a preferred embodiment of the instant invention . partial etching of the cap , second cladding and the semi - insulating layers is carried out for reasons explained herein . the etching is achieved by masking selected regions of the structure with a dielectric or photoresist followed by a wet etch of isotropical etchant . the mask is then removed with a solution of hf , for example . the removal of these layers selectively enables operation of the device with the attendant advantage of preventing current flow to the absorption region . thereby , any light which is transmitted through the diffusion surface from the active region will be absorbed more readily in this electrically unpumped region . accordingly , the tendency of the device to lase is suppressed , and the device functions as a high speed eled . a further preferred embodiment is as shown in fig5 d . to be specific , after the selective etching of the cap , second cladding and semi - insulating layers , a double channel 513 is revealed . the channel is etched via photolithographic techniques above described , using a dielectric or photoresist as a mask in the etching of the double channel in the first region 512 of the device and to etch the entire second region 513 of the device , as shown . note the first and second regions 511 and 512 of the device are the imaginary division of the device with the unetched semi - insulating portion 53 as the division between the first and second regions ( this terminology pertains throughout the disclosure with reference to the first and second regions ). the double channel could be etched in the first region deeper than in the second region , and thereby to be within about two microns of the active layer . the heat generated in the active layer could be readily dissipated through the two microns of semi - insulating inp , and readily through a thermally conductive material deposited ( described below in connection with fig5 e , below ) in the channel and across the first region as shown . choosing the channel to be etched within two microns of the active layer allows for heat dissipation without any appreciable absorption of the optical field ( via the evanescent tail ) of the active layer which tails off exponentially with distance at the semi - insulating layer / active layer interface . were the channel in contact with the active layer , a metal material in the channel would be absorbed the optical field of the active layer to some extent , whereas in the instant invention , there is no appreciable absorption . turning now to fig5 e , we see a deposited metal layer 514 as the heat sink . the metal layer is preferably an alloy of ti - pt - au or au - zn - au for a p - type cap layer . for an n - cap layer it is preferred to use an alloy of auge - ni - au or ge - au - ni - au . the layers are deposited by standard plating or evaporation techniques . the heat generated in the active layer is dissipated across the semi - insulating layer and through the thermally conductive layer enabling the device to operate at nearly linear light output versus current input characteristic . this method of heat dissipation is not possible with the structure of the prior art as for example an n - cap , p - n - p - n blocking layer , the thermally conductive layer would short the n - cap and the n blocking layers . finally , the device as shown in fig5 f has no heat dissipating channel and is fabricated above with the steps toward the channel fabrication eliminated . the layer of dielectric is shown as 515 . the benefits of such a structure are as described presently . first , this structure minimizes the area of the pn junctions through mesa structure , and has the benefit thereby of reducing the ill - effects of pn junction capacitance . secondly , the deposition of a semi - insulating layer as the isolating layer serves as well to decrease the capacitance between the p - electrode and the n - electrode , outside the mesa region . the advantage of having a reduction in the overall intrinsic capacitance of the eled is the great reduction in rise and fall time of the device due to a reduction in the device rc time constant . reducing the rc time constant increases the switching speed , and in the realm of nearly square - wave digital signals faster rise and fall response times will result in higher frequency devices with greatly enhanced communication bandwidths . this eled as designed experiences rise and fall times on the order of 0 . 5 nanoseconds . this rapid switching capability has resulted in a bandwidth of over 700 mhz . another benefit of the present device design is its capability to dissipate the joule heat generated in operation . joule heating in conventional light emitting devices results in non - linear light output power versus bias currents . the structure of the present invention has the ability to dissipate heat through two paths . turning to fig5 and 6 , the layer of semi - insulating inp which has a thermal conductivity of approximately 0 . 68 watt - cm - 1 - k - 1 forms one path . the layer 65 has the same thermal expansion coefficient and lattice constant as the n - doped inp substrate , and can thereby be grown to any desired thickness , which has obvious ramifications relative to the degree of electrical isolation as well as the ability of the device to dissipate heat . for example , this could be a layer of fe - doped inp exhibiting a resistivity in the range 10 6 - 10 10 ohm - cm , however other materials could be used in keeping with the theme and spirit of the invention . the dissipation of heat away from the pn junctions of the mesa structure allows the device to operate at high injection current levels without significant heating of the pn junctions , thereby improving the light output power linearity with respect to bias current . turning now to fig6 a - 6f , we see the fabrication steps of the present invention in a buried mesa heterostructure . there are two methods preferred to fabricate the buried mesa structure device , and each will be discussed separately . turning first to fig6 a , we see the planar layers of substrate 61 , first cladding layer 67 , active layer 68 and second cladding layer 69 which are preferably deposited by mocvd , however lpe , mbe or cbe will work . the layers are identical in materials doping types and doping levels as were stated above relative to the buried crescent device . succinctly , for an inp n - substrate , an n - inp first cladding layer , an ingaasp active layer and a p - inp second cladding layer , the first cladding layer is doped with s , si or sn as described above . the active layer is undoped / unintentionally doped or intentionally doped with zn which serves to decrease carrier lifetime and increase the bandwidth of the device . accordingly , bandwidth is increased by decreasing intrinsic capacitance as well as by selective doping of the active layer . however , care must be taken to not dope the active layer too greatly , as light intensity is adversely affected by too high of doping levels . the present invention enables increasing bandwidth even with an undoped / unintentionally doped active layer by virtue of the reduced capacitance . finally , the second cladding layer is doped p - type with zn as described above . turning now to fig6 b , we see the etched structure . etching is effected by photolithography preferably using patterned dielectric to mask the desired regions of the layers . the preferred etchant is hcl , however mixtures of hcl and h 3 po 4 are also possible . the etching again makes use of the characteristic planes of monocrystalline material , and the light diffusion surfaces are readily effected by etching to reveal the ( 111 ) planes . the dielectric is removed by hf solution . turning now to fig6 c , we see the growth of the various layers of the device . the preferred technique is lpe , however , mocvd , mbe or cbe are also possible . by the very nature of lpe , the growth rate in a concave surface is much faster than in a planar or convex surface , the semi - insulating layer 63 could be grown in the non - mesa region with no growth at the top of the mesa . after the semi - insulating layer is grown to result in a nearly planar wafer , the p - cladding 67 , 69 and p - cap layers 610 are grown in planar form thereon . the semi - insulating layer is doped preferably with co at a concentration of 10 19 / cm 3 . the preferred dopant for the p - cap layer is zn in concentration of 10 19 / cm 3 . fig6 d and 6e show the etching to effect the double channel 614 heat sink . as the etching and deposition of a thermally conductive layer is identical to the description associated with fig5 d and 5e , it will not be repeated . the dielectric layer is shown at 615 . turning now to fig7 a and 7b , we see alternative steps to that shown in the fabrication steps shown and described relative to fig6 b . clearly , the same etching is performed in fig7 a , with a dielectric layer as a mask in the etching of the mesas . however , instead of removing the dielectric layer 715 , it is left on during epitaxial growth of the semi - insulating layer so as to serve as a growth inhibitor . the layer of dielectric is deposited so that after etching , it overhangs the mesas as at 71 . this structure will allow epitaxial growth of the semi - insulating layer 73 on the substrate 70 , but will prevent its growth on the second cladding layer 73 . the structure that results is as shown in fig7 b . the preferred technique is growth of the semi - insulating layer , preferably fe - doped inp , by mocvd , however lpe , mbe and cbe . also , as described previously , other dopants are possible if not necessary given the desired substrate for a given structure . the doping concentrations are as stated previously . the growth of the semi - insulating layer is grown to planarize the wafer . after the growth of the semi - insulating layer the structure results as is shown in fig7 b , and the layer of dielectric layer is removed by hf . the cladding layers , active layer , cap layer are as described previously , and the structure can be further processed to effect the heat sink as described above . having described the preferred embodiments , it is clear that there are various techniques for fabrication as well as materials and dopants that are considered within the purview of the artisan of ordinary skill . such variations of the instant teachings contained herein are considered within the theme and spirit of the invention .