the present invention will now be described in detail with reference to the accompanying drawings , namely , fig1 to 3 . throughout the drawings , like reference numerals and letters are used to designate like or equivalent elements for the sake of simplicity of explanation . referring now to fig1 a first embodiment of the level conversion circuit according to the present invention will be described in detail . a first and second npn transistors 10 and 12 are connected to each other in a differential circuit 14 . that is , the emitter terminal of the first and second npn tranistors 10 and 12 are connected to each other and then connected to a low potential source 16 with the low potential vee of , e . g .,-- 2 . 5 volts through a current source 18 . the first and second npn transistors 10 and 12 have collector terminals connected to a high potential source 20 with the high potential vdd of , e . g ., 5 . 0 volts via source - drain paths of first and second pmos transistors 22 and 24 , respectively . that is , the first and second pmos transistors 22 and 24 have source terminals connected to the vdd potential source 20 and drain terminals connected to the collector terminals of the first and second npn transistors 10 and 12 , respectively . further , first and second complementary mos transistor circuits 26 and 28 are both connected between the vdd potential source 20 and a ground potential source g . in the first complementary mos transistor circuit 26 , a third pmos transistor 30 and a first nmos transistor 32 are connected at their drain terminals to each other . while the third pmos transistor 30 and the first nmos transistor 32 are connected at their sources to the vdd potential source 20 and the ground potential source g , respectively . similarly , in the second complementary mos transistor circuit 28 , a fourth pmos transistor 34 and a second nmos transistor 36 are connected at their drain terminals to each other . also the fourth pmos transistor 34 and the second nmos transistor 36 are connected at their sources to the vdd potential source 20 and the ground potential source g , respectively . the gate terminals of the first and third pmos transistors 22 and 30 are connected to each other and further to the connection node of the drain terminal of the first pmos transistor 22 and the collector terminal of the first npn transistor 10 . similarly the gate terminals of the second and fourth pmos transistors 24 and 34 are connected to each other and further to the connection node of the drain terminal of the second pmos transistor 24 and the collector terminal of the second npn transistor 12 . the first and second nmos transistors 32 and 36 are connected to each other and further to the connection node of the drain terminals of the third pmos transistor 30 and the first nmos transistor 32 in the first complementary mos transistor circuit 26 . one npn transistor in the differential circuit 14 , e . g ., the first npn transistor 10 is connected at its base terminal to an input terminal in for receiving ecl logic signals the other npn transistor , i . e ., the second npn transistor 12 is connected at its base terminal to a base bias potential source 38 with the intermediate potential vb between the high and low potentials vdd and vee , i . e ., about -- 1 . 3 volts . further a connection node between the drain terminals of the fourth pmos transistor 34 and the second nmos transistor 36 on the second complementary mos circuit 28 is connected to an output terminal out for outputting cmos logic level signals . an operation of the first embodiment of the level conversion circuit of the present invention will now be described . when high level ecl logic signals are applied to the input terminal in , the first npn transistor 10 is rendered conductive . on the other hand , the second npn transistor 12 is rendered non - conductive . in this state , the first pmos transistor 22 becomes conductive and the second pmos transistor 24 becomes non - conductive . then , a current which is applied from the potential source 20 to the differential circuit 14 flows through a first path of the first pmos transistor 22 and the first npn transistor 10 . or the current flows from the vdd potential source 20 to the vee potential source 16 through the first path and the current source 18 . the first pmos transistor 22 operates like a resistor , since its gate terminal and drain terminal are connected to each other . the first pmos transistor 22 is so set that the equivalent resistance has a fairly large amount in the conductive state . so that , the gate terminals of the first and third pmos transistors 22 and 30 and the collector terminal of the first npn transistor 10 are rendered in a low level state near the low potential on the vee potential source 16 . the third pmos transistor 30 is then rendered conductive so that a current flows from the high potential source vdd to the ground potential through the first complementary mos circuit 32 . because the first nmos transistor 32 also operates like a resistor with a fairly large equivalent resistance similar to that of the first pmos transistor 22 , the gate terminal of the second nmos transistor 32 is rendered in a high level state near the high potential on the vdd potential source 20 . on the other hand , the second and fourth pmos transistors 24 and 34 are rendered non - conductive . therefore , a current flows from a load connected to the output terminal out to the ground potential source g through the second nmos transistor 36 . as a result , the high ecl logic level applied to the input terminal in is converted to the low cmos logic level at the output terminal out . when low level ecl logic signals are applied to the input terminal in , the first npn transistor 10 is rendered non - conductive . on the other hand , the second npn transistor 12 is rendered conductive in opposite to the former case . in this state , the first pmos transistor 22 becomes non - conductive and the second pmos transistor 24 becomes conductive . then , a current which is applied from the current source 18 to the differential circuit 14 flows through a second path of the second pmos transistor 24 and the second npn transistor 12 . or the current flows from the vdd potential source 20 to the vee potential source 16 through the second path and the current source 18 . the second pmos transistor 24 operates like a resistor with a fairly large equivalent resistance similar to the first pmos transistor 22 , since its gate terminal and drain terminal are connected to each other . so that , the gate terminals of the second and fourth pmos transistors 24 and 34 and the collector terminal of the second npn transistor 12 are rendered in a low level state near the low potential on the low potential source vee . the fourth pmos transistor 34 is then rendered conductive . on the other hand , the gate terminals of the first and third pmos transistors 22 and 30 remain in the high level state since the first npn transistor 10 is non - conductive . in this state , the gate terminal of the second nmos transistor 36 is in the low level state . thus the second nmos transistor 36 is rendered non - conductive . accordingly , a current flows from the vdd potential source 20 to the output terminal out through the fourth pmos transistor 34 in the first complementary mos circuit 26 . but the second nmos transistor 36 fails to flow any current therethrough , since the second nmos transistor 36 is in the non - conductive state . as a result , the low ecl logic level applied to the input terminal in is converted to the high cmos logic level at the output terminal out . thus , the first embodiment of the level conversion circuit according to the present invention may convert the ecl logic level signals into the cmos logic level signals with the reduced speed and the reduced power consumption . fig2 shows the level conversion characteristics of the first embodiment . in the fig2 the solid line is a simulation graph of the input ec1 logic level signal and the broken line is a simulation graph of the output cmos logic level signal . as seen from the fig2 the output cmos logic level signal has a delay time td1 of about 2 . 3 nsec . ( nano second ) when the input ec1 logic level signal changes from the high level state to the low level state and a delay time td2 of about 2 . 0 nsec . when the input ecl logic level signal changes from the low level state to the high level state . in the above , the delay times are measured by time dulations between the times the respective signals change 50 % of their amplitudes . on the other hand , in the example of conventional level conversion circuits described above , the delay times td1 and td2 were 8 . 3 nsec . and 7 . 2 nsec . thus the first embodiment of the level conversion circuit according to the present invention performs the level conversion of the ecl logic level signals into the cmos logic level signals at the higher speed , in compared to the example of conventional level conversion circuits . referring now to fig3 there is shown a second embodiment of the level conversion circuit according to the present invention . the second embodiment of the level conversion circuit includes all of the components of the level conversion circuit shown in fig1 and further includes two additional components of third and fourth nmos transistors 40 and 42 . all of the components in fig3 which are identical to those of fig1 have been designated by the same reference numerals . since the differences between fig1 and fig3 resides in the connection of the additional third and fourth nmos transistors 40 and 42 , only these connections will now be explained . the third nmos transistor 40 has its source and gate terminals both connected to the vdd potential source 20 together , and its drain terminal connected to the connection node of the gate terminals of the first and third pmos transistors 22 and 30 and the drain terminal of the first pmos transistor 22 . the fourth nmos transistor 42 also has its source and gate terminals both connected to the vdd potential source 20 together , and its drain terminal connected to the connection node of the gate terminals of the second and fourth pmos transistors 24 and 34 and the drain terminal of the first pmos transistor 24 . an operation of the second embodiment of the level conversion circuit of the present invention will now be described . the third and fourth nmos transistors 40 and 42 operate to flow currents supplied from the vdd potential source 20 to the gate terminals of the pmos transistors 22 , 24 , 30 and 34 , respectively . that is , the third nmos transistor 40 flows the current into the gate terminals of first and third pmos transistors 22 and 30 , when the first path of the diffential circuit 14 , i . e ., the first npn transistor 10 and the first pmos transistor 22 are activated by the input of the high level ecl logic signal . the fourth nmos transistor 42 flows the current into the gate terminals of second and fourth pmos transistors 24 and 34 , when the second path of the diffential circuit 14 , i . e ., the second npn transistor 12 and the second pmos transistor 24 are activated by the input of the low level ecl logic signal . due to the currents applied through the third and fourth nmos transistors 40 and 42 , the pmos transistors 22 , 24 , 30 and 34 are reduced their turn - on times , i . e ., the times that the pmos transistors change from the non - conductive state to the conductive state . according to the second embodiment of the level conversion circuit , the output cmos logic level signal has the delay time td1 of about 2 . 27 nsec . ( nano second ) when the input ec1 logic level signal changes from the high level state to the low level state and the delay time td2 of about 1 . 91 nsec . when the input ec1 logic level signal changes from the low level state to the high level state . in the above , the delay times are measured the times that the respective signals take to change 50 % of their amplitudes just as in the first embodiment . thus the second embodiment of the level conversion circuit shown in fig3 performs the level conversion of the ecl logic level signals into the cmos logic level signals at a higher speed . according to the invention , when either the p - channel mos transistor or the n - channel mos transistor which together form the output stage is in a conductive state , the other transistor becomes non - conductive state , enabling ecl logic level signals to be changed rapidly to cmos logic level signals . in addition to which the consumption of electric power involved in this changing operation is reduced . from the foregoing detailed description , it can thus be seen that the present invention provides a level conversion circuit to perform the level conversion of the ecl logic level signals into the cmos logic level signals . the level conversion circuit of the present invention has the features of reduced circuit speed , low power consumption and high input impedance . while there has been illustrated and described what are at present are believed to be preferred embodiment of the present invention , it will be understood by those skilled in the art various changes and modifications may be made , and equivalents may be substituted for elements thereof without departing from the true scope of the invention . in addition , many modifications may be made to adapt a particular situation or material to the teaching of the present invention without departing from the central scope thereof . therefore , it is intended that this invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention , but that the invention will include all embodiments following within the scope the appended claims .