embodiments depicted in the drawings in fig1 - 4 illustrate the resulting structure of the different aspects of fabricating a gate structure 101 in a metal oxide semiconductor field effect transistor ( mosfet ) 100 with the use of high density plasma ( hdp ). fig1 illustrates an exemplary embodiment of a gate structure 101 in a mosfet 100 . gate structure 101 includes gates 120 disposed on substrate 110 . gates 120 are separated by vertical space 125 formed therebetween , which may be of the same depth as gates 120 . substrate 110 includes channel 112 that divides source - drain region 114 . each gate 120 includes gate electrode 122 and spacer 124 , and is disposed directly above corresponding channel 112 and source - drain region 114 . also illustrated in fig1 is a dual - layer liner 130 which includes of a protective layer 132 and a filling layer 134 . protective layer 132 is a high density plasma ( hdp ) film deposited at a bias power of , at maximum , approximately 300 w . protective layer 132 primarily provides protection of gates 120 from damage by high power deposition of high stress films , for example , but is not limited to filling layer 134 . however , the deposition of protective layer 132 also provide bottom - up fill of vertical space 125 . filling layer 134 is also a hdp film deposited at a high bias power of approximately 1000 w to approximately 2000 w to maximize bottom - up fill of vertical space 125 . typically , the desired thickness of dual - layer liner 130 ( i . e ., the combined thickness of protective layer 132 and filling layer 134 ) may range from , but is not limited to , for example , approximately 500 å to approximately 1 300 å . the thickness of each of protective layer 132 and filling layer 134 may be varied or adjusted to achieve this desired thickness . protective layer 132 usually has a thickness ranging from approximately 100 å to approximately 200 å . filling layer 134 usually has a thickness of approximately 300 å to approximately 1200 å . the hdp films may include , but are not limited to : nitride , oxide , doped nitride or doped oxide or any combination thereof . the nitride may be doped with , but is not limited to , for example , germanium , phosphorous or boron . the deposition of dual - layer liner 130 is performed in a single deposition step , where protective layer 132 and filling layer 134 of differing properties and purposes are deposited to provide conformality and stress variation . for example , protective layer 132 may have a density range of approximately 2 . 80 g / cc to approximately 2 . 85 g / cc and filling layer 134 may have a density range of approximately 2 . 5 g / cc or less . additionally , protective layer 132 may have a reflective index that range from approximately 1 . 95 to approximately 1 . 97 , while filling layer 134 may have a reflective index of greater than approximately 1 . 89 . multiple layers 136 of dual - layer liner 130 may be formed with the single deposition step , which occurs after completion of standard processes for the formation of gates 120 following reactive - ion etching ( rie ). dual - layer liner 130 is deposited using hdp chemical vapor deposition ( cvd ) to fill any vertical space 125 between spacers 124 in a bottom - up manner from the base of gates 120 . the deposition of dual - layer liner 130 levels out the bottom of vertical space 125 and provides for subsequent plasma enhanced chemical vapor deposition ( pecvd ) of nitride layers . fig2 illustrates another exemplary embodiment of gate structure 101 in mosfet 100 where , in addition to dual - layer liner 130 , a capping layer 140 is disposed over filling layer 134 forming tri - layer film stack 160 . capping layer 140 is formed from currently known or later developed pecvd techniques . capping layer 140 is usually deposited at a power ranging from approximately 300 w to approximately 1500 w depending on the desired thickness and the reliability requirement to be met . capping layer 140 is used to make up the desired thickness of a tri - layer film stack 160 . the desired thickness of tri - layer film stack 160 is the combined thickness of dual - layer liner 130 and capping layer 140 . the desired thickness of tri - layer film stack 160 may range from , but is not limited to , for example , approximately 500 å to approximately 1300 å . the thickness of capping layer 140 may vary according to the desired thickness of tri - layer film stack 160 and the thickness of deposited dual - layer liner 130 . usually , the thickness of capping layer 140 may range from , but is not limited to , for example , approximately 100 å to approximately 1100 å . each of protective layer 132 and filling layer 134 usually has a thickness that range from , but are not limited to , for example , approximately 100 å to approximately 200 å . protective layer 132 is deposited at medium bias ( high frequency ) power of no greater than approximately 300 w in order to provide a thin hdp nitride film for filling vertical space 125 in a bottom - up manner . medium bias ( high frequency ) power is also selected to avoid damage to any low temperature oxide liner ( lto ) ( not shown ) that exist over gate structure 101 . following the deposition of protective layer 132 , filling layer 134 is deposited at high bias ( high frequency ) power ranging from approximately 1000 w to approximately 2000 w to maximize bottom - up fill of vertical space 125 . this subsequent very high bias power for depositing filling layer 134 does not damage any lto in view of the coating formed by protective layer 132 . for example , in the case of a pfet , protective layer 132 is a hdp nitride film of a thickness of approximately 150 å deposited at a bias power of approximately 300 w without damaging topography of any lto ( not shown ) that exist as part of gate structure 101 . filling layer 134 is then deposited at a high bias power of approximately 1750 w . lto ( not shown ) is not damaged in view of deposition of protective layer 132 as a coating over the lto ( not shown ). subsequent to the deposition of filling layer 134 , pecvd follows to form capping layer 140 . dual - layer liner 130 and capping layer 140 forms tri - layer film stack 160 in vertical space 125 . tri - layer film stack 160 leaves a void - free region and does not pose any difficulty for subsequent processing with rie and exhibits high uniformity in thickness . hdp nitride film maybe selected as protective layer 132 and filling layer 134 because the deposition of hdp nitride film offers a high compressive nitride with compression ranging from approximately 0 . 7 gpa to approximately 3 . 5 gpa . the high compressive nitride facilitates composite stress in tri - layer film stack 160 . furthermore , the use of hdp easily integrates into the manufacturing process just before the next standard step ( i . e ., rie ) of the process . the deposition process for forming tri - layer film stack 160 demonstrates high repeatability , where multiple layers of tri - layer film stack 166 or 176 may be formed . fig3 illustrates an alternative embodiment of gate structure 101 in mosfet 100 , where following the formation of gates 120 , deposition of a base layer 150 is performed prior to the single step deposition of dual - layer liner 130 to form a tri - layer film stack 170 . base layer 150 is a pecvd thin film formed from currently known or later developed pecvd techniques . base layer 150 usually has a thickness that may range from , but is not limited to , for example , approximately 80 å to approximately 120 å . protective layer 132 has a thickness that may range from , but is not limited to , for example , approximately 100 å to approximately 200 å . filling layer 134 has a thickness that may range from , but is not limited to , for example , approximately 200 å to approximately 1100 å . tri - layer film stack 170 formed in this embodiment is such that a pecvd thin film coats any lto ( not shown ) that exists as part of gate structure 101 . the desired thickness of tri - layer film stack 170 ( i . e ., combined thickness of base layer 150 and dual - layer liner 130 ) may range from , but is not limited to , for example , approximately 500 å to approximately 1300 å . as with the previous embodiments , once base layer 150 is formed , thickness of dual - layer liner 130 , especially filling layer 134 therein may vary to make up the thickness of tri - layer film stack 170 . in another alternative embodiment shown in fig4 , gate structure 101 in mosfet 100 includes base layer 150 , dual - layer liner 130 and capping layer 140 . base layer 150 and capping layer 140 are both deposited using currently known pecvd or later developed techniques . dual - layer liner 130 is formed using currently known or later developed hdp cvd deposition of protective layer 132 and filling layer 134 in a single deposition step . the combination of dual - layer liner 130 between base layer 150 and capping layer 140 form a quadric - layer film stack 180 . thickness of the respective layers so formed is such that base layer 150 has a thickness that may range from but is not limited to , for example , approximately 80 å to approximately 120 å . protective layer 132 has a thickness ranging from , but is not limited to , for example , approximately 0 å to approximately 100 å . filling layer 134 has a thickness that may range from , but is not limited to , for example , approximately 200 å to approximately 500 å . capping layer 140 has a thickness of approximately 0 å to approximately 500 å . the desired thickness of quadric - layer film stack 180 ( i . e ., combined thickness of base layer 150 , dual - layer liner 130 and capping layer 140 ) may range from , but is not limited to , for example , approximately 500 å to approximately 1300 å . in order to adhere to the desired thickness , once base layer 150 is deposited , protective layer 132 may be omitted or at most be of a thickness of 100 å . the thickness of filling layer 134 and capping layer 140 may vary accordingly to make up the thickness of quadric - layer film stack 180 . multiple layers of quadric - layer 186 may be formed by repeating the same deposition processes . according to the fabrication process of the various embodiments of gate structure 101 in mosfet 100 , illustrated in fig1 - 4 , the bias power applied in the hdp deposition of the nitride film is optimized to allow compatibility with various types of rie . in addition to avoiding damage to any existing lto on the gate structure 101 , the optimized bias power also provides substantial bottom - up instead of sidewall deposition unlike the fabrication process of a typical mosfet 10 ( fig5 ) in the prior art . currently proposed fabrication process of dual - layer liner 130 , illustrated in fig1 - 4 , provides a more compatible conformality with gate structure 101 , and stress that can be varied to meet channel mobility requirements of a given technology . the inclusion of base layer 150 and / or capping layer 140 , illustrated in fig2 - 4 , enhance conformality and mitigate thin sidewall deposition . furthermore , the combination of base layer 150 and / or capping layer 140 with dual - layer liner 130 form tri - layer film stack 160 and 170 or quadric - layer film stack 180 . pecvd base layer 150 and / or capping layer 140 in tri - layer film stack 160 and 170 or quadric - layer film stack 180 form a barrier against mobile ions , which may otherwise diffuse through any lto ( not shown ) disposed on gate structure 101 and impede performance . each of protective layer 132 , filling layer 134 , within dual - layer liner 130 , capping layer 140 and base layer 150 for forming tri - layer film stack 160 , 170 and / or quadric - layer 180 , may be intrinsically stressed . typically , protective layer 132 may have an intrinsic compressive stress ranging from approximately 300 mpa to approximately 3300 mpa . while filling layer 134 may have an intrinsic compressive stress ranging from approximately 2000 mpa to approximately 3300 mpa . the intrinsic compressive stress of protective layer 132 and filing layer 134 may be varied such that a desired resultant composite compressive stress of the dual - layer liner 130 is achieved . the intrinsic stress may be varied to achieve desired net composite stress / strain in a multilayer film stack over a device channel through adjustment of thickness ratio between the individual layers . a multilayer film stack may include but is not limited to , for example , dual - layer liner 130 , tri - layer film stack 160 , 170 , quadric - layer film stack 180 , multiple layers of dual - layer liner 136 , multiple layers of trip - layer film stack 166 , 176 and multiple layers of quadric - layer film stack 186 . the foregoing description of various aspects of the disclosure has been presented for purposes of illustration and description . it is not intended to be exhaustive or to limit the scope of the invention to the precise form disclosed , and obviously , many modifications and variations are possible . such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims .