the insulated - gate field effect transistor of the embodiment of the present invention having a contact hole formed in an inter - layer insulating film on an s / d region adjacent to a gate electrode is described below by referring to fig3 a to fig3 h , fig4 a to fig4 e , fig5 and fig6 . the insulated - gate field effect transistor uses an insulated - gate field effect transistor having a floating gate in an eprom cell . fig3 a shows a state after an s / d region is formed in the surface layer of a semiconductor substrate of the both sides of a gate electrode having a floating gate and control gate . in fig3 a , symbol 11 is a semiconductor substrate made of silicon and 12 is a gate insulating film made of a silicon dioxide film formed on the semiconductor substrate 11 . symbol 13 is a gate electrode , comprising a floating gate 13 a and control gate 13 c formed above a floating 13 a in the state of putting an insulating film 13 b between them . the floating gate 13 a and control gate 13 c are made of polycrystalline silicon and the insulating film 13 b is made of a silicon dioxide film . symbol 14 is an insulating film on the control gate 13 c . 15 a and 15 b are s / d regions formed in the surface layer of the semiconductor substrate 11 of both sides of the gate electrode 13 . a plurality of insulated - gate field effect transistors are formed in an eprom . therefore , as shown in fig4 a , floating gates 13 a , 13 d , 13 e , 13 g , 13 h , and 13 j are formed separately from each other for each insulated - gate field effect transistor . the floating gates 13 a and 13 d are covered with a strip - shaped control gate 13 c common to them , the floating gates 13 e and 13 g are covered with a strip - shaped control gate 13 f common to them and the floating gates 13 h and 13 j are covered with a strip - shaped control gate 13 i common to them . the control gates 13 c , 13 f , and 13 i are arranged in parallel at predetermined intervals and connected to a word line . moreover , s / d regions 15 a to 15 d are formed in the surface layer of the semiconductor substrate 11 between the control gates 13 c , 13 f and 13 i and at that of both sides of the floating gates 13 a , 13 d , 13 e , 13 g , 13 h and 13 j . however , the s / d region of another side of the floating gates 13 e , 13 g , 13 h , and 13 j is not illustrated . in this case , a region between the control gates 13 c and 13 f is called such a side that a contact hole is formed where a contact hole is formed on the s / d regions 15 a and 15 c , while a region between the control gates 13 c and 13 i is called such an other side that a contact hole is not formed where a bulk interconnection layer for electrically connecting the s / d regions 15 b and 15 d with each other is formed in the surface layer of the semiconductor substrate 11 . the s / d region 15 a serves as a source or drain region common to adjacent insulated - gate field effect transistors having the floating gates 3 a and 13 e . the s / d region 15 b serves as a drain or source region common to adjacent insulated - gate field effect transistors having the floating gates 3 a and 13 h . the s / d region 15 c serves as a source or drain region common to adjacent insulated - gate field effect transistors having the floating gates 13 d and 13 g . the s / d region 15 d serves as a drain or source region common to adjacent insulated - gate field effect transistors having the floating gates 13 d and 13 j . first , to form insulating side walls 16 a to 16 d along the side surfaces of the control gates 13 c , 13 f , and 13 i shown in fig4 a under the above state , an insulating film 16 made of a silicon dioxide film with the thickness of 3 , 000 - 4 , 000 å on the entire surface of the semiconductor substrate 11 . fig3 b shows a sectional view of the film 16 taken along the line a — a in fig4 a . then , as shown in fig3 c , the insulating side wall 16 a is formed on the side surface of the gate electrode 13 by anisotropically etching the insulating film 16 by means of the reactive ion etching ( hereinafter referred to as rie ) using a fluorine - based gas such as hf . in this case , as shown in fig4 b , the insulating side walls 16 a to 16 d are formed along the side surfaces of the control gates 13 c , . 13 f , and 13 i . next , as shown in fig3 d , a polycrystalline silicon film ( conducting film ) 17 is formed on the entire surface and thereafter the polycrystalline silicon film 17 is anisotropically etched by rie using a chlorine - base gas . thereby , as shown in fig4 b , polycrystalline silicon films ( conducting side walls ) 17 a to 17 d respectively covering the side surfaces of the insulating side walls 16 a to 16 d and respectively contacting the semiconductor substrate 11 are left . subsequently , a resist film is formed and thereafter a window 20 of the resist film is patterned so that the conducting side walls 17 a and 17 c in a region between the s / d regions 15 a and 15 c of the side for forming a contact hole are exposed . next , as shown in fig4 c , the conducting side walls 17 a and 17 c are selectively etched through the window 20 and partly removed . thereby , the conducting side walls 17 a and 17 c are electrically separated for each transistor so that the conducting side walls 17 e and 17 f contacting the s / d region 15 a and the side walls 17 g and 17 h contacting the s / d region 15 c are left . then , after the resist film is removed , as shown in fig4 d , the side for forming a contact hole is masked with a not - illustrated new resist film to remove a natural oxide film from the surface of the semiconductor substrate 11 of the other side . subsequently , conductivity - type impurities same as those in the s / d regions 15 b and 15 d are introduced into the region to form a bulk interconnection layer in the surface layer of the semiconductor substrate 11 and electrically connect the s / d regions 15 b and 15 d of the other side each other . in this case , the conducting side walls 17 b and 17 d serve as masks for removing a natural oxide film and introducing impurities . moreover , the bulk interconnection layer serves as a source line 21 . fig3 e shows a sectional view taken along the line a — a in fig4 d and fig4 e shows a sectional view taken along the line b — b in fig4 d . after that , as shown in fig3 f , an inter - layer insulating film 18 is formed on the entire surface . then , as shown in fig3 g , the inter - layer insulating film 18 on the s / d region 15 a is selectively etched and removed by a fluorine - base etching gas to form a contact hole 18 a in the inter - layer insulating film 18 on the s / d region 15 a . in this case , a contact hole 18 b is also formed on the s / d region 15 c shown in fig4 d at the same time . next , as shown in fig3 h , an aluminum film is formed and thereafter patterned to form an s / d electrode or interconnection layer 19 connecting with the s / d regions 15 a and 15 c through the contact holes 18 a and 18 b . in this case , an s / d electrode or interconnection layer connecting with the s / d region 15 c through the contact hole 18 b shown in fig4 c is formed at the same time . then , an eprom having the connection shown in fig5 is completed after predetermined steps . in fig5 symbol 21 is a source line where sources of a desired transistor are connected each other and connected to a power - supply line vs . symbol 22 is a word line which is connected with the control gate electrode 13 c . symbol 23 is a bit line which is connected with the drain of each transistor . symbol 24 is a row decoder for sending an address signal to the control gate 13 c of a desired transistor through each word line 22 and 25 is a column decoder for sending an address signal to the drain of a desired transistor through each bit line 23 . as described above , the embodiment of the present invention has the conducting side wall 17 e covering the insulating side wall 16 a of the side where the contact hole 18 a is formed and also contacting with the s / d region 15 a . therefore , when forming the contact hole 18 a in the inter - layer insulating film 18 covering them , the contact hole 18 a is formed on the conducting side wall 17 e even if the contact hole 18 a approaches the gate electrode 13 due to a deviation of an alignment as shown in fig6 . in this case , the insulating side wall 16 a between the gate electrode 13 and conducting side wall 17 e is not exposed to an etchant for forming the contact hole 18 a in the inter - layer insulating film 18 because the insulating side wall 16 a is covered with the conducting side wall 17 e . therefore , the insulating side wall 16 a keeps the initial thickness . when the s / d electrode or interconnection layer 19 is formed in the contact hole 18 a under the above state , only the insulating side wall 16 a remains as an insulating film actually present between the s / d electrode or interconnection layer 19 and the gate electrode 13 because the s / d electrode or interconnection layer 19 contacts the conducting side wall 17 e . accordingly , its thickness is kept constant independently of the position of the contact hole . in case that the contact hole 18 a goes away from the gate electrode , the conducting side wall 17 e is covered with the inter - layer insulating film 18 a and the s / d electrode or interconnection layer 19 formed in the contact hole 18 b does not contact the conducting side wall 17 e as shown in fig3 e . even in this case , as both the conducting side wall 17 e and s / d electrode or interconnection layer 19 contact the s / d region , the conducting side wall 17 e and the s / d electrode or interconnection layer 19 have the same potential , so that only the insulating side wall 16 a remains as an insulating film actually present between the s / d electrode or interconnection layer 19 and the gate electrode 13 . accordingly , its thickness is kept constant independently of the position of the contact hole as shown in fig3 h . therefore , it is possible to prevent parasitic capacitances from fluctuating or accumulated charges from fluctuating due to leakage of them . moreover , when forming the source line 21 by selectively introducing conductivity - type impurities same as those of the s / d regions 15 b and 15 d into the semiconductor substrate 11 of the other side that a contact hole is not formed , as shown in fig4 d and fig4 e , the conducting side wall 17 b on the side surface of the control gate 13 c is left at the other side and serves as a mask for removing a natural oxide film and introducing impurities while the semiconductor substrate 11 is masked with a not - illustrated new resist film of the side for forming a contact hole . thus , the allowance for mask alignment increases by the width of the polycrystalline silicon film 17 b so that a patterning of a mask is easy . moreover , a sufficient space between a channel region under the gate electrode and a bulk interconnection layer is secured so that preventing a channel length from becoming short and a gate control voltage from fluctuating . for this embodiment , the polycrystalline silicon film 17 is used for the material of the conducting side wall . however , it is also possible to use other type of conducting side wall such as a refractory metal film or refractory metal silicide film . as shown in fig3 a , the present invention is applied to an insulated - gate field effect transistor having the gate electrode 13 which comprises the floating gate 3 a and control gate 13 c above the floating gate 3 a . however , the present invention can also be applied to an insulated - gate field effect transistor having a gate electrode which comprises only one layer . moreover , it is possible to replace the step of patterning the polycrystalline silicon film 17 a shown in fig4 c with the step of introducing conductivity - type impurities into the semiconductor substrate 11 shown in fig4 d .