referring now to the drawings , the details of specific example embodiments are schematically illustrated . like elements in the drawings will be represented by like numbers , and similar elements will be represented by like numbers with a different lower case letter suffix . referring to fig1 , depicted is a schematic block diagram of a device having a single digital - to - analog conversion ( dac ) capability and non - volatile memory , according to a specific example embodiment of this disclosure . the device , generally represented by the numeral 100 , may comprise a serial interface and address logic 102 , an input register 104 , a dac register 106 , a digital - to - analog converter ( dac ) 108 , power - down control 110 , an analog amplifier 112 , a non - volatile memory 114 , a charge pump 116 , and a power - on - reset ( por ) circuit 118 . the non - volatile memory 114 may be , but is not limited to , an electrically erasable and programmable read only memory ( eeprom ), flash memory , etc . for example , the non - volatile memory 114 may be used to store configuration register , dac input data ( e . g ., 12 bits of a digital representation of the analog voltage that the dac 108 is supposed to produce ), address bits ( e . g ., 3 bits for i 2 c address ) and test mode trim bits . the charge pump 116 may be used for writing to the non - volatile memory 114 . power may be supplied to the device 100 at voltage terminals vdd and vss . the serial interface and address logic 102 is coupled to a serial data bus 120 of n - bit width , e . g ., n = 1 , 2 , 3 , etc . configuration and data values may be written to or read from the non - volatile memory 114 and / or the input register 104 . the serial interface and address logic 102 determines whether the device 100 is being addressed by a bus master ( not shown ) over the serial bus 120 . a specific programmable device address allows specific operation and selection from a number of devices 100 . the device address is written to and stored in the non - volatile memory 114 so that a specific device address is maintained even when the device 100 has power removed therefrom . the dac output register 106 may be loaded from the input register 104 . also , the contents of the non - volatile memory 114 may be transferred to the input register 104 . a load dac output register input 122 may be used to ( a ) transfer the contents of the input register ( s ) 104 to the respective dac output register ( s ) 106 , ( b ) select a device 100 of interest in read / write address bit commands , and ( c ) enter test mode . when there is a logic transition on the input 122 , the contents of the input register ( s ) 104 may be loaded into the dac output register ( s ) 108 , thus generating a new analog voltage at the output of the analog amplifier 112 ( vout ). for selection of a device 100 of interest , a logic transition on the input 122 at a certain time during a command may be used to either read a device address or write a new device address into the selected device 100 . using the input 122 in this way allows determining the address programmed into a specific device 100 and also being able to change a specific device address when the device 100 is in an end use system without requiring removal of the device 100 and / or special test fixtures . to enter a device test mode , a higher then normal voltage , e . g ., 10 volts , may be applied to the input 122 . a ready / busy output 124 may be used to indicate when a write operation to the non - volatile memory 114 is completed . referring to fig2 , depicted is a schematic block diagram of a device having a plurality of channels with digital - to - analog conversion capabilities and non - volatile memories , according to another specific example embodiment of this disclosure . the device , generally represented by the numeral 200 , may comprise a serial interface and logic 102 , a plurality of input registers 104 , a plurality of dac registers 106 , a plurality of digital - to - analog converters ( dac ) 108 , a plurality of analog amplifiers 112 , a non - volatile memory 114 , and a charge pump 116 . power - on - reset ( por ) circuit 118 ( fig1 ), power - down control 110 ( fig1 ), an internal voltage reference and voltage reference value selection circuit are not shown but may also be part of the devices 100 and / or 200 . four adc channels are shown but it is contemplated and within the scope of this disclosure that any number of adc channels may be utilized in combination with the teachings of this disclosure . the non - volatile memory 114 may be , but is not limited to , electrically erasable and programmable read only memory ( eeprom ), flash memory , etc . for example , the non - volatile memory 114 may be used to store configuration register , dac input data ( e . g ., 12 bits of a digital representation of the analog voltage that the dac 108 is supposed to produce ), address bits ( e . g ., 3 bits for i 2 c address ) and test mode trim bits . the charge pump 116 may be used for writing to the non - volatile memory 114 . power may be supplied to the device 100 at voltage terminals vdd and vss . the serial interface and logic 102 may have an input (/ ldac ) for transferring dac settings from serial input latches to output latches , e . g ., dac registers 106 . the serial interface and logic 102 is coupled to a serial data bus of n - bit width , e . g ., n = 1 , 2 , 3 , etc . configuration and data values may be written to or read from the non - volatile memory 114 and / or the input registers 104 . the dac registers 106 may be loaded from the respective input registers 104 . also the contents of the non - volatile memory 114 may be transferred to the respective input registers 104 . the load dac output register input 122 and the ready / busy output 124 function as described hereinabove . a normal mode of the device allows user commands to write to and read from the device dac registers and non - volatile memory during normal operational thereof . referring to fig3 , depicted is a schematic byte diagram of an address , command and data protocol structure for fast mode sequentially writing to dac input register ( s ). the fast mode write command is comprised of a plurality of bytes 300 and may support , for example but is not limited to , 7 - bit slave addressing . the slave address may contain a device code 304 comprising four fixed identification bits ( e . g ., 1100 b ) and three address 306 bits ( a 2 , a 1 , a 0 ) used to select one of up to eight ( 8 ) devices . the device code 304 may be preprogrammed during manufacture , and unique address bits 306 may be programmed into the device 100 or 200 for a specific application as more fully described hereinbelow . the fast mode write command shown in fig3 begins with a start bit 302 followed by a plurality of bytes 300 ( 8 bits each ), each byte 300 is followed by a device ( slave ) acknowledge 310 , and terminating with a stop bit 320 . for this fast write command only the write command bits 312 ( c 2 = 0 and c 1 = 0 ) are used . in subsequent bytes 300 the c2 and c1 bits are ignored , c 2 , c 1 = x ( where x is a don &# 39 ; t care ). the fast mode write command is used to sequentially update the input register ( s ) 104 . the power down selection bits ( pd 1 , pd 0 ) 314 and the 12 bits of dac input data bits ( d 11 - d 0 ) 316 and 318 are sequentially updated for each dac channel ( bytes for three dac channels are shown in fig3 , bytes 300 f and 300 g would repeat for a fourth dac channel ). data in the non - volatile memory 114 is not changed by the fast write command shown in fig3 . the fast mode write command writes only the power - down selection bits 314 ( pd 1 and pd 0 ) of the configuration register , and 12 bits ( d 11 : d 0 ) of dac input data 316 and 318 of each dac channel . the write data is loaded sequentially from the first channel to the last channel of the device . each of the dac input registers 104 are updated ( written ) at the acknowledge pulse of that channel &# 39 ; s last input data byte . once the dac input registers 104 are loaded , the dac registers 106 and vout from each of the amplifiers 112 are updated at any time by changing the logic level at the load dac output register input 122 (/ ldac ). non - volatile memory 114 is not affected . referring to fig4 , depicted is a schematic byte diagram of an address , command and data protocol structure for writing one dac input register at a time . the multiple write command is comprised of a plurality of bytes 400 and may support , for example but is not limited to , 7 - bit slave addressing . the slave address may contain a device code 404 comprising four fixed identification bits ( e . g ., 1100 b ) and three address bits 406 ( a 2 , a 1 , a 0 ) used to select one of one of up to eight ( 8 ) devices . the device code 404 may be preprogrammed during manufacture , and unique address bits 406 may be programmed into the non - volatile memory 114 of the device memory 100 or 200 for a specific application as more fully described hereinbelow . the multiple write command shown in fig4 begins with a start bit 402 , followed by a plurality of bytes 400 ( 8 bits each ), each byte 400 is followed by a device ( slave ) acknowledge 410 , and terminates with a stop bit 420 . a first byte comprises a device code 404 , a device address 406 ( a 2 , a 1 , a 0 ) and a read / write bit 408 set to zero . a second byte 400 b comprises write command type bits 412 ( c 2 = 0 , c 1 = 1 and c 0 = 0 ), write function bits 428 ( w 1 = 0 and w 0 = 0 ), dac channel selection bits 426 a ( dac 1 and dac 0 ), and / udac bit 430 a . the multiple write command writes to one dac input register 104 at a time . the dac channel may be selected by using the dac register selection bits 426 ( dac 1 and dac 0 ), and only that channel is affected . more than one dac register 106 may be written to by sending repeat bytes , e . g ., bytes 400 e , 400 f and 400 g , with the respective dac register selection bits 426 for each dac channel to be updated . data in the non - volatile memory 114 is not changed by the fast write command shown in fig4 . a third byte 400 c comprises configuration bits : vref bit 432 , power down selection bits 414 a ( pd 1 and pd 0 ), dac gain selection bit 440 a ( gx ) and the four most significant dac data bits 422 a ( d 11 : d 8 ). a fourth byte 400 d comprises the least significant dac data bits 424 a ( d 7 : d 0 ). the configuration register bits : vref bit 432 a , power down selection bits 414 a ( pd 1 and pd 0 ) and dac gain selection bit 440 a ( gx ); and dac input data bits ( d 11 - d 0 ) 422 a and 424 a may be updated after the fourth byte 400 d acknowledge 410 d if the logic level at the load dac output register input 122 (/ ldac ) is low or / udac bit 430 is cleared . vout from the respective amplifier 112 may be updated using the / udac bit 430 , a logic change at the dac output register input 122 (/ ldac ), or through a general call software update . when / udac bit 430 is at a first logic level , the vout of the selected dac channel is updated as soon as the fourth byte 400 d is acknowledged 410 d ( the last byte of the selected dac register ) regardless of the logic state of the dac output register input 122 (/ ldac ). the dac input data bits ( d 11 - d 0 ) 422 and 424 are the dac input data of the selected dac channel ( bits 426 ). bytes 400 b , 400 c and 400 d are repeated for each of the next dac channels to be updated but without the need for specifying the write command type bits 412 a ( c 2 , c 1 and c 0 ) and write function bits 428 a ( w 1 and w 0 ), x = don &# 39 ; t care . for example , bytes 400 e , 400 f and 400 g represent the update data necessary for a second dac channel . subsequent dac channels may be similarly updated . the information contained in the second , third and fourth bytes described above may be repeated for each dac channel . write command protocols for two instances of dac channels are shown , however , write protocols for any number of dac channels are contemplated herein ( e . g ., fig2 ) and / or repeated for each one of the dac channels until the stop bit 420 terminates the write command protocol . referring to fig5 , depicted is a schematic byte diagram of an address , command and data protocol structure for sequentially writing to dac input registers and associated non - volatile memory locations . the sequential write command is comprised of a plurality of bytes 500 and may support , for example but is not limited to , 7 - bit slave addressing . the slave address may contain a device code 504 comprising four fixed identification bits ( e . g ., 1100 b ) and three address bits 506 ( a 2 , a 1 , a 0 ) used to select one of one of up to eight ( 8 ) devices . the device code 504 may be preprogrammed during manufacture , and unique address bits 506 may be programmed into the device 100 or 200 for a specific application as more fully described hereinbelow . the sequential write command shown in fig5 begins with a start bit 502 , followed by a plurality of bytes 500 ( 8 bits each ), each byte 500 is followed by a device ( slave ) acknowledge 510 , and terminates with a stop bit 520 . a first byte 500 a comprises a device code 504 , a device address 506 ( a 2 , a 1 , a 0 ) and a read / write bit 508 set to zero . a second byte 500 b comprises write command type bits 512 ( c 2 = 0 , c 1 = 1 and c 0 = 0 ), write function bits 528 ( w 1 = 1 and w 0 = 0 ), dac channel selection bits 526 ( dac 1 and dac 0 ), and / udac bit 530 . the sequential write command writes the configuration register bits : vref bit 532 , power down selection bits 514 ( pd 1 and pd 0 ), dac gain selection bit 540 ( gx ), and dac input data bits ( d 11 - d 0 ) 522 and 524 to the dac input registers 104 sequentially from the starting dac channel to the last dac channel , and this command also writes the same data sequentially to the non - volatile memory 114 . the starting dac channel is determined by the dac register selection bits 526 ( dac 1 and dac 0 ) in byte 500 b . subsequent dac channels are written after the completion of each respective byte pair , e . g ., bytes 500 e and 500 f for a second dac channel . additional dac channels are just repeats of byte pairs up to the maximum number of dac channels of the device 200 . when writing to the non - volatile memory 114 , the ready / busy output 124 ( fig1 and 2 ) remains at a first logic level until the write operation to the non - volatile memory 114 is completed . the ready / busy output 124 then returns to a second logic level . the ready / busy output 124 may be monitored by system software so as not to attempt a write operation to the non - volatile memory when the ready / busy output 124 is at the first logic level . any command received when the ready / busy output 124 is at the first logic level will be ignored . referring to fig6 , depicted is a schematic byte diagram of an address , command and data protocol structure for writing to a single dac input register and associated non - volatile memory locations . the single write command is comprised of a plurality of bytes 600 and may support , for example but is not limited to , 7 - bit slave addressing . the slave address may contain a device code 604 comprising four fixed identification bits ( e . g ., 1100 b ) and three address bits 606 ( a 2 , a 1 , a 0 ) used to select one of one of up to eight ( 8 ) devices . the device code 604 may be preprogrammed during manufacture , and unique address bits 606 may be programmed into the device 100 or 200 for a specific application as more fully described hereinbelow . the single write command shown in fig6 begins with a start bit 602 , followed by a plurality of bytes 600 ( 8 bits each ), each byte 600 is followed by a device ( slave ) acknowledge 610 , and terminates with a stop bit 620 . a first byte comprises a device code 604 , a device address 606 ( a 2 , a 1 , a 0 ) and a read / write bit 608 set to zero . a second byte 600 b comprises write command type bits 612 ( c 2 = 0 , c 1 = 1 and c 0 = 0 ), write function bits 528 ( w 1 = 1 and w 0 = 1 ), dac channel selection bits 626 ( dac 1 and dac 0 ), and / udac bit 630 . the single write command writes the configuration register bits : vref bit 632 , power down selection bits 614 ( pd 1 and pd 0 ) and dac gain selection bit 640 ( gx ), and the dac input data bits ( d 11 - d 0 ) 622 and 624 to the dac input register 104 for the dac channel specified by the dac channel selection bits 626 ( dac 1 and dac 0 ), and also writes the same information into associated locations in the non - volatile memory 114 . referring to fig7 , depicted is a schematic byte diagram of an address , command and data protocol structure for writing a new address into the device . the writing a new address command is comprised of a plurality of bytes 700 and may support , for example but is not limited to , 7 - bit slave addressing . the slave address may contain a device code 704 comprising four fixed identification bits ( e . g ., 1100 b ) and three address bits 706 ( a 2 , a 1 , a 0 ) used to select one of up to eight ( 8 ) devices . the device code 704 may be preprogrammed during manufacture , and unique address bits 706 are programmed into the device 100 or 200 . when the device receives the new address command , the current address contained in the three address bits 706 ( a 2 , a 1 , a 0 ) are replaced by overwriting these address bits in both the device register ( s ) and the associated locations of the non - volatile memory 114 . the writing of a new address command shown in fig7 begins with a start bit 702 , followed by a plurality of bytes 700 ( 8 bits each ), each byte 700 is followed by a device ( slave ) acknowledge 710 , and terminates with a stop bit 720 . a first byte comprises a device code 704 , a device address 706 a ( a 2 , a 1 , a 0 ) and a read / write bit 708 set to zero . a second byte 700 b comprises write command type bits 712 a ( c 2 = 0 , c 1 = 1 and c 0 = 1 ), the current device address 706 b ( a 2 , a 1 , a 0 ), and a first bit pattern 754 ( 0 , 1 ). a third byte 700 c comprises write command type bits 712 b ( c 2 = 0 , c 1 = 1 and c 0 = 1 ), the new device address 756 a ( a 2 , a 1 , a 0 ), and a second bit pattern 758 ( 1 , 0 ). a fourth byte 700 d comprises write command type bits 712 c ( c 2 = 0 , c 1 = 1 and c 0 = 1 ), the new device address 756 b ( a 2 , a 1 , a 0 ) as confirmation , and a third bit pattern 762 ( 1 , 1 ). the writing of a new address command is only valid if there is a logic level transition at the load dac output register input 122 (/ ldac ) during the slave acknowledge 710 b of the second byte 700 b , and the logic level at the input 122 remains in its new state for at least the end of the third byte 700 c . the load dac output register input 122 (/ ldac ) may be used to select a device when programming a new address therein . referring to fig8 , depicted is a schematic byte diagram of an address , command and data protocol structure for changing selection of a voltage reference . the change voltage reference selection command is comprised of bytes 800 a and 800 b , and may support , for example but is not limited to , 7 - bit slave addressing . the slave address may contain a device code 804 comprising four fixed identification bits ( e . g ., 1100 b ) and three address bits 806 ( a 2 , a 1 , a 0 ) used to select one of one of up to eight ( 8 ) devices . the device code 804 may be preprogrammed during manufacture , and unique address bits 806 are field programmable as described herein . the change voltage reference select bits command shown in fig8 begins with a start bit 802 , followed by bytes 800 a and 800 b ( 8 bits each ), each byte 800 is followed by a device ( slave ) acknowledge 810 , and terminates with a stop bit 820 . a first byte 800 a comprises a device code 804 , a device address 806 ( a 2 , a 1 , a 0 ) and a read / write bit 808 set to zero . a second byte 800 b comprises write command type bits 812 ( c 2 = 1 , c 1 = 0 and c 0 = 0 ), and dac reference selection bits 870 . each of the dac reference selection bits 870 may be used to select between either vdd or vref ( internal or external , not shown ) for its respective dac channel , e . g ., vdd when the dac reference selection bit 870 is at a first logic level or vref when at a second logic level . non - volatile memory 114 is not affected by this command . referring to fig9 , depicted is a schematic byte diagram of an address , command and data protocol structure for writing power - down selection bits into the dac input registers . the write power - down select bits command is comprised of bytes 900 a , 900 b and 900 c , and may support , for example but is not limited to , 7 - bit slave addressing . the slave address may contain a device code 904 comprising four fixed identification bits ( e . g ., 1100 b ) and three address bits 906 ( a 2 , a 1 , a 0 ) used to select one of one of up to eight ( 8 ) devices . the device code 904 may be preprogrammed during manufacture , and unique address bits 906 are field programmable as described herein . the write power - down select bits command is used to select either a normal or power down mode for each of the dac channels . two power - down bits 980 ( pd 1 , pd 0 ) are used for each of the dac channels , e . g ., dac channels a , b , c and d . when a normal mode is selected for a dac channel , there will an analog voltage output . when a power down mode is selected , there will be no analog voltage output , instead a fixed resistance value to ground or common will be substituted depending upon the logic values of the two power - down bits 980 ( pd 1 , pd 0 ). the write power - down select bits command shown in fig9 begins with a start bit 902 , followed by bytes 900 a , 900 b and 900 c ( 8 bits each ), each byte 900 is followed by a device ( slave ) acknowledge 910 , and terminates with a stop bit 920 . a first byte 900 a comprises a device code 904 , a device address 906 ( a 2 , a 1 , a 0 ) and a read / write bit 508 set to zero . a second byte 900 b comprises write command type bits 812 ( c 2 = 1 , c 1 = 0 and c 0 = 1 ), and power - down bits 980 a and 980 b . a third byte 900 c may comprise power - down bits 980 c and 980 d if those dac channels are implemented in the device 200 . non - volatile memory 114 is not affected by this command . referring to fig1 , depicted is a schematic byte diagram of an address , command and data protocol structure for writing gain selection bits to the dac input registers . the write gain selection bits to the dac input registers command is comprised of bytes 1000 a and 1000 b , and may support , for example but is not limited to , 7 - bit slave addressing . the slave address may contain a device code 1004 comprising four fixed identification bits ( e . g ., 1100 b ) and three address bits 1006 ( a 2 , a 1 , a 0 ) used to select one of one of up to eight ( 8 ) devices . the device code 1004 may be preprogrammed during manufacture , and unique address bits 1006 are field programmable as described herein . the write gain selection bits to the dac input registers command begins with a start bit 1002 , followed by bytes 1000 a and 1000 b ( 8 bits each ), each byte 1000 is followed by a device ( slave ) acknowledge 1010 , and terminates with a stop bit 1020 . a first byte 1000 a comprises a device code 1004 , a device address 1006 ( a 2 , a 1 , a 0 ) and a read / write bit 1008 set to zero . a second byte 1000 b comprises write command type bits 1012 ( c 2 = 1 , c 1 = 1 and c 0 = 0 ), and gain selection bits 1040 . each of the gain selection bits 1040 may be used to select the gain for its respective dac channel , e . g ., gain of one when the gain selection bit 1040 is at a first logic level or gain of two when at a second logic level . non - volatile memory 114 is not affected by this command . if the read / write bit ( x 08 ) in the first byte of each command is set to a logic “ high ” ( 1 ), then the device enters a read mode . there are two types of read modes : ( a ) normal read mode for reading register data , and ( b ) test mode read for accessing lock and trim bits . the test mode read may be entered into by asserting a high voltage on the load dac output register input 122 (/ ldac ). the read command executes only when the ready / busy output 124 indicates that the non - volatile memory 114 is not busy . referring to fig1 a - 11 d , depicted are schematic byte diagrams of an address , command and data protocol structures for reading in normal mode the dac input register and non - volatile memory of one or more dac devices . referring now to fig1 a , the read command in normal mode begins with a start bit 1102 followed by a first byte 1100 a sent by the bus master , e . g ., a digital processor ( not shown ), wherein the first byte 1100 a comprises a device code 1104 having four fixed identification bits ( e . g ., 1100 b ), three address bits 1106 ( a 2 , a 1 , a 0 ) used to select one of one of up to eight ( 8 ) devices , and a read / write bit 1108 ( set to logic 1 indicating a read operation ). once the first byte of this read command from the bus master is finished , a slave acknowledge 1110 a is asserted . the device code 1104 may be preprogrammed during manufacture , and unique address bits 1106 are field programmable as described herein . next a first slave byte 1150 a is sent by the slave device . the first slave byte 1150 a comprises the present status of the following data contained in the dac register 106 of dac channel a ( fig2 ): a ready / busy bit 1146 a that indicates the completion status of a write to the non - volatile memory 114 ( e . g ., logic 1 indicates write complete , logic 0 indicates otherwise ), the present status of the associated power - on - reset bit 1148 a , the dac channel indicated in the selection bits 1126 a ( dac 1 , dac 0 ), a zero ( 0 ), and the three address bits 1106 a ( a 2 , a 1 , a 0 ) of the device . after the first slave byte 1150 a has been read by the bus master , the bus master sends a master acknowledge 1160 a . after the slave device receives the master acknowledge 1160 a , a second slave byte 1150 b is sent by the slave device . the second slave byte 1150 b comprises the following data contained in the dac register 106 of dac channel a ( fig2 ): vref 1132 a status , power down selection bits 1114 a ( pd 1 and pd 0 ) status , the dac gain selection bit 1140 a ( gx ) status , and the four most significant dac data bits 1122 a ( d 11 : d 8 ) associated with the dac channel indicated in the selection bits 1126 a . after the second slave byte 1150 b has been read by the bus master , the bus master sends a master acknowledge 1160 b . after the slave device receives the master acknowledge 1160 b , a third slave byte 1150 c is sent by the slave device . the third slave byte 1150 c comprises the eight ( 8 ) least significant data bits 1124 a ( d 7 : d 0 ) contained in the dac register 106 associated with the dac channel indicated in the selection bits 1126 a . bytes 1150 a - 1150 c comprise the present contents of the dac register of the indicated dac channel 1126 a ( dac 1 , dac 0 ). after the third slave byte 1150 c has been read by the bus master , the bus master sends a master acknowledge 1160 c . then the addressed slave device sends a fourth slave byte 1150 d indicating the present status of the data contents contained in the non - volatile memory 114 . the fourth slave byte 1150 d comprises a ready / busy bit 1196 a that indicates the completion status of a write to the non - volatile memory 114 ( e . g ., logic 1 indicates write complete , logic 0 indicates otherwise ), the present status of the associated power - on - reset bit 1198 a , the dac channel indicated in the selection bits 1176 a ( dac 1 , dac 0 ), a zero ( 0 ), and the three address bits 1156 b ( a 2 , a 1 , a 0 ). after the fourth slave byte 1150 d has been read by the bus master , the bus master sends a master acknowledge 1160 d . after the slave device receives the master acknowledge 1160 d , a fifth slave byte 1150 e is sent by the slave device . the fifth slave byte 1150 e comprises the following data contained in the non - volatile memory 114 : vref 1182 a status , power down selection bits 1164 a ( pd 1 and pd 0 ) status , the dac gain selection bit 1190 a ( gx ) status , and the four most significant dac data bits 1172 a ( d 11 : d 8 ) associated with the dac channel indicated in the selection bits 1176 a . after the fifth slave byte 1150 e has been read by the bus master , the bus master sends a master acknowledge 1160 e . after the slave device receives the master acknowledge 1160 e , a sixth slave byte 1150 f is sent by the slave device . the sixth slave byte 1150 f comprises the eight ( 8 ) least significant data bits 1174 a ( d 7 : d 0 ) contained in the non - volatile memory 114 associated with the dac channel indicated in the selection bits 1176 a . bytes 1150 d - 1150 f comprise the present contents of the non - volatile memory 114 of the indicated dac channel 1176 a ( dac 1 , dac 0 ). after the sixth slave byte 1150 f has been read by the bus master , the bus master sends a master acknowledge 1160 f , and a stop bit 1120 a is asserted on the serial bus 120 . fig1 b shows the seventh ( 7th ) through the twelfth ( 12th ) slave bytes 1150 g - 1150 l that may be used to supply all of the previously mentioned status and data for the next dac channel b ( fig2 ). fig1 c shows the thirteenth ( 13th ) through the eighteenth ( 18th ) slave bytes 1150 m - 1150 r that may be used to supply all of the previously mentioned status and data for the next dac channel c ( fig2 ), if used . fig1 d shows the nineteenth ( 19th ) through the twenty - third ( 23rd ) slave bytes 1150 s - 1150 x that may be used to supply all of the previously mentioned respective status and data for the next dac channel d ( fig2 ), if used . a stop bit 1120 is asserted by the bus master ( not shown ) after the completion of reading the information for each subsequent dac register 106 and associated non - volatile memory 114 . this reading in normal mode command will terminate with a stop bit 1120 after the last dac channel is read . the repeat byte can start after sequentially reading all of the dac registers and non - volatile memory . a test mode of the device may entered into when the device receives a “ read / write command for test mode ” while a high voltage , e . g ., about 10 volts , is applied to the load dac output register input 122 (/ ldac ). no specific device address is required since only the device under test will have a high voltage at its input 122 . referring to fig1 , depicted is a schematic byte diagram of a test mode address , command and data protocol structure for writing a lock bit to the dac input registers . the write lock bit command is comprised of bytes 1200 a and 1200 b , and begins with a start bit 1202 , followed by bytes 1200 a and 1200 b ( 8 bits each ), each byte 1200 is followed by a device ( slave ) acknowledge 1210 , and terminates with a stop bit 1220 . a first byte 1200 a comprises a device code 1204 , and a read / write bit 1208 set to zero . a second byte 1200 b comprises write command type bits 1212 ( c 2 = 0 , c 1 = 1 and c 0 = 0 ), and lock bit 1244 . non - volatile memory 114 is not affected by this command . the lock bit 1244 may be cleared and set by the write lock bit command . the lock bit 1244 prevents unauthorized modification of the contents of the non - volatile memories 114 of the dac devices 100 and 200 . a write command in test mode may be executed when the lock bit 1244 is at a first logic level , e . g ., logic 0 , and locked from execution when at a second logic level , e . g ., logic 1 . referring to fig1 , depicted is a schematic byte diagram of a test mode address , command and data protocol structure for writing contents of the dac input registers to non - volatile memory . the write enable bit command is comprised of bytes 1300 a and 1300 b , and begins with a start bit 1302 , followed by bytes 1300 a and 1300 b ( 8 bits each ), each byte 1300 is followed by a device ( slave ) acknowledge 1310 , and terminates with a stop bit 1320 . a first byte 1300 a comprises a device code 1304 , and a read / write bit 1308 set to zero . a second byte 1300 b comprises write command type bits 812 ( c 2 = 1 , c 1 = 1 and c 0 = 0 ), and enable bit 1352 . when the enable bit 1352 is set , the contents of the associated dac channel registers are written to the non - volatile memory 114 . the enable bit 1352 is cleared and set by the write enable bit command . referring to fig1 , depicted is a schematic byte diagram of a test mode address , command and data protocol structure for writing bandgap voltage reference trim bits to the dac input registers . the write bandgap voltage reference trim bits command is comprised of bytes 1400 a , 1400 b and 1400 c , and begins with a start bit 1402 , followed by bytes 1400 a , 1400 b and 1400 c ( 8 bits each ), each byte 1400 is followed by a device ( slave ) acknowledge 1410 , and terminates with a stop bit 1420 at the end of byte 1400 c . a first byte 1400 a comprises a device code 1404 , and a read / write bit 1408 set to zero . a second byte 1400 b comprises write command type bits 1412 ( c 2 = 1 , c 1 = 0 and c 0 = 0 ), and voltage reference selection bit 1470 . a third byte 1400 c comprises bandgap absolute value trim bits 1477 ( vbg 3 , vbg 2 , vbg 1 and vbg 0 ) and bandgap amplifier offset trim bits 1484 ( bba 3 , bba 2 , bba 1 and bba 0 ). referring to fig1 , depicted is a schematic byte diagram of a test mode address , command and data protocol structure for writing buffer offset trim bits to the dac input registers . the write buffer offset trim bits command is comprised of bytes 1500 a , 1500 b and 1500 c , and begins with a start bit 1502 , followed by bytes 1500 a , 1500 b and 1500 c ( 8 bits each ), each byte 1500 is followed by a device ( slave ) acknowledge 1510 , and terminates with a stop bit 1520 at the end of byte 1500 c . a first byte 1500 a comprises a device code 1504 , and a read / write bit 1508 set to zero . a second byte 1500 b comprises write command type bits 1512 ( c 2 = 1 , c 1 = 0 and c 0 = 1 ), dac selection bits 1526 ( dac 1 , dac 0 ), and buffer amplifier selection bit 1588 . a third byte 1500 c comprises buffer amplifier a offset value trim bits 1586 a and buffer amplifier b offset value trim bits 1586 b . referring to fig1 , depicted is a schematic byte diagram of an address , command and data protocol structure for reading in test mode the dac input register and non - volatile memory of one or more dac devices . a high voltage is applied to the load dac output register input 122 (/ ldac ) of device 200 ( fig2 ) before and during execution of the test mode read command . the test mode read command of fig1 begins with a start bit 1602 followed by a first byte 1600 sent by the bus master , e . g ., a digital processor ( not shown ), wherein the first byte 1600 comprises a device code 1604 having four fixed identification bits ( e . g ., 1100 b ), three address bits 1606 ( a 2 , a 1 , a 0 ) used to select one of one of up to eight ( 8 ) devices , and a read / write bit 1608 ( set to logic 1 indicating a read operation ). once the first byte 1600 of this read command in test mode from the bus master is finished , a slave acknowledge 1610 is asserted by the slave device ( e . g ., 100 or 200 ) under test . next a first slave byte 1650 a is sent by the slave device . the first slave byte 1650 a comprises the present status of the following data contained in the dac register 106 of dac channel a ( fig2 ): a ready / busy bit 1646 that indicates the completion status of a write to the non - volatile memory 114 ( e . g ., logic 1 indicates write complete , logic 0 indicates otherwise ), a lock bit 1644 , dac channel selection bits 1626 ( dac 1 , dac 0 ), and a zero ( 0 ). after the first slave byte 1650 a has been read by the bus master , the bus master sends a master acknowledge 1660 a . after the slave device receives the master acknowledge 1660 a , a second slave byte 1650 b is sent by the slave device . the second slave byte 1650 b comprises the following data contained in the dac register 106 : bandgap absolute value trim bits 1677 ( vbg 3 , vbg 2 , vbg 1 and vbg 0 ), and bandgap amplifier offset trim bits 1684 ( bba 3 , bba 2 , bba 1 and bba 0 ). after the second slave byte 1650 b has been read by the bus master , the bus master sends a master acknowledge 1660 b . after the slave device receives the master acknowledge 1660 b , a third slave byte 1650 c is sent by the slave device . the third slave byte 1650 c comprises buffer amplifier a offset value trim bits 1686 a and buffer amplifier b offset value trim bits 1686 b . the fourth , fifth and sixth slave bytes 1650 d , 1650 e and 1650 f , respectively , present the same types of data stored in the non - volatile memory 114 as read by the master in slave bytes 1650 a , 1650 b and 1650 c above . after the sixth slave byte 1650 f has been read by the bus master , the bus master sends a master acknowledge 1660 f , and a stop bit 1620 is asserted on the serial bus 120 . referring to fig1 , depicted are schematic block and bus signal diagrams of various types of serial interfaces that may be used with the device shown in fig1 and 2 , according to specific example embodiments of this disclosure . as shown in fig1 ( a ), an i 2 c interface and logic 102 a has a serial clock line , scl , and a serial data line , sda . the i 2 c interface specification is available from phillips semiconductors and is hereby incorporated herein for all purposes . as shown in fig1 ( b ), a serial peripheral interface ( spi ) and logic 102 b has a serial clock , sck , a data out line , si , a data in line , so , and a chip select , cs . the spi interface specification is available from motorola , inc ., or from any device manufacture incorporating the spi interface in their products . the spi interface specification is hereby incorporated herein for all purposes . as shown in fig1 ( c ), a universal serial bus ( usb ) and logic 102 c has self clocking data lines d + and d −. the usb interface specification is available at www . usb . org , or from any device manufacture incorporating the usb interface in their products . the usb interface specification is hereby incorporated herein for all purposes . as shown in fig1 ( d ), a serial clock input - output ( scio ) and logic 102 d has a single self clocking data line scio . the scio interface may use manchester coding so that the clock and data are conveyed on a single bit line . other serial interface standards are known to those skilled in digital electronics design and may also be effectively used with the teachings of this disclosure . referring to fig1 , depicted are schematic plan views of two of many integrated circuit packages that may be used with the devices shown fig1 and 2 , according to specific example embodiments of this disclosure . the i 2 c interface is shown , but it is contemplated and within the scope of this disclosure that any integrated circuit package may be used with any serial interface bus and number of analog outputs . while embodiments of this disclosure have been depicted , described , and are defined by reference to example embodiments of the disclosure , such references do not imply a limitation on the disclosure , and no such limitation is to be inferred . the subject matter disclosed is capable of considerable modification , alteration , and equivalents in form and function , as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure . the depicted and described embodiments of this disclosure are examples only , and are not exhaustive of the scope of the disclosure .