refer now to the drawings wherein depicted elements are , for the sake of clarity , not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views . referring to fig1 a and 1b of the drawings , the reference numerals 100 - 1 and 100 - 2 generally designate plls in accordance with an embodiment of the present invention . the plls 100 - 1 and 100 - 2 generally comprise a phase / frequency detectors ( pfd ) 102 and 104 , a charge pump 106 , a filter 108 , and a voltage controlled oscillator ( vco ) 110 . a different between plls 100 - 1 and 100 - 2 exists in the feedback loop 111 - 1 and 111 - 2 , where divider 112 - 1 provides two feedback signals and divider 112 - 1 provides one feedback signal . turning first to fig1 a , the vco 110 generates an output signal out , which is output to other external circuitry and to the feedback loop 111 - 1 . the feedback loop 111 - 1 is generally comprised of a divider 112 - 1 and a phase loop error compensator or sigma - delta modulator 114 . divider 112 - 1 can be implemented using a conventional programmable divider having a multi - modulus prescaler followed by an a / m counter 124 ( as can be seen in fig2 ) for generating signal f 1 and a delay chain 125 for generating signal f 2 . preferably , the delay chain 125 is comprised of a plurality of d - type flip - flops 126 arranged in series and clocked on the output signal out from the vco 110 , so that signal f 2 is essentially a delayed copy of signal f 1 . additionally , for reduced noise / jitter , signal f 1 can be retimed by a flip - flop that is clocked by the vco 110 directly or by a signal in the prescaler 124 . moreover , the compensator 114 receives signal f 1 and provides a correction signal k to the precaler 124 . these signals f 1 and f 2 are then , preferably , used to achieve a lock condition in the pll 100 - 1 . signals f 1 and f 2 are compared to a reference signal ref in pfds 104 and 102 ( respectively ). ideally , when the pll 100 - 1 is in a locked condition , an edge of the reference voltage ref will occur in the about in middle or approximately equidistantly between the two corresponding edges of signals f 1 and f 2 ( as shown in fig3 a ). in other words and as seen in fig3 a , the time between t 1 and t 2 is approximately equal to the time between t 2 and t 3 . an up signal can then be provided to the up actuator or switch 118 of the charge pump 106 from the up output terminal of pfd 102 , while a down signal can be provided to the down actuator or switch 120 of charge pump 106 from the down output terminal of pfd 104 . by having the signal ref being between signal f 1 and f 2 , the charge pump 106 can output a positive current from current source 116 during the time from an edge of signal f 1 to an edge of the reference signal ref and a negative current from the current source 122 during the time from an edge of the reference signal ref to an edge of the signal f 2 . the charge pump 106 can then output a signal to filter 108 , which provides a filtered signal to the vco 110 . under these circumstances , if the effective positive and negative currents differ in magnitude , the edge of the reference signal ref will be offset from the middle . any phase error or jitter from the vco 110 will cause corresponding edges of signals f 1 and f 2 to move by about the same amount in the same direction . in other words , if pulse width for the up signal changes by δt , then the pulse width of the down signal changes by − δt . assuming a generally constant positive and negative current , a charge contribution would be : | i u |· δt −| i down |·(− δ t )=(| i up |+| i down |)· δ t ( 1 ) thus , the inequalities between positive and negative current can be cancelled or significantly reduced . additionally , the pll 100 - 1 allows the charge pump current to effectively be doubled compared to traditional designs . it should also noted that the linearization and doubled effective charge pump current only occurs when the phase error is small enough to maintain an edge of the reference signal ref between the corresponding edges of the signals f 1 and f 2 . outside this phase error range , the effective charge pump current is either | i up | or | i down |. therefore , the delay between signals f 1 and f 2 should be chosen to be larger than the largest or smallest value of the accumulated jitter that can be caused by the delta - sigma modulator 114 . alternatively , as can be seen in fig1 b , divider 112 - 2 can provide a single feedback signal f pll to each of pfds 102 and 104 , and two separate reference signals ref 1 and ref 2 can be provided to pfds 102 and 104 . in this configuration , an edge of signal f pll is approximately equidistantly between corresponding edges of signals ref 1 and ref 2 ( as can be seen in fig3 b where the span between times t 4 and t 5 is about the same as the span between times t 5 and t 6 ) to achieve substantially the same result as in pll 100 - 1 . having thus described the present invention by reference to certain of its preferred embodiments , it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations , modifications , changes , and substitutions are contemplated in the foregoing disclosure and , in some instances , some features of the present invention may be employed without a corresponding use of the other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention .