the request queue manager function is a crucial part of the centralized transfer controller with hub and ports architecture . to understand its various performance aspects it is helpful to consider first the transfer controller as a whole . the transfer controller with hub and ports architecture is optimized for efficient passage of data throughout a digital signal processor chip . fig1 illustrates a block diagram of the principal features of the transfer controller with hub and ports . it consists of a system of a single hub 100 and multiple ports 111 through 115 . at the heart of the hub is the transfer controller with hub and ports hub control unit 109 which acts upon request and status information to direct the overall actions of the transfer controller . the transfer controller with hub and ports functions in conjunction with a transfer request bus having a set of nodes 117 , which bring in transfer request packets at input 103 . these transfer request bus nodes individually receive transfer requests packets from transfer requesters 116 which are processor - memory nodes or other on - chip functions which send and receive data . secondly , the transfer controller uses an additional bus , the data transfer bus having a set of nodes 118 , to read or write the actual data at the requestor nodes 116 . the data transfer bus carries commands , write data and read data from a special internal memory port 115 and returns read data to the transfer controller hub via the data router 150 at inputs 104 . the transfer controller has , at its front - end portion , a request queue manager 101 receiving transfer requests in the form of transfer request packets at its input 103 . request queue manager 101 prioritizes , stores and dispatches these as required . request queue manager 101 connects within the transfer controller hub unit 100 to the channel request registers 120 which receive the data transfer request packets and process them . in this process , request queue manager 101 first prioritizes the transfer request packets and assigns them to one of the n channel request registers 120 . each of the n channel request registers 120 represents a priority level . if there is no channel available for direct processing of the transfer request packet , it is stored in the queue manager memory 102 . queue manager memory 102 is preferably a random access memory ( ram ). the transfer request packet is then assigned at a later time when a channel becomes available . the channel registers interface with the source 130 and destination 140 control pipelines which effectively are address calculation units for source ( read ) and destination ( write ) operations . outputs from these pipelines are broadcast to m ports through the transfer controller ports i / o subsystem 110 . i / o subsystem 110 includes a set of hub interface units , which drive the m possible external ports units . four such external ports are shown in fig1 as external ports 111 through 114 . the external ports units ( also referred to as application units ) are clocked either at the main processor clock frequency or at a different external device clock frequency . the external device clock frequency may be lower than or higher than the main processor clock frequency . if a port operates at its own frequency , synchronization to the core clock is required . as an example of read - write operations at the ports , consider a read from external port node 112 followed by a write to external port node 114 . first the source pipeline addresses port 112 for a read . the data is returned to the transfer controller hub through the data router unit 150 . on a later cycle the destination control pipeline addresses port 114 and writes the data at port 114 . external ports as described here do not initiate transfer requests but merely participate in reads and writes requested elsewhere on the chip . read and write operations involving the processor - memory ( transfer requestors ) nodes 116 are initiated as transfer request packets on the transfer request bus 117 . the queue manager 101 processes these as described above . on a later cycle a source pipeline output ( read command / address ) is generated which is passed at the internal memory port to the data transfer bus 118 in the form of a read . this command proceeds from one node to the next in pipeline fashion on the data transfer bus . when the processor node addressed is reached , the read request causes the processor - memory node to place the read data on the bus for return to the data router 150 . on a later cycle , a destination pipeline output passes the corresponding write command and data to the internal memory port and on to the data transfer bus for writing at the addressed processor node . the channel parameter registers 105 and port parameters registers 106 hold all the necessary parametric data as well as status information for the transfer controller hub pipelines to process the given transfer . both pipelines share some of the stored information . other portions relate specifically to one pipeline or the other . fig2 illustrates the interface of request queue manager 101 to the transfer controller hub unit boundary and particularly the request queue manager communications with the channel request registers 200 , channel parameters registers 105 and port parameters registers 106 . channel parameters registers 105 and port parameters registers 106 store critical data regarding for example , types of transfers , mode information , status , and much other information critical to the transfer process . channel request registers 200 pass information used in the source control pipeline 130 for generation of the read / pre - write commands 251 . similarly , channel request registers 200 pass information used in the destination control pipeline 140 for the generation of write command / write data words 252 . read response data 104 from the ports is returned to the destination pipeline via the data router unit 150 . request queue manager 101 , illustrated in fig3 , operates in conjunction with the transfer request bus 212 and handles incoming requests . queue manager control unit 201 sorts these requests by their priorities and stores them in the queue manager memory 102 . queue manager memory 102 may take several forms , but is preferably random access memory ( ram ) based . queue manager memory 102 may be partitioned into multiple queues . each such queue represents a priority level with which access requests in that queue should be performed by the transfer controller hub . fig3 shows six priority levels 210 , labeled ch0 through ch5 . the number of channels in request queue manager 101 is highly scalable , and controlled via a set of queue bounds registers 203 within request queue manager 101 . the number of queue bounds registers determines the number of queues . each queue within request queue manager 101 may be of different size , however each queue must contain at least enough memory space to store a single transfer request . request queue manager 101 also processes channel requests from the transfer controller hub 211 and supplies the next queued request to the hub on a per channel ( 1 channel per priority level ) basis . transfer requests from the transfer request bus 212 sent to request queue manager 101 are sorted and stored in the queue manager memory 102 until the transfer controller hub can process them . a priority field of the first double word on an incoming transfer request determines its priority and is used to select into which of the queues the transfer request will be placed . write pointer logic , which is part of the queue bounds registers 203 and read / write pointer block 204 , will increment the address only after each write and then only if the signal allowing queue manager memory 102 bypass is not active . if this increment causes the address to be equal to the next successive queue bounds value , then the next address will be reset to the original queue bounds value for that queue . as an optional enhancement , it is possible to bypass request queue manager 101 when an incoming transfer request packet is addressed to a currently empty queue and the transfer controller hub channel to which that queue corresponds is idle . this condition is detected by comparing the read and write pointers for the appropriate queue . if the read and write pointers are equal , the queue channel is empty . further inspection of the channel status within transfer controller hub 100 can detect the idle condition . thus the transfer request parameters may be directly loaded into the transfer controller hub channel registers 120 . this has the advantage of reducing latency on access requests . in the case of queue manager storage bypass , request queue manager 101 read and write pointers 204 for the appropriate channel are not incremented . transfer controller hub 100 accepts the next entry in request queue manager 101 as soon as the respective channel becomes available ( i . e . the previous request for that channel has completed ). these reads are on a per - channel basis with the highest priority being serviced first . this requires a “ data ready ” signal 221 to be sent back to each of the channels indicating when the respective channel is being serviced by request queue manager 101 . data is sent to the transfer controller hub via the path 222 shown in fig3 . for each read from queue manager memory 102 , the read pointer 204 is incremented except in the case of queue manager storage bypass as noted above . request queue manager 101 can issue only one store or one transfer request at a time . the “ channel request from hub ” signal 211 has a priority level higher than the “ request from the tr bus ” signal 212 . if there is a conflict between channel request from hub 211 and request from transfer request bus 212 , the latter is interrupted until the channel request is served . channel request service is allocated the ch0 priority level , which is the highest priority level , and is served first . requestor disable register block 206 is included in request queue manager 101 . transfer request “ reads ” that have a requestor id that has been disabled via requester disable register block 206 will be ignored . request queue manager 101 will continue to advance to the next request in the queue until one that is not disabled is located , or the queue is empty . request disable register block 206 is memory mapped and can be accessed through internal memory port 115 illustrated in fig1 and 2 . request queue manager 101 has an extra duty to inform the transfer request nodes 116 when one of the transfer requests has been taken out of its priority queue and passed to the transfer controller hub for processing . this is required to notify the individual transfer request nodes 116 when reserved queue slots have freed up . then transfer request nodes 116 can increment their counter value and issue another request if the counter was zero . the requestor id qack signal 226 is sent when it is read out of queue manager memory 102 for the transfer controller hub . the requester id qack signal 226 is passed along transfer request nodes 116 on another bus paralleling the transfer request bus . each transfer request node 116 can verify that the requestor id qack was sent during that cycle and update their counters if applicable . a valid bit is included on this additional bus to qualify when the requestor id was read out . in summary , the datapath in request queue manager 101 consists of three main parts . the first is the queue manager control unit 201 . this functional block takes in the channel request transfer request packet 211 , transfer request node transfer request packet 212 , and the queue manager “ queue empty ” 218 information from the hub . it then decodes the channel register transfer request packet , compares it with the “ queue empty ” information to check if any transfer request jilt packet is ready to be transferred . if there is a transfer packet and a “ channel ready ”, queue manager control unit 201 then issues the channel number , issues a read enable to request queue manager 101 main data path to read the packets from queue manager ram . if there is no transfer packet or “ channel ready ”, queue manager control unit 201 will then do a transfer request write to queue manager memory 102 provided there is a transfer request . if there is a transfer request and a “ channel ready ”, queue manager control unit 201 then issues the channel number and read enable to request queue manager 101 main data path to read the packets from queue manager memory 102 and also do the transfer request write to queue manager memory 102 . the second part of request queue manager 101 datapath is the main datapath . it has n read pointer counters and n write pointer counters for n queues , all a part of block 203 / 204 . for this example n equals six because there are six priority levels . based on whether a read or write operation is issued , request queue manager 101 datapath selects the read or write pointer of the corresponding queue . the datapath also detects whether the pointer will pass beyond the queue boundary . if the next address will go beyond the upper queue boundary , it will reset the next address to the lower queue boundary . request queue manager 101 main datapath also has n - 1 queue bound registers , which may be globally memory mapped . these n - 1 queue bound registers are also a part of queue bounds registers 203 . the queue bounds registers define the lower and upper bounds of the n queues . when they are reset to a new value , both the corresponding read and write pointers are reset to the bottom of the queue immediately .