fig4 shows a set of registers 2 ( registers 00 , 01 , 10 and 11 ). a 4 - way multiplexer 4 selectively connects one of the set of registers to a register bus 6 . the 4 - way multiplexer is controlled by a 2 - bit input from latches 8 and 10 . the latch 10 stores a lower order bit and the latch 8 stores a higher order bit . the 2 - bit word stored in the latches 8 and 10 selects the register having the corresponding 2 - bit identification number from amongst the four registers 00 , 01 , 10 and 11 . the inputs to each of the latches 8 and 10 are supplied by 2 - bit exclusive or gates 12 and 14 respectively . each of the exclusive or gates 12 , 14 has one input fed back from the output of its corresponding latch 8 , 10 and another input from a respective bit of a 2 - bit register selecting word ( regse11 , regse10 ). the 2 - bit registers selecting word corresponds to a control field from within a register selecting instruction word for the set of registers 2 concerned . table 1 shows the 2 - bit result of the exclusive or operation upon the various combinations of the current available register and control field input . table 1______________________________________ current available register 00 01 10 11______________________________________control 00 00 01 10 11field 01 01 00 11 10input 10 10 11 00 01 11 11 10 01 00______________________________________ thus , if the current available register , as identified by the bits stored in the latches 8 and 10 , is &# 34 ; 01 &# 34 ; and the control field input is &# 34 ; 10 &# 34 ;, then the output of the exclusive or operation will be &# 34 ; 11 &# 34 ;. &# 34 ; 11 &# 34 ; will then be stored in the latches 8 and 10 and the register &# 34 ; 11 &# 34 ; selected by the 4 - way multiplexer 4 . the various control field inputs can be considered to have the following functions : the operation of the exclusive or function is such that each register has its own assigned siblings 1 , 2 and 3 with the property that the application of a particular control field input acts as its own inverse . thus , if the current available register is &# 34 ; 10 &# 34 ; and the control field input applied is &# 34 ; 11 &# 34 ;, then the current available register will change to &# 34 ; 01 &# 34 ;. if the current available register is then &# 34 ; 01 &# 34 ; and the same control field input of &# 34 ; 11 &# 34 ; is applied , then the result will be &# 34 ; 10 &# 34 ;, which is the same register that was originally available . fig5 illustrates a system incorporating twelve sets of registers 2 as illustrated in fig4 . the system also includes a permanently available program counter register 16 and permanently available arithmetic operand registers a , b and c . upon execution of a register selecting instruction within the central processing unit of which the system illustrated in fig5 forms part , twelve control fields for respective sets of registers are loaded into a control field store 18 . from the control field store 18 , respective 2 - bit control fields are fed to the exclusive or gates 12 , 14 of corresponding sets of registers 2 . upon initialisation of the system , the register &# 34 ; 00 &# 34 ; from each set of registers 2 is selected as available and the control field store 18 is loaded with a 24 - bit word &# 34 ; 00 , 00 , 00 , 00 , 00 , 00 , 00 , 00 , 00 , 00 , 00 , 00 &# 34 ; indicating that no register swaps are required . these control field values are illustrated next to each of the pairs of exclusive or gates 12 , 14 in fig5 . the selected register from among the set of registers 2 is shown in black . fig6 illustrates the selection of different registers for some of these sets of registers . register set 20 is to swap to with its sibling 1 . register set 22 is to swap with its sibling 3 . register set 24 is to swap with its sibling 2 . register set 26 is to swap with its sibling 1 . the control field input that achieves this selection is &# 34 ; 00 , 01 , 00 , 00 , 11 , 00 , 00 , 10 , 01 , 00 , 00 , 00 &# 34 ;. these control field values are first applied to the exclusive or gates 12 , 14 and then the resulting outputs from the exclusive or gates 12 , 14 held within the latches 8 , 10 to control the 4 - way multiplexers 4 . the selected registers are connected to a register bus 28 to which the permanently available registers pc , a , b and c are also connected . fig7 shows a later operation in which further register selections following on from those illustrated in fig6 are made . in this case , all of the sets of registers other than sets 24 , 26 , 30 and 32 are left unaltered by applying a control field of &# 34 ; 00 &# 34 ;. thus , these unaltered sets of registers maintain the selected register from fig6 whether that be register 00 or another register selected in dependence upon a previously applied control field . register set 30 selects its sibling 2 to the previously selected register 00 , i . e . register 10 . the register set 32 also selects its sibling 2 to the previously selected register 00 . register set 24 selects its sibling 3 to the previously selected register 10 . referring to table 1 , with a current available register of 10 and an applied control field input to select the sibling 3 of &# 34 ; 11 &# 34 ;, the result of the exclusive or operation is &# 34 ; 01 &# 34 ; and this is the sibling that is selected , i . e . the sibling 3 to register 10 is register 01 . in an analogous manner , the register 01 from the set of registers 26 in fig6 is exclusive ored with a control field input of &# 34 ; 01 &# 34 ; to generate an output of &# 34 ; 00 &# 34 ; leading to selection of the register 00 for the set of registers 26 in fig7 . fig8 illustrates a further register selection operation performed upon the registers previously selected as illustrated in fig7 . in this case , register swapping only takes place for the sets of registers 20 and 22 . the control fields applied to the sets of registers are the same as those applied in fig6 . thus , the control field &# 34 ; 01 &# 34 ; is applied to the set of registers 20 acting upon a currently selected register 01 to yield a new selected register 00 . thus , it will be seen that re - applying the same control field as was applied in fig6 results in the re - selection of the original register 00 , i . e . a control field input is effectively its own inverse function whereby applying the control field twice yields the original result . in a similar manner , the control field input to the set of registers 22 is &# 34 ; 11 &# 34 ; which can be seen from table 1 to yield a new selected register 00 . although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings , it is to be understood that the invention is not limited to those precise embodiments , and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims .