embodiments of the present invention will be described hereinbelow with reference to the attached drawings . a magnetic video signal reproducing apparatus of the present invention will be described with reference to fig7 in which the same reference numerals as in fig2 have been retained for similar elements or sections which have the same functions , without repeating any detailed description thereof . the point different between the apparatus shown in fig2 and 7 is that a delay circuit 12 is additionally incorporated to fig7 . in the prior art apparatus , the horizontal synchronizing signal 9a is directly supplied to the latch circuit 10 as a clock signal . in the apparatus of the present embodiment , the horizontal synchronizing signal 9a is delayed through the delay circuit 12 by a predetermined delay time t , before being inputted to the latch circuit 10 as the clock signal . a counter well known to the art which counts clock signals generated by a crystal oscillator can be employed as the delay circuit 12 . this counter is reset at the rising edge of the horizontal synchronizing signal 9a and outputs a pulse signal when counting a specific number of clock signals corresponding to the delay time t . on the basis of the delayed clock signal , it is possible to improve a skew of the reproduced luminance signal 7a by the second time base correcting circuit 8 , as explained hereinbelow in more detail with reference to fig8 : in the same way as in fig4 ( a ) and fig4 ( b ), fig8 ( a ) and fig8 ( b ) show the reproduced luminance signals 7a - 1 and 7a - 2 of the first and third magnetic heads , respectively obtained when the magnetic heads are not switched . as shown , owing to the presence of the delay circuit 12 , the actual switch timings &# 34 ; a &# 34 ; and &# 34 ; b &# 34 ; of the magnetic heads are delayed by the delay time t ; that is , the magnetic heads are switched apparently at the timings &# 34 ; α &# 34 ; and &# 34 ; β &# 34 ;, respectively . accordingly , when the first magnetic head h1 is switched to the third magnetic head h3 , it is possible to obtain the reproduced luminance signal 7a - 3 as shown in fig8 ( c ). on the other hand , when the third magnetic head h3 is switched to the first magnetic head h1 , it is possible to obtain the reproduced luminance signal 7a - 4 as shown in fig8 ( d ). the operation of the second time base correcting circuit 8 for correcting the time bases of these signals will be described hereinbelow with reference to the waveform shown in fig8 ( e ). the reproduced luminance signal 7a - 5 as shown in fig8 ( e ) are written in order in the first to seventh line memories m1 to m7 of the second time base correcting circuit 8 , for a predetermined time period after the falling edge of the horizontal synchronizing signal 9a , in response to the clock signal generated on the basis of the horizontal synchronizing signal 9a following the jitter of the reproduced luminance signal 7a - 5 . further , the written reproduced luminance signal 7a - 5 is read , as the outputted luminance signal 8a as shown in fig8 ( f ), in response to the clock signal of a stable frequency . as described above , since the magnetic heads are switched by delaying the output signal 10a of the latch circuit 10 through the delay circuit 12 by the delay time t , it is possible to obtain the outputted luminance signal 8a whose skew has been improved . here , it is preferable that the delay time t is the maximum value less than ( 1h - τ ), where τ denotes the skew generated between both the magnetic heads . the reason of the above - mentioned relationship will be described with reference to fig9 and 10 . in the case where the delay time t exceeds the time ( 1h - τ ) as shown in fig9 and further the after - switch signal ( the signal selected after switching ) as shown in fig9 ( a ) leads the before - switch signal ( the signal selected before switching ) as shown in fig9 ( b ), there exists such a disadvantage that the horizontal synchronizing signal portion ( 9a ) on the reproduced luminance signal 7a is narrower in waveform width ( in the front portion ). on the other hand , in the case where the delay time t is excessively short as compared with the ( 1h - τ ) as shown in fig1 and further the signal is switched from the state as shown in fig1 ( a ) to that as shown in fig1 ( b ), there exists such a disadvantage that the switching noise of the magnetic heads appears at a middle portion of the picture , as shown in fig1 ( c ). accordingly , it is preferable to set the delay time t at the maximum value not more than the time ( 1h - τ ). in the first embodiment , the skew has been improved by appropriately setting the delay circuit 12 and the delay time t . however , there are some cases where the switching noise of the magnetic heads appears at a middle of the picture display ( referred to as &# 34 ; in - picture switching noise &# 34 ; hereinafter ) according to the skew time generated between both the magnetic heads . in the second embodiment , the in - picture switching noise can be eliminated by improving the write and read control operation to and from the line memories which constitute the second time base correcting circuit 8 . the second time base correcting circuit 8 will be described hereinbelow with reference to fig1 . the circuit comprises an a / d converting circuit 81 , a d / a converting circuit 87 , first to fourth line memories 82 to 85 ( referred to as a to d memories , hereinafter ) each for storing information data for one horizontal line ( 1h ), and a memory control circuit 86 . further , in fig1 , the output terminals awe to dwe , awr to dwr , are to dre , and arr to drr of the memory control circuit 86 denote the kinds of control signals outputted therefrom . in more detail , the awe to dwe are write enable signals for setting the a to d memories to the write enable status at the high level thereof ; the awr to dwr are write reset signals for resetting the write addresses of the a to d memories at the high level thereof ; are to dre are read enable signals for setting the a to d memories to the read enable status at the high level thereof ; and arr to drr are read reset signals for resetting the read addresses of the a to d memories at the high level thereof . that is , the a to d memories are all controlled in response to these control signals . all these memories a to d are not necessarily required to eliminating noise . therefore , only the following four methods are explained . the first method is to eliminate noise by stopping the reproduced luminance signal 7a from being written in the a and b memories ( i . e . two 1h memories ) as long as the in - picture switching noise is present , for improvement of noise elimination . this method will be explained in further detail with reference to fig1 . the magnetic heads are switched in response to the output signal 10a of the latch circuit 10 as shown in fig1 ( a ). therefore , the continuity of the fm ( frequency modulated ) signal is lost at the rising edge of the latch output signal 10a , with the result that the reproduced ( demodulated ) luminance signal 7a includes noise in synchronism with the rising edge of the latch output signal 10a , as shown in fig1 ( b ). the reproduced luminance signal 7a is usually controlled in such a way as to be written alternately for each 1h ( one horizontal period ) in the a and b memories of the second time base correcting circuit 8 . further , when the reproduced luminance signal 7a is being written in one memory , the other reproduced luminance signal 7a already written in the other memory before 1h is read . however , near the rising edge of the latch output signal 10a , the signal writing operation to the memory is stopped and further the reproduced luminance signal 7a is written to the b memory on the basis of the write enable signal bwe ( whose level is low during the period b6 ), as shown in fig1 ( d ). on the other hand , the signal writing operation to the a memory is performed in the same way as usual on the basis of the write enable signal awe as shown in fig1 ( c ). when the reproduced luminance signal 7a is written in response to the write enable signal bwe as described above , since no luminance signal 7a is written during the period b6 , the reproduced luminance signal 7a written during the period b5 is kept stored in the b memory . the stored signal is read on the basis of the read enable signals are and bre as shown in fig1 ( e ) and fig1 ( f ). that is , the luminance signal 8a as shown in fig1 ( g ) can be obtained by interpolating the noise period on the basis of the reproduced luminance signal 7a obtained 2h before . in this case , further , it is of course possible to stop all the writing operation for the horizontal line including noise . the second method is to eliminate noise by reading the luminance signal written in the a and b memories ( i . e . two 1h memories ) written during the period at which in - picture switching noise is absent , without reading the reproduced luminance signal written in the a and b memories during the period at which in - picture switching noise is present , for improvement of noise elimination . this method will be explained in further detail with reference to fig1 . the magnetic heads are switched in response to the output signal 10a of the latch circuit 10 as shown in fig1 ( a ). therefore , the continuity of the fm ( frequency modulated ) signal is lost at the rising edge of the latch output signal 10a , with the result that the reproduced ( demodulated ) luminance signal 7a includes noise in synchronism with the rising edge of the latch output signal 10a , as shown in fig1 ( b ). the reproduced luminance signal 7a is usually controlled in such a way as to be written alternately for each 1h ( one horizontal period ) in the a and b memories of the second time base correcting circuit 8 on the basis of the write enable signals awe and bwe as shown in fig1 ( c ) and fig1 ( d ). further , when the reproduced luminance signal 7a is being written in one memory , the other reproduced luminance signal 7a already written in the other memory before 1h is read on the basis of the read enable signals are and bre as shown in fig1 ( e ) and fig1 ( f ). however , during the period b7 when the signal including noise and written in the b memory is read as shown in fig1 ( e ), the read enable signal bre is set to a low level to stop reading the signal from the b memory . further , the read enable signal are is set to a high level to read the signal from the a memory . as described above , the luminance signal 8a as shown in fig1 ( g ) is obtained by interpolating the period at which noise is present by use of the other period at which noise is absent . the third method is to stop writing the reproduced luminance signal 7a in the memories , as long as the in - picture switching noise is present , by use of three or more memories for improvement of noise elimination . in the first method , when the number of memories to be used increases , the waveform of the interpolated signal deviates from the standpoint of time , and therefore the interrelation between the reproduced luminance signal and the interpolated signal deteriorates . being similar to the first method , this third method can overcome the above - mentioned problem . the third method will be described with reference to fig1 , in which four memories are used for convenience . however , the following is applicable to the case where three or five or more memories are used . the magnetic heads are switched in response to the output signal 10a of the latch circuit 10 as shown in fig1 ( a ). therefore , the continuity of the fm ( frequency modulated ) signal is lost at the rising edge of the latch output signal 10a , with the result that the reproduced ( demodulated ) luminance signal 7a includes noise in synchronism with the rising edge of the latch output signal 10a , as shown in fig1 ( b ). the reproduced luminance signal 7a is usually controlled in such a way as to be written cyclically for each 1h ( one horizontal period ) in the a and b memories of the second time base correcting circuit 8 . further , when the reproduced luminance signal 7a is being written in one memory , the other reproduced luminance signal 7a already written in the other memory before 1h is read . however , near the rising edge of the latch output signal 10a , the signal writing operation to the memory is stopped and further the reproduced luminance signal 7a is written to the c memory on the basis of the write enable signal cwe ( whose level is low during the period c8 , but high during the period c9 1h after c8 for the same period as c8 ), as shown in fig1 ( e ). on the other hand , the signal writing operation to the a , b and d memories is performed in the same way as usual on the basis of the write enable signals awe , bwe and dwe as shown in fig1 ( c ), fig1 ( d ) and fig1 ( f ). as described above , when the write enable signal cwe is used , although the signal is not written during the period c8 , since the signal is written during the period c9 having interrelation with the period c8 , it is possible to write the reproduced luminance signal 7a interpolated in place of noise in the c memory . the stored signal is read on the basis of the read enable signals are to dre as shown in fig1 ( g ) to fig1 ( j ). that is , the luminance signal 8a as shown in fig1 ( k ) can be obtained by interpolating the noise period on the basis of the reproduced luminance signal 7a obtained 1h after . the fourth method is to eliminate noise by reading the luminance signal written in the three or more memories during the period at which in - picture switching noise is absent , without reading the reproduced luminance signal written in the same memories during the period at which in - picture switching noise is present , for improvement of noise elimination . in the second method , when the number of memories to be used increases , the waveform of the interpolated signal deviates from the standpoint of time , and therefore the interrelation between the reproduced luminance signal and the interpolated signal deteriorates . being similar to the second method , this fourth method can overcome the above - mentioned problem . this method will be explained in further detail with reference to fig1 , in which four memories are used for convenience . however , the following is applicable to the case where three or five or more memories are used . the magnetic heads are switched in response to the output signal 10a of the latch circuit 10 as shown in fig1 ( a ). therefore , the continuity of the fm ( frequency modulated ) signal is lost at the rising edge of the latch output signal 10a , with the result that the reproduced ( demodulated ) luminance signal 7a includes noise in synchronism with the rising edge of the latch output signal 10a , as shown in fig1 ( b ). the reproduced luminance signal 7a is usually controlled in such a way as to be written cyclically for each 1h ( one horizontal period ) in the a to d memories of the second time base correcting circuit 8 on the basis of the write enable signals awe to dwe as shown in fig1 ( c ) to fig1 ( f ), respectively . further , when the reproduced luminance signal 7a is being written in one memory , another reproduced luminance signal 7a already written in another memory 2h before is read in sequence on the basis of the read enable signals are and dre as shown in fig1 ( g ) and fig1 ( j ), respectively . however , during the period when the signal including noise and written in the c memory is read as shown in fig1 ( b ), the read enable signal cre is set to a low level during the period c1 as shown in fig1 ( i ) to stop reading the signal from the c memory . instead , the read enable signal bre is set to a high level during the period c1 to read the signal from the b memory . as described above , the luminance signal 8a as shown in fig1 ( k ) can be obtained by interpolating the period at which noise is present by use of the other period at which noise is absent . in the above - mentioned first and second embodiments , the improvement is related to the luminance signal . in this third embodiment , the improvement is related to the chrominance signal for correcting the color rotation caused when the magnetic heads are switched . this third embodiment will be described hereinbelow with reference to fig1 to 27 . fig1 shows the main portion of the chrominance signal reproducing circuit 5 of this embodiment , which comprises a burst phase detecting circuit aa , a color rotation processor bb , and a 1 - h delay circuit ( 1hdl ) 61 . the burst phase detecting circuit aa detects the discontinuity of color rotation caused when the magnetic heads are switched ; that is , detects the phase difference of the burst signal included in the reproduced low frequency - converted chrominance signal 3a before or after the timing at which the magnetic heads are switched in response to the output signal 10a of the latch circuit 10 shown in fig7 . in other words , the reproduced low frequency - converted chrominance signal 3a is supplied to the burst phase detecting circuit aa before and after being passed through the 1 - h delay circuit 61 . the phase difference between the two ( before and after ) chrominance signals 3a is detected by the detecting circuit aa , and then two first and second color rotation correcting signals aa1 and aa2 ( the command signals for leading the phase by 90 and 180 degrees , respectively ) are supplied to the color rotation processor bb , for color rotation correction . the burst phase detecting circuit aa will be described in further detail hereinbelow with reference to fig1 and 18 . in fig1 , the burst phase detecting circuit aa comprises an a / d converting circuit 50 , a filter circuit 51 , a binarizing circuit 52 , a differentiating circuit 53 , a gate circuit 54 , a burst gate pulse generating circuit 55 , a counter circuit 56 , a timing pulse generating circuit 57 , a subtracting circuit 58 , a 4 - phase discriminating circuit 59 , a rotation correction signal generating circuit 60 , and latch circuits f1 to f3 . the reproduced low frequency - converted chrominance signal 3a having the carrier frequency of 629 khz as shown in fig1 ( b ) is applied to the a / d converting circuit 50 which then outputs the signal as shown in fig1 ( c ). the signal shown in fig1 ( c ) is applied to the filter circuit 51 which is composed of a first delay circuit 511 ( λ / 2 dl ) for providing a delay time of a half wavelength of the carrier frequency and a first subtracter 512 . fig1 ( d ) shows an output signal of the first delay circuit 511 , which is delayed by λ / 2 from the input signal shown in fig1 ( c ). therefore , the subtracter 512 outputs a subtraction signal 51a as shown in fig1 ( e ) to the binarizing circuit 52 . the binarizing circuit 52 extracts the sign bit of the output signal 51a of the subtracter 512 , and supplies the binarized signal 52a as shown in fig1 ( f ) to the differentiating circuit 53 . this differentiating circuit 53 generates a differentiated signal 53a as shown in fig1 ( g ) in synchronism with the rising edge of the binarized signal 52a . a gate pulse 55a as shown in fig1 ( h ) is supplied from the burst gate pulse generating circuit 55 to the gate circuit 54 on the basis of the horizontal synchronizing signal 9a shown in fig1 ( a ). the differentiated signal 53a is gated by the gate circuit 54 on the basis of the gate pulse 55a and outputted to the latch circuit f1 as a phase information signal 54a as shown in fig1 ( i ). accordingly , the time interval between the falling edge of the horizontal synchronizing signal 9a and the rising edge of the phase information signal 54a indicates the phase information of the burst signal related to the reproduced low frequency - converted signal 3a . therefore , it is possible to obtain the phase of the burst signal by measuring the above - mentioned time interval for each horizontal line . in addition , it is possible to discriminate the continuity of the color rotation by comparing the measured interval with the next measured interval , as described in further detail below . for convenience , the phase information signal 54a as shown in fig1 ( j ) is supplied to the first latch circuit f1 as a clock signal . further , a count data of the counter circuit 56 , which is cleared to start counting a clock signal supplied by a clock signal generator ( not shown ) in response to the falling edge of the horizontal synchronizing signal 9a , is supplied to the first latch circuit f1 . the first latch circuit f1 latches the counted data of the counter circuit 56 in response to the phase information signal 54a , and outputs the first latched data f1a as shown in fig1 ( k ) to the second latch circuit f2 . on the other hand , the timing pulse generating circuit 57 supplies a timing pulse 57a as shown in fig1 ( l ) to the second latch circuit f2 . this timing pulse 57a is generated in response to the horizontal synchronizing signal 9a and delayed from the rising edge of the phase information signal 54a by a constant time . the second latch circuit f2 latches the output data f1a of the first latch circuit f1 in response to this timing pulse 57a , and outputs the second latched data f2a as shown in fig1 ( m ) to the third latch circuit f3 . in the same way , the third latch circuit f3 latches the output of the second latch circuit f2 in response to the timing pulse 57a , and outputs the third latched data f3a as shown in fig1 ( n ) to the succeeding stage . d0 to d2 shown in fig1 ( m ) and fig1 ( n ) denote the data representative of the phases of the burst signals in the zeroth horizontal line to the second horizontal line , respectively . further , the second subtracter 58 subtracts the third output data f3a from the second output data f2a , and supplies the obtained phase difference data 58a as shown in fig1 ( o ) to the 4 - phase discriminating circuit 59 . the 4 - phase discriminating circuit 59 discriminates the current phase rotation on the basis of the phase difference data 58a , and supplies the discriminated data to the rotation correction signal generating circuit 60 , in order to obtain the first rotation correction signal aa1 for leading the phase by 90 degrees and the second rotation correction signal aa2 for leading the phase by 180 degrees as the phase leading command signals . the color rotation processor bb will be described hereinbelow with reference to fig1 and 20 . the point different from the prior art color rotation processor bb shown in fig6 is that in this embodiment there exists no feedback loop by use of the first phase comparing circuit 90 . therefore , the same reference numerals as in fig6 have been retained for similar circuits which have the same functions , without repeating any detailed description thereof . the frequency converting circuit 65 converts the reproduced low frequency - converted signal 3a into the high frequency - converted signal bb by multiplying the low frequency - converted signal 3a by the output signal 64a of the switching circuit 64 . in this embodiment , the switching circuit 64 selects the output signal 64a obtained under consideration of the color rotation correction . in more detail , the 4 phase - shifted signal generating circuit 63 supplies the first to fourth local oscillation signals s0 to s3 to the switching circuit 64 . the local oscillation signals s0 to s3 used for high frequency conversion have a local frequency of 4 . 2 mhz and four different phases each shifted by 90 degrees with respect to each other . these first to fourth local oscillation signals s0 to s3 can be selected in response to four - bit data selection signals 66a applied from the 2 - bit counting circuit 66 to the switching circuit 64 . the selected signal is outputted as an output signal 64a to the frequency converting circuit 65 . the operation of the 2 - bit counter circuit 66 will be described with reference to fig2 . the counter circuit 66 counts the horizontal synchronizing signals 9a as shown in fig2 ( a ) as the clock signal , and further adds or subtracts &# 34 ; 1 &# 34 ; or &# 34 ; 2 &# 34 ; to or from the ordinary counted value , respectively in response to the high level of the first or second rotation correction signals aa1 or aa2 ( the command signals for leading the phase by 90 or 180 degrees ) as shown in fig2 ( g ) or fig2 ( h ). the addition or subtraction operation of the 2 - bit counter circuit 66 can be determined by the output signal 10a of the latch circuit 10 as shown in fig2 ( i ). that is , if the output signal 10a is at a low level , the addition operation is determined to be executed ; and if at a high level , the subtraction operation is determined . fig2 ( b ) shows the counted value ( selected data ) of the 2 - bit counter circuit 66 thus obtained ; and fig2 ( c ) to fig2 ( f ) show the respective selected data 66a in the order of the lsb ( least significant bit ). the timings t1 to t3 shown in fig2 will be described in more practical way . first , at the timing t1 , since the output signal 10a of the latch circuit 10 is at a low level , the operation is in addition status . further , since the first rotation correction signal aa1 is at a high level , the selection data to be changed from &# 34 ; 0 &# 34 ; to &# 34 ; 1 &# 34 ; in the ordinary status is changed from &# 34 ; 0 &# 34 ; to &# 34 ; 2 &# 34 ; as shown by a left side thick box in fig2 ( b ). further , at the timing t2 , since the output signal 10a of the latch circuit 10 is at a low level , the operation is in addition status . further , since the second rotation correction signal aa2 is at a high level , the selection data to be changed from &# 34 ; 0 &# 34 ; to &# 34 ; 1 &# 34 ; in the ordinary status is changed from &# 34 ; 0 &# 34 ; to &# 34 ; 3 &# 34 ; as shown by a middle thick box in fig2 ( b ). further , at the timing t3 , since the output signal 10a of the latch circuit 10 is at a high level , the operation is in subtraction status . further , since the first and second rotation correction signals aa1 and aa2 are both at a high level , the selection data to be changed from &# 34 ; 3 &# 34 ; to &# 34 ; 2 &# 34 ; in the ordinary status is changed from &# 34 ; 3 &# 34 ; to &# 34 ; 3 &# 34 ; as shown by a right side thick box in fig2 ( b ), because &# 34 ; 3 &# 34 ; is further subtracted from &# 34 ; 2 &# 34 ;. as described above , since the phase rotation can be corrected for each 1h , it is possible to improve the color reproducibility during the high speed reproduction operation . here , there exists a problem in that a well - known apc loop for high - frequency conversion in the color rotation processor bb reveals a long pull - in time , which is caused by the discontinuity of the phase rotation produced when the magnetic heads are switched . the means for solving the above - mentioned problem will be described with reference to fig2 and 22 . for facilitate understanding of the operation , in fig2 ( a ) to fig2 ( d ), an ideal reproduced low frequency - converted chrominance signal 3a is shown together with the reproduced luminance signal 7a in the order of the horizontal lines , in which the phase of the burst signal in the reproduced low frequency - converted chrominance signal 3a sequentially lags behind by 90 degrees . however , if there exists a skew , since the skew is generated in the reproduced low frequency - converted chrominance signal 3a in the same way as in the reproduced luminance signal 7a , as shown in fig2 ( e ), the apc loop operates erroneously . to overcome this problem , in this embodiment , the main portion of a chrominance signal reproducing circuit as shown in fig2 is used . the points different between the circuit shown in fig1 and that shown in fig2 are that variable delay circuits 93a and 93b and a third time base correcting circuit ( tbc 3 ) are additionally incorporated . therefore , the same reference numerals as in fig1 have been retained for the same elements which have the same functions , without repeating any detailed description thereof . in this circuit , after a skew has been removed from the reproduced low frequency - converted chrominance signal 3a by the third time base correcting circuit 94 on the basis of the horizontal synchronizing signal 9a , the reproduced low frequency - converted chrominance signal 3a is supplied , as the signal 94a , to the color rotation processor bb to obtain the high frequency - converted signal bb after the predetermined processing . in the above - mentioned operation , a delay time is produced when the time base is corrected by the third time base correcting circuit 94 . therefore , it is necessary to delay the first and second color rotation correcting signals aa1 and aa2 also . the correcting signals are delayed by the variable delay circuit 93a and 93b . that is , the delay time of the variable delay circuits 93a and 93b are controlled automatically on the basis of the delay data 88a supplied from the third time base correcting circuit 94 , in such a way as to be roughly equal to the delay time of the third time base correcting circuit 94 . further , since the apc loop operation can be more stabilized by correcting the time base through the third time base correcting circuit 94 before the high frequency conversion , it is possible to interpose the third time base correcting circuit 94 at the position shown by ee in fig2 , in order that the time base of the reproduced low frequency - converted chrominance signal 3a may be corrected before being supplied to the 1h delay circuit 61 and the burst phase detecting circuit aa . in this case , the variable delay circuits 93a and 93b are not required , thus it being possible to simplify the circuit configuration . the third time base correction circuit 94 is shown in fig2 . the circuit 94 has the construction which includes a time base correction circuit the same as the second time base correction circuit 8 shown in fig1 and a delay quantity measuring circuit 88 . the constitution and the operation of the delay quantity measuring circuit 8 will be described with reference to fig2 and 25 . the operation of the time base correction circuit portion in fig2 is the same as that of the second time base correction circuit 8 , the difference therebetween is the signal handled , that is , the chrominance signal 3a in fig2 , while the luminance signal 7a in fig1 . thus , the explanation of the operation of the time base correction portion is omitted . in fig2 , the delay quantity measuring circuit 88 includes a counter 100 , a latch 101 , or - gates 100a and 101a . one of the write reset signals awr to dwr outputted from the memory control circuit 86 shown in fig2 is applied to a reset terminal r of the counter 100 , as a signal 100b via the or - gate 100a . output signals of q terminals of the counter 100 are reset at the rising edge of the signal 100b , thus , the counter 100 starts to count clock signals applied to a clock terminal ck of the counter 100 from a clock signal generator ( not shown ). sequentially , one of the read reset signals arr to drr outputted from the memory control circuit 86 is applied to a clock terminal ck of the latch 101 , as a signal 101b via the or - gate 101a . count value ( 100c of fig2 ( k )) of the counter 100 is applied to d terminals of the latch 101 , as data of m bits ( m is a positive integer ). the count values d1 , d2 , . . . , dn ( n is a positive integer ) of the counter 100 at respective timings when the signal 101b rises are sequentially latched to the latch 101 . each of the latched count values is outputted from q terminals of the latch 101 , as the delay data 88a , until the next count value is latched to the latch 101 as shown in fig2 ( l ). the delay data 88a ( d1 , d2 , . . . , dn ) represents the number of pulses of the clock signal during the time period from the incoming of the write reset signals awr to dwr to the incoming of the read reset signals arr to drr to the delay quantity measuring circuit 88 . in other words , the delay data 88a represents the time period of the delay time in which the chrominance signal is delayed by the line memories a to d , by the number of the pulses of the clock signal . the constitution and the operation of each of the variable delay circuits 93a and 93b as shown in fig2 will be described with reference to fig2 and 27 . the variable delay circuits 93a and 93b are composed of the same circuitry and operate in the same way . in fig2 , each of the variable delay circuits 93a and 93b includes down counters 102 and 103 , decoders 104 and 105 , a j - k flip - flop 106 and an inverter 103a . the delay data 88a is applied to both data input terminals d of the down counters 102 and 103 . the color rotation correction signal aa1 ( aa2 ) is directly applied to a reset terminal r of the down counter 102 and also applied to that of the down counter 103 via the inverter 103a . the decoders 104 and 105 apply pulse signals to j and k terminal of the j - k flip - flop 106 , respectively when detecting the respective count values becoming zero . more in detail , to the down counters 102 and 103 and also the flip - flop 106 , a clock signal of stable frequency is applied from a clock signal generator ( not shown ). each of the counters 102 and 103 accepts the delay data 88a applied to the data input terminals d in response to the rising edge of the color rotation correction signal aa1 ( aa2 ) applied to the reset terminal r . in detail , the down counter 102 accepts the delay data 88a or dn ( n = 1 , 2 , 3 , . . . ) applied to the data input terminals d in response to the rising edge of the color rotation correction signal aa1 ( aa2 ) and starts down - counting according to the clock signal . the counted value of the down - counting is applied to the decoder 104 which applies a plus signal to the j - terminal of the flip - flop 106 when the counted value becomes zero . thus , an output signal 106a from the q - terminal of the flip - flop 106 is raised to a high level . on the other hand , the down counter 103 accepts the delay data 88a or dn ( n = 1 , 2 , 3 , . . . ) applied to the data input terminals d in response to the falling edge of the color rotation correction signal aa1 ( aa2 ), because the signal aa1 ( aa2 ) is applied to the input terminals d via the inverter 103a . the down counter 103 then starts down - counting according to the clock signal . the counted value of the down - counting is applied to the decoder 105 which applies a plus signal to the k - terminal of the flip - flop 106 when the counted value becomes zero . thus , the output signal 106a from the q - terminal of the flip - flop 106 is thrown back to a low level . accordingly , the color rotation correction signal aa1 ( aa2 ) is delayed by the time period corresponding to the delay data 88a and outputted from the flip - flop 106 as the signal 106a . as described above , in this embodiment , since the color rotation is corrected on the basis of the reproduced low frequency - converted signal from which a skew has been removed , it is possible to obtain an excellent high frequency - converted signal bb without disturbing the apc loop operation . in the above - mentioned third embodiment , the discontinuity of the color rotation caused when the magnetic heads are switched is corrected by detecting the phase of the burst signal . however , since the burst signal is a signal converted to a low frequency range , it is difficult to decrease the crosstalk interference due to azimuth loss and therefore there exists a case where an error increases in detecting the burst signal phase . to overcome this problem , in this fourth embodiment , the burst signal converted to the low frequency range is passed through a comb - type filter to improve the precision of when the phase is detected . the comb - type filter incorporated in this fourth embodiment is shown in fig2 . the comb - type filter is composed of a delay circuit ( 1h ± 1 / 4λdl ) 68 and an adder circuit 69 . the delay time of the delay circuit 68 is controlled on the basis of the output signal 10a of the latch circuit 10 as shown in fig7 in corresponding to the forward and reverse phase shift of the burst signal . that is , when the signal 10a is at a low level , the delay time is set to 1h - 1 / 4λ ; and when at a high level , the delay time is set to 1h + 1 / 4λ . therefore , the input signal and the output signal of the delay circuit 68 match each other in phase . these two input and output signals are added by the adder circuit 69 , so that it is possible to obtain an output signal having an emphasized signal component effective against the crosstalk components . the above - mentioned comb - type filter is interposed between the a / d converting circuit 50 and the filter circuit 51 or between the filter circuit 51 and the binarizing circuit 52 in the circuit shown in fig1 , in order to reduce the crosstalk interference , thus it being possible to more accurately detect the phase of the burst signal . as described above , in the configuration of the present invention , since , when the discontinuity of the phase rotation caused by the switching of the first and second magnetic heads is detected by the phase detection means , the phase is shifted by the reproduced chrominance processing means to restore the phase rotation at recording , it is possible to correct the deviation of the phase caused by the switching in an open loop , without disturbing the chrominance signal in the horizontal lines immediately after the first and second magnetic heads have been switched , thus resulting in such an effect that it is possible to provide a magnetic video signal reproducing apparatus excellent in the high speed reproduction operation , in particular . furthermore , as described above , in the configuration of the present invention , since the time base is corrected by the time base correcting means before the reproduced low frequency - converted chrominance signal is converted into the high frequency range , it is possible to improve the pull - in time of the apc loop used for the high frequency conversion by the reproduced chrominance signal processing means , without disturbing the chrominance signal in the horizontal lines immediately after the first and second magnetic heads have been switched , thus resulting in such an effect that it is possible to provide a magnetic video signal reproducing apparatus excellent in the high speed reproduction operation , in particular .