fig1 shows the main components of a digital - signal forming circuit according to an embodiment of the present invention . referring to fig1 the present invention is described below . the digital - signal forming circuit includes a demodulator 1 , a signal comparator 2 composed of an operational amplifier , a make - and - break switch 3 , an average - reference voltage unit 4 , a controller 6 composed of a cpu , a received - signal strength detector 7 , a selection switch 8 composed of one - circuit - two - contact switch , a fixed - reference - voltage unit 9 , an if signal input terminal 21 to which an if signal is input , a radio - frequency - signal ( rf - signal ) input terminal 22 to which an rf signal is input , and a digital - signal output terminal 23 . the average - reference voltage unit 4 includes a resistor 11 connected across the input and output ends thereof , two diodes 12 and 13 connected across the input and output ends thereof so that their polarities are inverse , and a capacitor 14 connected between the output end and the ground . when the voltage of an input demodulated signal changes greatly , the voltage stored in the capacitor 14 is rapidly changed by the diodes 12 and 13 connected across the input and output ends of the average - reference voltage unit 4 so that their polarities are inverse . the fixed reference voltage unit 9 includes a resistor 15 and a capacitor 16 which are connected in parallel across the input end thereof and the ground . the controller 6 is provided with a strength - signal input terminal c , a data - input terminal d , a fixed - voltage output terminal e , a fixed - voltage output terminal f , and a selection - signal output terminal g . the demodulator 1 has an input end connected to the if input terminal 21 , and an output end connected to both the non - inverting input ( indicated as “+” in fig1 ) of the comparator 2 and one contact of the make - and - break switch 3 . the average - reference voltage unit 4 has an input end connected to the other contact of the make - and - break switch 3 and an output end connected to one fixed contact a of the selection switch 8 . the fixed - reference - voltage unit 9 is connected to the fixed - voltage output terminal e of the controller 6 and the other fixed contact b of the selection switch 8 . the movable contact of the selection switch 8 is connected to the inverting input ( indicated as “−” in fig1 ) of the comparator 2 . the output of the comparator 2 is connected to the digital - signal output terminal 23 and the data input terminal d of the controller 6 . the received - signal strength detector 7 has an input end connected to the rf signal input terminal 22 and an output end connected to the strength - signal input terminal c . the fixed - voltage output terminal f of the controller 6 is connected to the control terminal of the make - and - break switch 3 . the selection - signal output terminal g is connected to the control terminal of the selection switch 8 . the demodulator 1 outputs a demodulated signal by demodulating the if signal . the comparator 2 outputs a digital signal by shaping the demodulated signal into rectangular waves , while the non - inverting input (+) of the comparator 2 is being supplied with the demodulated signal and the inverting input (−) of the comparator 2 is being supplied with a reference voltage . the control terminal of the make - and - break switch 3 is supplied with a make - and - break signal . the make - and - break switch 3 is turned on when the make - and - break signal is at high level , while it is turned off when the make - and - break signal is at low level . when the make - and - break switch 3 is turned on , the demodulated signal is supplied from the demodulator 1 to the average - reference voltage unit 4 , and the average - reference voltage unit 4 uses averaging to convert the demodulated signal into a dc voltage . the average - reference voltage unit 4 stores it in the capacitor 14 , and applies it to the fixed contact a of the selection switch 8 . the fixed - reference - voltage unit 9 applies , to the fixed contact b of the selection switch 8 , a dc voltage output from the fixed - voltage output terminal e of the controller 6 . the control terminal of the selection switch 8 is supplied with a selection signal . when the selection signal is at high level , the fixed contact b and the movable contact are connected . when the selection signal is at low level , the fixed contact a and the movable contact are connected . the received - signal strength detector 7 outputs a strength signal having high level when the strength of the rf signal is not less than a predetermined value , and outputs the strength signal having low level when the strength of the rf signal is not more than the predetermined value . the controller 6 refers to the strength signal and to the digital signal output from the comparator 2 . when the strength signal is at low level , the controller 6 outputs the make - and - break signal at high level from a time just before the start of a synchronizing signal sy to the end of the synchronizing signal sy . in other cases , the controller 6 outputs the make - and - break signal at low level . the controller 6 also outputs the selection signal , whose logic level is equal to that of the strength level , from a time just before a receiving slot to the end of the receiving slot . fig2 illustrate the operating conditions of the components of the digital - signal forming circuit shown in fig1 . time chart ( a ) shows time - slot condition . time chart ( b ) shows the contents of the received signal . time chart ( c ) shows timing for monitoring the strength signal . time charts ( d ) to ( f ) show the operation of the digitalsignal forming circuit when a non - receiving slot has a small interference signal . time chart ( d ) shows strength - signal condition , time chart ( e ) shows the operating condition of the make - and - break switch 3 , and time chart ( f ) shows the operating condition of the selection switch 8 . time charts ( g ) to ( i ) show the operation of the digital - signal forming circuit when the non - receiving slot has a large interference signal . time chart ( g ) shows strength - signal condition , time chart ( h ) shows the operating condition of the make - and - break switch 3 , and time chart ( i ) shows the operating condition of the selection switch 8 . with reference to time charts ( a ) and ( b ) in fig2 time - slot condition and the contents of the received signal are described below . a time t 1 and a time t 2 are positioned in a non - receiving slot that is not assigned as a receiving period . the time t 1 is a time at which the strength signal output from the received - signal strength detector 7 is referred to by the controller 6 . the time t 2 is a time at which the make - and - break switch 3 or the selection switch 8 is switched in accordance with the condition of the strength signal being referred to . a time t 3 to a time t 5 are positioned in a receiving slot assigned as a receiving period . in the period between the time t 3 and a time t 4 , the synchronizing signal sy is received . in the period between the time t 4 and the time t 5 , the communication data sd is received . with reference to fig1 and 2 , the operation of the digital - signal forming circuit of the present invention is described below . at the time t 1 in the non - receiving slot that is not assigned as the receiving period , the controller 6 refers to the strength signal output from the received - signal strength detector 7 . at this time , both the make - and - break signal and the selection signal , output from the controller 6 , are at low level . accordingly , the make - and - break switch 3 is broken , and the selection switch 8 selects the fixed contact a ( the average - reference - voltage side ). when another person uses an adjacent channel to perform communication from a close place , the communication is input as an interference signal to the rf - signal input terminal 22 . thus , the strength signal is at high level . when the interference signal is not input to the rf - signal input terminal 22 , the strength signal is at low level . therefore , by using the level of the strength signal being referred to at the time t 1 in the non - receiving slot , it is possible to determine whether interference occurs . the operation of the digital - signal forming circuit , when the strength signal is at low level ( no interference ), is described below . in this case , the selection signal is unchanged to be at low level , and the selection switch 8 selects the fixed contact a ( the average - reference - voltage side ). at the time t 2 , the make - and - break switch 3 is closed by changing the make - and - break signal to be at high level . at the time t 4 , the make - and - break switch 3 is opened by changing the make - and - break signal to be at low level . at the time t 3 at which the receiving slot starts , the if signal modulated using a synchronizing signal sy is input to the demodulator 1 , and a demodulated signal sf is output from the demodulator 1 . the demodulated signal sf is supplied to the non - inverting input of the comparator 2 , and is supplied to the average - reference voltage unit 4 via the make - and - break switch 3 , so that the demodulated signal sf is converted into an average reference voltage vf . the average reference voltage vf is supplied to the inverting input of the comparator 2 , and a synchronizing signal sy shaped into rectangular waves are output from the comparator 2 . successively , at the time t 4 , the if signal , modulated using communication data sd instead of the synchronizing signal , is input to the demodulator 1 , and the make - and - break switch 3 is simultaneously opened , so that the demodulated signal sf is not supplied to the average reference voltage unit 4 . the average reference voltage vf stored in the capacitor 14 is supplied to the inverting input of the comparator 2 , and the communication data sd shaped into rectangular waves are output from the comparator 2 . the synchronizing signal sy and the communication data sd are supplied to the digital - signal output terminal 23 and the controller 6 . finally , the receiving slot ends at the time t 5 . the operation of the digital - signal forming circuit , when the strength signal is at high level ( i . e ., interference occurs ), is described below . in this case , the make - and - break signal is unchanged to be at low level , and the make - and - break switch 3 is continuously opened . the selection switch 8 is switched to the fixed contact b ( the fixed - reference - voltage side ) by changing the selection signal at the time t 2 to be at high level . at the time t 5 , by changing the selection signal to be at low level , the selection switch 8 is switched to the fixed contact a ( the average - reference - voltage side ). accordingly , during the receiving slot from the time t 3 to the time t 5 , a fixed reference voltage vc is supplied to the inverting input of the comparator 2 , and the synchronizing signal sy and the communication data sd , shaped into rectangular waves , are output from the comparator 2 to the the digital - signal output terminal 23 and the controller 6 .