the following description of the preferred embodiment ( s ) is merely exemplary in nature and is in no way intended to limit the invention , its application , or uses . for purposes of clarity , the same reference numbers will be used in the drawings to identify similar elements . as used herein , the term module and / or device refers to an application specific integrated circuit ( asic ), an electronic circuit , a processor ( shared , dedicated , or group ), and memory that execute one or more software or firmware programs , a combinational logic circuit , and / or other suitable components that provide the described functionality . for purposes of clarity , the same reference numerals will be used to identify similar elements . references to logical 1 , true , and on are equivalent to each other , and references to logical 0 , false , and off are equivalent to each other , unless otherwise noted . parts or all of the invention may also be implemented with equivalent embodiments using logic that is inverted from that disclosed . referring now to fig3 , an output port circuit 40 is shown . the output port circuit 40 is connected to the bias resistor 18 by the communication cable 14 . an output port 42 provides an output signal having a predetermined slew rate . a delay setting module 43 programmably sets slew rate by applying a delay signal to a delay time input 44 . the delay setting module 43 may program all of the delay modules individually to two or more delay values and / or collectively to a common delay value . 1 to n conductors may be used to connect the delay setting module to the delay to the delay cells 46 . in some implementations , the delay time input 44 may be a 3 - bit wide parallel binary input providing 2 3 = 8 unique slew rates . cascaded delay cells 46 - 1 , 46 - 2 , . . . , 46 - n , referred to collectively as the cascaded delay cells 46 , each receive the delay signal . each of the cascaded delay cells 46 has an input 48 - 1 , 48 - 2 , . . . , 48 - n , referred to collectively as the data inputs 48 , that receive a data bit . each of the cascaded delay cells 46 also has a delayed data output 50 - 1 , 50 - 2 , . . . , 50 - n , referred to collectively as the delayed data outputs 50 . each of the data inputs 48 - 2 through 48 - n is connected to a delayed data output 50 - 1 , 50 - 2 , 50 -( n − 1 ) of the preceding cascaded delay cell 46 . the data input 48 - 1 of the first cascaded delay cell 46 - 1 receives a data bit from an associated computing device 12 . each cascaded delay cell 46 propagates its data bit from its input 48 to its delayed data output 50 after the delay time . therefore , the data bit applied to the first input 48 - 1 propagates to the last delayed data output 50 - n after n multiples of the delay time . in a preferred embodiment , n = 8 and each cascaded delay cell 46 provides a delay time between about 125 picoseconds and 375 picoseconds . the preferred embodiment thereby provides a slew rate adjustable between about 1 nanosecond and 3 nanoseconds , although other delay ranges can be used . an output enable line 52 is active high and connected to a plurality of predrivers 54 - 1 , 54 - 2 , . . . , 54 - n , referred to collectively as the predrivers 54 . each of the predrivers 54 has a data input connected to the delayed data output 50 of a respective one of the cascaded delay cells 46 . each of the predrivers 54 implements a truth table , described later herein . the truth table uses the output enable line 52 and the delayed data output 50 to generate four output signals . the four output signals are communicated over output lines 56 - 1 , 56 - 2 , . . . , 56 - n , referred to collectively as output lines 56 , of each respective predriver 54 . the output lines 56 of each predriver 54 are connected to a respective driver 58 - 1 , 58 - 2 , . . . , 58 - n , referred to collectively as the drivers 58 . each of the drivers 58 has an input for a reference current signal 60 and a driver output port 62 . the driver output ports 62 are connected in parallel to form the output port 42 . when the output enable line 52 is high , a data bit propagates through the cascaded delay cells 46 and causes the driver output ports 62 to turn on or off in succession . as each output port 62 turns on or off , a magnitude of a signal appearing at the output port 42 increases or decreases , respectively , thereby providing a predetermined slew rate . turning now to fig4 , a partial schematic diagram is shown of the output port circuit 40 . the three lines of delay time input 44 are shown individually as 44 - 1 , 44 - 2 , and 44 - 3 . the delay time input 44 is connected to a digital - to - analog converter ( current dac ) 63 . a current output of the dac 63 is applied to a bias voltage generator 64 . the dac 63 receives the delay signal and converts it to a current as is described later . the bias voltage generator 64 converts the current to a positive bias voltage 66 and a negative bias voltage 68 . the positive and negative bias voltages 66 , 68 are applied to each of the cascaded delay cells 46 . the cascaded delay cells 46 use the positive and negative bias voltages 66 , 68 to operate internal circuitry as described later . circuitry of the drivers 58 will now be described . for the purpose of clarity , only the driver 58 - n will be described . the four output signals 56 from the predriver 54 are connected to an h - bridge . an output signal pp is connected to a gate of a pfet q 5 . an output signal np is connected to a gate of an nfet q 6 . an output signal nn is connected to a gate of an nfet q 7 . an output signal pn is connected to a gate of a pfet q 8 . a source of the nfet q 6 is connected to a source of the nfet q 7 . a source of the pfet q 5 is connected to a source of pfet q 8 . a drain of the nfet q 6 is connected to a drain of the pfet q 5 and provides a negative node of the driver output port 62 . a drain of the nfet q 7 is connected to a drain of the pfet q 8 and provides a positive node of the driver output port 62 . an nfet q 9 is configured as a current mirror and has a drain connected to the sources of the nfets q 6 and q 7 . a pfet q 10 is configured as a current mirror and has a drain connected to the sources of the pfets q 5 and q 8 . a current source is formed from nfets q 11 , q 12 , and a pfet q 13 . a gate and a drain of the nfet q 11 are connected to the reference current source 60 and a gate of the nfet q 12 . a source of the nfet q 11 is connected to a source of the nfet q 12 . a drain of the nfet q 12 is connected to a drain and a gate of the pfet q 13 . the sources of the nfets q 11 and q 12 are connected to a source of each nfet q 9 in the drivers 58 . a source of the pfet q 13 is connected to a source of each pfet q 10 in the drivers 58 . the nfet q 12 and the pfet q 13 mirror the reference current signal 60 flowing through the nfet q 11 and provide current to the drivers 58 . the nfet q 9 and pfet q 10 assure that the driver circuit output has a predetermined source impedance substantially free from influences resulting from process variations in manufacturing the nfets and pfets . turning now to fig5 , a truth table 70 is shown . the truth table 70 has a first input column for the delayed data bit appearing at the delayed data output 50 . a second input column is has a state of the output enable ( oe ) line 52 . four predriver output columns are provided , one for each of the predriver output signals pp , nn , pn , and np . entries in the four columns parenthetically indicate whether the associated pfet or nfet q 5 - q 8 is turned on or turned off . a rightmost output column indicates a logic state appearing at the driver output port 62 . the oe line 52 is a active high signal . when the oe line 52 is low , or zero , the pfets and nfets q 5 - q 8 are turned off and the driver output port 62 is electrically open ( 3 - state ). when the oe line 52 is high and the delayed data bit is low , or logical 0 , the pfet q 5 and the nfet q 7 are turned off , and the pfet q 8 and the nfet q 6 are turned on . this combination results in a logical 0 appearing at the driver output port 62 . when the oe signal is high and the delayed data bit is high , or logical 1 , the pfet q 5 and the nfet q 7 are turned on , and the pfet q 8 and the nfet q 6 are turned off . this combination results in a logical 1 appearing at the driver output port 62 . conventional combinatorial logic may be used to implement the truth table 70 in each of the predrivers 54 . turning now to fig6 , a schematic diagram is shown of the current dac 63 and the bias voltage generator 64 . the current dac 63 has an operational transconductance amplifier ( ota ) with an output connected to gates of pfets q 14 , q 15 , q 16 , q 17 , and q 18 . an inverting input 74 of the ota 72 is connected to a constant voltage source vref . a non - inverting input 76 of the ota 72 is connected to a drain of the pfet q 14 and to one end of a resistor 65 . the other end of the resistor 65 is connected to the reference voltage vss . the output of the ota 72 provides a current proportional to a voltage difference across the non - inverting 74 and inverting 76 inputs . a drain of the pfet q 15 is connected to the supply voltage vdd and to the drains of the pfets q 15 , q 16 , and q 18 . the three lines of the delay time input 44 are connected to gates of pfets q 19 , q 20 , and q 21 , respectively . a source of the pfet q 19 is connected to a drain of the pfet q 15 . a source of the pfet q 20 is connected to a drain of the pfet q 16 . a source of the pfet q 21 is connected to a drain of the pfet q 17 . drains of the pfets q 18 - q 21 are connected together and provide a programmable current output 78 . operation of the current dac 63 will now be described . the pfet q 14 mirrors a current provided by the output of the ota 72 . a magnitude of the current is established by adjusting a resistance of the resistor 65 . when the pfet q 19 is turned on by the first delay time input line 44 - 1 , the pfet q 15 mirrors the current flowing through the pfet q 14 . when the pfet q 20 is turned on by the second delay time input line 44 - 2 , the pfet q 16 mirrors the current flowing through the pfet q 14 . when the pfet q 21 is turned on by the third delay time input line 44 - 3 , the pfet q 17 mirrors the current flowing through the pfet q 14 . as the number of pfets q 19 - q 21 being turned on by the delay time input lines 44 increases , an increasing current flow is established through the programmable current output 78 . the sizes of pfets q 15 - q 18 can be unequal to provide up to eight discrete levels of current flow through the programmable current output 78 in accordance with delay time input lines 44 turning on / off the pfets q 19 , q 20 , and q 21 . in the bias voltage generator 64 , the current flow from the programmable current output 78 is applied to a drain and a gate of an nfet q 22 . a source of the nfet q 22 is connected to the reference voltage vss , a source of an nfet q 23 , and a source of an nfet q 24 . a drain of the nfet q 23 is connected to a drain and a gate of a pfet q 25 . a source of the pfet q 25 is connected to the voltage source vdd . a drain and a gate of the nfet q 24 are connected to a drain of a pfet q 26 . a gate of the pfet q 26 is connected to the gate and the drain of the pfet q 25 . a source of the pfet q 26 is connected to the supply voltage vdd . the drain of the pfet q 25 provides the positive bias voltage 66 , and the drain of the nfet q 24 provides the negative bias voltage 68 . operation of the bias voltage generator 64 will now be described . the current flow from the programmable current output 78 is mirrored by the nfet q 22 . the nfet q 23 mirrors the current flowing through the nfet q 22 . the pfet q 25 drops a voltage across its source and drain as it mirrors the current flowing through the nfet q 23 . the drain of the pfet q 25 thereby provides the positive voltage 66 with vdd less the voltage dropped across pfet q 25 . the pfet q 26 mirrors the current flowing through the pfet q 25 . the nfet q 24 drops a voltage across its source and drain as it mirrors the current flowing through the pfet q 26 . the drain of the nfet q 24 thereby provides the negative voltage 68 with a voltage equal to its source - drain voltage drop . the positive 66 and negative 68 bias voltages are applied to the delay cells 46 . turning now to fig7 , a schematic diagram of a delay cell 46 is shown . a source of a pfet q 27 is connected to the supply voltage vdd . a gate of the pfet q 27 is connected to the positive bias voltage 66 . a drain of the pfet q 27 is connected to a source of a pfet q 28 . a gate of the pfet q 28 is connected to the data bit input 48 of the delay cell 46 . a drain of the pfet q 28 is connected to a drain of an nfet q 29 , to one end of a capacitor c 1 , and to an input of an inverter 80 . the other end of the capacitor c 1 is connected to the reference voltage vss . a source of the nfet q 29 is connected to a drain of an nfet q 30 . a gate of the nfet q 29 is connected to the data bit input 48 of the delay cell 46 . a source of the nfet q 30 is connected to the reference voltage vss . a gate of the nfet q 30 is connected to the negative bias voltage 68 . an output of the inverter 80 provides the delayed data output 50 . operation of the delay cell 46 will now be described . a magnitude of the positive 66 and negative 68 bias voltages establishes drain - source resistances of the pfet q 27 and the nfet q 30 . if a logical 1 is applied to the data bit input 48 , the pfet q 28 turns off and the nfet q 29 turns on , thereby allowing the capacitor c 1 to discharge through the nfets q 29 and q 30 . a rate of discharge is determined by the magnitude of the negative bias voltage 68 . with the capacitor c 1 discharged , a logical 0 appears at the input of the inverter 80 and a logical 1 appears at the output of the inverter 80 . the rate of discharge determines the delay time for the delay cell 46 . alternatively , if a logical 0 is applied to the data bit input 48 , the nfet q 29 turns off and the pfet q 28 turns on , thereby allowing the capacitor c 1 to charge through the pfets q 27 and q 28 . a rate of charge is determined by the magnitude of the positive bias voltage 66 . when capacitor c 1 is charged , a logical 1 appears at the input of the inverter 80 and a logical 0 appears at the output of the inverter 80 . the rate of charge is preferably equal to the rate of discharge . turning now to fig8 , waveforms are shown for an example output port circuit 40 having n = 8 cascaded delay cells 46 , predrivers 54 , and drivers 58 . a horizontal axis of each plot indicates time in nanoseconds and a vertical axis of each plot represents volts . the column of plots at a left side of fig8 shows waveforms for a rising edge at the output port 42 caused by a logical 1 being applied to the data input 48 - 1 while the oe input 52 is high . a plot 82 shows a set of time correlated curves 84 representing the output signals nn from the predrivers 54 . each output signal nn begins rising after its associated cascaded delay cell 46 propagates the logical 1 data bit . a plot 86 shows a set of time correlated curves 88 representing the output signals pp from the predrivers 54 . each output signal pp begins falling after its associated cascaded delay cell 46 propagates the logical 1 data bit . a plot 90 shows a set of time correlated curves 92 representing the output signals np from the predrivers 54 . each output signal np begins falling after its associated cascaded delay cell 46 propagates the logical 1 data bit . a plot 94 shows a set of time correlated curves 96 representing the output signals pn from the predrivers 54 . each output signal pn begins rising after its associated cascaded delay cell 46 propagates the logical 1 data bit . a plot 98 shows a signal voltage 100 rising at a controlled slew rate in unison with each driver output port 62 applying the logical 1 date bit to the output port 42 . the signal voltage 100 rises as the drivers 58 activate in succession according to the output signals nn , pp , np , and pn . the column of plots at a right side of fig8 shows waveforms for a falling edge at the output port 42 caused by a logical 0 being applied to the data input 48 - 1 while the oe input 52 is high . a plot 102 shows a set of time correlated curves 104 representing the output signals nn from the predrivers 54 . each output signal nn begins falling after its associated cascaded delay cell 46 propagates the logical 0 data bit . a plot 106 shows a set of time correlated curves 108 representing the output signals pp from the predrivers 54 . each output signal pp begins rising after its associated cascaded delay cell 46 propagates the logical 0 data bit . a plot 110 shows a set of time correlated curves 112 representing the output signals np from the predrivers 54 . each output signal np begins rising after its associated cascaded delay cell 46 propagates the logical 0 data bit . a plot 114 shows a set of time correlated curves 116 representing the output signals pn from the predrivers 54 . each output signal pn begins falling after its associated cascaded delay cell 46 propagates the logical 0 data bit . a plot 118 shows a signal voltage 120 falling at a controlled slew rate in unison with each driver output port 62 applying the logical 0 data bit to the output port 42 . the signal voltage 120 falls as the drivers 58 activate in succession according to the output signals nn , pp , np , and pn . a time between each successive rising edge and / or each successive falling edge in the families of curves is equal to the delay time of the cascaded delay cells 46 . turning now to fig9 , families of waveforms are shown for the example output port circuit 40 having n = 8 cascaded delay cells 46 , predrivers 54 , and drivers 58 . each of the cascaded delay cells 46 provide the delay time in accordance with the delay time signal 44 . a horizontal axis of each plot indicates time in nanoseconds and a vertical axis of each plot represents volts . a plot 122 shows a family of eight rising edge waveforms 124 . each rising edge waveform is generated at the output port 42 with the cascaded delay cells 46 using a different one of eight discrete delay times . it can be seen from the family of rising edge waveforms 124 that increasing the delay time decreases the slew rate of the output port 42 . a plot 126 shows a family of eight falling edge waveforms 128 . each falling edge waveform is generated at the output port 42 with the cascaded delay cells using a different one of the eight discrete delay times . it can be seen from the family of rising edge waveforms 124 that decreasing the delay time increases the slew rate of the output port . those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms . therefore , while this invention has been described in connection with particular examples thereof , the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings , the specification and the following claims .