both the bridgeless power factor controller and the grid connected inverter are converters connected to the power grid . fig1 shows the general topology of the converter . s 1 , s 2 , s 3 , and s 4 are general power semiconductors . without losing generosity , they are drawn as ideal switches with anti - paralleled diodes . they can be mosfet , or igbt , or diode , whichever applicable . the ac source vac is the voltage source with a stable rms voltage level and a fixed frequency . lac 1 and lac 2 are the interface inductors . c is the dc side bulk capacitor . the dc side voltage vdc is to be regulated . in either power factor controller or inverter . vdc must be regulated to a constant value . the ac side current must be a sinusoidal waveform with the same phase angle as the ac voltage . the only difference is that the current sense polarity of a power factor controller is the reverse of an inverter . in the following description , the reversal of the polarity is not explicitly emphasized . it is implied that whenever a power factor controller is mentioned , the current polarity is defined as positive if the current flows from the ac side to the dc side ; and whenever an inverter is mentioned , the current polarity is defined as positive if the current flows from the dc side to the ac side . the control of the general converter as shown in fig1 includes two steps . the first step is to find out the ac side current reference , a ‘ sample based controller ’ is disclosed as an effective and easy - to - implement controller . the second step is to find a way to let the actual ac current follow the current reference as quickly as possible , a new current mode switching pattern is disclosed to improve the waveform and reduce the losses . since the ac side current has to be in phase with the ac voltage , it is straightforward to make the ac current reference to be proportional to the ac voltage . the difficult part is how to derive the proportion coefficient , which determines the magnitude of the current . the magnitude of the current determines the amount of power being delivered . so the coefficient is supposed to be derived from the power requirement . in voltage source converter , the variation in the dc side voltage ( vdc in fig1 ) reflects the relationship between ac side power and dc side power . v sc ( t )=√{ square root over ( 2 )} v rms sin ( ω t ) ( 1 ) where vac is the ac side voltage as shown in fig1 ; in steady state operation of the power factor controller , the current direction is from the ac side to the dc side , with the same phase angle of the ac voltage . assume the rms value of the current being irms , so i ac ( t )=√{ square root over ( 2 )} i rms sin ( ω t ) ( 2 ) where iac is the ac side current as shown in fig1 , with the direction from the ac side to the dc side . assume under steady state , the dc side voltage is vdc and dc side current is idc , as shown in fig1 . neglect the losses in the semiconductors , the inductor , and the wiring . the following set of power balance equations can be written . where pac ( t ) is the ac side instantaneous power ; pdc is the dc side power , which is a constant ; el ( t ) is the total energy stored in the inductors lac 1 and lac 2 ; ec ( t ) is the energy stored in the capacitor c ; lac 1 , lac 2 , and c are the inductors and the dc side capacitor in fig1 . from equations ( 1 )˜( 7 ), the dc side voltage can be derived as when δp = 0 , vdc 0 is the rms value of vdc . when δp = 0 , vdc ( t ) varies periodically at double of the line frequency . when δp & gt ; 0 , vdc ( t ) will ramp up when δp & gt ; 0 , vdc ( t ) will ramp down in practical , q 1 & lt ;& lt ; pdc . so when δp = 0 , vdc ( t ) reaches vdc 0 almost at the same time when the ac side voltage reaches zero . fig2 ( a ) shows the waveforms of the ac side voltage and current ; fig2 ( b ), ( c ) and ( d ) show the dc side voltage waveform when δp = 0 , δp & gt ; 0 and δp & lt ; 0 , respectively . the trend lines are drawn by connecting vdc ( t ) only at the moments of ac voltage zero - crossing points . the derivation of the ac side current reference is based on the above analysis and the results shown in fig2 . the control diagram is shown in fig3 . the current reference iacref is the product of the ac side voltage and a coefficient k . the coefficient k is derived from δvdc , which is the difference between the dc voltage reference and the actual dc voltage . the key point is that k is updated only at the zero crossing points of the ac input voltage . the controller which derives k is called ‘ sample based controller ’, because it updates k once every half cycle . the ‘ sample based controller ’ block in fig3 can be implemented either in hardware or in software . fig4 shows a hardware implementation example . in fig4 , the ‘ zero - crossing of vac ’ signal is from the ‘ zero - crossing detector ’ block in fig3 . it is a square waveform . both rising and falling edges indicate a zero - crossing point of the ac voltage . the ‘ signal conditioning ’ block in fig4 transforms the waveform into a pulsed logic signal . the signal is normally at low level . the rising and / or falling edges of the zero - crossing signal will trigger the logic signal to be high level for a short period of time , which is enough to activate the downstream sample / hold circuit . the pulse duration is in the order of micro - seconds . ‘ sample / hold 1 ’ and ‘ sample / hold 2 ’ blocks are used to get the new δvdc value and to keep the last δvdc value . it is important to have the ‘ delay 1 ’ block , so that the last δvdc value can be reliably sampled through ‘ sample / hold 2 ’ block , to become ‘ δvdc , old ’ signal . so the timing of ‘ delay 1 ’ block should be designed to make sure that the starting of the sample period of ‘ sample / hold 1 ’ is after the completion of the sample period of ‘ sample / hold 2 ’. k p , k d and k i are gain blocks . this gives the options of using any one or any combinations of p , i , or d controller . ‘ δvde , new ’ is the present difference between the dc voltage reference and the actual dc voltage . this signal , is fed to gain block k p directly for proportional controller output . the summing block ‘ sum 1 ’ takes ‘ δvdc , new ’ and ‘ δvdc . old ’ as inputs , with ‘ δdc , new ’ being positive , and ‘ δvdc , old ’ being negative . the result is fed to gain block k d for differential controller output . it is important to have delay block ‘ delay 2 ’ and sample / hold block ‘ sample / hold 3 ’ for a functional integrator . ‘ sample / hold 3 ’ is used as a memory of the integration result from the last time . the zero - crossing signal will trigger ‘ sample / hold 3 ’ block to feed the old integration value to one input of the summing block ‘ sum 2 ’. the other input of ‘ sum 2 ’ block is ‘ δvdc , new ’, so the output of ‘ sum 2 ’ is the new integration result . the ‘ delay 2 ’ block is important to prevent the output , of ‘ sample / hold 3 ’ block from changing . the timing of the delay block is a little longer than the completion of sample period of ‘ sample / bold 3 ’ block . in this way , the output of ‘ delay 2 ’ block will remain unchanged for the rest of the half cycle , until the next zero - crossing of the ac voltage . finally , the output is the coefficient k , which is the sum of p , i and d controllers . since the output is updated once every half cycle , it is actually a discrete pid controller with sample time being half of the line cycle . in fig3 and 4 , all functional blocks are simple analog circuits . fig3 and 4 form the block diagram of a complete integrated circuit . the circuit can greatly reduce the development cycle of the system , improve the reliability , and lower the system cost . the ‘ sample based controller ’ block in fig3 can also be implemented in software . fig5 shows a software flowchart example . in the initialization part , the gain values of k p , k d and k i are given . all the inputs and outputs are cleared to 0 . there should be software limits for the integrator output i and the overall output k . set both edges of zero - crossing signal to be interruptable . once a zero - crossing event happens , the interrupt part of the software is executed . in the interrupt software , the outputs of p , i and d controllers are calculated separately and then added up together to get the overall output k . with this method , only a low profile microcontroller is required , due to the low memory requirement , short execution time , and low interrupt frequency . the basis of the new switching pattern is the hysteretic control , in the conventional hysteretic switching pattern , the switches are controlled in pairs . fig5 shows the current flow of an inverter during positive half cycle of the ac voltage . refer to fig1 , s 1 and s 4 are always switched on and off at the same time ; s 2 and s 3 are switched on and off at the same time . whenever s 1 and s 4 are on , s 2 and s 3 must be off and vice versa . the logic is simple . however , there are two main disadvantages in this pattern . firstly , a deadtime has to be inserted during the commutation between s 1 and s 2 , and also between s 3 and s 4 , to avoid the risk of shoot - through . secondly , all the switches are commutated once in each switching cycle , which is not necessary and increases the losses . the idea of the disclosed switching pattern is to reduce the number of switching events . in each half line cycle , only one switch is in pwm mode for both pfc circuit and the inverter . the current flow for positive and negative half cycles of one switching pattern example for bridgeless pfc is shown in fig7 and fig8 , respectively . for a bridgeless pfc circuit , there are two diode and two controllable switches . in the positive half cycle , s 2 is in pwm mode and s 4 is kept off . in the negative half cycle , s 2 is kept off and s 4 is in pwm mode . let a logical variable h represent the sign of the ac side voltage , i . e ., define a hysteretic band δi ( δi & gt ; 0 ). let a logical variable s represent the relationship between the actual current and the current reference as follows : s is not changed when iac is between ( iacref − δi ) and ( iacref + δi ). according to fig7 and fig8 , the switching logic equations of the switches can be written as ; where h and s are the logic inverse of h and s , respectively . the current flow for positive and negative half cycles of one switching pattern example for the inverter is shown in fig9 and fig1 , respectively . for an inverter , there has to be four controllable switches . note fig9 and 10 have the same current path as in fig7 and 8 , except ; the reversal in the direction . in the positive half cycle , s 1 is in pwm mode , s 2 and s 3 are kept off , and s 4 is kept on . in the negative half cycle , s 1 is kept off , s 2 is kept on , s 3 is in pwm mode , and s 4 is kept off . the switching logic equations are : this method can be recombined to get up to four different switching patterns , due to the symmetric nature of the converter . another example is shown in fig1 ˜ 14 for another kind of current flow . for the power factor controller , instead of using s 1 and s 3 to be diodes , in this example , s 1 and s 2 are diode . for the inverter , instead of doing pwm on s 1 and s 3 , in this example , s 3 and s 4 are in pwm mode . the resulting switching logic equations for the power factor controller are : other combinations in power factor controllers include choosing s 3 and s 4 as diodes , or s 2 and s 4 as diodes . when s 3 and s 4 are diodes in power factor controllers , the switching logic equations are : the corresponding switching logic equations for the inverter with the same current path are : when s 2 and s 4 are diodes in power factor controllers , the switching logic equations are : the corresponding switching logic equations for the inverter with the same current path are : the switching pattern is based on hysteresis comparison and simple logics , so it can be integrated into one integrated circuit . one implementation example is shown in fig1 . the inputs to the circuit include the ac side voltage vac , the ac current reference iacref which is derived from the first step , the measured ac current iac , and the optional external setting ‘ hysteresis band setting ’. the outputs are the switching signals . since there are so many combinations , the outputs are designed to be suitable for ail combinations . for power factor controllers , the output ‘ h ’ and ‘ h ’ are not used . under this kind of switching pattern , for the bridgeless power factor controller , each controllable switch is in pwm mode for half cycle and in fully on mode for the other half cycle . for the grid connected inverter , one pair of the switches are switched at line frequency only . the other pair of the switches are in pwm mode for half cycle and in off mode for the other half cycle . all unnecessary switching events have been removed . this feature reduces the gate drive loss , which is a considerable reduction in the control power dissipation . there is no risk of shoot - through , so no deadtime is required . this is an important benefit , it not only improves the waveform by removing the distortion caused by the deadtime , but also improves the reliability . finally , the two steps can be combined into one integrated circuit , as shown in fig1 . fig1 ( a ) shows the top level block , diagram which is a combination of fig3 and fig1 . fig1 ( b ) shows the detail implementation of the ‘ sample based controller ’ block , which is the same as in fig4 . while exemplary embodiments described hereinabove , it should be recognized that these embodiments are provided for illustration and are not intended to be limitative . any modifications and variations , which do not depart from the spirit and scope of the invention , are intended to be covered herein .