a first embodiment of the present invention will be described with reference to fig1 . the voltage generating circuit of the present invention will be described by taking a voltage generating unit possessed by a flash memory as an example . fig1 is a block diagram showing the structure of a voltage generating portion 1 of the flash memory . the voltage generating portion 1 includes a first charge pump circuit 10 , a second charge pump circuit 20 , a regulation circuit 30 and a selection circuit 40 . a first charge pump circuit 10 includes a first buffer circuit 11 and a first pumping circuit 15 . the first buffer circuit 11 is connected to a control circuit and an oscillation circuit ( not shown ). further , the first buffer circuit 11 is connected to a voltage detecting circuit 50 . the first pumping circuit 15 is connected to an external power supply line l 1 via an input terminal ( in 1 ). according to this embodiment , the value of the external power supply voltage is set to 1 . 8 v or 3 v . the output of the first pumping circuit 15 is connected to an output terminal ( out 1 ). in the meantime , the external power supply whose voltage value is 1 . 8 v corresponds to a first external power supply of the present invention . the external power supply whose voltage value is 3 v corresponds to a second external power supply of the present invention . according to this embodiment , the voltage generating portion 1 includes three second charge pump circuits 20 a , 20 b , 20 c . the second charge pump circuit 20 a has a second buffer circuit 21 and a second pumping circuit 25 a . the second charge pump circuit 20 c has a second buffer circuit 21 and a second pumping circuit 25 c . the input of each second buffer circuit 21 is connected to the control circuit and the oscillation circuit . the output of a level converting circuit 22 possessed by each of the second buffer circuit 21 is connected to the input of the second pumping circuit 25 a , the input of the second pumping circuit 25 b and the input of the second pumping circuit 25 c . a second pumping circuit 25 a of the second charge pump circuit 20 a is connected to an internal power supply line l 2 via an input terminal ( in 2 ). the output of the second pumping circuit 25 a is connected to an output terminal ( out 2 ). the second pumping circuit 25 c of the second charge pump circuit 20 c are connected to the internal power supply line l 2 via an input terminal ( in 3 ). the output of the second pumping circuit 25 c is connected to an output terminal ( out 4 ). the second charge pump circuit 20 b includes a second buffer circuit 21 and a second pumping circuit 25 b . the second buffer circuit 21 of the second charge pump circuit 20 b is constructed in the same way as the second buffer circuit 21 of the second charge pump circuits 20 a , 20 c . the input of the second buffer circuit 21 of the second charge pump circuit 20 b is connected to the oscillation circuit and the control circuit . the output of the level converting circuit 22 of the second buffer circuit 21 is connected to the input of the second pumping circuit 25 b . the second pumping circuit 25 b is connected to the ground via an input terminal ( in 4 ). the output of the second pumping circuit 25 b is connected to an output terminal ( out 3 ). the input of a regulation circuit 30 a is connected to the output terminal ( out 2 ) of the second charge pump circuit 20 a . the output of the regulation circuit 30 a is connected to a word line wl . the input of a regulation circuit 30 b is connected to the output terminal ( out 3 ) of the second charge pump circuit 20 b . the output of the regulation circuit 30 b is connected to the word line wl . the input of a regulation circuit 30 c is connected to the output terminal ( out 4 ) of the second charge pump circuit 20 c . the output of the regulation circuit 30 c is connected to a bit line bl . the selection circuit 40 includes an input terminal ( in 5 ), an input terminal ( in 6 ), a switch sw , terminals t 1 , t 2 and an output terminal ( out 5 ). the input terminal ( in 5 ) is connected to the output terminal ( out 1 ) of the first charge pump circuit 10 . further , the input terminal ( in 5 ) is connected to the terminal t 1 . the terminal t 2 is connected to the external power supply line l 1 via the input terminal ( in 6 ). the switch sw is connected to the voltage detecting circuit 50 and the output terminal ( out 5 ). the output terminal ( out 5 ) is connected to the internal power supply line l 2 . next , the operation of the voltage generating portion 1 of the first embodiment will be described . first , an operation in case that the voltage detecting circuit 50 detects that the value of the external power supply voltage is 1 . 8 v will be described . according to this embodiment , if the voltage detecting circuit 50 detects that the value of the external power supply voltage is 1 . 8 v , the voltage detecting circuit 50 outputs a high level selection signal chn 1 to the switch sw of the selection circuit 40 . when the switch sw receives the high level selection signal chn 1 , it is connected to the terminal t 1 . at the same time , the voltage detecting circuit 50 outputs the high level selection signal chn 1 to the first buffer circuit 11 of the first charge pump circuit 10 . in the meantime , the selection signal chn 1 corresponds to the voltage selection command signal of the present invention . according to this embodiment , if a first operation clock signal clk 1 having an amplitude of 1 . 8 v is inputted to the first buffer circuit 11 by the oscillation circuit and a high level control signal en 0 is inputted to the first buffer circuit 11 by the control circuit , the first buffer circuit 11 outputs the first operation clock signal clk 1 having an amplitude of 1 . 8 v to the first pumping circuit 15 . in the meantime , the first operation clock signal clk 1 corresponds to a first clock signal of the present invention and 1 . 8 v corresponds to a first voltage level of the invention . when the first operation clock signal clk 1 is inputted to the first pumping circuit 15 , the first pumping circuit 15 starts voltage pumping operation . according to this embodiment , the first pumping circuit 15 is constructed of a capacity parallel connection type charge pump in which voltage pumping capacitors are connected through a plurality of stages . in the charge pump , a voltage pumping stage is formed of each voltage pumping capacitor . the first pumping circuit 15 is supplied with an external power supply voltage of 1 . 8 v by the external power supply line l 1 so as to accumulate electric charges in the voltage pumping capacitor on a first stage . after that , in the first pumping circuit 15 , a voltage of 1 . 8 v is supplied to the voltage pumping capacitor via the control terminal connected to the voltage pumping capacitor on the first stage by the first operation clock signal clk 1 . as a consequence , electric charges are accumulated in the voltage pumping capacitor on the first stage so that voltage between both ends of the capacitor rises . subsequently , the electric charges accumulated in the voltage pumping capacitor on the first stage is supplied to the voltage pumping capacitor on a next stage . then , like the voltage pumping capacitor on the first stage , the voltage of 1 . 8 v is supplied to the voltage pumping capacitor on the next stage by the first operation clock signal clk 1 . consequently , in the first pumping circuit 15 , the voltage between both ends of the voltage pumping capacitor is raised step by step by the plurality of the voltage pumping capacitors , so that the voltage of 1 . 8 v is raised toward the voltage of near 3 v gradually . according to this embodiment , voltage pumping interval of 1 . 8 v corresponds to a first voltage of the invention . if a low level control signal en 0 is inputted to the first buffer circuit 11 by the control circuit , the first buffer circuit 11 does not output the first operation clock signal clk 1 to the first pumping circuit 15 . as a consequence , the first pumping circuit 15 stops its voltage pumping operation . the first charge pump circuit 10 supplies a pumping voltage v 1 having a voltage value near 3 v to the selection circuit 40 . the pumping voltage v 1 undergoes subtraction / addition processing by a regulation circuit ( not shown ) so that the voltage value is adjusted to 3 v . because the pumping voltage v 1 is a result of pumping the voltage of 1 . 8 v to a voltage near 3 v by a plurality of the voltage pumping capacitors , it corresponds to a first precharge pumping voltage of the present invention . the pumping voltage v 1 is supplied to the internal power supply line l 2 via the input terminal ( in 5 ) of the selection circuit 40 , the terminal t 1 , the switch sw and the output terminal ( out 5 ). according to this embodiment , if the first operation clock signal clk 1 having an amplitude of 1 . 8 v is inputted to the second buffer circuit 21 of each of the second charge pump circuits 20 a - 20 c by the oscillation circuit and high level control signals en 1 a - en 1 c are inputted to the second buffer circuit 21 of each of the second charge circuits 20 a - 20 c by the control circuit , each of the level converting circuits 22 converts the first operation clock signal clk 1 to the second operation clock signal clk 2 having an amplitude of 3 v . in the meantime , 3 v corresponds to a second voltage level of the present invention . the level converting circuit 22 corresponds to a level converter of the present invention . the level converting circuit 22 outputs the second operation clock signal clk 2 having an amplitude of 3 v to each of the second pumping circuits 25 a - 25 c . in the meantime , the second operation clock signal clk 2 corresponds to a second clock signal of the present invention . when the second operation clock signal clk 2 is inputted to each of the second pumping circuits 25 a , 25 c , each of the second pumping circuits 25 a , 25 c starts its pumping operation . the second pumping circuits 25 a , 25 c are constructed of the capacity parallel connection type charge pump in which the pumping capacitors are connected through a plurality of stages . in the charge pump , the pumping stage is formed of each pumping capacitor . each of the second pumping circuits 25 a , 25 c is supplied with a voltage of 3 v by the internal power supply line l 2 , so as to accumulate electric charges in the pumping capacitor on the first stage . after that , in each of the second pumping circuits 25 a , 25 c , a voltage of 3 v is supplied to the pumping capacitor via the control terminal connected to the pumping capacitor on the first stage by the second operation clock signal clk 2 . as a consequence , electric charges are accumulated in the pumping capacitor on the first stage so that a voltage between both ends of the capacitor rises . after that , in each of the second pumping circuits 25 a , 25 c , a similar pumping operation as the first pumping circuit 15 is carried out so as to pump the voltage of 3 v to a voltage near 9 v . the second pumping circuit 25 a outputs a pumping voltage v 2 having a voltage value near 9 v to the regulation circuit 30 a via the output terminal ( out 2 ). the second pumping circuit 25 c outputs a pumping voltage v 3 having a voltage value near 9 v to the regulation circuit 30 c via the output terminal ( out 4 ). according to this embodiment , the pumping voltage v 2 and the pumping voltage v 3 correspond to the second precharge pumping voltage of the present invention . the pumping interval of 3 v corresponds to a second voltage of the invention . in the meantime , if low level control signals en 1 a , en 1 c are inputted to each of the second buffer circuits 21 by the control circuit , each of the second buffer circuits 21 does not output the second operation clock signal clk 2 to the second pumping circuits 25 a , 25 c . as a consequence , the second pumping circuits 25 a , 25 c stop each pumping operation . the regulation circuit 30 a carries out addition / subtraction processing on the pumping voltage v 2 so as to generate an adjustment voltage v 7 . after that , the regulation circuit 30 a supplies an adjustment voltage v 7 having a voltage value of 9 v to the word line wl . the regulation circuit 30 c carries out addition / subtraction on the pumping voltage v 3 so as to generate an adjustment voltage v 8 . after that , the regulation circuit 30 c supplies the adjustment voltage v 8 having a voltage value of 5 v to the bit line bl . in the second charge pumping circuit 20 b , when the second operation clock signal clk 2 is inputted to the second pumping circuit 25 b , the second pumping circuit 25 b starts its voltage - down operation . according to this embodiment , the second pumping circuit 25 b is constructed of capacity parallel connection type negative voltage charge pump in which voltage - down capacitors are connected in a plurality of stages . in the negative voltage charge pump , a voltage - down stage is formed of each voltage - down capacitor . in the second pumping circuit 25 b , a voltage of 3 v is supplied to the voltage - down capacitor by the second operation clock signal clk 2 via the control terminal connected to each voltage - down capacitor . in the second pumping circuit 25 b , the potential is lowered by each stage so that a voltage near − 9 v is generated . the second pumping circuit 25 b supplies a negative voltage v 4 having a voltage value near − 9 v to the regulation circuit 30 b via the output terminal ( out 3 ). in the meantime , when a low level control signal en 1 b is inputted to the second buffer circuit 21 by the control circuit , the second buffer circuit 21 does not output the second operation clock signal clk 2 to the second pumping circuit 25 b . as a consequence , the second pumping circuit 25 b stops the voltage - down operation . the regulation circuit 30 b carries out addition / subtraction processing on the negative voltage v 4 so as to generate an adjustment voltage v 9 . after that , the regulation circuit 30 b supplies the adjustment voltage v 9 having a voltage value of − 9 v to the word line wl at the time of erasing . on the other hand , when it is detected that the value of the external power supply voltage is 3 v by the voltage detecting circuit 50 , the following activity occurs . according to this embodiment , when the voltage detecting circuit 50 detects that the value of the external power supply voltage is 3 v , the voltage detecting circuit 50 outputs a low level selection signal chn 1 to the switch sw of the selection circuit 40 . the switch sw is connected to the terminal t 2 when it receives the low level selection signal chn 1 . at the same time , the voltage detecting circuit 50 outputs the low level selection signal chn 1 to the first buffer circuit 11 of the first charge pump circuit 10 . at this time , the first buffer circuit 11 does not output the first operation clock signal clk 1 to the first pumping circuit 15 . then , the first pumping circuit 15 carries out no voltage pumping operation and pumping voltage v 1 is not supplied to the selection circuit 40 . external power supply voltage v 11 having a voltage value of 3 v is supplied to the internal power supply line l 2 via the input terminal ( in 6 ), terminal t 2 , switch sw and output terminal ( out 5 ). the second pumping circuit 25 a carries out the above - described pumping operation so as to supply the pumping voltage v 2 to the regulation circuit 30 a through the output terminal ( out 2 ). further , the second pumping circuit 25 c carries out a similar pumping operation as the second pumping circuit 25 a so as to supply the pumping voltage v 3 to the regulation circuit 30 c via the output terminal ( out 4 ). the voltage - down operation of the second pumping circuit 25 b when the value of the external power supply voltage is 3 v is similar to the voltage - down operation of the second pumping circuit 25 b when the value of the external power supply voltage is 1 . 8 v . in this embodiment , the first operation clock signal clk 1 is inputted to the first pumping circuit 15 of the first charge pump 10 , the first pumping circuit 15 pumps up the external power supply voltage of 1 . 8 v toward the voltage near 3 v gradually by a plurality of voltage pumping capacitors . the first charge pump circuit 10 corresponds to a first charge pump unit of the present invention . pumping up the external power supply voltage of 1 . 8 v to the voltage near 3 v gradually using the first operation clock signal clk 1 corresponds to a first pumping step of the present invention . in this embodiment , the switch sw of the selection circuit 40 is connected to the terminal t 1 when it receives a high level selection signal chn 1 . consequently , the selection circuit 40 can select the pumping voltage v 1 supplied by the first charge pump circuit 10 . contrary to this , the switch sw of the selection circuit 40 is connected to the terminal t 2 when it receives the low level selection signal chn 1 . consequently , the selection circuit 40 can select the external power supply voltage v 11 of 3 v supplied via the terminal t 2 . therefore , the selection circuit 40 corresponds to a voltage selector of the present invention because the switch sw selects the pumping voltage v 1 or the external power supply voltage v 11 corresponding to the received selection signal chn 1 . selecting the pumping voltage v 1 corresponding to the high level selection signal chn 1 and selecting the external power supply voltage v 11 corresponding to the low level selection signal chn 1 corresponds to the voltage selection step of the present invention . further , converting the first operation clock signal clk 1 having an amplitude of 1 . 8 v to the second operation clock signal clk 2 having an amplitude of 3 v corresponds to a level converting step of the present invention . according to this embodiment , the second operation clock signal clk 2 is inputted to the second pumping circuits 25 a , 25 c of each of the second charge pump circuits 20 a , 20 c and then , the second pumping circuits 25 a , 25 c pump up the pumping voltage v 1 or the external power supply voltage v 11 selected by the selection circuit 40 toward a voltage near 9 v gradually by a plurality of pumping capacitors . therefore , the second charge pump circuits 20 a , 20 c correspond to a second charge pump unit of the present invention . pumping up the pumping voltage v 1 or the external power supply voltage v 11 toward a voltage near 9 v gradually using the second operation clock signal clk 2 whose voltage amplitude value is larger than the first operation clock signal clk 1 corresponds to a second pumping step of the present invention . an example of the flash memory having the voltage generating portion 1 of this embodiment will be described . in the meantime , the flash memory corresponds to a nonvolatile memory device of the present invention . in the voltage generating portion 1 of the flash memory , the control signals en 1 a - en 1 c are inputted to the second buffer circuit 21 of each of the second charge pumps 20 a - 20 c corresponding to the operation mode of the flash memory . when the flash memory is operated on program , erased or read ( including reading for verification of the program operation and erase operation ), the second charge pump circuit 20 a is activated with the control signal en 1 a . at the time of the program operation , the adjustment voltage v 7 having a voltage value of 9 v is supplied to the word line wl of the memory cell by the regulation circuit 30 a . at the time of the erase operation , the adjustment voltage v 7 is supplied to a well of the memory cell by the regulation circuit 30 a . at the time of read operation , the voltage value of the pumping voltage v 2 is adjusted to 4 v by the regulation circuit 30 a and the adjustment voltage v 7 having a voltage value of 4 v is supplied to the word line wl of the memory cell . in the meantime , the memory cell corresponds to a nonvolatile memory device of the present invention . at the time of erase operation , the second charge pump circuit 20 b is activated with the control signal en 1 b . at the time of erase operation , the adjustment voltage v 9 having a voltage value of − 9 v is supplied to the word line wl of the memory cell by the regulation circuit 30 b . at the time of program operation , the second charge pump circuit 20 c is activated with the control signal en 1 c . at the time of program operation , the adjustment voltage v 8 having a voltage value of 5 v is supplied to the bit line bl of the memory cell by the regulation circuit 30 c . by the operation of each of the second charge pump circuits 20 a - 20 c , programming to the memory cell by the pouring of hot electrons , erasing of the memory cell by fn tunneling and reading from the memory cell are carried out . in the flash memory , application of a high voltage to the memory cell for the program operation and erase operation and reading for verification of each operation are repeated a plurality of times . in the flash memory , when it is detected that the value of the external power supply is 1 . 8 v by the voltage detecting circuit 50 , the following operation occurs . at the time of program operation , application of a high voltage to the memory cell for programming and program setting for reading for verification thereof are repeated . when a high voltage is applied to the memory cell for the aforementioned program , the first charge pump circuit 10 and the second charge pump circuits 20 a , 20 c are activated with the control signal en 0 , the control signal en 1 a and the control signal en 1 c . at the time of reading for the aforementioned verification , the first charge pump circuit 10 and the second charge pump circuit 20 a are activated with the control signal en 0 and the control signal en 1 a . at the time of the erase operation , application of a high voltage to the memory cell for the erase operation and setting for reading for verification thereof are repeated . when a high voltage is applied to the memory cell for the erase operation , the first charge pump circuit 10 and the second charge pump circuits 20 a , 20 b are activated with the control signal en 0 and the control signals en 1 a , en 1 b respectively . at the time of reading , the first charge pump circuit 10 and the second charge pump circuit 20 a are activated with the control signal en 0 and the control signal en 1 a respectively . in an operation repeated by the embedded controller , the first charge pump circuit 10 continues to be activated with the control signal en 0 at the time of transition from the program operation or erase operation to the verify operation ( read operation ) or from the verify operation ( read operation ) to the program operation or the erase operation . thus , generation of the pumping voltage v 1 is maintained by the activated first charge pump circuit 10 . in the flash memory of this embodiment , while the activation of the first charge pump circuit 10 is maintained with the control signal en 0 , each of the second charge pumps 20 a - 20 c can be activated or deactivated with the control signals en 1 a - en 1 c corresponding to each operation such as the program operation . according to this embodiment , the control signal en 0 corresponds to a first control signal of the invention . the control signals en 1 a - en 1 c correspond to a second control signal of the invention . in this embodiment , the second charge pump units 20 a , 20 c correspond to a third charge pump unit of the present invention and the second charge pump unit 20 b corresponds to a fourth charge pump unit of the invention . further , the pumping voltages v 2 , v 3 correspond to a first output voltage of the invention and the negative voltage v 4 corresponds to a second output voltage of the invention . in the voltage generating portion 1 of this embodiment , the provision of the selection circuit 40 enables the selection of one of the pumping voltage v 1 obtained by pumping the external power supply voltage of 1 . 8 v and the external power supply voltages v 11 of 3 v and bring the selected voltage value closer to each of the adjustment voltages v 7 , v 8 outputted by the voltage generating portion 1 . in the voltage generating portion 1 of this embodiment , the pumping voltage v 1 having a value near each voltage value of the adjustment voltages v 7 , v 8 or the external power supply voltage v 11 is pumped up by the second charge pump circuits 20 a , 20 c so as to generate the pumping voltages v 2 , v 3 . thus , the time that passes until the voltage before pumped up reaches the pumping voltages v 2 , v 3 can be decreased . thus , the voltage generating portion 1 of this embodiment can raise the efficiency of pumping up the voltage before pumped to the pumping voltages v 2 , v 3 . furthermore , by setting the pumping interval ( 3v ) of the second pumping circuits 25 a , 25 c wider than the pumping interval ( 1 . 8 v ) of the first pumping circuit 15 , the quantity of pumping stages of the second pumping circuits 25 a , 25 c can be reduced compared with a case of determining the quantity of the pumping stages based on the pumping interval ( 1 . 8 v ) of the first pumping circuit 15 . consequently , the voltage generating portion 1 of this embodiment can reduce the occupied area of the second charge pump circuits 20 a , 20 c with a decrease in the quantity of the pumping stages of the second pumping circuits 25 a , 25 c , so as to reduce the occupied area of the voltage generating portion 1 . according to the control method of the voltage generating portion 1 of this embodiment , one of the pumping voltage v 1 obtained by pumping the external power supply voltage of 1 . 8 v and the external power supply voltages v 11 of 3 v can be selected and the selected voltage value can be brought closer to each voltage of the adjustment voltages v 7 , v 8 outputted from the voltage generating portion 1 . according to the control method of the voltage generating portion 1 of this embodiment , the pumping voltages v 2 , v 3 are generated by pumping up the pumping voltage v 1 having a value near each voltage of the adjustment voltages v 7 , v 8 or the external power supply voltage v 11 . as such , the time required until the voltage before pumped reaches the pumping voltages v 2 , v 3 can be decreased . thus , according to the control method of the voltage generating portion 1 of this embodiment , the efficiency of pumping the voltage before pumped to the pumping voltages v 2 , v 3 can be increased . furthermore , according to the control method of the voltage generating portion 1 of this embodiment , by setting the pumping interval ( 3 v ) of the second pumping circuits 25 a , 25 c wider than the pumping interval ( 1 . 8 v ) of the first pumping circuit 15 , the quantity of the pumping stages of the second pumping circuits 25 a , 25 c can be reduced compared with a case of determining the quantity of the pumping stages based on the pumping interval ( 1 . 8 v ) of the first pumping circuit 15 . in the flash memory of this embodiment , the first charge pump circuit 10 a is activated with the control signal en 0 and at the same time , each of the second charge pumps 20 a - 20 c is activated with the control signals en 1 a - en 1 c different from the control signal en 0 . then , the flash memory of this embodiment can maintain the activation condition of the first charge pump circuit 10 with the control signal en 0 and activate the second charge pump units 20 a - 20 c with the control signals en 1 a - en 1 c . thus , in the flash memory of this embodiment , the second charge pump units 20 a - 20 c can be activated with the control signals en 1 a - en 1 c different from the control signal en 0 independently of the first charge pump unit 10 a so as to accelerate the rise - up activity of the flash memory . for example , in the flash memory discussed above , while maintaining the activation condition of the first charge pump circuit 10 a with the control signal en 0 , the second charge pump units 20 a - 20 c can be activated so as to move from the program operation or the erase operation to the read operation or from the read operation to the program operation or the erase operation . consequently , in the flash memory , the second charge pump units 20 a - 20 c can be controlled to activation condition or deactivation condition corresponding to whether or not the respective control signals en 1 a - en 1 c are supplied , independently of the first charge pump unit 10 without returning the first charge pump unit 10 to the deactivation condition or the activation condition again . thus , by controlling the second charge pump units 20 a - 20 c into the activation condition rapidly with the control signals en 1 a - en 1 c in the flash memory discussed above , embedded controller activities including the program operation , erase operation and read operation can be carried out rapidly . the flash memory of this embodiment includes the second charge pump circuit 20 a for generating the pumping voltage v 2 at the time of program operation and the second charge pump circuit 20 c for generating the pumping voltage v 3 and further the second charge pump circuit 20 b for generating the negative voltage v 4 at the time of erase operation . thus , the flash memory of this embodiment can use a different charge pump for each operation so as to generate a voltage corresponding to each operation . then , in the flash memory of this embodiment , each of the second charge pump units 20 a - 20 c which are different from each other is used to move from the erase operation to the program operation or from the program operation to the erase operation , so as to generate a voltage corresponding to each operation rapidly . therefore , if the pumping voltages v 2 , v 3 corresponding to the program operation or the negative voltage v 4 corresponding to the erase operation are generated rapidly in the flash memory of this embodiment , the program operation and the erase operation can be accelerated corresponding to the pumping voltages v 2 , v 3 or the negative voltage v 4 . the second embodiment of the present invention will be described with reference to fig2 . the same reference numerals are attached to the same components as the first embodiment and description thereof is omitted . fig2 is a block diagram showing the structure of the voltage generating portion 1 a of this embodiment . a voltage generating portion 1 a includes a first delay circuit 60 as well as the voltage generating portion 1 of the first embodiment . according to this embodiment , the first delay circuit 60 is constituted of a delay locked loop ( dll ) circuit . the input of the first delay circuit 60 is connected to an oscillation circuit ( not shown ). the output of the first delay circuit 60 is connected to the first buffer circuit 11 of the first charge pump circuit 10 . in this embodiment , the voltage generating portion 1 a is operated as follows . an activity in the case the value of the external power supply voltage is detected to be 1 . 8 v by the voltage detecting circuit 50 will be described . in this embodiment , the first operation clock signal clk 1 is outputted to the first delay circuit 60 and each of the second buffer circuit 21 of the second charge pump circuits 20 a - 20 c by an oscillation circuit . when the high level control signals en 1 a - en 1 c are inputted to each of the second buffer circuits 21 by a control circuit ( not shown ), the level converting circuit 22 outputs the second operation clock signal clk 2 to each of the second pumping circuits 25 a - 25 c like the first embodiment . each of the second pumping circuits 25 a - 25 c starts its pumping / step - down operation when the high level ( amplitude of 3 v ) second operation clock signal clk 2 is inputted . on the other hand , a first delay circuit 60 generates a delay clock signal clk 1 ′ by delaying the phase of the first operation clock signal clk 1 after a specified delay time elapses . the delay time of the first delay circuit 60 is set to a time longer than the time required until the second operation clock signal clk 2 is outputted to each of the second pumping circuits 25 a - 25 c by each level converting circuit 22 . the first delay circuit 60 outputs the delay clock signal clk 1 ′ to the first buffer circuit 11 . the delay clock signal clk 1 ′ is outputted to the first pumping circuit 15 via the first buffer circuit 11 . the first pumping circuit 15 starts its pumping operation when the high level ( amplitude of 1 . 8 v ) delay clock signal clk 1 ′ is inputted . the delay clock signal clk 1 ′ corresponds to a first clock signal of the present invention . in this embodiment , the phase of the delay clock signal clk 1 ′ is delayed with respect to the phase of the second operation clock signal clk 2 by the first delay circuit 60 . thus , the timing that the delay clock signal clk 1 ′ inputs to the first pumping circuit 15 is delayed by the timing of the second operation clock signal clk 2 that is inputted to each of the second pumping circuits 25 a - 25 c . consequently , the pumping operation of the first pumping circuit 15 and the voltage pumping / step - down operation of each of the second pumping circuits 25 a - 25 c are carried out at different timings . in this embodiment , the phase of the delay clock signal clk 1 ′ to be inputted to the first pumping circuit 15 is delayed with respect to the phase of the second operation clock signal clk 2 to be inputted to each of the second pumping circuits 25 a - 25 c . thus , the first delay circuit 60 corresponds to a clock signal delay portion of the present invention . delaying the phase of the delay clock signal clk 1 ′ to be inputted to the first pumping circuit 15 with respect to the phase of the second operation clock signal clk 2 to be inputted to each of the second pumping circuits 25 a - 25 c corresponds to a clock signal delay step of the present invention . in the voltage generating portion 1 a of this embodiment , by delaying the phase of the delay clock signal clk 1 ′ to be inputted to the first pumping circuit 15 by the first delay circuit 60 with respect to the phase of the second operation clock signal clk 2 to be inputted to each of the second pumping circuit 25 a - 25 c , the pumping operation of the first pumping circuit 15 can be started after the pumping / step - down operation of each of the second pumping circuits 25 a - 25 c is started . in the voltage generating portion 1 a of this embodiment , the pumping operation of the first charge pump circuit 10 and the pumping / step - down operation of the second charge pump circuits 20 a - 20 c can be carried out at different timings . thus , the timing that peak current flows into the first charge pump circuit 10 can be made different from the timing that peak current flows into the second charge pump circuits 20 a - 20 c so as to suppress generation of power supply noise . according to the control method of the voltage generating portion 1 a of this embodiment , if the phase of the delay clock signal clk 1 ′ is delayed with respect to the phase of the second operation clock signal clk 2 , the pumping operation with the delay clock signal clk 1 ′ can be started after the pumping / step - down operation with the second operation clock signal clk 2 is started . according to the control method of the voltage generating portion 1 a of this embodiment , the pumping / step - down operation with the second operation clock signal clk 2 and the pumping operation with the delay clock signal clk 1 ′ can be carried out at different timings . for this reason , the timing that peak current flows by the pumping / step - down operation with the second operation clock signal clk 2 can be made different from the timing that peak current flows by the pumping operation with the delay clock signal clk 1 ′ so as to suppress generation of power supply noise . the third embodiment of the present invention will be described with reference to fig3 . the same reference numerals are attached to the same components as the first embodiment and the second embodiment and description thereof is omitted . a symbol en 1 in the same figure indicates a control signal outputted by a control circuit ( not shown ). fig3 is a block diagram showing the structure of a voltage generating portion 1 b of this embodiment . in the voltage generating portion 1 b , three second charge pump circuits 20 a , 20 d , 20 e are connected in parallel . the output terminals ( out 2 ) of the second charge pump circuits 20 a , 20 d , 20 e are connected to the regulation circuit 30 a . the output of the regulation circuit 30 a is connected to the word line wl . the voltage generating portion 1 b includes a phase adjusting circuit 65 . the input of the phase adjusting circuit 65 is connected to an oscillation circuit ( not shown ). in this embodiment , the phase adjusting circuit 65 is constructed of the dll circuit . the phase adjusting circuit 65 includes a 3 - phase clock generating portion . the 3 - phase clock generating portion is connected to a first output terminal t 1 , a second output terminal t 2 and a third output terminal t 3 . the first output terminal t 1 is connected to the second buffer circuit 21 of the second charge pump circuit 20 a . the second output terminal t 2 is connected to the second buffer circuit 21 of the second charge pump circuit 20 d . the third output terminal t 3 is connected to the second buffer circuit 21 of the second charge pump circuit 20 e . the voltage generating portion 1 b is operated as follows . an operation in the case the external power supply voltage is detected to be 1 . 8 v by the voltage detecting circuit 50 will be described here . according to this embodiment , the first operation clock signal clk 1 is outputted to the first buffer circuit 11 and the phase adjusting circuit 65 by an oscillation circuit . when the first operation clock signal clk 1 is inputted to a phase adjusting circuit 65 , the 3 - phase clock generating portion generates a fifth operation clock signal clk 5 , a sixth operation clock signal clk 6 and a seventh operation clock signal clk 7 , whose phases are different from each other by 90 °. the phase adjusting circuit 65 outputs the fifth operation clock signal clk 5 from the first output terminal t 1 to the second buffer circuit 21 of the second charge pump circuit 20 a . the phase adjusting circuit 65 outputs the sixth operation clock signal clk 6 from the second output terminal t 2 to the second buffer circuit 21 of the second charge pump circuit 20 d . the phase adjusting circuit 65 outputs the seventh operation clock signal clk 7 from the third output terminal t 3 to the second buffer circuit 21 of the second charge pump circuit 20 e . when the fifth operation clock signal clk 5 is inputted to the second buffer circuit 21 , the level converting circuit 22 outputs the second operation clock signal clk 2 a to the second pumping circuit 25 a like the first embodiment and the second embodiment . when the high level ( amplitude of 3 v ) second operation clock signal clk 2 a is inputted , the second pumping circuit 25 a starts its pumping operation . the second pumping circuit 25 a raises the pumping voltage v 1 toward a voltage near 9 v gradually with a plurality of pumping capacitors . the sixth operation clock signal clk 6 is inputted to the second buffer circuit 21 with its phase delayed by 90 ° with respect to the fifth operation clock signal clk 5 . consequently , the level converting circuit 22 outputs the second operation clock signal clk 2 b to the second pumping circuit 25 d . the second operation clock signal clk 2 b is delayed by 90 ° in phase with respect to the second operation clock signal clk 2 a . when the high level ( amplitude of 3 v ) second operation clock signal clk 2 b is inputted , the second pumping circuit 25 d raises the pumping voltage v 1 toward a voltage near 9 v gradually at a different timing from the second pumping circuit 25 a of the second charge pump circuit 20 a with a plurality of the pumping capacitors . the seventh operation clock signal clk 7 is inputted to the buffer circuit 21 with its phase delayed by 90 ° with respect to the sixth operation clock signal clk 6 . consequently , the level converting circuit 22 outputs the second operation clock signal clk 2 c to the second pumping circuit 25 e . the second operation clock signal clk 2 c is delayed by 90 ° in phase with respect to the second operation clock signal clk 2 b . when the high level ( amplitude of 3 v ) second operation clock signal clk 2 c is inputted , the second pumping circuit 25 e raises the pumping voltage v 1 toward a voltage near 9 v gradually at a different timing from the second pumping circuit 25 d and the second pumping circuit 25 e with a plurality of the pumping capacitors . in this embodiment , the fifth operation clock signal clk 5 , the sixth operation clock signal clk 6 and the seventh operation clock signal clk 7 , whose phases are different from each other by 90 ° are generated by the 3 - phase clock generating portion possessed by the phase adjusting circuit 65 . the phase of the second operation clock signal clk 2 b generated by the level converting circuit 22 based on the sixth operation clock signal clk 6 is delayed by 90 ° with respect to the phase of the second operation clock signal clk 2 a generated by the level converting circuit 22 based on the fifth operation clock signal clk 5 . additionally , the phase of the second operation clock signal clk 2 c generated by the level converting circuit 22 based on the seventh operation clock signal clk 7 is delayed by 90 ° with respect to the phase of the second operation clock signal clk 2 b generated by the level converting circuit 22 based on the sixth operation clock signal clk 6 . therefore , the phase adjusting circuit 65 corresponds to a phase adjusting portion of the invention because it can make the fifth operation clock signal clk 5 , the sixth operation clock signal clk 6 and the seventh operation clock signal clk 7 different in phase by 90 ° from each other . making the fifth operation clock signal clk 5 , the sixth operation clock signal clk 6 and the seventh operation clock signal clk 7 different in phase by 90 ° from each other corresponds to a phase adjusting step of the present invention . in the voltage generating portion 1 b of this embodiment , if the second operation clock signal clk 5 , the second operation clock signal clk 6 and the second operation clock signal clk 7 , inputted to the second pumping circuits 25 a , 25 d , 25 e of the second charge pump circuits 20 a , 20 d , 20 e are made different in phase by 90 ° from each other by the phase adjusting circuit 65 , the timings of the pumping operations of the second pumping circuits 25 a , 25 d , 25 e of the second charge pump circuits 20 a , 20 d , 20 e connected in parallel can be made different . in the voltage generating portion 1 b of this embodiment , the second pumping circuits 25 a , 25 d , 25 e of the second charge pump circuits 20 a , 20 d , 20 e can execute the pumping operation of accumulating electric charges in each pumping capacitor without interruption at a different timing . therefore , the voltage generating portion 1 b of this embodiment can prevent the voltage of the pumping capacitor from dropping by charging the pumping capacitor without interruption , thereby preventing a drop in voltage supply capacity to the word line wl . according to the control method of the voltage generating portion 1 b of this embodiment , by making the second operation clock signal clk 5 , the second operation clock signal clk 6 and the second operation clock signal clk 7 different in phase by 90 ° from each other , the pumping operation timings of the second pumping circuits 25 a , 25 d , 25 e of the second charge pump circuits 20 a , 20 d , 20 e connected in parallel can be made different . consequently , according to the control method of the voltage generating portion 1 b of this embodiment , the pumping operation of accumulating electric charges in the pumping capacitor of the second pumping circuits 25 a , 25 d , 25 e of the second charge pump circuits 20 a , 20 d , 20 e can be carried out at a different timing without interruption . therefore , according to the control method of the voltage generating portion 1 b of this embodiment , when the second pumping circuits 25 a , 25 d , 25 e of the second charge pump circuits 20 a , 20 d , 20 e execute the pumping operation without interruption , the voltage supply capacity to the word line wl can be prevented from dropping . a fourth embodiment of the present invention will be described with reference to fig4 . the same reference numerals are attached to the same components as the first to third embodiments and description thereof is omitted . fig4 is a block diagram showing part of the structure of the voltage generating portion 1 c according to this embodiment . the voltage generating portion 1 c includes a comparator comp 1 and third buffer circuits 71 , 72 as well as the structure of the voltage generating portion 1 b of the third embodiment . in the meantime , in fig4 , representation of the first charge pump 10 , the selection circuit 40 and the voltage detecting circuit 50 shown in fig3 is omitted . the non - inverting input terminal of the comparator comp 1 is connected to the word line wl . reference voltage e 1 is connected to the non - inverting input terminal of the comparator comp 1 . the input of the third buffer circuit 71 is connected to the second output terminal t 2 of the phase adjusting circuit 65 . the output of the third buffer circuit 71 is connected to the second buffer circuit 21 of the second charge pump circuit 20 d . the inhibition input terminal ( inh ) of the third buffer circuit 71 is connected to the output terminal ( n 1 ) of the comparator comp 1 . the input of the third buffer circuit 72 is connected to the third input terminal t 3 of the phase adjusting circuit 65 . the output of the third buffer circuit 72 is connected to the second buffer circuit 21 of the second charge pump circuit 20 e . the inhibition input terminal ( inh ) of the third buffer circuit 72 is connected to the output terminal ( n 1 ) of the comparator comp 1 . the voltage generating portion 1 c is operated as follows . as described above , the regulation circuit 30 a supplies the adjustment voltage v 7 to the word line wl . a voltage v 10 of the word line wl is inputted to the non - inverting input of the comparator comp 1 . the comparator comp 1 compares the voltage v 10 of the word line wl with the reference voltage e 1 . the value of the reference voltage e 1 is set to such a value which enables write operation to a memory cell connected to the word line wl to be carried out securely . if the value of the voltage v 10 is higher than the value of the reference voltage e 1 , the comparator comp 1 outputs a high level signal stop to each inhibition input terminal ( inh ) of the third buffer circuits 71 , 72 . if the value of the voltage v 10 is higher than the value of the reference voltage e 1 , it means that the voltage supply capacity of the voltage generating portion 1 c is sufficient . while the high level signal stop is inputted to the inhibition input terminal ( inh ) of the third buffer circuit 71 , the third buffer circuit 71 does not output the sixth operation clock signal clk 6 to the second buffer circuit 21 of the second charge pump circuit 20 d . consequently , the level converting circuit 22 does not output the second operation clock signal clk 2 b to the second pumping circuit 25 d . thus , the pumping operation of the second pumping circuit 25 d is stopped , so that no adjustment voltage v 7 is supplied to the word line wl . while the high level signal stop is inputted to the inhibition input terminal ( inh ) of the third buffer circuit 72 , the third buffer circuit 72 does not output the seventh operation clock signal clk 7 to the second buffer circuit 21 of the second charge pump circuit 20 e . consequently , the level converting circuit 22 does not output the second operation clock signal clk 2 c to the second pumping circuit 25 e . thus , the pumping operation of the second pumping circuit 25 e is stopped , so that no adjustment voltage v 7 is supplied to the word line wl . on the other hand , if the value of the voltage v 10 is lower than the value of the reference voltage e 1 , the comparator comp 1 outputs a low level signal stop to each inhibition input terminal ( inh ) of the third buffer circuits 71 , 72 . if the value of the voltage v 10 is lower than the value of the reference voltage e 1 , it means that the voltage supply capacity of the voltage generating portion 1 c is not sufficient . in this case , the third buffer circuits 71 , 72 output the sixth operation clock signal clk 6 and the seventh operation clock signal clk 7 to each of the second buffer circuits 21 . consequently , the second operation clock signal clk 2 b and the second operation clock signal clk 2 c are outputted to the second pumping circuit 25 d and the second pumping circuit 25 e by each level converting circuit 22 . thus , the second pumping circuits 25 d , 25 e continue the pumping operation so that the adjustment voltage v 7 is supplied to the word line wl . according to this embodiment , whether or not the value of the voltage v 10 of the word line wl is higher than the reference voltage e 1 can be detected by the comparator comp 1 . thus , the comparator comp 1 corresponds to a detector of the present invention . in this embodiment , with the high level signal stop outputted by the comparator comp 1 , the third buffer circuits 71 , 72 stop outputting of the sixth operation clock signal clk 6 and the seventh operation clock signal clk 7 to each of the second buffer circuits 21 . consequently , each level converting circuit 22 does not output the second operation clock signal clk 2 b and the second operation clock signal clk 2 c to the second pumping circuits 25 d , 25 e . thus , the third buffer circuits 71 , 72 correspond to a clock signal supply stop portion of the present invention . detecting whether or not the value of the voltage v 10 of the word line wl is higher than the reference voltage e 1 corresponds to a detecting step of the present invention . further , it is detected that the value of the voltage v 10 of the word line wl is higher than the reference voltage e 1 and outputting of the sixth operation clock signal clk 6 and the seventh operation clock signal clk 7 is stopped with the high level signal stop . consequently , stopping of use of the second operation clock signal clk 2 b and the second operation clock signal clk 2 c without generating the sixth operation clock signal clk 6 and the seventh operation clock signal clk 7 corresponds to a clock signal supply stop step of the present invention . if the second charge pump circuits 20 a , 20 d , 20 e in which the second operation clock signal clk 5 , the second operation clock signal clk 6 and the second operation clock signal clk 7 whose phases are different by 90 ° from each other are inputted , the second charge pump circuits 20 a , 20 d , 20 e being connected in parallel , are provided like the voltage generating portion 1 c of this embodiment , the voltage supply capacity of the voltage generating portion 1 c can be raised by the three second charge pump circuits 20 a , 20 d , 20 e . then , the second charge pump circuits 20 a , 20 d , 20 e can rise up the value of the pumping voltage v 2 toward 9 v rapidly using the high voltage supply capacity . further , if it is detected that the value of the voltage v 10 of the word line wl is higher than the value of the reference voltage e 1 by the comparator comp 1 and outputting of the second operation clock signal clk 2 b and the second operation clock signal clk 2 c to the second pumping circuits 25 d , 25 e is stopped by the third buffer circuits 71 , 72 as in the voltage generating portion 1 c of this embodiment , the pumping operation of the second pumping circuits 25 d , 25 e can be stopped . consequently , by executing the pumping operation of the second charge pump circuit 20 a , which is one of the three second charge pump circuits 20 a , 20 d , 20 e , the quantity of the operating second charge pump circuits can be reduced so as to save power consumption . additionally , by the pumping operation of the second charge pump circuit 20 a in which the second operation clock signal clk 2 a is inputted , the power supply capacity can be secured thereby preventing the voltage v 10 of the word line wl from dropping . according to the control method of the voltage generating portion 1 c of this embodiment , the second operation clock signal clk 5 , the second operation clock signal clk 6 and the second operation clock signal clk 7 whose phases are different by 90 ° from each other are employed and the pumping operations of the second charge pump circuits 20 a , 20 d , 20 e connected in parallel are executed so as to intensify the voltage supply capacity of the voltage generating portion 1 c . then , according to the control method of the voltage generating portion 1 c of this embodiment , the value of the pumping voltage v 2 can be raised up toward 9 v rapidly using the high voltage supply capacity . further , according to the control method of the voltage generating portion 1 c of this embodiment , if it is detected that the value of the voltage v 10 of the word line wl is higher than the value of the reference voltage e 1 and outputting of the second operation clock signal clk 2 b and the second operation clock signal clk 2 c to the second pumping circuits 25 d , 25 e is stopped , the pumping operation of the second pumping circuits 25 d , 25 e can be stopped . consequently , by executing the pumping operation of the second charge pump circuit 20 a , which is one of the three second charge pump circuits 20 a , 20 d , 20 e , the quantity of the operating second charge pump circuits can be reduced to save power consumption . additionally , the power supply capacity can be secured by the pumping operation of the second charge pump circuit 20 a in which the second operation clock signal clk 2 a is inputted , so as to prevent the voltage v 10 of the word line wl from dropping . a fifth embodiment of the present invention will be described with reference to fig5 . the same reference numerals are attached to the same components as the first embodiment and the like and description thereof is omitted . fig5 is a block diagram showing part of the structure of the voltage generating portion 1 d of this embodiment . fig5 indicates a control circuit 80 whose representation is omitted in the first embodiment . the voltage generating portion 1 d includes a second delay circuit 86 and an n type channel transistor m 1 . the control circuit 80 is connected to the input of the first buffer circuit 11 of the first charge pump circuit 10 , the input of the second buffer circuit 21 of the second charge pump circuit 20 a ′ and the input of the second delay circuit 86 . the output of the second delay circuit 86 is connected to the switch sw of the selection circuit 40 via a logical product gate circuit and . the output of the voltage detecting circuit 50 is connected to the logical product gate circuit and . the drain of the n type channel transistor m 1 is connected between the output of the second pumping circuit 25 a and the output terminal ( out 2 ) of the second charge pump circuit 20 a ′. the source of the n type channel transistor m 1 is connected to the ground . the gate of the n type channel transistor m 1 is connected to the control circuit 80 . the operation of the voltage generating portion 1 d will be described . an operation in case where it is detected that the value of the external power supply voltage is 1 . 8 v by the voltage detecting circuit 50 will be described . the voltage generating portion 1 d outputs the low level control signal en 0 to the first buffer circuit 11 by the control circuit 80 to stop the pumping operation . consequently , the first buffer circuit 11 does not output the first operation clock signal clk 1 to the first pumping circuit 15 . additionally , the voltage generating portion 1 d outputs the low level control signal en 1 to the second buffer circuit 21 by the control circuit 80 to stop the pumping operation . consequently , the level converting circuit 22 does not output the second operation clock signal clk 2 to the second pumping circuit 25 a . further , the voltage generating portion 1 d outputs a high level gate control signal to the gate of the n type channel transistor m 1 by the control circuit 80 to stop the pumping operation . consequently , the gate of the n type channel transistor m 1 is fixed to a high level voltage so that the n type channel transistor m 1 is turned to on . therefore , by the pumping operation of the second pumping circuit 25 a discussed above , electric charges accumulated in the pumping capacitor of the second pumping circuit 25 a are discharged to the ground via the n type channel transistor m 1 . as a result , the value of the voltage v 2 becomes lower than the value of the pumping voltage v 1 . the n type channel transistor m 1 corresponds to an output voltage adjusting unit of the present invention . additionally , when the voltage generating portion 1 d stops the pumping operation , it outputs the low level switch operation signal chn 2 to the second delay circuit 86 by the control circuit 80 . the second delay circuit 86 outputs a signal obtained by delaying the phase of the switch operation signal chn 2 after a predetermined delay time elapses to the logical product gate circuit and so as to change the switch operation signal chn 3 from high level to low level . the delay time of the second delay circuit 86 is set to a time required for the value of the voltage v 2 to drop below the value of the pumping voltage v 1 . the switch sw is connected from the terminal t 1 to the terminal t 2 by the second delay circuit 86 after the predetermined time elapses . according to this embodiment , the switch sw is connected from the terminal t 1 to the terminal t 2 when the value of the voltage v 2 becomes lower than the value of the pumping voltage v 1 . an external power supply voltage of 1 . 8 v is supplied to the second pumping circuit 25 a via the terminal t 2 , switch sw and the internal power supply line l 2 . the switch operation signal chn 3 corresponds to a connection instruction signal of the present invention . the second delay circuit 86 and the logical product gate circuit and correspond to an instruction signal output portion of the present invention . in this embodiment , lowering the value of the voltage v 2 relative to the value of the pumping voltage v 1 to stop the pumping operation corresponds to an output voltage adjusting step of the invention . in this embodiment , connecting the switch sw from the terminal t 1 to the terminal t 2 when the value of the voltage v 2 is lowered relative to the pumping voltage v 1 corresponds to an instruction step of the present invention . in the voltage generating portion 1 d of this embodiment , when the second operation clock signal clk 2 is stopped and the pumping operation of the second pumping circuit 25 a is stopped , the value of the voltage v 2 is lowered relative to the value of the pumping voltage v 1 by the n type channel transistor m 1 with the pumping voltage v 1 having a voltage value of 3 v supplied to the internal power supply line l 2 . consequently , the second pumping circuit 25 a can discharge electric charges accumulated in the pumping capacitor of the second pumping circuit 25 a to the ground securely and rapidly via the n type channel transistor m 1 when it is not pumping the voltage . the reason is that if the value of the pumping voltage v 1 is reset ahead , each internal node of each pumping stage in the second pumping circuit 25 a constituted of a capacity parallel connection type charge pump in which the pumping capacitors are connected through a plurality of stages is not reset . another reason is that if the voltage value of the internal power supply line l 2 is changed to the value ( 1 . 8 v ) of the external power supply line l 1 which is lower than the value ( 3 v ) of the pumping voltage v 1 , the reset speed of each internal node of each pumping stage in the second pumping circuit 25 a is lowered . in the voltage generating portion 1 d of this embodiment , when the value of the voltage v 2 is lowered relative to the value of the pumping voltage v 1 by the n type channel transistor m 1 , the switch operation signal chn 3 for connecting the switch sw to the terminal t 2 is outputted to the switch sw by the second delay circuit 86 and the logical product gate circuit and . then , in the voltage generating portion 1 d of this embodiment , the switch sw can be connected to the terminal t 2 after the value of the voltage v 2 is lowered relative to the value of the pumping voltage v 1 without connecting the switch sw to the terminal t 2 before the value of the voltage v 2 is lowered relative to the value of the pumping voltage v 1 . thus , in the voltage generating portion 1 d of this embodiment , when the switch sw is connected to the terminal t 2 and the external power supply voltage of 1 . 8 v is supplied to the second pumping circuit 25 a , electric charges accumulated in the pumping capacitor are discharged , so that the second charge pump circuit 20 a ′ can be protected from a voltage stress originating from electric charges accumulated in the pumping capacitor . thus , the voltage generating portion 1 d of this embodiment can lower the voltage stress applied to the second charge pump circuit 20 a ′ so as to intensify the operating reliability of the voltage generating portion 1 d . if the value of the internal power supply line l 2 is lowered relative to the value of the voltage v 2 before the value of the voltage v 2 is lowered relative to the value of the pumping voltage v 1 , the high level value of the second operation clock signal clk 2 is lowered from 3 v to 1 . 8 v . consequently , a difference of voltage between the internal pumping node in which the second clock signal clk 2 in the second pumping circuit 25 a is stopped at a high level and the second operation clock signal clk 2 rises temporarily so that the voltage stress is raised . according to the control method of the voltage generating portion 1 d of this embodiment , if the value of the voltage v 2 is lowered relative to the value of the pumping voltage v 1 when the pumping operation is stopped with no second operation clock signal clk 2 generated , electric charges accumulated in the pumping capacitor of the second pumping circuit 25 a can be discharged when the second pumping circuit 25 a is not pumping the voltage . according to the control method of the voltage generating portion 1 d of this embodiment , if the value of the voltage v 2 is lowered relative to the value of the pumping voltage v 1 , the switch operation signal chn 3 of connecting the switch sw to the terminal t 2 is outputted to the switch sw . then , according to the control method of the voltage generating portion 1 d of this embodiment , the switch sw can be connected to the terminal t 2 after the value of the voltage v 2 is lowered relative to the value of the pumping voltage v 1 without connecting the switch sw to the terminal t 2 before the value of the voltage v 2 is lowered relative to the value of the pumping voltage v 1 . therefore , according to the control method of the voltage generating portion 1 d of this embodiment , when the switch sw is connected to the terminal t 2 and the external power supply of 1 . 8 v is supplied to the second pumping circuit 25 a , electric charges accumulated in the pumping capacitor are discharged , so that the second charge pump circuit 20 a can be protected from a voltage stress originating from electric charges accumulated in the pumping capacitor . for the reason , according to the control method of the voltage generating portion 1 d of this embodiment , the voltage stress applied to the second charge pump circuit 20 a ′ can be reduced so as to intensify the operating reliability of the voltage generating portion 1 d . the sixth embodiment of the present invention will be described with reference to fig6 . same reference numerals are attached to the same components as the first embodiment and description thereof is omitted . fig6 is a block diagram showing the structure of the voltage generating portion 1 e of this embodiment . the voltage generating portion 1 e includes a third delay circuit 90 and a logical product gate circuit and 1 as well as the voltage generating portion 1 of the first embodiment . the input of the third delay circuit 90 is connected to the output of the voltage detecting circuit 50 . the output of the third delay circuit 90 is connected to the first input of the logical product gate circuit and 1 . the second input of the logical product gate circuit and 1 is connected to a control circuit ( not shown ). the output of the logical product gate circuit and 1 is connected to the first buffer circuit 11 of the first charge pump circuit 10 . next , the operation of the voltage generating portion 1 e will be described . an operation in case where it is detected that the value of the external power supply voltage is 1 . 8 v by the voltage detecting circuit 50 will be described . the voltage detecting circuit 50 outputs the high level selection signal chn 1 to the switch sw of the selection circuit 40 and the third delay circuit 90 . when the switch sw receives the high level selection signal chn 1 , it is connected to the terminal t 1 . the third delay circuit 90 generates the high level selection signal chn 5 in which the phase of the high level selection signal chn 1 is delayed after a predetermined delay time elapses . the third delay circuit 90 is set to a longer time than time required until the switch sw is connected to the terminal t 1 . in the meantime , the selection signal chn 5 corresponds to a delay signal of the invention . the high level control signal en 0 is inputted to the second input of the logical product gate circuit and 1 by the control circuit . the control signal en 0 corresponds to an activation control signal of the invention . when the high level selection signal chn 5 is inputted to the first input by the third delay circuit 90 , the logical product gate circuit and 1 outputs the high level control signal en 5 to the first buffer circuit 11 . the phase of the high level control signal en 5 to be inputted to the first buffer circuit 11 is delayed with respect to the phase of the selection signal chn 1 because the phase of the selection signal chn 5 which generates the control signal en 5 is delayed with respect to the phase of the selection signal chn 1 . the first buffer circuit 11 outputs the first operation clock signal clk 1 having an amplitude of 1 . 8 v to the first pumping circuit 15 . the first pumping circuit 15 starts its pumping operation and supplies the pumping voltage v 1 to the internal power supply line l 2 through the input terminal ( in 5 ) of the selection switch 40 , the terminal t 1 , the switch sw and the output terminal ( out 5 ). according to this embodiment , the selection signal chn 5 whose phase is delayed with respect to the selection signal chn 1 can be generated by the third delay circuit 90 . therefore , the third delay circuit 90 corresponds to a delay portion of the invention . according to this embodiment , if the high level selection signal chn 5 and the high level control signal en 0 are inputted , the logical product gate circuit and 1 outputs the high level control signal en 5 to the first buffer circuit 11 . the control signal en 5 corresponds to a voltage generation instruction signal of the present invention because it outputs the first operation clock signal clk 1 which starts the pumping operation of the first pumping circuit 15 to the first pumping circuit 15 through the first buffer circuit 11 . further , the logical product gate circuit and 1 corresponds to a generating portion of the present invention because it outputs the control signal en 5 . in this embodiment , the third delay circuit 90 and the logical product gate circuit and 1 constitute a voltage generating adjusting unit of the invention . generating the selection signal chn 5 whose phase is delayed with respect to the selection signal chn 1 corresponds to a delay step of the present invention . further , outputting the high level control signal en 5 using the high level selection signal chn 5 and the high level control signal en 0 corresponds to a generation step of the invention . generating the pumping voltage v 1 by the first operation clock signal clk 1 having an amplitude of 1 . 8 v after the switch sw is connected to the terminal t 1 by the high level selection signal chn 1 corresponds to a voltage generation adjusting step of the present invention . in the voltage generating portion 1 e of this embodiment , the first buffer circuit 11 outputs the first operation clock signal clk 1 which starts the pumping operation of the first pumping circuit 15 to the first pumping circuit 15 based on the control signal en 5 which is a result of logical product operation between the selection signal chn 5 and the control signal en 0 after the switch sw is connected to the terminal t 1 . therefore , in the voltage generating portion 1 e of this embodiment , the first pumping circuit 15 can generate the pumping voltage v 1 through the input terminal ( in 5 ) of the selection circuit 40 , the terminal t 1 , the switch sw and the output terminal ( out 5 ) in a condition in which the second charge pumps 20 a , 20 c are connected to the first charge pump 10 . then , the voltage generating portion 1 e of this embodiment can prevent the first pumping circuit 15 from getting into a unstable condition which generates the pumping voltage v 1 rapidly in a condition in which the second charge pump circuits 20 a , 20 c are not connected to the first charge pump circuit 10 . in the voltage generating portion 1 e of this embodiment , the logical product gate circuit and 1 outputs the control signal en 5 for the first operation clock signal clk 1 which starts the pumping operation of the first pumping circuit 15 to pass the first buffer circuit 11 based on the selection signal chn 5 generated by the third delay circuit 90 and the control signal en 0 . then , in the voltage generating portion 1 e of this embodiment , after the switch sw receives the selection signal chn 1 and is connected to the terminal t 1 , the logical product gate circuit and 1 can generate the control signal en 5 for the first operation clock signal clk 1 which starts the pumping operation of the first pumping circuit 15 to pass the first buffer circuit 11 . according to the control method of the voltage generating portion 1 e of this embodiment , after the switch sw is connected to the terminal t 1 , it outputs the first operation clock signal clk 1 which starts the pumping operation of the first pumping circuit 15 to the first pumping circuit 15 based on the control signal en 5 . thus , according to the control method of the voltage generating portion 1 e of this embodiment , the pumping voltage v 1 can be generated via the input terminal ( in 5 ) of the selection circuit 40 , the terminal t 1 , the switch sw and the output terminal ( out 5 ) in a condition in which the second charge pump circuits 20 a , 20 c are connected to the first charge pump circuit 10 . consequently , according to the control method of the voltage generating portion 1 e of this embodiment , the first pumping circuit 15 can be prevented from getting into an unstable condition which generates the pumping voltage v 1 quickly in the condition in which the second charge pump circuits 20 a , 20 c are not connected to the first charge pump circuit 10 . according to the control method of the voltage generating portion 1 e of this embodiment , the control signal en 5 is outputted for the first operation clock signal clk 1 which starts the pumping operation of the first buffer circuit 15 to pass the first buffer circuit 11 , based on the selection signal chn 5 and the control signal en 0 . then , according to the control method of the voltage generating portion 1 e of this embodiment , after the switch sw receives the selection signal chn 1 and is connected to the terminal t 1 , the control signal en 5 can be generated for the first operation clock signal clk 1 which starts the pumping operation of the first pumping circuit 15 to pass the first buffer circuit 11 . the seventh embodiment of the present invention will be described with reference to fig7 . same reference numerals are attached to the same components as the first embodiment and description thereof is omitted . fig7 is a block diagram showing the structure of the voltage generating portion 1 f of this embodiment . the voltage generating portion 1 f includes a diode d 1 as well as the voltage generating portion 1 of the first embodiment . the anode of the diode d 1 is connected to the external power supply line l 1 . the cathode of the diode d 1 is connected to the internal power supply line l 2 . the voltage generating portion 1 f is operated as follows when it is started . an operation in case where the value of the external power supply voltage is set to 1 . 8 v will be described here . a voltage of 1 . 8 v is applied to the diode d 1 by the external power supply line l 1 . consequently , the diode d 1 conducts in forward direction . if the diode d 1 conducts in the forward direction , the value of a voltage supplied to the internal power supply line l 2 is assisted by 1 . 2 v which is the value of the external power supply minus 0 . 6 v (− 0 . 6 v is a threshold of the diode ). then , when the voltage generating portion 1 f is started , the diode d 1 can assist the supply of voltage to the internal power supply line l 2 by the external power supply line l 1 connected to the first charge pump circuit 10 which reaches the predetermined voltage ( 3 v ) slowly . in the meantime , if the value of the external power supply voltage is set to 3 v , the value of the voltage supplied to the internal power supply line l 2 is assisted by 2 . 4 v rapidly because the transistor current drive capacity of the switch sw of the selection circuit 40 is assisted by the diode d 1 . in this embodiment , the current drive capacity of the second charge pump or the selection circuit is assisted by a voltage supplied to the internal power supply line l 2 by the diode d 1 at the time of the initial operation of the voltage generating portion 1 f . thus , the diode d 1 constitutes the assist circuit of the present invention . the diode d 1 corresponds to an assist diode of the present invention . in the voltage generating portion 1 f of this embodiment , the value of the voltage supplied to the second charge pump circuits 20 a , 20 c is assisted to a predetermined voltage value ( 1 . 2 v or 2 . 4 v ) so as to bring the value of that voltage supplied to the second charge pump circuits 20 a , 20 c close to the voltage value ( 1 . 8 v ) of the first external power supply or the voltage value ( 3 v ) of the second external power supply , so that a voltage which secures the voltage value of 1 . 2 v or 2 . 4 v can be supplied to the second charge pump circuits 20 a , 20 c early . thus , in the voltage generating portion 1 f of this embodiment , the second charge pump circuits 20 a , 20 c can be prevented from continuing an unstable condition without being supplied with any voltage in an initial condition such as the time of the startup of the voltage generating portion 1 f , thereby preventing the second charge pump circuits 20 a , 20 c from malfunctioning and permitting the second charge pump circuits 20 a , 20 c to start the operations early . in the voltage generating portion 1 f of this embodiment , provision of the diode d 1 connected between the external power supply line l 1 and the internal power supply line l 2 allows a voltage of 1 . 8 v or 3 v to be applied to the diode d 1 through the external power supply line l 1 , so that the diode d 1 conducts . in the voltage generating portion 1 f of this embodiment , when the diode d 1 conducts , a voltage which operates the second charge pump circuits 20 a , 20 c properly and early in the initial condition such as the time of start - up of the second charge pump circuits 20 a , 20 c can be applied without any control by monitoring the voltage applied to the second charge pump circuits 20 a , 20 c . according to the control method of the voltage generating portion 1 f of this embodiment , the value of the voltage supplied to the second charge pump circuits 20 a , 20 c is assisted to a predetermined voltage value ( 1 . 2 v or 2 . 4 v ) so as to bring the value of that voltage close supplied to the second charge pump circuits 20 a , 20 c to the voltage value ( 1 . 8 v ) of the first external power supply or the voltage value ( 3 v ) of the second external power supply , so that a voltage which secures the voltage value of 1 . 2 v or 2 . 4 v can be supplied to the second charge pump circuits 20 a , 20 c . thus , according to the control method of the voltage generating portion 1 f of this embodiment , the second charge pump circuits 20 a , 20 c can be prevented from continuing an unstable condition without being supplied with any voltage in an initial condition such as the time of the startup of the voltage generating portion 1 f , thereby preventing the second charge pump circuits 20 a , 20 c from malfunctioning and permitting the second charge pump circuits 20 a , 20 c to start the operations early . the present invention is not restricted to the above - described embodiments but may be implemented by changing part of the structure appropriately within a range not departing from the spirit of the present invention . although the voltage generating portion 1 of the above - described first embodiment generates the second operation clock signal clk 2 having an amplitude of 3 v with the first operation clock signal clk 1 and the high level control signals en 1 a - en 1 c , the second pumping circuits 25 a - 25 c may start the pumping operation with the control signals en 1 a - en 1 c after the second operation clock signal clk 2 having an amplitude of 3 v is generated with the first operation clock signal clk 1 . although the voltage generating portion 1 b of the above - described third embodiment includes the three second charge pump circuits 20 a , 20 d , 20 e , the voltage generating portion may include three or more second charge pump circuits . further , different from the third embodiment , the voltage generating portion may include three first charge pump circuits as well as the three second charge pump circuits . distinguishable from the voltage generating portion 1 c of the fourth embodiment , the voltage generating portion may be provided in any one of the third buffer circuit 71 and the third buffer circuit 72 . if the voltage generating portion includes three first charge pump circuits as well as the three second charge pump circuits 20 a , 20 d , 20 e , one or more third buffer circuits connected to each first charge pump circuit may be included . distinguishable from the voltage generating portion 1 d of the fifth embodiment , the voltage generating portion may include the p type channel transistor instead of the n type channel transistor m 1 . in this voltage generating portion , the drain of the p type channel transistor is connected between the output of the second pumping circuit 25 a and the output terminal ( out 2 ) of the second charge pump circuit 20 a ′. the source of the p type channel transistor is connected to the external power supply line l 1 . the gate of the p type channel transistor is connected to the control circuit 80 . distinguishable from the voltage generating portion 1 d of the fifth embodiment , the voltage generating portion may control the switch sw to change from the terminal t 1 to the terminal t 2 corresponding to a result of detection of the voltage detecting portion connected to the output terminal ( out 2 ) of the second charge pump circuit 20 a ′. in this case , the voltage detecting portion detects that the value of the voltage v 2 is lowered relative to the value of the pumping voltage v 1 by the p type channel transistor and the control circuit 80 outputs the low level switch operation signal chn 2 without use of the second delay circuit 86 . distinguishable from the voltage generating portion 1 e of the sixth embodiment described above , the voltage generating portion may include the third delay circuit 90 between the control circuit and the logical product gate circuit and 1 , the third delay circuit 90 generating signals by delaying the control signal en 0 .