referring to fig2 a decoder 40 has n inputs 42 . 2 n row signal lines 44 are output from the decoder 40 and connected to an sram 46 . sram 46 is preferably a single column sram , having 2 n positions individually addressed by the row lines 44 of the decoder 40 . the value of the selected sram 46 entry is connected to a column signal line 48 which provides an input signal to sense amplifier 50 . the output of sense amp 50 provides output signal data out . a write driver 52 is also connected to the column line 48 . write driver 52 consists of p - channel transistor 54 and 56 , and n - channel transistors 58 and 60 . transistors 56 and 58 are connected to the column signal line 48 , and are driven by a signal data in . data in contains a value to be written into an sram 46 location . signals we ( write enable ) and we - bar are used to write data into the sram 46 . when we is high we - bar is low , which turns on transistors 54 and 60 . in this event , column line 48 is driven to a value determined by data in . if data in is high , column line 48 is driven to ground , and if data in is low , column line 48 is driven to v cc . the value placed on column line 48 is stored into whichever sram 46 position is currently addressed by the signals used to drive decoder 40 . fig3 shows the construction of a preferred macrocell 68 utilizing the circuitry described in connection with fig2 . macrocell 68 contains four decoders 70 and four associated srams 72 . decoders 70 each have four input signal lines and are each capable of addressing 16 bit positions . the corresponding srams 72 therefore each have 16 bit storage positions . separate control lines are provided to address each decoder , so that a total of 16 decoder control lines 74 are provided to the macrocell 68 . each sram drives a column signal line 76 which is connected to a circuit block 78 containing a sense amplifier and write driver as described in connection with fig2 . sense amplifier output lines 80 are connected to combinational and sequential logic blocks 82 , which in turn drive macrocell output lines 84 . logic blocks 82 preferably contain flip - flops and combinational logic to provide various output functions of the values on output lines 80 . four input data lines 86 are provided to the macrocell 68 , with one line being connected to the write driver in each circuit block 78 . control signal lines 88 are provided to the macrocell 68 , and serve a dual purpose depending on how the macrocell 68 is configured . switch 90 is used to route the signal lines 88 to write enable lines 92 or combinational and sequential logic control signal lines 94 . fig3 illustrates a view of the macrocell 68 seen by a user . not shown are the configuration bits and their associated control lines used to actually configure the macrocell 68 . for example , configuration bits are contained within the combinational and sequential logic blocks 82 which drive multiplexers to select which of the available logic functions are to be performed . these configuration bits are set at configuration time , and cannot be changed during normal use . switch 90 is defined at configuration time in a similar manner . if macrocell 68 is to be used for providing logic functions , control signals on lines 88 are switched to combinational and sequential logic control signal lines 94 . if the macrocell 68 is configured to function as user - writable sram , four of the signals 88 are switched to write enable signal lines 92 . when macrocell 68 is functioning as user - writable sram , combinational and sequential logic blocks 8i are configured to simply provide a direct connection between sense amp output lines 80 and macrocell output lines 84 . configuration of the various elements within the macrocell 68 is controlled by the settings of configuration bits within the macrocell 68 . as known in the art , these configuration bits are written to using a separate set of address and control lines from those seen by the user during normal operation , and this separate set of signal lines is not shown in fig3 . when macrocell 68 is configured to function as a logic block , data in signal lines 86 are ignored and the write drivers in blocks 78 are disabled . control signal lines 88 are switched to connect to signal lines 94 , and used to control the state of combinational and sequential logic blocks 82 . the signals on lines 92 are used to , for example , clock flip - flops , set or reset flip - flops provide output enable signals for signal lines 84 , and to perform similar functions . in this configuration , macrocell 68 operates much as do those used in the prior art . when macrocell 68 is configured to function as user - writable ram , switch 90 is configurated to route four selected control signals 88 to write enable signal lines 92 . four additional control signals 88 can be used to provide the output enable signals on lines 94 . the combinational and sequential logic blocks 82 are configured to provide a direct connection between signal lines 80 and signal lines 84 . the write drivers within logic blocks 78 are enabled , and data input signal lines 86 provide data thereto . when macrocell 68 is used as user - writable ram , decoder control signal lines 74 are interpreted as address lines . if desired , each of the decoders 70 can be provided with identical address inputs , which configures the macrocell 68 as a 16 × 4 ram . by proper selection of the control signals 74 , macrocell 68 can also be configured as a 32 × 2 ram or a 64 × 1 ram . to configure the macrocell 68 as a 64 × 1 ram , the four signal lines 84 are tied to a common point in a programmable switching matrix outside the macrocell 68 , with only one at a time being enabled by the output enable signals available on signal lines 94 . since the shape of the ram is determined by the decoder control lines 74 , the shape of the ram is actually configured in the programmable switching matrix which provides the input signal lines to the macrocell 68 . different macrocells 68 can be configured together so as to provide user - writable ram of any desired depth and width . as will be appreciated by those skilled in the art , the use of macrocells 68 which can be configured to provide logic functions or to function as user - writable ram allows increased flexibility in configuring a programmable logic device . if only dedicated ram is provided as user - writable ram , it is certain that in many cases the proportions of available user - writable ram and ram providing logic functions will not be correct . with a macrocell 68 which can be configured to provide either function , a user can configure the programmable logic device in the most efficient manner to allow full use of all elements on the chip . this allows one or a small number of standard parts to be used for a wide variety of applications . as described in related co - pending application ser . no . 414 , 712 , titled configuratiuon memory for programmable logic device , a battery backup system can be used to preserve the contents of all sram when power is lost to the programmable logic device . configuration data is retained during a power loss , so that the device need not be reconfigured each time it is powered up . in addition , since the same macrocells 68 are used for user - writable memory and for logic functions , the user - writable memory is also saved by the backup supply . while the invention has been particularly shown and described with reference to a preferred embodiment , it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention .