a schematic block diagram of a complete opto - electronic test system for automated quality testing of two - dimensional flat articles having a high density of geometric structure thereon is shown in fig1 . as shown therein , a movable compound table 1 has a test specimen 2 thereon disposed beneath a lens 3 . a plate 4 is situated above the lens 3 which has a mirrored surface for reflecting a portion of light reflected off of the test specimen 2 from a light source ( not shown ) to a tv camera 5 , and transmitting the remaining portion of the reflected light from the test specimen 2 to a semiconductor image sensor 6 . a television monitor 7 is connected to the output of the camera 5 for visual observation of the test specimen 2 preferably with a suitable enlargement . the semiconductor image sensor 6 may consist , for example , of a series of photodiode lines which generate a total of 256 image points . the output signal from the image sensor 6 is first supplied to an analog signal pre - processor 8 which includes a difference formation unit 9 and a post - connected extreme value determination unit 10 , each of which is described more completely below . the output of the analog signal pre - processor 8 is connected to a number of error recognition circuits which operate in parallel and in the embodiment shown consist of a minimum geometry test unit 11 , a solder eye test unit 12 and a special geometry test unit 13 . the minimum geometry test unit 11 includes a test unit 14 therein for examining track widths and a test unit 15 for examining insulation widths . the solder eye test unit 12 is comprised of a recognition unit 16 which determines that a solder eye is being examined and a measurement unit 17 for determining the completeness of the solder eye . the special geometry test unit 13 is comprised of a short circuit test unit 18 for determining the presence of short circuits in conductor runs , and an open circuit test unit 19 for determining the presence of open circuits in conductor runs . each of the above units is more fully described below . a resolution reduction unit 20 is interconnected between the solder eye test unit 12 and the output of the analog pre - processor 8 which reduces the field of view being examined by the solder eye test unit 12 by a factor of 4 . a programmable resolution reduction unit 21 is interconnected between the special geometry test unit 13 and the output of the analog pre - processor 8 which is programmable to reduce the field of view being examined by the special geometry test unit 13 by a factor of n . these units are also more fully described below . the various outputs of the test units 11 , 12 and 13 are supplied in parallel to an error signal evaluator 22 which processes the received error signals and after linking each error signal with a set of position coordinates stores the error signal and the coordinates for subsequent use . the coordinates are determined by a position sensor of any suitable type known in the art which is associated with the compound table 1 which provides a position signal output to a sequence control unit 23 which in turn transmits the position information to the error signal evaluator 22 . after a complete scan of the test specimen 2 , which is undertaken in a meandering path , the error signal evaluator 22 provides signals to the sequence control unit 23 for re - positioning the compound table 1 at locations where an error is determined to be present for visual examination and classification of the error on the monitor 7 . the block diagram shown in fig2 is an expansion of the difference formation unit 9 shown in fig1 . an input signal on a line 24 is supplied from the image sensor 6 to a series of analog shift registers 25 which delay the signal on a line - by - line basis . the shift registers 25 may , for example , be ccd shift registers , and may have an individual length of 256 image points . the outputs i through vi of these shift registers are conducted via separate lines to a 6 × 6 image field 26 . the image field 26 is generated by a point - by - point delay of the signals i through vi in the column direction . twenty points are selected from the field 26 , belonging to the four spatial directions shown in fig2 and are supplied via twenty separate lines to a differentiator 27 . in each direction , the difference between two adjoining points of the six points in each line is determined and a weighting is given to each such difference depending upon the distance which the points lie from the center of the field . these calculations are undertaken for each of the four spatial directions and the sums of the weighted differences are subsequently compared to one another in each direction . the result which is greatest in terms of magnitude is allocated as the center point of the field 26 . the weighted differential formations for each of the four directions are conducted over four separate lines to a maximum selector 28 which undertakes the comparisons shown therein and results in the selection of a differential formation which has the greatest magnitude . the output of the maximum selector 28 in fig2 serves as the input to a second series of analog shift registers 29 shown in fig3 . the signal received from the maximum selector 28 is therein delayed on a line - by - line basis by the shift registers . the shift registers may of the same type as described in connection with fig2 that is , ccd shift registers having an individual length of 256 image points . the outputs i through v of the shift registers 29 are conducted by five separate lines to a 5 × 5 image field 30 . this image field 30 is generated by means of a point - by - point delay of the signals i through v in the column direction . seventeen points are selected from this field which belong to the four spatial directions shown in fig3 and are supplied by seventeen separate lines to an extreme value recognition unit 31 . the maximum of the input signals is detected by means of a correlation with a programmed function and transmits this signal to a binary image generator 32 which generates an edge vector a m , n which corresponds to the centerpoint m , n of the field 30 . a reconstructed image signal 33 is achieved by means of evaluation of the edge vector a m , n and edge vectors a m - 1 , n and a m , n - 1 which precede the edge vector a m , n row - wise and column - wise . the output signal 33 of the binary image generator 32 is transmitted to a first series of digital shift registers 34 shown in fig4 which delay the signal 33 on a line - by - line basis . these digital shift registers 34 may , for example , be ttl shift registers having an individual length of 256 image points . the outputs i through x of these shift registers are conducted by separate lines to a 10 × 10 image field 35 . this image field is generated by a point - by - point delay of the signals i through x in the column direction . thirty - four points are selected from this field belonging to the four spatial directions shown in fig4 and are supplied via thirty - four separate lines to a unit 36 for undertaking a determination of the track width , that is a conductor track , and simultaneously are transmitted to a unit 37 for undertaking an examination of the insulation width . a minimum insulation width can be programmed into a memory 38 and supplied to the insulation width examining unit 37 , and a minimum track width can similarly be programmed into a memory 39 and supplied to the track width examining unit 36 . in accordance with the minimum dimensions set by the memories 38 and 39 , the signals received from the image field 35 are adapted as to length and in accordance with the four spatial directions shown in the unit 35 . a schematically shown within the units referenced at 36 and 37 , the continuous point sequences received from the image field 35 are examined as to a minimum width and the signals reformed in the units 36 and 37 , which comprise a maximum length of ten image points and are connected in succession in the four spatial directions shown in the unit 35 , are connected to a comparator store 40 which may , for example , be a rom . the comparator store 40 has outputs 41 and 42 . an error signal appears at the output 41 when a conductor track width falls below the minimum track width programmed into the memory 39 , and an error signal appears at the output 42 when an insulation width falls below the minimum insulation width programmed into the memory 38 . the units shown in fig4 together comprise the minimum geometry test unit 11 shown in fig1 . the output signal from the binary image generator 32 shown in fig3 is simultaneously applied to the input of a resolution reduction unit 20 as shown in fig1 and shown in greater detail in fig5 . the unit 20 has a plurality of digital shift registers 43 which may , for example , be ttl shift registers having an individual length of 256 image points . the outputs i through iv of these shift registers are conducted via four separate lines to a 4 × 4 image field 44 . this image field is generated by a point - by - point delay of the signals i through iv in the column direction . the sixteen image points of this field are supplied via sixteen separate lines to a summation unit 45 which sums the inputs and supplies an output to a comparator 46 which supplies a high output if the sum is greater than eight and a low output if the sum is less than or equal to eight at an output line 47 . the resolution of the area being viewed is thus reduced by a factor of four so that more data points can be supplied to the post - connected solder eye test unit 12 for examination of a larger area such as may be encompassed by various solder eye configurations . as shown in fig6 the solder eye test unit 12 consists of a series of digital shift registers 48 which receive their input from the line 47 . the shift registers delay the input signal on a line - by - line basis and may , for example , be ttl shift registers having an individual length of 256 image points . the outputs i through xv of these shift registers are conducted by fifteen separate lines to a 15 × 15 image field 49 . this image field is generated by a point - by - point delay of the signals i through xv in the column direction . from this field the image points are supplied via separate lines to a number of error recognition circuits which in the present embodiment consist of three circuits referenced at 50 , 51 and 52 . each error recognition circuit corresponds to a different solder eye pattern and it will be understood that any number of such error recognition circuits may be utilized depending upon the number of solder eye patterns expected to be encountered . as shown in fig6 each unit 50 , 51 and 52 respectively contains a memory for storing a particular solder eye pattern with circuit 50 having a memory 53a for a type &# 34 ; a &# 34 ; eye pattern , circuit 51 having a memory 53b for a type &# 34 ; b &# 34 ; solder eye pattern , and circuit 52 has a memory 53c for storing a type &# 34 ; c &# 34 ; eye pattern . the pattern in each of the memories is compared in a correlator 54 in each circuit which generates a recognition signal on line 55 if the input signal corresponds to the type of solder eye pattern stored in the respective memory . the signal on line 55 enables a measurement to be undertaken in an error signal generator 56 which examines the input signals to each circuit for metallization at specific locations within the solder eye pattern corresponding to the circuit . upon a determination of the absence of metallization at a point where metallization should occur , an error signal 57 is generated by the generator 56 . an identical operation is undertaken in the circuits 51 and 52 respectively if a &# 34 ; b &# 34 ; type pattern is recognized or a &# 34 ; c &# 34 ; type pattern is recognized . the output signal 33 from the binary image generator 32 shown in fig3 is simultaneously applied to the input of a programmable resolution reduction unit 21 shown in fig1 and 7 which operates in a manner identical to that described in fig5 except that the number of shift registers and the correspondingly generated image field is programmable and is programmed in dependence upon the width of the track and insulation widths which were programmed into the minimum geometry test unit 11 in the memories 38 and 39 . those connections are not directly shown on fig1 however , an input 58 to the unit 21 is shown in fig7 for receiving this information . the purpose of the unit 21 is similar to that of the unit 20 , that is , the unit reduces the resolution of the images supplied to the post - connected circuitry shown in fig7 so that a number of data points representing a larger area can be examined and analyzed by the circuitry therein . an output 59 of the unit 21 is connected to the input of a series of digital shift registers 60 which may , for example , be ttl shift registers each having a length of 256 image points . the outputs i through v of the shift registers are conducted via separate lines to a 5 × 5 image field 61 . this image field is generated by means of a point - by - point delay of the signals i through v in the column direction . from the field 61 , an inner region of nine image points is supplied to a comparator storage which may , for example , be a rom in which an error pattern for a track interruption or open circuit , as is shown in fig7 a , is stored in eight directions . also from the image field 61 , the overall contents thereof consisting of twenty - five image points is supplied to a second comparator storage 64 in which an error pattern 65 for a short circuit , as is shown in fig7 b , is stored in eight directions . if the comparison is undertaken in either unit 62 or 64 results in a correspondence with the respective open or short circuit conditions shown in fig7 a and 7b , an error signal respectively appears on the lines 66 or 67 . all of the outputs of the test units 11 , 12 and 13 are supplied to an error signal evaluator 22 which may consist , for example , of a siemens microprocessor system smp 80 having a data memory in which the instantaneous coordinates of the position sensor associated with the compound table 1 are read in with each occurrence of an error signal from any of the circuits 11 , 12 or 13 . signal delays which occur as a result of processing in the error recognition circuits 11 , 12 and 13 are compensated for by a transit time shift of the error coordinates in the data memory with respect to the location coordinates on the test specimen 2 . such compensation has already occurred when the error coordinates are read in . the error coordinates in the data memory of the microprocessor are subsequently employed during a test run to displace the compound table in such a manner that the error location becomes visible on the television monitor 7 . in order to aid in the classification and evaluation and ultimate correction of errors lying in close proximity , error locations having a difference in coordinates which is less than an adjustable preselected amount are grouped together and evaluated and viewed as a single error . such group evaluation of a number of individual errors in close proximity is known as error compression . the sequence control unit 23 is interconnected between the compound table 1 and the error signal evaluator 22 for transmittal in both directions of coordinate and error information during a testing process . a complete test operation is as follows . at the beginning of a test series a format for the surface to be tested such as a printed circuit or an intermediate product used in the manufacture of printed circuits , is supplied to the system by inserting the test specimen 2 in the system on the compound table 1 and manually tracing the periphery of the specimen 2 with a measuring head of a type known in the art . this manually traced periphery is then utilized for all further tests within a single test series . a test cycle is then begun which consists of moving the test specimen 2 in a meandering path by movement of the compound table 1 beneath the lens 3 . the data transmitted to the image sensor 6 is analyzed in the manner described above and at the end of a test cycle , the compound table is automatically moved to a first error position as controlled by the error signal evaluator 22 and the sequence control unit 23 which corresponds to the first set of coordinates at which a first error was determined to exist . the error can then be magnified and visually observed on the monitor 7 . all subsequent stored errors are automatically viewed in sequence for visual examiniation by means of key actuation . after evaluating all errors , the compound table returns to a zero position so that the next test specimen 2 can be inserted . although automatic discrimination and evaluation of the electronic error reports from the units 11 , 12 and 13 could be undertaken , such automatic discrimination would require substantial circuit outlay and would not appreciably increase the recognition certainty . the visual display of the error regions allows human evaluation of the area in which an error is present and increases the certainty of recognition of such an error because the area has been electronically selected and an operator thus knows that an error is present within the area and need only view the monitor in order to classify and correct the error . although modifications and changes may be suggested by those skilled in the art , it is the intention of the inventors to embody within the patent warranted hereon all changes and modifications as reasonably and properly come within the scope of their contribution to the art .