with reference to fig1 a and 1b , a semiconductor memory device 10 according to the present invention is illustrated . semiconductor memory device 10 , which is also referred to herein as a semiconductor device , includes a substrate 12 including an array of conductively doped regions 14 therein . preferably , substrate 12 comprises a p - type semiconductor material . doped regions 14 preferably comprise an n - type semiconductor material and may , therefore , also be referred to herein as n - wells . word lines 16 extend across a surface of substrate 12 in a substantially mutually parallel relationship to one another . the regions of substrate 12 disposed between adjacent word lines 16 are referred to as bit contact regions 18 . bit contact regions 18 that are doped ( i . e ., comprise doped regions 14 of substrate 12 ) are referred to as bit contacts 20 . bit contact regions 18 or the bit contacts 20 thereof are exposed to a surface of semiconductor memory device 10 by means of a trench 22 aligned between adjacent word lines 16 . sidewall spacers 17 , which are disposed adjacent word lines 16 , electrically isolate the conductive elements of word lines 16 from the adjacent trench 22 . a plug 24 of conductive material disposed within trench 22 and an adjacent strap 26 of conductive material provide an electrically conductive link between bit contact 20 and a corresponding digit line 28 that extends across semiconductor memory device 10 substantially perpendicularly to word lines 16 . each digit line 28 preferably includes a conductive element 30 , an insulative cap 32 disposed over conductive element 30 , and a sidewall spacer 34 disposed laterally adjacent conductive element 30 and opposite strap 26 . the conductive element 30 of each digit line 28 preferably includes a metal silicide layer 36 and a conductive layer 38 disposed over metal silicide layer 36 . conductive layer 38 preferably comprises polysilicon . preferably , digit lines 28 have a width of less than about 0 . 25 microns and , more preferably , of at most about 0 . 18 microns . adjacent digit lines 28 are preferably spaced less than about 0 . 30 microns apart from one another and , more preferably , at most about 0 . 22 microns apart from one another . thus , digit lines 28 preferably have a pitch of less than about 0 . 55 microns and , more preferably , of at most about 0 . 40 microns . turning now to fig2 - 16 , a method is illustrated by which digit lines 28 ( see fig1 a and 1b ) of a desired thickness and pitch may be fabricated upon and in communication with corresponding bit contacts 20 of a semiconductor memory device 10 . with reference to fig2 , a semiconductor memory device 10 , which includes a trench 22 through which a bit contact region 18 is exposed , is illustrated . the conductive elements of the word lines 16 of semiconductor memory device 10 that are adjacent bit contact region 18 are exposed to trench 22 . trench 22 may be defined by known processes , such as mask and etch techniques , in order to expose bit contact region 18 . as shown in fig3 , if bit contact region 18 of substrate 12 has not been doped , bit contact region 18 may be doped by known processes , such as by implanting bit contact region 18 with arsenic . alternatively , bit contact region 18 may be doped after digit lines 28 ( see fig1 a and 1b ) have been fabricated and prior to fabricating plug 24 or strap 26 ( see fig1 a and 1b ). as illustrated in fig4 , any portions of the conductive elements of word lines 16 that are exposed to trench 22 may be electrically isolated from trench 22 by means of sidewall spacers 17 . of course , sidewall spacers 17 may be fabricated , as known in the art , such as by exposing the conductive material of word lines 16 to an oxidizing temperature , or by disposing a known oxidizing material in contact therewith , or by disposing an insulative material adjacent the conductive material of word lines 16 and patterning the insulative material to define sidewall spacers 17 therefrom . referring to fig5 , a layer 40 of silicon nitride may be disposed over a surface of semiconductor memory device 10 . preferably layer 40 of silicon nitride is disposed substantially over the surface of semiconductor memory device 10 , including the bit contacts 20 thereof . layer 40 may be fabricated , as known in the art , such as by chemical vapor depositing (“ cvd ”) silicon nitride over the surface on semiconductor memory device 10 . such a silicon nitride layer 40 may subsequently be employed as an etch stop . turning to fig6 , one or more layers of digit line material or materials may be disposed over the surface of semiconductor memory device 10 . as illustrated , a first digit line layer 42 may comprise a metal silicide . preferably , first digit line layer 42 comprises a refractory metal silicide , such as titanium silicide , tantalum silicide , cobalt silicide , or tungsten silicide . first digit line layer 42 may be fabricated , as known in the art , such as by chemical vapor deposition or by fabricating adjacent layers of silicon and metal and annealing these layers to one another . a second digit line layer 44 may be disposed over first digit line layer 42 . second digit line layer 44 preferably comprises an electrically conductive material , such as a metal or polysilicon . second digit line layer 44 may be fabricated , as known in the art , such as by chemical vapor deposition or physical vapor deposition (“ pvd ”). with reference to fig7 , an insulative layer 46 may be disposed over the layer or layers of digit line material . as shown , insulative layer 46 is disposed over second digit line layer 44 . insulative layer 46 may be fabricated , as known in the art , such as by oxidizing an underlying layer 42 or 44 of digit line material or by disposing an electrically insulative material over layer 44 of digit line material by chemical vapor deposition , spin - on - glass (“ sog ”), or other known processes . as digit lines 28 are defined through the layer or layers of digit line material , insulative layer 46 may be employed as an insulative cap 32 ( see fig1 a and 1b ) over each of the digit lines 28 . referring now to fig8 - 8b , a first mask 48 may be disposed over the uppermost layer 44 of digit line material . as shown in fig8 a , first mask 48 includes a plurality of mutually parallel apertures 50 that are alignable over trenches 22 and bit contacts 20 . as illustrated , first mask 48 shields elongated areas of semiconductor memory device 10 , over which digit lines 28 are to be defined . as shown in fig8 b , first mask 48 also preferably shields the periphery 6 of each die 4 of a wafer 2 that includes a plurality of dice 4 . although first mask 48 may be fabricated by any known process , the use of photomask technology is preferred . when a photomask is employed as first mask 48 , a photoresist may be disposed over a surface of semiconductor memory device 10 by known processes , such as by spinning the photoresist onto semiconductor memory device 10 , and the layer of photoresist exposed and developed , as known in the art . with reference to fig9 and 9 a , digit lines 28 may be defined through first mask 48 . known patterning processes may be employed to define digit lines 28 and their overlying insulative caps 32 . preferably , one or more isotropic etchants are employed to remove the materials of insulative layer 46 , second digit line layer 44 , and first digit line layer 42 either directly or indirectly ( i . e ., through apertures formed through an overlying layer ) through apertures 50 of first mask 48 . with reference to fig1 , the underlying layer 40 of silicon nitride may also be removed by known processes , such as by the use of an isotropic etchant . with reference to fig9 b , if a first mask 48 that shielded the peripheries of dice 4 ( see fig8 b ) was employed , a second mask 52 may be employed to remove any regions of insulative layer 46 , second digit line layer 44 , first digit line layer 42 , or layer 40 of silicon nitride that remain at the peripheries 6 of dice 4 . preferably , second mask 52 substantially shields digit lines 28 and other features of semiconductor memory device 10 , which are collectively referred to herein as a central region of the semiconductor memory device , and includes apertures 54 that expose the peripheries 6 of dice 4 . second mask 52 may be disposed upon semiconductor memory device 10 and defined , as known in the art , such as by the use of photomask techniques . any digit line materials , insulative materials , or silicon nitride that remain on the peripheries 6 of dice 4 may be removed either directly or indirectly through second mask 52 by known processes , such as by the use of etchants . the masks 48 and 52 may each be removed from semiconductor memory device 10 by known processes . referring to fig1 , upon removing layer 40 of silicon nitride , bit contact regions 18 are again exposed through trenches 22 . portions of sidewall spacers 17 may also be removed as silicon nitride layer 40 is removed . accordingly , it may be necessary to re - isolate the conductive elements of word lines 16 from their corresponding trench 22 . again , known processes may be employed to fabricate sidewall spacers 17 adjacent the conductive elements of word lines 16 . since bit contact regions 18 of substrate 12 are again exposed through their corresponding trench 22 , bit contact regions 18 may be conductively doped , as known in the art , to form bit contacts 20 if such doping was not previously performed . referring now to fig1 , another mask 56 may be disposed over semiconductor memory device 10 . preferably , mask 56 comprises a photomask , which may be defined by known processes , such as by disposing a photoresist over semiconductor memory device 10 and exposing and developing selected regions of the photoresist . mask 56 preferably substantially fills each of the trenches 22 of semiconductor memory device 10 and , thereby , shields bit contacts 20 . mask 56 also extends laterally over a strap region 58 of the semiconductor memory device 10 . each strap region 58 is disposed between a trench 22 and its corresponding digit line 28 . thus , mask 56 may protrude from trench 22 and somewhat from the surface of semiconductor memory device 10 . preferably , mask 56 contacts an exposed , electrically conductive lateral edge portion of the adjacent digit line 28 . mask 56 is preferably hard - baked , as known in the art , to facilitate the fabrication of structures ( i . e ., conductive plugs and straps ) having the desired dimensions and configurations . turning to fig1 , another layer 60 of insulative material may be disposed over semiconductor memory device 10 . preferably , mask 56 is exposed through layer 60 of insulative material . insulative material layer 60 preferably has a substantially planar surface . accordingly , insulative material layer 60 may be fabricated by known tetraethylorthosilicate (“ teos ”) wet dip processes . alternatively , layer 60 of insulative material may be deposited over semiconductor memory device 10 by known processes , such as by chemical vapor deposition or spin - on processes . mask 56 may then be exposed through insulative material layer 60 by known processes , such as by planarizing insulative material layer 60 ( e . g ., by chemical - mechanical planarization (“ cmp ”)) or by employing a blanket isotropic etch - back . insulative material layer 60 preferably insulates the exposed lateral edges of digit lines 28 , and may cover digit lines 28 . with reference to fig1 , mask 56 may be removed from semiconductor memory device 10 by known processes , such as by the use of solvents or heat , and semiconductor memory device 10 washed . upon removing mask 56 from semiconductor memory device 10 , cavities 62 , which are defined by trenches 22 , insulative material layer 60 , and digit lines 28 , are exposed . as shown in fig1 , upon disposing a layer 64 of conductive material over semiconductor memory device 10 , cavities 62 are preferably substantially filled with the conductive material . thus , the conductive material of layer 64 establishes an electrically conductive link between each bit contact 20 and its corresponding digit line 28 . conductive material of layer 64 may be fabricated by known techniques , such as by physical vapor deposition ( e . g ., sputtering ) or by chemical vapor deposition . preferably , polysilicon is employed as the conductive material of layer 64 . referring to fig1 , the uppermost portions of conductive material layer 64 are preferably removed so as to substantially expose insulative material layer 60 through conductive material layer 64 . accordingly , the remaining portions of conductive material layer 64 are substantially confined within cavities 62 and define conductive plugs 24 and straps 26 . the uppermost portions of layer 64 may be removed by known processes , such as by employing blanket isotropic etch - back techniques . alternatively , another mask could be disposed over the semiconductor device and the plugs 24 and straps 26 defined through apertures thereof . with reference to fig1 , yet another mask 66 may be disposed over semiconductor memory device 10 . mask 66 preferably shields the portions of layer 64 of conductive material that are disposed within cavities 62 . mask 66 may also shield digit lines 28 . the remaining regions of semiconductor memory device 10 are preferably exposed through mask 66 . known processes may be employed to fabricate mask 66 , such as the use of photomask techniques . the regions of semiconductor memory device 10 that are exposed through mask 66 are preferably exposed to an anisotropic etchant in order to further define plugs 24 and straps 26 and to remove any stringers of the conductive materials employed in layers 42 , 44 , and 64 that may remain in these exposed regions . preferably , an isotropic etchant is then employed to remove any remaining conductive materials that are exposed through mask 66 . accordingly , the use of both an anisotropic and an isotropic etchant is useful to substantially remove any stringers that may extend from or between plugs 24 , straps 26 , or digit lines 28 and that may cause electrical shorts in semiconductor memory device 10 , while facilitating the fabrication of digit lines having a thickness of less than about 0 . 25 microns and a pitch of less than about 0 . 55 microns . an insulative layer may then be disposed over plugs 24 and straps 26 by known processes . other structures may also be fabricated over plugs 24 , straps 26 , and their corresponding digit lines 28 , as known in the art . although the foregoing description contains many specifics and examples , these should not be construed as limiting the scope of the present invention , but merely as providing illustrations of some of the presently preferred embodiments . similarly , other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention . the scope of this invention is , therefore , indicated and limited only by the appended claims and their legal equivalents , rather than by the foregoing description . all additions , deletions and modifications to the invention as disclosed herein and which fall within the meaning of the claims are to be embraced within their scope .