fig1 is an exemplary block diagram for an optical transceiver which incorporates one embodiment of the present invention . this figure , as with all the included figures , is for illustrative purposes , and does not limit the possible applications of the present invention , or limit the appended claims . this optical transceiver may be on a nic card with a media access controller , some memory , and other circuits . included is a receive path including a photo diode 110 , sensing resistor 112 , pre - amplifier 120 , amplifier 130 , dc offset correction circuit 150 , clock and data recovery circuit 140 , and link and data detect 160 . a transmit path having an amplifier 170 , light emitting diode ( led ) driver 180 , multiplexer 175 , oscillator 185 , and led 190 is also shown . a receive fiber optic cable 105 carries an optical data signal to the reversed - biased photo diode 110 . photo diode 110 senses the amount of light from fiber optic cable 105 , and a proportional leakage current flows from the device cathode to anode . this current flows though sense resistor 112 , thereby generating a voltage . this voltage is amplified by pre - amplifier 120 , and sent to amplifier 130 . dc offsets are reduced by dc correction circuit 150 . the output of the amplifier 130 drives the clock and data recovery circuits 140 , as well as the link and data detect block 160 . the clock and data recovery circuits extract the clock signal embedded in the data provided on line 135 by the amplifier , and uses it to retime the data for output on lines 143 . if the link and data detect block 160 senses either a data or link signal at the data line 135 , a valid link signal is asserted on line 167 . if the link and data detect block 160 senses a data signal at the data line 135 , a receive squelch signal is de - asserted on line 163 . transmit data is provided on line 173 to amplifier 170 . amplifier 170 is enabled by the transmit enable signal on line 177 . when amplifier 170 is enabled , transmit data is passed to the multiplexer 175 . multiplexer 175 passes the transmit data to the led driver 180 which in turn generates a current through light emitting diode ( led ) 190 . when current is driven through led 190 , light is emitted and transmitted on fiber optic cable 195 . when the led driver 180 is not driving current though led 190 , the led is off , and the fiber optic cable 195 is dark . if the amplifier 170 is disabled , multiplexer 175 selects the idle signal from oscillator block 185 . oscillator block 185 provides an idle signal through the multiplexer 175 to the led driver 180 . this idle signal is used by the receiver to ensure that a valid optical connection has been made at both ends of the fiber - optic cable 105 . as discussed above , the physical media limitations distort the received signal . moreover , the delay through the amplifier 170 , multiplexer 175 , led driver 180 , and led 190 may not be the same for a light - to - dark as for a dark - to - light transition . this mismatch causes what is referred to as a duty cycle distortion . further , electrical noise in the power supply and data path create jitter and phase noise , which is where the delay through the transmitter changes as a function of time . it is the function of clock and data recovery circuits , such as block 140 , to retime the data so it is in a more useable form for digital circuits , and provide a clock synchronized to the data . fig2 is a block diagram of a clock and data recovery circuit 200 , which may be used as block 140 in fig1 , as well as many other applications . this architecture is shown for exemplary purposes , and does not limit either the possible applications of the present invention , or the appended claims . other architectures will be readily apparent to those skilled in the art . for example , the charge pump may be included in the low - pass filter . included in fig2 are a half - rate phase detector 210 , charge pump 220 , low - pass filter 230 , and vco 240 . a differential data input is provided to the half - rate phase detector 210 on data lines 135 . alternately the data input may be single ended . demuliplexed data is provided on lines 215 and 217 . the half - rate phase detector compares data on lines 135 with the clock signals on line 147 , and outputs an error signal on line 222 that is proportional to the phase error between the clock and data signals . the half - rate phase detector 210 provides this error signal on line 222 , as well as a reference signal on line 224 to charge pump 220 . the reference signal on line 224 is a data dependent signal which is used to correct for the data dependence of the error signal on line 222 . charge pump 220 provides a correction signal that is filtered by low - pass filter 230 , and sent to the vco 240 . vco 240 provides the differential clock signal on line 147 which is used by the half - rate phase detector 210 for retiming the data input signal . these blocks form a feedback loop in which a clock signal is extracted from an incoming data stream , and used to retime the data . as its name implies , the voltage controlled oscillator is an oscillator , the frequency of which is controlled by a voltage , in this case the voltage vtune provided by the low - pass filter 230 . as the voltage out of the filter 230 changes , so does the oscillation frequency . if the data on line 135 and the clock on line 147 do not have the desired phase relationship , for example the data edges are occurring too soon , the half - rate phase detector 210 outputs an error voltage . this voltage drives the charge pump 220 , the output of which is filtered and applied to the vco 240 . this voltage has the result of increasing the vco frequency , such that the clock edges advance . when the desired phase relationship is achieved , vtune changes such that the frequency drops back to the “ correct ” frequency , and this loop is said to be locked . hence , these clock and data recovery circuits are often referred to as phase - locked loops , or plls . the frequency of the clock signal on line 147 is half the data rate of the data signal on lines 135 . the frequency of the half - rate phase detector outputs , data 1 on line 215 , and data 2 on line 217 , are each half the frequency of the data signal on lines 135 . also , the error signal on line 222 and the reference signal on line 224 provide a relatively low frequency , essentially differential , correction signal . these features provide several important benefits . for example , using a reference signal gives context to the error signal , reducing any loop dependency on the data pattern on data lines 135 . if there are no data transitions this loop has no error or reference signal information to use to lock , but since there is no data to recover , this special case is of no interest . further , the vco 240 operates at half the frequency as compared to conventional architectures . this not only saves power and simplifies the circuit design , but also enables using slower , more economical processes to achieve the same system function and performance . similarly , higher performing circuits may be implemented on the same process as compared to other architectures . for example , the data rate may be 10 gbits / sec , while the vco runs at 5 ghz . using two data outputs each operating at half the data rate also saves power . this is because it generally takes more than twice the power to double circuit speed in the absence of any design improvements . that is , a point of diminishing returns is reached where the application of more power fails to increase circuit speed proportionately . therefore , reducing the switching requirements by half results in a greater than expected power savings . architectures consistent with the present invention allow low cost processes to be used in demanding applications , for which they would not otherwise be suitable . also , conventional systems often employ what is known as a “ bang - bang ” phase detector . in bang - bang detectors , for each data edge , depending on its relation to the clock , a charge - up or charge - down signal is sent to a charge pump . such detectors alternate between advancing and delaying the clock signal from the vco , and never reach a stable point . accordingly , bang - bang detectors always have a systematic jitter . moreover , these pulses have fast edges containing high frequency components that couple to the supply voltage and inject noise into other circuits . reducing this noise requires either filtering , or using separate supply lines decoupled from each other . by using a low frequency , effectively differential signal out , the linear half - rate phase detector of the present invention does not have this systematic jitter , and does not disturb the power supply and other circuits to the same extent . fig3 is a block diagram for a vco 300 , which may be used as the vco 240 in fig2 . vco 300 includes three inverter elements in series . this architecture is generally known as a ring oscillator . the first inverter element is comprised of inverter 330 , inverter 320 , delay 310 , and summing junction 340 . the second inverter element includes inverter 370 , inverter 360 , delay 350 , and summing junction 375 . the third inverter element is comprised of inverter 390 , inverter 385 , delay 380 , and summing junction 395 . clock signals at the output of summing junction 340 are driven through inverter 370 , and also through delay 350 and inverter 360 , to the summing junction 375 . signals vfine and vcourse on lines 305 and 307 adjust the relative weighting of these two paths . for example , if inverter 360 is off and inverter 370 is on , the clock signal at 340 drives through inverter 370 to summing junction 375 with a minimum delay . if inverter 370 is off and inverter 360 is on , the clock signal at summing junction 340 drives through the delay 350 and the inverter 360 , and the signal is delayed a maximum amount . alternately , inverter 370 and inverter 360 may each be partially on , such that the signal at summing junction 375 is a composite of signals traveling through inverter 370 , and delay 350 and inverter 360 . in this case the delay from summing junction 340 to summing junction 375 is somewhere between the minimum and maximum delays . fig4 is a schematic for one of the three vco inverter elements shown in fig3 . included are a first inverter stage including m 1 410 , m 2 420 , and current sources 430 and 440 , and second inverter stage including m 3 445 , m 4 445 , and current sources 465 and 470 . the first inverter and the second inverter outputs share load resistors 490 and 495 , which correspond to the summing junctions shown in fig3 . signal vin at lines 405 and 415 coupled to the first inverter stage and the delay 450 . the delay 450 in turn couples to the second inverter . signals vfine on lines 475 and vcourse on line 480 , and their compliments on lines 476 and 481 , adjust the relative weighting of each inverter &# 39 ; s contribution to the output signal vout at lines 425 and 435 . using separate fine and course current sources allow for accurate overall delay control and greater noise immunity . the vout signal at lines 425 and 435 couple to the next inverter cell &# 39 ; s vin lines 405 and 415 . as an example , when vin is asserted high , that is the voltage on line 405 rises above the voltage on line 415 , m 1 410 turns on , and conducts current from the current sources 430 and 440 . this current flows through load resistor 490 , dropping the voltage on line 425 in relation to line 435 . similarly , after the delay set by delay block 450 , m 3 445 turns on and begins to conduct current from current sources 465 and 470 . this current also flows through load resistor 490 , thus completing vout &# 39 ; s high to low transition . with regards to the specific example shown in fig2 , a differential vtune voltage from the low - pass filter 230 could be used to drive the vfine and vfinebar inputs , while the vcourse and vcoursebar voltages could be driven by a second loop used for achieving frequency lock . alternately , the same loop could be used for frequency lock , or the same loop with some modifications could be used . fig5 is a block diagram for a half - rate phase detector which may be used as block 140 in the transceiver of fig1 , as well as other applications . included are a first latch 510 , a second latch 520 , a third latch 560 , a fourth latch 570 , first xor gate 540 , second xor gate 550 , and buffers 530 and 580 . all signal paths are shown as being differential , but may alternately be single - ended . for example , the data may be a single - ended signal on line 505 , with line 515 coupled to a bias point , preferably at a voltage approximately equal to the middle of the data input voltage swing . in the preferred embodiment shown here , all signal paths are differential , except for the error and reference signal paths , which are single - ended . using differential signals reduces the jitter caused by noise from such sources as the power supply and bias lines . modifications to this block diagram will be readily apparent to one skilled in the art . for example , the first and second latches may be replaced by a flip - flop . clock signal clockx clocks the first latch 510 and the fourth latch 570 . complementary clock signal clocky clocks the second latch 520 and the third latch 560 . differential data signal is provided on lines 505 and 515 to the first latch 510 and the third latch 560 . when the clockx line is high , data on lines 505 and 515 pass to the a lines 511 and 512 . when clockx is low , data on lines 505 and 515 are latched in first latch 510 . conversely , when the clockx signal is high , the clocky signal is low , and data on lines 505 and 515 are latched by the third latch 560 . when the clocky signal is high , data on lines 505 and 515 pass to the b lines 561 and 562 at the output of the third latch 560 . signals on the a line 511 and 512 , and the b lines 561 and 562 are xored by the first xor gate 540 producing an error signal on line 585 . signals on the a lines 511 and 512 , and the b lines 561 and 562 , are latched by the second latch 520 and the fourth latch 570 . specifically , when the clocky signal is high , the signal on lines 511 and 512 pass through the second latch 520 to lines c 521 and 522 . but when clocky is low data on lines 511 and 512 are latched by the second latched 520 . similarly when clockx is high , data on the b lines 561 and 562 pass through the fourth latch 570 to the d lines 571 and 572 . when clockx is low , data on the b lines 561 and 562 are latched by the fourth latch 570 . data at the outputs of the second latch 520 and the outputs of the fourth latch 570 are xored by the second xor gate 550 producing a reference signal on line 555 . data at the outputs of the second latch 520 , the c lines 521 and 522 , drive the first buffer 530 which outputs the first demultiplexed data signal on lines 535 and 545 . the outputs of the fourth latch 570 , lines d 571 and 572 , drive the second buffer 580 , which outputs the second demultiplexed data signal on lines 565 and 575 . the error signal on line 585 and reference signal on line 555 are sent to the charge pump . to improve performance , some circuit delay time and trace paths should be matched to each other . specifically , the first latch clock - to - output delay and the traces coupling the first latch to the second latch and the xor gate 540 should match the third latch clock - to - output delay and the traces coupling the third latch to the fourth latch and the xor gate 540 . also , the second latch clock - to - output delay and the traces coupling the second latch to the buffer 530 and the xor gate 550 should match the fourth latch clock - to - output delay and the traces coupling the fourth latch to the buffer 580 and the xor gate 550 . fig6 is a schematic for an exemplary circuit implementation of a latch used for the first latch 510 , and fourth latch 570 , in fig5 by one embodiment of the present invention . it will be obvious to one skilled in the art that other latches can be used , for example a bipolar latch could be used . the second latch 520 and third latch 560 may be similar , with the exception that the clockx and clocky terminals are reversed . included are input differential pair devices m 1 610 and m 2 620 , latching devices m 3 630 and m 4 640 , clock input devices m 5 670 and m 6 680 , and current source m 7 690 . current for the latch is generated by m 7 690 . a voltage vcs is applied to the gate of m 7 690 resulting in a bias current flowing in its drain . this current is steered through either m 5 670 , or m 6 680 , by the clockx and clocky signals on lines 675 and 685 . if the voltage on line 675 is higher than the voltage on 685 , that is clockx is high and clocky is a low , the drain current of m 7 is steered through m 5 670 to the differential pair m 1 610 and m 2 620 . in this case , the signals dx on line 615 and dy 625 are passed to the output lines qx 635 and qy 645 . for example , if the signal dx on line 615 is higher than the signal dy on line 625 , the current from m 5 670 flows through m 1 610 across load 650 pulling qy line 645 low . m 2 620 is off , the voltage at qx lines 635 is pulled up to vcc , and is high . conversely , if the signal dx on line 615 is lower than the signal dy on line 625 , m 1 is off , qy is high , m 2 is on , and the current from m 5 flows through the load resistor r 2 660 and the signal qx 635 is low . if the signal clockx on line 675 is lower than the voltage of the signal clocky on line 685 , m 5 is off , and the current from the drain of m 7 690 passes through m 6 680 . if qx on line 635 is high and the signal qy on line 645 is low , m 3 630 is on , and m 4 640 is off . the current from m 6 680 flows through m 3 630 across load resistor r 1 650 pulling down and keeping qy on line 645 low . m 4 649 is off , whereby the signal qx on line 635 remains high . in this way the data on lines qx 635 and qy 645 remain latched . input pair devices m 1 and m 2 are both off , so any signal changes at dx and dy , lines 615 and 625 have no effect on the output signals qx and qy on lines 635 and 645 . fig7 a is a truth table for an xor gate . the xor function is deconstructed into the or of 2 nor terms in column 702 . the xor gate shown in fig7 b is designed using this equivalent expression . fig7 b is an exemplary xor gate implemented in accordance with truth table column 702 of fig7 a . the alternative expression from fig7 a allows for designing an xor gate without using stacked devices . this in turn , eliminates the mismatch between gate delays for different inputs which otherwise result . included in this xor gate are a first nor gate including m 1 705 , m 2 710 , and m 3 715 , a second nor gate including m 4 720 , m 5 725 , and m 6 730 , current sources m 9 740 and m 10 745 , output current mirror m 7 750 and m 8 755 , output load resistor 765 , and output offset current source 760 . bias voltage vcs is applied to the gates of m 9 740 and m 10 745 , thereby generating bias currents in their drains . the signals ax on line 707 and by on line 712 swing above and below the signal voltage vb on line 717 . for example if either ax or by are higher than vb , the drain current of m 9 is shunted through m 1 705 or m 2 710 to vcc , line 733 . if both the ax signal on line 707 and the by signal on line 712 are low or below the voltage vb on line 717 , the current from the drain of m 9 passes through m 3 715 to m 7 750 . similarly , only if the signals ay on line 727 and bx on line 732 are low or below the voltage vb on line 717 , does the current from the drain of m 10 pass through the device m 4 720 to m 7 750 . current in m 7 750 is mirrored in the drain of m 8 755 and applied across output load resistor 765 , generating a voltage at the x output on line 757 . output offset current 760 creates a dc voltage at the output for proper biasing to the charge pump . using pmos devices for m 7 750 and m 8 755 limits the error and reference signals &# 39 ; bandwidth . the xor gate smoothes the logical outcome by first performing a high - speed logical operation , and then low - pass filtering the output . but this is advantageous to the overall system . for example , the power supply noise injected by this xor gate is very limited , since high frequencies are attenuated by the pmos mirror . also , this gate provides some high frequency filtering , thus reducing the burden on the following charge pump and low - pass filter . an alternate embodiment for an xor gate can be found in commonly assigned u . s . provisional patent application ser . no . 60 / 183 , 169 , filed feb . 17 , 2000 , titled “ linear full - rate phase detector and clock data recovery circuit using the same ,”. also , other architectures which may be used to implement some of the circuits herein can be found in commonly assigned u . s . pat . no . 6 , 424 , 194 , titled “ current controlled cmos logic family ,”, which is incorporated herein by reference . fig8 is a charge pump which may be used as charge pump 220 in fig2 , as well as other applications . included are a common mode circuit including m 7 805 , m 5 810 , m 6 815 , m 8 830 , m 9 835 , and amplifier including m 1 820 , m 2 825 , m 3 840 , and m 4 845 , and current sources m 10 850 and m 11 855 . the error signal on line 822 , and the reference signal on line 827 , are provided as differential inputs to the amplifier . bias voltage vcsp is applied to the gates of m 10 850 and m 11 855 , thereby generating currents in their drains . if the error voltage on line 822 rises above the reference voltage on line 827 , the current through m 1 increases and the voltage on line 817 increases . correspondingly the current and m 2 825 decrease , thereby lowering the voltage on line 812 . if the common mode voltage on lines 817 and 812 is too high , devices m 5 810 and m 6 815 shut off . the current in m 7 805 increases , thus increasing the current in m 9 835 which is mirrored in devices m 3 840 and m 4 845 . this increase in current tends to drive down the voltages on lines 817 and 812 . in this way , vout &# 39 ; s common mode is adjusted to be centered around the voltage vref on line 807 . the charge pump provides a differential output voltage proportional to the difference between the error and reference signals , and provides them at the correct bias point for use by following circuits . fig9 is a timing diagram for a half - rate phase detector consistent with one embodiment of the present invention , such as the circuit illustrated in fig5 . this and the following timing diagrams are not limited to the circuit shown in fig5 however , and may be generated by other circuitry consistent with the present invention . shown are input waveforms clockx 900 and data 910 , and resulting waveforms a 920 , b 930 , error 940 , c 950 , d 960 , and reference 970 . in a preferred embodiment , clockx 900 is approximately a 50 percent duty cycle waveform , but clock signals with other duty cycles , such as 33 or 67 percent may be used . alternately , other duty cycles may be used consistent with the present invention , such as 40 or 60 percent . waveform a 920 follows the data signal 910 when clockx 900 is high . when clockx 900 returns low , the signal on waveform a 920 is latched , or stored , and does not respond to changes in data 910 . conversely , waveform b 930 follows the data signal 910 when clockx 900 is low . when clockx 900 returns high , the signal on b 930 is latched , or stored , and does not respond to changes in data 910 . the signal a 920 is xored with the signal b 930 , resulting in the error waveform 940 . for some time following each clockx rising and falling edge , the a 920 and b 930 signal levels are equal . this is because one signal has just latched , while the other had been latched and is now following the data signal 910 . during this time the error 940 signal level is low . if the signal level at data 910 changes , the error signal 940 is asserted high . if the data 910 signal level does not change , but rather remains constant , error 940 remains low . for example if data bit 902 and data bit 904 are both low , then error signal portion 906 is low . waveform c 950 follows signal a 920 when clockx 900 is low . when clockx 900 returns high , c 950 is latched , its value stored , and accordingly its value is retained until clockx 900 returns low . waveform d 960 follows signal b 930 when clockx 900 is high . when clockx 900 returns low , signal d 960 is latched , its value stored , and so its value is retained until clockx 900 returns high . signals c 950 and d 960 are the demultiplexed data outputs . for example , data bits of data signal 910 have been sequentially labeled 0 , 1 , 2 , and so on . waveform c 950 comprises the odd bits of data waveform 910 , and waveform d 960 comprises 0 and the even bits of data waveform 910 . waveforms c 950 and d 960 are xored , resulting in reference 970 . error signal 940 is dependent on the phase relationship between data 910 and clockx 900 in the following manner . for example , if data bit 904 is low and data bit 912 is a high , then error pulse 916 is high . if the data signal 910 advances , that is shifted to the left , then pulse 916 in the error signal 940 widens ( becomes longer in duration ). if the data signal 910 is delayed , that is shifted to the right , then pulse 916 of error signal 940 narrows ( becomes shorter in duration ). but note as above , if data pulse 904 and data pulse 912 are equal , then data pulse 916 is low . therefore , the average voltage of error waveform 940 is dependent not only on the phase error between clockx 900 and data 910 , but on the data pattern of data 910 . for this reason , the error signal 940 is most meaningful in the context of reference signal 970 . if we assume random data , that is the probability of each in data bit and 902 being high or low is equal , then half of all error pulses 906 are high and half are low . if the clockx 900 and data 910 signals are in quadrature , that is they are at right angles or ninety degrees shifted apart , then for half the time between clock edges the error signal 940 is low , and half the time it is an error pulse that may be low or high . accordingly , for random data , when phase lock is achieved , the average signal level of error signal 940 is one - fourth its peak value . the average value of reference signal 970 is also data dependent . for example , if data bit 902 and 904 are both low then reference bit 918 is low . but if data bit 904 and data bit 912 are not equal , reference bit 928 is high . for random data the probability of two consecutive bits being equal is the same as the probability of two consecutive bits being unequal . thus , half the reference bits 918 are low , and half are high . therefore , the average value of the reference signal 970 is half its peak value . if the data is not random , for instance if data 910 is a long string of either high or low data bits , then error pulses , such as 906 , and reference pulses , such as 917 are low . the error signal &# 39 ; s average value is at a minimum , as is the reference signal 970 . but if the data changes every bit , then each error signal pulse and each reference bit is high . therefore the error signal is equal to half its peak value and the reference signal equals its peak value . thus , the error signal and reference signal divided by two have the same data pattern dependency , while the error signal also tracks the phase error . this means the data dependency of error signal 940 can be corrected by subtracting half the average value of the reference signal 970 . from a circuitry implementation , this means in fig7 , pmos mirror devices m 7 750 and m 8 755 should be scaled differently for xor gates 540 and 550 in fig5 . specifically , either m 8 can be doubled , or m 7 can be halved in xor gate 540 as compared to xor gate 550 . the difference signal between the error and one - half the reference signals is not dependent on the data pattern , but is dependent on the phase error . this resulting signal has approximately a zero value when the data signal &# 39 ; s edges are aligned with the center between the clock edges . as the data is delayed , the differential value becomes negative . as the data advances , the difference becomes positive . this pattern dependency reduction of the half - rate phase detector output reduces the pattern dependent phase error that would otherwise occur , though there may be random pattern dependent jitter that would remain unaffected . each data bit has a duration t 1 943 . the reciprocal of the data bit duration t 1 943 is referred to as the data rate . each clock period has a duration t 2 947 , where t 2 is equal to twice t 1 . the clock frequency , or clock rate , is the reciprocal of the duration t 2 947 . therefore , the clock frequency is half the data rate . it is interesting to note that the data and clock signals &# 39 ; switching frequency , that is the reciprocal of the duration between rising and falling edges , is the same . in conventional systems , the clock &# 39 ; s switching rate is twice what is shown in fig9 . accordingly , the vco &# 39 ; s bandwidth and related clock path for circuitry implementing fig9 is half that of conventional systems . this provides a savings in power , and eases the complexity and risk of the circuit design . fig1 is a timing diagram of the various waveforms for a half - rate phase detector used in one embodiment of the present invention . included are input waveforms clockx 1000 and data 1010 , and resulting waveforms a 1020 , b 1030 , error 1040 , c 1050 , d 1060 , and reference 1070 . this timing diagram is for a specific data 1010 input pattern . each transition in data 1010 , such as 1002 and 1004 , results in pulses in error signal 1040 , specifically 1006 and 1008 , and high reference bits 1012 and 1014 . fig1 is a timing diagram of the various waveforms for a half - rate phase detector used in one embodiment of the present invention . included are input waveforms clockx 1100 and data 1110 , and resulting waveforms a 1120 b 1130 , error 1140 , c 1150 , d 1160 , and reference 1170 . data waveform 1110 is the same as data waveform 1010 in fig1 . in this specific example , data waveform 1110 has been delayed relative to clockx waveform 1100 . again , each transition in data waveform 1110 , such as 1102 and 1104 , results in pulses in error waveform 1140 , specifically 1106 and 1108 , and high reference bits 1112 and 1114 . but this time , since the data waveform 1110 has been delayed , error pulses 1106 and 1108 are narrower than the corresponding pulses 1006 and 1008 in fig1 . accordingly , the average value of error signal 1140 is lower than the average value of error signal 1040 in fig1 . reference bits 1112 and 1114 , however , are the same as reference bits 1012 and 1014 in fig1 . therefore , the same data waveform 1110 in fig1 , and 1010 in fig1 , results in a lower error value . but the same reference signal , shown as 1170 in fig1 and 1070 in fig1 , is achieved , so the reference signal is independent of the phase error , but it is dependent on the data pattern . fig1 graphs the error voltage and reference voltage outputs for a half - rate phase detector consistent with one embodiment of the present invention . the voltages of error signal 1210 and reference signal 1220 are graphed as a function of the phase error between the data and clock signals . error signal 1210 is proportional to the phase error . error signal 1210 may be linear . alternately , error signal may have nonlinear characteristics . reference signal 1220 is approximately independent of the phase error , but is a function of the data pattern . reference signal 1220 may become discontinuous or notched when the phase error is near plus or minus 180 degrees . fig1 is a flow chart for a method of recovering data and clock signals from a data stream consistent with one embodiment of the present invention . in act 1310 , a data input signal , a clock signal , and the clock signal complement are provided . the data input is applied to a first latch clocked by the first clock signal in act 1320 . the data is applied to a second latch clocked by the complementary clock signal in act 1330 . in act 1340 the first latch &# 39 ; s output is applied to a first xor gate and a third latch . the second latch &# 39 ; s output is applied to the first xor gate and a fourth latch in act 1350 . in act 1360 , the third latch &# 39 ; s output and the fourth latch &# 39 ; s output are applied to a second xor gate . the first xor gate &# 39 ; s output is used as an error signal , the second xor gate &# 39 ; s output is used as a reference signal , the third latch &# 39 ; s output is used as a first data output , and the fourth latch &# 39 ; s output is used as a second data output in act 1370 . in act 1380 the error signal is subtracted from half the reference signal , and filtered . the filter output is used to adjust the clock signal and its complement in act 1390 . embodiments of the present invention have been explained with reference to particular examples and figures . other embodiments will be apparent to those of ordinary skill in the art . therefore , it is not intended that this invention be limited except as indicated by the claims .