exemplary embodiments of the invention described herein provide a method , system , and computer program product for processor error checking . in accordance with such exemplary embodiments , processor error checking for reliability availability serviceability (“ ras ”) is provided without the use of duplicate processing circuitry . turning now to the drawings in greater detail , wherein like reference numerals indicate like elements , fig1 illustrates an example of a computer system 100 including an exemplary computing device (“ computer ”) 102 configured for processor error checking . in addition to computer 302 , exemplary computer system 100 includes network 120 and other device ( s ) 130 . network 120 connects computer 102 and other device ( s ) 130 and may include one or more wide area networks ( wans ) and / or local area networks ( lans ) such as the internet , intranet ( s ), and / or wireless communication network ( s ). other device ( s ) 130 may include one or more other devices , e . g ., one or more other computers , storage devices , peripheral devices , etc . computer 102 and other device ( s ) 130 are in communication via network 120 , e . g ., to communicate data between them . exemplary computer 102 includes processor 104 , main memory (“ memory ”) 106 , and input / output components ) 108 , which are in communication via bus 103 . processor 104 may include multiple ( e . g ., two or more ) processors , which may implement pipeline processing , and also includes cache memory (“ cache ”) 110 , controls 112 , and one or more components configured for processor error checking that will be described below . cache 110 may include multiple cache levels ( e . g ., l1 , l2 , etc .) that are on or off - chip from processor 104 ( e . g ., an l1 cache may be on - chip , an l2 cache may be off - chip , etc .). memory 106 may include various data stored therein , e . g ., instructions , software , routines , etc ., which , e . g ., may be transferred to / from cache 110 by controls 112 for execution by processor 104 . input / output component ( s ) 108 may include one or more components , devices , etc . that facilitate local and / or remote input / output operations to / from computer 102 , such as a display , keyboard , modem , network adapter , ports , etc . ( not depicted ). fig2 illustrates an example of a processor pipeline staging 200 of exemplary computer 102 that is configured for processor error checking . exemplary pipeline staging 200 may , e . g ., be implemented by processor 104 . stage ( or cycle ) d 1 ( or d 1 stage ) and stage d 2 are decode stages during which one or more instructions can be decoded in parallel and saved in one or more stage latches or holding tanks (“ ht ”). stage d 3 is a multiplexing stage during which one or more decoded instructions (“ instruction processing data ” or “ instruction data ”; e . g ., instruction address data and instruction text data ) from ht and from one or more instruction queues and address queues (“ iq / aq ”) 204 are multiplexed . iq / aq 204 is updated when instruction processing data from ht is delayed from moving to stage g 1 , e . g ., due to one or more stalls in one or more downstream stages . stage g 3 is a dispatch stage during which instruction processing data is sent to execution units such as a fixed point unit (“ fxu ”). also , during stage g 3 , one or more register reads are performed in preparation for forming a memory address . an address calculation for ( e . g ., for accessing a data cache memory 110 ) is performed during stage a 0 . during stage a 1 and stage a 2 , the cache memory is accessed , and during stage a 3 , cache data is formatted and routed to the fxu for use during instruction execution . cache misses are broadcasted during stage a 4 and acted upon during stage a 5 and stage a 6 . if an instruction for a fetch operation or store operation misses the cache , the instruction is recycled back from stage a 5 into stage g 1 , a recycle queue 208 ( e . g ., ten entries deep ) is used to sufficiently maintain the instructions in case they need to be recycled . an instruction address queue (“ iaq ”) 212 holds one or more instruction addresses (“ ia ” or “ instruction address data ”) of instructions successfully decoded ( e . g ., during stage g 3 ) and maintains the ia until a post recycling point of the instructions ( e . g ., stage a 6 ). an ia from an instruction fetch unit (“ ifu ”) is sent ( e . g ., two cycles ) after the instruction text (“ itext ” or “ instruction text data ”) of the instruction . the itext is used ( e . g ., immediately ) in stage d 1 for decoding and the ia is used in stage a 0 in an address generation adder ( not depicted ) to calculate information such as a relative branch target address or a relative cache address . data in iq / aq 204 along with stages g 1 , g 2 and g 3 are used for grouping information , address generation interlock / bypass , binary floating point dispatch , general purpose register (“ gpr ”) reads for address generation , etc . instructions are decoded and stacked in iq / aq 204 while there are empty entries if stage g 1 is stalled . as instructions are read from iq / aq 204 into latches for stage g 1 , information about potential grouping is collected and sent to one or more controls (“ control ” or “ controls ”). during stage g 1 , grouping bits are examined and a control determines whether the two instructions can be grouped . if the two instructions in the stage g 1 latches can be grouped together , both instructions move from stage g 1 to stage g 2 to stage g 3 . alternately , if the instructions cannot be grouped , they are split . for example , the older instruction is moved to stage g 2 while the younger instruction is moved from a younger pipe to an older pipe and another instruction fills the slot in the younger pipe . fig3 illustrates an example of a processor pipeline subsystem 300 of exemplary computer 102 in accordance with exemplary processor pipeline staging 200 . exemplary subsystem 300 includes an instruction decoder 302 , which can decode one or more instructions into instruction processing data . decoder 302 is in communication with holding tank ( ht ) 304 , which is a stage latch that can hold a decoded instruction ( i . e ., instruction processing data ), e . g ., if one or more downstream components along path 305 are busy or otherwise unavailable , ht 304 is in communication via path 307 with parity generator 306 , which can generate one or more parity bits ( or “ parity data ”) based on the instruction processing data . parity generator 306 is in communication with stage latch 308 , which is in communication with iaq 212 ( which was described above ). iaq 212 is in communication with stage latch 310 , which is in communication with stage latch 312 . stage latch 312 is in communication with parity data compare unit 314 , which , e . g ., may include logic gate circuitry such as one or more logic - xor gates . ht 304 is also in communication with iq / aq 204 ( which was described above ) via path 303 . iq / aq 204 is in communication with multiplexer 328 , which is also in communication with bypass 327 and recycle path 329 . multiplexer 328 is in communication with g 1 stage latch 324 ( i . e ., associated with stage g 1 ), which is in communication with g 2 stage latch 326 ( i . e ., associated with stage g 2 ). g 2 stage latch 326 is in communication with g 3 stage latch 316 , which is in communication with recycle queue 208 and parity generator 318 . recycle queue 208 is also in communication with multiplexer 328 via path 329 . parity generator 318 is in communication with stage latch 320 , which is in communication with parity data compare unit 314 . the components ( e . g ., 204 , 328 , 324 , 326 , 316 , 208 ) along path 305 between ht 304 and parity generator 318 can be considered an instruction processing pipeline 350 , and the components ( e . g ., 212 , 308 , 310 , 312 ) can be considered an instruction queue pipeline 370 . control 322 is in communication with and / or control of one or more components of queue pipeline 370 and may also be in communication with and / or control of one or more components of processing pipeline 350 . furthermore , processing pipeline 350 may be controlled by control 323 independently of queue pipeline 370 , which is controlled by control 322 . latches 308 , 310 , 312 , 320 324 , 326 facilitate the synchronization of processing pipeline 350 and queue pipeline 370 . therefore , alternate configurations , such as additional or fewer latches , may be included in some embodiments accordingly . subsystem 300 provides reliability availability serviceability (“ ras ”) checking in accordance with exemplary embodiments described herein without the use of duplicate processing circuitry for processor error checking . in an exemplary operation , one or more instructions are received at instruction decoder 302 and decoded into instruction processing data . the instruction processing data may be held in ht 304 prior to proceeding along path 305 to processing pipeline 350 ( e . g ., if one or more components of pipeline 350 are busy or otherwise unavailable ). concurrently , the instruction processing data ( e . g ., instruction address data ) proceeds along path 307 in queue pipeline 370 . along path 307 , parity generator 306 generates one or more parity bits (“ pre - processing parity data ) based on the instruction processing data . the parity bits are maintained ( e . g ., stored ) along with ( e . g ., asynchronous ) instruction processing data ( e . g ., instruction address data ) in iaq 212 and may be accessed ( not depicted ) by pipeline 350 or other pipelines ( e . g ., during stage g 3 ) for use in address generation ( e . g ., during stage a 0 of relative instruction data ). the parity bits for the unprocessed instruction data proceed through queue pipeline 370 to parity data compare unit 314 , and the instruction processing data ( e . g ., instruction address data ) and / or the parity bits may also proceed to other components , paths , etc . ( not depicted ). concurrent to the instruction data flow ( i . e ., instruction address data and instruction parity data ) along path 307 and through instruction queue pipeline 370 , instruction processing data ( e . g ., instruction address data and instruction text data ) proceeds ( e . g ., after release from ht 304 if needed ) along path 305 to instruction processing pipeline 350 . some of the instruction data may proceed along iq / aq bypass path 327 to multiplexer 328 , while other instruction data may be held in iq / aq 204 ( which may , e . g ., be six entries deep in some embodiments ), e . g ., if one or more downstream components of pipeline 350 are busy or otherwise unavailable to process the instruction data ( i . e ., there are one or more stalls ). recycled instruction data may also proceed to multiplexer 328 via recycle queue path 329 . the instruction processing data is appropriately prioritized ( e . g ., arbitrated ) through multiplexer 328 to g 1 stage latch 324 , onto g 2 stage latch 326 , and onto g 3 stage latch 316 , during which processing such as grouping , dispatching , etc . of the instruction data may be performed . after g 3 latch 316 , some of the instruction data may be recycled by proceeding to recycle queue 208 and back to multiplexer 328 to proceed through stages g 1 , g 2 , g 3 , which recycle flow may occur one or more times . instruction data may , e . g ., be recycled if the instruction data can not proceed to other downstream components , pipelines , etc . ( not depicted ), e . g ., if busy or otherwise unavailable , or if an error is detected in the instruction data . instruction processing data proceeds ( e . g ., directly or after recycling ) from stage g 3 latch 316 to parity generator 318 where one or more parity bits (“ post - processing parity data ) are generated based on the processed instruction data . the instruction processing data also proceeds to other stages , components , pipelines , etc . ( not depicted ) to complete the instruction processing . the processed instruction parity bits proceed to parity data compare unit 314 and are compared to the unprocessed instruction parity bits from queue pipeline 370 . if the parity bits from the two pipelines 350 , 370 do not match , then an error related to the processing ( e . g ., staging , queuing , etc .) of the instruction data has occurred and been detected . for example , the error detected by the parity data mismatch may be a data error ( e . g ., one or more data bit - flips , e . g ., per parity group ) or a control error ( e . g ., a lack of synchronization between the controls 322 , 323 ). as a result , an error signal is generated by compare unit 314 . for example , parity data compare unit 314 may output a logic - 0 signal if no error is detected or a logic - 1 signal if an error is detected ( or vice versa ). as discussed above , compare unit 314 may include logic gate circuitry such as one or more logic - xor gates . error output 315 can be communicated , e . g ., to an instruction recovery unit ( not depicted ), which may trigger a block of creating a checkpoint for the completion of the instruction data processing and a recovery of the instruction data for reprocessing to negate the error ( i . e ., an error recovery operation ). for example , a checkpoint and recovery operation may be triggered in which transient updates made as a result of processing the instruction data are discarded and processing is restarted at the most previous checkpoint ( i . e ., correctly architected ) state before the processing error occurred . instruction processing pipeline 350 and instruction queue pipeline 370 are both normally utilized for processing purposes in computer 102 . therefore , duplicate circuitry is not needed for processor error checking in accordance with the foregoing exemplary operation . fig4 illustrates an example of a method 400 for processor error checking executable , e . g ., on exemplary computer 102 . in block 402 , instruction processing data is received . for example , a decoded instruction is received ( e . g ., from instruction decoder 302 ) that includes instruction address data and instruction text data . in block 404 , pre - processing parity data is generated ( e . g ., by parity generator 306 ) based on the instruction data . for example , one or more parity bits are generated . in block 406 , the pre - processing parity data is maintained . for example , the pre - processing data is stored in an 1 aq of an instruction queue pipeline ( e . g ., iaq 212 of queue pipeline 370 ). in block 408 , the instruction data is processed . for example , the instruction processing data flows through an instruction processing pipeline ( e . g ., processing pipeline 350 ) during which it is processed . in block 410 , post - processing parity data is generated ( e . g ., by parity generator 318 ) based on the instruction data processed via the instruction processing queue . in block 412 , the post processing parity data is compared to the pre - processing parity data . if the parity data matches , in block 414 , an error signal is transmitted that indicates that an error occurred related to the processing of the instruction data . additional variations of method 400 may be performed , e . g ., in accordance with the exemplary operation of processor pipeline subsystem 300 described above . elements of exemplary computer system 100 , exemplary processor pipeline staging 200 , and exemplary processor pipeline subsystem 300 are illustrated and described with respect to various components , modules , blocks , etc . for exemplary purposes . it should be understood that other variations , combinations , or integrations of such elements that provide the same features , functions , etc . are included within the scope of embodiments of the invention . the flow diagram described herein is just an example . there may be many variations to this diagram or the blocks ( or operations ) thereof without departing from the spirit of embodiments of the invention . for instance , the blocks may be performed in a differing order , or blocks may be added , deleted or modified . all of these variations are considered a part of the claimed invention . furthermore , although an exemplary execution of the flow diagram blocks is described with respect to elements of exemplary computer system 100 , exemplary processor pipeline staging 200 , and exemplary processor pipeline subsystem 300 , execution of the flow diagram blocks may be implemented with respect to other systems , subsystems , etc . that provide the same features , functions , etc . in accordance with exemplary embodiments of the invention . as described above , embodiments of the invention may be embodied in the form of computer - implemented processes and apparatuses for practicing those processes . embodiments of the invention may also be embodied in the form of computer program code containing instructions embodied in tangible media , such as floppy diskettes , cd - roms , hard drives , or any other computer - readable storage medium , wherein , when the computer program code is loaded into and executed by a computer , the computer becomes an apparatus for practicing the invention . the present invention can also be embodied in the form of computer program code , for example , whether stored in a storage medium , loaded into and / or executed by a computer , or transmitted over some transmission medium , such as over electrical wiring or cabling , through fiber optics , or via electromagnetic radiation , wherein , when the computer program code is loaded into and executed by a computer , the computer becomes an apparatus for practicing the invention . when implemented on a general - purpose microprocessor , the computer program code segments configure the microprocessor to create specific logic circuits . while the invention has been described with reference to exemplary embodiments , it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention . in addition , many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof . therefore , it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention , but that the invention will include all embodiments felling within the scope of the appended claims . moreover , the use of the terms first , second , etc . do not denote any order or importance , but rather the terms first , second , etc . are used to distinguish one element from another .