the image capture and transmission system of the subject invention is suited for capturing a single frame analog image signal and transmitting the captured signal via either a cellular or land line telephone system . the preferred embodiment is shown and described and is particularly well suited for use in combination with a standard motorola flip phone . the camera is not part of the system and the image captured by the camera is introduced into the system via standard cable , as will be described . turning now to fig1 a hand held cellular telephone 10 is shown with the image transmission system 12 mounted integrally therein . a standard motorola flipphone ® is shown . however , it will be readily understood by those who are skilled in the arts that the invention can be readily adapted to other telephone configurations . the cellular telephone includes a flip cover 14 , and led panel 15 , a keypad 16 and an antenna 18 , as is standard . the battery pack 20 is normally secured directly to the phone body 11 . in the preferred embodiment of the invention , the transmission system 12 is inserted between the battery pack 20 and the body 11 , as shown . the battery pack 20 provides the power for both the telephone and the transmission system . the standard connectors between the battery pack and the phone body are utilized to couple the transmission system 12 to the standard battery pack and the phone . the cable 22 and connector 24 are used to connect the system 12 and phone 10 . the connector 24 is connected to the phone via the standard phone hands free ( or data ) port 25 . the various control buttons , status readouts and ports for operating the transmission system 12 with the telephone 10 are located on the opposite side panels 26 ( fig1 ) and 28 ( fig2 ) of the transmission system housing . an exploded view of the assembly of the image facsimile transmission system 12 of the present invention is shown in fig3 . the housing 30 is an open topped box of standard construction , typically an unitary member of high impact plastic or similar material . the housing may be custom molded in the well known manner . seated in the housing 30 is the processor board 32 , containing the processor 34 and other circuitry , as more fully shown in block diagram form in fig4 . the modem board 36 is placed over the processor board 32 . the housing cover 38 fits over the entire assembly and sits on the top edges of the sidewalls of the box 30 to close the unit . the processor board 32 is seated directly on pads 40 provided in the box and held in place by standoff screws 42 . the modem board 36 is seated directly on the stand off posts 42 and the cover 38 is placed over the modem board 36 . the assembly is then secured in assembled relationship by screws 44 . a window 46 provides an opening in alignment with the power connectors on the telephone 10 , permitting the power interface 48 mounted on board 36 to communicate directly with the cellular telephone 10 . also mounted on the modem board 36 is a rj - 11 switch 50 for switching between pots and cellular or radio and an insulated mini - phono jack 52 for video input and remote trigger signals . the landline hook - up can be used whether or not the system is installed on the cellular telephone 10 . a latch 54 is installed in the latch recess 55 provided in the box 30 , and is spring loaded in the latched position by spring 56 . the latch 55 permits the entire assembly to be secured to the flip phone 10 in the same manner as the battery pack 20 would be secured in a non - modified phone configuration . the battery pack 20 is mounted on the outside of the bottom 58 of the box 30 , with the power connections being interfaced to the phone 10 via the interface window 60 in the box 30 , and interface circuitry 62 in the processor board 32 and 48 in the modem board 36 . the displays and control button switches are mounted in openings provided in the side walls of the box 30 , as better seen in fig1 and 2 . as shown in fig1 and 2 , a series of led readout lamps 64 a - d are provided on side 26 , 28 of the box 30 . the control switches or buttons 66 a - h are also located on the two sides of 26 , 28 of the box 30 . in the preferred embodiment , the lamp 64 a indicates a busy processor signal , the lamp 64 b indicates when the system is in a sending mode . button 66 d controls selection of the send mode . the lamps 64 c indicate image storage capacity level . the button switches 66 e and 66 f controls the abort mode and erase mode , respectively . the control buttons 66 a - c are on the opposite side panel 26 of the box 30 and include video input format switch 66 a , resolution select button 66 b an on / off button switch 66 c . high medium and low resolution indicator lamps 64 e are also on this side panel . switch 66 h is the data capture switch . the circuitry housed on the processor board 32 and the modem board 36 is shown in fig4 . the circuitry is partitioned into distinct functional areas , as follows : dc / dc convertor power supply 70 ; push button control switches 66 ; lamps 64 ; the video decoder circuit 72 ; video buffer 74 ; frame and video buffer controller 76 ; image and program store 78 ; data ram and program store 80 ; digital signal processor 82 ; rs - 232 level synchronous and asynchronous ports 84 ; modem 86 ; rj - 11 presence switch 50 ( see fig3 ); and the i / o decoder 88 . the system is a battery operated frame grabber , video compressor , image transmission device adapted for accepting ntsc , composite or s - video as an input . in the preferred embodiment , it has a harvard architecture dsp engine for compression and transmission . transmission is accomplished via several methods , the asynchronous rs - 232 port , the synchronous rs - 232 port a cellular phone compatible modem or a land line modem interface . the modem 86 is implemented on the daughter board 36 ( fig3 ). the daughter board interface ( not shown ) allows other optional functions to be designed in place of the modem in the well - known manner . the system memory is separated into two access areas : the program and data memory 80 , each of which is 64k words ; and the memory 78 accessed by a decode of the dsp address bus and the i / o instructions . a separate i / o address is implemented to allow contiguous memory blocks of greater than 64k words as is required for the large number of words in a frame of video . a programmable logic device ( pld ) 76 provides the registers , extended i / o address and additional “ glue logic ” required . the power supply 70 is adapted to receive between 5 . 5vdc and 8 . 2vdc which can be accepted as input to the dc / dc converter for providing output voltage of 5 . 0vdc . the video format selection is controlled by a combination of a single three conductor video input jack , and a slide switch 66 a ( fig1 ) to indicate either s - video / monochrome or composite . the video input jack is a mini - phono jack 52 , which will have the sleeve connected to ground . the tip contact is y ( luma ) and the ring contact is c ( chrominance ) if the input is s - video . for composite or monochrome video inputs , the tip contact is the video . the remote capture interface is a mini - phone jack 50 , which provides both capture functions and busy led feedback . the slide switch 66 a provides a status bit to be read by the software . this bit is assigned to a bit position 10 in the general status register . for example , in the composite position the switch 66 a is open and this is read as logic one in the register . the video decoder 72 may be adapted to accept both s - video or composite pal , ntsc or secam signals . the video is input through the mini - phono jack 52 and is detected and available to the processor 82 via the video status bits in the system status register . in the preferred embodiment the decoder 72 is a brooktree bt829 which automatically detects pal / secam and ntsc video standards . the format detected is available in the register set . the device features an extensive set of registers accessible via its i 2 c interface . these registers may be used to program the decoder to any of a variety of formats , as more fully described in the bt829 / bt827 videostream ii decoders manual , september , 1996 , incorporated by reference herein . the decoder may be programmed to produce either 640 × 480 ycrcb images from an ntsc source or 768 × 576 ycrcb images from a pal source . the decoder is powered on by a command from the processor 82 prior to capture of a frame and off by a command from the processor 82 upon completion of the capture of a frame . the decoder is isolated from the rest of the system by zero load buffers and isolation switches to allow power control . in the preferred embodiment , the decoder takes approximately 0 . 5 seconds to lock onto a valid video source . the decoder may be programmed 10 milliseconds after the decoder on command is initiated . the video decoder 72 is controlled by an i 2 c bus interface , which is implemented in the pld 76 and accessed by software using bit positions 0 and 1 , for sda and scl , respectively , in the i 2 c control register . a third bit , bit 2 , is available for changing between master and slave mode . the default position is slave . this is further described in the brooktree bt829 / bt827 data sheet , incorporated by reference herein . the video buffer 74 is a 16 bits wide by 512k deep buffer . the buffer holds one complete frame of ntsc square pixel imagery . the video buffer is written to by the video controller 76 which conditions the control signals provided by the video decoder 72 . the buffer 74 is read by the processor 82 via the controller 76 which also conditions the control signals provided by the processor during an i / o operation . the video buffer is mapped into the processor i / o space . an extended i / o address is generated in a pld . when the most significant bit extended i / o address 31 ( msb e1oad31 ) of the i / o address bus is 0 , the video buffer is selected . the frame detector , extended address and video controller circuitry 76 identifies the start of a frame and initiates the capture of that frame . image capture is initiated under software control by writing a logic 1 to bit position 6 ( snap ) of the power management and command register . the controller will issue a hold to the processor 82 , and upon receipt of the acknowledge ( holda ), takes control of the processor data bus . the controller waits for the odd field to start and then saves two consecutive fields in contiguous memory . as part of the capture sequence , this circuitry resets the extended address bus to all zeroes as the location of the first pixel data , auto increments the address and generates the write strobe for the video buffer 74 in response to the control inputs from the decoder 72 . upon completion of the frame , hold is released . the software is responsible for clearing the snap bit after released and before commanding another capture . the controller 76 also provides the control signals and extended i / o address bus for reading the image in response to i / o operations by the processor 82 . the extended i / o address bus operation is programmable by the processor . three registers control operation of this bus . the first two set the base address used as the starting address . since the address bus is 20 bits wide , two i / o locations are used to write the base address from the processor &# 39 ; s 16 bit data bus . the third register is the offset register . the offset is added to the base address after each read or write to generate the next address to be accessed . this permits convenient traversing either across a line of pixels or down a column of pixels . during boot by the processor 82 the extended address bus will initialize to ooooh and the increment by one after each read strobe of the processor . this requires that the module to be loaded be located at the bottom of the image / program store 78 . since the processor 82 uses only the least significant byte when booting , this section of code requires two memory locations for each word of executable code . each word of the program must be divided into two bytes and loaded upper byte lower byte in that order into successive memory locations . location 0000h must have the upper byte of the destination in program memory , and location 0001h must have the lower byte of the destination . the next two locations 0002h and 0003h must contain the upper byte and lower byte of the length in bytes to be loaded . this is more fully covered in the boot loader section of the tms320c2xx user &# 39 ; s guide , incorporated by reference herein . wait states for all memory accessed via the extended address bus will be controlled by the extended address bus controller . the image and program storage 80 is a 16 bit × 1 m flash file memory , providing lifetime up to 1 million erase cycles per block . addresses are generated by the controller pld 76 and the dsp 82 . the image and program storage is mapped into i / o space except at processor boot . at power up , the designated boot block will be mapped into program space and the boot program loaded from the program storage flash ram ( 78 ) into the program ram 80 . upon completion of the boot operation , the program storage will revert to i / o space . the image and program store is selected in extended i / o memory space by setting the msb eioad31 , of the extended address to 1 . two wait states will be required for access to this memory . the number of wait states is controlled by the extended address bus controller . in the preferred embodiment , an intel 28f016sv flash memory is used . programming is controlled by the register set on the flash chip and the busy signal it provides . the busy signal ry / by is inverted and connected to int 3 of the processor 82 . this flash part features a 128 word buffer to allow writing of a page of data at a time . complete details of this device are further described in the intel data sheet , july , 1995 and the specification update , july , 1996 , incorporated by reference herein . the data and program run ram 80 are each 64k words . the software will be responsible for controlling the software wait state register in the processor 82 for data and program ram access . the data signal processor ( dsp ) 82 of the preferred embodiment is a texas instruments tms320lc203 and has an advanced harvard architecture , software programmable wait states , a synchronous serial port , and an asynchronous serial port . on board ram , 544 words , is accessible as either data or program ram . a 20mhz oscillator will be used which results in single cycle instructions taking 50 ns . the processor monitors the control switches 66 , interprets the commands and performs the tasks commanded , which include : ( 1 ) powering up and down ; ( 2 ) loading the boot code ; ( 3 ) initiating video capture ; ( 4 ) video compression ; ( 5 ) image transmission over the modem a ) to wireless telephone ; b ) to landline ; ( 6 ) image transmission over the rs - 232 port ; ( 7 ) reprogramming the flash memory ; and ( 8 ) comsec interface over the rs - 232 port . more complete details of the processor 82 are included in the texas instruments data sheet and users guide , incorporated by reference herein . the on board cellular phone compatible modem 86 is set to interface to the cellular phone 10 through the cellular line interface drivers and receivers . the drivers and receivers provide any required level translation and connect to the cellular phone connector . an isolation circuit 87 is utilized before the cellular phone interface . this is accomplished by using an fet pack that is switched active and non - active by the rj11 selection circuit : ( 1 ) async with dtr data terminal ready ; and or ( 2 ) sync radio interface cable id / dtr ; or ( 3 ) branch telephonic daa , ( a ) rj - 11 switch or ( b ) cellular . the modem provides a host interrupt to the processor 82 , assigned to int 2 of the processor a . daa ( direct access arrangement ) circuit is provided for connection to the pots telephone line . the isolation circuit is adapted to power down the entire data capture and transmission module whenever a data input signal is not present , preserving battery power . the system powers up only when the user engages the capture sequence by depressing the capture switch and begins transmission . in the preferred embodiment , the power up sequence takes 0 . 5 second . fig5 is an exemplary schematic of one embodiment of the invention , incorporating the features shown and described in fig4 . the pin and wire numbers are shown in the drawing . viewing part a of the drawing from left to right , module 101 provides cellular phone power “ on ” “ off ”. the microcontroller unit 103 is the modem controller . module 104 is a crystal circuit for the modem 105 . amplifier 106 is a speaker amplifier . part b shows the modem ram 107 and the modem program storage memory 108 . part c is the cell phone interface section of the circuit . the amplifier 109 is the d . c . reference buffer . amplifier 110 is the modem rx signal amplifier and signal conditioner . amplifier 111 is the pots landline rx amplifier and signal conditioner . switches 112 are the cell phone isolation switches . the blocked area 113 provide cell phone emi filters . part d is the pots direct access arrangement , with signal level clamping circuitry 114 , with an isolation transformer at 115 . ac isolation is provided by the capacitor network 116 comprising capacitors c 26 and c 27 . the blocked area 117 is the pots line loading current control . the diode bridge 118 provides a polarity bridge . switch 48 at 119 provides “ off hook ” or open line switch and a ring detection circuit . a surge protector is provided at 121 , and an emi filter networks provided at 122 . part e is the power management circuitry . circuit 123 is the battery voltage sensor . the power switch is provided at 125 , with the power - up process status driver at 125 , the processor power on switch at 126 and the main power switching circuit at controller 129 . switch 130 is the video decoder power . part f is the processor 131 , with the oscillator at 132 . part g shows the program and data ram 133 and connectors 134 . part h shows the video buffer ram 135 and 136 . the program and image storage flash ram is shown at 137 . part i includes the video oscillator 138 and video input and conditioning circuitry 139 for managing input into the video decoder 140 . the video decoder isolation switches are shown at 141 ; the video address generator plp 1142 ; the videotiming and glue logic plp 143 ; the pld bootstrap logic 144 and the serial prom ( 1x256k ) boot program module 145 for pld 144 . part k includes the remote trigger jack 146 , the radio keying fet ( ptt ) 147 ; the radio digital mode keying transistor or digital data mode control ( ddmc ) 148 and the serial i / o drivers and receivers 149 . the data port is designated as 150 . part l is the led array 151 ; the composite / s - video switch 1152 and the push button array 153 . the preferred embodiment captures the high - resolution ( 640 × 480 ) full color images from any ntsc source like video cameras , monochrome image intensifiers , monochrome night visions devices ( such as flirs ) and the like . depending on application , medium and low resolution may also be selected based on user selection . the system can be operated locally or remotely through the host interface software . in the remote mode , the image can be captured , stored and / or transmitted by remote “ dial up ” using land line telephone or cellular systems , or other communications systsems such as radio or the like . in the preferred embodiment , the system firmware may be loaded and accessed for troubleshooting via remote access as well . the system of the present invention is specifically designed to operate over the public switched land line telephonic systems ( pots ) and cellular services . the invention is designed with a hardware port for digital radio operation , as well . the preferred embodiment of the invention is fully compatible with and integrates with a standard amp cellular phone such as by way of example , a motorola flip phone , and supports ntsc monochrome composite and s - video sources including video cameras , camcorders , vcrs , still image cameras , image intensifiers and flir - night vision devices . in the preferred embodiment , all of the circuitry for the system is on a card or slice which is inserted between the battery pack and the body of a standard motorola cellular phone . full isolation of the system circuitry is provided , permitting power preservation for cellular telephone use when data transmission is not activated . the present invention , permits a still frame visual image to be captured at a remote location and either stored locally or sent immediately , over land line or wireless communication systems , to a remote location such as , by way of example , a computer system wherein the image could be merged directly into newsprint . the image may also be printed as a hard copy using any windows based printer or group - iii facsimile machine , anywhere in the world . where desired , the images may be stored in memory for later recall , and may be archived on a portable medium such as a memory card or the like . in addition to multiple resolution capability , the system may be used with multiple compression algorithms such as jpeg , wavelet and other compression schemes . in the preferred embodiment of the invention , the controller is programmed to permit smart addressing of the video ram , allowing for row or column access to the image data , decimation and non - linear , sequential pixel access . other configurations are contemplated and are within the teachings of the invention . while specific embodiments have been shown and described herein , it will be understood that the invention includes all modifications and enhancements within the scope and spirit of the claims .