the present invention is believed to be applicable to a variety of different types of devices and processes , and has been found to be particularly suited for the management of memory access ( read and / or write ) with a memory array . while the present invention is not necessarily limited to such applications , various aspects of the invention may be appreciated through a discussion of examples using this context . fig4 illustrates a streaming memory system , according to an example embodiment of the present invention . the system includes an address buffer 52 , memory 54 , a read buffer 56 and a schedule / control circuit 58 , with applications of each described in further detail hereinafter . while memory 54 is shown implemented as a discrete semiconductor circuit chip , the streaming memory system is implemented on a single integrated chip and / or in a variety of fashions , depending upon the particular application . the address buffer 52 inputs addresses that will be used with the memory 54 to access certain particular memory cells during read or write operations . the address buffer 52 is implemented having storage capabilities that are large enough to handle a particular implementation ( and corresponding memory buffer requirements ). in this regard , the address buffer 52 is generally large enough to store addresses for a predetermined number of memory accesses that have been provided by a computer system 60 ( or other processing arrangement or system ). the address buffer 52 receives and queues a number of addresses , which are operated upon in an order that is relative to an efficiency characteristic of access to the memory 54 and may , for example , involve operating upon these addresses in an order different from that received by the address buffer 52 . the schedule / control unit 58 acts upon the addresses in the address buffer 52 as a function of characteristics of the memory 54 . for instance , where an address in the address buffer 52 corresponds to an active portion of the memory 54 , that address may be implemented with storing the data in the memory , in a manner independent from an order in which addresses are received in the address buffer 52 . this approach facilitates the efficient use of access to the memory 54 , with other addresses in the address buffer 52 being acted upon accordingly , relative to active portions of the memory 54 and / or the order in which the addresses are received . the read buffer 56 stores the data that is read out from the memory device 54 . this allows , therefore , the data that is read out to be stored and subsequently transmitted from the read buffer 56 to the computer system 60 in the same order as the order in which the addresses were received by the address buffer 52 from the computer system 60 , for those addresses corresponding to read operations . that is , the order in which addresses are acted upon ( e . g ., and data read to ) the memory 54 does not necessarily affect the order in which data is read out from the read buffer 56 . further , the order in which data is read out from the read buffer 56 can be correlated to the order in which addresses ( corresponding to the data ) are received at the address buffer 52 . the schedule / control circuit 58 controls the operation of re - ordering the addressing , as will now be further described in connection with a particular example application of the system shown in fig4 . it should be noted , however , that the operations that are conventionally required in order to access a memory device are not described in detail . in many applications , such conventional operations differ depending upon the type of memory device that exists , such as conventional dynamic random access memories , synchronous dynamic random access memories , or rambus ® dynamic random access memories , as well as other types of memories that are accessed as one or more banks of rows and columns . on initiation of a new cycle , a new address is input to the address buffer 52 . addresses in the address buffer 52 are compared with the address of the active row in the previous cycle is made ( e . g ., using a comparator in the schedule / control circuit 58 that compares the row address of each address with the row address of the currently active row ). if one of more of the addresses in the address buffer 52 correspond to an address associated with the active row from the previous cycle ( also termed currently active row ), the schedule / control circuit 58 initiates those control signals required to perform column addressing of the oldest ( i . e ., earliest received ) address in the address buffer 52 that corresponds to the active row using a priority encoder that selects the first address entered into the address buffer that is contained in the currently active row . that oldest corresponding address , therefore , is operated upon during that cycle and is input into memory 54 so that the memory cell associated with that address can be accessed . thus , the comparator ( and , e . g ., a priority encoder ), implemented using , e . g ., hardwired logic that make up the schedule / control circuit 58 , operate every cycle in parallel to select an access to be run . each cycle the logic scans the addresses in the address buffer 52 to find one ( if any ) that is to an active row and selects this address for a column access . if a simultaneous row access is also possible , the logic in the schedule / control circuit 58 also scans the addresses to find one for which a row access would be profitable , one for which there are no more addresses to the active row in its bank and ( optionally ) for which there are several other addresses in the same row queued . thus , for certain memory devices , while column addressing of an address is performed , the schedule / control circuit 58 can also initiate row addressing of a row in a bank other than the currently active row bank . for instance , if column addressing of an address associated with the active row is accessing data in bank 1 , the schedule / control circuit 58 may initiate row addressing for a row within bank 6 , since bank 6 does not currently contain an active row , such that in a subsequent cycle column addressing of that row can take place . with this approach , row access latency can be hidden under column accesses to other banks , thus improving efficiency of this system . once a row access is initiated , the schedule / control circuit 58 will also initiate subsequent control operations , depending on whether a read or a write operation was to take place . if a write operation takes place , the associated data is written into the addressed memory cell location . if a read operation takes place , the schedule / control circuit 58 causes the read out of data from the addressed memory cell location , and storage of that data into a read buffer 56 . the data is then read out of the read buffer 56 in the order that the read addresses were initially received into the address buffer 52 ( e . g ., as discussed above ). in one particular application , in a read operation , the read buffer 56 is indexed by a pair of pointers in a manner such as that used to reorder instructions in processors that allow out of order execution . as each read access is inserted into the address buffer 52 , the next sequential location in the read buffer 56 is identified by a read - tail pointer , reserved for this access , and marked pending . the value of the read - tail pointer is queued with the address in the address buffer 52 to record the location assigned and the read - tail pointer is incremented modulo the size of the read buffer 56 . when the queued read access is actually performed , the data read is inserted into the read buffer 56 location reserved for this access using the pointer queued with the address in the address buffer 52 and this location is marked full . in another implementation , a read - head pointer is used to remove data from the read buffer 56 . on reset the read - head and read - tail pointer both point to the same location and that location is marked empty . as read accesses arrive , the read - tail pointer is incremented by the schedule / control circuit 58 and locations are marked pending to allocate sequential read buffer 56 locations to these sequential accesses . finally , as read accesses are performed , some of these pending locations are filled . whenever the location identified by the read - head pointer is marked full , the value in that location is output , the location marked empty , and the read - head pointer incremented modulo the size of the read buffer 56 . because the read - data for the accesses is output in the same order that the read addresses arrived , ordering , read order is preserved even though memory accesses are performed out of order . the read buffer 56 in effect reorders the out of order memory accesses . on another embodiment , ordering is effected in connection with the completion of memory write operations out of order with operations that read or write other memory rows ( not to be of the same address ). the schedule / control circuit 58 always performs accesses in the same row in the original requested order , thus preserving the original order for two writes to the same location or a read and a write to a given location . the ordering of write operations and the relative ordering of reads and writes by always scanning for accesses to an active row are preserved in the order that accesses arrived . thus , an ‘ older ’ access to a given row , and hence a given location , will always occur before a later access to the same row , and hence same location . only accesses to distinct rows and hence distinct locations are reordered . thus , read before write or write before read hazards are not a problem with the schedule / control circuit 58 re - ordering . in another example embodiment of the present invention , the address buffer 52 and the read buffer 56 are partitioned so that addresses and data for each of separate banks are buffered separately . thus , the schedule / control circuit 58 can access the partitioned buffer associated with a currently active bank and perform an equality comparison on a those address bits necessary to determine if another address in the partitioned buffer corresponds to the currently active row in the currently active bank . the schedule / control circuit 58 then further determines whether to perform fast column addressing for a currently active bank using the other address , or instead initiate addressing of another bank in the manner previously described . with the latter approach involving addressing of another bank , row addressing of another bank is performed while the fast column addressing of the bank that previously had an associated active row is ongoing . the present invention also contemplates initiating access of multiple rows in different banks at the same time . while the present invention has been described with reference to several particular example embodiments , those skilled in the art will recognize that many changes may be made thereto without departing from the spirit and scope of the present invention .