in the following description , numerous details are set forth . it will be apparent , however , to one skilled in the art that embodiments of the invention may be practiced without these specific details . in other instances , well - known structures , devices , and techniques have not been shown in detail , in order to avoid obscuring the understanding of the description . the description is thus to be regarded as illustrative instead of limiting . reference in the specification to “ one embodiment ” or “ an embodiment ” means that a particular feature , structure , or characteristic described in connection with the embodiment is included in at least an embodiment of the invention . the appearances of the phrase “ in one embodiment ” in various places in the specification are not necessarily all referring to the same embodiment . [ 0016 ] fig2 illustrates an exemplarily cross - sectional view of a power grid 200 in accordance with an embodiment of the present invention . the power grid 200 includes a first power bus 202 and a second power bus 206 each having wires 203 a - e and 207 a - e , respectively . in an embodiment , the wires within each set of wires ( 203 a - e and 207 a - e ) may be separated with any type of dielectric . as illustrated , in accordance with one embodiment , the wires ( e . g ., 203 a - e and 207 a - e ) may be electrically coupled by , for example , utilizing connectors 205 and 209 ( shown throughout wires 203 a - e and 207 a - e , respectively ). in an embodiment , it is envisioned that these connectors ( e . g ., 205 and / or 209 ) may be an integral part of the wires ( e . g ., 203 a - e and / or 207 a - e ), instead of a separate structure . in one embodiment , the wires ( e . g ., 203 a - e and / or 207 a - e ) and / or connectors ( e . g ., 205 and / or 209 ) may be constructed utilizing the same material . in an embodiment , the wires ( e . g ., 203 a - e and / or 207 a - e ) and / or connectors ( e . g ., 205 and / or 209 ) may be constructed by using material selected from a group including copper , aluminum , silver , gold , other types of conductive substances , and / or any combination thereof . the first and second power buses ( 202 and 206 ) each have bumps 204 a - b and 208 a - b , respectively . the power grid 200 further includes a first ground bus 210 and a second ground bus 214 each having bumps 212 a - c and 216 a - c , respectively . in one embodiment , any pair of adjacent power and ground buses may be as close to each other as possible without causing a short . it is envisioned that the distance between adjacent power and ground buses may depend on the technology utilized to implement the circuitry . for example , the minimum distance between adjacent power and ground buses may be 30 microns in one technology and 10 in another . also , it is envisioned that by decreasing the distance between each power and ground bus pair the mutual inductance is increased , thereby decreasing overall inductance of a design . lowering inductance is envisioned to be greatly beneficial for certain applications , especially where higher frequencies ( currently , exceeding 2 ghz in some designs ) are utilized . in an embodiment , the lower inductance permits increased speeds for a design in addition to improving reliability . the formula ( 1 ) below illustrates the effects of reducing the mutual inductance more specifically . l total = l 1 + l 2 −( 2 * l mutal ) ( formula 1 ) in formula 1 , l 1 and l 2 are the inductances associated with circuits 1 and 2 , l mutual is the mutual inductance of circuits 1 and 2 , and l total is the total inductance for circuits 1 and 2 ). in an embodiment , the circuits 1 and 2 may be adjacent power and ground buses , respectively . it is also envisioned that the total inductance may be reduced by lowering the inductance of each circuit . for example , in an embodiment , the power and / or ground buses may be made wider in width and / or shorter in length . however , depending on the available floor space and / or associate costs , it may be more desirable to reduce the total inductance ( l total ) by increasing the mutual inductance ( l mutual ). accordingly , in an embodiment , it is desirable to decrease the gap between paired power and ground buses without causing a short and / or negatively affecting the signal carrying capabilities of the adjacent buses ( for example , through varying electrical fields associated with the adjacent buses and the like ). in such an embodiment , it is envisioned that the inductance of a power and ground grid is lowered without changing the resistance associated therewith . as illustrated in fig2 the bumps from different power buses may be substantially aligned ( for example , vertically ), in an embodiment . for example the bump 204 a of the first power bus 202 may be aligned with the bump 208 a of the second power bus 206 . similarly , in an embodiment , the bumps from the ground buses may be aligned . for example , the bump 212 b of the first ground bus 210 may be aligned with the bump 216 b of the second ground bus 214 . in an embodiment , the bumps of a power bus may be equidistance from bumps of an adjacent ground bus . for example , the distance from the bump 204 a to the bumps 212 a and 212 b may be substantially equal . similarly , in an embodiment , the bumps of a ground bus may be substantially equidistance from bumps of an adjacent power bus . for example , the distance from the bump 212 b to the bumps 204 a and 204 b may be substantially equal . [ 0021 ] fig3 illustrates an exemplarily cross - sectional view of an extended power grid 300 in accordance with an embodiment of the present invention . the power grid 300 includes a first power bus 202 having a bump 204 a and wires 203 a - e . the power grid 300 further includes a first ground bus 210 having a bump 212 a and wires 211 a - e . as illustrated , the bumps 204 a and 212 a may not be vertically aligned ( such as discussed with respect to fig2 ). in an embodiment , the wires within each set of wires ( 203 a - e and 211 a - e ) may be separated with any type of dielectric . as illustrated in fig3 in accordance with one embodiment , the wires ( e . g ., 203 a - e and 211 a - e ) may be electrically coupled by , for example , utilizing connectors 205 and 213 ( shown throughout wires 203 a - e and 211 a - e , respectively ). in another embodiment , it is envisioned that the wires 203 a - e and 211 a - e may each be a single wire ( e . g ., 203 and 211 ). it is also envisioned that process limitations may require a set of wires instead of a single wire . in a further embodiment , it is envisioned that these connectors ( e . g ., 205 and / or 213 ) may be an integral part of the wires ( e . g ., 203 a - e and / or 211 a - e ), instead of a separate structure . in one embodiment , the wires ( e . g ., 203 a - e and / or 211 a - e ) and / or connectors ( e . g ., 205 and / or 213 ) may be constructed utilizing the same material . in an embodiment , the wires ( e . g ., 203 a - e and / or 211 a - e ) and / or connectors ( e . g ., 205 and / or 213 ) may be constructed by using material selected from a group including copper , aluminum , silver , gold , other types of conductive substances , and / or any combination thereof . the power grid 300 additionally includes extended wires 302 a - b and 304 a - b . as illustrated in fig3 in accordance with one embodiment , the wires ( e . g ., 302 a - b and 203 a - e ) may be electrically coupled by , for example , utilizing connectors 303 ( shown throughout wires 302 a - b ). similarly , in accordance with one embodiment , the wires ( e . g ., 304 a - b and 211 a - e ) may be electrically coupled by , for example , utilizing connectors 305 ( shown throughout wires 304 a - b ). in an embodiment , it is envisioned that these connectors ( e . g ., 303 and / or 305 ) may be an integral part of the wires ( e . g ., 302 a - b and / or 304 a - b ), instead of a separate structure . in another embodiment , the wires ( e . g ., 302 a - b and / or 304 a - b ) and / or connectors ( e . g ., 303 and / or 305 ) may be constructed utilizing the same material . in yet another embodiment , the wires ( e . g ., 302 a - b and / or 304 a - b ) and / or connectors ( e . g ., 303 and / or 305 ) may be constructed by using material selected from a group including copper , aluminum , silver , gold , other types of conductive substances , and / or any combination thereof . it is envisioned that the set of wires 203 a - e of the first power bus 202 may be extended ( e . g ., utilizing the extended wires 302 a - b ) on an opposite side from the first ground bus 210 . and , the set of wires 211 a - e may be extended ( e . g ., utilizing the extended wires 304 a - b ) on an opposite side from the first power bus 202 . such extension of the wire sets 203 a - e and 211 a - e by , for example , the extended wires 302 a - b and 304 a - b , respectively , will not cause shorting in embodiments where the wire sets are brought as close to each other as possible , in part , to reduce the total inductance ( see , e . g ., the discussion with respect to fig2 ). the total inductance is reduced for one or both of the following two reasons : ( 1 ) the reduced self - inductance ( e . g ., by introducing wider conductance paths ), and / or ( 2 ) the increased mutual inductance ( see , e . g ., fig3 ). the effect is envisioned to provide a wider power and / or ground bus , depending on which bus ( es ) are widened by adding wires . also , in accordance with one embodiment of the present invention , it is envisioned that the mutual inductance between , for example , the extended wires 304 a - b and an adjoining power grid ( not shown ) may be increased , whereas the mutual inductance between the set of wires 211 a - e and the adjoining power grid may be reduced . accordingly , in an embodiment of the present invention , wire sets may be extended by adding one or more wires on an opposite side of the wire set from the neighboring power / ground bus . for example , with respect to fig2 if the second power bus 206 and the second ground bus 214 are considered as a pair of power and ground buses , then wire set 207 a - e may be extended by adding wires on the opposite side from the second ground bus 214 . similarly , wires 215 a - e may be extended by adding wires on the opposite side from the second power bus 206 . in one embodiment , the extension of the wire sets may result in reduction of resistance associated with the power and / or ground buses . the reduction in resistance may reduce the voltage variation due to dc , which is also known as the ir drop ( where i is for current and r is for resistance and the multiplication of the two result in voltage in accordance with the ohm &# 39 ; s law , i . e ., v = i * r ). an advantage of lrlips , in accordance with an embodiment of the present invention , is that the power and ground grid has the ability to be adjusted to any resistance value without changing the bump pattern . for example , a power and ground grid with very little resistance may be designed , but such a design may leave very little room to route global signals . therefore , lrlips , in accordance with an embodiment of the present invention , permits striking of a right balance of power and ground resistance and global signal tracking . in addition , in an embodiment , localized power and ground grids may be adjusted so as to tune a given ic to have the same ir drop in all transistors without changing the power and ground bumps . furthermore , reduction in inductance of a power grid reduces the voltage variations due to ac , which is also known as l *( di / dt ) ( where l stands for inductance and di / dt indicates the rate of change in current ( i ) over time ( t )). the di / dt is largely determined by the architecture , frequency , and power of an ic . the inductance , l , may be reduced with lrlips , in accordance with an embodiment of the present invention , since the power and ground grids are so close and tightly coupled together ( see , e . g ., the discussion with respect to fig2 ). it is envisioned that , in an embodiment , having a lower inductance power and ground grid will reduce voltage variations due to variations of current with respect to time . these current variations may be difficult to predict and estimate in cases where they are dependant on instruction and data patterns . thus , by reducing the inductance ( l ) of a given power and ground grid , certain embodiments of the present invention dampen the effects of large current variations , thereby reducing large voltage variations , which in turn improves reliability and circuit performance . it is envisioned that in an embodiment having a stable and predictable voltage at all transistors is paramount in achieving maximum performance and minimum power consumption . in addition , having a stable and predictable voltage at all transistor will increase reliability of an ic ( e . g ., if not enough guard band was allotted for voltage variation in the power budget estimates ). additionally , in an embodiment , the present invention provides the flexibility of removing individual power and ground bumps without increasing voltage drops or modifying the overall power and ground bump structure . this would be useful when an individual bump is , for example , over an alpha sensitive circuit . this is especially valuable because nearly all bumps may contain lead ( lead emits alpha particles ). in a further embodiment , a widened metal may be utilized to compensate for the voltage drop associated with removing a bump . in addition , lrlips , in accordance with one embodiment of the present invention , does not impact the yield or the manufacturability of the vlsi chip . according , lrlips , in accordance with an embodiment of the present invention , may allow an ic to perform faster , reduce the overall ic power consumption , and / or provide some combination of these performance and power benefits . moreover , an ic may perform faster by having the minimum voltage at the transistors that is higher , so the transistor would switch faster at the low voltage corner . in particular , the minimum voltage would be higher since the budget for ac and dc voltage drops will be lower ( i . e ., vtran = vsupply − vac_drop − vdc_drop , where vtran is the voltage at the transistor , vsupply is the supply voltage , vac_drop is the voltage associated with an ac drop , and vdc_drop is the voltage associated with a dc drop ). alternately , in an embodiment , the voltage at the transistor may be left the same ( e . g ., resulting in the same performance ) and the vsupply lowered to reduce the overall power consumption . accordingly , in one embodiment , the bump pattern may be diagonal to reduce cheesing of package power planes . thus , reducing resistance ( r ) and inductance ( l ) on , for example , a ceramic package . such an embodiment is envisioned to also reduce the overall voltage drops . the foregoing description has been directed to specific embodiments . it will be apparent to those with ordinary skill in the art that modifications may be made to the described embodiments , with the attainment of all or some of the advantages . for example , the embodiments of the present invention may be applied equally well to any device with a power and / or ground grid . therefore , it is the object of the appended claims to cover all such variations and modifications as come within the spirit and scope of the embodiments of the present invention .