in fig1 a functional block diagram of a basic processing module ( called the q - module ) utilized in the practice of the present invention , the q - module 10 is shown having a pair of shift registers 12 and 14 , each of length l . shift register 12 is designated the &# 34 ; source &# 34 ; shift register , and shift register 14 is designated the &# 34 ; reference &# 34 ; shift register . the shift register 12 has respective input and output terminals 16 , 18 , designated si and so . similarly the reference shift register 14 has respective input and output terminals 17 , 19 , designated ri and ro . the source shift register 12 is controlled by an input clock 20 and a recirculating clock 22 , while the reference shift register 14 is controlled in similar fashion by an input clock 24 and a recirculating clock 26 . the pulse rates of the recirculating clocks 22 , 26 are l times the rates of the input clocks 20 , 24 . a multiplier stage 30 is coupled to receive inputs from the shift registers 12 and 14 . one input 32 of the multiplier 30 is coupled to both the input 16 and output 18 of the source shift register 12 . the other input 34 of the multiplier 30 is coupled to both the input 17 and the output 19 of the reference shift register 14 . the multiplier 30 performs the dot product multiplications of signals applied to the inputs 32 , 34 which are accumulated in an accumulator stage 36 and supplied as the dot product s · r at output line 38 . signal squaring stages 40 and 42 are also connected respectively to the input 16 and output 18 of the source shift register 12 . the outputs of these signal squaring stages 40 , 42 are applied as plus and minus inputs to an accumulator 44 , the output of which constitutes the source magnitude ( ms ) signal on output line 46 of the q - module 10 . similarly , a pair of signal squaring stages 50 , 52 are connected respectively to input 17 and output 19 of the reference shift register 14 , and these squared signal outputs are supplied to the plus and minus inputs of an accumulator 54 to develop on output line 56 the reference magnitude ( mr ) signal . in the operation of the q - module of fig1 source and reference data signals , represented respectively as the functions [ i ( i , j )] and [ r ( i , j )], are applied to the respective shift registers 12 and 14 . these are processed in blocks of l samples . between successive blocks of input data samples , the l samples stored in each of the two shift registers 12 , 14 , are recirculated under control of the recirculating clocks 22 , 26 . after recirculating , the dot product of the two vectors stored in the shift registers 12 , 14 appears at the s · r output 38 . as data is loaded into the shift registers , a record is kept of the squares of the values entering the shift registers and the squares of the values leaving the shift registers . if the shift registers 12 , 14 are loaded with zeros on startup , the magnitudes of the vectors stored in the respective shift registers are available at the ms and mr outputs 46 , 56 at any given time . thus , at the end of a recirculation cycle , the magnitudes and dot product of the vectors contained in the respective shift registers are available on module output lines 46 , 56 and 38 . a plurality of q - modules 10 of fig1 ( numbers q1 - qk ) is interconnected with associated circuitry as indicated in fig2 . as shown in fig2 the first q - module q1 is connected in series with a delay stage d1 so that its so output ( line 18 of fig1 ) is coupled to the input of delay stage d1 . the time delay of a delay stage is chosen so that a q - module shift register and its following delay stage are effective to store one row of the image being compared . the output of the delay stage d1 is connected to the si input of the second q - module q2 ( line 16 of fig1 ), the so output of which is coupled to a second delay stage d2 . succeeding q - modules 10 and delay stages d are serially connected in similar fashion through the q - module q ( k - 1 ) and delay stage d ( k - 1 ) to the final q - module qk . the ms lines 46 of each of the k q - modules ( ms1 , ms2 . . . msk ) are applied to a first summation stage 60 . similarly , the mr outputs 56 of the k q - modules ( mr1 , mr2 . . . mrk ) are applied as inputs to a second summation stage 62 . a third summation stage 64 is connected to receive the s · r outputs of the q - modules ( sr1 , sr2 . . . srk ). the output of the first summation stage 60 , representing the function | v | 2 , and the output of the second summation stage 62 , representing the function | r | 2 , are applied to a multiplier 66 , the output of which is applied to a square root taking stage 68 which develops the function | v || r |. this is applied to a fourth summation stage 70 . the output of the dot product summation stage 64 is the dot product v · r which is applied to the summation stage 70 for combination with the output of the square root stage 68 to develop the output function g ( r , v ) on output line 72 . since the q - modules are constructed to operate continuously as data is applied in real time , the output line 72 of the circuit arrangement of fig2 carries the desired calculation of the function g ( r , v ) in real time . in the operation of the circuit of fig2 it will be understood that the reference r , a k × l matrix , has been loaded into the reference shift registers 15 of all k q - modules . immediately upon loading the reference r , there is available the function | r | 2 . the corrupted image , which contains the reference , is loaded serially into the source side of the q - module q1 . between samples of the source , g ( r , v ) is calculated for the vector v contained in the respective source registers 12 of the k q - modules . in this way , every k × l sub - image is compared with the stored reference . this correlation system provides the following significant advantages over other correlation schemes which are known . 2 . the system is not limited to one or two bit digitization . particular advantages of the system of the invention may be appreciated from a review of fig3 - 9 which represent the results of testing particular embodiments of the invention while varying certain control parameters and comparing the system of the invention with a system operating on the conventional mean absolute difference ( mad ) algorithm . in this simulation to demonstrate the effectiveness of the algorithm utilized in the inventive embodiment ( equation ( 4 ) above ), the function g was evaluated by using a particular 64 × 64 pixel image array . the test image was constructed in simulation of a terrain area . each pixel was represented by an 8 - bit binary number correspondind to levels between 255 ( white ) and 0 ( black ). the minimum pixel magnitude was 139 , the mean was 155 , and the maximum was 207 . a 16 × 16 pixel sub - array of this test image was designated as the reference , which in turn was correlated with a corrupted version of the original image to demonstrate performance . this is equivalent to setting the dimension p in equation ( 4 ) equal to 256 , or considering the 16 × 16 array as a vector of dimension 256 . the corrupted image array was computed in the following manner . if [ i ( i , j )] represents the original image array , then represents the corrupted image , where k represents a gain , m an offset , and n ( i , j ) random gaussian noise with zero mean and variance σ 2 . the signal to noise ratio ( snr ) with respect to the reference was computed using the values of g ( r , v ) were then computed for each v , where v is any 16 × 16 sub - array contained in [ t ( i , j )]. these values were then subtracted from 255 in order to make the minimum a maximum . the results are displayed in the three - dimensional plots of fig3 - 6 and 9 , scaled from 0 to 255 along the vertical axis . to verify the independence of g to changes in gain , gain ( k ) was set at 1 and at 0 . 1 , the other variables remaining at 0 . the correlation results are shown in fig3 and 4 , respectively , and indicate insignificant variation between the two conditions . to verify the independence of g to changes in offset , the values of g were computed for the case : k = 1 , m = 50 , σ = 0 . this result is displayed in fig5 and shows that the offset had little effect on the correlation peak when compared to the ideal case shown in fig3 . to assess the overall performance for combined offset and noise , the values of g were computed for the case k = 0 . 35 , m = 20 , σ = 6 . the snr for this condition is 0 . 775 . the result is depicted in fig6 which shows that , while the perturbations resulting from these severe signal interference conditions are significant , the correlation peak is still manifestly apparent . for comparison with correlation techniques utilizing the mean absolute difference ( mad ) algorithm , which uses the function s defined by ## equ5 ## s and g were compared for the case k = 1 , m - 0 , σ = 0 to establish base line performance . the result of the mad algorithm is shown in fig7 . comparison of fig7 with fig3 suggests that the mad algorithm might be a better choice for correlation , since the correlation peak is more prominent . to simulate a more realistic situation , however , noise was introduced and the gain was changed by 5 %. the results for the s function and the g function are shown respectively in fig8 and 9 . as is clearly evident in fig8 the correlation peak for s has virtually disappeared under these conditions while the peak for the g correlation function ( fig9 ) remains unchanged . further testing and comparison under simulated conditions were conducted for a number of other reference locations in the image array . in each case , where differences in gain and noise were introduced , the g function algorithm out - performed or matched the s function algorithm . a comparison was also made of the g function against the function f ( c , d ) defined above in equation ( 1 ). the results for the two functions were virtually identical ; this was expected , since the g function was derived from f . the form of the g function utilized in the invention was chosen for simplicity of hardware implementation . as has been demonstrated , the g correlation function implemented in the system represented in fig2 operates effectively to develop correlation results which are superior to those of alternative algorithms , particularly where the effects of noise and gain variations are considered . at present , commercial multipliers are available which can be operated at a 17 megahertz rate . thus a q - module ( fig1 ) with an 8 bit long shift register ( l = 8 ) can be operated at a 2 megahertz data rate . using 128 of the q - modules ( 4 in each row ), it is possible to locate a 32 × 32 pixel reference contained in a 256 × 256 pixel array within 1 / 30 seconds . using vsli techniques , it should be possible to develop a q - module capable of handling an 8 bit input in a single package . although there have been described above specific arrangements of a real time two - dimensional digital correlator in accordance with the invention for the purpose of illustrating the manner in which the invention may be used to advantage , it will be appreciated that the invention is not limited thereto . accordingly , any and all modifications , variations or equivalent arrangements which may occur to those skilled in the art should be considered to be within the scope of the invention as defined in the annexed claims .