please refer to fig1 , which is a function block diagram of a chip 10 and a circuit board 12 , both of which are installed in a micro - controller system , according to the present invention . the circuit board 12 , for example , is a motherboard and the chip 10 is a chip installed on the motherboard . the circuit board 12 can also be a printed circuit board with an add - on card installed and the chip 10 is for controlling the add - on card . the chip 10 comprises an i / o circuit 16 and a core circuit 14 for data calculation and information manipulation . the i / o circuit 16 buffers and transforms both data manipulated by the core circuit 14 and data ready to be transmitted to the circuit board 12 and raw data ready to be transmitted to the core circuit through the circuit board 12 . as described previously , the core circuit 14 is biased by a low - leveled voltage and generates low - leveled data and signals of low levels , which are to be pumped by the i / o circuit 16 and then to be transmitted to the circuit board 12 . on the contrary , the i / o circuit 16 reduces the voltage of both raw data and signals ready to be transmitted from the circuit board 12 to the core circuit . since the i / o circuit 16 is designed to exchange data with the circuit board 12 and vice versa , bias voltages to bias the i / o circuit 16 and the circuit board 12 are of equal levels . the circuit board 12 and the i / o circuit 16 of the chip 10 are biased by two distinct direct voltages vcc and vss ( can be referred as ground ) respectively . since the core circuit 14 needs a low - leveled voltage as a bias voltage , the chip 10 has to combine with the circuit board 12 to form a regulator 18 to generate a regulated voltage vp 25 to bias the core circuit 14 . typically , the circuit board 12 provides the chip 10 with a direct voltage of 3 . 3 volts , while the bias voltage to bias the core circuit 14 is of 2 . 5 volts . for such a configuration , the regulator 18 generates the regulated voltage vp 25 , capable of providing power for the core circuit 14 to operate , with the direct voltage vcc of 3 . 3 volts . in the regulator 18 , a bipolar junction transistor qp 1 , which is installed on the circuit board 12 , functions as a charging circuit to provide currents . a capacitor cp 1 functions as a power module 24 . in accordance with the transistor qp 1 and the power module 24 , the chip 10 comprises an operational amplifier 20 , a bandgap circuit 22 for generating a bandgap voltage vbg 0 , and two voltage - dividing resistors rp 0 and rp 1 . a bias voltage , whose level is between the direct voltages vcc and vss , biases the regulator 18 . the operational amplifier 20 has two differential input ends , labeled by “+” and “−” and connected to node np 1 and to a bandgap voltage output end of the bandgap circuit 22 respectively . an output end op 0 of the operational amplifier 20 is electrically connected to a base of the transistor qp 1 for biasing the base of the transistor qp 1 with a driving voltage as a driving signal . in operation , the chip 10 can connect the output end op 0 to the transistor qp 1 of the circuit board 12 with a pin . the direct voltage vcc biases an emitter of the transistor qp 1 . a collector of the transistor qp 1 is electrically connected to the power module 24 at node np 0 . the power module 24 comprises a capacitor of high capacitance for voltage regulation and bypassing the interference of alternative fluctuation as well . the capacitor can be charged to a stable state and generates the regulated voltage vp 25 at node np 0 . the regulated voltage vp 25 of the power module 24 at node np 0 can be transmitted back to the chip 10 through another corresponding pin . the regulated voltage vp 25 not only provides the core circuit 14 with the biased voltage , it also generates a divided voltage vs 0 at node np 1 through the use of the resistors rp 0 and rp 1 . after comparing the bandgap voltage vbg 0 with the direct voltage vs 0 , the operational amplifier 20 generates a driving voltage vd 0 to control the transistor qp 1 . operations of the regulator 18 are described as follows : when the circuit board 12 enables the chip 10 to start to function , the circuit board 12 provides the regulator 18 with the direct voltage vcc to enable the regulator 18 to function . in the meantime , the operational amplifier 20 also starts to compare a voltage vs 0 at node np 1 with the bandgap voltage vbg 0 generated by the bandgap circuit 22 . since node np 0 and the voltage vs 0 both are kept at low level before the regulator 18 functions , as the operational amplifier 20 starts to function , the operational amplifier 20 outputs the driving voltage vd 0 of a low level at the output end op 0 due to a comparison result that the voltage vs 0 is far smaller than the bandgap voltage vbg 0 . in the mean time , a voltage across the emitter and base of the transistor qp 1 is almost equal to a voltage difference between the direct voltages vcc and vss , enabling the transistor qp 1 to generate a high - leveled current ic 0 as a charging current to charge the high - capacitanced capacitors cp 1 of the power module 24 . as the charging process keeps functioning , the voltages at node np 0 as well as at node np 1 are increasing and the operational amplifier 20 keeps increasing the driving voltage vd 0 at the output end op 0 . the degree to which the driving voltage vd 0 is increased corresponds to the degree to which a voltage across the emitter and base of the transistor qp 1 is decreased , enabling the transistor qp 1 to conduct lesser currents . the operational amplifier 20 is capable of controlling the driving voltage vd 0 by detecting the voltage vs 0 and stabling the voltage vp 25 at node np 0 . after reaching to the stable state , the operational amplifier 20 keeps the voltage vs 0 to be equal to the bandgap voltage vbg 0 . that is , the voltage vp 25 is equal to ( 1 + rp 0 / rp 1 ) vbg 0 . such the stable voltage vp 25 can function as the direct biased voltage for the core circuit 14 . the current for the core circuit 14 to operate is therefore supplied by the transistor qp 1 . occasionally , when the voltage vp 25 is changed , the operational amplifier 20 accordingly controls the driving voltage vd 0 to be dynamically compensated . for example , if the core circuit 14 needs more current due to an increment of calculation , the capacitor cp 2 is capable of preventing the voltage vp 25 at node np 0 from dropping abruptly . the voltage vp 25 of a slightly reduced level enables the voltage vs 0 to drop accordingly and a voltage across the emitter and base of the transistor qp 1 to rise , thus increasing currents ic 0 flowing through the transistor qp 1 to meet the demand of increasing currents for the core circuit 14 . however , although the regulator 18 shown in fig1 can generate the stable voltage vp 25 to bias the core circuit 14 , the regulator 18 has a problem that the regulator 18 actuates too great currents to flow through the transistor qp 1 in the beginning , the too great currents probably burning the transistor qp 1 . as described previously , when the regulator 18 starts to operate , voltage at node np 0 has a low level and the driving voltage vd 0 output by the operational amplifier 20 at the output end op 0 also has a low level . therefore , a voltage across the emitter and base of the transistor q 1 is almost equal to a voltage difference , 3 . 3 volts for example , between the direct voltages vcc and vss . however , the level of the voltage across the emitter and base of the transistor q 1 for the transistor q 1 to actuate a significant current is generally equal to 0 . 7 to 0 . 8 volts . theefore , the current actuated by the regulator in the beginning of operation is in fact greater than a current for the transistor qp 1 to operate normally dramatically . such a high - leveled current probably burns the transistor qp 1 while the regulator 18 is in the beginning of operation . accordingly , the present invention also presents an amended regulator . please refer to fig2 , which is a function block diagram of a regulator 38 fabricated between a chip 30 and a circuit board 32 according to the present invention . in accordance with allocation of modern microprocessor , the chip 30 also comprises a core circuit 34 and an i / o circuit 36 , the core circuit 34 operating at the voltage v 25 of a lower level , and the i / o circuit 36 as well as the circuit board 32 biased by the direct voltage vcc of a higher level . the direct bias vss can be ground of zero volts . in order to generate the regulated voltage v 25 for the core circuit 34 , a regulator 38 is fabricated between the chip 30 and the circuit board 32 for generating the regulated voltage v 25 according to the direct bias vcc provided by the circuit board 32 . the regulator 38 is biased by a voltage between the direct bias vcc and vss . the regulator 38 comprises a bandgap voltage generator 42 fabricated in the chip 30 for generating a bandgap voltage vbg , an operational amplifier 40 , a control circuit 48 , a mos transistor q 3 functioning as a charge circuit , and two voltage - dividing resistors r 0 and r 1 . in accordance with the above circuit , the circuit board 32 also comprises a bjt q 1 and a power module 46 for providing currents and appropriate reduced voltage . the operational amplifier 40 comprises a positive input end inp electrically connected to node n 1 , a negative input end inn for receiving the bandgap voltage vbg , and an output end op . in operation , the operational amplifier 40 generates a corresponding driving voltage vd as a driving signal at the output end op by referring by referring a voltage difference between the positive and negative input ends inp and inn . the driving voltage vd is for controlling a base of the transistor q 1 . in practice , the chip 30 can comprises a pin to electrically connect the output end op to the base of the transistor q 1 , whose emitter is biased by the direct voltage vcc and a collector is electrically connected to node n 0 . based on the control of the driving voltage vd , the transistor q 1 is capable of providing a charging current ic to flow to node n 0 . the power module 46 comprises a capacitor c 1 of high capacitance for voltage regulation and bypassing unnecessary interference , enabling a voltage at node n 0 to be stable . with the power module 46 as a load , the regulator 38 is capable of generating the regulated voltage v 25 at node n 0 . the regulated voltage v 25 at node n 0 can be transmitted back to the core circuit 34 for biasing the core circuit 34 by connecting node n 0 through another pin in the chip 30 to a node n 3 of the chip 30 . the resistors r 0 and r 1 are capable of generating a dividing voltage vs , equal to ( r 1 /( r 0 + r 1 )) v 25 , at node n 1 and transmitting the dividing voltage vs to the positive input end inp of the operational amplifier 40 . in the present invention , the control circuit 48 generates voltage signals vpc , vop and vopb as control signals . the transistor q 3 , as a pre - charging circuit , comprises a drain biased by the direct voltage vcc , a body biased by the direct voltage vss , a gate controlled by the voltage vpc , and a source electrically connected to node n 3 . with the above connection , the transistor q 3 is capable of generating a pre - charging current to flow to node n 3 based on the control of the control circuit 48 . the operational amplifier 40 , controlled by the voltage vop as well as vopb , selectably either disables the operational amplifier 40 to stop functioning or enables the operational amplifier 40 to start to function . in the preferred embodiment of the present invention , when the operational amplifier 40 is disabled , the operational amplifier 40 continuously outputs a high - leveled voltage ( that is the direct voltage vcc ) at the output end op to turn off the transistor q 1 . when the operational amplifier 40 is enabled , the operational amplifier 40 generates the corresponding driving voltage vd at the output end op by referring a voltage difference between the positive and negative input ends inp and inn . in accordance with the above allocation , the regulator 38 functions as following descriptions . in the beginning , the circuit board 32 provides the chip 30 and the regulator 38 with the direct voltage vcc . in the meantime , the control circuit 48 disables the operational amplifier 40 with the voltages vop and vopb . as described previously , the disabled operational amplifier 40 outputs the driving voltage of a high level at the output end op and disables the transistor q 1 to actuate currents because of a voltage of substantial zero volts between the emitter and base of the transistor q 1 . while the operational amplifier 40 is disabling , the control circuit 48 controls the transistor q 3 with the voltage vpc of a high level to provide the pre - charging charge ipc to flow through nodes n 3 and n 0 and charge the power module 46 . in other words , at this moment the pre - charge current ipc for charging the power module 46 is not generated by the transistor q 1 , but by the transistor q 3 instead . as the transistor q 3 keeps charging the power module 46 , the regulated voltage v 25 at node n 0 rises from a voltage of a low - level ( equal to the level of the direct voltage vss ), and the control circuit 48 keeps estimating how high the regulated voltage v 25 has risen until the control circuit 48 estimates that the regulated voltage v 25 has risen to a voltage equal to a predetermined voltage . in the preferred embodiment of the present invention , the predetermined voltage is a voltage whose level is slightly lower than that of the regulated voltage v 25 . as soon as the control circuit 48 has estimated that the regulated voltage v 25 has risen to the predetermined voltage , the control circuit 48 changes levels of the voltage signals vop , vopb and vpc , enables the operational amplifier 40 , and turns off the transistor q 3 not to provide the pre - charging current ipc . after starting to function , the operational amplifier 40 generates the corresponding driving voltage vd by referring a voltage difference between the voltage vs and the bandgap voltage vbg and controls the transistor q 1 to actuate the charging current ic to charge the power module 46 . eventually , the operational amplifier 40 keeps the regulated voltage v 25 to have a stable level equal to ( 1 + r 0 / r 1 ) vbg . from the above descriptions , when the regulator 38 begins to function and the regulated voltage v 25 is equal to zero volts , the regulator 38 disables the feedback control between the operational amplifier 40 and the transistor q 1 , preventing the operational amplifier 40 from excessively driving the transistor q 1 because of too high a voltage difference between the voltage vs and the bandgap voltage vbg . when disabling the operational amplifier 40 , the regulator 38 provides the pre - charging current ipc with the transistor q 3 , served as a pre - charging circuit , to flow to the power module 46 and to charge the capacitors c 1 and c 2 , raising the regulated voltage v 25 at node n 0 . as soon as the regulated voltage v 25 is raised to the predetermined voltage , the control circuit 48 controls the transistor q 3 with the signal vpc not to actuate and to stop providing the pre - charging current ipc . the control circuit 48 , in the meantime , enables the operational amplifier 40 with the signals vop and vopb , enabling the feedback control between the operational amplifier 40 and the transistor q 1 and stabilizing the regulated voltage v 25 . that is , while the operational amplifier 40 is functioning , the regulated voltage v 25 is not a low - leveled voltage any more and the voltage vs is becoming closer and closer to the bandgap voltage vgp , enabling the operational amplifier 40 to output the driving voltage vd of a level higher than that of the low - leveled voltage . therefore , as the driving voltage vd actuates the transistor q 1 , a problem of too low a voltage between the emitter and base can be approved and the transistor q 1 will not be exceedingly driven to actuate too great a current . fig3 is a circuit diagram of a practical embodiment of the operational amplifier 40 according to the present invention . fig4 is a circuit of a practical embodiment of the control circuit 48 according to the present invention . as shown in fig3 , the operational amplifier 40 is biased by voltages ranging between the direct voltages vcc and vss and is composed of nmos transistors t 1 , t 2 , t 5 to t 8 , t 12 and t 14 and pmos transistors t 3 , t 4 , t 9 to t 11 and t 13 . nmos transistors s 1 to s 3 and s 7 and pmos transistors s 4 and s 5 are functioned as switch transistors for the need to enabling or disabling the operational amplifier 40 . each of the nmos transistors comprises a body biased by the direct voltage vss . each of the pmos transistors also comprises a body biased by the direct voltage vcc . the transistors t 1 and t 2 form a differential pair . the transistors t 1 and t 2 comprise respective gates , serving as the positive and negative input ends of the operational amplifier 40 . the transistor t 5 , connected to the differential pair at node n 5 and serving as a current source for bias , comprises a gate electrically connected to gates of the transistors t 6 , t 7 and t 14 to form a current mirror . a support circuit 50 , capable of generating a current ir to serve as a reference current , adjusts a level of a bias voltage at node t 5 through the use of the current mirror . the transistors t 3 and t 4 function as active loads of the differential pair . the transistors t 3 and t 4 comprise respective gates connected to gates of the transistors t 9 and t 11 and form another current mirror . in summary , the transistors t 1 and t 5 form a differential input stage of the operational amplifier 40 . signals amplified by the differential input stage are further amplified by a second stage , including the transistors t 6 to t 11 , of the operational amplifier 40 . the operational amplifier 40 has the transistors t 12 and t 13 as a class ab output stage and node n 8 as the output end op . in contrast to the transistors t 1 to t 14 , which form a basic structure of the operational amplifier 40 , the switch transistors s 1 to s 7 control biases applied to the gates of the transistors t 1 to t 14 and enables or disables the operational amplifier 40 . the transistors s 1 , s 2 and s 7 have gates controlled by the signal vop generated by the control circuit 48 , please further refer to fig2 , while the transistors s 3 to s 5 have gates controlled by the signal vopb . operations for the operational amplifier 40 to disable or enable by referring by referring the signals vop and vopb are described as follows : when disabling the operational amplifier 40 , the control circuit sets the signals vop and vopb to have a high and low level respectively , conducting the switch transistors s 1 to s 7 . conducted transistors s 1 and s 3 reduce a voltage at node n 6 to a voltage equal to the direct voltage vss , turning off the transistors t 5 to t 7 and t 14 and enabling the current ir generated by the support circuit 50 to flow into the conducted transistor q 3 instead of the transistor q 14 . likewise , conducted transistors s 2 and s 7 pull voltages at the gates of the transistors tb and t 12 down to a voltage equal to the direct voltage vss and turn off the transistors t 8 and t 12 accordingly . the transistor t 10 is actuated . conducted transistors s 4 and s 5 pull voltages at the gates of the transistors t 3 , t 4 , t 9 and t 11 up to a voltage equal to the direct voltage vcc and turn off these four transistors . the actuated transistor t 10 combined with the turned off transistor t 11 are capable of pulling a voltage at the gate of the transistor t 13 down to a voltage of a low level , turning on the transistor t 13 , and pulling a voltage ( the driving voltage shown in fi . 2 ) at the output end op up to a voltage equal to the direct voltage vcc . when the regulator 38 just starts operating , the operational amplifier 40 is disabled and the high - leveled driving voltage vd at the output end makes a voltage difference between the emitter and the base of the transistor q 1 neglected and turns off the transistor q 1 . in contrast , when enabling the operational amplifier 40 , the control circuit 48 pulls the voltage vop up to a voltage of a high level and the voltage vopb down to a voltage of a low level . the transistors s 1 to s 7 are then turned off from affecting biases applied to the gates of the transistors t 1 to t 14 , the transistors t 1 to t 14 then capable of executing normal functions that the operational amplifier 40 has , generating the corresponding driving voltage vd at the output end op by referring by referring a voltage difference between the positive and negative input ends inp and inn . as shown in fig4 , the control circuit 48 of the present invention comprises nmos transistors m 1 to m 3 , m 5 , m 6 , m 9 to m 11 , pmos transistors m 4 , m 7 and m 8 , and an inverter 52 and a nor gate 54 , both of which are biased by voltages ranging between the direct voltage vcc and vss . each of the pmos transistors has a body biased by the direct voltage vcc , while each of the nmos has a body biased by the direct voltage vss . the transistors m 1 to m 3 have respective gates all electrically connected to the direct voltage vcc for forming an internal pre - charging circuit 56 , which is electrically connected to a gate of the transistor m 6 at node n 9 . the transistor m 6 further comprises a drain and a source , both of which are biased by the direct voltage vss and form a capacitor as a second power module . the internal pre - charging circuit 56 is capable of charging the capacitor formed by the transistor m 6 and generating a voltage v 2 at node n 9 . the transistors m 7 , m 9 and m 10 are connected to form a circuit of an inverter , receiving the voltage v 2 as an input voltage with the gate and outputting the voltage vpc for the control circuit 48 to control the transistor q 3 at node 10 , please further refer to fig5 . through the use of the nor gate 54 and the inverter 52 , the control circuit 48 is capable of generating another two control signals vop and vopb with the voltage vpc to enable or disable the operational amplifier 40 . please refer to fig5 , which is a timing diagram of voltages at corresponding nodes of the regulator 38 in operation according to the present invention , an abscissa representing time and an ordinate representing levels of the voltages . in fig5 , solid lines from top to bottom represent the regulated voltage v 25 , a voltage vreg , the voltage v 2 in the control circuit 48 , as shown in fig4 , and the signals vpc , vop and vopb for the control circuit 48 to control the transistor q 3 and the operational amplifier 40 . in following paragraph fig5 will be used to illustrate operations of the control circuit 48 and the regulator 38 as well . as shown in fig5 , it is assumed that the circuit board 32 enables the chip 30 to start to operate at time t0 . as described previously , at this moment the circuit board 32 begins to provide the regulator 38 with the direct voltage vcc . at time t0 the voltage vreg of a low level enables the transistors m 4 and mb ( referring to fig4 ) to be turned on and the transistors m 5 and m 11 to be turned off . in the meantime , the internal pre - charging circuit 56 begins to actuate a current ipc 2 as a second pre - charging current to flow to the gate of the transistor q 6 through node n 9 due to the bias the direct voltage vcc , like charging the capacitor formed by the transistor q 6 and raising the voltage v 2 at node n 9 for a voltage of a low level . however , a voltage at node n 9 at time t0 is still a low - leveled voltage , which turns on the transistor m 7 and turns off the transistors m 9 and m 10 , pulling the voltage vpc at node n 10 as well as the voltage vop up to voltages of high levels . the inverter 52 of the control circuit 48 pulls the signal vopb down to a voltage of a low level . as described previously , the high - leveled voltage vpx turns on the transistor q 3 and enables the transistor q 3 to actuate the pre - charging current ipc to charge the power module 46 and to raise the voltage v 25 . in the meantime , the signal vop has a high level and the signal vopb has a low level , enabling the operational amplifier 40 to be disabled and to output the driving voltage vd of a high level at the output end op to turn off the transistor q 1 ( referring to fig2 , fig3 , and corresponding descriptions ). as shown in fig5 , as the internal pre - charging circuit 56 charges the transistor m 6 at time t0 , the voltage v 2 at node n 9 starts to rise from a voltage of a low level and eventually reaches to a voltage great enough to turn off the transistor m 7 and to turn on the transistors m 9 and m 10 , thus reducing the high - leveled voltage vpc at time t0 to the voltage vpc of a low level at time t1 , reducing the high - leveled voltage vop to the voltage vop of a low level , and raising the low - leveled voltage vopb at time t1 to the voltage vopb of a high level . moreover , from the time t0 to t1 , not only does the internal pre - charging circuit 56 of the control circuit 48 charge the capacitor formed by the transistor q 6 , the transistor q 3 , as a pre - charging circuit , of the regulator 38 also charges the capacitors c 1 and c 2 of the power module 46 , raising the regulated voltage v 25 at node n 0 from the time to on . up to time t1 , the regulated voltage v 25 has been raised to a voltage of a level equal to a voltage level v 25 m . since the voltages vpc , vop and vopb at time t1 have changed , the transistor q 3 is then turned off and stops actuating the pre - charging current ipc . the operational amplifier 40 begins to operate after time t1 and adjusts the driving voltage vd to drive the transistor q 1 to charge the power module 46 , raising the driving voltage vd after time t1 until that the driving voltage vd is stable . the stable driving voltage vs is equal to ( 1 + r 0 / r 1 ) vbg . for example , the stable driving voltage vs is 2 . 5 volts . the stable driving voltage vs can then used for the operations of the core circuit 34 . it is apparent from the previous descriptions that when the operational amplifier 40 and the transistor q 1 begin to operate , the regulated voltage v 25 is generated by the transistor q 3 in the pre - charging circuit from time t0 to t1 , from a voltage of a low level at time t0 to a voltage equal to the voltage v 25 m at time t1 . the operational amplifier 40 drives the transistor q 1 at time t1 with the regulated voltage v 25 instead of the driving voltage vd of a low level and prevents the transistor q 1 from burning out due to too great a current . additionally , it can be seen in fig5 that the sooner the voltage vc 2 of the control circuit 48 is changed , the earlier the operational amplifier 40 as well as the transistor q 1 begin to operate . for example , if the voltage vc 2 changes in accordance with a dotted curve vc 2 p , at time tp the voltage vc 2 rises to a voltage to enable the voltages vpc and vop to be reduced and the voltage vopb to be increased . therefore , as the regulated voltage v 25 is raised to be equal the stable regulated voltage v 25 mp , the regulated voltage v 25 is then made stable by the operational amplifier 40 and the transistor q 1 . in other words , in order to control the transistors q 3 and q 1 capable of operating sequentially when the regulated voltage v 25 is raised to be equal to a predetermined voltage , the internal pre - charging circuit 56 of the control circuit 48 can be controlled to adjust the speed to charge the transistor m 6 , the transistor q 3 charging the power module 46 to a voltage equal to the predetermined voltage when the voltage vc 2 is raised to a voltage whose level is high enough to trigger the voltages vpc , vop and vopb to change . moreover , the transistor m 6 and currents actuated by the internal pre - charging circuit 56 can be adjusted to adjust the speed for the internal charging circuit 56 to charge the transistor m 6 . for example , if the current ipc 2 actuated by the pre - charging circuit 56 is equal to one - tenth of the pre - charging current ipc flowing through the transistor q 3 , and the equivalent capacitance of the transistor m 6 is also equal to one - tenth of the equivalent capacitance of the power module 46 , the voltage vpc 2 will rise as fast as the regulated voltage v 25 when the transistor q 3 is in operation . therefore , the rising speed for the voltage vpc 2 can be used to estimate the rising speed for the voltage v 25 and the timing for the transistors q 3 and q 1 to operate sequentially . in contrast to the prior art , the present invention can provide a regulator capable of providing a stable and concise regulated voltage in a feedback control manner . in the prototype regulator , since the operational amplifier controls the bjt transistor qp 1 to operate according to a low - leveled regulated voltage in the beginning and drives the transistor qp 1 exceedingly , the transistor qp 1 is easily burned - out , disabling the regulator to generate the regulated voltage and preventing the core circuit of the chip from getting the bias voltage and operating . in the present invention , the transistor q 3 functions as a pre - charging circuit and raises the regulated voltage to a voltage equal to a predetermined voltage prior to the operations of the operational amplifier and the bjt transistor q 1 , preventing the transistor q 1 from burning out due to too great driving currents to drive the transistor q 1 after the operational amplifier starts to function , allowing the regulator to function normally thereafter , and ensuring that the core circuit can obtain the concise and stable bias voltage . following the detailed description of the present invention above , those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention . accordingly , the above disclosure should be construed as limited only by the metes and bounds of the appended claims .