the invention will now be described with reference to the accompanying figures . in the figures , various aspects of the structures have been shown and schematically represented in a simplified manner to more clearly describe and illustrate the invention . by way of overview and explanation , the present invention comprises a software program that calculates yield for a sampling region on a semiconductor wafer and based upon the calculated yield predicts yield of the semiconductor wafer and / or adjusts the boundary of at least one sampling region such that the adjusted sampling region predicts a higher or lower yield for the semiconductor wafer . some sampling regions comprise shapes such as , but not limited to , quadrants , pie slices and rings , which can be symmetrical or asymmetrical . the software program iteratively chooses sampling region boundaries based upon a nearest neighbor approach such that the finally selected sampling region boundary encapsulates the maximum number of good die . finally , the software program identifies bad sampling regions , i . e . the outer periphery of the semiconductor wafer that often contains partial die , from the beginning and automatically excludes such from wafer test runs . in - line testable structures test the die in predetermined quantities and locations on the semiconductor wafer . often the in - line testable structure test not each die , but instead a representative sampling of die . in accordance with the present invention , the software assigns the test data to a sampling region . the software then calculates the yield for the die in the assigned sampling region . based upon the calculated yield for the sampling regions , the present invention either predicts the yield of the semiconductor wafer and / or adjusts the boundary of the sampling region such that the adjusted sampling region predicts either a higher or lower yield for the semiconductor wafer . based upon such calculations , the software program identifies combinations of regions that have the highest predicted yield , suggests process modifications , and initiates new semiconductor wafer runs to satisfy shipment fulfillment . fig1 depicts a semiconductor wafer 100 partitioned into four quadrant sampling regions . the description below describes the situation where each sampling region has at least one tested die it being understood , however , that each sampling region must not have a tested die . for example some sampling regions such as the outer periphery of the semiconductor wafer are known to have bad die . accordingly , in such sampling regions the die must not be tested , but instead would be presumed bad . while all sampling regions have tested die in fig1 , not every die has been tested in any sampling region . die 155 represents an untested die , while die 150 and 160 represent bad and good die respectively . fig1 depicts a wafer with a representative sampling of tested die . with continued reference to fig1 , contrary to prior art knowledge , bad die 150 are not randomly distributed on the semiconductor wafer . with respect to the top half of the semiconductor wafer 100 , the fourth sampling region 116 comprises only bad die , while the third sampling region 114 comprises eight bad die and one good die 160 . therefore , the top half of the semiconductor wafer with sampling regions 114 , 116 comprises only one good die . with respect to the bottom half of the semiconductor wafer , the first sampling region 110 comprises only four bad die and two good die , while the second sampling region 112 comprises only three bad die and seven good die . clearly , the bottom half of the wafer contains the most good die . in accordance with the inventive method of the present invention , the bottom half would be the recommended salvaged region of the wafer . even with the improved sampling of the present invention , however , one good die 160 will be discarded . fig2 depicts the same semiconductor wafer 100 of fig1 with adjusted sampling region boundaries 220 , 222 , 224 , 226 , and 228 in accordance with a further embodiment of the present invention . note that the same number of good and bad die are present on the semiconductor wafer 100 , however in accordance with the present invention , the boundaries of the sampling regions have been adjusted . the software program recognized that at least one good die 160 could be salvaged in the upper right hand sampling region of the semiconductor wafer and iteratively moved the boundaries of the sampling regions to encapsulate the good die . accordingly , based upon this adjusted boundary approach , if the sampling regions 220 , 222 are salvaged , only bad die are discarded . fig3 illustrates the statistical yield prediction of the present invention for the semiconductor wafer 100 depicted in fig1 and 2 . the predicted yield 380 for the combination of the first , second , and third quadrants 110 , 112 , 114 of fig1 is 70 %. with reference to fig2 , the predicted yield 382 for the combination of the first and second slice 220 , 222 is 45 . 5 %. the software of the present invention also calculates yield capacities for a combination of sampling region types . as shown in fig3 , the predicted yield 384 for the combination of the third , fourth , and fifth slices 224 , 226 , 228 along with the second quadrant 112 is 34 . 5 %. fig1 depicts the predefined shape sampling method of the present invention , however as detailed above the present invention further comprises a dynamically chosen sampling region based upon a nearest neighbor method . in accordance with this method , a first region is tested for predicted yield . next , a region neighboring that first region is tested for predicted yield . if the neighboring region has predicted yield characteristics similar to the first region , the first region expands to include that neighboring sampling region . otherwise , the first region excludes the neighboring sampling region and chooses another neighboring sampling region for predicted yield comparison . in so doing , the present invention dynamically chooses sampling regions . fig4 illustrates the semiconductor wafer partitioned into overlaying circular and pie shaped sampling regions in accordance with the preferred embodiments of the present invention . it should be understood , that while the five circular sampling regions 170 – 174 and eight pie shaped sampling regions 140 – 147 are symmetrical , asymmetrical shapes are also within the spirit and scope of the present invention . the present invention calculates yield for any combination of pie shaped and / or circular sampling region . if a particular combination , such as for example circular sampling region 170 in combination with pie shaped sampling regions 144 and 145 predicted the most number of good die , such combination would be identified as the sampling region from which the die should be cut for shipment . with continued reference to the nearest neighbor method of the present invention and fig4 , if the present invention tests sampling region 174 , which represents the outer periphery of the semiconductor wafer , and as is common with the outer periphery of a semiconductor wafer determines that the die are partial , and accordingly bad , the present invention would test the nearest neighbor , or in other words sampling region 173 . sampling region 173 represents the ring closest to the outer periphery . if the present invention determines that the sampling region 173 has a similar deficient calculated yield , sampling regions 173 and 174 would be combined . future testing of the combined sampling region 173 and 174 could then be prevented . alternatively , die from the combined sampling regions 173 and 174 would be automatically discarded . once the present invention has calculated the yield for a given sampling as well as either identified the combination of sampling regions that maximizes predicted yield for the semiconductor wafer , such information can be used to predict semiconductor lot , and better still semiconductor shipment yield . if the predicted semiconductor lot or shipment yield does not meet a predetermined criteria , the present invention can initiate new semiconductor wafer runs . alternatively , if the predicted semiconductor lot or shipment does not meet the predetermined criteria , the present invention can alter semiconductor fabrication process conditions . while the present invention has been particularly described in conjunction with a specific preferred embodiment and other alternative embodiments , it is evident that numerous alternatives , modifications and variations will be apparent to those skilled in the art in light of the foregoing description . it is therefore intended that the appended claims embrace all such alternatives , modifications and variations as falling within the true scope and spirit of the present invention .