the present invention is related to display drivers , and more particularly to approaches for utilizing single display driver chips to drive multiple displays . turning to fig2 , a display system 200 including an existing single display driver chip 210 configured to drive two or more displays 245 , 250 is depicted in accordance with some embodiments of the present invention . single display driver chip 210 includes an lcd driver 215 and a memory buffer 220 as indicated by the dashed line . in some cases , a processor 230 and / or a memory 235 may also be incorporated on the same chip as lsc driver 215 . lcd driver 215 is programmable by processor 230 via a program interface 225 . such programming may be accomplished through use of any of a number of programming approaches and interfaces known in the art and consistent with the requirements of lcd driver 215 , and may be accomplished by executing one or more instructions that are maintained in a memory 235 . such instructions may be executable by processor 230 and / or lcd driver 215 , and may be , for example , software or firmware instructions . it should be noted that memory 235 may be any form or combination of computer readable media including , but not limited to , a hard disk drive , a random access memory , a flash memory , a removable magnetic storage media , a cd rom , combinations of he aforementioned and / or the like . lcd driver 215 provides a display output set that includes both a display data portion and one or more timing signals . such timing signals may include , but are not limited to , a horizontal sync signal , a vertical sync signal and a display clock . based on the disclosure provided herein , one of ordinary skill in the art will recognize a variety of timing signals and display data that may be included in a display output set provided by lcd driver 215 . in different embodiments of the present invention , one portion 260 of the display output set is driven directly to both display 245 and display 250 . another portion 270 of the display output set is driven indirectly to both display 245 and display 250 via a splitter logic circuit 240 also referred to herein as a splitter device . display system 200 may be configured in a variety of novel ways to allow existing single display driver chip 210 to support two or more displays . four different approaches are described below in relation to fig4 - 6 , but it should be noted that other approaches may be possible in accordance with different embodiments of the present invention . turning to fig3 a - 3 b , a method in accordance with one or more embodiments of the present invention for utilizing an existing single display driver chip 210 to drive two or more displays is discussed . the method operates through defining a virtual display 300 . virtual display 300 is a memory buffer that is defined to maintain a display memory for a first display 310 , and a display memory for a second display 320 virtually positioned horizontally next to first display 310 . thus , where virtual display 300 is defined to be of a dimension x - width and y - height , the memory buffer is a size 2x * y . it should be noted that while virtual display 300 is shown as a rectangular memory area , that a linear or other memory area of the above mentioned size may be utilized in accordance with different embodiments of the present invention . virtual display 300 is defined within memory buffer 220 as a double wide , single high display . in combination with virtual display 300 , lcd driver 215 is programmed by processor 230 to operate on a single wide , double high display . this causes lcd driver 215 to assert a horizontal sync at the half way point of each display line ( i . e ., addresses [ x − 1 , 0 ], [ x − 1 , 1 ] . . . [ x − 1 , y ]), and at the completion of each display line ( i . e ., addresses [ 2x , 0 ], [ 2x , 1 ] . . . [ 2x , y ]). in such a configuration , the display data and the vertical sync timing signal are provided directly from lcd driver 215 to display 245 and display 250 . in contrast , the display clock and the horizontal sync timing signals from lcd driver 215 are provided indirectly to display 245 and display 250 via splitter logic circuit 240 . in operation , the display clock is passed to display 245 for the first half of the display line ( i . e ., addresses 0 to x − 1 ) and gated from display 250 for the same period , and passed to display 250 for the second half of the display line ( i . e ., addresses x to 2x − 1 ) and gated from display 245 for the same period . similarly , horizontal syncs generated for the first half of the display line ( i . e ., addresses [ x − 1 , y − 1 ]) are passed to display 245 , and horizontal syncs generated for the second half of the display line ( i . e ., addresses [ 2x − 1 , y − 1 ]) are passed to display 250 . it should be noted that some displays may effectively ignore the display clock when horizontal and vertical syncs are not received . for example , a display may clock in a defined number of display data ( i . e ., pixels ) after reception of a horizontal sync , but ignore display data received in excess of the defined number . in such a circumstance , it may not be necessary to gate the display clock to the particular display . alternatively , in some cases a display may ignore horizontal and vertical syncs that are not received with an active display clock . in such instances , by gating the display clock to a particular display it would not be necessary to also gate the horizontal and vertical syncs to the display . the aforementioned embodiments of the present invention may be described as having a device splitter that asserts a first horizontal sync for the first display upon a first assertion of the virtual horizontal sync and asserts a second horizontal sync for the second display upon a second assertion of the virtual horizontal sync . such language is used in its broadest sense to mean any situation where a horizontal sync is alternated between multiple displays . thus , this may include , but is not limited to : ( 1 ) asserting the horizontal sync to display 245 on one assertion of the horizontal sync provided by lcd driver 215 and not to display 250 , and asserting the horizontal sync to display 250 on a subsequent assertion of the horizontal sync provided by lcd driver 215 and not to display 245 ; ( 2 ) providing the display clock from lcd driver 215 to display 245 during one assertion of the horizontal sync and gating the display clock to display 250 during the same period , and providing the display clock from lcd driver 215 to display 250 during a subsequent assertion of the horizontal sync and gating the display clock to display 245 during the same period ; and ( 3 ) gating both the horizontal sync and the display clock to display 245 during one period and not to display 250 during the same period , and gating both the horizontal sync and the display clock to display 250 during a subsequent period and not to display 245 during the same period . based on the disclosure provided herein , one of ordinary skill in the art will recognize a variety of other approaches that may be used to assert a horizontal sync to one device and not the other , and then asserting the horizontal sync to the other display during a subsequent period . turning to fig3 b , a flow diagram 301 graphically displays the above described process . following flow diagram 301 , memory buffer 220 is provisioned to hold a 2x * y memory ( block 306 ). this is the double wide , single high virtual display . in addition , lcd driver 215 is programmed to treat virtual display 300 as a unified single wide , double high display ( block 311 ). the memory address to memory buffer 220 is reset to the beginning of the display memory for a first display 310 ( block 316 ). display data from the beginning address is then read from memory buffer 220 and provided to both display 245 and display 250 ( blocks 321 , 326 ). the display clock may be , however , only passed through to display 245 during access to display memory 310 , and only to display 250 during access to display memory 320 . it is then determined whether the address is the last address in a line of virtual display 300 ( i . e ., 2x − 1 ) ( block 331 ). where it is determined that the address is the last address in the line ( block 331 ), it is determined whether the address is the last address of virtual display 300 ( i . e ., 2x − 1 , y − 1 ) ( block 346 ). where the address is the last address of virtual display 300 ( block 346 ), the vertical sync from lcd driver 215 is passed to both display 245 and display 250 ; the horizontal sync is passed from lcd driver 215 by splitter logic circuit 240 to display 250 ; and the memory address is reset ( block 316 ). in contrast , where the address is not the last address of virtual display 300 ( i . e ., the x address is at a maximum , but the y address is not ) ( block 346 ), the horizontal sync is passed from lcd driver 215 by splitter logic circuit 240 to display 245 ( block 351 ), the address is incremented ( block 361 ), and the next display data is read from memory buffer 220 ( block 321 ). alternatively , where it is determined that the address is not the last address in the line ( block 331 ), it is determined whether the address is the mid - address in the line ( i . e ., x − 1 ) ( block 336 ). where it is determined that the address is the mid - address in the line ( block 336 ), the horizontal sync is passed from lcd driver 215 by splitter logic circuit 240 to display 250 ( block 341 ), the address is incremented ( block 361 ), and the next display data is read from memory buffer 220 ( block 321 ). in contrast , where it is determined that the address is not the mid - address in the line ( block 336 ), the address is incremented ( block 361 ), and the next display data is read from memory buffer 220 ( block 321 ). as just some of the advantages of the embodiments discussed in relation to fig3 a - 3 b , lcd driver 215 treats virtual display 300 as one large screen in memory , and provides a relatively simple implementation . it should be noted that the display clock is an nx clock for a given display refresh rate where n represents the number of displays driven . in some cases , splitter logic circuit 240 may include buffers that may be used to re - time display data and / or timing signals to provide desired setup and hold times in relation to the display clock . turning to fig4 a - 4 b , another method in accordance with some embodiments of the present invention for utilizing existing single display driver chip 210 to drive two or more displays is discussed . the method operates through defining a virtual display 400 . virtual display 400 is a memory buffer that is defined to maintain a display memory for a first display 410 , and a display memory for a second display 420 virtually positioned vertically next to first display 410 . thus , where virtual display 400 is defined to be of a dimension x - width and y - height , the memory buffer is a size x * 2y . it should be noted that while virtual display 400 is shown as a rectangular memory area , that a linear or other memory area of the above mentioned size may be utilized in accordance with different embodiments of the present invention . virtual display 400 is defined within memory buffer 220 as a single wide , double high display . in combination with virtual display 400 , lcd driver 215 is programmed by processor 230 to operate on a double buffered single wide , single high displays . this causes lcd driver 215 to assert a horizontal sync at the end of each display line ( i . e ., addresses x ), and to assert a vertical sync at the end of each of the double buffers ( i . e ., addresses [ x − 1 , y − 1 ] and [ x − 1 , 2y − 1 ]). in such a configuration , the display data and the horizontal sync timing signal are provided directly from lcd driver 215 to display 245 and display 250 . in contrast , the display clock and the vertical sync timing signals from lcd driver 215 are provided indirectly to display 245 and display 250 via splitter logic circuit 240 . in operation , the display clock is passed to display 245 while addresses associated display memory 410 are accessed and gated from display 250 for the same period , and passed to display 250 while addresses associated display memory 420 are accessed and gated from display 245 for the same period . similarly , a vertical sync generated for the end of display memory 410 ( i . e ., address [ x − 1 , y − 1 ]) is passed to display 245 , and a vertical sync generated for the end of display memory 410 ( i . e ., address [ x − 1 , y − 1 ]) is passed to display 250 . again , it should be noted that some displays may effectively ignore the display clock when horizontal and vertical syncs are not received . for example , a display may clock in a defined number of display data ( i . e ., pixels ) after reception of a horizontal sync , but ignore display data received in excess of the defined number . in such a circumstance , it may not be necessary to gate the display clock to the particular display . alternatively , in some cases a display may ignore horizontal and vertical syncs that are not received with an active display clock . in such instances , by gating the display clock to a particular display it would not be necessary to also gate the horizontal and vertical syncs to the display . the aforementioned embodiments of the present invention may be described as having a device splitter that asserts a first vertical sync for the first display upon a first assertion of the virtual vertical sync and asserts a second vertical sync for the second display upon a second assertion of the virtual vertical sync . such language is used in its broadest sense to mean any situation where a vertical sync is alternated between multiple displays . thus , this may include , but is not limited to : ( 1 ) asserting the vertical sync to display 245 on one assertion of the vertical sync provided by lcd driver 215 and not to display 250 , and asserting the vertical sync to display 250 on a subsequent assertion of the vertical sync provided by lcd driver 215 and not to display 245 ; ( 2 ) providing the display clock from lcd driver 215 to display 245 during one assertion of the vertical sync and gating the display clock to display 250 during the same period , and providing the display clock from lcd driver 215 to display 250 during a subsequent assertion of the vertical sync and gating the display clock to display 245 during the same period ; and ( 3 ) gating both the vertical sync and the display clock to display 245 during one period and not to display 250 during the same period , and gating both the vertical sync and the display clock to display 250 during a subsequent period and not to display 245 during the same period . based on the disclosure provided herein , one of ordinary skill in the art will recognize a variety of other approaches that may be used to assert a vertical sync to one device and not the other , and then asserting the vertical sync to the other display during a subsequent period . turning to fig4 b , a flow diagram 401 graphically displays the above described process . following flow diagram 401 , memory buffer 220 is provisioned to hold a double buffered x * y memory ( i . e ., x * 2y ) ( block 406 ). this is a single wide , double high virtual display . in addition , lcd driver 215 is programmed to treat virtual display 400 as a double buffered single wide , single high display ( block 411 ). the memory address to memory buffer 220 is reset to the beginning of display memory 410 ( block 416 ). display data from the beginning address is then read from memory buffer 220 and provided to both display 245 and display 250 ( blocks 421 , 426 ). the display clock is , however , only passed through to display 245 during access to display memory 410 and only to display 250 during access to display memory 250 . it is then determined whether the address is the last address in a line of virtual display 300 ( i . e ., x − 1 ) ( block 431 ). where it is determined that the address is not the last address in a line ( block 431 ), the address is incremented ( block 471 ), and the next display data is read from memory buffer 220 ( block 421 ). where it is determined that the address is the last address in the line ( block 431 ), it is determined whether the address is the last address of display memory 410 ( block 436 ). where it is determined that the address is the last address of display memory 410 ( block 436 ), both a horizontal sync and a vertical sync is applied to display 245 ( block 456 ), the address is incremented ( block 471 ), and the next display data is read from memory buffer 220 ( block 421 ). alternatively , where it is determined that the address is not the last address of display memory 410 ( block 436 ), it is determined whether the address is within display memory 410 or display memory 420 ( i . e ., whether the address is less than y − 1 ) ( block 441 ). where it is determined that the address is within display memory 410 , a horizontal sync is asserted to display 245 ( block 461 ), the address is incremented ( block 471 ), and the next display data is read from memory buffer 220 ( block 421 ). alternatively , where it is determined that the address is not within display memory 410 ( block 441 ), it is determined whether the address is the last address in display memory 420 ( i . e ., address 2y ) ( block 446 ). where it is determined that the address is the last ( block 446 ), a horizontal sync and a vertical sync are asserted to display 250 ( block 451 ), the address is reset ( block 416 ), and the next display data is read from memory buffer 220 ( block 421 ). alternatively , where it is determined that the address is not the last address in display memory 420 ( block 446 ), a horizontal sync is asserted to display 250 ( block 466 ), the address is incremented ( block 471 ), and the next display data is read from memory buffer 220 ( block 421 ). as just some of the advantages of the embodiments discussed in relation to fig4 a - 4 b , lcd driver 215 treats virtual display 400 as one large screen in memory , and provides a relatively simple implementation . it should be noted that the display clock is an nx clock for a given display refresh rate where n represents the number of displays driven . in some cases , splitter logic circuit 240 may include buffers that may be used to re - time display data and / or timing signals to provide desired setup and hold times in relation to the display clock . turning to fig5 a - 5 b , yet another method in accordance with some embodiments of the present invention for utilizing existing single display driver chip 210 to drive two or more displays is discussed . the method operates through defining a first virtual display 500 and a second virtual display 510 . virtual display 500 is a memory buffer that is defined to maintain a display memory for a first display 505 , and a display memory for a second display 515 . both virtual display 500 and virtual display 510 may be maintained in the same memory buffer . it should be noted that while virtual displays 500 , 510 are shown as a rectangular memory areas , that a linear or other memory area of the above mentioned size may be utilized in accordance with different embodiments of the present invention . virtual display 500 and virtual display 510 are defined within memory buffer 220 . in combination with virtual displays 500 , 510 , lcd driver 215 is repeatedly re - programmed by processor 230 to operate on distinct displays . this causes lcd driver 215 to assert horizontal syncs and vertical syncs tailored for the respective displays . in such a configuration , the display data is provided directly from lcd driver 215 to display 245 and display 250 . in contrast , the display clock , the vertical sync , and the horizontal sync timing signals from lcd driver 215 are provided indirectly to display 245 and display 250 via splitter logic circuit 240 . in operation , the display clock , the horizontal sync and the vertical sync are passed to display 245 while addresses associated display memory 505 are accessed and gated from display 250 for the same period , and passed to display 250 while addresses associated display memory 515 are accessed and gated from display 245 for the same period . turning to fig5 b , a flow diagram 501 graphically displays the above described process . following flow diagram 501 , memory buffer 220 is provisioned to hold two distinct memory buffers ( block 406 ). these are virtual displays 500 , 510 . lcd driver 215 is programmed to drive a display of the same size as virtual display 500 ( block 511 ), and the memory address is reset ( block 516 ). while programmed to drive virtual display 500 , the display clock is provided to display 245 , and gated from display 250 . display data is read from the memory ( block 521 ) and provided to both display 245 and display 250 ( block 526 ). it is then determined if the address corresponds to the last address in a display line of virtual display 500 ( i . e ., ( x − 1 ) 1 ) ( block 531 ). where the address does not correspond to the last address in a display line of virtual display 500 ( block 531 ), the address is incremented ( block 546 ), and the next data is read from memory buffer 220 ( block 521 ). of note , since the controller is being reprogrammed , each screen may have a buffer at an independent address . further , the sizes and color depths of the two displays may also be different . alternatively , where it is determined that the address does correspond to the last address in a display line of virtual display 500 ( block 531 ), it is additionally determined whether the address corresponds to the last address in virtual display 500 ( block 536 ). where the address does not correspond to the last address in virtual display 500 ( block 536 ), a horizontal sync is asserted to display 245 ( block 541 ), the address is incremented ( block 546 ), and the next data is read from memory buffer 220 ( block 521 ). where the address does correspond to the last address in virtual display 500 ( block 536 ), a horizontal sync and a vertical sync are asserted to display 245 ( block 551 ), and lcd driver 215 is re - programmed programmed to drive a display of the same size as virtual display 510 ( block 556 ), and the memory address is reset ( block 561 ). while programmed to drive virtual display 510 , the display clock is provided to display 250 , and gated from display 245 . display data is read from the memory ( block 566 ) and provided to both display 245 and display 250 ( block 571 ). it is then determined if the address corresponds to the last address in a display line of virtual display 510 ( i . e ., ( x − 1 ) 2 ) ( block 576 ). where the address does not correspond to the last address in a display line of virtual display 510 ( block 576 ), the address is incremented ( block 591 ), and the next data is read from memory buffer 220 ( block 566 ). alternatively , where it is determined that the address does correspond to the last address in a display line of virtual display 510 ( block 576 ), it is additionally determined whether the address corresponds to the last address in virtual display 510 ( block 581 ). where the address does not correspond to the last address in virtual display 510 ( block 581 ), a horizontal sync is asserted to display 250 ( block 586 ), the address is incremented ( block 591 ), and the next data is read from memory buffer 220 ( block 566 ). where the address does correspond to the last address in virtual display 510 ( block 581 ), a horizontal sync and a vertical sync are asserted to display 250 ( block 596 ), and lcd driver 215 is re - programmed programmed to drive a display of the same size as virtual display 500 ( block 511 ), and the memory address is reset ( block 516 ). the process of re - programming lcd driver 215 may be accomplished during a vertical sync period of the particular displays . such an approach allows for driving two displays with different characteristics . as just some of the advantages of the embodiments discussed in relation to fig5 a - 5 b , lcd driver 215 is capable of displays with different characteristics including , but not limited to , display size and display clock rate . in such embodiments , both displays are treated as distinct virtual displays in memory . it should be noted that the display clock is approximately an nx clock for a given display refresh rate where the number of driven displays is n . in particular cases , the display clock may be n 1 + n 2 and the two displays sizes may be very different . in some cases , a smaller display may require slower clocks than a larger display . it may turn out that the wall clock time is about equivalent to nx , but two distinct clock frequencies will be required to drive the displays ( one frequency for each display ). in some cases , splitter logic circuit 240 may include buffers that may be used to re - time display data and / or timing signals to provide desired setup and hold times in relation to the display clock . turning to fig6 a - 6 b , yet a further method in accordance with one or more embodiments of the present invention for utilizing an existing single display driver chip 210 to drive two or more displays is discussed . the method operates through defining a virtual display 600 . virtual display 600 is a memory buffer that is defined to maintain a display memory for double wide , single high display where data destined for two different displays are interleaved . in one particular embodiment of the present invention , the data destined for the two different displays is interleaved on a pixel by pixel basis . based on the disclosure provided herein , one of ordinary skill in the art will recognize a variety of other approaches to interleaving that may be used in accordance with different embodiments of the present invention . in combination with virtual display 600 , lcd driver 215 is programmed by processor 230 to operate on a double wide , single high display . this causes lcd driver 215 to assert a horizontal sync at the end of each display line ( i . e ., addresses [ x − 1 , 0 ], [ x − 1 , 1 ] . . . [ x − 1 , y − 1 ]). in such a configuration , the display data , horizontal sync and the vertical sync timing signal are provided directly from lcd driver 215 to display 245 and display 250 . in contrast , the display clock is provided indirectly to display 245 and display 250 via splitter logic circuit 240 . in operation , the display clock is divided by two with one cycle of the divided display clock being passed to display 245 , and the other cycle of the display clock being passed to display 250 . turning to fig6 b , a flow diagram 601 graphically displays the above described process . following flow diagram 601 , memory buffer 220 is provisioned to hold a 2x * y memory ( block 606 ). this is the double wide , single high virtual display . in addition , lcd driver 215 is programmed to treat virtual display 600 as a unified double wide , single high display ( block 611 ). the memory address to memory buffer 220 is reset to the beginning of virtual display 600 ( block 616 ). display data from the beginning address is then read from memory buffer 220 and provided to both display 245 and display 250 ( blocks 621 , 626 ). the display clock is , however , provided on an alternating basis to display 245 and then to display 250 . thus , for example , the divided display clock is provided to display 245 in association with one display data , to display 250 in association with a succeeding display data , back to display 245 in association with the next succeeding display data , and then back to display 250 in association with the next succeeding display data . it is determined whether the address is the last address in the line ( i . e ., address 2x − 1 ) ( block 631 ). where it is determined that the address is not the last address in the line ( block 631 ), the address is incremented ( block 636 ) and the next display data is read from memory buffer 220 ( block 621 ). in contrast , where it is determined that the address is the last address in the line ( block 631 ), it is determined whether the address is also the last address of virtual display 600 ( i . e ., 2 − 1x , y − 1 ) ( block 641 ). where the address is not the last address of virtual display 600 ( block 641 ), the horizontal sync is passed from lcd driver 215 to both display 245 and display 250 ( block 646 ), the address is incremented ( block 636 ), and the next display data is read from memory buffer 220 ( block 621 ). alternatively , where it is determined that the address is the last address of virtual display 600 ( block 641 ), the vertical sync and the horizontal sync from lcd driver 215 are passed to both display 245 and display 250 ( block 651 ), and the memory address is reset ( block 616 ). as just some of the advantages of the embodiments discussed in relation to fig6 a - 6 b , only a 1x display clock is provided to both displays . it should be noted that special graphics software may be used to interleave the data into virtual display 600 . in some cases , splitter logic circuit 240 may include buffers that may be used to re - time display data and / or timing signals to provide desired setup and hold times in relation to the display clock . it should be noted that in each of the aforementioned embodiments , the display data is provided directly to multiple displays . in some cases , this can resulting problematic setup and hold issues in relation to clocking the display data in to the recipient displays . thus , some embodiments of the present invention utilize buffers to re - time the display data ( e . g ., performing line caching ) provided to the respective displays . turning to fig7 , a display system 700 including an existing single display driver chip 710 configured to drive two or more displays 745 , 750 is shown in accordance with other embodiments of the present invention . single display driver chip 710 includes an lcd driver 715 and a memory buffer 720 as indicated by the dashed line . lcd driver 715 is programmable by a processor 730 via a program interface 725 . such programming may be accomplished through use of programming approach known in the art and consistent with lcd driver 715 , and may be accomplished by executing one or more instructions that are maintained in a memory 735 . such instructions may be executable by processor 730 and / or lcd driver 715 , and may be , for example , software or firmware instructions . it should be noted that memory 235 may be any form or combination of computer readable media including , but not limited to , a hard disk drive , a random access memory , a flash memory , a removable magnetic storage media , combinations of he aforementioned and / or the like . lcd driver 715 provides a display output set that includes both a display data portion and one or more timing signals . such timing signals may include , but is not limited to , a horizontal sync signal , a vertical sync signal and a display clock . based on the disclosure provided herein , one of ordinary skill in the art will recognize a variety of timing signals and display data that may be included in a display output set provided by lcd driver 715 . in different embodiments of the present invention , one portion 760 of the display output set is driven to both display 745 and display 750 via respective fifo memories 792 , 794 . another portion 770 of the display output set is driven indirectly through fifo memories 792 , 794 via a splitter logic circuit 740 . fifo memories 792 , 794 may be used to re - time signals from lcd driver 715 to displays 745 , 750 as is known in the art . in contrast to that known in the art , one or more of the timing signals from lcd driver 715 may be reformed from a single display format produced by lcd driver 715 to a multiple display format consistent with that discussed above in relation to fig3 - 6 . in conclusion , the present invention provides novel systems , devices , methods and arrangements for driving a display . while detailed descriptions of one or more embodiments of the invention have been given above , various alternatives , modifications , and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention . therefore , the above description should not be taken as limiting the scope of the invention , which is defined by the appended claims .