embodiments of the present invention will be described hereinafter with reference to the accompanying drawings . first , a voltage generating circuit according to embodiment 1 of the present invention is described with reference to the drawings . fig1 is a circuit diagram showing configuration of a voltage generating circuit . fig2 is a circuit diagram showing a differential amplifier circuit . fig3 is a circuit diagram showing a gate voltage stabilizing circuit . in the present embodiment , there is provided a gate voltage stabilizing circuit that suppresses a change of a gate voltage of a step - down transistor , when a standby state changes to an active state or when an active state changes to a standby state . as shown in fig1 , a voltage generating circuit 30 is provided with a differential amplifier circuit 1 , a gate voltage stabilizing circuit 2 , an n channel mis transistor nt 1 , an n channel mis transistor nt 2 , an n channel mis transistors nt 11 to nt 13 , an n channel mis transistor ntt 1 , an n channel mis transistor ntt 2 , a p channel mis transistors pt 11 to pt 13 , a p channel mis transistor ptt 1 , a p channel mis transistor ptt 2 , resistances r a1 to r a4 , resistances r s1 to r s4 , and a capacitor c 1 . note that a mis transistor is also referred to as a metal insulator semiconductor field effect transistor ( misfet ). the voltage generating circuit 30 is provided inside a semiconductor chip as a semiconductor storage , for example . the voltage generating circuit 30 receives input of a high potential side power source v d voltage as an external supply voltage and a high potential side power source v pp voltage as a supply voltage for stepping up a word line voltage , and outputs an output voltage v int as a stepped - down internal supply voltage to unillustrated various circuits provided in the semiconductor chip . in the p channel mis transistor ptt 1 , the high potential side power source v pp voltage is inputted into a source thereof , and a control signal pgm to be outputted from the differential amplifier circuit 1 is inputted into a gate . the p channel mis transistor ptt 1 turns “ on ” when the control signal pgm is at “ low ” level to output an output voltage ( gate voltage ) v g from the drain side . in the n channel mis transistor nt 1 , the output voltage ( gate voltage ) v g is inputted into a drain thereof to connect a gate thereto . the n channel mis transistor nt 1 acts as a diode - connected mirror transistor . in the n channel mis transistor nt 2 , the output voltage ( gate voltage ) v g is inputted into a drain to connect a gate thereto . the n channel mis transistor nt 2 acts as a diode - connected mirror transistor . in the p channel mis transistor ptt 2 , the high potential side power source v dd voltage is inputted into a source , and a control signal vpg is inputted into a gate . the p channel mis transistor ptt 2 turns “ on ” when the control signal vpg is at “ low ” level . the n channel mis transistor ntt 1 is an output transistor of a source follower type . a drain thereof is connected to a drain of the p channel mis transistor ptt 2 , the output voltage ( gate voltage ) v g is inputted into a gate , and an output voltage v int is outputted as an internal supply voltage that has been stepped down when the control signal vpg is active . the n channel mis transistor ntt 2 is an output transistor of a source follower type . the high potential side power source v dd voltage is inputted into a drain thereof , the output voltage ( gate voltage ) v g is inputted to a gate , and the output voltage v int is outputted as the internal supply voltage that has been stepped down in the standby state and the active state . the n channel mis transistor ntt 1 that is a step - down transistor supplies an output voltage v int potential when the control signal vpg turns “ on ” the p channel mis transistor ptt 2 ( in the active state ). the n channel mis transistor ntt 2 that is a step - down transistor supplies the output voltage v int potential in the standby state and in the active state , not by using the control signal vpg . here , assume that the amount of current in the active state is iact , the amount of current in the standby state is istb , a gate width of the n channel mis transistor ntt 1 is w1 , and a gate width of the n channel mis transistor ntt 1 is w2 . where the gate lengths of the n channel mis transistors ntt 1 and ntt 2 are same , designing is performed so as to satisfy the following : in other words , designing is performed so that an amount of load current per unit gate width in the standby state can match that in the active state . one end of the capacitor c 1 is connected to sources of the n channel mis transistors ntt 1 and ntt 2 , and the other end thereof is connected to the low potential side power source v ss . the capacitor c 1 is mounted ( on - chip ) on a semiconductor integrated circuit to be provided in the voltage generating circuit 30 . in the n channel mis transistor ntt 11 , a drain is connected to the source of the n channel mis transistor nt 1 , a source is connected to one end of a resistance r a4 , and a control signal act is inputted into a gate . in the p channel mis transistor pt 11 , a source is connected to the source of the n channel mis transistor nt 1 , a drain is connected to one end of the resistance r a4 , and a control signal / act is inputted to a gate . the control signal / act is a signal having an opposite phase to the control signal act . the n channel mis transistor nt 11 and the p channel mis transistor pt 11 function as transfer gates and turn “ on ” when the control signal act is at “ high ” level ( the control signal / act is at “ low ” level ). the other end of the resistance r a4 is connected to a node n 1 . one end of a resistance r a3 is connected to a node n 1 . in the n channel mis transistor nt 12 , a drain is connected to the other end of the resistance r a3 , a source is connected to one end of the resistance r a2 , and the control signal act is inputted into a gate . in the p channel mis transistor pt 12 , a source is connected to other end of the resistance r a3 , a drain is connected to one end of the resistance r a2 , and the control signal / act is inputted into a gate . the n channel mis transistor nt 12 and the p channel mis transistor pt 12 function as transfer gates and turn “ on ” when the control signal act is at “ high ” level ( the control signal / act is at “ low ” level ). the other end of the resistance r a2 is connected to a node n 2 . one end of a resistance r a1 is connected to the node n 2 . in the n channel mis transistor nt 13 , a drain is connected to the other end of the resistance r a1 , a source is connected to the low potential side power source v ss that is a ground voltage , and the control signal act is inputted into a gate . in the p channel mis transistor pt 13 , a source is connected to the other end of the resistance r a1 , a drain is connected to the low potential side power source v ss , and the control signal / act is inputted into a gate . the n channel mis transistor nt 13 and the p channel mis transistor pt 13 function as transfer gates and turn “ on ” when the control signal act is at “ high ” level ( the control signal / act is at “ low ” level ). on end of the resistance r s4 is connected to the source of the n channel mis transistor nt 2 , and the other end thereof is connected to the node n 1 and a node n 3 . one end of a resistance r s3 is connected to the node n 3 and the other end thereof is connected to one end of a resistance r s2 . the other end of the resistance r s2 is connected to the node n 2 and a node n 4 . one end of a resistance r s1 is connected to the node n 4 and the other end thereof is connected to the low potential side power source v ss . here , on the n channel mis transistor nt 2 side ( the n channel mis transistor nt 2 , the resistances r s1 to r s4 ), current always flows to the low potential side power source v ss side , while on the n channel mis transistor nt 1 side ( the n channel mis transistor nt 1 , the resistances r a1 to r a4 , the n channel mis transistors nt 11 to nt 13 , and the p channel mis transistors pt 11 to pt 13 ), current flows to the low potential side power source v ss side in the active state ( when the control signal act is at “ high ” level ( the control signal / act is at “ low ” level )). a feedback voltage v a that is a voltage resistive - divided from the nodes n 2 and n 4 is inputted to a (+) port on the input side of the differential amplifier circuit 1 . as shown in fig2 , the differential amplifier circuit 1 is provided with n channel mis transistors nt 21 to nt 23 , a p channel mis transistor pt 21 , and a p channel mis transistor pt 22 . in the differential amplifier circuit 1 , a reference voltage v ref is inputted to a (−) port on the input side , the feedback voltage v a is inputted to the (+) port on the input side , and a differential amplified signal is outputted as the output voltage ( gate voltage ) v g . the reference voltage v ref used herein is a highly - precise voltage that has very low dependence on temperature and the high potential side power source v dd voltage . for example , such highly - precise voltage is outputted from a band gap reference ( bgr ) circuit . in the p channel mis transistor pt 21 , a source is connected to the high potential side power source v dd . in the p channel mis transistor pt 22 , a source is connected to the high potential side power source v dd , a gate is connected to a drain of the pt 22 and a gate of the p channel mis transistor pt 21 . the p channel mis transistor pt 21 and the p channel mis transistor pt 22 constitutes a current mirror circuit . in the n channel mis transistor nt 21 , a drain is connected to a drain of the p channel mis transistor pt 21 and the reference voltage v ref is inputted into a gate of the n channel mis transistor nt 21 . in the n channel mis transistor nt 23 , a drain is connected to the drain of the p channel mis transistor pt 22 and the feedback reference v a is inputted to a gate of the n channel mis transistor nt 23 . the n channel mis transistor nt 22 and the n channel mis transistor nt 23 form a differential pair . the output voltage ( gate voltage ) v g is outputted from between the drain of the p channel mis transistor pt 21 and the drain of the n channel mis transistor nt 22 . in the n channel mis transistor nt 21 , a drain is connected to sources of the n channel mis transistors nt 22 and nt 23 , a source is connected to the low potential side power source v ss , and a control signal cmpg is inputted into a gate . the n channel mis transistor nt 21 functions as a constant current source . as shown in fig3 , the gate voltage stabilizing circuit 2 is provided with a capacitor c 2 , an inverter inv 1 , an inverter inv 2 , an n channel mis transistor nt 31 , and an n channel mis transistor nt 32 . one end of the capacitor c 2 is a gate of one of the n channel mis transistors , and the other end thereof is the commonly connected source and drain of the n channel mis transistors . the gate voltage stabilizing circuit 2 has a function to suppress a change in the gate voltage of the step - down transistor when the standby state changes to the active state or when the active state changes to standby state . in the n channel mis transistor nt 31 , a drain is connected to a node n 5 ( output voltage ( gate voltage ) v g ), a source is connected to a node n 11 , and a control signal sg 1 is inputted into a gate . in the n channel mis transistor nt 32 , a drain is connected to the node n 11 , the output voltage ( gate voltage ) v g is inputted into a source , and a control signal sg 2 is inputted into a gate . one end of the capacitor c 2 is connected to the node n 11 , and the other end thereof is connected to a node n 12 . the inverter inv 1 inputs the control signal vpg and inverses the signal . the inverter inv 2 inputs a signal to be outputted from the inverter inv 1 , and outputs a signal to the node n 12 , the signal having been inverted from the signal outputted from the inverter inv 1 . next , operation of a voltage generating circuit will be described with reference to fig4 . fig4 is a chart showing operation of the voltage generating circuit . here , the operation of the voltage generating circuit is divided into the following 3 periods and described : ( a ) a period of a standby state ( including time to change to an active state ), ( b ) a period of the active state , and ( c ) a period after the active state changes to the standby state . as shown in fig4 , in the voltage generating circuit 30 , first , the control signal vpg is at “ high ” level , and therefore the p channel mis transistor ptt 2 turns “ off ,” in the standby state ( period ( a )). accordingly , the n channel mis transistor ntt 1 does not supply output voltage v int potential , while the n channel mis transistor ntt 2 supplies the output voltage v int potential . in the gate voltage stabilizing circuit 2 , the n channel mis transistor nt 31 turns “ off ” when a control signal sg 1 is at “ low ” level , the n channel mis transistor nt 32 turns “ on ” when a control signal sg 2 is at “ high ” level , and the node 12 is at “ high ” level when the control signal vpg is at “ high ” level . accordingly , no charge is accumulated in the capacitor c 2 . then , immediately after the standby state changes to the active state ( period ( a )), the control signal vpg changes from “ high ” level to “ low ” level and the p channel mis transistor ptt 2 turns “ on ”. thus , the n channel mis transistor ntt 1 supplies the output voltage v int potential . meanwhile , the n channel mis transistor ntt 2 still supplies the output voltage v int potential irrespective of whether it is in the standby state or in the active state . at this time , a voltage on the drain side ( the node n 6 ) of the n channel mis transistor ntt 1 increases , and therefore the gate voltage v g is likely to rise due to coupling capacitance between the drain and gate of the n channel mis transistor ntt 1 . in the gate voltage stabilizing circuit 2 , however , the control signal sg 1 changes from “ low ” level to “ high ” level to cause the n channel mis transistor nt 31 to turn “ on ,” the control signal sg 2 changes from “ high ” level to “ low ” level to cause the n channel mis transistor nt 32 to turn “ off ,” and the control signal vpg changes from “ high ” level to “ low ” level to cause the node n 12 to change to “ low ” level . accordingly , charges flow from the node n 5 ( output voltage ( gate voltage ) v g ) into the capacitor c 2 and are accumulated therein . thus , the gate voltage stabilizing circuit 2 functions so as to lower the gate voltage v g applied to the n channel mis transistor ntt 1 and to control increase of the output voltage ( gate voltage ) v g . here , in the conventional configuration without the stabilizing circuit according to the present invention shown in fig3 , assume that a coupling capacitance between the drain and the gate of the n channel mis transistor ntt 1 is cgd , a gate capacitance of the n channel mis transistor ntt 1 is cg , a voltage fluctuation between the standby state and the active state of the drain voltage of the n channel mis transistor ntt 1 is δvd , and a fluctuation in the output v int of the voltage generating circuit 30 and in the gate voltage of the n channel mis transistor ntt 1 are δv g . the following expressions are obtained . as the gate capacitance cg becomes larger , δv g becomes smaller , and thus the fluctuation in v int also becomes smaller , which however leads to the problem that the chip area expands . thus , by providing the gate voltage stabilizing circuit 2 as shown in fig3 of this embodiment , an attempt is made to absorb an increased potential of the gate voltage v g through coupling , when the standby state transits to the active state . as it is believed that the charge generated in the node 5 due to coupling is δv g × cg , the charge generated in the node n 5 can be absorbed if the capacitance of the capacitor c 2 is determined so as to satisfy the following expression , where the capacitance of the capacitor c 2 in fig3 is c 3 and the voltage of the control signal vpg is v pg . a case of stepping down the gate voltage v g to be applied to the gate of the n channel mis transistor ntt 1 will be described later . next , when the standby state changes to the active state and after a predetermined period of time elapses ( period ( b )), the control signal vpg is at “ low ” level and accordingly the p channel mis transistor ptt 2 has turned “ on ”. therefore , the condition is maintained in which the n channel mis transistor ntt 1 supplies the output voltage v int potential and the n channel mis transistor ntt 2 supplies the output voltage v int potential . in the gate voltage stabilizing circuit 2 , since the control signal sg 1 changes from “ high ” level to “ low ” level to turn the n channel mis transistor nt 31 “ off ,” the control signal sg 2 changes from “ low ” level to “ high ” level to turn the n channel mis transistor nt 32 “ on ,” and the node n 12 becomes “ low ” level with the control signal vpg at “ low ” level , charges are accumulated in the capacitor c 2 . then , immediately after the active state changes to the standby state ( period ( c )), the control signal changes from “ low ” level to “ high ” level and the p channel mis transistor ptt 2 turns “ off ”. the state is thus maintained in which the n channel mis transistor ntt 1 no longer supplies the output voltage v int potential , while the n channel mis transistor ntt 2 continues to supply the output voltage v int potential . at this time , the voltage on the drain ( node n 6 ) side of the n channel mis transistor ntt 1 is stepped down , and therefore the output voltage ( gate voltage ) v is likely to lower due to the coupling capacitance of the n channel mis transistor ntt 1 . in the gate voltage stabilizing circuit 2 , however , since the control signal sg 1 changes from “ low ” level to “ high ” level to turn the n channel mis transistor nt 31 “ on ,” the control signal sg 2 changes from “ high ” level to “ low ” level to turn n channel mis transistor nt 32 “ off ,” the control signal vpg changes from “ low ” level to “ high ” level to change the node n 12 to “ high ” level , the charges accumulated in the capacitor c 2 are discharged to the node n 5 ( output voltage ( gate voltage ) v g ). thus , the gate voltage stabilizing circuit 2 functions to step up the gate voltage v g to be applied to the gate of the n channel mis transistor ntt 1 , and thereby suppress a drop of the output voltage ( gate voltage ) v g . next , after the active state changed to the standby state and the predetermined period elapsed ( period ( c )), which are not shown , the gate voltage stabilizing circuit 2 is set to the same as the standby state in the period ( a ). as described above , the voltage generating circuit in this embodiment is provided with the differential amplifier circuit 1 , the gate voltage stabilizing circuit 2 , the n channel mis transistor nt 1 , the n channel mis transistor nt 2 , the n channel mis transistors nt 11 to nt 13 , the n channel mis transistor ntt 1 , the n channel mis transistor ntt 2 , the p channel mis transistors ptt 11 to ptt 13 , the p channel mis transistor ptt 1 , the p channel mis transistor ptt 2 , the resistances r a1 to r a4 , the resistances r s1 to r s4 , and the capacitor c 1 . the gate voltage stabilizing circuit 2 is provided with the capacitor c 2 , the inverter inv 1 , the inverter inv 2 , the n channel mis transistor nt 31 , and the n channel mis transistor nt 32 . when the standby state changes to the active state , or when the active state changes to the standby state , the gate voltage stabilizing circuit 2 suppresses a change in the gate voltage of the n channel mis transistor ntt 1 that is a step - down transistor . thus , while an increase is suppressed in the capacitance of the capacitor c 1 mounted ( on - chip ) in a semiconductor integrated circuit where the voltage generating circuit 30 is provided , a fluctuation can be suppressed in the output voltage ( gate voltage ) v g to be generated when the standby state changes to the active state or when the active state changes to the standby state . thereby , the output voltage v int can be outputted as an internal supply voltage that has been stably stepped down . although this embodiment uses a mis transistor for the transistor constituting the voltage generating circuit 30 , a metal oxide semiconductor ( mos ) transistor ( also referred to as mosfet ) may be used as well . a voltage generating circuit according to a second embodiment of the present invention will be described hereinafter with reference to the accompanying drawings . fig5 is a circuit diagram showing a configuration of the voltage generating circuit . fig6 is a circuit diagram showing a gate voltage stabilizing circuit on a low potential side power source side . fig7 is a circuit diagram showing a gate voltage stabilizing circuit on a high potential side power source side . in this embodiment , there are provided a gate voltage stabilizing circuit that suppresses any change in the gate voltage of a step - down transistor when a standby state changes to an active state , and a gate voltage stabilizing circuit that suppresses any change in the gate voltage of the step - down transistor when the active state changes the standby state . hereinbelow , same symbols are assigned to components identical to those in the embodiment 1 , a description of which is omitted , and only different parts will be described . as shown in fig5 , a voltage generating circuit 30 a is provided with the differential amplifier circuit 1 , a gate voltage stabilizing circuit 3 , a gate voltage stabilizing circuit 4 , the n channel mis transistor nt 1 , the n channel mis transistor nt 2 , the n channel mis transistors nt 11 to nt 13 , the n channel mis transistor ntt 1 , the n channel mis transistor ntt 2 , the p channel mis transistors pt 11 to pt 13 , the p channel mis transistor ptt 1 , the p channel mis transistor ptt 2 , the resistances r a1 to r a4 , the resistances r s1 to r s4 , and the capacitor c 1 . the voltage generating circuit 30 a is provided inside a semiconductor chip as a semiconductor storage , for example . the voltage generating circuit 30 a receives input of a high potential side power source v dd voltage as an external supply voltage and a high potential side power source v pp voltage as a supply voltage for stepping up a word line voltage , and outputs an output voltage v int as a stepped - down internal supply voltage to unillustrated various circuits provided in the semiconductor chip . as shown in fig6 , the gate voltage stabilizing circuit 3 is provided with a capacitor c 3 , an n channel mis transistor nt 41 , and an n channel mis transistor nt 42 . one end of the capacitor c 3 is a gate of one of the n channel mis transistors , and the other end thereof is the commonly connected source and drain of the n channel mis transistors . the gate voltage stabilizing circuit 3 has a function to suppress a fluctuation in a gate voltage of the step - down transistor when the standby state changes to the active state . in the n channel mis transistor nt 41 , a drain is connected to the node n 5 ( output voltage ( gate voltage ) v g ), a source is connected to the node n 21 , and a control signal is inputted into a gate . in the n channel mis transistor nt 42 , a drain is connected to the node n 21 , a source is connected to a low potential side power source v ss , and a control signal sg 4 is inputted into a gate . one end of a capacitor c 3 is connected to the node n 21 and the other end is connected to the low potential side power source v ss . as shown in fig7 , the gate voltage stabilizing circuit 4 is provided with a capacitor c 4 , a p channel mis transistor pt 41 , and a p channel mis transistor pt 42 . one end of the capacitor c 4 is a gate of one of the p channel mis transistors , and the other end thereof is the commonly connected source and drain of the p channel mis transistors . the gate voltage stabilizing circuit 4 has a function to suppress a change in a gate voltage of the step - down transistor when the active state changes to the standby state . in the p channel mis transistor pt 42 , a source is connected to a high potential side power source v dd , a drain is connected to a node n 22 , and a control signal sg 6 is inputted into a gate . in the p channel mis transistor pt 41 , a source is connected to the node n 22 , a drain is connected to the node n 5 , and a control signal sg 5 is inputted into a gate . one end of a capacitor c 4 is connected to the node n 22 and the other end is connected to the high potential side power source v dd . next , the operation of the voltage generating circuit will be described hereinafter with reference to fig8 . fig8 is a drawing showing operation of the voltage generating circuit . here , the operation of the voltage generating circuit is divided into the following 3 periods and described : ( a ) a period of a standby state ( including time to change to an active state ), ( b ) a period of the active state , and ( c ) a period after the active state changes to the standby state . as shown in fig8 , in the voltage generating circuit 30 a , first , in the standby state ( period ( a )), the control signal vpg is at “ high ” level , the p channel mis transistor ptt 2 accordingly turns “ off ,” and the n channel mis transistor ntt 1 does not supply the output voltage v int potential , while the n channel mis transistor ntt 2 supplies the output voltage v int potential . in the gate voltage stabilizing circuit 3 , since the n channel mis transistor nt 41 has turned “ off ” with the control signal sg 3 at “ low ” level , and the n channel mis transistor nt 42 has turned “ on ” with the control signal sg 4 at “ high ” level , a voltage of 0 ( zero ) is applied to both electrodes of the capacitor c 3 . in the gate voltage stabilizing circuit 4 , since the p channel mis transistor pt 41 has turned “ off ” with the control signal sg 5 at “ high ” level and the p channel mis transistor pt 42 has turned “ on ” with the control signal sg 6 at “ low ” level , a high potential side power source v dd is applied to both electrodes of the capacitor c 4 . next , immediately after the standby state changes to the active state ( period ( a )), since the control signal vpg changes from “ high ” level to “ low ” level and the p channel mis transistor ptt 2 accordingly turns “ on ,” the condition is maintained in which the n channel mis transistor ntt 1 supplies the output voltage v int potential and the n channel mis transistor ntt 2 supplies the output voltage v int potential . at this time , the voltage on the drain ( node n 6 ) side of the n channel mis transistor ntt 1 rises , and therefore the output voltage ( gate voltage ) v g is likely to rise due to the coupling capacitance of the n channel mis transistor ntt 1 . however , in the gate voltage stabilizing circuit 3 , the control signal sg 3 changes from “ low ” level to “ high ” level to turn the n channel mis transistor nt 41 “ on ,” and the control signal sg 4 changes from “ high ” level to “ low ” level to turn the n channel mis transistor nt 42 “ off ”. accordingly , charges flow from the node n 5 ( output voltage ( gate voltage ) v g ) to the capacitor c 3 via the n channel mis transistor nt 41 and are accumulated . for this reason , the gate voltage stabilizing circuit 3 functions to lower the gate voltage v g to be applied to the gate of the n channel mis transistor ntt 1 and to suppress a rise of the output voltage ( gate voltage ) v g . in addition , the gate voltage stabilizing circuit 4 is in the same condition as in the standby state . next , when the standby state changes to the active state and after a predetermined period elapses ( period ( a )), the control signal is “ low ” to turn the p channel mis transistor ptt 2 “ on ,” and therefore both the n channel mis transistor ntt 1 and the n channel mis transistor ntt 2 supply the output voltage v int potential . in the gate voltage stabilizing circuit 3 , since the control signal sg 3 changes from “ high ” level to “ low ” level to turn the n channel mis transistor nt 41 “ off ,” and the control signal sg 4 changes from “ low ” level to “ high ” level to turn the n channel mis transistor nt 41 “ on ,” the charges accumulated in the capacitor c 3 are discharged to the low potential side power source v ss . in the gate voltage stabilizing circuit 4 , since the control signal sg 5 keeps “ high ” level to cause the p channel mis transistor pt 41 to be “ off ,” the control signal sg 6 keeps “ low ” level to cause the p channel mis transistor pt 42 to continue to be “ on ,” the condition continues in which there is no potential difference between both ends of the capacitor c 4 . then , immediately after the active state changes to the standby state ( period ( c )), since the control signal vpg changes from “ low ” level to “ high ” level to turn the p channel mis transistor ptt 2 “ off ,” the n channel mis transistor ntt 1 no longer supplies the output voltage v int potential . meanwhile , the n channel mis transistor ntt 2 supplies the output voltage v int potential . at this time , the voltage on the drain ( the node n 6 ) side of the n channel mis transistor ntt 1 lowers , and the output voltage ( gate voltage ) v g is likely to lower due to the coupling capacitance of the n channel mis transistor ntt 1 . in the gate voltage stabilizing circuit 4 , however , since the control signal sg 5 changes from “ high ” level to “ low ” level to switch the p channel mis transistor pt 41 from “ off ” to “ on ,” and the control signal sg 6 changes from “ low ” level to “ high ” level to switch the p channel mis transistor pt 42 from “ on ” to “ off ,” charges accumulated in the capacitor c 4 are discharged to the node n 5 ( output voltage ( gate voltage ) v g ). for this reason , the gate voltage stabilizing circuit 4 functions to increase the gate voltage v g to be applied to the gate of the n channel mis transistor ntt 1 , and to suppress a drop of the output voltage ( gate voltage ) v g . in addition , the gate voltage stabilizing circuit 3 maintains the previous condition . next , when the active state changes to the standby state , and after a predetermined period elapses ( period ( c )), which are not illustrated , the gate voltage stabilizing circuit 4 is set to the same condition as in the standby state of the period ( a ). thus , while an increase is suppressed in the capacitance of the capacitor c 1 mounted ( on - chip ) in a semiconductor integrated circuit where the voltage generating circuit 30 a is provided , a fluctuation can be suppressed in the output voltage ( gate voltage ) v g to be generated when the standby state changes to the active state or when the active state changes to the standby state . as descried above , in the voltage generating circuit of this embodiment , there are provided the differential amplifier circuit 1 , the gate voltage stabilizing circuit 3 , the gate voltage stabilizing circuit 4 , the n channel mis transistor nt 1 , the n channel mis transistor nt 2 , the n channel mis transistors nt 11 to nt 13 , the n channel mis transistor ntt 1 , the n channel mis transistor ntt 2 , the p channel mis transistors pt 11 to pt 13 , the p channel mis transistor ptt 1 , the p channel mis transistor ptt 2 , the resistances r a1 to r a4 , the resistances r s1 to r s4 , and the capacitor c 1 . the gate voltage stabilizing circuit 3 is provided with the capacitor 3 , the n channel mis transistor nt 41 , and the n channel mis transistor nt 42 . the gate voltage stabilizing circuit 3 suppresses a change in the gate voltage of the step - down transistor when the standby state changes to the active state . the gate voltage stabilizing circuit 4 is provided with the capacitor c 4 , the p channel mis transistor pt 41 , and the p channel mis transistor pt 42 . the gate voltage stabilizing circuit 4 suppresses a change in the gate voltage of the step - down transistor when the active state changes to the standby state . thus , while an increase is suppressed in the capacitance of the capacitor c 1 mounted ( on - chip ) in a semiconductor integrated circuit where the voltage generating circuit 30 a is provided , a fluctuation can be suppressed in the output voltage ( gate voltage ) v g to be generated when the standby state changes to active state or when active state changes to the standby state . thereby , the output voltage v int can be outputted as an internal supply voltage that has been stably stepped down . a voltage generating circuit according to an embodiment 3 of the present invention will be described hereinafter with reference to the accompanying drawing . fig9 is a circuit diagram showing a configuration of a voltage generating circuit . fig1 is a circuit diagram showing a gate voltage stabilizing circuit on the high pressure side power source side . in this embodiment , there are provided a gate voltage stabilizing circuit that suppresses a change in the gate voltage of the step - down transistor when a standby state changes to an active state , and a gate voltage stabilizing circuit that suppresses a change in the gate voltage of the step - down transistor when the active state changes to the standby state . hereinbelow , same symbols are assigned to components identical to those in the embodiment 1 , a description of which is omitted , and only different parts will be described . as shown in fig9 , the voltage generating circuit 30 b is provided with the differential amplifier circuit 1 , a gate voltage stabilizing circuit 3 a , a gate voltage stabilizing circuit 4 a , the n channel mis transistor nt 1 , the n channel mis transistor nt 2 , the n channel mis transistors nt 11 to nt 13 , the n channel mis transistor ntt 1 , the n channel mis transistor ntt 2 , the p channel mis transistors pt 11 to pt 13 , the p channel mis transistor ptt 1 , the p channel mis transistor ptt 2 , the resistances r a1 to r a4 , the resistances r s1 to r s4 , and the capacitor c 1 . the voltage generating circuit 30 b is provided inside a semiconductor chip as a semiconductor storage , for example . the voltage generating circuit 30 b receives input of a high potential side power source v dd voltage as an external supply voltage and a high potential side power source v pp voltage as a supply voltage for stepping up a word line voltage , and outputs an output voltage v int as a stepped - down internal supply voltage to unillustrated various circuits provided in the semiconductor chip . as shown in fig1 , the gate voltage stabilizing circuit 3 a is provided with an n channel mis transistor nt 51 and a resistance r 1 . the gate voltage stabilizing circuit 3 a has a function to suppress a change in the gate voltage of the step - down transistor when the standby state changes to the active state . in the n channel mis transistor nt 51 , a drain is connected to a node n 5 ( output voltage ( gate voltage ) v g ), and a control signal sg 7 is inputted into a gate . the resistance r 1 is connected to a source of the n channel mis transistor nt 51 and the other end is connected to the low potential side power source v ss . when the standby state changes to the active state , the n channel mis transistor ntt 1 that is a step - down transistor supplies the output voltage v int potential , and then the output voltage ( gate voltage ) v g is likely to rise , a control signal having a pulse waveform is inputted into the gate of the n channel mis transistor nt 51 . when the control signal sg 7 in a pulse waveform is at “ high ” level , the n channel mis transistor nt 51 turns “ on ” and functions to suppress a rise of the output voltage ( gate voltage ) v g by drawing out extra charges to be accumulated on the gate of the n channel mis transistor ntt 1 to the low potential side power source v ss through the resistance r 1 . here , the control signal sg 7 sets a duty ratio and an application period of the pulsed waveform so as not to excessively draw the charges to be accumulated on the gate of the n channel mis transistor ntt 1 . as shown in fig1 , a p channel mis transistor pt 51 and a resistance r 2 are provided in the gate voltage stabilizing circuit 4 a . the gate voltage stabilizing circuit 4 a has a function to suppress a change in the gate voltage of a step - down transistor when the active state changes to the standby state . one end of the resistance r 2 is connected to the high potential side power source v dd and the other end is connected to a source of the p channel mis transistor pt 51 . in the p channel mis transistor pt 51 , a control signal sg 8 is inputted into a gate and a drain is connected to the node ns ( output voltage ( gate voltage ) v g . when the active state changes to the standby state , the n channel mis transistor ntt 1 that is a step - down transistor turns “ off ,” and the output voltage ( gate voltage ) v g is likely to lower , the control signal sg 8 having a pulse waveform is inputted into the gate of the p channel mis transistor pt 51 . when the pulsed control signal sg 8 is at “ low ” level , the p channel mis transistor pt 51 turns “ on ” and functions to supply charges to the gate of the n channel mis transistor ntt 1 via the resistance r 2 and to suppress a drop of the output voltage ( gate voltage ) v g . here , the control signal sg 8 sets a duty ratio and an application period of the pulse waveform so as not to supply excessive charges to the gate of the n channel mis transistor ntt 1 . next , operation of the voltage generating circuit will be described with reference to fig1 . fig1 is a drawing showing the operation of the voltage generating circuit . here , the operation of the voltage generating circuit is divided into the following 3 periods and described : ( a ) a period of a standby state ( including time to change to an active state ), ( b ) a period of the active state , and ( c ) a period after the active state changes to the standby state . as shown in fig1 , in the voltage generating circuit 30 b , first in the standby state ( period ( a )), since the p channel mis transistor ptt 2 is “ off ” with the control signal vpg at “ high ” level , the n channel mis transistor ntt 1 does not supply the output voltage v int potential , while the n channel mis transistor ntt 2 supplies the output voltage v int potential . in the gate voltage stabilizing circuit 3 a , the control signal sg 7 is at “ low ” level , and therefore the n channel mis transistor nt 51 is “ off ”. thus , there is no exchange of a charge between the low potential side power source v ss side and the node n 5 ( output voltage ( gate voltage ) v g ) via the resistance r 1 . in the gate voltage stabilizing circuit 4 a , the control signal sg 8 is at “ high ” level , and therefore the p channel mis transistor pt 51 is “ off ”. thus , there is no exchange of a charge between the high potential side power source v dd side and the node n 5 ( output voltage ( gate voltage ) v g ) via the resistance r 2 . next , immediately after the standby state changes to the active state ( period ( a )), as the control signal vpg changes from “ high ” level to “ low ” level and the p channel mis transistor ptt 2 accordingly turns “ on ,” the condition is maintained in which the n channel mis transistor ntt 1 supplies the output voltage v int potential , and the n channel mis transistor ntt 2 supplies the output voltage v int potential . at this time , the voltage on the drain ( the node n 6 ) side of the n channel mis transistor ntt 1 rises , and therefore the output voltage ( gate voltage ) v g is likely to rise due to the coupling capacitance of the n channel mis transistor ntt 1 . in the gate voltage stabilizing circuit 3 a , however , since the control signal sg 7 changes from “ low ” level to “ high ” level to turn the n channel mis transistor nt 51 “ on ,” charges flow from the node n 5 ( output voltage ( gate voltage ) v g ) to the low potential side power source v ss side through the n channel mis transistor nt 51 and the resistance r 1 . thus , the gate voltage stabilizing circuit 3 a functions to lower the gate voltage v g to be applied to the gate of the n channel mis transistor ntt 1 and to suppress a rise in the output voltage ( gate voltage ) v g . in addition , the gate voltage stabilizing circuit 4 a is in the same condition as in the standby state . then , when the standby state changes to the active state and after a predetermined period elapses ( period ( a )), the control signal sg 7 is at “ low ,” and therefore the n channel mis transistor nt 51 turns “ off ”. accordingly , there will be no longer exchange of a charge between the low potential side power source v ss side and the node n 5 ( the output voltage ( gate voltage ) v g ) through the resistance r 1 . in the gate voltage stabilizing circuit 4 a , the control signal sg 8 remains at “ high ,” and therefore the p channel mis transistor pt 51 remains to be “ off ”. accordingly , there is no exchange of a charge between the high potential side power source v dd side and the node n 5 ( output voltage ( gate voltage ) v g ) through the resistance r 2 . then , immediately after the active state changes to the standby state ( period ( c )), the control signal vpg changes from “ high ” level to “ low ” level , and therefore the p channel mis transistor ptt 2 turns “ off ”. accordingly , the n channel mis transistor ntt 1 no longer supplies the output voltage v int potential , while the n channel mis transistor ntt 2 supplies the output voltage v int potential . then , the voltage on the drain ( the node n 6 ) side of the n channel mis transistor ntt 1 lowers , and the output voltage ( gate voltage ) v g is likely to lower due to the coupling capacitance of the n channel mis transistor ntt 1 . in the gate voltage stabilizing circuit 4 a , however , since the control signal sg 8 changes from “ high ” level to “ low ” level to switch the p channel mis transistor pt 51 from “ off ” to “ on ,” charges flow from the high potential side power source v dd side to the node n 5 ( output voltage ( gate voltage ) v g ) through the p channel mis transistor pt 51 and the resistance r 2 . for this reason , the gate voltage stabilizing circuit 4 a functions to raise the gate voltage v g to be applied to the gate of the n channel mis transistor ntt 1 and to suppress a drop of the output voltage ( gate voltage ) v g . in addition , the gate voltage stabilizing circuit 3 a maintains the previous condition . next , when the active state changes to the standby state and after a predetermined period elapses ( period ( c )), which is not unillustrated , the gate voltage stabilizing circuit 3 a is set identical to the standby state . thus , while an increase is suppressed in the capacitance of the capacitor c 1 mounted ( on - chip ) in a semiconductor integrated circuit where the voltage generating circuit 30 b is provided , a fluctuation can be suppressed in the output voltage ( gate voltage ) v g to be generated when the standby state changes to the active state or when the active state changes to the standby state . as described above , in the voltage generating circuit of the present embodiment , there are provided the differential amplifier circuit 1 , the gate voltage stabilizing circuit 3 a , the gate voltage stabilizing circuit 4 a , the n channel mis transistor nt 1 , the n channel mis transistor nt 2 , the n channel mis transistors nt 11 to nt 13 , the n channel mis transistor ntt 1 , then the n channel mis transistor ntt 2 , the p channel mis transistors pt 11 to pt 13 , the p channel mis transistor ptt 1 , the p channel mis transistor ptt 2 , the resistance r a1 to r a4 , the resistance r s1 to r s4 , and the capacitor c 1 . the n channel mis transistor nt 51 and the resistance r 1 are provided in the gate voltage stabilizing circuit 3 a . the gate voltage stabilizing circuit 3 a suppresses a change in the gate voltage of the step - down transistor when the standby state changes to the active state based on the control signal sg 7 having a pulse waveform . the p channel mis transistor pt 51 and the resistance r 2 are provided in the gate voltage stabilizing circuit 4 a . the gate voltage stabilizing circuit 4 a suppresses a change in the gate voltage of the step - down transistor when the active state changes to the standby state based on the control signal sg 8 having a pulse waveform . thus , while an increase is suppressed in the capacitance of the capacitor c 1 mounted ( on - chip ) in a semiconductor integrated circuit where the voltage generating circuit 30 b is provided , a fluctuation can be suppressed in the output voltage ( gate voltage ) v g to be generated when the standby state changes to the active state or when the active state changes to the standby state . thereby , the output voltage v int can be outputted as a stable stepped - down internal supply voltage . in addition , since a fluctuation in the output voltage ( gate voltage ) v g is suppressed by using the control signals sg 7 and sg 8 that have pulse waveforms , excessive drawing or supply of charges can be suppressed . the present invention is not limited to the embodiments described above , and various changes may be made therein without departing from the scope of the invention . although a voltage generating circuit is used as a step - down power source for a semiconductor memory , for example , the voltage generating circuit may also be used as a step - down power source for a system on a chip ( soc ), an analog or digital lsi or the like . in addition , although a high potential side power source v dd voltage as an external supply voltage is directly supplied to the source of the p channel mis transistor ptt 2 and the drain of the n channel mis transistor ntt 2 in the voltage generating circuit , an rc circuit for suppressing a fluctuation in the high potential side power source v dd voltage may be provided between the high potential side power source v dd and the source of the p channel mis transistor ptt 2 , and between the high potential side power source v dd and the n channel mis transistor ntt 2 .