in the following description , similar reference numerals refer to same or similar devices / components . a person of ordinary skill in the art may make embodiments utilizing same or similar methods / architectures according to disclosure / teaching of the present invention , so repeated description is not provided . an embodiment provides an smps , of which when ocp / olp is triggered , maximum output current / power is independent of input voltage and conduction modes . please refer to booster 10 of fig1 . power p transferred to load capacitor 20 by inductor 12 may be expressed as follows : p = ½ * l * ( i 2 cs - peak − i 2 cs - ini )* f sw ( 1 ) where l represents inductance of inductor 12 , i cs - peak represents peak value of inductor current flowing through inductor 12 ( which is also peak value of current flowing through switch 14 ), i cs - ini represents initial inductor current flowing through inductor 12 ( which is also initial current flowing through switch 14 ) each time switch 14 turns on , and f sw represents switching frequency of switch 14 . in dcm operation , i cs - ini is 0 amps ; in ccm operation , i cs - ini is greater than 0 amps . the right half of equation ( 1 ) should be a fixed value because maximum output power p olp is a fixed value when olp is triggered . the right half of equation ( 1 ) should be a fixed value for ocp as well , because maximum output current c ocp is a fixed value when ocp is triggered , assuming output voltage v out is kept at a fixed voltage level . assuming switching frequency f sw of booster 10 does not change , a part in equation ( 1 ), when olp / ocp is triggered , can be rewritten as : i 2 cs - peak − i 2 cs - ini = 4 * i cs - avg *( i cs - peak − i cs - avg )= k 1 ( 2 ) where i cs - avg represents ½ *( i cs - peak + i cs - ini ), which may also represent average inductor current flowing through switch 14 when switch 14 is turned on ; k 1 is a constant , too . where k is a constant , v cs - peak and v cs - avg represent voltage levels of current sensing signal v cs corresponding to inductor currents i cs - peak and i cs - avg , respectively . when ocp / olp occurs , as long as v cs - peak and v cs - avg meet the requirement of equation ( 3 ), maximum output current / power defined by ocp / olp approximates a fixed value . fig3 is a graph illustrating relationship between v cs - peak and v cs - avg of equation ( 3 ). two dashed lines represent v cs - peak = v cs - avg and v cs - peak = k / v cs - avg , respectively . for example , if booster 10 is designed to operate in dcm , v cs - peak of 0 . 9 volts should trigger ocp / olp , meaning v cs - avg is 0 . 45 volts , and k should be 0 . 45 * 0 . 45 volts 2 . solid curve of fig3 represents relationship between v cs - peak and v cs - avg when ocp / olp is triggered . thus , as long as v cs - peak and v cs - avg of any switching cycle are known , and are substituted into equation ( 3 ) for calculation , it may be determined whether output current / power is greater or less than maximum output current / power defined by ocp / olp , thereby updating limiting signal v cs - limit . after a few switching cycles , output current / power of every switching cycle will be approximately a fixed value , which is maximum output current / power defined by ocp / olp . fig4 is a diagram illustrating controller 18 b that may be utilized with booster 10 of fig1 according to an embodiment , and may be utilized with other types of smps . gate controller 34 receives signals from other signal processor 32 and signal delay compensator 51 for driving switch 14 . signal delay compensator 51 may approximately compensate signal delay effect , making peak value v cs - peak of current sensing signal v cs almost equal to limiting signal v cs - limit . thus , limiting signal v cs - limit may be seen as peak value v cs - peak of current sensing signal in any switching cycle . converter 56 approximately takes limiting signal v cs - limit as an input , and outputs expected average inductor current signal v cs - avg - exp according to relationship between v cs - peak and v cs - avg ( which may be obtained through simplification of solid line in fig3 ). average current comparator 52 compares average current v cs - avg - real ( which is the average of v cs when switch 14 is turned on ) and expected average inductor current signal v cs - avg - exp . output of average current comparator 52 causes modifier 54 to modify limiting signal v cs - limit . clamp 59 is utilized for limiting maximum and minimum of limiting signal v cs - limit . it can be seen from fig4 that converter 56 , average current comparator 52 , and modifier 54 substantially form a closed loop . after multiple switching cycles , relationship between v cs - peak and v cs - avg approaches solid line of fig3 or a corresponding segment thereof , such that operation of the loop causes maximum output current / power defined by ocp / olp to become a fixed value . signal delay compensator 51 , converter 56 , and average current comparator 52 , and modifier 54 may be seen as a regulator that modifies limiting signal v cs - limit to cause peak value v cs - peak and average current v cs - avg - real corresponding to current sensing signal v cs - limit to approach predetermined relationship in fig3 with progression of switching cycles . for example , when expected average inductor current signal v cs - avg - exp is lower than average current v cs - avg - real , limiting signal v cs - limit increases in the next switching cycle . thus , expected average inductor current signal v cs - avg - exp approaches average current v cs - avg - real in the next switching cycle . fig5 a and fig5 b illustrate two types of signal delay compensator 51 a and 51 b that may be utilized with fig4 . in fig5 a , signal delay compensator 51 a primarily comprises comparators 502 , 504 , capacitor 508 , current sources i r , i l , and resistors r b , r bias1 . if peak value v cs - peak of current sensing signal v cs is greater than limiting signal v cs - limit comparator 504 causes current source i r to charge capacitor 508 and pull up capacitor voltage v bias . if peak value v cs - peak of current sensing signal v cs is less than limiting signal v cs - limit current source i l slowly discharges capacitor 508 and pull down capacitor voltage v bias . current source i l must be much smaller than current source i r . voltage v bias1 is generated across resistor r bias1 as capacitor voltage v bias is converted into current i bias through resistor r b and current mirrors 506 , 507 , thereby providing a lower limiting signal v cs - limit - lower lower than limiting signal v cs - limit . output signal of comparator 502 turns off switch 14 when current sensing signal v cs is greater than lower limiting signal v cs - limit - lower . after multiple switching cycles , capacitor voltage v bias is held at approximately a fixed value , making comparator 502 early send signal when current sensing signal v cs equals lower limiting signal v cs - limit - lower finally causing peak value v cs - peak of current sensing signal v cs to equal limiting signal v cs - limit . current source i l may be optional if self - leakage of capacitor 508 , or junction leakage , is utilized to pull down capacitor voltage v bias slowly . signal delay compensator 51 b of fig5 b may also cause peak value v cs - peak of current sensing signal v cs to equal limiting signal v cs - limit . different from generation of lower limiting signal v cs - limit - lower in fig5 a , fig5 b shows generating higher current sensing signal v cs - higher . other circuit architecture and operating principles of fig5 b are same or similar to fig5 a , and can be derived from fig5 a by persons skilled in the art . fig6 illustrates average current comparator 52 a , modifier 54 a , and clamp 59 a , which may be utilized with fig4 . it can be seen from variation in output voltage v m of average current comparator 52 a whether average current v cs - avg - real ( average of current sensing signal v cs ) is greater than or less than expected average inductor current signal v cs - avg - exp . current source 362 provides fixed current i con to charge capacitor 366 when current sensing signal v cs is greater than expected average inductor current signal v cs - avg - exp . current source 364 provides fixed current i con to discharge capacitor 366 when current sensing signal v cs is less than expected average inductor current signal v cs - avg - exp . current sensing signal v cs increases linearly , so output voltage v m increases if average current v cs - avg - real is greater than expected average inductor current signal v cs - avg - exp when gate signal gate causes switch 14 to turn on . output voltage v m decreases if average current v cs - avg - real is relatively small . modifier 54 a updates limiting signal v cs - limit according to output voltage v m when gate - bar signal gate causes switch 14 to turn off . to prevent over voltage or under voltage , clamp 59 a utilizes two diodes to force voltage level of limiting signal v cs - limit between top limit v cs - limit - top and bottom limit v cs - limit - bottom . fig7 illustrates , in the left side , the relationship of limiting signal v cs - limit and expected average inductor current signal v cs - avg - exp , namely the relationship of v cs - peak and v cs - avg of fig3 ; and , in the right side , a simplification result thereof . the relationship of v cs - peak and v cs - avg in fig3 is a curve , circuit implementation of which may be relatively complicated . thus , the curve in fig3 may be represented as a single line segment or a piecewise linear curve . a signal straight line is a simplest method for representing upper half of the curve , as shown by line l in the right side of fig7 . lower half of the curve may be omitted , as such conditions do not arise in practical operation . line l in fig7 ( right ) may be realized by multiple different types of circuits . for example , as shown in fig8 , a simple operational amplifier together with resistors r 1 and r 2 may realize line l , acting as a converter 56 a for use in controller 18 b of fig4 . fig9 illustrates a controller 18 c according to an embodiment , which may be utilized with booster 10 of fig1 , and is suitable for use with other types of smps . fig9 does not include signal delay compensator 51 of fig4 , utilizing only comparator 36 to replace signal delay compensator 51 so as to expect peak value v cs - peak of current sensing signal vcs not to be greater than limiting signal v cs - limit . as described above , due to signal delay , such an architecture causes peak value v cs - peak to approach but exceed limiting signal v cs - limit . in fig9 , peak value detector 61 is utilized for detecting peak value v cs - peak . converter 57 takes peak value v cs - peak as input , and outputs expected average inductor current signal v cs - avg - exp roughly based on relationship between v cs - peak and v cs - avg ( which could be obtained from the simplification of solid curve in fig3 ). fig9 also includes a closed loop , substantially formed by peak value detector 61 , converter 57 , average current comparator 52 , modifier 54 , comparator 36 , gate controller 34 , switch 14 , and sense resistor 22 . after multiple switching cycles , relationship between v cs - peak and v cs - avg approaches solid line or a corresponding segment thereof in fig3 , such that operation of the loop causes maximum output current / power defined by ocp / olp to become a fixed value . peak value detector 61 , converter 57 , and average current comparator 52 , and modifier 54 can be seen as another adjusting module for adjusting limiting signal v cs - limit to cause peak value v cs - peak and average current v cs - avg - real corresponding to current sensing signal v cs to approach predetermined relationship in fig3 along with progression of switching cycles . fig1 illustrates one example of a peak value detector 61 a . a capacitor thereof may store peak value v cs - peak . fig1 illustrates simplified relationship of v cs - peak and v cs - avg for causing maximum output current / power defined by ocp / olp to become a fixed value . fig1 illustrates a converter 57 a for realizing relationship in fig1 , and usable in fig9 . those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention .