embodiments of the present invention are now described with reference to the accompanying drawings . fig1 is a block diagram showing an embodiment of the present invention . in fig1 a control lsi circuit 1 comprises a priority control circuit 4 for receiving memory request signals , a memory timing control circuit 5 for generating various timing signals , an address register 6 for holding an address signal from a request source , and a selector circuit 7 for switching a row address and a column address supplied to a dynamic random access ( dram ) memory 3 . further , a data lsi circuit 2 comprises a write data register 8 for holding write data , an ecc generation circuit 9 for generating an error check code ( ecc ) for the write data , an ecc correction and detection circuit 11 for detecting and correcting an error in a read - out data , and a read data register 10 for temporarily holding the read - out data . operation of the lsi circuits is now described . the control lsi circuit 1 receives memory request signals 12 ( req - 0 , . . . , req - n ) from external processing units , input / output units and the like ( not shown ) through the priority control circuit 4 . when a plurality of request signals req - 0 - req - n are supplied to the priority control circuit 4 simultaneously , the priority control circuit 4 selects a request signal having the highest priority and returns a reception signal to the request source which has issued the request signal while a start signal 20 is supplied to the memory timing control circuit 5 simultaneously . the memory timing control circuit 5 produces , in response to the start signal 20 from the priority control circuit 4 , an ras ( row addresss strobe ) signal 17 , a cas ( column address strobe ) signal 18 and a we ( write enable ) signal 19 which are control signals for the dram 3 , an address latch signal 21 and a row address selection signal 22 supplied to the address register 6 and the selector circuit 7 , respectively , in the control lsi circuit 1 and a write data latch signal 23 and a read data latch signal 24 supplied to the write data register 8 and the read data register 10 , respectively , in the data lsi circuit 2 . a request address signal 13 supplied from the request source is held in the address register 6 in response to the address latch signal 21 from the memory timing control circuit 5 . the request address signal held in the address register 6 is supplied to the selector circuit 7 so that a row address signal and a column address signal are selected from the request address signal in the selector circuit 7 and are supplied to the memory 3 as a memory address signal 16 . switching of the row address signal and the column address signal is made in response to the row address selection signal 22 from the memory timing control circuit 5 . the foregoing operation is a common procedure to the reading and the writing operation of data . on the other hand , the data lsi circuit 2 receives a write data signal 14 from the request source in the write data register 8 in response to the write data latch signal 23 from the control lsi circuit 1 in the case where the data is written into the memory . the error check code ( ecc ) generation circuit 9 generates an ecc for the write data and the circuit 9 supplies the write data with the ecc added as a memory data signal 15 to the dram 3 . further , in the case where data is read out of the memory , a memory data signal 15 read out of the dram 3 is subjected to the error detection and correction in the ecc correction and detection circuit 11 . the read data is held in the read data register 10 in response to the read data latch signal 24 from the control lsi circuit 1 and is returned as the read data signal 14 to the request source . the ecc generation circuit 9 and the ecc correction and detection circuit 11 can utilize a known circuit configuration . fig2 is a circuit diagram of an output route in the lsi circuit 1 . fig2 shows a circuit of an output route for the memory address signal 16 and fig3 shows a circuit of an output route for the ras signal . in fig2 flip - flops 31 and 32 generate the row address signal and the column address signal , respectively . an and / or gate 33 selects one of the row and column address signals in response to a row address selection signal 22 and is produced through a buffer 34 as the memory address signal 16 . further , in fig3 a flip - flop 35 generates the ras signal , which is produced through an and / or gate 36 and a buffer 37 as the ras signal 17 . in the output circuit shown in fig2 and 3 , it is assumed that the delay time of the propagation of signals in the gate can be neglected and when the delay times of the and / or gate 33 and the buffer 34 are t a and t b , respectively , the delay time of the row address signal until it is produced as the memory address signal 16 after being selected by the row address selection signal is equal to a sum of the delay times t a and t b , that is , t 1 + t b . further , when the delay times of the and / or gate 36 and the buffer 37 are t c and t d , respectively , the delay time of the ras signal until being produced from the buffer 37 after it is set in the flip - flop 35 is equal to a sum of the delay times t c and t d , that is , t c + t d . if the and / or gates 33 and 36 and the buffers 34 and 37 are constituted of gates of the same type , the delay times t a and t b are equal to the delay times t c and t d , respectively , that is , t a = t c and t b = t d so that the delay time of the row address signal until it is produced from the buffer 34 after being selected by the row address selection signal is equal to the delay time of the ras signal until it is produced from the buffer 37 after being set in the flip - flop 35 . since a lower and gate of the and / or gate 36 in fig3 is a dummy gate and is always supplied at its one input with &# 34 ; 0 &# 34 ; level signal , the lower and gate is not essential . however , the lower and gate is provided purposely in order for the delay time of the and / or gate 36 to be equal to that of the and / or gate 33 . a severe time relation is required between the row address signal and the ras signal . to meet this time relation requirement , when the gate circuits shown in fig2 and 3 are constituted of gates 33 and 36 of a same type , a timing between both of the signals can be set without considering a difference between the delay times , since there is no difference in the delay times of the gates . as described above , the delay time of signals required for generation of the control signals for controlling the dram such as the start signal 20 , the address latch signal 21 , the row address selection signal 24 and the like can be only the propagation delay time in the lsi circuit by incorporating the priority control circuit 4 , the memory timing control circuit 5 , the address register 6 and the selector circuit 7 into the same lsi circuit . accordingly , the delay time of the signals propagated between the lsi circuits can be removed so that reduction of the access time and reception of the request signal in a short cycle pitch can be attained . further , the output routes for the control signals such as the row address signal and the ras signal and the column address signal and the cas signal which require a severe time relation can be constituted of gates of the same type , so that the timing between the control signals can be set without considering the delay time of the signals in the gates to thereby reduce the access time . referring now to fig4 and 5 , expansion of the memory system according to the present invention is described . in order to increase a memory capacity and the throughput of the memory system , when the number of memory banks is increased , the memory system can be configured as shown in fig4 for example . in fig4 a control lsi circuit 41 generates control signals 44 required for the memory control and control signals 45 required for control of the data lsi circuits 42a and 42b . with the control signals 44 and 45 , since an increase of signal lines due to an increase of the number of banks is relatively small , it is easy to generate control signals of two kinds by the single control lsi circuit . on the other hand , the number of signal lines for data is many and the number of pins of the lsi circuit must be greatly increased in order to control data of two kinds by the single data lsi circuit . accordingly , since it is difficult to constitute the data lsi circuit by a mass - produced gate array , the single data lsi circuit controls data for a single memory bank . in fig4 the data lsi circuit 42a controls the memory bank 43a and the data lsi circuit 42b controls the memory bank 43b . fig5 shows a further expansion of the memory system shown in fig4 . in fig5 a control lsi circuit 51a controls data lsi circuits 52a and 52b and memory banks 53a and 53b , and a control lsi circuit 51b controls data lsi circuits 52c and 52d and memory banks 53c and 53d , so that a memory system including four memory banks is configured . further , in the memory system of fig5 the request signals from the request source are received by the control lsi circuit 51a collectively and a start signal 54 which is a trigger signal for generation of the control signals is transmitted to the control lsi circuit 51b . in the embodiment illustrated in fig5 each of the control lsi circuits 51a and 51b possesses the function of controlling two memory banks and each of the data lsi circuits 52a , 52b , 52c and 52d possesses the function of processing data for one memory bank . accordingly , for example , if a width of data is 32 bits and a width of address on the side of the request is 31 bits , each of the control lsi circuit 51a and 51b requires 31 pins for interfacing with an address bus and 13 pins in total of 10 pins for a memory address and 3 pins one for each of the ras , cas and we signals for one memory bank when the control lsi circuit interfaces with a dram having the memory capacity of one megabits , and the control lsi circuit can be incorporated into an lsi circuit having about 100 pins even if other pins such as a request pin and the like are included . further , each of the data lsi circuits 52a to 52d requires 32 pins for interfacing with a data bus and 39 pins for interfacing with the dram ( 32 bits for data plus 7 bits for ecc ) and can be incorporated into an lsi circuit having about 100 pins in total in the same manner as the control lsi circuit . in this manner , by constituting the control circuit of the dram by the lsi circuits divided into the control and data lsi circuits , the number of pins of the lsi circuits can be distributed to both of the lsi circuits with balance , so that a memory system having good expandability can be attained . in the embodiment , the foregoing description has been made to the case where the control lsi circuit possesses the function of controlling two memory banks and the data lsi circuit possesses the function of processing data for one memory bank . however , the present invention is not limited thereto and the number of memory banks capable of being handled by each of the lsi circuits may be changed within the range of the number of gates or pins of the lsi circuit . according to the present invention , since the skew due to a difference of the delay time between the control signals for the dram can be made small , a high performance memory system having a reduced cycle time may be provided . further , the number of pins for the lsi circuits can be distributed properly by the division of the lsi circuit to the control and data lsi circuits and a low - cost dram control lsi circuit can be provided which is capable of utilizing a mass - produced gate array . a combination of a plurality of control and data lsi circuits can increase the memory banks easily and a memory system having a high expandability can be provided .