a flow to design a near / sub - threshold solution asic using software programmable adaptive dynamic voltage control ( advc ) to improve the device power performance and to ensure optimal energy per operation for a given required speed or target operation . in the following description , numerous specific details are set forth . however , it is understood that embodiments of the invention may be practiced without these specific details . in other instances , well - known circuits , structures and techniques have not been shown in detail in order not to obscure the understanding of this description . reference throughout the specification to “ one embodiment ” or “ an embodiment ” means that a particular feature , structure , or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention . thus , the appearance of the phrases “ in one embodiment ” or “ in an embodiment ” in various places throughout the specification are not necessarily all referring to the same embodiment . furthermore , the particular features , structures , or characteristics may be combined in any suitable manner in one or more embodiments . moreover , inventive aspects lie in less than all features of a single disclosed embodiment . thus , the claims following the detailed description are hereby expressly incorporated into this detailed description , with each claim standing on its own as a separate embodiment of this invention . for one embodiment of the invention , the implementation may be effected using software control on the operating voltage to improve the device power per given performance . by increasing the operating voltage , the performance increases exponentially while the dynamic power increase only by the power of two . however , the adaptive dynamic voltage control ( advc ) algorithm defines the operating voltage to be the lowest possible voltage at which the device operates correctly . for another embodiment of the invention , the decision on the correct operating voltage for the device is done using different sensors which exist inside the silicon such as temperature sensors or process monitor sensors or other unique sensors as shown at fig1 block 104 and also a first fail circuit as shown at fig1 block 102 and a software algorithm that checks both sensors output and also the performance of the first fail circuits which are built to be the worst case path of the logic design per a specific device . the first fail circuit is connected to a different power source which can also be controlled by the software without influencing the rest of the logic voltage , the software changes this voltage level up and down until the first fail circuit goes from non - functional state to functional state and utilizes this information to know the lowest optimal voltage which is needed for the design to operate correctly . for another embodiment of the invention , the implementation uses an exemplary circuit of a power management unit ( pmu ) block . this block includes a programmable dc2dc block ( item 100 in fig1 ) which generates the required voltage to operate the digital logic of the device from the battery input , a programmable ldo block ( item 101 in fig1 ) which generates the required voltage for the first fail circuits from the battery input . the implementation also includes a cpu block ( item 103 in fig1 ) which runs the advc software algorithm that controls the different blocks inside the pmu , reads the on chip sensors and operates the first fail circuit to determine the correct operational voltage level for another embodiment of the invention , the implementation includes a software algorithm for adaptive dynamic voltage control ( advc ) that calculates the optimal voltage to be used for the design per a given required frequency as shown in fig2 . the process shown in fig2 begins with reset or wake - up of the cpu ( box 200 in fig2 ) which reads the target speed from the flash or gets it from the higher level software ( box 201 in fig2 ). then the cpu powers - up the different sensors inside the device ( box 202 in fig2 ) and reads different sensors data ( box 203 in fig2 ). from the data that was read from the different sensors the cpu calculates the target operating voltage per the given target frequency ( box 204 in fig2 ). the cpu then sets the initial voltage for the first fail circuit to give the target voltage as was calculated ( box 205 in fig2 ). then the cpu checks the correct operation of the first fail circuit ( box 206 in fig2 ). if the first fail circuit fails to operate correctly , then the cpu sets the fail register and increases the first fail voltage output by a small increment for ( box 207 in fig2 ). then the cpu checks again the operation of the first fail circuit and if again it &# 39 ; s not working correctly it raises the voltage of the first fail by another small increment . the cpu continues with this loop until it gets the first fail circuit to work correctly . when the first fail circuit works correctly the cpu checks if the fail flag equals 1 ( box 208 in fig2 ), if not then the cpu knows the first fail logic didn &# 39 ; t fail before and it can reduce the voltage by a small decrement ( box 209 in fig2 ) and go back to check the first fail circuit operation . if the fail flag equals 1 then the cpu knows the loop ended and sets the design voltage using the dc2dc output to the same value as the first fail voltage with a small increment ( box 210 in fig3 ) this changes the voltage level of the digital logic of the device to the required voltage which is the optimal voltage per the needed frequency and the device environment parameters . then the cpu powers down the different sensors ( box 211 in fig2 ) goes to sleep for a short period ( box 212 in fig2 ) and when woken - up starts the loop again . for another embodiment of the invention , the implementation includes a first fail circuit which is illustrated in fig3 . this figure shows the top level block diagram of the first fail circuitry in accordance with one embodiment of the invention . the first fail circuitry includes one input register ( item 300 in fig3 ) which can be written to by the cpu and few digitally controlled delay lines ( dll ) ( items 301 - 302 in fig3 ) and few sampling registers , according to the number of the dll &# 39 ; s used ( items 303 - 304 in fig3 ). these registers can be read back by the cpu . one of these sampling registers is read at a time using the multiplexer ( item 305 in fig3 ). the different dll blocks ( items 301 - 302 in fig3 ) are identical in circuitry , but different in implementation , with each dll having different wire lengths between its internal circuits , which makes the delay of each dll circuit different to represent different worst case paths in the design . fig4 describes the detailed design of the digitally controlled delay lines ( dll ) elements . these are comprised of delay cells ( items 400 , 402 , 404 , 406 , 408 in fig4 ) and multiplexers ( items 401 , 403 , 405 , 407 , 409 in fig4 ). the control bus choses per multiplexer if the path with the delay cell is chosen ( control [ x ]== 1 )) or the path without the delay cell is chosen ( control [ x ]== 1 )). in this way the cpu can digitally control the delay of the dll . for another embodiment of the invention , the first fail circuit path length is programmable and can be controlled by the software after the device is manufactured and characterized . with this method after performing the chip characterization the length of this first fail path can be determined to exactly represent the worst case path in the design of the digital logic of the device . for another embodiment of the invention , the first fail circuit comprises of a few identical dll circuits that are designed with the same circuitry , but with different wire lengths in each dll . by using all different dll paths , it is possible to represent worst case paths in the design of the digital logic of the device both for paths with short wires between circuitry and for paths with long wires between circuitry . embodiments of the invention have been described as including various operations . many of the processes are described in their most basic form , but operations can be added to or deleted from any of the processes without departing from the scope of the invention .