there will now be described by way of example the best mode contemplated by the inventors for carrying out the invention . in the following description , numerous specific details are set out in order to provide a complete understanding of the present invention . it will be apparent , however , to those skilled in the art that the present invention may be put into practice with variations of the specific . fig1 a and 1 b show the amplitude and phase distortion characteristics of a typical class ab power amplifier . fig1 a gives the output signal envelope in volts as a function of the input signal envelope in volts , showing the characteristic amplitude compression as the amplifiers nears its saturated output power . fig1 b gives the phase shift through the high power amplifier as a function of the input signal amplitude envelope . the effect of amplifier distortion on a spread - spectrum modulated signal is illustrated in fig1 c and 1 d . fig1 c shows the power spectrum of a 20 channel qpsk signal applied to the power amplifier input , whilst fig1 d shows the resulting power spectrum at the amplifier output . the spectrum has developed sidebands , termed ‘ regrowth sidebands ’ which are characteristic of amplifier distortion . regrowth sidebands are a system problem since they can potentially interfere with neighbouring communication channels . specification limits on regrowth sidebands are therefore stringently specified in most cellular communication standards . fig2 shows a conventional cavity combiner transmitter system . a plurality of separate transmitters tx 1 , tx 2 . . . txm each generate a signal which occupies a particular radio frequency band which is then amplified by respective high power amplifier hpa 1 , hpa 2 , . . . hpan . the set of n such amplified signals are combined by a cavity combiner p 10 for feeding to an antenna p 15 . a disadvantage of this is the expensive cavity combiner which typically needs to be adjustable in order to combine the power amplifiers with low loss , and maintain this low loss even in the event of an amplifier failure . fig3 shows an alternative transmitter architecture which is enabled by use of a linearised amplifier such as described in this document . multiple transmitters on various channel frequencies are combined at a low signal level by a passive combiner ( p 20 ). in contrast to the cavity combiner ( p 10 ) described previously , the passive combiner ( p 20 ) does not need to be low loss and can therefore be an inexpensive hybrid type . such a passive combiner also maintains high isolation between its input ports in the event of a fault on one of its inputs . the combined output , being a composite of modulated signals at different channel frequencies , is then applied to a linearised high power amplifier ( p 25 ) such as that described in this document . due to the improved linearity performance of the amplifier , the multi - carrier signal is amplified without generating unacceptable intermodulation products and is radiated from antenna ( p 15 ) via a low cost , low loss band filter ( p 30 ). fig4 shows a block diagram of a first embodiment made in accordance with the invention . in use , an rf input signal ( 10 ) is applied to a high power amplifier ( 22 ) via a directional coupler ( 12 ), a first delay line ( 14 ), an amplitude modulator ( 16 ) and a phase modulator ( 18 ). an output of the amplifier ( 22 ) provides an amplified output signal ( 28 ) which is sampled by a directional coupler ( 26 ). the sampled rf output from the directional coupler ( 12 ) is applied to a power splitter ( 32 ), the outputs of which are connected to an envelope detector ( 34 ) and a second delay line ( 40 ). the output of the envelope detector is connected to an adaptive pre - distorter subsystem ( 70 ). the adaptive pre - distorter subsystem ( 70 ) generates two outputs : a gain correction signal ( 92 ) which is connected to the control port of first amplitude modulator ( 16 ); and a phase correction signal ( 94 ) which is connected to the control port of phase modulator ( 18 ). the adaptive pre - distorter ( 70 ) generates the correction signals ( 92 , 94 ) as functions of input ( 36 ) in such a way that the input signal , delayed by ( 14 ) anrd modulated by modulators ( 16 , 18 ), on passing through the high power amplifier ( 22 ) emerges with lower distortion than if no pre - distortion subsystem had been employed . the purpose of the pre - distorter gain and phase transfer functions is therefore to cancel the gain and phase distortion produced in the power amplifier ( 22 ). the purpose of delay line ( 14 ) is to compensate for any delay skew between the signal ( 10 ) modulation and the correction signals ( 92 , 94 ) induced by processing delay in the correction path ( 12 , 32 , 34 , 70 ). the error detection subsystem ( 60 ) requires as inputs a sample ( 42 ) of the input signal ( 10 ) and a sample ( 54 ) of the output signal ( 28 ), normalised to the same signal level and aligned in time . output sample ( 54 ) is normalised to the same level as ( 42 ) by attenuating the coupled output of coupler ( 26 ) in attenuator ( 52 ); input sample ( 42 ) is time - aligned with ( 54 ) by delaying one output of power splitter ( 32 ) in delay line ( 40 ). in order to compensate for changes in the high power amplifier ( 22 ) gain and phase distortion characteristic , for example due to temperature or channel frequency changes the pre - distorter ( 70 ) operates on an adaptive basis . that is , the pre - distorter ( 70 ) adaptively adjusts its gain and phase transfer functions in response to residual gain error ( 82 ) and residual phase error ( 84 ) signals fed back from an error detection subsystem ( 60 ). the pre - distortion functions therefore optimally converge as the system operates . fig5 shows an implementation of error detection subsystem ( 60 ) as may be used in the above described amplifier . the input signals ( 42 ) and ( 54 ) are each split by power splitters ( 602 ) and ( 604 ) respectively . an output of splitter ( 602 ) is fed to envelope detector ( 610 ) and an output of splitter ( 604 ) is fed to envelope detector ( 612 ). the envelope detectors ( 610 , 612 ) produce output voltages proportional to the amplitude envelope of signals ( 42 ) and ( 54 ) respectively . the output voltage of detector ( 610 ) is subtracted from the output of detector ( 612 ) by a differential amplifier ( 616 ) to produce a signal ( 618 ) proportional to the amplitude error between ( 42 ) and ( 54 ). the difference signal ( 618 ) is divided in analogue divider block ( 620 ) by signal ( 614 ) being the output of envelope detector ( 610 ) to produce a signal ( 82 ) which is proportional to the gain error between ( 42 ) and ( 54 ). the implication of this is that the gain error signal ( 82 ) is a metric ( only of the gain distortion ( amplitude compression or expansion ) in the power amplifier and is independent of the input signal envelope level . this can improve the stability of the amplitude adaptation loop allowing parameter μ g to be set more closely for rapid conversions . the remaining outputs of splitters ( 602 ) and ( 604 ) are fed . to a phase comparator ( 630 ) which has two outputs ( 632 ) and ( 634 ). if the rf input from splitter ( 602 ) is represented in polar form by r 1 . cos ( ω c t + α ) and the rf input from splitter ( 604 ) is represented by r 2 . cos ( ω c t + β ) then the response of phase comparator ( 630 ) is such that output ( 632 ) is proportional to r 1 . r 2 . cos ( β − α ) and output ( 634 ) is proportional to r 1 . r 2 . sin ( β − α ). analogue divider block ( 636 ) divides output ( 634 ) by ( 632 ) to give phase error signal ( 84 ): it should be noted that this divider is merely correcting for the amplitude response of the differential phase detector and hence performs a different role to that ( 620 ) in the gain error loop . phase error signal ( 84 ) is then equal to tan ( β − α ) which for ( β − α ) small is approximately proportional to ( β − α ). variations of the error detector ( 60 ) are possible . depending on the performance required , the amplitude analogue divider ( 620 ) may be omitted ( although μ g will need to be set to a lower value in order to preserve a loop stability ), an alternative configuration of amplitude detectors and signal processing elements may be used . alternative types of phase discriminator may also be used . a variation of the error detector ( 60 ) may be implemented which generates error signals ( 82 , 84 ) relating to the signs of the amplitude and phase errors only , as are commonly employed elsewhere in the field of control systems . the error detection block ( 60 ) may be partially or entirely replaced by digital implementation , wherein the rf signals ( 42 , 54 ) are digitised and the error signals ( 82 , 84 ) are computed by digital signal processing means ( dsp ). the feeding of these . error signals to gain blocks ( 724 , 754 ) into the predistorter ( 70 ) can then be performed in the digital domain . fig6 shows an implementation of the adaptive digital pre - distorter ( 70 ). signal ( 36 ), being proportional to the amplitude envelope of the system input ( 10 ) is filtered by a low - pass anti - alias filter ( 702 ) and is digitised by ( 704 ), an analogue - to - digital converter . the m - bit output of the adc is connected to the m bits of an address bus ( 760 ) via a multiplexer ( 706 ). the address bus ( 760 ) is used to select an address in ram ( 710 ) a 2 m word phase correction random access memory ( ram ) and ( 740 ), a 2 m word gain correction ram . the data bus ( 713 ) of phase correction ram ( 710 ) is connected to ( 712 ), a latching digital - to - analogue converter ( dac ). the output of the dac ( 712 ) is filtered by a low - pass anti - alias filter ( 714 ) to give phase correction signal ( 94 ). in a similar arrangement , the data bus ( 743 ) of gain correction ram ( 740 ) is connected to latching dac ( 742 ). the output of dac ( 742 ) is filtered by low - pass anti - alias filter ( 744 ) to give gain correction signal ( 92 ). a two phase clocking scheme is implemented . on phase one of the clock , the adc ( 704 ) samples the filtered input signal ( 36 ) and asserts the digital result on address bus ( 760 ) via multiplexer ( 706 ) which is open for this path on phase one of the clock . in response to the input address and with the read - write input on the ram ( 762 ) being set to ‘ read ’, phase correction ram ( 710 ) asserts a correction value on its data bus ( 713 ) which is converted to an analogue phase correction signal ( 94 ) via dac ( 712 ) and filter ( 714 ), which in the first embodiment is low - pass and band - pass in the second embodiment , as will become apparent . similarly , gain correction ram ( 740 ) asserts a correction value on its data bus ( 743 ) which is converted to an analogue gain correction signal ( 92 ) via dac ( 742 ) and filter ( 744 ). in this way the gain and phase correction signals required by the system are generated during clock phase one . to facilitate adaptation , the contents of address bus ( 760 ), phase ram data bus ( 713 ) and gain ram data bus ( 743 ) are clocked into first - in - first - out ( fifo ) buffers ( 708 ), ( 716 ) and ( 746 ) respectively on phase one of the clock . the length of these buffers is adjusted so as to time align the three fifo - stored signals with the delay on the residual gain and phase error signals ( 82 ) and ( 84 ), which are delayed by analogue delays in the rest of the system . on phase two of the clock , the contents of the correction rams ( 710 , 740 ) are set into write mode via their read - write inputs ( 762 , 764 ) and their contents are adapted . the residual phase error signal ( 84 ) is filtered by anti - alias filter ( 720 ) and digitised by adc ( 722 ). the result is multiplied by a fixed coefficient μ p in ( 724 ) and is applied to a subtractor ( 726 ). the subtractor forms the difference between the output of fifo ( 716 ) and the output of ( 724 ). the resulting digital signal ( 727 ) is applied to the phase ram data bus ( 713 ) via a 3 - state buffer ( 728 ) which passes data on phase two but isolates it on phase one of the clock . in a similar arrangement the residual gain error signal ( 82 ) is filtered by anti - alias filter ( 750 ) and digitised by adc ( 752 ). the result is multiplied by a fixed coefficient μ g in ( 754 ) and is applied to a subtractor ( 756 ). the subtractor forms the difference between the output of fifo ( 746 ) and the output of ( 754 ). the resulting digital signal ( 757 ) is applied to the phase ram data bus ( 743 ) via a 3 - state buffer ( 758 ) which passes data on phase two but isolates it on phase one of the clock . the settings of convergence parameters μ p and μ p are adjusted to achieve the desired convergence speed whilst maintaining system stability . the action of adaptation is as follows : on phase two of the clock , multiplexer ( 706 ) switches to pass data from fifo ( 708 ) to address bus ( 760 ). if the delay in fifos ( 708 , 716 ) and ( 746 ) is k cycles of the pre - distorter clock then on clock phase two the address bus ( 760 ) is thereby set to select the entries in rams ( 710 , 740 ) corresponding to the signal envelope k clock cycles ago . at the same time , the output of fifo ( 716 ) corresponds to the phase correction value which was used k clock cycles ago . the output of ( 724 ) constitutes a metric of the residual phase error left at the same instant ( k clock cycles ago ) when this phase correction was applied , assuming the fifo delays have been adjusted correctly . therefore the output of subtractor ( 726 ) represents an improved estimate of the phase correction factor needed for the signal envelope value currently asserted on address bus ( 760 ). during phase two of the clock the write enable control of phase correction ram ( 710 ) is strobed , thereby writing the improved estimate ( 727 ) into the correct location of the ram . similarly , for adaptation of the gain correction , fifo ( 746 ) yields , on clock phase two , the gain correction factor applied k cycles previously . subtractor ( 756 ) forms an improved estimate of the correction factor needed for the envelope value asserted on address bus ( 760 ) by subtracting the scaled residual gain error at the output of ( 754 ) from the fifo ( 746 ) output . during phase two of the clock the write enable control of gain correction ram ( 740 ) is strobed , thereby writing the improved estimate ( 757 ) into the correct location of the ram . whilst the above figure shows a particular embodiment of the adaptive predistorter ( 70 ), those skilled in the art will be able to implement the same functionality in a different arrangement of hardware and / or software . the architecture provides a method whereby the lut adaptively ‘ learns ’ the pre - distortion coefficients required . the input and output signals of the system are sampled . it is preferable that the input signal is delayed and the output signal attenuated so that the sampled signals are equal in power and any skew in the modulation envelope is resolved . such delay and attenuation may be intrinsically associated with the circuitry , but it is preferable that dedicated circuit components are provided whereby the power and skew between the input signal at the gain and phase detector may be controlled . the two signals are each split into two : one output being fed into a gain error detector and the other being fed into a phase error detector . the gain error detector produces an output approximately proportional to the gain error between the signals , the phase error detector produces an output approximately proportional to the phase error between the signals . the gain and phase error signals are digitised by an anti - alias filter and adc . as the pre - distorter operates , the input envelope samples and gain and phase correction samples are delayed in first - in - first - out ( fifo ) buffer memory to align them in timing with the sampled error signals from the gain and phase error detectors . the gain and phase error signals are multiplied by a fixed fractional convergence parameter and are subtracted from the delayed gain and phase correction signals respectively to obtain signals which are an improved estimate of what the correction signals at the stored signal envelope should have been . the improved gain and phase correction estimates are written back , sample by sample , into the lookup table using the delayed envelope signal to determine the correct addresses , thereby improving the accuracy of the pre - distortion in future . the method of adaptation described above modifies one look - up table entry corresponding to one quantised envelope value for each sample of the gain and phase error signals . hence each entry of the look - up table converges independently of the others . while having a large number of independent table entries has the benefit of being able to adapt to the wider strain of am - am and am - pm functions , it can be disadvantageous with respect to convergence speed and estimation error . variations of the algorithm are possible where the use of a single sample of the gain and phase error signals are used to modify multiple adjacent look - up table entries , using a primary knowledge of the properties of the look - up table function , such as limits in the rate of change of amplifier distortion with amplitude that are known for the amplifier employed . as an illustration of the principle , one such variation consists of the steps of : taking an off - line copy of the current gain and phase look - up tables ; adapting one or more entries according to the basic algorithm ; filtering using a low - pass filter the off - line gain and phase tables with respect to envelope value index ; and , writing the modified tables back into the predistorter . in the event that the gain modulator ( 16 ) has sufficient gain adjustment range to absorb all system tolerances as well as all gain compression effects , and the phase modulator ( 18 ) has full four - quadrant phase adjustment capability , then the pre - distorter will adapt to track out changes in gain and phase response of the high power amplifier ( 22 ) and no further control systems are needed . the rf modulated input waveform may be represented as x c ( t )= re { x ( t ) exp ( jω c t )}, where x ( t ) is the baseband equivalent complex signal . the proposed architecture performs adaptive pre - distortion of x c ( t ) in the polar domain by the following steps : a ) the complex modulus x env ( t ) of the input signal x ( t ) is obtained , typically by an envelope detector , viz : b ) the envelope signal x env ( t ) is sampled at rate f s and quantised to m - bits to yield a sequence of samples i k where any i k may take the value 0 . 2 m − 1 . c ) each i k is used as an index to select an entry from a 2 m - entry lookup table ( lut ) which stores two output coefficients for each index . one output is a gain correction sample g k ( i k ) and the other is a phase correction sample p k ( i k ). d ) the stream of selected gain correction coefficients g k ( i k ) is converted to a continuous time analogue representation via a digital - to - analogue converter ( dac ) to yield gain correction signal g ( t ). e ) the stream of selected phase correction coefficients p k ( i k ) is converted to a continuous time analogue representation via a digital - to - analogue converter ( dac ) to yield phase correction signal p ( t ). f ) the correction signals g ( t ) and p ( t ) are applied to the input signal by appropriate amplitude and phase modulators to yield pre - distorted signal x p ( t ) as follows : g ) the pre - distorted input x p ( t ) is applied to the input of the high power amplifier , whereupon if the lut coefficients g ( i ) and p ( i ) have been set correctly , the output from the power amplifier will emerge with less distortion than if no correction had been employed . given the power amplifier rf output waveform y c ( t )= re { y ( t ). exp ( jω c t )}, where y ( t ) is the baseband equivalent complex signal , and also given a target linear rf gain g , the lut coefficients g ( i ) and p ( i ) are set to optimum values by the following adaptation process : h ) a gain error signal ε g ( t ) is derived as follows : subject to the particular implementation of error detector ( 60 ), ε g ( t ) may be an approximation to the above function and have a restricted linear range or relate simply to the ε g of the ideal gain error . i ) the gain error signal ε g ( t ) is sampled at a rate f s to yield a sequence ε g , k where ε g , k = ε g ( k / f s ). j ) a phase error signal ε p ( t ) is derived as follows : subject to the particular implementation of error detector ( 60 ), ε g ( t ) may be an approximation to the above function and have a restricted linear range or relate simply to the ε g of the ideal gain error . k ) the phase error signal fp ( t ) is sampled at a rate f , to yield a sequence ε p , k where ε p , k = ε p ( k / f s ). l ) an improved estimate g ′ k of each gain correction coefficient g k is formed as follows : m ) an improved estimate p ′ k of each phase correction coefficient p k is formed as follows : n ) the improved estimates g ′ k and p ′ k are written back into lookup table entry i k . o ) the sample number k is incremented by 1 and the process repeated from step ( i ). this assumes no propagation or processing delay in the operations or in the power amplifier . a practical implementation will require certain signals to be delayed in order to remove timing skew , however this does not influence the nature of the algorithm . fig7 shows a block diagram of the second embodiment of the invention . wherein the system includes second amplitude ( 20 ) and second phase ( 21 ) modulators and baseband processing elements ( 86 , 87 , 88 , 89 ). these form slow feedback loops operating in the gain and phase domains in order to centre the operation of the pre - distorter and allow system components of greatly reduced operating range to be used . the operation of the slow gain feedback loop is as follows : the gain error signal ( 82 ) is integrated by integrator ( 88 ) and amplified by gain block ( 89 ). it is then applied to a second amplitude modulator ( 20 ) which adjusts the signal level into the second phase modulator ( 21 ) and high power amplifier ( 22 ). the arrangement forms a control loop with integral action whereby the output level is adjusted to set the sampled output ( 52 ) at the same average envelope voltage as the sampled input ( 42 ). similarly , the operation of the slow phase feedback loop is as follows : the phase error signal ( 84 ) is integrated by integrator ( 86 ) and amplified by gain block ( 87 ). it is then applied to a slow phase modulator ( 21 ) which adjusts the phase of the signal into the high power amplifier ( 22 ). the arrangement forms a control loop with integral action whereby the average phase of the sampled output ( 52 ) is adjusted to the same average phase as the sampled input ( 42 ). when slow loops are used , it is required that the correction signal anti - alias filters ( 714 ) and ( 744 ) have a zero at dc ( i . e . are ac coupled ) in order to prevent the pre - distorter adaptation and slow loop adjustments interacting . the sampled rf output from directional coupler ( 12 ) is applied to a power splitter ( 32 ), the outputs of which are connected to an envelope detector ( 34 ) and a delay line ( 40 ). the output of the envelope detector is connected to an adaptive pre - distorter subsystem ( 70 ). the adaptive pre - distorter subsystem ( 70 ) generates two outputs : a gain correction signal ( 92 ) which is connected to the control port of first amplitude modulator ( 16 ); and a phase correction signal ( 94 ) which is connected to the control port of first phase modulator ( 18 ). as described in relation to the first embodiment , the pre - distorter ( 70 ) adaptively adjusts its gain and phase transfer functions in response to residual gain error ( 82 ) and residual phase error ( 84 ) signals fed back from an error detection subsystem ( 60 ) and the error detection subsystem ( 60 ) operates as described above . the ‘ slow feedback ’ control system nulls out the average gain and phase errors in the adaptation loop . the output of the gain error detector mentioned above is integrated and amplified to provide a control signal which modulates a gain control element between the pre - distorter and the power amplifier itself . similarly , the output of the phase error detector mentioned above is integrated and amplified to provide a control signal which modulates a phase control element between the pre - distorter and the power amplifier . these feedback control loops adjust to trim out the amplitude and phase errors between the two signal paths into the gain and phase error detectors , ensuring that these detectors are operated at their optimum operating point . a further benefit is that with the slow loops controlling the average gain and phase response of the high power amplifier , the range of gain and phase adjustment required from the pre - distorter is greatly reduced . previous designs for providing pre - distorted amplification are too complex to be easily realisable in discrete form . the present invention provides a completely polar - domain design which is capable of providing pre - distortion to a standalone radio frequency power amplifier rather than being necessarily being incorporated into an existing dsp system . the analogue signal processing used to condition error signal and provide input signals eliminates the need to accurately digitise wideband signals at the carrier frequency in order to drive dsp implementations of the error feedback system and pre - distorter . the correction signals from the pre - distorter are applied to the input signal via analogue radio frequency control elements whereby at no stage is the input signal to the power amplifier required to be in the digital domain . the use of slow loops can be used to stabilise the power amplifier gain and phase response , thereby reducing the dynamic range required from the pre - distorter look - up table . this is of advantage for many applications such as in the provision of high power linear amplifiers in the transmission of signals in cellular radio base stations .