the process of the present invention is described in the context of forming gate oxides of different thicknesses on a single semiconductor layer by way of example only . it will be apparent to one skilled in the art that the present invention is not limited to the specific embodiments of fig2 - 8 . referring now to the drawings , fig2 shows a semiconductor layer 10 which is preferably composed of epitaxial silicon . semiconductor layer 10 shall hereinafter be referred to as epitaxial silicon layer 10 . epitaxial silicon layer 10 is typically grown on a silicon wafer substrate utilizing well known crystal growth techniques , e . g ., chemical vapor deposition . epitaxial silicon layer 10 can contain a plurality of device tubs 11 formed by ion implanting dopants such as boron , phosphorus , arsenic , etc ., in selected regions of epitaxial silicon layer 10 and thereafter annealing to electrically activate the dopants . prior to or after formation of the device tubs , a sacrificial thermal oxide layer ( not shown ), typically about 150 å thick , can optionally be grown on epitaxial silicon layer 10 to remove any defects from epitaxial silicon layer 10 . this sacrificial thermal oxide layer may be grown by various processes known to those skilled in the art , e . g ., chemical vapor deposition ( cvd ). in a typical process , the sacrificial thermal oxide layer is grown by heating epitaxial silicon layer 10 to a temperature ranging from about 600 ° c . to about 1200 ° c . and then subjecting the substrate to oxidation . the sacrificial thermal oxide layer is completely etched back using , for example , a 10 : 1 hf etch . oxide layer 12 is then preferably grown on epitaxial silicon layer 10 as illustrated in fig3 . the thickness of oxide layer 12 can vary from about 60 to about 500 å , preferably from about 80 to about 200 å . oxide layer 12 can be formed on epitaxial silicon layer 10 by various processes known to those skilled in the art , such as by heating the substrate to a temperature ranging from about 600 to about 1200 ° c ., preferably from about 700 to about 900 ° c ., and subjecting the substrate to oxidation , e . g ., wet or dry o 2 . referring to fig4 a selected area of oxide layer 12 is exposed in accordance with this invention by depositing masking layer 14 on oxide layer 12 . masking layer 14 is patterned to provide window 16 which exposes a selected area of first oxide layer 12 . masking layer 14 typically comprises a resist material or any other material known to be suitable as a masking material . turning now to fig5 ions 18 are implanted by implantation means ( not shown ) such that ions 18 pass through window 16 and penetrate the exposed area of oxide layer 12 and epitaxial silicon layer 10 underlying the exposed area of oxide layer 12 . implantation of ions 18 in epitaxial silicon layer 10 damages , i . e ., amorphizes , the crystal lattice structure of epitaxial silicon layer 10 . fig6 depicts amorphized region 20 where ions 18 are implanted in a selected region of epitaxial silicon layer 10 . oxide layer 12 partly serves the function of preventing excess damage to epitaxial silicon layer 10 from occurring when ions 18 are implanted in epitaxial silicon layer 10 . ions 18 are selected for their ability to amorphize epitaxial silicon layer 10 . such ions include silicon , fluorine , arsenic , and mixtures thereof . silicon is preferred . ions 18 can be implanted via any suitable technique , preferably via ion mixing implantation , at doses typically ranging from about 1 × 10 12 to about 5 × 10 16 , preferably from about 1 × 10 15 to about 5 × 10 15 , ions per cm 2 and energies typically ranging from about 5 to about 500 , preferably from about 20 to about 50 , kev . ion mixing implantation typically involves implanting ions into a substrate either in the presence or absence of an intermediate layer to amorphize the surface of the substrate . the dosage and / or energy of such an amorphizing implant will vary depending upon the thickness of exposed oxide layer 12 and the amount of damage to epitaxial silicon layer 10 which is desired . the amount of damage to epitaxial silicon layer 10 can be determined , of course , by controlling the dosage and energy of the amorphizing implant . appropriate dosages and energies of amorphizing implants carried out in accordance with this invention can therefore be determined by routine experimentation . after amorphization of selected regions of epitaxial silicon layer 10 is complete , masking layer 14 is removed , e . g ., by dry or wet etch . in an alternative embodiment herein , thermal annealing can be employed to repair part of the damage caused by the amorphizing implant . typically , thermal annealing can be carried out at a temperature ranging from about 600 to about 1200 ° c ., preferably from about 750 to about 900 ° c ., for between about 0 . 1 to about 120 minutes , preferably between about 60 to about 90 minutes . following such an annealing step , oxide layer 12 is removed by any suitable method , e . g ., chemical etching , utilizing known and conventional techniques , e . g ., a 10 : 1 hf solution . gate oxide 22 is subsequently grown on epitaxial silicon layer 10 as shown in fig7 . gate oxide 22 can be grown on epitaxial silicon layer 10 by any suitable growth technique . typically , gate oxide layer 22 is grown on epitaxial silicon layer 10 by heating the substrate to a temperature ranging from about 600 to about 1200 ° c ., preferably from about 700 to about 900 ° c ., and subjecting the substrate to oxidation , such as wet or dry o 2 . following oxidation , as depicted in fig7 gate oxide 22 grown on amorphized region 20 of epitaxial silicon layer 10 will be thicker than gate oxide layer 22 grown on non - amorphized regions of epitaxial silicon layer 10 . in an alternative embodiment , gate oxide 22 can be selectively grown on amorphized region 20 and / or non - amorphized regions of epitaxial silicon layer 10 utilizing techniques which are well known in the art , e . g ., by masking and etching to provide windows exposing the regions where gate oxide is to be selectively grown . fig8 discussed below demonstrates that the thickness of gate oxide grown on a region which has been amorphized as disclosed herein is a function of the energy of the amorphizing implant . in general , the thicknesses of gate oxides grown on amorphized regions will broadly range from about 40 to about 500 å , preferably from about 100 to about 160 å . the thicknesses of gate oxides grown on non - amorphized regions will broadly range from about 20 to about 400 å , preferably from about 80 to about 130 å . thus , gate oxides of varying thicknesses are formed on a semiconductor substrate utilizing the process described herein . fig8 shows transmission electron micrographs ( tems ) of cross - sections of epitaxial silicon layers having oxide ( sio2 ) layers grown on the surfaces thereof . fig8 ( a ) is a tem of a cross - section of a 130 å - thick oxide layer grown on a non - amorphized epitaxial silicon layer ( control ). fig8 ( b )-( e ) are tems of cross - sections of oxide layers grown on epitaxial silicon layers which have been amorphized . the epitaxial silicon layers shown in fig8 ( b )-( e ) ( designated &# 34 ; si &# 34 ; in the tems ) were each implanted with silicon at a dose of 5 × 10 15 si / cm 2 using ion mixing implantation . the energies used to implant the si ions in each of the epitaxial silicon layers of fig8 ( b )-( e ) was 15 kev , 20 kev , 30 kev and 50 kev , respectively . a 140 å - thick oxide layer grew on the epitaxial silicon layer of fig8 ( b ) and 160 å - thick oxide layers grew on the epitaxial layers of fig8 ( c )-( e ). these data show that oxides will grow differentially thicker on amorphized regions relative to non - amorphized regions of an epitaxial silicon layer . various mos devices , e . g ., n - mos , p - mos and cmos devices , can be formed on the variable thickness gate oxides in accordance with known procedures . thus , e . g ., polysilicon can be deposited on the gate oxides to form gate stacks and dopant species can be introduced into the semiconductor layer by diffusion or ion implantation to create source and drain regions on both sides of the gate stacks . as the dopant species is introduced , the gate stacks serve as self - aligned masks shielding the channels under the gates from the dopant species . in a particularly preferred embodiment herein , devices operating at both 5v and within the range of from about 1 . 8 to about 3 . 3v are fabricated on the variable thickness gate oxides produced in accordance with the process of this invention . while the invention has been particularly shown and described with reference to these various embodiments , it will be recognized by those skilled in the art that modifications and changes may be made to the present invention without departing from the spirit and scope thereof , which is set forth in the following claims .