the word signature , as used in both the specification and the claims herein is not to be construed solely as meaning the name of a person . any sequence of characters or words or symbols may be processed by this invention and are intended to be within the meaning of the word signature . fig1 is a representation of a signature display , in accordance with this invention . since the display will occupy a pre - determined area , the horizontal dimension of the area is designated as x plot and the vertical dimension of the area is designated as y plot . each time a signer lifts his pen , in writing his signature , a space is alloted between the pen lift and the next pen down location , which space is designated as δp . the region over which writing occurs without a pen lift is designated as a sector . thus , the signator here first used a down stroke for the front side of the h , which is designated as sector one . he then lifted his pen . following the pen lift a space δp is allocated . thereafter , the rest of the first name was written in the space which is designated as sector 2 . the pen was then lifted to cross the t &# 39 ; s . this caused the establishment of another space designated as δp . the dash like stroke of sector 3 results from the crossing of the t &# 39 ; s . thereafter , upon pen lift another δp space is allocated . a dot over the &# 34 ; i &# 34 ; is written . this is designated as sector 4 and is followed by another space δp . thereafter the initial d is written in the space denoted as sector 5 . this is followed by another δp space . the dot following the d occurs in sector 6 . this is followed by another space δp . this is followed by the last name crane , which forms sector 7 . in summary , each time the pen is lifted a δp spacing is allocated before the next part of the signature is displayed . the δ p spacing is followed by a sector whose horizontal length is determined by the distance between the maximum and minimum horizontal display locations derived from the pen signals between a single pen down and pen up operation . accordingly , in the horizontal direction , the problem presented is that , in view of the limited xplot space allowed , the spacing allocated to all of the δp &# 39 ; s must be subtracted from xplot , and then the remainder of the signature must be fitted into the remaining space . in the vertical or y direction , the signals within each sector are positioned so that the average y value for the sector equals zero . that is the y average for each sector is calculated and then subtracted from each y value within the sector . in effect this makes all of the various sectors straddle the mid line . in addition , the maximum and minimum y value for all sectors is found and all of the y values are then scaled so that the maximum y value just fits within the bounds of the display area . referring now to fig2 a pen 10 , such as is described and claimed in u . s . pat . no . 3 , 915 , 015 , is used by way of example , for generating force signals , such as x and y signals which are respectively generated as the pen is moved in the x and in the y direction , and p signals which are pressure signals generated when the pen is pressed down against the paper for writing . each one of the respective x , y and p signals is applied to respective sampling circuits , 12 , 14 , and 16 , which sample these signals at intervals determined by the output of a free - running pulse generator 18 . the samples , derived by the sampler circuits 12 , 14 and 16 , are applied to respective a to d converters , 20 , 22 , 24 , for the purpose of being digitized . the x and y signals , which are sampled are proportional to the force in these respective directions in a coordinate system fixed to the pen . on the assumption that the instantaneous x and y values are proportional to the instantaneous x and y velocities in the plane of the paper , ( i . e . due to pure drag of the pen on paper ) then by integrating these instantaneous x and y velocities one can obtain x and y coordinate values from which the signature may be recreated . the x and y forces generated by the pen are not exactly proportional to the instantaneous pen velocity but close enough that by integrating the force signals as described above , coordinate signals x and y are generated which when plotted provide a useful facsimile of the original signature . the re - created signature generally looks like a distorted version of the familiar static signature . it is the distortions in fact that carry the interesting dynamic information . in the remainder of this disclosure , capital x and y symbols will represent integrals of the basic force signals , x and y , derived directly from the pen . more specifically , xij and yij will represent respectively the horizontal and vertical i ( th ) coordinate of the j ( th ) sector of the re - created signature . when the pen is pressed down on a surface for writing , the p signal generated is indicative of that situation . this signal is applied to a threshold circuit 26 , and to an inverter circuit 28 . if the p signal exceeds the level of a bias voltage provided by the threshold circuit 26 , indicative of the fact that the pen is actually being used for writing , a pulse generator 30 , is actuated to provide a pulse , which sets a flip flop 32 . the set state output of the flip flop circuit is a &# 34 ; start signature signal &# 34 ;, indicative of the fact that a signature has been started . the set state output of the flipflop 32 is also applied to an and gate 34 , to act as an enabling input . the other input to the and gate 34 is the output of the inverter 28 . in the presence of the p signal , no output is applied by the inverter 28 to the and gate 34 . in the absence of the p signal , an input is applied by the inverter to the and gate 34 . and gate 34 output actuates a pulse generator 36 . the inverter output is also used to enable another and gate 38 . the output of the pulse generator 36 is applied to a time delay circuit 40 . after an interval , determined by the time delay circuit 40 , if the pen 10 is still up so that the inverter output is still present , the and gate 38 applies its output to reset flip flop 32 . the purpose of the circuit just described is to distinguish between pen ups which occur in the usual writing of the signature , either between names or for the purpose of crossing t &# 39 ; s or dotting i &# 39 ; s , and those pen - ups which occur when a person has completed the signature . the time delay 40 is set for an interval sufficient to allow for crossing t &# 39 ; s , dotting i &# 39 ; s or other activities during the course of writing a signature wherein the pen is lifted from the paper . however , if the signature is ended , the time delay interval is exceeded and the flip - flop 32 is reset . the output of the and gate 38 which resets flip flop 32 also serves as an &# 34 ; end - signature signal .&# 34 ; it was previously stated that when the pen is down during the course of writing , an output is received from the threshold circuit 26 . this output , besides being applied to the pulse generator 30 , is also applied to a clipper circuit 41 and a differentiator circuit 42 . the p signals generated by the pen 10 , which appear at the output of the clipper circuit 41 comprise a wavetrain such as p1 wherein each time the pen is applied to the paper a pulse is generated having a duration for as long as the pen is maintained applied to the paper , and each time the pen is lifted from the paper a no pulse interval occurs until the next pen down activity . this pulse wavetrain is differentiated by the differentiator 42 providing a wavetrain such as p2 , having positive going signals corresponding to the positive leading edges of the p1 pulses signifying pen down actions , and negative going actions corresponding to the trailing edges of the p1 pulses , which occur when the pen is lifted . the output of the differentiator is applied to an inverter circuit 44 and to a clipper circuit 46 . the clipper circuit eliminates the negative going signals in the output of the differentiator and therefore the clipper circuit output comprises a train of signals each one of which is indicative of a pen down operation . these are identified as pd signals . the clipper 48 following the inverter 44 provides an output only in the presence of positive going signals from inverter 44 , ( and therefore negative going signals from differentiator 42 ) and does not pass negative going signals . the output pulses passed by clipper 48 are applied to a counter 50 . since the pulses passed by clipper 48 occur only at pen up times then the output of the clipper 48 will be the pen up signals ( pu ). counter 50 counts the number of pen up signals that occur during the course of a signature . counter 50 is reset in the presence of a start - signature - signal output from flip flop 32 . since , as previously indicated , the number of sector , s , which occur during the course of writing a signature is measured by the number of pen ups , the count output , s , of the counter 50 indicates the number of sectors inthe signature . each count output of the counter is multiplied by δp , supplied to multiplier 52 , from a δp signal source 53 . the multiplier output , sδp provides an indication of the amount of δp space that must be allocated at any given time for the amount of signature completed at that time . the final output indicates the total amount of space required for all of the spaces between sectors . the start signature signal enables an and gate 54 , which has as its second input the output of the free - running pulse generator 18 . this it will be recalled , provides the sampling timing signals . when the and gate 54 is enabled by the start signature signal output of flip flop 32 , pulses from the free - running pulse generator 18 are applied to a second and gate 56 and also to the sampling circuits 12 , 14 and 16 . and gate 56 is enabled in the absence of a pen up signal . this is achieved by pu being applied through an inverter 58 to the and gate 56 . inverter output 58 activates and gate 56 during the process of writing a signature while the pen is being applied to the paper . accordingly , when the pen is first applied to the paper to write a signature , pulses from the free - running pulse generator 18 are applied through the and gates 54 and 56 to a counter 60 . at the end of the first sector , a pen up signal appears and counter 60 at that time will indicate a count , designated as nj , indicative of the samples which were taken over the j ( th ) sector . upon the occurrence of a pd signal , when the pen is next applied to the paper to continue writing , the counter is reset and will then commence to count again the number of samples which occur over the next writing sector . the output of the and gate 56 is also applied to an and gate 62 , to constitute one enabling input . a free - running oscillator 64 , applies pulses to the and gate 62 at a frequency which is at least 4 times greater than the frequency of the free - running pulse generator 18 and is synchronized therewith . the output of the and gate 62 is used to drive a clock counter 66 . the outputs of the clock counter 66 are designated as c1 through c4 . the output of the free - running oscillator 18 is applied to another and gate 68 . this and gate is only enabled in the presence of the set output of a flip flop 70 . this flip flop is set in response to an end signature signal . the output of the and gate 68 is applied to a &# 34 ; es &# 34 ; counter 72 . this counter counts for as many counts as the maximum number of signature samples to be taken ( n ). it provides an output for each count esl through esn . the last count esn , is used to reset flip flop 70 . when this occurs and gate 68 is disabled and no more pulses are applied through it to the counter . it should be noted that the digital values which are derived from the a to d converters 20 and 22 may be negative as well as positive . a negative x i occurs when the writer moves the pen to the left . negative y i values occur when the pen is moved vertically downward as opposed to vertically upward . fig3 is a block schematic diagram of the circuits used for deriving an unscaled set of x coordinate values together with a scale factor kx . the sample x i signals derived from a to d converter 20 , are added in an adder 80 together with signals from a δx signal source 82 . δx represents a factor that can adjust the effects of leftward and rightward writing . without such compensation , if the pen is rolled to the right , for example , the instantaneous x i values are larger than with the pen vertical . thus , closed loop segments such as e &# 39 ; s and l &# 39 ; s would tend to become thinner . in fact , with enough roll to the right , the minus x i component generated during the leftward writing segments would be smaller in magnitude than the plus x i contribution due to the roll itself and therefore the x i signals would never become negative . in such a case there would be no closed loops at all in a resulting signature plot . conversely , if the pen has a leftward roll , closed loops are exaggerated . compensating effects can be achieved if desired by adding a fixed positive or negative value δx to each value of x i . if δx is positive , loops are deemphasized . if δx is negative , loops are exaggerated . the same effects can be achieved in the vertical direction if a fixed δy is added to each y i sample . a positive value of δy causes each recreated segment of the signature to slope upward . a negative value of δy causes each segment to slope downward . δx and δy are empirically determined by observing what values are required to obtain the best results . the adder 80 is enabled to add its inputs upon the application of a c1 pulse from the clock counter . the output of the adder 80 is applied to an adder 84 . the output of the adder 84 is applied to a register 86 . the output of the register 86 is applied to the adder 84 to be added to the output of the adder 80 . adder 84 and register 86 are instructed to add on the c2 count of the counter 66 . effectively , adder 84 and register 86 constitute a digital integrator , the adder 84 adds the latest sample ( x i + δx ) to the previous sum which the register 86 accumulated . each output of the adder 84 constitutes a coordinate which is designated as xij , i . e ., with ith x coordinate of sector j . the xij output , as shown in fig7 is stored in the memory for further processing . the xij output of the adder 84 output is applied to two comparators respectively 88 , 90 , and also to two respective sets of gates , 92 , 94 . a second input to comparator 88 is the output of a register , designated as max latch 96 . a second input to the comparator 90 is designated as min latch 98 . gates 92 are enabled to transfer the output of the adder 84 into max latch when comparator 88 indicates that the adder 84 output are greater than the current contents in max latch 96 . gates 94 are enabled to transfer the contents of the adder 84 into the min latch 98 when the comparator 90 output indicates that the adder 84 contents are less than the current contents in the min latch 98 . initially max latch 96 , is filled with all zeroes , and initially min latch 98 , is filled with all ones . accordingly , by the time the signature has been completely written , max latch will contain the maximum xij and min latch will contain the minimum xij . the comparators and min and max latch registers are enabled to become operative in response to the c3 clock pulse . at the conclusion of the signature , as shown in fig2 the es counter is enabled to start counting . upon the occurrence of the es1 output , min latch and max latch can supply their contents to a subtractor 100 , which subtracts the contents of the min latch register from the max latch register to provide a difference . also the min latch contents are dumped into a register 99 which supplies min latch to fig8 . the difference is applied to a divider circuit 102 to be divided by a number representing the difference between x total plot space and ( s - 1 ) δp space required . to obtain this , the value ( s - 1 ) δp is applied to a subtractor to be subtracted from a number representative of the length of the xplot which is provided by an xplot signal source 104 . ( s - 1 ) δp is obtained by applying sδp , the output of multiplier 52 and the value δp to a subtractor circuit 105 . its output is ( s - 1 ) δp . the subtractor 106 is enabled in response to the es1 signal output of the counter 72 , and applies its output to the divider 102 . in response to the es2 signal from the es counter , the divider 102 performs the necessary division and its output is stored in a register 104 , designated as the kx register . fig4 is a block schematic diagram illustrating an arrangement for deriving the y coordinates as well as the average y for each sector and the maximum and minimum y &# 39 ; s . the yi signals together with the δy signal from a source 106 , are applied to an adder 108 . in response to a c1 pulse , the adder 108 adds its inputs and applies them to a digital integrator 110 . digital integrator 110 comprises circuits such as adder 84 and register 86 , in fig3 which operate to integrate the digital input . the digital integrator 110 is enabled to become operative in response to a c2 clockpulse . the output of the digital integrator comprises the coordinate yij , i . e . the ith y coordinate of sector j . digital integrator 110 resets each time a pen down pulse pd occurs , indicative of the beginning of the next sector . accordingly , the output of the digital integrator 110 , at the end of each sector , comprises a sum of all of the y coordinates for that sector . the respective coordinate values yij are stored in a memory , as shown in fig7 in association with the coordinate xij values . in order to determine the average yij , designated as yj for each sector j , the outputs of the digital integrator 110 are summed by a following digital integrator 112 . this integrator adds the successive yij coordinates and applies the sum to a divider 116 , which at pu time is enabled to divide this number by nj , which is the count at pu time in counter 60 , shown in fig2 . this count represents the number of samples which were taken during the jth sector just ended . the digital integrator 112 is reset at pd time . the output of the divider 116 , as indicated , represents the value of yj , which is the average y value for the particular sector . the yj value for each sector is stored in memory , as shown in fig7 . the determination of a maximum yij and minimum yij employs the same structure as was used for determining the maximum xij and minimum xij . the digital integrator 110 output is applied to two comparators respectively 120 , 122 and also to two sets of gates , respectively 124 , 126 . the output of the gates are applied to a max latch register 128 , and the output of the gates 126 are applied to a min latch register 130 . comparator 120 , upon the occurrence of a c3 clock pulse , compares the output of the adder 110 with the output of the max latch 128 . if the adder output is greater than the max latch output then gates 124 will transfer the contents of the adder into the max latch register replacing its contents . if the adder contents are less than the contents of the min latch register 130 , the comparator 122 will produce an output which enables the gates 126 to transfer the contents of the adder 110 into the min latch register replacing its contents . the pen down signal resets max latch and min latch to their respective inital states , which in the case of max latch is an all zero state and in the case of min latch is a one state . the yj value for the sector for which the min latch and max latch has just been calculated , is applied to two subtractors respectively 132 and 134 . subtractor 132 will subtract the average y value y from the max latch value upon the occurrence of a pen up signal pu . subtractor 134 will subtract the min latch value from the average y value upon the occurrence of a pen up signal . the differences are applied to circuits shown in fig5 for the purpose of determining a value designated as y &# 39 ; max , which is used to obtain the largest y coordinate value over all segments . referring now to fig5 there is shown a block schematic diagram for determining y &# 39 ; max and then retaining the one of the y &# 39 ; max or the output of the max latch 128 , designated as y big , whichever is bigger . the yj - ymin output from the subtractor 132 are applied to a comparator gate 136 , and to gates 138 . the ymax - yj output of subtractor 134 is applied to the comparator 136 and to gates 140 . gates 138 are enabled by the comparator output to enter yj - ymin into a register 142 if yj - ymin exceeds ymax - yj . if ymax - yj exceeds yj - ymin the comparator enables gates 140 to enter ymax - yj into the register 142 . thus at the end of each sector register 142 will retain the larger of the two values applied to the comparator 136 , which is designated as y &# 39 ; max . the y &# 39 ; max signal for each sector at pd time is entered into a comparator 150 and also applied to gates 152 . also applied to comparator 150 are the contents of a register 156 . the contents of register 156 , designated as ybigger , are also applied to gates 154 . at pu time the comparator is enabled to compare its inputs , y &# 39 ; max and ybigger . the comparator output , if y &# 39 ; max exceeds ybigger will enable gates 152 to transfer the y &# 39 ; max signals into the register 156 . if the ybigger signals exceed y &# 39 ; max , gates 154 are enabled to transfer the ybigger signals into the register 156 . therefore , at the end of the signature , register 156 will contain the ybigger , for all sectors , which is the greatest y signal which is generated in the course of the writing of the signature . register 156 is closed by an end signature signal . referring to fig6 there may be seen a block schematic diagram for computing the scale factor ky . a multiplier 160 , receives as an input the y bigger output of the register 156 . upon the occurrence of an es2 signal from the es counter , the multiplier receives a signal from the &# 34 ; two times &# 34 ; signal source 162 instructing it to double its contents . as is well known , this is done by shifting the digits of a binary number one place to the left . the contents of the multiplier 160 , at es2 time , is applied to a divider 164 , to be divided into the y plot quantity , derived from the y plot signal source 166 . the resultant output of the divider 164 is ky . referring now to fig7 there may be seen a block schematic diagram which provides for the storage of the xij and yij coordinates together with the δp spacing and the yj or average y for a sector in a memory 170 . the manner in which these quantities are stored in the memory is represented in the drawing . a zero or no flag bit is stored with each of the coordinates . the coordinates are stored in the sequence in which they are generated . the first sector storage commences with coordinates x11 and y11 , extending until the end of the sector as identified by a pen up signal , and the coordinates then are x1n1 and y1n1 . in the next location there is stored a flag bit designated as &# 34 ; 1 &# 34 ;, the δp data , and the average y for the sector represented by y1 . then there follows the coordinate information for the next sector represented by x21 , y21 down through x2n2 y2n2 . this is followed by the flag bit &# 34 ; one &# 34 ;, 2δp , and y2 . pressure signals pij may also be stored adjacent the xij and yij . in this manner the data generated by the circuits represented in fig3 and 4 , namely the xij , yij and yj data together with the output of the multiplier 52 is stored in the memory . the write - in signal to the memory is supplied by the start signature signal . the xij and yij inputs are applied to gates 172 , which are enabled in the presence of a c4 pulse . gates 174 have as their inputs the output of the multiplier 52 , namely sδp , the y input and a flag bit which is derived from a flag bit source 176 . these gates are enabled in the presence of a delayed pen up pulse . this is obtained by applying the pu signal to a delay circuit 178 , whose output pud is applied to the gates to enable the gates 174 . the address locations in which the inputs are stored is determined by an address counter 180 . this cunter receives signals which enable it to advance its count from an or gate 182 . one input to the or gate comprises c4 signals . the address counter output is applied to a set of gates 186 which are enabled by the reset output of flip flop 214 during the write in of the coordinate information as well as the flagbit , δp and y information . the address counter also applies its output to a second set of gates 188 . these gates are enabled each time a pen up ( pu ) pulse occurs to enable the write in of the address in the address counter 180 , at that time , to a second memory , 190 . the address in the address counter 180 at the time that a pu pulse occurs is the address in which a flag one bit , sδp , and the yj data is stored . the address in the memory 190 in which this data is stored is provided by an address counter 192 . this address counter is enabled to advance in response to an output of an or gate 194 . one input to this or gate is a pud pulse output from the delay circuit 178 . accordingly , upon the occurrence of a pu signal , the storage address of a flag bit δp and yj is stored in a memory 190 at an address provided by an address counter 192 . with each address , there is also stored a flag 2 bit derived from a flag 2 bit source 189 . in this manner , the memory 170 will store the coordinate data , sδp and yj data while the memory 190 will store the addresses of the sδp and yj locations in the memory 170 , and a flag 2 bit . upon the occurrence of the end signature signal , address counters 180 and 192 are reset and the memory 170 and the memory 190 are transferred from their write modes to their read modes . at this time , the es counter 72 in fig2 commences providing an output . the es1 output of the es counter is applied to an or gate 196 , the output of which disenables gates 186 . the es1 pulse is also applied to an or gate 198 , the output of which enables a set of gates 200 . the end signature signal transfers both the memories 170 and 190 into their read states . accordingly , when the address counter 192 is transferred to its first address count state by the end signature signal , there is a read out from the memory 190 , into an address register 204 , of the address of the sδp and and yj data , together with the flag 2 bit . the address register 204 applies its output to the gates 200 , which are now enabled , and accordingly , the memory 170 will read out the flag 1 bit , δp and yj into the respective registers 206 , 208 and 210 , in which are respectively stored the flag 1 bit , δp and yj . the flag 1 bit is applied to an exclusive or gate 212 , whose output is applied to a flip flop 214 . the es1 count output is also applied to the exclusive or gate 212 . in the presence of es1 , and the flag 1 bit , exclusive or gate 212 will have no effect on the flip flop 214 . in the absence of the es1 count pulse , the output of the exclusive or gate 212 will set flip flop 214 . the flag 1 bit is applied through a delay circuit 195 to the or gate 194 to advance the address counter 192 to its next count state . the flag 2 bit which is read out of the memory 190 , along with each address is applied through a delay circuit 216 to reset flip flop 214 . when flip flop 214 is in its reset state , its reset output enables gates 186 and disenables gates 200 . further , termination of the es1 pulse permits gates 186 to become enabled and gates 200 to become disenabled . at that time , all further count outputs of the es counter are applied to a gate 218 , whose output is applied to the or gate 182 . it further should be noted that gate 218 is inhibited by the set output of flip flop 214 , it is enabled by the reset output of flip flop 214 . accordingly , the es2 count output is now applied to the address counter 180 setting it in its first count and first address state which is the location of the x11 and y11 coordinates . since the address gates 186 are now enabled the first sector coordinate information will be successively read into the respective xij , yij , and pij registers 220 , 222 and 223 . address counter 180 will continue to be sequenced by the count outputs from the es counter successively reading out the xij and yij data of the first sector into the respective registers 220 and 222 . when the flag one bit , and the δp and y1 data , at the end of the first sector storage locations , is read out into the registers provided for them , the flag 1 bit is applied to set the flip flop 214 whereupon the gates 186 are inhibited and gates 200 are enabled . address counter 192 provides the address of the next location in the memory 170 where 2δp and y2 are stored together with the flag 1 bit . these are read out into the respective registers provided therefore and replace the digital information which has just previously been read out . when flip flop 214 is set , it disenables the gate 218 whereby the address counter 180 cannot advance but holds the location from which the last readout has occurred . shortly after the readout from the memory 170 , the flag 2 bit resets flip flop 214 enabling address counter 180 to continue addressing the memory 170 through its now enabled gate 186 . in the manner described , the read out from the memory 170 will first provide the data which was written into the memory at the end of the sector , and will then provide , in sequence , the coordinate data from that sector . it will then proceed to replace the sector data with the data for the following sector , followed by the coordinate information for that sector . the memory 170 may be sequenced through its reading cycle in response to es pulses while the memory 190 may be sequenced through its reading cycle , also in response to pulses from the es counter . the es counter is provided with a sufficient count capacity to take care of all of the recordations required for the sectors . fig8 is a block schematic diagram of the further processing of the xij signal which has been read out into the register 220 . the xmin signal , which was stored in the min latch 98 , in fig3 is subtracted from each xij coordinate read out of the memory 170 into register 220 by a subtractor circuit 223 . a multiplier 224 , then multiplies the difference by the kx scaling factor that was calculated in fig3 and held in register 104 . multiplier 224 is enabled to multiply in response to each es output from the gate 218 , shown in fig7 . the output of the multiplier 224 is applied to an adder 226 , which adds to the scaled xij the δp displacement in register 208 , producing an output designated as x ij &# 39 ;. if a displacement from the side of x plot is desired , then the digital representation of this displacement may be provided by a δt source 228 , and added to an x ij &# 39 ; by an adder 230 . the resultant , x ij &# 34 ; signal may be placed in a register 232 or transferred into a memory along with the finally processed y . sub . ij signal , or may now be displayed on a display device , such as a crt , along with finally processed y ij &# 34 ; signals . fig9 shows the further processing required for the y ij signals . each y ij signal , which is read out of the memory 170 has subtracted from it the yj signal which is the average value for the sector . subtraction is provided by a subtraction circuit 234 , to which the y ij and y j signals are applied . the output of the subtractor circuit , which is designated as y ij &# 39 ;, is applied to a multiplier 236 . the other input to the multiplier is the ky scaling factor , which was generated by the circuitry shown in fig6 . the multiplier is enabled by es2 - n signals from gate 218 in fig7 . the output of the multiplier 236 is designated as y ij &# 34 ; and is the scaled coordinate which can be plotted along with the corresponding x ij &# 34 ;, which was generated in the circuitry shown in fig8 . as shown in fig1 , the y ij &# 34 ; and x ij &# 34 ; may be sequentially stored in a memory 240 , or may be displayed if desired on a cathode ray tube device . in the display mode , a point is illuminated on the face of a cathode ray tube , for instance at each x ij &# 34 ;, y ij &# 34 ; coordinate . if desired , in order to render distinctions between successively written signatures , if they exist , the pressure samples shown being taken in fig2 may be stored in the memory with each x ij and y ij coordinate . the pressure sample pi is read out of memory with each associated x ij and y ij coordinate held in a register until the x ij and y ij signals are processed into x ij &# 34 ; and y ij &# 34 ; and then either stored , as represented in fig1 with x ij &# 34 ; and y ij &# 34 ; for future display , or used immediately to modulate the brightness of each x ij and y ij coordinate shown on a crt . storage of the indicated data for a plurality of signatures and the ability to recall the data from storage by properly addressing the storage , is a technique which is well - known by those skilled in the computer art and thus will not be described here . fig1 illustrates one manner in which this system may be used . the x ij &# 34 ; and y ij &# 34 ; signals derived from a signature are recorded in a card , either in the form of magnetic signals on a magnetic stripe , or as embossed symbols . the card may be inserted in a card reader 242 , which scans the recorded coordinate information and applies these signals to a suitable display device 244 , such as a cathode ray display device 244 . a pen 246 is then used by the person who wishes to show that he is the correct card holder , for writing a signature corresponding to the one on his card . signal processing circuits 248 such as those described in fig1 through 9 convert the signals received from the pen 246 into the coordinate signals which are then applied to a display device 250 to be displayed thereby . the signatures displayed on both display devices are then compared to determine whether or not the card holder is the individual who should be having it and using it . another system for using this invention is schematically represented by fig1 . here the pen 246 is used by the individual who wishes to be identified , to write a signature . the output of the pen 246 is applied to the processing circuit 248 which in turn produce the x and y coordinate signals which are applied to the display device 250 to be displayed . a card reader 252 is employed to read an address which is embossed or magnetically recorded on a card , which is the address in a central computer memory of the location where the coordinates of an original signature of the individual who was using the card is supposed to be stored . this address information is applied to a communication system 254 , which supplies it to a memory address circuit 256 , at a central location . the memory address circuit then addresses the memory 258 , which provides as an output the x ij &# 34 ; and y ij &# 34 ; coordinates . these are transmitted through the communication system 254 to a second display device 260 , which is located at the place where the individual is signing his signature . a comparison of display devices 250 and 260 can then readily determine whether or not the card holder is indeed the individual who should be holding it . fig1 shows still another way in which the system described may be used . a copy is made on a card of the appearance of a signature which has been processed and displayed on a crt for example . the person who wishes his signature verified then uses the pen 264 to write his signature . the signals generated by the pen are processed by the processing circuits 266 and then displayed for comparison by the display device 268 . the system which has been described herein is one which not only can be built as a hardwired special purpose computer but also , those skilled in the art who are given this disclosure can program a general purpose computer to perform the sequence of processing steps required to convert the force signals generated by a pen into the coordinate signals x ij &# 34 ; and y ij &# 34 ; which are either stored for further use or displayed . attached hereto , as an appendix to this specification , but still a part hereof , are flow charts illustrating the sequence followed by a general purpose computer in response to a program instructing it to perform the operations described herein . also attached hereto is a computer print out of a program for a general purpose computer which instructs the computer to perform the processing of pen signals as described above , and then to display the coordinate signals which have been derived . the program instructs the computer to follow the sequence described in the flow charts . accordingly , it is intended that both the hardwired computer and a programmed general purpose computer be encompassed within the scope and spirit of the claims herein . ## str1 ## ## spc1 ## ## spc2 ##