the present invention , which provides a process of fabricating a trench capacitor semiconductor memory device having a temperature sensitive high dielectric material incorporated into the storage node of the capacitor , will now be described in greater detail by referring to the drawings that accompanying this application . it is noted that in the various drawings like elements or components are referred to be like and corresponding reference numerals . before describing the process of the present invention it is again emphasized that the process of the present invention overcomes the drawbacks in prior art deep trench semiconductor memory cells by forming the trench storage region after the sti regions and preformed layers of a gc stack are formed . by forming the storage trench after high temperature sti and gc processing , the temperature sensitive high dielectric constant material formed in the storage trench of the memory cell does not degrade and thus it does not interact by diffusion with the underlying semiconductor material . furthermore , in the present invention the buried - strap outdiffusion does not see several high temperature processing steps which contribute to large buried - strap outdiffusion in the prior art . thus , the lateral outdiffusion of the buried - strap formed in the present invention is significantly reduced as compared with prior art memory cell structures . with this in mind , attention is directed to fig3 ( a ) which shows an initial semiconductor structure which is employed in step ( a ) of the present invention . specifically , the semiconductor structure shown in fig3 ( a ) comprises a semiconductor substrate or wafer 10 having at least one storage trench region 12 and a raised shallow trench isolation ( sti ) region 14 adjacent to storage trench region 12 formed therein . the structure further comprises preformed layers 16 of a partial gate conductor stack formed thereon which are spaced apart by storage trench region 12 and raised sti region 14 . semiconductor substrate or wafer 10 is composed of any semiconducting material including , but not limited to : si , ge , sige , gaas , inas , inp and all other iii / v compounds . of these semiconducting material , it is preferred that semiconductor substrate or wafer 10 be composed of si . the semiconductor substrate or wafer may be of the p - type or the n - type depending on the type of semiconductor memory device being manufactured . the preformed layers of the partial gate conductor shown in fig3 ( a ) are composed of a bottom gate oxide layer 16 a such as sio 2 , a middle layer of polysilicon 16 b and a top polish stop layer 16 c such as si 3 n 4 . the layers are formed sequentially on the surface of the semiconductor substrate or wafer starting with layer 16 a , then 16 b and finally 16 c . the structure shown in fig3 ( a ) is fabricated using conventional techniques well known to those skilled in the art . for example , the structure shown in fig3 ( a ) can be fabricated as is shown in fig4 ( a )-( d ). specifically , as is shown in fig4 ( a ), a semiconductor substrate or wafer 10 is first provided and gate oxide layer 16 a is grown on the surface of semiconductor substrate or wafer 10 using conventional thermal growing techniques well known to those skilled in the art . this includes heating the semiconductor substrate or wafer in an oxygen ambient at a temperature of from about 800 ° to about 1100 ° c . until a gate oxide having a thickness of from about 4 to about 10 nm is formed on the surface of the semiconductor substrate or wafer . next , a layer of polysilicon 16 b is formed on the surface of gate oxide 16 a using standard deposition techniques well known to those skilled in the art . suitable deposition processes that may be employed in forming polysilicon layer 16 b include , but are not limited to : chemical vapor deposition , plasma vapor deposition , low pressure chemical vapor deposition , high density chemical vapor deposition and other like deposition processes . the thickness of the polysilicon layer formed is typically in the range of from about 10 to about 500 nm . polish stop 16 c is then formed on polysilicon layer 16 b using standard deposition techniques , including those mentioned above , that are well known to those skilled in the art . the polish stop is composed of a conventional material such as si 3 n 4 which resists erosion during subsequent planarization and etching steps . the thickness of the polish stop layer formed is typically of from about 10 to about 500 nm . the next step in forming the structure of fig3 ( a ) is illustrated in fig4 ( b ). specifically , fig4 ( b ) shows a structure which contains a trench 14 a which is formed in layers 16 a , 16 b , and 16 c as well as the surface of semiconductor substrate or wafer 10 . it is noted that trench 14 a is used in forming sti region 14 . the structure of fig4 ( b ) is fabricated using standard lithography , etching and planarization , all of which are well known to those skilled in the art . specifically , the structure shown in fig4 ( b ) is fabricated by providing a conventional resist having a preformed pattern on top of layer 16 c of the structure shown in fig4 ( a ) using standard deposition techniques which include spin - on coating and dip coating . the pattern is then etched by standard etching techniques well known to those skilled in the art through layers 16 c , 16 b , 16 a as well as into semiconductor substrate or wafer 10 . suitable etching techniques that can be employed include , but are not limited to : reactive ion etching ( rie ), plasma etching and ion beam etching . the depth that etching is performed into the semiconductor substrate or wafer is typically of from about 100 to about 700 nm . it should be noted that the resist is removed at this time using conventional stripping techniques well known to those skilled in the art . a thermal silicon dioxide layer , not shown in the drawings , is then grown in the trench of the raised sti region using conventional thermal growing techniques , including the use of an oxygen - containing ambient and heating to a temperature of from about 750 ° to about 1100 ° c . the thickness of the grown silicon dioxide layer in trench 14 a is typically of from about 3 to about 30 nm . a sti dielectric , not shown in the drawings , is then formed over the thermal silicon dioxide layer using standard deposition techniques such as low pressure chemical vapor deposition or a plasma - assisted process . suitable sti dielectrics include , but are not limited to : high density plasma tetraethylorthosilicate ( hdp teos ) oxide . it should be noted that in the drawings of the present invention , the above two components , i . e . thermal silicon dioxide layer and sti dielectric are not shown . instead , sti region 14 is meant to include those two components as well as others that may be present in a conventional sti region . to provide a planar structure , as is shown in fig4 ( b ), the structure is then planarized using standard planarization techniques well known to those skilled in the art , including , but not limited to : chemical mechanical polishing , rie and grinding . [ 0049 ] fig4 ( c ) shows the next steps employed in fabricating the structure illustrated in fig3 ( a ). specifically , to the planarized structure of fig4 ( b ) there is formed a hard dielectric mask layer 18 , e . g . boron doped silicon dioxide ( bsg ), which is then patterned utilizing standard lithography techniques and reactive ion etched to remove a portion of the hard dielectric mask . the patterned structure is shown in fig4 ( c ). next , a storage trench 20 is formed in semiconductor substrate or wafer 10 using hard dielectric layer 18 as a masking film . specifically , rie using reactive gases such as hbr , nf 3 , o 2 or he is employed in fabricating storage trench 20 . by “ storage trench ” it is meant that etching is performed to a depth of from about 1 to about 10 μm . the structure containing storage trench 20 which forms the capacitor region of the device is shown in fig4 ( d ). hard dielectric mask 18 is then removed by an hf - etching process to provide the structure shown in fig3 ( a ). it is again emphasized that the above description provides one way of fabricating the structure shown in fig3 ( a ). other ways of fabricating the structure shown in fig3 ( a ) are also known and are thus contemplated herein . in accordance with step ( b ) of the present invention , a bottom electrode 22 is then formed in storage trench 20 ( bottom wall , sidewalls as well as areas outside the deep trench ) using conventional deposition techniques well known to those skilled in the art . for example , bottom electrode 22 can be formed by chemical vapor deposition , metallo - organic chemical vapor deposition , electroplating or electrodeless plating . the material employed in forming bottom electrode 22 includes any conductive oxide which is typically used as a bottom electrode of a capacitor . exemplary conductive oxides include , but are not limited to : ruo 2 , srruo 3 , la — sr — co — o , iro 2 and other like conductive oxides . in addition to conductive oxides , metals such as pt or ir can also be used as the bottom electrode . the structure containing bottom electrode 22 is shown in fig3 ( b ). in an optional embodiment of the present invention , a diffusion barrier layer is formed in storage trench 20 prior to forming bottom electrode 22 . suitable diffusion barrier layers that can be optionally employed in the present invention include , but are not limited to : tin , tialn , tasin , cosi and other like materials which are capable of preventing the diffusion of oxygen into the semiconductor substrate or wafer . chemical vapor deposition or physical vapor deposition are two deposition processes that can be employed in the present invention in forming the optional diffusion barrier layer . after formation of bottom electrode 22 , a layer of a temperature sensitive high dielectric constant material 24 is formed on the surface of the bottom electrode , see fig3 ( c ). the term “ temperature sensitive ” is used herein to denote a material which when in contact with silicon and heated to temperatures over 600 ° c . oxidizes the silicon and degrades by reacting with silicon or by breaking up into other compounds . the temperature sensitive high dielectric constant material utilized herein is however not in direct contact with silicon . it nevertheless becomes unstable by itself at temperatures of about 550 ° c . and above . on the other hand , the term “ high dielectric constant material ” denotes a material which has a dielectric constant relative to a vacuum higher than about 7 . more preferably , the high dielectric constant material employed in the present invention has a dielectric constant of from about 20 to about 10 , 000 . suitable temperature sensitive high dielectric constant materials that can be employed in the present invention include perovskite - type oxides such as barium strontium titanium oxide ( bsto ), lead zirconium titanium oxide ( pzto ), strontium bismuth tantalate ( sbt ) and ta 2 o 5 . the temperature sensitive high dielectric constant material is formed on bottom electrode 22 using standard deposition processes including chemical vapor deposition or sputtering . a top electrode 26 is then formed on top of temperature sensitive material 24 utilizing standard deposition techniques such as chemical vapor deposition . the top electrode may be composed of the same or different conductive oxide as the bottom electrode . thus , top electrode 26 may be composed of ruo 2 , srruo 3 , la — sr — co — o and iro 2 . alternatively , pt or ir can be employed . the structure containing top electrode 26 is shown in fig3 ( d ). in an optional , but highly preferred embodiment of the present invention , a conducting barrier layer is formed over top electrode 26 prior to filling the trench with polysilicon 28 . this conducting barrier layer which is formed by conventional deposition processes serves to prevent interaction between the temperature sensitive high dielectric constant material and the polysilicon . tin , tialn , cosi and tasin are some examples of conducting barrier layers that may be employed in the present invention . for clarity , the conducting barrier layer is not shown in the drawings . the remaining portion of storage trench 20 is filled with polysilicon 28 , preferably n +- doped polysilicon , using standard deposition processes and then the polysilicon is recessed using a dry etch containing gas such as sf 6 , he , o 2 or nf 3 to a depth of from about 0 . 5 to about 1 . 5 μm . the structure obtained from these combined steps of the present invention is shown in fig3 ( e ). it should be noted that the recess process mentioned above and the description that follows regarding fig3 ( f )-( j ) refers to processing steps that are employed in the present invention in fabricating the capacitor in the storage trench region . next , as is shown in fig3 ( f ), a conformal insulating collar oxide 30 is then formed over the semiconductor substrate or wafer 10 and the sidewalls of storage trench 20 which were again left exposed by the above recess process . the conformal insulating collar oxide is formed by conventional deposition processes such as low pressure chemical vapor deposition or plasma - assisted chemical vapor deposition to a thickness of from about 10 to about 30 % of the storage trench diameter . dry etching using an anisotropic removal processing gas such as c 4 f 8 , ch 3 f , cf 4 , c 3 f 8 , co , o 2 or ar is then employed so as to etch material from the wafer plane and the bottom of storage trench 20 , but leaving material along the sidewalls of the storage trench . the trench is then filled with low pressure chemical vapor deposited polysilicon 32 which may or may not be doped and planarized utilizing a dry etch or chemical mechanical polishing process . as shown in fig3 ( g ), the low pressure chemical vapor deposited polysilicon is then recessed to a predetermined depth , e . g . 20 to 50 nm , utilizing a dry etch process such as previously described hereinabove . the collar dielectric is then removed using a hf containing etch from upper regions of the storage trench , see fig3 ( h ). the next steps employed in the present invention in completing the fabrication of the capacitor in the storage trench , which is shown in fig3 ( i ), comprise depositing a low pressure chemical vapor deposition polysilicon layer 34 which may or may not be doped over the structure and then recessing using an anisotropic dry etch process containing gases such as hbr , cl 2 , hcl , sf 6 , he or o 2 to a depth of from about 5 to about 30 nm below the surface of semiconductor substrate or wafer 10 . capacitor 36 is then completely fabricated in the storage trench by forming a trench top oxide ( tto ) dielectric film 38 and planarizing to the top of layer 16 c , see fig3 ( j ). the tto dielectric film is formed by conventional deposition processes including low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition and planarization is carried out using one of the previously mentioned planarization techniques , e . g . chemical mechanical polishing . [ 0064 ] fig3 ( k ) shows a structure which includes a completely formed gate conductor stack which includes preformed gate conductor layers 16 a and 16 b , as well as a polysilicon layer 16 d , a salicide layer , i . e . wsi , 16 e and cap layer , si 3 n 4 , 16 f . polysilicon layer 16 d is formed using the same deposition techniques as is described for polysilicon layer 16 b . layer 16 e is formed by chemical vapor deposition or sputtering and it has a thickness of from about 20 to about 200 nm . in regard to cap layer 16 f , that layer is formed by low pressure chemical vapor deposition and it has a final deposited thickness of from about 20 to about 300 nm . it should be noted that barrier layer 16 c is removed prior to depositing layers 16 d , e and f . the various gate stack layers are then patterned using conventional lithography and a rie dry etch process stopping in gate oxide layer 16 a and the tto / sti oxide , see fig3 ( l ). a gate sidewall oxidation may be done by conventional process . sidewall spacers 42 , e . g . si 3 n 4 , are formed over the patterned gate conductor stack 40 a using deposition techniques well known to those skilled in the art . the semiconductor memory structure is then fully fabricated as follows : source / drain diffusion regions 50 are formed in the semiconductor substrate or wafer 10 using conventional ion implantation followed by appropriate annealing steps . in fig3 ( l ), 50 a represents a bitline diffusion region and the mosfet region of the memory cell is defined as comprising patterned gate stack region 40 a , region 50 and region 50 a . the gate sidewall oxidation and junction anneal steps mentioned hereinabove drive the n + dopant from polysilicon region 28 through polysilicon regions 32 and 34 forming a limited buried - strap outdiffusion region 44 . the limited buried - strap outdiffusion region of the present invention has a lateral dimension 52 of less than 50 nm . more preferably the lateral dimension 52 of the buried - strap is from about 15 to about 30 nm . an insulating layer 46 such a boron - phosphorous doped glass is deposited over the structure covering patterned gate conductor regions 40 a , exposed gate oxide region 16 a , and capacitor 36 using conventional deposition processes such as spin - on coating and chemical vapor deposition . insulating layer 46 is then planarized using one of the aforementioned planarization techniques , and borderless diffusion contacts 48 are formed by standard lithography , dry etching , depositing a polysilicon layer and planarization . it is noted that the memory cell of fig3 ( l ) is unlike prior art memory cells since the lateral outdiffusion of the buried - strap is significantly reduced as compared with prior art structures . more the distance , δ 2 , is greater for the inventive structure as compared with prior art structures , like the type shown in fig1 . this greater distance means that the off - current problem typically observed with prior art structures is significantly reduced herein . in a dram cell in which the designed distance 43 between the near edge of the trench capacitor and the far edge of the gate conductor stack 40 a is about 1 . 5 times a minimum feature size f of 0 . 15 μm , the distance 62 is nominally at least 50 % of the distance 43 . a distance δ 2 , of nominally 75 % or greater can be achieved with the process disclosed herein for a 7f 2 dram cell with f equal to 0 . 15 micron . while the present invention has been particularly shown and described with respect to preferred embodiments thereof , it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made without departing from the spirit and scope of the present invention .