the synchronization circuit according to the invention is suitable for all applications in which data are transmitted cdma - coded . it can be used directly for processing an external signal derived from a received signal if the fundamental sequence is an m - sequence , but use for processing cdma - coded signals which use other types of fundamental sequences , such as , for example , gold sequences or kasami sequences , is also possible . each m - sequence can be generated by a binary feedback shift register of length n and has , inter alia , the property that , with one exception , each sequence of a length n — in the case presented below as an example , n is 10 — occurs exactly once in the m - sequence of length n = 2 n − 1 — in this case 1023 . various representations are possible for the binary quantities and their logic operators . most familiar is the representation by 0 and 1 with the addition modulo 2 ( also known as exclusive - or logical combination ) ( b 1 , b 2 )→ b 1 ⊕ b 2 as both an associative and a commutative relationship , according to the following table : the logical combination of an element with the zero element 0 leaves the former unchanged while the logical combination with 1 converts 0 into 1 and 1 into 0 . leads to the following representation , which is equivalent but more easily implemented and which is used in the embodiment : ( p 1 , p 2 )→ p 1 { circle over ( x )} p 2 =− p 1 · p 2 . ( 2 ) − 1 is the zero element . the logical operation can evidently be readily extended to include any real numbers , i . e . analog values . each m - sequence p 1 , . . . , p n with n = 2 n − 1 can be generated , starting from an initial sequence p 1 , . . . , p n of length n which does not consist exclusively of zero elements , by recursively forming further values according to the pattern : p i = p i − n { circle over ( x )} p i − rm { circle over ( x )} . . . { circle over ( x )} p i − r1 , ( 3 ) where 0 & lt ; r 1 & lt ; . . . r m & lt ; n and the polynomial x n + x rm + . . . + x r1 + 1 is prime with respect to the arithmetic defined above . for example , in each case may apply . since all n possible segments of length n , apart from the segment consisting only of zero elements , are passed through before the initial sequence recurs , the choice of the latter is of no importance . on transmission of cdma - coded data , each transmission channel is characterized by a specific fundamental sequence which is repeated constantly . a section of a possible fundamental sequence is shown in fig3 . for each data bit , usually several , e . g . twenty , copies of the fundamental sequence are transmitted . they are logically combined with the respective data bit so that the fundamental sequence occurs either in unchanged form or is inverted , depending on the value of said data bit . the synchronization circuit according to the invention comprises ( fig1 ) an analog feedback shift register 1 and a buffer 2 in front of it . the buffer 2 comprises an adder 3 and a shift register 4 with 1023 memory locations for analog values . the output of the shift register 4 is fed back to the second input of the adder 3 . the analog feedback shift register 1 comprises an adder 5 and an analog shift register 6 with ten memory locations . a feedback circuit 7 is connected to taps at the tenth memory location and at a further memory location or a plurality of further memory locations . in the example , corresponding to ( 4 ), only one further tap is present at the third memory location . in the feedback circuit 7 , the tapped analog values are combined according to a feedback function . the graph of a possible feedback function with two arguments f ( x 1 , x 2 ) is shown in fig2 . the output of the feedback circuit 7 is connected via a gain block 8 to the second input of the adder 5 . the output of the gain block 8 is moreover connected to a discriminator 9 which comprises a squaring circuit or another circuit mapping the input signal into the positive domain , a low - pass filter and a threshold value detector and outputs a binary signal . the discriminator may also be connected to any other point of the loop formed by the shift register 6 , the feedback circuit 7 , the gain block 8 and the adder 5 . the input signal is present as a digital signal of a specific bit resolution , e . g . 12 bit for the magnitude and an additional bit for the sign . the values may be represented as floating point numbers or as integers . however , they are designated below as analog values for distinction from binary values . the input signal contains a binary sequence which can be generated by a binary feedback shift register which has the same feedback pattern as the analog feedback shift register 1 , i . e . in the case presented a feedback pattern in which in each case the new value is generated by logical operation according to ( 4 ). however , there may be a very strong background noise , the typical signal / noise ratio being , for example , − 35 db . the analog values of the input signal , which are elements of an input sequence , first enter the buffer 2 . there , a plurality , for example , twenty , instances of consecutively determined sequences of in each case 1023 values , each of which corresponds to a fundamental sequence with added background noise — which after all is sent twenty times in succession for transmitting one data bit — are superposed , i . e . the 1023 analog values of the first instance which correspond to the chips of the fundamental sequence are stored in the memory locations of the shift register 4 and then fed back sequentially to the adder 5 , and the corresponding values of the second instance are added thereto and the original value is overwritten with the result . this is repeated until the sum of the twenty instances is stored in the shift register 4 . since , in the summation , the noise is superposed only in an uncorrelated manner , a substantial improvement of the signal / noise ratio can be achieved thereby . if , however , the data bit value changes during the summation and the corresponding fundamental sequence is inverted , the summation can also lead to partial cancellation . in this case , however , no synchronization occurs within a specific time span with regard to this fundamental sequence which then leads to termination and filling of the shift register 4 with new data , as will be explained further below . the basic sequence stored in the buffer 2 is now read out repeatedly for generating an external sequence and in each case fed to the input of the analog shift register 1 . since the fundamental sequence may be inverted by logical combination with the data bit , two analog shift registers can also be used , the external sequence being fed via an inverter to one of them . that analog feedback shift register 1 which receives an advantageous sequence , i . e . one which contains a component as similar as possible to the coded fundamental sequence p 1 , . . . , p 1023 , should now generate therefrom an internal sequence a 1 , . . . , a 1023 which corresponds to this fundamental sequence and which should moreover agree with the external sequence in terms of the phase position . the external sequence corresponds to repetitions of the basic sequence which contains the fundamental sequence p 1 , . . . , p 1023 with background noise added . for the stability and the synchronization behaviour in the case of large negative signal / noise ratios , the choice of a suitable feedback function f is of considerable importance . with the functions known to date , it has not been possible to achieve any synchronization in the case of sequences with a high background noise . in the search for more suitable feedback functions , various features have proved advantageous . thus , in the chosen representation of the binary values — in other representations some of the properties have to be appropriately transformed — they should as far as possible have the following properties . the feedback function should substantially be a linear combination of the arguments in each sector which is defined by specific values of the sign of the arguments . the resulting discontinuities at the sector limits can be smoothed , but it has been found that such modifications tend to adversely affect the behaviour and therefore should not be large . if the magnitudes of the arguments are 1 , the magnitude of the feedback value should be slightly less than 1 , preferably between 0 . 90 and 0 . 99 . it is advantageous if the feedback function gives a value of magnitude 1 in the case of arguments of magnitude 1 , i . e . | f ( x 1 , . . . , x m )|= 1 for | x 1 |= . . . =| x m |= 1 , ( 5 ) and the function value is then multiplied by a selectable factor k & lt ; 1 , in particular 0 . 90 & lt ; k & lt ; 0 . 99 . this multiplication is performed by the adjustable gain block 8 , which follows the feedback circuit 7 evaluating the feedback function . the sign of the feedback function should in each case the inverse of the sign of the product of the negative arguments , i . e . sig ( f ( x 1 , . . . , x m ))=− sig ((− x 1 )· . . . ·(− x m )). ( 6 ) if x 1 , . . . , x m each have the magnitude 1 , i . e . can also be regarded as binary quantities , said two properties result in f ( x 1 , . . . , x m ) corresponding to the logical combination x 1 { circle over ( x )} . . . { circle over ( x )} x m . it is furthermore advantageous if the feedback function f is invariant on interchanging the arguments . it should be antisymmetrical and monotonic as a function of each individual argument , i . e . when other arguments are kept constant . a feedback function f which has all the abovementioned properties and with which synchronization could be achieved even in the case of signals with a strong background noise is f ( x 1 , . . . , x m )=− sig ((− x 1 )· . . . ·(− x m ))·(| x 1 |+ . . . +| x m |)/ m ( 7 ) apart from scaling which ensures that ( 5 ) is fulfilled , this function is , in each sector , a linear combination of the arguments with a coefficient of + 1 or − 1 . f ( x 1 , x 2 )=− sig ( x 1 · x 2 )·(| x 1 |+| x 2 |)/ 2 , ( 8 ) it is shown in fig2 only the transitions at the sector limits having been smoothed by linear interpolation . if a representation of binary values other than that in the example described is chosen , the conditions must be appropriately adapted to the feedback function . furthermore , the factor k can , depending on implementation as a fixed or variable quantity , be integrated into the feedback function , which , for example , would require adaptation of the condition ( 5 ). since , thanks to the buffer 2 , the synchronization circuit operates with stored data , its operating speed is independent of the chip rate of the received signal and may be substantially higher . the power of the internal sequence generated , which is tapped at the output of the gain block 8 , serves as a criterion for successful synchronization . while the elements of the internal sequence have about the same value as those of the external sequence before synchronization , the latter is amplified after synchronization by a factor of 1 /( 1 − k ) which is thus usually between 10 and 100 . the power of the internal sequence ( a i ) accordingly increases greatly , as shown in fig4 . this increase is registered by the discriminator 9 , in which the power is determined by squaring and smoothed by filtering through a low - pass filter and averaged over a relatively long time segment and finally the result compared with a threshold value . a corresponding binary signal which indicates the completed synchronization is output . if no synchronization occurs after a certain time , there is generally no sense in continuing the procedure with the same data . the lack of synchronization may be accidental , for example due to a particularly unfavourable form of the noise component , due to an unfavourable phase position of the received signal or due to an unfavourable sampling time before a data bit change , which leads to instances of sequences in which the component containing the desired fundamental sequence occurs with different signs being added in the buffer 2 ( fig1 ), which can lead to a serious attenuation of said component compared with the noise component . in such cases , it is expedient to fill the buffer 2 with a new basic sequence and to restart the synchronization process with it . there are of course various possible deviations from the example described . thus , especially in the case of good quality of the input signal , the buffer need not be present and the input sequence can be fed directly as an external sequence to the input of the analog feedback shift register . there are also various possibilities for implementation ; in particular , different degrees of integration can be chosen . the stated parts of the synchronization circuit need by no means be present as separate components . the shift register can , for example , be formed in each case by a corresponding memory with linear addressing and a write pointer and a read pointer .