the present teaching relates to an improved apparatus and method for generating a large δv be without using a large number of transistors and without increasing the input voltage beyond that of a non - stacked bandgap cell . consequently , δv be can be increased without consuming a large die area . in addition , the present teaching also aims at enhancing the performance of bandgap references via increasing the voltage of a δv be generator with reduction in bandgap output voltage noise . in accordance with the present teaching , to reduce the number of transistors used in producing a larger δv be , stacking is applied . for instance , to produce a δv be of 108 mv at 25 ° c ., two stacks each having an 8 : 1 ratio can be used . therefore , a total of 18 transistors can achieve the same level of performance as 65 transistors used in the prior art . this yields a significant reduction of transistors used , which provides exponential reduction in the number of transistors . although prior art solutions also adopt stacking , the present teaching stacks multiple δv be s in a manner that does not increase noise , but rather decreases noise , and no additional input voltage beyond that of a non - stacked architecture is required . that is , the same input voltage required for a single δv be stack is used for a δv be generator with multiple stacks with the same δv be voltage . using a similar example as discussed previously , without stacking , to achieve a δv be of 216 mv , a ratio of 2191 : 1 transistors would be required . in accordance with the stacking approach disclosed herein , four stacks each having an 8 : 1 ratio can be used to achieve 216 mv of δv be with the same input voltage . in other words , theoretically 36 transistors could achieve the same level of performance as 2192 transistors without increasing the input voltage and still minimizing the noise . the present teaching is illustrated in fig4 having stacking shown with respect to a dobkin cell . as shown , a stacked bandgap reference circuit 400 comprises two levels of δv be generators . the stacked bandgap reference circuit 400 comprises an error amplifier 465 , a current source path ( a current source 415 and a diode connected transistor 420 ), a sub - circuit connecting between the output of the error amplifier v out and the ground ( resistors r 3 a 470 , r 3 475 , r 4 480 , and q 3 485 ), a first stack ( transistors 430 , 435 , and 445 ) and a second stack ( transistors 450 , 455 , and 460 ). although prior art may also stack δv be s , the present teaching stacks additional δv be s in a way so that no additional input voltage is needed beyond that of a non - stacked bandgap cell . moreover the stacking occurs where the δv be resistor is between the base terminal of the bjts . to increase δv be , the illustrated embodiment shows that the first level of δv be can be directly supplemented by adding a resistor , shown as r 3 a 470 , on top of the existing resistor , r 3 475 , and an additional emitter ratioed differential pair 450 and 455 with both emitters connected to transistor 460 to the ground . it is understood that although the illustrated embodiment applies stacking in the context of the dobkin cell , the present teaching is not limited to such a particular context . in some embodiments , identical stages may be employed . that is , the tail current sources q 5 435 and q 6 460 are identical . the δv be generators , q 1 430 / q 2 445 and q 1a 450 / q 2a 455 , also have identical current density ratios , say n . the current density ratio can be set by varying the emitter areas , the currents , or both in the corresponding δv be devices . consider a dobkin cell where a δv be generator comprises q 1 , q 2 , and r 3 . an expression to describe the circuit by going around a closed loop containing these devices is where v r3 is the voltage drop across r 3 475 and v be1 and v be2 are the emitter base voltages of devices q 1 430 and q 2 445 , respectively . as one skilled in the art of bandgap reference design would recognize , v be = v t * ln ( i c /( i s * a )) where v t is the thermal voltage , i c is the collector current , i s is the saturation current , and a is the emitter area . the argument of the natural logarithm term is called the current density as earlier denoted as j . the voltage across r 3 is given by the expression v r3 = i 1 * r 3 , where i 1 is the current through r 3 . combining the natural logarithm terms discussed above , this equation becomes where n is the current density ratio of devices q 1 430 and q 2 445 . when stacking is applied in a manner as disclosed herein , the expression for v out can be similarly derived . referring to fig4 where a stacked dobkin cell is shown , based on the closed loop formed by different devices , v out can be expressed as assuming that the base currents of q 1 , q 2 , q 1 a , q 2 a can be ignored , this expression can be rewritten as v out =*( r 3a + r 3 + r 4 )+ v be3 where i 1 is the current in resistor r 3a 470 , r 3 475 , r 4 480 , and q 3 485 without the base currents . considering the closed loop containing the two stacked δv be generators , we have v r3a + v r3 + v be1 − v be2 + v be1a − v be2a = 0 i 1 = v t /( r 3a * r 3 )* ln ( n 2 ). substituting the previous equation , we can derive the expression for v out as follows v out =( 1 + r 4 /( r 3a + r 3 ))* v t * ln ( n 2 )+ v be3 in this expression , the first term corresponds to the ptat term and the second term corresponds to the ctat term . the natural logarithm term includes an exponent denoting the multiplying effect of stacking two δv be generators . by mathematical operation , the exponent in the natural logarithm term can be moved to the front of the ptat term , making clear the multiplicative effect of the stacking described herein . that is v out = 2 *( 1 + r 4 /( r 3a + r 3 ))* v t * ln ( n )+ v be3 . the effect of the added stage is apparent in this derived equation where the ptat term is doubled . therefore , by stacking δv be generators in accordance with the present teaching described herein , the efficient multiplicative effect makes it possible to have much less die area to achieve the same result . in addition , the stacking as described herein does not need additional larger input voltage , as many architectures that achieve a multiplying effect of current densities would require . the required increase of input voltage for the present teaching is directly proportional to the increase in δv be as would be for a non - stacked architecture such as a widlar or brokaw cell . this is usually on the order of 100 mv . for example , if a 100 mv δv be is desired , using an architecture without stacking , a current density ratio of 48 : 1 is required . this in turn requires a total of 49 transistors . with our embodiment using two identical stages the same δv be can be developed using a current density ratio of 7 : 1 for a total of 16 transistors . when additional increase in δv be is needed , more stages can be added as shown in fig5 where a triple stacked dobkin cell is illustrated , according to an embodiment of the present teaching . with three stacked δv be generators , the expression for the output voltage is v out =( 1 + r 4 /( r 3b + r 3a + r 3 ))* v t * ln ( n 3 )+ v be3 , or v out = 3 *( 1 + r 4 /( r 3b + r 3a + r 3 ))* v t * ln ( n )+ v be3 generally , there is no inherent limit to the number of stages that can be stacked in accordance with the present teaching . when there are k stages stacked together , assuming k identical stages each having current density ratio n : 1 , a general expression for the output voltage can be derived as v out = k *( 1 + r 4 /( k * r 3 ))* v t * ln ( n )+ v be3 it is clear that the natural logarithm of the product of transistor ratios increases exponentially with respect to a conventional bandgap without a stacked δv be generator . the above discussion assumes that r 3 = r 3a = r 3b . . . and the emitter ratios , n , of the differential pairs are perfectly identical . in practice due to mismatches in manufacturing , this will not be the case . however , the current ratio in the differential pairs will be close enough to dynamically adjust so that the ptat current through r 3 is equal to the ptat current through r 3a . as discussed herein , the stacking according to the present teaching also reduces noise . specifically , noise reduction is achieved by breaking up the δv be cell into multiple devices . when they are broken up , the noise in separate devices are uncorrelated , making the total noise a combination of rss ( root - sum - square ) and , thus , smaller . as someone skilled in the art of analog design would recognize , devices at the input of the amplifier ( e . g ., error amplifier 465 in fig4 and error amplifier 580 in fig5 ) are usually the dominate contributors to noise . in some embodiments , such noise may be reduced by increasing the current density ratio , n . this reduces the noise because it lowers the gain required in the ptat term . in this embodiment , the emitter current density can be made arbitrarily large without much cost in the die area resulting in less gain needed . in addition , the overall ptat resistance from various resistors , e . g ., r 3a , r 3b b , . . . , is now broken up into several individual pieces . in a single stage δv be generator , the noise with respect to this overall resistance is 4ktrb , where k is boltzman &# 39 ; s constant , t is temperature in kelvin , r is the resistance , and b is the bandwidth . that is , when a single stage is used , the noise is a combination of the noise sources from that stage . when stacking as disclosed herein is applied ( e . g ., three stage stacking ), since the overall ptat resistor is broken up into several individual pieces in corresponding stacks , the resulting overall noise is root , sum , squared ( rss ) together as an overall resistance . this is shown in the equation below e nt =( e r3 2 + e r3a 2 + e r3b 2 ) 1 / 2 where e nt is the total noise level and e r3 , e r3a , e r3b are the noise sources from the three individual δv be generators . particularly , when identical stages are stacked , the total noise combined is determined by e ′ n = e n /√ n , where e n is the noise from each stage and n is the number of stages . thus , the total noise level of the stacked δv be generator is √ n times less than that of each of the individual stages . the above discussion is based on specific exemplary embodiments . although not limiting , it is understood that there are various implementations that may be employed to realize the present teaching . for instance , in fig4 and fig5 , the circuit bias currents 415 and 515 are shown coming from a current source . this bias current can also be realized as a resistor . in addition , the current source could be temperature independent , ptat , ctat , or some other variations . the tail current sources , e . g ., transistors q 5 and q 6 in fig4 and q 7 in fig5 can be identical or set to have different values . the emitter ratios or current density of the δv be generators q 1 / q 2 , q 1a / q 2a , and q 1b / q 2b , can be identical or set to different ratios . the resistors r 3 , r 3a , and r 3b , can be identical or set to different values . the collector resistors , r 1 and r 2 , can be identical or set to different values . the discussion above with respect to stacking is based on the assumption that the base current is ignored . consider the double stacked dobkin cell ( shown in fig4 ). a source of output voltage error may occur due to the base currents flowing through transistors q 1 430 , q 2 445 , and q 1a 450 . the current from the error amplifier 465 that reaches resistor r 3 475 is 2 * i b ( combined base currents of transistors q 1a 450 and q 2 445 ) less than the current flowing through transistor r 3a 470 . it reduces by another i b ( base current of q 1 430 ) when the current gets to resistor r 4 480 and transistor q 3 485 . these base currents vary with temperature causing a temperature dependent error which detracts from the temperature independent circuit . when base current is taken into account in the analysis , it can be shown that in addition to the ideal output voltage terms ptat and ctat , an error due to base currents exists . to eliminate this error , fig6 illustrates an exemplary solution . circuit 600 as shown in fig6 includes all similar components as in fig4 with an additional resistor , r 5 657 , inserted between v out and the base of transistor q 2a 655 . to overcome the error caused by base currents , the value of r 5 can be determined as follows r 5 = r 4 *( 3 * r 3a + r 3 )/( r 3a + r 3 + r 4 ) when two identical stages are stacked , i . e ., r 3a = r 3 , this reduces to in some embodiments , as the number of stages and the ratio of emitter areas increase , the δv be ptat term may eventually exceed the v be ctat term , thus effectively eliminating resistor r 4 ( e . g ., resistor 590 in fig5 ) altogether . when this occurs , different exemplary approaches may be employed to boost the ctat term . the first exemplary approach is to employ a v be multiplier . this is illustrated in fig7 , where circuit 700 comprises four stages of stacking , 710 , 720 , 730 , and 740 , an error amplifier 755 , and a sub - circuit connecting the voltage output of the circuit 700 and the ground , including resistors r 3c 760 , r 3b 765 , r 3a 770 , r 3 775 , transistor q 3 780 and resistors r 4a 785 and r 4b 790 . resistors r 4a 785 and r 4b 790 are connected in series with the middle connection point coupled to the base of transistor q 3 780 , one end of the series connected to the collector of transistor q 3 780 , and the other end of the series connected to the emitter of transistor q 3 780 . with this solution , the voltage across the transistor q 3 780 is multiplied by a factor determined based on the ratio of r 4a 785 to r 4b 790 , i . e ., ( 1 + r 4a / r 4b ). this multiplying factor will enable an increase of the ctat term and allow for an even larger ptat term . the second exemplary approach is to employ two v be s and retain resistor , r 4 . this exemplary solution is illustrated in fig8 . in this illustrated embodiment , circuit 800 comprises four stages of stacking , 810 , 820 , 830 , and 840 , an error amplifier 855 , and a sub - circuit connecting the voltage output of the circuit 800 and the ground , including serially connected resistors r 3c 860 , r 3b 865 , r 3a 870 , r 3 875 , r 4 880 , and two transistors q 3a 885 and q 3 890 . the two v be s require a larger ptat term which can be accomplished by increasing δv be through additional stages and / or increasing the value of r 4 880 . the order of devices in the sub - circuit may not be important . for example , the diode connected devices q 3 890 and q 3a 885 need not be arranged together . in some embodiments , another approach may be employed to increase the δv be . this is shown in fig9 , where a cross - coupled v be loop is added within each ptat generator . for instance , in ptat generator 910 , a cross - coupled v be loop 920 is added between a pair of differential transistors and its corresponding tail current source . in ptat generator 930 , a cross - coupled v be loop 940 is added between a pair of differential transistors and its corresponding tail current source . resistors r 5 - r 8 in those added cross - coupled loops are for reducing the g m of the additional devices to keep the circuit stable . the specific illustration of the sub - circuit 960 in fig9 used the same circuit as shown in fig8 . however , any implementation of the same circuitry described herein may be employed . in some embodiments , still another approach may be adopted to increase the δv be within a stage . in accordance with this approach , diode connected devices may be introduced in ptat generators . this is shown in fig1 . for instance , in ptat generator 1010 , a pair of diode connected devices 1020 are added between a pair of differential transistors and their corresponding tail current source . in ptat generator 1030 , another pair of diode connected devices 1040 are added between a pair of different transistors and their corresponding tail current source . the sub - circuit 1060 between the output of error amplifier 1050 and the ground can be implemented in accordance with any of the embodiments discussed herein . using these alternative approaches , an additional diode connected bjt , q 3a , is added to the output string . there are other variations in implementing the present teaching . for example , npn transistors may be replaced with pnp transistors . without deviating from the present teaching , base current cancellation or curvature correction schemes may also be included in the implementations . in some embodiments , currents may be ratioed through δv be cells to increase the δv be . devices used for current source ( s ) or error amplifiers may be based on mosfets . a shunt regulator instead of series regulator may also be employed . in implementing the error amplifier ( e . g ., 460 , 580 , 665 , 755 , 855 , 950 , 1050 in fig4 - 10 ), an architecture different from what is shown in fig3 may be used . in addition , multiple input error amplifiers may also be used . furthermore , in different implementations , an error amplifier therein may be biased differently . rather than using a independent current source 415 , a current can be internally generated and bootstrapped eliminating the need for additional bias circuitry . in some embodiments , the diode connected device q 3 ( see fig4 - 10 ) may be similarly used as in a dobkin cell to gain up the output voltage beyond a bandgap voltage . moreover , components r 3 , r 4 , and q 3 may be interchanged . two or more diode connected devices may be used in the output . a current reference may be alternatively employed in place of a voltage reference . overall , in accordance with the present teaching , a larger δv be can be achieved with fewer transistors without the penalty of a higher input voltage supply or increased noise . a larger δv be translates into a high performance low noise voltage or current reference . while the inventions have been described with reference to the certain illustrated embodiments , the words that have been used herein are words of description , rather than words of limitation . changes may be made , within the purview of the appended claims , without departing from the scope and spirit of the invention in its aspects . although the inventions have been described herein with reference to particular structures , acts , and materials , the invention is not to be limited to the particulars disclosed , but rather can be embodied in a wide variety of forms , some of which may be quite different from those of the disclosed embodiments , and extends to all equivalent structures , acts , and , materials , such as are within the scope of the appended claims .