one example of a semiconductor integrated circuit device according to this invention , as shown in fig1 comprises : an output mosfet circuit including a p - type mosfet q3 and an n - type mosfet q4 ; an intermediate potential setting circuit 2 including a p - type mosfet q1 and an n - type mosfet q2 ; a nand gate 3 including p - type mosfets q5 and q6 and n - type mosfets q7 and q8 ; a nor gate 4 including p - type mosfets q9 and q10 and n - type mosfets q11 and q12 ; inverters 5 and 6 ; an input terminal din ; an output terminal dout ; and a load capacitor cl . further in fig1 reference character dp designates a first output control signal ; dn , a second output control signal ; ps1 , a third output control signal ; ps2 , a fourth output control signal ; and oe , an output enable signal . the operation of the semiconductor integrated circuit device thus organized will be described with reference to a time chart shown in fig2 . when the output enable signal oe is set to &# 34 ; l &# 34 ; from &# 34 ; h &# 34 ;, the first output control signal dp is raised to &# 34 ; h &# 34 ; while the second output control signal dn is set to &# 34 ; l &# 34 ;, and both of the mosfets q3 and q4 forming the output mosfet circuit 1 are rendered non - conductive ( off ). in this case , the output terminal dout is held at &# 34 ; h &# 34 ; or &# 34 ; l &# 34 ; depending on whether the load capacitor cl is charged or discharged . then , the third output control signal ps1 is raised to &# 34 ; h &# 34 ;. in this case ; ( 1 ) if the output terminal dout is initially at &# 34 ; l &# 34 ;, the drain , gate and source of the n - type mosfet q2 forming the intermediate potential setting circuit 2 are &# 34 ; h &# 34 ;, &# 34 ; h &# 34 ; and &# 34 ; l &# 34 ;, respectively , and therefore the mosfet q2 is rendered conductive , so that charging current flows in the load capacitor cl through the mosfet q2 , and the potential of the output terminal dout is increased . ( 2 ) in this operation , the potential of the first output control signal dp is made lower than the &# 34 ; h &# 34 ; level temporarily because the mosfet q2 is rendered conductive ( on ) as was described above . if the decrease of the potential exceeds the threshold value of the p - type mosfet q3 , then the latter q3 is also rendered conductive ( on ). as a result , current flowing through the mosfet q3 is also applied to the load capacitor cl , so that the potential of the output terminal dout reaches the intermediate potential quickly . ( 3 ) on the other hand , immediately after the intermediate potential setting signal ps1 is raised to &# 34 ; h &# 34 ;, i . e ., the gate of the mosfet q1 is set to &# 34 ; l &# 34 ;, the drain , gate and source of the p - type mosfet q1 are at &# 34 ; l &# 34 ;, &# 34 ; l &# 34 ; and &# 34 ; l &# 34 ;, respectively , and therefore the p - type mosfet q1 is non - conductive ( off ). however , when the potential of the output terminal dout increases until the drain - source voltage of the mosfet q1 exceeds its threshold voltage vth , the mosfet q1 is turned on , so that a through - current flows in both the mosfets q2 and q1 . in this case , the source and drain of the p - type mosfet q1 are held lower than &# 34 ; h &# 34 ;, and because of the substrate bias effect the threshold voltage is higher than at the zero bias ( with the source or drain held at &# 34 ; h &# 34 ;) accordingly , the p - type mosfet q1 is turned on later than the n - type mosfet q2 . and , as the channel resistance of the p - type mosfet q1 is higher than that of the n - type mosfet q2 because of the substrate bias effect , the through current is smaller than that in the conventional semiconductor integrated circuit device in which the intermediate potential setting circuit comprises only the n - type mosfets . when the p - type mosfet q1 is turned on , the second output control signal dn is raised from &# 34 ; l &# 34 ;; however , it cannot reach the threshold voltage of the n - type mosfet q4 because of the high channel resistance of the p - type mosfet q1 , and no through current flows in the output mosfet circuit 1 ( q3 and q4 ). ( 4 ) in the case where the output terminal dout is initially held at &# 34 ; h &# 34 ;, the p - type mosfet q1 is turned on immediately when the intermediate potential setting signal ps1 is raised to &# 34 ; h &# 34 ;, so that the load capacitor cl is discharged through the mosfet q1 , and the potential of the output terminal dout is decreased from &# 34 ; h &# 34 ;. in this operation , the second output control signal dn is raised from &# 34 ; l &# 34 ; temporarily , to turn on the n - type mosfet q4 . as a result , the load capacitor is discharged through the mosfet q4 too , and the potential of the output terminal dout reaches the intermediate potential quickly . ( 5 ) on the other hand , the n - type mosfet q2 is turned on after the potential of the output terminal dout is decreased and the drain - source voltage exceeds the threshold voltage of the mosfet q2 . however , since the potentials of the source and the drain of the mosfet q2 are higher than &# 34 ; l &# 34 ;, and because of the substrate bias effect , the threshold voltage vth is higher than at the zero bias time ( the source or drain held at &# 34 ; l &# 34 ;). accordingly , the n - type mosfet q2 is turned on later than the p - type mosfet q1 . and because of the substrate bias effect , the channel resistance of the mosfet q2 is higher than that of the mosfet q1 , and therefore the through current is small . when the mosfet q2 is turned on , the potential of the first output control signal dp is decreased from &# 34 ; h &# 34 ;; however , since the channel resistance of the mosfet q2 is high , the descrease of the potential does not exceeds the threshold voltage of the p - type mosfet q3 , and no through current flows in the output mosfet circuit 1 ( q3 and q4 ). as is apparent from the above description , whether the output terminal is initially held at &# 34 ; h &# 34 ; or &# 34 ; l &# 34 ;, by setting the output enable signal oe to &# 34 ; l &# 34 ; and raising the third output control signal ps1 to &# 34 ; h &# 34 ;, the potential of the output terminal dout can be quickly set to the intermediate potential which is determined by the ratio of resistance of the p - type mosfet q1 and the n - type mosfet q2 . thereafter , by setting the third output control signal ps1 to &# 34 ; l &# 34 ; and raising the output enable signal oe to &# 34 ; h &# 34 ;, the potential of the output terminal dout is set to &# 34 ; h &# 34 ; or &# 34 ; l &# 34 ; according to the level of the input terminal din . as was described above , in outputting data , the potential of the output terminal is changed from the intermediate potential at all times . therefore , the time required for outputting the data is reduced , the peak value of the charging or discharging current accompanying the variation of output is small , and noise induced in the power source line or ground line is suppressed . in the above - described embodiment , the output enable signal oe is controlled by the nand gate 3 and the nor gate 4 to set the first and second output control signals dp and dn respectively to &# 34 ; h &# 34 ; and &# 34 ; l &# 34 ;. this control may be carried out with any means which can set the first and second output control signals dp and dn to &# 34 ; h &# 34 ; and &# 34 ; h &# 34 ;, &# 34 ; l &# 34 ; and &# 34 ; l &# 34 ;, or &# 34 ; h &# 34 ; and &# 34 ; l &# 34 ;,. respectively . in the above - described embodiment , the third and fourth control signals ps1 and ps2 may be any pair of complementary signals opposite in logical value from each other . and the circuitry should be such that the gates of the n - type mosfet q2 and the p - type mosfet q1 are held at &# 34 ; h &# 34 ; and &# 34 ; l &# 34 ;, respectively , for a certain period of time . as was described above , in the semiconductor integrated circuit device comprising the output mosfet circuit and the intermediate potential setting circuit for setting the potential of the output terminal to the intermediate potential prior to variation of the output , the intermediate potential can be set without increasing the through current . therefore , with the semiconductor integrated circuit device of the invention , the data outputting operation can be achieved at high speed , the charging or discharging current of the load capacitor can be reduced in peak value , and noises induced can be suppressed .