reference will now be made in detail to one or more embodiments of the invention . while the invention will be described with respect to these embodiments , it should be understood that the invention is not limited to any particular embodiment . on the contrary , the invention includes alternatives , modifications , and equivalents as may come within the spirit and scope of the appended claims . furthermore , in the following description , numerous specific details are set forth to provide a thorough understanding of the invention . the invention may be practiced without some or all of these specific details . in other instances , well - known structures and principles of operation have not been described in detail to avoid obscuring the invention . an improved programmable logic block architecture is provided for programmable logic devices such as fpgas . this improved architecture may be used regardless of the slice bit size . certain slices within a programmable logic block will not have a one - to - one lut / register ratio whereas other slices within the programmable logic block may possess a one - to - one lut / register ratio . for example , in a 2 - bit slice architecture , a conventional one - to - one lut / register slice such as slice 200 of fig2 may be denoted as an “ type a ” slice . slices having a reduced register / lut ratio may be constructed using a number of alternative embodiments . as seen in fig4 a , a two - bit slice 400 includes a single register 120 for both luts 100 . in this embodiment , a three - to - one multiplexer 405 receives both combinatorial outputs 105 from luts 100 as well as data input 125 to select for a data input d to register 120 . as used herein , two - bit slice 400 will be referred to as a “ type b ” slice . an alternative embodiment for a two - bit slice having a reduced register / lut ratio is illustrated in fig4 b . a two - bit slice 410 includes a first lut 100 a providing a combinatorial output 105 a and a second lut 100 b providing a combinatorial output 105 b . however , in contrast to slice type b , only combinatorial output 105 a may be registered in register 120 . thus , multiplexer 130 selects only between combinatorial output 105 a and data input 125 . combinatorial output 105 b thus cannot be registered in two - bit slice 410 . as used herein , two - bit slice 410 will be referred to as a “ type c ” slice . another alternative embodiment for a two - bit slice having a reduced register / lut ratio is illustrated in fig4 c . a two - bit slice 420 includes two luts 100 wherein each lut provides a combinatorial output 105 as discussed above . however , two - bit slice 420 does not include a register . thus , two - bit slice 420 can only provide combinatorial outputs 105 and cannot provide a sequential output as would be the case if it included a register . because no register is included , two - bit slice 420 does not receive a data input 125 . as used herein , two - bit slice 420 will be referred to as a “ type d ” slice . given these illustrative two - bit slice embodiments having reduced register / lut ratios , their inclusion within a programmable logic block architecture will now be addressed . for example , consider a programmable logic block that includes eight luts . an eight - lut programmable logic block may include 4 two - bit slices . if conventional type a slices were used , this eight - lut programmable logic block would include eight registers . to save die space and eliminate little or seldom - used registers , eight - lut programmable logic blocks are described herein that do not include eight registers . the number of registers may range from seven to zero in an eight - lut programmable logic block having a reduced register / lut ratio . including no registers strongly impacts design flexibility . however , including seven registers provides only minor die space savings . it has been observed that a set of six registers provides a sufficient design flexibility vs . die space savings tradeoff . thus , the following discussion will show various embodiments for a six - register - eight - lut programmable logic block . it will be appreciated , however , that the number of registers within a programmable logic block having a reduced register / lut ratio is not limited to a particular value such as six . turning now to fig5 a , an eight - lut programmable logic block 500 includes three type a slices 200 . because three type a slices 200 will provide six registers 120 ( as can be seen from inspection of fig2 ), the remaining slice in programmable logic block 500 is a type d slice 420 so that the total number of registers 120 equals six . an alternative embodiment is illustrated in fig5 b for a programmable logic block 510 that includes two type a slices 200 . because two type a slices 200 will provide four registers 120 , programmable logic block 510 also includes two type b slices 400 so that the total number of registers 120 equals six . another alternative embodiment is illustrated in fig5 c for a programmable logic block 520 that also includes two type a slices 200 . rather than use two type b slices , programmable logic block 520 includes two type c slices 410 so that the total number of registers 120 equals six . it will be appreciated that other alternative embodiments may also be constructed . for example , as an alternative to two type c slices in programmable logic block 520 , a single type b and a single type c slice could have been included . for illustration clarity , the interconnections described previously within and between the slices in programmable logic blocks 500 , 510 , and 530 are represented by a dotted line 530 . rather than use six registers within each eight - lut programmable logic block , alternative embodiments may be constructed using a different number of registers . for example , fig6 a illustrates an eight - lut programmable logic block 600 that includes two type a slices 200 and two type d slices 420 . thus , programmable logic block 600 includes just four registers 120 . an alternative embodiment for a four - register architecture as illustrated in fig6 b for which an eight - lut programmable logic block 620 includes four type b slices 400 . as seen in fig6 c , a four - register slice architecture may also be achieved using four type c slices 410 in an 8 - lut programmable logic block 630 . a four - register slice architecture may also be achieved using a mixture of type b and c slices . for illustration clarity , the interconnections within and between the slices in programmable logic blocks 600 , 620 , and 630 are represented by a dotted line 640 . as discussed above , the number of bits within each slice need not be limited to two bits . a conventional four - bit slice has a one - to - one register - to - lut ratio and thus has a type a architecture as discussed analogously with respect to fig2 . this ratio may be reduced as seen in fig7 a for a four - bit slice 700 having a type b slice architecture . thus , a combinatorial output 105 a from a lut 100 a or a combinatorial output 105 b from a lut 100 b may be registered in a register 120 a through appropriate selection in a multiplexer 405 a that may also select for a data input 125 a . similarly , a combinatorial output 105 c from a lut 100 c or a combinatorial output 105 d from a lut 100 d may be registered in a register 120 b through appropriate selection by a multiplexer 405 b that may also select for a data input 125 b . a four - bit slice 705 having a type c architecture is illustrated in fig7 b . as discussed analogously with respect to fig4 b , combinatorial output 105 a from a lut 100 a may be registered in a register 120 a through appropriate selection by a multiplexer 130 a . multiplexer 130 a may also select for a data input 125 a . similarly , a combinatorial output 105 c from lut 100 c may be registered in a register 120 b through appropriate selection by a multiplexer 130 b . multiplexer 130 b may also select for a data input 125 b . a combinatorial output 105 b from a lut 100 b and a combinatorial output 105 d from a lut 100 d cannot be registered in slice 705 . a four - bit slice 710 having a type d architecture is illustrated in fig7 c . in a type d slice architecture , no registers are provided to register the lut combinatorial outputs . thus , combinatorial outputs 105 a through 105 d from respective luts 100 a through 100 d cannot be registered in slice 710 . the type a through type d four - bit slices discussed above may be organized in various ways to form eight - lut programmable logic blocks . for example , as seen in fig8 a , a programmable logic block 800 may include a four - bit type a slice 805 and a four - bit type b slice 700 . thus , programmable logic block 800 includes six registers 120 . an alternative embodiment for an eight - lut , 6 - register programmable logic block is illustrated in fig8 b with respect to a programmable logic block 810 . programmable logic block 810 includes a 4 - bit type a slice 805 and a four - bit type c slice 705 . for illustration clarity , the interconnections between the slices in programmable logic blocks 800 and 810 are represented by a dotted line 820 . other eight - lut programmable logic block architectures that incorporate 4 - bit slices may be constructed with less than six registers 120 . for example , as seen in fig9 a , an eight - lut programmable logic block 900 includes a single four - bit type a slice 805 and a single four - bit type d slice 710 . alternatively , as seen in fig9 b , an eight - lut programmable logic block 905 includes two four - bit type b slices 700 . in yet another alternative embodiment as seen in fig9 c , an eight - lut programmable logic block 910 includes two four - bit type c slices 705 . for illustration clarity , the interconnections between the slices in programmable logic blocks 900 , 905 , and 910 are represented by dotted lines 920 . four - bit slices may also be used to construct sixteen - lut programmable logic blocks ( which could also be constructed with two - bit slices ). turning now to fig1 a , a sixteen - lut programmable logic block 1000 includes three four - bit type a slices 805 and a single four - bit type d slice 710 . thus , programmable logic block 1000 includes twelve registers 120 . other sixteen - lut programmable logic block architectures having 12 registers and four - bit slice granularity may be constructed . for example , as illustrated in fig1 b , a programmable logic block 1010 includes two four - bit type a slices 805 and two four - bit type b slices 700 . another alternative embodiment is shown in fig1 c for a programmable logic block 1020 that includes two four - bit type a slices 805 and two four - bit type c slices 705 . for illustration clarity , the interconnections between the slices in programmable logic blocks 1000 , 1010 , and 1020 are represented by dotted lines 1030 . turning now to fig1 a , a sixteen - lut programmable logic block 1100 having eight registers 120 and a four - bit slice granularity is illustrated . programmable logic block 1100 includes two four - bit type a slices 805 and two four - bit type d slices 710 . similarly , as seen in fig1 b , a sixteen - lut programmable logic block 1100 includes four four - bit type b slices 700 . in an alternative architecture illustrated in fig1 c , a sixteen - lut programmable logic block 1120 includes four four - bit type c slices 705 . for illustration clarity , the interconnections between the slices in programmable logic blocks 1100 , 1110 , and 1120 are represented by dotted lines 1130 . the above - described embodiments of the present invention are merely meant to be illustrative and not limiting . it will thus be obvious to those skilled in the art that various changes and modifications may be made without departing from this invention in its broader aspects . accordingly , the appended claims encompass all such changes and modifications as fall within the true spirit and scope of this invention .