in the following detailed description , certain exemplary embodiments of the present invention are shown and described , by way of illustration . as those skilled in the art would recognize , the described exemplary embodiments may be modified in various ways , all without departing from the spirit or scope of the present invention . accordingly , the drawings and description are to be regarded as illustrative in nature , rather than restrictive . fig2 is a view that illustrates a light emitting display device according to an embodiment of the present invention . referring to fig2 , the light emitting display device includes a display region 300 including a plurality of pixels 400 connected to scan lines s 1 to sn and data lines d 1 to dm , a scan driver 100 for driving the scan lines s 1 to sn , a data driver 200 for driving the data lines d 1 to dm , and a timing controller 500 for controlling the scan driver 100 and the data driver 200 . the timing controller 500 generates data driving control signals dcs and scan driving control signals scs corresponding to externally supplied synchronization signals . the data driving control signals dcs generated in the timing controller 500 are supplied to the data driver 200 , and the scan driving control signals scs are supplied to the scan driver 100 . in addition , the timing controller 500 supplies externally supplied data to the data driver 200 . the scan driver 100 is supplied with the scan driving control signals scs from the timing controller 500 . the scan driver 100 supplied with the scan driving control signals scs sequentially supplies the scan signals to the scan lines s 1 to sn . that is , the scan driver 100 selects pixels 400 to be supplied with data signals by sequentially supplying the scan signals to the scan lines s 1 to sn . the data driver 200 is supplied with the data driving control signals dcs from the timing controller 500 . the data driver 200 supplied with the data driving control signals dcs generates currents or voltages ( which may be predetermined ) as data signals corresponding to the gray level values of the data . for example , in a case where predetermined voltages are generated as the data signals , the data driver 200 supplies the data signals to the pixels 400 selected by the scan signals . also , in a case where predetermined currents are generated as the data signals , the data driver 200 is supplied with the predetermined currents from the pixels 400 selected by the scan signals ( current sink ). in either case , the data driver 200 includes at least one data driving circuit 600 , which will be described later in more detail . the display region 300 includes pixels 400 formed in the crossing ( or intersection ) regions defined by the scan lines s 1 to sn and the data lines d 1 to dm . each of the pixels 400 is supplied with a first power of a first power source elvdd and a second power of a second power source elvss . the pixels 400 charge voltages ( or predetermined voltages ) corresponding to the data signals and supply currents corresponding to the charged voltages from the first power source elvdd via organic light emitting diodes ( not shown ) to the second power source elvss to display images with a brightness ( or a certain brightness or a predetermined brightness ). fig3 is a view that illustrates a data driving circuit 600 of fig2 according to a first embodiment of the present invention . for the convenience of description , the data circuit 600 of fig3 is shown to have j channels ( or j output channels ). referring to fig3 , the data driving circuit 600 includes a shift register part 601 , a sampling latch part 602 , a holding latch part 603 , a first switching part 604 , a signal generation part 605 , a second switching part 606 , and an output stage 607 . the shift register part 601 is supplied with an external source start pulse ssp and an external source shift clock ssc . the shift register part 601 supplied with the source shift clock ssc and the source start pulse ssp sequentially generates j sampling signals while shifting the source start pulse ssp for every period of the source shift clock ssc . here , the shift register part 601 includes j shift registers 6011 to 601 j . the sampling latch part 602 sequentially stores data corresponding to the sampling signals sequentially supplied from the shift register part 601 . here , the sampling latch part 602 includes j sampling latches 6021 to 602 j to store j data . the storing capacity of each of the sampling latches 6021 to 602 j is capable of storing the data ( or predetermined bits of the data ). the holding latch part 603 is inputted with and stores data from the sampling latch part 602 . the holding latch part 603 supplies its stored data to the first switching part 604 . here , the holding latch part 603 includes j holding latches 6031 to 603 j . the storing capacity of each holding latch 6031 to 603 j is capable of storing the data ( or predetermined bits of the data ). the first switching part 604 is supplied with data from the holding latch part 603 . the first switching part 604 supplied with the data from the holding latch part 603 transmits the data to the signal generation part 605 having dacs 6051 to 605 h . here , the first switching part 604 connects each of the holding latches 6031 to 603 j to a different one of the dacs 6051 to 605 h at every frame . for example , the first switching part 604 may connect the first holding latch 6031 to the first dac 6051 during the kth frame ( where k is a natural number ), and may connect the first holding latch 6031 to the second dac 6052 during the k + 1th frame . the signal generation part 605 is inputted with data from the first switching part 604 and then generates data signals corresponding to the inputted data . for this , the signal generation part 605 includes h dacs 6051 to 605 h ( where h is a natural number greater than j ). that is , the number of the dacs 6051 to 605 h included in the signal generation part 605 is set up to be greater than j . the dacs 6051 to 605 h included in the signal generation part 605 generate current or voltage values ( or predetermined current or voltage values ) corresponding to the gray level values of the data . the signal generation part 605 , which generates the voltage data signals or current data signals , supplies the generated data signals to the second switching part 606 . for example , in a case where voltage data signals are generated in the signal generation part 605 , the output stage 607 includes a plurality of buffers 6071 to 607 j , and in a case where current data signals are generated , the output stage 607 includes a plurality of sample / hold circuits 6071 to 607 j . the second switching part 606 is supplied with data signals from the signal generation part 605 . the second switching part 606 supplied with data signals from the signal generation part 605 connects the dacs 6051 to 605 h to different ones of the different buffers 6071 to 607 j or different ones of the samples / hold circuits 6071 to 607 j at every frame . for example , the second switching part 606 may connect the first buffer ( or the first sample / hold circuit ) 6071 to the first dac 6051 during the kth frame , and may connect the first buffer ( or the first sample / hold circuit ) 6071 to the second dac 6052 during the k + 1th frame . in practice , the second switching part 606 controls the connection between the signal generation part 605 and the output stage 607 so that the data signals generated by the data stored in the ith holding latch ( where i is a natural number ) may be supplied to the ith buffer ( or the ith sample / hold circuit ). the output stage 607 is supplied with j data signals from the second switching part 606 . in the case where the current data signals are supplied to the second switching part 606 , the sample / hold circuits 6071 to 607 j located in the output stage 607 charge the voltages corresponding to the current data signals supplied thereto , and the sample / hold circuits 6071 to 607 j are supplied with currents ( which may be predetermined ) from the pixels 400 via the data lines d 1 to dj corresponding to the charged voltages . on the other hand , in the case where the voltage data signals are supplied from the second switching part 606 , each of the voltage data signals is supplied via the buffers 6071 to 607 j to the data lines d 1 to dj . fig4 a to 4c are views that illustrate an embodiment of an operational procedure of a first switching part 604 ′ and a second switching part 606 ′ that can be used in the data driver 600 of fig3 . here , it is assumed that the signal generation part 605 ′ includes dacs 6050 to 605 j + 1 having a number equal to as many as the number of channels ( or output channels ) plus 2 . that is , assuming that the data driver 600 is connected to 100 data lines , the signal generation part 605 ′ includes 102 dacs . referring to fig4 a , the first switching part 604 ′ shifts the data stored in each of the holding latches 6031 to 603 j to the left by one channel during the kth frame to supply the data to the dacs 6050 to 605 j − 1 . then , the dacs 6050 to 605 j − 1 generate current data signals or voltage data signals corresponding to their supplied data and supply them to the second switching part 606 ′. at this time , the second switching part 606 ′ shifts the current data signals or the voltage data signals supplied from the dacs 6050 to 605 j − 1 to the right by one channel and supplies them to the output stage 607 . that is , the second switching part 606 ′ controls the connection between the signal generation part 605 ′ and the output stage 607 so that the data signals generated by the data supplied from ith holding latch may be supplied to the ith data line . referring to fig4 b , the first switching part 604 ′ supplies the data stored in each of holding latches 6031 to 603 j to the dacs 6051 to 605 j located in the original ( or un - shifted ) channel during the k + 1th frame as shown in fig4 b . then , the dacs 6051 to 605 j generate current data signals or voltage data signals corresponding to their supplied data and supply them to the second switching part 606 ′. at this time , the second switching part 606 ′ supplies the data signals outputted from the dacs 6051 to 605 j to the output stage 607 , but does not shift the data signals outputted from the dacs 6051 to 605 j . referring to fig4 c , the first switching part 604 ′ shifts the data stored in each holding latch 6031 to 603 j to the right by one channel and supplies them to the dacs 6052 to 605 j + 1 . then , the dacs 6052 to 605 j + 1 generate current data signals or voltage data signals corresponding to their supplied data and supply them to the second switching part 606 ′. at this time , the second switching part 606 ′ shifts the current data signals or the voltage data signals supplied from the dacs 6052 to 605 j + 1 to the left by one channel and supplies them to the output stage 607 . as described above , the data driving circuit 600 of the present invention sets up the dac connected to the specific holding latch during the kth frame to be different from the dac connected to the specific holding latch during the k + 1th frame . accordingly , each of the data lines d 1 to dj is supplied with the data signals generated by the dac that is different from the dac used in the previous frame at every frame . as such , if each of the data lines d 1 to dj is supplied with the data signals generated in the dac that is different from the dac used in the previous frame at every frame , the display region 300 may display uniform images . in other words , if the data signals generated in the dacs with a variation ( or a predetermined variation ) are supplied to the different data lines d 1 to dj at every frame , error diffusion occurs , thus making it possible to display uniform images . on the other hand , the connection procedure of the first and second switching parts 604 ′, 606 ′ of the present invention is not limited to those shown in fig4 a to 4b , and may be modified in various suitable manners so long as each of the data lines d 1 to dj at every frame is supplied with the data signals generated in the dac that is different from the dac used in the previous frame at every frame . fig5 a to 5c are views that illustrate another embodiment of an operational procedure of a first switching part 604 ″ and a second switching part 606 ″ that can be used in the data driver 600 of fig3 . here , it is assumed that a signal generation part 605 ″ includes dacs 6051 to 605 j having a number equal to as many as the number of channels ( or output channels ). referring to fig5 a , the first switching part 604 ″ shifts the data stored in parts of the holding latches 6031 , . . . . 603 j − 2 ( e . g ., holding latches 6031 , 6034 , and 603 j − 2 ) to the right by two channels during the kth frame and shifts the data stored in the remaining holding latches 6032 , 6033 , . . . 603 j − 1 , 603 j ( e . g ., holding latches 6032 , 6033 , 6035 , 6036 , and 603 j − 1 , 603 j ) to the left by one channel to supply the data to the dacs 6051 to 605 j . then , the dacs 6051 to 605 j generate current data signals or the voltage data signals corresponding to their supplied data and supply them to the second switching part 606 ″. at this time , the second switching part 606 ″ shifts parts of the current data signals or the voltage data signals supplied to the dacs 6051 to 605 j to the left by two channels and shifts the remaining data signals to the right by one channel to supply the data signals to the output stage 607 . that is , the second switching part 606 ″ controls the connection between the signal generation part 605 ″ and output stage 607 so that the data signals generated by the data supplied from the ith holding latch may be supplied to the ith data line . referring to fig5 b , the first switching part 604 ″ supplies ( without shifting ) the data stored in each holding latch 6031 to 603 j to the dacs 6051 to 605 j located in the original channel during the k + 1th frame . then , the dacs 6051 to 605 j generate current data signals or voltage data signals corresponding to their supplied data and supply them to the second switching part 606 ″. at this time , the second switching part 606 ″ supplies the data signals outputted from the dacs 6051 to 605 j to the output stage 607 , but does not shift the data signals supplied from the dacs 6051 to 605 j . referring to fig5 c , the first switching part 604 ″ shifts the data stored in parts of the holding latches 6033 , . . . 603 j ( e . g ., holding latches 6033 , 6036 , and 603 j ) to the left by two channels and shifts the data stored in the remaining holding latches 6031 , 6032 , . . . 603 j − 2 , 603 j − 1 to the right by one channel during the k + 2th frame to supply the data to the dacs 6051 to 605 j . then , the dacs 6051 to 605 j generate current data signals or voltage data signals corresponding to their supplied data and supply them to the second switching part 606 ″. at this time , the second switching part 606 ″ shifts parts of the current data signals or the voltage data signals supplied to the dacs 6051 to 605 j to the right by two channels and shifts the remaining data signals to the left by one channel to supply the data signals to the output stage 607 . as described above , the data driving circuit 600 of the present invention sets up the connection between the holding latch part 603 and the signal generation part 605 ″ during the kth frame to be different from the connection between the holding latch part 603 and the signal generation part 605 ″ during the k + 1th frame . accordingly , each of the data lines d 1 to dj is supplied with the data signals generated by the dac that is different from the dac used in the previous frame at every frame . as such , if each of the data lines d 1 to dj is supplied with the data signals generated in the dac that is different from the dac used in the previous frame at every frame , the display region 300 may display uniform images . in other words , if the data signals generated in the dacs with a variation ( or a predetermined variation ) are supplied to the different data lines d 1 to dj at every frame , error diffusion occurs , thus making it possible to display uniform images . on the other hand , the connection procedure of the first and second switching parts 604 ″, 606 ″ of the present invention is not limited to those shown in fig5 a to 5c , and may be modified in various suitable manners so long as each of the data lines d 1 to dj at every frame is supplied with the data signals generated in the dac that is different from the dac used in the previous frame at every frame . fig6 is a view that illustrates a data driving circuit 600 ′ according to a second embodiment of the present invention . in describing fig6 , parts that are substantially the same as the parts shown and described with reference to fig3 will be assigned the same reference numerals , and the detailed description thereof will be omitted . referring to fig6 , a signal generation part 609 in the data driving circuit 600 ′ according to the second embodiment of the present invention generates current data signals corresponding to data supplied from the first switching part 604 . for this , the signal generation part 609 includes a plurality of dacs 6091 to 609 h . the dacs 6091 to 609 h , which generate current data signals , are supplied with currents from the pixels via the second switching part 606 and the data lines d 1 to dj ( current sink ). then , each of the pixels 400 generates light corresponding to the current supplied to the data driving circuit 600 ′. the construction of the second embodiment is substantially identical to that of the first embodiment except that each of the dacs 6091 to 609 h included in the signal generation part 609 is supplied with the current from the pixels 400 via the second switching part 606 and data lines d 1 to dj . that is , the operational procedures of the first and second switching parts 604 , 606 are substantially identical to the first and second switching parts 604 ′, 604 ″, 605 ′, and / or 605 ″ as shown in fig4 a to 5c . however , in the second embodiment of the present invention , the output stage ( e . g ., 607 ) is omitted , and the second switching part 606 is directly connected to the data lines d 1 to dj . fig7 is a view that illustrates a data driving circuit 600 ″ according to a third embodiment of the present invention . in describing fig7 , parts that are substantially the same as the parts shown and described with reference to fig3 will be assigned the same reference numerals , and the detailed description thereof will be omitted . referring to fig7 , the data driving circuit 600 ″ according to the third embodiment of the present invention further includes a level shifter part 610 located to be connected to the holding latch part 603 . the level shifter part 610 raises the voltage level of data supplied from the holding latch part 603 and then supplies it to the first switching part 604 . by contrast , if data with high voltage level data are supplied from an external system to a data driving circuit , expensive high voltage circuit parts corresponding to the high voltage level need to be used , thus causing the manufacturing cost to be raised . therefore , in the third embodiment , the data with low voltage level are supplied from an external system to the data driver 600 ″, which in turn are stepped up to high voltage level in the level shifter part 610 . as such , low voltage circuit parts corresponding to the low voltage level may be used ( in place of the expensive high voltage circuit parts ). as described above , in a data driving circuit , a light emitting display device using the same , and the driving method thereof , the connection between the holding latch part and signal generation part during the previous frame is set up to be different from the connection between the holding latch part and signal generation part during the current frame . therefore , the data lines are supplied with the data signals generated in the dac that is different from the dac used in the previous frame at every frame , which in turn diffuses errors of the dacs , thus making it possible to display uniform images . while the invention has been described in connection with certain exemplary embodiments , it is to be understood by those skilled in the art that the invention is not limited to the disclosed embodiments , but , on the contrary , is intended to cover various modifications included within the spirit and scope of the appended claims and equivalents thereof .