fig3 shows a branch control circuit according to an embodiment of the present invention . the branch control circuit comprises an instruction buffer 101 for holding instructions that are provided in an instruction fetching stage of a pipeline process , a sub - decoding circuit 102 for decoding only a short format relative branch instruction , and a main decoding circuit 103 for decoding a normal - type relative branch instruction . in operation , the sub - decoding circuit 102 decodes only a short format relative branch instruction , for branch prediction . the main decoding circuit 103 receives first one of instructions stored in the instruction buffer 101 through a signal line 106 , and decodes into an internal instruction , which is provided to a signal line 109 for later processes . also , the main decoding circuit 103 predicts whether or not a general format relative branch instruction is taken , and provides a branch target address to a signal line 111 and a branch address valid signal to a signal line 110 . fig4 shows an instruction format employed by the present invention . a basic unit of this format is one half word ( hw ) and has a variable length . an instruction of one half word comprises a field bi containing branch prediction information , and a field inst containing an instruction function and operand information . in this embodiment , the field bi comprises one bit , which will be &# 34 ; 1 &# 34 ; when the field inst following the field bi is a head of a branch instruction and when the branch instruction is predicted to be taken , and will be &# 34 ; 0 &# 34 ; in other cases . the field inst comprises sixteen bits . the instruction fetch circuit provides instructions of aligned four half words to the instruction buffer 101 in one cycle . the instruction buffer 101 is capable of storing , for example , eight half words of instructions , and provides first three half words of instructions to the main decoding circuit 103 through the line 106 . fig5 shows formats of short format and general format relative branch instructions employed by the prediction control circuit of the present invention . a sum of the address of a branch instruction and a displacement contained in the branch instruction is used as a branch target address . the short format relative branch instruction is one half word in length . bits 0 to 7 of field inst of this instruction represent an operation code ( op code ), and bits 8 to 15 represent a displacement (# d8 ). a double of the displacement # d8 defines a difference between the address of the branch instruction and the branch target address . the general format relative branch instruction may include a displacement of eight , sixteen , or thirty - two bits . if the displacement size is eight bits , a field ss of the instruction will be &# 34 ; 00 &# 34 ;. if the displacement size is sixteen bits , the field ss of the instruction will be &# 34 ; 01 &# 34 ;. in this case , the instruction comprises two half words , in which the first one indicates a function of the instruction , and the second one indicates a displacement . if the displacement size is thirty - two bits , the field ss of the instruction will be &# 34 ; 10 &# 34 ;. in this case , the instruction comprises three half words , in which the first one indicates a function of the instruction , the second one indicates upper sixteen bits of a displacement , and the third one indicates lower sixteen bits of the displacement . the sub - decoding circuit 102 handles only the short format relative branch instruction , and predicts whether or not the branch is taken . fig6 is a detailed circuit diagram showing the sub - decoding circuit 102 of fig3 . the sub - decoding circuit 102 comprises an instruction latch 401 , a fetching pc 402 , a selector 403 , a branch instruction decoding circuit 404 , and an adder 405 . in operation , instructions of four half words are read from the instruction fetch circuit through the line 104 , and stored in the instruction latch 401 . a first address of the read instructions is stored in the fetching pc 402 through a line 105 . since a minimum instruction unit is a half word , a bit 31 of the fetching pc 402 is always &# 34 ; 0 &# 34 ;. instructions are aligned in four half words . an instruction with bits 29 and 30 of its address being &# 34 ; 00 &# 34 ; is stored in a field inst [ 0 - 15 ] of the instruction latch 401 , an instruction with bits 29 and 30 being &# 34 ; 01 &# 34 ; in a field inst16 - 31 ], an instruction with bits 29 and 30 being &# 34 ; 10 &# 34 ; in a field inst [ 32 - 47 ], and an instruction with bits 29 and 30 being &# 34 ; 11 &# 34 ; in a field inst [ 48 - 63 ]. when instructions are successively fetched , the bits 29 and 30 of the fetching pc 402 are &# 34 ; 00 &# 34 ; and all four half words of the instruction latch 401 are valid . when a branch target instruction is fetched , the bits 29 and 30 of the fetching pc 402 indicate a branch target address , and in the instruction latch 401 , only the fields after the branch address are valid . for example , if the bits 29 and 30 of the fetching pc 402 are &# 34 ; 10 &# 34 ;, the fields inst [ 32 - 47 ] and inst [ 48 - 63 ] and fields bi [ 2 ] and bi [ 3 ] are valid . the selector 403 selects one of the four half words stored in the instruction latch 401 according to bits of the fields bi [ 0 ] to bi [ 3 ] of the instruction latch 401 and the bits 29 and 30 of the fetching pc 402 . the selector 403 then provides the selected half word to the branch instruction decoding circuit 404 and adder 405 . fig7 is a table showing statuses of the bits 29 and 30 of the fetching pc 402 and statuses of the branch prediction information bits bi [ 0 ] to bi [ 3 ] of the instruction latch 401 , and outputs of the selector 403 corresponding to these statuses . supposing the bits 29 and 30 of the fetching pc 402 are &# 34 ; 10 &# 34 ; with bi [ 0 ]= 0 , bi [ 1 ]= 0 and bi [ 2 ]= 1 , the selector 403 selects the field inst [ 32 - 47 ] of the instruction latch 401 . if the latch 401 is storing a branch instruction which is predicted to be taken , the selector 403 selects the branch instruction of half word and provides the same to the branch instruction decoding circuit 404 and adder 405 . if the instruction latch 401 is storing no branch instruction which is predicted to be taken , i . e ., if all bits of the fields bi [ 0 ] to bi [ 3 ] are each 0 , the selector 403 provides all &# 34 ; 1 &# 34 ;. the branch instruction decoding circuit 404 receives an upper byte of the output of the selector 403 . if the upper byte coincides with one of operation code field ops of short format relative branch instructions , the circuit 404 asserts a branch address valid signal 107 . the bit pattern of all &# 34 ; 1 &# 34 ; does not coincide with any operation code field ops of the short format relative branch instruction . in this case , the circuit 404 doesn &# 39 ; t assert a branch address valid signal 107 . the adder 405 adds a value obtainable by shifting a lower byte of the output of the selector 403 by one bit to the left to a value of the fetching pc 402 , and provides a result of the addition to a signal line 108 . fig8 shows flows of a pipeline process with the sub - decoding circuit 102 carrying out branch prediction according to the present invention . in the figure , the sub - decoding circuit 102 and instruction buffer 101 of fig3 simultaneously receive a new instruction , and the sub - decoding circuit 102 decodes the instruction in this cycle . since the main decoding circuit 103 decodes first one of instructions stored in the instruction buffer 101 , the sub - decoding circuit 102 and main decoding circuit 103 simultaneously decode different instructions , respectively , in cycle 1 of fig8 . the decoding in the sub - decoding circuit 102 is carried out only to confirm a short format relative branch instruction . usually , before an instruction processed by the sub - decoding circuit 102 starts to be processed by the main decoding circuit 103 , preceding instructions stored in the instruction buffer 101 are processed in the main decoding circuit 103 . in fig6 preceding instruction il decodes in the main decoding circuit 103 in cycle 1 . an important thing is that a branch instruction bi is followed , just after it , by a target instruction ti . in this case , if branch prediction is correct , the pipeline process will not be disturbed by the branching . fig9 is a detailed circuit diagram showing the main decoding circuit 103 of fig3 . the main decoding circuit 103 comprises an instruction latch 701 that is a shift register , a decoding pc 702 , a selector 703 , a decoding circuit 704 , a first adder 705 , and a second adder 706 . instructions of three half words are given from the instruction buffer 101 to the main decoding circuit 103 , and stored in the instruction latch 701 . among the instructions of three half words , a first half word including a field bi [ 0 ] and a field inst [ 0 - 15 ] is provided to the decoding circuit 704 . the decoding circuit 704 converts the instruction into an internal instruction , which is supplied to an effective address computing portion through the signal line 109 . the length of the decoded instruction is provided to the second adder 706 . the second adder 706 adds the contents of the decoding pc 702 , i . e ., an address of the first half word of the instruction latch 701 to the decoded instruction length provided by the decoding circuit 704 . when the next instruction is supplied from the instruction buffer 101 to the main decoding circuit 103 , an output of the second adder 706 is stored in the decoding pc 702 . if a branch is taken , an instruction fetch address is stored in the decoding pc 702 from an instruction fetching portion through the line 105 . when the field bi [ 0 ] is &# 34 ; 1 &# 34 ; and the field inst [ 0 - 15 ] coincides with a bit pattern of a general format relative branch instruction of two or three half words in length , the decoding circuit 704 provides a branch address valid signal 110 . at this moment , a branch address has been computed already by the selector 703 and first adder 705 . the selector 703 selects a displacement included in the general format relative branch instruction . the size of the displacement is indicated by a section ss of bits 6 and 7 of the field inst [ 0 - 15 ] of the instruction . fig1 is a table showing relations between bit statuses of the field ss of the first half word and selected outputs of the selector 703 . in fig9 the first adder 705 adds a value of the decoding pc 702 to a displacement ( bit values of corresponding one of the inst fields of fig1 ) of the relative branch instruction that is a selected output of the selector 703 , thereby finding a branch target address , which is supplied to a signal line 111 . fig1 is a view showing pipeline flows with the main decoding circuit 103 of fig9 carrying out branch prediction . in cycle 1 , the main decoding circuit 103 decodes a branch instruction bi that has been predicted that branch is taken . in cycle 2 , an instruction ti specified by the branch instruction is fetched . in cycle 3 , the fetched instruction ti is decoded by the main decoding circuit 103 . accordingly , only one cycle of the pipeline process may be disturbed between the branch instruction bi and the instruction ti . as explained above , according to the embodiment of the present invention , the branch prediction information field bi of one bit is provided for each half word , and it will be &# 34 ; 1 &# 34 ; if the branch prediction is taken , and &# 34 ; 0 &# 34 ; if it will be not taken . in this way , prediction is made for each branch instruction . the field bi may comprise more than one bit to hold a history of directions of several past branches to carry out branch prediction based on the history . the main decoding circuit 103 may be modified to carry out branch prediction on an unconditional branch instruction , which is one of short format relative branch instructions having a field bi of &# 34 ; 0 &# 34 ; and on which the sub - decoding circuit 102 may not carry out the branch prediction . various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof .