while the invention is susceptible to various modifications and alternative forms , specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail . it should be understood , however , that there is no intent to limit the invention to the particular forms disclosed , but on the contrary , the invention is to cover all modifications , equivalents , and alternatives falling within the spirit and scope of the invention as defined by the claims . like reference numbers signify like elements throughout the description of the figures . for purposes of clarity and in no way limited thereto , the present invention is described hereafter in the context of decoding a row address for a memory cell array . it should be understood that the principles of the present invention are equally applicable to decoding a column address for a memory cell array . referring now to fig3 an integrated circuit memory device 30 , in accordance with the present invention , preferably includes a row predecoder 31 that is coupled to a row main decoder 35 . the row main decoder 35 is coupled to a memory cell array 37 . the integrated circuit memory device further includes an internal signal generator 33 , which is coupled to both the row predecoder 31 and the row main decoder 35 . exemplary operations of the integrated circuit memory device 30 will be described hereafter with reference to the signal timing diagram of fig7 . a row address rai and a row address strobe signal { overscore ( ras )} ( i . e ., external master signal ) are provided as inputs to the row predecoder 31 and the internal signal generator 33 , respectively . typically , the row address strobe signal { overscore ( ras )} is generated external to the row predecoder 31 , internal signal generator 33 , row main decoder 35 , and memory cell array 37 . the row address rai may be externally or internally generated . as shown in fig7 it is customary for the row address rai to be provided for a predetermined length of time , tas ( i . e ., row address setup time ) before the row address strobe signal { overscore ( ras )} is activated ( ie ., driven to a logic 0 level ). the internal signal generator 33 , in response to the activation of the row address strobe signal { overscore ( ras )}, activates an internal master signal pr and , optionally , an enable signal pnbls by driving both the internal master signal pr and the enable signal pnbls to a logic 1 level . the row predecoder 31 , however , predecodes the row address rai during the inactive state ( ie ., logic 1 level ) of both the row address strobe signal { overscore ( ras )} and the internal master signal pr to generate the predecoded row address draij . the row main decoder 35 decodes the predecoded row address draij and activates a word line enable signal nwei by driving the word line enable signal nwei to a logic 1 level in response to the activation of the enable signal pnbls . note , however , that the enable signal pnbls can be eliminated and replaced with the internal master signal pr without changing any finctionality of the integrated circuit memory device 30 because the enable signal pnbls and the internal master signal pr may be identical signals . when the word line enable signal nwei is activated , a corresponding word line in the memory cell array 37 is activated . accordingly , a corresponding memory cell is selected from the memory cell array 37 . advantageously , the integrated circuit memory device 30 in accordance with the present invention may reduce the time between activation of the row address strobe signal { overscore ( ras )} and activation of the word line enable signal nwei . specifically , the row predecoder 31 predecodes the row address rai during the inactive state of both the row address strobe signal { overscore ( ras )} and the internal master signal pr . in contrast with conventional integrated circuit memory devices , the row predecoder 31 need not wait for the internal signal generator 33 to activate the internal master signal pr before predecoding the row address rai . moreover , because the predecoded row address draij is already available when the row address strobe signal { overscore ( ras )} is activated , the row main decoder 35 can activate the word line enable signal nwei immediately upon activation of the internal master signal pr and , optionally , the enable signal pnbls . as discussed hereinabove with respect to fig1 and 2 , conventional integrated circuit memory devices may delay activation of the enable signal pnbls with respect to activation of the internal master signal pr by a predetermined time tf to provide the row predecoder 11 with time to generate the predecoded row address draij . accordingly , address decoding speed may be improved thereby facilitating higher speed operation of the integrated circuit memory device . as will be appreciated by those skilled in the art , the foregoing principles and concepts may also be applied to decoding a column address . for example , the row address rai may be a column address , the row predecoder 31 may be a column predecoder , the row main decoder 35 may be a column main decoder , and the word line enable signal nwei may be a bit line enable signal . referring now to fig4 the row predecoder 31 is illustrated in greater detail . the row predecoder 31 preferably comprises one or more unit predecoders 41 , 43 , and 45 , which predecode row address bits ra [ 0 : 1 ], ra [ 2 : 4 ], and ra [ 5 : 6 ], respectively . the unit predecoders 41 , 43 , and 45 latch the predecoded row address signals dra 01 & lt ; 0 : 3 & gt ;, dra 234 & lt ; 0 : 7 & gt ;, and dra 56 & lt ; 0 : 3 & gt ;, respectively , during the deactivated state of both the row address strobe signal { overscore ( ras )} ( logic 1 level ) and the internal master signal pr ( logic 0 level ). three unit predecoders 41 , 43 , and 45 are shown in fig4 because seven bits are used for the row address rai . in this example , the number of unit predecoders may range from one to three . a preferred embodiment of the unit predecoder 41 is shown in fig5 . the remaining unit predecoders 43 and 45 may be embodied in like fashion . note , however , that the unit predecoder 43 receives three row address bits ra [ 2 : 4 ] instead of two row address bits like the unit predecoders 41 and 45 and generates an eight bit predecoded row address signal dra 234 & lt ; 0 : 7 & gt ;. the unit predecoder 41 includes a plurality of nand gates ( nd 1 and nd 2 ), transmission gates ( t 1 and t 2 ), and latches ( l 1 and l 2 ). nand gate nd 1 receives supplementary bits ra 0 b and ra 1 d as inputs , where raib corresponds to the complement of rai . the transmission gate t 1 transmits the output of the nand gate nd 1 during the deactivated state of both the row address strobe signal { overscore ( ras )} ( logic 1 level ) and the internal master signal pr ( logic 0 level ). the latch l 1 latches the output of the transmission gate t 1 and outputs the predecoded row address bit dra 01 & lt ; 0 & gt ;. nand gate nd 2 receives row address bits rao and rai as inputs . the transmission gate t 2 transmits the output of the nand gate nd 2 during the deactivated state of both the row address strobe signal { overscore ( ras )} ( logic 1 level ) and the internal master signal pr ( logic 0 level ). the latch l 2 latches the output of the transmission gate t 2 and outputs the predecoded row address bit dra 01 & lt ; 3 & gt ;. in other words , the unit predecoder 41 predecodes row address bits ra [ 0 : 1 ] during the deactivated state of both the row address strobe signal { overscore ( ras )} ( logic 1 level ) and the internal master signal pr ( logic 0 level ) and latches the corresponding predecoded row address bits dra 01 & lt ; 0 : 3 & gt ;. as illustrated in fig3 , and 7 , the row predecoder 31 is active while the internal master signal pr is in a logic 0 state . that is , the transmission gates t 1 , t 2 , . . . ti allow a predecoded row address draij to propagate through to the latches l 1 , l 2 , . . . li . when the internal master signal pr transitions from the logic 0 state to the logic 1 state , however , the row predecoder 31 switches from an active state to an inactive state . that is , the transmission gates ti , t 2 , . . . ti prevent a predecoded row address draij from propagating through to the latches l 1 , l 2 , . . . . li . a preferred embodiment of the row main decoder 35 is shown in fig6 . the row main decoder 35 includes a pmos precharge transistor p 1 electrically connected between a reference potential vdd and the input terminal of a latch l 3 at node n . the transistor p 1 may precharge node n to the reference potential vdd in response to a control signal pdpx applied to its gate terminal . the row main decoder 35 further includes a plurality of nmos transistors n 1 , n 2 , n 3 , and n 4 connected in series between the node n and a ground reference potential vss . the latch l 3 comprises two inverters i 5 and i 6 configured as shown , which latch the inverse of the voltage level at node n for output as the word line enable signal nwei . the predecoded row address bits draij are applied to the gates of the nmos transistors n 1 through n 4 as follows : dra 01 & lt ; i & gt ;, i = 0 through 3 are applied to the gate of the nmos transistor n 1 ; dra 234 & lt ; i & gt ;, i = 0 through 7 are applied to the gate of the nmos transistor n 2 ; and dra 56 & lt ; i & gt ;, i = 0 through 3 are applied to the gate of the nmos transistor n 3 . the internal master signal pr or , optionally , the enable signal pnbls is applied to the gate of the nmos transistor n 4 . operations of the row main decoder 35 will now be described . when the enable signal pnbls is activated to a logic 1 level and the predecoded row addresses dra 01 & lt ; i & gt ;, dra 234 & lt ; i & gt ;, and dra 56 & lt ; i & gt ; are activated to a logic 1 level by the row predecoder 31 , the nmos transistors n 1 through n 4 are turned on and the node n is pulled to the reference potential vss , which corresponds to a logic 0 level . as a result , the output of the latch l 3 , which is the word line enable signal nwei , is activated to a logic 1 level . as illustrated in fig3 , and 7 , the row main decoder 31 is inactive while the internal master signal pr is in a logic 0 state . that is , the nmos transistor n 4 is turned off and prevents the latch l 3 from activating the word line enable signal nwei . when the internal master signal pr transitions from the logic 0 state to the logic 1 state , however , the row predecoder 31 switches from an inactive state to an active state . that is , the nmos transistor n 4 is turned on , which allows the latch l 3 to activate the word line enable signal based on the predecoded row address bits draij applied to the nmos transistors n 1 , n 2 , and n 3 . thus , opposite states of the internal master signal pr trigger the row predecoder 31 and the row main decoder 35 , which may prevent a new predecoded row address draij from being input to the row main decoder 35 before a previous predecoded row address draij has been decoded . the principles of the present invention have been described herein in connection with row address decoding in an integrated circuit memory device . from the foregoing it can readily be seen that the present invention may allow predecoding of the row address rai during the inactive state of both the row address strobe signal { overscore ( ras )} and the internal master signal pr . because the predecoded row address draij is already available when the row address strobe signal { overscore ( ras )} is activated , the row main decoder 35 can activate the word line enable signal nwei immediately upon activation of the internal master signal pr and , optionally , the enable signal pnbls . accordingly , address decoding speed may be improved thereby facilitating higher speed operation of the integrated circuit memory device . in concluding the detailed description , it should be noted that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention . all such variations and modifications are intended to be included herein within the scope of the present invention , as set forth in the following claims .