hereinafter , exemplary embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings . fig1 is a plan view illustrating an exemplary embodiment of a display panel . fig2 is a plan view illustrating an exemplary embodiment of a first pixel of fig1 . fig3 is a cross - sectional view illustrating an exemplary embodiment of a display panel including a thin film transistor substrate taken along the line i - i ′ of fig2 . fig4 is a cross - sectional view illustrating an exemplary embodiment of the thin - film transistor substrate taken along the line i - i ′ of fig2 . fig5 is a cross - sectional view illustrating an exemplary embodiment of a thin - film transistor substrate taken along the line ii - ii ′ of fig2 . fig6 is a cross - sectional view illustrating an exemplary embodiment of a thin - film transistor substrate taken along the line iii - iii ′ of fig2 . referring to fig1 , the display panel includes a plurality of gate lines gl , a plurality of data lines dl and a plurality of pixels . the gate lines gl may extend in a first direction d 1 . the data lines dl may extend in a second direction d 2 , which is substantially crossing the first direction d 1 . alternatively , the gate line gl may extend in the second direction d 2 , and the data line dl may extend in the first direction d 1 . the pixels may be arranged in a matrix shape . the pixels may be disposed in areas defined by the gate lines gl and the data lines dl . each pixel may be connected to a corresponding gate line gl and a corresponding data line dl adjacent to the pixel . each pixel may have a v - shape . alternatively , the pixel may have a rectangle shape extending in a direction , a z - shape or the like . referring to fig2 to 6 , the display panel includes a first substrate 100 , a second substrate 200 and a liquid crystal layer 300 . the first substrate 100 may include a first base substrate 110 , a gate insulating layer 120 , a data line dl , a first passivation layer 130 , an organic insulating pattern 140 , a common electrode ce , a second passivation layer 150 and a pixel electrode pe . the first base substrate 110 may be a transparent insulation substrate . for example , the transparent insulation substrate may be a glass substrate , a plastic substrate or the like . the first base substrate 110 may include a plurality of pixel areas for displaying an image . a plurality of the pixel areas may be disposed in a matrix shape having a plurality of rows and a plurality of columns each pixel may further include a switching element . for example , the switching element may be a thin film transistor tft . the switching element may be connected to the gate line gl and the data line dl adjacent to the switching element . the switching element may be disposed at a crossing area of the gate line gl and the data line dl . a gate pattern may include a gate electrode ge and the gate line gl . the gate pattern may be disposed on the first base substrate 110 . the gate line gl is electrically connected to the gate electrode ge . the gate insulating layer 120 may be disposed on the first substrate 110 to cover the gate pattern and may insulate the gate pattern . a semiconductor pattern sm may be disposed on the gate insulating layer 120 . the semiconductor pattern sm may overlap the gate electrode ge . a data pattern may include the data line dl , a source electrode se and a drain electrode de . the data pattern may be disposed on the semiconductor pattern sm , which is formed on the gate insulating layer 120 . the source electrode se may overlap the semiconductor pattern sm . the source electrode se may be electrically connected to the data line dl . the drain electrode de may be spaced apart from the source electrode se on the semiconductor pattern sm . the semiconductor pattern sm may have a conductive channel between the source electrode se and the drain electrode de . the tft may include the gate electrode ge , the source electrode se , the drain electrode de and the semiconductor pattern sm . the gate insulating layer 120 may include an inorganic insulating material . for example , the gate insulating layer 120 may include silicon oxide ( sio x ) or silicon nitride ( sin x ). the first passivation layer 130 may be disposed on the gate insulating layer 120 to cover the data pattern and may insulate the data pattern . the first passivation layer 130 may be disposed on the gate line gl , the data line dl and the thin - film transistor tft . the first passivation layer 130 may be disposed on a whole surface of the first base substrate 110 . the first passivation layer 130 may include an inorganic insulating material . for example , the first passivation layer 130 may include silicon oxide ( sio x ) or silicon nitride ( sin x ). the organic insulating pattern 140 may be disposed on the gate pattern including the gate line gl and the data pattern including the data line dl , and may cover the gate pattern and the data pattern . for example , the organic insulating pattern 140 may cover the gate line gl , the data line dl and the thin - film transistor tft . thus , a coupling capacitance occurs between the gate pattern and the common electrode ce or between the data pattern and the common electrode ce . the organic insulating pattern 140 may include an opening overlapping with the pixel area . thus , a remainder area except for an area including the gate line gl , the data line dl and the thin - film transistor tft may be exposed . therefore , an organic material in the pixel area may be removed , so that a yellowish screen may be prevented , thus improving a display quality . the organic insulating pattern 140 includes a photosensitive organic material . for example , the organic insulating pattern 140 may include a photosensitive organic material such as a photo acryl or the like . for example , a thickness of the organic insulating pattern 140 may be about 1 μm to about 3 μm . when the thickness of the organic insulating pattern 140 is less than trim , a coupling capacitance between the gate pattern and the common electrode ce or between the data pattern and the common electrode ce may be not reduced . when the thickness of the organic insulating pattern 140 is more than 3 μm , the display panel may be too thick . for example , a permittivity ( c ) of the organic insulating pattern 140 may be equal to or less than 4 . 5 . generally , a capacitance is proportional to the permittivity . thus , when the permittivity is more than 4 . 5 , a coupling capacitance between the gate pattern and the common electrode ce or between the data pattern and the common electrode ce may be not reduced . the common electrode ce may be disposed on a whole surface of the first base substrate 110 . for example , the common electrode ce may be overlapped with the data line dl . the organic insulating pattern 140 may be formed between the data line dl and the common electrode ce . thus , a coupling capacitance between the data line dl and the common electrode ce may be reduced . for example , the common electrode may include a transparent conductive a transparent conductive material , such as indium tin oxide ( ito ), indium zinc oxide ( izo ) and aluminum - doped zinc oxide ( azo ). for example , the common electrode ce may have a slit pattern . the second passivation layer 150 may be disposed on the common electrode ce . the second passivation layer 150 may insulate the common electrode ce and the pixel electrode pe . the second passivation layer 150 may be disposed on a whole surface of the first base substrate 110 . the second passivation layer 150 may include an inorganic insulating material . for example , the second passivation layer 150 may include silicon oxide ( sio x ) or silicon nitride ( sin x ). the pixel electrode pe may be disposed on the second passivation layer 150 . the pixel electrode pe may be electrically connected to the thin - film transistor tft through the contact hole ch . the pixel electrode pe may be connected to the drain electrode de of the thin - film transistor tft , and a grayscale voltage may be applied to the pixel electrode pe through the thin - film transistor tft . the pixel electrode pe may be disposed on the pixel area . for example , the pixel electrode pe may be disposed between adjacent data lines dl . for example , the pixel electrode pe may include a transparent conductive material , such as indium tin oxide ( ito ), indium zinc oxide ( izo ) and aluminum - doped zinc oxide ( azo ). for example , the pixel electrode pe may have a slit pattern . thus , a grayscale voltage may be applied to the pixel electrode pe and the common electrode ce , thus forming an electric field . the second substrate 200 may include a second base substrate 210 , a color filter cf and a black matrix bm . the second base substrate 210 may be a transparent insulation substrate . for example , the transparent insulation substrate may be a glass substrate , a plastic substrate or the like . the color filter cf may be disposed on the second base substrate 210 . adjacent color filters cf may be disposed between adjacent data lines dl . the color of light may be changed by the color filter cf and the light may penetrate the liquid crystal layer 300 . color filters cf may include a red color filter , green color filter and a blue color filter . each of the color filters cf may correspond to one of the pixel areas . color filters , which are adjacent to each other , may have different colors from each other . for example , the color filters cf may be overlapped on a border between pixel areas adjacent to each other . alternatively , the color filters cf may be spaced apart from a border between pixel areas adjacent to each other in the first direction d 1 . for example , the color filters cf may be formed in a island - shape on the data lines dl . the black matrix bm is disposed on the color filter cf to block light . the black matrix bm may be formed to be corresponding to a non - display area of the pixel , so that light provided form an outside may be blocked . for example , the black matrix bm may be overlapped with the gate line gl , the data line dl and the thin - film transistor tft . for example , the black matrix bm may be formed in a metal material having a low transmissivity or a black material including a photosensitive organic material . for example , the metal material may include molybdenum , titanium , tungsten or an alloy thereof . for example , the black material may further include a coloring agent such as carbon black , an organic or inorganic pigment , a color mixed pigment or the like . the liquid crystal layer 300 may be disposed between the first substrate 100 and the second substrate 200 . for example , the liquid crystal layer 300 may include liquid crystal molecules . an alignment of the liquid crystal molecules in the liquid crystal layer 300 may be controlled by an electric field applied between the common electrode ce and the pixel electrode pe . therefore , a light transmittance of the pixel may be controlled . it is not illustrated in the figures , the display panel may include an alignment layer to aligning the liquid crystal molecules . the alignment layer may pre - tilt the liquid crystal molecules of the liquid crystal layer 300 . fig7 is a cross - sectional view illustrating an exemplary embodiment of a thin - film transistor substrate taken along the line i - i ′ of fig2 . a thin - film transistor substrate according to an exemplary embodiment in fig7 is substantially the same as the thin - film transistor substrate according to an exemplary embodiment in fig4 to 6 . the same reference numerals will be used to refer to the same or like parts as those described in the previous exemplary embodiment in fig4 to 6 and any further repetitive explanation concerning the above elements will be omitted . referring to fig2 and 7 , the first substrate 100 includes a first base substrate 110 , a gate insulating layer 120 , a data line dl , a first passivation layer 130 , an organic insulating pattern 140 , a color filter cf , a black matrix bm , a common electrode ce , a second passivation layer 150 and a pixel electrode pe . for example , the first substrate 100 may have coa ( color filter on array ) structure that a color filter is formed on a thin - film transistor substrate , and boa ( black matrix on array ) structure that a black matrix is formed on a thin - film transistor substrate . according to an exemplary embodiment , a thin - film transistor substrate and a display panel may be used for a liquid crystal display apparatus , an organic light emitting apparatus or the like . the foregoing is illustrative of the inventive concept and is not to be construed as limiting thereof . although a few exemplary embodiments of the inventive concept have been described , those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the inventive concept . accordingly , all such modifications are intended to be included within the scope of the inventive concept as defined in the claims . therefore , it is to be understood that the foregoing is illustrative of the inventive concept and is not to be construed as limited to the specific exemplary embodiments disclosed , and that modifications to the disclosed exemplary embodiments , as well as other exemplary embodiments , are intended to be included within the scope of the appended claims . the inventive concept is defined by the following claims , with equivalents of the claims to be included therein .