fig2 is a block diagram of a linear regulator 200 for supplying a regulated output voltage v out to a load 202 . load 202 can be any type of electronic circuit that receives a substantially constant voltage source . in one implementation , linear regulator 200 receives an input signal ( e . g ., a power source voltage v power ) from a power supply 204 ( e . g ., a transformer ) that can fluctuate outside of the operating range of linear regulator 200 and / or load 202 . in one implementation , linear regulator 200 includes an mode selection circuit 206 , internal voltage generation circuit 208 , a power switch 210 , middle stage circuitry 212 , and sense circuitry 214 . mode selection circuit 206 includes circuitry for determining a mode of operation for linear regulator 200 . in one implementation , linear regulator 200 operates according to two modes ( i . e ., one mode at any given time )— a regulating mode and a direct - supplying mode . in the regulating mode , linear regulator 200 is controlled to output a regulated ( or monitored ) output voltage v out ( through power switch 208 ). in the direct - supplying mode , linear regulator 200 is controlled to couple ( or supply ) power source voltage v power ( from power supply 200 ) directly to load 202 , without any voltage regulation . in one implementation , mode selection circuit 206 determines a mode of operation for linear regulator 200 based on a voltage level of power source voltage v power . that is , if the power source voltage v power exceeds the operating range of linear regulator 200 and / or load 202 , then linear regulator 200 operates according to the regulating mode . and , if the power source voltage v power is within the operating range of linear regulator 200 and / or load 202 , linear regulator 200 operates according to the direct - supplying mode . internal voltage generation circuit 208 generates a substantially stable internal bias reference ( e . g ., voltage v clamp ) that is used to supply a bias voltage to circuitry within linear regulator 200 — e . g ., mode selection circuit 206 , middle stage circuitry 212 , and sense circuitry 214 . in one implementation , voltage v clamp is supplied to circuitry within linear regulator 200 all the time . in one implementation , voltage v clamp is always substantially within the operating range of circuitry within linear regulator 200 even though the power source voltage v power may fluctuate or exceed the operating range of linear regulator 200 . for example , if the power source voltage changes from 4 . 5 volts to 9 volts , then voltage v clamp , in one implementation , will accordingly change from 4 . 5 volts to 5 . 5 volts . internal voltage generation circuit 208 can include any type of circuitry ( e . g ., one or more diode - connected mosfet transistors as described below ) for generating a substantially stable internal bias voltage v clamp . power switch 210 operates to couple output v out of linear regulator 200 to power source voltage v power . power switch 210 can include one or more transistors ( not shown ). power switch 210 can be controlled by a control voltage vp , as discussed in greater detail below . in one implementation , power switch 210 directly couples power source voltage v power to output v out ( i . e ., power switch 200 is fully on ( or closed )) when power source voltage v power is within the operating range of linear regulator 200 and / or load 202 . when power source voltage v power exceeds the operating range of linear regulator 200 and / or load 202 , power switch 210 is controlled to supply a regulated output voltage v out to load 202 . middle stage circuitry 212 includes circuitry for reducing a power consumption of linear regulator 200 when linear regulator 200 is operating in the direct - supplying mode , i . e ., when power source voltage v power is within the operating range of linear regulator 200 and / or load 202 . in one implementation , current flow to middle stage circuitry 212 and sense circuitry 214 is substantially shut off when power source voltage v power is being directly coupled ( or supplied ) to output v out of linear regulator 200 . as discussed in greater detail below , sense circuitry 214 can include one or more operational transconductance amplifiers . middle stage circuitry 212 further includes one or more transistors ( not shown ) that are controlled by the internally generated voltage v clamp to protect one or more transistors ( not shown ) within linear regulator 200 from stress ( or reaching a breakdown voltage ) when v power exceeds the operating range of linear regulator 200 , one implementation of which is discussed below in association with fig4 a - 4c . sense circuitry 214 includes circuitry for regulating output voltage v out when linear regulator 200 is operating in the regulating mode , i . e ., when power source voltage v power exceeds the operating range of linear regulator 200 and / or load 202 . sense circuitry 214 is operable to maintain a regulated output voltage at a pre - determined voltage level . in one implementation , sense circuitry 214 operates using voltage v clamp as a bias voltage reference . sense circuitry 214 can include any type of sensing circuitry for sensing an output voltage and generating a control signal responsive to the sensed output voltage . fig3 shows a process 300 for regulating an output voltage of a linear regulator ( e . g ., linear regulator 200 ). a power source voltage ( e . g ., power source voltage v power ) is received by the linear regulator ( step 302 ). in one implementation , the power source voltage is a fluctuating voltage generated by a transformer , which power source voltage can exceed an operating range of the linear regulator and / or an associated load ( e . g ., load 202 ). a substantially stable internal bias reference ( e . g ., voltage v clamp ) is generated ( e . g ., using internal voltage generation circuit 208 ) ( step 304 ). the substantially stable internal bias reference can be used to supply a bias voltage to circuitry within the linear regulator . for example , in one implementation , sense circuitry associated with the linear regulator is supplied a substantially stable internally generated bias reference that is within an operating range of one or more transistors associated with the sense circuitry . a determination is made ( e . g ., through mode selection circuit 206 ) whether the power source voltage is outside ( e . g ., exceeds ) the operating range of the linear regulator and / or the associated load ( step 306 ). if the power source voltage is outside ( e . g ., exceeds ) the operating range of the linear regulator and / or load , then the output voltage of the linear regulator is regulated ( e . g ., through sense circuitry 214 ) using the internally generated bias reference ( step 308 ). if the power source voltage is not outside the operating range of the linear regulator and / or the associated load , then power is substantially shut off to voltage regulation circuitry ( e . g ., using middle stage circuitry 212 ) ( step 310 ). in one implementation , current is substantially shut off to the sense circuitry and middle stage circuitry associated with the linear regulator . the power source voltage is directly coupled to the output of the linear regulator ( e . g ., through power switch 210 ) ( step 312 ). after steps 308 , 312 , method 300 returns to step 304 , discussed above . fig4 a - 4c illustrate one implementation of linear regulator 200 , including mode selection circuit 206 ( fig4 b ), internal voltage generation circuit 208 ( fig4 c ), power switch 210 , middle stage circuitry 212 , and sense circuitry 214 . in one implementation , linear regulator 200 is fabricated through a 5 volt cmos process . of course , other appropriate processes may be utilized . in such an implementation , linear regulator 200 includes transistors and other circuitry ( as discussed below ) that have an operating range of below substantially 6 volts . referring to fig4 a - 4c , mode selection circuit 206 includes resistors r 3 - r 4 , a comparator 402 , and inverters i 1 - i 2 . internal voltage generation circuit 208 includes resistor r 5 , and pmos transistor mp 5 , mp 6 , mp 7 , mp 8 . power switch 210 includes a pmos transistor mp 1 . middle stage circuitry 212 includes resistor r 6 , nmos transistors mn 1 , mn 2 , mn 3 , mn 4 , mn 5 , mn 6 , pmos transistors mp 2 , mp 3 , mp 4 , an inverter i 3 , and a current source i bias . sense circuitry 214 includes resistors r 1 - r 2 , and an operational transconductance amplifier 404 . as discussed above , in one implementation , linear regulator 200 operates in two modes — a regulating mode and a direct - supplying mode — as determined by mode selection circuit 206 . in operation during regulating mode , power source voltage v power exceeds an operating range of linear regulator 200 — e . g ., power source voltage varies between 6 - 9 volts . in response , comparator 402 ( of mode selection circuit 206 ) compares a reference voltage v ref to a voltage v prop that is directly proportional to power source voltage v power . if voltage v prop is greater than reference voltage v ref , then mode selection circuit pulls control signal v comp ( and v s ) to a low voltage level . inverters i 1 - i 2 are buffers that increase a drive capability of control signal v comp . the buffered control signal v s is provided to an input to an inverter i 3 in middle stage circuitry 212 . transistor mp 3 is turned off , and an output of operational transconductance amplifier 404 of sense circuitry 214 is activated to regulate the output voltage v out of linear regulator 200 . in one implementation , operational transconductance amplifier 404 is connected in a negative feedback arrangement to equalize reference voltage v ref and a feedback voltage v fb . voltage v out is given by the following equation : v out = ( 1 + r ⁢ ⁢ 1 r ⁢ ⁢ 2 ) × v ref ( eq . ⁢ 1 ) where v ref is a reference voltage that can represent a bandgap voltage ( e . g ., 1 . 2 volts ). the output voltage v out is further regulated by controlling an amount of dissipation current i d through resistor r 6 , and nmos transistors mn 1 , mn 2 in middle stage circuitry 212 . a voltage drop across resistor r 6 — i . e ., the product of resistor r 6 and dissipation current i d — defines the v gs ( gate - to - source voltage ) of pmos transistor mp 1 . by controlling the v gs of pmos transistor mp 1 , a load current through pmos transistor mp 1 can be accordingly reduced ( or increased ) during the regulating mode of linear regulator 200 . dissipation current i d is controlled as follows . a current mirror formed by nmos transistors mn 3 , mn 4 provide a biasing current for diode - connected pmos transistor mp 4 . in turn , the diode - connected pmos transistor mp 4 generates a biasing voltage v bias to control pmos transistor mp 2 . pmos transistor mp 2 behaves as a switch ( i . e ., due to a large w / l ratio ), and voltage v d at the drain of pmos transistor mp 2 is pulled up to substantially equal power source voltage v power . dissipation current i d flowing through resistor r 6 , and nmos transistors mn 1 , mn 2 , is given by the following equation : i d = ( v power - v p r ⁢ ⁢ 6 ) ( eq . ⁢ 2 ) where v p is defined by the v gs of pmos transistor mp 1 . because power voltage source v power can exceed the breakdown voltage of the cmos transistors within linear regulator 200 , internal voltage generation circuit 208 generates a substantially stable internal bias voltage v clamp to supply a proper supply voltage to circuitry within linear regulator 200 . referring to fig4 c , internal voltage generation circuit 208 includes 4 diode - connected pmos transistors mp 5 - mp 8 and resistor r 5 that provide a bias voltage v clamp that is clamped within the range of , for example 4 . 5 - 5 . 5 volts . in the implementation shown , nmos transistors mn 2 , mn 5 have gates connected to bias voltage v clamp to protect nmos transistors mn 1 , mn 4 from exceeding a breakdown voltage , even though power source voltage v power may be greater than the breakdown voltage . in one implementation , the value of resistor r 6 and the size ( i . e ., w / l ratio ) of nmos transistor mn 1 are small to avoid any issues with stability . for example , in one implementation , resistor r 6 has a value of 10 k ohms and nmos transistor mn 1 has a w / l ratio of 2 . 5 μm / 3 . 5 μm . the poles at nodes 1 and 2 ( fig4 a ) have a value of 1 r ota × ⁢ c par ⁢ ⁢ and ⁢ ⁢ 1 r 6 × ⁢ c gate , respectively , in which r ota , c par , and c gate represent an output impedance of operational transconductance amplifier 404 , a parasitic capacitance at node 1 , and a gate capacitance of pmos transistor mp 1 . the poles at nodes 1 and 2 are pushed to high frequencies and therefore linear regulator 200 can be considered as a one - pole system , having a transfer function as follows : h ⁡ ( s ) = ( g m_ota × ⁢ r ota ) × ( g m_mn ⁢ 1 × ⁢ r 6 ) × ( g m_mp ⁢ 1 × ⁢ r out ) r out × ⁢ c l ⁢ s + 1 × r 1 r 1 + ⁢ r 2 ( eq . ⁢ 3 ) in which g m — ota , g m — mn1 , g m — mp1 represents the transconductance of operational transconductance amplifier 404 , nmos transistor mn 1 , and pmos transistor mp 1 , respectively , and r out represents an output impedance at output v out . in operation during direct - supplying mode , power source voltage v power is within an operating range of linear regulator 200 — e . g ., power source voltage varies below 6 volts . in response , comparator 402 ( of mode selection circuit 206 ) pulls control signal v comp ( and v s ) to a high voltage level . node 3 is pulled low through nmos transistor mn 6 , and the biasing current flowing through nmos transistors mn 4 , mn 5 and pmos transistor mp 4 is cut off . thus , biasing voltage v bias is pulled up to substantially equal power source voltage v power and pmos transistor mp 2 is turned off . also , the gate of pmos transistor mp 3 is pulled low to fully turn on pmos transistor mp 3 , which causes node 1 to be pulled up to be substantially equal to bias voltage v clamp . nmos transistors mn 1 , mn 2 are fully on , while pmos transistor mp 2 is off . as a result node 2 — i . e ., control signal v p — is pulled to a low voltage level , and pmos transistor mp 1 is fully activated to supply power source voltage v power directly to load 202 without any voltage regulation . middle stage circuitry 212 pulls node 4 — i . e ., bias voltage v bias high — to substantially shut off pmos transistor mp 2 . thus , no current flows through , e . g ., middle stage circuitry 212 and sense circuitry 214 , which reduces power dissipation of linear regulator 200 during times that power source voltage v power is substantially stable . in one implementation , the resistance value of resistor r 6 is small , and therefore cutting off current flowing through resistor r 6 reduces a large amount of power dissipation within linear regulator 200 . fig5 shows a graph 500 of output voltage v out in response to a fluctuating power source voltage v power . as shown in fig5 , curve 502 rises linearly in an unregulated fashion until power source voltage v power ( and output voltage v out ) reaches 6 volts ( a breakdown threshold for 5 volt cmos transistors ). at this voltage , linear regulator 200 begins to regulate output voltage v out at substantially 5 volts as power source voltage v power continues to rise . fig6 shows a graph 600 of a transient response waveform of linear regulator 200 . the transient response waveform represents a measure of how fast linear regulator 200 returns to steady - state conditions after a load change ( e . g ., a change in load current to load 202 ). linear regulator 200 can be used in a wide range of applications . for example , linear regulator 200 can be used with circuitry of a battery charger circuit 700 , as shown in fig7 . in particular , linear regulator 200 can be used to supply a substantially stable bias voltage to battery charger integrated circuit 702 , even though a power supply ( not shown ) ( which supplies power to linear regulator 200 ) may have a fluctuating power source voltage . battery charger circuit 700 can be used to charge electronic circuits and devices having re - chargeable batteries . for example , electronic devices can include cellular phones , mp3 / mp4 players , digital cameras , and so on . in one implementation , when a re - chargeable battery is fully charged ( e . g ., by battery charger circuit 700 ), battery charger circuit 700 goes into a stand - by mode . while battery charger circuit 700 is in a stand - by mode , linear regulator 200 can directly supply the power source voltage received from the power supply ( not shown ) to battery charger circuit 700 , according to the direct - supplying mode described above . during this mode of operation , current is substantially shut off to voltage regulating circuitry within linear regulator 200 , which reduces power dissipation and heat generation within battery charger circuit 700 . a number of implementations have been described . nevertheless , it will be understood that various modifications may be made without departing from the spirit and scope of the invention . for example , steps of methods described above can be performed in a different order . accordingly , other implementations are within the scope of the following claims .