fig1 shows a part of an electrical component 1 with integrated circuit 2 and an electrical connection from the integrated circuit 2 to the interconnect 8 . the connection shown here by way of example is an smd ( surface mounted device ) connection , in which the connections from the component 1 to the printed circuit board 9 ( the pins ) are soldered directly onto the printed circuit board 9 without being conducted through a bore in the printed circuit board 9 . proceeding from its end point 3 on the integrated circuit 2 , the electrical connection is composed of a bond wire 4 , the connection point 5 of the bond wire to the pin 6 , the pin 6 itself and the solder point 7 of the pin . the connecting interconnect 8 and the printed circuit board 9 are also entered . this leads to the rest of the electrical circuit in which the component is installed . an equivalent circuit diagram of the electrical connection is shown under this . in this , bond wire 4 , connection point 5 , pin 6 and solder point 7 are viewed as being independent sections of the electrical connection . for analysis of its electrical behavior , each section can be replaced by the ohmic line impedance δr devolving onto the section , an inductance δl and a capacitance δc as well as a terminating impedance δg that a signal interacts with in this section upon transition into the next section , insofar as the signal is considered to be a propagating wave . an internal resistance r in is set for the integrated circuit itself . the solder point 7 on the interconnect 8 is set as r out as an equivalent . for illustration , the sections in fig1 are illustrated directly by arrows from the electrical smd connection shown immediately above . the testing device is integrated into the integrated circuit . the generation of the test pulse can ensue , for example , by a clock - controlled uni - vibrator . alternatively to this cost - beneficial and space - saving solution , tunnel diodes are suited for generating even steeper signal edges . it can be assured by a delay element that the above - described conditions for the signal rise time t r are adhered to . t r should be smaller than the signal propagation time . alternatively , the signal propagation time can be delayed to such an extent that , given the wavelength λ corresponding to the signal width , the apparent length over which the test signal runs on the connection under test is greater than approximately λ / 2 . as a result of the delay element , it is not absolutely necessary to implement a complicated solution as a test signal generator that can generate extremely steep pulse edges ; rather , a standard solution suffices . fig2 shows two components 1 with the testing device disclosed here , additionally referenced a , b for further distinction , and a schematic electrical connection in the form of the interconnect 8 between two terminals of the components 1 . each of the two components can then independently test with the testing device disclosed here as to whether the electrical connection up to and including the interconnect is in a proper condition . this is indicated by the circular arrow in the drawing . it stands for the path of the test signal that , reflected , runs to the end of the electrical connection placed in the component . no higher - ranking comparison is thus needed , in contrast to the prior art , for example , the testing method with logic tests and boundary scan elements . a statement about the connections is first possible not only when a component applies logic commands ( test vectors ) to the pins and the result is read out at the other component and compared in a higher - ranking fashion . according to the embodiment described here , the component itself can already implement a test dependent on the anticipated terminating impedances at the other end of the electrical connections , here the input impedance of the pin of component b as seen proceeding from component a , without having to take the remaining logic behavior of the circuit in which the components are installed into consideration . fig3 shows the further structure of the testing device in a component 1 which includes a test signal generator 10 and an evaluator 11 . a multiplexer is also provided , this successively applying the test signal to the individual electrical connections under test , the pins here . this is shown in the drawing by the arrow to pin no . 1 and the successively ensuing cut - in by the circular , broken - line arrow . a switch function that connects the active electrical connection under test at the moment to the test signal generator and the evaluator is thereby implemented at each pin or at the beginning of the electrical connection under test . the delivery of the evaluation signal to the evaluator ensues in an opposite manner , in that the connection at which a reply signal is anticipated at the moment is likewise successively connected to the evaluator 11 by a multiplexer . fig4 explains how the delivery of the test signal to the pins ensues upon employment of the existing boundary scan test architecture . the figure shows a boundary scan cell according to the jtag standard that is expanded by two drivers 13 and 14 . a multiplexer 12 is also additionally provided for the above - described selection of the pin to be tested . when the signal for the test mode is applied to the input enb , the input for the test mode type 15 , then the test signal is conducted via a driver 13 and the multiplexer 12 to the output . when the test mode is not activated , then the input signal is forwarded directly to the output . the reply signal is received at the evaluation signal output 16 . the integration into an existing test architecture offers the advantage that both tests can be implemented . the added outlay for this is relatively slight . given components with an extremely low number of pins , however , a solution without a simultaneous implementation of boundary scan cells would likely be more beneficial . fig5 shows the circuit diagram of an embodiment of the evaluator 11 described here by way of example . this is composed of a reference voltage divider that prescribes reference voltages in fixed graduations via resistors 19 that are divided off from the circuit adjacent at the reference voltage input 18 . this is followed by analog comparators 20 . the analog comparators forward their result into a following latch 22 . a decoder 21 and the actual evaluation unit , composed of a register 23 and a digital comparator , are connected to the latch 22 . the evaluation signal is applied to the evaluation signal input 17 . this is then compared to all values by the reference voltage divider by the resistors 19 . when the evaluation signal exceeds the value of a specific step , the respective analog comparator 20 forwards a signal to the following latch 22 . the “ sampling ” itself ensues via a gate circuit that acquires the reply signal between the values t 1 and t 2 . insofar as electrical connecting lines are to be tested in simple circuits in which multiple reflections are not expected , it is adequate to select the time gate between t 1 and t 2 such that t 1 corresponds to the start time of the test signal and t 2 corresponds to a value 2τ + t with τ as an anticipated propagation time of a signal over the electrical connection under test in a single direction and t as a safety margin . in this case , the reflected signal is acquired in every instance . the decoder 21 converts the information into a data word , here having a width of 8 bits . given a data word width of 8 bits for the decoder , a comparison to 255 compartmentalized reference values is accordingly necessary . the result is written into a register 23 and subsequently compared to the anticipated value in a digital comparator 24 . in order to allow a tolerance , a suitable plurality of last bits should not be considered , since an exact coincidence is probably precluded due to the above - described , multiple conversion of the reply signal . in contrast to standard a / d converters , the reply signal is quantized first . the corresponding memory cell of the following latch is set at every exceeded value of the reference voltage , which is present in steps . a “ thermometer code ” is present , by which a value “ 1 ” is assigned to each of the values prescribed by the graduated reference voltage when the value is exceeded . the latch consequently stores that highest value of the reply signal that has been reached ( the maximum value ) in that the value “ 1 ” resides in a series up to the position that corresponds to the maximum value of the reply signal , which may only have been briefly reached once . the advantage of such a parallel quantization is the high process speed . fig6 shows an embodiment with an external test controller for an existing boundary scan test architecture . components 1 — three are entered here by way of example — having a respective testing device of the species previously described are connected to a test controller 25 that fetches the results of the testing device integrated on each component 1 via a data line . the controller has an interface 26 for the output of the data outside the electrical circuit . for an existing test architecture according to the boundary scan method , the existing tap test controller that outputs the test results of the boundary test scan is advantageously employed in that it is appropriately expanded and its control command set is expanded by a command for the output of the test results of the testing device disclosed here . alternatively , it is conceivable to integrate the test controller in one or more of the components 1 . the embodiment shown in fig6 has the advantage that the test results can be interrogated from the outside by data calling . it is thus possible for digital circuits that are / can be connected to a data transmission line ( as is the case , e . g ., for telephone switching systems ) to make a remote diagnosis as to whether an error is present in a connection on the circuit or , conversely , whether a component fault is more probable . the advantageous possibility of limiting oneself to testing for a few typical errors in order to obtain a simple test evaluation is explained on the basis of fig7 through 9 b . these figures show the result of respective simulation calculations . the equivalent circuit diagram as shown in fig1 has been selected as model for the electrical connection . however , a further simplification was undertaken in that no division into sections was undertaken . what is mainly decisive for the signal image is the terminating impedance at the end of the electrical connection . when the simulation is refined further , then further reflections occur at the transfer resistances of the sections ; in the simplification selected here , however , these are negligible since the terminating impedance at the end of the connection under test causes the greatest effect . of course , the ideal , calculated signal images cannot be achieved in this way in a real measurement , but for an adequate selection of the measuring tolerance , the result can be transferred . fig7 shows the modification of the test signal image for a terminating impedance r = 0 , corresponding to the case p ≈− 1 . the value at the right is the path of the electrical connection under test . the left edge corresponds to the starting point at which the test signal generator and evaluator lie . the right - hand edge corresponds to the location at which the reflection occurs , the location of the terminating impedance . the test signal runs from left to right and back . the test signal 27 is shown shortly after the start of the test , the test signal 28 shortly after the reflection , and the reply signal 29 . this is the behavior of an electrical connection to ground in the “ good ” case , and , given a faulty connection , this is recognized as shorted to ground . fig8 shows the modification of the test signal image for a matched terminating impedance . this corresponds to the case p ≈ 0 . the test signal 27 is shown after the start of the test and the test signal 30 at the end of the electrical connection under test . here , the characteristic impedance corresponds to the terminating impedance ; no reflection occurs . an electrical connection to another component with matched input impedance is recognized as ok , and a faulty connection to a component with a high - impedance input is recognized as being shorted to another electrical connection . fig9 a and 9 b show the modification of the test signal image for a terminating impedance r =∞. the test signal 27 after the start of the test and the test signal 28 shortly after the reflection at the end of the electrical connection under test are shown in fig9 a . fig9 b shows the reply signal . in this case , the terminating impedance is very high compared to the characteristic impedance r →∞). as a fault , this corresponds to a missing connection ( missing contact ) and corresponds to an open connection for the expected “ good ” case . the test on the basis of these three values of the reflection coefficient enables a test without having to previously calculate the exact values of the “ good ” case , as would be required for other intermediate values of the reflection coefficient . the error categorization is rather clear for these values . accordingly , a test program for the component can be developed from a determination of the resistances adjacent at the pins in a defined condition without having to subject the overall circuit to a measurement or calculation of anticipated values . furthermore , an inventive testing device can be advantageously integrated on an electrical circuit in addition to the known boundary scan testing method , this inventive testing device specifically testing the connections . these can also be tested by the inventive testing device during the service life of the digital circuit , in contrast to the production test methods according to the boundary scan method . the above - described method , circuit , and device are illustrative of the principles of the present invention . numerous modifications and adaptations thereof will be readily apparent to those skilled in this art without departing from the spirit and scope of the present invention .