firstly , the course of events in the setting phase or the programming phase will be discussed . in fig1 there is illustrated a setting unit 1a and a unit comprising a timer circuit , for example a fuse which is here illustrated by the dashed line 1b . the setting unit 1a is connected to the fuse 1b via the contracts k1 and k2 , and after contact has been achieved between the setting unit 1a and the fuse 1b , the setting or the programming of a timer circuit in the fuse 1b can commence . in fig2 there are illustrated various signal courses , and the line designated k1 for the upper signal course of fig2 represents the signal communication between the setting unit 1a and the fuse 1b . this communication signal can appropriately be a modulated power supply voltage , a voltage being applied after having obtained contact between the setting unit 1a and the fuse 1b , such that the fuse 1b is supplied with a voltage v + via the contact k1 in relation to the contact k2 . the modulation of the supplied voltage v + can be an increase of the voltage from v + to a higher voltage v ++, and back to v +. in other words there can as data signals be used a power supply voltage exceeding a certain reference voltage according to a given pattern . the timer circuit which is housed by the fuse 1b , comprises a detector 4 which detects whether a switched on setting unit 1a is connected to the fuse 1b for supplying electric power to the fuse . the detector 4 can for example be constructed as a current detector detecting current above a certain value . to the detector 4 there is connected a regulator 5 which regulates the supply voltage to the fuse , the internal non - regulated supply voltage being supplied via the contact 3 through a diode 14 and to the regulator 5 . during the programming phase the internal voltage source will not be active , and there will then be no current from the contact 3 . the diode 14 serves to prevent unnecessary current consumption from the setting unit 1a . the output from the regulator 5 will during normal operating conditions via the contact k6 , supply all the electronic circuits which are connected to the time setting circuit in the fuse 1b . in the fuse 1b there is also included a feedback circuit 8 which via its terminal k9 will reset the electronic circuitry each time the regualtor 5 is switched on . when the fuse 1b is supplied with voltage from the setting unit 1a , the detector 4 will , via a buffer 11 , set the control logic 15 to a programming mode . at the same time a current switch 7 will be enabled to function when a signal from a pulse comparator 10 which is connector to the one input contact k1 , and / or the control logic 15 , is sent out to said current swtich 7 . when the supply voltage is switched on , an oscillator 12 will start oscillating . the oscillator 12 is appropriately a free running oscillator having a good short time stability . the output from the oscillator 12 is connected to a divider unit 16 and a frequency selector 17 . the oscillator frequency is determined on the basis of a desired resolution on in the timer circuit and the dividing factor in the setting unit . a suitable resolution can for example be 0 . 1 second , and the dividing factor 1000 times , a fact which involves that the oscillator must operate with a frequency of minimum 10 khz . because the control logic 15 is set to programming mode , the frequency selector 17 , upon signal from the control logic 15 , will be set to select an input signal direct from the oscillator 12 . when the timer circuit depicted in fig1 is reset , it is made ready for setting of the time in question . the setting of the fuse , i . e . the timer circuit in the fuse , is in the disclosed proposal for solution implemented with two pulses a and b , as this appears from the signal diagram at the top of fig2 . pulse a gives information about programmed time , the length of pulse a corresponding to the accurately set time divided with a known factor . if this factor is made equal to 1000 , and if it is desired to set the timer circuit to 100 seconds , the pulse a will have a duration of 100 milliseconds . pulse b is a write pulse , which entails that the set information is stored in a memory . when the pulses a and b , respectively , are supplied to the fuse , they will be detected by the pulse comparator 10 . a signal s13 from the pulse comparator 10 will then close the current switch 7 as long as the pulses remain . the additional current consumption which is caused by the current switch 7 at the output from the detector 4 , will be registered by the setting unit 1a , and in this manner one will quickly get a response to whether larger parts of the electronic circuitry in the fuse operate satisfactorily . during this first part of this programming phase the control logic 15 will be controlled by the signal s13 as a pace setter . the control logic 15 enables a gate 18 to be opened for clock pulses from the frequency selector 17 to a counter 19 as long as the pulse a exists . after the termination of pulse a , what has been stored in the counter 19 will be an unknown number of clock pulses which are proportional to the duaration of the set time in the fuse setting unit 1a . the pulse b enables the control logic 15 to send a write pulse to the memory 20 , and the contents of the counter 19 will then be stored in for example non - volatile transistor cells in the memory 20 . after the reading into the memory 20 , the first part of the programming phase is terminated , and one will thereafter pass on to a checking phase . the control logic 15 will then be controlled by an internal pace maker which is tapped by the divider unit 16 . the control logic 15 will then run through an inherent routine , the starting thereof being transferring the contents of the memory 20 to the counter 19 . the counter 19 then starts its down counting , and the frequency selector 17 selects an input signal direct from the oscillator 12 . the control logic opens the gate 18 to allow the counter 19 to start its down counting , there being provided a pulse c on the signal line s13 . pulse c will the have a duration corresponding to the time it takes to count down the counter 19 to zero . pulse c on the signal line s13 will effect the current switch 7 to close as long as pulse c exists . pulse c will be detected by the setting unit 1a and will compare the length of pulse a with pulse c . if the oscillator 12 has had a constant frequency throughout the complete programming phase , pulse c will have the same duration as pulse a , a fact which is checked by the setting unit 1a . the control logic 15 and the counter 19 are both connected to an output buffer 21 , and the control logic 15 will cater for no activity of the output buffer 21 during the programming phase . after comparison and control of the pulses a and c , the programming phase is completed , and the setting unit 1a will switch off the power supply to the fuse 1b , whereafter the setting unit is removed from the fuse . if the above mentioned timer circuit resides in a projectile , the trajectory thereof will commence at the moment of discharge , the internal supply voltage being supplied via the contact 3 . the regulator 5 will then supply the electronic circuitry with electric power via the output k6 , whereas the resetting circuit 8 will reset the electronic circuitry , and the oscillator 12 will start oscillating . the detector 4 will now register that no fuse setting unit is connected to the fuse and will set the control logic 15 to trajectory mode via the buffer 11 . the control logic 15 adjusts the frequency selector 17 to select clock pulses from the divider unit in the setting unit 16 . this involves that the pulse length which the data in the memory 20 represent , now will be multiplied by the same factor which was used in the fuse setting unit during this programming of the timer circuit . if the oscillator frequency from the oscillator 12 is the same as during the programming phase , the running time of the timer circuit will correspond to the time being set on the setting unit . the control logic 15 will immediately after the resetting of the electronic circuitry run through an inherent routine , it now being controlled by the same internal pace maker as during the checking part of the programming phase . what wil happen now , is that the contents of the memory 20 in first instance will be transferred to the counter 19 which has been set to down counting , whereafter the gate 18 will open and the counter 19 commence to count down . the output buffer 21 will not be enabled to received signal from the counter 19 . when the timer circuit has run out in the counter 19 has counted down to zero , it will output a signal to the output buffer 21 . the output 22 will now be activated and the trajectory phase terminated . it is to be understood that the above described embodiment only illustrates an arbitrary proposal for solution , only one counter and one memory being used therein . however , it is of course possible to include a further memory and / or counter for achieving av greater flexibility and security . the counters and / or memories can either be programmed simultaneously with pulse a and pulse b , or they can be programmed in series by means of a new pulse from the setting unit , this new pulse appearing between pulse a and b and giving information to the counter and / or memory number 2 . it can often be desired to have a fixed time which has to run out before the output buffer 21 is activated . if this is implemented as a hardware programmed counter , it will constitute a fair contribution to the safety if the memory 20 with non - volatile transistor cells should possibly fail . the accuracy of such a counter will , however , be dependent on the long time stability of the oscillator 12 . it is also possible to set the timer circuit to various modes . this can be done in that the setting unit supplies to the fuse a new pulse after pulse a . the control logic 15 will compare the length of this pulse with the pulse duration of the internal time reference in the fuse by tapping a signal from the down counter 16 at an appropriate location . the result can be stored in separate 1 - bits non - volatile transistor cells when the write pulse b is supplied . by an appropriate design of the control logic 15 it is possible to read all the programmed times and modes of the setting of the fuse during the checking part of the programming phase . it is also possible to read the programmed times and modes without a previous setting of the fuse . it is to be understood that the principle of setting the timer circuit by means of pulse width modulation ( period setting ) also can be used where the setting signal is transferred by means of electro magnetism , radio waves or light . combinations of variations in solution can render a very versatile timer circuit . the timer circuit can operate alone or in a timer fuse or be combined with proximity and impact functions . 1 . in the setting unit the program source or modulator modulates the power supply voltage from v + to v ++ volts . 2 . in the timer a current switch ( 7 ) modulates the current consumption of the timer whenever programming pulses are transferred from the setting unit or control signal ( pulses ) transferred from the timer to the setting unit . an example of the setting unit 1a is illustrated in fig3 . and the timing logic for same is illustrated in fig4 . the modulated power supply voltage is produced by changing the reference input of the regulator . before programming starts , the output of the modulator is low and switch , sw1 , is not connected . the output voltage of the regulator is then fixed by r 2 and r 3 to v + volts . when the modulator applies pulse a and b , ( see fig4 ), the switch sw1 , will close and connect the resistor , r4 , in parallel with r 3 and the regulator output voltage will increase to v ++ volts . the regulator has to be designed such that the current consumption of the regulator has to be designed such that the current consumption of the regulator itself will not change when the output voltage changes between v + and v ++. r 1 is the current sensing resistor . when the fuse is connected , but no programming takes place , the voltage drop across r , is less than the voltage drop across the diode d , and the output of the comparator is low . when programming pulses , v ++, is applied to the timer , or when the timer responds with control pulses , the supply voltage will be current modulated by the by the current switch 7 in the timer . this additional current consumption that the current switch 7 causes will result in an additional voltage drop of over r 1 , which is greater than the diode voltage of diode d . the output of the comparator will change to high and this will be detected by the control unit . in this manner , the control unit will , during programming , compare the setting pulses from the modulator in the setting unit with the control pulses from the modulator in the setting unit with the control pulses from the timer , and during the checking phase , it will compare the control pulses with the previously transmitted setting pulses . note that the control unit must have a memory for storing setting pulses .