the present invention will now be described more fully hereinafter with reference to the accompanying drawings , in which preferred embodiments of the invention are shown . this invention may , however , be embodied in different forms and should not be construed as limited to the embodiments set forth herein . rather , these embodiments are provided so that this disclosure will be thorough and complete , and will fully convey the scope of the invention to those skilled in the art . in the drawings , the thickness of layers and regions are exaggerated for clarity . it will also be understood that when a layer is referred to as being “ on ” another layer or substrate , it can be directly on the other layer or substrate , or intervening layers may also be present . moreover , the terms “ first conductivity type ” and “ second conductivity type ” refer to opposite conductivity types such as n or p - type , however , each embodiment described and illustrated herein includes its complementary embodiment as well . like numbers refer to like elements throughout . referring now to fig3 an integrated power semiconductor device according to a first embodiment of the present invention will be described . in particular , a unit cell 200 of a preferred integrated power semiconductor device has a predetermined width “ w c ” ( e . g ., 1 μm ) and comprises a highly doped drain layer 114 of first conductivity type ( e . g ., n +), a drift layer 112 of first conductivity type having a linearly graded doping concentration therein , a relatively thin base layer 116 of second conductivity type ( e . g ., p - type ) and a highly doped source layer 118 of first conductivity type ( e . g ., n +). a source electrode 128 b and drain electrode 130 may also be provided at the first and second faces , in ohmic contact with the source layer 118 and drain layer 114 , respectively . the source electrode 128 b also preferably forms an ohmic contact with the base layer 116 in a third dimension ( not shown ). the drift layer 112 may be formed by epitaxially growing an n - type in - situ doped monocrystalline silicon layer having a thickness of about 4 μm on an n - type drain layer 114 ( e . g ., n + substrate ) having a thickness of 100 μm and a first conductivity type doping concentration of greater than about 1 × 10 18 cm − 3 ( e . g . 1 × 10 19 cm − 3 ) therein . as illustrated , the drift layer 112 may have a linearly graded doping concentration therein with a maximum concentration of greater than about 5 × 10 16 cm − 3 ( e . g ., 3 × 10 17 cm − 3 ) at the n +/ n non - rectifying junction with the drain layer 114 and a minimum concentration of 1 × 10 16 cm − 3 at a depth of 1 μm and continuing at a uniform level to the upper face . the base layer 116 may be formed by implanting p - type dopants such as boron into the drift layer 112 at an energy of 100 kev and at a dose level of 1 × 10 14 cm − 2 , for example . the p - type dopants may then be diffused to a depth of 0 . 5 μm into the drift layer 112 . an n - type dopant such as arsenic may then be implanted at an energy of 50 kev and at dose level of 1 × 10 15 cm − 2 . the n - type and p - type dopants are then diffused simultaneously to a depth of 0 . 5 μm and 1 . 0 μm , respectively , to form a composite semiconductor substrate containing the drain , drift , base and source layers . as illustrated by fig3 the first conductivity type ( e . g ., n - type ) doping concentration in the drift layer 112 is preferably less than about 5 × 10 16 cm − 3 at the p - n junction with the base layer 116 ( i . e ., second p - n junction ), and more preferably only about 1 × 10 16 cm − 3 at the p - n junction with the base layer 116 . the second conductivity type ( e . g ., p - type ) doping concentration in the base layer 116 is also preferably greater than about 5 × 10 16 cm − 3 at the p - n junction with the source layer 118 ( i . e ., first p - n junction ). furthermore , according to a preferred aspect of the present invention , the second conductivity type doping concentration in the base layer 116 at the first p - n junction ( e . g ., 1 × 10 17 cm − 3 is about ten times greater than the first conductivity type doping concentration in the drift region at the second p - n junction ( e . g ., 1 × 10 16 cm − 3 ). a stripe - shaped trench having a pair of opposing sidewalls 120 a which extend in a third dimension ( not shown ) and a bottom 120 b is then formed in the substrate . for a unit cell 100 having a width w c of 1 μm , the trench is preferably formed to have a width “ w t ” of 0 . 5 μm at the end of processing . a gate electrode / source electrode insulating region 125 , a gate electrode 127 ( e . g ., polysilicon ) and a trench - based source electrode 128 a ( e . g ., polysilicon ) are also formed in the trench . because the gate electrode 127 is made relatively small and does not occupy the entire trench , the amount of gate charge required to drive the unit cell 200 during switching is much smaller than the amount of gate charge required to drive the unit cell 100 of fig2 ( assuming all other parameters and dimensions are equal ), as described more fully hereinbelow . as will be understood by those skilled in the art , the trench may also be formed as a cylindrical or annular - shaped trench which when viewed in transverse - cross section appears as a trench having opposing sidewalls . here , the trench - based source electrode 128 a is electrically connected to the source electrode 128 b in a third dimension ( not shown ). the portion of the gate electrode / source electrode insulating region 125 extending adjacent the trench bottom 120 b and the drift layer 112 may also have a thickness “ t 1 ” in a range between about 1500 å and 3000 å , for example , to inhibit the occurrence of high electric field crowding at the bottom corners of the trench and to provide a substantially uniform potential gradient along the trench sidewalls 120 a . however , the portion of the gate electrode / source electrode insulating region 125 extending opposite the base layer 116 and the source layer 118 preferably has a thickness “ t 2 ” of less than about 750 å , and more preferably about 500 å to maintain the threshold voltage of the device at about 2 - 3 volts . the use of tapered trench - based insulating regions to improve electric field profiles in highly doped drift region mesas is also described in u . s . application ser . no . 09 / 322 , 424 , to b . jayant baliga , entitled “ power semiconductor devices that utilize tapered trench - based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same ”, filed may 28 , 1999 , the disclosure of which is hereby incorporated herein by reference . in particular , these tapered trenchbased insulating regions are most preferably designed to have a nonuniform thickness t ins ( y ) in a range between about 0 . 5 and 1 . 5 times t ideal ( y ), where t ideal ( y )| y ≧ α = ε ins (( 2ε s e cr / qw m n d ) ( y −- α )+ ¼w m )/ ε s and ε ins is the permittivity of the electrically insulating region , ε s is the permittivity of the drift region , e cr is the breakdown electric field strength of the drift region , q is the electron charge , n d is the first conductivity type doping concentration in the drift region , w m is a width of the mesa , y is the depth , relative to a top of the first trench , at which the thickness of the electrically insulating region is being determined and α is a non - negative constant . the constant α may equal zero in the event the power device is a schottky rectifier and may equal the depth of the p - base region / n - drift region junction in the event the power device is a vertical mosfet , for example . numerical simulations of the unit cell 200 of fig3 were performed using a drift region doping concentration which increased from a value of 1 × 10 16 cm − 3 at a depth of 1 micron to a value of 2 × 10 17 cm − 3 at a trench depth ( t d ) of 5 microns . the thin portion of the gate / source electrode insulating region 125 extended to 1 . 2 microns of a total trench depth of 4 . 7 microns and had a thickness of 500 å . the thick portion of the gate / source electrode insulating region 125 had a thickness of 3000 å . the n + source layer 118 depth was set to 0 . 3 microns , and the depth of the p - type base region 116 was set to 0 . 9 microns . a half - cell width of 1 micron was used based on 1 micron design rules . the polysilicon gate electrode 127 extended to 1 . 2 microns and the polysilicon source electrode 128 a extended from 1 . 5 microns to 4 . 4 microns . based on these parameters , the specific on - resistance ( r on , sp ) at a gate bias of 15 volts was found to be 114 microohm cm 2 and the device blocked more than 60 volts . comparisons of the potential distributions and contours in the device of fig3 at a drain bias of 60 volts , against the device of fig2 indicated essentially no change in the electric field profile within the drift region . this finding suggests that the trench - based source electrode 128 a does not upset the degree of charge coupling and field distribution required to obtain high performance operation . moreover , even though the specific on - resistance of the device of fig3 was about 20 % greater than the specific on - resistance of the device of fig2 the high frequency figure - of - merit ( hfom ), defined as ( r on , sp ( q gs + q gd )) − 1 , where q gs and q gd represent the gate - source and gate - drain charge per unit area , was also calculated to be three ( 3 ) times better than the hfom for the device of fig2 . this result means the device of fig3 is very suitable for high frequency operation . referring now to fig4 a - 4k , a preferred method of forming the integrated power semiconductor device of fig3 will be described . as illustrated best by fig4 a , the method begins with the step of forming a semiconductor substrate 10 by epitaxially growing a drift region 12 of first conductivity type ( e . g ., n - type ) on a highly doped drain region 14 of first conductivity type which has a doping concentration greater than 1 × 10 18 cm − 3 therein . computer controlled in - situ doping of the drift region 12 is also preferably performed during the epitaxial growth step so that the drift region 12 has a linearly graded ( or step graded ) first conductivity type doping concentration therein which decreases in a direction away from the drain region 14 . in particular , the drift region 12 is preferably doped so that the doping concentration of the drift region 12 at the abrupt non - rectifying junction ( j 3 ) is greater than about 1 × 10 17 cm − 3 and more preferably about 3 × 10 17 cm − 3 , but less than 5 × 10 16 cm − 3 at the first face 15 a and more preferably only about 1 × 10 16 cm − 3 at the first face 15 a . referring now to fig4 b , a thin base region 16 is then formed in the substrate 10 by patterning a first implant mask ( not shown ) on the first face 15 a and then performing an implant of second conductivity type dopants through the first mask . the implanted second conductivity type dopants can then be diffused into the drift region 12 to an initial depth of about 0 . 5 μm , for example . these steps are then preferably followed by the steps of patterning a second implant mask ( not shown ) on the first face 15 a and performing an implant of first conductivity type dopants through the second mask . the second mask is also preferably patterned in a third dimension ( not shown ) so that portions of the underlying base region 16 do not receive the implanted source dopants . these portions of the base region 16 which extend to the first face 15 a can be ohmically contacted by a source electrode at the end of processing . the implanted first conductivity type dopants and the second conductivity type dopants can then be diffused to a depth of about 0 . 5 μm and 1 . 0 μm , respectively , to provide a base region thickness “ t c ” of about 0 . 5 μm . preferably , boron ( b ) is used as a p - type dopant and is implanted at a dose level of about 1 × 10 14 cm − 2 and at an energy of 100 kev . arsenic ( as ) is preferably used as an n - type dopant and is implanted at a dose level of about 1 × 10 15 cm − 2 and at an energy of 50 kev . as will be understood by those skilled in the art , the implant and diffusion steps will cause the doping profile of the second conductivity type dopants in the substrate 10 to be generally gaussian in shape and have a maximum value at the first face 15 a . the doping concentration in the base region 16 will also have a maximum value adjacent the source region 18 and a minimum value adjacent the drift region 12 . in particular , the implant and diffusion steps may be performed so that the first conductivity type dopant concentration of the source region 18 at the first face 15 a is greater than 1 × 10 18 cm − 3 and the second conductivity type dopant concentration in the base region 16 is greater than about 1 × 10 17 cm − 3 at a first p - n junction ( j 1 ) with the source region 18 , but less than about 5 × 10 16 cm − 3 and more preferably only about 1 × 10 16 cm − 3 at the second p - n junction ( j 2 ) with the drift region 12 . to meet these criteria , the first conductivity type doping concentration in the drift region 12 should be about 1 × 10 16 cm − 3 at the second p - n junction ( j 2 ). because of this relatively low value of 1 × 10 16 cm − 3 in the drift region 12 , the base region 16 can be made thin ( e . g ., 0 . 5 μm ) without being susceptible to parasitic reach - through breakdown and can be doped relatively low to maintain the transistor &# 39 ; s threshold voltage at about 2 - 3 volts . referring now to fig4 c , an etching mask 22 including a stress relief oxide layer 22 a and an oxidation barrier layer 22 b ( e . g ., si 3 n 4 ) is then patterned on the first face 15 a to define openings which expose adjacent portions of the first face extending over the source and base regions 18 and 16 . the source , base and drift regions are then chemically etched to form a plurality of trenches 20 . as illustrated , each of the trenches has opposing vertical sidewalls 20 a which define interfaces between the source , base and drift regions and an interior of the trench , and a trench bottom 20 b in the drift region . facing sidewalls 20 a of adjacent trenches also define respective mesas 17 which may have uniform widths of about 0 . 5 μm at the end of processing . the trenches 20 and mesas 17 , which extend in a third dimension , not shown , can be of stripe or similar geometry . the mesas 17 can also be polygonal ( e . g ., hexagonal ) in shaped with the trenches 20 defining a continuous mesh when viewed from a direction normal to the face 15 a . as explained more fully hereinbelow , the widths of the mesas 17 can be selected to improve the blocking voltage capability of the transistor . in particular , the width of the mesas 17 ( at the end of processing ) and the doping concentration in the drift region 12 at j 3 should be selected so that their product is within the range of 1 × 10 13 - 2 × 10 13 cm − 2 to obtain a preferred charge concentration in the drift region 12 . in addition , the width of the mesas 17 and the doping concentration in the drift region 12 at j 2 should be selected so that their product is within the range of 1 × 10 11 - 2 × 10 12 cm − 2 . referring now to fig4 d which illustrates a cross - section of three adjacent mesas 17 , the method continues with the formation of a first electrically insulating region 24 ( e . g ., sio 2 ) having a first thickness greater than 1000 å and more preferably about 3000 å , on the trench sidewalls 20 a and the trench bottom 20 b of each trench 20 . this step is preferably performed by oxidizing the etched source , base and drift regions , using the oxidation barrier layer 22 b as an oxidation mask . as will be understood by those skilled in the art , the growth of an oxide having a thickness of about 3000 å will typically consume about 0 . 1 μm or more of semiconductor material . accordingly , the initial widths of the mesas 17 should be selected so that at the end of processing the widths are at the desired value of about 0 . 5 μm . referring now to fig4 e - 4k , a conformal n - type first polycrystalline silicon region 26 is then deposited and etched until it is recessed in the trench to a depth just below the second p - n junction ( j 2 ). this first polysilicon region 26 defines a trench - based source electrode . an oxide etching step is then performed to remove the first electrically insulating region 24 from the portions of the sidewalls 20 a which extend adjacent the etched source and base regions 18 and 16 , as illustrated best by fig2 f . referring now to fig4 g , a second electrically insulating region 28 ( e . g ., sio 2 ) having a second thickness less than about 1000 å and more preferably about 500 å , is then formed on the exposed trench sidewalls 20 a and on the polysilicon region 26 . referring now to fig2 h , a conformal second polycrystalline silicon region 30 is then deposited on the second electrically insulating region 28 . the second polycrystalline silicon region 30 is then etched until it is recessed in the trench to a depth just below the first face 15 a . steps are also preferably performed to expose the first polysilicon region 26 in a third dimension ( not shown ) so that subsequent contact can be made to a source electrode on the face 15 a . a third electrically insulating region 32 is then formed on the etched second polycrystalline silicon region 30 by oxidizing the second polycrystalline silicon region 30 , as illustrated by fig2 . the stress relief oxide layer 22 a and the oxidation barrier layer 22 b ( e . g ., si 3 n 4 ) are then etched to expose the source region 18 and base region 16 at the first face 15 a , as illustrated by fig4 j . a source metal contact layer 34 is then deposited on the first face 15 a and a drain metal contact layer 36 is deposited on an opposing second face 15 b to form ohmic contacts to the source , base and first polysilicon regions ( 18 , 16 and 26 ) and drain region 14 , respectively , as illustrated by fig4 k . referring now to fig5 an integrated power semiconductor device 300 according to a second embodiment of the present invention will be described . as illustrated , this power device 300 includes an active device region and an edge termination region which may extend adjacent an outermost edge of a semiconductor substrate containing the power device 300 . according to one aspect of this embodiment , the active device region may include a plurality of unit cells which are similar to the unit cells 100 and 200 of fig2 and 3 , respectively . however , to improve edge termination characteristics , an edge termination trench is provided in the edge termination region and a uniformly thick first field plate insulating region 134 is provided which lines the sidewalls and bottom of the edge termination trench . a field plate 136 , comprising a material such as n - type polysilicon , is also provided on the first field plate insulating region 134 . in addition , a second field plate insulating region 138 is provided on the first face and this second field plate insulating region overlaps the first field plate insulating region 134 . to complete the field plate structure , a field plate extension 140 is provided . this field plate extension 140 , which is electrically connected to the field plate 136 , is provided on the second field plate insulating region 138 and extends opposite the face of the substrate , as illustrated . this field plate extension 140 may also comprise n - type polysilicon . the field plate 136 is also preferably connected to the source electrode 128 b or gate electrode 126 . to improve the edge termination and breakdown characteristics of the integrated power device 300 even further , the edge termination trench is preferably positioned so that a transition mesa region is defined between opposing sidewalls of the edge termination trench and the trench corresponding to the outermost unit cell of the device 300 . however , unlike the mesa regions which are defined between trenches within the active device region of the integrated power device 300 , the transition mesa region is preferably formed to be devoid of a source region of first conductivity type . instead , a preferred breakdown shielding region 117 of second conductivity type ( e . g ., p - type ) is provided . the breakdown shielding region 117 may be formed at the same time the base region 116 is formed , for example . however , as illustrated best by fig6 which is a cross - sectional view of an integrated power semiconductor device 300 ′ according to a third embodiment of the present invention , the breakdown shielding region 117 ′ may also be formed deeper ( and more highly doped ) than the base region 116 to further increase the likelihood that avalanche breakdown will occur in the transition mesa region instead of within the active region . the use of breakdown shielding regions to improve the breakdown characteristics of power semiconductor devices is also described in commonly assigned u . s . application ser . no . 09 / 167 , 298 , filed oct . 6 , 1998 , entitled “ rugged schottky barrier rectifiers having improved avalanche breakdown characteristics ”, the disclosure of which is hereby incorporated herein by reference . numerical simulations of the unit cell 300 of fig5 were performed using a drift region doping concentration which increased from a value of 1 × 10 16 cm − 3 at a depth of 1 micron to a value of 2 × 10 17 cm − 3 at a trench depth ( td ) of 5 microns . the thin portion of the gate electrode insulating region 124 had a thickness of 500 å , the thick portion of the gate electrode insulating region 124 had a thickness of 3000 å and the first field plate insulating region 134 had a uniform thickness of 3000 å . based on these parameters , the simulated potential contours were shown to be uniformly spaced in both the active and termination regions . the simulated current flowlines also indicated that breakdown would occur simultaneously in both the active and termination regions so long as the breakdown shielding region 117 is electrically connected to the source electrode 128 b . accordingly , breakdown in the integrated power device 300 of fig5 is not expected to be edge limited . moreover , in applications where the gd - mosfet unit cells in the active region are expected to be frequently driven into avalanche breakdown , it is preferable to move the location of avalanche breakdown to the more highly doped and deeper breakdown shielding region 117 ′ within the device 300 ′ of fig6 . in particular , by increasing the depth of the breakdown shielding region 117 ′, the breakdown voltage can be decreased to a level which will provide sufficient protection to the unit cells in the active device area and improve the lifetime and reliability of the overall device 300 ′. in addition , as described more fully hereinbelow with respect to fig7 the breakdown voltage and the specific on - resistance r sp , on can also be scaled downward by decreasing the epitaxial layer thickness of the drift region 112 . referring now to fig7 an integrated power semiconductor device 400 according to a fourth embodiment of the present invention will be described . as illustrated , this power device 400 is a hybrid device which may contain the gd - umosfet unit cells of fig2 and 3 ( having non - uniformly thick gate insulating regions therein ) extending adjacent one sidewall of each trench in the active region and a modified tmbs schottky rectifier ( acting as a flyback diode ) extending adjacent an opposing sidewall of each trench . in the modified tmbs schottky rectifier illustrated on the left side of the unit cell of fig7 preferred charge coupling is provided by a gate electrode within a trench having a non - uniformly thick gate insulating region therein , instead of an anode electrode and a uniformly thick insulating region . moreover , whereas conventional tmbs rectifiers , such as those disclosed in u . s . pat . no . 5 , 612 , 567 to baliga which is hereby incorporated herein by reference , include a linearly graded drift region doping concentration which extends all the way to the schottky rectifying junction at the face , a uniformly doped region extends adjacent the schottky rectifying junction in the modified tmbs rectifier of fig7 . as illustrated , this uniformly doped portion of the drift region has a doping concentration of 1 × 10 16 cm − 3 therein . the advantages of including a uniformly doped region adjacent the schottky rectifying junction in a tmbs device are more fully described in the aforementioned application entitled “ rugged schottky barrier rectifiers having improved avalanche breakdown characteristics ”. this hybrid power device 400 is designed so that the gd - mosfet unit cells have very low specific on - state resistance , the modified tmbs structure has very low leakage current and low on - state voltage drop and the combined hybrid structure exhibits very low parasitic inductance . in particular , simulations of the hybrid device of fig7 illustrate that the on - state voltage drop of both the gd - mosfet and modified tmbs are reduced because of improved current spreading in the n + substrate region 114 . the specific on - resistance r sp , on can also be scaled downward by decreasing the epitaxial layer thickness of the drift region 112 . this reduction in epitaxial layer thickness causes the nonrectifying junction formed between the drift region 112 and the drain region 114 ′ ( illustrated by the dotted line in fig7 ) to move up along the sidewalls of each trench , without any other modification in the process . accordingly , the reduction in epitaxial layer thickness ( or increase in trench depth ) results in the formation of an interface between the bottom of the trench 120 b and the drain region 114 ′. the simulations also indicate the possibility of higher temperature operation with smaller heat sinks because of an improvement in the leakage current characteristics . the hybrid device also limits the amount of parasitic inductance between the gd - mosfet and modified tmbs rectifiers within each unit cell . as further illustrated by fig7 an increase in the depth of the base region 116 to the level illustrated by the dotted line 116 ′ can also be used advantageously to suppress the degree of any impact ionization near the gate insulating region 124 which may arise in response to hot electron injection during avalanche breakdown . in particular , steps to form the gate insulating region so that there is an overlap between the thick portion of the gate insulating region 124 ( extending upward from the bottom of the trench ) and the base region 116 can be used to enhance the electric field contours at the corner of the gate between the thick and thin portions and thereby shield the gate insulating region from the effects of hot electron induced instabilities during avalanche breakdown . accordingly , the gate insulating region 124 may have a first thickness ( shown as t 2 ) of less than about 750 å as measured between the gate electrode 126 and a first intersection between the first sidewall and the p - n junction formed between the source region 118 and p - base region 116 . in addition , the gate insulating region 124 may have a second thickness ( shown as t 1 ) of greater than about 1500 å as measured between the gate electrode 126 and a second intersection between the first sidewall and the p - n junction formed between the p - base region 116 and the drift region 112 . moreover , because of the illustrated graded doping profile of the base region 116 which falls off near the base / drift region junction , it is still possible to form an inversion layer channel across the entire base region 116 even though the gate oxide thickness is relatively large ( e . g ., 3000 å ) at the drain side of the base region 116 . designing the unit cell to provide this gate shielding advantage may , however , result in some increase in the specific on - state resistance of the device . in the drawings and specification , there have been disclosed typical preferred embodiments of the invention and , although specific terms are employed , they are used in a generic and descriptive sense only and not for purposes of limitation , the scope of the invention being set forth in the following claims .