referring to fig1 there is shown a schematic diagram of a pndram cell 100 consisting of an nmos transistor 110 connected to a capacitor 120 . schematically , it is indistinguishable from a conventional dram single transistor ( 1t ) cell . the capacitor can be fabricated using any planar , trench , or stacked cell technology . nmos transistor 110 switches on when the wordline ( wl ) rises , coupling the storage node ns to the bitline bl . unlike conventional dram cells , a pndram cell features two alternative functions : 1 ) a temporary storage , wherein the capacitor 120 stores data as a capacitive charge , or 2 ) a permanent storage , wherein the capacitor 120 stores data as an anti - fuse caused by oxide breakdown . whenever the oxide of the capacitor 120 is not in breakdown , capacitor 120 holds data at node ns when the wordline wl is at a low potential . in order to maintain physical 1 data , the voltage at node ns must be periodically refreshed . this refresh is similar to a conventional dram refresh operation . physical 0 data does not require refreshing since the sources of the node ns leakage current are created by the n + diffusion of nmos transistor 110 , the substrate of which is connected to ground ( 0v ). this results in a non - volatile memory capable of storing physical 0 data unless the cell is overwritten to be a physical 1 . when the oxide of the capacitor 120 is in breakdown , the node ns is short - circuited to node nplt , which is connected to vdd ( 1 . 5v ). this results in a non - volatile memory that stores physical 1 data . the detailed array configuration and control methods in : ( 1 ) programming mode , and ( 2 ) read / write modes will be discussed next . fig2 shows a block diagram and the internal timing of a pndram . the pndram 200 consists of a core 230 consisting of cell array 205 , row decoder ( rdec ) 250 , column decoder ( cdec ) 260 , sense amplifiers 210 , and column switches 220 . the pndram core 230 is supported by address buffer block 240 , control block 280 , data input / output ( dq ) block 270 , in accordance with known dram protocols , including its conventional row address storable signal ({ overscore ( xras )}), column address strobe signal ({ overscore ( xcas )}), and write enable signal ({ overscore ( xwe )}). the following discussion assumes that control pins of the pndram follows existing asynchronous dram standards , with a row address strobe { overscore ( ras )} and a column address strobe { overscore ( cas )}. when the signal { overscore ( xras )} falls , control block 280 generates a row internal signal , labeled rint . rint activates address buffer 240 , triggering rdec 250 in core 230 . one wordline wl 202 in array 205 then rises in accordance with the decoded result . this allows cell data 100 to be read on bitlines bl /{ overscore ( bl )} 204 , generating a small voltage difference between bl and { overscore ( bl )} pair . after the signal has been sufficiently developed on the bl /{ overscore ( bl )} pair , sense amplifiers 210 are enabled , latching the data in the sense amplifiers . when the signal { overscore ( xcas )} falls , control block 250 generates a column internal signal ( cint ). the state of the read / write internal signal rwint can be determined by the polarity of { overscore ( xwe )} when { overscore ( xcas )} falls . if xwe is at high at the falling edge of { overscore ( xcas )}, rwint switches to high , indicative of a read mode . if { overscore ( xwe )} is at low at the falling edge of { overscore ( xcas )}, rwint switches to low , which is indicative of a write mode . address buffer 240 generates column addresses which are subsequently transferred to column decoder cdec 260 . column switch 220 is activated as a function of the decoding result . this allows bit information in the corresponding sense amplifier to be transferred to io circuit 270 by way of the data input / output bus ( i / o -{ overscore ( i / o )} pair ). data appears at the i / o pin when operating in read mode . a write mode operates in the opposite manner . fig3 shows a detailed configuration of pndram core 230 ( fig2 ) that consists of a plurality of 1t cells 100 arranged in an array matrix 205 ( fig2 ), cmos cross - coupled sense amplifiers 210 , and column switches 220 . for simplicity sake , sense amplifiers 210 are not shared with other arrays , although in a standard dram array design , sense amplifiers are typically shared with bitline multiplexing ( not shown ). row decoder ( rdec ) 250 and column decoders ( cdec ) 260 , shown in fig2 are thus eliminated . unlike a dram , the pndram array newly includes a programming mode , wherein any 1t cells 100 can be electrically programmed as an eprom cell or as an anti - fuse , by controlling voltage signals nplt 206 and φeq 208 . the following discussion assumes that the capacitor oxide of the cell 100 is in breakdown mode when 7v are applied between nplt and node ns . the pndram is provided with a plate voltage control mode which allows node nplt to be forced externally by multiplexing the data mask pin ( dqm ) or any other alternative pin ( not shown ). the detailed eprom programming mode in the pndram is realized by the procedures described hereinafter . step 1 : when the signal { overscore ( ras )} ( not shown ) remains at high , epdram is in stand - by mode , and all the wordline wls , { overscore ( φp )}, φn , φeq , csls alternate between gnd ( 0v ), vdd ( 1 . 5v ), gnd ( 0v ), vdd ( 1 . 5v ), and gnd ( 0v ), respectively . the bitline bls are precharged to ½ vdd ( 0 . 75v ), and all storage node nss are isolated from the respective bitlines bl . the voltage of node nplt and 10 lines are connected to gnd ( 0v ) and vdd ( 1 . 5v ), respectively . [ note that the node nplt is common to all the cells of the array ]. step 2 : a plate voltage control mode is enabled , coupling node nplt to pin dqm ( not shown ) or to any equivalent pin typical of a dram standard package . the node nplt is then forced from its value at the dqm pin to 5v . since all storage nodes ns are isolated from the bitlines bl , the voltage swing 0v - 5v at nplt couples nodes ns to 5v . the ns voltage is assumed to have been originally at 0v ( or close to it ) because of the nmos array . optionally , physical 0 data may be written into all the nodes ns using a dram write to guarantee 0v voltage . the ns voltages become , therefore , 5v . step 3 : the signal { overscore ( ras )} is enabled to initiate a pndram refresh mode , which is similar to any typical dram refresh protocol . this switches φeq to low , disabling the bitline bl equalizers . the following discussion assumes that cell 100 & lt ; i , j & gt ; needs to be programmed as an eprom cell . the corresponding wl & lt ; i & gt ; rises to the boosted wl voltage ( 3v ). cells 100 & lt ; i , j & gt ; and 100 & lt ; i + 1 , j & gt ; initiate a signal . nodes ns & lt ; i , j & gt ; and ns & lt ; i + 1 , j & gt ; are coupled to bitlines bli and bli + 1 , respectively . the voltages at bl & lt ; i & gt ; and bl & lt ; i + 1 & gt ; increase by a certain amount ( e . g ., 300 mv ). signals φn and φp then switch to high and low , respectively . cmos sense amplifiers 210 are activated , as it is done in a conventional dram ½ vdd sensing scheme . bl & lt ; i & gt ;, { overscore ( bl )}& lt ; i & gt ;, bl & lt ; i + 1 & gt ; and { overscore ( bl )}& lt ; i + 1 & gt ; become 1 . 5v , 0v , 1 . 5v and 0v , respectively , once the sense amplifiers 210 have amplified the bitlines bl voltages . step 4 : as it is done in a conventional dram write mode , the signals { overscore ( cas )} and { overscore ( we )} ( not shown ) are activated , thereby writing physical 0 data in cell & lt ; i , j & gt ;. io and { overscore ( io )} are forced to 0v and 1 . 5v , respectively , switching the corresponding csl & lt ; i & gt ; to high ( 1 . 5v ). bl & lt ; i & gt ; and { overscore ( bl )}& lt ; i & gt ; forced by io ( 0v ) and { overscore ( io )} ( 1 . 5v ), correspondingly switch bl & lt ; i & gt ; and { overscore ( bl )}& lt ; i & gt ; to low ( 0v ) and high ( 1 . 5v ), respectively . this allows node ns & lt ; i , j & gt ; to switch to 0v . [ note : bl & lt ; i + 1 & gt ; and { overscore ( bl )}& lt ; i + 1 & gt ; remain at 1 . 5v and 0v , respectively , while ns & lt ; i + 1 , j & gt ; remains at 1 . 5v ]. step 5 : node nplt is boosted from 5v to 7v . nodes ns & lt ; i , j + 1 & gt ; and ns & lt ; i + 1 , j + 1 & gt ; switch to 7v due to the swing of node nplt . on the other hand , nodes ns & lt ; i , j & gt ; and ns & lt ; i + 1 , j & gt ; remain at 0v and 1 . 5v , respectively , because they are forced by the corresponding sense amplifiers 210 . [ note that the voltage difference between node ns & lt ; i , j & gt ; and node nplt is 7v , resulting in the cell oxide breaking down ]. as a result , node ns & lt ; i , j & gt ; is short - circuited to node nplt . node ns & lt ; i + 1 , j & gt ;, on the other hand , is not short - circuited to node nple since the voltage of ns & lt ; i + 1 , j & gt ; remains at high ( 1 . 5v ) when only 5 . 5v are applied to the capacitor of cell 100 & lt ; i + 1 , j & gt ;. similarly , the voltages of the capacitors of cells 100 & lt ; i , j + 1 & gt ; and 100 & lt ; i + 1 , j + 1 & gt ; are 0v , thereby precluding an oxide breakdown from occurring . step 6 : steps 0 - 5 are repeated to program any cells as eprom cells by design or by customer &# 39 ; s request . the pndram read mode operation is essentially the same as it was done for the dram cell read mode discussed previously . node nplt is coupled to vdd ( 1 . 5v ). if node ns of cell 100 is not short - circuited to node nplt , the cell will behave as any conventional dram cell or as a physical 0 eprom cell . if short - circuited to node nplt , the read result will be a physical 1 , and the cell will behave as a physical 1 eprom cell . there is no write mode for a pndram except for the one time programming mode discussed previously . dram cells need to be refreshed in a conventional refresh operation . although the eprom cells do not require it , optionally they can also be refreshed as it is routinely done to conventional dram cells . this allows maintaining existing dram standard . fig4 shows an experimental 128 mb pndram core 230 consisting of thirty - two 4 mb arrays ( 205 ), row decoder ( rdec ) 250 , and column decoder ( cdec ) 260 . the concept of the pndram has been confirmed by an experimental 128 mb dram by enabling the proposed pndram protocol and methodology with one 4 mb array ( 205 ). it also shows the bit - map wherein cells showing t - shape are electrically programmed . [ note : other cells operate as dram cells ]. the cells electrically programmed can maintain the data even after the chip is powered off . optionally , all cells , regardless whether dram or eprom cells , may write a physical 0 data pattern as the power - on mode . this power - on mode guarantees that the eprom cells having this physical 0 data actually store a physical 0 . the power - on mode may be enabled by either an external pndram command or internally by on - chip control logic . although the invention in its preferred embodiment uses a 8f 2 1t transistor cells , the concept can be applicable for any type of cells such as 7f 2 , 6f 2 , 5f 2 , and 4f 2 . in summary , the invention provides control methods and applications to have 1t ( or 2t ) cells behave as dram cells and eprom cells . the oxide breakdown voltage is applied to eprom cells selected by the wl , csl , sense amplifiers , and plate voltage control . the invention also assumes a ½ vdd sensing scheme . however , any vdd pre - charged sensing schemes are applicable for a given reference voltage . while the invention has been discussed in terms of a preferred embodiment with 8f ½ vdd sensing scheme , those skilled in the art will recognize that other changes and modifications may be introduced without affecting the scope and the spirit of the invention .