3 nm process

In semiconductor manufacturing, the 3 nm process is the next die shrink after the 5-nanometre MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. , Intel, Samsung, and TSMC have all announced plans to put a 3 nm semiconductor node into commercial production. Samsung's process is based on GAAFET (gate-all-around field-effect transistor) technology, a type of multi-gate MOSFET technology, while TSMC's 3nm process will still use FinFET (fin field-effect transistor) technology, despite TSMC developing GAAFET transistors. Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (multi-bridge channel field-effect transistor).
The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density, increased speed and reduced power consumption. For example, TSMC has stated that its 3nm FinFET chips will reduce power consumption by 25 to 30 percent at the same speed, increase speed by 10 to 15 percent at the same amount power and increase transistor density by about 33 percent compared to its previous 5nm FinFET chips.
History.
Research and technology demos.
In 1985, a Nippon Telegraph and Telephone (NTT) research team fabricated a MOSFET (NMOS) device with a channel length of 150 nm and gate oxide thickness of 2.5 nm. In 1998, an Advanced Micro Devices (AMD) research team fabricated a MOSFET (NMOS) device with a channel length of 50 nm and oxide thickness of 1.3 nm.
In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm, using the PMOS and NMOS processes. In 2006, a team from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center, developed a 3 nm width multi-gate MOSFET, the world's smallest nanoelectronic device, based on gate-all-around (GAAFET) technology.
Commercialization history.
In late 2016, TSMC announced plans to construct a 5 nm–3 nm node semiconductor fabrication plant with a co-commitment investment of around US$15.7 billion.
In 2017, TSMC announced it was to begin construction of the 3 nm semiconductor fabrication plant at the Tainan Science Park in Taiwan. TSMC plans to start volume production of the 3 nm process node in 2023.
In early 2018, IMEC and Cadence stated they had taped out 3 nm test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography.
In early 2019, Samsung presented plans to manufacture 3 nm GAAFET (gate-all-around field-effect transistors) at the 3 nm node in 2021, using its own MBCFET transistor structure that uses nanosheets instead of nanowires; delivering a 35% performance increase, 50% power reduction and a 45% reduction in area when compared with 7nm. Samsung's semiconductor roadmap also included products at 8, 7, 6, 5, and 4 nm 'nodes'.
In December 2019, Intel announced plans for 3 nm production in 2025.
In January 2020, Samsung announced the production of the world's first 3 nm GAAFET process prototype, and said that it is targeting mass production in 2021.
In August 2020, TSMC announced details of its N3 3 nm process, which is new rather than being an improvement over its N5 5 nm process. Compared with the N5 process, the N3 process should offer a 10–15% (1.10–1.15×) increase in performance, or a 25–35% (1.25–1.35×) decrease in power consumption, with a 1.7× increase in logic density (a scaling factor of 0.58), a 20% increase (0.8 scaling factor) in SRAM cell density, and a 10% increase in analog circuitry density. Since many designs include considerably more SRAM than logic, (a common ratio being 70% SRAM to 30% logic) die shrinks are expected to only be of around 26%. TSMC plans risk production in 2021 with volume production in the second half of 2022.
Beyond 3 nm.
The ITRS uses (as of 2017) the terms "2.1 nm", "1.5 nm", and "1.0 nm" as generic terms for the nodes after 3 nm. "2-nanometre" (2 nm) and "14 angstrom" (14 Å or 1.4 nm) nodes have also been (in 2017) tentatively identified by An Steegen (of IMEC) as future production nodes after 3 nm, with hypothesized introduction dates of around 2024, and beyond 2025 respectively.
In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes; however, as of 2019, other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable. TSMC began research on 2 nm in 2019. It has been reported that TSMC is expected to enter 2 nm risk production around 2023 or 2024.
In December 2019, Intel announced plans for 1.4 nm production in 2029. 
In May 2021 IBM announced it had produced 2 nm chipmaking technology at their manufacturing research center in Albany and had successfully made a prototype "fingernail-sized" chip with upwards of 50 billion transistors,
which translates to 333 million transistors per square millimeter (assuming a chip area of 150 square millimeters as communicated by IBM). By comparison, TSMC's 3nm chips would contain around 291 million transistors per square millimeter.