PowerPC 400

The PowerPC 400 family is a line of 32-bit embedded RISC processor cores based on the PowerPC or Power ISA instruction set architectures. The cores are designed to fit inside specialized applications ranging from system-on-a-chip (SoC) microcontrollers, network appliances, application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) to set-top boxes, storage devices and supercomputers.
Applied Micro Circuits Corporation (AMCC) bought assets concerning the 400 family cores from IBM in April 2004 for $227 million, and they now market the processors under their own name. IBM continues evolving the cores while supplying design and foundry services around the cores. Several cores are also available for licensing by OEMs from IBM and Synopsys.
Variants.
PowerPC 403.
Introduced in 1994, the PowerPC 403 was one of the first PowerPC processors. It was the first one targeted strictly to the embedded market. Compared to the other PowerPC processors of the era (PowerPC 601, PowerPC 603 and PowerPC 604), it was at the very low end, lacking a memory management unit (MMU) or floating point unit (FPU), for instance. The core was offered for custom chips and in pre packaged versions, including versions with MMU, speeds ranging from 20 to 80 MHz.
The PowerPC 403 is used in, among other appliances, thin clients, set-top boxes, RAID-controllers, network switches and printers. The first TiVo used a 54 MHz PowerPC 403GCX.
AMCC acquired the design of 403 from IBM in 2004, but have chosen not to market it, instead focusing on the 405 and 440 cores.
PowerPC 401.
While the 403 was popular, it was also too high performance and too costly for some applications, so in 1996 IBM released a bare bones PowerPC core, called PowerPC 401. It has a single issue, three-stage pipeline, with no MMU or DMA and only 2 KB instruction and 1 KB data L1 caches. The design contained just 85,000 transistors in all and operated at up to 100 MHz, drawing only 0.1 W or less. Applications using the 401 core range from set-top boxes and telecom switches to printers and fax machines.
PowerPC 405.
The PowerPC 405 was released in 1998 and was designed for price or performance sensitive low-end embedded system-on-a-chip (SoC) designs. It has a five-stage pipeline, separate 16 KB instruction and data L1 caches, a CoreConnect bus, an Auxiliary Processing Unit (APU) interface for expandability and supports clock rates exceeding 400 MHz. The 405 core adheres to the Power ISA v.2.03 using the Book III-E specification. Both AMCC and IBM are developing and marketing processors using 405 cores. IBM and Synopsys also offers a fully synthesizable core. IBM has announced plans to make the specifications of the PowerPC 405 core freely available to the academic and research community.
PowerPC-405-based applications include digital cameras, modems, set-top boxes (IBM's STB04xxx processors), cellphones, GPS-devices, printers, fax machines, network cards, network switches, storage devices and service processors for servers. Up to two 405 cores are used in Xilinx Virtex-II Pro and Virtex-4 FPGAs. In 2004 Hifn bought IBM's PowerNP network processors that uses 405 cores.
PowerPC 440.
Introduced in 1999, the PowerPC 440 was the first PowerPC core from IBM to include the "Book E" extension to the PowerPC specification. It also included the CoreConnect bus technology designed to be the interface between the parts inside a PowerPC based system-on-a-chip (SoC) device.
It is a high-performance core with separate 32 KB instruction and data L1 caches, a seven-stage out-of-order dual-issue pipeline, supporting speeds of up to 800 MHz and L2 caches up to 256 KB. The core lacks a floating point unit (FPU) but it has an associated four-stage FPU that can be included using the APU (Auxiliary Processing Unit) interface. The 440 core adheres to the Power ISA v.2.03 using the Book III-E specification.
Xilinx currently incorporates one or two cores (depending on the member of the family) into the Virtex-5 FXT FPGA.
Both AMCC and IBM are developing and marketing stand alone processors using 440 cores. IBM and Synopsys also offers fully synthesized cores.
PowerPC 450.
The processing core of the Blue Gene/P supercomputer designed and manufactured by IBM. It is very similar to the PowerPC 440 but few details are disclosed.
PowerPC 460.
Introduced in 2006, the 460 cores are similar to the 440 but reach 1.4 GHz, are developed with multi-core applications in mind and have 24 additional digital signal processing (DSP) instructions. The cores are designed to be low-power but high performance and the 464-H90 is expected to draw only 0.53 W at 1 GHz. The 460 core adheres to Power ISA v.2.03 using the Book III-E specification.
PowerPC 470.
The 470 embedded and customizable core, adhering to the Power ISA v2.05 Book III-E, was designed by IBM together with LSI and implemented in the PowerPC 476FP in 2009. The 476FP core has 32/32 kB L1 cache, dual integer units and a SIMD capable double precision FPU that handles DSP instructions. Emitting 1.6 W at 1.6 GHz on a 45 nm fabrication process. The 9 stage out of order, 5-issue pipeline handles speeds up to 2 GHz, supports the PLB6 bus, up to 1 MB L2 cache and up to 16 cores in SMP configurations.