EVEX prefix

The EVEX prefix (Enhanced vector extension) and corresponding coding scheme is an extension to the 32-bit x86 (IA-32) and 64-bit x86-64 (AMD64) instruction set architecture. EVEX is based on, but should not be confused with the MVEX prefix used by the Knights Corner processor.
The EVEX scheme is a 4-byte extension to the VEX scheme which supports the AVX-512 instruction set and allows addressing new 512-bit ZMM registers and new 64-bit operand mask registers.
Features.
EVEX coding can address 8 operand mask registers, 16 general-purpose registers and 32 vector registers in 64-bit mode (otherwise, 8 general-purpose and 8 vector), and can support up to 4 operands.
Like the VEX coding scheme, the EVEX prefix unifies existing opcode prefixes and escape codes, memory addressing and operand length modifiers of the x86 instruction set .
The following features are carried over from the VEX scheme: 
EVEX also extends VEX with additional capabilities:
For example, the EVEX encoding scheme allows conditional vector addition in the form of
 VADDPS zmm1 {k1}{z}, zmm2, zmm3
where {k1} modifier next to the destination operand encodes the use of opmask register k1 for conditional processing and updates to destination, and {z} modifier (encoded by EVEX.z) provides the two types of masking (merging and zeroing), with merging as default when no modifier is attached.
Technical description.
The EVEX coding scheme uses a code prefix consisting of 4 bytes; the first byte is always 62h and derives from an unused opcode of the 32-bit BOUND instruction, which is not supported in 64-bit mode. 
The ModR/M byte specifies one operand (always a register) with "reg" field, and the second operand is encoded with "mod" and "r/m" fields, specifying either a register or a location in memory. Base-plus-index and scale-plus-index addressing require the SIB byte, which encodes 2-bit "scale" factor as well as 3-bit "index" and 3-bit "base" registers. Depending on the addressing mode, Disp8/Disp16/Disp32 field may follow with displacement that needs to be added to the address.
The EVEX prefix retains fields introduced in the VEX prefix:
New functions of the existing fields:
There are several new bit fields:
The encoding of the EVEX prefix is as follows:
The following table lists possible register addressing combinations (bit 4 is always zero when encoding the 16 general purpose registers):
A few VEX-encoded AVX blending instructions have 4 operands. To accommodate this, VEX has IS4 addressing mode, which encodes 4th operand (a vector register) in bits Imm8[7:4] of the immediate constant. Similar EVEX-encoded blend instructions have their 4th operand in a mask register. No EVEX-encoded instruction uses IS4 addressing mode encoding.