Clarkdale (microprocessor)

Clarkdale is the code name for an Intel processor, initially sold as desktop Intel Core i5 and Core i3 and Pentium. It is closely related to the
mobile Arrandale processor; both use dual-core dies based on the
Westmere 32 nm die shrink of the Nehalem microarchitecture, and have integrated Graphics as well as PCI Express and DMI links.
Clarkdale is the successor of the 45 nm Core microarchitecture-based Wolfdale processor that is used in the many desktop Intel Core 2, Celeron and Pentium Dual-Core processors. While Wolfdale typically used both a north bridge and a south bridge, Clarkdale already contains the major north bridge components, which are the memory controller, PCI Express for external graphics, integrated graphics and the DMI connector, making it possible to build more compact systems without a separate northbridge or discrete graphics as Lynnfield.
The Clarkdale processor package contains two dies: the 32 nm processor die with the I/O connections, and the 45 nm graphics and integrated memory controller die. Physical separation of the processor die and memory controller die resulted in increased memory latency.
The CPUID for Clarkdale is family 6, model 37 (2065x). The mobile equivalent of Clarkdale is Arrandale.
Brand names.
Clarkdale processors are sold under the Intel Core, Pentium and Celeron brand names, with varying feature sets. The Core i5 versions generally have all features enabled, with the Core i5-661 and Core i5-655K models lacking Intel VT-d and TXT like the Core i3, which also does not support Turbo Boost and AES new instructions. In addition, the Pentium and Celeron versions do not have SMT, and they can only use a reduced amount of third-level cache.
The Xeon L340x line has a lower clock frequency and thermal design power, and supports unbuffered ECC memory in addition to the features of the Core i5-6xx, but has support for the integrated graphics disabled.
Importantly, although the memory controller in Clarkdale processors is on-package, it is on a separate die from the CPU cores, and thus has increased latency compared to processor architectures which integrate it on-die with the main CPU cores.