2 nm process

In semiconductor manufacturing, the 2 nm process is the next die shrink after the 3 nm process node. As of 2020, both TSMC and Intel have 2nm products on their roadmaps, with earliest production scheduled for 2023 or later.
Background.
In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes; however, as of 2019, other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable.
TSMC began research on 2 nm in 2019. TSMC expected to transition from FinFET to GAAFET transistor types when moving from 3nm to 2nm. It has been reported that TSMC is expected to enter 2 nm risk production around 2023 or 2024. 
Intel's 2019 roadmap scheduled potentially equivalent 3 nm and 2 nm nodes for 2025 and 2027 respectively. In December 2019, Intel announced plans for 1.4 nm production in 2029.
In August 2020, TSMC began building a R&D lab for 2 nm technology in Hsinchu, expected to become partially operational by 2021. In September 2020 (SEMICOM Taiwan 2020) it was reported that TSMC Chairman Mark Liu had stated the company would build a plant for the 2 nm node at Hsinchu in Taiwan, and that it could also install production at Taichung dependent on demand. 
At the end of 2020, seventeen of the European Union countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as 2 nm as well as a designing and manufacturing custom processors, assigning up to 145 billion euro in funds.
In May 2021, IBM announced it had produced 2 nm class transistor using three silicon layer nanosheets with a gate length of 12nm.