AMD Lance Am7990

AMD Lance Am7990 IEEE 802.3 Ethernet Media Access Controller (MAC) controller were introduced in 1985. Its architecture is the basis for AMD's PCnet Family of highly integrated single-chip Ethernet controllers. The one exception is the Am79C940 MAC.
The Am7990 chip was fabricated in NMOS technology and has no integrated Manchester encoder/decoder (ENDEC) nor does it have an integrated 10BASE-T transceiver.
Compatibility.
A later refabricated chip called the C-LANCE Am79C90 is made with 0.8 micrometre CMOS technology. The original NMOS version Am7990 and the CMOS Am79C90 version differ in some details which may affect device driver compatibility.
The datasheet for the CMOS version states that the CMOS and NMOS versions are the same. But the "Table B-1. Comparison Summary of the C-LANCE and LANCE Devices" in the datasheet shows they differ. These differences are not likely to require modifications of any device driver.
The PCnet family of Ethernet controllers (PCnet-ISA II, PCnet-32, PCnet-PCI II and PCnet-FAST) is LANCE software compatible. This means you should be able use the original 16-bit software on these members of the PCnet family of single-chip Ethernet controllers.
Features.
The Am7990 can handle 10BASE-5 Type A, 10BASE-2 Type B, and 10BASE-T. Back-to-back packet reception with as little as 0,5 μs interframe spacing. DMA/Bus mastering 24-bit (16M) address capable. Up to 128 ring buffers can be used. 48 byte receive/transmit FIFO. Operates with supply and logic. Features a Time-domain reflectometer (TDR) with a granularity of 30 meter. maximum frequency. 
Physically a DIP-48 or PLCC-68 package is used.
CSR0 slave read data can cause timing violations on DAL lines.
Chip bugs.
The old LANCE (Rev. C) chips have a bug which causes garbage to be inserted in front of the received packet. The workaround is to ignore packets with an invalid destination address (garbage will usually not match). Of course, this precludes multicast support.
The Amiga SANA-II network interface API has poor multicast support. And this chip bug might be the reason.
No capability for transmit buffer byte count of zero.
Receive lockup may occur if bus latency is large.
External loopback on a live network may cause reception of invalid loopback failure indications.
Receive descriptor zero byte count buffer interpreted as 4096 available bytes.
Will poll computer memory every 1.6 ms for new packets to transmit.