Low-power FSM synthesis

Finite state machines (FSMs) are widely used to implement control logic in various applications such as microprocessors, digital transmission, digital filters and digital signal processing. Even for designs containing a good number of datapath elements, the controller occupies a sizeable portion. As the devices are mostly portable and hand-held, reducing power dissipation has emerged as the primary concern of today’s VLSI designers. While the datapath elements can be shut down when they are not being used, controllers are always active. As a result, the controller consumes a good amount of system power. Thus, power-efficient synthesis of FSM has come up as a very important problem domain, attracting a lot of research. The synthesis method must be able to reduce both dynamic power and leakage power consumed by the circuit.
FSM synthesis.
An FSM can be defined as a quintuplet that consists of a set of primary inputs, a set of primary outputs, a set of states, a next-state function and an output function. The next-state function maps the present-state and the primary inputs to a next-state; the output function maps the primary inputs and present-state onto the primary outputs. Any deterministic sequential function can be represented by the use of this model. A FSM can be separated into two parts viz., combinational circuit and memory.
The optimal synthesis of finite-state machines is an important step in digital design. The three basic steps involved in the FSM synthesis are:
Low-power synthesis.
In CMOS circuits, power is dissipated in a gate when the gate output changes from 0 to 1 or from 1 to 0. Optimizing for low average power consumption in digital CMOS circuits is in most of the cases motivated by reducing the problems related to either heat generated by the integrated circuit (IC) or by limited power supply resources, as in portable battery-operated equipment.
The most common approach for low power FSM synthesis is to divide the FSM into two or more sub-FSMs in which at any given instant only one of these is active. The power minimization problem can be considered at various levels viz., algorithmic, architectural, logic and circuit levels. The dynamic power consumed in synchronous CMOS circuits is given by:
 formula_1
where formula_2 is the probability of a signal transmission within a clock period at node formula_3, formula_4 is the switched capacitance, formula_5 is the supply voltage and formula_6 is the clock frequency.
Limitations.
The amount of power that is saved by partitioning the FSM is mainly determined by how good the partitioning algorithm can cluster strongly connected states together in sub-FSMs and by how large the cost is, in terms of power, to make a state transition from one sub-FSM to another.