WDC 65C51

The CMOS W65C51 Asynchronous Communications Interface Adapter (ACIA) provides an easily implemented, program controlled interface between microprocessor based systems and serial communication data sets and modems. It is produced by Western Design Center (WDC) and is a drop-in replacement for the MOS Technology 6551.
The ACIA has an internal baud rate generator, eliminating the need for multiple component support circuits. The transmitter rate can be selected under program control to be 1 of 15 different rates from 50 to 19,200 bits per second, or at 1/16 times an external clock rate. The receiver rate may be selected under program control to be either the Transmitter rate or at 1/16 times the external clock rate. The ACIA has programmable word lengths of 5, 6, 7 or 8 bits; even, odd or no parity 1, 1½ or 2 stop bits.
The ACIA is designed for maximum programmed control from the microprocessor (MPU) to simplify hardware implementation. Three separate registers permit an MPU to easily select the W65C51 operating modes, data checking parameters and determine operational status.
The command register controls parity, receiver echo mode, transmitter interrupt control, the state of the RTS line, receiver interrupt control and the state of the DTR line.
The control register controls the number of stop bits, the word length, receiver clock source and transmit/receive rate.
The status register indicates the status of the IRQ, DSR and DCD lines, transmitter and receiver data Registers, and overrun, framing and parity error conditions.
Transmitter and receiver data Registers are used for temporary data storage by the transmit and receiver circuits, each able to hold one byte.
Known bugs.
The N version datasheet has a note regarding the Transmitter Data Register Empty flag:
"The W65C51N loads the Transmitter Data Register (TDR) and Transmitter Shift Register (TSR) at the same time. A delay should be used to insure that the shift register is empty before the TDR/TSR is reloaded. This feature of the W65C51N works different from earlier 6551 designs."
This means the TDRE flag cannot be relied on for flow control.
The S version datasheet has removed this note.
It has been reported that some W65C51 chips have the TDRE flag stuck high<ref name="https://github.com/andrew-jacobs/w65c816sxb-hacker/blob/master/w65c816sxb.inc">https://github.com/andrew-jacobs/w65c816sxb-hacker/blob/master/w65c816sxb.inc</ref>