Delay calculation

Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and wire.
There are many methods used for delay calculation for the gate itself. The choice depends primarily on the speed and accuracy required:
Similarly there are many ways to calculate the delay of a wire. The delay of a wire will normally be different for each destination. In order of increasing accuracy (and decreasing speed), the most common methods are:
Often, it makes sense to combine the calculation of a gate and all the wire connected to its output. This combination is often called the "stage delay".
The delay of a wire or gate may also depend on the behaviour of the nearby components. This is one of the main effects that is analyzed during signal integrity checks.
Delay calculation in digital design.
In the context of semi-custom digital design, pre-characterized digital information is often abstracted in the form of the above mentioned 2-D look up table (LUT). The idea behind semi-custom design method is to use blocks of pre-built and tested components to build something larger, say, a chip.
In this context, the blocks are logic gates such as NAND, OR, AND, etc. Although in reality these gates will be composed of transistors, a semi-custom engineer will only be aware of the delay information from input pin to output pin, called a timing arc. The 2D table represents information about the variability of the gate's delay with respect to the two independent variables, usually the rate of change of the signal at the input and the load at the output pin. These two variable are called slew and load in design parlance. 
A static timing analysis engine will first calculate the delay of the individual cells and string them together to do further analysis.
Statistical delay calculation.
As chip dimensions get smaller, the delays of both gates and wires may need to be treated as statistical estimates instead of deterministic quantities. For gates, this requires extensions to the library formats. For wires, this requires methods that can calculate the means and distributions of wire delays. In both cases it is critical to capture the dependence on the underlying variables such a threshold voltage and metal thickness, since these result in correlations among the delays of nearby components. See for an early example.