
Boundary scan description language

Boundary scan description language (BSDL) is a hardware description language for electronics testing using JTAG. It has been added to the IEEE Std. 1149.1, and BSDL files are increasingly well supported by JTAG tools for boundary scan applications, and by test case generators.
BSDL overview.
BSDL was a subset of VHDL. However, since IEEE 1149.1-2013, it is no longer a "proper" subset of VHDL but it is considered based on VHDL. It is formally defined in IEEE Standard 1149.1 Annex B. Each BSDL file describes one version of an IC and has many package pin maps as are available for a particular die. This is necessary because, for example, two different BGA packages will have different balls; even if the ball has the same name it may be bonded to a different signal on the other package, and sometimes bondings change between revisions.
Each digital signal (pin or ball) on the package is defined, as are the registers and opcodes used in an IEEE 1149.1, IEEE 1149.6, IEEE 1149.8.1, IEEE 1532 and IEEE 1149.4 compliant IC. There is one instruction register, a minimum of a 1-bit bypass register, one boundary scan register and optionally a 32 bit device_id register. The registers other than the instruction register are called TDRs or Test Data Registers. The boundary scan register (BSR) is unique as it is the register which is also mapped to the I/O of the device. Many of the BSDL definitions are sets of single long string constants.
Note that registers not involved in boundary scan are often not defined. Instructions that are not publicly defined are included in the INSTRUCTION_PRIVATE section. Microprocessor register descriptions in BSDL typically do not include enough information to aid in building a 1149.1 based emulator or debugger.