
List of Xilinx FPGAs

This article contains general information about field-programmable gate array (FPGA) devices from Xilinx, based on official specifications.
Terminology.
The fields in the table listed below describe the following:
Model naming.
The model name of most devices has some indication of its size, but the exact scheme used has varied over time:
Series overview.
Note: The process information for early FPGA devices (before Virtex) may be inaccurate, due to the devices being subject to die shrink without changing the model name — the process listed above may not be the only process in which a given device has been manufactured.
Early FPGA devices.
XC2000.
The XC2000 devices have the following user-programmable blocks:
Note: the available user I/O amount varies with chip packaging.
XC3000.
The XC3000 devices have the following user-programmable blocks:
Note: the available user I/O amount varies with chip packaging.
XC4000, Spartan.
The XC4000 and Spartan devices have the following user-programmable blocks:
Note: the available user I/O amount varies with chip packaging.
XC5200.
The XC5200 devices have the following user-programmable blocks:
Note: the available user I/O amount varies with chip packaging.
XC6200.
The XC6200 family is unusual in several ways:
XC8100.
The XC8100 family is unusual in several ways:
Virtex, Spartan-II.
The Virtex and Spartan-II devices are made of the following user-programmable blocks:
The Virtex and Spartan-II devices are functionally identical to each other and differ only in available size range, performance, and packaging options. The Spartan-IIE devices use the same die as the corresponding Virtex E devices, but have some block RAM and DLLs disabled.
Note: the available user I/O amount varies with chip packaging. Additionally, not all I/Os can be used as part of a differential pair, so the available differential pair count can be smaller than half of the available I/O count.
Virtex-II.
The Virtex-II devices are made of the following user-programmable blocks:
Virtex-II Pro devices include some additional blocks:
Note: the available user I/O and multi-gigabit transceiver amount varies with chip packaging.
Note: the CLB count for Virtex-II Pro devices is no longer a simple columns×rows multiplication, as the CLB grid contains holes for the PowerPC cores.
Spartan-3.
The Spartan-3 devices are made of:
Note: the available user I/O amount varies with chip packaging. Additionally, not all I/Os can be used as part of a differential pair, so the available differential pair count can be smaller than half of the available I/O count.
Note: for families other than Spartan-3, the CLB grid is irregular and includes holes for block RAMs and DCMs, so the CLB count is not a simple multiplication of columns×rows
Virtex-4.
The Virtex-4 devices are made of:
The Virtex-4 FX devices additionally contain:
Note: the I/O banks count includes special bank 0, which contains only dedicated configuration I/O (no user I/O)
Note: the available user I/O, I/O bank, and multi-gigabit transceiver amount varies with chip packaging.
Note: the CLB count for FX devices is no longer a simple columns×rows multiplication, as the CLB grid contains holes for the PowerPC cores.
Virtex-5.
The Virtex-5 devices are made of:
Note: the I/O banks count includes special bank 0, which contains only dedicated configuration I/O (no user I/O)
Note: the available user I/O, I/O bank, and multi-gigabit transceiver amount varies with chip packaging.
Note: the CLB count for FXT devices is no longer a simple columns×rows multiplication, as the CLB grid contains holes for the PowerPC cores.
Virtex-6.
The Virtex-6 devices are made of:
Note: the I/O banks count does not include special bank 0, which contains only dedicated configuration I/O (no user I/O)
Note: the available user I/O, I/O bank, and multi-gigabit transceiver amount varies with chip packaging.
Note: Virtex-6 CLB grid is irregular and contains holes (for configuration center and PCI Express blocks), and so the CLB count is no longer a simple columns×rows multiplication
Note: The CXT devices use an identical die to the corresponding LXT devices, but with some disabled blocks and reduced performance (GTX transceivers have a speed range of 150 Mb/s to 3.75 Gb/s).
Spartan-6.
The Spartan-6 devices are basically Spartan-3A DSP devices upgraded with some Virtex-6 technology. They are made of:
7 Series.
The 7 series devices are made of:
Depending on exact device family, devices may also contain some special blocks:
Note: many 7 series devices are actually software-limitted versions of larger devices: for example, XC7A35T is the exact same die as XC7A50T, with the same geometry and block count, but the Xilinx development tools artificially limit device usage to the limits in the table above. Such software-limitted devices have very different behavior from "full" devices when nearing full utilization: a design that would have utilized 90% of XC7A50T resources will most likely fail to route (or succeed with very suboptimal performance), since the place&route tool will have very little space to optimally arrange blocks and will likely run out of routing resources due to suboptimal placement. However, an XC7A35T design that utilizes even 100% of its resources will almost certainly route with no performance degradation, as it is far from the real hardware limits, and the placer has full freedom to utilize any subset of the available blocks as long as the total used CLB/DSP/block RAM count is within the allowed software limit. The software-enforced limits are marked with * in the above table.
Note: some Spartan-7 devices are identical to some Artix-7 devices, but with disabled transceivers. However, this is different from the above software-enforced usage limit: the transceivers cannot be used anyway, as their power and I/O pads are not bonded out to device pins in the packaging.
Note: the Artix-7 devices use the same PCI Express block as Kintex-7 devices, with Gen2×8 support, but they can only be used in at most Gen2×4 configuration due to GTP transceiver limitations.
Note: several devices have smaller max User I/Os count than the I/O bank count would imply. This means that the device is not available in any packaging that actually bonds out the complete set of pads.
UltraScale and UltraScale+.
The UltraScale devices are made of:
The UltraScale+ devices have a few differences:
Zynq UltraScale+ devices are ARM Cortex-A53 based systems on chip sharing a die with an FPGA. The SoC part of the device is called a Processing System (PS). Each model of Zynq UltraScale+ MPSoC is available in up to 3 sub-models: CG, EG, and EV. The main differences among these sub-models are in the CPU and GPU configurations. Zynq UltraScale+ RFSoC devices are available in DR sub-models, which have PS capabilities identical to MPSoC EG sub-models.
Zynq UltraScale+ devices have some additional blocks:
Note: the clock region grid is irregular on some UltraScale+ devices because of a hole in bottom for the Processing System (and possibly the VCU).
Versal.
In 2018, Xilinx announced a product line called Versal. Versal chips will contain CPU, GPU, DSP, and FPGA components. Versal will be fabricated using 7nm process technology. Xilinx has stated that Versal products will be available in the second half of 2019.
The Versal devices are made of: