Phase Locking in Millimeter Wave Frequency Synthesizers-Design overview of Charge Pump Phase Locked Loops

Phase Locked Loops are key blocks which are widely adopted in all area of electronics, especially transceivers in wireless communication systems. The application of Phase Locked Loop varies from generation of local oscillator signal for upconversion and down conversion, generation and distribution of clock signals and jitter reduction. The most extensive use of Phase Locked Loop is for frequency synthesis. The requirements of synthesizer architectures depend on various system requirements and specifications which are based on regulatory standards. The design of Phase Locked Loop components involves the consideration of various techniques to resolve the nonidealities at front end high frequency components as well as back end low frequency components. This paper presents the background and importance of a Phase Locked Loop, various approaches over the years, design choices for each block and practical design methodology for Charge Pump Phase Locked Loops. This paper also presents the system level design of Phase Locked Loop and supply noise interactions among sub modules inside a charge pump Phase Locked Loop. Key–Words: Phase locking, Charge Pump, Voltage Controlled Oscillator, Frequency dividers, Loop filter Received : June 2019, Revised : Nov 2019, Accepted : May 2020


Introduction
Phase locking is an important technique widely employed in majority of analog, digital and RF systems. It is an integral part especially in high speed serial links for clock and data recovery as well as in clock synthesizers. Modern processors and system-on-chips utilize multiple Phase Locked Loops (PLL) to cater their varying demands. Conventional PLLs are implemented using Charge Pump architecture as shown in figure 1.  [1] and [2]. A typical Charge Pump implementation of PLL consists of a phase and frequency detector (PFD), a charge pump (CP), a loop filter (LF), a voltage controlled oscillator (VCO) and divider in feedback to use it for varying applications. This paper presents an overview of operating principles, basic architecture, and selection of circuit blocks and design methods of Charge Pump Phase Locked Loop based on CMOS technology. The paper is organized as follows. Section 2 gives the fundamentals of Phase Locking, s domain representation of charge pump PLL and frequency synthesizer and figures of merit of PLL. Section 3 and 4 describes the front end and back end components of PLL and its design choices. Section 5 gives the practical design methodology and Section 6 presents system level design of PLL. Finally Section 7 and 8 sums up the state-of-the-art performance of PLLs and supply noise interaction in a charge pump PLL and section 9 concludes the paper.

Fundamentals of Phase Locking
PLL is generally characterized in terms of phase and frequency variables. The best analogy to understand PLL is by using a voltage follower as given in figure 2. As the feedback forces Vout to be equal to Vin in a voltage follower, in a PLL feedback forces output and input phases to be equal. Using the phase variables, all the analysis of any feedback systems like stability analysis or noise analysis could be extended to PLLs also [3]- [5].

Narrowband PLL
In Narrow-band PLLs, [11]- [16] VCOs are implemented using resonant characteristics of LC tank circuit. The long-term jitter performance of narrowband PLLs makes them a superior choice over wideband PLLs. At the same time, these types suffer from a very low tuning range which is only 10-20% of the center frequency. These PLLs consume more area for realizing on chip inductors.

PLL as a frequency synthesizer
PLL fundamentally corrects the phase difference between the two periodic input signals and the output of the PLL is always a multiplication of the input reference frequency [17]. The output frequency or synthesized frequency can be expressed as Depending on the N value, synthesizers are classified as an integer synthesizer or a fractional synthesizer [18]- [22].

S domain model of PLL as a frequency synthesizer
Even though PLLs are nonlinear feedback systems, their operation can be approximated by linear analysis using Laplace transforms. All the individual blocks are represented in s domain to get the complete model. The Fig 3 represents the simplified s domain model of synthesizer [23]- [26]. The type and order of PLL is mostly determined by the number of poles located at origin and the number of poles in the system. All VCOs have a pole at origin which makes all PLL atleast type 1. In order to track the phase, another pole is added by a capacitor C 1 at dc. This makes the overall PLL a type 2. But the presence of two poles at origin causes instability. So a resistor R 1 in series with C 1 capacitor is added which introduces a zero and hence stabilizes the loop. The current pulses from charge pump may further produce ripples in the control line of VCO [27]- [31]. The ripples deteriorate the spectral purity and generate spurs. This can be minimized by the addition of another capacitor C 2 , which makes the PLL a type 2, third order synthesizer. Higher order and types of PLL are possible, but seldom used because of loop stability issues. The figure 3 shows the s domain representation of a Type II order 3 system.
The phase frequency detector and charge pump are combined and represented by K P F D . The loop filter used here is of the order two.K V CO , VCO conversion gain represents the tuning or sensitivity of the frequency which is measured in rad/s [32], [33]. The open loop transfer function

Figures of merit of a PLL frequency synthesizer
The design of a PLL is a detailed process which involves multitude of variables. In the preliminary design phase, limiting the number of such variables help in deciding the architecture of each block and adopting the technology node. The three fundamental figures of merit considered in the design of PLL are phase noise, spurs, lock time [34]- [39].

Phase Noise
It is the random deviation of a frequency tone that is spread around the center frequency. Ideally the tone of a PLL is characterized by an impulse, whereas the real one is spread in the frequency domain shown in the figure 4.A transfer function based study will help to estimate the contribution of phase noise of each block to the total phase noise of the PLL. The figure 5 shows the typical phase noise of PLL components.

Spurious Emissions / Spurs
The two fundamental reasons for reference spurs are mismatches of currents in a charge pump and the leakage currents. Banerjee [17] and Maxim [18] proposed two models to predict the spurious emissions. The expression proposed by Banerjee is used to calculate the spurs.

Lock time
Lock time specifies the maximum time that can be used in the commutation of a channel to another. This is defined by IEEE 802.11a standard and must be less than 1 ms. In a frequency synthesizer lock time is determined by a set of parameters identified in the loop.

PLL front end components and design choices
The components of a frequency synthesizer operate at varying range of frequencies.
The prescalars, which are the first stage frequency dividers and voltage controlled oscillators typically operates at high frequency and are together known as front end high frequency components [40]- [43].

Prescalars / Frequency dividers
The first frequency divider (FD) stages in a synthesizer are called as prescalars. They are not treated separately for a low frequency synthesizer, but for a mm wave synthesizer, prescalar needs to operate at the highest frequency of the loop and thus its design is challenging.
The figure 6 shows the basic classification of prescalar for mm wave frequencies. It is categorized as analog, digital and a combination of both known as hybrid. The choice of different topologies depends on various requirements like power consumption, locking range, phase noise and complexity of design. The basic analog frequency divider if first proposed in [44] is a regenerative type where it employs a mixer based on a Gilbert cell. These types of dividers does not self oscillate. Moreover the performances of these dividers are not satisfactory above 60 GHz [45][46][47][48][49][50]. The locking range which is based on eqn 1 is less for these types and power requirement is also more.
The promising analog divider which is widely used is of injection locking type where the oscillators are forced to oscillate from its resonant frequency. By properly choosing the amplitude and frequency of the sinusoid, the circuit will oscillate at the injection frequency; the figure 7 shows the injection locking principle. These dividers can be adopted for high frequency division but at the cost of lock range and design complexity.

Digital frequency dividers
The digital dividers are of two types -static and dynamic. Static dividers are mostly based on edge The maximum operating frequency of a static FD is given by where τ pd is the propagation delay from input to output. [25]- [27] Dynamic dividers are different from static in the use of latches and true single phase clock dividers in the circuit topology. If static is good for better locking range, dynamic is good for its low power consumption.

Travelling Wave frequency dividers
This topology was first proposed in [51] with bipolar technologies and later with CMOS technologies. This topology offers many advantages like differential outputs and less number of transistors leading to less parasitics. The figure 8 shows a travelling wave FD, where it consists of three differential amplifiers. The operation resembles that of a bistable differential amplifier that can switch between master and slave state. The analog nature of the circuit can be identified by studying the current transitions between different branches of the circuit.

Voltage Controlled Oscillator
Voltage Controlled Oscillator (VCO) [52]- [53], [63] is considered as the heart of any synthesizer that operates at the highest frequency. It provides the actual oscillations at the output. The spectral purity of the synthesizer depends on VCO and its ability to reject common mode noise. The lock range of the PLL is determined by the tuning range of VCO. Figure 9 shows the classification of VCOs [54].
Ring oscillator is a popular resonator less VCO, where it uses cascade stages of inverters. The tuning of these kinds of oscillators is done by varying the transconductance of the delay stages. Typically a tuning range of more than 30% is possible with these types. But tuning can be achieved at the cost of spectral purity and phase noise performance. The ring oscillators reported are limited to a maximum of 15 GHz in bulk CMOS processes and therefore not a choice for mm wave frequency synthesizers [55].
Another category is resonator based VCO [54], where a tank circuit is employed. The main advantages of using a resonator based VCO is it can work close to the maximum frequency f max of a given technology [56]. The frequency of oscillation is determined by where L and C are the inductance and capacitance. The design of oscillator with low phase noise can be done using the Leeson's phase noise model as shown in figure 10 [57] - [59]. This model shows the variation of phase noise based on the frequency offset, center frequency and the Q factor of the LC tank.  The circuit in figure 11 shows a CMOS based VCO. The oscillation frequency is varied by the tuning mechanism and is usually accomplished by the capacitors.
The voltage swing in the CMOS cross-coupled oscillator is twice the voltage swing in the NMOS cross-coupled oscillator. From (1), the phase noise decreases as the voltage swing increases. In order to have lower phase noise, CMOS topology is better than NMOS type.

PLL Back end Components & design choices
Compared to front end components, PLL back end components including Phase Frequency Detector, Charge pump and feedback divider chain operates at lower frequencies.
This section presents an overview and design choices for back end circuits.

Feedback divider
Feedback divider generates an output which is very close to synthesizer reference frequency. The input for the divider chain comes from the prescalar. In most of the cases the prescalar frequencies will be in the range of GHz and feedback dividers need to divide those frequencies into MHz range to get close to reference frequency.
A dual modulus divider is a widely used circuit to change the division ratio in a frequency synthesizer. These circuits are used when area is a concern and are commonly implemented in MOS Current Mode Logic MCML or Source Coupled Logic (SCL). The different approaches in the design of CML dividers relate the gate delay to the power consumption, with the constraint of a given output swing and voltage gain of the differential pairs, in order to satisfy the requirement on the noise margin. Phase noise is an impor-tant criterion in the design of dividers, as there is a tight compromise between low phase noise and high frequency of operation. A popular CML based topology is shown in figure 12.

Phase Frequency Detector, Charge Pump and Loop filter
The components PFD, CP and loop filter forms the rest of the PLL back end whose combined task is to provide a stable dc tuning voltage to the VCO so that synthesizer can move towards lock state. PFD is a circuit which detects both the phase and frequency between two signals and generates an output in proportion to them. The simple and widely used implementation is with two edge triggered D flip flops. PFD implementation has a potential problem known as dead zone problem when the phase error is very small which leads to incorrect operation of subsequent stages or even zero loop gain. This dead zone prevents the synthesizer to work until the phase error reaches a certain minimum value. Many PFD implementations are reported [59][60][61] aimed at robust designs in improving the various characteristics of PFD like operating frequency, dead zone, complexity, and symmetry. The next component in the line is the charge pump which converts the output signal of PFD into a charge and thereby responsible for moving control voltage of VCO up or down by pumping current in or out of the loop filter as shown in figure 14. The increase in V ctrl is given by The average charge dumped per cycle is given by The transfer function of the PFD and the charge pump is given by P D(s) = K P D = I CP 2π (12)

Practical considerations for the design of charge pump
The design of charge pump is done in such way that reduces mismatches between up and down currents and thereby nullifies charge deposition at the loop filter. Fluctuations or variations in the filter voltage due to current mismatch in the charge pump result in reference spurs or discrete spurs in the output spectrum of the frequency synthesizer, called as reference feedthrough. In addition, to maintain a constant loop-bandwidth, the magnitude of the charge pump output currents must be independent of the output voltage. Authors in [5] proposed a charge pump for low-voltage PLLs that combines a replica biasing technique and a feedback structure. Current matching is improved over a wide output voltage range. Apart from the mismatches, output impedance of the charge pump is also considered invariably.
The loop filter, the last circuit in the back end, suppresses the high frequency components at the charge pump output. The overall loop dynamics and stability depends on loop filter. . It consists of a resistor in series with a capacitor C 1 both of which are in parallel with another capacitor C 2 . The capacitor C 1 introduces a pole which is balanced by the resistor introducing a zero so that it is stable in the given frequency range. The addition of C 2 is to suppress the ripples in the control voltage, V ctrl . This may lead to the system becoming unstable. Hence, the capacitor and resistor values are chosen such that they ensure optimum stability and maximum high frequency noise component rejection. The transfer function of the loop filter is given by The

Practical Design Methodology
The most crucial part in the design of a frequency synthesizer is the determination of practical and realizable specifications for the back end and front end circuits. This section proposes a practical design methodology to determine the initial requirements for the various specifications that need to be considered for the design. Table 1 shows specifications to be targeted in the design of a mm wave frequency synthesizer.

Identifying Initial requirements of a synthesizer
The first step in the design of a synthesizer is to develop the initial requirements. A sample initial requirement for a mm wave synthesizer is as shown in Table 2.

Architectural selection
With the initial requirements, architecture selection can be done for both front end and back end circuits. Depending on the target specifications architectures can be selected and simulated in block level and later.

Synthesizer integration
The overall circuits can be simulated in any of the available CAD tools. Transistor level simulation of complete synthesizer is a tedious process. Due to the large simulation time, front end and back end circuits are simulated separately before integration. The figure 16 shows practical methodology for the design of synthesizer. It is a good practice to start with the system level simulation before implementing individual blocks in circuit level.
6 System level design of PLL This section discusses the system level design of PLL using the CPPSim toolkit. The CPPSim package includes two tools namely, PLL Design Assistant and Sue2. Initially the designing is done using PLL Design Assistant which considers the ideal conditions. Further, Sue2 is used to complete the system level design by including the non-idealities like charge pump mismatch and non-zero phase error. A black box approach in order to understand the operation of PLL is performed using the PLL Design Assistant tool by CPPSim software. The PLL design assistant tool provides a graphical user interface to design PLL at the transfer function level. This section presents the analysis of results obtained using design assistant tool. With the PLL design assistant, noise performance of the PLL under different configurations was examined and we decided on the system parameters needed to meet the GSM phase noise specifications and also to meet the settling time requirements. Also, the impact of parameter variations was analyzed along with its effects on phase noise and settling time. Fig 17 to Fig 19 shows the results of phase noise under various conditions and closed loop step response and stability analysis of a PLL designed with PLL design assistant tools.

State-of-the-art in CMOS PLL
This section compares different CMOS frequency synthesizers implemented so far in diverse technology processes. An overview of recent state-ofthe-art synthesizers representing their technology node and fundamentals figures of merit is given in Table 3. The frequency is expressed in Giga Hertz, technology node in nm, phase noise measured at 1 MHz offset in dBc per Hz and power in milli watts.

Conclusion
Phase locking as described in this paper is one of the inevitable approaches for frequency synthesis. This paper presented the background and importance of a Phase Locked Loop, various approaches over the years, system level design approaches, practical design methodology, architectures for Charge Pump PLLs. The system level design of a Charge Pump Phase locked loop was presented with PLL design assistant tool and supply noise interactions among sub modules inside a charge pump PLL are also discussed.