Generating Complete and Finite Test Suite for ioco: Is It Possible?

Testing from Input/Output Transition Systems has been intensely investigated. The conformance between the implementation and the specification is often determined by the so-called ioco-relation. However, generating tests for ioco is usually hindered by the problem of conflicts between inputs and outputs. Moreover, the generation is mainly based on nondeterministic methods, which may deliver complete test suites but require an unbounded number of executions. In this paper, we investigate whether it is possible to construct a finite test suite which is complete in a predefined fault domain for the classical ioco relation even in the presence of input/output conflicts. We demonstrate that it is possible under certain assumptions about the specification and implementation, by proposing a method for complete test generation, based on a traditional method developed for FSM.


Introduction
Testing from Input/Output Transition System (IOTS) has received great attention from academy and industry alike. The main research goal is to devise a theoretically sound testing framework when the behavior of an Implementation Under Test (IUT) is specified as the IOTS model. It is assumed that the tester controls when inputs are applied, while the IUT autonomously controls when, and if, outputs are produced. The IUT's autonomy causes issues in testing. Simply stated, the interaction between the IUT and the tester should be assumed to be asynchronous, since otherwise the tester should have the ability to block the IUT when the latter is ready to produce output but the former has input to be sent. Most approaches based on the so-called ioco conformance relation do not offer sound solutions to the problem of conflicts between inputs and outputs. In particular, the proposal [15] for input-enabled testers addressing the conflicts lead to uncontrollable tests, while it is widely agreed that only controllable tests, which avoid any choice between inputs or between input and output, should be used. The approaches for test purpose driven test generation from the IOTS implemented in tools such as TGV [8] and TorX [16], as well as in Uppaal Tron which also accepts the IOTS, face the same problem of treating input/output conflicts.
These issues have drawn significant attention of the testing community, e.g., [1,6,7,11], and have been dealt with by allowing implicitly or explicitly the presence of channels, e.g., FIFO queues, between the IUT and tester [6,7,17]. However, queues impose a hard burden on the tester, since the communication is now distorted by possible delay in the transmission of messages via queues. In the extreme case, queues render some important testing problems undecidable [4,5]. The issue is caused by the conflict between input and output enabled in the same state; while the IUT should be ready to receive input, it may choose to produce an output, blocking or ignoring incoming input. It has been shown that when all the states have either inputs or outputs, but not both, in the so-called Mealy IOTS, such problems do not arise [12].
Apart for the problem of input/output conflicts, the question of generating complete and finite test suite from IOTS w.r.t. the ioco relation remains open. The test generation method which is most referred in the literature relies on non-deterministic choice between: (1) stopping testing; (2) applying a randomly chosen input; or (3) checking for outputs [14]. The problem with this approach is that, although completeness is guaranteed in some theoretical sense, the practical application of this method is problematic. It requires that the process be repeated an undetermined number of times, since there is no indication of when the completeness has been achieved and thus the process can stop.
On the other hand, generation methods from Finite State Machines (FSM) approach the problem of test completeness by explicitly stating a set of faulty (mutant) FSMs, called a fault domain, which model potential faults of the IUT; then, a test suite is generated that targets each faulty FSM. Its completeness implies that each IUT possessing the modelled faults will be detected by the test suite. The existing methods for complete test generation are applicable not only to minimal deterministic machines, as the early methods [2,3,18], but also to nondeterministic FSMs [10]. This motivated a previous attempt to rephrase FSM methods for checking experiments to the IOTS model [13]. In particular, an analogue of the Harmonized State Identifier Method (HSI-method) was elaborated there for the trace equivalence relation between the specification and implementation IOTSs. The input/output conflicts were addressed by assuming that the tester detecting (using some means) them will just try to repeatedly re-execute the expected trace to verify if it can be generated by the IUT.
In this paper, we investigate whether it is possible to construct a finite test suite for a given IOTS specification which is complete in a predefined fault domain for the classical ioco relation even in the presence of input/output conflicts. Our solution to the latter is based on the assumption that any IUT in a fault domain resolves each such conflict in favor of inputs; that is, we assume that the IUT is eager to process inputs and, whenever it is in a state where it can either receive an input or produce an output, it will produce an output only if no input is available. We demonstrate this by elaborating a test generation method inspired by the HSI method [19], generalizing and adapting its concepts to the realm of IOTS. We illustrate the method with a running example. This remainder of this paper is organized as follows. In Section 2, we introduce the main concepts of IOTS and test cases. In Section 3, we present the generation method, and demonstrate that the obtained test suite is a complete for a given fault domain. Finally, in Section 4, we conclude the paper and point to future work.
2 Input/output transition system and test cases 2.1 Input/output transition system and related definitions We use input/output transition systems (IOTS, a.k.a. input/output automata [9]) for modelling systems. Formally, an IOTS S is a quintuple (S, s 0 , I, O, h S ), where S is a finite set of states and s 0 ∈ S, is the initial state, I and O are disjoint sets of input and output actions, respectively, and h S ⊆ S × (I ∪ O) × S is the transition relation. S is deterministic if h S is a function on a subset of S × (I ∪ O), i.e., if (s, x, s ) ∈ h S and (s, x, s ) ∈ h S , then s = s . While we shall consider only deterministic IOTSs, they may have outputnondeterminism, i.e., have several outputs enabled in a state.
For IOTS S, let init S (s) denote the set of actions enabled at state s, i.e., init S (s) = {x ∈ I ∪ O | ∃s ∈ S, (s, x, s ) ∈ h S }; let inp S (s) and out S (s) denote the set of inputs and outputs, respectively, enabled at state s. Thus, inp S (s) = init S (s) ∩ I; out S (s) = init S (s) ∩ O. We omit the subscript if it is clear which IOTS is considered. A state s is a sink state if init(s) = / 0; s is an input state if inp(s) = / 0. We denote the set of input states by S in . An input state s is stable (quiescent) if init(s) ⊆ I. An input state s is a quasi-stable state if out(s) = / 0. In a quasi-stable state, there is an input/output conflict (note that the IOTS itself does not provide any mechanism for resolving such conflicts). A state is an output state if it is neither sink nor input state. Figure 1 shows an example of an IOTS, where I = {a, b} and O = {0, 1}. Input states are numbered; states 1 and 4 are stable, whereas states 2 and 3 are quasi-stable.
For IOTS S, a path from state s 1 to state s n+1 is a sequence of transitions p = (s 1 , a 1 , s 2 )(s 2 , a 2 , s 3 ) . . . (s n , a n , s n+1 ), where (s i , a i , s i+1 ) ∈ h S for i = 1, . . . , n. Let ε denote the empty sequence of actions. We say that s n+1 is reachable from s 1 . IOTS S is initially-connected if each state is reachable from the initial state. A sequence u ∈ (I ∪ O) * is called a trace of S from state s 1 ∈ S if there exists path (s 1 , a 1 , s 2 )(s 2 , a 2 , s 3 ) . . . (s n , a n , s n+1 ), such that u = a 1 . . . a n . We use the usual operator after to denote the state reached after the sequence of actions (we consider only deterministic IOTS), i.e., s 1 -after-u = s n+1 ; if u is not a trace of s 1 , then s 1 -after-u = / 0. Let also Tr(T ) denote the set of traces from states in T ⊆ S. For simplicity, we denote Tr({s}) as Tr(s) and use Tr(S) to denote Tr(s 0 ). A trace u of IOTS S is completed, if s 0 -after-u is a sink state. A trace u of IOTS S is a bridge trace from input state s, if s-after-u ∈ S in and for each proper prefix w of u, s-after-w / ∈ S in . Given an IOTS S = (S, s 0 , I, O, h S ) and a state s ∈ S, let S/s denote the IOTS that differs from S in the initial state changed to s, removing states and transitions which are unreachable from s.
We use a designated symbol δ to indicate quiescence in S, that is, the absence of outputs. Quiescence can be encoded by adding self-looping δ transitions to the stable states; the resulting IOTS has the output action set O ∪ {δ }. Traces of this IOTS which end with δ are quiescent traces and traces containing δ are suspension traces. In the rest of the paper, we assume that Tr(S) includes all kinds of traces.
An IOTS T = (T,t 0 , I, O, h T ) is a submachine of the IOTS S = (S, s 0 , I, O, h S ), if T ⊆ S and h T ⊆ h S . A state s ∈ T of a submachine T of S is output-preserving if for each x ∈ O such that (s, x, s ) ∈ h S , we have that (s, x, s ) ∈ h T . The submachine T of S is output-preserving if each state which is not a sink state is output-preserving. The submachine is trivial if T is a singleton and h T = / 0. The IOTS S is progressive if it has no sink state and each cycle contains a transition labeled with input, i.e., there is no output divergence. The IOTS S is input-complete if all inputs are enabled in input states, i.e., inp(s) = / 0 implies that inp(s) = I, for each state s. The IOTS S is single-input if |inp(s)| = 1, for each input state s; it is output-complete if out(s) = O, for each output state s.
In this paper, we assume that specifications and implementations are input-complete progressive deterministic initially-connected IOTS; we let IOT S(I, O) denote the set of such IOTSs with input set I and output set O.
To characterize the common behavior of two IOTSs in IOT S(I, O) we use the intersection operation. The intersection S ∩ P of IOTSs S = (S, s 0 , I, O, h S ) and P = (P, p 0 , I, O, h P ) is an IOTS (Q, q 0 , I, O, h S∩P ) with the state set Q ⊆ S × P, the initial state q 0 = (s 0 , p 0 ), and the transition relation h S∩P , such that Q is the smallest state set obtained by using the rule ((s, p), x, (s , p )) ∈ h S∩P ⇐⇒ (s, x, s ) ∈ h S and (p, x, p ) ∈ h P . The intersection S ∩ P preserves only common traces of both machines; in other words, for each state (s, p) of S ∩ P we have Tr((s, p)) = Tr(s) ∩ Tr(p); moreover, out((s, p)) = out(s) ∩ out(p). Thus, Tr(S ∩ P) = Tr(S) ∩ Tr(P).
Given two IOTSs S and T, such that S has at least one sink state s ∈ S, the IOTS obtained by merging the initial state of T with a sink state s is called the chaining of S and T in the sink state s, denoted S@ s T.
For conformance testing, we consider a usual ioco relation.
Definition 1 Given two IOTSs P, S ∈ IOT S(I, O), S = (S, s 0 , I, O, h S ) and P = (P, p 0 , I, O, h P ), we write P ioco S if for each trace α ∈ Tr(S), we have that out(P-after-α) ⊆ out(S-after-α). If P ioco S then we say that state p 0 is a reduction of state s 0 . The reduction relation between states is also defined for states of the same IOTS S ∈ IOT S(I, O), namely, s 1 is a reduction of s 2 , if S/s 1 ioco S/s 2 .
We write P¨ïoco S, if not P ioco S. We notice that if the specification IOTS S contains some state that is a reduction of another state then there exist an implementation P ∈ IOT S(I, O) and state p ∈ P, that is a reduction of both states of S. Intuitively, the two states are "merged" into a single state in the implementation. As a result, a conforming implementation may have fewer states than its specification. This observation motivates the following definitions and statements.
Definition 2 Two states of S ∈ IOT S(I, O) are compatible, if there exists a state of an IOTS P ∈ IOT S(I, O) that is a reduction of both states; otherwise, i.e., if for any P ∈ IOT S(I, O), no state of P is a reduction of both states, they are distinguishable.
According to this definition, compatible states can be "merged" in an implementation IOTS into a single state and it can still be a reduction of the specification IOTS, however, any reduction of the specification IOTS cannot have a state that is a reduction of distinguishable states.
The compatibility of states can be easily determined by the intersection of IOTSs, a simple and inexpensive operation. By definition, if two states of a given IOTS are compatible, there exists a state of some input-complete, progressive IOTS which is a reduction of both states. Such a state is the initial state of the intersection of two instances of a given machine initialized in different states, since the intersection represents all the common traces of the two states. On the other hand, if the two states are distinguishable, the intersection is not a progressive IOTS. This fact is stated in the following lemma. Proof. Suppose that s 1 and s 2 are compatible. We show that S/s 1 ∩ S/s 2 ∈ IOT S(I, O), that is, S/s 1 ∩ S/s 2 is input-complete, progressive, deterministic and initially-connected. Let α ∈ Tr(S/s 1 ∩ S/s 2 ). Thus, α ∈ Tr(S/s 1 ) ∩ Tr(S/s 2 ). We have that s 1 = S/s 1 -after-α and s 2 = S/s 2 -after-α are also compatible. Hence, by Definition 1, there exists a state p of P ∈ IOT S(I, O), with P = (P, p 0 , I, O, h P ) that is a reduction of s 1 and s 2 . It holds that out(p) ⊆ out(s 1 ) and out(p) ⊆ out(s 2 ). As P is progressive, we have that init(p) = / 0, and thus there exists x ∈ out(p); hence, x ∈ init(s 2 ) ∩ init(s 2 ). It follows that (S/s 1 ∩ S/s 2 )-after-α is not a sink state, since it is followed by x, at least. Thus, S/s 1 ∩ S/s 2 has no sink state. If x is an input, then I ⊆ init(s 1 ) and I ⊆ init(s 2 ), since S is input-complete. Therefore, I ⊆ init((S/s 1 ∩ S/s 2 )-after-α), and S/s 1 ∩ S/s 2 is input-complete. As S is progressive, it does not have cycles with transitions labeled only with outputs. Hence, neither S/s 1 ∩ S/s 2 has such cycles, i.e., S/s 1 ∩ S/s 2 is also progressive. As S is deterministic and initially-connected, so are S/s 1 , S/s 2 and, consequently, S/s 1 ∩ S/s 2 . It follows then that S/s 1 ∩ S/s 2 ∈ IOT S(I, O).

Test definitions and problem statement
To simplify the discussion, we refer to inputs and outputs always taking the view of the implementation, IUT; thus, we say, for instance, that the tester sends an input to the IUT and receives outputs from it, and define test cases accordingly preserving the input and output sets of the specification IOTS S = (S, s 0 , I, O, h S ). Recall that δ is included into O; in particular, the output δ of a test case is interpreted as the fact that the tester executing the test case detects quiescence of the IUT.
Definition 3 A test case over input set I and output set O is an acyclic single-input output-complete  The problem of complete test suite generation for a given IOTS was addressed in [14,15]. To generate such a test suite a simple algorithm is suggested, which, however, should be executed an indeterminate number of times to achieve the test completeness w.r.t. the ioco relation. In the first work [14], only controllable test cases are generated; the problem with that solution is that the tester must be able to somehow preempt any output each time a test case prescribes sending some input to the IUT. In the second work [15], "the most important technical change with respect to [14] is the input enabledness of test cases, which was inspired by [11]". In terms of our definitions, test cases are uncontrollable; they contain quasi-stable states, where both inputs and outputs are enabled. The intention behind this is to address input/output conflict present in the specification IOTS, since the specification itself provides no clue how an implementation resolves input/output conflict. The behavior of the tester executing uncontrollable test cases may become nondeterministic (the tester has to execute one of the two mutually exclusive actions) and the test results may not always be reproducible. The approaches to generation of controllable tests that tolerate input/output conflicts based on the use of queues are elaborated in several work [4,6,7,11,12,17]. The problem is that one needs to know the size of queues to obtain a finite complete test suite.
In this paper, we demonstrate, first, that controllable tests that tolerate input/output conflicts can be constructed without knowing the size of queues, and second, that it is possible to obtain in a systematic way a finite set of controllable test cases which is a complete test suite in a finite set of IOTSs. The key assumption we make about the implementation IOTSs in the fault domain is that each implementation when it is a quasi-stable state with the input/output conflict, it does not produce any output if its input queue contains an input. We call such implementations input-eager. A subset of IOT S(I, O) that contains input-eager IOTSs is denoted IEIOT S(I, O). Finiteness of complete test suites results from further constraining this set by the number of its input states, as we demonstrate later.
Testing any input-eager IOTS allows one to use two controllable test cases dealing with input/output conflict; in a quasi-stable state one test case does not send any input and only observes output sequence concluded by quiescence and another one just sends input. In the latter case, the tester does not need to preempt IUT outputs, as an input-eager IOTS will not produce them since the input queue is not empty and contains the input from the tester.

Generating complete test suites for IOTS
In this section, we investigate whether a classical method for constructing a complete test suite for the FSM model can be reworked to achieve the same result for the IOTS model even with input/output conflicts, namely a test suite with controllable test cases complete in a finite fault domain, without transforming IOTS into Mealy machine. To demonstrate that it is in fact possible, we develop here a counter-part of the HSI-method [19] for the simplest case, when the FSM is completely specified, minimal, and the fault domain contains FSMs with the number of states not exceeding that of the specification machine.
The HSI-method for FSMs uses sets of distinguishing input sequences, so-called harmonized state identifiers, one per state, such that any two identifiers share an input sequence which distinguishes the two states. These input sequences are appended to state and transition covers in order to check that every state of the implementation corresponds to some state of the specification and every transition of the implementation corresponds to a transition of the specification.
Accordingly, we need first to define state and transition covers, as well as harmonized state identifiers for a given IOTS.

State and transition covers for IOTS
We first turn our attention to the notion of state cover, needed in tests to eventually establish a mapping from states of the specification to states of the IUT. We focus only on input states of the specification IOTS. First, to check the IUTs reaction to some input it is in fact sufficient to apply the input to a given input state, observe an output sequence, and if it is correct then check whether a proper input state is reached. Output state identification can thus be avoided. However, even considering only input states, some input state of the specification may not be mapped to any state of the IUT even if the latter is a reduction of the specification. Therefore, we should define a state cover targeting only those input states of the specification which have a corresponding state in any ioco-conforming implementation.
Definition 5 Given an initially connected IOTS S and an input state s, s is certainly reachable (creachable), if any P ∈ IOT S(I, O), such that P ioco S, contains an input state that is a reduction of s.
It turns out that the certainly reachable states can be determined by considering a submachine of S, similarly to the FSM case [10].
Lemma 3 An input state s of an IOTS S is c-reachable if S contains a single-input acyclic outputpreserving submachine of S which has s as the only sink state.
Proof. Let C s be a single-input acyclic output-preserving submachine of S, which has s as the sink state. The input state s is the only sink state in the submachine; hence all its completed traces converge in s. The submachine is output-preserving, this means that for each α ∈ Tr(C s ), if C s -after-α = s then out(C s -after-α) = out(S-after-α). Hence for any IOTS P ∈ IOT S(I, O), such that P ioco S, it also holds that out(P-after-α) ⊆ out(S-after-α), thus out(P-after-α) ⊆ out(C s -after-α). This implies that P should have at least one of the completed traces of C s ; let β be such a completed trace. It is easy to see that P ioco S implies that for any γ ∈ Tr(P), P-after-γ is a reduction of S-after-γ. Hence in any IOTS P ∈ IOT S(I, O), such that P ioco S, the state P-after-β is a reduction of S-after-β . The result follows, since β is a completed trace of C s and, thus, S-after-β = s.

Definition 6
Given a c-reachable input state s of an IOTS S, a single-input acyclic output-preserving submachine C s , which has s as the only sink state, is a preamble for state s.
Preambles for states can be determined by Algorithm 1, adapted from [10].
Algorithm 1 for constructing a preamble for a given input state. Input: An IOTS S and input state s ∈ S. Output: a preamble if the state s is c-reachable. Construct an IOTS R = (R, r 0 , I, O, h R ) as follows R := {s}; h R := / 0; While s 0 / ∈ R and there exist an input state s / ∈ R and nonempty A ⊆ I, such that for each x ∈ A, (s , x, s ) ∈ h S , and for each trace γ ∈ Tr(s ), where γ ∈ O * , there exists a prefix γ such that s -after-γ ∈ R.
End While; If s 0 / ∈ R then return the message "the state s is not c-reachable" and stop; Else let R = (R, r 0 , I, O, h R ), where r 0 := s 0 , be the obtained IOTS; Starting from the initial state, remove in each state all input transitions, but one, to obtain a singleinput submachine with the only sink state s; Delete states which are unreachable from the initial state; Return the obtained machine as a preamble for the state s and stop.
A preamble can be used to transfer from the initial state to c-reachable input states. For the initial state itself, the preamble is simply the trivial IOTS, which contains only the initial state. Figures 2.a, 2.b  and 3 show the preambles for states 2, 3 and 4, respectively, of the IOTS in Figure 1.
We assume that each input state of the specification IOTS S is c-reachable and the initial state is a stable state. An input state cover Z of S is a set of preambles, one for each input state, i.e., Z = {C s | s ∈ S in }.
In FSM-based testing, a state cover is extended to a transition cover, by adding all inputs to each transfer sequence of the state cover. In an IOTS, an input applied in an input state may be followed by a number of output sequences leading to various stable states, creating quiescent traces of IOTS. The set of all possible quiescent traces created by x ∈ I in input state s ∈ S in is {xγδ ∈ Tr(s) | γ ∈ O * }. We use Cov(s, x), called (s, x)-cover, to refer to an IOTS, such that Tr(Cov(s, x)) = {xγδ ∈ Tr(s) | γ ∈ O * } and the set of sink states is {s-after-xγ | γ ∈ O * }. For instance, Cov(2, a) for state 2 and input a of  the IOTS in Figure 1 has the trace a01δ , whereas Cov(1, a) has the traces a01δ , a111δ and a101δ . A transition cover V of S is the set of preambles of an input state cover chained with (s, x)-covers, i.e., V = {C s @ s Cov(s, x) | s ∈ S in , x ∈ I}. Notice that each bridge trace starting from a quasi-stable state s ∈ S in is covered by Cov(s , x), for some input state s and input x. More generally, we state the following lemma.
Lemma 4 Given an IOTS S ∈ IOT S(I, O) and a bridge trace β from an input state s ∈ S in , there exist input state s ∈ S in and input x, such that γβ γ δ ∈ Tr (Cov(s , x)), for some traces γ ∈ Tr(s ) and γ ∈ Tr(s -after-γβ ).
Proof. If β starts with an input, then the results follows directly, since with γ as the empty sequence β γ d is a quiescent trace starting at state s. If β starts with an output, then, β ∈ O * and s is a quasi-stable state. Notice that there exists γ ∈ O * , such that β γ δ ∈ Tr(s), since S is progressive. Moreover, there exist an input state s , a trace γ starting with x and followed by outputs, such that s -after-γ = s. Thus, γβ γ δ ∈ Tr (Cov(s , x)).
The IOTS, obtained by removing from R(s 1 , s 2 ) the sink state ⊥ s 2 and all transitions leading to it, is called a distinguisher of s 1 from s 2 and is denoted by W(s 1 , s 2 ).
Separator R(s 1 , s 2 ) can be obtained from the intersection S/s 1 ∩ S/s 2 = (Q, (s 1 , s 2 ), I, O, h S /s 1 ∩ S/s 2 ), similar to the case of FSM [10], as follows (Algorithm 2). First we determine the intersection S/s 1 ∩ S/s 2 and identify the states where the two IOTSs S/s 1 and S/s 2 disagree on outputs. For each such state, we add transitions leading to sink states ⊥ s 1 and ⊥ s 2 . In the final step, we determine a separator as a single-input output-preserving acyclic submachine of the obtained IOTS by removing inputs, as in Algorithm 1.
Algorithm 2 for constructing a separator for two input states. Input: An IOTS S and distinguishable input states s 1 , s 2 ∈ S in . Output: a separator R(s 1 , s 2 ). Construct the IOTS S/s 1 ∩ S/s 2 = (Q, (s 1 , Starting from the initial state, remove in each state all input transitions, but one, to obtain a singleinput submachine with the only sink states ⊥ s 1 and ⊥ s 2 ; Delete states which are unreachable from the initial state; Return the obtained machine as a separator for the states s 1 and s 2 , and stop. Notice that a separator of states s 1 and s 2 is obviously a separator of s 2 and s 1 , i.e., R(s 1 , s 2 ) = R(s 2 , s 1 ), whereas a distinguisher of s 1 from s 2 is different from a distinguisher of s 2 from s 1 , i.e., W(s 1 , s 2 ) = W(s 2 , s 1 ). Figure 4 shows a separator R(1, 4) obtained by Algorithm 2, as well as the corresponding distinguishers W(1, 4) and W(4, 1).
We consider only input-state-minimal specification IOTS, so we are interested in distinguishers of only input states. If s 1 is a stable state and s 2 is a quasi-stable state then the separator R(s 1 , s 2 ) is simple; it has a transition with δ leading from the state (s 1 , s 2 ) to state s 1 and a transition for each o ∈ out(s 2 ), leading to s 2 . Thus, a distinguisher of each stable state from any quasi-stable state has a single δtransition, we call it a quiescence distinguisher of a stable state s, denoted W δ (s). It should be included into a stable state identifier of the state s.
Definition 8 A state identifier of input state s, denoted ID(s), is a set of distinguishers W(s, s ) for each input state s distinguishable from s, including W δ (s) if state s is stable. A set of input state identifiers {ID(s) | s ∈ S in }, is harmonized, if for each pair of input states s 1 and s 2 , such that both are either stable or quasi-stable states, there exists a separator R(s 1 , s 2 ), such that W(s 1 , s 2 ) ∈ ID(s 1 ) and W(s 2 , s 1 ) ∈ ID(s 2 ).
For the IOTS in Figure 1, we have that ID(1) includes W δ (1) as well as W (1,4) in Figure 4.   Figure 5 shows the example of a test case, obtained by chaining the preamble C 2 , Cov(2, a) with the quiescent trace a01δ , and distinguisher W (1,4). Notice that the quiescence distinguisher W δ (4) of a stable state 4 is also used to identify this state, since the quiescent trace a01δ has it as a suffix. The f ail state is replicated to reduce the clutter.

Complete test suite
Completing each IOTS in the set D, we finally obtain a test suite T S = {TC(U) | U ∈ D}. Consider now the subset of IEIOT S(I, O) restricted by the number of input states less or equal to that of the specification IOTS S; we denote it by IEIOT S(I, O, k), where k is the number of input states in S. We state the main result of the paper. Before proving Theorem 1, we state some auxiliary results.
Lemma 5 Given two IOTSs P, S ∈ IOT S(I, O), if P is an initially connected submachine of S with the same initial state s 0 , then P ioco S.
Proof. Let α be a trace of S. We show that out(P-after-α) ⊆ out(S-after-α). Let s = S-after-a. If s / ∈ P, where P is the set of states of P, then out(P-after-α) = / 0, and the result follows. If s ∈ P, we have that out P (s) ⊆ out S (s). As s = P-after-α, the result also follows. Thus, P ioco S. Definition 9 Given two IOTSs P, S ∈ IOT S(I, O), P = (P, p 0 , I, O, h P ) and S = (S, s 0 , I, O, h S ), P is inputstate homeomorphic to S, if there exists a bijective map ϕ from P in to S in such that for every state p ∈ P in , each bridge trace γ ∈ Tr(p), it holds that ϕ(p)-after-γ = ϕ(p-after-γ).
P and S are input-state isomorphic, if P is input-state homeomorphic to S and S is input-state homeomorphic to P.
Notice that for output-deterministic IOTSs, input-state isomorphic IOTSs are also input-state homeomorphic. An output-nondeterministic IOTS S that is input-state homeomorphic to P differs from P in state names, as well as in the set of bridge traces in some states, since it may have fewer bridge traces, while input-state isomorphic IOTSs differ just in state names.
Corollary 2 Given two IOTSs P, S ∈ IOT S(I, O), if P is input-state homeomorphic to S, then P is inputstate isomorphic to an initially connected submachine of S with k input states and the same initial state. Proof. Let N ∈ IEIOT S(I, O, k), such that N passes T S. T S contains test cases where preambles of an input state cover are chained with harmonized identifiers to the respective states. Thus, for input states s and s , T S contains the test cases TC(C s @ s W(s, s )) and TC(C s @ s W(s , s)). Let α be a completed trace of C s and α be a completed trace of C s , such that α, α ∈ Tr(N). As N passes T S, no f ail state is reached when the distinguishers W(s, s ) and W(s , s) are applied after α and α , respectively. Since no state can reach sink state in both distinguishers (see Definition 7), we have that the states N-after-α and N-after-α are different, i.e., N-after-α = N-after-α . These are input states, thus, for each pair of input states of S there exist a pair of distinct states in N; consequently, N has at least k input states. As N ∈ IEIOT S(I, O, k), N has exactly k input states.
Let T ∈ (Z ∪ V ), t ∈ sink(T), α ∈ Tr(T) ∩ Tr(N), such that T-after-α = t, N-after-α ∈ N in . Similarly, let T ∈ (Z ∪ V ), t ∈ sink(T ), α ∈ Tr(T ) ∩ Tr(N), such that T -after-α = t . Notice that α and α are completed traces of IOTSs in the state or transition cover, which are also traces of N. We prove that S-after-α = S-after-α if and only if N-after-α = N-after-α. Let s = S-after-α and s = S-after-α . Suppose first that S-after-α = S-after-α. Thus, TS contains TC(T@ s W(s, s )) and TC(C s @ s W(s , s)), and as N passes T S, no f ail state is reached when the distinguishers W(s, s ) and W(s , s) are applied after α and α , respectively. Since no state can reach sink state in both distinguishers, we have that N-after-α = N-after-α . Suppose now that S-after-α = S-after-α. We prove by contradiction that N-after-α = N-after-α. Assume that N-after-α = N-after-α. Thus, let s be an input state, different from s = S-after-α. Let β ∈ Tr(C s ), such that β ∈ Tr(N). As T S contains TC(T@ s W(s, s )) and TC(C s @ s W(s , s)) and N passes T S, we have that N-after-α = N-after-β . Analogously, we can show that we have that N-after-α = N-after-β . Thus, N-after-α is distinct from k − 1 distinct input states of N and N-after-α is also distinct from k − 1 distinct input states of N. As N-after-α = N-after-α, N has k + 1 states, which contradicts the fact that N ∈ IEIOT S(I, O, k) and has at most k input states. Therefore, N-after-α = N-after-α. Thus, let ϕ be a bijection from the input states N in of N to the input states S in of S, such that for each completed trace χ of an IOTS in the state cover Z or transition cover V , which is also a trace of N, we have that ϕ(N-after-χ) = S-after-χ. Let p be an input state of N. There exists a completed trace α of an IOTS in the input state cover Z, such that α is also a trace of N and N-after-α = p. Thus, it holds that ϕ(N-after-α) = ϕ(p) = S-after-α. Let γ ∈ Tr(p) be a bridge trace, such that αγ is a completed trace of an IOTS in the transition cover V . Thus, it follows that ϕ(p)-after-γ = ϕ(N-after-α)-after-γ = (S-after-α)-after-γ = S-after-αγ = ϕ(N-after-αγ) = ϕ((N-after-α)-after-γ) = ϕ(p-after-γ), i.e., ϕ(p)-after-γ = ϕ(p-after-γ). Therefore, we have that N is input-state homeomorphic to S.
We can now prove Theorem 1.
Proof of Theorem 1. We first prove that T S is sound for S in IEIOT S(I, O, k). Let N ∈ IEIOT S(I, O, k), such that N ioco S. We have that for each test U ∈ T S, Tr pass (U) ⊆ Tr(S). Thus, Tr pass (U ∩ S) = Tr pass (U) ∩ Tr(S) = Tr pass (U). Since N ioco S, we have, for each α ∈ Tr(S), out(N-after-α) ⊆ out(S-after-α). Let β ∈ Tr pass (U ∩ N); hence, β ∈ Tr pass (U) and β ∈ Tr(N). As Tr pass (U) ⊆ Tr(S), we have that β ∈ Tr(S). It follows that Tr pass (U ∩ N) = Tr pass (U) ∩ Tr(N) ⊆ Tr pass (U) ∩ Tr(S) = Tr pass (U ∩ S) = Tr pass (U). Hence, Tr pass (U ∩ N) ⊆ Tr pass (U). As a result, N passes each test of T S, and T S is thus sound for S in IEIOT S(I, O, k) for the ioco relation.
We now prove by contradiction that T S is exhaustive for S in IEIOT S(I, O, k). Assume that T S is not exhaustive S in IEIOT S(I, O, k); thus, there exists N ∈ IEIOT S(I, O, k), such that N¨ïoco S and N passes T S. As N passes T S, by Lemma 6, we have that N is input-state homeomorphic to S; thus, by Corollary 2, N is input-state isomorphic to an initially connected submachine of S with k input states; hence, by Lemma 5, N ioco S, a contradiction. We conclude then that T S is exhaustive for S in IEIOT S(I, O, k).
Therefore, T S is complete for S in IEIOT S(I, O, k) w.r.t. the ioco relation.

Concluding Remarks
In this paper, we have investigated whether it is possible to construct a finite test suite for a given IOTS specification which is complete in a predefined fault domain for the classical ioco relation even in the presence of input/output conflicts. Our conclusion is that it is in fact possible; however, under a number of assumptions about the implementations and the specifications. We have proposed a generation method which produces a finite test suite, which is complete for a given fault domain. The issue of conflicts between inputs and outputs is tackled by assuming that the implementation is "eager" to read inputs and thus such conflict is solved in favor of input, i.e., outputs are produced only if no input is presented to the implementation. The proposed generation method is based on a classical FSM method. Thus, we rephrased the notions related to FSM generation methods, such as state cover, transition cover, state identifier, to the IOTS model. The method applies to IOTS that is minimal in the sense defined in the paper and each input state is reachable in any ioco-conforming implementation. A remarkable feature of the method is that it requires no assumption about distinguishability of output states or about their number in the specification and any implementation. Also no bound on the buffer's length in the implementation is required to generate a complete test suite.
Our future work will focus on extending the class of IOTSs for which the approach is applicable by relaxing the mentioned constraints.