

P tile Avalon-ST for PCIe IP Core have both rx\_n\_in and rx\_p\_in . Before, the binding difference should be taught to have only one pin . Now I confuse how to binding it.

  ,input  wire          rx\_n\_in0 

     ,input  wire          rx\_n\_in1 

     ,input  wire          rx\_n\_in2 

     ,input  wire          rx\_n\_in3 

     ,input  wire          rx\_n\_in4 

     ,input  wire          rx\_n\_in5 

     ,input  wire          rx\_n\_in6 

     ,input  wire          rx\_n\_in7 

     ,input  wire          rx\_n\_in8 

     ,input  wire          rx\_n\_in9 

     ,input  wire          rx\_n\_in10 

     ,input  wire          rx\_n\_in11 

     ,input  wire          rx\_n\_in12 

     ,input  wire          rx\_n\_in13 

     ,input  wire          rx\_n\_in14 

     ,input  wire          rx\_n\_in15 

     ,input  wire          rx\_p\_in0 

     ,input  wire          rx\_p\_in1 

     ,input  wire          rx\_p\_in2 

     ,input  wire          rx\_p\_in3 

     ,input  wire          rx\_p\_in4 

     ,input  wire          rx\_p\_in5 

     ,input  wire          rx\_p\_in6 

     ,input  wire          rx\_p\_in7 

     ,input  wire          rx\_p\_in8 

     ,input  wire          rx\_p\_in9 

     ,input  wire          rx\_p\_in10 

     ,input  wire          rx\_p\_in11 

     ,input  wire          rx\_p\_in12 

     ,input  wire          rx\_p\_in13 

     ,input  wire          rx\_p\_in14 

     ,input  wire          rx\_p\_in15 

     ,input  wire          tx\_n\_out0 

     ,input  wire          tx\_n\_out1 

     ,input  wire          tx\_n\_out2 

     ,input  wire          tx\_n\_out3 

     ,input  wire          tx\_n\_out4 

     ,input  wire          tx\_n\_out5 

     ,input  wire          tx\_n\_out6 

     ,input  wire          tx\_n\_out7 

     ,input  wire          tx\_n\_out8 

     ,input  wire          tx\_n\_out9 

     ,input  wire          tx\_n\_out10

     ,input  wire          tx\_n\_out11

     ,input  wire          tx\_n\_out12

     ,input  wire          tx\_n\_out13

     ,input  wire          tx\_n\_out14

     ,input  wire          tx\_n\_out15

     ,input  wire          tx\_p\_out0 

     ,input  wire          tx\_p\_out1 

     ,input  wire          tx\_p\_out2 

     ,input  wire          tx\_p\_out3 

     ,input  wire          tx\_p\_out4 

     ,input  wire          tx\_p\_out5 

     ,input  wire          tx\_p\_out6 

     ,input  wire          tx\_p\_out7 

     ,input  wire          tx\_p\_out8 

     ,input  wire          tx\_p\_out9 

     ,input  wire          tx\_p\_out10

     ,input  wire          tx\_p\_out11

     ,input  wire          tx\_p\_out12

     ,input  wire          tx\_p\_out13

     ,input  wire          tx\_p\_out14

     ,input  wire          tx\_p\_out15

 

 

Thanks a lot !! 







 How to bind pins for P tile PCIe
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Hello Sir,

 

The serial output and serial input always some with differential pin. So, they should have "P" and "N" pins. For PCIe IP before P-tiles, the "N" pin is not generate at the PCIe IP top level. However, if you run full compilation. You can see fitter auto assign the "N" pin appended with (n) . You can find this info in the fitter report, under resource section, output/input pins. below is the screenshot for non-ptile PCIe fitter report.

![pn.JPG](/t5/image/serverpage/image-id/6599iDE169E0569EA8D63/image-size/large?v=1.0&px=999 "pn.JPG")

For P-tile, the "P" and "N" pins is declare at the PCIe IP top level, what you need to do is pull both "P" and "N" signal to your design top level. And you only need to take care about the "P" pin location like what you did for non-Ptile PCIe, then quartus will auto fit the "N" pin for you.






Thanks , thanks very much, I have figure it out. 

I was so stupid that I asked you this question, which brought you trouble.






No problem 😄 Hope my answer here can help others user as well.



