In processes of fabricating microelectronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited onto a surface of a substrate in a stepwise fashion. Portions of the layers may be removed, followed by further processing by selectively adding and removing materials, all with great precision. As layers are deposited onto and then removed from the substrate, the uppermost surface of the substrate may become non-planar. Before adding more material, the non-planar surface is sometimes processed by “planarization” to produce a smooth surface for a subsequent layer and processing.
Planarizing or polishing a non-planar surface is a process where material of a non-planar surface is removed to leave a highly planar surface. Planarization is useful to remove undesired surface topography such as a rough (un-even) surface, or defects such as agglomerated materials, crystal lattice damage, scratches, or contaminated layers or materials. In one particular use, planarization removes excess material that has been deposited over a substrate surface to fill features such as channels or holes of a lower layer or layers or holes, if the deposited layer exhibits an un-even surface.
Chemical-mechanical planarization, or chemical-mechanical polishing (CMP), is an established commercial technique for planarize substrates in microdevice fabrication. CMP uses a liquid chemical composition known as a CMP composition, alternately a polishing composition, a polishing slurry, or just slurry, in combination with a CMP pad, to mechanically and chemically remove material from a non-planar substrate surface. A slurry can be typically applied to a substrate by contacting the surface of the substrate with a CMP polishing pad to which the slurry has been applied. Material is typically removed from the substrate surface by a combination of mechanical activity of abrasive material contained in the slurry, and chemical activity of chemical materials of the slurry.
To advance the eternal objective of reducing sizes of microelectronic devices, components that make up the devices must be smaller and must be positioned ever more closely together. Electrical isolation between circuits is important for ensuring optimum semiconductor performance, but becomes increasingly difficult with smaller devices. To that end, various fabrication methods involve etching shallow trenches into a semiconductor substrate and then filling the trenches with insulating material, thereby isolating nearby active regions of an integrated circuit. One example of such a process is referred to as shallow trench isolation (STI). This is a process in which a semiconductor layer is formed on a substrate, shallow trenches are formed in the semiconductor layer via etching or photolithography, and dielectric material is deposited over the etched surface to fill the trenches.
To ensure complete filling of trenches, an excess amount of the dielectric material is deposited over the etched surface. The deposited dielectric material (e.g., a silicon oxide) conforms to the topography of the underlying semiconductor substrate, including at the trenches. Thus, after the dielectric material has been placed, the surface of the deposited dielectric material is characterized by an uneven combination of raised areas of the dielectric material separated by trenches in the dielectric material, the raised areas and trenches of the dielectric material aligning with corresponding raised areas and trenches of the underlying surface. The region of the substrate surface that includes the raised dielectric material and trenches is referred to as a pattern field of the substrate, e.g., as “pattern material,” “pattern oxide,” “pattern dielectric,” etc. This region is characterized by a “step height,” which is the difference in height of the raised areas of the dielectric material relative to the trench height.
Excess dielectric material that makes up the raised areas is removed by a CMP process to produce a planar surface. During removal of the raised area material, an amount of material of the trenches will also be removed. This removal of material from the trenches is referred to as “trench loss.” In a useful process the rate of removal of material from trenches is well below the rate of removal from raised areas. Thus, as material of the raised areas is removed (at a faster rate compared to material being removed from the trenches) the pattern dielectric becomes a highly planarized surface that may be referred to as a “blanket” region of the processed substrate surface, e.g., “blanket dielectric” or “blanket oxide.”
Chemical Mechanical polishing processes for removing pattern dielectric materials can be characterized by performance parameters that include: various polishing rates (i.e., removal rate), trench loss, planarization efficiency, and a highly desired property of “self-stopping” behavior.
Trench loss is the amount (thickness, e.g., in Angstroms (Å)) of material removed from trenches in achieving planarization of pattern material by eliminating an initial step height. Trench loss is calculated as the initial trench thickness minus a final trench thickness.
Removal rate refers to a rate of removal of material from a surface of a substrate and is usually expressed in terms of units of length (thickness) per unit of time (e.g., Angstroms (A) per minute). Different removal rates relating to different regions of a substrate, or to different stages of a polishing step, can be important in assessing process performance. A “pattern removal rate” is the rate of removal of dielectric material from raised areas of pattern dielectric at a stage of a process during which a substrate exhibits a substantial step height. “Blanket removal rate” refers to a rate of removal of dielectric material from a planarized (i.e., “blanket”) dielectric material at an end of a polishing step, when step height has been significantly (e.g., essentially entirely) reduced.
Planarization efficiency relates to trench loss that occurs, per step height reduction, in achieving a planar surface, i.e., step height reduction divided by trench loss.
In various dielectric polishing steps (e.g., of an STI process) the rate of removal of pattern dielectric is typically a rate-limiting factor of the overall process. Therefore, high removal rates of pattern dielectric (the “pattern removal rate”) are desired to increase throughput. Good efficiency in the form of relatively low trench loss is also very important. Further, if the removal rate of dielectric remains high after achieving planarization (i.e., the “blanket removal rate”), overpolishing occurs, resulting in added trench loss.
In certain particularly unique and advantageous processes, overpolishing and associated trench loss can be avoided if a blanket removal rate is especially low. A related and highly desirable performance property is referred to as “self-stopping” behavior. Self-stopping behavior is a highly uncommon process feature, especially in processes that also include high pattern removal rate. In a self-stopping process, when a large percentage of topography thickness (e.g., raised portions) has been removed, the removal rate decreases dramatically. With self-stopping behavior the removal rate is effectively high while a significant step height is present at the substrate surface, but will then become extremely low when the surface becomes effectively planar.
Advantages of self-stopping slurries result from the reduced blanket removal rate, which produces a wide endpoint window. As one practical effect, self-stopping behavior can allow for processing of substrates having reduced dielectric film thickness, allowing for a reduced amount of material to be deposited over a structured lower layer. Also, the need for endpoint detection can be eliminated and planarization can be more efficient. Substrates can be polished with lower trench loss by avoiding overpolishing or unnecessary removal of dielectric after planarization.
Need exists for ongoing improvement in CMP compositions and processes of chemical-mechanical planarization and polishing, including for processing substrates that contain pattern dielectric materials (e.g., silicon oxide). Desired compositions and methods should perform at useful or advantageously high pattern removal rates, while also providing improved planarization efficiency by way of reduced or low levels of trench loss. In highly preferred embodiments, a slurry and process can exhibit self-stopping behavior.