a dual damascene process for forming conductive interconnects on an integrated circuit die . the process comprises providing a layer of porous , ultra low - k dielectric material in which a via opening is subsequently formed . a thermally degradable polymeric material is applied to the side walls of the opening such that the porogen material penetrates deeply into the porous ulk dielectric material . once a conductive material has been provided with the opening and polished back by means of chemical mechanical polishing , the complete structure is subjected to a curing step to cause the porogen material with the ulk dielectric layer to decompose and evaporate , thereby restoring the porosity of the dielectric layer .