page_title: Signal integrity
section_title: Routing topology
hierarchical_section_title: Signal integrity / Chip-to-chip signal integrity / Routing topology
caption_attribution_description: English: Tree topology similar to that of DDR2 Command/Address (CA) bank
context_page_description: Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise, distortion, and loss. Over short distances and at low bit rates, a simple conductor can transmit this with sufficient fidelity. At high bit rates and over longer distances or through various mediums, various effects can degrade the electrical signal to the point where errors occur and the system or device fails. Signal integrity engineering is the task of analyzing and mitigating these effects. It is an important activity at all levels of electronics packaging and assembly, from internal connections of an integrated circuit, through the package, the printed circuit board, the backplane, and inter-system connections.
context_section_description: The noise levels on a trace/network is highly dependent on the routing topology selected. In a point-to-point topology, the signal is routed from the transmitter directly to the receiver (this is applied in PCIe, RapidIO, GbE, DDR2/DDR3/DDR4 DQ/DQS etc.). A point-to-point topology has the least SI-problems since there is no large impedance matches being introduced by line T's (a two-way split of a trace).
  For interfaces where multiple packages are receiving from the same line, (for example with a backplane configuration), the line must be split at some point to service all receivers. Some stubs and impedance mismatches are deemed to occur. Multipackage interfaces include BLVDS, DDR2/DDR3/DDR4 C/A bank, RS485 and CAN Bus. There are two main multipackage topologies: Tree and fly-by.
caption: Tree topology similar to that of the DDR2 Command/Address (CA) bank
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