page_title: Quad data rate
hierarchical_section_title: Quad data rate
caption_attribution_description: How Quad Pumping Works
context_page_description: Quad data rate is a communication signaling technique wherein data are transmitted at four points in the clock cycle: on the rising and falling edges, and at two intermediate points between them. The intermediate points are defined by a second clock that is 90° out of phase from the first. The effect is to deliver four bits of data per signal line per clock cycle.
  In a quad data rate system, the data lines operate at twice the frequency of the clock signal. This is in contrast to double data rate systems, in which the clock and data lines operate at the same frequency.
  Quad data rate technology was introduced by Intel in its Willamette-core Pentium 4 processor, and was subsequently employed in its Atom, Pentium 4, Celeron, Pentium D and Core 2 processor ranges. This technology has allowed Intel to produce chipsets and processors that can communicate with each other at data rates expected of the traditional front side bus technology running from 400 MT/s to 1600 MT/s, while maintaining a lower and thus more stable actual clock frequency of 100 MHz to 400 MHz.
context_section_description: Quad data rate (QDR, or quad pumping) is a communication signaling technique wherein data are transmitted at four points in the clock cycle: on the rising and falling edges, and at two intermediate points between them.  The intermediate points are defined by a second clock that is 90° out of phase from the first.  The effect is to deliver four bits of data per signal line per clock cycle.
  In a quad data rate system, the data lines operate at twice the frequency of the clock signal. This is in contrast to double data rate systems, in which the clock and data lines operate at the same frequency.
  Quad data rate technology was introduced by Intel in its Willamette-core Pentium 4 processor, and was subsequently employed in its Atom, Pentium 4, Celeron, Pentium D and Core 2 processor ranges. This technology has allowed Intel to produce chipsets and processors that can communicate with each other at data rates expected of the traditional front side bus (FSB) technology running from 400 MT/s to 1600 MT/s, while maintaining a lower and thus more stable actual clock frequency of 100 MHz to 400 MHz.
caption: In QDR, the data lines operate at twice the frequency of the clock signal.
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