page_title: Incremental encoder
section_title: Clock synchronization
hierarchical_section_title: Incremental encoder / Incremental encoder interface / Clock synchronization
caption_attribution_description: English: A 2 flip-flop synchronizer, which uses two D flip-flops to synchronize an asynchronous binary input signal to a clock. The first flip flop performs synchronization. The second flip flop reduces the frequency of errors due to metastability.
context_page_description: An incremental encoder is a linear or rotary electromechanical device that has two output signals, A and B, which issue pulses when the device is moved. Together, the A and B signals indicate both the occurrence of and direction of movement. Many incremental encoders have an additional output signal, typically designated index or Z, which indicates the encoder is located at a particular reference position. Also, some encoders provide a status output that indicates internal fault conditions such as a bearing failure or sensor malfunction.
  Unlike an absolute encoder, an incremental encoder does not indicate absolute position; it only reports changes in position and, for each reported position change, the direction of movement. Consequently, to determine absolute position at any particular moment, it is necessary to send the encoder signals to an incremental encoder interface, which in turn will "track" and report the encoder's absolute position.
  Incremental encoders report position changes nearly instantaneously, which allows them to monitor the movements of high speed mechanisms in near real-time.
context_section_description: An incremental encoder interface largely consists of sequential logic which is paced by a clock signal. However, the incoming encoder signals are asynchronous with respect to the interface clock because their timing is determined solely by encoder movement. Consequently, the output signals from the A and B (also Z and alarm, if used) line receivers must be synchronized to the interface clock, both to avoid errors due to metastability and to coerce the signals into the clock domain of the quadrature decoder.
  Typically this synchronization is performed by independent, single-signal synchronizers such as the two flip-flop synchronizer seen here. At very high clock frequencies, or when a very low error rate is needed, the synchronizers may include additional flip-flops in order to achieve an acceptably low bit error rate.
caption: A 2-FF synchronizer. The line receiver's output signal is applied to Din; the Dout signal is sent to the quadrature decoder.