page_title: 7 nm process
section_title: 7 nm patterning difficulties
hierarchical_section_title: 7 nm process / 7 nm patterning difficulties
caption_attribution_description: English: Self-aligned double patterning has excellent control of spacer-defined features, but the remaining features are vulnerable to being split into two populations: core and gap.
context_page_description: In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nm process as the MOSFET technology node following the 10 nm node. It is based on FinFET technology, a type of multi-gate MOSFET technology.
  Taiwan Semiconductor Manufacturing Company began production of 256 Mbit SRAM memory chips using a 7 nm process in 2017, before Samsung began mass production of 7 nm devices in 2018. The first mainstream 7 nm mobile processor intended for mass market use, the Apple A12 Bionic, was released at Apple's September 2018 event. Although Huawei announced its own 7 nm processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips are manufactured by TSMC.
  AMD has released their "Rome" processors for servers and datacenters, which are based on TSMC's 7 nm node and feature up to 64 cores and 128 threads. They have also released their "Matisse" consumer desktop processors with 16 cores and 32 threads.
context_section_description: The 7 nm foundry node is expected to utilize any of or a combination of the following patterning technologies: pitch splitting, self-aligned patterning, and EUV lithography. Each of these technologies carries significant challenges in critical dimension (CD) control as well as pattern placement, all involving neighboring features.
caption: Spacer patterning issues. Spacer patterning has excellent CD control for features directly patterned by the spacer, but the spaces between spacers may be split into core and gap populations.
exif: {}