  == L0, L3 (transparent) cache ==  Comparison of current ARM cores, says L0. I'll let that slide, maybe. Would there really be any different to L1? I know it's direct mapped and smaller. I assume it's all transparent. I'm not familiar with the cache instrunctions in ARM. IA64/Itanium has some L3 instructions if I recall. I guess no such advanced stuff (for levels) in ARM.   