Time division multiplex telecommunications systems
United States Patent [1 1 Hardy [111 3,878,338 [451 Apr. 15, 1975 l l TIME DIVISION MULTIPLEX TELECOMMUNICATIONS SYSTEMS John Heskeith Martin Hardy, Ipswich, England [73] Assignee: The Post Office, London, England [22] Filed: Nov. 21, I972 [21] Appl. No.: 308,551  
 [75] Inventor:  
 Primary ExaminerRalph D. Blakeslee Attorney, Agent, or Firm-Hall &amp; Houghton [57] ABSTRACT A digital switching network employing pulse code modulation (p.c.m.) for conveying information, for use in time division multiplex (t.d.m.) telecommunications systems. The receive portions of n. p.c.m. systems are applied as inputs to a scanning matrix with each system having been delayed by one bit more than the previous system. The output of the scanning matrix (comprising separate wires on which are read out, at any instant, a different digit from each of the n systems) is written into a random access memory that is one which has a unique storage location for each digit of the n, systems), The output of this memory is interconnectible through t.d.m. connection means with a second random access memory, there being read-out (in parallel) from the first memory and written (in parallel) into the second memory at any instant all of the digits of a channel of one of the p.c.m. systems. The output of the second memory is applied to a second scanning matrix the outputs of which are connected to the send portions of n, p.c.m. systems. At any instant, there are read out from the second memory, on separate wires, a different digit of each of the n, systems, and on each output of the second scanning matrix there are read-out (in series) the digits of each channel of a respective p.c.m. system. The outputs of the second scanning matrix include delays applied in the reverse order to the delays in the inputs of the first-mentioned scanning matrix.  
 25 Claims, 11 Drawing Figures PATENTEUAPR 1 5197s MSU SHEET GIUF 11 OTHER CONCENTRATOR INTER MS U LINKS AND OTHER SER V/CES F/GJ  ELL/23 L 28 2 29 5% 0% UNIT70 20 E 207 FIG 7 sum DEUF 11 A 21 12; 26 ct 301E211 2T: 8 8 E a 475-: 25 27 E 20 E 8 E 206 0: M 0 E --&#39;P&#39; F 1 8 JL 5222 r UNIT7O 2 FIG 7 g 201 J*@ A P5 5 L23 K 400 24 a 8 20 INTER MSU g A LINKS AND OTHER N SERVICE FIG. 2.  
 WENTEUAPRISWs 3,878,338  
 SHEET on D? 11 \I QMFu-AWCDN BINARY-DEC/MAL corvvsmm.  
 lB/NARYCOUNTERI 4&#39;4 PATENTEDAPR 1 5 I975 SHEET CSUF 11 CYCL/C ADDRESS GENERATOR 200 65 AND LOGIC CIRCUIT 28 CHANNEL x G9 CHANNEL 1 RE D READ READ x ADDRESS ENABLE ADDREss READ (sYsrEMND) (SYSTEM N0.) (CHANNEL N0.) ENABLE /55 CHANNEL 53 l (N0. I 7 L N P D R s T sH/FTREC/sTER A l 54* 4 4 56mg); SHIFT REGISTER SET TO l I 1 ALL 7&#39;s l A BINARY C0uN rER 55/ PATENTEDAPRI 51975 SHEET G70! 11 FROM COMMON CONTROL PATENTEBAPR 1 5x975 SHEET U8 BF 11 READ 0 ENABLE READ ENABLE W- WRITE R- READ FIG. 8.  
 PATENTEDAPR I 5l975 SHEET USUF 11 PATENTEU R 1 5 I SHEET lUUF 11 8 Es SE28 O\ om o 25$ C a QQW mm mm mm PATENTEDAFR 1 5 I975 SHEET MW 11 mm mokqmmzmw mmmmqmq 0396 29mm J 8:2: SE28 J TIME DIVISION ML&#39;LTIPLEX TELECOMMUNICATIONS SYSTEMS This invention relates to time division multiplex (t.d.m.l telecommunications systems. with particular reference to digital switching systems. employing pulse code modulation (p.c.m.) for conveying information. and it will be described in relation thereto.  
  The object ofthe invention is the provision of an integrated p.c.m. system for the transmission and switching of digital information. thereby making unnecessary any intermediate demodulation-remodulation sequence.  
  It should be understood that the information to be transmitted may originate in the form of either speech or data in any form.  
  The present invention provides a digital switching network comprising at least one first storage means having a plurality of inputs which are the receive portions of respective p.c.m. systems. the first storage means being operable to store. in parallel. the serial digits of each channel of said p.c.m. systems; at least one second storage means having a plurality of outputs which are the send portions of respective p.c.m. systems; t.d.m. connection means for interconnecting out puts of the first storage means with inputs ofthe second storage means. and control means operable to establish a desired connection between an input channel of the first storage means and an output channel ofthe second storage means by: reading-out. in parallel. from said first storage means. the digits of said input channel at a time allocated by said t.d.m. connection means; writ ing-in said readout. in parallel. into the second storage means at the said allocated time. and serially readingout to said output channel the parallel-stored digits of said input channel from the second storage means.  
  In an embodiment of the invention there are at least one pair of first storage means the outputs of which are common and at least one pair of second storage means the inputs of which are common.  
  The control means may include a common control connected to receive information from any input channel of first storage means relating to a desired connec tion to be established between that input channel and an output channel of second storage means. The con trol means may then also include a call set-up unit operable to test for the existence of a free input channel in conjunction with the existence of a free output channel necessary to establish the said desired connection. and then to apply addresses to the first and second storage means to read-out from first storage means the digits of said free input channel and to write-in said readout into second storage means.  
  In embodiments of the invention described herein. the control means includes. for the first and second storage means at least one respective information address memory. in bothway communication with the common control. for storing the address of each operational location ofthe storage means. The control means also includes. for the first storage means. at least one state of channel memory. in bothway communication with the common control. for storing the state of each input channel of the first storage means. and. for the second storage means. at least one state of channel memory. in bothway communication with the common control. for storing the state of each output channel of the second storage means. In addition. the control means includes. for the second storage means. at least one second address memory. in hoth way communication with the common control. for receiving information relating to the interconnections required between outputs of the first storage means and inputs of the second storage means to establish a desired connection between an input channel and an output channel.  
  By way of example only. embodiments of the invention will now he described with reference to the accompanying drawings in which:  
  FIG. I is a block schematic diagram of a telephone exchange system embodying the invention.  
  FIGS. 2 and 3 fit together. and show a block schematic diagram of the MAIN SWITCHING L&#39;NIT depicted in FIG. 1.  
  FIGS. -I and 5 fit together. and shown in more detail the operation of the RECEIVE CONVERSION L&#39;NIT and RECEIVE DIGITS STORE shown in FIGS. 2 and Q FIG. 6 is a timing chart of the input p.c.m. systems within the SCANNING MATRIX shown in FIG. 4.  
  FIG. 7 is a block schematic diagram of a CALL SET- UP UNIT associated with the MAIN SWITCHING UNIT shown in FIGS. 2 and 3.  
  FIG. 8 shows the READ ENABLE waveforms used in connection with the WRITING and READING process.  
  FIG. 9 is a block schematic diagram of another form of MAIN SWITCHING UNIT. and  
  FIGS. 10 and II show. in greater detail. a RECEIVE MODULE and a SEND MODULE respectively of FIG. 9.  
  The telephone exchange system depicted in FIG. I comprises a concentrator arrangement. in which the subscribers I are formed into groups. of say ltltltl. each subscriber of a group being connected by an individual local pair 2. to a CONCENTRATOR 3. which in turn is connected by a number of p.c.m. systems 4 to a MAIN SWITCHING UNIT (MSU) 5. which makes provision for connecting together any two subscribers. or connecting a subscriber to another MSU (not shown) via an inter-MSU link. or to other circuits. such as trunks. operator etc.  
  It is convenient at this stage to explain what is to be understood by certain terminology used in the explanation of the embodiment.  
  A p.c.m. system is typically made up of 32 channels (0-31 I each channel formed by a time slot. The sampling rate is taken to be 8 kHz. thereby giving the 32 time slots an occupancy of I25 micro-seconds. this period being termed a frame. Each slot is 8-bit coded. i.e. 8 binary digits. Two of the channels. namely 0 and 16. are used for signalling. the remaining 30 channels being used for information. which may originate as speech or data.  
  Each p.c.m. system is carried on a time division multiples (t.d.m.) circuit comprising two Z-wire highways (HW) designated as RECEIVE or SEND. in accordance with the direction of transmission relative to the MSU.  
  Operation of the MSU will now be described with reference to FIGS. 2 and 3 in which a plurality of p.c.m. systems A to N are shown connected to the MSU.  
  Each of the p.c.m. systems A to N is terminated in the MSU on a respective SYSTEM CONTROL 20 as shown in FIG. 2. The output of each SYSTEM CON- TROL 20 is a respective Z-wire RECEIVE HW 2I which is connected as one input to one of two RE CEIVE CONVERSION UNITS 22. 202. Each SYS- TEM CONTROL is also connected by a bothway circuit 23 with a COMMON CONTROL 24 the function of which will be described below. Each ofthe RE- CEIVE CONVERSION UNITS 22. 202 has provision for eight of the I-w ire RECEIVE HWs 21 (designated 0-7l to be connected to it. and it is for this reason that two such UNITS are shown in FIG. 2. In general. the number of RECEIVE CONVERSION LNITS required will depend on the total number of p.c.m. systems terminating at the MSU. The Z-wire RECEIVE HWs 21 of the incoming p.c.m. systems A to N are not distributed in strict rotation as input to RECEIVE CON VER- SION UNIT 22. 202 as a matter of security.  
  Each RECEIVE CONVERSION UNIT 22. 202 ca ters for a total of 256 input channels. and its purpose is to comert the serially-disposed 8 digits ofeach channel into parallel form on eight outputs. The output 25 of each RECEIVE CONVERSION UNIT 22. 202 (comprising the eight outputs 25) is connected as input to a respective RECEIVE DIGITS STORE 26. 206 comprising 8 parallel stores one for each store of the digits and each ha\ing a capacity of 256 bits. The output of each RECEIVE DIGIT STORE 26. 206 comprises eight paths in parallel and is referred to as a READ PARALLEL HIGHWAY (HW) 27. 207 respecti\ely. The two READ PARALLEL HW&#39;s 27. 207 are cross connected with two similar eight-path WRITE PARALLEL HWs 30. 300 (FIG. 3) in t.d.m. connection means comprising a space switch 105 and each WRITE PARALLEL HW 30, 300 is connected as input to a respective SEND DIGITS STORE 31. 301 similar to RECEIVE DIGITS STORE and having a capacity for 256 hits in each of eight parallel stores. Each SEND DIGIT STORE 31. 301 has an output of eight paths 32. one for each of the eight digits connected as input to a respective SEND CONVERSION UNIT 33. 303 hav ing eight outputs. each of which is a Z-wire SEND HW connected to a respective one of the SYSTEM CON- TROL 20. in FIGS. 2 and 3 for example one of the SEND HW&#39;s carries the reference 34 and is shown connected to SYSTEM CONTROL 20 of the p.c.m. system The purpose of a SEND CONVERSION UNIT 33. 303 is to convert a parallel-stored 8-bit code into a se&#39; rial code on a Z-wire SEND HW.  
  Each RECEIVE DIGITS STORE 26. 206 is associated with a LOGIC CIRCUIT 28. 208; INFORMA- TION ADDRESS MEMORY 29. 209; eight ADDRESS GENERATORS 200. 200&#39; (one for each digit of the RECEIVE DIGITS STORED and a STATE OF CHAN- NEL MEMORY 201. 201&#39;.  
  Similarly. each SEND DIGITS STORE 31. 301 is associated with a LOGIC CIRCUIT 35. 305&#39;. INFORMA- TION ADDRESS MEMORY 36. 306; ADDRESS GENERATORS 37. 307 and STATE OF CHANNEL MEMORY 38. 308.  
  In addition each SEND DIGITS STORE 31. 301 has a CROSS POINT PT.) ADDRESS MEMORY 39.  
  The INFORMATION ADDRESS MEMORIES and STATE OF CHANNEL MEMORIES of both the RE- CEIVE and SEND DIGITS STORES. and the XPT. ADDRESS MEMORIES of the SEND DIGITS STORE are in bothway communication with a COMMON CONTROL 24. by means of paths 302.  
 SET-L&#39;P CONNECTION The set-up of a connection between. say. calling channel of p.c.m. system A. and a called channel of p.c.m. system K (which connection is designated by COMMON CONTROL 24 as a result of information received from channel .v will now be described System A terminates in SYSTEM CONTROL 20. and the information from the calling channel is conveyed by bothway path 23 to the COMMON CON- TROL 24.  
  The 2-wire RECEIVE HW 21 of system A terminates as input O. together with similar inputs 1-7. on RE- CEIVE CONVERSION UNIT 22. Within this unit the eight input systems. each of 32 serial Sbit channels are scanned in such a way that the contents of each channel is written in parallel on eight paths 25 into the RE CEIVE DIGITS STORE 26. at locations corresponding to their system and channel number. This process is termed cyclic writing&#34;.  
  The addresses of all locations in the RECEIVE DIG- ITS STORE 26 that are currently carrying traffic. are also stored in the INFORMATION ADDRESS MEM- ORY 29 associated with it. and which is in bothway communication with the COMMON CONTROL 24.  
  COMMON CONTROL 24. having been instructed by the calling channel .v of system A that a connection is required to a called destination reached over system K. will find a free channel y in system K over which the required connection can be setup. and will ascertain which SEND CONVERSION UNIT provides access to system K 1 in FIG. 3 it is SEND CONVERSION UNIT 303 and its output Z-wire SEND HW 304 which provide access to system K. COMMON CONTROL 24 must also ascertain the RECEIVE and SEND CON- VERSION UNITS involved in the other direction. ie called channel to calling channel. In FIG. 3 system K has access by Z-wire RECEIVE HW 400 to RECEIVE CONVERSION UNIT 202. and SEND CONVERSION UNIT 33 has access. over Z-w&#39;ire SEND HW 34. to sys tem A.  
  The COMMON CONTROL 24. over the paths 302. will store the address of the calling channel in INFOR- MATION ADDRESS MEMORIES 29 on the RE- CEIVE side. and 36 on the SEND side. and the ad dresses of the called channel in INFORMATION AD- DRESS MEMORIES 209 on the RECEIVE side. and 306 on the SEND side.  
  In order to setup a bothway connection. the COM- MON CONTROL 24 must find two common channels. in the PARALLEL HWs. one that is free both in the READ PARALLEL HW of the calling channel. and in a WRITE PARALLEL HW leading to the required called destination. and another that is free in the READ PARALLEL HW of the called destination and in a WRITE PARALLEL HW leading to the calling channel. ie in the connection being set-up from calling channel .v of system A to called channel v of system K. the first channel must be free in both t.d.m. READ PARALLEL HW 27 and in t.d.m. WRITE PARALLEL HW 300. and the second channel must be free in both t.d.m. READ PARALLEL HW 207 and in t.d.m. WRITE PARALLEL HW 30.  
  COMMON CONTROL 24 tests in co-operation with a CALL SET-UP UNIT (FIG. 7]. for the two common channels. by application over the paths 302, to STATE OF CHANNEL MEMORIES. 201 for RE- CEIVE DIGITS STORE 26&#39;. 308 for SEND DIGITS STORE 30I&#39;. 201&#39; for RECEIVE DIGITS STORE 206. and 38 for SEND DIGITS STORE 31.  
  The CALL SET-UP UNIT 70 is described in more detail later with reference to FIG. 7.  
  Having selected the channels. COMMON CON- TROL 24 instructs each of the XP&#39;I&#39;. ADDRESS MEM- ORIES 39 and 309 as to which crosspoints of the space switch I05 must be operated. and at what time. and instructs INFORMATION ADDRESS MEMORIES 29. 306. and 209. 36.  
  The calling channel information is read-out of the RECEIVE DIGITS STORE 26 in parallel on to the t.d.m. READ PARALLEL HW 27. This is termed acyclic reading&#39;v The information is cross-connected. by reason of the operated crosspoints. to t.d.m. WRITE PARALLEL HW 300 and written-in to SEND DIGITS STORE 301, where it is stored in parallel. This is termed acyclic writing.  
  By means of SEND CONVERSION UNIT 303. the information is read-out from SEND DIGITS STORE 30I and transmitted serially on Z-vvire SEND HW 304 to the SYSTEM CONTROL of system K. This is termed cyclic reading.  
  A similar sequence ofevents takes place. in the other direction. when channel y ofsystem K is originating information. involving the following components: SYS- TEM CONTROL 20 of system K; RECEIVE HW 400&#39;.  
 RECEIVE CONVERSION UNIT 202: RECEIVE DIG- ITS STORE 206; READ PARALLEL HW 207: WRITE PARALLEL HW 30. SEND DIGITS STORE 31. SEND CONVERSION UNIT 33. and Z-Wire SEND HW 34 to SYSTEM CONTROL 20 of system A.  
  The arrangement shown in FIGS. 2 and 3 will now be described in more detail with reference to FIGS. 4 and 5.  
  A RECEIVE CONVERSION UNIT. such as 22 of FIG. 2, comprises an 8 X 8 SCANNING MATRIX {or series/parallel conversion means) 40. in which each vertical 0-7 is a Z-wire. 32 channel p.c.m. RECEIVE HW 2].. and each horizontal 0-7 is an output to a dif ferent one of the DIGIT STORES 0-7 of RECEIVE DIGITS STORE 26. The enable inputs 42 of the SCANNING MATRIX 40 are connected diagonally to eight scan outputs of a SCAN GENERATOR comprising BlNARY-DECIMAL CONVERTER 43, driven by a 3-bit BINARY COUNTER 44. driven at 2.048 M Hz.  
  The 4-wire p.c.m. systems enter the MAIN SWITCH- ING UNIT in frame alignment. and then the Z-wire RE- CEIVE HW&#39;s I-7 are re-timed. each being delayed by l-bit (488 115) more than the previous system. by means of DELAY UNITS 45. before being applied to the SCANNING MATRIX 40. This allows the scanning process to extract the serial 8-bit coded content of each channel of each of the eight systems. on to eight parallel outputs (one for each ofthe digits 0-7) and write them into the RECEIVE DIGITS STORE 26, at a location corresponding to the system and channel number of the digit. each of the digit stores having a capacity of 256 bits. The RECEIVE DIGITS STORE 26 constitutes a random access memory having a unique storage location for each of the 256 digits of the eight p.c.m. systems. thereby providing full availability.  
  The timing of the serial digits of the input systems within the SCANNING MATRIX 40. is illustrated in the chart shown in FIG. 6. from which it can be seen that at any instant in time. the eight parallel outputs refer to a different digit from each of the p.c.m. systems. and that the bit outputs of some systems refer to one channel. while the bit outputs of the other systems refer to a different channel. with the exception ofevery I in 8 bit times. when all outputs refer to the same channel. If the chart is examined from system 0 down to system 7 for any instant of time. it is seen that for 7 out of 8 bits. one or more systems refer to channel .v. and the remainder to channel .\&#39;-I.  
  The 256 K Hz output 46 of BINARY COUNTER 44 is used to drive a CHANNEL NUMBER GENERA- TOR 52 of the ADDRESS GENERATOR 200 CHAN- NEL NUMBER GENERATOR 52 is a 5-bit BINARY COUNTER the outputs 53 of which each correspond to a channel number x, and are fed into a gate G8 of the LOGIC CIRCUIT 28. and into parallel input SHIFT REGISTER 54, the outputs 55 of which are fed into gate G7 of the LOGIC CIRCUIT 28 and correspond in each case to a channel number one less than the corresponding output of BINARY COUNTER 52. i.e. channel .v-I.  
  BINARY COUNTER 52 thus provides channel .v outputs. and SHIFT REGISTER 54 provides channel .v-I  
 -- outputs.  
  The selection of channel number .v or .v-l for a particular DIGITS STORE is determined by the outputs of 7-bit SHIFT REGISTER 58 which are applied to the second enable input of channel member gates G7 and G8. The SHIFT REGISTER 58 is set to all [&#39;5&#39; by a synchronising pulse from the output of the BINARY COUNTER 44.  
  The system number for each DIGIT STORE 0-7 of RECEIVE DIGITS STORE 26. is generated by a 3 bit BINARY COUNTER 56 of the ADDRESS GENERA- TOR. the COUNTER 56 being synchronised to zero by output 42 of BlNARY-DECIMAL CONVERTER 43.  
  Each of the DIGIT STORES 0-7 of RECEIVE DIG- ITS STORE 26 has eight address inputs L to N and P to T. of which inputs L. M and N are the system number. and inputs P. O. R. S and T are the channel numher.  
  It will be seen in FIG. 5 that a portion only of LOGIC CIRCUIT 28 is shown. relating only to input L of the system address. and input P of the channel address in respect of DIGIT STORE O it should be understood that a similar arrangement applies also to inputs M. N. O. R. S and T. and also to each of the other DIGIT STORES l-7.  
  The 24-bit serially-coded. 256 channels of eight incoming p.c.m. systems are stored in parallel in the RE CEIVE DIGITS STORE 26, the eight outputs of which constitute the READ PARALLEL HW 27. Referring back to FIGS. 2 and 3. it is seen that the 8-t.d.m. path READ PARALLEL HWs 27 and 207 are crossconnected with 8-t.d.m. path WRITE PARALLEL HW&#39;s 30 and 300, each connected as inputs to an arrangement of SEND DIGIT STORES 3| and 301 and SEND CONVERSION UNITS 33 and 303, having as outputs 2-wire SEND HW&#39;s. such as 34 and 304 respectively. This arrangement operates in a manner similar to that already described relating to the RECEIVE side. but in the opposite mode. in that the WRITE and READ functions are reversed. so that an 8-bit parallel code from WRITE PARALLEL HW 30 is written into SEND DIGITS STORE 3I and converted by SEND CONVERSION UNIT 33 into an 8-bit serial code for transmission on a Z-wire SEND HW. such as 34. Only one ADDRESS GENERATOR 37. 307 is associated with each SEND DIGITS STORE 31. 301 as mentioned above. the reason for this being that each of the WRITE PARALLEL HW&#39;s 30. 300 is in frame alignment.  
  It will be remembered that the Z-wire REC. HW&#39;s 2I are delayed relative to each other before being applied to the SCANNING MATRIX 40. and therefore it is necessary to restore the Z-wire SEND HWs -7 (34. 304 etc.) into alignment. before they are applied to the SYSTEM CONTROLS 20. The SEND HW&#39;s accordingly include delay units in a manner similar to that shown in FIG. 4 for the RECEIVE HW&#39;s. but in re\erse order. SEND HW 0 being delayed by 7 bits relative to SEND HWO. down to SEND HW 6 being delayed by l-bit. (see also FIG. II described below).  
  In order to provide non-blocking switching. the READ and WRITE PARALLEL HW&#39;s are operated at twice the p.c.m. bit rate employed for the rest of the MSU. Thus the PARALLEL HW&#39;s operate at 4.096 MHz. with l 2 channels per frame.  
  No such limitation is implied however. The PARAL- LEL HWs may be operated at the same bit-rate as the rest of the MSU (an arrangement of this type being described below with reference to FIGS. 9 and 10) or at any other suitable rate.  
  The selection of the two free common channels in the parallel highways. one for each direction of transmission between the RECEIVE DIGITS STORES and the SEND DIGITS STORES will now be described in more detail. relative to FIG. 7. For simplicity. the description will be restricted to the selection of two free common channels for one direction of transmission only (say. from RECEIVE DIGITS STORE 26 to SEND DIGITS STORE 303) and it will be understood that the selection of two free common channels for the other direction of transmission will be similar.  
  The CALL SET-UP UNIT 70 is associated. by means of allocation switches 7I(u) and 71th) with the STATE OF CHANNEL MEMORIES 201 and 308. and the INFORMATION ADDRESS MEMORIES 29 and 306. of the RECEIVE and SEND DIGITS STORES 26 and 303.  
  The STATE OF CHANNEL MEMORIES 201. 308 store &#39;0&#39; for a busy channel and l for a free channel.  
  The COMMON CONTROL (FIG. 2). via lead 76. stores the system and channel address of the calling channel (.t of system A) in 9-bit SHIFT REGISTER 77 of the INFORMATION ADDRESS MEMORY 29 (8 bits for system and channel address. and 1 bit for state of channel). and via lead 78. the system and channel address of the called channel (y of system K) in 17-bit SHIFT REGISTER 79 of the INFORMATION AD- DRESS MEMORY 306 (8 bits for system and channel address. I bit for state of channel. and 8 bits for crosspoint address}.  
  It then instructs each of the STATE OF CHANNEL MEMORIES I and 308 to output their contents to the CALL SET-UP UNIT 70. where they are stored in 5 l 2-bit SHIFT REGISTERS 700 and 70I respectively. whose outputs are compared in gate 702. Coincident free channels are gated. through gate 703 by a coincident channel pulse from 9-bit SHIFT REGISTER 704 to lead 705 and. via allocation switch 7Ilbl. are transmitted on lead 706 to 9-bit SHIFT REGISTER 707 associated with the RECEIVE DIGITS STORE 26. and  
 Ill  
 also. via lead 708. to 9-bit SHIFT REGISTER 709 associated with the SEND DIGITS STORE 303. The coincident free channels applied to SHIFT REGISTER 707 are compared with the output of COUNTER 7I0 running in synchronism with the ADDRESS MEMORIES and. at coincidence in gate 7I I. the information held in REGISTER 77 is written into the INFORMATION ADDRESS MEMORY 29. and into STATE OF CHANNEL MEMORY 20]. Similarly. the coincident channels via allocation switch 71(1)) are applied on lead 708 to SHIFT REGISTER 709 where they are compared with COUNTER 712 running in synchronism with the ADDRESS MEMORIES. and at coincidence the information held in REGISTER 79 is written into the INFORMATION ADDRESS MEMORY 306. into STATE OF CHANNEL MEMORY 308 and into the XPT. ADDRESS MEMORY 309 of the SEND DIGITS STORE 303.  
  The logic circuit of a cyclic address generator. as shown in FIG. 5. will not be described in more detail. The system and channel number addresses for the RE- CEIVE DIGITS STORES are generated by means of these cyclic address generators. and the process is termed -cyclic writing. A similar arrangement applies for the SEND DIGITS STORES. except that the operation is reversed. i.e. cyclic reading.  
  This is illustrated in FIG. 8. in which the READ EN- ABLE waveforms are shown at (a) applying to the RE- CEIVE DIGIT STORES. and at (b) applying to the SEND DIGIT STORES.  
  An example of the WRITING and READING operation will be explained for RECEIVE DIGITS STORE 26 (i.e. waveform 8(a) appliesl with reference to FIG. 5.  
  With the output of the READ ENABLE waveform generator at I). cyclic addressing takes place. The system number is connected to the system address inputs L to N of each DIGIT STORE 0-7 of RECEIVE DIG- ITS STORE 26 and one input of each of the channel number gates G5. G7 and G8 is enabled. The selection of channel number .v or .v-] for a particular one of the DIGIT STORES 0-7 is determined by the outputs S3 and S5 of BINARY COUNTER 52 and SHIFT REGIS TER 54. which are applied as inputs to the channel gates G8 and G7 respectively.  
  With the output of the READ ENABLE waveform generator at l. cyclic addressing is inhibited and the READ address is connected to all DIGIT STORES.  
  A detailed operation of the logic circuitry will now be given. the circuit being in the form of positive logic NAND gates. It is convenient to refer to the more posi tive output voltage of gate as represented by logical l. and the more negative output voltage as represented by logical 0.  
  Signal leads will be referred to in accordance with this nomenclature. in that for example. if the condition of data on a lead is as the result of logical I. the lead will be designated as DATA. whereas if the condition is as a result of logical I). the lead will be designated as DATA.  
  For the purpose of this explanation. designate the data applied to leads of FIG. 5 as follows:  
 Lead L from BINARY COUNTER 56. as DATA 1 Lead 53 from BINARY COUNTER 52 as DATA 2 Lead 55 from BINARY COUNTER 54 as DATA 3 READ ADDRESS (CHANNEL NO.) input to G5 as DATA 4 READ ADDRESS (SYSTEM NO.) input to G2 as DATA 5 Output of SHIFT REGISTER 58 as SELECT WRITE (cyclic addressing) READ ENABLE (SYSTEM NO.) input to G2. G3  
  and G5 I) output of G2 and G3 l Cyclic address applied to G4. G7 and G8 Input to G4 is DATA I Input to G7 is DATA 3 Input to G8 is DATA 2 Output of G4 is DATA 1 Output of G2 is I Output of GI is DATA 1. input to DIGIT STORES Inputs to G7 are DATA 3. I from G3. and SELECT Inputs to G8 are DATA 2. I from G3. and SELECT Inputs to G5 are DATA 4 and Output of G I Case I SELECT =I Output of G7 DATA 3 Output of G8 I Case 2 SELECT U Output of G7 I Output of G8 DATA 2 Therefore the output of G6 in. Case I is DATA 3 Case 2 is DATA 2 READ READ ENABLE (SYSTEM NO.)  
  input to G2. G3 and G5 I output of G2 and G3 READ ADDRESS input to G2 DATA 5 output of G2 DATA 5 input to G4 DATA 1 output of 0-8 (l output ofGI DATA 5 READ ADDRESS (CHANNEL NO.) input to G5 DATA 4 other input to G5 I output of (i5 DATA -linput to (I7 (I input to (its (I output ol (i7 I output ol (i8 I input to (in DATA -I. I and I Therefore the output of (in DATA 4.  
  FIG. 9 is a block schematic diagram of another form of MAIN SWITCHING UNIT which could be used in the telephone exchange system illustrated diagrammat ically in FIG. 1. Many of the components of the UNIT illustrated in FIG. 9 correspond to components of the UNIT illustrated in FIGS. 2 and 3 and carry the same reference numerals: reference may. accordingly. be made to the preceding description for further information concerning these components. if required.  
  FIG. 9 shows the Z-wire RECEIVE HW 2! of one of eight p.c.m. systems 0 to 7 connected. through a respective LINE CONVERTOR and CLOCK EXTRAC TOR 9]. a BIT ALIGNER 92 and SLOT ALIGNER 93 to a RECEIVE MODULE 95 (i). It will be understood that the RECEIVE HWs 2| of the other seven of the p.c.m. systems 0 to 7 are also connected in a similar manner to the RECEIVE MODULE 95(1). as indicated in FIG. l0 which shows the RECEIVE MODULE in greater detail.  
  The RECEIVE MODL LE 95 (it includes a RE- CEIVE CONVERSION UNIT 22 comprising DELAY UNITS 45,, 45 and a series/parallel conversion means comprising serial-parallel convertors 94.. 94; and input speech multiplexors 96 96 (FIG. I0). The serialparallel convertors 94 are eightbit shift registers and the outputs of the registers are multiplexed together by the multiplexors 96 so that. as in FIGS. 2 and 3. the seriallydisposed digits of each input channel into parallel form on eight outputs 25. As already mentioned with reference to FIG. 6. there is read out. on the output wires 25. a different digit of the eight p.c.m. systems. The outputs 25 of the RECEIVE CONVERSION UNIT 22 are connected. as in FIGS. 2  
 &#39; and 3. as inputs to a RECEIVE DIGITS STORE 26 27) and the eight-path READ PARALLEL HW 27 is cross-connected in a SPACE SWITCH 105 with a similar eight-path WRITE PARALLEL HW 30. However in FIG. 9 the READ PARALLEL HW 27 is common (as indicated) to (or. in other words. constitutes the output of) a second RECEIVE MODULE (1&#39;1&#39;) (not shown) which is identical in all respects to the RE- CEIVE MODULE 95(i). Two groups of eight p.c.m. systems (i.e. SIZ channels) are thus brought together on the READ PARALLEL HW 27 so that the switch&#39; ing between the PARALLEL HWs 27 and 30 is now subject to blocking. It is envisaged. however. that in practice the amount of blocking would be small.  
  The WRITE PARALLEL HW 30 is common. in a similar manner. to two identical SEND MODULES 97(1&#39;) and 97(ii) only one (97th) of which is shown in FIG. 9. The SEND MODULE 97 includes a SEND DIGITS STORE 31. similar to the RECEIVE DIGITS STORE 26. and comprising eight parallel stores 500 (FIG. II) each having a capacity of 256 bits. The STORE 31 constitutes a random access memory having a unique storage location for each of the 256 digits of the eight p.c.m. systems. thereby providing full availability. The eight output paths of the SEND DIGITS STORE 31 are connected to a SEND CONVERSION UNIT 33 comprising a parallel/series conversion means (eight output speech demultiplexors 960 t 960 and eight parallel-serial convertors 940 940; in the form of 8-bit shift registers and DELAY UNITS 450., 450; (FIG. II). The read-out on the eight output paths of the STORE 3] comprises. at any in stant. a different digit of each of the eight p.c.m. systerns as already explained with reference to FIG. 6 and SEND CONVERSION UNIT 33 converts a parallel stored eight-bit code into a code in serial form on the Z-wire SEND H.W. of one of eight p.c.m. systems.  
  Associated with the RECEIVE DIGITS STORE 26 and forming part of the RECEIVE MODULE 95(1) are a LOGIC CIRCUIT 28 and eight CYCLIC ADDRESS GENERATORS 200 (see FIG. I0 and also FIG. 5). each of the GENERATORS having an input from a respective SLOT ALIGNER 93.  
  Associated with the SEND DIGITS STORE SI. in similar mantter. and fornting part of the SEND MOD- LLE 97H) is a LOGIC CIRCIIT 35 but only ottc CY- CLIC ADDRESS GENERATOR 37 for a reason which will he described below.  
  A single CALL CONTROL UNIT 90 (FIG. 9) is associated with hoth of the RECEIVE MODL&#39;LES 95(1) and 95th). and with hoth of the SEND MODL&#39;LES 97lfl and 97th). The CALI. CONTROL I&#39;NIT 90 contprises an INFORMATION ADDRESS MEMORY 29 and STATE OF CHANNEL MEMORY l which are associated with the RECEIVE DIGITS STORE 2b. and a second INFORMATION ADDRESS MEMORY 36 and a second STATE OF CHANNEL MEMORY 38 which are associated with the SEND DIGITS STORE Tlte CALL CONTROL UNIT 9&#34; is in both way communication with a CALL SET-UP UNIT 70 and a COMMON CONTROL 24.  
  In general. the futtctions of the various components of FIG. 9 are the sante as those of the correspottding components in FIGS. 2 to 4 attd 7 and will not be described in detail. Some modifications are. of course. necessary in view of the fact that the READ PARAL- LEL HW 27 and the WRITE PARALLEL HW are common to two groups of eight pent. systems and these tttodifications will he apparent from the following description of the operation of the SWITCHING UNIT shown in FIG. 9.  
  The READ ENABLE waveforms applying to the RE- CEIVE and SEND DIGITS STORES 26 and SI are as shown in FIG. 84a) and (II) respectively: that is. for the RECEIVE DIGITS STORE 26 there are one \v&#39;rite&#34; period and two read&#34; periods for each ofthe 256 time slots in one frame of I25 micro-seconds while. for the SEND DIGITS STORE 31 the operations are reversed.  
  Taking the RECEIVE DIGITS STORE 26 as an example. during the &#34;write&#34; periods. the operation described ahove as cyclic writing&#34; takes place: that is. the RECEIVE DIGITS STORE 26 is provided with an eight-bit address by the appropriate one of the CY- CLIC ADDRESS GENERATORS 200 via the logic circuit 28. As described ahove with reference to FIG. 5. each CYCLIC ADDRESS GENERATOR Includes a 5-bit synchronous counter (shown in FIG. 5 at 5Zl which is clocked at the pent. slot rate and is reset by a signal front the SLOT ALIGNER 93. The 5-bit synchronous counter provides the channel number of the pent. system to which it relates. and the remaining three hits of the eight-hit address [which constitute the system number) are provided by a 3-bit hinary counter (shown in FIG. 5 at 56).  
  As a more specific example of the operation of cyclic writing. consider the case of channel 5 of pent. system 7. One of the CYCLIC ADDRESS GENERA- TORS 200 is in frame alignment with the slot-aligned pent. system 7. and at the instant (during a -write period) when channel 5 of this system is fully-contained within the shift register 94-. binary 7 (Le. III) is applied to the input speech multiplesors 96... 96-. thereby presenting channel 5 of system 7 to the RE- CEIVE DIGITS STORE 2f). Simultaneously. binary 7 is also applied to the LOGIC CIRCI&#39;IT 28 causing the contents of the appropriate CYCLIC ADDRESS GEN- ERATOR 200 tie 7 and 5) to he applied to the address inputs (shown in FIG. 5 as L to N and P to T) of til the RECEIVE DIGITS STORE 26 so that channel 5 of system 7 is stored in locatiott I l l (lllltll.  
  The information written into the RECEIVE DIGITS STORE 2b is stored for up to one frame attd may be read out during the acyclic periods of that frame in any one of the 512 time slots attd passed to the READ PARALLEL HW 27. During this operation [referred to ahove as aeylic reading) an acylic address is provided by the CALL CONTROL UNIT and is applied to all of the associated DIGIT STORES. Since the two SEND MODLLES 97(1&#39;) and 97(1&#39;1&#39;) do not operate independently during the &#34;read periods of FIG. 8a. the acyclic address includes an additional hit. compared with the uttit of FIGS. 2 and 3. to determine which of the two SEND MODLLES is to he used.  
  The read and write operations associated with SEND DIGITS STORE 31 are generally similar to those described above. but are reversed. However. the WRITE PARALLEL HWs 30 are in frame alignment so that only one CYCLIC ADDRESS GENERATOR 37 is required in association with the SEND DIGITS STORE 31. together with a simplified fornt of LOGIC CIRCL&#39;IT 35.  
  Dttring the write periods of FIG. 8b the acyclic address provided hy the CALL CONTROL UNIT 90 is applied to the LOGIC CIRCUIT 35.  
  During the read periods of FIG. 8b. the CYCLIC ADDRESS GENERATOR 37 provides addresses which cause all information relating to a particular time slot (i.e. channel) to he read out of the SEND DIGITS STORE 31 in ascending order of system number. The CYCLIC ADDRESS GENERATOR 37 comprises an 8-bit synchronous counter clocked at the pent. slot rate. with the three least significant bits providing the system number and the five ntost significant hits providing the time slot lchannel) numher.  
  Durittg time slot II in alternate frames. the outputs of the SEND DIGITS STORE 31 are inhihited arid the frame sync. pattern is inserted by a SYNC. INSER- TION UNIT 99. That is. the MAIN SWITCHING L&#39;NIT of FIG. 9 defines time slot 0 on its SEND pent. systents.  
  The output of the SEND DIGITS STORE 31. which is in the fornt of parallel 8-bit words is demultiplexcd attd converted into serial form by the SEND CONVER- SION UNIT 33. and the staggering ofthe bits produced by the parallel multiplexing process is then removed by the delay units 450 {FIG II) which are applied in reverse order to the corresponding receive delay units 45 of FIG. 10. The outputs of the delay units 450 are then in frame alignment and are passed to a LINE CON- VERTOR I00 [9) and then to line.  
  A SYNC. CODE CHECKER I01 and two PARITY GENERATOR CHECKERS I02. I03 are included in the LNIT of FIG. 9 to provide monitoring checks. but are ttot essential components.  
  Dttring free ittterttal time slots. the locations corresponding l in the RECEIVE DIGITS STORES 26 ofthe two RECEIVE MODL&#39;LES (1&#39;) and 95mm to the time slots 0 are successively addressed and the sync. code tfrantc alignment pattern) which occurs in alternatc frames is read out to the SYNC CODE CHECKER [0]. This provides some check that the RECEIVE DIGITS STORES 26 are functioning (although not necessarily in all locations) and that the preceding transntission paths are transparent.  
  While information is being written into the RE- CEIVE DlGlTS STORES 26. the SPACE SWITCH 105 is effectively idle. since simultaneous reading and writing is not possible. As a result. 256 time slots/frame exist in the SPACE SWlTCH [05. which can be used for internal signalling and data transfer purposes: these signalling slots may. for example. be used to transmit (among other things) a parity bit for the previous speech slots. In the L&#39;Nl&#39;f shown in H6. 9. parity bits for the odd and even speech slots are generated in the odd and even frames respectively. More particularly. during the signalling slots in the odd frames. the PAR- lTY CHECKER 103 on the output side of the SPACE SWITCH 105 causes the space-switch cross points which are operated during the previous odd speech slots to he reoperated. A parity hit is generated and is compared with the parity hit generated in the succeeding odd signalling slot. A similar process occurs during the even frames for the even speech slots. The PARl&#39;fY CHECKER 102 on the input side of the space switch 105 operates in a similar manner.  
  It will be appreciated that a SYNC. CODE (HECKER l0! and PARlTY GENERATOR CHECK- ERS I02. 103 could he employed in a similar manner in the UNl&#39;l&#39; shown in FIGS. 2 and 3.  
 1 claim:  
  1. A time division multiplex digital switching network comprising. in combination a plurality of pulse code modulated communication systems each comprising a plurality of channels. with a plurality of serial digits per channel. each system having an input highway and an output highway.  
 a receive conversion unit to which the plurality of input highways are connected. said receive conver&#39; sion unit comprising a plurality of receive delays. there being for each input highway. at respective unique receive delay which may be zero and to which the input highway is connected. and a series/parallel conversion means to which the outputs of said receive delays are connected. for converting the serial digits of the channels of said input highways into parallel form on a plurality of outputs of said series/parallel conversion means.  
 first storage means to which the plurality of outputs of said series/parallel conversion means are connected. for storing in parallel the serial digits ofthe channels of the input highways.  
 second storage means having a plurality of inputs and a plurality ofoutputs.  
 switchable t.d.m. connection means for interconnecting outputs ofthe first storage means with inputs of the second storage means.  
 it send conversion unit comprising a parallel/series conversion means to which the outputs of the sec ond stage means are connected. and a plurality of send delays. there being. for each output highway. at respective unique send delay. which may be zero and to which an output of said parallel/series conversion means is connected. for converting parallel digital information on the outputs of said second storage means into serial form on any one of a plurality of outputs of said send delays. each output highway being connected to the output of the respective send delay.  
 control means for operating said connection means to establish a desired connection between a chan- Jll nel of an input highway and a channel of an output highway by reading-out in parallel from the first storage means the digits of the said input channel at a time allocated by said connection means and writing-in said read-out in parallel into the second storage means at the said allocated time.  
  2. A network as claimed in claim I. having at least one pair of first storage means the outputs of which are common and at least one pair of second storage means the inputs of which are common.  
  3. A network as claimed in claim l. including for each first storage means. an address generator o erable to generate a respective address for each input channel of said first storage means and to apply the address to the first storage means to write-in. in parallel. the serial digits of the channel.  
  4. A network as claimed in claim 1. including. for each second storage means. an address generator operable to generate a respective address for each output channel of said second storage means and to apply the address to the second storage means to read out. in series. the parallel-stored digits of the channel.  
  5. A network as claimed in claim 1. in which the control means includes a common control connected to receive information from a channel of an input highway relating to a desired connection to be established between that channel and a channel of an output highway.  
  6. A network as claimed in claim 5. in which the con trol means includes a call set-up unit operable to test for and allocate in said t.d.m. connection means a free channel necessary to establish the said desired connection. and then to apply addresses to the first and second storage means to read-out from the first storage means the digits of said channel of an input highway and to write-in said read-out into the second storage means.  
  7. A network as claimed in claim 5. in which the control means includes. for the first and second storage means. at least i one respective information address memory. in bothway communication with the common control. for storing the address of each operational location of the storage means.  
  8. A network as claimed in claim 5. in which the control means includes. for the first storage means. at least one state of channel memory. in bothway communication with the common control. for storing the state of each input channel of said t.d.m. connection means.  
  9. A network as claimed in claim 5. in which the control means includes. for the second storage means. at least one state of channel memory. in bothway communication with the common control. for storing the state of each output channel of said t.d.m. connection means.  
  10. A network as claimed in claim 5 in which the t.d.m. connection means is a cross-point matrix and the control means includes. for the second storage means. at least one second address memory. in both way communication with the common control. for receiving information relating to the interconnections required between outputs of the first storage means and inputs of the second storage means to establish a desired connection between an input channel and an output channel.  
  11. A network as claimed in claim I. in which the receive delays comprise delays of U to (n,l) bits to which the input highways of pcm. systems 0 to tu l I respectively are connected. and the series/parallel conversion means has n, outputs on which are read out in 15 parallel. at any instant. a different digit from each of the n, systems.  
  12. A network as claimed in claim 1]. in which the first storage means has a unique storage location for each of the mp digits of the :1. systems (in being the number of channels in each system and p being the number of digits per channel l.  
  13. A network as claimed in claim I. in which the parallel/series conversion means has n, inputs into which are written in parallel. at any instant. a different digit from each of np.c.m. systems. and the send delays comprise delays of -1 to U bits to which the output highways of p.c.m. systems U to (Hf-l respectively are connected.  
  14. A network as claimed in claim [3. in which the second storage means has a unique storage location for each of the mp digits of the ri systems (In being the number of channels in each system and p being the number of digits per channel).  
  IS. A network as claimed in claim I. in which said se rieslparallel conversion means gimprises a single scanning matrix the outputs of which area plurality of separate wires. and a scan generator for reading out at any instant. on said separate wires. a different digit from each of said p.c.m. systems.  
  16. A network as claimed in claim 1. in which said se ries/parallel conversion means comprises a plurality of shift registers. and multiplesor means to which the out puts of the shift registers are connected.  
  1&#39;]. A network as claimed in claim 1. in which said first storage means comprises. for each output of said series/parallel conversion means. a respective parallel digit store.  
  18. A network as claimed in claim 1. in which said parallel/series conversion means comprises demultiplexor means and a plurality of shift registers to which the outputs of the demultiplesor means are connected.  
  1). A time division multiplex communication system comprising in combination a plurality of incoming pulse code modulated communication systems each comprising a plurality of channels. with a plurality of serial digits per channel. each system having an input highway.  
 a plurality ofoutgoing pulse code modulated communication systems each having an output highway. and  
 a receive conversion unit interconnected between said highways. said unit comprising. for each input highway at respective unique receive delay which may be zero and to which the input highway is connected. and a series/parallel conversion means to which the outputs of said receive delays are connected. for converting the serial digits of each channel of said input highways into parallel form on a plurality of outputs of said series/parallel conversion means.  
 20. A time division multiples communication system comprising in combination a plurality of incoming pulse code modulated communication systems each comprising a plurality of channels. with a plurality of serial digits per channel. each system having an input highway.  
 a plurality of outgoing pulse code modulated communication systems each having an output highway. and  
 a send conversion unit interconnected between said highways. said unit comprising a parallel/series conversion means having a plurality of inputs for receiving in parallel form the digits of the channels of said input highways and. for each output highway. a respective unique send delay which may be zero and to which the output highway is connected. for converting parallel digital information on the inputs of said parallel/series conversion means into serial form on one of said output highways.  
 2]. A time division multiples communication system comprising in combination a plurality of incoming pulse code modulated communication system each comprising a plurality of channels. with a plurality of serial digits per channel. each system having an input highway.  
 a plurality of outgoing pulse code modulated communication systems each having an output highway. and  
 receive and send conversion units interconnected between said highways.  
 said receive conversion unit comprising. for each input highway. at respective. unique receive delay which may be zero and to which the input highway is connected and a series/parallel conversion means to which the outputs of said receive delays are connected. for converting the serial digits of each channel of said input highways into parallel form on a plurality of outputs of said series/parallel conversion means. and  
 said send conversion unit comprising a parallel/series conversion means having a plurality of inputs for receiving in parallel form. the digits of the channels of said input highways. and for each output highway. a respective unique send delay which may be zero and to which the output highway is connected. for converting parallel digital information on the inputs of said parallel/series conversion means into serial form on one of said output highways.  
  22. A system as claimed in claim 2i. in which the receive delays comprise delays of 0 to (In-l) bits to which the input highways of p.c.m. systems 0 to (u,l respectively are connected. and the series/parallel conversion means has n outputs on which are read out in parallel. at any instant. a different digit from each of the a systems.  
  23. A system as claimed in claim 21. in which the parallel/series conversion means has n inputs into which are written in parallel. at any instant. a different digit from each of M p.c.m. systems. and the send delays comprise delays of (&#34;g l to 0 bits to which the output highways of p.c.m. systems (i to -l respectively are connected.  
  24. A system as claimed in claim 21. in which said series/parallel conversion means comprises a single scanning matrix. the outputs of which are a plurality of separate wires. and a scan generator for reading out at any instant. on said separate wires. a different digit from each of said p.c.m. systems.  
  25. A system as claimed in claim 2!. in which said series/parallel conversion means comprises a plurality of shift registers. and multiplexor means to which the outputs of the shift registers are connected.