Electronic selector having a number of inlets and an equal number of outlets for exchange of analog or digital signals
United States Patent Hemdal Apr. 1 1975 Lutz 179/18] Primary E.raminerHarold I. Pitts Arlorney, Agent, or FirmHane, Baxley &amp; Spiecens [75] Inventor: Goran Anders Henrik Hemdal,  
  Skarholmen, Sweden [57] ABSTRACT An electronic selector for the exchange of PAM or [73] Asslgnee&#39; gf g z ggfi g$ggg M Encsson PCM coded information without blocking is disclosed in which the number of outlets of the selector is equal [22] Filed: May 11, 1973 to the number of inlets. Between each of the inlets and the outlets of the selector, an analog shift register is [21] Appl&#39; connected which for each pair of inlets and outlets comprises a first and a second stage. Each first stage is [30] Foreign Application Priority Data controlled by a selector inlet control unit which cycli- May 30. I972 Sweden 7056/72 Cally and sequentially activates the first stages, 80 that each PAM or PCM unit of information appearing on I52] US. CI- 340/166, 340/168 SR an inlet is stored in the first stage. The selector also 1 1] Int. Cl. H04 3/00 contains a selector outlet control unit which n dep rr 8] Field of Search 340/166 R, I47 C, 168 SR; dence on a marker, cyclically activates a predeter- 179 3 233 1505 mined one of the second stages, so that the informa tion stored in the first stage is transferred to the prede- [56] References Cit d termined second stage and thereby to the desired out- UNITED STATES PATENTS M of the selector- 3694580 M972 Inosc .r 340/!66 X 6 Claims, 2 Drawing Figures SHIFT 0 sum REG. REG 0;  
 sure sucr SHIFI BIZ sm B22 REG. 01 STAGE SHIFT MARKER I&#39;llllI 13. &#34;II 1 0F 2 JiOgOZ smgr smc SHIFT 512 STAGE smrr  REG STAGE I G/n DECODER Z CLOCK PULSE PHASEC REGiSTER RESISTER BINARY COUNTER DECODER Y 7 CLOCK PULSE PHASE B AVKI  X 7 CLOCK PULSE PHASE A ELECTRONIC SELECTOR HAVING A NUMBER OF INLET AND AN EQUAL NUMBER OF OUTLETS FOR EXCHANGE OF ANALOG OR DIGITAL SIGNALS BACKGROUND OF THE INVENTION The present invention relates to an electronic selector having a number of inlets and an preferably equal number of outlets for the exchange or switching of analog or digital signals such as pulse amplitude modulated (PAM) or pulse code modulated (PCM) signals.  
  Within the telecommunication technique, electronic selectors are more and more being used instead of utilizing mechanical switching elements. The electronic utilize devices such as transistors. flip-flop circuits, gate circuits and integrated design of these devices because of the still more increasing need of high-speed selectors. The present invention relates to a selector of the kind in which a shift register known per se for analog or digital signals is used.  
  In. for example, the article Analog-Speicherkette: Eine neuartige Schaltung zum Speichern und Verzogern von Signalen in the journal Electronics Letters&#34; Dec. 1967, Vol. 3, No. l2 a shift register for analog signals is described. It consists ofa number of shift register stages containing transistors. There is fed to all stages simultaneously stepping pulses so that the analog information, which is stored in one stage, is fed to the following stage in response to such stepping pulse.  
  By means of a register of the above mentioned kind which has been applied to an electronic selector according to the gist of the present invention, the longtime desire for such selectors can be met. The object of the present invention is an electronic selector, which can transfer analog as well as digital signals from a number of inlets to an equal number of outlets without blocking, by means of inexpensive, simple and highspeed switching elements.  
 BRIEF DESCRIPTION OF THE DRAWINGS The invention. the characteristics of which appear from the appended claims. will be described more in detail by means of the accompanying drawings, in which FIG. 1 shows a circuit diagram for an electronic selector according to the present invention,  
  FIG. 2 shows a timing diagram for certain control pulses which are supplied to the selector according to FIG. 1.  
 DESCRIPTION OF THE PREFERRED EMBODIMENT The selector according to FIG. 1 has a number of n inlets lI-ln and an equal number of outlets l-0n. It is now assumed that a number of pulse amplitude modulated time division multiplex signals are to be transferred by the selector from each of the inlets ll-In to a predetermined one of the outlets 01-0&#34;. The signals have been sampled in a manner known per se so that they consist of voltage pulses whose amplitudes correspond to the instaneous amplitude of the signal in the sampling time. These voltage pulses are fed consecutively to the inlets ll-ln. Each of the inlets Il-ln is connected to a corresponding outlet (II-0n through an analog shift register consisting of two stages BII, B21, B12, B22 and soon. For example, the analog shift registcr comprising stages Bll and B12 connect inlet I1 to outlet 01. As it appears from FIG. 1 the junction points between the first and the second stages are connected together to a common connection point 0.  
  According to the principle of the known shift register. shift pulses are to be delivered to the shift register stages, so that a signal supplied to one of the inlets ll-ln can be transferred to a specific outlet 01-011. In order to achieve this, the first shift register stages 811 to Bln are connected via the opening control gates GII-Gln, respectively, to an inlet control unit comprising a decoder AVKI and a binary counter BR. The counter BR is stepped forward by clock pulses on its inlet X. The outlet signals from the counter are fed from the decoder AVKI to the opening control gates GIl-Gln. The opening state of of the gates is controlled by clock pulses on a common inlet Y. The clock pulses on the inlet X are shown in FIG. 2, line a. These pulses step the counter BR forward and consequently the decoder AVKI, as is indicated on line d. On line b the clock pulses on the inlet Y are indicated. Within the time interval between two clock pulses on the inlet X, which step the binary counter BR, a clock pulse according to FIG. 2, line I), should appear. Such clock pulse as an opening pulse is fed to the gates GIl-Gln, so that shift pulses could be delivered from the decoder AVKl to the first stage in the respective analog shift register. Within the same interval, when the clock pulses ac cording to FIG. 2, line b, have ceased, also clock pulses according to FIG. 2, line c, should appear at an inlet Z of the opening gates to an outlet control unit as it will be further described below. The decoder AVK] consists. for example, ofa binary-to-decimal converter, the activation of a certain binary state of the outlets l-m of the binary counter BR causing an outlet conductor of the decoder having the corresponding decimal order number 1-11 to be selected and activated. The number of outlets from the binary counter BR is assumed to be equal to m and the number of outlets of the decoder AVKl is assumed to be equal to the number of inlets and outlets of the selector. For each clock signal fed to the inlet X the outlets of the counter BR thus are activated. 2&#34; different numbers being obtained before the counter is again reset to zero and the process is repeated. In other words, counter BR is a binary counter which counts modulo 2&#39;. Simultaneously with the stepping of the counter BR, the outlet conductors l-n of the decoder AVKI are selected and for each opening control pulse at the inlet Y, one of the gates GIl-Gln will transfer a shift pulse through to associated first shift register stage Bil-Bln, If an analog shift register of such a known type is used, in which for the stepping of a unit of information two pulses with opposite polarity must be fed simultaneously to the shift register stages, the shift pulse can be fed directly as well as via an inverting circuit.  
  In order that the sampling pulses which are shifted from the inlets II-ln to the outlets of the respective shift register stage Bll-Bln should be transferred through the selector to the intended one of the outlets Ill-0n, an outlet control unit is arranged which controls the shift register stages 821-8212. This unit contains registers llRl-llRn. each of which is associated with one of the inlets. Each register stores in the form ofa binary word the address of which of the shift register stages B21- 82): is to receive the unit of information to be transferred within a decoder period during which such information has been received by to the first stage in the analog shift registers. The recording of the addresses in the registers ORI-()Rn takes place in a manner known per se from a marker M. Each of the addresses in the registers ORI-0R are fed via one of the sets of AND- gate GI I-Glm. G2l-G2m, GnI-Gnm to the m inlets of a decoder AVKZ. Decoder AVKZ is similar to the decoder AVKl and converts the binary words representing the addresses at the inlets l-m to a decimal number, so that one of its outlets l-n will be activated. One inlet of each of the opening gates is connected to the outlets of the decoder AVKZ and the other inlet of the opening gates is connected to a common inlet Z. Open pulses according to FIG. 2. line I. are fed common in Z the analog information from the first shift reg ister stages is shifted to desired selector outlet after the information has been stored in the first shift register stage and within one and the same decoder period.  
  As it appears from FIG. 2 an opening pulse according to FIG. 2, line b, to an inlet control unit should have ceased before an opening pulse according to FIG. 2, line t. arrives to the outlet control unit. Hence the crosstalk arising from the residual charges which are obtained in the shift register stages in a selector to which PAM signals are fed and in which a shift register stage connected to the inlet is activated at the same time as the activation of the shift register stage which is connected to the intended outlet is avoided.  
  Thus by means of the binary counter BR and the decoder AVKl each of the inlets ll-ln in the selector is selected consecutively. The transfer ofthe value. which will thereby be stored in the respective shift register stages Bl l-Bla and which represents a sampled value of a pulse amplitude modulated signal (or a digital value of a pulse code modulated signal). occurs by means of the analog shift registers between the inlets and the outlets of whose selector. the registers operate according to the principle of the known analog shift register.  
  Thus the operation of the selector can briefly be summed up as follows. The incoming pulses at the inlet X step the counter BR forward and the pulses at the inlets Y and Z open the gates Gll-Gln and the gates G01- Glln. respectively. within the same decoder period as it has been described above. Starting from the zero position ofthe counter BR. first the outlet 1 of the decoder AYKI is selected and. after that, the outlets 2. n. Thus a shift pulse to the stage Bll will appear when the inlet Y is activated and the analog information appearing on the inlet II is stored in the stage Bll.  
  Owing to the fact that one inlet of the gates Gll- Glm. Gnl-Gnm in the outlet control unit is connected to the respective outlets l-u of the decoder AVKI in the inlet control unit. when the outlet 1 of the same is activated. the gates Gl l-Glm will be opened for the signals appearing across the outlets of the register 0R1. In each one of the registers ORI-0R address information is stored for each inlet ll-ln about the outlet which is to be connected to the inlet in question. For example. assume that for an analog signal at the inlet ll. the outlet 02 is to be selected. By means of the outlet I of the decoder AVK] being selected. the corresponding register ORI is selected. and the binary information then at the gates GI l-Glm is fed to the decoder AVKZ. This activates therewith one of its n outlets. more specific, the outlet 2 according to the example. When a pulse at the inlet Z appears. the gate G02 is opened and a shift pulse is delivered to the stage B22.  
 which will thereby shift the analog signal stored in the shift register stage B1] to the outlet 02. Thus the incoming analog signal to the selector is transferred from the inlet ll of the selector to its outlet 02. In a similar manner the exchange of the remaining signals on inlets l2-ln is carried out.  
  The described selector operates not only for pulse amplitude modulated signals (PAM) but also for pulse code modulated signals (PCM In the case when PCM signals are to be transferred either all the bits in the PCM code can be transferred in series across one single selector or there could be connected in parallel so many selectors as there are bits in a PCM word. for example 8, and transfer will be in parallel. The size of the selector is limited by the used maximal shift frequency and by the selected sampling frequency in the pulse code modulation.  
 I claim:  
  I. An electronic selector for transferring information represented by a given parameter of information pulse signal from one of a plurality of inputs to one of a plurality of outputs comprising: a first plurality of stages, each of said stages temporarily storing a pulse signal and shift register having an information signal input, an information signal output and a shift pulse input; means for connecting the information signal input of each of said shift register stages to one of the inputs of the selector. respectively; a common channel; means for com necting the information signal output of all of said shift register stages to said common first control channel; means for transmitting first shift pulses having a first phase to the shift pulse input of each of the first plural ity of shift register stages in sequence whereby each said stage accepts and stores the information pulse signal then present at its information signal input; a second plurality of shift register stages for temporarily storing a pulse signal, each having an information signal input. an information signal output and a shift pulse input; means for connecting each of the information signal inputs of said shift register stages ofsaid second plurality to said common channel; means for connecting the information signal output of each of said shift register stages of said second plurality to one of the outputs of the selector. respectively; a second control means, operating in synchronism with said first means. for transmitting second shift pulses having a second phase delayed from said first phase to each of the shift register stages of said second plurality in a given sequence whereby the shift register stage receiving a second shift pulse accepts and stores the pulse signal for the shift register stage of said first plurality which received the first shift pulse immediately preceding said second shift pulse.  
  2. The electronic selector of claim 1 wherein each of said shift register stages is an analog shift register stage.  
  3. The electronic selector of claim I wherein said first shift pulses occur cyclically and said second control means includes aa register means for storing infor mation for selecting each of the shift registers of said second plurality. read out means activated by each of said first shift pulses for extracting the information from said register means for selecting a particular shift register stage of said second plurality, and means con nected to said read out means for transferring the second shift pulse to said particular shift register stage of said second plurality.  
  4. The electronic selector of claim 3 wherein said first control means comprises a clock pulse source. a modulo-n clock pulse counter where n equals the number of shift register stages in said first plurality. first decoder means connected to said counter for converting the count being stored in said modulo-n counter to a signal on one of a plurality offirst lines. a source of said first shift pulses. a plurality of two-input AND-gates. each of said AND-gates having a first input connected to said source of said first shift pulses and a second input connected to a different one of said first lines.  
  5. The electronic selector of claim 4 wherein said register means is a plurality of registers each storing an address word indicating one of the shift register stages of said second plurality. second decoder means having a plurality of inputs for converting an address word present at the inputs to a signal on one of a plurality of second lines, means connected to each of said first lines for connecting a different one of said registers to said second decoder means. the particular register so connected being dependent on which of said first lines transmits a signal. a source of said second shift pulses, a second plurality of two-input AND-gates; each of the AND-gates of said second plurality having a first input connected to said source of said second shift pulses and a second input connected to a different one of said second lines.  
 6. The electronic selector of claim 1 wherein the number of inputs and outputs are equal.