Digital data handling system
( Apr. 22, 1975 DIGITAL DATA HANDLING SYSTEM [75] Inventor: Peter William East. Felbridge. near East Grinstead. England 3.720.952 3/l973 Lawsinc 343/l8 E 3.73.905 3/l973 Newman ct al 328/10) 3.764.999 iii/I973 Simons ct al 343/18 E [73] Assignee: U.S. Philips Corporation. New Prinmry Examiner-Maynard R. Wilbur York. NY. Assistant Examiner-Ci. E. Montone Filed: 0- l5. I973 .gl&#39;ticrzllll&#39;). Agenl. or Flrm-Frank R. Tnfart; George B. [2!] Appl. No.: 406.375  
  ABSTRACT [30) Foreign Application Priority Data A system for selectively storing parallel trains of digioci. 16, i973 U i d Ki d H 475 3 73 tal information produced in a converter from a plurality of received signals, comprises a plurality of stores [52 u.s. Cl. 343/5 or; 328/109: 343/5 SA; arranged in Parallel storing channels plurality of 343/18 E; 340M461 Comparators connected between a pair of stores and [5 l Int. Cl. GOls 9/02 beiween corresponding Outputs of the Converter I0 [58] Field of Search 343/18 E 5 5A; 5 [)P; certain coincidence between received and stored in- 333/1091 |37 formation. counting circuits for registering each match in respective comparators. andpreference logic cir- [5 References Cited cuits for resetting all stores except the ones at which a UNITED STATES PATENTS mach 3.484.704 lZ/I969 Hungcrford 328/[37 4 Claims. 3 Drawing Figures 8 l l 1 z I I 5f0EE.$\ I F1 91 |1 -u -u i /Mwa/r Cowp- I C l LINE aware/17012 l I I I FS&#39;l Q 851 I 1 MA I I raw FM1 wear 7: BM&#39;l I F51 Java GATE I M FBCI l I R L.l A11 l FBU l I: I l/L P/ZEFEEENCE I LOG/C C/E&#39;CU/f l l DIGITAL DATA HANDLING SYSTEM The present invention relates to a digital data handling system and more particularly to a system in which a large number of digital input pulses are received and which require sorting.  
  The present invention finds particular application in the field of radar receivers in which a radar receiver. receives a large number of incoming signals from various radar stations and converts these incoming signals into digital signals representing the frequency. bearing. pulse width etc. of each particular signal received from a respective radar transmitter. In any particular application a pulse repetition frequency of l KHz and up to I sets of incoming signals can be expected. Each incoming signal is converted into approximately 35 digital bits therefore the bit repetition rate expected from the analogue to digital converter can be 3.5 megabits per second. Such a repetition rate would overload the normal computer storage techniques and therefore it is an object of the present invention to provide adequate data sorting for such a large number of incoming signals.  
  According to the present invention there is provided a digital data handling system including a plurality of store groups serving a number of channels of information, in which related signals are fed into the stores of a corresponding group. including a comparing circuit which establishes correlation between an input signal and stored data. in which when a correlation is established between a further series of input signals and the stored signals a counter is stepped forward one position. and in which preference logic is provided to ensure that a particular set of data is stored in only one store group. such that the input information is self sorting.  
  An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:  
  FIG. I shows a data storegin system incorporating the present invention.  
  FIG. 2 shows in more detail a comparator of FIG. 1 and FIG. 3 shows the preference logic used in the ar rangement of FIG. 1.  
  Referring now to FIG. I, there is shown an aerial and receiver system R which receives a large number of sig nals. Particularly the aerial and receiver system R is designed to receive and to sort signals from radar stations, either stationary or moving. The aerial is omnidirectional and receives signals at a large number of frequencies over a given range.  
  Signals from the aerial and receiver system R are fed to an analogue to digital converter AD. The output of the analogue to digital converter AD is in parallel form and may consist of several parallel channels each one of which may have several parallel outputs. In a particular example chnnels F. B. W. and H are provided each with separate parallel outputs. The digital signals on channel F may represent a measurement of frequency, the signals on channel B. a measurement of the bearing of a radar set. the signals on channel W. a measure of the width of the received pulse and the signals on channel H the height or size of the received pulse.  
  Considering firstly channel F the digital pulses are fed in parallel to a number of stores Fl FN. Similarly the pulses on channels B. W. and H. are fed to respective stores Bl to EN. WI WN and HI- HN.  
  When an input pulse from a distant radar set is received at the aerial and receiver system R the information of the frequency. bearing. pulse width. and pulse height is fed from the aerial system and associated receiver to the analogue to digital converter A-D. The frequency. bearing. pulse width and pulse height are then obtainable on the outputs of AD in a digital form. The frequency is fed in digital form in parallel to all the stores Fl FN and similarly the bearing. pulse width and pulse height are fed in digital form to the respective stores Bl BN;W1- WN and H1 HN. Hence if all the so stores Fl FN are initially empty they will then receive and store the same information i.e.. the frequency of the particular radar station detected. in digital form.  
  Referring now to FIG. 2 showing a comparing circuit for two stores in a store group. for simplicity, only two of the outputs of AD are shown. these being F and B channels representing the frequency and bearing of the received pulse from a distant radar set. Only stores F1 and B1 are shown in order to simplify the explanation. The lines F and B continue as in FIG. 1 to feed the further stores F2 FN and B2 EN. The contents of the store F1 are fed in parallel to one input of a subtractor F51. The other input of the subtractor is connected directly to the output F of the analogue to digital converter A D. The output ofthe subtractor is connected to a matching circuit FM] the output of which is fed to an AND gate F81. The output of AND gate FBI is fed to a counter FBC] and to a preference logic circuit FBLl. The input information on channel B is fed to a store B1 and also to a subtractor BSl to which also the output of the store BI is connected. The output of subtractor BSl is fed to a matching circuit BM]. the output of which is fed to a second input of AND gate FBI.  
  When a signal is received on the aerial and receiver system R and fed to the analogue to digital converter AD the digital signals are produced on the outputs. F. B, W and H. The output signal on channel F is in the form of It] parallel digits. These digits are stored in the previously empty stores Fl to FN. When the store F1 is filled the output from the store Fl provides a clock inhibit via line C] which prevents any further informa tion being stored in the store Fl until after a reset pulse is received along the reset line RL. The instantaneously stored information in store F1 is compared with itself in the subtactor FSl, the output of FSl therefore being zero. The matching circuit FMl therefore records that a match between these two signals has been obtained and provides an input to AND gate FBI. Similarly the data on channel B is stored in store B1 and compared with itself in subtractor BS1, matching circuit BM] providing a second input to AND gate FBI. Therefore AND gate FBI provides an output which advances the counter FBCl by one position. The matching circuits FM! and BM! can be set such that an output is given when the signal stored in stores Fl or B1 is equal to any signal received along lines F and B or when any signal is received along lines F or B which is within a certain tolerance of the stored value.  
 If all the stores F] to FN were empty then they will all have stored information given by the first set of par- 3 The operation of this preference logic will be described hereinafter with reference to FIG. 3.  
  It is anticipated that numerous signals will arrive at the aerial and receiver system R and will be subse quently transferred in digital form to the stores Fl to FN. If the second signal received is of a different fre quency to the value stored in Fl the subtractor FSl will give a large output and the matching circuit FMl will not record a match. This second signal will therefore be stored in a further store for example store F2. This process will be continued until a signal is received which is of the same frequency as the value stored in store Fl. When such a signal is received the subtractor PS1 will give either a zero or a small output within the tolerance range of the matching circuit FM] and the matching circuit FMl will give an output 1 to an input of the AND gate FBI. lfthe signal has been received from the same radar station as the previous information stored in F] and B] then the bearing received on line B will also provide a match and a further input will be provided for AND gate FBI thus setting the counter FBCl forward one more position. lfthe second series ofinfor mation is also stored in a further store, for example FN. this store will be reset by the preference circuit FBLN associated with that particular store so that only one store is used to store the information. V  
  After several minutes the counters FBCI FBCN will have counts of varying numbers depending on a repetition frequency of each incoming pulse ,from the various radar transmitters. The information of frequency. bearing and pulse repetition frequency is therefore readily obtainable by reading the stores F B and FBCI in the case of the first radar transmitter and FN BN and FBCN in the case ofthe Nth radar transmitter.  
  Referring now to H6. 3 the preference logic circuits pertaining to respective store groups channels of input information are referenced FBL], FBLZ. FBL3 FBLN. Therefore circuit FBLN will serve to reset stores FN. BN. WN. and HN. The preference circuitry FBL 1 contains only an AND gate A] with three inputs All to Al3. The first input signal at All is present when there is a count of l in the counter FBCl, the second input signal at A12 is present when one of the counters in the higher numbered groups has a count of greater than 1 and the third input signal at Al3 occurs when a match has been recorded on comparator l.  
  The preference circuitry FBL 2 includes an AND gate A2 with three inputs A21, A22 and A23. lnput signal at A2] is present when there is a count of l in the counter C2; input signal at A22 is present when the OR gate OR2l gives an output and input signal at A23 is present when there is a match on comparator 2.  
  The OR gate OR 21 has two inputs, one from the Comparator 1 match signal source MI and one from the output of OR 32 in counter of a 3 which gives an output when any channel higher number than counter 2 has a count greater than I.  
  OR gate 22 has two inputs, on OR 22] the output of OR 32 and on OR 222 the output of the counter of channel 2 when the counter has a reading greater than 1. OR gate OR 22 gives an output when either counter 2 or any counter with a higher number has a count greater than I.  
  OR gate OR 23 has two inputs, OR 23] from the match signal source Ml of comparator l and OR 232 from the match signal source M2 of comparator 2. OR  
  a match.  
  The preference circuitry for FBL N includes only an AND gate AN with three inputs ANl, ANZ and AN3. lnput signal at AN] is present when there is a count of l in the counter ofC N. input signal at AN 3 is present when a match is recorded on comparator N and input signal at AN2 is received from OR (N-] )3 (not shown) in FBL N-l.  
 The preference circuitry operates as follows:  
 First case Assume all stores Fl FN, Bl BN etc are empty. When the first sets of frequency and bearing informations are received they will respectively be stored in all the stores. It is desired to store the information only in store group l and this is accomplishedas follows:  
  All store groups record match signals and have a count of l in there stores. OR gates OR 2!, OR 23, OR 31 etc. provide the third signal input M] from comparator l to AND gates A2 and A3 etc. to reset all the stores in store groups 2, 3 N. Therefore the value is stored only in store group 1 and all other store groups are reset.  
 Second case Now assume that store group 2 has recorded several matches and has a count greater than 1 in its counter. Assume that store group I has been cleared because. for example its information was redundant. also assume that store group 3 is also free to receive information i.e.. its stores are empty.  
  All three store groups will record the information. and will have match signals. Store groups I and 3 will have 1 counts in their counters. Store group 2 will not and therefore its AND gate A2 can not give an output. FBL will obtain its third input. A12 to Al from OR gate OR22 because OR 222 will have an input from the counter since the counter is greater than 1. Therefore store group 1 is reset.  
  FBL 3 will receive a third input to A3 on A32 from the match signal on store group 1 via OR 23 and OR 31 or from the store group 2 match signal via OR 31 and store group 3 will therefore be reset.  
  The following rule can be formulated for FIG. 3. A store group is reset only when a match pulse and a count of l is present and if any counter ofa lower number has any count at all recorded or when any any counter in a group of a higher number has a count greater than i. i  
  To each store a digital running averager can be attached which will continuously give the mean value of that parameter over the mean active period. This period can either be a fixed period of time or a fixed count in the counter. Therefore on read out the average value over any give period may be obtained.  
  It is useful to use this average value to up date the associated store. Thus the match circuit will record a match only when signals are received within the tolerance range each side of the running average value.  
 What is claimed is:  
  l. A digital data handling system for use in connection with receiver means adapted for receiving signals from a plurality of transmitters. comprising: means for converting the received signals into parallel output trains of binary digital information representing predetermined parameters of each signal, a plurality of groups of storing units arranged in parallel storing channels connected to respective outputs of said converting means. a plurality of comparing means each assigned to at least one pair of storing units in each group for producing an output signal when the stored digital information in each unit of said pair corresponds to information at corresponding outputs of said converting means. a plurality of counting means assigned to each comparing means and controlled by the output signal therefrom. and a plurality of preference logic circuits each assigned to a pair of storing units for producing a reset signal for said pair when a coincidence of output signals from a corresponding comparing means. from a corresponding counting means and from any of the subsequent and preceeding comparing means. occurs.  
  2. A digital data handling system as claimed in claim I wherein the comparing means includes a pair of subtractors connected between an output of said converting means and a corresponding storing unit. a pair of matching circuits for providing match signals from the output signals of said suhtractors. and an AND&#34; gate having two inputs connected to said matching circuits for producing control output signals for said counting means and for said preference logic circuits.  
  3. A digital data handling system as claimed in claim I wherein each preference logic circuit includes an AND&#34; gate having a first input connected to the output of a corresponding counting means. a second input connected to respective outputs of comparing means subsequent and preceding storing groups. a third input connected to the output of a corresponding comparing means. and an output connected to a reset line of the assigned pair of storing unit.  
  4. A digital data handling system as claimed in claim 3 wherein intermediate preference logic circuits in each store channel include respectively. three OR gates each having a first input connected to the output of comparing means in a preceeding group and a second input connected to the output of comparing means in the subsequent group. whereby the outputs of said OR gates control the inputs of said AND gates.  
  l l l