Digital automatic gain control circuit
|45] Apr. 22, 1975 United States Patent Milanes l DIGITAL AUTOMATIC GAIN CONTROL CIRCUIT BACKGROUND OF THE INVENTION This invention relates to automatic gain control circuits and more particularly to a digital automatic gain control circuit which provides a voltage which can cause rapid changes in the gain of a variable gain amplifier so that the level of output signals from the amplifier remain nearly constant even when the amplitude of the digital input signals changes suddenly.  
  In modern data processing systems data characters are stored on magnetic tape or magnetic disks for retrieval and use at a later time. ln magnetic tape recording each of the data characters is represented by a cornbination of binary ones and binary zeros which are stored along the width of the magnetic tape. When the data characters are read from the tape it is found that the amplitude of the binary ones and binary zeros may vary over a wide range. These changes in amplitude may be caused by dirt on the magnetic tape, mechanical tape flutter, wear on the magnetic head. wear of the magnetic tape, or differences in the magnetic oxide which is deposited on the tape. These variations in the signals may cause errors to be introduced into the data being read from the magnetic tape. What is needed is an automatic gain control system to prevent variations in the amplitude of the binary ones and binary zeros being read from the magnetic tape.  
  Several prior art automatic gain control circuits have been developed which vary the gain of an amplifier to partially correct for the differences in amplitudes of the binary signals being read from the tape. These&#39; prior art automatic gain control circuits work fairly well when the signals from the magnetic tape vary in amplitude at a slow rate. However` the circuits are unable to change the gain of the amplifier quickly, so that any sudden decrease in amplitude of the signals being read from the magnetic tape may cause some of the binary signals to be completely lost by the detector circuit in the tape subsystem.  
  The present invention alleviates some of the disadvantages of the prior art automatic gain control circuits by checking the amplitude of each of the binary signals being read from the magnetic tape and by increasing the gain of an amplifier in the circuit when the amplitude of these binary signals decreases. This rapid change in the gain of the amplifier prevents loss of binary signals being read from the magnetic tape even when the level of the signals suddenly changes.  
  lt is. therefore, an object of this invention to provide a new and improved digital automatic gain control circuit.  
  Another object of this invention is to provide an automatic gain control circuit having increased speed of response over the prior art circuits.  
  A further object of this invention is to use digital circuits to provide automatic gain control.  
  Still another object of this invention is to provide an improved automatic gain control circuit which is useful with a variety of types of signals.  
 SUMMARY OF THE INVENTION The foregoing objects are achieved in the instant in vention by providing a pulse automatic gain control circuit having a pulse-to-analog converter which provides a voltage which can cause rapid changes in the gain of a variable gain amplifier so that the level of output signals from the amplifier remains nearly constant even when the amplitude of the digital input signals changes suddenly.  
 Other objects and advantages of this invention will 5 become apparent from the following description when taken in connection with the accompanying drawings.  
 BRIEF DESCRIPTION OF THE DRAWINGS FIG. l is a diagram of one embodiment of the instant invention; and  
  FIG. 2 illustrates waveforms which are useful in explaining the operation of the invention shown in FIG. l.  
 DESCRIPTION OF THE PREFERRED EMBODIMENT The digital automatic gain control circuit of FIG. l includes a pair of amplifiers ll and 12, a peak detector 14, an emitter follower 15, a pair of threshold detectors I7 and 18, and a pulse-to-analog converter which includes a pair of .IK flip-flops 2l and 22, inverters 52 and 53 and summing circuit 24. The input signal is applied to the signal input terminal 26 where it is amplified by the variable gain amplifier l1 and by amplifier 12 and applied to the output terminal 30. The variable gain amplifier ll may be one of several types which are available from several manufacturers. One variable gain magnifier which may be used is the A795 which is a multiplier or a variable gain amplifier. The voltages on input leads 9 and 4 are multiplied to give the output signal on the output lead. The gain of the amplifier ll is controlled by the amplitude of the voltage on input lead 4. As the voltage on the input lead 4 becomes more positive the gain of amplifier 11 increases. Conversely. as the voltage on the input lead 4 of amplifier Il becomes less positive the gain of the amplifier decreases. The circuit of the A795 is more fully described in the booklet Fairchild Linear Integrated Circuits Data Catalog&#34;` November |97 l by Fairchild Semiconductor` Mountain View, Calif. Amplifier 12 is a commonly used type of direct-coupled amplifier employing transistors 73, 74 and 75.  
  The output signal from terminal 30 is coupled to the input leads of the peak detector 14 and to the emitter follower I5. The emitter follower l5 provides isolation between the output terminal 30 and the input leads of the threshold detectors 17 and I8. The detectors 14, I7 and I8 each include a differential voltage comparator having reference numerals 40. 48 and 49 respectively. When the voltage on the positive lead of a comparator is less than the voltage on the negative lead the compar ator develops a low value of output voltage on the output lead. When the voltage on the positive lead is greater than the voltage on the negative lead the comparator provides a positive value of voltage at the output lead. A comparator which may be used is the A710 which is available from several manufacturers. Details of the operation of the A710 may be found in the &#34;Fairchild Linear Integrated Circuits Data Catalog&#34;, November l97l, by the Fairchild Semiconductor. Mountain View` Calif. The peak detector I4 includes a first differentiator and phase shift circuit 37, a zero crossing detector 38, a second differentiator 4l and an open collector inverter 46. Resistor 32, capacitor 33, resistor 3S and capacitor 36 of differentiator 37 form a filter circuit to reject noise.  
  The operation of the circuit of FIG. l will now be described in connection with the waveforms shown in FIG. 2. The voltage waveform A of FlG. l is applied to the input terminal 26 and is amplified by amplifiers l1 and l2 and provided to the output terminal 30 as waveform B. lt should be noted that the amplitude of waveform A varies over a wide range while the waveform B has a fairly constant amplitude. The signal of waveform B is applied to the input lead of the peak detector 14 where the phase is shifted approximately 90 degrees by the resistor 35 and capacitor 33 and applied to the upper input lead of amplifier 39. The amplified and phase shifted voltage of waveform C is applied to the positive input lead of the differential voltage comparator or differential amplifier 40. At the time the voltage of waveform C crosses the zero axis the voltage at the output lead of the differential voltage comparator 40 becomes a positive value as shown in waveform D. The voltage of waveform D is differentiated by capacitor 44 and resistor 45 and applied to the input lead of the open collector inverter 46. The open collector inverter 46 eliminates the negative pulses which are developed across resistor 45 and provides negative going trigger pulses to the C input leads of the .IK flip-flops 21 and 22 in response to positive going pulses. An inverter provides a logical operation of inversion for an input signal applied thereto. The inverter provides a high positive output signal representing a binary one when the input signal applied thereto has a low value, representing a binary zero, Conversely` the inverter provides an output signal representing a binary zero when the input signal represents a binary one. Such an inverter is shown in FIG. l and represented by the reference numerals 52 and 53. The inverter 46 which is marked with an asterisk is an open collector inverter which provides a low output voltage in response to a high input voltage; however, a low value of input voltage causes the open collector inverter to be an open circuit.  
  The .IK flip-flops 2l and 22 are circuits adapted to operate in either one of two stable states and to transfer from the state in which they are operating to the other stable state upon the application of a trigger signal thereto. ln one state of operation the .IK flip-flop represents a binary one l-state) and in the other state it represents a binary zero (O-state). The three leads entering the left-hand side of the flip-flop symbol, for example` flip-flop 2l, provide the required trigger signals. The upper lead, the J lead, provides the set signal, the lower lead, the K lead` provides the reset sighal and the center lead provides the trigger signal. When the set input signal on the J lead is positive, and the reset signal on the l( lead is positive, a negative trigger signal on the C lead causes the flip-flop to change to the l-state, if it is not already in the l-state. When the reset signal has a low value and the set signal has a low value, a negative trigger signal causes the flip-flop to transfer to the O-state if it is not already in the O-state. The O output lead leaving the right-hand side of the flip-flop delivers a one output signal of the flip-flop.  
  The biasing circuit 25 provides a bias voltage to the differential comparators 48 and 49 so that comparator 48 provides a positive value of output voltage when the signal applied to the positive input lead has a level greater than the level 2 shown in waveform G of FIG. 2. The differential voltage comparator 49 is biased so that comparator 49 provides a positive value of output voltage when the input voltage at waveform G is greater than the level l shown in waveform G. When the level is less than level l neither comparator 48 nor 49 provide a positive value of output voltage.  
  The operation of the automatic gain control circuit will now be described with three different levels of signals at waveform G. The first signal level discussed will be a signal having an amplitude greater than level 2 at the input leads of comparators 48 and 49. The operation of the automatic gain control circuit will then be discussed using a signal which is between levels l and 2 as shown in waveform G. The third amplitude of signal will be a signal having a value less than level l shown in waveform G.  
  When the signal shown in waveform G has a value greater than level 2 comparator 48 provides a positive signal to the .l and K input leads of flip-flop 2l at the same time that a negative pulse is applied to the C lead of flip-flop 21 thereby causing flip-flop 2l to be set so that the Q output lead of flip-flop 2l provides a high value of output voltage. The high value of output voltage on the Q output lead of flip-flop 21 is inverted by inverter 52 to provide a low value of input voltage on input lead 77 to the summing circuit 24. This low value of input voltage on input lead 77 causes diode 60 to be back biased so that no current flows through diode 6l. At this time the only charge on capacitor 63 is due to a current flowing from the +12 volt source through resistor 57 and 58 to ground. The voltage divider comprising resistors 57 and 58 provides a low value of positive voltage on output lead thereby causing the gain of the variable gain amplifier ll to be low.  
  When the input signal to the variable gain amplifier ll decreases the voltage at the output terminal 30 of amplifier 12 decreases slightly. When this voltage at the output terminal 30 causes the input voltage of waveform G to have a value between level l and level 2 the signal on the positive input lead of comparator 48 is low causing comparator 48 to provide a low value of voltage to input leads .l and K of flip-flop 2l at the time the negative trigger pulse is applied to the C input lead. This causes flip-flop 2l to be reset so that the voltage on the Q output lead of flip-flop 21 is low. The low value of voltage is inverted by inverter 52 to provide a high value of voltage to input lead 77 of summing circuit 24. This high value of voltage on lead 77 causes diode 60 to conduct and to provide a higher positive value of voltage on output lead 80 of summing circuit 24. This positive voltage on lead 80 causes the gain of amplifier 11 to increase and to increase the amplitude of waveform B.  
  When the amplitude of waveform G decreases below level l the signal on the positive input leads of comparators 48 and 49 is low causing comparators 48 and 49 to provide a low value of voltage to the .l and l( input leads of flip-flops 2l and 22 at the time that the negative pulse is applied to the C input lead. This causes flip-flops 2l and 22 to be reset so that the voltage on the Q output lead of flip-flops 21 and 22 is relatively low. The low value of voltage on the Q output lead of flip-flops 21 and 22 is inverted by inverters 52 and 53 respectively to provide a high value of positive voltage to input leads 77 and 78 of summing circuit 24. The positive voltages on input leads 77 and 78 cause diode 60 and 6l to be rendered conductive so that a current flows through diode 60 and 6l to provide a higher value of positive voltage across capacitor 62. This higher value of voltage across capacitor 63 provides a higher positive voltage on lead 80 and causes the gain of the variable gain amplifier ll to be increased so that the signal on the output terminal 30 is almost as large as it was when the input signal on terminal 26 was larger.  
  When capacitor 63 is made relatively small the voltage across capacitor 63 can be changed at a rapid rate so that even one low value of pulse to the input leads of comparators 48 and 49 causes an increase in the voltage across capacitor 63 and causes a gain of&#39; the variable gain amplifier ll to be increased so that the next pulse is not lost. lf it is desired to have a smoother control other comparators and other flip-flops can be added to the circuit shown in FIG. l. This also requires that more diodes and more resistors be connected between the upper plate of capacitor 63 and the +12 volt terminal of the summing circuit 24.  
  While the principles of the invention have now been made clear in an illustrative embodiment, there will be many obvious modifications of the structure, proportions, materials and components without departing from those principles. The appended claims are intended to cover any such modifications.  
 What is claimed is:  
  l. A digital automatic gain control circuit for use with a source of signals, said circuit comprising:  
 a variable gain amplifier having first and second input leads and an output lead, the gain of said amplifier being determined by the amplitude of voltage applied to said second input lead, said first input lead of said amplifier being coupled to said source of signals;  
 a peak detector having an input lead and an output lead, said input lead of said peak detector being coupled to said output lead of said amplifier;  
 a first threshold detector having an input lead and an output lead, said input lead of said first threshold detector being coupled to said output lead of said amplifier. the amplitude of voltage from said threshold detector being determined by the amplitude of a signal from said amplifier;  
 a first flip-flop having first, second and third input leads and an output lead, said first and said third input leads of said first flip-flop being connected to said output lead of said first threshold detector, said second input lead of said first flip-flop being connected to said output lead of said peak detector` the voltage from said output lead of said flipflop being determined by the amplitude of voltage applied to said first and said third input leads of said first flip-flop; and  
 a summing circuit, said summing circuit being connected between said output lead of said first flipflop and said second input lead of said amplifier, the voltage which said summing circuit provides to said second input lead of said amplifier being determined by the value of voltage from the output lead of said flip-flop.  
 2. A digital automatic gain control circuit as defined in claim l including:  
 a second threshold detector having an input lead and an output lead, said input lead of said second threshold detector being coupled to said output lead of said amplifier; and  
 a second flip-flop having first, second and third input leads and an output lead, said first and said third input leads of said second flip-flop being connected to said output lead of said second threshold detector, said second input lead of said second flip-flop being connected to said output lead of said peak detector, said output lead of said second fiip-flop being coupled to said summing circuit.  
 3. A digital automatic gains control circuit for use with a source of signals, said circuit comprising:  
 a variable gain amplifier and first and second input leads and an output lead, said first input lead of said amplifier being coupled to said source of signals the gain of said amplifier being determined by the amplitude of voltage applied to said second input lead;  
 a phase shift circuit having an input lead and an output lead. said input lead of said phase circuit being coupled to said output lead of said amplifier&#39;,  
 a zero crossing detector having an input lead and an output lead, said input lead of said zero crossing detector being connected to said output lead of said phase shift circuit;  
 a differentiator having an input lead and an output lead, said input lead of said differentiator being coupled to said output lead of said zero crossing detector;  
 a first threshold detector having an input lead and an output lead, said input lead of said threshold detector being coupled to said output lead of said amplifier, the amplitude of voltage from said threshold detector being determined by the amplitude of a signal from said amplifier;  
 a first threshold detector having first, second and third input leads and an output lead, said first and said third input leads of said flip-flop being connected to said output lead of said first threshold detector, said second input lead of said first flip-flop being coupled to said output lead of said differentiator, the voltage from said output lead of said flipflop being determined by the amplitude of voltage applied to said first and said third input leads of said first flip-flop; and  
 a summing circuit, said summing circuit being connected between said output lead of said first flipflop and said second input lead of said amplifier, the voltage which said summing circuit provides to said second input lead of said amplifier being determined by the value of voltage from the output lead of said flip-flop.  
 4. A digital automatic gain control circuit as defined in claim 3 including:  
 an open collector inverter having an input lead and an loutput lead, said input lead of said inverter being connected to said output lead of said differentiator, said output lead of said inverter being connected to said second input lead of said first flip-flop.  
 5. A digital automatic gain control circuit as defined in claim 3, including:  
 a second threshold detector having an input lead and an output lead, said input lead of said second threshold detector being coupled to said output lead of said amplifier; and  
 a second flip-flop having first, second and third input leads and an output lead, said first and said third input leads of said second flip-flop being connected to said output lead of said second threshold detector, said second input lead of said second flip-flop being coupled to said output lead of said differentiator, said output lead of said second flip-flop being lead of said amplifier; and coupled to said summing circuit. a second flip-flop having first, second and third input 6. A digital automatic gain control circuit as defined leads and an output lead, said first and said third in claim 3 including: input leads of said second flip-flop being connected an open collector inverter having an input lead and 5 to said output lead of said second threshold detecan output lead` said input lead of said inverter tor, said second input lead of said first and said secbeing connected to said output lead of said differond Hip-flops each being connected to said output entiator; lead of said inverter, said output lead of said seca second threshold detector having an input lead and ond flip-op being coupled to said summing ciran output lead, said input lead of said second l0 cuitA threshold detector being coupled to said output