Apparatus for improving the shape of characters formed by a row and column coordinate matrix for display on a cathode-ray tube
DISPLAY ON A CATHODE-RAY TUBE John Elmer Gilliam, Carshalton Beeches, England US. Philips Corporation, New York, N.Y.  
 Filed: July 10, 1972 Appl. N0.: 270,280  
 lnventor:  
 [73] Assignee:  
 [30] Foreign Application Priority Data July 30, 1971 United Kingdom 36054/71 References Cited UNITED STATES PATENTS 1/1969 Clark 340/324 AD READ- ONLY MEMORYZ CLOCK PULSES PARA LE. TO SERIAL (EONVERTER l Q United States Patent 1191 1111 3,878,536  
 &#39; Gilliam Apr. 15, 1975 APPARATUS FOR IMPROVING THE SHAPE 3.573.789 4/1971 Sharp et a1. 340/32&#39;4 AD or CHARACTERS FORMED BY A ROW 3223-23; 3113;; w v 1 a $011 6 a AND COLUMN COORDINATE MATRIX FOR 3,697,976 10/1972 Fenton 315/22 Primary E.\-aminerlohn W. Caldwell Assistant ExaminerMarshall M. Curtis Attorney, Agent, or FirmFra1nk R. Trifari [57] ABSTRACT An addressing circuit arrangement for character display apparatus in which the characters are composed in a matrix form. When doubling the character height extra elements are added on either side of the character so as to improve its shape resulting in a roundingoff effect. To this end the addressing circuit arrangement is formed with shift registers, bistable circuits and gates which jointly supply write-early and writelate signals.  
 5 Claims, 7 Drawing Figures CLOCK PULSE ROM PSC  
 BISTABLE l DEVICES BISTABLE DEV)CES CU&#34; &#39;cunson C P QLOCK PULSE PATENTEU 3 878 536 snmmfs Fig.1  
 Fig.2  
 PATENTEDAPR 1 5 I975 sum 2 9g 3 Fig.3c  
 Fig.3b  
 PATENTEDAPR 1 5191s saw 3 9 3 READ-ONLY MEMORY PSC CLOCK PULSE l M I PARALLEL T0 SERIAL CONVERTERSR1 lglgT lgL E I CP SHIFT REGISTERS;  
  l CP GATE CU &#39;-C7UR$OR G E G1 R &#39;3&#39; J l GATE 5 E A i 2 L GATE  I E Gaga; P 1 BS1 BS 2 G g E C A F B l q T GATE CP QLOCK PULSE CLOCK PULSE Fig. 4  
 GATE  
 CRT  
 APPARATUS FOR IMPROVING THE SHAPE OF CHARACTERS FORMED BY A ROW AND COLUMN COORDINATE MATRIX lFOR DISPLAY ON A CATIIODE-RAY TUBE This invention relates to circuit arrangements for use in character display systems in which the character format is formed by a row and column coordinate matrix and characters to be displayed are built up row-by-row from discrete character elements which are identified within the matrix by character generating data, with each row of character elements being written onto a display screen once in one line scan or twice in succes sive line scans of the system.  
  It is known to use in such an addressing circuit arrangement a read-only&#34; memory device which is responsive to input data, pertaining to characters to be displayed, to produce character generating data which modulates a video signal of the system to effect the character display. Typically, a character format can be a coordinate matrix composed of 35 discrete elements arranged in 7 rows and columns, this format being derived from a read-only&#34; memory device which gives 35 bits of information in 7 rows and 5 columns, one row at a time. With such a device character generating data pertaining to 64 different characters can be produced selectively in response to appropriate input data. Since the character generating data is required to modulate a video signal, it is produced serially (as 1&#39;s and Us) by using a parallel-to-serial convertor to convert each row of 7 bits of data read out from the read-only memory device into serial form. Also, in order to effect character display on a C.R.T screen using standard line and frame scans, the logic of the addressing circuit arrangement would be so organized that for each line of characters to be displayed, the characters would be built-up row-by-row, as a whole, and the lines of characters built-up in succession. Thus, it would take 7 sweep lines of the C.R.T. beam to build-up one line of characters. In the first sweep line, input data to the read-only memory device would cause it to produce character generating data in respect of the first row of discrete ele&#39; ments for the first character, than in respect of the first row of discrete elements for the second character, and so on for each character. In the second line sweep, character generating data in respect of the second row of discrete elements for each character would be produced in turn, and so on for the remaining sweep lines.  
  The width of the characters displayed in the above fashion will be determined by the lengths of the discrete elements. This width can be varied without affecting the standard line and frame scans for the C.R.T. screen, The height of the displayed characters will be determined by the line spacing of the C.R.T. screen, so that the height cannot be varied, using 7 sweep lines as aforesaid, unless the line spacing is varied. However, it is possible to double the character height by so arrang ing the logic of the addressing circuit arrangement that each row of character elements is repeated once in the next successive line scan. Unfortuantely, with this double scan method of increasing the character height the shape of the displayed characters is degraded.  
  lt is an object of the present invention to provide a means for improving the shape of displayed characters which are generated using this double scan method.  
  A circuit arrangement according to the invention is characterized in that when the successive line scans occur the circuit arrangement is responsive in respect of each character element, just prior to it being written, to cause that character element when it is written to be lengthened so as to extend into the adjacent element position at one or each side of its own element position when another character element is written in the corresponding adjacent element position in the adjacent preceding character element row or will be written in the corresponding adjacent element position in the adjacent succeeding character element row, but not when another character element is written or will be written, as the case may be, in the element position corresponding to that of the character element concerned in either of the adjacent character element rows and not when a character element is written or will be written in the adjacent element position into which the character element concerned would otherwise extend when lengthened The effect of a circuit arrangement according to the invention is to roundcff character shapes to improve their appearance as displayed on a C.R.T. screen. Suitably, a C.R.T. system embodying the invention can be arranged to increase a character element length by a half in reponse to a command from the circuit arrangement to lengthen the character element. When the character element is to extend into the adjacent element position to the left of its own position the command would be a write early command, whereas when the character element is to extend into the adjacent element position to the right of its own position the command would be a write late command, If the character element is to extend into both adjacent element positions then both commands would be given by the circuit arrangement, and the character element length, as written, would be twice its normal length. It has been found that a normal character element length which is twice the character element height can be used to form characters whose appearance will be improved by the rounding-off facility which a circuit arrangement according to the invention provides.  
  In carrying out the invention the circuit arrangement can be arranged to store the character generating data in respect of each character element position at a time just prior to that position being the next reached by the line scan, and also to store at this time the character generating data in respect of the eight character element positions that are immediately adjacent that element position, that is, the adjacent element positions in the same character element row on each side of it, the character element positions corresponding to it in the adjacent preceding row and adjacent succeeding the row, and the character element positions adjacent these corresponding element positions on each side of them, the circuit arrangement being responsive to determine from this stored data whether a character element to be written into this next character element position is to be written early or written late, or both, to lengthen it. To this end the circuit arrangement can comprise a first set of three cascase-connected bistable devices of which the middle device stores the character generating data in respect of said next character element position, the input device stores the character generating data in respect of the adjacent character element position to the right of said next position and the output device stores the character generating data in respect of the adjacent character element position to the left of said next position, a second set of three cascade-connected bistable devices for storing the character generating data in respect of the three corresponding character element positions in the adjacent preceding character element row and a third set of three cascade-connected bistable devices for storing the character generating data in respect of the three corresponding character element positions in the adjacent succeeding character element row, together with input means for feeding synchronously to each set of the bistable devices the serially produced character generating data for the whole of the respective character element row at a clock rate which is synchronized-with the live scan, first gating means responsive in each clock pulse period for producing a write-early command signal in respect of said next character element position when the conditions of the middle and output devices of the first and second sets or of the middle and output devices of the first and third sets, as the case may be, signify the write-early condition to said first gating means, and second gating means responsive in each clock pulse period for producing a write-late command signal in respect of said character element position when the conditions of the middle and input devices of the first and second sets or of the middle and input devices of the first and third sets. as the case may be, signify the write-late condition to said second gating means. the circuit arrangement further comprising output means for extracting the character generating data in respect of said next character position from the output device of said first set so that this data is available for utilisation one clock pulse period after the clock pulse period at which a write-early and/or a write-late command signal could have been produced in respect of an element to be written into this character position, and delay means for delaying by two clock pulse periods the write-late command signal, if produced. so that this signal becomes available after the writing of the element in said position.  
  Conveniently, said first and second gating means are gated either by each clock pulse or by its complement so that the write-early and write-late command signals persist for one half a clock pulse period whereby each can be utilised to lengthen a character element by one half.  
  Preferably, said input means of the circuit arrangement comprises a parallel-to-serial convertor which is adapted to convert character generating data received from a read-only memory device into serial form and to apply this data continually to the input device of said third set of bistable devices at the clock pulse rate, this data being also fed from the output of the convertor to the input of a first shift register which has a capacity sufficient to store the complete data for a whole character element row, this first shift register being also clocked at the clock pulse rate to produce a data output which lags the data output from the convertor by one complete character element row and which is applied to the input device of said first set of bistable devices and also to the input of a second shift register which likewise has a capacity sufficient to store the complete data for a whole character element row and is clocked at the clock pulse rate to produce a data output which lags the data output&#39;from the convertor by two complete character element rows and the data output from the first shift register by one complete character element row, the data output from the second shift 4 register being applied to the input device of said second set of bistable devices.  
  In further considering the nature of the invention reference will now be made by Way of example to the accompanying drawings of which:  
  FIG. 1 shows character shapes which are produced from a 7 X 5 element format using 7 sweep lines of a C.R.T. beam;  
  FIG. 2 shows character shapes which are produced from a 7 X 5 element format using 14 sweep lines of a C.R.T. beam;  
  FIG. 3 shows the rounding-of of the character shapes of FIG. 2 in conformity with the invention;  
 . FIGS. 3a, 3b and 3c illustrate the explanation of the rounding-off of the character shape A. and  
  FIG. 4 shows a block diagram of a circuit arrangement which provides a character rounding facility in accordance with the invention.  
  Referring to the drawings, the character shapes A, B and C shown in FIG. 1 can be produced from a character format composed of 35 discrete character elements arranged in 7 rows and 5 columns. These character shapes can be displayed on a C.R.T. screen in 7 sweep lines using standard line and frame scans. The character shapes A and B shown in FIG. 2 can be produced from the same character format, but in this instance each row of elements in each character is written twice so that 14 sweep lines are necessary to display these characters on a C.R.T. screen using standard line and frame scans. These latter characters are of greater width than those of FIG. 1, this being achieved by making each discrete character element longer so that the character width is more compatible with the doubled character height. However, as can be seen from FIG. 2, this doubled height degrades the character shape where the character should be rounded to give it a more pleasing appearance. Because each character element is written twice vertically it becomes possible to make some character elements larger than others to achieve a rounding effect as can be seen from the character shapes A and B shown in FIG. 3.  
  The circuit arrangement represented by the block diagram shown in FIG. 4 provides such a rounding facility. This circuit arrangement comprises a cursor CU of nine bistable devices A to I that can be considered as a runner which is continually centred on and travels with the spot on a C.R.T. screen as character elements are written onto the screen by the spot to build up a line of characters row-by-row. The cursor CU is controlled by clock pulses CP. The bistable device E is provided with character generating data in respect of each character element position just prior to the position being reached by the C.R.T. line scan and the other eight bistable devices A to D and F to I are provided with character generating data in respect of all the character element positions that are immediately adjacent that position. This character generating data is continually updated in synchronization with the C.R.T. line scan. In accordance with the character generating data which they receive, these devices A to I are set to a 1 condition when a character element is to be written into the character element position to which they currently obtain and to a 0 condition when no element is to be written in that position. These conditions of the devices A to I are then gated in accordance with the following considerations to determine whether or not the element to be written in the position to which device E currently obtains is to be lengthened when it is written onto the C.R.T. screen.  
  Consider the fragmental part of the character shape A shown in FIG. 3a. The cursor CU is shown superimposed on this part with its center (bistable device E) over the position 21 which is the position of the single element, with double width in the second (repeated) row at the apex of the character shape A. To round off the character shape it is necessary to lengthen this element p1 so that it extends into the element position to its left because of the element which will be in the position (p2 in FIG. 3) diagonally below it to the left (to which bistable device G, FIG. 3a, obtains). However, no lengthening is necessary into the position to the left (to which bistable device D obtains) if an element is already in that position. Also, lengthening would not be wanted if an element were to be written in the position immediately below (to which bistable device H obtains) the position currently being dealt with. Thus, the combination of() and l outputs D E, E, G, where the dash above the letter signifies that the corresponding bistable device is set to 0) from the bistable devices D, H, E and G signify that lengthening to the left is required for the element to be written into the element position currently being dealt with. It is also necessary in rounding-off the character shape to lengthen this ele ment so that it extends into the element position to its right. Applying the same logic as before, it will be apparent that the combination of O and l outputs (F: F, E and I) signify that lengthening to the right is required. Similarly, if an element has been written into the position (A) diagonally above and to the left of the position (E) being dealt with and no element has been written into the position (D) to the left or into the position (B) above, then the combination of 0 and l outputs (A, E, DI B) would signify that lengthening to the left is required for the element to be written into the position (E) being dealt with. Likewise if an element has been written into the position (C) diagonally above and to the right of the position (E) being dealt with and no element will be written into the position (F) to the right or has been written into the position (B) b e, then the combination ofO and l outputs (C, E, F, B) would signify that lengthening to the right is required for the element to be written into the position (E) being dealt with.  
  In the fragmental part of the character shape A shown in FIG. 3b, the cursor CU is shown superimposed on this part with its center (bistable device E) over the position p2 which is the position of the second element in the third (unrepeated) row of the character shape A. The position to which device E pertained in FIG. 3a is now covered by device C. The shaded portion at each side of this position represents the lengthening of the element therein into adjacent positions at each side of it as just described. In FIG. 3b neither of the aforesaid conditions is satisfied for lengthening to the left the element to be written into the position (E) now being dealt with because th e two possible 0 and] output combinations are (E,A, ETD) and (E, G, H, D). With regard to lengthening to the right, this is required and the element written into position (C) (P1 in FIG. 3) in conjunction with no element written into position (B) and no element to be written into position (F) p duces the O and 1 output combination (E, C, B F) which signifies this requirement.  
  In the fragmental part of the character shape A shown in FIG. 3:, the cursor CU is shown superimposed on this part with its center(bistable device E) over the position p3 which is the position of the first element in the repeated row which forms the crossbar of the character shape A. This further example of the cursor CU positioning has been given merely to illustrate that even though the element in position C is diagonally above and to the right of the element to be written into position (E), no output combination signifying the lengthening of the element to the right will be produced because of the presence of the element in position B (B output instead of]? output) and/or the pending presence of an element in position F (F output instead of Eoutput).  
  Turning now to the remainder of the circuit arrangement shown in FIG. 4, the bistable devices F, E and D comprise a first cascade-connected set. the bistable device C, B and A comprise a second cascade-connected set and the bistable devices I, H and C comprise a third cascade-connected set.  
  The outputs of the bistable devices A to I on which are produced the output combinations E, G, F, Dand E, A, D which signify lengthening to the left of a character element to be written are connected to respective AND gates G1 and G2. The outputs of these gates G1 and G2 are fed via an OR gate G3 to a further AND gate 04 which is gated with CLOCK PULSES (:F to produce a write-early command signal which is applied via a further OR gate G5 to the video stage of a C.R.T. display system. The CLOCK PULSES CF (the complement of CLOCK PULSIES CP) have a repetition rate appropriate for synchronizing the write-early command signals thus produced with the C.R.T. beam sweep. Similarly, the outputs of the bistable devices A to I on which are produced the output combinations E, I, I-I, EandF B C, E which signify the lengthening to the right of a character element to be written are connected to respective AND gates G6 and G7, the output of each of which is fed via an OR gate G8 and two bistable devices BS1 and BS2 to a further AND gate G9 where it is gated with the CLOCK PULSES CP to produce a write-late command signal which is appled via the OR gate G5 to the C.R.T. video stage. The CLOCK PULSES CP are also used to progress the character generating data through the three sets of bistable devices l, H, G: F, E, D: and C, B, A.  
  In order to prevent the write-early command signal from being produced after the point in time when it should have been, both this command signal and the write-late command signal are produced one CLOCK PULSE period (period element D in FIG. 3a) before the element concerned (E) is to be written. The writeearly command signal is then utilised in that CLOCK PULSE period of element D at the end of which period data for the element concerned (E) is clocked from device E to device D so that this data can be read out from device D in the next CLOCK PULSE period of element E and fed via the OR gate G5 to the C.R.T. video stage for utilisation. The bistable devices BS1 and BS2 are also driven by the CLOCK pulses CP so that the write-late command signal is delayed by two CLOCK PULSE periods so as to be produced in the period following the one in which the element concerned (E) was written. The write-early and write-late command signals can be gated with the actual CLOCK PULSES P or the CLOCK PULSE complement CP. In either case the duration of the bright up (i.e. the element lengthening in respect of each command signal) will be one half the normal element length, for FIG. 3a the last part of the element D and the first part of the element F, FIG. 3b shows the result. Suitably, the bistable devices A to l are D-type flip-flops type FJJl3 l The bistable device BS1 and BS2 are suitably a dual .IK flip-flop type FJJ l 2 1. Both types are available from Mullard Limited, a British Company, Abacus House, 33, Gutter Lane. London. EC. 2., England.  
  The character generating data is fed to the third set of bistable devices I, H and G from a parallel-to-serial convertor PSC which receives this data from a readonly memory device ROM. lt is assumed that in known manner, in respect of each line of characters to be displayed, the read-only memory ROM supplies in parallel the character generating data for the first row of each character in turn, then data for the second row of each character in turn, and so on, this data being converted into serial form by the convertor PSC for application to the bistable device I at the CLOCK PULSE rate. This serially-generated data is also applied to a first shift register SR1 which can store data for one whole character row, the data in the register SR1 being fed at the CLOCK PULSE rate to the input bistable device F. A second shift register SR2 receives the data output from the shift register SR1 and feeds it to the input bistable device C at the CLOCK PULSE rate. This shift register SR2 can also store data for one whole character row. The result is that data in respect of the character row being written in the current C.R.T. line scan is fed progressively into the first set of bistable devices F, E and D, data in respect of the character row written in the previous C.R.T. line scan is fed progressively into the second set of bistable devices C, B and A, and data in respect of the character row to be written in the next succeeding C.R.T. line scan is fed progressively into the third setof bistable devices I, H and G.  
 I claim:  
  1. Apparatusfor improving the shape of displayed characters for use in a character display system in which the character format is formed by a row and column coordinate matrix and characters to be displayed are built up row-by-row from discrete character ele- &#39;ments which are identified within the matrix by character generating data, said apparatus comprising writing means for writing each row of character elements onto &#39;a display screen twice in successive line scans of the system, and character lengthening means responsive in respect of each character element, just prior to it being written, for causing that character element when it is written to be lengthened so as to extend into the adjacent element position at one or each side of its own element position when another character element is written in the corresponding adjacent element position in the adjacent preceding character element row or will be written in the corresponding adjacent element position in the adjacent succeeding character element row, but not when another character element is written or will be written, as the case may be, in the element position corresponding to that of the character element concerned in either of the adjacent character element rows and not when a character element is written or will be written in the adjacent element position into which the character element concerned would otherwise extend when lengthened.  
  8 2. The apparatus of claim 1 wherein said character lengthening means comprises cursor means which is arranged to store the character generating data in respect of each character element position at a time just prior to that position being the next reached by the line scan, and also to store at the same time the character generating data in respect of the eight character element positions that are immediately adjacent that element position, namely, the adjacent element positions in the same&#39;character element row on each side of it, the character element positions corresponding to it in the adjacent preceding row and adjacent succeeding row, and the character element positions adjacent these corresponding element positions on each side of them, said character lengthening means being responsive to determine from this stored data whether a character element to be written into this next character element position is to be written early or written late, or both, to lengthen it.  
  3. The apparatus of claim 2 wherein said cursor means comprises a first set of three cascade-connected bistable devices of which the middle device stores the character generating data in respect of said next character element position, the input device stores the character generating data in respect of the adjacent character element position to the right of said next position and the output device stores the character generating data in respect of the adjacent character element position to the left of said next position, a second set of three cascade-connected bistable devices for storing the character generating data in respect of the three corresponding character element positions in the adjacent preceding character element row and a third set of three cascade-connected bistable devices for storing the character generating data in respect of the three corresponding character element positions in the adjacent succeeding character element row, said apparatus further comprising input means for feeding synchronously to each set of said bistable devices seriallyproduced character generating data for the whole of the respective character element row at a clock rate which synchronized with the line scan, first gating means responsive in each clock pulse period for producing a write-early command signal in respect of said next character element position when the conditions of the middle and output bistable devices of the first and second sets, or of the middle and output bistable devices of the first and third sets, as the case may be, sig-.  
 nify the write-early condition to said first gating means,  
 and second gating means responsive in each clock.  
 pulse period for producing a write-late command signal in respect of said character element position when the conditions of the middle and input bistable devices of the first and second sets or of the middle and input bistable devices of the first and third sets, as the case may be, signify the write-late condition to said second gating means, output means for extracting the character generating data in respect of said next character position from the output bistable device of said first set so that this data is available for utilization one clock pulse period after the clock pulse period at which a write-early and/or a write-late command signal could have been produced in respect of an element to be written into this character position, and delay means for delaying by two clock pulse periods the write-late command signal, if produced, so that this signal becomes available after the writing of the element in said position.  
  4. The apparatus of claim 3 wherein said first and second gating means are gated either by each clock pulse or by its complement so that the write-early and write-late command signals persist for one-half a clock pulse period whereby each can be utilized to lengthen a character element by one half.  
  5. The apparatus of claim 3 further comprising a read-only memory device, said input means comprising a parallel-to-serial convertor which is adapted to convert character generating data received from said readonly memory device into serial form for applying this data continually to the input bistable device of said third set of bistable devices at the clock pulse rate first and second shift registers, each having a capacity sufficient to store the complete data for a whole character element row, said data being also fed from the output of said convertor to the input of said first shift register, said first shift register being also clocked at the clock pulse rate to produce a data output which lags the data output from the convertor by one complete character element row and which is applied to the input bistable device of said first set of bistable devices and also to the input of said second shift register which is clocked at the clock pulse rate to produce a data output which lags the data output from the convertor by two com plete character element rows and the data output from the first shift register by one complete character element row. the data output from the second shift register being applied to the input bistable device of said second set of bistable devices.  
  l l l