Electrical computing system for simultaneously performing a plurality of operations on two or more operands
United States Patent 1 1 [111 3,875,392  
 Keeler, II Apr. 1, 1975 1 ELECTRICAL COMPUTING SYSTEM FOR 1571 ABSTRACT SIMULTANEOUSLY PERFORMING A PLURALITY OF OPERATIONS ON TWO OR MORE OPERANDS [761 lnventor: Miner-S. Keeler, II, 2525 Indian Trl., SE, Grand Rapids, Mich. 49506 [22] Filed: June 18, 1973 [21] Appl. No.: 371,258  
 OTHER PUBLICATIONS J. Earle et al., Exponent Differences &amp; Preshifter,&#34; IBM Tech. Disclosure Bulletin, Dec. 1966, pp. 848-849.  
 Primary ExaminerMalcolm A. Morrison Assistant Exumt&#39;nerDavid H. Malzahn Attorney, Agent, or FirmPrice, Heneveld, Huizenga &amp; Cooper so. so 25 mmaea NUMBER a+ l0.|.0l (omit o 72 E g Q10! 53 52 m as A system for performing high speed operations on two operands comprises a first series of filters, one of which corresponds to each of the possible input operands and a second series of filters also including one corresponding to each possible operand of the system. The first and second series of filters are selectively actuated by a first and second source, respectively, such that when the sources are actuated by the user to provide signals corresponding to the desired first and second operands, only the filters of the first and second series corresponding to the selected operands are actuated. A signal applied to an input terminal of the filters will be applied to output terminals thereof only when a filter has been actuated by a signal from a corresponding source. In a system with n filters in each of the series, n correlation circuits are provided, each including a pair of input terminals, one of which is coupled to a unique filter of the first series of filters, the other of which is coupled to a unique filter of the second series such that each filter of the first set is coupled to a correlation circuit coupled to a unique filter of the second set to provide an output signal from a correlation circuit which is applied to a display or output device for simultaneously providing signals representing the operations of addition, subtraction, multiplication and division or other operations of the selected operands.  
 12 Claims, 8 Drawing Figures omm we a sess wwewswaaaaa1 7 EV CORRELATOR 95 I62:  
 75 FOR 2-3 m &#34;5 I64 74 *4 16! 56 6 uses e&#39;e&#39;eeiiseeasaaaai aaeaaaaeaasae l n I! n I! n u 1/ n I; u I! I/ e MULTIPLV WITENTEU H975 3,875,392  
 SHLU 1 GF 4 J i PROVIDING IDENTIFYING CORRELATING IDENTIFYING OPERANDS OPERANDS OPERANDS OPERANDS I I IO I2 I6 l4 ORDERING [8/ OUTPUT INFORMATION 7 UTILIZING 2o ORDERED FIG I INFORMATION 9| FIG 6 4o L KEYBOARD STORAGE NUMBER 4 33 [3-34 CIRCUIT OURCE S i 35 3e 39 a I STORAGE NUMBER cIRcuIT SOURCE 2 2&#34; OPERATOR FIG 3 PATENTEB APR 1 9 SHEET 2 m g NUMBER SOURCE (0-7 NUMBER SOURCE (0-7) FILTER (0) 4 56 9 T fmwvwkmwfm l r l m l 4 A M w w n 4 5 6 7 8 m m m m w 3 6 7 8 l m m m w w 6 a w 4 R M R 81R 0 m 0 M 2 A: A A ma L. 2 2 E E R 0 MR R R w 8/ 0 O0 0 O k 0 2 CF 4r CF 9 CF 7 W 5 l 3 8 fix 8 ix )23 4 5 6 7 8 O 54 7 7 77 7 7 R( 5 6 4 8 9 EDnk. 4 4 7 4. BE 4 5 6 5 M U 5 5 5 .H \I \II NF u my a} 3 w) w w 7 3 5 8 9 FIG 2A ELECTRICAL COMPUTING SYSTEM FOR SIMULTANEOUSLY PERFORMING A PLURALITY OF OPERATIONS ON TWO OR MORE OPERANDS BACKGROUND OF THE INVENTION The present invention relates to an improved computing system and method and more particularly. to a system for simultaneously performing a plurality of operations on two or more operands.  
  Much of the time consumed in computer operation is the time consumed in the arithmetic operations within the computer. With serial arithmetic units. any operation upon two words (operands) requires a minimum of a full word time since one word must be serially shifted through the arithmetic unit. In parallel arithmetic units which are somewhat faster, some operations may be performed in a simple bit-time such as the addition of two words since the word may be shifted into the arithmetic unit in a single-bit time. When, however. different operations are to be performed on the same operators. the step must be repeated for each operation thereby greatly increasing the computation time.  
  Recently. efforts have been made to reduce the computation time by providing simultaneous computations such as multiply-add and multiply-subtract units. US. Pat. No. 3,202,805 to L. D. Amdahll. issued on Aug. 24. I965. represents one such development. Although such a system generally represents an improvement over the series arithmetic units. the system still requires several shift registers which increase the computation time of the system. as well as many components to provide additional simultaneous computation.  
 SUMMARY OF THE INVENTION The system of the present invention. however, dis cards conventional techniques employed for providing arithmetic operations between operands and employs a unique filter system for uniquely identifying selected operands and for providing simultaneous output signals representative of the various operations performed between the two operands. The computation time is greatly reduced since the time required is only the actuation of the filters which can be simultaneous. In one embodiment. this is followed by the actuation of a circuit unique to the two selected operands.  
  The method employed in providing output signals representative ofthe operands performed on two operands includes the steps of uniquely identifying each operand and actuating a circuit unique to the operands which actuates an output device representing the results or solution of the operations simultaneously performed between the operands.  
  Systems embodying the present invention include means for providing signals representing at least first and second operands. A first series of filters uniquely identifying each operand of the system is provided and is responsive to the application of signals from the providing means for developing an output signal uniquely identifying the operand identified by the signal. Additional filters are provided to uniquely identify each operand of the system and are coupled to the providing means. Circuit means are provided for interconnecting the first and additional filters such that when two signals identifying at least two operands are applied to the system. a unique pair of interconnected filters are actuated. Output means are coupled to each unique pair of filters to simultaneously provide programmed output information corresponding to one or more operations performed on the operands.  
  An object of the present invention is to provide a calculation method capable of providing simultaneous outputs representing one or more operations per formed on at least two operands.  
  Another object of the present invention is to provide a high speed calculating system.  
  A further object of the present invention is to provide a calculation circuit employing a first and a second series of interconnected number filters. each filter of which corresponds to a unique number.  
  Still a further object of the present invention is to provide an electrical circuit for simultaneously providing a plurality of output signals representing the results of a plurality of simultaneous calculations performed between two operands.  
  These and other objects of the present invention will become apparent upon reading the following description thereof together with the accompanying drawings in which:  
 BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a flow diagram in block form showing the calculation steps performed in practicing the present invention;  
  FIG. 2A is an electrical circuit diagram in block form, of a portion of one embodiment of the present invention;  
  FIG. 2B is an electrical circuit diagram in schematic form of the display portion of the embodiment of FIG. 2A and electrically interconnected to the circuit of FIG. 2A by interconnections XX;  
  FIG. 3 is an electrical circuit diagram in block form of one circuit which can be employed to generate signals representing first and second operands on which an operation is to be performed;  
  FIG. 4 is an electrical circuit diagram in schematic form illustrating one embodiment of a number source used in the present invention;  
  FIG. 5 is an electrical circuit diagram in schematic form illustrating one embodiment of a number filter employed in the present invention;  
  FIG. 6 is an electrical circuit diagram in block form of one embodiment of a correlator circuit employed in the present invention; and  
  FIG. 7 is an electrical circuit diagram in schematic and block form illustrating an alternative embodiment of the present invention.  
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. I, it is seen that the computation system embodying the invention includes the step 10 of providing signals representing first and second operands and providing first and second operand identification units I2 and 14 identifying each of the operands. Next, the signals are correlated I6 to uniquely identify both of the operands and correlation information is processed I8 during which the output inform ation is ordered to provide an output signal. The output information is then applied to and utilized by a utilization means 20.  
  The calculating system embodying the present invention is shown in detail in the remaining figures. Before discussing the structure in detail. however. it is noted that providing step 10 may include. for example. an  
 electrical keyboard providing signals representative of a number. which signals can be of any desired format such as binary. binary coded decimal or the like. These signals then actuate number sources providing signals directly used in the present system. The operand identification process steps 12 and I4 include number filters which receive the simultaneously provided number signals and concurrently uniquely identify each of the numbers. This information is correlated by circuit means which activate output means in a format suitable for either direct display such as an optical display of the resultant number or in a format which can be used to interface with further processing or control circuits such as electrical output signals.  
  Although the preferred embodiment described herein relates specifically to numerical calculations of the above discussed arithmetic functions. it is to be understood that the use of the method and system of the present invention is not so limited and can be employed. for example, to provide any of a desired number of operations simultaneously on two or more operands. For example. the system can be programmed to provide a Taylor or Fourier series expansion of the operands or La Place. or other transformations.  
  Continuing now with the description of the preferred embodiment of the system. reference is first had to FIGS. 2-6. In FIG. 2, first and second sources of operators 30 and 32. respectively. generate 3-bit digital signals. each bit having a logic l or a logic *O state which can be represented by a -ll-V electrical signal or a electrical signal respectively. In the illustrated embodiment. the sources generate unique signals for the digits -7 using a number source ofthe type shown in FIG. 4. It is understood that the 3-bit binary number sources illustrate one aspect of the present invention. it being understood that the number of bits or the coding scheme can be changed. respectively. as necessary to provide a system of any degree of complexity required for a given application.  
  The number source shown in FIG. 4 includes three output lines 31. 33 and 35 selectively coupled to voltage sources +V and l+-V by three pole single throw push button switches to provide output logic signals for the 3-bit code employed. For the number 2. for example. switch 2 will be actuated to close its contacts to provide a logic output signal of 010. When the switch for number 3 is actuated. it will provide a logic output signal of (Jl l. The switch representation ofthe number source 30. shown in FIG. 4. is for purposes of illustration only. it being understood that the mechanical switches shown will in practice be solid state devices such as transistors.  
  In practice it may be desired to provide a single keyboard which a user can employ to generate electrical signals representing the operands used by the system. An electrical circuit which can be used together with a conventional digital keyboard is shown in FIG. 3 where a keyboard 36 provides digital information to first and second storage circuits 38 and 39. respectively. for storing first and second signals. respectively. representative of desired operands.  
  To simultaneously store the first and second operand signals. a key 34 is provided on the keyboard and is actuated after the first operand has been entered on the keyboard to provide a second operand enable signal on conductor 41 which is applied to the storage circuits 38 and 39 to inactivate and activate these circuits respectively. It is noted here that circuits 38 and 39 can be of conventional design as. for example. a shift register which has enabling and disabling input terminals coupled to conductor 41 such that they will either receive and store information from the keyboard output terminal 40 or the information stored in the circuit will not be changed by the information on terminal 40.  
  In use. the operator of the keyboard will first type in the first operand which will be stored in circuit 38, then actuate key 34 to disable circuit 38 and activate storage circuit 39 which receives the subsequently inserted operand signal from output terminal 40 0f the keyboard. Storage circuits 38 and 39 are coupled to first and second number sources 30 and 32, respectively. such that once the two operands are inserted into the storage circuit and the keyboard operator actuates a clear or readout key of the keyboard, the information stored in the storage circuits is applied to number sources 30 and 32 which respond thereto to generate the 3-bit binary code information and apply it to the circuit shown in FIG. 2.  
  It is to be understood that any number of circuit systems will operate together with a conventional digital keyboard to provide the desired actuation of the number sources 30 and 32 employed with the calculating system. The circuit format shown in FIG. 3 is merely illustrative of one such system. The actuation of sources 30 and 32 by BCD or other signals from circuit 38 and 39 is conventional and not discussed in detail.  
  The calculating system shown in FIG. 2 immediately responds to the signals from the sources and representing the two operands to provide an output simultaneously displaying addition. subtraction. multiplication and division of the two numbers entered in the keyboard by the user of the system. The system includes a first series of number filters (i.e.. detector or gate circuits) 42-49 corresponding to the numbers 0-7. In a system where n represents the number of operands in the system. there will be It number filters in the first series. The number filters include control input terminals 52-59. as seen in the figure. and signal input terminals 62-69 as also seen in the figure. Each of the control input terminals 52-59 is coupled to the output terminal 30&#39; of number source 30 to receive therefrom a 3-bit binary coded signal representative of a unique operand generated by the number source. Thus. the interconnecting conductors will include at least three lines coupling terminal 30 to each of the number filters of the first series thereof. The signal input terminals 62-69 are each coupled to a supply voltage as seen in the figure.  
  In the embodiment shown in FIG. 2. for the sake of clarity. the circuit elements are shown for performing the operations of addition. subtraction. multiplication and division on the numbers 2 and 3. Thus. the detailed circuit elements for providing only this operation are shown. The number filters of the first of the first series include output terminals 72-79. as seen in the figure. for providing an output signal at one of these terminals only when the electrical signal from terminal 30&#39; ofthe number source uniquely identifies and corresponds to the number represented by the particular associated number filter. Thus. the number filters in effect couple the signal applied to input terminals 62-69 to output terminals 72-79 only when actuated by a signal from number source 30 which corresponds to that associated number filter. When an operand is entered into the systern and actuates number source 30. one and only one of the number filters will provide an output signal at its associated output terminal.  
  For the number 2. selected as the first operand of the example. a digital signal UIU. as shown in parentheses adjacent terminal 30. will be applied to all of the number filters simultaneously but only number filter 44 will provide a positive output signal (logic I at output terminal 74. The remaining number filter outputs will be at a logic low (0) level. Each output terminal of each number filter will in turn be coupled to a plurality of correlator circuits. one for each unique operator of the series. Thus. for number filter 44. output terminal 74 will be coupled to eight correlator circuits correspond ing to the combined operands -27 in the system. In the figure. terminal 74 of number filter 44 is coupled to input terminals til. 83 and 85 of correlators 8U. 82 and 84 for the operations of 22. 2&#39;3 and 24 respectively. Each of the correlators further includes an additional input control terminal (shown as 86. 87 and 88 for correlators 8U. 82 and 84 respectively) to receive a control signal from the output terminals of a second series of number filters 92-99. Before continuing with a description of the system. a brief description of one embodiment of the number filters is shown in FIG. 5  
 and now described.  
  Basically. the purpose of a number filter is to provide an output signal at an output terminal thereof only when actuated by an electrical signal corresponding to an operand uniquely identified by the particular num ber filter. Thus. the filter operates to detect a unique operand. Thus. for number filter 44. shown in FIG. 5. a positive signal will be generated at output terminal 74 thereofonly when the input terminals 64a. 64b and 64c receive a logic (I. logic l and logic 0 signal respectively. In the embodiment shown in FIG. 5, the number filter can be comprised of a series of interconnected PNP and NPN transistors having their emitter to collector current paths coupled in series. as shown. with their base terminals individually coupled to the three input conductors to receive the logic drive signals from the number source. Circuit 44. for example. includes a first PNP transistor 140 having an emitter terminal 141 coupled to the 13+ terminal 42. a base terminal I42 coupled to input terminal 64a. and a collector terminal 143 coupled to the emitter terminal of a second transistor 146. Biasing resistors 1-H and I45 are provided to render the transistor nonconductive upon the receipt of any signal other than a logic I) and be switched to a con ductive state upon the receipt of a logic 0 signal to base terminal I42. Similarly. bias resistor 147 is provided to bias NPN transistor I46 in a nonconductive state unless a logic 1 is received and resistors I48 and I49 coupled as shown in the figure to bias PNP transistor 150 in a nonconductive state except upon the receipt of a logic U signal applied to the base terminal thereof by input terminal 641*.  
  In place of the circuit elements shown. any suitable controlled switching devices. preferably solid state. can be employed to provide an output signal only when a preselected digital code is applied to the respective input terminals of the number filter. Thus. the number filter need not take the specific form shown In FIG. 5 but can be of any suitable design to provide an output signal only when uniquely acitivatcd by the signals corresponding to the associated operand.  
  Continuing now with the description of the system shown in FIG. 2, the number filters 92-99 are identical in construction to filters 42-49 and include control input terminals l02-l09, respectively. for receiving signals from output terminal 32&#39; of number source 32. Number filters 92-99 further include input terminals 112-119. respectively. commonly coupled to the B+ supply voltage and output terminals 122-129, each interconnected to a plurality of associated correlator circuits. For the example chosen (2&#39;3 number source has its output terminal coupled to correlator 82 such that when number source 32 is actuated by the user of the system to provide an electrical signal corresponding to the number 3. output terminal 125 will provide a positive output signal.  
  As seen in FIG. 2. in a system with a first and second operands. the calculating system includes a correlators. one being assigned for each unique pair of first and second number filters provided. In the figure. only three correlators for the operations on 22. 2-3 and 2-4 are shown for the sake of clarity. it being understood that each number filter has n correlators associated therewith. which correlators are coupled to the n number filters of the other set.  
  The correlators can be constructed as shown in FIG. 6 where input terminals 83 and 87 of correlator 82 are coupled to an AND gate 89 having an output terminal 90 coupled to the input of an inverting amplifier 91 providing a second output terminal 90&#39; from the correlator. When the two number filters associated with cor relator 82 in the example are actuated by signals from number sources 30 and 32 associated with number filters 44 and 95. gate 89 will be actuated to provide a positive output signal (or a logic 1 output signal) at terminal 90 while amplifier 9] responds to this signal to provide a logic 0 output signal at terminal 90&#39;. In the present system. it is desired to provide both 1 and O logic signals representing an operation to assure compatiblity with existing logic systems which may be interfaced with the system. In some systems. the inverting amplifier may not be required. Each of the remaining correlators is the same as shown in FIG. 2. In the embodiment shown. there will be 64 such correlators for the [6 number filters of the first and second series.  
  It is seen that each correlator. therefore. represents a unique solution to the operation of one operand on a second operand. The output conductors 90 and 90&#39; of each correlator can be directly coupled to an output device which either displays in binary coded form the solution or provides output signals of a format suitable for interface with other systems. For the sake of simplicity. only the output wiring of correlator 82 in FIG. 2 is shown and is interconnected to a display panel to provide a visual output indication of the resultant s0 lution to the operations performed on the two operands.  
  Display I60 includes an array oflight emitting diodes 162 for providing an output indication for the operation of addition. an array 163 of light emitting diodes providing an output indication of the operation of subtraction. an array 164 oflight emitting diodes providing the output solution to the operation of multiplication. and finally. an array 165 of light emitting diodes providing the output solution for the operation of division. Each of the arrays of light emitting diodes includes a plurality of diodes sufficient to provide a unique display for the solution for each and every operation associated with that array for the operands of the system.  
 Extending from the output terminals of each correlator is a pair of conductors (I70 and 172 for correlator 82) which are directly coupled to preselected ones of the diodes ofeach of the arrays such that when the correlator corresponding to two particular operands is actuated by the associated number filters. the display 160 will provide a simultaneous light output display in the preferred embodiment as illustrated by the wiring shown in FIG. 2.  
  Since a single array of light emitting diodes is used to display all of the solutions to the particular operation. it is seen that each light emitting diode of the array will be electrically coupled to a plurality of correlators in the computer system. It is necessary. therefore. to provide current steering diodes to electrically isolate light emitting diodes desired not to be actuated when the pair of conductors 170. I72 from a correlator is actuated to activate the array.  
  Thus. for example. as seen on the multiplication operation of FIG. 2, where for the examples shown it is desired to actuate light emitting diodes 162a and 16217 but not I620. a pair of steering diodes 166 and 166&#39; is provided such that diode I620 will not be actuated on the acutuation of conductors I70 and 172 but con versely will be actuated upon the actuation of output conductors I73 and 174 from another correlator corresponding to a different solution for one or more different operators. The actuation of conductors I73 and 174 will. however, not actuate diodes 162a and 1621;. Similarly and in a conventional manner. current steering diodes will be provided for suitably interconnecting the various output conductors I70 and 172 from each of the correlators to each of the arrays of the display I60.  
  It is seen that such a system lends itself to large scale integration techniques currently employed for manufacturing a plurality of solid state devices on a single monolithic integrated circuit chip. Although in the computing system described herein. the actual circuit elements can become somewhat expansive, the interconnection and the formation of the elements can be commercially achieved by virtue of the large scale integration techniques to make a practical working system.  
  For the example shown. it is seen that six light emitting diodes will provide. for the functions add, subtract and multiply. the solution to these operations for the selected operands. To provide the decimal information required for the division operation, in addition to the six light emitting diodes. a plurality of additional light emitting diodes I68 are provided together with decimal point indicators 167 to carry out the division to the desired decimal point representation. Thus. for example. output conductors I70 and 172 will be coupled. as seen in FIG. 2. to the diodes as shown to provide the binary equivalent of the number 66 with a decimal point preceding the binary equivalent to provide an output corresponding to 2+3 carried out to two decimal points. It is apparent that by adding additional diodes. the division can be carried out to any desired number of digits.  
  In addition to the basic light emitting diodes of each array. the add. subtract and multiply arrays include a zero light emitting diode I6l for activation when the solution to the operation is zero. A special light emitting diode is provided for the subtract and divide operations to indicate a negative number and a nondivisible number respectively. These diodes are indicated as diodes I69 and 165&#39; respectively.  
  By extending the structure describing the basic principle of operation herein to incorporate the desired number of operands. the system can accommodate any degree of calculation desired on any number of operands. In addition. the system can be programmed to employ the basic principles herein to provide mathematical operations other addition, conventional addition. subtraction. multiplication and division as noted earlier. Another embodiment of the invention which eliminates the usage of eorrelators and. therefore, reduces the required number of circuit elements and computation time is shown in FIG. 7.  
  In the FIG. 7 circuit. there is provided a first number source 230 having an output terminal 230&#39; coupled to each of the control input terminals 250-259 of a first series of number filters 240-249 respectively. Each of the number filters includes signal input terminals 260-269 which are coupled to a B+ voltage supply. shown in FIG. 7, such that at output terminals 270-279 associated with the number filters 240-249. respectively. there will be applied an output signal only when an electrical signal from source 230 corresponding to an operand actuates a particular number filter identifying the operand. In the example shown in FIG. 7. the operand associated with source 230 is the number 6.  
  The output terminals of each of the number filters of the first set of number filters are coupled to an additional series of number filters identical to those of the first series. Additional number filter series 280-289, respectively. each include it number filters where n represents the numbeer of different operands used in the system. The output voltage at the output terminals of the first series of number filters. when present by the actuation of one of the filters of the first series. supplies the operating voltage for the voltage input terminals 360-369 of the additional series (280-289) of number filters. The input control signal is provided by a second number source 232 having an output terminal 232&#39; coupled to each of the control input terminals of each number filter in each additional series of number filters.  
  For the example shown in FIG. 7. the operand generated by the second number source 232 is the number 5 which is applied to the input of the additional series 286 of number filters associated with and coupled to output&#39;terminal 276 of number filter 246 of the first series of number filters. Thus. when the first number source is actuated to generate an electrical signal corresponding to the number 6 and the second number source is actuated to provide a signal representative of the number 5. only thefifth number filter 290 of the additional series 286 of number filters coupled to number filter 246 will be actuated to generate an output signal representative of the operations performed on operands 6 and 5 in that order as indicated on the output conductor 292 associated with number filter 290.  
  There will be u number filters in the circuit shown in FIG. 7 with a unique number filter ofone ofthe additional series of number filters being actuated upon the actuation of number sources 230 and 232. Each of the outputs of each number filter of each additional series of number filters will be coupled to arrays 300, 302, 304 and 306 of light emitting diodes 308 which arrays can be identical to those shown in FIG. 2 to provide an output display in binary coded form of the numerical equivalent of the operation performed. The display is not shown in detail in FIG. 7 since it is substantially identical to that shown in FIG. 2.  
  In the system shown in FIG. 7. therefore. only number filters are employed together with the number sources to provide an activation of a unique output conductor corresponding to operations performed on a pair of operands. This signal provides a logic I signal used to actuate the displays in conjunction with a continuously generated logic developed by a low voltage (logic 0) generator 310 with an output terminal 3l2 which is applied to the cathodes of the light emitting diodes in a conventional manner. Again. current steering diodes will be required to isolate the respective light emitting diodes to assure only those associated with a unique conductor will be actuated to indicate the solu tion to the operation for the particular operands selected and applied to the calculator.  
 It will become apparent to those skilled in the art that other arrangements of number sources with number filters can be provided to provide the parallel and simultaneous actuation of at least two number filters which in turn have their outputs uniquely coupled or combined through circuit means or directly to activate an output circuit or display for providing useful output information from the calculator system. The embodiments shown in FIGS. 2 and 7 are illustrative of the principle in which the simultaneous parallel actuation of the number sources greatly reduces the computing time of the system and permits programming of a system for a particular operation or operations to be performed on the operands inserted into the system.  
  The advantage of the system in addition to providing instantaneous calculation is that a plurality of operations can be simultaneously outputted and when this is combined with interface equipment, can be utilized to greatly increase the efficiency of a computer installation when. for example. the computing system described herein is employed as a subroutine to provide multiple and simultaneous outputs for different operations between two operands. Many modifications to the preferred embodiment can be made. for example. the number sources shown in H68. 2 and 7 can be actuated by a keyboard and circuits as shown in FIG. 3. Alternatively. the number sources may themselves be incorporated directly in a keyboard with switches as shown in FIG. 4. These and other modifications will, however. fall within the spirit and scope of the present invention as defined by the appended claims.  
  The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:  
  l. A calculating system for simultaneously performing and outputting the solutions of multiple operations on two or more operands comprising:  
 number source means for generating multiple bit binary electrical signals uniquely representing each number used in the system;  
 first number detector means coupled to said number source means for providing a unique output signal identifying a first number when actuated by a signal from said number source means representing said first number;  
 second number detector means coupled to said number sou rec means for providing a unique output signal identifying a second number when actuated by a signal from said number source representing said second number, wherein said first and second num ber detectors each comprises at least one series of binary signal responsive circuits. each series including one circuit uniquely associated with each number of the system and wherein each circuit includes a control terminal coupled to said number source means and an output terminal providing an output signal thereat when a multiple bit binary electrical signal applied to said control terminal from said number source means corresponds to the number uniquely identified by said circuit;  
 additional circuit means coupled to said first and second number detector means to provide an output signal uniquely identifying the combination of first and second numbers entered into the system by said number source means; and  
 output circuit means coupled to said additional circuit means and responsive to signals therefrom to provide a simultaneous output representation of the solutions for two or more operations performed on numbers entered into said system.  
  2. The system as defined in claim 1 wherein said number source means comprises first and second number sources having output terminals coupled to each of said control terminals of said binary signal responsive circuits associated only with said first and second binary signal responsive number detectors, respectively. and actuatable to generate signals uniquely identifying one of the numbers used in the system.  
  3. The system as defined in claim 2 wherein said additional circuit means comprises a series of logic circuits each having a first and a second input terminal. one terminal of which is coupled to an output terminal of a unique binary signal responsive circuit associated with said first number detector. the other terminal coupled to an output terminal of a unique binary signal responsive circuit associated with said second number detector. said logic circuit including an output terminal providing an output signal thereat only when predetermined signals are applied to said first and second input terminals of said logic circuit from the associated binary signal responsive circuits.  
  4. The system as defined in claim 3 wherein each of said logic circuits comprises an AND gate and said series of logic circuits and AND gates coupled to each unique pair of binary signal responsive circuits. one AND gate being associated with each binary responsive signal circuit of said first number detectors and a binary responsive signal circuit associated with a predetermined one of said second number detectors.  
  5. The system as defined in claim 4 wherein said output circuit means comprises arrays of indicators coupled to said output terminal of each of said AND gates to be actuated by a signal applied from an AND gate to display the solution to more than one operation performed between at least two numbers generated by said number sources.  
  6. A calculating system for simultaneously performing and outputting the solutions of multiple operations on two or more operands comprising:  
 means for generating electrical signals uniquely representing each operand used in the system;  
 first operand identification means coupled to said generating means for providing a unique output signal identifying a first operand when actuated by a signal from said generating means representing said first operand;  
 second operand identification means coupled to said generating means for providing a unique output signal identifying a second operand when actuated by a signal from said generating means representing said second operand; circuit means coupled to said first and second operand identification means to provide an output signal uniquely identifying the combination of first and second operands entered into the system by said generating means wherein said first and second operand identification means each comprises at least one series of detector circuits. each series including one detector uniquely associated with each operand of the system and wherein each detector includes a control terminal coupled to said generating means and an output terminal providing an output signal thereat when an electrical signal applied to said control terminal from said generating means corresponds to the operand uniquely identified by said detector and wherein said generating means comprises first and second operand sources having output terminals coupled to each of said control terminals of said detectors associated only with said first and second operand identifi cation means. respectively; and actuatable to generate signals uniquely identifying one of the oper ands used in the system; said circuit means comprises a series of AND circuits each having a first and a second input terminal. one terminal of which is coupled to an output terminal of a unique detector associated with said first operand identification means. the other terminal cou&#39; pled to an output terminal of a unique detector associated with said second operand identification means said AND circuit including an output terminal providing an output signal thereat only when signals are applied to said first and second input terminals of said AND circuit from the associated detectors. wherein an AND circuits is provided and coupled to each unique pair of detectors. one detector associated with said first operand identification means. the remaining detector associated with the second operand identification means; and  
 output circuit means comprising a plurality of arrays ofindicators. each array coupled to said output terminals of said AND circuits to simultaneously display the solutions to a plurality of operations performed between at least two operands generated by said operand sources.  
  7. A calculating system for simultaneously performing and outputting the solutions of multiple operations on two or more operands comprising:  
 means for generating electrical signals uniquely representing each operand used in the system;  
 first operand identification means coupled to said generating means for providing a unique output signal identifying a first operand when actuated by a signal from said generating means representing said first operand;  
 second operand identification means coupled to said generating means for providing a unique output signal identifying a second operand when actuated by a signal from said generating means representing said second operand;  
 circuit means coupled to said first and second operand identification means to provide an output signal uniquely identifying the combination of first and second operands entered into the system by said generating means;  
 output circuit means coupled to said circuit means and responsive to signals therefrom to provide a simultaneous output representation of the solutions for two or more operations performed on operands entered into said system. wherein said first operand identification means comprises at least one series of detector circuits. said series including one detector uniquely associated with each operand of the system and wherein each detector includes a control terminal coupled to said generating means and an output terminal providing an output signal thereat when an electrical signal applied to said control terminal from said generating means corre sponds to the operand uniquely identified by said detector circuit; and  
 wherein said second operand identification means comprises a plurality of series of detector circuits and said circuit means comprises means coupling input terminals of detector circuits of one series of each of said plurality of series to an output terminal of a unique detector associated with said first operand identification means such that when signals representing two operands are generated by said generating means. a unique detector associated with said second operand identification means will be actuated to provide a signal at an output terminal thereof. said circuit means including additional means coupling output terminals of each detector of each series of said plurality of series of detectors other than said one series to said output circuit means.  
  8. The system as defined in claim 7 wherein said output circuit means comprises at least a first array of indi cators coupled to said output terminals of each of said detectors of said operand identification means to be actuated by a signal applied from a detector to display the solution to an operation performed between at least two operands generated by said generating means.  
  9. The system as defined in claim 8 wherein said output circuit means includes a plurality of arrays of indicators. each array coupled to output terminals of each of said detectors of said second operand identification means to simultaneously display the solutions to a plurality of operations performed between at least two operands generated by said generating means.  
  10. A system for providing high speed operations be tween two numbers comprising:  
 a first number source having an output terminal for providing electrical signals thereat corresponding to any one of the numbers in the system;  
 a second number source having an output terminal for providing electrical signals thereat corresponding to any number of the system;  
 a source of electrical potential.  
 at first series of number gates; each gate comprising an input terminal coupled to said source of electrical potential. an output terminal. and at least one control terminal coupled to said output terminal of said first number source. each of said gates including circuit means responsive to signals applied to said control terminal when an electrical signal corresponding to the number assigned the particular number gate is applied to said control terminal from said first number source to couple a signal at said input terminal to said output terminal:  
 a second series of number gates. each gate comprising an input terminal coupled to said source of electrical potential an output terminal. and at least one control terminal coupled to said output terminal of said second number source, each of said gates including circuit means responsive to signals applied to said control terminal when an electrical signal corresponding to the number assigned the particular number gate is applied to said control terminal from said second number source to couple a signal at said input terminal to said output termi nal;  
 a series of AND circuits coupling each combination of number gates of said first and second series thereof, each AND circuit including a first input terminal coupled to one of said number gates of said first series of number gates and a second input terminal coupled to one of said number gates of said second series of number gates for providing first and second output signals at first and second output terminals thereof only when both of the as sociated number gates are actuated by a number source to apply a signal to said AND circuit; and  
 means coupled to said first and second output terminals of said AND circuits to provide simultaneous output signals uniquely identifying the resultant numbers for more than one operation performed between numbers generated by said first and second number sources.  
 11. A system for providing high speed operations between two numbers comprising:  
 a first number source having an output terminal for providing electrical signals thereat corresponding to numbers used in the system;  
 a second number source having an output terminal for providing electrical signals thereat corresponding to numbers used in the system;  
 a source of electrical potential:  
 it first series of number detectors each comprisng individual circuits corresponding to one of each of the numbers used in the system, said circuits having an input terminal coupled to said source ofelectrical potential and an output terminal, said circuits including a control terminal coupled to said output terminal of said first number source to be actuated to apply a signal at said input terminal to said output terminal of said detectors only when an electrical signal corresponding to the number assigned the detector is applied to said control terminal from said first number source; and at least a second series of number detectors comprising individual detector circuits corresponding to one of each of the numbers used in the system, said circuits having an input terminal coupled to an output terminal of one of said detectors of said first se rites and each including an output terminal said circuits including a control terminal coupled to said output terminal of said second number source to be actuated to couple a signal applied to said input terminal from said detector of said first series to said output terminals when an electrical signal corresponding to the number assigned said detector circuit in said second series is applied to said control terminal from said second number source; and  
 output circuit means coupled to said output terminals of said second series of detectors to provide signals indicating the solution to an operation performed between two numbers entered by said number sources.  
  [2. The system as defined in claim 11 and further including a plurality of second series of number detectors with one series for each number used in the system and each series including a detector for each number used in the system; and means coupling input terminals of each detector of a series of detectors to the output terminal of a unique detector of said first series and the control input of each detector to said output terminal of said second number source such that when said first number source provides a signal corresponding to a first number and said second number source provides a signal corresponding to a number. only one number detector of said plurality of series of number detectors will be actuated to provide an output signal for the unique combination of numbers entered by said num ber sources.