Vector tablet digitizing system
O United States Patent 1 [111 3,875,331 Hasenbalg Apr. 1, 1975 i 1 VECTOR TABLET DIGITIZING SYSTEM Primary ExaminerThomas A. Robinson [75] Inventor: Ralph D. Hasenbalg, Canoga Park,  
 Calif. [57] ABSTRACT [73] Assignee: Vector General, Inc., Canoga Park, electrostatic digitizing System is Provided which C m includes an X, Y digital tablet and a stylus as a graphic input unit, which serves to digitize drawings, or the [22] Flled: 1973 like, and which may be used in a variety of graphics 211 App} 413,773 applications and systems. The surface of the tablet emits a changing electrostatic field which is detected by the tip of the stylus. The field is time multiplexed to [52] Cl 178/19 178/18 340/l4635 provide three necessary functions, which will be re- 340/347 AD ferred to as the X-axis digitize function, the Y-axis l5l] lltl. Cl G08C 21/00 digitize function! and the pen near detect function [58] held at Search 340/14635 347 AD; The circuitry to be described incorporates a potentio- 178/l8&#39; 20; 318/567 metric feedback system whereby the stylus senses only 235/61) I97; 33/] M; 35/9 C an error value. The circuitry is also such that attenuation at the stylus input does not directly affect the 0p- [561 References cued eration of the system. The embodiment of the system U TED S S P S to be described is constructed to incorporate anti- 3.302.l94 1/l967 Green ct. al. 340/347 AD toggle and over-scale features, as well as an adjustable 3.342.935 9/1967 Lcifer ct al. 340/l46.3 SY margin feature. 3,59l,7l8 7 [97] A.&#39; &#39;l 178 I9 I mm M d I 10 Claims, ll Drawing Figures FIG ll) FROM PEN DC RESTORE COMPARATOR TABLET CONTROL LOGIC TABLET TIMlNG COUNTER [FIGS] TAX REGlSTER DIG AL MULTIPLEXER TAY REGISTER llO SENSE LOGIC DIA LADDER AND COMFLEMENT UPI DOWN COUNT E R NPEN NEAR 5N5 PEN NEAR INVERTING AMPLIFIERS lND SWlTClES SWITCH lFlG. O)  
  mo cues uxsra sra NXTAOS NYTADS N TA )(CL NTAYCL OVERSCALE IP- FLD Zll seamen 220 NTAMO-S TAY 0- 5 NTAYO TAXO-S NTAXO -x AXIS TABLET s|em| +X AXIS TABLET S|GNAL&#39; -Y AXIS SIGNAL Y AXIS SIGNAL PEN SIGNAL PEN NEAR BIAS CLOCK SIGNAL LOAD COUNTER STROBE x STROBE Y STROBE AXIS SELECT MULTIPLEXER STROBE TIMING DIAGRAM TIME SElL&#39;EI FIG.6  
 SHEET C? 3F 10 FIG? V1(-XTAB) V2(+XTAB) margin sefling margin semng X- coordinate Point Voltage n L &#39;J 1 1 PEN SNS TIME VECTOR TABLET DIGITIZING SYSTEM BACKGROUND OF THE INVENTION Digitizing tablet systems are known in which a tablet is provided that creates an electrostatic field, the field being detected by a stylus. However, the prior art systems have certain inherent drawbacks, in that the amplitude of the output signal is a function of the position of the stylus, and unless extreme care is taken, errors can be introduced into the outputs of the system. As described above, the improved system of the present invention utilizes a potentiometer feedback circuit so that the stylus senses only an error value, and the effect of the stylus position as it is moved towards and away from the plane of the tablet is reduced.  
  The tablet digitizing system of the invention can perform a variety of functions. For example, it can be used to digitize existing drawings, to edit old drawings, or to create new drawings. It can also serve the same functions as the prior art tracking balls, joy stick units, control dials, light pens, and the like.  
  The data tablet digitizing system of the invention includes an X, Y digital tablet, as mentioned above, and it utilizes the aforesaid potentiometric feedback circuitry for noise-free operation and for high accuracy at reasonable cost. In the embodiment to be described, the electronic portion of the system is separable from the tablet to allow convenient digitizing of large scale drawings. An over-scale output permits tablet edges to be used for function selections. Adjustable margins permit variable scaling and position adjustments.  
 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective representation of a digital tablet and associated stylus, together with a housing which encases the electronic package of the invention;  
  FIG. 2 is a plan view, somewhat schematically illustrating the electrical wiring associated with the digital tablet of FIG. 1;  
  FIG. 3 is a block diagram of a system which embodies the invention in one of its aspects;  
  FIG. 4 is a timing diagram including a series of curves useful in explaining the operation of the system of FIG. 3;  
  FIG. 5 is a more complete block diagram of the systern;  
  FIG. 6 is a further schematic representation of the tablet;  
  FIG. 7 is a circuit diagram representative of the tablet circuitry;  
  FIG. 8 is a series of curves useful in understanding the operation of the system;  
  FIG. 9 is a logic circuit diagram of certain of the components of the system; and  
  FIGS. 10 and 11 are schematic diagrams of other electronic components of the system.  
 DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT As mentioned above, the representation of FIG. 1 includes a digital tablet l0 and a stylus 12. The stylus 12 is connected through an electric cord 14 to the electronic portion of the apparatus which is enclosed, for example, within the housing 16.  
  As shown in FIG. 2, the digital tablet I0 includes, for example, input terminals designated X and +X, and input terminals designated +Y and -Y. A series of re- The wires 50 extend across the tablet in spaced parallel relationship with one another.  
  Likewise, a similar series of resistors, such as the resistors 52, 54, 56, 58, 60 and 62 are connected between the terminals +Y and -Y. A further plurality of electric wires 64 extend across the under surface of the tablet 10 in spaced, parallel relationship to one another, and at right angles to the wires 50. Each of the wires 64 is connected to a corresponding tap on the second series of resistors enumerated above.  
  In the operation of the system, the terminals +X and -X are first activated so that a current flow through the first series of resistors establishes each of the wires 50 at a particular potential level. This potential level is detected by the tip of the stylus 12 through electrostatic coupling with the wires 50, as the stylus is moved across the surface of the tablet 10. Then, the terminals +Y and -Y are activated so that a current flows through the second series of resistors, establishing the wires 64 at different potential values. These latter potential values are also detected by the stylus 12, as it is moved into contact with the surface of the tablet l0, and into electrostatic coupled relationship with the wires 64.  
  As shown in the block diagram of FIG. 3, the tablet 10 is activated by the +X and -X axis signals and by the +Y and -Y axis signals, these being derived from a digital-to-analog converter 100. The output of the stylus 12 is amplified in an amplifier I02, and the amplified signal is passed to a DC restoration, comparator and strobe logic circuit, represented by the block 104. A Pen Near bias F is introduced to the block 104, whereas a square wave M is introduced to the digitalto-analog converter 100.  
  The output of the block 104 is applied to an up-down counter 106 to set the counter for an up count or for a down count, when it is strobed by a suitable strobe signal. The output of the up-down counter 106 is applied to an X register 108, and to a Y register 110. The outputs of the registers 108 and 110 are applied to a digital multiplexer 112 whose output, in turn, is applied to the up-down counter I06, and to the digital-toanalog converter 100. Appropriate strobe signals I, J L are applied to the registers 108 and 110, and to the digital multiplexer 112. Also, an axis select signal K i: applied to the digital multiplexer 112.  
  The aforesaid signals are represented by the timing diagram of FIG. 4. During the operation of the system three periods occur which are repeated cyclically on microsecond basis. These periods comprise the X-axi: period,&#34; the Y-axis period,&#34; and the Pen Near pe riod. During the X-axis period, the X tablet signal A is applied to the X terminal of the tablet, and the tablet signal B is applied to the +X terminal of FIG. 2 These signals, as shown in the timing diagram of FIG 4 are of opposite polarity. Then, during the Y-axis pe riod, the Y signal C is applied to the Y terminal 0 FIG. 2 and the +Y signal D is applied to the +Y termi nal of FIG. 2 with opposite polarity, as also shown II the timing diagram. Then, during the Pen Near pe riod, the X axis signal A and +X axis signal B are botl applied with the same polarity to the X terminal and +X terminal of FIG. 2.  
  The Pen Near bias F is applied with a predetermined polarity to the circuit 104 during the Pen Near period, and the signal E developed by the stylus l2, and amplified by the amplifier 102 must have sufficient ampli tude to exceed the Pen Near bias before a Pen Near output signal will be generated.  
  The block 104 also produces a Load Counter strobe H which conditions the up-down counter 106 for an up count or a down count, under the control of the clock signal G. The X register is controlled by the strobe signal I, and the Y register is controlled by the strobe signal J. The Axis Select signal K applied to the digital multiplexer 112 has the waveform shown in FIG. 4, and the multiplexer strobe signal L also has the illustrated waveform. Finally, the square wave M applied to the digital-to-analog converter 100 has the illustrated waveform of FIG. 4.  
  As mentioned above, a potentiometer feedback circuit is used in the system to increase the accuracy and to provide the added features enumerated above. The surface of the tablet emits a changing electrostatic field which is detected by the tip of the stylus 12. Time multiplexing of the electrostatic field provides the three necessary functions, namely, X-axis digitize, Y-axis digitize and Pen Near detect.  
  In the operation of the system, the output of the X register 108 is applied to the digital-to-analog converter 100 by the digital multiplexer 112 during each X-axis period. At the same time, a positive level of the square wave M is applied to the analog input of the digitaI-to-analog converter 100. Two outputs are obtained from the digital-to-analog converter, one being proportional to the negative value of the product of the amplitude of the square wave M and the digital input derived from the X register; and the other being proportional to the full scale output minus the product of the square wave amplitude and the digital input. The two outputs from the digital-to-analog converter 100 derived during each X-axis period may be represented as follows:  
 -X K,(sq.amp) [(dig. value) (max. dig. va-  
  +X K (sq.amp) [(max. dig. value) (I+Km )(dig. value)] where:  
 +X is the voltage at the right edge of the tablet 10;  
 X is the voltage at the left edge of the tablet;  
 K, is the max. gain from the sq. wave to the output of the surface driving amplifiers;  
 Km, is the left margin constant as a fraction of (sq.  
 wave) (max. dig. value);  
 Km is the right margin constant as a fraction of (sq. wave) (max. dig. value).  
  During the positive half-cycle of the square wave M, the direct current restoration circuit in the block 104 nulls the output from the stylus 12 to zero. The direct current restoration circuit is then disabled, and the square wave M changes to a negative value for the latter portion of each X-axis period. The voltage at the right hand side of the tablet (+X) now goes positive while the voltage at the left edge (-X) goes negative. During the latter half of the X-axis period, and during the negative half cycle of the M square wave, the updown counter 106 is loaded with the value in the X register by way of the digital multiplexer 112, and under the control of the Load Counter signal H.  
  At the end of the X-axis period, the output from the comparator in the block 104 is strobed into a flip-flop indicating that the new stylus position is to be left or right of the old position. If a logic circuit (to be described) which prevents continuous toggling of the least significant bit does not inhibit the counter clock, the counter is stepped up or down one count. This new value is loaded into the X register by the X strobe I, if the strobe is not inhibited by an over-scale logic circuit, also to be described.  
  During the Y-axis period, the same functions occur to control and up-date the Y register 110. The X register 108 and Y register are both connected to an appropriate output display, or to an appropriate utilization system, since the contents of the two registers represents the X-axis and Y-axis digitized values corresponding to the different stylus positions on the surface of the tablet.  
  Thus, a servo approach is utilized in the system to cause the values of the X register 108 and Y register 110 to track the positions of the stylus 12. At all stylus positions, a null field condition is generated at the stylus point, with the register contents being controlled by the servo circuitry to control the +X, X and +Y, Y values until a null is reached. That is, the voltages at the edges of the tablet change in opposite polarity and by amplitudes that make the change at the position of the stylus tip only an error value.  
  During each Pen Near period, the X-axis signals A and B appear at the -X terminal and +X terminal of FIG. 2 with the same amplitude and same polarity. The X voltage is positive during the first half-cycle of the Pen Near period, and negative during the second halfcycle. The Pen Near bias F introduced to the pen comparator circuit in the block 104 is adjustable to a predetermined level. If the amplitude of the stylus output signal E from the amplifier 102 exceeds the Pen Near bias amplitude for both of the half-cycles of all cycles during a time delay, a Pen Near output will be generated to inform the utilization means that the signals detected by the stylus are valid and should be processed. To prevent continuous changes in the Pen Near output when the stylus is at a threshold value, the Pen Near comparator bias level F is decreased when Pen Near is detected to produce a hysteresis effect.  
  If the up-down counter 106 is loaded with a full scale positive value from the X register 108 or Y register 110, and a TUP clock from the unit 104 causes a spillover into the next more significant bit, the register strobe I or J is then inhibited to prevent a wrap-around condition in the register. The same register Strobe Inhibit signal occurs when a full scale negative value is loaded into the updown counter 106 and a TDN clock occurs from the unit 104. Thus the registers 108 and 110 lock at full-scale positive or negative values when an over-scale condition occurs. Two over-scale outputs, one for X and one for Y indicate when an overscale condition is present.  
  A switch in the stylus 12 closes when pressure is applied to the point of the stylus. A level detector circuit senses the switch closure and supplies the pen pressure output.  
  A more complete block diagram of the system is shown in FIG. 5 in which components similar to those previously shown in FIG. 3 are referred to by the same numbers. The system shown in FIG. 5 includes a pen pressure comparator 200 which responds to a signal when the stylus switch is closed, and which is connected to a buffer 202. The system also includes a direct current restoration comparator 204 which is included in the block 104 of P16. 3. The signal from the amplifier 102 is applied to the comparator 204. The comparators 200 and 204 are shown in circuit detail in FIG. 11. The comparator 204 is connected to Pen Near sense logic represented by the block 210.  
  The system further includes a tablet timing counter 206 and tablet control logic 208 connected to a digitalto-analog ladder and complement switch represented by the block 209, and which is included in the block 100 of FIG. 3. The switch 209 is connected to the tablet through inverting amplifiers and PET switches, represented by the block 212 and 214. The tablet control logic 208 is also connected to over-scale flip-flop represented by the block 211. The block 211, and the updown counter 106 are connected to register clock gates 220. The various logic values developed in the system are represented in the diagram of FIG. 5. The Pen Near sense logic 210 is shown in more detail in FIG. 9, and the BIA logic 209 and associated amplifiers are shown in more detail in FIG. 10.  
  The tablet timing counter 206 is formed of four flipflops TAC1-TAC4, and is used to generate the tablet cycle sense periods, the strobes, the register clocks, and the like. In the constructed embodiment, the duration of one complete tablet cycle is l50 microseconds.  
  The TAX register 108 is a lO-bit register consisting of eight flip-flops TAXO-TAX7, and two extension flip-flops to provide TAX8, TAX9 digital signals. The register contents are multiplexed by the digital multiplexer 112 and applied to the digital/analog converter blocks 209, 212 and 214 to produce the XTAB and +XTAB voltages for the X-axis of the tablet 10. The digital output from the TAX register 108 is also loaded into the up-down counter 106 by way of the digital multiplexer 112, which is either incremented or decremented to make the corresponding register track the stylus position in a closed loop operation (TAMO-9).  
  The contents of the up-down counter 106 are then loaded back into the corresponding TAX register 108 or TAY register 110 (TUDO-9). If the up-down counter overflows or underflows, the register strobes are inhibited to prevent wrap-around of the register contents, as explained above, and, as a result, when an over-scale condition exists, the register contents remain unchanged, either full or empty.  
  The TAY register 110 provides TAYO-9 digital output signals which track the Y coordinate position of the stylus, and which are also applied to the digital multiplexer 112 for multiplexing with the corresponding digital output signals from the TAX register 108.  
  The digital multiplexer 112 passes the TAXO-9 signals to the digital/analog converter 209 and to the counter 106 during the X-period, and the TAYO-9 signals to the digital/analog converter and counter during the Y-period. During the Pen Near period, the TAMO- 9 digital output signals from the multiplexer are forced to logical *ones&#34; and applied to the digital-to-analog converter to produce the XTAB and SNS RING signals for the tablet 10.  
  The tablet control logic 208 develops the counter load (NTUDLD) and up-down strobe signals (NTUPCL, NTDNCL) for the up-down counter 106,  
 the DC restore signal (TDCRES) for the comparator 204, and the strobe signals NTAXCL and NTAYCL for the registers 108 and 110. ln addition, the tablet control logic supplies a supplemental bit, TAM10, to the digital/analog converter 209.  
  Since a closed loop system requires a detected error signal to null itself out, the system has a tendency to hunt when at the null value. The TAM10 signal, along with anti-toggle flip-flops, inhibit strobing of the counter and subsequent toggling of the register least significant bits. Instead, the TAM10 signal, with the same binary weight as the least significant bit TAM9, is toggled, and the registers maintain a steady binary value when at the null position.  
  For example, for anti-toggle logic operation in the X channel, the output of the TAXANT flip-flop is gated to drive the eleventh bit (TAM 10) of the digital/analog converter during the X-axis time and prevents continuous toggling of the least significant bit (TAX9 If an up command is indicated by the TUP flip-flop and the TAXANT flip-flop is false, then the TUP strobe to the counter will be inhibited. Also, if a down command is indicated by the TUP flip-flop and the TAXANT flipflop is true, the TDN strobe will be inhibited. Therefore, if the stylus is in a position where the change in the output of the digital/analog converter caused by the toggling of TAM10 on successive operating cycles causes alternate TUP and TDN commands, no change in the TAXO-9 output bits will occur. However, if the pen moves so that the TUP flip-flop is in the same state for two successive operating cycles, the counter 106 will be strobed and a new value will be fed into the X register. The operation for the Y sense period is the same.  
  The up-down counter 106 consists of a ten bit counter (TUDO-9) plus an overflow state (TAMOV). The counter is alternately loaded from the TAX and TAY registers 108, 110, and is then either incremented, decremented, or not strobed, depending on the state of the pen sense signal TUCOM and the states of the anti-toggle flip-flops, described above. The counter output is then loaded back into the appropriate TAX or TAY register to update its value. In the event of an overflow or underflow, the counter output TAMOV sets the appropriate over-scale flip-flops and inhibits the strobe to the corresponding register 108 or 110.  
  The digital/analog ladder network in the block 209 provides the binary-weighted resistors which produce multiplication of the digital input value times the digital/analog reference value for the NOD] and NOD2 signal outputs. Instead of utilizing a DC voltage for the digital/analog reference, the complementary switch alternately selects :7.5 volts to provide the 20 KHz square wave reference M (FIGS. 4 and 8). The ladder resistors provide a gain of one-half full scale value for TAMO to l/l024 full scale value for TAM9. The additional anti-toggle signal TAM10 has the same binary value as TAM9. During the Pen Near period, the TAMO-9 digital signals are forced to logical ones. However, the digital/analog three most significflhi blti are inhibited by TACl and results in a bit confl ilfalion for resistor selection to g&#39;herate the SNS Rl G and XTAB signals for the tabli:  
  The inverting amplifiers find FET switfilis in the block 212 and 214 are palfi of the digitallflfifilog converter. The block 212 receives the NODl Qlltput from the block 209 and provides tablet excitation voltages minus YTAB and minus XTAB proportional to the register digital value times the square wave value. Field effect transistors are used in the block to provide the switching required alternately to energize the X/Y axes and the sense ring. The circuitry of the block 212 also contains left X and bottom Y margin adjustment potentiometers.  
  The circuitry of the block 214 is the same as the circuitry of the block 212, except that the output tablet control voltages +XTAB and +YTAB are proportional to the logical zeros from the corresponding register multiplied by the square wave value. Only one inverting amplifier is used in the block 214 with the result that the +XTAB and +YTAB output voltages are of opposite polarity to the YTAB and -XTAB output voltages. as is desired. The block 214 also includes right X and top Y margin adjustment potentiometers. The po tentiometers adjust the portions of the square wave signal M which are added to the plus and minus outputs of the blocks 212 and 214 in each axis when the corresponding axis is active. Increasing the amount of the square wave summed with the output moves the margin towards the center. The four potentiometers allow setting any margin to any value within the range of the specification. The tablet is linear and accurate for all settings of the margin adjustments.  
  Six gates are used in the register clock gates of block 220 to generate the register clock or strobe signals, three for each of the TAX and TAY registers 108, 110. If an over-scale condition exists, the term TAMOV becomes high, and the strobes are inhibited, so that the contents of the up-down counter 106 are prevented from being loaded back into the corresponding register.  
  Two over-scale flip-flops are provided in the block 211 to generate low active X or Y over-scale signal outputs. If an over-scale condition exists in only one axis, that register value is set at either its upper or lower limit. depending on the over-scale condition, while the other register accurately tracks and reflects the stylus coordinate position on the corresponding axis.  
  The direction current restoration-comparator circuitry in the block 204 receives the stylus signal from the amplifier 102 and generates a digital tablet up signal (TUCOM) or a tablet down signal (NTUCOM) for the tablet control logic 208 and for the Pen Near sense logic 210. During the first half cycle of both the X and Y sense periods, the tablet DC restore signal (TDCRES) grounds the pen signal output and discharges the pen capacitors in preparation for detecting the pen X or Y sense signal during the second half cycle. The TUP flip-flop then sets at the end of the X or Y period if the comparator output TUCOM survives until that time. During the Pen Near sense period, an adjustable 20 KHz bias is applied to the comparator reference. When the pen output magnitude exceeds the reference bias on both half cycles of the Pen Near period, the TUCOM signal causes the Pen Near sense logic 210 to generate a Pen Near output signal. The Pen Near sense logic consists of three flip-flops TASNSl-3, and associated logic, to generate a low active NPEN NEAR SNS output when the pen is held close to the surface of the tablet 10.  
  When the pen pressure switch is activated as a result of contact of the point of the stylus 12 with the surface of the tablet 10, the pen pressure comparator 200 switches to provide a signal output which is buffered in the buffer 202 and which appears as a low active NPEN PRS SNS signal. The output signals from the buffer 202 and the Pen Near sense logic 210 are utilized by the apparatus activated by the system so that the apparatus will respond only at the appropriate times to the output signals from the system.  
  The data tablet shown schematically in FIG. 2 is also shown in a further schematic diagram of FIG. 6. The data tablet in a constructed embodiment contains 150 separated vertical wires etched on the top surface for generating pen sense signals in the X-axis. Each such wire is connected to its adjacent wire by a ohm resistor to form a linear 2980 ohm resistance across the tablet X surface. The wires are spaced on 0.1 inch centers to provide an overall tablet X dimension of 14.9 inches. The bottom of the tablet contains identical etched wires and resistors for Y-axis sensing, as described above. A square 0.5 inch sense ring 250 is installed 0.l inches beyond the outermost wires on both the top and bottom surfaces of the tablet. The purpose of the sense ring is to inhibit the Pen Near signal output when the stylus is positioned in the over-scale area outside of the X- and Y-surface limits.  
  Reference is made to FIG. 7 for an analysis of the data tablet electrical operation. Since operation and voltage sensing of the X- and Y-axes are identical, only the X-axis aspect will be analyzed. The excitation voltages are shown in V1 and V2 in FIG. 7; the voltage at a given coordinate point is shown as VP: and X distances on the tablet surface are shown as d1 and d2.  
  The voltage sensed by the stylus (VP) is then determined by the following equation:  
 dig. value)Kml] (d2)+ [(max. dig. value)- (dig. value)+(max. dig. value)Km2]d2} 3 where:  
 V,, is the sensor input voltage; K0 is the gain from the tablet surface to the sensor input.  
  The voltage form selected for V1 and V2 is the 20 KHz square wave output from the digital-to-analog converter to provide a step change which may be sensed more readily by capacitive coupling to the stylus sensor. The voltage V1 is the inverted output from the digital-to-analog converter whose amplitude is determined by the digital 1 bits; while the voltage V2 is the uninverted output whose amplitude is determined by the digital 0 bits. The outputs of the digital-toanalog converter (for the X-axis) are then as follows:  
 V1 K1(sq.amp.) [(dig. value )+(mas.dig.-  
  value)](m11. (4 V2 K1(sq.amp.) [(max.dig.value)(1+Km2)(dig.-  
 value)] where values for the illustrated embodiment are approximately: K1 1.0 sq. amp. 7.5 volts dig. value 0 to L0 depending on pen position max. dig. value l.0 Kml 0.0404 to 0.2904 depending on margin setting Km2 0.0404 to 0.2904  
  In general, the potential across the tablet surface is in the order of 8.106V to 11.856V maximum, depending on the settings of the margin adjustment potentiometers. In any case. the -XTAB and +XTAB square waves are always of opposite potential. As a result, for any digital input to the D/A, a voltage null will always exist somewhere across the face of the tablet. For example, if the XTAB square wave swings +/-4.l33V while the +XTAB square wave swings /+4.I33V, the voltage potential at the zero X point in the center of the tablet is zero. At this time, the tablet X register value is at mid range. If the register value is zero, the voltage and Y-periods, the first TUCOM signal sets a TUP flipflop in the tablet control logic 208 which, in turn, sets an anti-toggle flip-flop TAXANT. During the following X- or Y-period, if the TUCOM signal is again high, the TUP flip-flop is again set and the counter I06 is incremented to increase the value of the corresponding X or Y register one bit Each successive TUCOM high signal then continues to increment the counter and the corresponding register. In the same way, if the TUCOM signull appears at the X side of the tablet and when the nal is low for two successive periods. the TAXANT register is all *1s&#34;, the null is at the +X side. flip-flop is re-set, and the counter 106 is decremented The tablet circuitry is configured to keep the voltage to decrease the corresponding register. The purpose at the sensed point (VP) at 0V. This is accomplished and operation of the anti-toggle logic circuit has been by using the pen output drive the register in the approdescribed previously. If the TUCOM signal is low durpriate direction, thereby adjusting the XTAB voltage l5 ing the first half and high during the second half of the potentials, until the voltage at the pen point coordinate 6 1 ea 6 8 Pe od. IiP-IIOPS are Set in the Perl nulls out. Thus, a servo process is used to make the reg- Near Sense lOgiC 210 hich, in turn, acti ate the NPEN ister values track the pen position. This results in: EAR SNS Output Signaldl (dl+d2)Km1 d1 1 Kml+l m2 31 &#39;+&#34;&#39;d2 d1 (dl+d2) m1 +d2 M l+I ml+Km2 1+Kml+Km2 dig. value (5) max. dlg. value Since the distances dl&#39; and d2 are offset by constant The tablet timing counter 206, the tablet control values from the d1 and d2 distances for any margin setlogic 208, and the Pen Near sense logic 210 are shown tings, the digital value of the register is linearly related 39 in logic detail in FIG. 9. The digital/analog ladder and to the distance d1 and does not depend on the magnicomplement switching network 209, the inverting amtude of the square wave or the attenuation at the pen plifier 212, and the inverting amplifier 214 are all sensor input. shown in simplified schematic detail in FIG. 10. The  
  As explained above, the stylus 12 uses capacitive pen pressure comparator 200 and DC restore comparasensing to detect the changing electrostatic field at the tor 204 are shown in circuit detail in FIG. 11. surface of the tablet I0. The signal sensed by the capac- As shown in FIG. 9, the timing of the system is under itive pick-up in the stylus is amplified by the prethe control of a four stage, modified cyclic counter amplifier 102 and passed on to the direct current resto- (TACI-TAC4) which completes one cycle for the sysration and comparator 204 of FIG. 5 to generate a tem in ISO microseconds. The counter is decoded to TUCOM signal. The presence of the TUCOM signal, if 40 divide the operational cycle into three sense periods, as it survives for the required amount of time, increments follows: the up-down counter 106 which increases or decreases the value of the corresponding register 108 or 110 until a voltage null exists at the pen coordinate position. The NTACLNTACZ X period presence of the TUCOM signal results in the counter =3 pelzliod P M being incremented, and the presence ofits complement f car NTUCOM results in the counter being decremented, so {gig :23 s g lfjlf as to achieve the null point. The stylus 12 also includes a pressure switch, as mentioned above, which is acti- Vated y its F&#39; Pressure against the tablet Surfafie, The digital/analog converter, as illustrated in FIG. 10 and which is appli IO e P 200 Of 5 is configured to receive digital data from the registers to provide a discret PEN PR5 3N5 output signal. 108 and 110 by way of the multiplexer 112 to provide AS also explained above, the system UIIIIIZS a repetitwo Simultaneous compleme nary analgg utputs Du tive I50 microsecond sense cycle which is divided into i th X p i d, th di ital inputs received from the three separate sense periods so that the system may se- TAX i t r 108, b way of the digital multiplexer quentially sense the X-channel, the Y-channel, and the 112, causes the circuit to generate the XTAB and Pen Near conditions. The logic of the system requires +XTAB voltages for the X-axis excitation of the tablet a minimum of two consecutive pen sense up (TU- 10. During the Y period, the digital inputs received COM) signals, or two consecutive down (NTU- from the TAY register 110 by way of the digital multi- COM) signals, as shown by the curves of FIG. 8 to genplexer 112, cause the system to generate the -YTAB erate an up or down strobe and update the registers and +YTAB voltages for the Y-axis excitation of the 108, 110 to the current stylus coordinate position tablet. During the Pen Near period, the digital inputs value. are forced to ones, and the circuit generates the As also pointed out above, during the first half of XTAB and +XTAB voltages for the X-axis. At the each of the X- and Y-periods, the output of the stylus is inhibited by a direct-current restoration signal (TDCRES). During the second half of each of the X- same time, the SNS RING voltage is applied to the tablet sense ring to inhibit the NPEN NEAR SNS signal output when the pen is positioned in those areas.  
  The digital/analog converter uses the ZOKHZ i 7.5 volt square wave (M) for its voltage reference. This results in l80 out-of-phase outputs with a maximum potential difference of ll.838V between the minus and the selected input resistors connected to the nodes, thus driving the node potentials close to V. This then satisfies the equation for establishing the tablet excitation voltage values. The feedback resistors and the lad plus TAB outputs The XTAB and YTAB signals are der resistor values, without the margin adjust circuits, applied to the -X and Y terminals of the tablet rewould provide an amplifier scale factor of 1, however, spectively and are in phase with the-square wave referthe output voltages are offset by a value of 0.302V to ence M; while the +XTAB and +YTAB signals are ap- 2.169V. depending on the setting of the margin adjust plied to the +X and +Y terminals, and are 180 out-ofpotentiomcters A. B, C. D. phase with the XTAB and YTAB signals. That is. l() The resistance values of the ladder in FIG. are biduring the X or Y periods. when the voltage potential nary weighted such that bit TAMO (MSB) results in a at one terminal of the tablet is positive, the potential at gain of /2 full scale, TAMI with a gain of A full scale. the opposite terminal is negative. Since the current through the feedback resistor to In essence, the digital/analog converter consists of a NODl must equal the sum of the current through the pair of operational amplifiers ARS and AR6, with feedselected input resistors, the gain of the amplifier is the back resistors, one for each channel, and a combinasum of the binary values of the ladder resistors selected tion of input resistors. During the X period. digital by the FET switches closed by logical ones. input signals TAMO-9 representing the contents of the Maximum output is achieved when TAMO-9 are set TAX register 108, control the FET switches Q23-Q64 to ones. The output is then l 1/1024 times the square in the resistance ladder network. At the same time. the wave amplitude times K, or effectively i 7.802 to FET switches select the X-axis operational amplifier 9.669V, depending on the setting of the margin potenfeedback resistors, select the X-margin adjust circuits. tiometer. At the same time, the +XTAB voltage level, connect the amplifier outputs to the XTAB and as a result of no digital zeros input, and margin adjust +XTAB signal lines, and ground the YTAB and SNS current only to NODE 2, is in the order of 0.302 to RING outputs to the tablet. 2.169V, and is opposite in polarity to the -XTAB sig- The current to NODl is determined by the selection nal voltage. When the TAMO-9 inputs are all zeros, of a combination of input resistors as a result of logical the :XTAB voltage values are reversed. one inputs while the current to NODZ is determined by While a particular embodiment of the invention has the input resistors selected by the logical zero inputs. been shown and described, modifications may be The inverted outputs of the operational amplifiers made. It is intended in the following claims to cover all stabilize at a value such that their feedback currents the modifications that come within the spirit and scope through the 4.49K resistors equals the current through of the invention.  
 APPENDIX LOGIC TERMS AND EQUATIONS Term Equation Description CL] Buffered 80 KHz data tablet clock. CLZ Buffered 80 KHz data tablet clock. CL3 Buffered 80 KHz data tablet clock. NCL inverter 80 KHz data tablet clock. NODE l Node of o rational amplifier R5 for -XTAB and YTAB signals. NODE 2 Node of erational amplifier R6 for +XTAB and +YTAB signals. N PEN NEAR SNSl Low-active pen near signal output to LED. N PEN NEAR SNS2 Low-active pen near signal output. PEN PRS SNS Output of pen pressure switch comparator. NPEN PRS SNSl Low-active pen pressure signal to LED. NPEN PRS SNS2 Low-active pen pressure si nal output. SNS RING l.3l9V square wave to tablet sense ring. TAC4 Tablet counter LSB flip-flop KHz) J NTAC4CLI. Toggled by I25 a s clock K =TAC4.CLI. To led by l2.5 u s clock TAC3 Tab et counter 2nd LSB flip-flop (20 KHZ). NTAC3.TAC4.CL1. Follow TAC4. K TAC3.TACA.CL l. Follow TAC4. TAC2 Tablet counter Y- Start Y-sense period. End Y-sense period.  
 APPENDIX -Conlinued [IN 1 HiRMS .-\\l) EULA FIONS K TAC l .NTAC2.TAC3.TAC4.CL1.  
 TAClS TAC l.  
 NTAC&#39; l S.  
 = NTACl.  
 TAC2S TACZ.  
 TACZSl TACZS.  
 TAC2S2 TACZS TAC2S3 TACZS.  
 NTAC2S NTACZ.  
 NTACZSI NTAC2S.  
 NTACZSZ NTACZS.  
 NTAC2S3 NTAC2S TAMOV TAMO-9 TAXO-9.NTAC1.NTAC2.  
 + TAYO-9.NTACl.TAC2.  
 NTAMO-9 TAM l0 Description Tablet pen-sense tart pensense period. End pen-sense period. FET switch gate signal. Pen-sense period. When high. turns on FET 28 to a Ely ARfi output to NO 1 for SNS RING and outputs to tablet. X or Y sense period. When high, grounds SNS RING out ut and applies i .SV square wave to margin adjust circuits. Y-sense control signal for FET gates. Y-sense period, generate TACZSI, 2, and 3. When high, turns on O2] to provide AR5 out ut to inverter AR8 an connect feedback resistor R133 to NODE l. Ysense control signal. When high. turns on FETs Q18 and 019 to connect Y margin circuits and feedback for ARS and ARfi. Also closes FETs Q22 and 029 to ground and --outputs. Y-sense control signal. When hi turns on FET O2 to provide +YTAB signal output. X-axis and pen-sense eriods.  
 hen hisgh, enerate NTACZ l, and 3. X-axis and pen-sense eriods.  
  hen high, turns on 022 to provide ARS output to inverter AR? and connect feedback resistor R122 to p. Multiplexer output signals.  
 Select TAX REG outputs for counter inputting and multi lexer outputs (NT MO- Select TAY REG outputs for counter inputting and multiplexer outputs (NTAMO-9).  
 Low-active multiplexer signal out uts.  
 Anti-togg e control signal to DAC (binary wei ht of l/l023 full sca e).  
  15 APPENDIX (ontinued LUUK&#34; lERMS AND EQK ATIONS lcrm ltquutiun Description TASNSl TAXNSZ TASNS3 TAXU-9 TAXANT NTAXCL TAXCLl TAXCLZ TAXCL3 TAYO-9 TAYANT NTAYC L TAYCLl TAYCLZ TAYCL] TCL SET TUCOM ,TACl .NTAC3.TAC4.NCL  
 RESET SET RESET TAXANTNTAC l rNTACl TAYANTTACZ,  
 + TASNSl .NCL  
 = TACI.NTAC3.NTAC4.  
 = TUCOM ,TAC l ,TAC2.TAC4.NCL.  
 + TASNSZNCL,  
 = TACLNTACELNTAC4.  
 = NTASNS l .TASNSlTACZNTACl NTAC4.CL3.  
 TASNS l .TAC2.NTAC3.NTAC4.CL3.  
 + NTASNSZTACZNTACIl NTAC4.CL3.  
 = TUPrTAC2.NTAC3rTAC4.CL3.  
 = TAC2.NTAC3.TAC4.CL2.  
 = TAXCLNTAMOV.  
 = TAXCLNTAMOV TAXCLNTAMOV.  
 = TUP.TACl .NTAC3.TAC4.CL3.  
 = NTUPiTACl .NTAC3.TAC4rCL3.  
 = TACl .NTAC3.TAC4rCL2.  
 = TAYCLNTAMOV.  
 = TAYCLNTAMOV.  
 = TAYCLNTAMOV X-sense period, increase D/A output by 73 MV.  
 Y esense period, increase D/A output by 7.3 MM  
 No. l  
 Set during pen period of no pen-sense (TUCOM high during lst half cycle) Hold set until sampled by TASNS3.  
 Reset after resetting TASNS3.  
 Pen-sense condition (TUCOM high during 2nd half of pen period) Hold until sampled by TASNS3.  
 Reset after sampling Not 3.  
 Pen sense condition, activate N PEN NEAR SNS signals after 50 MS Reset for no-sense condition, Reset for no-sense condition.  
 Data table X register outputs.  
 flo TL COM at end of X- eriod, enerate TUPC to increment counter if TUP during next X- eriodr No TU OM at end of X-erpiod, generate NTDNCL to decrement counter if NTUP during next X-period. Low-active X REG clock. Generate TAXCL to load TAX REG from counter if no TAMOV, TAX REG clock. Load TAX REG from Counter. TAX REG clock Relieve TAXCLI. TAX REG clock. Relieve TAXCLl. Data tablet Y register outputs Y anti-toggle flip-flop. TUCOM at end of Y- period. generate NTUPCL to increment counter if TUP during next Y- el&#39;iodv No TU OM at end of Y- eriod, generate N DNCL to decrement counter if NTUP during next Y-period. Low-active Y REG clock. Generate TAYCL to load TAY REG from counter if no TAMOV. TAY REG clock. Load TAY REG from counter. TAY REG clock Relieve TAYCL]. TAY REG clock. Relieve TAYCL]. Data tablet 80 KHz clock in base with CLl. CL and CL3.  
 APPENDIX Continued LOGIC TERMS AND EQL&#39;ATIONS Term Eq uatiori Description TDCRES signal. NTACl .NTAC3.CL2  
 Tablet DC restore Restore pen capacitor potential to zero during X and Y periods.  
 + NTAC l .NTAC 3 .TAC 4 Restore n capacitor potentia to zero during X and Y periods.  
 NTDNC L NTU P.NTAXANT.TAC2 NTACB. NTAC4.CL.  
 Tablet counter down clock. Two successive X-sense down clocks. decrement counter X coordinate value. NTUP.NTAYANT.TAC1.NTAC3.  
 NTAC4.CL.  
 Two successive Y-sense down clocks. decrement counter Y coordinate value.  
 TUCOM Pen sense comparator output signal (reference timing dia am).  
 NTUDLD NTAC l .TAC3.TAC4.CL2.  
 Tablet counter oad signal. Load TAMO-9 multiplexer outputs into counter.  
 TU DO-9 Tablet counter outputs signals TUDO is MSB.  
 TUP  
 SET  
  flo TUCOMNTACI .TAC3.TAC4.NCL. p  
 X or Y up-count condition detected.  
 + TUP.NCL.  
 enerated.  
 = TAC2.TAC3.NTAC4.CL2. TAC l .TAC3.NTAC4.CL2.  
 =TU P.TAX ANTIACZ .NTAC3.  
 NTAC4.CL.  
 RESET NTUPCL Hold until up-clock is eset after X-sense. Reset after Y-sense. Tablet counter up clock. Two successive X-sense up clocks, increment counter X coordinate value.  
 + TUP.TAYANT.TAC l .NTAC3.  
 NTAC4.CL.  
 Two successive Y-sense up clocks. increment counter Y coordinate value.  
 NXSTB NTACl .NTAC2.NTAC3.NTAC4.CL2.  
 Tablet X output strobe X register data on TAMO-9 multiplexer output lines.  
 XSTUD TAC2.NTAC3.NTAC4.CL.  
 X U/D counter strobe. Generate up clock if TUP.TAXANT or down clock of NTUPNTAXANT.  
 NXTAOS SET RESET +XTAB TAMOVTAXCL. NTAMOV.TAXCL.  
 X overscale output signal.  
 Overflow condition. No overflow condition. X output signal to tablet X axis.  
 X output signal to tablet X axis.  
 NYSTB TAC2.NTAC3.NTAC4.CL.  
 Tablet Y output strobe. Y register data on TAMO-9 multiplexer output lines.  
 YSTUD TACI .NTAC3.NTAC4.CL.  
 Y U/D counter strobe. Generate up clock if TUP.TAYANT or down clock it NTURNTAYANT.  
 NYTAOS SET RESET +YTAB signal TAMOVTAYCL. NTAMOVTAYC L.  
 Y overscale output Overflow condition. No overflow condition. Y output signal to tablet +Y axis.  
 Y output signal to tablet Y axis.  
 What is claimed is:  
 1. An electrostatic digitizing system comprising: an 60 lus and to said first circuitry and including a counter for controlling the digital contents of the registers in accordance with the position of the stylus on the tablet surface and for controlling said exciting potentials as a function of the position of the stylus on said surface.  
  2. The electrostatic digitizing system defined in claim 1, in which said digital tablet includes a first series of electric wires extending in spaced and parallel relationship across the plane surface; first resistor means interconnecting the wires of the first series; means for intro-