Digital frequency-shift keying receiver
United States Patent Carlow et al.  
 [111 3,879,665 Apr. 22, 1975 l l DiGllTAL FREQUENCY-SHIFT KEYING Primar)- E.\&#39;uminer-Robert L. Griffin RECElVER Assistant E.\&#39;an1inerMarc E. Bookbinder Inventors Earl Fred Carlow Scottsdale, Attorne Agent. or Firm-Vi ncent J. Rauner; Kenneth Harold Garth Nash. Tempe. both of Stevens Ariz.  
 [73] Assignee: Motorola, Inc., Chicago. Ill. [57] ABSTRACT 22 Filed; June 2 7 A digitally implemented frequency-shift keying receiver receives an input periodic oscillation signal of a Appl&#39; 374594 first frequency; designated a binary 1&#34; and of a second frequency. designated a binary 0&#34;. A unidirec- 52 us. cl 325/320; l78/66 R; 178/88; Iimwl Pulse is generated each time the input Signal 5 37 329 0 passes through a reference voltage. either positive 51 Int. Cl. H04] 27/14 going or negative going- The time between pairs of 58 Field of Search 325/30. 45, 320. 344, 349. these Pulses is measured y Starting free running 5 7; l78l66 R 66 A 7 g; 79 2 p counter with a first pulse and by stopping and re- 179/2 E; 329/104, 126, 128 starting the counter with a second pulse. If the time between two of these pulses is sufficiently long. an up- 5 References Cited down counter counts in one direction and if the time UNITED STATES PATENTS is sufficiently short. it counts in the other direction. a o 7 The up-down counter. by providing a prescribed&#39;num f g ber of counts in either direction to reach a threshold. 147 367 3/197 Sm 5555 effectively filters the input signal. An output stage. re- X Q 5 5 Giles sponsive to the threshold of the up-down counter. pro- 3.660.771 5 1972 Buluguni ct ul... 325/320 Vides either a binary 1 of binary 31170.250 6 1972 F k&#39; 325 320 I m m 6 Claims, 2 Drawing Figures 20 I4 22 f A B it 5 O DECODER I2 l3 DETECTOR COUNTER UILDOWN D u COUNTER l6 &#39;9 Bar &#39;DEcoor-:R 5 9 UP R DECODER DIGITAL FREQUENCY-SHIFT KEYING RECEIVER BACKGROUND OF THE INVENTION 1. Field of the Invention Frequency-shift keying receivers receive periodic input signals of a first frequency and of a second frequency, providing a binary 1 output in response to the first frequency input and a binary in response to the second frequency input. More particularly, the FSK receiver of this invention handles the incoming signals in digital fashion.  
 2. Prior Art In the past, the conversion of an input signal of two different frequencies into output binary l or 0 (often referred to as mark and *space&#34;, respectively) is accomplished in largely analog fashion.  
  For example, in a well known circuit, a pair of selective bandpass filters are each tuned to one of the two input frequencies. A comparison circuit compares the output energy of the filters and if the energy in the 1 bandpass filter is greater than the energy in the 0 bandpass filter, the output is given as a l. The converse is true for a O indication. This circuitry requires high Qs for each filter and that its parameters remain extremely stable under shock, temperature and vibration conditions. Components required are high precision and therefore expensive. Factory adjustments are required to align the filters and periodic maintenance is performed to keep the center frequency of each properly positioned.  
  Another approach is the zero crossing detector which relates numbers of zero crossings per unit of time to either a l or a 0 output. This circuit is not limited to 0 volts of course, but is applicable to any reference voltage. A linear filter removes the high frequency components from the detected signal and passes only the l 0 data. The output of the filter, however, does not have sharp data transitions and a limiting amplifier or comparator must be added.  
  A more recent and popular circuit is the phase locked loop which automatically locks onto the received signal and indicates l s and O s by levels in the control voltage. This circuit requires precision components and the accuracy of the center frequencies designed into the system is in the order of l to 5 percent. Also, the output does not have sharp data transitions and a limiting amplifier or comparator is required.  
  Our invention accurately measures each half period of the cycle of the incoming signal and determines whether the half cycle is a l or a O. A plurality of these half cycles are averaged together via a digital filtering technique to statistically establish that the incoming signal is indeed a l or a O. The need for costly, precision components is greatly reduced and the system accuracy is improved.  
 BRIEF SUMMARY OF THE INVENTION A frequency&#39;shift keying (FSK) receiver receives an input, periodic oscillation signal, of a first or a second frequency representing a l or a 0, respectively. A threshold detector detects each crossing of a reference potential made by the incoming signal, whether negative or positive going, and provides a pulse for each such crossing. A crystal-controlled oscillator provides accurate clock pulses to a free running counter. The counter starts counting the clock pulses whenever a pulse from the threshold detector is produced. The  
 count is immediately stopped and re-started when another pulse from the threshold detector is produced.  
  A prescribed count of the counter is translated with the output of the translator serving as a set input to a flipflop. If the incoming signal is of a higher frequency, the prescribed count is never reached and the flipflop never set, indicating a 1 frequency. If the input signal is of a lower frequency, the prescribed count is reached and translated, and the flip-flop set, indicating a O input. The prescribed count represents the geometric mean between the two input frequencies.  
  The flip-flop therefore provides a voltage level output representative of a binary 0 when it has been set, the voltage level being used to cause an up-down counter to count in an up direction. As each input 0 is received, the counter counts up an additional count until a prescribed threshold is reached. In this manner, digital filtering is effectively provided. In like manner, when a l is received at the input, the flip-flop is not set and it provides an output voltage level representative of an input 1. This voltage level causes the up-down counter to count in a down direction. Each time a 1 is received at the input, the counter counts down until a negative threshold is reached thus providing an effective filtering action for the 1. Both the positive and the negative thresholds of the up-down counter are decoded, and an output stage whose output is either a first voltage level representative of a binary 1 or a second voltage level representative of a binary 0, is either set or reset determined by the particular threshold.  
  A primary object of this invention is to provide an F SK receiver which digitally processes incoming analog signals.  
  Another object is to provide an FSK receiver that digitally filters the incoming analog signal.  
  Still another object is to provide an FSK receiver that does not require high accuracy components.  
  Still another object of this invention is to provide an FSK receiver that is susceptible of implementation using integrated circuit techniques.  
  These and other objects are evident in the detailed description that follows.  
 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the FSK receiver. FIG. 2 illustrates idealized waveforms present at various points in FIG. 1.  
 DETAILED DESCRIPTION The FSK receiver 10 of FIG. 1 is shown in block form. Input terminal 11 is connected to threshold detector 12 to receive input periodic oscillation signals and to produce pulses every time the input signal crosses a reference potential, irrespective of crossing. Threshold detector 12, in the preferred embodiment, is a well known zero crossing detector. The output from threshold detector 12 is connected via line 21 to counter 13. Counter 13 is a binary counter provided with a crystal controlled oscillator to produce pulses for counting. In the preferred embodiment, the crystal controlled oscillator has a frequency of 1 MHz, thereby producing one pulse every microsecond. Counter 13 is of the resettable type and reset each time a pulse from threshold detector 12 is received. An output from counter 13 is decoded by decoder 14. A predetermined count causes decoder 14 to produce an output and to apply that output via line 22 to the set input of flip-flop 20 which in turn supplies an indicia signal, indicating whether the input signal is a l or a 0. Output of flipflop 20 serves the indicia signal as a conditioning input to up-down counter which also has an input from threshold detector 12. The reset input to flip-flop comes from threshold detector 12. The up-down counter 15 has a down decoder 16 to provide a set input to flip&#39;flop 18, and an up decoder 17 to provide a reset input to flip-flop 18. The Q output of flip-flop 18 provides the output of the circuit on line 19.  
  The components all shown in block form in FIG. 1 are all well known, available circuits and need not be described in detail. The description of the operation of the receiver that follows, will further describe the operation of these available components.  
 OPERATION Referring to both FIGS. 1 and 2, the input periodic oscillation signal is shown as signal A in FIG. 2. Signal A has been shaped and limited by stages not shown but also could be a sine wave having a plurality of cycles at one frequency representative of a binary l and having a plurality of cycles of another frequency representative of a binary 0. In the same manner, signal A is shown having a first frequency between times 0 and 3, representing a binary l, and also referred to as mark frequency. Then from time 3 through time 6 a second, lower frequency is shown representing a binary O, which is also referred to as space frequency. In the preferred embodiment, the 1 frequency is 1270 Hz and the 0 frequency is: 1070 Hz.  
  The plurality of cycles representing a l and representing a 0 is dictated by data or bit rates previously established in the industry, together with the frequency (f,,,) representing the binary l and the frequency 0&#34;,) representing the 0 frequency. A typical bit rate is in the order of 300 bits per second, which is not intended to be accurately represented by signal A, signal A being merely illustrative.  
  Signal A is differentiated and rectified by the threshold detector&#39;producing a unidirectional pulse at each crossing of a reference voltage, as indicated by signal B. A unidirectional pulse for purposes of this specification is defined as a brief voltage or current excursion in one direction from a reference level. The half cycle period off equals l/2f,,, and forf, equals 1/2fl.  
  In this preferred embodiment, f equals 1270 Hz and 1&#34;, equals 1070 Hz with corresponding half cycle periods equal respectively, to 393.5 microseconds and 467.5 microseconds (rounded off to the nearest 0.5 microsecond). The geometric mean is the selected point of discrimination and is the square root of the product of 393.5 microseconds and 467.5 microseconds, which equals 429 microseconds. 429 microseconds is used as a threshold setting in the counter 13, which in binary notation equals 1 10101 10]. Those binary positions which contain ls when the number is reached are monitored by decoder 14 which sends out a set signal to flip-flop 20 when all of those bits are 1. When the incoming signal is a I, however, the counter will never get to a count of 429 because the half cycleperiod is only 393.5. The counter, as described earlier, counts 1 every microsecond and therefore when the counter reaches a count of 393, another pulse from threshold converter 12 re-starts thecounter without it ever having reached a count of 429 and therefore without ever having set flip-flop 20. In the case of a 0 input, the  
 counter reaches 429, resulting in the setting of flip-flop 20. The counter continues to count up to 467 at which time a pulse from the threshold detector 12 restarts the counter and resets flip-flop 20. When the Q output of flip-flop 20 is a 0 as a result of flip-flop 20 not having been set, up-down counter 15 counts down a selected number of counts as shown in the up-down counter curve of FIG. 2. When a count of4 is made, from 4 to 0, the counter remains at 0 until it receives an up-count command. The up-count command is received when the output Q of flip-flop 20 is a 1 as a result of flip-flop 20 having been set. The C signals of FIG.&#39;2 illustrate the setting and clearing of flip-flop 20 when a 0 signal is received at input 11. When C is .a l coincidentally with a B signal, the up-down counter is commanded to count up. As can be seen in FIG. 2, the counter counts from 0 to 4 and remains at 4 until commanded to count down by an absence of a C pulse. The up-down counter is, effectively, a digital filter. By setting a threshold count, noise is eliminated. Because of the difference in frequencies between f,, and f,, the count down is not equal in time to that of the count up and therefore there is some bias distortion (exaggerated in FIG. 2 for illustrative purposes). Following is a table of other commonly used FSK frequencies together with the geometric mean for each pair.  
 TABLE I FSK FREQUENCY PAIRS Geometric Mean Rounded off to k sec.  
  The down decoder 16 decodes a zero count of the up-down counter 15 and sets the output flip-flop 18. The up decoder 17 monitors the up-down counter 15, in the preferred embodiment for a count of four at which count the flip-flop 18 is reset. The output waveform D on line 19 is shown in FIG. 2.  
  The particular available circuits used as shown in FIG. 1 are not intended to limit this invention. For example, a zero crossing detector need not be used. The input signal can be differentiated and rectified, producing the signal train B of FIG. 2. The flip-flops may be simple latch circuits and, of course, many counters are available of the reset type and of the up-down type. Decoders are also well known. Therefore, the spirit and scope of this invention contemplates implementation through a wide variety of known circuits.  
 We claim:  
  1. A digital frequency-shift keying (FSK) receiver including shaping means for receiving an input periodic oscillation signal of a first frequency, designated a binary 1 and of a second frequency, designated a binary 0, comprising:  
 a. threshold detector means connected to the shaping means for producing a plurality of unidirectional pulse position signals whenever a positive going or a negative going portion of the periodic oscillation signal passes through a prescribed potential;  
 b. timing means connected to said threshold detector means for measuring the time between the pulses produced by the detector means to provide indicia signals representative of whether the input signals are of the 1 or 0 frequency; and  
 c. output means connected to said timing means and responsive to the indicia signals for providing on a single output line an output pulse of one polarity if the input signal is at the binary 1 frequency and an output pulse of the opposite polarity if the input signal is at the binary 0 frequency.  
 2. The FSK receiver of claim 1 wherein said timing means further comprise:  
  a. resettable counter means connected to said threshold detector means for counting digital pulses of a predetermined frequency in response to a first pulse position signal, and being responsive to a second pulse position signal for resetting to a first predetermined state, said resettable counter means being responsive for generating a counter output signal upon reaching a predetermined count,  
 b. indicia signal generating means connected to said resettable counter means and being responsive to the counter output signal for providing an indicia signal of a polarity representative of a binary 1 upon the generation of a counter output signal, and for providing an indicia signal of a polarity representative of a binary 0 in the absence of a counter output signal.  
 3. The FSK receiver of claim 1 wherein the output means further comprise:  
 a. up-down counting means connected to said indicia signal generating means and being responsive to the indicia signals for counting in one direction when the indicia signal represents a binary 1 input signal and in the other direction when the indicia signal represents a binary 0 input signal;  
 b. threshold decoding means connected to said updown counting means for providing a first voltage level representative of a binary 1 input in response to a predetermined count from the up-down counting means in one direction, and for providing a second voltage level representative of a binary 0 input in the other direction; and  
 c. bistable output means connected to said threshold decoding means for providing a binary 1 output when set by the first voltage level and a binary 0 ouput when set by the second voltage level.  
 4. The FSK receiver of claim 2 wherein the output means further comprise:  
 a. up-down counting means connected to said indicia signal generating means and being responsive to the indicia signals for counting in one direction when the indicia signal represents a binary l input signal and in the other direction when the indicia signal represents a binary 0 input signal;  
 b. threshold decoding means connected to said updown counting means for providing a first voltage level representative of a binary 1 input in response to a predetermined count from the up-down counting means in one direction, and for providing a second voltage level representative of a binary 0 input in the other direction; and  
 c. bistable output means connected to said threshold decoding means for providing a binary 1 output when set by the first voltage level and a binary 0 output when set by the second voltage level.  
 5. The FSK receiver of claim 2 wherein the resettable counter means further comprise:  
 a binary counter for counting the digital pulses, a decoding circuit connected to the binary counter and to said indicia signal generating means for producing a binary counter output signal when the binary counter reaches the predetermined count, and said indicia signal generating means being responsive to said binary counter output signal.  
 6. The FSK receiver of claim 4 wherein the resettable counter means further comprise:  
 a binary counter for counting the digital pulses, a decoding circuit connected to the binary counter and to said indicia signal generating means for producing a binary counter output signal when the binary counter reaches the predetermined count, and said indicia signal generating means being responsive to said binary counter output signal.