Digital system forming a frequency multiplex system
United States Patent [191 [1 1 3,875,340  
 Roy et al. 5] Apr. 1, 1975 i 1 DIGITAL SYSTEM FORMING A OTHER PUBLICATIONS FREQUENCY MULTIPLEX SYSTEM 7th International Conference on Communications,  
 [75] Inventors: Marie-Annick Roy, Antony; Alain (j p n-i [)esombre, both f Montreal. Canada, June. 71, &#34;An Exploratory Termi- Paris, all of France y Freeny at [73] Assignee: Compagnie Industrielle des Telecommunications Cit-Alcatel, Primary Examiner-David L. Stewart Paris. France Attorney Agent, or Firm-Craig &amp; Antonelli [22] Filed: July 3, 1973 3 Foreign A fi ti p Data Digital system which, from n voice frequency chan- Jul). Frmcc 74032 nels, furnishes a band of a frequency multiplex system, for example, a primary base group of twelve channels [s2] U 8 Cl 179/15 FD 79/15 FS of4 kHz each, covering the band 60 108 kHz. and [&#39;51] H04j &#34;04 comprises between an analog-digital input converter [-58] Field &#39;5 F5 receiving the voice frequency channels and a digitalnglls analog output converter emitting the desired band. only members of the digital type operating on digital [56] References Cited information or data words.&#34;  
  UNITED STATES PATENTS 9 Claims. 5 Drawing Figures 3.676.598 7/l972 Kurth l79/i5 FD lo -e nu convearsn k COMMUTATOR I t l COMMUTATOR T m sinmt I 1 y I (P) i E u i /]2Mu|.ru=i.|En/toe|c i o&#34; 9 5 i (2m i surrsa x- \I (2% CD59&#34;. 14 \/-1 30) ism 16 OR GATE hilt;  
 I {BUFFER}! 8 -4 (U (2Fh) cusokt 22 Du) 4 on care 5 t 20 (2m i 5&#39; {(P) /MULTIPLIERILOGIC E (Fh) (Fh) grh) 24 27 i, b. t sinukt m COMMUTATOR LII-ER PATENTEU 975 SziZET 2 [IF 5 LOGIC MULTIPLI ER DIGITAL v 7 FILTER DIGITAL SYSTEM FORMING A FREQUENCY MULTIPLEX SYSTEM The present invention pertains to the field of apparatus which effect the grouping of a certain number of telephone channels within a given frequency band. It relates to a system which furnishes from n voice frequency channels a hand of a frequency multiplex system. for example a primary hase group of twelve channels each having 4 kHy covering the (\(l I80 kHz hand. and comprises. between an analog-digital input converter receiving the voice frequency channels and a digitalsmalog output converter emitting the desired hand. for example a primary hase group. only digital metnhers operating on information or data words.&#34; The application envisaged is the provision of frequency multiplex systems for telephone transmission.  
  It is known to generate a frequency multiples system. or a portion of a frequency multiplex system. for example a primary hase group. by two modulation steps: a first modulation. or premodulution. which furnishes premodulation channels all having the same disposition in the spectrum. and then a second modulation. which has the effect of transposing each premodulated channel into one of the channels of the primary hase group taken as an example. or twelve channels each occupying 4 kHz hetvveen (i and I0? kHl. Such manipulations are effected by means of modulators and associated filters.  
  One particularly advantageous means for producing transposed channels is a modulator with two paths in parallel. one of which comprises a lirst modulator receiving one voice frequency channel and moreover a current ofcos ,1. (II I &#39;rrFI followed by a low-pass filter and by a second modulator supplied furthermore with a current ofcos IL -I. (1 I I 1W2). and the second path of which comprises a third modulator receiving a current of sin 12,1. followed hy a low-pass filter. and by a fourth modulator supplied with a current of sin $2 1. the output currents of the second and of the fourth modulators heing added in order to furnish at the output the transposed channel.  
  The principal advantage ofa modulator with transposition of two paths of this type resides in that. since the carrier currents are dephased hy 1r/2 from one hranch to the other. the products of the second modulation are found to he dephased at the output alternately by 11&#39; or /ero. A simple adding means then makes it possihle to restore the desired products.  
  The present invention applies this principle to a de vice having a digital operation between an analogdigital input converter and a digital-analog output converter by manipulating words of a predetermined numher of hits. for example p hits. each of which represents a coded digital value. but while the simple transposition of the analog into the digital method would require two parallel paths of digital operation. the present invention. making use of properties peculiar to the digital operation. employs only a single path. and the only price paid for this simplification of the apparatus is that the frequency of the clock which serves for setting the frequency of operation of the system must he douhled.  
  The present invention will he explained in further dctail hereinafter with reference to the accompanying drawings. wherein:  
  FIGv I is a schematic diagram of the overall multipleving system according to the present invention.  
 Ill  
  FIG. 2 is a more detailed diagram of the multiplier/- logic and buffer memory portion of the system according to FIG. 1:  
  FIG. 3 illustrates the spectral composition of the different signals;  
  FIG. 4 is a schematic diagram showing the application of an implement according to the present invention to a multiplexing system of a more elevated order. and  
  FIG. 5 is a diagram of the application of two systems according to the present invention to a multiplexing system of a higher order.  
  In order to describe the basic concepts of this invention. the system of FIG. I provides for the multiplexing of II II voice frequency channels covering a total width of 4 kHz into a primary hase group of (i0 I08 kHY.  
  The values of the parameters are as follows: Lowfrequency spectrum 300 3.400 H7; band width II 3.l00 Hr: first modulation frequency FI 300 3.400/2 L850 Hr. second modulation frequencies/1 ti kH1; /2 ll) kH/1flv&#39; 2 l\&#39;.-l) lv&#39;HI&#39;. .jii kHz; with It being equal to the order or sequence of the channel hetween I and II II.  
  The sampling frequency for a group having a width of 48 kHr is selected to he equal to I-Iv l 1&#39;. kHl l-l X 3 Jv The n channels I ton are applied to an analog-digital converter [0 on a time-sharing hasis. operating at a clock frequency H: I: X Iii I: X l 12 kHv. On each ofthe n outputs of the converter III each level sampled is coded by p hits in parallel. for example. it may he assumcd that p II.  
  A step-hy-step commutator II operating at a fre quency [-71 i I: X I I1 kHv picks up in succession the coding with p hits of each of the 12 channels in the course of a frame&#34; period of 8.) as III II kHYl.  
  The movahle contact of the commutator II applies a signal X. .tl) to one input of a suhassemhly I2 which comprises essentially a multiplier and a logic circuit which receives the output of a commutator I3 operating at a frequency of IN: 24 X I I2 kH/ and which furnishes during alternate times a signal cos III I,- and a signal sin !Il!,-. wherein II, 2 7T I&#34;l.  
  The period of I&#34;! 1.850 Hr is 540 us. the frame period heing 8.) us. and there results therefrom a total numher of the values of cos II equal to a little more than o0 per period l/I-l. and as many l&#39;or sin Ila. Each of these values is maintained identical during a frame period of 8.) us. These values are coded in p hits. and it will he assumed for example that p 12.  
  At the output of the sul&#39;iassemhly l2 where in principle 2p hits will come to he present. preferahly the p hits of strong weight are selected. The suhassemhly I2 is also set to a frequency of 2H1. It has two outputs on two buffer memories I4 and I5. From the first one there issues a signal i (I). a product of .v (it by cos 11,1; from the other one there issues a signal .v (I). a product of A (I) by sin ll i.  
  The signals .t;i (I) and i (I) are applied via an ()R cireuit [6 to the input of a conventional digital filter I7 having a pass-hand of Fl t 3/2. The digital filter l7 delivers at the output of a third buffer memory [8 a signal .v (I) and at the output of a fourth buffer memory 19 a quadrature signal .i. t l). the two signals heing applied via an OR circuit 20 to one input of a suhassemhly 2|. having the same construction and operation as the suhassembly 12. On another input. the subassembly 21 receives the output of a commutator 22 which. during a frame period of 8.9 as. picks up l2 values of cos (a r and l&#39;. values of sin w, A varying from l to II.  
  For a primary base group (ill 108 kHy. the values of]. (alt/Z vary from (w to 50 kHz. from 4 to 4 kH All of the members 12 to 22 are operated at a frequency of 2Fh.  
  From subassembly 2! issues a signal with 1 bits 1;. (I I. and the signal in quadrature R. (ll. The first signal at the output of a buffer memory 23 and the second signal are applied to the inputs of an adder 24. From adder 24 issues a signal n, I] which is applied to a digital-analog converter 25.  
  The members 23. 24 and 25 operate at a frequency Fh. To the output of analog bandpass lilter 26 there is provided at terminal 27 a primary base group 108 kH The operating frequency is marked beside each member in FIG. 1.  
  Fl(i. 2 is a more detailed diagram of the members l2. l4 and IS. The subassembly 12 comprises a multiplier M] which receives on the one hand the p bits of the signal (I). the coding of a channel sample coming from the commutator 1] (FIG. ll. On the other hand. the multiplier Ml receives by way of p ()R circuits 34 the output signals of AND gates 3|. or the output signals of p AND gates 33. which receive the output signals of the commutator 13 (FIG. 1). the gates 33 receiving the clock pulses of frequency 2Fh and the gates 3| receiving via an inverter 32 the inverse of this clock pulse signal of frequency 2Fh.  
  The buffer memory 14 comprises a first series of p AND gates 35 which receive the outputs l p of the multiplier Ml respectively. as well as the clock signal 2Fh via an inverter 37. which receives the clock signal as well as a second series of AND gates 36. each of which receives the output signal of the AND gate 35 of the saute order and the clock signal ZFh having traversed two inverters 4] and 38 in series.  
  The buffer memory I5 is constituted in an exactly identical fashion with a first series of AND gates 39 receiving the clock signal 2Fh and a second series of AND gates 40 receiving via the inverter 4| the inverse of the clock signal 2Fh.  
  p ()R circuits 16 (FIG. I) each receive an output of the buffer memory I4 and the output of the same order of the buffer memory 15. The outputs of these ()R circuits 16 are applied to the input of the digital filter 17. At the output of the numerical filter 17 two buffer memories l8 and 19 are connected exactly in the same fashion as the memories 14 and IS are connected to subassembly I2. This arrangement allows for timesharing of the equipment for each of the two terms in quadrature A}. (I) and i (1). .v (r) and L (1). respectively.  
  At the output of the second multiplier contained in suhassembly 2|. a single buffer memory 23 suffices for applying the terms x (I and i (1) to the adder 24. The members 24 and operate at a frequency Fh.  
  FIG. 3 shows the spectral composition of the different signals. In order to simplify the diagram. the hand width W301) 3.40GHz) of the low frcquency signal has been replaced by b (0 4.000 H7). or Fl h/Z. which changes nothing in principle.  
  The succession of operations carried out by the members of FIG. 2 is understood by taking into account the Fourier transformation which causes a spectrum .\l  
 J to correspond to any signal .\(t) cited above.  
  Five graphs provide the spectra .i ll w). ml. or .i lj w). (j ml or .iqtj w). i w). or .i lj w). and w) v\ -,{j (u) .r tj w] of the signals (r) of the same index. Marked on the graph .\;.lj w) is the response of the numerical filter 17 (curve Cl and on the graph .r (j w] there is pro\ided the response of the analog filter 26 [curve C2). It will be noted that the channels are differentiated solely from the second modulation by the carriers fl to fn.  
  FIG. 4 shows schematically the application of a multiplexer according to the present invention to the generation of a secondary group of channels covering 312 553 kH7 from two synchronized PCM frames. with 32 channels each. of which 30 are information channels and two are auxiliary channels. For a pass band of 240 kHz. the sampling frequency of the multiplexer must be greater than 480 kHz, and it has been assumed to be equal to 73 X 8 I 584 kHz.  
  Two PM frames. T, and T are provided with a frequency of 2,048 kH/ (32 channels sampled at the fre&#39; quency of 8 kHz. definition of 8 bits). The same clock H serves for setting the frequency for the two synchronized frames at the input. [Zach of these frames is received in a buffer memory (M,. M each containing 30 channels. It is necessary to pass from the PCM frequency to the input frequency of the multiplexer which. for (10 channels. is equal to (it) X 584 kHv. This is done by means of a subassembly G comprising at the input a commutator K. an assembly R of 73 delay lines T in cascade. of l.7 as each. whose outputs are collected by an ()R circuit J. The sub-assembly (i is operated at a frequency of (10 X 584 kHl.  
  A subassembly 0 corresponding to the members l2. l3 23 of FIG. I operating at a frequency of 584 X (it) X 1 kH/ is connected to the output of OR gate J. The frequency of the first modulation Fl is always equal to [.850 Hz. The frequencies of the second modulation. E fk at the number (it). are graduated from 34 to 271) kH/, from 4 to 4 kH/..  
  The subassembly is followed by a subtraction and nonaddition member 28. like the member 24 of PIG. I. so as to take into account the desired sense or direction of the modulation. which is here direct. instead of the inverted sense or direction in the primary base group. The subtraction member 28 is followed by a digitalanalog converter 2) and by a filter 30 with a passband of 3 l 2 552 kH/ at the output of which the secondary group is found at terminal 30a.  
  The members 28 and 2) are operated at the frequency of (it) X 584 kHv. The two synchroniycd input PCM framesT, and T are thus directly transposed into a secondary group of a frequency multiplex. The operating frequency has been indicated beside each member.  
  FIG. 5 has reference to the direct transposition of two PCM frames T, and T,, of 32 channels each. which are not synchronized. into a secondary group of 60 channels 312 552 kHz of a frequency multiplex system.  
  Each frame is set in frequency by its own clock HI and Hlll. Each of these frames is received in the memory MI and MI].  
  The equipment comprises two unitary multiplexers. one formed by elements (ll. Ql. 28l and 29]. the other of eletncnts (ill. OH. 28 and 29]]. These members or subassemblies have a structure and operation analo gous to the elements (i. Q. 28. 29 of FIG. 4. Elements (il and (ill are operated at a frequency of X 584 kHv. elements ()l and OH at a frequency of 2 X 30 X 584 kHz. and elements 28L 28H. 29&#34;. and 29&#34; are operated at a frequency of 30 X 584 kHz. At the output of the band-pass filter 30 there is found at terminal 3011 the secondary group 3 l 2 552 kHz. The operating frequency has been indicated beside each member in FIG. 4.  
  While we have shown and described several embodiments in accordance with the present invention, it is understood that the same is not limited thereto but is susceptible of numerous changes and modifications as known to a person skilled in the art. and we therefore do not wish to be limited to the details shown and described herein but intend to cover all such changes and modifications as are obvious to one of the ordinary skill in the art.  
 What is claimed is:  
  l. A digital system for forming a frequency multiplex group from n incoming channels, operated at a sampling frequency Fs. comprising analog-digital conversion means receiving said 11 incoming channels and furnishing digital values .t!l at the output thereof, first multiplication means for multiplying said digital values .r- .(Il by alternate digital values of cos Ila-F and sin 2111&#34;,! and furnishing signals .Yggt} and Rat!) in quadrature. operating at the frequency 2/) Fs. digital filtering means for receiving in common said values .\1-,(t) and i t!) and furnishing digital values .r and .iql!) in quadrature. second multiplication means operating at the frequency 2n Fs and receiving in common said quadrature values .\,(I) and .i.(!) for multiplying said values alternately by digital values of cos Err/L! and sin 211151. wherein It varies from l to :1. addition means operating at the frequency n Fs and receiving output signals .\;,l I and .t -.(1) in quadrature from said second multiplication means for furnishing signals .\&#39;,;(t). a digitalanalog converter connected to the output of said addition means. and an analog band-pass filter having a bandwidth of fill Hi8 kHv connected to the output of said digital-analog converter.  
  2. A system according to claim 1. characterized in that said digital filtering means is associated with an input logic circuit operating as a buffer memory for the alternate application of said values Xgt&#39;) and .t tl) in quadrature to said filtering means. and with an output logic circuit operating as a buffer memory for the alternate extraction of the two series of products in quadrature from said filtering means.  
  3. A system according to claim 2. characterized in that said second multiplication means is associated with an input logic circuit operating as a buffer memory for the alternate application of said values rat) and .ial) in qtuldrature to said second multiplication means. said addition means being connected to said second multiplication means by means of a direct connection by means of a single logic circuit operating as a buffer memory.  
  4. A system according to claim I. further including means for repeating n times the same value of cos Z&#39;n&#39;F I; and n times the same value of sin ZTrF I; at the input of said first multiplication means.  
  5. A system according to claim 4. further including means for selectivelychanging said sampling frequency Fr connected to the input of said analog-digital conver sion means.  
  6. A digital system for forming a frequency multiplex group from two non-synchronized PCM frames. comprising first and second system groups connected to said PCM frames. respectively. said first and second system groups terminating in common at a single bandpass filter. each system group comprising means for changing the sampling frequency of the system. analogdigital conversion means receiving said n incoming channels and furnishing digital values .Ygl) at the output thereof. first multiplication means for multiplying said digital values I) by alternate digital values of cos 217F I and sin IrrFa and furnishing signals ml!) and f t!) in quadrature. operating at the frequency 201 Fr. digital filtering means for receiving in common said values AMI) and i t!) and furnishing digital values 14(1) and fat) in quadrature. second multiplication means operating at the frequency In Fx and receiving in common said quadrature values 1) and .f&#39;,(! l for multiplying said values alternately by digital values of cos 211 and sin Err/ill. wherein it varies from I to n. addition means operating at the frequency n Fs and receiving output signals .\&#39;.-,(I) and -,(t) in quadrature from said second multiplication means for furnishing signals .\&#39;.;(l). and a digital-analog converter connected to the output of said addition means.  
  7. A system according to claim 6. characterized in that said digital filtering means is associated with an input logic circuit operating as a buffer memory for the alternate application of said values .\;,(I) and id!) in quadrature to said filtering means. and with an output logic circuit operating as a buffer memory for the altcrnate extraction of the two series of products in quadrature from said filtering means.  
  8. A system according to claim 7. characteriled in that said second multiplication means is associated with an input logic circuit operating as a buffer memory for the alternate application of said values .utl) and .i tl) in quadrature to said second multiplication means. said addition means being connected to said second multiplication means by means of a direct connection by means of a single logic circuit operating as a buffer memory.  
  9. A system according to claim 6. further including means for repeating n times the same value of cos 21rF i,- and n times the same value of sin Zn-Fa, at the input of said first multiplication means.