Integrated circuit linear time delay extender for static relays
BACKGROUND OF THE INVENTION 
     The present invention relates to static relays and more particularly to a novel dual-comparator and clamp circuit for simplified linear adjustment of the static relay time delay period over a multiple order of magnitude range without altering the basic charging curve of the delay network. 
     The present invention is an improvement of the static relays described and claimed in U.S. Pat. Nos. 3,319,127, issued May 9, 1967; 3,573,555, issued Apr. 6, 1971; and 3,766,436, issued Oct. 16, 1973, all of which are assigned to the assignee of the present invention. 
     The above-indicated patents describe static relay devices having an inverse time-current characteristic and which replace electromechanical relays which were previously employed to obtain the desired characteristic. The static relay devices of the above patents essentially comprise a pick-up circuit which is connected to the circuit being monitored; a timing circuit which is charged from the pick-up circuit when the circuit being monitored develops or otherwise generates an output which exceeds a known threshold value according to a predetermined inverse current-time characteristic so as to activate the pick-up circuit; and a tripping circuit which is operated in accordance with the inverse time-current relationship of the timing circuit so as to be tripped when the output of the timing circuit reaches the tripping threshold of the tripping circuit. The characteristic of the timing circuit is related to the circuit being monitored such that when the condition of the circuit being monitored exceeds a predetermined value over time intervals associated therewith a tripping operation is performed. It should be understood, in this respect, that overcurrent conditions of small magnitude must persist for a greater time interval to initiate a tripping operation and conversely overcurrent conditions of large magnitude will cause faster time-out of the timing circuit to cause initiation of the tripping operation. 
     It is desirable to provide such static relays with the capability of being adjusted over extremely large time delay ranges of several orders of magnitude, e.g., 1000:1 or 10,000:1. 
     One technique, described in U.S. Pat. No. 3,573,555, utilizes a variable duty-cycle free-running multivibrator circuit powered by the line being monitored, having &#34;on&#34; and &#34;off&#34; time periods which are adjustable over a substantial time range without altering the desired curve shape of the time-current characteristic. This adjustment, in accordance with an adjustable resistance element and a time dial setting knob provided therewith, resulted in an impractical and non-uniform inverse marking of the potentiometer dial and was extremely complex and tedious to design, assemble, and use. A later technique, described in U.S. Pat. No. 3,766,436, utilizes a variable duty-cycle free-running multivibrator circuit powered by the line being monitored, having a substantially constant &#34;off&#34; time interval and adjustable &#34;on&#34; time intervals to provide a substantially linear adjustable time range extension ratio and time dial therefor. 
     However, the variable duty-cycle clamp circuit of U.S. Pat. No. 3,766,436 has a maximum adjustment range of approximately fifteen times the base charging rate of the basic time delay network. To obtain a 5% unit-to-unit repeatability of the time extension previously realized by the use of this multivibrator, the circuit of the last-mentioned patent requires closely matched transistors and capacitors, which matching procedure is extremely tedious and costly. 
     BRIEF DESCRIPTION OF THE INVENTION 
     It is desirable to extend the charging time of the basic resistance-capacitance timing circuit over a range of at least four orders of magnitude greater than the base charging rate while maintaining a linear extension ratio adjustment and without requiring the use of closely matched components in the time delay extender, thus simplifying the design, assembly, and operation of the device while lowering the cost thereof. 
     The integrated circuit linear time delay extender of the present invention employs a dual-threshold and clamp circuit design having a fixed resistance element whose resistance provides substantially constant &#34;on&#34; time intervals and an adjustable resistance element whose resistance may be simply and readily adjusted by an adjustable control having linear (i.e., equally spaced) graduations or markings, which adjustable resistance provides adjustable &#34;off&#34; time intervals resulting in an adjustable duty-cycle which makes it possible to provide a static relay having a multiple-order-of magnitude time delay adjustment range adjusted by setting an essentially completely linear time dial. The dual-threshold and clamp design, contrary to the design employed in the abovementioned U.S. Pat. Nos. 3,573,555 and 3,766,436, provides time extension ranges of at least several orders of magnitude greater than the base charging rate of the basic time delay network and, contrary to the design employed in the last mentioned U.S. patent, provides substantially constant &#34;on&#34; time intervals and adjustable &#34;off&#34; time intervals. 
     Accordingly, a primary object of this invention is to provide novel means for extending the time delay range of a static relay. 
     Another object of this invention is to provide novel means for such extension over a range of several orders of magnitude. 
     A further object of this invention is to provide a novel means having an adjustable &#34;off&#34; timing interval for such extension. 
     A still further object of this invention is to provide such novel adjustable time delay means which significantly simplifies both the design and operation of a static relay. 
     It is still another object of this invention to provide a novel variable duty-cycle dual-threshold and clamp circuit to enable such time delay extension means. 
     These as well as other objects of the invention will become apparent from the following description of the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a static relay of the type described in U.S. Pat. No. 3,766,436; 
     FIG. 2 is a schematic diagram of a variable duty-cycle dual-threshold and clamp circuit in accordance with the present invention and the timing circuit portion of a static relay with which it is used; and 
     FIG. 3 illustrates the various waveshapes of the variable duty-cycle dual-threshold and clamp circuit of the present invention at circuit terminals as indicated in FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 shows a static relay of the type described in U.S. Pat. No. 3,766,436. Since this circuit is described in detail in the aforesaid patent, only a brief description of its operation will be given for purposes of simplicity. 
     If a fault or overload current is developed in any one or more of the three lines 10, 11, and 12 being monitored, the maximum voltage condition, after a.c. to d.c. conversion, appears across buses 22 and 23. The d.c. voltage, in addition to being the level to be monitored provides the operating power for the entire static relay, so that no other power source is required for operation of the device. The series connected circuit of diode 50, resistor 54 and zener diode 52, coupled across buses 22 and 23, establishes a constant voltage level (Vcc) on conductor 53. The series circuit composed of diode 95 and resistor 35 coupled across buses 22 and 23 applies a d.c. voltage level to the base of transistor 59. When this value exceeds the constant voltage reference value on line 53, transistor 59 is rendered non-conductive, causing transistor 61 to be rendered non-conductive. This removes a short-circuit condition from the cathode electrodes of diodes 80, 81, and 82, enabling the d.c. current from bus 22 through diode 76, resistor 72, and resistors 70 and 71 and diodes 80, 81, and 82 into capacitors 73, 74, and 75 to develop an output applied to the input line 86 coupled to the base of transistor 91 whose collector is coupled to the trigger electrode of a controlled rectifier 89 which is provided to conduct and hence trigger control rectifier 87 to energize a trip coil 88 when the value at line 86 reaches a predetermined threshold value which will require a longer time interval in the presence of overload currents of low magnitude and alternatively, a shorter time interval in the presence of overload current of significantly greater magnitude. 
     In order to provide a time adjustment range over which the static relay may be operated, the variable duty-cycle clamp circuit 130 is provided. The circuit operates as a free-running multivibrator having constant &#34;off&#34; time intervals whose time duration is established by resistance element 135 and capacitive element 133, and having adjustable &#34;on&#34; time intervals whose time durations are controlled by the adjustment of adjustable resistance element 137. It can be seen, for example, that increasing the resistance of adjustable resistor 137 provides an increase of the time interval of the &#34;on&#34; time of the multivibrator and decreasing the resistance of resistor 137 provides a decrease of the time interval of the &#34;on&#34; time of the multivibrator, with essentially no effect on the time interval of the &#34;off&#34; time. 
     The circuit of FIG. 1 provides a linear arrangement for the adjustment of the time delay extension of the static relay but requires that the components determining &#34;on&#34; and &#34;off&#34; time intervals, particularly the capacitors 133 and 134 and the transistors 131 and 132, be closely matched in order that the multivibrator have a 5% repeatability from one unit to the next. Additionally, the range of adjustment is restricted to a maximum extension of approximately 15 times the base charging rate of the timing network due to the design restraints placed upon the allowable ratio of the maximum-to-minimum resistance of the &#34;on&#34; time interval setting resistances 136 and 137. The flow of saturation current into the base of transistor 131 through the adjustable &#34;on&#34; time interval resistance 137 requires that the sum of the resistances 136 and 137 be always less than or equal to the product of the collector resistance 138 and the d.c. common-emitter current gain factor of the transistor 131. To insure the recovery of the time-interval-determining circuitry before the circuit reswitches, the &#34;on&#34; resistance value must be greater than or equal to 5.8 times the value of the collector resistance 138. The ratio of the maximum-to-minimum resistances indicates that the maximum extension range achievable with the prior variable duty-cycle clamp circuit is E&#39; = 0.171Xh FE  (where E&#39;  is the maximum extension ratio achievable in the prior circuit and h FE  is the d.c. common-emitter current gain of the transistor). Thus, the use of transistors 131 and 132 with a maximum h FE  of 100 will result in a maximum extension range of approximately 17 times the base charging rate of the timing network. 
     FIG. 2 shows a dual-threshold and clamp circuit which replaces the variable duty-cycle clamp circuit 130 of FIG. 1 to overcome the requirement for matched components while allowing an extension ratio in excess of 10,000 times the base charging rate of the time circuit to be realized. 
     The constant voltage reference level on conductor 53, established as previously described, charges capacitor 201 through a diode 200 and a charging resistor 202. The voltage V 1  (refer to FIG. 3) across capacitor 201 increases at an exponential rate determined by the values of the capacitor 201 and the resistor 202. This voltage is coupled to both a trigger input of a minimum determining comparator 205 and a threshold input of a maximum-determining comparator 206. Two voltage reference levels are generated from the constant voltage level on conductor 53 by a reference voltage divider comprised of resistances 207, 208 and 209. A minimum-voltage reference level, Va, is developed across resistance 207 and is coupled to the reference input of the minimum-determining comparator 205 which develops an output signal when the trigger input, being that voltage across the timing capacitor 201, has decreased to a value less than the voltage level appearing across resistor 207. A maximum-reference voltage level, Vb, developed across series-connected resistors 207 and 208, is coupled to the reference input of the maximum-determining comparator 206 which develops an output when the threshold input, i.e., the voltage appearing across the timing capacitor 201, has increased to a value greater than the reference voltage Vb. 
     The output of the maximum-determining comparator 206 is coupled to the setting input 210a of a bistable latch circuit 210, whose output is thereby set to a first voltage level and causes both discharge transistor 211 and clamp transistor 212 to conduct. The collector of the discharge transistor 211 reverse biases diode 200 by switching the anode voltage V 2  thereof to ground potential. The flow of current from Vcc is shunted through transistor 211, which also discharges capacitor 201 through adjustable resistance 213, and transistor 211 to ground bus 23. The timing capacitor voltage V 1  exponentially decreases at a rate determined by the values of the timing capacitor 201 and the discharge resistor 213 until a trigger voltage equal to the minimum reference voltage V a , across resistor 207, is reached causing the output of minimum-determining comparator 205, coupled to reset input of the flip-flop 210, to reset output 210c to the zero voltage level, whereby the base-emitter junctions of both discharge and clamp transistor 211 and 212 are reverse-biased and switched to the non-conducting state. The cut-off discharge transistor 211 removes the zero-potential short circuit from the anode of diode 200, current to flow through charging resistor 202 and forward biased diode 200 into timing capacitor 201, whose voltage V 1  begins to exponentially increase and the charge-discharge cycle just described is repeated as long as constant voltage line 53 is energized. 
     During the charging time T 1  of timing capacitor 201, clamp transistor 212 is cut off which causes the extender diode 141 to be reverse-biased and permits the timing network intermediate voltage V 4  to rise. During the discharge portion of the cycle, the collector of clamp transistor 212 goes to zero. Hence V 3  is at zero potential and the extender diode 141 is forward-biased by the application of the timing circuit input voltage V in  to its anode through resistor 72. The timing circuit input voltage V in  is the current-sensing circuit voltage on bus 22 minus the voltage drop across diode 76. While diode 141 is forward-biased, the timing circuit intermediate voltage V 4  is essentially zero and reverse-biases each of the timing circuit diodes 80, 81, and 82, thereby preventing any change of the voltage appearing across each of the three timing circuit capacitors 73, 74, and 75. Thus, it is seen that the timing circuit output voltage V out  increases at a rate determined by the time-current characteristic of the timing circuit during the charging or &#34;on&#34; time interval and maintains the previous voltage level during the discharge or &#34;off&#34; time interval, thereby increasing the time required for the timing circuit output voltage V.sub. out to rise to the trip level by an extension ratio E equal to the ratio of the total time period T 2  to the &#34;on&#34; time interval T 1 . 
     Turning now to a consideration of linearity and adjustment range of the variable duty-cycle time extender of FIG. 2; 
     Let T 0   be the base charging rate of the basic timing circuit T 1  be the &#34;on&#34; time of the variable duty-cycle time extender circuit of the invention 
     T 2  be the total time period for one cycle of the extender circuit, and 
     T e  be the extended charging time of the basic timing circuit operated on by the variable duty-cycle time extender circuit. Therefore, using the above reasoning and notation: 
     
         T.sub.e = (T.sub.2 /T.sub.1) × T.sub.0               (1) 
    
     
         e = (t.sub.e /T.sub.0) = T.sub.2 /T.sub.1                  (2) 
    
     as T 1 , the &#34;on&#34; time, is a first constant (k&#39;), then 
     
         E = (T.sub.2 /k&#39;) = k × T.sub.2                      (3) 
    
     where k is the reciprocal of k&#39; and is a second constant. 
     During the &#34;on&#34; time interval: 
     
         V.sub.1 = Va + (Vcc - Va) (1-e.sup.-.sup.t/R.sbsp.1 C)     (4) 
    
     where Vcc is the substantially constant voltage maintained on bus 53 by zener diode 52 
     201 is a capacitor having capacitance value C 
     202 is a resistor having resistance value R 1  ; when V 1  is equal to Vb, 
     
         T.sub.1 = R.sub.1 C 1n [(Vcc-Va)/(Vcc-Vb)] = A (a third constant) (5) 
    
     During the &#34;off&#34; time interval: 
     
         V.sub.1 = Vb(e.sup.-.sup.(t.sup.-`)/R.sbsp.2 C)            (6) 
    
     where 213 is a resistor of value R 2  ; when V 1  is equal to Va, 
     
         T.sub.2 = R.sub.2 C 1n(Vb/Va) + T.sub.1                    (7) 
    
     substituting (5) in (7) 
     
         T.sub.2 = R.sub.2 B+A                                      (8) 
    
     where B = C 1n(Vb/Va) is a fourth constant. Then, from (3), (5) and (8), 
     
         E = T.sub.2 /T.sub.1 = 1 + XR.sub.2                        (9) 
    
     where X = B/A = a fifth constant. 
     When R 2  is zero, E = 1 (no extension of the basic charging rate) which is the predictable delay attributable to the discharge time of a short-circuited capacitor. If R 2  is increased in steps of value equal to (1/X), i.e., a constant increase of resistance, then E = 1 + N where N is an integer step of &#34;off&#34; resistance 213. The resistance value of resistor 213 may be incremented by any method which indicates and yields linear resistance steps. To obtain equal time separations, the values of R 2  must be in equal resistance separations. This states that equal resistance steps for R 2  will produce equal steps in the time delay for the basic timing circuit. If a potentiometer is used for R 2 , the dial markings will be linear since linear resistance changes produce linear time delays. 
     In a preferred embodiment, an integrated circuit contains the flip-flop 210, the transistors 211 and 212, the comparators 205 and 206, and the resistances 207, 208, 209, and 214. The limiting parameters of the integrated circuit embodiment of the present invention are the leakages of the capacitors 73, 74, and 75 in the timing circuit and the maximum value of the adjustable duty-cycle resistance 213 that will cause the integrated circuit to cease operation. It has been found that an extension range E in excess of 10,000 times greater than the base charging rate can be realized. 
     There has just been described a novel integrated circuit time delay extender for a static relay which provides linear control settings with linear adjustable resistance changes to produce linear time delay extensions. 
     Although there has been described a preferred embodiment of this novel invention, many variations and modifications will now be apparent to those skilled in the art. Therefore this invention is to be limited, not by the specific disclosure herein, but only by the appended claims.