Phase filter for reducing the effects of the noise components altering discrete phase modulated signals
BACKGROUND OF THE INVENTION 
     This invention relates to digital data transmission systems and more particularly, to a phase filter for reducing the effects of the noise components altering the signals transmitted through a system in which the phase of the transmitted signals is modulated by discrete values, at discrete times. 
     Phase modulation is a technique widely used in data transmission systems and a detailed description thereof is provided, for example, in &#34;Data Transmission&#34; by W. R. Bennett and J. R. Davey, chapter 10, McGraw-Hill, New York 1965 and &#34;Principles of Data Communications&#34; by R. W. Lucky, J. Salz and E. J. Weldon Jr., chapter 9, McGraw-Hill, New York 1968. In those digital data transmission systems that utilize phase modulation, the digital data to be transmitted modulate the phase of a carrier at particular instants or sampling times. The direct modulation method, called &#34;Coherent Phase Modulation&#34;, consists in making a predetermined phase absolute value to correspond to a data group or character. For instance, in an eight-phase system, i.e., in a system in which the phase of the transmitted signal can assume eight distinct discrete values, it is possible to make the eight phase absolute values π/8, 3π/8, . . . , 15π/8, respectively, to correspond to the eight characters 000, 001, 011, 010, 110, 111, 101 and 100 as shown in the diagram of FIG. 1a. The modulation method the most currently used, called &#34;Differential Phase Modulation&#34;, consists in making a phase change rather than a phase absolute value to correspond to a character. Always in an eight-phase system, it is possible to make phase variations Δφ = π/8, 3π/8, . . . , 15π/8 to correspond to the eight characters 000, 001, 011, . . . , 100. This type of modulation can also be illustrated by the diagram of FIG. 1a by taking the phase value of the signal emitted at the preceding sampling time as reference axis OX. The so-modulated carrier frequency is sent, through a transmission medium, to a receiver coupled thereto. At the receiver, the phase value of the signal received at sampling times is detected, and then the value of the transmitted data is extracted therefrom. This extraction is generally done by comparing the phase of the signal received at a given sampling time with a reference phase available in the receiver or with the phase of the signal received at the preceding sampling time according to the use of a coherent or differential detection, as described in the above-referenced books. 
     It is to be noted that phase modulation as briefly described above, is not the only one process for transmitting digital data, in which the phase of the transmitted signals represents the data. For instance, it is the case of the quadrature amplitude modulation a description of which can be found in the above-referenced book by R. W. Lucky et al, chapter 7 and more particularly in paragraph 7.1.5. Briefly, the quadrature amplitude modulation consists in modulating the amplitude of two carriers in quadrature by discrete values, said carriers being emitted in the same time. The following table shows the correspondence between the digital characters, the amplitude of each of the carriers in quadrature A and B and the phase and the amplitude of the signal resulting from the combination of these carriers, in an eight-state system illustrated by the diagram of FIG. 1b. 
     
         ______________________________________                                    
Digital Amplitude Amplitude Phase of Amplitude                            
characters                                                                
        of A      of B      the result-                                   
                                     of the                               
                            ing signal                                    
                                     resulting                            
                                     signal                               
______________________________________                                    
000     + 3        0          0      + 3                                  
001     + 1       + 1        π/4  +√2                           
011      0        + 3       2π/4  + 3                                  
010     - 1       + 1       3π/4  +√2                           
110     - 3        0        4π/4  + 3                                  
111     - 1       - 1       5π/4  +√2                           
101      0        - 3       6π/4  + 3                                  
100     + 1       - 1       7π/4  +√2                           
______________________________________                                    
 
    
     From this table, it appears that, in this example, the data can be directly derived from the value of the phase of the emitted resulting signal. 
     It would be desirable if the emitted signals should be received without distortion in the receiver. In practice, however, the transmission media introduce disturbances such as intersymbol interference and the noise components mainly due to frequency shift, phase intercept, phase jitter and white noise, which disturbances alter the emitted signals when transmitted through the transmission medium. 
     Intersymbol interference is due to an interaction between successive emitted signals, which interaction is caused by amplitude and phase distortions introduced by the transmission medium. When intersymbol interference appreciably affects the quality of the received signals, it is cancelled or reduced by an appropriate device called an &#34;Equalizer&#34;. Within the scope of this invention, it is assumed that intersymbol interference is cancelled by an appropriate equalizer, as necessary. 
     Frequency shift is a disturbance affecting the emitted signals when they are transmitted through a transmission medium in which they are submitted to an intermediate processing and more particularly, when telephone lines are used as the transmission medium. Said intermediate processing mainly includes the transposition of the emitted signals from one frequency band to another as required by the public network. A frequency shift f s  introduces a phase shift φ s  = 2πf s  t, where t is the time, which phase shift directly affects the phase of the received signal. 
     Phase intercept is due to the presence of a difference between the actual phase of a frequency and the phase corresponding to the ideal channel phase/frequency characteristic, at the ends of the frequency bandwidth of the transmission channel. This phase intercept introduces an arbitrary constant in the received phase value. 
     Phase jitter results from a random noise frequency modulation of the signals when passing through the transmission medium. Often, it is due to the variation of the power sources of the devices used to carry out the above-indicated intermediate processing. 
     White noise is due to the additive noise in the transmission medium and to the residual intersymbol interference. It is characterized by a flat frequency spectrum with equal contributions for all the frequencies, but in which the various frequencies exhibit random phases. 
     These noise components have practically no effect in the low speed digital data transmission systems but avoid correct data detection in high speed systems. In those systems using phase modulation, an increase of the transmission speed is generally obtained by increasing the number of the distinct discrete values which can be assumed by the phase of the emitted signal, which increase appears as a decrease of the gap between two adjoining phase values. For instance, in a four-phase system, this gap is of 90°, but it is only of 22.5° in a sixteen-phase system. Then it is often not possible to discriminate between two possible phase values in presence of the various above-indicated disturbances and it becomes imperative to provide a device to cancel or reduce the effects of these noise components before detecting data. 
     U.S. Pat. No. 3,855,539, filed Mar. 16, 1973 on behalf of Alain Croisier, which patent is assigned to the assignee of the present invention, describes a method and a device for reducing the effects of the noise components altering the phase of discrete phase modulated signals. According to this method, a correction value is subtracted from the received signal phase value. The result of this subtraction is multiplied by a first factor proportional to the number of distinct discrete values that the phase of the emitted signal can assume. The integral part of this product represents the data while the fractional part is used to provide said correction value. Said correction value is obtained by multiplying said fractional part by a second factor and by integrating the result of this last multiplication. Controlling the value of the second factor enables to minimize the effects of the various above-indicated components selectively. However, this method shows a drawback consisting in the fact that the reduction of the effect of the phase jitter is necessarily accompanied by a decrease of the performance with respect to the white noise. The curves shown in FIG. 3 of the above-indicated patent application enables one to appreciate the difficulty encountered to find a good decrease of phase jitter/increase of white noise compromise. 
     One of the objects of this invention is to overcome this drawback by providing an optimum phase filter for minimizing, the effects of phase intercept, frequency shift, phase jitter and white noise altering discrete phase modulated signals. 
     Another object of this invention is to provide an adaptive phase filter allowing to reduce the phase jitter effect to a minimum, whatever the noise modulation frequency causing said jitter, may be. 
     The objects of this invention are generally obtained by providing a phase filter including two decision filters which can be linked through a cascade or a parallel connection. The first decision filter cancels the phase intercept component and the phase shift component introduced by the frequency shift, and the second decision filter minimizes the random component representing phase jitter and white noise. In the first decision filter, a first error signal corresponding to an estimated value of the phase intercept and phase shift components is subtracted from the phase value of the received signal. The result of this first subtraction is applied to a detector-separator which separates the data and the residual noise component. The residual noise component is applied to a linear filter generating from the previous residual noise components, the estimated value of the phase intercept and phase shift components. In the second decision filter, a second error signal corresponding to an estimated value of the random component is subtracted from the result of the first subtraction. The result of this second subtraction is applied to a detector-separator which fetches the data and the residual random component out. Said component is applied to a linear filter which generates from the previous residual random components, the estimated value of the random component. When the phase jitter characteristics are unknown or if they are varying in time, the estimated value of the random component can be obtained by an adaptive predictive filter. 
     These and other objects, advantages and features of the present invention will become more readily apparent from the following specification when taken in conjunction with the drawings. 
     SUMMARY OF THE INVENTION 
     According to the present invention, a phase filter is disclosed which minimizes the effects of noise components altering the value of the phase of a digital signal in a digital data transmission system in which the phase of the digital signal can assume Q distinct values representing the data, with the phase filter including two decision filters. The first decision filter cancels residual noise components representing the phase intercept component and the phase shift component introduced by frequency shift, and the second decision filter minimizes the random noise component representing phase jitter and white noise. The first decision filter includes a first means for providing a first difference signal in response to taking the difference between the received digital signal and a first error signal corresponding to an estimated value of the residual noise component. Also included is a first detector which is responsive to the first difference signal for separating the data portion from the residual noise portion of said first difference signal. Further included is a first linear filter which is responsive to the residual noise portion of the first difference signal for generating the first error signal. The second decision filter includes a second means for providing a second difference signal in response to taking the difference between the first difference signal and a second error signal corresponding to an estimated value of the random noise component. Also included is a second detector which is responsive to the second difference signal for separating the data portion from the random noise portion of the second difference signal, with a data representative signal being provided at a first output and a random noise representative signal being provided at a second output. Further included is a second linear filter which is responsive to the random noise representative signal for generating the second error signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A and 1B show diagrams respectively illustrating an eight-phase modulation and an eight-state quadrature amplitude modulation. 
     FIG. 2 is a schematic illustration of a phase filter in cascade form according to this invention. 
     FIG. 3 is a diagram making the analysis of the first decision filter operation, easier. 
     FIG. 4 schematically shows as an example, a digital embodiment of linear filter W(z), 12, of FIG. 2. 
     FIG. 5 shows the shape of spectrum Rx(e j2 .sup.πfT) of random component x n  in example 1 of second decision filter 8. 
     FIG. 6 schematically shows another possible embodiment of second decision filter 8 of FIG. 2. 
     FIG. 7 schematically shows as an example, an embodiment of a Wiener adaptive optimal predictive digital filter which can be used in second decision filter 8. 
     FIG. 8 shows another possible embodiment of second decision filter 8, including an adaptive predictive filter. 
     FIG. 9A shows the phase filter of FIG. 2 in which second decision filter 8 is as shown on FIG. 6. 
     FIG. 9B shows the phase filter in parallel form corresponding to the phase filter in cascade form of FIG. 9A. 
     FIG. 10A shows the phase filter of FIG. 2 in which second decision filter 8 is as shown in FIG. 8. 
     FIG. 10B shows the phase filter in parallel form corresponding to the phase filter in cascade form of FIG. 10A. 
     FIG. 11 schematically shows an example, of a detector-separator used in this invention. 
     FIG. 12 is a waveshape relationship diagram of certain signals present in the circuit of FIG. 11. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The phase filter of the invention operating on sequences of discrete values, the Z-transform will be used as a mathematical tool. For the description of the theory of the Z-transform and of its applications, it is possible to refer, for example, to the articles entitled: &#34;Z-Transforms and Their Applications in Control Engineering&#34; by Y. Azar, published in &#34;The Radio and Electronic Engineer&#34; July 1965, pages 53 to 57 and &#34;Digital Filter Design Techniques in the Frequency Domain&#34; by C. M. Rader and B. Gold, &#34;Proceedings of the IEEE&#34;, Vol. 55, No. 2, February 1967, pages 149 to 171, and for a detailed study, it would be possible to refer, for example, to &#34;Theory and Application of the Z-Transform Method&#34; by E. I. Jury, John Wiley, New York, 1967. 
     To relieve the reader of the necessity of referring to other documents, a summary of the Z-Transform theory and the results which will be used in this description is given in the following. 
     Suppose a linear system characterized in the time-domain by its continuous impulse response h(t). In response to a continuous input signal s(t), this filter provides a continuous output signal g(t) defined by the following convolution relation ##EQU1## 
     If the Laplace transformation is used in the frequency domain, relation (1) becomes 
     
         G(p) = H(p) S(p)                                           (2) 
    
     with p = complex frequency 
     in which G(p), H(p) and S(p) are the Laplace transforms of g(t), h(t) and s(t), respectively. H(p) is called the &#34;transfer function&#34; of the system. The Laplace transform is used very much in studying continuous systems since it allows to replace the integration operation defined in (1) by the simple algebraic operation defined in (2). 
     The Z-transform operates as the Laplace transform, in studying discrete systems. By definition, the Z-transform of the sequence of discrete values s(nT), n=positive integer, and T=appearance periods of the discrete value, is: ##EQU2## where z is a complex variable z=e pT . 
     Relation (2) becomes 
     
         G(z) = H(z) S(z)                                           (4) 
    
     where S(z) and G(z) are the Z-transforms of the sequences of discrete values s(nT) and g(nT), and H(z) is the Z-transform of discrete impulse response h(nT). 
     Thus, the Z-transform of the output sequence of a discrete filter is the product of the Z-transform of the input sequence and function H(z) characterizing the filter, which function is similar to a transfer function. 
     A table for converting the sequences of values and their Z-transforms can be found, for example, in the above-indicated book by E. I. Jury. 
     It should be simply noted here that 
     the Z-transform of sequence x(nT) defined by 
     
         x(nT) = 0 for n &lt; 0 
    
     
         x(nT) = 1 for n ≧ 0 
    
      is ##EQU3## the Z-transform of a sequence delayed by an elementary delay T is equal to the Z-transform of the initial sequence multiplied by z.sup. -1 . 
     The phase filter according to the invention will be described, now, in a cascade form and a parallel form, successively. 
     Referring to FIG. 2 which shows the phase filter in cascade form, it is seen that the discrete value of phase φ&#39; n  fetched out from the received signal and which is supposed to be digitally encoded without limiting the scope of the invention, is applied to one of the inputs of a binary multiplier 2, via line 1. The second input of multiplier 2 is connected to the output of a storage element 4 which can be, for example, a binary register, or a simple prearranged connection assembly, via line 3. The output of multiplier 2 is connected via line 5 to the input of a first decision filter 6 the output of which is, in turn, connected via line 7, to the input of a second decision filter 8 which delivers as an output on line 9, the signals representing the detected data. The first decision filter 6 includes a binary subtractor 10, a detector-separator 11 and a digital linear filter 12. The output of multiplier 2 is connected via line 5 to the (+) input of subtractor 10 the output of which is connected via line 13 to the input of detector-separator 11 which will be described with more details with reference to FIG. 11. Output Er of detector-separator 11 is connected via line 14 to the input of filter 12 the output of which is connected via line 15 to the (-) input of subtractor 10. Second decision filter 8 includes two binary subtractors 16 and 17, a detector-separator 18, a digital predictive filter 19 and two delay elements 20 and 21, each introducing an elementary delay T equal to the sampling time period. The output of subtractor 10 of decision filter 6 is connected via line 7 to the (+) input of subtractor 16 the output of which is connected to the input of detector-separator 18 whose output is connected to output line 9. The output of detector-separator 18, is further connected via line 22, to the input of delay element 20 the output of which is connected to the (-) input of subtractor 17 via line 23. The (+) input of subtractor 17 is connected to the output of delay element 21 whose input is connected to line 7 via line 24. The output of subtractor 17 is connected via line 25, to the input of predictive filter 19 the output of which is connected to the (-) input of subtractor 18 via line 26. 
     The operation of the device schematically shown on FIG. 2 will now be described. 
     Within the scope of this invention, assume the case of a digital data transmission system in which the phase value of the signal emitted at sampling times, represents the data. The receiver of the system should process the received signal to allow correct detection of the phase of the signal received at sampling times to fetch the data out. Processing the received signal which is not within the scope of the invention, generally includes, automatic control of the received signal amplitude to allow further processing of constant mean power signals, sampling of the signal received at times t=nT and the conversion of the sampled signal in digital form. In addition, it includes, if necessary, the equalization of the received signal to reduce the effects of intersymbol interference. Detecting the value of the received signal phase, also sampled and equalized if necessary, at sampling times, is not within the scope of the invention either, and can, for instance, be ensured by the phase detector described in U.S. Pat. No. 3,825,737, filed Dec. 11, 1972 on behalf of Alain Crosier, which patent is assigned to the assignee of the present invention. 
     These phase values form the input signals of the device of this invention. 
     The signal applied to the input of the phase filter of the invention, shown on FIG. 2, appears, therefore, as a sequence of discrete phase values (φ&#39; n ), where φ&#39; n  is the phase value of the signal received at sampling time t=nT. 
     Phase φ&#39; n  can be expressed as follows 
     
         φ&#39;.sub.n = φ.sub.n + ε.sub.n               (6) 
    
     where 
     φ n  is the discrete value of the phase of the signal emitted at time t=nT, and represents the data, and 
     ε n  represents all disturbances or noises introduced during the signal transmission. 
     In a Q phase system, Q being a positive integer, i.e., in a system in which the emitted signal phase can assume Q distinct discrete values at each sampling time, φ n  can take the following values ##EQU4## 
     Noise ε n  can be expressed as follows ##EQU5## where 
     a o  is a constant representing phase intercept 
     a 1  is a constant representing the frequency shift between two successive sampling times, and 
     x n  is a random noise component representing phase jitter and white noise. 
     Phase φ&#39; n  is applied via line 1, to an input of multiplier 2 which multiplies it by factor Q/2π stored in storage element 4. Multiplier 2 provides at its output, on line 5, signal y n . ##EQU6## Substituting φ&#39; n  by its value obtained for expression (6), into expression (9) ##EQU7## which can be expressed as follows 
     
         y.sub.n = 1.sub.n + b.sub.n                                (11) 
    
     with ##EQU8## 
     From (7) and (8), one has, respectively 
     
         1.sub.n = 0, 1, 2, . . . , (Q-1)                           (12) 
    
     
         b.sub.n = a.sub.0 + a.sub.1 n + x.sub.n                    (13) 
    
     It is to be noted that 1 n  is an integer representing the data and that b n  represents all the noise components introduced during the transmission. It is to be noted that the very particular purpose of the multiplication of value φ&#39; n  by factor Q/2π is to apply to the input of first decision filter 6, a signal y n  equal to an integer in the absence of noise, which appears in equations (11) and (13) by making b n  =0. 
     The object of the system of this invention is to retrieve 1 n  and to minimize the effects of b n . According to this invention, the reduction of the effects of b n  to a minimum is obtained by cancelling phase intercept a o  and phase shift a 1  n introduced by frequency shift a 1 , by using first decision filter 6 and by reducing random component x n  by using second decision filter 8. 
     The operation of first decision filter 6 will now by analyzed. 
     Signal y n  available on line 5 is applied to the (+) input of subtractor 10 which receives at its (-) input an error signal u n  supplied by linear filter 12 the transfer function of which is referenced W(z). Subtractor 10 supplies at its output, difference y n  -u n  which is applied to the input of detector-separator 11. 
     The analysis of the system according to this invention will be carried out assuming that no detection errors appear, said errors being supposed to be very rare. From (11), we have 
     
         y.sub.n -u.sub.n = 1.sub.n + b.sub.n - u.sub.n                            
y.sub.n -u.sub.n = 1.sub.n + f.sub.n                                      
                with f.sub.n = b.sub.n - u.sub.n                          
                                 (14)                                     
 
    
     Since 1 n  is a positive integer, saying that there is no detection errors means that f n  is a fractional number the absolute value of which is comprised between 0 and 1. The function of detector-separator 11 to be described in detail with reference to FIG. 11, consists in fetching 1 n  and f n  out of difference y n  -u n  applied to it. In detector-separator 11, only output E r  providing residual noise component f n , is used and connected to line 14. Signal f n  is applied to linear filter 12 with transfer function W(z), the function of which consists in generating error signal u n  from the sequence of residual noise components {f n  }. 
     It should be noted that when only first decision filter 6 is necessary, i.e., when the effects of the random component can be neglected, output Da of detector-separator 11 providing 1 n  as an output of the phase filter, will be used. 
     Now, transfer function W(z) will be determined so that first decision filter 6 cancels phase intercept a o  and phase shift a 1  n introduced by the frequency shift. For that, it is always assumed that there is no detection errors and the response of decision filter 6 will be analyzed with respect to noise b n  only. In this case, decision filter 6 can be as shown on FIG. 3. It should be noted that in the filter shown on the figure, detector-separator 11 is cancelled since it has no effect on residual noise component f n  when there is no detection errors. On the other hand, random component x n  in noise b n  will be neglected, which will be verified later. 
     Therefore, it is assumed that: 
     
         b.sub.n = a.sub.o + a.sub.1 n 
    
     
         n = 0, 1, 2, . . .                                         (15) 
    
     Determining W(z) so that first decision filter 6 cancels a o  and a 1  n, i.e., cancels b n  as defined by (15), means determining W(z) so that f n  =0 when b n  =a o  +a 1  n. 
     Assume that B(z) and F(z) are the Z-transforms of b n  and f n , respectively, from (3) ##EQU9## From FIG. 3, we have 
     
         F(z) = B(z) - W(z) F(z) 
    
     or ##EQU10## or 
     
         F(z) = G(z) B(z)                                           (18) 
    
     with ##EQU11## 
     It should be noted that G(z) represents the transfer function of first decision filter 6. 
     From (16) and (15) ##EQU12## From (5) ##EQU13## Furthermore ##EQU14## Relation (5) can be expressed as follows ##EQU15## The derivative from (23) with respect to z can be expressed as follows: ##EQU16## Relation (24) can be written ##EQU17## Substituting (25) into (22) ##EQU18## Substituting (21) and (26) into (20) ##EQU19## Now, it will be shown that a filter the transfer function of which is as follows ##EQU20## cancel a noise B(z) as defined by (27) 
     In effect, by substituting the values of B(z) and G(z) given in expressions (27) and (28), respectively, into (18), we have the following expression of F(z) ##EQU21## corresponding sequence {f n  } of which will now be determined. Expression (29) can be expressed as follows ##EQU22## From (25) ##EQU23## and ##EQU24## Substituting (31) and (32) into (30) ##EQU25## From the Z-transform definition recalled in (3), we have 
     
         f.sub.n = a.sub. 0 (n+1) α.sup.n + (a.sub.1 -a.sub.0)nα.sup.n.sup.-1 
    
     or ##EQU26## 
     Since 0 &lt; α &lt; 1, it is seen from expression (34), that f n  → 0 when n → ∞. In other words, decision filter 6 with transfer function G(z) as defined by (28), cancels phase intercept a 0  and phase shift a 1  n when n → ∞, i.e., in steady condition. 
     It is to be noted, from expression (28), that G(z)→1 when α→1, i.e., that the effect of the first decision filter on the components other than a 0  and a 1  n, and in particular on random component x n , can be neglected when α→1, which verifies the original assumption according to which x n  was neglected in the analysis of first decision filter 6. 
     However, when α→1, the time response of the filter becomes infinite. Therefore, it is necessary to choose α so that decision filter 6 cancels components a 0  and a 1  n and does not have appreciable effect on component x n  while having a correct response time. A good compromise is obtained, for example, with α=0.9. 
     Transfer function G(z) of first decision filter 6 being determined by expression (28), transfer function W(z) of linear filter 12 is obtained by calculating W(z) in function of G(z) from (19) and by replacing G(z) by its value derived from (28). We have ##EQU27## and ##EQU28## 
     FIG. 4 schematically shows an example of a digital embodiment of a digital linear filter 12 in canonical form with transfer function W(z) as defined by relation (35). The embodiment of a digital filter from its transfer function, is a technique known in the art and a description of which can be found, for example, in the article entitled: &#34;Digital Filter Design Techniques in the Frequency Domain&#34; by C. M. Rader and B. Gold, published in the &#34;Proceedings of the IEEE&#34;, Vol. 55, No. 2, February 1967, pages 149 to 171. In FIG. 4, lines 14 and 15 have the same references as in FIG. 2. The filter shown on the figure conventionally includes two binary summing devices 110 and 112, two delay elements each shown as a block T, each one introducing an elementary delay T, and four binary multiplying devices multiplying the signals delivered from the outputs of the delay elements by factors +2, -1, 2(1-α), and (α 2  -1) respectively, said factors appearing in expression (35) of transfer function W(z). In the embodiment shown on the figure, the output of summing device 112 is connected to the input of a modulo Q logic unit 40 the output of which is connected to line 15. 
     The use of a modulo Q logic unit is made necessary by the type of the signals processed in the system of the invention. In effect, input signal φ&#39; n  applied to line 1 represents a phase value lying within the range 0 -2π radians. Then, this phase value is multiplied by factor Q/2π by multiplying device 2, therefore, result y n  of this multiplication is a value lying within the range 0 - Q. As seen above, Y n  is applied to the (+) input of subtractor 10 the (-) input of which receives error signal u n . To avoid saturation of the system, it is therefore necessary for signal u n  to be also comprised between 0 and Q, i.e., for the output signal of filter 12 to be included between 0 and Q, which involves the use of a modulo Q logic unit at the output of this filter. 
     By referring again to FIG. 4, it can be seen that the modulo Q logic unit is, in fact, very simple when operating on binary numbers. In effect, it is known that the binary representation of a number by m bits is a modulo 2 m  representation of this number and that the representations of x and x+p2 m  (p is an integer) are identical for the m low-order bits. The representation of the negative numbers is obtained by using the 2&#39;s complement, i.e., by adding the negative value of x to 2 m . It is to be noted that, as in the case of the binary representation with a sign bit, the highest order bit is 0 for x ≧0 and 1 for x &lt; 0. 
     In the embodiment shown on FIG. 4, Q is coded with 8 bits and then, the modulo Q logic unit is a binary modulo 2 8  logic unit. Inside the filter itself, the use of 16 bit binary numbers has been chosen to have a better accuracy in the calculations, thus the outputs of summing devices 110 and 112 are 16 bit numbers. The operation consisting of taking only the modulo 2 8  value of the filter output signal, i.e., of the summing device 112 output signal, is simply ensured by taking only the 8 low-order bits of the signal provided by summing device 112. Logic unit 40 is limited to a shift register 41 of 16 bits the input of which is connected to the output of summing device 112 and to a two input AND gate 42. The output of register 41 is connected to an input of AND gate 42 which is rendered conductive only for the 8 low-order bits, i.e., the first 8 bits of the number stored in register 41. AND gate 42 is conditioned by a gate control signal Tr applied to the second input of AND gate 42. AND gate 42 delivers at its output, modulo 2 8  error signal u n  which is applied to the (-) input of subtractor 11 through line 15 (FIG. 2). 
     The operation of second decision filter 8 will be analysed in the next paragraph. 
     It is assumed that transfer function W(z) of filter 12 is chosen as determined by expression (35) so that the noise component at the input of second decision filter 8 has essentially the same characteristics as the ones of noise b n  applied to the input of first decision filter 6, except that components a 0  and a 1  n are supposed to be removed by decision filter 6. With reference to expression (13), it is seen that the noise at the input of second decision filter 8 includes, then, only random component x n . The signal applied to the input of decision filter 8 is, therefore, the sum of signal 1 n  representing the data, the value of which is not affected by the first decision filter (when there is no detection error) and of random noise component x n . Signal 1 n  +x n  is applied via line 7 to the (+) input of subtractor 16 which receives, at its (-) input, an error signal which is, in fact, an estimated value of  x n , referenced x n . The output signal of subtractor 16 can be written 1 n  +e n , where e n  represents the difference between x n  and x n , i.e., the residual random component. Signal 1 n  +e n  is applied to the input of detector-separator 18 identical to detector-separator 12, except that only the output delivering signal 1 n  representing the detected data, is used. Signal 1 n  detected by detector-separator 18 is applied via line 22, to the input of elementary delay element 20 with transfer function z.sup. -1  and providing signal 1 n   -1  at its output. Signal 1 n   -1  is applied to the (-) input of subtractor 17 the (+) input of which receives signal 1 n  +x n  delayed by elementary delay element 21, i.e., signal 1 n   -1  +x n   -1 . The output signal of subtractor 17 representing random component x n   -1  when there is no detection error, is applied to the input of predictive filter 19 with transfer function P(z), via line 25. The function of predictive filter 19 the output of which is connected to the (-) input of subtractor 16, consists in predicting the estimated value of x n , x n , from the prior values of the random component, to minimize residual random component e n  at the input of detector-separator 18. 
     Predictive filter 19 with transfer function P(z) will be now determined so that second decision filter 8 minimizes random component x n . For this purpose, it will be successively assumed that the spectrum of random component x n  is known, then that it is undetermined or time-varying. 
     First assumption: The shape of the spectrum of x n  is known. 
     It is assumed that sequence {x n  } has a known rational spectrum. The power spectral density R x  (z) of x n  can be expressed as follows: ##EQU29## where N(z) and D(z) are z-polynomials all of whose zeroes lie outside the unit circle, and N(z.sup. -1 ) and D(z.sup. -1 ) are the conjugated polynomials of N(z) and D(z) respectively, readily obtained by replacing z by z.sup. -1 . It can be shown that any finite energy rational noise spectrum can be transferred into this form by applying the &#34;spectral factorization&#34; method. It can be shown that optimal predictive filter P(z) of x n , in the mean square sense, i.e., predictive filter P(z) which minimizes e n  2, is ##EQU30## where 
     
         a = N(0)/D(0). 
    
     now, it is possible to determine the whole transfer function of second decision filter 8. For this purpose, it is always assumed that there is no error detection and only the noise components are considered. By referring to FIG. 2 and using the Z-transform. 
     
         E(z) = (1-z.sup..sup.-1 P(z) ) X(z)                        (38) 
    
     where 
     E(z) and X(z) are the Z-transforms of e n  and x n , respectively. 
     Expression (38) can be expressed as follows 
     
         E(z) = H(z) X(z)                                           (39) 
    
     with 
     
         H(z) = 1-z.sup..sup.-1 P(z)                                (40) 
    
     where 
     H(z) is the transfer function of second decision filter 8. 
     By substituting the value of P(z) derived from expression (37) into expression (40), one obtains transfer function H(z) of second decision filter 8 which reduces random component x n  in the assumption under consideration. We have ##EQU31## 
     
         R.sub.e (z) = |H(z)|.sup.2 R.sub.x (z) = H(z) H(z.sup..sup.-1) R.sub.x (z)                              (41&#39;) 
    
     From (36) and (41) 
     
         R.sub.e (z) = a.sup.2                                      (42) 
    
     This expression shows that the optimum filter is the one which produces a white noise spectrum at the input of detector-separator 18. On the other hand, a 2  represents total noise power e n  2. 
     EXAMPLES 
     Let the power spectral density R x  (z) of sequence {x n  } be of the form ##EQU32## where P i  = 2 (2πf i  T) 2  (1-μ i   2 ) 
     g i  (z) = 1-2μ i  cos (2πf i  T)z + μ i   2  z 2   
     T = sampling period x n   2  .sub.≲ 1 
     The two terms in brackets in expression (43) represent the noise components concentrated in frequency bandwidths proportional to (1-μ i ) and centered at f i  Hz, and term k 3  represents white noise. 
     EXAMPLE 1 
     Let k 1  =4, k 2  =k 3  =1 T = 1800Hz, f 1  =55Hz, f 2  =110Hz and μ 1  =μ 2  =0.85. 
     Spectrum R x  (e j2 .sup.πft) corresponding to this example is shown on FIG. 5. 
     combining terms in expression (43), we obtain a rational expression that factors into the form (36Combining where 
     
         N(z) = 0.63(1-1.34z+0.56z.sup.2) (1-1.13z+0.4z.sup.2) 
    
     
         D(z) = (1-1.67z+0.7225z.sup.2) (1-1.58z+0.7225z.sup.2) 
    
     
         a.sup.2 = 0.39 
    
     We obtain transfer function P(z) ##EQU33## 
     EXAMPLE 2 
     Repeating the above example with k 3  =1/4 gives 
     
         N(z) = 0.4(1-1.46z+0.61z.sup.2) (1-0.78z+0.25z.sup.2) 
    
     
         D(z), same as example 1 
    
     
         a.sup.2 = 0.163 
    
     It should be noted that in example 2, a 2  is much smaller than in example 1, indicating that the filter is more effective when the white noise component is small compared with the other components. 
     The embodiment of digital predictive filter 19 will not be described here since it can be conventionally obtained from the expression of P(z), as described, for example, in the above-mentioned article by C. M. Rader and B. Gold. 
     It should be noted that the configuration of decision filter 8 as shown in FIG. 2, can be modified to obtain a configuration identical to the one of the first decision filter shown in FIG. 2. FIG. 6 shows a possible configuration of second decision filter 8, designated 8&#39;. In this configuration, line 7 is connected to the (+) input of a binary subtractor 30 the output of which is connected to the input of a detector-separator 31 identical to detector-separators 11 and 18. A first output of the detector-separator is connected to data output line 9 while a second output is connected via line 32 to the input of a digital linear filter 33 the transfer function of which is referenced L(z). The output of filter 33 is connected to the (-) input of subtractor 30 via line 34. In operation, signal 1 n  +x n  is applied via line 7, to the (+) input of subtractor 30 the (-) input of which receives an error signal v n  provided by filter 33. The subtractor provides at its output, signal 1 n  +e n  where e n  =x n  -v n  is the residual random component at the input of detector-separator 31. As indicated above, the function of the detector consists in detecting 1 n  and e n . When there is no detection error, 1 n  is provided on line 9 while residual random component e n  is supplied by the second output of detector-separator 31 connected to line 32. The function of filter 33 consists in generating error signal v n  from the prior values of residual random component e n . 
     It will now be shown that the configurations of second decision filters 8 and 8&#39; as they appear in FIGS. 2 and 6, respectively, are equivalent and l(z) will be determined so that the configuration of FIG. 6 reduces random component x n  to a minimum. It will be always assumed that there is no detection error and only the noise components will be considered. By referring to FIG. 6 and using the Z-transform, we have: 
     
         E(z) = X(z) - L(z) E(z)                                    (44) 
    
     or ##EQU34## where E(z) and X(z) are the Z-transforms of e n  and x n , respectively. 
     Expression (45) can be expressed as follows 
     
         E(z) = H&#39;(z) X(z)                                          (46) 
    
     with ##EQU35## where H&#39;(z) is the transfer function of the configuration of the filter shown on FIG. 6. 
     In order to have the two configurations of second decision filters 8 and 8&#39; as they appear on FIGS. 2 and 6, respectively, equivalent, it is necessary for said two configurations to have the same transfer function, i.e., 
     
         H&#39;(z) = H(z)                                               (48) 
    
     or from (40) and (47) ##EQU36## From which, it can be deduced that we must have ##EQU37## or ##EQU38## The value of L(z) so that the second configuration of second decision filter 8 shown in FIG. 8, cancels random component x n , is readily obtained by replacing P(z) in (54) by its value derived from (37). It yields: ##EQU39## Reconsidering example 1 ##EQU40## 
     So far, one has determined the two possible configurations of second decision filter 8, when the shape of the spectrum of random component x n  is known. The second assumption will now be studied. 
     Second Assumption: The x n  spectrum shape is undetermined or time-varying. 
     It was seen above that random component x n  is mainly due to phase jitter and white noise. Now, we will consider the case when the phase jitter effect is preponderant over the white noise effect and random component x n  will be considered as phase jitter. 
     Since phase jitter is generally provided with a spectrum limited between 0 and 300 Hz while the sampling frequency, i.e., the character transmission rate in a digital data transmission system is very often at least equal to 1200 Hz, it is possible to obtain a good estimated value of x n  by using an adaptive predictive filter, for instance a Wiener adaptive predictive filter. It will be briefly recalled below what is a Wiener adaptive predictive filter of order p. 
     Assume that s n   -1  is the (n-1) th  sample of a low frequency signal, and that s n  is an estimated value of the next sample. Estimated value s n  is obtained by carrying out an extrapolation on the last p samples. This can be expressed as follows 
     
         s.sub.p.sub.+1                                                            
     = α.sub.1 s.sub.1 + α.sub.2 s.sub.2 + ...                
     + α.sub.p s.sub.p                                              
s.sub.p.sub.+2                                                            
     = α.sub.2 s.sub.2 + ... + α.sub.p s.sub.p.sub.+1         
.                                (53)                                     
.                                                                         
s.sub.n                                                                   
     = α.sub.1 s.sub.n.sub.-p + α.sub.2 s.sub.p .sbsb.n       
     .sbsb.p .sbsb.1 + ... + α.sub.p s.sub.n.sub.-1                 
 
    
     with n ≧ 2p. 
     Factors α i , i=1,2, . . . , p are adjusted so that error E n   -1 , in the means square sense, between the actual value of s q  and its estimated value s q , q=p, (p+1), is at a minimum: ##EQU41## In this assumption, it is possible to replace predictive filter 19 of second decision filter 8 shown in FIG. 2, by a Wiener adaptive predictive filter. If a Wiener filter of order p=5, for instance, is used, estimated value x n  of x n  is obtained from the following iteration relation 
     
         x.sub.n = α.sub.1 x.sub.n.sub.-1 + α.sub.2 x.sub.n.sub.-2 + α.sub.3 x.sub.n.sub.-3 + α.sub.4 x.sub.n.sub.-4 + α.sub.5 x.sub.n.sub.-5                              (55) 
    
     The values of α i , i=1, . . . 5, are calculated so that error E n   -1  in the mean square sense, between x q  and x q , q=6, . . . , (n-1) is at a minimum. We have ##EQU42## 
     FIG. 7 schematically shows an example of a digital embodiment of such a Wiener adaptive predictive filter 19&#39;. 
     Signal x n   -1  provided from the output of subtractor 17 (FIG. 2) is applied to the input of a 5T long delay line 50, T being the sampling period via line 25. In a digital embodiment, this delay line consists in a shift register including five stages, each one introducing a delay T. This delay line includes six taps 51-1, 51-2, . . . , 51-6 positioned with respect to T so that when value x n   -1  is applied to the input of delay line 50, and therefore, is available at tap 51-1, values x n   -2 , x n   -3 , x n   -4 , x n   -5  and x n   -6 , respectively, are available at taps 51-2, . . . , 51-6. 
     Taps 51-1, . . . , 51-5 are respectively connected to a first input of five binary multipliers 52-1, . . . , 52-5. The output of these multipliers are connected to the inputs of a summing device 53 the output of which supplies estimated value x n  on line 26. The output of summing device 53 is further connected via line 54, to the input of a delay element 55 introducing a delay T, the output of said delay element thus supplying value x n   -1 . The output of delay element 55 is connected to the (-) input of a binary subtractor 56, the (+) input of which is connected to line 25 via line 57. The output of subtractor 56 providing error signal ε n   -1  =x n   -1  -x n   -1 , is connected via line 58, to a first input of five binary multipliers 59-1, 59-2, . . . , 59-5, the second inputs of which are respectively connected to taps 51-2, . . . , 51-6. The outputs of multipliers 59-1, . . . , 59-5 are respectively connected to the input of five digital integrators 60-1, 60-2, . . . , 60-5 which, in the embodiment shown on the figure, consist in reversible counters. Each of integrators 60-1, . . . , 60-5 is provided with a resetting input, respectively connected to lines 61-1, . . . , 61-5. The outputs of integrators 60-1, . . . , 60-5 are respectively connected to the input of five factor adjusting logic units 62-1, 62-2, . . . , 62-5, the outputs of which are respectively connected to the second input of each of multipliers 52-1, . . . , 52-5. The outputs of logic units 62-1, . . . , 62-5, respectively supply the values of factors α 1 , α 2 , . . . α 5 . To simplify the drawing, only logic unit 62-1 is shown in detail, other logic units 62-2, . . . , 62-5 being identical to the first one. Logic unit 62-1 includes a two input AND gate 63-1 with two inputs, one of which is connected to the output of integrator 60-1 and the second one is connected to a first control signal source (not shown), via line 64-1. The output of AND gate 63-1 is connected to a first input of a binary multiplier 65-1 the second input of which is connected to a storage element 67-1 via line 66-1. The output of multiplier 65-1 is connected to the (-) input of a binary subtractor 68-1 the (+) input of which is connected to a second control signal source (now shown) via line 69-1. The output of subtractor 68-1 is connected to the second input of multiplier 52-1. 
     The device shown on FIG. 7 will now be described. 
     The device shown on the figure should provide estimated value x n  obtained from expression (55), factors α i , i=1, . . . , 5 being obtained by minimizing error E n   -1  defined by expression (56) recalled below. ##EQU43## ##EQU44## with 
     
         ε.sub.q = x.sub.q - x.sub.q                        (59) 
    
     Error E n   -1  appearing as a square sum ε q   2 , q=6, (n-1), minimizing E n   -1  is the same as minimizing all ε q   2 , q=6, . . . , (n-1) successively and summing the minimum values of ε q   2  obtained in this way. One will consider the instant where signal x n   -1  is applied to the input of the Wiener predictive filter and analyse the minimization of ε n   -1   2 , while showing how the device shown on the figure takes the minimum values of the prior ε q   2  into account. 
     Since the only adjustable elements which can be modified to minimize ε n   -1   2  are the values of coefficients α i , i=1, 2, . . . , 5, elementary error ε n   -1   2  will be minimum if the derivative of ε n   -1   2  with respect to the various coefficients, is cancelled, i.e., if ##EQU45## we have ##EQU46## Substituting ε n   -1  by its value derived from (59) ##EQU47## 
     Signal x n   -1  being independent from the values of coefficients α i , expression (61) becomes ##EQU48## but, from (55) 
     
         x.sub.n.sub.-1 = α.sub.1 x.sub.n.sub.-2 + α.sub.2 x.sub.n.sub.-3 + α.sub.3 x.sub.n.sub.-4 + α.sub.4 x.sub.n.sub.-5 + α.sub.5 x.sub.n.sub.-6             (64) 
    
     or ##EQU49## Derivating expression (65) with respect to α i  ##EQU50## Then, expression (63) becomes ##EQU51## Therefore, ε n   -1   2  is minimized by making 
     
         (x.sub.n.sub.-1 -x.sub.n.sub.-1) x.sub.n.sub.-1.sub.-i =0 for i=1, . . . , 5                                                         (68) 
    
     With reference to FIG. 7, it will be shown that the device of said figure, applies relation (68). 
     For clarity, only the adjustment of the value of coefficient α 1 , i.e., the application of expression (68) for i=1, will be described, the adjustment of the other coefficients being similar. Signal x n   -2  available on tap 51-2 is applied to the second input of multiplier 59-1 the first input of which receives signal ε n   -1  =x n   -1  -x n   -1  via line 58. Signal ε n   -1  is provided by the output of subtractor 56 which receives, on its (+) input, signal x n   -1  via line 57, and on its (-) input, signal x n   -1  available at the output of delay element 55. Therefore, the output of multiplier 59-1 provides product (x n   -1  -x n   -1 ) x n   -2  which is applied to the input of integrator 60-1 which accumulates the value of this product with the prior values of said product. A resetting line 61-1 is provided since, in practice, said products are accumulated only during a determined period of time, equal, in general, to the length of delay line 50. The result of this accumulation, which will be referenced Δα 1 , is used to adjust the value of α 1  until this result is null. The result of the accumulation is applied to the input of the logic unit 62-1 provided for adjusting coefficients and supplying the new value of α 1  at its output. In practice, this adjustment is not performed on each sampling time but, in general, after a determined period of time equal in general, to the length of delay line 50, and it is the reason why it has been provided, at the input of logic unit 62-1, and AND gate 63-1 which is rendered conductive only after this determined period of time has elapsed. Signal Δα 1  is then applied to the first input of multiplier 65-1 which receives on its second input, a value μ  stored in element 67-1 and representing the increment step of coefficients α i . The output of multiplier 65-1 providing product μΔα 1  is connected to the (-) input of subtractor 68-1 to the (+) input of which is applied the prior value of α 1 . 
     
         α.sub.1 new = α.sub.1 old - μΔα.sub.1 
    
     which is applied to the second input of multiplier 52-1. Multiplier 52-1 multiplies the new value of α 1  with signal x n   -1  available from tap 52-1. Then, multiplier 52-1 carries product α 1  x n   -1  out, said product being applied to one of the inputs of summing device 53. Summing device 53 receives, on its other inputs, in the same way, products α 2  x n   -2 , α 3  x n   -3 , α 4  x n   -4 , α 5  x n   -5 , and supplies as an output, estimated value x n  defined by expression (55). Estimated value x n  is applied through line 54 to the input of delay element 55 which will apply it at the next sampling time, to the (-) input of subtractor 56. Then, value x n  will be used to carry on the coefficient adjusting procedure. This value x n  is further applied to the (-) input of subtractor 16 (FIG. 2) via line 26, for minimizing random component x n  through second decision filter 8 (FIG. 2). 
     It should be noted that the adaptative predictor operates exactly as a conventional transversal equalizer, except that the error criterion is different. The above-described predictor cnverges exactly as an equalizer the taps of which are spaced by the sampling period. It should also be noted that, since the predictor operates as a low pass filter, the white noise has little effect on the estimate of the phase jitter. 
     FIG. 8 shows another possible configuration of decision filter 8 designated as 8&#34;, including an adaptive predictive filter. 
     Signal 1 n  +x n  available on line 7 (FIG. 2) is applied to the (+) input of a binary subtractor 70 the (-) input of which receives an estimated value of x n , x n . Signal 1 n  +x n  -x n  supplied from the output of subtractor 70 is applied to the input of a detector-separator 71 which provides signal 1 n  representing the data on line 9 and residual random component x n  -x n  on line 72. Signal x n  -x n  is applied to the input of an elementary delay element 73 introducing an elementary delay T so that signal x n   -1  -x n   -1  is available at its output, said signal is applied via line 74, to a first (+) input of a binary adder 75 the second (+) input of which receives signal x n   -1  via line 76. Thus, adder 75 provides at its output, signal x n   -1  which is applied to the input of an adaptive predictive filter 77 providing signal x n  at its output. Signal x n  is applied to the (-) input of subtractor 70, via line 78, and to the input of an elementary delay element 80 introducing an elementary delay T via line 79. Signal x n   -1  available from the output of delay element 80, is applied to the second (+) input of adder 75 via line 76. 
     It should be noted that the function and the operating conditions of adaptive predictive filter 77 are identical to the ones of predictive filter 19 provided in the configuration shown on FIG. 2 and that it is possible to use the Wiener predictive filter described in FIG. 7 as an adaptive predictive filter. 
     So far, the system has been described as a phase filter in which both decision filters 6 and 8 are connected in cascade. Now, the system will be described as a phase filter in parallel form, in the cases when the predictive filter of the second decision filter is provided with fixed coefficients, and then when said filter is adaptive. 
     CASE OF A PREDICTIVE FILTER WITH FIXED COEFFICIENTS 
     For clarity, the phase filter, shown in FIG. 9a, is in cascade form similar to FIG. 2, with the second decision filter 8 having the configuration as shown in FIG. 6. In FIG. 9b, the corresponding parallel form is shown. It should be noted that the same reference numbers are used for the same elements in the structure of FIG. 9a as shown in FIGS. 2 and 6 since the operation of the respective elements has been described before. 
     In FIG. 9b, signal y n  available on line 5 is applied to the (+) input of a binary subtractor 90 the output of which is connected to the input of a detector-separator 91. The first output of detector-separator 91 connected to line 9, provides the signal representing data 1 n , while the second output of detector-separator appearing on line 32 is connected in parallel to filters 92 and 93 with transfer functions W&#39;(z) and L&#39;(z), respectively. The outputs of filters 92 and 93 are added in binary adder 94 the output of which is connected to the (-) input of subtractor 90. 
     Now, it will be shown that the structures of FIGS. 9a and 9b are equivalent by considering their transfer functions. 
     As seen above, transfer functions G(z) and H&#39;(z) of decision filters 6 and 8 of FIG. 9a are given by relations (19) and (47), respectively, ##EQU52## 
     Transfer functions S c  (z) of the cascade configuration shown on FIG. 9a can be expressed as follows 
     
         S.sub.c (z) = G(z) H&#39;(z) 
    
     or ##EQU53## 
     Transfer functions S p  (z) of the parallel configuration shown on FIG. 9b can be directly established from the diagram of FIG. 9b ##EQU54## 
     In order to make the cascade and parallel forms equivalent, we must have 
     
         S.sub.c (z) = S.sub.p (z) 
    
     or 
     
         (1+W(z)) (1+L(z)) = 1+W&#39;(z) + L&#39;(z)                        (71) 
    
     For instance, it is possible to select W&#39;(z)=W(z) and to derive the value of L&#39;(z) from relation (71). It yields 
     
         L&#39;(z) = L(z) (1+W(z))                                      (72) 
    
     Substituting W(z) and L(z) by their values derived from (35) and (52&#39;) respectively, into (72), we obtain the value of L&#39;(z) in the case of above example 1. 
     CASE OF THE ADAPTIVE PREDICTIVE FILTER 
     For clarity, the phase filter shown on FIG. 10a, is in cascade form similar to FIG.2, with the second decision filter 8 having the adaptive configuration as shown in FIG. 8. In FIG. 10b the corresponding parallel form is shown. The same reference numbers are used for the same elements in the structure of FIG. 10a as shown on FIGS. 2 and 6, since the operation of the elements has been described before. 
     In FIG. 10b, signal y n  available on line 5 is applied to the (+) input of a binary subtractor 95 the output of which is connected to the input of a detector-separator 96. The first output of detector-separator 96, connected to line 9, provides the signal representing data 1 n  while the second output of detector-separator 96 is connected in parallel to the input of filter 97 with transfer function W(z), which is identical to filter 12 of FIG. 2, and to the input of an elementary delay element 98. The output of filter 97 is connected to the first (+) input of a binary adder 99 the output of which is connected to the (-) input of subtractor 95. The output of delay element 98 is connected to the first (+) input of a binary adder 100 the output of which is connected to the input of an adaptive predictive filter 101. The output of filter 101 is connected to the second (+) input of adder 99 and to the input of a delay element 102 the output of which is connected to the second (+) input of adder 100. 
     It should be noted that the first loop including subtractor 95, detector-separator 96 and filter 97 is identical to first decision filter 6 shown in FIG. 2. The operating conditions of the first loop being identical to the ones of first decision filter 6, in the cascade form. 
     The second loop including subtractor 95, detector-separator 96, delay elements 98 and 102, adder 100 and adaptive filter 101, is identical to second decision filter 8&#34; as described with reference to FIG. 8. In the parallel form shown on FIG. 10b, the second output of detector-separator 96 supplies both residual component f n  and residual random component x n  -x n . However, as seen above in the description of the operation of first decision filter 8&#34;, residual component f n  →0 in steady condition. In steady conditions, the signal applied to the input of delay element 98 is only comprised of x n  -x n  and thus, the operating conditions of the second loop are identical to the ones of decision filter 8&#34; shown in FIG. 8. Thus, the second loop operates exactly as decision filter 8&#34; of FIG. 8 and adaptive filter 101 can be as the Wiener adaptive predictive filter shown in FIG. 7. 
     With reference to FIG. 11, an example of a digital embodiment of the detector-separators used in the invention, will now be described. 
     It was seen above that the function of the detector-separator used in the invention consists in isolating, from the signal applied thereto, term 1 n  representing the data, and the residual components marked f n  in the case of the detector-separator of first decision filter 6, and e n  =x n  -x n  in the case of the detector-separator of second decision filter 8. 
     Furthermore, it was seen that 1 n  is a positive integer (relation (12)). 
     
         1.sub.n = 0, 1, 2, . . . (Q-1) 
    
     and that, when there is no detection error, residual noise component e n , for example, is a fractional number the absolute value of which is comprised between 0 and 1. 
     It is possible to isolate 1 n  and e n  in several different ways. If, for instance, the signal applied to the input of the detector-separator is equal to 2.6, it can be arbitrarily said that: 
     1 n  =3 and e n  =-0.04 i.e., that -0.5 &lt; e n  &lt; 0.5 
     or 
     1 n  =2 and e n  =+0.6 i.e., that 0 &lt; e n  &lt; 1 
     FIG. 11 describes an example of a digital detector-separator using the second possible solution. 
     It is assumed that the case of a eight-phase digital data transmission system is considered and that the signal applied to the input of the detector-separator shown on the figure appears as a eight-bit binary word. The device shown on the figure includes an eight-bit shift register 103, a latch 104, three AND gates 105, 106 and 107 and an OR gate 108. The input binary word is applied to the input of shift register 103. The input binary word represents both an integer 1 n  representing the data, and a fractional number representing the noise. In the case of an eight-phase system, 1 n  can assume one of the eight values 1 n  =0, 1, 2, . . . , 7, and can be coded by three bits (2 3  =8 phases) which are the three high-order bits in the input binary word. In the device shown on FIG. 11, 1 n  is detected by connecting the output of shift register 103 to a first input of AND gate 105 and by conditioning said AND gate 105 only when the three high-order bits are available at the output of shift register 103. AND gate 105 is controlled by applying an appropriate transfer control signal Tr 2 on the second input of AND gate 105 via line 109. The output of AND gate 105 is connected to line 9 (FIG. 2) from which 1 1 .sbsb.n is available. The fractional part of the input binary word representing the noise is also obtained by connecting the output of shift register 103 to a first input of AND gate 106 and by enabling the gate when the five low-order bits are available from the output of shift register 103. AND gate 106 is controlled by applying an appropriate transfer control signal Tr 1 on the second input of AND gate 106 via line 110. The five low-order bits transmitted by AND gate 106 are applied to line 14 through OR gate 108. However, these five bits being the five low-order bits of an eight-bit binary word, it is necessary to convert these five bits into an eight-bit binary word. In the device shown on the figure, the five bits to eight bits conversion is readily carried out by repeating the last of the five bits, three times. A tap is provided for this purpose at the fifth bit position of shift register 103 and this tap is connected to the input of latch 104 which reads the bit which is in this bit position when the input binary word is in shift register 103. This reading is controlled by timing signal Tr 3 applied to this latch via line 111. The binary state assumed by latch 104 is transmitted through AND gate 107 and OR gate 108 for three bit times following the first five bits fetched out of shift register 103. AND gate 107 is controlled by applying an appropriate transfer control signal Tr 2 on the second input of AND gate 107 via line 112. The timing sequence for Tr 1 , Tr 2  and Tr 3  is illustrated in FIG. 12. 
     While the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.