Logic circuits-employing junction-type field-effect transistors
This is a division, of application Ser. No. 267,213 filed June 28, 1972, and now abandoned. 
    
    
     The present invention relates to logic circuits comprising field-effect transistors. 
     The Applicants filed a U.S. Pat. application, Ser. No. 183,565. 
     In this application, FIG. 1 describes a novel junction-type field-effect transistor produced by a novel method which makes use in particular of techniques of ion implantation and heat treatments at temperatures never in excess of 1,000°C. 
     The transistor obtained by this method has a semi-insulating substrate. Its parasitic capacitances are reduced because the accuracy obtained in the lateral dimensions of the component is extremely high whilst its area is very small. 
     The accuracy of the transverse dimensions likewise being very high, it is possible to produce very thin n-type or p-type films, with low dispersion. 
     The transistors thus obtained can be easily integrated and have numerous advantages over conventional transistors. Since the current is produced by majority charge carriers, the storage time is negligible whereas in conventional junction transistors, even gold-doped ones, it reaches 3 × 10 -   9  secs. 
     The input resistance is much higher than that of these transistors. Finally, their manufacturing technology makes it possible to eliminate certain drawbacks of conventional junction-type field-effect transistors. 
     Their pinch-off voltage Vp and consequently their blocking voltage V B  ≃ - V p  is lower so that the gate bias voltage is in the order of 1v instead of 5v and the supply voltage can be reduced from 15v to a maximum of 8. 
     Moreover, the velocity of operation is increased, since the channel length is shortened. The drain capacitance is low and the current is therefore reduced. 
     An object of the present invention is logic circuits in which such transistors are used. 
    
    
     The invention will be better understood from a consideration of the ensuing description and by reference to the attached drawings in which: 
     FIGS. 1, 2 and 3 illustrate examples of inverters in accordance with the invention; 
     FIG. 4 is an explanatory diagram; 
     FIGS. 5 and 6 respectively illustrate in plan and in transverse section, an example of such an integrated circuit gate. 
    
    
     In FIG. 1, a logic inverter of the type known as an AND-NOT gate, has been shown. It has four inputs E 1 , E 2 , E 3 , E 4  and an output S. 
     If any of the inputs carries a voltage level corresponding to the digit 0, then the output should carry a voltage level corresponding to the digit 1. 
     If none of the inputs carries the level 0, that is to say if all of them carry the level 1, then the output should carry the level 0. 
     This circuit uses a transistor T of the type described in the afore-mentioned Patent Application. Its source is earthed. Its drain is connected to the positive terminal of the d.c. supply B 1 , which supplies a voltage + 8 volts, across a resistor R C . 
     Its gate is connected across a resistor R 2  to the negative terminal of a d.c. supply B 2 , supplying a voltage - 1 v, on the one hand, and to one electrode of a Zener diode Z having a breakdown voltage of 5v, on the other. The other electrode of this diode is connected to the positive terminal of the battery B 1  across a resistor R 1 . 
     Between the diode Z and the resistor R 1 , at the point A, there are connected the four inputs E 1  to E 4  of the inverter, this across respective diodes D 1  to D 4  connected to operate in the forward direction towards said inputs. 
     The operation of the system is as follows: 
     The voltage applied to the inputs are of two levels, the level 0 corresponding for example to 1v, the level 1 to 8 v. 
     If one of the inputs is at the level 0, for example the input E 1 , a first conductive path is established between the battery B 1  and the input E 1 . 
     Since the diode D 1  is conductive, the potential at the point A is ≃ 1.7 volts, the voltage drop across a conductive diode being in the order of 0.7 v. Across the terminals of the Zener diode a voltage of less than 2.7 volts appears. This diode, since it does not conduct until around 5 v, remains blocked. The voltage applied to the gate of T is thus in the order of -1 v. Transistor T is therefore blocked. The output voltage appearing at output terminal S is equal to 8 v, that is to say level 1. 
     If all the inputs E 1  or E 4  are placed at level 1, that is to say 8v, the Zener diode conducts, the potential at A then being in the order of 5 v; the diodes D 1 , D 2 , D 3  and D 4  are all blocked. 
     There are then two other conductive paths, one from the battery B 1  to the battery B 2 , the other from the battery B 1  to earth across transistor T which latter is then conductive the voltage applied to its gate being in the order of 0 v. The output voltage is in the order of 1 v, that is to say corresponding to level 0. 
     The circuit described is thus a logic AND-NOT gate or as it is more commonly known a NAND gate. 
     The structure described is applicable to a logic system with a high noise margin and large intervals between logic levels. 
     The transistor T has a blocking voltage V B  (source-gate voltage beyond which it does not conduct), in the order of -1v. Its pinch-off voltage V p  (source-drain voltage beyond which it is saturated, when the voltage applied to its gate is that applied to the source), is equal to V p  = - V B . 
     FIG. 2 illustrates a gate based upon the same principle, but with a narrower noise margin, V 1  - V 0  being in the order of 3 v and the supply voltage being around 4 v. In this figure, references which are the same as those used in the earlier figure, indicate the same elements. 
     The Zener diode has been replaced by four diodes F 1 , F 2 , F 3 , and F 4  connected in series in the forward direction from B 1  to B 2  ; the input diodes are Schottky diodes with a threshold of ≃ 0.5 v. B 1  supplies + 4 v. The resistors R 2  and R 1  have resistances in the order of 10 5  ohms. The operation is the same as in the preceding case. 
     One of the inputs E 1  for example is at the level 0, which corresponds to 1 v, the level 1 corresponding to 4 v. 
     The diode D 1  is conductive, and the potential A is in the order of 1.5 v, the resistance of R 2  being very high, and the voltages across the terminals of the diodes F 1  to F 4  is thus in the order of 2.5 v. However, the voltage required to drive them conductive is in the order of 3 v so that they remain blocked. 
     The gate voltage of the transistor T is thus around - 1 v. This transistor is therefore blocked. The voltage at S is at level 1, that is to say 4 v. 
     If all the inputs are at level 1, none of the diodes D 1  to D 4  conducts. By contrast, since the diodes F 1  to F 4  carry a voltage in excess of 3 v across their extreme terminals, they are conductive. The voltage on the gate is in the order of 0 v. The transistor T is in a conductive state, and the voltage V S  drops to level 0, that is to say to a figure in the order of 1 v. 
     In FIG. 3, a transistor having a very small channel thickness is used. More precisely this thickness is equal to that of the depletion layer produced by the diffusion voltage at the control junction. In other words, if the gate voltage is 0, no current will flow from the source to the drain. Such a current will only flow if the gate is forward biased, the transistor operating then by the unpinching of the channel because the control voltage has the effect of reducing the depletion layer. 
     The gate is a Schottky gate or pn-junction. In the case of the Schottky gate, there is no injection of minority charge carriers when the gate is forward biased. 
     FIG. 3 illustrates a gate utilising this transistor. The supply voltage is 2.5 v 
     
         V.sub.0 = 0.5 v. 
    
     
         V.sub.1 = 2.5 v. 
    
     the diode Z is replaced by two forward-operated diodes F 1  and F 2  and the resistor R 2  is earthed. The input diodes D 1 , D 2 , D 3 , and D 4  are Schottky diodes with a threshold of ≃ 0.5 v. 
     The operation is the same as in the preceding cases. If all the inputs are at V 0  (0.5 volt) and the voltage at A is 1v, the diodes F 1  and F 2  do not conduct, the gate is at zero potential and the transistor T does not conduct. 
     Preferably, the diodes D will be Schottky diodes, because these do not involve minority charge carriers; the speed of operation is improved. 
     By contrast, the diodes F should be conventional junction type diodes because their threshold value is higher (≃ 0.7 v) and the stored charge can accelerate the variations in gate potential. The diode Z can be of either type. 
     FIG. 4 illustrates the characteristic V S  = f (V E ). for the case shown in FIG. 2. 
     In the present case, it is the current flowing through the transistor T which is used to feed the following stages. Thus it is the current passed at the saturation limit which determines the &#34;fan out&#34; that is to say the number of elements which the element in question can supply. 
     For low-consumption logic circuits, an input current i E  of 30 μA can be taken as the basis. 
     If a &#34;fan out&#34; of 5 is required, then the saturation current of the transistor, at the voltage Vg corresponding to the logic level 0 (in the case of the output) or 1 (in the case of the input) should be slightly more than five times the input current of the following gates, taking into account the current flowing through the load resistor which can assumed to be in the order of i E , so that: 
     
         I.sub.DS 1 ≃ 200 μA 
    
     for Vg = 0 volts. 
     The voltage V E  corresponding to the 0 input condition, should be ≦ the pinch-off voltage V p  of the transistor (output voltage at level 1), equal to the saturation voltage V S  of the transistor; to obtain V p  = V S  = 1v, a channel thickness of ≃ 0.4 μ for a concentration of n ≃ 10 16  at/cm -   3  is required. 
     Since the supply voltage is around 4 volts, the respective 0 and 1 are thus: 
     0 1 volt 
     1 4 volts 
     this gives us R C  = (V a  - V S )/i E  = 10 5 Ω 
     The noise margin is in the order of 1 volt in both directions. 
     The resistances R 1  and R 2  are equal to R C . 
     The length of the channel is 2 μ, and its width 40 μ. 
     The two following figures illustrate the circuit of FIG. 2, in plan and transverse section, after integration by the method described in the Patent Application referred to earlier. 
     The substrate 1 is of p-conductive silicon with a concentration of ≃ 10 13  at-cm 3 , that is to say it is a semiinsulator. A silica layer (SiO 2 ) 2 has been deposited upon the substrate, for example by cathode sputtering. Its thickness is around 8,000 A (FIG. 6). 
     Windows 3 for the source of the transistor T, 4 for its drain, 5 for the supply contact, 6 for the contact between the diodes D 1  to D 4  and the resistor R 1 , 7, 8, 9 and 10 for the connection to the cathodes of the diodes F 1  to F 4 , 11 for the contact connecting the resistor R 2  to the battery B 2 , and 12, 13, 14, 15 for the connections to the cathodes of the diodes D 1  to D 4 , are opened in this layer by a technique of electronic masking (FIGS. 5 and 6). 
     Using phosphorus ion implantation, there are implanted in these windows zones of n+ type (concentration 10 20  at/cm 3 ); the implantation energy is in the order of 100 Kev, and the thickness of the implanted layer is ≃ 0.6 μ. 
     Using electronic masking and chemical or ion etching, the windows 16 are opened in order to delimit the channel of the transistor T, the windows 17, 18, 19, 20 to delimit the cathodes of the diodes F 1  to F 4 , the windows 21, 22, 23, 24 to delimit the cathodes of the diodes D 1  to D 4 , and the windows 25, 26, and 27 to respectively delimit the resistors R 2 , R 1  to RC. 
     In these windows phosphorus ions are implanted at an energy of 150 Kev in order to produce a thickness of 0.7 μ and an impurity concentration of 10 16  at/cm 3 . 
     The system is annealed at around 600°C for a half an hour in order to reconstitute the crystal lattice. 
     A new layer of SiO 2 , 0.6 μ in thickness is deposited by cathode sputtering in order to reclose all these windows. 
     A window 28 is formed inside the old window 16, by electronic masking and chemical etching, in order to delimit the gate; at the same time, the windows 29, 30, 31, 32 in which the anodes of the diodes F 1  to F 4  are to be implanted, are formed. 
     In the zones corresponding to these windows, boron ions are implanted at an energy of 50 Kev. The thickness of the implanted layer is ≃ 0.3 μ and the p+ impurity concentration is ≃ 10 20  at/cm 3 . 
     The channel thickness is thus ≃ 4.10 -   5  cm. Annealing is carried out for half an hour at 800°C in order to reconstitute the crystal lattice. 
     Windows 3, 34, 35, 36 and 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 are opened by electronic masking and chemical etching or ion etching, in order to respectively delimit the anodes of the Schottky diodes D 1  to D 4  and the various contacts. 
     Aluminium is deposited over the whole of the surface using a cathode-sputtering process. 
     The Schottky diodes D 1  to D 4  and the contact zones 37 to 49 are then delimited by electronic masking and chemical or ion etching. 
     A gate of this kind draws around 160 μW. 
     It has a propagation time of some nanoseconds. 
     Logic circuits of this kind are more highly resistant to the effects of radiation than ones manufactured using MOS transistors. They are little affected by the application of over-voltages to the gate.