Adaptable programmed calculator having provision for plug-in keyboard and memory modules
This is a continuation of application Ser. No. 318,451, filed Dec. 26, 1972, now abandoned. 
    
    
     TABLE OF CONTENTS 
     Title of Section 
     Background of the Invention 
     Summary of the Invention 
     Description of the Drawings 
     Description of the Preferred Embodiment 
     System Architecture 
     Arithmetic and Register Circuit 
     Read-Only Memory Circuit 
     Input/Output Circuit 
     Data Storage Circuit 
     Clock Driver 
     Led display 
     Output Printer 
     Power Supply 
     Plug-In Keyboard Function Block 
     Plug-In ROM/PROM Option 
     Data Storage Option 
     Instruction Set 1 
     Instruction Set 2 
     System Microprogramming 
     Detailed Listing of Routines and Subroutines of Instructions 
     Calculator Operation 
     Diagnostic Notes 
     BACKGROUND OF THE INVENTION 
     This invention relates generally to calculators and improvements therein and more particularly to calculators which may be easily adapted to meet the specific needs of each user. 
     Calculators constructed according to the prior art have generally taken one of two approaches toward reducing the labor content of repetitious, routine computational tasks. The first is by means of programmability. The programmable machine has the inherent advantage of program versatility in that it can be programmed to solve problems encountered in nearly all disciplines including mathematics, science, engineering, business, finance, statistics, etc. Unfortunately, this versatility has added significantly to cost. The user is, therefore, paying for considerably more calculating capability and versatility than is required, for instance, in solving repetitive problems related to the same discipline. The approach which has recently been taken to solve this problem is that of a &#34;dedicated&#34; calculator. Such a machine generally has built-in, fixed programming which allows it to handle only a narrow range of problems. Even though these dedicated calculators are less expensive than programmable types, they have a serious shortcoming in that their programs can not be changed. 
     SUMMARY OF THE INVENTION 
     The principal object of this invention is to provide an improved programmed calculator that has more capability and flexibility than conventional calculators which are dedicated for solving a narrow range of problems and which is smaller and less expensive than conventional programmable calculators. 
     Another object of this invention is to provide an adaptable calculator in which programs stored in a read-only memory or programmable read-only memory are written at the user language level rather than the microprogram level, thereby allowing the user to generate or alter such programs without knowledge of the microprogramming language of the calculator. 
     Another object of this invention is to provide an adaptable calculator in which the user may enlarge the keyboard thereof by plugging into said keyboard a function block containing a plurality of keys together with associated read-only memory, said keys either representing predefined functions or functions definable by the user. 
     Another object of this invention is to provide an adaptable calculator in which a definable plug-in function block for enlarging the keyboard of the calculator contains a table of microprogram functions and in which such functions, together with additional functions from a microprogram library contained elsewhere in the calculator, may be selectively employed to construct functions or programs to be associated with particular ones of a plurality of keys contained within said function block. 
     Another object of this invention is to provide an adaptable calculator in which a program stored in a plug-in read-only memory or a plug-in programmable read-only memory can call not only microprogram functions stored within the calculator mainframe, but also microprogram functions stored within a plug-in keyboard function block employed in the calculator. 
     Another object of this invention is to provide an adaptable calculator in which each key of a user-definable keyboard function block represents a function or program defined, by a read-only memory or programmable read-only memory currently plugged into the calculator, as a sequence of microprogram subroutines which are contained within the calculator mainframe and/or the user-definable function block and which may or may not be represented as keyboard functions. 
     Another object of this invention is to provide an adaptable calculator in which a user-level program written in a read-only memory or a programmable read-only memory may be run without the availability of keys associated with program writing. 
     Another object of this invention is to provide an adaptable calculator in which each peripheral input/output unit is interfaced to the calculator by means of a single printed circuit board which contains all necessary hardware and software for driving the peripheral. 
     Another object of this invention is to provide an adaptable calculator in which the user may designate an automatic decimal point mode for automatically placing the decimal point in entered data at a preselected position. 
     Another object of this invention is to provide an adaptable calculator in which the user may employ a PER CENT key in combination with data and one or more of the four arithmetic operators. 
     Another object of this invention is to provide an adaptable calculator in which the user may enter various items of data, each followed by an arithmetic operator and may enter an equal sign following any of the entered arithmetic operators for calculating the result to that point. 
     Other and incidental objects of this invention will become apparent from a reading of this specification and an inspection of the accompanying drawings. 
     These objects are accomplished in accordance with the illustrated preferred embodiment of this invention by employing a keyboard input unit, an optional light-emitting diode (LED) display, an output printer, and five MOS/LSI circuits. 
     The keyboard input unit includes a group of data keys for entering numeric data into the calculator, a group of control keys for controlling the various modes of the calculator and the operations of the output printer, a group of operand keys for designating the mathematical operations to be performed on various items of data, and a group of program keys for controlling the execution of library programs stored within a plug-in read-only memory (ROM) or programmable read-only memory (PROM). 
     The keyboard also includes a blank section which will accommodate a plug-in function block containing fifteen keys and associated read-only memory. Various function blocks may be dedicated to different disciplines and problem solving areas. For example, a dedicated function block oriented toward statistics includes keys whose representative functions would be helpful in solving statistical problems. Likewise, a mathematics function block would include various mathematical functions available as the result of key actuations. In addition, a user-definable function block may be plugged into the calculator keyboard. This block contains 15 keys, each having a transparent cap which the user may remove for the purpose of inserting a function label. Each of these keys is associated with a particular function or program contained within a plug-in ROM or PROM currently employed with the calculator. Such function or program may then be called by simply actuating the associated key of the user-definable function block. 
     The optional 15-digit LED output display unit is contained within a plug-in printed circuit board which is automatically accommodated by the calculator. 
     The 18-column output printer unit is an integral part of the calculator and gives a printed record of entered data, arithmetic operators, calculated results, and diagnostic notes. Printing may be suppressed and otherwise controlled by means of keys on the keyboard input unit. 
     The MOS/LSI circuits include eight read-only memory circuits in which subroutines for performing various functions are stored. These circuits also supervise program execution and serve to control any peripheral input/output units which may be connected to the calculator. The read-only memory group comprises these eight individual read-only memory circuits which are identical in structure and differ only in the way in which they are programmed. 
     A control and timing circuit is used for scanning the keyboard, for retaining status information relating to the condition of the calculator or of a particular subroutine, and for generating a next address in read-only memory. 
     An arithmetic and register circuit contains an adder, a group of working registers, a group of data storage registers forming a stack, and a constant storage register for storing microprogramming level flags associated with various subroutines. 
     A data storage circuit provides ten data storage registers, five of which are used for parentheses nesting, three of which are used for performing various internal system housekeeping functions at the microprogram level, one of which is a grand total register which may be interrogated by the user, and the last of which is accessible to the user for storing a single item of data. 
     The last MOS/LSI circuit, the input/output (I/O) circuit, enables the calculator to communicate with various I/O peripheral units such as a typewriter on an X-Y plotter and determines whether the proper peripheral configuration for running a particular program is present. It also includes a binary arithmetic logic unit (ALU) for performing binary arithmetic, a program address counter used in running programs, and the necessary logic circuit for driving the internal printer unit. 
     The calculator may be operated manually from the keyboard input unit utilizing functions available as keys on the basic keyboard, on a dedicated plug-in function block, or on a user-definable plug-in function block. The calculator may also be operated automatically from a program comprising user-level language instructions and stored in a plug-in read-only memory unit (ROM), a plug-in programmable read-only memory unit (PROM) or a read/write memory unit associated with a plug-in magnetic card reading and recording unit. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a front perspective view of an adaptable calculator according to the preferred embodiment of this invention. 
     FIG. 2 is a rear perspective view of the adaptable calculator of FIG. 1. 
     FIG. 3 is a block diagram of the calculator of FIG. 1. 
     FIG. 4 is a detailed schematic diagram showing the interconnection of the arithmetic and register circuit and the control and logic circuit of FIG. 3. 
     FIG. 5 is a waveform diagram illustrating the timing sequence of the interconnecting busses of FIG. 3. 
     FIG. 6 is a block diagram of the control and timing circuit of FIG. 3. 
     FIG. 7 is a more detailed block diagram of the keyboard scanning circuitry of FIG. 6. 
     FIG. 8 is a detailed schematic diagram of the keyboard circuitry of FIG. 7. 
     FIG. 9 is a block diagram of the arithmetic and register circuit of FIG. 3. 
     FIG. 10 is a path diagram of the actual data paths for the registers A-F and M of FIG. 9. 
     FIG. 11 is a waveform diagram illustrating the output signals for the display decoder outputs A-E of FIGS. 9 and 10. 
     FIG. 12 is a waveform diagram illustrating the actual signals on the display decoder outputs A-E of FIGS. 9 and 10 when the digit 9 is decoded. 
     FIG. 13 is a waveform diagram illustrating the timing of the START signal generated by the display decoder of FIG. 9. 
     FIG. 14 is a schematic diagram of the clock driver of FIG. 4. 
     FIG. 15 is a waveform diagram illustrating the timing relationship between the input and output signals of the clock driver of FIG. 14. 
     FIG. 16 is a detailed schematic diagram of the read-only memory group of FIG. 3. 
     FIG. 17 is a block diagram of one of the read-only memory circuits φ-7 of FIG. 16. 
     FIG. 18 is a waveform diagram illustrating a typical address signal and a typical instruction signal. 
     FIG. 19 is a timing diagram illustrating the important timing points for a typical addressing sequence. 
     FIG. 20 is a waveform diagram illustrating the word select signals generated in the control and timing circuit of FIGS. 3 and 6 and in the read-only memory circuits φ-7 of FIG. 3 and 17. 
     FIG. 21 is a detailed schematic diagram of the input/output (I/O) processor of FIG. 3. 
     FIGS. 22A-B are a block diagram of the I/O circuit of FIG. 21. 
     FIG. 23 is a waveform diagram illustrating the timing relationship between the SYNC, START, EERA, I S , SRI, and IXT signals of the I/O circuit of FIG. 22. 
     FIG. 24 is a detailed schematic diagram of the data storage assembly of FIG. 3. 
     FIGS. 25A-B are a block diagram of the data storage circuit of FIG. 24. 
     FIG. 26 is a waveform diagram illustrating the timing relationship between the SYNC, START, I S , and BCD signals of the data storage circuit of FIG. 25. 
     FIG. 27 is a detailed schematic diagram of the timing circuitry associated with the printer of FIG. 3. 
     FIG. 28 is a detailed schematic diagram of the driver circuitry associated with the printer of FIG. 3. 
     FIG. 29 is a block diagram of the LED display of FIG. 3. 
     FIG. 30 is a logic diagram of the anode driver of FIG. 29. 
     FIG. 31 is a waveform diagram illustrating the timing relationship between various signals associated with the anode driver of FIGS. 29 and 30. 
     FIG. 32 is a schematic diagram of the basic inductive drive circuit for one of the light emitting diodes employed in the LED display of FIGS. 3 and 29. 
     FIG. 33 is a waveform diagram illustrating the timing relationship between the decimal point drive signals for the LED display of FIGS. 3 and 29. 
     FIG. 34 is a schematic diagram of the inductive drive circuit for one digit of the LED display of FIGS. 3 and 29. 
     FIG. 35 is a logic diagram of the cathode driver of FIG. 29. 
     FIG. 36 is a schematic diagram of the LED display of FIG. 3. 
     FIG. 37 is a schematic diagram of one segment of the LED display of FIGS. 3 and 36. 
     FIG. 38 is an equivalent piecewise-linear model for the circuitry of FIG. 37. 
     FIG. 39 is a waveform diagram illustrating the inductor current and LED anode voltages associated with the circuitry of FIG. 37. 
     FIG. 40 is a schematic diagram of a system clock generator employed by the calculator in the absence of the LED display option. 
     FIG. 41 is a schematic diagram of a power supply system which may be employed by the calculator of FIG. 1. 
     FIG. 42 is a flow chart of the overall microprograming system employed with the calculator of FIG. 1. 
     FIG. 43 is a flow chart of a display wait loop employed in the calculator of FIG. 1. 
     FIG. 44 is a detailed schematic diagram of the ROM group select circuitry contained within the calculator. 
     FIG. 45 is a detailed schematic diagram of a plug-in keyboard function block which may be employed in the calculator of FIG. 1. 
     FIG. 46 is a detailed schematic diagram of an optional plug-in ROM/PROM which may be employed in the calculator of FIG. 1. 
     FIG. 47 is a detailed schematic diagram of an optional data storage unit which may be plugged into the calculator of FIG. 1. 
     FIG. 48 is a flow chart showing the microprograming steps involved in an open parenthesis routine employed in the calculator. 
    
    
     Description Of The Preferred Embodiment 
     SYSTEM ARCHITECTURE 
     Referring to FIGS. 1 and 2, there is shown a desk top electronic calculator 10 including a keyboard input unit 12 for entering data and instructions into the calculator, an optional seven-segment LED output display unit 14 for displaying each data entry and the results of calculations performed by the calculator. The calculator also includes an 18-column output printer unit 16 for printing intermediate and final results of calculations, entered data, arithmetic operators, and diagnostic notes. Keyboard input unit 12 also includes a covered blank section 18 which will accommodate a 15-key function block 20 for expanding the capabilities of the calculator. Function block 20 may be oriented toward a particular problem solving area in which case its keys will represent functions which are useful in making calculations relating to that discipline. Alternatively, function block 20 may be a user-definable type in which the various keys may be labeled and defined to be functions or programs stored in a ROM or PROM 22 tailored to the requirements of each user. The function or program so defined may then be executed by simply actuating the associated key on the user-definable function block. ROM or PROM 22 may be removably plugged into the calculator by means of hinged top cover 24. The calculator may employ a ROM or PROM 22 without also employing a plug-in function block 20. In such case, the ROM or PROM contains one or more programs which the user may execute from the main keyboard. 
     As shown in FIG. 2, the calculator also includes three I/O receptacles 26 covered when not in use by receptacle caps 28. These receptacles serve to connect the calculator to various I/O peripheral units such as a typewriter, a marked sense card reader, and X-Y plotter, etc. 
     As shown in the overall block diagram of FIG. 3, the calculator also includes an MOS/LSI control and timing circuit 30, an MOS/LSI arithmetic and register circuit 32, eight MOS/LSI read-only memory circuits comprising a read-only memory group 34, an MOS/LSI data storage circuit contained within a data storage assembly 36, and an MOS/LSI input/output circuit contained within an input/output processor 38. 
     The MOS/LSI circuits are two-phase dynamic types with low thresholds for assuring compatibility with standard TTL bipolar circuits and for operation at very low power levels. They are organized to process 14-digit BCD words in a digit-serial, bit-serial manner. They are also capable of bit-serially processing 56-bit binary words. The maximum bit rate or clock frequency is 200 kilohertz, which gives a word time of 280 microseconds. This means that a floating point addition may be accomplished in 60 milliseconds. 
     Control and timing circuit 30, read-only memory (ROM) group 34, arithmetic and register circuit 32, data storage assembly 36, and input/output processor 38 are tied together by a six-line bus 40. This bus comprises a SYNC line, an instruction (I s ) line, a word select (WS) line, an instruction address (I a ) line, a START line, and a BCD line. All operations occur on a 56-bit (b o  -b 55 ) word cycle (14 four-bit BCD digits). The timing sequence for some of the interconnecting lines comprising bus 40 are shown in FIG. 4. 
     The SYNC line carries synchronization signals from control and timing circuit 30 to ROM circuits φ-7 in read-only memory group 34 and to arithmetic and register circuit 32 to synchronize the calculator system. It provides one output each word time. This output also functions as a 10-bit wide window (b 45  -b 54 ) during which instruction line I s  is active. 
     The instruction line I s  carries 10-bit instructions from the active read-only memory circuit of ROM group 34 to the other ROMs, to control and timing circuit 30, to data storage assembly 36, and to input/output processor 38, each of which decodes the instructions locally and responds to or acts upon them if they pertain thereto and ignores them if they do not. In order to free instruction bit patterns normally associated with the arithmetic and register circuit and the control and timing circuit, the I s  line is gated prior to being shown to these circuits. For example, the ADD instruction affects arithmetic and register circuit 32 but is ignored by all other circuits. Similarly, the SET STATUS BIT 5 instruction sets status flip-flop 5 in control and timing circuit 30 but is ignored by all other circuits. 
     The actual implementation of an instruction is delayed one word time from its receipt. For instance, an instruction may require the addition of digit 2 in two of the registers in arithmetic and register circuit 32. The ADD instruction would be received by arithmetic and register circuit 32 during bit times b 45  -b 54  of word time N+1. Thus, while one instruction is being executed, the next instruction is being fetched. 
     The WS line carries an enable signal from control and timing circuit 30 or one of the ROM circuits in read-only memory group 34 to arithmetic and register circuit 32 to enable the instruction being executed thereby. Thus, in the example of the previous paragraph, addition occurs only during digit 2 since the adder in the arithmetic and register circuit 32 is enabled by the WS line only during this portion of the word. When the WS line is low the contents of the registers in arithmetic and register circuit 32 are recirculated unchanged. Three examples of WS timing signals are shown in FIG. 4. In the first example, digit position 2 is selected out of the entire word. In the second example, the last 11 digits are selected. This corresponds to the mantissa portion of a floating point word format. In the third example, the entire word is selected. Use of the word select feature allows selective addition, transfer, shifting or comparison of portions of the registers within arithmetic and register circuit 32 with only one basic ADD, TRANSFER, SHIFT or COMPARE instruction. Some customization in the ROM word select fields is available via masking options. 
     The I a  line serially carries the addresses of the instructions to be read from read-only memory circuits φ-7 of ROM group 34. These addresses originate from control and timing circuit 30, which contains an instruction address register that is incremented each word time unless a JUMP SUBROUTINE or a BRANCH instruction is being executed. Each address is transferred to ROMs φ-7 during bit times b 19  -b 26  and is stored in an address register of each ROM. However, only one ROM is active at any given point in time, and only the active ROM responds to an address by outputting an instruction on the I s  line. Control is transferred between the ROM circuits φ-7 by a ROM SELECT instruction. This technique allows a single eight-bit address, plus eight special instructions, to address up to eight ROMs of 256 words each. 
     The START line carries a one-bit pulse which occurs during bit time b 0  and is used to synchronize operations of data storage assembly 36 and input/output processor 38 with those of arithmetic and register circuit 32. 
     The BCD line carries numerical data between arithmetic and register circuit 32, input/output processor 38, and any basic or optional units containing data storage circuits. The format of the data carried on this line is illustrated in FIG. 4. 
     The CARRY line 42 transmits the status of the carry outputs of the adder in arithmetic and register circuit 32 to control and timing circuit 30. The control and timing circuit uses this information to make conditional branches, dependent upon the numerical value of the contents of the registers in arithmetic and register circuit 32. 
     Control and timing circuit 30 is organized to scan a five-by-eight matrix of switches in search of an interconnection that designates actuation of a key. Any type of metal-to-metal contact may be used as a key. Bounce problems associated with keyboard switch contact are overcome by programmed lockouts in a key entry routine. Each key has an associated six-bit code. To accommodate more than the 40-key maximum represented by the five-by-eight matrix scanner included in the control and timing circuit, an additional keyboard multiplexor circuit is provided. This circuitry is shown in detail in FIG. 8. 
     A standard power supply circuit contains a power-on circuit which supplies a signal for forcing the calculator to start up in a known condition when power is supplied thereto. A line switch on the calculator keyboard controls the application of operating power. The primary outputs of the calculator are a built-in printer 44 and an optional plug-in LED display unit 46. 
     CONTROL AND TIMING CIRCUIT 
     Referring now to FIGS. 4 and 6, control and timing circuit 30 contains the master system counter 52, scans the keyboard 12, retains status information about the system or the condition of an algorithm, and generates the next ROM address. It also originates the subclass of word select (WS) signals which involve the pointer 54, a four-bit counter that points to one of the register digit positions. 
     The control unit of control and timing circuit 30 is a microprogrammed controller 56 comprising a 58 word (25 bits per word) control ROM, which receives qualifier or status conditions from throughout the calculator and sequentially outputs signals to control the flow of data. Each bit in this control ROM either corresponds to a single control line or is part of a group of N bits encoded into 2 N  mutually exclusive control lines and decoded external to the control ROM. At each phase 2 clock a word is read from the control ROM as determined by its present address. Part of the output is then fed back to become the next address. 
     Several types of qualifiers are checked. Since most commands are issued only at certain bit times during the word cycle, timing qualifiers are necessary. This means the control ROM may sit in a wait loop until the appropriate timing qualifier becomes true, then move to the next address to issue a command. Other qualifiers are the state of the pointer register, the PWO (power on) line, the CARRY flip-flop, and the state of each of the 12 status bits. 
     Since the calculator is a serial system based on a 56 bit word, a six-bit system counter 52 is employed for counting to 56. Several decoders from system counter 52 are necessary. The SYNC signal is generated during bit times b 45  -b 54  and transmitted to the arithmetic and register circuit 32 and all ROM groups present in the calculator system. Other timing qualifiers are sent to the microprogrammed control ROM 56 as mentioned in the previous paragraph. 
     System counter 52 is also employed as a keyboard scanner as shown in FIG. 7. The three most significant bits of system counter 52 go to a one-of-eight decoder 58, which sequentially selects one of the keyboard row lines 60. The least significant three bits of the system counter count modulo seven and go to a one-of-five multiplexor 62, which sequentially selects one of the keyboard column lines 64 (during 16 clock times no key is scanned). The multiplexor output is called the key down signal. If a contact is made at any intersection point in the five-by-eight matrix (by depressing a key), the key down signal will become high for one state of system counter 52 (i.e., when the appropriate row and column lines are selected). The key down signal will cause that state of the system counter to be saved in key code buffer 66. This six-bit code is then transferred to the ROM address register 68 and becomes a starting address for the program which services the key that was down (two leading zero bits are added by hardware so an eight-bit address exists). Thus, during each state of system counter 52, the decoder-multiplexor combination 58 and 62 is looking to see if a specific key is down. If it is, the state of the system counter becomes a starting address for execution of that key function (note that 16 of the 56 states are not used for key codes). By sharing the function of the system counter and using a keyboard scanning technique directly interfaced to the MOS circuitry, circuit complexity is reduced significantly. 
     While the control and timing circuit 30 is capable of scanning 40 keys without the use of additional logic circuitry, the calculator keyboard 12 may be optionally configured with 50 keys. The additional keyboard multiplexing circuitry required to increase the scanning capacity of the control and timing circuit to 50 keys is shown in FIG. 8. 
     A 28-bit shift register which circulates twice each 56-bit word time is employed in the control and timing circuit of FIG. 6. These 28 bits are divided into three functional groups, namely the main ROM address register 68 (eight bits), the subroutine return address register 70 (eight bits), and the status register 72 (twelve bits). 
     The main read-only memories φ-7 each contain 256 words of ten bits each, thereby requiring an eight-bit address. This address circulates through a serial adder/subtractor 74 and is incremented during bit times b 47  -b 54  (except in the case of BRANCH and JUMP SUBROUTINE instructions, for which the eight-bit address field of the ten-bit instruction is substituted for the current address). The next address is transmitted over the I a  line to each of the main ROMs φ-7 during bit times b 19  -b 26 . 
     The status register 72 contains 12 bits or flags which are used to keep track of the state of the calculator. Such information as whether the decimal point has been hit, the minus sign set, etc. must be retained in the status bits. In each case the calculator remembers past events by setting an appropriate status bit and asking later if it is set. A yes answer to a status interrogation will set the carry flip-flop 76 as indicated by control signal IST in FIG. 6. Any status bit can be set, reset, or interrogated while circulating through the adder 74 in response to the appropriate instruction. 
     The instruction set allows one level of subroutine call. The return address is stored in the eight-bit return address register 70. Execution of a JUMP SUBROUTINE instruction stores the incremented present address into return address register 70. Execution of the RETURN instruction retrieves this address for transmission over the I a  line. Gating is employed to interrogate the 28 bits circulating in the shift register 68-72 for insertion of addresses at the proper time as indicated by the JSB control signal in FIG. 6. 
     An important feature of the calculator system is the capability to select and operate upon a single digit or a group of digits (such as the exponent field) from the 14-digit registers. This feature is implemented through the use of a four-bit pointer 54 which points to the digit of interest. Instructions are available to set, increment, decrement, and interrogate pointer 54. The pointer is incremented or decremented by the same serial adder/subtractor 74 used for addresses. A yes answer to the IS POINTER N instruction will set the carry flip-flop 76 via control signal IPT in FIG. 6. 
     The word select feature was discussed above in connection with FIGS. 3 and 5. Some of the word select signals are generated in control and timing circuit 30, namely those dependent on pointer 54, and the remainder in the main read-only memories φ-7. The pointer word select options are (1) pointer position only and (2) pointer position and all less significant digits. For instance, assume the mantissa signs of the numbers in the A and C registers of arithmetic and register circuit 32 are to be exchanged. The pointer would be set to position 13 (last position) and the A EXCHANGE C instruction with a pointer position word select field would be given. If all of the word except the mantissa signs are to be exchanged, the A EXCHANGE C instruction would be given with the pointer set at 12 and the word select field set to pointer and less significant digits. The control and timing circuit word select (WS) output is OR connected with the ROM word select output and transmitted to arithmetic and register circuit 32. 
     Any carry signal out of the adder in arithmetic and register circuit 32, with word select also high, will set carry flip-flop 76. This flip-flop is interrogated during the BRANCH instruction to determine if the existing address should be incremented (yes carry) or replaced by the branch address (no carry). The branch address is retained in an eight-bit address buffer 78 and gated to the I a  line by the BRH control signal. 
     The power-on signal is used to synchronize and preset the starting conditions of the calculator. It has two functions, one of which is to get the address of control ROM 56 set to a proper starting state, and the other of which is to get the system counter 52 in control and timing circuit 30 synchronized with the counter in each main ROM φ-7. As the system power comes on, the PWO signal is held at a logical 1 (0 volts in this system) for at least one second. This allows system counter 52 to make at least one pass through bit times b 45  -b 54  when SYNC is high, thereby setting main ROM φ active and the rest of the ROMs inactive. When PWO goes to a logical 0 (+6 volts), the address of control ROM 56 is set to 000000 where proper operation can begin. 
     ARITHMETIC AND REGISTER CIRCUIT 
     Arithmetic and register circuit 32 shown in FIG. 9 provides the arithmetic functions and a portion of the data storage for the calculator. It is controlled by the WS, I s , and SYNC lines and receives instructions from the ROMs φ-7 over the I s  line, sends information back to control and timing circuit 30 via the CARRY line 42, partially decodes the display information before transmitting it via output lines 80 to the anode driver of output display unit 14, and provides a START pulse to the cathode driver of output display unit 14 for synchronizing the display, said START pulse also being used for synchronizing the input/output processor and all data storage circuits employed in the calculator. 
     Arithmetic and register circuit 32 contains seven 14-digit (56-bit) dynamic registers A-F and M and a serial BCD adder/subtractor 82. Actual data paths, not shown in FIG. 9 due to their complexity, are discussed below and shown in FIG. 10. The power and flexibility of an instruction set is determined to a great extent by the variety of data paths available. One of the advantages of a serial structure is that additional data paths are not very costly (only one additional gate per path). The structure of arithmetic and register circuit 32 is optimized for the type of algorithms required by the calculator. 
     The seven registers A-F and M can be divided into three groups: (1) the working registers A, B, and C with C also being the bottom register of a four-register stack; (2) the next three registers D, E, and F in the stack; and (3) a separate storage register M communicating with the other registers through register C only. In FIG. 10, which shows the data paths connecting all the registers A-F and M, each circle represents the 56-bit register designated by the letter in the circle. In the idle state (when no instruction is being executed in arithmetic and register circuit 32) each register continually circulates since with dynamic MOS registers information is represented by a charge on a parasitic capacitance and must be continually refreshed or lost. This is represented by the loop re-entering each register. 
     Registers A, B, and C can all be interchanged. Either register A or C is connected to one adder input, and either register B or C to the other. The adder output can be directed to either register A or C. Certain instructions can generate a carry via carry flip-flop 76 which is transmitted to control and timing circuit 30 to determine conditional branching. Register C always holds a normalized version of the displayed data. 
     In the stack formed by registers C, D, E and F a ROLL DOWN instruction is executed by the following transfers: F→E→D→C→D. A STACK UP instruction is executed by the following transfers:  C→D→E→F. Thus, it is possible to transfer a register and also let it recirculate so that, in the last example, the contents of C are not lost. The structure and operation of a stack such as this are further described in copending U.S. Patent Application Ser. No. 257,606 entitled IMPROVED PORTABLE ELECTRONIC CALCULATOR, filed on May 30, 1972, by David S. Cochran et al., and issued on Dec. 25, 1973, as U.S. Pat. No. 3,781,820. 
     In serial decimal adder/subtractor 82 a correction (addition of 6) to a BCD sum must be made if the sum exceeds nine (a similar correction for subtraction is necessary). It is not known if a correction is needed until the first three bits of the sum have been generated. This is accomplished by adding a four-bit holding register 84 (A 60  -A 57 ) and inserting the corrected sum into a portion 88 (A 56  -A 53 ) of register A if a carry is generated. This holding register 84 is also required for the SHIFT A LEFT instruction. One of the characteristics of a decimal adder is that non-BCD codes, such as 1101, are not allowed. They will be modified if circulated through the adder. The adder logic is minimized to save circuit area. If four-bit codes other than 0000-1001 are processed, they will be modified. This is no constraint for applications involving only numeric data (however, if ASCII codes, for instance, are operated upon, incorrect results will be obtained). 
     Arithmetic and register circuit 32 receives the instruction during bit times b 45  - b 54 . Of the ten types of instructions hereinafter described, arithmetic and register circuit 32 must respond to only two types, namely ARITHMETIC &amp; REGISTER instructions and DATA ENTRY/DISPLAY instructions. ARITHMETIC &amp; REGISTER instructions are coded by a 10 in the two least significant bits of I s  register 86. When this combination is detected the most significant five bits are saved in I s  register 86 and decoded by instruction decoder 90 into one of 32 instructions. 
     The ARITHMETIC &amp; REGISTER instructions are active or operative only when the word select signal (WS) generated in one of the ROMs φ-7 or in control and timing circuit 30 is a logical one. For instance, suppose the instruction A+C→C, MANTISSA WITH SIGN ONLY is called. Arithmetic and register circuit 32 decodes only A+C→C. It sets up registers A and C at the inputs to adder 82 and, when WS is high, directs the adder output to register C. Actual addition takes place only during bit times b 12  to b 55  (digits 3-13) since for the first three digit times the exponent and exponent sign are circulating and are directed unchanged back to their original registers. Thus, the word select signal is an INSTRUCTION ENABLE in arithmetic and register circuit 32 (when it is a logical 1, instruction execution takes place, and when it is a logical 0, recirculation of all registers continues). 
     The DATA ENTRY/DISPLAY instructions, except for digit entry, affect an entire register (the word select signal generated in the active ROM is a logical 1 for the entire word cycle). 
     Some of these instructions are: UP STACK, DOWN STACK, MEMORY, EXCHANGE M←→C, DISPLAY ON, or DISPLAY TOGGLE. A detailed description of their execution is given hereinafter. 
     For greater power savings, display decoder 92 is partitioned to partially decode the BCD data into seven segments and a decimal point in arithmetic and register circuit 32 by using only five output lines (A-E) 80 with time as the other parameter. Information for seven segments (a-g) and a decimal point (dp) are time shared on the five output lines A-E. The output wave forms for output lines A-E are shown in FIG. 11. For example, output line D carries the segment e information during T 1  (the first bit time of each digit time) and the segment d information during T 2  (the second bit time of each digit time); output E carries the segment g information during T 1 , the segment f information during T 2 , and the decimal point (dp) during T 4 . The actual signals which would appear if the digit 9 were decoded are shown in FIG. 12. The decoding is completed in the anode driver of output display unit 14 as explained hereinafter. 
     The registers in arithmetic and register circuit 32 hold fourteen digits comprising ten mantissa digits, the mantissa sign, two exponent digits, and the exponent sign. Although the decimal point is not allocated a register position, it is given a full digit position in the output display. This apparent inconsistency is achieved by using both the A and B registers to hold display information. The A register is set up to hold the displayed number with the digits in the proper order. The B register is used as a masking register with the digit 9 inserted at the decimal point location. When the anode driver of output display unit 14 detects a decimal point code during T 4 , it provides a signal to the cathode driver of the output display unit directing a move to the next digit position. One digit and the decimal point share one of the fourteen digit times. The digit 9 mask in register B allows both trailing and leading zeros to be blanked (i.e., by programming nines into the B register). Use of all three working registers for display (i.e., the C register to retain the number in normalized form, the A register to hold the number in the displayed form, and the B register as a mask) allows the calculator to have both a floating point and a scientific display format at the expense of only a few more ROM states. 
     The display blanking is handled as follows. At time T 4  the BCD digit is gated from register A into display buffer 94. If this digit is to be blanked, register B will contain a nine (1001) so that at T 4  the end bit (B 01 ) of the B register will be a one (an eight would therefore also work). The input to display buffer 94 is OR connected with B 01  and will be set to 1111 if the digit is to be blanked. The decimal point is handled in a similar way. A two (0010) is placed in register B at the decimal point location. At time T 2  the decimal point buffer flip-flop is set by B 01 . Any digit with a one in the second position will set the decimal point (i.e., 2, 3, 6, or 7). 
     Display decoder 92 also applies a START signal to line 48. This signal is a word synchronization pulse, which resets the digit scanner in the cathode driver of output display unit 14 to assure that the cathode driver will select digit 1 when the digit 1 information is on outputs A, B, C, D, and E. The timing for this signal is shown in FIG. 13. 
     One other special decoding feature is required. A minus sign is represented in tens complement notation or sign and magnitude notation by the digit 9 in the sign location. However, the display must show only a minus sign (i.e., segment g). The digit 9 in register A in digit position 2 (exponent sign) or position 13 (mantissa sign) must be displayed as minus. The decoding circuitry uses the pulse on the I s  line at bit time b 11  (see FIG. 5) to known that the digit 9 in digit position 2 of register A should be a minus and uses the SYNC pulse to know that the digit 9 in digit position 13 of register A should also be a minus. The pulse on the I s  line at bit time b 11  can be set by a mask option, which allows the minus sign of the exponent to appear in other locations for other uses of the calculator circuits. 
     READ-ONLY MEMORY CIRCUIT 
     ROM group 34, as shown in FIG. 3, contains eight individual MOS read-only memory circuits, labeled φ-7. These circuits store the subroutines required for executing various functions of the calculator system. Each ROM circuit contains 256 ten-bit words, which means a total of 15,360 bits available in the entire ROM group. A detailed diagram of ROM group 34, showing each of the ROM circuits φ-7, is given in FIG. 16. A block diagram of one of the ROM circuits is shown in FIG. 17. Since the ROM circuits φ-7 are identical except for the way in which they are programmed, only one circuit is shown in the block diagram. 
     In addition to ROM group 34 contained within the basic calculator, other ROM groups may be present in a particular calculator configuration by virtue of their presence in various ones of the calculator options. For example, each plug-in keyboard function block contains a ROM group, as does the data storage option and each peripheral input/output interface card. 
     FIG. 44 shows in detail the circuitry required for selecting the ROM group required to perform each given function. The heart of this circuitry is a set of three flip-flops whose outputs are designated A, B, and C. Each of these flip-flops comprises one-half of a dual D-type flip-flop package 184. Several logic gates are employed for controlling the states of these flip-flops. Outputs A, B, and C are connected to ROM group 34 in the main system, the function block ROM group, and the data storage option ROM group, respectively. These outputs control the clamping gates of their respective ROM groups. 
     The ROM group associated with each peripheral input/output interface card is responsible for controlling itself and, therefore, includes its own flip-flop. At the time such a ROM group is turned on, the selected peripheral I/O unit will place a negative-true pulse on the line labeled RGC in FIG. 44. This causes flip-flops A, B, and C to be reset. 
     FIG. 44 also includes power-on circuitry 186 which provides a signal (PWO) for initializing all of the calculator hardware. PWO will remain low for approximately 1.5 seconds after the power supplies are fully active. This guarantees that the printer motor has come up to speed and that the printer sector counter in the I/O circuit has been synchronized with the printer. In summary, the PWO signal performs the following functions: 
     1. Inhibits spurious printer operation during start-up 
     2. Resets printer circuitry contained within the I/O circuit 
     3. Selects instruction set 1 
     4. Selects basic system ROM group (ROM group A) 
     5. turns on ROM φ in each ROM group 
     6. Insures that the first ROM address given after termination of the PWO signal is address zero 
     Basically, each ROM circuit within main system ROM group 34 of FIG. 16 responds to a serial address input with a serial address output. During every 56-bit word time, an address is inputted, least significant bit first, from bit b 19  through bit b 26 . Every ROM φ-7 in the system receives this same eight-bit address and, from bit time b 45  through b 54 , attempts to output onto the I s  line. However, a ROM enable (ROE) flip-flop 96 in each ROM insures that no more than one ROM actually sends an instruction on the I s  line at the same time. 
     All output signals are inverted so that the steady-state power dissipation is reduced. The calculator circuits are P-channel MOS. Thus, the active signals that turn on a gate are the more negative. This is referred to as negative logic, since the more negative logic level is the logical 1. As mentioned above, a logical 0 is +6 volts and a logical 1 is 0 volts. The signals on the I a  and I s  lines are normally at logical 0. However, when the output buffer circuits are left at logical 0 they consume more power. A decision was therefore made to invert the signals on the I a  and I s  outputs and re-invert the signals at all inputs. Thus, signals appear at the I a  and I s  outputs as positive logic. The oscilloscope pattern that would be seen for instruction 1101 110 011 from state 11 010 101 is shown in FIG. 19. 
     The serial nature of the calculator circuits requires careful synchronization. This synchronization is provided by the SYNC pulse, generated in control and timing circuit 30 and existing during bit times b 45  - b 54 . Each ROM has its own 56-state counter 98, synchronized to the system counter 52 in control and timing circuit 30. Decoded signals from this state counter 98 open the input to the address register 100 at bit time b 19 , clock I s  out at bit time b 45 , and provide other timing control signals. 
     As the system power comes on, the PWO signal is held at 0 volts (logical 1 ) for at least one second. The PWO signal is wired (via a masking option) to set ROM enable (ROE) flip-flop 96 on main ROM φ and to reset it on all other ROMs. Thus, when operation begins, ROM φ will be the only active ROM. In addition, control and timing circuit 30 inhibits the address output during start-up so that the first ROM address will be zero. The first instruction must be a JUMP SUBROUTINE to get the address register 68 in control and timing circuit 30 loaded properly. 
     FIG. 18 shows the important timing points for a typical addressing sequence. During bit times b 19  - b 26  the address is received serially from control and timing circuit 30 and loaded into address register 100 via the I a  line. This address is decoded, and at bit time b 44  the selected instruction is gated in parallel into the I s  register 102. During bit times b 45  - b 54  the instruction is read serially onto the I s  line from the active ROM (i.e., the ROM with the ROM enable flip-flop set). 
     Control is transferred between ROMs by a ROM SELECT instruction. This instruction will turn off ROE flip-flop 96 on the active ROM and turn on ROE flip-flop 96 on the selected ROM. Implementation is dependent upon the ROE flip-flop being a master-slave flip-flop. In the active ROM, the ROM SELECT instruction is decoded by a ROM select decoder 104 at bit time 44, and the master portion of ROE flip-flop 96 is set. The slave portion of ROE flip-flop 96 is not set until the end of the word time (b 55 ). In the inactive ROMs the instruction is read serially into the I s  register 102 during bit times b 45  - b 54  and then decoded, and the ROE flip-flop 96 is set at bit time b 55  in the selected ROM. A masking option on the decoding from the three least significant bits of the I s  register 102 allows each ROM to respond only to its own code. 
     The six secondary word select signals are generated in the main ROMs φ-7. Only the two word select signals dependent upon the POINTER come from control and timing circuit 30. The word select of the instruction is retained in the word select register 106 (also a master-slave). If the first two bits are 01, the instruction is of the arithmetic type for which the ROM must generate a word select gating signal. At bit time b 55  the next three bits are gated to the slave and retained for the next word time to be decoded into one of six signals. The synchronization counter 98 provides timing information to the word select decoder 108. The output WS signal is gated by ROE flip-flop 96 so only the active ROM can output on the WS line, which is OR connected with all other ROMs and also control and timing circuit 30. As discussed above, the WS signal goes to arithmetic and register circuit 32 to control the portion of a word time during which an instruction is active. 
     The six ROM-generated word select signals used in the calculator are shown in FIG. 20. Read-only memories φ-7 output a single pulse on the I s  line at bit time b 11  to denote the exponent minus sign time. This pulse is used in the display decoder of arithmetic and register circuit 32 to convert a 9 into a displayed minus sign. The time location of this pulse is a mask option on the ROM. 
     INPUT/OUTPUT CIRCUIT 
     The input/output (I/O) processor 38 of FIG. 3 is shown in more detail in FIG. 21. It includes an MOS/LSI input/output circuit 110, a one-of- 16 decoder 112, and various other logic gates. The I/O processor serves as a binary arithmetic logic unit, drives the printer unit (Seiko model 102), and controls the flow of instructions and addresses between the arithmetic and register circuit, the control and timing circuit, and the read-only memory group. 
     I/O processor 38 is linked to the arithmetic and register circuit and the control and timing circuit by eight signals, which are (1) input clock phase (φ 1 ), (2) output clock phase (φ 2 ), (3) power on (PWO), (4) instruction line (I s ), (5) timing (START), (6) data bus (BCD), (7) flag line (FLG), and (8) alternate ROM address input (EXT). 
     I/O circuit 110 includes twenty outputs (C1-C20) comprising parallel data signals used by the printer unit. C13 controls the printer solenoid for column 13. C19 and C20 control the PRINT, STANDBY, ADVANCE PAPER, and RED commands. Outputs C9-C18 are employed as memory address lines when a ROM, PROM, or read/write memory is plugged into the calculator. Output lines C1-C8 are bidirectional and are used as inputs when the LATCH line is grounded. Output lines C1-C18, along with the LATCH and GIOE lines, are available at each I/O peripheral slot to be used as needed by each peripheral unit, as directed by the interface software associated with each such peripheral unit. 
     The EISI line of FIG. 21 is used as a gate control for the instruction line I s . It also comprises one of the inputs, along with lines IOC1, IOC2, and IOC3, to one-of- 16 decoder 112. Switching transients might be expected to appear as the various IOC lines change state. To eliminate this problem, a decoder strobe signal SCE is issued by I/O circuit 110. By means of this technique, a total of 14 different command signals are received from decoder 112 as pulses of approximately 200 microsecond duration. These signals are described in the table below. 
     
         ______________________________________                                    
Decoder Pin No.      Function                                             
______________________________________                                    
1           Interrogate PRINT OFF key                                     
2           Interrogate function block keyboard flag                      
3           Turn on busy light                                            
4           READ command for plug-in ROM or PROM                          
5           Interrogate AUTO DECIMAL key                                  
6           Select ROM group for data storage option                      
7           Select ROM group for function block                           
8           Return control to main ROM group                              
9           TG8 (reserved for control of peripherals)                     
10          TG9 (reserved for control of peripherals)                     
14          General I/O device enable                                     
15          Turn off busy light                                           
16          WRITE command for read/write memory                           
17          YINTF instruction reserved for control of                     
            peripherals                                                   
______________________________________                                    
 
    
     Light emitting diode (LED) 114 shown in FIG. 21 is used as a busy light. When lit, it indicates that the calculator is busy and cannot accept keyboard commands. The busy light will be turned on at the onset of the power-on sequence, during execution of one of the routines involving exponentiation, or during execution of a library program. Upon completion of any of these functions the busy light will be turned off, and the calculator will then accept keyboard entries. 
     The status of the PRINT OFF and AUTO DECIMAL keys as well as the FPS line, which originates in the keyboard multiplexor, is examined by decoder 112. If the appropriate signal is present the FLG&#39; line will be pulled low for approximately 200 microseconds. The FLG&#39; line may be used by the interface circuitry associated with various input/output peripheral units. 
     Input lines TP and TR to I/O circuit 110 are timing signals received from the printer. 
     The MOS input/output circuit 110 of FIG. 21 is shown in detail in the block diagram of FIGS. 22A-B. An instruction set switching scheme has been implemented in the I/O circuit to achieve greater efficiency. 
     The instruction lines of the read-only memories φ-7 of ROM group 34 are tied directly to the I s  input to the I/O circuit. The I/O circuit issues a signal EIS1. When this signal is high, the instruction lines of the ROM circuits are fed to the I s  line going to the control and timing circuit 30 and the arithmetic and register circuit 32. When EIS1 is low, the I s  line going to the control and timing circuit and the arithmetic and register circuit is held low, and the I/O circuit is enabled to give instructions with the same bit patterns as used normally by the control and timing circuit and the arithmetic and register circuit. Since the I/O circuit has the ability to remember in which instruction set mode it is operating, it doesn&#39;t try to execute those instructions designated as IS2 instructions when the calculator is in the IS1 mode. The power-on (PWO) line to the I/O circuit insures that the I/O circuit powers up in the IS1 instruction set. When IS1 is executed, the internal IS2 instruction flip-flop 114 is reset, which implies that EIS1 will go high and the I/O circuit will accept only those instructions whose bit patterns are the same in all instruction sets. When IS2 is executed, EIS1 will go low, and the IS2 instruction flip-flop 114 will be set. 
     The input/output circuit includes an instruction register 116 which converts the serial instruction coming from ROM group 34 on the I s  line to a parallel instruction for decoding by instruction decoding ROM 118. Nine-bit shift register 120 and one-bit shift register 122 serve as an output register for the I/O circuit. 
     I/O circuit 110 also includes a 56-bit shift register 124, called the T-register. This register serves as the primary working register when the I/O circuit is called upon to perform binary arithmetic operations. Logic gates 126 and 128 form a bidirectional buffer for the BCD line, allowing binary data to be inputted to or outputted from the I/O circuit by means of the BCD line. Binary processor ROM 130 serves as an arithmetic logic unit for performing all the basic binary operations on the contents of the T-register. It also helps control data transfers into the T-register. In performing binary arithmetic with the I/O circuit, a carry on line 132 may result from a particular operation. This condition causes a signal on the FLG line and sets status bit eleven in the control and timing circuit 30. 
     I/O circuit 110 further comprises a 14-bit register 133, known as the P-register. This register is available to the user as a 14-bit storage register, but is generally employed by the calculator system as a program counter. The 14 least significat bits in the T-register 124 can be loaded into the P-register 133, without altering the contents of T-register 124. The contents of P-register 133 can be loaded into the 14 least significant bits of T-register 124 by means of the PTT instruction. In this case, the 42 most significant bits of the T-register and the entire contents of the P-register are unaltered. 
     The PINC instruction performs a binary increment on the number stored in the P-register. Not only is the incremented binary number placed in P-register 133, but also the ten least signficant bits of the incremented number are loaded sequentially onto the output lines C9-C18. The PDEC instruction is similar to PINC except that the binary number stored in the P-register is decremented by one. The instructions PINC and PDEC have a common restriction in that if the decimal equivalent of the number in the P-register exceeds 1,023, the number displayed on output lines C9-C18 will not only have an insufficient number of bits, but the bit displayed on line C18 will always be logical 1. Arithmetic logic unit 134 is employed to perform the increment and decrement operations called for by PINC and PDEC. 
     The parallel data output lines C1-C18 are low power TTL compatible. Lines C1-C8 may be used to either input or output data, whereas lines C9-C18 are outputs only. When the LATCH input line to the I/O circuit is high, lines C1-C8 become outputs, and when LATCH is low, these lines become inputs The data found on C1-C8 when LATCH is held low is transferred into the output buffer register 136. After LATCH is released the data loaded will remain as an output on lines C1-C8. 
     The data on lines C1-C8 may be operated on by two instructions, EERA and IXT. These instruction lines are shown as 138 and 140, respectively, in FIGS. 22A-B. The instruction EERA is understood by both the control and timing circuit 30 and the I/O circuit 110. When this instruction is executed, the eight-bit word on lines C1-C8 is sent serially on the EXT output line and during the same period of time as the addresses are sent to ROM group 34. Control and timing circuit 30 recognizes the EERA command and transfers the data from its EXT input line to its IA output line. In this way the next ROM address is obtained from the I/O circuit. After executing EERA, bits C1-C8 will contain the same data (either zeros or ones) as bit C9. 
     The instruction IXT exchanges the data on lines C1-C8 with the eight most significant bits of T-register 124. The remaining bits of T-register 124, as well as lines C9-C18 of the I/O register 120, are unaltered. 
     I/O circuit 110 also contains the necessary logic circuitry and memory for driving printer unit 16, which is a Seiko model 102. This printer has 18 columns and a choice of 13 characters per column. It includes a rotating print drum having 13 sectors. Two timing signals are required from the printer as inputs to I/O circuit 110. They are labeled on FIGS. 22A-B as TP and TR and are clocked with phase two of the clocks. 
     During operation the print drum is continually rotating, and the current sector of the printer is continually noted by sector counter 142. During the portion of time that the printer is enabled the end of each sector is marked by a flag pulse which sets status bit eleven in control and timing circuit 30. The method of obtaining a print begins with the construction of a printer mask in C-register 144 of arithmetic and register circuit 32 and T-register 124 of I/O circuit 110. The columns 1-4 of the printer (right to left) are printed according to the data in the C-register. Each digit position is filled with a hexadecimal number (O-15) which represents the sector to be printed. A hexadecimal 13, 14 or 15 will leave a blank in the given column position. Printing is best accomplished when the numeric entries on the print drum coincide with their respective sector numbers. The four least significant digits of T-register 124 are loaded in a similar manner for columns 15-18. 
     The RED instruction preceding the print subroutine shifts the ribbon into the red printing position. The ribbon will remain in that position until a paper advance occurs. A paper advance instruction (ADV) is used to terminate each print sequence. The putput format for driving the printer is such that during the period of time that the printer is enabled a logical zero on lines C1-C18 indicates that the column solenoid under consideration should be energized. The outputs on lines C19 and C20 control the modes of operation of the printer as shown in the table below. 
     
         ______________________________________                                    
C19       C20       Mode                                                  
______________________________________                                    
Low       Low       Printer Standby                                       
Low       High      Energize Ribbon Solenoid                              
High      Low       Energize Paper Solenoid                               
High      High      Enable Printing Solenoids                             
______________________________________                                    
 
    
     The portion of I/O circuit 110 which relates to the printer also includes a four-bit shift register 148 which receives data to be printed from either T-register 124 of I/O circuit 110 or C-register 144 of arithmetic and register circuit 32 and presents it in parallel form to comparator 150. Data select logic circuitry 146 transmits data from either the C-register or the T-register to shift register 148. Comparator 150 functions to compare the current sector count received from sector counter 142 with the output of shift register 148 to determine when the print drum is in the proper position to print each particular data item. Printer controller 152 receives printer-related instructions from instruction decoding ROM 118 and, in response thereto, controls the print sequence. 
     I/O circuit 110 further comprises a master clock 154 which supplies the required timing signals within the I/O circuit. Also included is Schmitt trigger 156 which receives FLG&#39; signals from peripheral input/output units employed with the calculator and properly gates these with clock signal φ2 from control and timing circuit 30. 
     DATA STORAGE CIRCUIT 
     The data storage assembly 36 of FIG. 3 is shown in more detail in FIG. 24. It includes an MOS/LSI data storage circuit 158 and a bidirectional amplifier 160. Data storage circuit 158 contains ten data storage registers. In addition to the single data storage circuit employed in the calculator as basically configured, the user may optionally configure the calculator to include additional data storage. Also, data storage circuits are included as integral components within the optional plug-in keyboard function blocks and the optional peripheral input/output interface cards associated with various peripheral I/O units which might be employed with the calculator. 
     The BCD lines associated with the arithmetic and register circuit 32 and the I/O circuit 110 are directly connected to each other and could, in turn, be directly connected to as many as three additional data storage circuits. Bidirectional amplifier 160 is provided to drive the excessive capacitance seen by the BCD line when more than three data storage circuits are employed. Since the BCD line carries binary data in both directions, amplifier 160 must have bidirectional capability. In order to control the direction of data flow through the amplifier, a steering signal (BDE) is required. Normally, this signal will be low (logical 0), in which case the BCD line from arithmetic and register circuit 32 and I/O circuit 110 is the input, while the BCD line connected to the data storage circuits is the output. 
     A DATA STORAGE TO C-REGISTER instruction (DSTC) is decoded by all the data storage circuits present in the current configuration of the calculator. This would include the data storage circuit in the basic calculator as well as those currently employed in a keyboard function block, optional data storage, and peripheral input/output interface cards. Even though only the previously addressed data storage circuit executes the DSTC instruction, all of the data storage circuits present will respond by bringing the BDE line to a logical 1 level during the entire word in which the data transfer occurs. By using this technique only the BDE line from the single data storage circuit in the basic calculator is required to control the direction of amplifier 160 for all of the data storage circuits. 
     The MOS data storage circuit 158 of FIG. 24 is shown in detail in the block diagram of FIGS. 25A-B. Data storage circuit 158 recognizes three separate instructions which are received directly from the read-only memory circuits via the I s  line. These include (1) ADDRESS FROM C-REGISTER TO DATA STORAGE (ATDS), (2) DATA FROM C-REGISTER TO DATA STORAGE (DTDS), and (3) READ FROM DATA STORAGE INTO C-REGISTER (DSTC). These serial instructions are received by a 10-bit shift register 162, converted into a 10-bit parallel signal, and transmitted to instruction decoder 164. 
     The contents of the C-register in arithmetic and register circuit 32 are continuously displayed on the BCD line, except when one of the above instructions is issued. When a data transfer instruction occurs, that instruction will only be executed if there exists at least one data storage register which has previously been enabled. Once enabled, a register will remain enabled until another data transfer instruction is issued which addresses a different register. 
     The designation of each register comprises two separate parts The ten registers within each data storage circuit are numbered 0, 1, 2 . . . 8, 9. The data storage circuits within a particular calculator configuration are themselves numbered 0, 1, 2, 3 . . . 62, 63. Each data storage circuit may be coded in any combination, thereby eliminating the necessity of different data storage circuits for association with different addresses. The circuit address bits, in ascending order of significance, are designated as B1, B2, B3, B4, A1, A2. If bits B1-B4 are considered as a hexadecimal number, then only 10 of the 16 possible combinations are allowable BCD characters. Normal addresses are those utilizing the ten allowable BCD codes for bits B1-B4. The special addresses are the remaining combinations. Normal register addresses are designated by 0≦D 3  D 2  D 1  ≦399, where all three digits are allowable BCD numbers. If D 2  is restricted to the hexadecimal numbers ten through sixteen, then 240 addresses are available. 
     To address a data storage circuit it is necessary to enter the binary (or BCD) code of the appropriate circuit number into the A and B inputs to six-bit comparator 166. For example, to establish the register addresses for a circuit as 130 through 139 would mean that the circuit should be identified as circuit 13. The BCD code for 13 is 01 0011. Therefore, the inputs to comparator 166 would be as shown below. 
     A2 = 0 
     a1 = 1 
     b4 = 0 
     b3 = 0 
     b2 = 1 
     b1 = 1 
     the address decoding logic of the data storage circuits is capable of handling floating point addresses. In order that an address be accepted by a data storage circuit the exponent must be either +0, +1 or +2. The sign of the mantissa is always ignored by a data storage circuit. In addition, the addresses are truncated to the next lowest integer. For example, the numbers -3.79, 3.1854, +3.00, and -3.00 would, as addresses, enable register three. If an exponent equal to zero is given, only the most significant digit of the mantissa will be interrogated to determine a register number in the range 0-9. If an exponent equal to +1 is found, the two most significant digits of the mantissa are interrogated to determine a register number in the range 0-99. When an exponent equal to +2 is encountered in an address, the three most significant digits of the mantissa are interrogated and checked for a number in the range 0-399. 
     I/O circuit also includes four sample and hold flip-flops 168 for storing the desired register (0-9) within a particular data storage circuit. A one-of-10 decoder 170 actually selects the desired register within the circuit. An exponent = 0 line 172, an exponent = 1 line 174, and an exponent = 2 line 176 serve to indicate whether the exponent of a floating point number used as an address was decoded a 0, 1, or 2, respectively. For purposes of illustration only two of the 10 56-bit storage registers comprising each data storage circuit have been shown in FIGS. 25A-B as items 178 and 180. All 10 of the registers are identical in construction. Also included within data storage circuit 158 is a sample and hold flip-flop 182 for remembering whether or not a register previously addressed is located within a given dta storage circuit. 
     Several signals associated with data storage circuit 158 and their relative waveforms with respect to a 56-bit word time are shown in FIG. 26. 
     CLOCK DRIVER 
     A bipolar clock driver 188, one phase of which is shown in FIG. 14, requires less than 25 milliwatts of power and can drive loads up to three hundred picoforads with a voltage swing of +7 to -14 volts. An ENABLE input 190 allows both outputs Q 1  and Q 2  to be held to V CC , the MOS logical 0. This is an effective means of strobing the clock. During DC operation, the transistor pair Q 1  -Q 2  allows only one of the output transistor pairs Q 5  -Q 6  or Q 7  -Q 8  to conduct. Diode D 3  prohibits conduction from transistor Q 6  to transistor Q 8  during transient operation. Thus, the only possible transient short circuit current must flow from transistor Q 5  to transistor Q 7 . However, the limited current handling capability of Q 5  (a lateral PNP) limits this current to less than 5 milliamps peak. The input signals for clock driver 188 are generated on the anode driver of optional output display unit 14, or, if the display unit is not employed in the calculator, then by means of the clock generator circuitry shown in FIG. 40. The outputs of the clock driver are connected to each of the MOS/LSI circuits in the calculator. The timing relationship of the input and output signals of the clock driver circuit are shown in FIG. 15. 
     LED DISPLAY 
     An optional plug-in light emitting diode (LED) output display unit 14 may be employed with the calculator. As shown in the block diagram of FIG. 29, the display unit comprises an anode driver 192, a cathode driver 194, and three 5-digit LED clusters 196. 
     The display unit employs an inductive drive technique which is inherently efficient because of the absence of components representing large power losses. The only dissipation is created by the parasitic resistances and the saturated transistor switches. An inductive driver like that used in the calculator is shown and described in copending U.S. patent application Ser. No. 202,475 entitled LIGHT EMITTING DIODE DRIVER, filed on Nov. 26, 1971, by Donald K. Miller, and issued on Aug. 28, 1973, as U.S. pat. No. 3,755,697. 
     The display circuitry used in the calculator is shown in FIG. 36. It comprises an 8 × 15 array of LEDs in which the eight rows are scanned by the anode driver and the 15 columns by the cathode driver. A simplified circuit diagram for a segment of the display involving one LED is shown in FIG. 37. The equivalent piecewise-linear circuit model is shown in FIG. 38. An analysis of this model shows the inductor current buildup and discharge to be nearly linear for the parameters used in the calculator. The discharge-time to charge-time ratio is approximately: ##EQU1## 
     FIG. 38 shows the inductor current for a basic calculator clock frequency of 175 KHz. The average LED current can be calculated from the formula ##EQU2## 
     The worse case display power (i.e., 13 figure eights and two minus signs) is about 110 milliwatts. FIG. 38 also shows the ringing inherent in the inductor drive technique. 
     The display information is partially decoded in arithmetic and register circuit 32 and completely decoded into eight signals, representing seven character segment plus a decimal point, within bipolar anode driver 192 of output display unit 14. 
     As discussed above, anode driver 192 includes the basic clock generator for the calculator. In the event the optional display unit is not employed, the clock signals are derived from separate clock generator circuitry located elsewhere in the basic calculator. This separate clock generator circuitry is shown in detail in FIG. 40. The low power TTL inverters 198 and the associated passive elements form an oscillator whose frequency is, under worst case conditions, always less than or equal to 720 kilohertz. The oscillator output is a square wave. Duel J-K master-slave flip-flop 200 operates on the output of the oscillator to provide output signals comprising 360 kilohertz and 180 kilohertz square waves. The resulting clock phase signals φ1T and φ2T appearing at the outputs of gates 202 are identical to the signals generated by the clock generator portion of anode driver 192. 
     A logic diagram of the anode driver 192 is shown in FIG. 30. The clock generator portion thereof uses an external LC circuit to set the oscillator frequency at a nominal 800 kilohertz rate. Flip-flops B1 and B2 are clocked off alternate phases of flip-flop B1 to provide two 200 kilohertz square waves as shown in FIG. 31. Flip-flop B3 is clocked from flip-flop B2 and in turn clocks flip-flop B4 to provide further division of the basic clock frequency of approximately 200 kilohertz. The two-phase clock signals φ1T and φ2T are generated from flip-flops BL and B1 and the 800 kilohertz oscillator 200. These signals are on for 625 nanoseconds and are separated by 625 nanoseconds, as shown in FIG. 31. A periodic counter-clock signal (CCL) is also derived from the anode driver 192 and is sent to cathode driver 194 once each digit time. The trailing edge of this signal causes the display to step to the next digit. 
     The display consists of fifteen characters while the basic calculator word cycle consists of 14 digits. The extra character is the decimal point. As explained above, a BCD two is placed in register B at the digit position of the decimal point. The display decoder 92 in arithmetic and register circuit 32 indicates this by a signal on outputs B and E during bit time T 4  (see FIG. 11). When this condition is decoded by the anode driver, the decimal point is excited and an extra counter clock signal is given to step the display to the next position (see FIGS. 31, 32, and 33). Therefore, all remaining digits in register A are displaced one digit in the display. 
     FIGS. 32 and 33 show the simplified circuit and the timing relationship for the decimal point. The timing is critical since all the inductor current in segment b (the last to be excited) must be decayed before the counter clock signal is given to step to the next digit, or the remaining current would be discharged through the wrong digit and a faint lighting of segment b on the same digit with the decimal point would occur. The decimal point insertion technique is the reason all other seven segments are excited during the first half of the digit time. The decimal point charging time is one-half that of the other segments. The decimal point segment receives the same current in one-half the time and is one-half as bright as the other segments. 
     As described above, an inductive circuit method of driving the light emitting diodes is employed. Basically, the method involves using the time required for current to build up in an inductor to limit current, rather than using a resistor as is normally the case with LED displays. This saves power since the only lossy components in the drive system are the parasitic inductor and transistor resistances. The drive circuit for one digit is shown in FIG. 34. Assuming the cathode transistor switch T c  is closed, an anode switch T a  is closed for 2.5 microseconds, allowing the current to build up to a value I p  along a nearly triangular waveform (the early part of an exponential buildup). When anode switch T a  is opened, the current is dumped through the LED, decaying in about 5 microseconds. The anodes are strobed according to the sequence in FIG. 31. The primary reason for sequentially exciting the anodes is to reduce the peak cathode transistor current. Since the decay time is approximately twice the buildup time, it works out that the peak cathode current is about 2.5 times the peak current in any segment. The LEDs are more efficient when excited at a low duty cycle. This means high currents for short periods (80 ma. anode current, 250 ma. cathode current). FIG. 31 also shows the relationship between the anode strobing sequence and the display output signals (A-E) from arithmetic and register circuit 32. 
     The cathode driver 194 of output display unit 14 comprises a 15-position shift register for scanning the 15-digit display once each word time. This scanning operation moves from digit to digit in response to counter clock signals from the anode driver. Once each word time a START signal arrives from arithmetic and register circuit 32 to restart the procedure. A block diagram of cathode driver 194 is shown in FIG. 35. 
     OUTPUT PRINTER 
     As discussed above, primary control for output printer unit 16 is provided within MOS/LSI input/output circuit 110. However, some additional circuitry outside the I/O circuit is provided to perform timing and driving functions relative to the output printer. 
     FIG. 27 is a detailed schematic diagram of the printer timing circuitry. I/O circuit 110 requires a pulse train (TP) from the printer which denotes the sector divisions as the print drum rotates. Between sectors twelve and zero of the print drum, a RESET signal is given by the printer to the printer timing circuitry, which responds by issuing a signal (TR) to the I/O circuit for resetting sector counter 142. 
     Since both RESET and TP are derived from a magnetic pick up within the printer, they have very slow rise and fall times. In addition, they are very low level signals. The printer timing circuitry of FIG. 27 operates on these signals to present them in better form to the I/O circuit. Operational amplifiers 206 serve as level detectors. In order to mask the problem of spurious pulses resulting from the fact that signal TP has very little magnitude, a retriggerable monostable multivibrator 208 is provided to receive the output signal of operational amplifier 206. Since both signals TP and TR must be received by I/O circuit 110 in synchronization with phase 2 of the clock signal, a dual D-type flip-flop 210 is provided. 
     The printer drive circuitry of FIG. 28 simply accepts the low level TTL signals of the I/O circuit 110 for interfacing to the various solenoids of printer 16, which require higher power levels for operation. 
     POWER SUPPLY 
     The calculator power supply system, shown in detail in FIG. 41, is constructed according to conventional practices and delivers +6 volts, +15 volts, +5 volts, +7.5 volts, and -12 volts to the various calculator circuits. 
     PLUG-IN KEYBOARD FUNCTION BLOCK 
     FIG. 45 shows a detailed schematic diagram of the circuitry comprising each plug-in keyboard function block. Each such block contains two MOS/LSI data storage circuits 158 which are constructed and accessed by the calculator microprograms as described above. Also included are eight MOS/LSI read-only memory circuits which form a ROM group 212. Again, these circuits are identical to those of the basic calculator except for their bit patterns, which are set forth in the instruction listing at a later point in this specification. The function block circuitry also includes a bipolar clock driver 188 which is identical to that described above. 
     PLUG-IN ROM/PROM OPTION 
     As described above, the user may employ with the calculator a plug-in ROM or PROM containing library programs written in user level language. These programs may be executed by the user from the keyboard. A detailed schematic diagram of each plug-in ROM/PROM is given in FIG. 46. Included are four conventional 256-bit read-only memories or programmable read-only memories 214, in which are stored the instructions comprising the library program. The advantage of using a programmable read-only memory (PROM) lies in the fact that the program instructions may be modified. A decoder 216 selects which of the ROMs or PROMs 214 is to be addressed, based on the two most significant bits of the total address. Transistor switch 218, in response to a READ instruction, pulls the LATCH input of I/O circuit 110 low, thereby allowing data from the ROMs or PROMs 214 to be loaded into the I/O circuit. Logic circuitry 222 issues a flag to I/O circuit 110 whenever a given address exceeds the memory capacity of the ROM/PROM option currently employed. Transistor switch 224 provides an output, delayed in time from that of transistor 218, for enabling decoder 216. Regulator circuitry 226 provides additional regulation of two of the power supply voltages as they are applied to the ROM/PROM circuitry. Logic gate 228 is employed by some plug-in keyboard function blocks to determine if the program stored in ROM or PROM 214 is proprietary, in which case program listing is prohibited. 
     DATA STORAGE OPTION 
     The optional plug-in data storage, described above, is shown in detailed schematic form in FIg. 47. Each increment of plug-in data storage comprises 30 registers, which are provided by three MOS/LSI data storage circuits 158. These circuits are identical in construction and function to that described in detail earlier in this specification. Three MOS/LSI read-only memory circuits, like those described in detail earlier in this specification, comprise a ROM group 230. The bit patterns for these individual ROM circuits are contained in the instruction listing below. The data storage option also includes a clock driver 232 as described above. 
     INSTRUCTION SET 1 
     Every function performed by the calculator is implemented by a sequence of one or more ten-bit instructions stored in the ROMs φ-7 of read-only memory group 34 or one of the ROM groups in a keyboard function block 20, an optional data storage unit, or one of the optional input/output interface cards. The serial nature of the MOS calculator circuits allows the instruction bits to be decoded from least significant bit to most significant bit (right to left) serially. If the first bit is a one, the instruction is either a subroutine jump or a conditional branch as selected by the second bit, with eight bits remaining for an address. The next largest set of instructions, the arithmetic set, starts with a zero followed by a one (right to left), leaving eight bits for encoded instructions. 
     With three exceptions, instruction set 1 includes those instructions executed by the arithmetic and register circuit, the control and timing circuit, and the read-only memory circuits. These three exceptions are represented by three instructions within instruction set 1 which are executed by the data storage circuit. The mnemonics and associated bit patterns for these three instructions are as follows: 
     
         MNEMONIC         BIT PATTERN                                              
______________________________________                                    
DSTC             1 0 1 1 1 1 1 0 0 0                                      
ATDS             1 0 0 1 1 1 0 0 0 0                                      
DTDS             1 0 1 1 1 1 0 0 0 0                                      
______________________________________                                    
 
    
     These instructions are discussed in detail in the portion of this specification above which deals with the MOS/LSI data storage circuit. 
     The 10 different types of instructions comprising instruction set 1 are shown in the following table. 
     
         __________________________________________________________________________
TABLE OF INSTRUCTION TYPES (X = DON&#39;T CARE)                               
    AVAILABLE                                                             
TYPE                                                                      
    INSTRUCTIONS                                                          
              NAME           FIELDS                                       
__________________________________________________________________________
                               8                                          
1   256 (ADDRESSES)                                                       
              JUMP SUBROUTINE                                             
                             SUBROUTINE ADDRESS                           
                                          0 1                             
    256 (ADDRESSES)                                                       
              CONDITIONAL BRANCH                                          
                             BRANCH ADDRESS                               
                                          1 1                             
                               5      3                                   
2   32 × 8                                                          
              ARITHMETIC/REGISTER                                         
                             OPERATION                                    
                                     WORD 1 0                             
    = 256                      CODE  SELECT                               
                              4   2                                       
3   64        STATUS OPERATIONS                                           
                             N    F  0  1 0 0                             
    (37 used)                    I.sub.5 I.sub.4                          
                                     I.sub.3                              
                                        I.sub.2  I.sub.1  I.sub.0         
              SET BIT N         F = 00                                    
              INTERROGATE N     F = 01                                    
              RESET N           F = 10}                                   
              CLEAR ALL         F = 11}  (N = 0000)                       
                              4  2                                        
4   64        POINTER OPERATIONS                                          
                             P   F   1  1 0 0                             
    (30 used) SET POINTER TO P  F = 00                                    
              INTERROGATE P     F = 10                                    
              DECREMENT P       F = 01}                                   
              INCREMENT P       F = 11}  P = XXXX                         
                              4  2                                        
5   64        DATA ENTRY/DISPLAY                                          
                             N   F   1 0 0 0                              
    (20 used)                                                             
              LOAD CONSTANT     F = 01                                    
              I.sub.s → A                                          
                                F = 1X (N = XX01)                         
              BCD INPUT TO C-REGISTER                                     
                                F = 1X (N = XX11)                         
              STACK INSTRUCTIONS                                          
                                F = 10  N = (---0)                        
              AVAILABLE         F = 00                                    
                              3  2                                        
6   32        ROM SELECT, MISC.                                           
                             N   F   1 0 0 0 0                            
    (11 used) SELECT ROM N      F = 00                                    
              KEYBOARD ENTRY    F = 10 (N = XX1)                          
              EXTERNAL ENTRY        (N =  XX0)                            
              SUBROUTINE RETURN F = 01 (N = XXX)                          
                              4                                           
7   16        (RESERVED FOR  X X X X  1 0 0 0 0 0                         
              PROGRAM STORAGE                                             
                             3                                            
8    8        MOS CIRCUIT)   X X X   1 0 0 0 0 0 0                        
9    7        AVAILABLE      X X X   0 0 0 0 0 0 0                        
10   1        NO OPERATION (NOP)                                          
                             0 0 0   0 0 0 0 0 0 0                        
__________________________________________________________________________
 
    
     There are two type 1 instructions, JUMP SUBROUTINE and CONDITIONAL BRANCH. They are decoded only by control and timing circuit 30. No word select is generated and all registers in arithmetic and register circuit 32 merely recirculate. The object of the JUMP SUBROUTINE instruction is to move to a new address in ROM and to save the existing address, incremented by one, as a return address. The last instruction in a subroutine must be a RETURN to continue the program where it was left previously. 
     As discussed above, control and timing circuit 30 contains a 28-bit shift register 68-72 which holds the current 8-bit ROM address and also has eight bits of storage for one return address (see FIG. 6). During bit times b 47  -b 54  the current ROM address flows through the adder 74 and is incremented by one. Normally this address is updated each word time. However, if the first two bits of the instruction, which arrive at bit times b 45  -b 46 , are 10, the incremented current address is routed to the return address portion 70 of the 28-bit shift register, and the remaining eight bits of the instruction, which are the subroutine address, are inserted into the address portion 68. These data paths with the JSB control line are shown in FIG. 6. In this way the return address has been saved and the jump address is ready to be transmitted to the ROM at bit times b 19  -b 26  of the next word time. 
     The most frequently used instruction is the CONDITIONAL BRANCH, which, based upon data or system status, implements the decision-making capability of the calculator. In the calculator system described here this instruction also functions as an unconditional branch. 
     The format of the CONDITIONAL BRANCH instruction, as shown in the instruction table above, is two ones followed by an 8-bit branch address. The instruction is received at bit times b 45  -b 54 . The last eight bits of the instruction are stored in the address buffer register 78 (See FIG. 6). During the next word time the carry flip-flop 76 is checked at bit time b 19 . If the carry flip-flop was set during the previous word time, the current ROM address is transmitted to the ROMs φ-7. If the carry flip-flop was not set, the branch address is read from the address buffer register 78 onto the I a  line and loaded into the ROM address register 100 (see FIG. 17). Thus, the instruction causes a branch if there is no carry. There are three ways the carry flip-flop 76 can be set: (1) by a carry generated in the arithmetic and register circuit 32; (2) by a successful interrogation of the pointer position; and (3) by a successful interrogation of one of the 12 status bits. An example is given in the table below. 
     
         __________________________________________________________________________
EXAMPLE OF CONDITIONAL BRANCH EXECUTION                                   
    ADDRESS                                                               
          INSTRUCTION                                                     
WORD                                                                      
    RECEIVED                                                              
            SENT    INSTRUCTION                                           
                              RESULT                                      
    AT ROM                                                                
           BY ROM   EXECUTED                                              
__________________________________________________________________________
N-1 P     INCREMENT SIGN                                                  
                      --        --                                        
          DIGIT                                                           
N   P+1   CONDITIONAL                                                     
                    INCREMENT SIGN                                        
                              CARRY GENERATED                             
          BRANCH TO DIGIT     IF A-REGISTER                               
          ADDRESS Q           NEGATIVE                                    
N+1 P+2   CONTENTS OF                                                     
                    CONDITIONAL                                           
                              SEND P+2                                    
          P+2       BRANCH                                                
    or      or                 or                                         
    Q     CONTENTS OF Q       SEND Q                                      
__________________________________________________________________________
 
    
     A typical test condition is to determine the sign of a number. Suppose at address P in the program a branch to location Q is desired if the sign of A is positive, while program execution is to continue if the sign is negative. In the example give in the table above, the instruction INCREMENT THE A-REGISTER, WORD SELECT OF SIGN DIGIT ONLY is given at location P. During word time N-1 the instruction is received by arithmetic and register circuit 32 and is executed at word time N (the same word time when the CONDITIONAL BRANCH instruction is received by control and timing circuit 30). If the sign of A is negative, there will be a nine in the sign digit. Incrementing this position will generate a carry and set the carry flip-flop 76 in control and timing circuit 30. Since the instruction causes a branch if no carry is generated, the program execution will jump to location Q only if the sign is positive (i.e., was a zero), otherwise execution continues at P+2. 
     Note that during word time N+1 the calculator did nothing more than select which of two addresses to send next (all registers merely recirculate). Performing a branch actually takes two word cycles to execute; one to ask a question and set the carry flip-flop 76 if the answer is YES, and the other to test if the carry flip-flop was set and transmit the proper address. In many cases, asking the question is an arithmetic operation (i.e., A+B→A) which must be performed anyway. In this case, the branch requires only one extra instruction. 
     Contrary to most instruction sets, this set has no unconditional branch instruction. However, since an ordinary JUMP is one of the most frequently used instructions, the CONDITIONAL BRANCH is also used to effect an unconditional branch or jump by insuring that the carry flip-flop 76 is reset when an unconditional branch is desired. This is the reason the sense of the CONDITIONAL BRANCH is branch on no carry. The carry flip-flop 76 is reset during execution of every instruction except ARITHMETIC (type 2) and INTERROGATION OF POINTER or STATUS (types 3 and 4). Since only ARITHMETIC and INTERROGATION instructions can set the carry flip-flop 76, the constraint is not severe. The JUMP SUBROUTINE instruction can also be used as an unconditional branch if the previous return address does not need to be saved. In summary, CONDITIONAL BRANCH can be used as an unconditional branch provided the state of the carry flip-flop 76 is known to be reset (i.e., provided the conditional branch does not follow an arithmetic or an interrogation of pointer or status instruction). 
     ARITHMETIC &amp; REGISTER (type 2) instructions apply to the arithmetic and register circuit 32 only. There are thirty-two ARITHMETIC &amp; REGISTER instructions divided into eight classes encoded by the left most five bits of the instruction. Each of these instructions can be combined with any of eight word select signals to give a total capability of two hundred fifty-six instructions. The 32 ARITHMETIC &amp; REGISTER instructions are listed in the table below. 
     
         ______________________________________                                    
TABLE OF TYPE TWO INSTRUCTIONS                                            
(in order of binary code)                                                 
CODE     INST        CODE       INST                                      
______________________________________                                    
0 0000   0-B         1 0000     A-B                                       
0 0001   0→B  1 0001     B⃡C                           
0 0010   A-C         1 0010     SHIFT C RIGHT                             
0 0011   C-1         1 0011     A-1                                       
0 0100   B→C  1 0100     SHIFT B RIGHT                             
0 0101   0-C→C                                                     
                     1 0101     C+C→C                              
0 0110   0→C  1 0110     SHIFT A RIGHT                             
0 0111   0-C-1→C                                                   
                     1 0111     0→A                                
0 1000   SHIFT A LEFT                                                     
                     1 1000     A-B→A                              
0 1001   A→B  1 1001     A⃡B                           
0 1010   A-C→C                                                     
                     1 1010     A-C→A                              
0 1011   C-1→C                                                     
                     1 1011     A-1→A                              
0 1100   C→A  1 1100     A+B→A                              
0 1101   0-C         1 1101     A⃡C                           
0 1110   A+C→C                                                     
                     1 1110     A+C→A                              
0 1111   C+1→C                                                     
                     1 1111     A+ 1→A                             
______________________________________                                    
 KEY: A,B,C are registers, →means goes into, ⃡means    
 interchange                                                              
 
    
     The eight classes of ARITHMETIC &amp; REGISTER instructions together with a parenthetical indication of the number of instructions within each class are as follows: 
     (1) CLEAR(3) 
     (2) transfer/exchange(6) 
     (3) add/subtract(7) 
     (4) compare(6) 
     (5) complement(2) 
     (6) increment(2) 
     (7) decrement (2) 
     (8) shift(4) 
     there are three CLEAR instructions. These instructions are 0→A, 0→B, and 0→C. They are implemented by simply disabling all the gates entering the designated register. Since these instructions can be combined with any of the eight word select options, it is possible to clear a portion of a register or a single digit. 
     There are six TRANSFER/EXCHANGE instructions. These instructions are A→B, B→C, C→A, A←→B, B←→C, and C←→A. This variety permits data in registers A, B, and C to be manipulated in many ways. Again, the power of the instruction must be viewed in conjunction with the word select option. Single digits may be exchanged or transferred. 
     There are seven ADD/SUBTRACT instructions which use the adder circuitry 82. They are A±C→C, A±B→A, A±C→A, and C+C→C. The last instruction can be used to divide by five. This is accomplished by first adding the number to itself via C+C→C, then multiplying by two, then shifting right one digit, and dividing by 10. The result is a divide by five. The algorithm is used in the square root routine. 
     There are six COMPARE instructions. These instructions are always followed by a CONDITIONAL BRANCH. They are used to check the value of a register or a single digit in a register without modifying or transferring the contents thereof. These instructions (type 2) may easily be found in the instruction table above since there is no transfer arrow present. They are: 
     (1) O-B (Compare B to zero) 
     (2) A-C (Compare A and C) 
     (3) c-1 (compare C to one) 
     (4) O-C (Compare C to zero) 
     (5a-b A-B (Compare A and B) 
     (6) a-1 (compare A to one) 
     If, for example, it is desired to branch if B is zero (or any digit or group of digits is zero as determined by WS) the O--B instruction is followed by a CONDITIONAL BRANCH. If B was zero, no carry (or borrow) would be generated and the branch would occur. Again, it is easy to compare single digits or a portion of a register by appropriate word select options. 
     There are two COMPLEMENT instructions. The number representation system in the calculator is sign and magnitude notation for the mantissa, and tens complement notation in the exponent field. Before numbers can be subtracted, the subtrahend must be tens-complemented (i.e., O-C→C). Other algorithms require the nines complement (i.e., O-C-1→C). 
     There are four INCREMENT/DECREMENT instructions. They are A±1→A and C±1→C. 
     There are four SHIFT instructions. All three registers A, B, and C may be shifted right, while only A may be shifted left. The ARITHMETIC &amp; REGISTER instruction set is summarized by class in the table below. 
     
         ______________________________________                                    
TABLE OF TYPE TWO INSTRUCTIONS                                            
(divided by class)                                                        
CLASS            INSTRUCTION    CODE                                      
______________________________________                                    
1) CLEAR         0→A     10111                                     
                 0→B     00001                                     
                 0→C     00110                                     
2) TRANSFER/     A→B     01001                                     
EXCHANGE         B→C     00100                                     
                 C→A     01100                                     
                 A⃡B                                          
                                11001                                     
                 B⃡C                                          
                                10001                                     
                 C⃡A                                          
                                11101                                     
3) ADD/SUBTRACT  A+C→C   01110                                     
                 A-C→C   01010                                     
                 A+B→A   11100                                     
                 A-B→A   11000                                     
                 A+C→A   11110                                     
                 A-C→A   11010                                     
                 C+C→A   10101                                     
4) COMPARE       0-B            00000                                     
                 0-C            01101                                     
                 A-C            00010                                     
                 A-B            10000                                     
                 A-1            10011                                     
                 C-1            00011                                     
5) COMPLEMENT    0-C→C   00101                                     
                 0-C-1→C 00111                                     
6) INCREMENT     A+1→A   11111                                     
                 C+1→C   01111                                     
7) DECREMENT     A-1→A   11011                                     
                 C-1→C   01011                                     
8) SHIFT         Sh A Right     10110                                     
                 Sh B Right     10100                                     
                 Sh C Right     10010                                     
                 Sh A Left      01000                                     
______________________________________                                    
 
    
     The 28-bit shift register 68-72 in control and timing circuit 30 contains 12 status bits or flags used to remember conditions of an algorithm or some past event (e.g., that the decimal point key has already been depressed). These flags may be individually set, reset, or interrogated or all bits may be cleared (reset simultaneously). The format for the STATUS OPERATION instructions (type 3) given in the instruction type table above is repeated below. 
     
         ______________________________________                                    
TABLE OF STATUS INSTRUCTION DECODING                                      
BIT NO.  I.sub.9  I.sub.8  I.sub.7  I.sub.6                               
                     I.sub.5  I.sub.4                                     
                              I.sub.3                                     
                                   I.sub.2  I.sub.1  I.sub.0              
______________________________________                                    
FIELD    N           F        0    1 0 0                                  
______________________________________                                    
        F     INSTRUCTION                                                 
        0 0   SET FLAG N                                                  
        0 1   INTERROGATE FLAG N                                          
        1 0   RESET FLAG N                                                
        1 1   CLEAR ALL FLAGS (N=0000)                                    
______________________________________                                    
 
    
     If status bit N is one when the INTERROGATE N instruction is executed, the CARRY flip-flop 76 in control and timing circuit 30 will be set. The status bit will remain set. INTERROGATE is always followed by a CONDITIONAL BRANCH instruction. The effective form of the INTERROGATE instruction is IF STATUS BIT N=0, THEN BRANCH or IF STATUS BIT N≠1, THEN BRANCH. The reason for this negative orientation is that all branches occur if the test is false (i.e., carry flip-flop=0), a result derived from combining conditional and unconditional branches under one instruction. 
     Status bit 0 is set when a key is depressed. If cleared it will be set every word time as long as the key is down. 
     A four-bit counter 54 in control and timing circuit 30 functions as a pointer or marker to allow arithmetic instructions to operate on a portion of a register. Instructions are available to set and interrogate the pointer at one of fourteen locations or to increment or decrement the present position. The pointer instruction decoding is given in the table below. 
     
         ______________________________________                                    
TABLE OF POINTER INSTRUCTION DECODING                                     
BIT NO.   9 8 7 6     5 4       3     2 1 0                               
______________________________________                                    
FIELD     P           F         1     1 0 0                               
______________________________________                                    
F       INSTRUCTION                                                       
00      SET POINTER TO P                                                  
10      INTERROGATE IF POINTER AT P                                       
01      DECREMENT POINTER}  P = XXXX                                      
11      INCREMENT POINTER     i.e., don&#39;t care                            
 
    
     As with the STATUS INTERROGATE instruction, the carry flip-flop 76 is set if the pointer is at P when the INTERROGATE IF POINTER AT P instruction is executed. Like the status interrogation, the actual question is in the negative form IF P≠N, THEN BRANCH. This instruction would be followed by a CONDITIONAL BRANCH. In a math routine the pointer allows progressive operation on a larger and larger portion of a word. After each iteration through a loop, the pointer is decremented (or incremented) and then tested for completion to force another iteration or a jump out of the loop. 
     The DATA ENTRY &amp; DISPLAY instructions (type 5) are used to enter data into arithmetic and register circuit 32, manipulate the stack and memory registers, and blank the display. Sixteen instructions in this set are not recognized by any of the existing circuits and are, therefore, available for other external circuits that might be employed with other embodiments of the calculator. The table below contains a detailed listing of the DATA ENTRY &amp; DISPLAY instructions. 
     
         __________________________________________________________________________
TABLE OF TYPE 5 INSTRUCTIONS                                              
(X =      don&#39;t care, which in this context                               
          means the instruction does not                                  
          depend on this bit; either a 1 or                               
          a 0 here will cause the same                                    
          execution.)                                                     
          I.sub.9 I.sub.8 I.sub.7 I.sub.6 I.sub.5 I.sub.4    1 0 0 0      
I.sub.9 I.sub.8 I.sub.7 I.sub.6                                           
        I.sub.5                                                           
          I.sub.4                                                         
            INSTRUCTION                                                   
0000 → 1111                                                        
        0 0 16 Available Instructions                                     
0000 → 1001                                                        
        0 1 Enters 4-bit code N into                                      
            C Register at pointer position                                
              (LOAD CONSTANT)                                             
__________________________________________________________________________
0 0 0 0 1 X DISPLAY TOGGLE                                                
0 0 1 0 1 X EXCHANGE MEMORY, C→M→C                          
0 1 0 0 1 X UP STACK, C→C→D→E→F               
0 1 1 0 1 X DOWN STACK, F→F→E→D→A             
1 0 0 0 1 X DISPLAY OFF                                                   
1 0 1 0 1 X RECALL MEMORY, M→M→C                            
1 1 0 0 1 X ROTATE DOWN, C→F→E→D→C            
1 1 1 0 1 X CLEAR ALL REGISTERS 0→A,B,C,D,E,F,M                    
X X 0 1 1 X I.sub.S → A register (56 bits)                         
X X 1 1 1 X BCD → C register (56 bits)                             
__________________________________________________________________________
 
    
     The first set of 16 possible instructions (I 5  I 4  = 00) in the table above is not used by the calculator. 
     The next instruction (I 5  I 4  = 01) in this table is called the LOAD CONSTANT (LDC) or DIGIT ENTRY instruction. When this instruction is executed, four bits in I 9  -I 6  will be inserted into the C-register at the location of the pointer, and the pointer will be decremented. This allows a constant, such as π (pi), to be stored in read-only memory and then transferred to arithmetic and register circuit 32. To transfer a 10-digit constant requires only 11 instructions (one to preset the pointer). Several exceptions exist in the use of this instruction. When used with the pointer in position 13, it cannot be followed by an ARITHMETIC &amp; REGISTER instruction (i.e., type 2 or 5 instructions). With P = 12, LOAD CONSTANT can be followed by another LOAD CONSTANT but not by any other type 2 or 5 instructions. When used with the pointer in position 14, the LOAD CONSTANT instruction has no effect. However, when P = 12 and LOAD CONSTANT is followed by a type 2 or 5 instruction, position 13 in the C-register is modified. Loading non-digit codes (1010-1111) is not allowed since they will be modified when passing through the adder. 
     The next set of instructions (I 6  I 5  I 4  = 01X) in the type 5 instruction table above includes two DISPLAY instructions and six STACK or MEMORY instructions. The display flip-flop in arithmetic and register circuit 32 controls blanking of all the LEDs. When it is reset, the 1111 code is set into the display buffer 94, which is decoded so that no segments are on. There is one instruction to reset this flip-flop (I 9  I 8  I 7  = 100) and another to toggle it (000). The toggle feature is convenient for blinking the display. 
     The remaining type 5 instructions include two affecting memory (EXCHANGE C←→M and RECALL M→C), three affecting the stack (UP, DOWN, and ROTATE DOWN), one general CLEAR, one for loading register A from the line I S  (I 7  I 6  I 5  = 011), and one for loading the C-register from the BCD line (111). Neither of the last two instructions depends on bits I 9 , I 8 , or I 4 . The I S  →A instruction is designed to allow a key code to be transmitted from a program storage circuit to arithmetic and register circuit 32 for display. The entire 56 bits are loaded, although only two digits of information are of interest. The BCD →C instruction allows data input to arithmetic and register circuit 32 from a data storage circuit or the I/O circuit. 
     The ROM SELECT and other type six instructions are denoted by the pattern 10000 in instruction bits I 4  -I 0 . The decoding table for these instructions is shown below. 
     
         __________________________________________________________________________
TABLE OF TYPE 6 INSTRUCTIONS                                              
CIRCUIT                                                                   
AFFECTED                                                                  
       I.sub.9 I.sub.8 I.sub.7 I.sub.6 I.sub.5 I.sub.4 I.sub.3 I.sub.2    
       I.sub.1 I.sub.0                                                    
                   INSTRUCTION                                            
__________________________________________________________________________
       0 0 0 0 0 1 0 0 0 0                                                
                   ROM SELECT. ONE OF EIGHT AS                            
ROM     ↓ 0 0 1 0 0 0 0                                            
                   SPECIFIED IN BITS I.sub.9 - I                          
       1 1 1 0 0 1 0 0 0 0                                                
       X X X 0 1 1 0 0 0 0                                                
                   SUBROUTINE RETURN                                      
CONTROL                                                                   
&amp;      X X 0 1 0 1 0 0 0 0                                                
                   EXTERNAL KEY CODE ENTRY TO                             
TIMING             CONTROL &amp; TIMING CIRCUIT                               
       X X 1 1 0 1 0 0 0 0                                                
                   KEYBOARD ENTRY                                         
       1 X 0 1 1 1 0 0 0 0                                                
                   SEND ADDRESS FROM C-REGISTER                           
DATA               INTO DATA STORAGE CIRCUIT                              
STORAGE                                                                   
       1 0 1 1 1 1 0 0 0 0                                                
                   SEND DATA FROM C-REGISTER                              
                   INTO DATA STORAGE CIRCUIT                              
__________________________________________________________________________
 
    
     The ROM SELECT instruction allows transfer of control from one ROM to another. Each ROM has a masking option which is programmed to decode bits I 9  -I 7 . A SELECT ROM 3 instruction read from ROM 1 will reset the ROE flip-flop 96 in ROM 1 and set the ROE flip-flop 96 in ROM 3. The address is incremented in control and timing circuit 30 as usual. Thus, if SELECT ROM 3 is in location 197 in ROM 1, the first instruction read from ROM 3 will be location 198. 
     Bits I 6  I 5  = 01 designate a SUBROUTINE RETURN (RET) instruction. There are eight bits of storage in the 28-bit shift register 68-72 of control and timing circuit 30 for retaining the return address when a JUMP SUBROUTINE instruction is executed. This address has already been incremented so execution of RET is simply a matter of outputting the address on the I a  line at bit times b 19  -b 26  and also inserting it into the ROM address portion 68 of the shift register. It is also still retained in the return address portion 70. 
     A key code is entered into control and timing circuit 30 by depressing a key on the keyboard. A key depression is detected by a positive interrogation of status bit 0. During a computation the keyboard is locked out because this status bit would ordinarily not be interrogated until a return to the display loop. The actual key depression saves the state of the system counter, which is also the key code, in the key code buffer 66 (see FIG. 6) and also sets status bit 0. Execution of the KEYBOARD ENTRY instruction routes the key code (six bits) in the key code buffer 66 onto the I a  line and into ROM address register 68 at bit times b 19  -b 26 . The most significant two bits b 25  and b 26  are set to zero so that a KEYBOARD ENTRY instruction always jumps to one of the first 64 states. 
     Two algorithms will now be discussed to further illustrate the instruction set. The first of these algorithms is a display wait loop which is employed after a key has been processed and while waiting for another key to be actuated. The second of these algorithms is a floating point multiply operation. 
     A flow diagram of the display wait loop is shown in FIG. 43. This loop is entered after a keystroke has been processed, register A has been properly loaded with the number to be displayed, and register B contains the display mask as discussed above. Two flags or status bits are required. Status bit 0 (S0) is hardwired in control and timing circuit 30 to be automatically set whenever a key is down. Status bit 8 (S8) is used in this program to denote the fact that the key which is presently down has already been processed since a routine may be finished before the key is released. In states DIS1 and DIS2, these two status bits are initialized. Then a loop is used as a time delay to wait out any key bounce. In DIS4, status bit 8 (S8) is checked. The first time through the algorithm it must be 1 since it was set in DIS1 to indicate that the key has been processed. In state DIS5 the display is turned on. Actually, the display is toggled since it must previously have been off. There is no separate instruction for turning on the display. At this time the answer appears to the user. In DIS6, status bit 0 (S0) is checked to see if a key is down. If not (i.e., S0=0), the previous key has been released and status bit 8 (S8) is reset to 0 (DIS7). The machine is now ready to accept a new key since the previous key has been processed and released. The algorithm cycles through DIS6 and DIS7 waiting for a new key. This is the basic wait cycle of the calculator. If S0 = 1 in DIS6, the key which is down may be the old key (i.e., the one just processed) or a new key. This can be determined upon return to DIS4 where status bit 8 (S8) is checked. If a new key is down (S8=0), execution jumps to DIS8, the display is blanked, and a jump out is made to service the key. A listing of the algorithm is given in the table below. 
     
         __________________________________________________________________________
TABLE OF WAIT LOOP ALGORITHM                                              
LABEL                                                                     
     OPERATION     COMMENT                                                
__________________________________________________________________________
DIS1:                                                                     
     1 → S8 SET STATUS 8                                           
DIS2:                                                                     
     0 → S0 RESET STATUS 0                                         
DIS3:                                                                     
     P-1 → P                                                       
                   DECREMENT POINTER,                                     
     IF P # 12     48 WORD LOOP (3 × 16)                            
     THEN GO TO DIS3                                                      
                    TO WAIT OUT KEY BOUNCE                                
     DISPLAY OFF                                                          
DIS4:                                                                     
     IF S8 # 1     IF KEY NOT PROCESSED,                                  
     THEN GO TO DIS8:                                                     
                    LEAVE ROUTINE                                         
DIS5:                                                                     
     DISPLAY TOGGLE                                                       
                   TURN ON DISPLAY                                        
DIS6:                                                                     
     IF S0 # 1     IF KEY UP, RESET                                       
     THEN GO TO DIS7:                                                     
                   S8 AND WAIT                                            
     GO TO DIS2:   KEY DOWN. CHECK IF                                     
                    SAME KEY                                              
DIS7:                                                                     
     0 → S8 INDICATE KEY NOT                                       
                    PROCESSED                                             
     GO TO DIS6:   BACK TO WAIT FOR KEY                                   
DIS8:              BLANK DISPLAY                                          
DIS9:                                                                     
     KEYS → ROM ADDRESS                                            
                   JUMP TO START OF PROGRAM                               
     ↓       TO PROCESS KEY THAT WAS                               
                    DOWN                                                  
     CONTINUE                                                             
__________________________________________________________________________
 
    
     The floating point multiply algorithm multiplies x times y, where register C contains x in scientific notation and register D contains y. When the multiply key is depressed the wait loop algorithm will jump to a ROM address corresponding to the first step of the multiply algorithm because of the way the instruction KEYS → ROM ADDRESS (state DIS9 in FIG. 43) is executed. The key code actually becomes the next ROM address. At this time the contents of registers A-D are indicated by the following: 
     Register A contains the floating point form of x 
     Register B contains the display mask for x 
     Register C contains the scientific form of x 
     Register D contains the scientific form of y 
     The algorithm for executing floating multiply is given in the table below. The letters in parentheses indicate word select options as follows:P = POINTER POSITION                  M = MANTISSA FIELD WITHOUT SIGNWP =    UP TO POINTER POSITION                  MS =                      MANTISSA WITH SIGNX = EXPONENT FIELD                  W = ENTIRE WORDXS =    EXPONENT SIGN S = MANTISSA SIGN ONLY 
     
         TABLE OF FLOATING POINT MULTIPLY ALGORITHM                                
LABEL                                                                     
     OPERATION      COMMENT                                               
__________________________________________________________________________
MPY1:                                                                     
     STACK → A                                                     
                    TRANSFER y TO A. DROP STACK.                          
MPY2:                                                                     
     A+C → C(X)                                                    
                    ADD EXPONENTS TO FORM EXPONENT                        
                    OF ANSWER.                                            
     A+C → C(S)                                                    
                    ADD SIGNS TO FORM SIGN                                
     IF NO CARRY GO TO MPY3                                               
                    OF ANSWER                                             
      0 → C(S)                                                     
                    CORRECT SIGN IF BOTH NEGATIVE.                        
MPY3:                                                                     
      0 → B (W)                                                    
                    CLEAR B, THEN TRANSFER                                
      A → B (M)                                                    
                    MANTISSA OF y.                                        
      0 → A(W)                                                     
                    PREPARE A TO ACCUMULATE PRODUCT.                      
      2 → P  SET POINTER TO LSD (LEAST                             
                    SIGNIFICANT DIGIT) MULTIPLIER                         
                    (MINUS 1).                                            
MPY4:                                                                     
     P+1 → P INCREMENT TO NEXT DIGIT.                              
MPY5:                                                                     
     A+B → A(W)                                                    
                    ADD MULTIPLIER MANTISSA TO PARTIAL                    
     C-1 → C(P)                                                    
                    PRODUCT C(P) TIMES. WHEN C(P)=0,                      
     IF NO CARRY GO TO MPY5                                               
                    STOP AND GO TO NEXT DIGIT.                            
     SHIFT RIGHT A(W)                                                     
                    SHIFT PARTIAL PRODUCT RIGHT.                          
     IF P # 12      CHECK IF MULTIPLY IS COMPLETE                         
     THEN GO TO MPY4                                                      
                    (IS POINTER AT MSD).                                  
     IF A (P) &gt; 1   CHECK IF MSD = 0. IF SO MUST                          
     THEN GO TO MPY6                                                      
                    SHIFT LEFT AND CORRECT EXPONENT.                      
     SHIFT LEFT A(M)                                                      
                    MULTIPLY BY 10 AND DECREMENT                          
                    EXPONENT.                                             
     C-1 → C(X)                                                    
MPY6:                                                                     
     C+1 → C(X)                                                    
                    ALWAYS DO THIS TO CORRECT FOR                         
                    FACTOR OF 10 TOO SMALL.                               
     A → B(XS)                                                     
                    DUPLICATE EXTRA PRODUCT DIGITS                        
     A+B → A (XS)                                                  
                    ADD 11th DIGITS.                                      
     IF NO CARRY GO TO MPY7                                               
                    IF SUM LESS THAN 10, THEN DONE.                       
     A+1 → A(M)                                                    
                    IF SUM MORE THAN 10, ADD 1.                           
     IF NO CARRY GO TO MPY7                                               
                    IF ANSWER WAS NOT ALL 9s, THEN DONE.                  
     A+1 → A(P)                                                    
                    IF ANSWER WAS ALL 9s ADD 1                            
     C+1 → C(X)                                                    
                    AND INCREMENT EXPONENT.                               
MPY7:                                                                     
     A EXCHANGE C(M)                                                      
                    GET ANSWER MANTISSA INTO C.                           
     GO TO MASK 1   GO TO ROUTINE TO POSITION THE                         
                    ANSWER IN A AND MAKE THE PROPER                       
                    MASK IN B.                                            
__________________________________________________________________________
 
    
     INSTRUCTION SET 2 
     Whereas the instructions contained within instruction set 1 are those executed by the arithmetic and register circuit, control and timing circuit, read-only memory circuits, and data storage circuit, instruction set 2 comprises those instructions executed by the input/output (I/O) circuit. 
     In some instances the same bit pattern may be representative of an instruction within instruction set 1 as well as an instruction within instruction set 2. This situation requires that the various calculator circuits be made aware of the instruction set under which an instruction is given. In view of this requirement, an IS1 or IS2 mode instruction is issued to designate that instructions which follow are to be taken from either instruction set 1 or instruction set 2, respectively. Following the execution of an IS2 instruction, the arithmetic and register circuit and the control and timing circuit are inhibited from responding to subsequent instructions, since they will be instruction set 2 types. 
     The instructions comprising instruction set 2 are described in the following table, with bit patterns shown in ascending order of significance from right to left. 
     
         __________________________________________________________________________
TABLE OF INSTRUCTIONS (INSTRUCTON SET 2)                                  
MNEMONIC                                                                  
       BIT PATTERN                                                        
               DESCRIPTION                                                
__________________________________________________________________________
ISL    1001000000                                                         
               ENABLE INSTRUCTION SET 1                                   
IS2    0101000000                                                         
               ENABLE INSTRUCTION SET 2                                   
TTC    0111111000                                                         
               T-REGISTER → C-REGISTER                             
CTT    0111110000                                                         
               C-REGISTER → T-REGISTER                             
XOR    0010001000                                                         
               T-REGISTER EXCLUSIVE OR C-REGISTER                         
               →T-REGISTER                                         
IOR    0011001000                                                         
               T-REGISTER INCLUSIVE OR C-REGISTER                         
               →T-REGISTER                                         
AND    0010101000                                                         
               T-REGISTER LOGICAL AND C-REGISTER                          
               →T-REGISTER                                         
ADD    0001101000                                                         
               T-REGISTER LOGICAL AND C-REGISTER                          
               →T-REGISTER                                         
SLT    0100001000                                                         
               SHIFT T-REGISTER LEFT ONE BIT                              
SRT    0101001000                                                         
               SHIFT T-REGISTER RIGHT ONE BIT                             
TINC   1100001000                                                         
               INCREMENT T-REGISTER BY ONE                                
TDEC   1101001000                                                         
               DECREMENT T-REGISTER BY ONE                                
YBC    1110001000                                                         
               INTERROGATE BINARY CARRY                                   
EERA   0001010000                                                         
               EXTERNAL ENTRY TO ROM A                                    
IXT    0100101000                                                         
               I/O REGISTER ⃡ T-REGISTER                      
CCS    1111110000                                                         
               COMPARE C-REGISTER WITH SECTOR COUNTER                     
TCS    1101110000                                                         
               COMPARE T-REGISTER WITH SECTOR COUNTER                     
PRE    0101110000                                                         
               PRINTER ENABLE                                             
ADV    0011110000                                                         
               ADVANCE PAPER                                              
RED    0001110000                                                         
               PREPARE FOR RED PRINT                                      
TTP    1000000000                                                         
               LOAD T-REGISTER INTO PROGRAM COUNTER                       
PTT    1000101000                                                         
               LOAD PROGRAM COUNTER INTO T-REGISTER                       
PINC   0111000000                                                         
               INCREMENT PROGRAM COUNTER BY ONE                           
PDEC   1001001000                                                         
               DECREMENT PROGRAM COUNTER BY ONE                           
RMGRA  0000100000                                                         
               SELECT ROM GROUP A                                         
RMGRB  0010100000                                                         
               SELECT ROM GROUP B                                         
RMGRC  0100100000                                                         
               SELECT ROM GROUP C                                         
YADP   0110100000                                                         
               INTERROGATE AUTO DECIMAL POINT                             
               SWITCH                                                     
READ   1000100000                                                         
               READ PROGRAM MEMORY                                        
SBL    1010100000                                                         
               SET BUSY LIGHT                                             
YFKB   1100100000                                                         
               INTERROGATE FUNCTION BLOCK                                 
               KEYBOARD FLAG                                              
YPOC   1110100000                                                         
               INTERROGATE PRINT-ON COMMAND FLAG                          
YINTF  0000100000                                                         
               INTERROGATE FLAG                                           
WRITE  0010100000                                                         
               WRITE PROGRAM INSTRUCTION                                  
RBL    0100100000                                                         
               RESET BUSY LIGHT                                           
GIOE   0110100000                                                         
               GENERAL I/O ENABLE                                         
ELON   1010100000                                                         
               ERROR LIGHT ON                                             
TG9    1100100000                                                         
               GENERAL I/O INSTRUCTION 1                                  
TG8    1110100000                                                         
               GENERAL I/O INSTRUCTION 2                                  
__________________________________________________________________________
 
    
     SYSTEM MICROPROGRAMMING 
     Referring to FIG. 42, there is shown a flow chart of the overall calculator microprogramming. A detailed listing of the routines shown in this diagram is given later in this specification. The start-up sequence begins by placing the calculator power switch in the &#34;on&#34; position. This forces the control and timing circuit to enable ROM group A and to activate address 000 on ROM A-φ. The instruction located at this address commences execution of the machine initiation routine. The purposes of this routine are to clear all working registers, clear the status bits register, place the calculator in the manual control mode, set the numeric output format to fixed point with two decimal places, call the initiation routines associated with peripheral I/O units, and indicate the status of the calculator system by printing CLEAR on the output printer unit. 
     Upon completion of the machine initiation routine, control is passed to the system supervisor routines. The first tests are routine user code and operation mode code. A nonzero routine code causes control of the system to be transferred to the keyboard function block routines issuing ROM group B call instructions. If the result of the user code test is zero, the operation mode test is activated. A zero result indicates manual control mode, whereas a nonzero result indicates the program run mode. 
     In the manual control mode, the contents of the C-register in the arithmetic and register circuit are formatted for numeric output, the appropriate display mask is built, and the display is switched on. A nonzero data storage user flag results in control being transferred to the data storage routines. If this flag test is zero, control remains in the main system. If the key previously depressed is in the down position, the calculator system remains in a wait loop until that key is released. Releasing a key at this point indicates completion of the previous execution routine and forces the calculator into an idle loop, waiting for a new key to be depressed. 
     When a new key is depressed, a special flag is set in the status bit register which causes the calculator to exit the wait loop. After approximately 3 milliseconds of delay the central processor is prepared for execution of a new routine by resetting some pointer flags and by properly allocating data to various registers. The short time delay is used to eliminate any problems associated with bouncing keyboard switch contacts. If the currently depressed key is associated with a keyboard function block, control is transferred to the function block routines. If the currently depressed key is preceded by the SHIFT key, control is then transferred to ROM A-6 where execution routines for instructions from ROM A-2 and ROM group C have their beginning points. Otherwise, the central processor is prepared to accept a digit entry by resetting the A-register. Execution routines contained in ROM A-1 are now called. 
     In the program run mode, a test is first made to determine if the STOP key has been depressed. If it has, the proper flags are changed to indicate a mode change from program run to manual control, after which control is transferred to the system supervisor starting point. If the STOP key has not been depressed, the program counter is incremented, and a new instruction is read from program memory. If the program memory has not been exceeded, the central processor is prepared to accept a digit entry and to accept a new instruction as the starting address for a routine. In the event memory capacity is exceeded during an increment step, an error routine is called which results in an error message being printed. At the same time, the calculator is returned to manual control and microprogramming control is transferred to the beginning point of the system supervisor. 
     Each execution routine is associated with a particular instruction from the machine language. All of these routines are described in detail below in that portion of the instruction listings which deals with ROM A-φ through A-7. The routine associated with the left parenthesis key is shown in flow chart form at FIG. 48. 
     DETAILED LISTING OF ROUTINES AND SUBROUTINES OF INSTRUCTIONS 
     A complete listing of all of the routines and subroutines of instructions employed by the calculator and of all of the constants employed by these routines and subroutines is given below. The listing includes all routines and subroutines employed by the calculator as basically and optionally configured. All of these routines, subroutines, and constants are stored in the individual ROM circuits within each ROM group, as indicated at the top of the first page associated with each ROM group. Each line of listing associated with each ROM circuit is separately numbered in the first column from the left-hand side of each page. This facilitates reference to different parts of the listing. Each address within each of the ROM circuits is represented in octal form by four digits in the second column from the left-hand side of each page. Branching addresses are represented in octal form by four digits in the fourth column from the left-hand side of each page. The bit pattern of each instruction or constant is represented as ten bits in the fourth column from the left-hand side of each page. Labels associated with particular ones of the instructions are located in the fifth column from the left-hand side of each page. A mnemonic representation for each of the instructions is shown in the sixth column from the left-hand side of each page. Labels associated with the branch instructions are represented in the seventh column from the left-hand side of each page. Explanatory comments are given in the remaining portion of each page. ##SPC1## ##SPC2## ##SPC3## ##SPC4## ##SPC5## ##SPC6## ##SPC7## ##SPC8## ##SPC9## ##SPC10## ##SPC11## ##SPC12## ##SPC13## ##SPC14## ##SPC15## ##SPC16## 
     CALCULATOR OPERATION 
     The basic calculator contains three register locations into which numbers are either entered for immediate use or are stored for later use. These are the X-register, C-register, and RT-register. 
     Each number which the user enters from the keyboard is placed in the X-register. If the calculator is configured with the plug-in LED display unit, the number is displayed as it is entered. The X-register also receives the result of each mathematical operation. 
     Each time the EQUALS key is actuated, a result is generated, which is placed in the X-register and also added to the contents of the RT-register for accumulating the result total. 
     The C-register may be used for storing any constant for later use in making calculations. Whenever the STORE key is actuated, the contents of the X-register are duplicated (stored) in the C-register. Any constant stored in the C-register remains unaltered until either another constant is stored therein or the calculator is switched off. The RECALL key is used to bring the contents of the C-register back into the X-register. 
     Actuating the CLEAR key erases the contents of the X and RT registers and causes the word CLEAR to be printed on the output printer. CLEAR operations leave the contents of the C-register unaltered. 
     Actuating the CANCEL ENTRY key erases the X-register but leaves the C and RT registers unaltered. 
     When operating power to the calculator is removed all storage registers are erased. 
     In addition to printing CLEAR and tallying keyboard operations, the calculator informs the user of his operating errors by printing diagnostic notes when an error has been made. A table of diagnostic notes appears later herein. Some errors may be readily corrected, while others may require that the CLEAR key be actuated and the problem begun again. 
     The four basic arithmetic operations comprising addition, substraction, multiplication, and division may be easily accomplished with the calculator. The first operand is entered; the desired operation key is actuated; the second operand is entered; and then the EQUALS key is actuated to execute the calculation. The result is placed in the X-register. When performing calculations involving more than one operator, each successive operation uses the result of the previous operation. 
     A red busy light on the keyboard flashes whenever the calculator is performing a function and cannot accept key actuations. When the calculator is executing a library program stored in a plug-in ROM or PROM, the busy light may remain on for several seconds. This light simply serves to remind the operator that the calculator will ignore any key actuations which occur during the time it is busy. 
     Negative numbers are entered by first keying in the number and then changing its sign. The sign is changed by successively actuating the SHIFT key and the LEFT PARENTHESIS key. Negative numbers are printed in red on the output printer. 
     As discussed above, the calculator performs successive mathematical operations by using the result of the previous operation. By using the LEFT PARENTHESIS and RIGHT PARENTHESIS keys, operations may be grouped together just as is done in standard mathematical notation involving parentheses. Use of parentheses in expressions eliminates the need for storing and recalling intermediate results. The output printer prints the result of each operation within parentheses at the time each right parenthesis is entered. Parentheses may be nested up to and including five levels. 
     The EXPONENT key is used to raise any number to any power. The number to be raised is entered, followed by the EXPONENT key, followed by the power. 
     The PERCENT key may be used in conjunction with all four arithmetic operators to calculate, for example, a percentage of a number in the X-register or to further use a percentage of a number in the X-register within a calculation. For example, if it is desired to calculate 6% of 39.95, the user would enter 39.95, followed by the MULTIPLY key, followed by 6, followed by the PERCENT key, terminated by the EQUALS key, to give a result of 2.40. As a further example, if the user wishes to discount or subtract 20% from 80, he would first enter 80, followed by the SUBTRACT key, followed by 20, followed by the PERCENT key, terminated by the EQUALS key, to give a result of 64. As a final example, if it is desired to calculate the simple interest for a term of 2 years on $500 at 7%, the user would first enter 500, followed by the MULTIPLY key, followed by 7, followed by the PERCENT key, followed by the MULTIPLY key, followed by 2, terminated by the EQUALS key, to give a result of $70. 
     The output printer unit is associated with several keys which control its operation. The PRINT OFF key suppresses tallying of keyboard operations on the printer, but allows printing of the diagnostic notes plus CLEAR. Actuation of the PRINT key prints the current contents of the X-register, regardless of whether the PRINT OFF mode is in effect. The symbol # accompanies each number printed by actuating the PRINT key. The PAPER key is used to quickly advance the printer paper. When the calculator is turned on the display and print format is automatically set to ROUND 2. This means that each number displayed and/or printed is shown with two digits to the right of the decimal point. This format can be altered to indicate from zero to six decimal point digits by actuating the ROUND key followed by the appropriate number. Printed and displayed numbers may be shown in floating point, or scientific notation by actuating the ROUND key followed by the DECIMAL POINT key. 
     Some of the calculator keys represent dual functions, distinguished by whether actuation has been preceded by actuation of the SHIFT key. Actuation of the SHIFT key followed by the EXPONENT key operates to calculate the reciprocal of the contents of the X-register. Actuation of the SHIFT key followed by the DIVIDE key results in calculating the common logarithm of the number in the X-register. Actuation of the SHIFT key followed by the MULTIPLY key is used to calculate the natural logarithm of the contents of the X-register. 
     Actuation of the SHIFT key followed by the ADD key operates to raise the Naperian logarithm base e to the power indicated by the contents of the X-register. Actuation of the SHIFT key followed by the SUBTRACT key acts to divide the number in the X-register by 12. 
     When solving problems involving the entry of many numbers in the same form, such as dollars and cents, the AUTO DECIMAL POINT key may be used to automatically place the decimal point at a specified position in each number entry. This eliminates physically depressing the DECIMAL POINT key at the proper point during entry of each number. The place at which the decimal point is automatically located is specified by the current rounding format. For instance, if the calculator is operating in round 2 format and the automatic decimal point feature is being used, the decimal point will be placed so that two digits will be indicated to the right thereof. 
     The RT-register accumulates results that are placed in the X-register each time the EQUALS key is actuated. To recall the contents of the RT-register to the X-register, and at the same time display and print the new contents of the X-register, the user simply actuates the SHIFT key followed by the EQUALS key. 
     As described in detail earlier in this specification, the user may plug into the calculator optional data storage units. This option is available to expand the single C-register of the basic calculator in increments of 30 or 100 registers. The extra registers are numbered zero through 29 or zero through 99. To store the data currently in the X-register into one of the registers of the data storage option the SHIFT key is first actuated, followed by the STORE key, followed by the desired register number, terminated by the EQUALS key. To recall a number from optional data storage into the X-register, the same key sequence is followed except that the RECALL key is actuated instead of the STORE key. It is possible to obtain a printed listing of all the data stored in the optional registers by means of the following key sequence: SHIFT, START PROGRAM, PRINT, EQUALS. The register contents are printed in blocks of ten, beginning at register zero. To erase all of the optional data storage registers, the following key sequence is observed: SHIFT, START PROGRAM, ZERO, EQUALS. The optional data storage registers may be incremented or decremented, respectively, by actuating the SHIFT key, followed by the START PROGRAM key, followed by either the ADD key or the SUBTRACT key. 
     As discussed above, a plug-in read-only memory (ROM) or programmable read-only memory (PROM) may be employed with the calculator. Such a ROM or PROM may contain one or more programs written in a user level language which may be run from the calculator keyboard. The programs stored within a plug-in ROM or PROM may be generated by either the user or factory personnel by means of instruction routines stored within ROM A-φ of the basic calculator ROM group. Each of these routines has a starting address in ROM A-φ associated with it. When generating a program for implementation in a plug-in ROM or PROM, the starting address of each routine to be performed is placed in the ROM or PROM bit patterns in the order in which such routines are to be performed by the program. The available routines from which the user may select in creating a program to be implemented in a plug-in ROM or PROM include many which are not represented as keyboard functions executable in the manual mode. The table below lists each available instruction, together with its starting address in ROM A-φ of the basic calculator ROM group. 
     
         __________________________________________________________________________
INSTRUCTION ROUTINE                                                       
             MNEMONIC                                                     
                    INSTRUCTON DESCRIPTION                                
STARTING ADDRESS                                                          
__________________________________________________________________________
064          START  START PROGRAM EXECUTION                               
012          /      FLOATING POINT DIVISION                               
013          *      FLOATING POINT MULTIPLICATION                         
014          STOX   POWER FUNCTION (X.sup.Y)                              
016          )      RIGHT PARENTHESIS                                     
020          =      EQUAL                                                 
022          .      DECIMAL POINT                                         
023          φ  DIGIT ZERO                                            
026          (      LEFT PARENTHESIS                                      
032          3      DIGIT 3                                               
033          2      DIGIT 2                                               
034          1      DIGIT 1                                               
036          %      PERCENT                                               
040          +      FLOATING POINT ADDITION                               
042          6      DIGIT 6                                               
043          5      DIGIT 5                                               
044          4      DIGIT 4                                               
046          CRCL   RECALL DATA FROM USER                                 
                    STORAGE REGISTER TO X-REGISTER                        
050          -      FLOATING POINT SUBTRACTION                            
052          9      DIGIT 9                                               
053          8      DIGIT 8                                               
054          7      DIGIT 7                                               
056          STO    STORE DATA INTO USER STORAGE REGISTER                 
062          RUN    CONTINUE PROGRAM EXECUTION                            
063          LE     SAT LAST ENTRY FLAG                                   
066          CANCEL CANCEL ENTRY                                          
070          SHIFT  SHIFT                                                 
072          RND    ROUND                                                 
073          CLR    CLEAR WORKING REGISTERS                               
076          PRTX   PRINT DATA IN X-REGISTER                              
150          JMP-   JUMP RELATIVE BACKWARD                                
107          NOP    PROGRAMMED PAUSE                                      
131          CHS    CHANGE SIGN OF DATA                                   
207          LBL    LABEL HEAD BEGINNING                                  
152          JMP+   JUMP RELATIVE FORWARD                                 
224          SUBLBX JUMP SUBROUTINE TO COMPUTED LABEL                     
225          SUBLBL JUMP SUBROUTINE TO LABEL                              
226          SUB    JUMP SUBROUTINE TO ADDRESS                            
237          TBL    CALL FUNCTION BLOCK TABLE FUNCTION ()                 
240          Fφ1                                                      
                    CALL FUNCTION BLOCK KEY FUNCTION #1                   
241          Fφ2                                                      
                    CALL FUNCTiON BLOCK KEY FUNCTION #2                   
242          Fφ3                                                      
                    CALL FUNCTION BLOCK KEY FuNCTION #3                   
243          Fφ4                                                      
                    CALL FUNCTION BLOCK KEY FUNCTiON #4                   
224          Fφ5                                                      
                    CALL FUNCTION BLOCK KEY FUNCTION #5                   
245          Fφ6                                                      
                    CALL FUNCTION BLOCK KEY FUNCTION #6                   
246          Fφ7                                                      
                    CALL FUNCTION BLOCK KEY FUNCTION #7                   
247          Fφ8                                                      
                    CALL FUNCTION BLOCK KEY FUNCTION #8                   
250          Fφ9                                                      
                    CALL FUNCTION BLOCK KEY FUNCTION #9                   
251          F1φ                                                      
                    CALL FUNCTION BLOCK KEY FUNCTION #10                  
252          F11    CALL FUNCTION BLOCK KEY FUNCTION #11                  
253          F12    CALL FUNCTION BLOCK KEY FUNCTION #12                  
254          F13    CALL FUNCTION BLOCK KEY FUNCTION #13                  
255          F14    CALL FUNCTION BLOCK KEY FUNCTION #14                  
256          F15    CALL FUNCTION BLOCK KEY FUNCTION #15                  
263          STOP   STOP PROGRAM EXECUTION                                
267          1/X    RECIPROCAL OF X-REGISTER                              
270          EXP    EXPONENTIAL FUNCTION (e.sup.x)                        
275          IFφ                                                      
                    IF DATA IS ZERO TEST                                  
300          STEP   PROGRAM EXECUTION STEP                                
312          IF+    IF DATA IS POSITIVE TEST                              
316          IF-    IF DATA IS NEGATIVE                                   
322          IFLE   IF LAST ENTRY FLAG SET TEST                           
140          PRTACC PRINT GRAND TOTAL FROM ACCUMULATOR                    
325          PRTDS  LIST DATA STORAGE OPTION REGISTERS                    
326          CLDS   CLEAR OPTIONAL DATA STORAGE REGISTER                  
327          DS+    INCREMENT DATA STORGE GIVEN BY (C)                    
330          DS-    DECREMENT DATA STORAGE GIVEN BY (C)                   
331          STO    STORE DIRECT IN DATA STORAGE ADDRESS ()               
332          ACC+   CHANGE STORE TO ACCUMULATE +                          
333          ACC-   CHANGE STORE TO ACCUMULATE -                          
334          ACC*   CHANGE STORAGE TO ACCUMULATE ×                  
335          ACC/   CHANGE STORAGE TO ACCUMULATE ÷                    
336          RCL    RECALL FROM DATA STORAGE ADDRESS ()                   
337          EXCH   EXCHANGE WITH DATA AT ADDRESS ()                      
342          RET    RETURN FROM SUBROUTINE                                
346          SFLG   SET FLAG ()                                           
347          IFFLG  IF FLAG () SET TEST                                   
353          JMPLBX GO TO COMPUTED LABEL                                  
354          JMPLBL GO TO LABEL                                           
355          JMP    GO TO ADDRESS                                         
362          X/12   X-REGISTER DIVIDED BY 12                              
363          ADV    PRINTER PAPER ADVANCE                                 
373          END    PROGRAM END                                           
374          LOGX   COMMON LOGARITHM                                      
375          LNX    NATURAL LOGARITHM                                     
376          CALL   CALL I/O UNIT ()                                      
__________________________________________________________________________
 
    
     Even though a plug-in ROM or PROM is employed, the calculator may still be used in the manual mode. A plug-in ROM or PROM may contain any number of separate programs, limited only by the capacity of the ROM or PROM. Separate programs may be designated by any number between zero and 900. To run a program which is the only one contained in a particular ROM or PROM it is only necessary to actuate the RUN PROGRAM key. If the program contains halts for data entry from the keyboard the user must, after each data entry, actuate the RUN/STOP key. If the ROM or PROM currently employed contains several programs, the user may begin execution of any one of them by actuating the RUN PROGRAM key, followed by the program designation number, followed by actuation of the RUN/STOP key. During execution of a ROM/PROM program successive actuations of the RUN/STOP key will first halt and then resume program execution. 
     In implementing a program in plug-in ROM or PROM, those instruction routines residing in ROM A-φ of the basic calculator may be utilized, as shown and described above. In addition, when one of the plug-in keyboard function blocks is employed with the calculator, additional instruction routines residing within each function block are also available for use in constructing a program in plug-in ROM or PROM. 
     The instruction routines available in the MATH/USER DEFINABLE plug-in keyboard function block are shown in the table below. These functions are called by the function block table call routine TBL, located at address 237 of ROM A-φ and shown in the table above, by specifying the key code accompanying each instruction routine listed below. 
     
         ______________________________________                                    
INSTRUCTION ROUTINES IN THE TABLE OF MATH/USER                            
DEFINABLE FUNCTION BLOCK                                                  
KEY                                                                       
CODE  INSTRUCTION ROUTINE                                                 
______________________________________                                    
00    ANGLE ENTRY (DEGREES, MINUTES, SECONDS)                             
01    SINE                                                                
02    COSINE                                                              
03    TANGENT                                                             
04    ARC SINE                                                            
05    ARC COSINE                                                          
06    ARC TANGENT                                                         
07    SQUARE ROOT OF X-REGISTER                                           
09    X.sup.2                                                             
10    π (PI)                                                           
11    INTEGER OF X                                                        
12    ABSOLUTE VALUE OF X                                                 
13    RECTANGULAR TO POLAR CONVERSION                                     
14    POLAR TO RECTANGULAR CONVERSION                                     
15    DISPLAY DATA STORAGE REGISTER φ                                 
16    VECTOR ACCUMULATE +                                                 
17    VECTOR ACCUMULATE -                                                 
18    RECALL VECTOR ACCUMULATE ±                                       
19    CLEAR VECTOR ACCUMULATE ±                                        
20    CONVERT DEGREES, MINUTES, SECONDS TO                                
      DECIMAL DEGREES                                                     
21    CONVERT DECIMAL DEGREES TO DEGREES,                                 
      MINUTES, SECONDS                                                    
22    CONVERT GRADS TO DECIMAL DEGREES                                    
23    CONVERT DECIMAL DEGREES TO GRADS                                    
24    CONVERT RADIANS TO DECIMAL DEGREES                                  
25    CONVERT DECIMAL DEGREES TO RADIANS                                  
26    CONVERT MILS TO DECIMAL DEGREES                                     
27    CONVERT DECIMAL DEGREES TO MILS                                     
28    ENTER EXPONENT                                                      
30    PRINT DATA STORAGE REGISTERS φ &amp; 1                              
      WITH X,Y LABELS                                                     
31    PRINT DATA STORAGE REGISTERS φ &amp; 1                              
      WITH R,A LABELS                                                     
4N    STORE IN N* 0≦N≦9                                     
5N    RECALL FROM N* 0≦N≦9                                  
______________________________________                                    
 *Where N is one of the 10 data storage registers within the function     
 block.                                                                   
 
    
     In addition to their availability in constructing programs for plug-in ROM or PROM, the above listed instruction routines may be called from the basic calculator keyboard in the manual mode. This is accomplished by successively actuating the SHIFT key and the DECIMAL POINT key followed by the key code of the desired instruction routine (function). 
     Each of the 15 keys on the MATH/USER DEFINABLE plug-in function block is associated with a particular address in a plug-in ROM or PROM. Therefore, a program written in a ROM or PROM may be arranged so that its starting address corresponds to that associated with one of the function block keys. Such a program may then be executed by simply depressing the related function block key. These keys have removable transparent caps, within which the user may insert labels identifying the program or function associated therewith. 
     DIAGNOSTIC NOTES 
     As discussed above, user errors occurring during operation of the calculator are indicated by means of a printed note. A listing of these notes with corresponding error description is given below. 
     
         __________________________________________________________________________
NOTE φφ                                                           
      TOO MANY SUBROUTINE CALLS OR RETURNS                                
NOTE φ4                                                               
      FIVE PARENTHESES LEVELS ALREADY ASSIGNED                            
NOTE φ5                                                               
      RIGHT PARENTHESIS NOTE PRECEDED BY LEFT PARENTHESIS                 
NOTE φ8                                                               
      NEGATIVE NUMBER RAISED TO A NON-INTEGER POWER                       
NOTE φ9                                                               
      LOG OR LN OF A NEGATIVE NUMBER                                      
NOTE 11                                                                   
      BEFORE RESULT MEANS REGULAR OVERFLOW                                
      AFTER RESULT MEANS RT-REGISTER OVERFLOW                             
NOTE 12                                                                   
      LOG OR LN OF ZERO                                                   
NOTE 15                                                                   
      ZERO TO A NEGATIVE POWER                                            
NOTE 16                                                                   
      ATTEMPTED DIVISION BY ZERO                                          
NOTE 20                                                                   
      LABEL NOT FOUND                                                     
NOTE 21                                                                   
      Iφ UNIT NOT FOUND                                               
      PROGRAM MEMORY EXCEEDED                                             
      PROGRAM MEMORY NOT READY                                            
      DATA STORAGE SOFTWARE NOT READY                                     
      FUNCTION BLOCK NOT READY                                            
NOTE 22                                                                   
      RIGHT PARENTHESIS AFTER AN OPERATION                                
NOTE 24                                                                   
      EQUAL SIGN INSIDE PARENTHESES                                       
NOTE 26                                                                   
      DATA STORAGE ADDRESS NOT FOUND                                      
__________________________________________________________________________