Dual emitter programmable memory element and matrix
BACKGROUND OF INVENTION 
     It is known to form field programmable integrated circuit memory matrixes with a variety of different electrically alterable elements. Thus for example, fusible links and transistors are employed for this purpose. The fusible link matrix normally incorporates a link of nichrome or the like which melts and separates upon the application of sufficient electrical power thereto to form an open circuit as the programmed bit in the matrix. A transistor matrix is programmed by application of sufficient electrical power to electrically short one junction of the transistor so as to leave only a single forward conducting diode as a programmed bit in the matrix. These type of matrixes have generally replaced the diode matrixes and are herein termed ROMs. 
     The advantages and wide applicability of field programmable memories has been amply demonstrated by the commercial success thereof. In this rapidly moving field there have been made numerous significant advancements including the programming method and system of U.S. Pat. No. 3,733,690. As a continuation of this rapid advancement in the field, the present invention provides an improved programmable ROM element and matrix affording greater flexibility to the designer and simplification of programming requirements. 
     SUMMARY OF INVENTION 
     The present invention comprises a field programmable integrated circuit matrix having a plurality of dual emitter transistor elements formed in a single substrate with first emitters of the matrix connected in rows and second emitters of the matrix in columns by electrical conductors. Individual elements of the present invention are irreversibly programmed by energizing a selected row and column to pass a current from one emitter to the other of a selected element for electrically shorting one base emitter junction and thus providing a base connection to a single emitter transistor as a programmed location or address. Alternatively, the element may be conventionally programmed by providing a collector connection. Furthermore, it is possible to apply sufficient programming current to electrically short an emitter to both the base and collector whereby a single diode with very low storage time is provided as a programmed address. 
    
    
     DESCRIPTION OF FIGURES 
     The present invention as illustrated as to a preferred embodiment thereof in the accompanying drawings wherein: 
     FIG. 1 is a schematic plan illustration of a dual emitter programmable element in accordance with the present invention; 
     FIG. 2 is a sectional view taken in the plane 2--2 of FIG. 1; 
     FIG. 3 is a schematic illustration of the equivalent electrical circuit programmable element of the FIGS. 1 and 2; and 
     FIG. 4 is a schematic illustration of a portion of a matrix comprised of interconnected elements of the present invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENT 
     A memory array or matrix in accordance with the present invention is comprised of a plurality of dual emitter transistor elements formed in a single substrate and one of such elements is illustrated in FIGS. 1 and 2. Upon a substrate 11 which may have a p- conductivity there is preferably provided an epitaxial layer 12 of n- conductivity. An n+ conductivity buried collector region 13 is provided by conventional techniques below the upper surface 14 of the epitaxial layer and generally disposed in the substrate. A base region 16 of p conductivity extends into the epitaxial layer 12 at the upper surface 14 above the region 13, and within the base region there are provided two n+ emitter regions 17 and 18 extending into the upper surface thereof as illustrated. The base region 16 may be made quite small inasmuch as the present invention does not require separate electrical contact thereto. 
     In accordance with the conventional integrated circuit technology, the upper surface 14 is covered by a protective insulating layer and in the circumstance of a silicon substrate the layer is formed as a silicon oxide layer 19. Openings are made by conventional techniques through the oxide layer 19 to the emitter regions 17 and 18 and separate electrical conductors 21 and 22 extend therethrough into ohmic contact with these regions 17 and 18. 
     The structure of the dual emitter element illustrated in FIGS. 1 and 2 briefly described above may be readily formed by conventional integrated circuit techniques. The element may be considered as two transistors with the region 16 comprising a common base for such transistors, the common collector being provided by the region 13 and the portions of layer 12 between region 13 and the base 16. The regions 17 and 18 may be considered as emitters of the two transistors with electrical contacts extending from these emitters. It will be appreciated that a plurality of these elements are formed as by diffusion and other conventional processing steps in a single substrate to form a matrix as further discussed below. 
     There is illustrated in FIG. 3 an equivalent electrical circuit of the dual emitter transistor matrix element of FIG. 2. In FIG. 3 the element is illustrated as two transistors Q 1  and Q 2  having the bases thereof connected together by a resistor R B  which represents the resistance of the base 16 between the two emitters 17 and 18. The collectors of Q 1  and Q 2  are shown to be connected together by a resistor R C  which represents the combined epitaxial layer and buried collector resistance from the base 16 downwardly through the region 13 and back up to the base. In FIG. 3 the elements of the transistor Q 1  are labeled for convenience E 1  for the emitter, C 1  for the collector and B 1  for the base and, similarly, the elements of transistor Q 2  are labeled E 2  for the emitter, C 2  for the collector and B 2  for the base. These identifications are employed in the following description of the programming of the element of the present invention in a memory matrix. 
     It is first noted that the element of the present invention, as illustrated in FIGS. 1 and 2 and electrically represented in FIG. 3, may be programmed in the same manner as a single emitter structure. Thus, by providing a collector contact, current may be forced from either emitter E 1  or E 2  to the collector by external circuitry so that either base-emitter junction may be shorted to leave only a forwardly conducting transistor junction at the matrix address as an indication of a programmed bit. 
     The present invention may, however, be more advantageously programmed by forcing a current from one emitter to the other. The emitter which is reverse biased will short to the base leaving the other emitter intact. Considering this programming somewhat further and referring to FIG. 3, if a current is forced from E 2  to E 1 , a small current will flow from B 2  to B 1  through R B  and through the Q 1  base-emitter junction to turn on transistor Q 1 . Most of the current flowing into E 2  will flow through the base-collector junction of Q 2  which is forward biased by the voltage drop developed across R B  and then through R C  and from collector to emitter of Q 1 . The ratio of collector current to base current is determined by R C , R B  and the amplification, or beta, of Q 1 . This ratio can be made quite high with the result that Q 2  is programmed very much as if the current flow was entirely from emitter to collector. 
     It is noted that a number of advantages are attained by the present invention programmed as described immediately above.  Comparing the present invention, for example, to a conventional single transistor matrix, it is noted that in the latter matrix the programming current must flow through either a fairly long narrow buried collector or a collector contact or both, which results in a high series resistance. In the dual emitter structure of the present invention, the programming current flows through a very short buried collector and through a second transistor. The series resistance may thus be made quite small even with a fairly high resistivity buried layer. This allows the use of a lower programming voltage. 
     A further, and possibly even more important, advantage of the present invention is that following programming of a bit or address, a transistor remains rather than a diode as in a single transistor matrix. In an array in accordance with the present invention, programming provides a means of selectively making contact to bases of transistors. Considering this point further it is noted that a programmed element of the present invention wherein a current is passed from E 2  to E 1  causes shorting of the E 2  - B 2  junction so that in effect the E 2  connection is made to B 1  without actually providing a physical contact to the base. It will be appreciated that this is advantageous in limiting the size of the base. It is further noted that for some type of ROMs a transistor is a much more desirable array element than a diode. The transistor remaining after programming of an element of the present invention can also be employed simply as a diode and thus it will be seen that the dual emitter structure of this invention is much more versatile than a conventional single transistor array. 
     It is also possible in programming of an element of the present invention to force a programming current into Q 2 , for example, until the emitter E 2  shorts to both the base and collector of Q 2 . While such shorting in a single transistor array is highly disadvantageous, it may be intentionally carried out in accordance with the present invention to short the emitter to base and collector of Q 2 , for example. The foregoing produces a transistor Q 1  with its base and collector shunted by R C  + R B . This then produces a diode, i.e., from the collector-base to emitter of Q 1  with a very low storage time as opposed to the relatively long storage time of a base-emitter diode or a base-collector diode. For certain applications this very short storage time is highly advantageous. It is also noted that the intentional shorting of emitter to both base and collector obviates certain prior art problems of limiting shorting to the base-emitter junction. 
     The present invention may be employed in a variety of ways for a memory array, as generally noted above, and in FIG. 4 there is illustrated a portion of a matrix having rows 41, 42, etc. and columns 51, 52, etc. with dual emitter transistor elements 60 disposed at each &#34;crossover&#34; of row and column with one emitter connected to a row and the other to a column at the crossover. Programming of individual elements 60 of the matrix of FIG. 4 may be readily accomplished by passing a current between the emitters of any desired element. To this end there is schematically illustrated in FIG. 4 a power supply 71 and control 72 connected, for example, to row 42, column 51. This then provides for passing a current from one emitter to the other of the element 60 at the crossover of row 42 and column 51 so as to program the element at that location or address. As noted above, such programming may be accomplished by shorting one of the base-emitter junctions of the element 60. This then provides a transistor connected between the row 42 and column 51 as a programmed location or address in the matrix. Alternatively, as noted above, it is also possible to program the element by applying sufficient programming current through the control 72 to short one of the emitters of the element 60 to both the base and collector of the element. This then produces a diode of very low storage time at the programmed address. 
     It will be appreciated that, although the present invention has been described with respect to particular preferred embodiments thereof, numerous variations and modifications may be made within the spirit of the present invention. It is not intended to limit the present invention to the terms of description nor details of illustration.