Time-division telephone system embodying trunks having demodulating-adder circuits
This invention relates to an improved telephone exchange system, which is especially useful as a private telephone system, for example, in a firm or a building independent of the public telephone system. 
     Although a variety of private telephone exchange systems have been developed and are available commercially, they have such disadvantages and inconveniences such as the increase in the number of the terminal telephone sets, that is, the subscribers, is practically limited since, with increase of the number of subscribers, not only the number of line conductors increases but also the central processing unit becomes significantly larger and more complicated and expensive, that they have few, if any, functions other than simple conversation and it is almost hopeless to increase their functions in view of their structure, and that they often suffer such troubles as cross talk and service interruptions which are generally caused by erroneous operation which sometimes is beyond correction. 
     Accordingly, an object of this invention is to provide an improved telephone exchange system including few line conductors and a compact central unit and having many functions in addition to the normal conversation and a high degree of reliability. 
     The telephone exchange system according to this invention comprises a plurality of telephone sets each having a microphone and an ear-phone, means for generating a hook signal in response to a telephone call starting action and means for generating coded information signals, a plurality of pairs of first gates connected respectively to said microphones and ear-phones, a first line conductor connected in common to the outputs of said first gates connected to said microphones, a second line conductor connected in common to the inputs of said first gates connected to said earphones, a plurality of trunk circuits each including a demodulator-adder circuit for demodulating and then adding the inputs thereof and a coded information receiving circuit connected to the output of said demodulator-adder circuit for receiving said coded information signal selectively from said output, second and third gates connected between said first line conductor and the inputs of said demodulator-adder circuit of said each trunk circuit, a fourth gate connected between the output of said demodulator-adder circuit of said each trunk circuit and said second line conductor, a common signal sound generating device connected to the inputs of said fourth gates through fifth gates respectively, a subscriber scanning device for receiving a hook signal from a first telephone set which may be an arbitrary one of said plurality of telephone sets and producing a subscriber discriminating signal for said telephone set, a central information processor for storing the status of said plurality of telephone sets and trunk circuits and time-divisional gating signals which are peculiar respectively to said plurality of telephone sets, producing a first subscriber information signal corresponding to said first telephone set and a trunk signal for designating one of the vacant trunk circuits in response to said subscriber discriminating signal and also producing a second subscriber information signal corresponding to a second telephone set which is designated by the output of the coded information receiving circuit of said designated trunk circuit in response to said output, and a gate control device for supplying said time-divisional gating signal which is peculiar to said first telephone set to said first gates connected to said first telephone set and said second, fourth and fifth gates connected to said designated trunk circuit and also supplying said time-divisional gating signal which is peculiar to said second telephone set to said first gates connected to said second telephone set and said third, fourth and fifth gates connected to said designated trunk circuit. 
    
    
     Other objects and features of this invention will be described in detail hereinunder with reference to the accompanying drawings. 
     In the drawings: 
     FIG. 1 is a schematic circuit diagram representing in block form a fundamental configuration of the system of this invention; 
     FIG. 2 is a circuit diagram representing an embodiment of the trunk circuit used in the system of FIG. 1; 
     FIG. 3 is a waveform diagram presented as an aid in explaining the operation of the system of FIG. 1; 
     FIG. 4 is a schematic block diagram representing a variation of the circuit of FIG. 1; 
     FIG. 5 is a schematic block diagram representing another variation of the circuit of FIG. 1; 
     FIG. 6 is a circuit diagram representing an embodiment of the circuit of FIG. 5; 
     FIG. 7 is a schematic block diagram representing a modification of the circuit of FIG. 1; 
     FIG. 8 is a block diagram representing a coded information transmitting system included in the system according to this invention; 
     FIG. 9 is a block diagram representing a coded information receiving system included in the system according to this invention; 
     FIG. 10 is a schematic circuit diagram representing an embodiment of the system as shown in FIG. 8; 
     FIG. 11 is a schematic circuit diagram representing an embodiment of the system as shown in FIG. 9; 
     FIG. 12 is a waveform diagram presented as an aid in explaining operations of the circuits of FIGS. 10 and 11; 
     FIG. 13 is a schematic block diagram representing an embodiment of the gate control device of FIG. 1; 
     FIG. 14 is a waveform diagram presented for an aid in explanation of operation of the circuit of FIG. 13; 
     FIG. 15 is a diagram representing a circuit connection of the respective gates of FIG. 1, presented for an aid in explaining a particular aspect of the circuit of FIG. 1; 
     FIGS. 16(1), (2) and (3) are waveform diagrams representing signal waveforms at certain points of the circuit of FIG. 15; 
     FIG. 17 is a diagram representing an equivalent circuit of the circuit of FIG. 15 in its specific operation; 
     FIG. 18 is a schematic circuit diagram representing an embodiment of circuit connection of the circuit of FIG. 1 according to this invention; 
     FIG. 19 is a circuit diagram representing a more concrete embodiment of the circuit of FIG. 18; and 
     FIGS. 20 (a), (b), (c) and (d) are diagrams representing signal waveforms at certain points of the circuit of FIG. 19, presented for an aid in explaining operation of that circuit. 
    
    
     Throughout the drawings, like reference numerals and symbols are used to denote like structural components. 
     Referring to FIG. 1, the system includes a plurality of telephone sets 1.1, 1.2, . . . 1.n as shown by dashed blocks, and each telephone set includes a handset H having a microphone M and an earphone E, a pair of transformers T and a pair of amplifiers A, which form a transmission channel and a reception channel, respectively. Though not shown in the drawing, each telephone set also includes a hook signal generator, which may be a simple contact switch, for generating a so-called &#34;hook signal&#34; when the handset is taken up, and a coded information generator, which may be a telephone dial or a key board, for generating coded information such as telephone number and other coded instructions by manual operation. 
     The outputs of the transmission channels of the telephone sets 1.1, 1.2, . . . 1.n are connected respectively through a plurality of gates &#34;G1T&#34; 2.1, 2.2, . . . 2.n to a single line conductor TL and, similarly, the inputs of the reception channels of these telephone sets are supplied respectively through a plurality of gates &#34;G1R&#34; 3.1, 3.2, . . . 3.n from a single line conductor RL. 
     Between the both line conductors TL and RL, connected in parallel fashion are a plurality of trunk circuits 4.1, 4.2, . . . 4.m (generally, m &lt; n) through gates &#34;G2&#34; 5.1, 5.2, . . . 5.m, gates &#34;G3&#34; 6.1, 6.2, . . . 6.m and gates &#34;G4&#34; 7.1, 7.2, . . . 7.m. Each trunk circuit includes a demodulator-adder circuit DA having a pair of inputs and a single output and a coded information receiver IR connected to the output of the demodulator-adder circuit DA, and is connected between both line conductors TL and RL in such fashion that the pair of inputs of the demodulator-adder circuit DA are connected respectively through the gates G2 and G3 to the line conductor TL and the output thereof is connected through a resistor R and the gate G4 to the line conductor RL. 
     To the inputs of the gates G4 7.1, 7.2, . . . 7.m there is also supplied the output of a signal sound generating unit 9 as shown by a dashed block in the drawing through a single line conductor SL and a plurality of gates &#34;G5&#34; 8.1, 8.2, . . . 8.m, respectively. The signal sound generating unit 9 includes a plurality of sound signal generators 10.1, 10.2, . . . 10.k and corresponding gates &#34;G6&#34; 11.1, 11.2, . . . 11.k, and the generators 10.1, 10.2, . . . 10.k are connected respectively through the corresponding gates G6 to the common line conductor SL. 
     The hook signals from the respective telephone sets 1.1, 1.2, . . . 1.n are transferred generally through loop current circuits to a subscriber scanning device 12 of a known type, which scans the subscribers or telephone sets and produces subscriber discriminating signals corresponding to the subscribers from which the hook signals are transferred. 
     The output of the subscriber scanning device is coupled to a central processing unit 13 for producing gate instruction signals. The outputs of the coded information receivers LR are connected also to the unit 13. The output of the central processing unit 13 is coupled to a gate control unit 14 having outputs, that is, gating signals which are applied respectively to the control terminals of all the gates G1, G2, . . . G6 in accordance with the instruction signals applied from the central processing unit 13. 
     FIG. 2 shows an embodiment of the demodulator-adder circuit DA of each trunk circuit. The inputs from the gates G2 and G3 are respectively applied to both ends of a parallel connection of a series connection of two capacitors C1 and C2 and a series connection of two resistors R1 and R2. The junction of C1 and C2 is grounded and the junction of R1 and R2 is connected to the gate electrode of a field-effect transistor T1 with source electrode connected to a voltage source and drain electrode grounded through a resistor R3. The drain electrode is also connected through a capacitor C3 to the input of an amplifier A1. The output of the amplifier A1, that is, the output of the demodulator-adder circuit DA is coupled to the gate G4 as described previously. 
     Now the operation of the system will be described hereinunder with reference to FIG. 3 as well as FIGS. 1 and 2. 
     When the handset H of an arbitrary telephone set, which is hereinunder marked &#34;A&#34;, is taken up, a hook signal is transferred to the subscriber scanning unit 12. The unit 12 detects that this hook signal came from the telephone set &#34;A&#34; and sends a subscriber &#34;A&#34; discriminating signal to the central processing unit 13. Thus, the &#34;ENGAGED&#34; condition of the subscriber &#34;A&#34; is written in the memory of the unit 13 and the subscriber &#34;A&#34; information stored previously in the memory of the unit 13 is read out and transferred to the gate control unit 14. The subscriber &#34;A&#34; information includes a time-divisional gate control signal PA (FIG. 3) and the gate control unit 14 sends this signal to the gates G1T and G1R belonging to the telephone set &#34;A&#34;. The time-divisional gate control signal is previously determined so as to be exclusively peculiar to each subscriber. 
     At the same time, the central processing unit 13 reads out from its memory a vacant one of the trunk circuits 4.1, 4.2, . . . 4.m and sends a trunk information signal to the gate control unit 14 to designate a trunk circuit to be used. Thus, the gate control unit 14 sends the same gate control signal PA to the gates G2, G4 and G5 belonging to the trunk circuit designated by the central processing unit 13. 
     Then, a coded information signal representing the telephone number of another arbitrary telephone set, which is hereinunder marked &#34;B&#34;, is transferred from the telephone set &#34;A&#34; through the gates G1T and G2 which are opened synchronously by the control signal PA and through the demodulator-adder circuit DA, and picked up by the coded information receiver IR and thereby transferred to the central processing unit 13. The central unit 13 senses the subscriber &#34;B&#34; and, if it is vacant, sends a subscriber &#34;B&#34; information to the gate control unit 14. The gate control unit 14 transfers a time-divisional gate control signal PB (FIG. 3) to the gates G1T and G1R of the telephone set &#34;B&#34; and the gates G3, G4 and G5 of the designated trunk circuit. 
     At the same time, the central processing unit 13 produces a sound signal information designating the &#34;CALL&#34; signal and the gate control unit 14 sends both gate control signals PA and PB to the gate G6 of the signal sound generating unit 9, which is connected to the sound signal generator arranged to produce the &#34;CALL&#34; signal. Thus, the &#34;CALL&#34; signal is synchronously sampled by both gate control signals PA and PB at the gates G6, G5 and G4 to form a waveform S1 as shown in FIG. 3. The waveform S1 consists of two groups of pulses S1A and S1B and is transferred through the line conductor RL, and the group S1A is sampled by the gate control signal PA at the gate G1R of the telephone set &#34;A&#34;, while the group S1B is sampled by the control signal PB at the gate G1R of the telephone set &#34;B&#34;. Thus, the &#34;CALL&#34; signal is reproduced by the reception channels of both telephone sets &#34;A&#34; and &#34;B&#34; and the &#34;CALL&#34; sound is heard by both subscribers &#34;A&#34; and &#34;B&#34; concurrently. 
     If the subscriber &#34;B&#34; is &#34;engaged&#34;, the gate G6 connected to the sound signal generator arranged to produce the &#34;ENGAGED&#34; signal is driven by the control signal PA. Therefore, the subscriber &#34;A&#34; hears an &#34;ENGAGED&#34; sound. 
     When the subscriber &#34;B&#34; takes up his handset H in response to the CALL signal, the hook signal is sensed by the subscriber scanning unit 12 and the central processing unit 13 sends an instruction to the gate control unit 14 to close the gate G6 to stop the CALL signal. 
     Now, the conversation signal produced by the transmission channel of the telephone set &#34;A&#34; is sampled by the gate control signal PA at the gate G1T to form a waveform S2 and the conversation signal produced by the transmission channel of the telephone set &#34;B&#34; is sampled by the waveform PB at the corresponding gate G1T to form a wave form S3, for example, as shown in FIG. 3. As will be understood, the conversation signal output from each gate G1T is a pulse-amplitude-modulated signal. Both signals S2 and S3 are transferred through the line conductor TL as a waveform S4 having two groups of pulses A and B and then sampled respectively by the gates G2 and G3 to be supplied to the two inputs of the demodulator-adder circuit DA of the trunk circuit. 
     The inputs of the demodulator-adder circuit DA are demodulated and summed up therein at the same time. This function will be well understood with reference to the circuit of FIG. 2. The signals S2 and S3 are supplied respectively to both ends of the series connection of the capacitors C1 and C2 and stored temporarily in these capacitors. Accordingly, both signals appear at both ends of the series connection of the resistors R1 and R2 at the same time though the application of both signals to the circuit is not at the same time, and a voltage corresponding to the sum appears at the junction of both resistors. This voltage is amplified by the field effect transistor T1 and the amplifier A1 and output from the demodulator-adder circuit DA. 
     This sum signal is sampled by the gate control signals PA and PB at the gate G4 to form a waveform S5 consisting of two groups of pulses having the same amplitude which corresponds to the sum of the amplitudes of the pulses A and B. Both groups are transferred through the line conductor RL and sampled respectively by the gates G1R of the telephone sets &#34;A&#34; and &#34;B&#34;. Accordingly, the voices of both subscribers &#34;A&#34; and &#34;B&#34; are concurrently heard by both subscribers. 
     As the gate control signals are respectively peculiar to the subscribers as abovementioned, the same operation is obtainable between any pair of subscribers in completely independent and confidential condition with respect to the other subscribers, as long as a vacant trunk circuit exists. 
     The resistor R in the trunk circuit serves a function of maintaining the output impedance of the demodulator-adder circuit DA higher than the input impedance of the gate G4 for preventing backward flow of the sound signal from the gate G5 to the demodulator-adder circuit. It will be understood that the output of each gate G5 may be connected to the output of the gate G4 instead of its input. It will be further understood that the gates G5 may be omitted by connecting the line conductor SL directly to the line conductor RL. However, it should be noted that such reduction and omission of repeated gatings may increase interference and other troubles. 
     Referring next to FIG. 4 showing a variation of the trunk circuit, which will be referred hereinunder as &#34;conference trunk&#34;. This trunk circuit 15 includes two demodulator-adder circuits DA, an adder circuit AD connected to the outputs of both demodulator-adder circuits, a resistor R connected at an end to the output of the adder circuit AD and a coded information receiver IR connected also to the output of the adder circuit. The four inputs of the trunk circuit 15 are respectively connected through two &#34;G2&#34; gates 5M and 5N and two &#34;G3&#34; gates 6M and 6N to the common line conductor TL and the other end of the resistor R is connected through a pair of &#34;G4&#34; gates 7M to the line conductor RL and through a pair of &#34;G5&#34; gates 8M and 8N to the line conductor SL. It is noted that the conference trunk 15 is identical in structure to a pair of normal trunk circuits as shown in FIG. 1 which jointly utilize a coded information receiver IR and a resistor R and is additionally provided with an adder AD. 
     According to another feature of this invention, the system is provided with a plurality of conference trunks as above in addition to the normal trunk circuits 4.1, 4.2, . . . 4.m (FIG. 1). When the &#34;CONFERENCE&#34; key of the coded information input keyboard on one telephone set marked &#34;A&#34; is actuated, a &#34;CONFERENCE&#34; information produced thereby is transferred to the central processing unit 13 and the central processing unit 13 designates a vacant conference trunk 15. In response to trunk information from the central processing unit 13, the gate control unit 14 sends the gate control signal PA peculiar to the subscriber &#34;A&#34; to the gates 5M, 7M and 8M. If the subscriber &#34;A&#34; calls the second subscriber &#34;B&#34; by the key board in this condition, coded subscriber &#34;B&#34; information is transferred through the gate 5M, demodulator-adder DA and adder circuit AD and picked up by the coded information receiver IR and the gate control signals PB peculiar to the subscriber &#34;B&#34; is sent to the gates 6M, 7M and 8M, thereby a CALL signal is transferred to the subscriber &#34;B&#34;, as described with reference to the trunk circuit of FIG. 1. Similarly, the subscriber &#34;A&#34; can call third and fourth subscribers &#34;C&#34; and &#34;D&#34; by pushing the telephone numbers of them successively to send the gate control signal of the subscriber &#34;C&#34; to the gates 5N, 7N and 8N and that of the subscriber &#34;D&#34; to the gates 6N, 7N and 8N, respectively. 
     Thus, the voices of the subscribers &#34;A&#34; and &#34;B&#34; are transferred through the gates 5M and 6M to the corresponding demodulator-adder circuit and the voices of the subscribers &#34;C&#34; and &#34;D&#34; are transferred through the gates 5N and 6N to the other demodulator-adder circuit, respectively, to be demodulated and summed up. The sum outputs of both demodulator-adder circuits DA are summed up again in the adder circuit AD to form a total sum of the voice signals of the four subscribers &#34;A&#34;, &#34;B&#34;, &#34;C&#34; and &#34;D&#34;. The resultant sum output of the adder circuit AD is sampled at the gates G4 and the gates G1R of the respective subscribers by their peculiar gate control signals. Accordingly, the voice of any subscriber can be heard by all the subscribers and, therefore, these four subscribers can have a conference together through their telephones. 
     Although the abovementioned conference trunk can be used for a conference of four or less members only, it is to be understood that a large-scaled conference trunk can be used for larger conferences of five or more members and can be constructed by combining three or more trunk circuits through a single adder circuit AD. 
     FIG. 5 shows another variation of the system of FIG. 1. As shown in the drawing, a switch SW is inserted between the outputs of the demodulator-adder circuits DA of every adjoining trunk circuit in this embodiment. When one switch SW is closed to combine two trunk circuits, the outputs of the demodulator-adder circuits of both trunk circuits are intermixed through the switch SW. Therefore, if the gates G4 and G5 of both trunk circuits are driven in common by the gate control signals of all subscribers involved, the same function as in the conference trunk of FIG. 4 is obtainable. In this embodiment, moreover, larger conferences can be obtained by simply closing two or more switches SW to combine three or more trunk circuits. Control of the switches SW and the gates G4 and G5 may be effected by previously programming the central processing unit 13. 
     FIG. 6 shows a circuit in which the demodulator-adder circuit DA of FIG. 2 is utilized in the embodiment of FIG. 5. As the circuit is self-explanatory, no further description will be made thereon. 
     Referring next to FIG. 7, this system includes a gate &#34;G7&#34; 15.0 and a plurality of gates &#34;G8&#34; 15.1, 15.2, . . . 15.j which are controlled by the gate control unit 14 in substantially same fashion as the &#34;G1R&#34; gates, and in addition to the latter, and the line conductor RL is connected to the inputs of the gates G7 and G8, respectively. The system further includes a plurality of demodulator-adder circuits 16.1, 16.2, . . . 16.j, which are analogous to the demodulator-adder circuits DA in the trunk circuits as described in conjunction with the system of FIG. 1, and the output of the gate G7 is connected to the first inputs of the all demodulator-adder circuits, while the outputs of the gates G8 are connected respectively to the second inputs of the respective demodulator-adder circuits. The outputs of the demodulator-adder circuits 16.1, 16.2, . . . 16.j are connected respectively through transformers T and amplifiers 17.1, 17.2, . . . 17.j to speakers 18.1, 18.2, . . . 18.j. Each speaker may be a group of speakers. Each amplifier is provided with a driving terminal and a driving voltage is supplied from a voltage source V through relay switches 19.1, 19.2, . . . 19.j respectively to the driving terminals of the respective amplifiers. The relay switches are controlled by a relay control unit 20 coupled to the central processing unit 13. 
     When a subscriber marked &#34;C&#34; wants to page through a speaker marked &#34;D&#34;, for example, he pushes certain keys on his key-board in a predetermined fashion to input coded &#34;local-C paging&#34; information. This coded information is received by the coded information receiving circuit IR of a specified vacant trunk circuit and transferred to the central processing unit 13. The central unit 13 sends gate information to the gate control unit 14 and relay information to the relay control unit 20. 
     In response to the gate information, the gate control unit 13 sends a time-division gate control signal peculiar to the subscriber &#34;C&#34; to the gates G1T and G1R of the subscriber &#34;C&#34; and the gate G2 of the specified trunk circuit, another time-division gate control signal peculiar to the speaker &#34;D&#34; to the gate G3 of the same trunk circuit and the gate G8 corresponding to the speaker &#34;D&#34;, and both gate control signals to the gates G4 and G5 of the same trunk circuit and the gate G6 connected to the sound signal generator which produces a paging notice sound. At the same time, in response to the relay information, the relay control unit 20 sends a relay driving signal to the relay switch coupled to the amplifier corresponding to the speaker &#34;D&#34;, thereby actuating said amplifier. 
     Thus, the paging notice sound and succeeding voice of the subscriber &#34;C&#34;, which are transferred through the line conductor RL, are sampled by the above active gate G7, demodulated by the corresponding demodulator-adder circuit, amplified by the actuated amplifier and reporduced by the speaker &#34;D&#34;. When the subscriber &#34;C&#34; puts down the handset, the central processing unit 13 sends an instruction to the gate control unit 14 and the relay control unit 20 to interrupt the gate control signals and the relay driving signal, to restore the original condition. 
     When the subscriber &#34;C&#34; wants to page through all the speakers, he pushes certain keys in predetermined fashion to input coded &#34;over-all paging&#34; information. In this case, the central processing unit 13 is previously programmed to send instructions to the gate control unit 14 and the relay control unit 20 to send a time-division gate control signal peculiar to &#34;over-all paging&#34; to the gate G7 and also to the gates G3, G4, G5 and G6 as abovementioned, and to send a relay driving signal to all the relay switches 19.1, 19.2, . . . 19.j. Thus, the paging notice sound and the subscriber&#39;s voice are sampled by the gate G7, demodulated by all the demodulator-adder circuits 16.1, 16.2, . . . 16.j and, therefore, reproduced by all speakers 18.1, 18.2, . . . 18.j. 
     In case of &#34;over-all paging&#34;, cross-talk or interference may occur when &#34;local paging&#34; is made at the same time through one of the speakers. However, the trouble can be overcome by previously programming the central unit 13 so that the gate G8 used for the &#34;local paging&#34; is temporarily closed for the &#34;over-all paging&#34; time. 
     Referring to FIG. 8, this block diagram represents a schematic configuration of the means for generating coded information signals included in each telephone set as described in the preface and specified in the claims. This means includes a phase-code modulator circuit 21 provided with a key board K having a plurality of keys numbered &#34;0&#34;, &#34;1&#34;, &#34;2&#34;, . . . &#34;15&#34;, for example. The phase-code modulator 21 produces a phase-code modulation signal &#34;Z&#34; corresponding to the number of a pushed key and supplies it to a twin frequency oscillator circuit 22 which produces a signal &#34;F 0  &#34; having two alternating frequencies under control of the phase-code modulation signal &#34;Z&#34;. The resultant twin frequency code modulation signal &#34;F 0  &#34; is filtered by the filter 23 to remove higher harmonics and transferred through the gate &#34;G1T&#34; as abovementioned and the line conductor TL to a specified trunk circuit. While the voice or conversation signal also comes into the gate G1T from the microphone M as described previously, a gate 25 is provided before the gate G1T in order to block the voice signal during transmission of the coded information under control of a gate control signal Y as described later. 
     As a feature of this invention, the twin frequency code modulation signal F 0  is also supplied to a frequency divider circuit 24 and the phase-code modulator circuit 21 is controlled by the frequency-divided signals Q. This feature will be described in detail later. 
     The coded information transferred in a form of twin frequency code modulation signal F, is received by the coded information receiving circuit IR in the trunk circuit. FIG. 9 represents a schematic configuration of this circuit. The signal F 1  output from the demodulator-adder circuit DA passes a band-pass filter 26 and comes in a frequency discriminator 27. The frequency discriminator 27 discriminates two frequencies included in the signal and produces an output signal which is identical to the abovementioned phase-code modulation signal Z. This signal Z is processed in a phase-code modulation demodulator circuit 28 having binary coded outputs which are supplied to the central information processing unit 13. 
     Referring to FIG. 10, there is shown an embodiment of the circuit of FIG. 8. The phase-code modulator circuit 21 includes a binary encoder 29 which is provided with a keyboard having sixteen keys K 0 , K 1 , K 2 , . . . K 15  corresponding respectively to decimal codes 0, 1, 2, . . . 14 and 15, for example. The binary encoder 29 has five outputs A, B, C, D and X. The outputs A, B, C and D correspond respectively to inversions of the first, second, third and fourth bits of a binary code which corresponds to a decimal code input through the key-board. For instance, when the key K 13  is pushed to input a decimal code &#34;13&#34; which corresponds to a binary code &#34;1101&#34;, the outputs A, B, C and D are &#34;0&#34;, &#34;1&#34;, &#34;0&#34; and &#34;0&#34;, respectively. The outputs A, B, C and D are applied to two data selectors 30 and 31 having seven inputs U0, U1, U2, U3, U4, U5 and U6 each, together with their otiginals A, B, C and D obtained through NOT gates as shown. In this embodiment, the outputs A, A, B, B and C are coupled respectively to the inputs U3, U4, U5, U6 and U7 of the data selector 30 and the outputs C, D and D are coupled respectively to the inputs U0, U1 and U2 of the data selector 31. The inputs U1 and U2 of the data selector 30 are assigned to &#34;START&#34; signal bits S and S and maintained always &#34;1&#34; and &#34;0&#34; respectively, and the inputs U5 and U6 of the data selector 31 are assigned to &#34;STOP&#34; signal bits F and F and maintained also always at &#34;1&#34; and &#34;0&#34; respectively. The fifth bits E and E are unnecessary in this embodiment since the greatest binary code is &#34;1111&#34; which corresponds to the last key K 15  and, therefore, the corresponding inputs U3 and U4 of the data selector 31 are maintained always at &#34;0&#34; and &#34;1&#34;, respectively. Also, the first input UO of the data selector 30 and the last input U7 of the data selector 31 are maintained always at &#34;1&#34; in order to keep the output reference at HIGH level. 
     On the other hand, the output X of the binary encoder 29 is a signal as shown in FIG. 12, which appears in response to a pushing action of any key on the key-board and has chatters CH, that is a plurality of pulses, at the both starting and terminating ends of the pushing action. The output X is integrated by an integration circuit 32 (X 1  of FIG. 12), inverted by a NOT gate 33 and then differentiated by a differentiation circuit 34 (X 2  of FIG. 12). The signal X 2  is applied to the input of a flip-flop circuit 35 consisting of two NAND gates to invert its Y output, which has been preset at HIGH level, into LOW level. In response to this inversion, the twin frequency oscillator circuit 22 initiates its operation. 
     The twin frequency oscillator 22 is a flip-flop circuit comprising two NAND gates, resistors R H  and R L , a capacitor C and a controlled switch 36 which are interconnected as shown in the drawing, and producing a clock pulse train F 0  (FIG. 12) with two different frequencies f H  and f L  for the reason as described below. The output F 0  of the twin frequency oscillator 22 is applied to the frequency divider 24, which is a 2 7  counter having seven outputs Q1, Q2, . . . Q7 and a RESET input connected to the Y output of the flip-flop 35 in this embodiment. The outputs Q1, Q2, . . . Q7 are frequency-divided signals of the input clock F 0  by divisors 2, 4, 8, 16, 32, 64 and 128, respectively, while only Q1 and Q6 are shown as examples in FIG. 12. 
     Among the outputs of the counter 24, three outputs Q3, Q4 and Q5 are applied to both data selectors 30 and 31 as their control inputs. That is to say, every application of the control inputs, the inputs U0, U1, U2, . . . U7 are successively coupled to the output terminals Z. On the other hand, the output Q6 of the counter 24 is directly connected to the SET input of the data selector 30 and is connected through a NOT gate 37 to the SET input of the data selector 31, so that the data selector 30 is operated during the LOW level of Q6 and the data selector 31 is operated during the HIGH level thereof. Thus, a phase-code modulated signal as shown by Z in FIG. 12 is produced from the output terminals Z when A, B, C and D are &#34;1&#34;, &#34;0&#34;, &#34;1&#34; and &#34;1&#34;, respectively, for example. 
     In this waveform Z, one bit time corresponds to one cycle (one period) time of the quarter frequency signal Q2, and the first half thereof is occupied by a specific code (e.g., &#34;A&#34;) and the second half is occupied by its inversion (e.g., &#34;A&#34;). 
     The output of the NOT gate 37 is differentiated into a waveform Q6&#39; (FIG. 12) by a differentiation circuit 38 and applied to the RESET terminal of the flip-flop circuit 35. Thus, the Y output of the flip-flop 35 restores its HIGH level at the trailing edge of the signal Q6 to stop operation of the oscillator 22 and reset the counter 24. The Y output is also applied to the gate 25 (FIG. 8) to close it during the operation of the oscillator 22 in order to prevent the conversation signal from mixing in the coded information signal. 
     During this time, the output Z is applied to the twin frequency oscillator circuit 22 as a control input of the controlled switch 36 to close it by its HIGH level and open it by its LOW level. When the switch is closed and the resistor R H  is inserted in the circuit, the output F 0  becomes to have the high frequency f H  and, when it is opened to remove the resistor R H  therefrom, F 0  has the low frequency f L . 
     It is understood from the above description that one bit time of the phase-code modulated signal Z is determined by frequency-division of both frequencies f H  and f L , so that there is no phase difference between the waveform of frequency f H  and that of frequency f L  at the time of frequency interchange. This is an important feature of this invention since it enables very simple demodulation of the modulated signal. 
     The output F 0  of the twin frequency oscillator circuit 22 is filtered by a filter circuit 23 to remove its higher harmonics and transferred through the gate G1T to the lead conductor TL, as a twin frequency code modulated signal F 1  as shown in FIG. 12. 
     As described previously in conjunction with the circuit of FIG. 9, the twin frequency code modulated signal F 1  is received by the coded information receiving circuit IR in the trunk circuit, filtered by the band-pass filter 26 and applied to the frequency discriminator circuit 27 to restore the phase-code modulated signal waveform Z as shown in FIG. 12. The phase-code modulated signal Z is demodulated by the phase-code demodulator circuit 28. 
     FIG. 11 shows an embodiment of the phase-code demodulator circuit 28. In this circuit, the phase-code modulated signal Z is applied through a NOT gate 39 to a shift register 40 having a clock input CL, a gate signal input G, a reset signal input R and seven parallel outputs Qa, Qb, Qc, Qd, Qe, Qf and Qg. The output of the NOT gate 39 is also applied directly to one input of an exclusive OR gate 41 and through a resistor 42 to another input thereof which is grounded through a capacitor 43. The output of the exclusive OR gate 41 is connected directly to a monostable circuit 44 whose output is connected to the clock input CL of the shift register 40, and connected through a NOT gate 45 to another monostable circuit 46 whose output is connected to the gate signal input G thereof. The output of the monstable circuit 46 is also connected through a differentiation circuit 47 to the reset input of the shift register 40. 
     When the inversion of Z is applied from the NOT gate 39 to the exclusive OR gate 41, one input terminal is at an opposite level with respect to the other input terminal for a short time determined by a time constant of the circuit consisting of the resistor 42 and the capacitor 43 and the output keeps HIGH level during this time and soon drops to LOW level, thereby producing a waveform as shown by Z 1  in FIG. 12. The monostable circuit 44 is previously arranged such that its output G becomes HIGH at each leading edge of the waveform Z, and maintains this level for a time period equal to about 75 percent of one bit time of the phase-code modulated signal Z as abovementioned. Accordingly, the output of the monostable circuit 44 is as shown at Q in FIG. 12. The signal Q is applied to the shift register 40 as its shift control pulse to control shift operation of the input Z. 
     On the other hand, the monostable circuit 46 is arranged such that its output becomes HIGH at the first leading edge of the signal Z 1  and maintains this condition until the signal Z from the frequency discriminator circuit 27 (FIG. 9) is completely transferred through the NOT gate 39 into the shift register 40. Accordingly, the output waveform of the monostable circuit 46 is shown by G in FIG. 12. This output G is differentiated by the differentation circuit 47 as shown by G&#39; and applied to the reset terminal R of the shift register 40. Therefore, the shift register 40 is reset at the first leading edge of the inverted input signal Z. 
     The input signal Z is shifted successively in the shift register by the clock pulse Q and output from the terminals Qa, Qb, Qc, Qd, Qe, Qf and Qg with waveforms as shown by the same symbols in FIG. 12, respectively. As readily understood from the drawing, these outputs reach at least statuses &#34;1&#34; &#34;0&#34;, &#34;1&#34;, &#34;1&#34;, &#34;0&#34;, &#34;1&#34; and &#34;1&#34;, respectively, and, if they correspond to the input codes &#34;F&#34;, &#34;E&#34;, &#34;D&#34;, &#34;C&#34;, &#34;B&#34;, &#34;A&#34; and &#34;S&#34;, respectively, this means that the input codes at the phase-code modulator 21 (FIGS. 9 and 10) have been reproduced. The output codes &#34;A&#34;, &#34;B&#34;, &#34;C&#34;, &#34;D&#34; and &#34;E&#34; are transferred to the central processing unit 13 for the purpose as described previously. 
     In the above-described coded information transmission system of twin frequency code modulation type, the transmission speed is higher than that of the prior pulse number transmission type, and a fewer number of frequency oscillators are required and a multi-frequency filter is not required for demodulation as compared with the multi-frequency type. Moreover, it is easy to separate the coded information from the conversation to prevent erroneous operation due to interference. Furthermore, as a single oscillator device can include two signal sources of different frequencies, the same temperature stability is obtainable on the both frequencies and, accordingly, design of the demodulator is facilitated. 
     Referring next to FIG. 13, this drawing shows an embodiment of the gate control device 14 of FIG. 1. The circuit includes a clock pulse generator 48 which produces a clock pulse train CP, as shown in FIG. 14, having a pulse width of 375 nanoseconds and a pulse interval of 250 nanoseconds, for example. This pulse train CP is supplied to a frequency divider 49, which is a 2 5  counter circuit having five outputs C0, C1, C2, C3 and C4 (FIG. 14) in this embodiment. These outputs form a binary code of five bits and is applied successively to first sets of inputs of write control devices 50 and 51, respectively. To second sets of inputs of the respective write control devices 50 and 51, there is also applied a binary code having five bits C0, C1, C2, C3 and C4 from the central information processing unit 13 (FIG. 1). This code carries trunk circuit information and, for example, the first (lowermost) bit &#34;C0&#34; is used to distinguish transmitting station and receiving station, that is, &#34;0&#34; of this bit expresses the transmitting station and &#34;1&#34; expresses the receiving station. The other four bits C4, C3, C2 and C1 form a binary code corresponding to the trunk circuit number. In this embodiment, &#34;0000&#34; expresses the trunk circuit 4.1 and &#34;1111&#34; indicates the trunk circuit 4.16 (FIG. 1). 
     The write control devices 50 and 51 are controlled in their write operation by a control signal which is, for example, an inversion CP of the clock pulse CP supplied through a NOT gate 54. In these circumstances, the write control devices 50 and 51 pass the trunk circuit information code for 250 nanoseconds, the clock pulse interval, when coincidence is obtained between both binary codes from the frequency divider 49 and the central processing unit 13. The outputs of the write control devices 50 and 51 are respectively supplied to first sets of inputs of subscriber data memory 52 and sound signal data memory 53. 
     The second set of inputs of the subscriber data memory 52 is also a binary code having eight bits A0, A1, A2, A3, A4, A5, A6 and A7 and carrying a subscriber information. In this embodiment, the bits A6, A5, A4, A3, A2, A1 and A0 form a binary code corresponding to the subscriber number, that is, &#34;0000000&#34; expresses a subscriber X1 having decimal number &#34;001&#34; and &#34;1111111&#34; expresses a subscriber X128 having number &#34;128&#34;. The eighth (uppermost) bit &#34;A7&#34; is used for distinguishing whether the subscriber is using a trunk circuit or not, that is, &#34;1&#34; of the bit A7 expresses use of the trunk circuit and &#34;0&#34; expresses not-use thereof. 
     The subscriber data memory is a random access memory of 8 bits and 32 words, for example, and stores the above information in an address specified by the trunk circuit information supplied from the write control device 50 under control of the signal CP. The stored information is read out from the memory 52 every 128 counts of the 2 5  counter 49, that is, at 20 microsecond periods and applied to a logic circuit 54. To the logic circuit 54, there are also applied the clock pulse CP from the clock pulse generator 48 and the detection signal Q from an operation detecting circuit 57. The detecting circuit 57 checks the clock pulse CP to verify operation of the clock pulse generator and keeps its output Q at HIGH level &#34;1&#34; in case of normal operation and at LOW level &#34;0&#34; in case of abnormal operation. 
     The logic circuit 54 includes at most 128 AND circuits for obtaining logic products of the inputs A7, CP and Q and seven members from A0, A1, A2, A3, A4, A5, A6, A0, A1, A2, A3, A4, A5 and A6, which outputs are respectively connected to the gates &#34;G1T&#34; and &#34;G1R&#34; as their gate control pulses. For example, the AND gate having inputs A7, CP, Q, A6, A5, A4, A3, A2, A1 and A0 is connected to the &#34;G1T&#34; gate 2.1 and the &#34;G1R&#34; gate 3.1 and produces an output when the logic product of these inputs is &#34;1&#34; to open these gates for 375 nanoseconds at a period of 20 microseconds. 
     On the other hand, the write control device 51 supplies the truck circuit information (C4,C3,C2,C1,C0) to a sound signal data memory 53 which is, for example, a random access memory of 4 bits and 16 words, in the same fashion as in the case of the write control device 50. To the memory 53, there is also supplied a sound signal information code consisting of four bits B0, B1, B2 and B3. The last bit &#34;B3&#34; is used for distinguishing whether any signal sound is used or not and &#34;1&#34; of this bit expresses its use, while &#34;0&#34; expresses non-use. The other bits B2, B1 and B0 form a binary code expressing the sort of sound signal. For example, &#34;000&#34; expresses &#34;initial buzz&#34; which can be heard when the handset is taken up first, and &#34;001&#34; expresses &#34;call ring&#34; after the telephone number is introduced. The sound signal information is also stored similarly in the memory 53 and read out also in a 20 microsecond period. This information is supplied to a logic circuit 55 together with the signals CP, Q and A7. The logic circuits 55 also includes a plurality of AND gates having seven inputs which are CP, Q, A7 and B3 and three members of B0, B1, B2, B0, B1 and B2. The outputs of these AND gates are connected respectively to the gates G6 corresponding to the respective sound signal generators (FIG. 1). 
     The outputs C0, C1, C2 and C4 of the frequency divider 49 is also supplied to a logic circuit 56 together with the signals CP, Q, A7 and B3. The logic circuit 56 includes four groups of AND gates. The AND gates of the first group have the inputs CR, Q, A7 and CO and four members from C1, C2, C3, C4, C1, C2, C3 and C4 and their outputs are connected respectively to the gates G2 (FIG. 1). The AND gates of the second group have the same inputs as the first group except that CO is substituted for CO, and their outputs are connected respectively to the gates G3, respectively. Those of the third group have the same inputs as the first and second groups except that CO and CO are cancelled, and their outputs are connected respectively to the gates G4 (FIG. 1). Those of the fourth group have the same inputs as the third group and an additional input B3, and connected respectively to the gates G5 (FIG. 1). This input combination, output connection and output waveforms are partly illustrated in FIG. 14 as an example. 
     As will be understood from the above description, in this embodiment of the invention, confirmation or distinction bits CP, Q, A7, B3 and CO are supplied to the logic circuits 54, 55 and 56 in addition to the normal digital codes. Due to the inputs CP and Q, the logic circuits 54, 55 and 56 do not produce any output when no clock pulse is generated or it is abnormally generated. Due to presence of the input A7, no gate is opened and no communication is effected when no specific trunk circuit is shared for operation. Due to presence of the signal B3, the gates G5 and G6 are kept as closed when the signal sound generating device is not used. The signals C0 and C0 serve to distinguish the transmitter and receiver. By applying these distinction signals to the logic circuits, any interference or cross-talk which may be caused by some trouble in circuit or erroneous operation is overcome. 
     The transmission gates (G1T) 2.1, 2.2, . . . 2.n coupled respectively to the telephone sets 1.1, 1.2, . . . 1.n and the G2 gates 5.1, 5.2, . . . 5.m and the G3 gates 6.1, 6.2, . . . 6.m respectively coupled to the demodulator-adder circuits DA1, DA2, . . . DAm of the trunk circuits 4.1, 4.2, . . . 4.m are generally interconnected as shown in FIG. 15 through the line conductor TL which is grounded through a resistor R T . While these gates may be composed of bipolar transistors or MOS (metal oxide semiconductor) transistors, MOS transistors are prefered for this purpose since they exhibit such high advantages as low power consumption and high packing density. However, due to high conduction resistance, MOS transistors encounter a problem of low switching speed caused by load capacitance and stray capacitance when driven by time-division gate control signals. 
     More particularly, the gates G1T each have stray capacitance C.sub.α, the line conductor TL has stray capacitance C T  and the gates G2 and G3 each have stray capacitance C 62 , as shown in FIG. 15. For instance, when the G1T gate 2.1 and the G2 gate 5.1 are opened synchronously to transfer subscriber information from the telephone set 1.1 through the line conductor TL to the demodulator-adder circuit DA1, the stray capacitances C.sub.α, C T  and C.sub.β  are inserted in parallel with respect to the flow of subscriber information and, therefore, the total stray capacitance C S  is written as follows. 
     
         C.sub.S = nC.sub.α + 2mC.sub.β  + C.sub.T 
    
     if the conduction resistances of the gates 2.1 and 5.1 are represented by resistors R 2 .1 and R 5 .1, an equivalent circuit is given by FIG. 17. 
     Under the above circumstances, a pulse signal A appearing at the output of the G1T gate 2.1, as shown in FIG. 16 (1), is stored in the capacitor C 1  of the demodulator-adder circuit DA1 and also in the total stray capacitance C S . In this case, the leading edge of the signal A stored in the capacitance C 1  is deformed as shown in FIG. 16(3) by the resistors R 2 .1 and R 5 .1. Moreover, the charge stored in the total stray capacitance C S  is discharged through the resistor R T  simultaneously with closure of the gates 2.1 and 5.1, taking a long discharge time due to large value of the total stray capacitance C S . This results in a slow trailing edge which may interfere with another subscriber signal pulse B being transferred side by side through the same conductor and cause cross-talk, as shown by shaded portion in FIG. 16(2). According to another feature of this invention, the abovementioned trouble is removed by reducing the driving impedance and stray capacitance of the line conductor by using the following circuit configuration. 
     FIG. 18 shows an improvement of the circuit of FIG. 15. In this arrangement, the n G1T gates 2.1, 2.2, . . . 2.n are classified into s groups each including r G1T gates and the outputs of G1T gates of the respective groups are connected to the inputs of s impedance transformers 57.1, 57.2, . . . 57.s, respectively. The outputs of the impedance transformers are connected respectively through forwardly directed diodes 58.1, 58.2, . . . 58.s to one end of the line conductor TL. The m trunk circuits 4.1, 4.2, . . . 4.m are also classified into t groups each including q trunk circuits and the inputs of trunk of the respective groups are connected to the outputs of t impedance transformers 60.1, 60.2, . . . 60.t respectively. The inputs of the impedance transformers are connected in common with the other end of the line conductor TL. 
     Assuming now the total stray capacitance of the circuit in the lefthand side of the cathode of each diode as C&#39; and that of the circuit in the righthand side of the input of each impedance transformer 60.1, 60.2, . . . or 60.t as C&#39;.sub.β, each impedance transformer is provided to make C&#39; less than rC and C&#39; less than 2qC. Therefore, the total stray capacitance C S  &#39; of the circuit of FIG. 18 is as follows. ##EQU1## 
     The impedance transformers 57.1, 57.2, . . . 57.s and 60.1, 60.2, . . . 60.t also reduce the transmission line between the G1T gates and the gates G2 and G3. The abovementioned reduction of stray capacitance and driving impedance results in improvement of the leading edge of the pulsed information. Low output impedances of the impedance transformers 57.1, 57.2, . . . 57.s enable reduction of the grounding resistance R T . 
     Resistors 59.1, 59.2, . . . 59.s for grounding the inputs of the impedance transformers 57.1, 57.2, . . . 57.s are provided for reducing the time-constant due to stray capacitances C of the G1T gates. This time constant can be made small by reducing the value of these resistors but this value can not be made extremely small since a.c. loss due to the conduction resistance of the G1T gate is increased thereby. The object of each diode is to block any information coming in the corresponding impedance transformer from the other impedance transformers. 
     FIG. 19 shows a preferred embodiment of the arrangement of FIG. 18, in which the impedance transformers 57.1, 57.2, . . . 57.s and 60.1, 60.2, . . . 60.t are composed of bipolar transistors. FIGS. 20(a), (b), (c) and (d) show the waveforms at the circuit points (a), (b), (c) and (d), respectively, as shown in FIG. 19. In this circuit, the information signal reduces its amplitude successively due to the base-emitter voltage V be  of the transistors and the forward voltage drop V d  of the diode, but keeps its leading and trailing edge in good condition. 
     When the input impedances of the impedance transformers 60.1, 60.2, . . . 60.t are very low, the grounding resistor R T  can be omitted. Furthermore, these impedance transformers may be also omitted.