Alarm electronic timepiece
BACKGROUND OF THE INVENTION 
     This invention relates to an alarm electronic timepiece having a multi-alarm function, having two channels, wherein one of them relates to a single alarm circuit, and the other channel relates to a repeat alarm circuit. The channels are separately provided and independent of each other. 
     In the conventional alarm timepiece, a single alarm for operating at a predetermined time and for not operating alarm at the next occurrence of the predetermined time is preferable for use at different predetermined times. However, it is difficult to usually operate to develop an alarm signal at the same predetermined time every day. On the other hand, a repeat alarm function for repeatedly operating an alarm signal at the same predetermined time is very convenient, however it is necessary to reset the memorized contents of the alarm circuit for use to only one time. 
     SUMMARY OF THE INVENTION 
     This invention aims to eliminate the above noted difficulty and insufficiency, and the object of the present invention is to provide in a timepiece an alarm function having single alarm and repeat alarm circuits, namely two alarm channels. 
    
    
     EXPLANATION OF THE DRAWINGS 
     FIG. 1 shows a block diagram of the alarm electronic timepiece of the present invention, 
     FIG. 2 shows details of gate circuitry used in the timepiece illustrated in FIG. 1; and 
     FIG. 3 shows details of setting circuitry used in the timepiece illustrated in FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows a circuit block diagram of the present invention. The alarm electronic timepiece is composed of a time counter 1, a coincidence circuit 2 for applying an alarm signal to an alarm device 5 when the time information of said time counter 1 coincides with present alarm time information of a single alarm counter 3 and repeat alarm counter 4, and a channel selecting alarm time setting circuit 6 for selecting one of said alarm counters 3 and 4 and setting the alarm time of one of said alarm counters 3 and 4. Said alarm device 5 is composed of a buzzer or light emitting diode or liquid crystal. 
     Referring now to the operation of the present invention: 
     Said alarm device 5 is operated when the time information of said time counter 1 operated by a 1Hz signal from the oscillating dividing circuit 7, coincides with the time information of said alarm counters 3 and 4. When the time information of said single alarm counter 3 coincides with the time information of said time counter 1, said single alarm counter 3 is reset by the coincidence output from said coincidence circuit 2, whereby the alarm time is no longer set in said single alarm counter 3 after the set time has elapsed. Namely said single alarm counter 3 is a single alarm means, not a repeating type alarm. When the time information of said repeat alarm counter 4 coincides with the time information of said time counter 1, the reset input signal is not applied to said single alarm counter 3 so that the single alarm counter 3 is not reset. Further the reset input signal is not applied to said repeat alarm counter 4, whereby said repeat alarm counter 4 is not reset. The repeat alarm counter 4 will not be reset unless an external reset signal is applied thereto, and therefore the alarm signal is generated by said alarm device whenever the set time occurs. 
     Said single alarm counter 3 and repeat alarm counter 4 respectively define different channels. The channels are selected by said channel selecting circuit 6, whereby it is possible to set the alarm time according to which of said channels is selected namely said single alarm counter 3 and repeat alarm counter 4 respectively. 
     According to the present invention, it is possible to separately mount said single alarm counter and repeat alarm counter as two channels, whereby it is possible to make a convenient watch having two channels. 
     FIG. 2 shows the detailed structure of the embodiment, illustrated in FIG. 1. A 32 Hz signal as a clock pulse is generated from the oscillating dividing circuit 7. The comparison between the single alarm counter 3, the repeat alarm counter 4 and the time counter 1 is operated every 31 milliseconds. At this time the contents of said counters 3 and 4 are alternately compared with the contents of said time counter 1 by the inverter 25. When said 32 Hz pulse signal is applied to the AND-gate 21, said AND-gate 21 becomes ON whereby a signal is applied to said coincidence circuit 2 via OR-gate 22, the contents of said time counter 1 and counter 4 are compared, and an alarm is generated by the output applied from said coincidence circuit 2 to the alarm device only when the times coincide. At this time, a zero level signal is applied to AND-gate 24 by the inverter 25, whereby the reset pulse is not applied to said single alarm counter 3, and the memorized contents in said counter 3 is not reset. Further, a pulse signal having a phase opposite to that of the clock pulse of said oscillating dividing circuit 7 is applied to AND-gate 23, and said AND-gate 23 becomes ON when and the contents of the pulse is &#34;1,&#34;  said time counter 1 and the counter 3 are compared via said OR-gate 22. 
     The output signal is generated from said coincidence circuit 2 when the contents of said counter 3 and time counter 1 coincide, whereby said alarm device 5 is operated. The signal level &#34;1&#34; from said inverter 25 and the signal level &#34;1&#34; of said coinciding circuit 2 are applied to said AND-gate 24 whereby the output of said AND-gate becomes &#34;1&#34;,  and is the reset signal applied to said counter 3. 
     Further, FIG. 3, shows the detailed circuit structure of the channel selecting and alarm time setting circuits. 
     Said circuit is composed of said time counter 1, SW 1  for selecting said single alarm counter 3 and repeat alarm counter 4, and SW 2  and SW 3  for amending or setting the time of each of the counters 3 and 4. The pulse generating circuits 10A, 10B and 10C for generating the pulse signal when said switches SW 1 , SW 2  and SW 3  are closed are connected to said switches SW 1 , SW 2  and SW 3  for amending or setting the time of said counters 3 and 4. 
     The registers 11 and 12 are respectively connected to said pulse generating circuits 10A and 10B, and said registers 11 and 12 are said pulse generating circuit 10c and respectively connected to the transmission-gates 13-17. 
     Referring now to the operation of the circuit construction in FIG. 3, the pulse signal from Q 1  of said register 11 is &#34;1&#34; when said time counter 1 is selected by the channel selecting operation, and the transmission gates 13 and 15 corresponding to the hour and minute counters 1a and 1b of said time counter 1 become ON. When the channel selecting switch SW 1  is operated to the ON-position, a pulse signal is generated from said pulse generating circuit 10A, and the memorized contents of said register 11 is shifted by said pulse signal whereby the output Q 1  becomes &#34;1.&#34; Said transmission gates 13 and 15 are respectively connected to the transmission-gates 16 and 17, and at this time Q 3  is &#34;0.&#34; The transmission-gate 16 is connected to the hour counter 3A of said single alarm counter 3, and the transmission-gate 17 is connected to the minute counter 3B of said counter 3. 
     When the figure selecting switch SW 2  selects the hour, the output Q 4  of said register 12 is &#34;1,&#34; and said transmission-gate 14 is connected to said transmission-gate 13. Said transmission-gate 13 is connected to said transmission-gate 16 whereby said hour counter 3A of said single alarm counter 3 is set by the setting switch SW 3  via said transmission-gates 13, 14 and 16. 
     When said figure selecting switch SW 2  is pushed, the output Q 4  of said register 12 becomes 0, and said transmission gate 14 is connected to said transmission-gate 15. Further said transmission-gate 15 is connected to said transmission-gate 17 whereby the minute counter 3B of said single alarm counter 3 is selected, and the contents of said minute counter 3B is set by said setting switch SW 3 . 
     When said channel selecting switch SW 1  is operated, the output Q 1  becomes &#34;0,&#34; the output Q 3  becomes &#34;1&#34; whereby said transmission gate selects said repeat alarm counter 4, and the minute and hour of contents said repeat alarm counter 4 are set in the same ways as those of said single alarm counter 3. Therefore, it is possible to respectively set the alarm time for said single and repeat alarm counters 3 and 4.