Balanced-to-single-ended signal converters
The present invention relates to balanced-to-single-ended signal converters (BSESC&#39;s) suitable for construction in monolithic integrated circuit form. 
     Integrated BSESC&#39;s often take the form of current mirror amplifiers (CMA&#39;s) with minus unity current gain. These CMA&#39;s typically comprise matched master and slave current mirroring transistors of bipolar type. The master transistor is provided with direct coupled collector-to-base feedback to adjust its emitter-to-base potential for conditioning its collector-to-emitter path to conduct essentially all of an inverting-input current. The emitter-to-base potential of the master mirroring transistor is applied as the emitter-to-base potential of the slave mirroring transistor to condition its collector-to-emitter path to demand a current similar to the inverting-input current, which demand is subtracted from a non-inverting-input current to yield a single-ended output current. The common-mode signal rejection of the balanced-to-single-ended signal conversion relies upon the matching of the collector current versus emitter-to-base voltage characteristics of the master and slave mirroring transistors. 
     Unfortunately, this matching is sharply affected by differences in the temperatures of the mirroring transistors. For one degree Kelvin (1° C.) of difference between their emitter-base junction operating temperatures, the collector currents of matched silicon mirroring transistors will differ by 8 to 9%, if their base-emitter potentials are made equal. In monolithic integrated circuits experiencing steep on-chip thermal gradients, such as circuits having output stages delivering watts of power, such differences in operating temperature between adjacent transistors are likely to occur. Further, because the thermal gradients change appreciably at audio frequency rates in many integrated circuits, it is difficult or impossible to overcome mismatch, caused by temperature differences between the transistors, by introducing a compensating mismatch by other means--e.g., by scaling their respective effective emitter-base junction areas. 
     For one Kelvin of difference between their emitter-base junction operating temperatures the collector currents of matched silicon mirroring transistors will differ only 0.7%, if their base currents are made equal. This suggested to the present inventor the desirability of using BSESC&#39;s relying solely on the matching of the comon-emitter forward current gains (h fe  &#39;s) of a pair of transistors in place of CMA&#39;s in balanced-to-single-ended conversion applications. 
     A BSESC constructed in accordance with the present invention includes a pair of transistors of the same conductivity type responsive to balanced signals applied to their respective base electrodes to provide a single-ended signal at the interconnection of their serially connected collector-to-emitter paths. 
    
    
     In the drawing: 
     FIG. 1 is a block schematic diagram of a conventional power operational amplifier; and 
     each of FIGS. 2, 3, 4 and 5 is a schematic diagram of a balanced-to-single-ended signal converter constructed in accordance with the present invention; 
     each of FIGS. 6 and 7 is a schematic diagram of a differential amplifier and bias circuit particularly well suited for operation with a balanced-to-single-ended signal converter as shown in FIG. 2 in furtherance of the present invention, and 
     each of FIGS. 8 and 9 is a schematic diagram of a current supply suitable for use in the bias circuit of FIG. 6 or 7. 
    
    
     The power operational amplifier of FIG. 1, enclosed within a dashed-line rectangle symbolic of its being constructed within the confines of a monolithic integrated circuit, has non-inverting and inverting input terminals OP AMP IN and OP AMP IN for applying signals to an initial differential amplifier stage DAS. The balanced output currents from this differential amplifier stage are supplied to a balanced-to-single-ended signal converter BSESC for conversion to single-ended form. This single-ended signal is applied to an intermediate amplifier stage IAS which includes means for establishing the dominant 6 dB per octave roll-off in open-loop frequency response typical of an operational amplifier. This means is shown in FIG. 1 as comprising an on-chip Miller integrating capacitor C, although an off-chip capacitor may be used instead and the integration may be done in other ways. The amplified and rolled-off signal from intermediate amplifier stage IAS is applied as input signal to an output, or power, amplifier stage OAS which responds to supply the amplified output signal appearing at the output terminal OP AMP OUT of the operational amplifier. 
     In operation, the output terminal OP AMP OUT of the operational amplifier is normally direct-coupled to its inverting input terminal OP AMP IN via a feedback network FBN, as shown in FIG. 1, to complete an overall degenerative feedback loop to arrange for the voltage at terminal OP AMP OUT to have a prescribed value (usually midway between relatively positive and relatively negative operating potentials) when the input voltages at terminals IN and IN are alike. This overall feedback establishes quiescent operating conditions on all stages of the amplifier; and, assuming the intermediate amplifier stage IAS to include a transconductive or voltage amplifying device, establishes a quiescent potential across the input circuit of that stage and, thus, across the BSESC output circuit. As noted above, in the prior art a current mirror amplifier with minus unity current gain is usually used for the balanced-to-single-ended signal converter BSESC. 
     FIG. 2 shows a BSESC having first and second input connections IN1 and IN2 for receiving respective balanced input signals--e.g., from a preceding differential amplifier stage--that are applied as base currents to NPN transistors Q1 and Q2, respectively. The emitter of Q2 is connected via a common terminal COM to a point of reference potential, shown here as ground, which reference potential is normally the relatively negative operating supply potential for the operational amplifier. In cases where the operational amplifier is not operated with a single supply but with positive and negative operating voltage supplies, this reference potential would normally be the negative operating voltage. Q1 and Q2 have similar common emitter forward current gains h feNPN , and their collector-to-emitter paths are serially connected between the common terminal COM and a bias terminal BIAS to receive a bias potential, as will be more particularly described below. The interconnection of their collector-to-emitter paths connects to the output terminal OUT of the BSESC. 
     Common-emitter amplifier transistor Q3 is an NPN transistor in the intermediate amplifier stage IAS receiving an operating voltage at its collector electrode and being arranged to work into a collector load LM to develop the amplified and rolled-off signal to be applied to the output amplifier stage OAS. (In FIGS. 2-5 the resistor LM and B+ voltage represent the collector load and operating voltage, respectively. Another type of collector load--e.g., a constant current generator--may be used instead.) The overall feedback of the operational amplifier will regulate the emitter-to-base potential V BEQ3  of Q3 to a quiescent value that establishes the potential at terminal OUT. This potential is quiescent emitter-to-collector potential V CEQ2  of Q2. 
     Particularly in critical applications, it is desirable that Q2 have a quiescent emitter-to-collector potential V CEQ1  that is substantially equal to V CEQ2 , so that the self-heating of Q2 is the same as the self-heating of Q1. This is in line with the desire to keep the operating potentials of Q1 and Q2 as nearly alike as possible. So, it is preferred to use a bias supply VS1 applying a potential 2V BEQ3  between terminals COM and BIAS. This provides Q1 a collector potential that conditions it to operate in the normal mode of transistor operation. Q2 is conditioned to operate in the normal mode of transistor operation by V BEQ3  being applied to its collector electrode. 
     Responsive to input current flow therethrough, terminal IN1 will be at a quiescent input potential V IN1  that is equal to V BEQ3  +V BEQ1 , V BEQ1  being the offset potential across the emitter-base junction of Q1. It is desirable to make the quiescent input potential V IN2  at terminal IN2 substantially equal to V IN1  so as to present the same voltages to each half of the differential amplifier stage DAS. This matches the portions of their output current versus input voltage characteristics that the transistors in each half of this earlier stage operate on, and so reduces input offset voltage error--i.e., the static difference in potential between terminals OP AMP IN and OP AMP IN of the operational amplifier. Accordingly, an NPN transistor Q4 self-biased by collector-to-base connection to form a diode means DM1 is inserted between terminal IN2 and the base of Q2, poled for simultaneous conduction with the base-emitter junction of Q2. The respective emitter-to-base potentials V BEQ2  and V BEQ4  of Q2 and Q4 sum to make V IN2  equal to V BEQ2  +V BEQ4 , which substantially equals V BEQ3  +V.sub. BEQ1. 
     There may be an undesirable residual unbalance between the emitter current of Q1 and the collector current of Q2, that is not exactly that required by Q3 as quiescent base current to maintain its quiescent collector current at nominal value. If no way were provided to offset this residual unbalance, the overall feedback of the operational amplifier would correct it, undesirably providing an input offset error between its input terminals OP AMP IN and OP AMP IN. A potentiometer P with end connections to terminals COM and BIAS and an adjustable tap connection connected via the relatively-high-resistance resistor R to terminal OUT provides for correcting this residual unbalance while nulling the input offset error. 
     During operation of the FIG. 2 BSESC, increase of the current supplied to terminal IN1 and decrease of the current supplied to terminal IN2 will increase the conduction of Q1 vis-a-vis the conduction of Q2. The emitter current of Q1 increases respective to the collector current of Q2, increasing the base current drive to Q3. On the other hand, increase of the current supplied to terminal IN2 and decrease of the current supplied to IN1 will increase the conduction of Q2 vis-a-vis that of Q1. The collector current of Q1 will increase respective to the emitter current of Q2, decreasing the base current drive to Q3--indeed, shutting it off entirely and charging capacitor C under fast-slewing conditions. 
     It is worthy to note that while a current mirror amplifier used as a BSESC offers no current gain, the FIG. 2 BSESC offers a current gain of h feNPN . For normal integrated circuit NPN&#39;s this current gain is from 30 to 100 times. Further, since the transistors Q1 and Q2 operate with emitter-to-collector voltages of only a V BE  there exists the possibility of making them super-beta types in which h feNPN  ranges up to 1000 or so. 
     FIG. 3 shows how the BSESC is modified when the current gain of Q3 is increased by preceding it in a direct-coupled cascade connection--e.g., the Darlington cascade connection--with another NPN transistor Q5. The quiescent potential at terminal OUT is regulated by the overall feedback of the operational amplifier to V BEQ3  +V BEQ5 , where V BEQ5  is the quiescent emitter-to-base potential of Q5. Bias supply VS1 applying a +2V BE  potential to terminal BIAS is replaced by bias supply VS2 applying a +4V BE  potential to terminal BIAS. This is done to make V CEQ1  substantially the same as V CEQ2 , so the self-heating of Q1 is substantially the same as the self-heating of Q2. Terminal IN1 is at a quiescent potential of V BEQ3  +V BEQ5  +V BEQ1 . The quiescent potential at terminal IN2 is made to be substantially equal to this +3V BE  potential by replacing diode means DM1 with diode means DM2 providing a +2V BE  offset between the base of Q2 and terminal IN 2. Diode means DM 2 includes, besides diode-connected NPN transistor Q4, another diode-connected NPN transistor Q6 in series connection therewith. 
     FIG. 4 shows the BSESC of FIG. 2 may be used to drive a common-base amplifier NPN transistor Q7. Analogously, FIG. 5 shows how the BSESC of FIG. 3 may be used to drive a Darlington connection of NPN transistors Q7 and Q8 at the emitter of Q7. These connections are less favored. Not only does one lose the current gains of the transistors driven by the BSESC. One must use potentiometer P to adjust for the appreciable emitter current of Q7, since that emitter current flows in a direction opposite to the flow of the natural excess of the quiescent emitter current I EQ1  of Q1 over the quiescent collector current I CQ2  of Q2. This comes about because of the common-collector forward current gains of transistors being larger by unity than their common-emitter forward current gains. Of course, this may be compensated for by constant current generator means being connected between the terminal COM and the emitter of Q7, although this refinement is not shown in FIGS. 4 and 5. 
     FIG. 6 shows a form the differential amplifier stage DAS preceding the BSESC of FIG. 2 may take. PNP transistors Q11 and Q12 are connected in long-tailed pair configuration, the interconnection of their emitter electrodes receiving tail current I T  from the output circuit of a current mirror amplifier CMA1. The base electrodes of Q11 and Q12 are at the OP AMP IN and OP AMP IN terminals, respectively, and their collector electrodes connect to separate ones of the IN1 and IN2 input connections of the FIG. 2 BSESC. The current mirror amplifier CMA1 has its input circuit connected to a current supply IS1 of a type that withdraws a current I S  proportional to the quiescent collector current I CQ3  of Q3 (shown in FIG. 2) divided by h feNPN . By choosing the constant of proportionality and the current gain of current-mirror amplifier CMA1 appropriately, the natural excess of I EQ1  over I CQ2  will tend to satisfy exactly the base current requirement of Q3. 
     FIG. 7 shows another operational amplifier input stage also suited to conditioning the FIG. 2 BSESC for tending to satisfy exactly the base current requirement of Q3. NPN emitter-follower transistors Q21 and Q22 couple terminals OP AMP IN and OP AMP IN to the emitters of plural-collector PNP transistors Q23 and Q24, respectively. First ones of the collector electrodes of Q23 and Q24 connect to separate ones of the input connections IN1 and IN2 of the FIG. 2 BSESC; second ones of the collector electrodes of Q23 and Q24 connect to their respective base electrodes, connecting Q23 and Q24 as respective current mirror amplifiers. A current supply IS2 demands a current I S  proportional to I CQ3  /h feNPN , which demand is satisfied in equal measures from the interconnected input circuits of these current mirror amplifiers. The output circuits of these current mirror amplifiers between the emitter and first collector electrodes of Q23 and Q24 supply similar quiescent currents, each proportional to I CQ3  /h feNPN  to the input connections IN1 and IN2 of the FIG. 2 BSESC. 
     FIG. 8 shows one type of apparatus for generating I CQ3  to provide a constant current generator collector load for Q3, and an I S  proportional to I CQ3  /h feNPN . A current mirror amplifier CMA2 supplies I CQ3  from its output circuit responsive to a current I R  withdrawn from its input circuit. In FIG. 8 I R  is equal to the collector current demand I CQ31  of an NPN transistor Q31. It and NPN transistor Q32 receive the same base bias voltage--e.g., 2V BE  -- and have similar emitter potentials by virtue of their respective emitter-follower actions. Q31 and Q32 are provided with respective emitter degeneration resistors R31 and R32, and their respective emitter currents will be in the same ratio as the conductances of their respective emitter degeneration resistors, in accordance with Ohm&#39;s Law. Thus, too, their collector currents I CQ31  and I CQ32 , assuming their base currents to be negligible, in accordance with Kirchoff&#39;s Law of Currents. I CQ32 , which then is proportional to I R  and thus to I CQ3 , is withdrawn as emitter current from NPN transistor Q 33 , causing a base current flowing as I S  that is (h feNPN   +1 ) times smaller. This closely approximates an I S  that is proportional to I CQ3  /h feNPN  since h feNPN  is normally many times greater than unity. 
     FIG. 9 shows another type of apparatus for generating I CQ3  and I S . NPN transistor Q41 is provided direct coupled collector-to-base feedback via diode-connected NPN transistor Q42 in its collector current path and the emitter-follower action of an NPN transistor Q43 that conducts its base current. This feedback constrains the potential at the end of resistor 41, connected to point X in the collector circuit of Q41, to which the base of Q43 also connects, to be equal to V BEQ41  +V BEQ43 , the sum of the respective emitter-to-base offset potentials of Q41 and Q43. I R  will flow in accordance with Ohm&#39;s Law through R41 which connects the input circuit of CMA2 to point X, and thence in largest part through diode-connected Q42 to the collector of Q41 to flow as the collector current I CQ41  of Q41. I CQ41 , being substantially equal to I R , will thus be proportional to I CQ3  ; and the base current I BQ41 , being equal to I CQ41  /h feNPN , will be proportional to I CQ3  /h feNPN . This base current gives rise by the common-base-amplifier action of Q43 to an I S  substantially equal to itself and thus proportional to I CQ3  /h feNPN . The diode-connected Q42 reduces the emitter-to-collector voltage of Q42 to substantially equal its emitter-to-base voltage, permitting Q41 to be of super-beta type together with Q1 and Q2. 
     One skilled in the art and armed with the foregoing disclosure will be able to generate other embodiments of the present invention, and this should be borne in mind when construing the scope of the following claims. Constant current generating means are current generating means supplying currents at sufficiently high source impedance, that the values of these currents, are substantially unaffected by changes in the impedance of the load they supply or to changes in potential across that load. The generated currents may, however, be changing signal currents, as, for example, the collector currents supplied by Q11 and Q12 in FIG. 6.