Electronic data processing system for real time data processing
BACKGROUND OF THE INVENTION 
     This application is a continuation-in-part of Ser. No. 603,213 filed Aug. 8, 1075, now abandoned, which is incorporated by reference in its entirety. 
    
    
     The invention relates to an electronic date processing system (EDP-system) specially designed for real time data processing and for limiting the effect of apparatus and programming faults, i.e. for improving reliability, and particularly for the control and regulation of technical processes. 
     In the subsequent discussion reference is made to the following publications: 
     (1) Plessmann, K. W.: Prozesssignalelemente. Interfacing of sensors and final control-elements to control computers. Elektro-Anzeiger 1974, No. 5 and No. 9 
     (2) Syrbe, M.: Messen, Steuern, Regeln mit Prozessrechnern. Measuring and Controlling by Means of Control Computers. Akademische Verlagsgesellschaft, Frankfurt (1972), sect. 4.4. 
     (3) Klaus, J.: Programmierbare Vielstellen-Messanlage nach dem Party-Line-System. Programmable Arrangement for Data Acquisition of Many Measuring Points According to the Party-Line-System. Elektronik 1972, No. 10. 
     (4) Halling, H.: Serielles CAMAC-Loop-System mit intelligenten Crate Controllern. Serial CAMAC-Loop-System Comprising Intelligent Crate Controllers. PDV-Entwicklungsnotiz, PDV-E9, P3.1/3, Jul-KfA (1973). 
     (5) Farber, G.: Duplexringleitungssystem mit normierten Schnittstellen. Duplex Ringbus System with Standardized Interfaces. PDV-Entwicklungsnotiz (PDV-E18, P3.2/2, M-PCS/1 (1973). 
     (6) Syrbe, M.: Messen, Steuern, Regeln mit Prozessrechnern. Measuring and Controlling by Means of Control Computers. Akademische Verlagsgesellschaft, Frankfurt (1972), sect. 2 and 3 
     (7) Farber, G.: Dezentralisierte Datenverarbeitungskonzepte mit Hilfe von Mikroprozessoren. Concepts of Decentralizing Data Processing by the Use of Microprocessors. On-line 1973, pp 784-789. 
     In such real time EDP-systems a hardware structure and a distribution of working capacities is needed which, on the one hand, despite a wide physical distribution of the measuring sensors and process actuators, combines low wiring costs with high reliability, and which, on the other hand, possesses approximately the same operating convenience as a high performance central computer. Account must also be taken of the falling tendency of semiconductor equipment costs and of the continued rise in planning, wiring and programming costs. 
     Real time data processing systems are known which comprise a centrally localized computer which is occasionally duplicated for increasing its reliability.sup.(1),(2). All the process sensors and actuators are usually connected star-like via a central cable distributor, an arrangement which involves considerable expenditure for cabling. Sometimes, mostly in the context of laboratory automation, these several components are interconnected by a common &#34;bus&#34; .sup.(3),(4),(5) which means &#34;data transmission line&#34;, an arrangement which does reduce wiring cost, although by reducing reliability and real time processing capability, certainly not improving the same. Also known are so-called hierarchic computer systems, but these incorporate dispositional functions in the system without optimization and include no arrangements relative to the effects above mentioned .sup.(6). In the field of commercial, i.e. non-real-time data processing, data processing systems comprising distribution computer terminals for data input have been proposed.sup.(7). 
     SUMMARY OF THE INVENTION 
     The object of the invention is an electronic data processing system with a hardware structure and operating system which is optimal with respect to wiring costs, reliability and performance. 
     According to the invention, this object is achieved by use of a plurality of distributed, that is spatially separated, simultaneously running real time microcomputer stations which are interconnected by a self-contained high-speed bus in such a way that each component (e.g. each microcomputer station or process input/output device) is accessible by at least two independent paths. The basic structure of the microcomputer stations is so designed by the provision of suitable gates (switches) that operations at reduced capacity can continue when the bus interchange unit or the microcomputer or the process input/output device fails. The minicomputer stations may be used with a main computer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Some embodiments of the invention will now be described by way of an example with reference to the accompanying drawings, in which: 
     FIG. 1 is a diagram showing the locations of the process sensors and manipulating devices, the microcomputer stations and the main computer by vectors in a coordinate plane; 
     FIG. 2 is a diagram showing the intermediate step of the minimization of the length of the cables by way of calculation and indicates the frequency distribution of the sensors and actuators over the locating coordinate x; 
     FIG. 3 is a diagram showing the result of the length minimization of the cables by way of calculation; it shows the optimal total cable length S as a function of the number of the microcomputer stations m; 
     FIG. 4 shows a decentralized structure model with several microcomputers connected to a ring bus; 
     FIG. 5 shows a decentralized structure model with several microcomputers connected to a common branch line; 
     FIG. 6 shows a concept of the microcomputer station with a switching system permitting connection of the microcomputer and/or the input/output devices to a serial bus; 
     FIG. 7 illustrates the wiring structures of a process computer system comprising several microcomputer stations connected by a ring bus; 
     FIGS. 8 and 9 are two possible functional diagrams based on FIG. 7; 
     FIG. 10 is a schematic representation of one method of transmission control; 
     FIGS. 11, 12 and 13 are schematic representations of two modes of centralized communication control; 
     FIG. 14 is a schematic representation of a circuit arrangement for a receiving/transmitting module; and 
     FIG. 15 is a graphical representation of transmission probabilities. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The geometric layout of the wiring system is to be optimized by way of calculation. The ring structure of the bus is chosen because this is the simplest way of interconnecting the microcomputer stations through at least two independent paths. 
     In order to achieve the desired properties, the spatial distribution of the microcomputer stations in the area of the process sensors and actuators is to be so arranged that the sum of all the cable lengths is a minimum and very much shorter than in the case of a central computer with star-type cabling, depending upon the number of microcomputer stations. Sensors are devices measuring analog or digital signals or, more generally, primary elements of the technical process to be controlled. Actuators, e.g., manipulating devices or manipulators, serve components positioning elements or, are provided as, final controlling elements of the technical process to be controlled. The necessary decisions are subject to qualifying conditions, such as the association of locally distributed microcomputer stations allocated to subsidiary processes, for instance, in locations unsuitable for microcomputer stations or for cables taken through cable duct runs. For large scale processes, the assumption is justified that these qualifying conditions will not significantly affect the optimum number and the optimal locations of the microcomputer stations so that optimal conditions, worked out without taking account of such qualifications, may still serve as useful starting points for further planning. 
     In FIG. 1 the locations of the process sensors 1 and actuators 2, the microcomputer stations 3 and the main computer 4 are represented by their vectors s in an x, y coordinate plane. The total line length S when there are m microcomputer stations and n.sub.μ sensors and manipulators connected to the μth microcomputer station can then be calculated from ##EQU1## where ##EQU2##  is the total number of sensors and manipulators μ s .sbsb.v is the positional vector of the vth sensor and manipulator in the area of the μth microcomputer station. 
     sμ is the positional vector of the μth microcomputer station. 
     s o  is the positional vector of the main computer. 
     S depends upon m, s.sub.μ, and is always related to the given s v . The first term contains the cable lengths connecting the sensors and actuators to the microcomputer stations, whereas the two other generally very much smaller terms contain the ring bus. Analytically, the minimum for this expression cannot be calculated. The problem is similar to the &#34;round trip problem&#34; in operations research. It should therefore be considered as a multistage decision process solved by dynamic programming. For this purpose, a quadratic suboptimization trial quantity S of distance without the second terms is selected and the result corrected by variance, as an intermediate step. For the sake of simplicity the solution will be given in unidimensional form, 
     1st Step: ##EQU3## The intermediate step is shown in FIG. 2 which indicates the frequency distribution of the sensors and manipulating devices over the locating coordinate x. The quadratic distance measure displaces x o  in the direction towards remote x v . This shift is compensated by a stepwise approach of the next center of density when checking the variation of S 1  →S 1  (gradient method). 
     2nd Step: The number of sensors and actuators is divided at x o , which means ##EQU4## 
     The intermediate step is provided as above, followed by further steps, discontinued when a predetermined limit |S i-1  -S i  | has been reached. 
     The result regarding S is shown in FIG. 3 as the optimal total cable length S as a function of the number of microcomputer stations m. In a final step, the total cost K is numerically minimized with S(m), 
     
         K=S·K.sub.s +m·k.sub.MK ≐min      (8) 
    
     where 
     k s  . . . cost of cable per unit of length 
     k MK  . . . cost per microcomputer station 
     DISTRIBUTION OF TASKS BETWEEN THE DISTRIBUTED PROCESSORS 
     When a programming system is highly segmented a favorable distribution of tasks between the different computers (microcomputers and main computer), can be achieved in a multiple computer system. Tasks in the field of problem solving which do not exceed the available storage capability of a microcomputer station can be handled by that station without causing flow of data through the bus to grow excessively. The complete technical process is subdivided into a plurality of technical subprocesses. This plurality of subprocesses and their dependencies are mapped onto the plurality of microcomputer stations and the communication between them. Thus the complete technical process can be controlled. The following Table gives a plausible distribution of tasks in a process computer system of decentralized structure according to FIG. 4: 
     
                       TABLE 1                                                     
______________________________________                                    
Distribution of tasks in a process computer system                        
of decentralized structure according to FIG. 4.                           
Tasks     Stations        in Computer                                     
______________________________________                                    
Data acquisition                                                          
          Signal input    Storage of all data                             
          Smoothing       files                                           
          Plausibility control                                            
                          process model updating                          
          Redundancy reduction                                            
                          Standardization of                              
                          digital range, to                               
                          console input-output                            
Control   Holding circuit Adaptive Control                                
          (interpolation) Optimization                                    
          Monitoring (highest                                             
                          Monitoring (other                               
          priority)       priorities)                                     
          DDC             Material flow monito-                           
          Signal output   ring and balances                               
Back-up   Simple DDC algorithms                                           
                          Tasks of faulty                                 
                          microprocessors                                 
Man-machine                                                               
          Self-test       Display of opera-                               
communication             tive state at cen-                              
Operability               tral control                                    
Maintenance               Fault analysis                                  
                          Test programs                                   
                          Maintenance program                             
                          Program compiling                               
______________________________________                                    
 
    
     According to Table 1 the main computer performs on-line programming (i.e. compiling, linking, down-line loading of the microcomputer stations), test and emergency tasks. 
     DECENTRALIZED STRUCTURE MODEL WITH DISTRIBUTED MICROCOMPUTERS 
     The invention will now be more particularly described with reference to FIGS. 4 to 12. FIG. 4 shows several microcomputer stations 5, a main computer 6 with standard peripherals 7. In FIG. 4 the main computer and the microcomputer stations are interconnected by interchange switching units (KW) 8 and a ring bus 9. The microcomputer stations are each equipped with a microprocessor (MK) 10, input/output devices (E/A) 11 and an internal working storage (ASP) 12. They perform direct digital control (DDC) algorithms, signal processing and back-up tasks as well as man machine communication tasks. Several operating states must be distinguished, some of which are: microcomputer inoperable, process I/O inoperable, interchange switching unit inoperable. Depending on these operating states, the microcomputer station is operating, for instance, isolated from the bus line or the process I/O is controlled externally by another computer (microcomputer or main computer) by means of the communication through the ring bus. If the bus has a ring structure, each computer in this multiple computer system can communicate with every other computer through two paths. The microcomputer stations each perform the tasks mentioned above. The ring bus reduces the failure probability of the bus system by nearly the square although the cost of the ring bus is usually only slightly above that of the branch. 
     Furthermore a structure with a common branch line 14 to the main computer (HR) 13 is possible (FIG. 5). 
     BUS AND DATA COMMUNICATION 
     Although a reduction in the amount of data is achieved by preliminary processing in the microcomputer stations, a high transfer rate through the bus is to be expected when there is a fault and also when the system is starting up. This maximum flow of information determines the necessary channel capacity. In principle, a decision can be made as to whether a parallel or serial transfer system on the bus is to be used. Combination solutions are also feasible. 
     A conventional parallel bus is capable of handling a transfer rate of about 1 megabaud over a distance of, for instance, 1 km. Significant increases of this transfer rate (for instance by one order of magnitude) are not to be expected because the different group delay distortions on the parallel lines cannot be controlled without considerable extra expense. The differences in delay times are due to inhomogeneities along the length of the path. 
     Serial busses working with two wire transmission lines in the form of coaxial cables or with optical fiber cables are at present already capable of achieving bit rates of about 20 megabaud over distances of several hundred meters. Intermediate amplification and slight reduction of throughput enable distances of several kilometers to be successfully bridged. Other increases in transfer speeds, for instance by as much as an order of magnitude, will be possible in the near future if the present rate of component development continues. 
     Among the several illustrated structures, that shown in FIG. 4 has a particularly low failure probability. If one of the microcomputers (MK) fails, then its tasks should be capable of being performed by another computer. These requirements dictate the structure of the interchange switching system. 
     FIG. 6 is one concept of such an interchange switching system 17 which permits connection to be made to a high-speed serial bus. 
     When, in this concept, an interchange switching system sends a call to the bus all the other interchange switching systems are set to address-receiving state by their station controller 18. In those interchange switching systems which recognize their own station code by the address check unit 21, the receiving state is maintained, the input gate 19 remains open and gate A 20 is closed. The input gates of those interchange switching stations which have not been called reclose. In the following shift register 22, the necessary serial to parallel conversion of the received information takes place. Gate B 23 conveys instructions, data and addresses to the microcomputer 24. Instructions may also be conveyed to the station controller. The microcomputer will then control the input/output operations by gate C 26. However, if the microcomputer has failed, then the information bypasses it by means of gate B and gate C directly to the input/output devices 27. During transmission, the shift register carries out the parallel-to-serial conversion. The input gates which were open during transmission are closed by a code end signal. The ring bus 25 is opened at one point during operation for physical reasons. Depending upon the failure situation, transmission may be in only one direction or in both directions. Faults in the bus must be isolated from the neighboring stations. Faults due to reflexions in the case of electrical transmission lines at the open bus ends can be disregarded for slow transfer rates but for higher transfer rates they must be terminated by the wave resistance 28 of the ring bus. In order to provide the correct states of termination, the system must be continuously informed of the nature of the fault and its location. For this purpose each interchange switching unit sends test messages in the event of a transmission failure detected either by a time-out circuit or by a check word failure. By means of these test messages, the operability of all bus line segments, each of which connects two neighboring stations, is tested; and the bus line status is determined and reported to all stations still connected together. 
     RELIABILITY AND MAINTAINABILITY 
     The inherent reliability of a process computer system depends substantially upon the probability of failure of the several components, of data transfer through the channels, the possiblities of limiting errors by the programming system, the erro-freedom of the programs themselves and the reliability of man-machine communication. 
     It is now proposed to use the independent, though small, computing capacity of the microcomputers to achieve the desired reduction in the effect of faults without the provision of a special back-up system. For this purpose, DDC algorithms are provided in all microcomputers as well as smoothing, plausibility check, redundancy reduction algorithms and emergency programs. Redundancy reduction is performed by a hardware and/or software unit in each station. This unit receives all input signals from the technical subprocess associated with a computer station and recognizes significant changes of at least those process signals which cause data transfers through the bus line system. By virtue of this unit, the data transfer rate through the bus line system is minimized. These program modules are kept available in the main computer, too. Fault reports based on concurrent self-checking processes trigger emergency steps in microcomputer stations or in the main computer if necessary as described in more detail below. Smoothing is the well known method of low-pass filtering (analog or digital) of process signals. Plausibility check performs a check of e.g. the range of values of the measured process signals. Redundancy reduction avoids recording of redundant values of the process signals. Fault reports are generated by the station controllers 18 (FIG. 6) and layed down in status words in each station. 
     A status word contains bits indicating 
     the activities of the internal information paths of the station--e.g. time-out signal and address or data error 
     the operability of power supply 
     the periodical resetting of a time-out circuit by program 
     the activity on the ring bus derived from a time out signal or from a check word 
     the correct real time control of a test control loop connected to the input-output devices of the station. 
     A status word like this exists in the station controller which generates status reporting messages to each other station for triggering external control by another computer of the system and which causes an adequate switching state of the gates 19, 20, 23 and 26 contained in the interchange switching unit. The gates are controlled by the station controller in accordance with the transmitting or receiving activity on the ring bus respectively of said status word: 
     In case of failure of the computer 24, consisting of a processing unit 10 and a working storage 12, the computer 24 is disconnected by means of the gates 23 amd 26, and another computer station of the system being triggered in said manner supplies the input/output devices 11 by means of messages conveyed by the ring bus and the gates 19 and 23. 
     In case of failure of the interchange unit 8 or the ring bus 9, gate 23 is closed, the exchange of messages with other computer stations is suspended and the computer 24 supplies the input/output devices 11 in an isolated manner. 
     FIG. 7 illustrates the wiring structure of a process computer system comprising several microcomputer stations 32 connected by a ring bus 34 to the main computer 33. The entire flow of data in this ring bus in monitored and controlled by a priority unit (VRW) 35. The priority unit (VRW) coordinates the communication between the processor stations which takes place by messages to be sent on the bus line system by the source station and to be taken from the bus line by the destination station. This priority unit may be built up centralized or decentralized by hardward or by programs running in every computer station particularly in their interchange switching system (KW) 31. This ensures that only one computer is on the bus at any one time. Steps which serve for improving reliability are indicated in chain lines. 
     Based on FIG. 7, two possible functional diagrams are illustratively shown in FIGS. 8 and 9. 
     In FIG. 8, the ring bus structure and the microcomputers provide redundancy areas. If the two possible transfer paths between two computers on a ring line are to provide a quadratic reduction of the failure probability of the line system, then steps must be taken to ensure that the failure probabilities of the two separate paths are completely independent. The two paths leading to a microcomputer must therefore be contained in different cable duct runs. The task distribution has been so chosen that central coordination tasks proceed only in the main computer 37 and in a central priority controller 38. The main computer can undertake the functions of failed microcomputers 36, but the tasks performed by the main computer can be only partly solved by the microcomputers. Since the functions of the priority controller are needed for any data traffic between the computers, the priority controller is shown in this functional block diagram incorporated between the interchange switching unit 39 and the two branches of the ring bus 40. The non-redundant parts, such as the priority controller, interchange switching units and input/output devices 41 of the stations can be of very reliable design, particularly since the development of computer technology leads to the expectation that in the next few years the mean fault intervals in standardized switching units will lengthen substantially. If, therefore, the requirements which the system reliability is to fulfill are not set too high, the provision of an independent back-up system can be dispensed with. 
     In FIG. 9 the tasks distributed between the main computer 42 and the microcomputers 43 are evenly weighted. Consequently, functionable computers can undertake the tasks of a faulty computer. The priority controller 44 for the bus is duplicated. Furthermore, connections 47 between neighboring microcomputer stations are provided in such a way that each microcomputer can also operate the sensors 46 and actuators 45 associated with one of its neighbors. The expenditure which is involved in realizing these steps is substantially lower than that involved in the provision of an additional back-up system. Nevertheless, the system efficiency, when there are partial breakdowns, is exceptionally high. 
     The introduction of parallel redundancy permits system modules to be replaced or maintained while the system remains in operation. Consequently, after repair or replacement of a module the system will completely reincorporate this module in its operations without any further action on the part of the operator being required. 
     By the employment of highly integrated semiconductor circuitry (LSI), particularly of microcomputers, a structure in self-contained boxes (e.g. casting) is possible. Another simplification arises by a power supply through the bus line. The current needed by the computer stations may be fed in a decentralized manner into a part of the bus line especially constructed as a power supply bus. Each station feeds into this power supply bus and branches that portion needed by the station. Thus, the amount of the current to be fed in at each station can be dimensioned according to the structure of the distribution system of the distributed computer stations. 
     Particularly rapid bus lines which are free from electromagnetic interference are achieved by using optical fiber cables. The supply of current through such a bus is possible, for instance, by making use of the metal sheath. 
     A further improvement in reliability is secured by a variable or distributed allocation of bus line control. For instance, the operative station having the lowest code number transmits time slices of predetermined priority which are seized in the order of their code number or position in the ring by the stations which have messages of this priority to transmit. If no time slices arrived within the allocated time the station having the next higher code number automatically takes over this function. 
     In the following, two possible methods of transmission control are outlined as examples. 
     The first method is called &#34;serial transmission with central control&#34;. It is based on the existence of one single transmission controller at a time by means of a corresponding program module. Each station surveys the intervals between messages, each time counter being proportionally adjusted to the ordinal number of the station concerned. In case the station with the lowest address fails, the succeeding station (next time counter value) activates its program module. In case of line interruption the activation is automatically shifted to the station next to the interruption. At the end of an additional and longer time interval that station initiates a different mode of transmission: &#34;oscillating mode of transmission&#34; (FIG. 10). 
     The master station transmits dummy messages containing priorities. The first station requesting to transmit replaces the dummy message by full message containing a destination/address. all the stations fowarding a full message can set the semaphores and hereby signal their request of transmission to the master station on the quickest way possible. The latter transmits dummy messages of the requested priority as long as all requests are served. 
     The reliability and security of the system is basically not affected by the omission of messages of acknowledgement, as described in a different paper. 
     However, the method described above requires a special message of acknowledgement to the master station. It signals the end of each activity of communication (FIGS. 11, 12). Otherwise a buffer storage has to be provided in each station in case of replacing a dummy message by a full message and simultaneously receiving a subsequent full message to be forwarded. 
     The second method is called &#34;simultaneous transmission with individual control&#34;. It is based on the existence of transmission controllers in each station. The observer station, as soon as the signal of the end of a message being forwarded has passed and no signal of the start of a new message has arrived at the receiver, may transmit a message of its own (FIG. 13). Priorities do not exist. The messages are of variable length. The longest message provided comprises a maximum of 1,200 bits including the complete header and the check code, and lasts up to 120 μs at a transmission rate of 10 Mbit/s. 
     This method allows the transmission of several simultaneous messages, unless busy segments of the ring bus overlap. However, a buffer storage has to be provided in each station in order to avoid the collision of messages in case of overlapping and a transmission of message at the same time (FIG. 14). 
     A line interruption does not require any particular measure for messages containing destination addresses of stations up to the interruption. As to the remaining destination addresses, the &#34;oscillating mode of transmission&#34; is required. Obviously a time counter of long intervals is necessary in each station which effects the alternate activation of either station next to the interruption. 
     QUANTIFICATION OF THE &#34;SERIAL TRANSMISSION WITH CENTRAL CONTROL&#34; 
     The efficiency of this method is determined by the service rate P sj . This is based upon the following suppositions: 
     no varying priorities of messages 
     uniform probability distribution of destination addresses 
     uniform probability distribution of transmission requests. 
     Definitions: 
     n . . . total number of stations 
     j . . . ordinal number of station 
     P . . . probability of transmission request 
     P l1  . . . probability of master station 1 transmitting a dummy message 
     P lj  . . . probability of station j receiving a dummy message 
     P sj  . . . probability of staton j transmitting a full message 
     P u  . . . probability of a full message having a destination/address beyond master station 1. 
     The probability of station j receiving a dummy message decreases with the distance to master station 1: 
     
         station 2: P.sub.12 =P.sub.l1 
    
     
         station 3: P.sub.13 =P.sub.l1 ·(1-p) 
    
     
         station 4: P.sub.14 =P.sub.l1 ·(1-p).sup.2 
    
     
         station j: P.sub.lj =P.sub.l1 ·(1-p).sup.j-2 
    
                                                                (9) 
     The transmission probability results from the compound probability that a transmission request exists and a dummy message arrives. Using Eq. (9) we obtain: 
     
         P.sub.sj =p·P.sub.l1 ·(1-p).sup.j-2      (10) 
    
     The master station 1 transmits dummy messages as long as it does not transmit a full message of its own or has to forward a full message from another station: 
     
         P.sub.l1 =1-p.sub.s1 -P.sub.u                              (11) 
    
     where we write because of the uniform distribution of destination addresses: ##EQU5## The master station 1 itself transmits a full message with the probability P s1  on request of a transmission (p) and if the bus is not busy with a full message being forwarded (1-p u ): 
     
         P.sub.s1 =P·(1-p.sub.u).                          (13) 
    
     From this we may calculate the transmission probability P ll  using the Eq. (11) to (13). ##EQU6## With the help of Eq. (10) we get the transmission probability P sj  of a station j: ##EQU7## The result is particularly dependent on the position of the station j relative to the master station 1. For very small p only, it approximately equals the transmission request probability. ##EQU8## 
     Details are shown in FIG. 15. 
     QUANTIFICATION OF &#34;SIMULTANEOUS TRANSMISSION WITH INDIVIDUAL CONTROL&#34; 
     In addition to the same assumptions as in the preceding paragraph, it is also assumed: 
     P s  . . . probability of a random station transmitting a full message 
     P u  . . . probability of this station receiving a full message that contains a destination/address beyond it and that has to be forwarded. 
     P v  . . . as before, but buffered temporarily and to be forwarded later. 
     The probability that a random station transmits is calculated from the compound probability that a transmission request of its own exists and that no other message has to be fowarded: 
     
         P.sub.s =P(1-P.sub.u -P.sub.v).                            (17) 
    
     In accordance with Eq. (12) it is found: ##EQU9## The probability of being forced to buffer temporarily sults from the compound probability which arises from the coincidence of message forwarding with either message transmission or forwarding the buffer contents: 
     
         P.sub.v =P.sub.u ·(P.sub.s +P.sub.v).             (19) 
    
     From this the following is obtained: ##EQU10## wherefrom: ##EQU11## Here the transmission probability is independent of the position of the station on the ring bus. 
     Again, for very small p it approximately equals the transmission request probability: ##EQU12## 
     Details for 5, and 50 stations are shown in FIG. 15. 
     COMPARISON AND SELECTION OF A METHOD 
     The characteristics of the two methods with regard to the transmission requests of the stations can be pointed out by the following apparent qualifications: 
     &#34;serial transmission with central control&#34; shows a relative maximum of transmission probability at each station depending on average transmission request probability, number of stations, and position of observer station. The transmission probability decreases very fast beyond this maximum; 
     &#34;simultaneous transmission with individual control&#34; shows a monotone increase transmission probability depending on average transmission request probability and number of stations, but, it is independent of the position of the stations. 
     Hereby, the planning to apply the first method will be particularly difficult as exceeding the maximum of the transmission probability has to be avoided and stations with a particularly high transmission request probability have to be arranged as near to the master station 1 as possible. 
     The reliability and performance of the computer system is further increased by dynamic allocation of the several data processing programs to the microcomputers, according to their operability, ascertained by the above described fault detector circuits and programs. The operability of each individual station is regularly checked as described above. These status information are transmitted to the main computer and possibly to all the other stations as well. In dependence thereon, the allocation of tasks, i.e. the allocation of partial programs (activation or loading), can be effected according to the state of the system. This is facilitated by a coordinated addressing control of the entire storage space available in the system. This enables any computer station, simply by means of the message address, to gain direct access to storage facilities which are physically associated with another processor station. 
     The facilities outlined in the preceding paragraph also provide fundamental means for making programming easier and facilitating communication between man and computer system. By extending higher programming languages as well as operational and system components by a station and loading division for describing the station properties and for determination of the reactions desired in case of breakdowns, it is possible to reload the microcomputer stations from a main computer, equipped with standard periphery and possibly lacking a process periphery, to provide programming assistance for the entire system by compiler, linkage editor and loader. Any suitable program can be loaded through the bus into the corresponding computer station dependent on the functional state of the entire system, although the programmer will be formulating the programs in one higher language. 
     The invention may be embodied in other specific forms without departure from the spirit or essential characteristics thereof. The embodiments are therefore to be considered in all respects as illustrative and not restrictive.