Method and apparatus for offset error correction
BACKGROUND OF THE INVENTION 
     Drifting of the null or zero point in various types of transducing or measuring devices used in such applications as weighing scales and signature verification systems is well-known. Such a null or zero reference drift is intolerable in the case of remote unattended installations of such devices and systems as mentioned above, since frequent manual adjustments cannot be made in such remote installations. Various automatic means for compensating such offset errors have been developed, and function, in general, by virture of careful attention to design, utilization of high-grade low-drift components, and suitable inclusion of compensation components exhibiting complementary drift characteristics. Such means generally function entirely within the analog signal domain, are costly and achieve varying degrees of success due to component tolerances. 
     In the case of hybrid computational systems, such as signature verification systems, which embrace both analog and digital signal domains, utilization of available digital components in large part already present in the system offers the opportunity for the provision of accurate, efficient and inexpensive drift compensation means. 
     SUMMARY OF THE INVENTION 
     This invention relates to a method and apparatus for correction of null or zero reference offset error, and more particularly relates to a method and apparatus for correction of null or zero reference offset error resulting from drift of the null point of the output signal of a measuring or transducing device such as, for example, a signature pad utilized in a signature verification system. 
     In accordance with one embodiment of the invention, apparatus for compensating for drift from a null point of a measuring device comprises comparison means for comparing a first signal from said measuring device with a derived second signal and for providing an output signal representative of the difference between said first and second signals; analog-to-digital converter means to which said output signal is applied, for providing a digital equivalent of said output signal; digital-to-analog converter means for providing said second signal to said comparison means; and data processing means coupled to said analog-to-digital converter means and to said digital-to-analog converter means, and operable in an iterative operation to generate a compensating value which, when applied to said digital-to-analog converter means, results in said second signal having a predetermined relationship to said first signal, said compensating value being generated in a plurality of inerations commencing from a predetermined initial value by incrementing said digital-to-analog converter means to change the magnitude of said second signal until said output signal applied to said analog-to-digital converter means by said comparison means attains a predetermined value. 
     In accordance with another embodiment of the invention, a method for compensating for drift from a null point of a measuring device comprises the steps of comparing a measurement output signal from said measuring device with a compensating signal; providing a comparison output signal representative of the difference between said measurement output signal and said compensating signal; comparing said comparison output signal with a previous comparison output signal; modifying the compensating signal by a predetermined amount in the event of a given result of the comparison of the preceeding step; and repeating all of the preceding steps with successive modifications of said compensating signal until said comparison output signal attains a predetermined value. 
     It is accordingly an object of the present invention to provide a method and apparatus for compensating for drift from a null point of a measuring device. 
     Another object is to provide accurate, efficient and inexpensive drift compensation method and means for the signature pad of a signature verification system. 
     An additional object is to provide a drift compensation system comprising an appropriately-programmed microcomputer, an analog-to-digital converter, a digital-to-analog converter and an operational amplifier in a closed feedback correction loop configuration. 
     A further object is to provide a method for drift compensation comprising use of a compensation signal to offset a signal representing drift from a null point, modification of said compensation signal by successive measurements of the difference between the drift signal and the compensation signal, and incrementally modifying said compensation signal after each measurement until a desired difference value of the difference signal is obtained. 
     A further object is to provide diagnostic means for detecting malfunctions of the drift compensation means. 
     With these and other objects, which will become apparent from the following description, in view, the invention includes certain novel features and combinations of parts, a plurality of embodiments of which are hereinafter described with reference to the drawings which accompany and form a part of this specification. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the hardware components of the offset error correction system of the present invention. 
     FIGS. 2A-2F inclusive taken together from a detailed flow diagram showing the operation of the system. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, a system 10 embodying the present invention is shown. In the illustrated embodiment, the drift compensation system is applied to a writing table transducer or signature pad 12 which is utilized to generate a signal or waveform representative of the varying forces applied by a person in writing predetermined data, such as a signature. A plurality of waveforms so generated, representing a corresponding plurality of signatures, are used to produce a reference, which can then be utilized in verification of the authenticity of the identity of the same person in the future by comparison of a similar sample with the reference. One suitable form of the table 12 is shown in co-pending United States Patent Application Ser. No. 889,766, inventor Donald W. Baver et al., filed Mar. 24, 1978, now U.S. Pat. No. 4,143,357, issued Mar. 6, 1979, and assigned to the assignee of the present application. The specific component types and values set forth herein for the various elements of the system are those used in the illustrated embodiment, but other appropriate types and values could be employed if desired. 
     An output signal e s  from the signature pad 12 is applied through a 10,000-ohm resistor 14 and a path 16 to the non-inverting input of an operational amplifier 18, which may be a National Semiconductor type 308. The path 16 is connected to a base reference potential, shown as ground, through a 1-megohm resistor 20. 
     The output of the amplifier 18 is connected over a path 22 to the input of an analog-to-digital converter 24 which may be of type ADC82AG manufactured by Burr-Brown Research Corporation. This is an eight-bit converter, which is connected for a 0 to +10v. input range. It is coupled to an input port 26 of a microcomputer 28, which may be an Intel SBC80/10, and controlled by the microcomputer via lines 29. An output port 30 of the microcomputer 28 is coupled to an eight-bit unipolar digital-to-analog converter 32 which may be a Precision Monolithics type DAC-03BD. The output of the converter 32 is connected through a 100,000-ohm fixed resistor and a 100-ohm variable resistor 36 to a base reference potential, shown as ground. A further path extends from the slide of the variable resistor 36 through a 5,000-ohm variable resistor 38 and an 8,200-ohm fixed resistor 40 to the inverting input of operational amplifier 18. A 1-megohm fixed resistor 42 is connected in a path between the inverting input and the output of operational amplifier 18. 
     It may be seen that the analog voltage output of the digital-to-analog converter 32 is reduced in amplitude by the voltage divider comprising the resistor 34 and the trimmer potentiometer 36. This reduced voltage, designated as e a , is applied through the gainsetting resistors 38 and 40 to the inverting input of the amplifier 18, while the analog output voltage e s  of the signature pad 12 is applied to the non-inverting input of said amplifier. 
     The analog output voltage E o  of the operational amplifier 18 is given approximately by 
     
         E.sub.o =A(e.sub.s --e.sub.a) 
    
     where A represents the amplification factor. 
     For the resistor values cited above for resistors 38, 40 and 42, the amplification factor of the operational amplifier circuit is approximately 100. 
     From the above equation, it will be seen that the voltage E o  can be reduced to zero amplitude by suitable adjustment of the voltage e a , such that e a  is approximately equal to e s . Since the value of the voltage e a  is derived from the output of the digital-to-analog converter 32, which is controlled by the associated microcomputer 28 in a manner which will subsequently be described, means are thus provided for automatic correction of any drift of the voltage e s  away from the ideal &#34;null&#34; state in which it should repose when no writing pressure is applied to said pad. 
     The output voltage e a  of the digital-to-analog converter 32 is reduced to a suitable level by the previously-mentioned voltage divider comprising the resistor 34 and the trimmer potentiometer 36. The setting of this potentiometer establishes the &#34;step resolution&#34; value of the adjustment voltage e a  ; that is, the actual change in voltage e a  which is produced by a single unit of incremental change in the digital value applied to the converter 32 by the microcomputer 28 through the output port 30. This setting represents a compromise between fineness of null adjustment and magnitude of the maximum drift of the signature pad 12 which can be corrected by the system, and thus sets a limit on the adjustment range. 
     The trimmer potentiometer 36 is initially adjusted such that E o  varies approximately four millivolts for each incremental change of the digital data word applied to the input of the digital-to-analog converter 32. For this adjustment setting, the maximum, range of adjustment of E o  is slightly in excess of 1 volt as the digital data word which is applied by the microcomputer 28 through the output port 30 to the digital-to-analog converter 32 is varied from 0 to its maximum value which, for an eight-bit word, is 255 decimal or FF hexadecimal. Once this adjustment has been made, the input word to the digital-to-analog converter 32 is set by the microcomputer 28 to a midscale value of 128 decimal (80 hexadecimal). Next, with no force being applied to the signature pad 12, its output balance potentiometer 14 is adjusted to bring the amplifier output voltage E o  to a &#34;null&#34; value (i.e. 0 volts). At this time the voltage e s  is at an amplitude of about +5 millivolts, and the amplitude of the voltage e a  is also at a value of approximately 5 millovolts. Now, by varying the value of the digital input word which is applied to the digital-to-analog converter 32, the output voltage E o  can be adjusted over a range of + or -0.5 volt (500 millivolts) about the null point, so long as the voltage e s  is held constant at 5 millivolts. The output voltage E o  of the operational amplifier 18 is converted to a digital value by the analog-to-digital converter 24 and is input to the microcomputer 28 through the input port 26. In this manner, the microcomputer 28, under appropriate software program control which will subsequently be described, can monitor the status of the null point and can correct for drift by modifying the value of the digital data word which is applied through the output port 30 to the digital-to-analog converter 32. The digital data word which is applied from the output port 30 to the converter 32 is latched or held in said port and continuously applied to the converter 32 until such time as a decision is made in the microcomputer that a change in value should be made in order to correct the drift. As will subsequently be seen, a number of measurements are taken of the value E o  in order to obtain a number of data word values, from which an average is then taken and utilized during the sensing of a signature by the signature pad 12. As implemented in the signature verification system, the null drift of the signature pad 12 may be measured and corrected immediately prior to the making of each signature. 
     The method by which the microcomputer 28 functions to correct the null drift and to provide the desired compensating data word value is best explained by reference to the flow diagrams of FIGS. 2A, 2B, 2C, 2D, 2E and 2F. 
     Referring now to FIG. 2A, the drift compensating process is commenced at an appropriate time during overall signature verification system operation by the System Executive Program, as indicated by block 50. A loop counter COUNT is initialized to a value of 32; an initial value INITV is set to 16; and a totalizing counter SUM is cleared to 0 in starting the program, all as shown in block 52. These designated quantities may be stored in appropriate register or memory locations. A COUNT value of 32 is selected arbitrarily as a suitable total number of positive and negative loop samples from which an average may be derived, with each of the 32 iterations including both a positive and a negative loop sample, for a total of 64 samples. Other values than 32 would be suitable and can be selected. However, selection of a power of 2 simplifies the division procedure to be subsequently discussed, so that ideally COUNT should be selected from among the numbers 2, 4, 8, 16, 32, 64, etc. The division process which is used for derivation of an average can be conveniently accomplished in the microcomputer of the illustrated example simply by shifting right the contents of a register an appropriate number of times. 
     The INITV value of 16 is selected to provide a suitable initial magnitude for the PRIOR VALUE parameter which is subsequently used in the program for evaluating each analog-to-digital data word generated. The totalizing counter SUM is set to 0 in preparation for accumulating a total which is used in establishing the average digital-to-analog data word value. 
     The process next proceeds to block 54, in which the PRIOR VALUE register is set to the INITV magnitude and the digital-to-analog control register, representing the data word value, is set equal to 0. It should be noted that these values could be retained in memory locations rather than in registers, if desired, at the expense of increased execution time. The microcomputer employed in the illustrated embodiment of the system contains a sufficient number of registers to permit the dedication of two of said registers for these parameters. 
     Continuing, as shown in block 56, the digital-to-analog data word held in the digital-to-analog control register is outputted to the digital-to-analog converter 32. It will be seen that block 56 is the first block in a loop 57 in which the digital-to-analog data word is successively incremented in value. For the first iteration of this loop 57, the digital-to-analog data word is 0, resulting in an analog voltage output of e a  of 0 volts. This causes the output E o  of the amplifier 18 to be set to some positive value of output voltage as determined by the previously-mentioned equation: E o  =A(e s  -e a ). 
     Next in the process, the digital-to-analog data word is tested to determine whether or not it is at its maximum value of 255 decimal (FF hexadecimal), as shown in decision block 58. This maximum value condition cannot exist for a properly-adjusted and normally-functioning system, which has been initially set with the input word to a mid-scale value of 128 decimal, as previously described. However, in the event of certain malfunctions, such as excessive offset voltage e s  from the signature pad 12 or a burnout failure of the digital-to-analog converter 32, the loop 57 commencing with block 56 will be traversed 255 times without resulting in proper adjustment of the voltage e a . In such case, the &#34;Yes&#34; exit from the decision block 58 is taken; an error character, shown in the illustrated embodiment as the ASCII code &#34;P&#34;, is stored in a reserved memory location, as represented by block 60; and path 62 is taken to an ABORT routine, represented by blocks 64 and 66 in FIG. 2F, in which a flag is set in block 64 to indicate that a hardware failure has occurred. The ABORT condition may optionally be handled in a suitable manner by the Executive Program; for example, the host computer may be notified of the failure. It should be noted that this is a fatal or catastrophic failure mode and that attempts to utilize the system 10 must be prevented until the malfunction has been serviced. Storage of the unique error character &#34;P&#34; is useful in diagnostic analysis. 
     Returning to FIG. 2A, and assuming that the data word test is successful so that the &#34;No&#34; exit from decision block 58 is taken, the analog-to-digital data output word representing the value of E o  is read into the microcomputer 12 from the analog-to-digital converter 24 through the input port 26, as represented by block 68 (FIG. 2B). The new analog-to-digital data word is then compared to the PRIOR VALUE, as indicated in decision block 70. Normally the new data word will be less than the PRIOR VALUE (or the initial value INITV for the first pass through the loop 57), because the voltage E o  will normally successively decrease as the digital-to-analog converter output is increased one step value for each pass through the loop 57. 
     If the new analog-to-digital data value is greater than the prior value, this indicates that some other factor is responsible, such as, for example, an increased force being improperly applied to the signature pad 12 by a customer seeking to establish his or her identity. In such case, the &#34;No&#34; exit is taken from the decision block 70, and path 72 is followed to a routine comprising blocks 74, 76, 78 (FIG. 2F), wherein an error indicator lamp may be flashed or an audible tone sounded until the fault clears or a time-out occurs. The warning continues over loop 75 for so long as the system continues to determine, as shown by decision block 77, that the analog-to-digital data word is not less than the initial value INITV, or until some other limit has been reached in accordance with the programming of the system. Exit from the loop 75 occurs when it is determined in decision block 77 that the analog-to-digital data word is less than the initial value INITV. This will normally take place when the improperly-applied force is removed from the signature pad 12. In such case, the system returns via the &#34;Yes&#34; exit from block 77 over path 79 to block 52 (FIG. 2A). 
     If the system is operating normally, and the &#34;Yes&#34; exit from block 70 is taken, the PRIOR VALUE is replaced with the new analog-to-digital data value as shown in block 80. In addition to this, a small tolerance factor must be added to the analog-to-digital data value stored at this time, because an AC ripple component may be present in the output voltage E o  of the amplifier 18. Addition of this tolerance factor is easily accomplished by incrementing the PRIOR VALUE register. Three such incrementing operations are carried out in the illustrated embodiment, though a different tolerance magnitude could be selected if desired. 
     Proceeding with system operation, in block 82 the analog-to-digital data word is tested, and if it is not equal to 0, the &#34;No&#34; exit is taken, and path 84 is followed to block 86, where the digital-to-analog data word held in the digital-to-analog control register is incremented one step, and operation continues from block 86 over path 88 to the previously-mentioned block 56 for a further traverse of the loop 57. If the analog-to-digital data word is 0, the loop 57 is exited via the &#34;Yes&#34; exit of block 82. 
     Next, in decision block 90, another diagnostic test is made to detect the instance in which either the circuitry of the signature pad 12 has failed or the power to the signature pad 12 has been interrupted. A test limit value LIM1 is arbitrarily set relatively low (e.g. 10 decimal or 0A hexadecimal). In block 90, if the digital-to-analog data word is less than LIM1, the &#34;Yes&#34; exit is taken, the ASCII character for &#34;L&#34; is stored in the error character memory location, as indicated in block 92, and path 62 is followed to the ABORT routine. Here again, the error condition is fatal, and system operation must be suspended until maintenance is performed. 
     Next, assuming that the normal &#34;No&#34; exit is taken from decision block 90, the digital-to-analog data word held in the digital-to-analog control register is added to the totalized SUM being maintained in a register pair of the system microcomputer (specifically the H and L register pair in the illustrated embodiment), as shown in block 94 of FIG. 2C. 
     In block 96, the digital-to-analog data word held in the digital-to-analog control register is set to the maximum value of 255 decimal (FF hexadecimal) prior to entering a second adjustment loop 98. This loop, which might be termed the N loop, controls the digital-to-analog converter such that the null point of the amplifier output voltage E o  is approached from the region in which E o  values are of negative polarity, in contrast to the first loop 57 described previously, which can be termed the P loop, wherein the null point is approached from the region in which E o  is of positive polarity. 
     The use of the two loops 57 and 98 is based upon the results of experimentation, and the desire to enhance accuracy to the maximum possible extent. For a system in which a less rigorous standard of accuracy is acceptable, the P loop only could be utilized. In fact, an operative system could be provided in which no averaging operation, such as will subsequently be described, takes place, and in which the data word value is determined simply by a series of operations of the P loop in which the output E o  is ultimately set by incrementation off the digital-to-analog register 32 to a value which results in a zero output voltage E o  when the signature pad 12 is at rest. In the illustrated embodiment however, the system incorporates both the P and N loops, and exhibits accuracy of a higher degree than that which could be obtained by using only one loop or by not performing the averaging operation. 
     The reason why greater accuracy is obtained by use of both the P and N loops is believed to be due largely to the asymmetrical ripple component present on the amplifier output voltage E o . This ripple component arises from deliberate minimal filtering of the demodulator utilized in the force-to-voltage transducer circuitry of the signature pad 12 with which the present invention is utilized in the illustrated embodiment. The degree of filtering represents a design trade-off between dynamic response times of the transducer output voltage and the ripple amplitude. The asymmetry of the ripple waveform results from diode mismatch in the transducer demodulator, and its nature may be expected to differ from unit to unit. Thus, it is believed that incorporation of the P and N loops provides a means for attaining minimal error regardless of individual variations in component values in the other portions of the system with which the present invention is utilized. 
     Continuing now with the description of the system, in block 100 (FIG. 2C) the digital-to-analog data word is outputted to the digital-to-analog converter. Block 100 is the initial block in the N loop 98, and it will be seen that the digital-to-analog converter voltage during the operation of this loop commences at its maximum value and decreases incrementally in stairstep fashion until the loop exit decision condition is satisfied. It will be remembered from the previous discussion that exactly the opposite occurs in the P loop 57, in which the digital-to-analog converter voltage starts at 0 and increases toward its maximum value. 
     Continuing with the process, in decision block 102, the digital-to-analog data word is tested for 0.  If the data word is equal to 0, implying a circuit failure, the &#34;Yes&#34; exit from block 102 is taken, and ASCII character &#34;N&#34; (denoting the N loop 98) is stored in the error character memory location, as represented in block 104, and path 62 is followed to the ABORT routine, represented by blocks 64, 66 (FIG. 2F). 
     Assuming that the normal &#34;No&#34; exit is taken from the decision block 102, the analog-to-digital data word is read as shown in block 106, and tested for 0 in decision block 108. In considering the operation of the N loop 98, it should be noted that since the signature pad 12 of the illustrated embodiment produces a unipolar voltage waveform, the analog-to-digital converter 24 utilized therewith is of the positive polarity type. This converter translates all negative polarity voltage values to a 0 value digital word. Therefore, exit from the N loop 98 via the &#34;No&#34; exit of the decision block 108 takes place during the first iteration of the loop 98 in which the analog-to-digital data word output exceeds 0. Such iteration is the one during which the magnitude of the digital-to-analog data word has been decremented sufficiently that the corresponding voltage output e a  applied to the inverting input of the amplifier 18 results in an output from said amplifier which is sufficient to produce an output from the analog-to-digital converter 24 of a value of 1 or more; that is, when the least significant bit of the word output from the analog-to-digital converter 24 becomes true (logical 1). For the eight-bit analog-to-digital converter used in the system of the illustrated embodiment, this occurs when output E o  slightly exceeds 39 millivolts. 
     For as long as the analog-to-digital data word remains 0, the &#34;Yes&#34; exit over path 110 from decision block 108 is taken, the digital-to-analog data word is decremented by one bit (thus decreasing the digital-to-analog converter output voltage by one step value) in block 112, and the program remains in the N loop 98, returning over path 114 to block 100. Once the analog-to-digital data word becomes non-zero, the &#34;No&#34; exit from block 108 is taken and the digital-to-analog data word is added to the SUM, block 116 (FIG. 2D). 
     In block 118, the loop counter COUNT is decremented by 1 and is tested for 0 in decision block 120. The loop counter was originally initialized, as described previously, for a count of 32 decimal at the beginning of the operation. 
     By following path 122 from the &#34;No&#34; exit of block 120, it may be seen that the loop counter COUNT is counting the iterations of an outer loop 124 which encloses the P loop 57 and the N loop 98. For each pass through this outer loop 124, two values of the digital-to-analog data word are determined, one by the P loop 57 and one by the N loop 98. These values are then accumulated in the totalizer SUM. Therefore, for an outer loop count of 32, a total of 64 values are accumulated, necessitating division by 64 to obtain an average value for the digital-to-analog data word. This division is performed in blocks 126, 128 and 130 by six right shifts of the register pair (H and L in the illustrated embodiment) containing the SUM, as determined by the division count, or DCNT. 
     After the above division operation, the value SUM (now the average SUM) is compared with warning limits LIM2 and LIM3, in decision block 132 (FIG. 2E). If it is found that the value SUM is either greater than LIM2 or less than LIM3 an ASCII character &#34;A&#34; is stored for future diagnostic purposes, as shown by block 134, in the error character memory location, but system operation continues. Setting of these two limits is somewhat arbitrary, and is dictated by the long-term aging drift characteristic of the circuitry. Typically, the limits might be set at the ten percent and ninety percent points of the digital-to-analog data word range. Hence, in the illustrated embodiment, suitable values are 225 decimal (E1 hexadecimal) for LIM2 and 25 decimal (19 hexadecimal) for LIM3. 
     If the value SUM passes the two limit tests of the block 132, the &#34;No&#34; exit is taken to block 136, where as ASCII SPACE (20 hexadecimal) character is stored in the error character memory location, to indicate an absence of error. It should be noted that this ASCII SPACE character, as well as all of the other error characters previously discussed, are of particular significance only in the illustrated embodiment, and that other characters or codes may be alternatively used, as appropriate. 
     The operation then proceeds to block 138, in which the SUM value is loaded into the digital-to-analog control register, thereby becoming the digital-to-analog data word. 
     In blocks 140, 142 and 144 (FIG. 2E), a final adjustment is made to the digital-to-analog data word. The null point of 0 voltage point of E o , as read by the eight-bit analog-to-digital converter, is actually slightly less than 39 millivolts, corresponding to the converter&#39;s least-significant-bit resolution. The voltage E o  may be adjusted closer to the actual 0 than the analog-to-digital converter is capable of detecting, by incrementing the digital-to-analog data word a suitable number of steps. It has been previously explained that the potentiometer 36 is initially adjusted such that the voltage E o  decreases approximately 4 millivolts for each increment (i.e. an increase of 1) of the digital-to-analog data word. A final adjustment of the voltage E o  is made in the loop comprised of blocks 142 and 144. It has been found by experience that an increment count DAJCT (or digital-to-analog adjustment count) of 8 gives good results in this respect. During extended system tests, the 0 adjustment has been consistently maintained within plus or minus 5 or 6 millivolts from true 0, which is less than a 1/4 bit error in respect to the resolution of the analog-to-digital converter in the illustrated embodiment. 
     As shown in FIG. 2F, the adjusted digital-to-analog data word is outputted to the digital-to-analog converter in block 146, a READY indicator is turned on in block 148, and return to the System Executive Program is effected, as shown in block 150. 
     Below is a group of program listings in Intel 8080 assembly language for the system operations described above. ##SPC1## 
     While the form of the invention illustrated and described herein is particularly adapted to fulfill the objects aforesaid, it is to be understood that other and further modifications within the scope of the following claims may be made without departing from the spirit of the invention.