Automatic tuning circuits for voltage controlled filters, by digital phase control
This invention relates to an improvement in automatic tuning circuits for voltage controlled filters, by digital phase control. 
     In particular this invention relates to a digital circuit which is able to automatically tune a voltage controlled filter (e.g. a YIG type filter or a Varicap filter) on the same frequency of a signal or on a frequency shifted by a selectable off-set Δf and to maintain the desired tuning for an indefinite period of time. 
    
    
     This invention will now be described with reference to a presently preferred embodiment, referred to as a non-limitative example and based on the attached figures, wherein: 
     FIG. 1 shows the general block diagram of the circuit according to the invention; and 
     FIG. 2 shows wave forms which explain how the circuit in FIG. 1 does work. 
    
    
     With reference to FIG. 1 the part embodied in the dashed area indicates the object of this invention, while the oscillator 1, the switch I, the filter 2 and the radio frequency detector 6 are conventional devices whose characteristics depend upon the operating frequencies. 
     In particular there is an oscillator 1 which generates a specified frequency such as that of a local oscillator of a super-heterodyne, while the users are a mixer and a path to be filtered such as for example a receiver front-end, which has to be filtered at a frequency usually off-set by Δf with respect to the frequency of the wave generated by the oscillator 1. 
     The circuit works in the following way. 
     In tuning search phase the operator operates the &#34;tuning control,&#34; closing switch 11, to provide the desired frequency offset voltage from source V o  to adder node N, and activating clock generator 3, while maintaining switch I in the A position, in which the oscillation produced by oscillator 1 output is passed through filter 2. Clock generator 3 generates a square-wave at a frequency which can range from a few KHz to some tens of KHz and depends upon the filter tuning changing rate and upon the quantization error desired on the tuning. 
     The frequency of the clock generator 3 is divided by an M-bit divider 4 in such a way as to obtain a square-wave signal at a relatively low frequency. This signal at the divider 4 output carries out three functions: 
     (a) it drives circuit 5 to generate a low frequency sawtooth, which passing through the analog adder Σ, scans the filter response during a Δf 1  interval selected as a function of the frequency range within which the tuning is looked for; that range is defined by the sawtooth signal amplitude and can be adjusted by means not shown; 
     (b) it presets at high level the output Q of bistable FF1, to enable the gate P1 to pass clock signals; 
     (c) it provides the storage signal to register R. 
     Due to the sweeping of the filter response controlled by the sawtooth signal, the oscillator 1 frequency periodically matches that filter, so that at the radio frequency detector 6 output connected to the filter 2 output, there will be a pulsed wave form with the same pattern of filter pass-band, the length of which is proportional to the sawtooth wave rate driving the filter tuning, the delay with respect to the sawtooth wave starting point depending upon the filter 2 out-of-tuning condition compared to the oscillator 1 frequency of oscillation. In particular, when filter 2 is centered with respect to oscillator 1, the lag is equal to half of a sawtooth period, while the lag is lower than this amount if the filter is lower tuned, and is higher if the filter is higher tuned. (These situations are shown in FIG. 2, where A indicates the sawtooth oscillation; B the time response of the filter tuned on the oscillator; C and D the filter out-of-tuning with respectively a negative and a positive Δf). 
     The radio frequency detector 6 output is squared in the squarer 7, and in correspondence with the rise of this square-wave, bistable FF1 is reset, the output Q of which goes to a logic zero, then disabling the gate P1 and blocking the clock pulse stream from the M-bit counter 12. In that way the M-bit counter acts as lag reader, i.e. as a phase discriminator. 
     It is to be noted that the square-wave coming from the squarer 7 has a length depending on the filter 2 form factor. To avoid the error introduced by square-wave finite length, coming from squarer 7, there is provided a second gate P2, a second M-bit counter 8 followed by a divide by 2 circuit which measures the square-shaped wave length. (The division by M and the subsequent division by 2 is provided as it is required to center the filter with respect to the oscillation of the oscillator 1). 
     The numeric word corresponding to such a length, divided by two, is subtracted in the binary subtractor circuit 9 from the tuning error to obtain the correct centering of a filter response. 
     The error is referred to the centered situation, corresponding to one-half of said lag. 
     The so corrected error is integrated by a digital integration circuit made by register R and binary adder S. The stored data are sent to digital-analog converter 10 which converts them to an analog voltage. 
     This voltage is sent to the analog adder node N and the output of this node is sent to the previously mentioned analog adder Σ. 
     In the adder node N can be added a frequency offset voltage obtained from voltage source V o  after the locking of the loop has been accomplished, to provide a preset out-of-tuning of filter 2 with respect to oscillator 1. 
     When the tuning search phase is ended, switch I is repositioned on main path B, and the register R stores indefinitly the voltage value to be provided to the filter until a new &#34;tuning control&#34; is required. 
     Changes are possible in respect of the aforementioned. For example: 
     (a) oscillator 1 is a VCO (Voltage Controlled Oscillator) and a coarse preset of tuning is obtained; 
     (b) oscillator 1 is a VCO and the automatic tuning control is fed-back to the same oscillator instead of the filter; 
     (c) use of the above mentioned circuit for the linearization of oscillator characteristics with respect to those of the filter (e.g. in case a highly linear YIG filter is used); 
     (d) automatic periodic setting of the tuning control signal to correct possible thermal shifts of the oscillator and/or filter characteristics. 
     This invention has been described with reference to a presently preferred embodiment, referred to as a non limitative example; it is clear that in practice several changes and modifications could be carried out without departing from the scope of this invention.