Comparison circuit having bidirectional hysteresis
BACKGROUND OF THE INVENTION 
     This invention relates generally to a comparison circuit for comparing input signals to a reference potential and more particularly to a comparison circuit having bidirectional hysteresis. 
     Many forms of comparison circuits are generally known in the art for comparing an input signal to a reference signal to produce an output signal indicative of some predetermined relationship therebetween. Generally, these comparison circuits comprise a differential amplifier circuit wherein a reference potential is applied at one input thereof and an input signal is applied to the other input. A particular kind of load circuitry is connected to the differential amplifier circuit for producing the output signal when the input signal obtains a predetermined relationship with respect to the reference signal. For example, U.S. Pat. No. 3,872,323 to Thomas M. Frederiksen et al, issued Mar. 18, 1975 discloses a comparision circuit comprising such a differential amplifier and a differential to single ended converter circuit which is exemplary of the prior art. 
     Whenever such comparision circuits are used in a high noise environment there is always a chance that the comparator circuit may be falsely tripped by generated noise. Therefore, it is desirable to introduce hysteresis into the comparator circuit such that after the input signal has reached a predetermined magnitude the comparator circuit will be tripped and thereafter is not affected by any high noise generated on the input signal. Comparison circuits having hysteresis introduced therein are generally known in the art as exemplified by U.S. Pat. No. 3,725,673 issued Apr. 3, 1973 to Thomas M. Frederiksen. 
     A problem with many of the prior art comparison circuits having hysteresis introduced therein is the complexity of the circuitry required to provide the hysteresis. A need therefore exists in the art to provide a comparision circuit generally free of complexity in its circuitry and therefore inexpensive to fabricate. 
     SUMMARY OF THE INVENTION 
     Therefore it is an object of the invention to provide an improved comparison circuit. 
     It is another object of the present invention to provide a comparison having bidirectional hysteresis introduced therein. 
     Still another object of the present invention is to provide a comparision circuit, having hysteresis, which is suitable to be manufactured in monolithic integrated circuit form. 
     In accordance with the foregoing objects a comparison circuit having bidirectional hysteresis is provided in the preferred embodiment of the invention which includes a differential amplifier stage having first and second inputs, a differential-to-single ended circuit coupled to the differential amplifier circuit, and a bias and output circuit coupled to an output of the differential-to-single ended circuit. During quiescent circuit operation the bias and output circuit produces both a nominal bias potential to the second input of the differential amplifier and an output signal from the comparison circuit. At such time when the magnitude of the signal applied at the first input of the differential amplifier becomes greater than the nominal bias potential the bias and output circuit is caused to switch operating states such that the magnitude of the nominal bias potential is significantly reduced whereby hysteresis is introduced into the comparison circuit and the output signal inhibited. This state continues until the signal at the first input of the differential amplifier becomes less than said reduced bias potential and the comparison circuit is returned to its quiescent operating state. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The single FIGURE of the drawing is a schematic diagram of a preferred embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The single FIGURE of the drawing illustrates comparison circuit 10 of the preferred embodiment which is suitable to be manufactured in integrated circuit form. Comparison circuit 10 is shown as including differential amplifier stage 12 comprising NPN transistors 14 and 16 and PNP transistors 18 and 20, differential-to-single ended converter circuit 22, and bias and output circuit 24. 
     Differential amplifier stage 12 includes NPN transistors 14 and 16 having respective collectors thereof coupled to a source of operating potential, V+, at terminal 26. The base electrode of transistor 14 is adapted to be coupled to an input terminal for receiving an input signal applied thereto. The base electrode of transistor 16 is connected at junction node 30 to a resistive divider network comprising resistors 32, 34 and 36. The emitter electrodes of transistors 14 and 16 are connected, respectively, to the emitter electrodes of multi-collector PNP transistors 18 and 20 of which the base electrodes are interconnected. As shown, a first collector of transistor 18 and transistor 20 are interconnected together with the base electrodes thereof through current source 38 to ground potential 39. The other collector electrode of transistor 18 which forms a first output of differential amplifier 12 and the other collector electrode of transistor 20 which forms the second output of the differential amplifier circuit are connected to differential-to-single ended converter circuit 22 at nodes 46 and 44 respectively. 
     As is generally known in the art, differential-to-single ended converter circuit 22 comprises a first NPN transistor 40 and diode 42. The collector of transistor 40 is connected to the output of the differential amplifier stage with the emitter electrode thereof being coupled to ground potential 39. The base electrode of transistor 40 is directly connected to the anode of diode 42 and to the second output of the differential amplifier at node 44. The cathode of diode 42 is connected to ground potential 39. An output is provided at node 46 of differential-to-single ended converter 22. As will be explained later in detail, in response to the input signal at the input becoming greater in magnitude than the nominal reference voltage provided at node 30, a driving signal is provided at node 46. 
     Bias and output circuit 24 includes the resistor divider network comprising resistors 32, 34, and 36, switching transistor 48 and an output transistor 50. Switching transistor 48, an NPN transistor, has its base electrode connected to the output of differential-to-single ended converter circuit 22 at junction 46. The collector of transistor 48 is connected at node 52 to the resistor divider network between resistors 34 and 36. The emitter of switching transistor 48 is coupled to ground reference potential. Transistor 50 has its base electrode connected to resistor 36, its emitter electrode coupled to ground reference potential and its collector electrode coupled to output terminal 54 of the comparison circuit. 
     Assuming no input signal, comparison circuit 10 is in a nominal state as will be hereinafter described. Normally, transistor 50 is in a saturated state and sinks current at output terminal 54. Further, transistor 48 is in an off state such that a bias reference potential V B  is provided at node 30 produced by the resistive divider network comprising resistors 32, 34 and 36 and the base to emitter junction voltage of transistor 50. In this nominal state, transistor 14 is nonconductive and transistor 16 is conductive. Likewise transistors 18 and 20 are nonconductive and conductive, respectively. Therefore, current is provided at the collector of transistor 20 to differential-to-single ended converter 22 which is connected to the differential outputs of amplifier 12. As is known in the art, differential-to-single ended converter circuit 22 is comprised of a current mirror circuit such that the current flowing through diode 42 is mirrored through transistor 40 to ensure the balanced current conditions mentioned above. Therefore, in a nominal state, current is sourced to diode 42 and transistor 40 is nonconductive. In this condition, no output current is supplied to the base of transistor 48, at node 46. Thus, switching transistor 48 is in an off condition as assumed above. 
     In response to an input signal applied to the input terminal of comparison circuit 10 becoming substantially equal to or greater than the nominal bias potential, V B , transistor 14 is caused to conduct heavier then transistor 16 which in turn causes a greater magnitude of current at the node 46. This excess current is then utilized to provide base drive current to switching transistor 48 thereby turning this transistor on. Transistor 48 immediately becomes saturated thereby rendering transistor 50 nonconductive. With transistor 48 in a saturated state, the resistive divider network is then comprised of only resistor 32 and 34 plus the saturation voltage of transistor 48. Hence, the bias potential at node 30, V B , is substantially reduced. Transistor 48 will be maintained in a conductive state until such time that the input signal decreases below the magnitude of the reduced bias potential at node 30. When this condition occurs, transistor 48 is then rendered nonconductive because the excess current is no longer available at node 46. V B  then increases to its nominal value. The comparison circuit is then caused to be switched to its nominal operating state, i.e., transistor 50 sinking source current at output terminal 54. 
     What has been described, is a comparison circuit having bidirectional hysteresis. The hysteresis is introduced into the circuit by providing a first bias potential of a first magnitude which must be overcome by the input signal reaching a value substantially equal to or greater thereto which causes switching at the output of the comparison circuit. In response to the output being switched, the first bias potential is caused to be substantially decreased such that the output cannot be switched back to its original state until such time that the magnitude of the input signal becomes substantially equal to or less than this reduced value. Hence, after the input signal has caused initial switching, any noise generated signal induced on the input signal will not cause the output to be prematurely tripped.