Differential amplifier
BACKGROUND OF THE INVENTION 
     This invention relates to an improved differential amplifier wherein the input terminal voltage of the differential amplifier is maintained at substantially zero potential regardless of the variations of power source voltages when no input signal is received. 
     Conventionally, a differential amplifier comprising a pair of transistors has been proposed, in which a signal input terminal is derived from the base of the first amplifier transistor. A compensation transistor is coupled to the base of the first amplifier transistor for absorbing the base current of the first amplifier transistor. This type of differential amplifier is indicated at page 73 of &#34;OPERATIONAL AMPLIFIERS Design And Applications&#34; published by McGRAW-HILL KOGADUSHA, LTD. In such a differential amplifier, a resistor is connected to the emitter of the compensation transistor and the amount of current absorbed from the base of the first amplifier transistor is controlled by adjusting the resistance of the resistor associated with the compensation transistor. Accordingly, in the case where the voltages in positive and negative power sources are independently varied, the collector current of the compensation transistor and the collector currents of the amplifier transistors are individually varied. These variations individually vary the base currents of the compensation transistor and the first amplifier transistor, with the result that the input terminal voltage of the differential amplifier fluctuates from the zero voltage level and thus the applied input signal is to be superimposed on the input terminal voltage being varied. Consequently, the compensation transistor does not operate to completely absorb the base current of the first transistor when the power source voltages are varied. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention is to provide an improved differential amplifier eliminating the above-mentioned drawback. Briefly, and in accordance with the present invention, the base of a compensation transistor whose polarity is opposite to the first amplifier transistor is connected to the base of the first amplifier transistor to absorb the base current of the first amplifier transistor. A load circuit comprising a transistor and a variable resistor is connected in series to the compensation transistor, which implements current mirror operation together with a current minor circuit coupled to the differential amplifier. Hence, the input terminal voltage of the differential amplifier is maintained at substantially zero potential when no input signal is received regardless of the variations of the power source voltages. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The single FIGURE is a circuit diagram showing one preferred embodiment according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A preferred embodiment according to the present invention will now be described with reference to the accompanying drawing. 
     In a single FIGURE, PNP transistors Q 1  and Q 2  constitute a differential amplifier wherein the commonly connected emitters of the transistors Q 1  and Q 2  are connected through a resistor R 0  to a positive power source +V cc . The base of the transistor Q 1  is connected to a signal input terminal IN via an NPN transistor Q 5  which will be described later on. One terminal of an input resistor R 1  is connected to the line between the bases of the transistors Q 1  and Q 5  while the other terminal thereof is grounded. The collector of the transistor Q 1  is connected to the next stage amplifier whose output is connected to one terminal of a load resistor R L  having the other terminal being grounded. The output of the amplifier system as shown is derived from an output terminal OUT. A resistor R 6 , the transistor Q 2  and Q 1 , and the next stage amplifier constitute a negative feedback circuit for compensating thermal drift of the transistor Q 1 . The collectors of the transistors Q 1  and Q 2  are connected to the collectors of NPN transistors Q 3  and Q 4 , respectively. The base of the transistor Q 4  is connected to the collector of the same transistor and to the base of the transistor Q 3 , thereby constituting a current mirror circuit. The emitters of the transistors Q 3  and Q 4  are connected to a negative power source -V cc  through resistors R 3  and R 4 , respectively. The transistor Q 5  is provided for absorbing the base current of the transistor Q 1 , and whose emitter is connected to the collector of the transistor Q 6 , base to the base of the transistor Q 1  and collector to the positive power source +V cc . The emitter of the transistor Q 6  is connected through a variable resistor R 5  to the negative power source -V cc . The base of the transistor Q 6  is connected to the bases of the transistors Q 3  and Q 4 , thereby constituting a current mirror circuit together with the transistors Q 3  and Q 4 . 
     The operation of the differential amplifier thus constructed will next be described. The base potential V R2  of the transistor Q 2  is supplied by a resistor R 2  whose one terminal is connected to the base of the transistor Q 2  and whose other terminal is grounded. The base potential V R2  of the transistor Q 2  is maintained approximately zero voltage because the resistance of the resistor R 2  is small. The collector current I C5  of the transistor Q 5  is approximately equal to the collector current I C6 . 
     Due to the current mirror operation implemented by the transistors Q 4  and Q 6 , the following relationship is established: 
     
         I.sub.C5 =(R.sub.4 /R.sub.5)·I.sub.C2             . . . (1) 
    
     where I C2  is the collector current of the transistor Q 2 . 
     On the other hand, when no input signal is received, there is a relationship of I C1  =I C2 . Further, with respect to the transistors Q 5  and Q 2 , the following equations can be established: 
     
         I.sub.C5 =h.sub.FE5 ·I.sub.B5                     . . . (2-1) 
    
     
         I.sub.C1 =I.sub.C2 =h.sub.FE1 ·I.sub.B1           . . . (2-2) 
    
     where h FE5  and h FE1  represent d.c. current amplification ratios of the transistors Q 5  and Q 1 , respectively. By substituting equations (2-1) and (2-2) for equation (1), the following can be obtained. 
     
         h.sub.FE5 ·I.sub.B5 =(R.sub.4 /R.sub.5) h.sub.FE1 ·I.sub.B1                                        . . . (1&#39;) 
    
     Provided that the base current I B1  of the transistor Q 1  and the base current I B5  of the transistor Q 5  are equal to each other, there will be no current flow in the resistor R 1  and thus the voltage V R1  of the input terminal become zero. Therefore, this can be implemented by adjusting the variable resistor R 5  so as to satisfy the following relationship: 
     
         (R.sub.4 /R.sub.5)=(h.sub.FE5 /h.sub.FE1)                  . . . (3) 
    
     In the case where the negative power source voltage is varied, since an impedance of the transistor Q 2  viewed from the negative power source is large, the sum of the base-emitter voltage V BE4  of the transistor Q 4  and the voltage V R4  across the resistor R 4  is substantially not varied, so that the collector current I C2  of the transistor Q 2  is not varied. Accordingly, due to the current mirror operation, the collector currents I C1  and I C6  of the transistors Q 1  and Q 6  are not varied in due course. As a consequence, the base current I B1  of the transistor Q 1  is completely absorbed by the transistor Q 5  and thus the input terminal voltage V R1  is not caused to be varied. On the other hand, in the case where the positive power source voltage is varied, if a constant current source is connected between the commonly connected emitters of the transistors Q 1  and Q 2  and the positive power source +V cc , the base currents I.sub. B1 and I B5  are not varied. In order to reduce the cost, however, the resistor R 0  is employed in this embodiment in lieu of the current source. In this case, since the resistance of the common emitter resistor R 0  is not infinite, the collector current I C2  of the transistor Q 2  is varied. The base currents I B5  and I B1  of the transistors Q 5  and Q 1  are represented by the following equations. 
     
         I.sub.B5 =(I.sub.C5 /h.sub.FE5)=(1/h.sub.FE5)·(R.sub.4 /R.sub.5)·I.sub.C2                               . . . (4) 
    
     
         I.sub.B1 =(I.sub.C1 /h.sub.FE1)=(I.sub.C2 /h.sub.FE1)      . . . (5) 
    
     From equation (3), since (1/h FE5 )·(R 4  /R 5 )=(1/h FE1 ), the base 
     current I B1  of the transistor Q 1  is equal to the base current I B5  of the transistor Q 5 . Therefore, the input terminal voltage V R1  is maintained zero voltage. 
     As can be appreciated from the above description, it can be understood that the input terminal voltage is maintained zero potential regardless of the voltage variations in the positive and negative power sources. 
     As is apparent, according to the present invention, the input terminal voltage of the differential amplifier is not varied by the variations of the power sources. Further, even though a ripple component is superimposed on the d.c. voltage of the power source, the differential amplifier according to the present invention rejects such a ripple component. This means that a filter provided in the power source can be simplified without causing any inconvenience in the operation of the differential amplifier. 
     Although the present invention has been described with respect to a specific embodiment, it will be appreciated by one skilled in the art that a variety of changes may be made without departing from the scope of the invention.