Clocked comparator
The invention relates to a clocked voltage-comparator formed by means of transistors which each have a control electrode and a second main electrode, which comparator comprises: 
     a comparison stage for comparing an analog input voltage with an analog reference voltage and applying the result of the comparison in the form of an intermediate signal and its complement, which stage comprises two transistors arranged as a first differential pair, the input voltage and the reference voltage being applied to the respective control electrodes of said transistors, whose first main electrodes are connected to a common terminal for applying a bias current and whose second main electrodes are each coupled to a first d.c. supply terminal via a load and supply the intermediate signal and its complement respectively; 
     a latching stage coupled to the comparison stage, which latching stage serves for generating logic states in conformity with the output signals from the comparison stage, which latching stage comprises two transistors arranged as a second differential pair forming a bistable latch, the signals received from each of the branches of the comparison stage being applied to the respective control electrodes of said latching-stage transistors, whose first main electrodes are connected to a common terminal and whose second main electrodes are cross-coupled to the control electrodes of the transistors of the second pair to form the outputs of said latching stage. 
     Such a circuit arrangement may be employed, for example, in an analog-to-digital converter of the parallel type in which the analog input signal is applied to the inputs of a plurality of parallel comparator circuits to form a digital output signal, in which comparator circuits this input voltage is compared with a reference voltage which differs for each comparator circuit. The output signals of the comparator circuits are converted into a digital output signal by means of a decoding device. The clocked comparator used in such a parallel analog-to-digital converter is generally of a type as defined in the opening paragraph. 
     Such a circuit is known, inter alia from U.S. Pat. No. 4,121,120. This known circuit, which is equipped with bipolar transistors, comprises a comparison stage constituted by a first pair of emitter-coupled transistors whose bases receive the input signals. This circuit also comprises an amplifier stage formed by a second pair of emitter-coupled transistors whose bases receive the signals from the collectors of the transistors of the comparison stage. Finally, this circuit comprises two latching stages comprising a third and a fourth emitter-coupled transistor pair, respectively, whose collectors are cross-coupled to the collectors of the first transistor pair and to the collectors of the second transistor pair respectively. Moreover, the emitters of these first, second, third and fourth transistor pair are each coupled to a current source via a transistor switch, the switches of the comparison stage and of the first latching stage having their commoned emitters coupled to a first current source and the switches of the amplifier stage and the second latching stage having their commoned emitters coupled to a second current source. These switches are controlled by clock signals in such a way that the comparison stage and the second latching stage are operated simultaneously, i.e. exactly when the amplifier stage and the first latching stage are inoperative. On the output of the first latching stage this known circuit produces an intermediate signal whose logic states follow the sign of the difference between the input signal and the reference signal applied to the input of the comparison stage, which difference is sampled on a rising edge of the clock signal and which is latched by the second latching stage until another stage appears on a rising edge. 
     However, in order to realise novel logic systems with a higher information-processing capacity such circuits should be constructed by means of new technologies, such as, for example, a technology using gallium-arsenide field-effect transistors. 
     If, for example, a depletion-type gallium-arsenide field-effect transistor is selected as the active element of a clocked comparator very high operating speeds can be obtained in combination with a very low power consumption. 
     However, the requirements to be met in order to obtain a very high operating speed are more stringent than the requirements to be met in order to obtain circuits having a low power consumption. 
     Therefore, it is the object of the present invention to provide a novel clocked comparator whose operating speed is increased not only by the use of an ultra-fast technology but in particular by the use of a special circuit arrangement without a consequent increase in power consumption. 
     According to the present invention this object is achieved in a comparator as defined in the opening paragraph, which is characterized in that: 
     the terminal to which the first differential pair is connected is coupled to a second d.c. supply terminal, for example earth, via a current-source trsnsistor; 
     the terminal to which the second differential pair is connected is brought directly at the potential on the second d.c. supply terminal, 
     the second differential pair is coupled to a third differential pair comprising two transistors arranged in parallel with the transistors of the second differential pair, a clock signal being applied to the control electrodes of the transistor of said third differential pair. 
     In this arrangement the latching stage is not disabled by disconnecting a current generator, as in the prior-art method, but by directly imposing the logic stage 0 upon each of the two branches of the differential pair by means of two parallel transistors which are controlled by the same clock signal as the current source of the comparison stage to which said latching stage is coupled. In this way faster operation is achieved. 
     An embodiment of the invention is characterized in that the second main electrodes of the first differential pair are each coupled to the respective control electrodes of the second differential pair via a coupling resistor. The coupling resistor via which the signals from the comparison stage are applied to the latching stage minimize the adverse effects of switching between the stages. 
    
    
     Embodiments of the invention will now be described in more detail, by way of example, with reference to the accompanying drawings. 
     FIG. 1 is a block diagram of the comparator in accordance with the invention. 
     FIG. 2 shows a circuit in accordance with the invention equipped with enhancement-type field-effect transistors. 
     FIG. 3 shows signal waveforms in different parts of the circuit as a function of the clock signals. 
     FIG. 4 shows a digital-to-analog converter circuit constructed by means of comparators in accordance with the invention. 
    
    
     As is shown in FIG. 1 the clocked comparator in accordance with the invention comprises a comparison stage 1, which is coupled to a first latching stage 3 via coupling resistors R C , and an amplifier stage 2 of a structure similar to that of the comparison stage 1 and coupled to a second latching stage 4 via coupling resistors R&#39; C . 
     The comparison stage receives an analog signal V IN  and an analog reference signal V REF . The outputs of the comparison stage, which are coupled to those of the latching stage, supply an intermediate signal V M  and its complement V M . 
     The comparison stage 1 and the latching stage are controlled by the same clock signal C. 
     The intermediate signal V M  and its complement are applied to the amplifier stage 2. The outputs of this stage, which are coupled to those of the latching stage 4, supply the digital output signal in phase with the value of the difference between the input signal V IN  and the reference signal V REF . 
     The amplifier stage 2 and the latching stage 4 are controlled by the complement C of the clock signal. 
     In an embodiment of the invention the comparison stage and the amplifier stage are controlled by means of a fixed potential V B . 
     In an embodiment of the invention shown in FIG. 2 the clocked comparator in accordance with the invention is equipped with enhancement-type field-effect transistors, for example gallium-arsenide transistors with a cut-off voltage V T  &gt;0 such that they are normally cut off in the absence of a signal. 
     As is shown in FIG. 2, the comparison stage comprises two transistors 10 and 12 whose sources are coupled to each other and whose gates receive the analog input voltage V IN  and the analog reference voltage V REF  respectively. 
     The drains of the transistors 10 and 12 receive a first d.c. supply voltage V DD  via a load resistor R 3  and R 13  respectively. 
     The sources of the transistors 10 and 12 which are coupled to the terminal 19 are connected to a second d.c. supply voltage, for example earth potential, via a current transistor 13 controlled by the clock signal C. 
     The first latching stage comprises two transistors 32 and 30 whose sources are coupled to the terminal 39. This terminal is connected directly to earth potential. 
     This latching stage is driven by two transistors 52 and 50, which are arranged in parallel with the transistors 32 and 30 respectively, under control of the clock signal C. 
     When the comparison stage is enabled the latching stage is directly set to the 0 state. It is known that, in order to obtain a satisfactory effect with such a comparison stage coupled to a latching stage, it is essential that the differential pair of the latching stage is disabled at the exact instant at which the differential pair of the comparison stage is enabled. Otherwise the circuit arrangement will exhibit instabilities. It is often very difficult to meet this requirement, in particular when the comparison stage and the latching stage are controlled by different clock signals. 
     In accordance with the present invention this problem is solved in that the latching stage and the comparison stage are controlled by the same signal. 
     An additional advantage of this is that the 0 state is obtained immediately. Thus, the transit time within one transistor is gained and the comparator operates more rapidly. 
     In accordance with an embodiment of the invention a third d.c. supply voltage V B  may be applied to the gate of the currentsource transistor 13 to render this transistor continuously conductive. The comparator stage is then continuously operative and instabilities are also avoided. 
     This embodiment is very interesting if the comparator comprises only one comparison stage coupled to the first latching stage. 
     The gates 8 and 18 of the transistors 32 and 30 are cross-coupled to the drains of the transistors 30, 50 and 32, 52 respectively. Moreover, the gates of the transistors 32 and 30 receive the signals from the comparison stage via coupling resistors R 4  and R 14  respectively. 
     The points 8 and 18 constitute the outputs of the arrangement comprising the comparison stage and the first latching stage. 
     The points 8 and 18 are connected to inverter/follower stages respectively. Point 8 is connected to an inverter stage comprising the transistor 102 and the load resistor R 2  and the follower stage comprises the transistor 100 and the resistor R 1 . 
     The inverter stage connected to point 18 comprises the transistor 112 and the resistor R 12  and the follower stage comprises the transistor 110 and the resistor R 11 . 
     The inverter stage serves to pull up the high level of the output of the latching stage. The follower stage serves to reduce the output impedance of the combination comprising the comparison stage and the latching stage. 
     The combination of the amplifier stage and the second latching stage is constructed and operates in exactly the same way as the combination comprising the comparison stage and the first latching stage. However, the transistors and the coupling or load resistors may have slightly different values in order to ensure a better matching. 
     The amplifier stage comprises two transistors 20 and 22 whose sources are coupled to each other and whose gates receive the intermediate signal V M  and it complement V M  respectively appearing on the source electrodes of the transistors 100 and 110 of the follower stages described in the foregoing. The source electrodes coupled to terminal 29 are connected to, for example, earth via a current source transistor 23 which is controlled by the complementary clock signal C. 
     The drains of the transistor 20 and 22 are connected to the first d.c. supply voltage V DD  via load resistors R 23  and R 33  respectively. 
     The second latching stage comprises two transistors 40 and 42 whose source electrodes are connected to terminal 49. This terminal is connected directly to ground potential. 
     This latching stage is driven by two transistors 60 and 62, which are arranged in parallel with the transistors 40 and 42 respectively and which are controlled by the complementary clock signal C. 
     When the amplifier stage is now enabled the latching stage is immediately set to the 0 state. 
     In the same way as in the foregoing the third d.c. supply voltage V B  may be applied to the gate of the current-source transistor 23 in order to render this transistor continuously conductive. The amplifier stage is then operated continuously. 
     The gates 38 and 28 of the transistors 40 and 42 are crosscoupled to the drains of the transistors 42, 62 and 40, 60 respectively. Further, the gates of the transistors 40 and 42 receive the signals from the amplifier stage via coupling resistors R 34  and R 24  respectively. 
     The points 38 and 28 constitute the outputs of this combination of the amplifier stage and the second latching stage. 
     These points 38 and 28 are connected to inverter/follower stages. The inverter stage connected to point 38 comprises a transistor 132 and the load resistor R 32  and the follower stage comprises the transistor 130 and the resistor R 31 . 
     Similarly, the inverter stage connected to point 28 comprises the transistor 122 and the resistor R 23  and the follower stage comprises the transistor 120 and the resistor R 21 . 
     The digital output signal of the comparator appears on the source electrode of the follower transistor 120 and its complement S appears on the source electrode of the follower transistor 130. 
     As is shown in FIG. 3, when the difference between the analog input signal V IN  and the analog reference signal V REF  applied to the comparison stage is positive and the rising edge of the clock signal C appears at the instant T 1 , for example the complementary signal V M  is latched in the high stage and the complementary output signal S goes low. 
     Subsequently, if at the instant T 2  a rising edge of the clock signal C appears and the difference becomes negative, the complementary signal V M  is sampled in the low state and the complementary output signal S is latched in the low state. 
     On the falling edge of the clock signal, at the instant T 3 , the difference still being negative, the complementary intermediate signal V M  is latched in the low state and the complementary output signal S is sampled in the high state. 
     Finally, at the instant T 4 , when the difference becomes positive on a rising edge of the clock signal C, the complementary output signal is latched in the high state. 
     Thus, the output signal S remains in phase with the sign of the differnce between the input signal V IN  and the reference signal V REF . 
     The analog-to-digital converter shown in FIG. 4 comprises a plurality of comparators (COMP 1, . . . COMP N) arranged in parallel which comparators each comprise two inputs. The analog input voltage V IN  to be converted is applied to an input of each comparator. A reference voltage across the series arrangement of a plurality of resistors is applied to the other input of each comparator. If all the resistors are identical this yields a geometrical progression of reference voltages, the ratio between the reference voltage being V REF/2 . The various reference voltages with the sequence numbers 1, 2, . . . i, 2n-1, 2n then constitute a series V REF/2n , V REF/2  n-1, . . . V REFn , the latter voltages being employed only to indicate an overload bit. The outputs of the comparators are connected to the inputs of a logic encoding device (COD), which supplies an n-bit digital output signal in accordance with an arbitrary code, which may be for example the Gray code. The encoding device is constructed in conformity with the required code, but is not described in detail because this encoding device falls beyond the scope of the present invention. A memory (MEMO) may be coupled to the output encoding device to preserve the information from the encoding device for at least a part of the clock period, thus allowing the comparators to be synchronised. The clock signal for the comparators and the latches is delivered by an external circuit. These circuits may be integrated on the same semiconductor substrate. 
     If the comparator described here is constructed by means of gallium-arsenide Schottky-gate transistors the voltages V IN , V REF , V M , V M , S and S will have high levels of 0.6 V and low levels of 0.1 V. 
     The threshold voltages of the transistors are V T  =0.1 V. 
     The d.c. supply voltages are as follows: 
     the first voltage V DD  =2 V 
     the second voltage=earth potential 
     the third voltage V B  =0.5 V. 
     The gate widths L and the values of the resistors R are specified in the following Table. 
     
                       TABLE I                                                     
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Transistors        Resistors                                              
No.      L in μm    No.      R                                         
______________________________________                                    
10,12    50μ        R.sub.4, R.sub.14                                  
                                1.8 kΩ                              
32,30    20μ        R.sub.3, R.sub.13                                  
                                2.2 kΩ                              
52,50    20μ        R.sub.2, R.sub.12                                  
                                  7 kΩ                              
102,112  10μ        R.sub.1, R.sub.11                                  
                                  3 kΩ                              
100,110  30μ                                                           
13       30μ                                                           
22,20    25μ        R.sub.34, R.sub.24                                 
                                1.6 kΩ                              
40,42    20μ        R.sub.33, R.sub.23                                 
                                1.6 kΩ                              
60,62    20μ        R.sub.32, R.sub.22                                 
                                  7 kΩ                              
122,132  10μ        R.sub.31, R.sub.21                                 
                                  3 kΩ                              
130,120  30μ                                                           
23       30μ                                                           
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     The use of an identical comparator in an analog-to-digital converter is also advantageous when the converter is constructed as an integrated circuit. 
     It will be obvious that several variants are conceivable to those skilled in the art without departing from the scope of the present invention as defined in the appended claims.