IC card and an identification system thereof
BACKGROUND OF THE INVENTION 
     The present invention relates to an IC card incorporating an IC circuit in a card, and an IC card identification system for identifying various IC card states wherein the IC card is supplied to a card holder or a customer through an issuer such as a manufacturer or a bank and the card holder goes shopping in a store. 
     A conventional magnetic card has a magnetic coating which is formed on the surface thereof and on which a key code or a confidential number, an account number and so on are magnetically recorded. The magnetic contents such as the key code are known to at least bank personnel since the holder as a user must submit his key code to the bank. In addition, a magnetic record can be relatively easily accessed. Because of this, the private key code of the magnetic card cannot be kept secret. 
     In place of such a magnetic card, an IC card incorporating an IC has been recently proposed that disables easy reading of recorded contents. However, there are many opportunities for unfair practice on such an IC card. It is very difficult to prevent such unfair practice in a construction of a conventional IC card and its identification system. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to prevent theft or forgery of an IC card during dispatch of an IC card from a manufacturer to an IC card issuer and from the issuer to the holder, to provide an IC card which cannot be subject to unfair practice when it is used, and an IC card identification system. 
     According to an aspect of the present invention, there is provided an IC card comprising an IC circuit which includes: 
     first memory means for storing a plurality of secret data; 
     second memory means for storing production master key (PMK) data preset by a manufacturer and used for checking validity of an issuer, and initialization personal identification number (IPIN) data used for checking validity of a card holder; 
     third memory means for storing personal identification number (PIN) data preset by the card holder and used for checking validity of the holder; 
     interface means for controlling input/output data with respect to the IC card; 
     comprising means for comparing external data supplied through said interface means with the data stored in said second or third memory means; 
     inhibiting means for inhibiting an access of said first memory means in accordance with a noncoincidence signal from said comparing means; and 
     permitting means for permitting the access of said first memory means in response to a coincidence signal from said comparing means. 
     According to another aspect of this invention, there is provided: 
     an IC card incorporating an IC circuit including a memory for storing a plurality of secret data preset by a manufacturer, the plurality of secret data including at least production master key (PMK) data and initialization personal identification number (IPIN) data; 
     printout means for printing out the PMK data by the manufacturer in a strictly secret state on a first sealed sheet, the PMK data being stored in said IC card; 
     means for separately delivering said IC card and the first sealed sheet to an issuer; 
     means for identifying the PMK data obtained by entering the PMK data printed on said first sealed sheet with the PMK data stored in said memory of said IC card; 
     means for storing primary account number (PAN) data in said IC card upon detection of a coincidence between the entered PMK data and the PMK data stored in said memory and for printing out the IPIN data read out from said memory on a second sealed sheet; 
     means for separately delivering said IC card and said second sheet to a card holder; 
     means for identifying IPIN data entered by the IPIN data printed on said second sealed sheet with the IPIN data stored in said memory of said IC card; and 
     means for storing personal identification number (PIN) data which is arbitrarily selected by the card holder in the IC circuit upon detection of a coincidence between the entered IPIN data and the IPIN data stored in said memory. 
     According to further aspect of this invention, there is provided: 
     an IC card incorporating an IC circuit including a memory for storing card authentication (CA) data preset by a manufacturer and given such that different CA data are assigned in units of IC cards; 
     a host computer for reading out the different CA data from the respective IC cards and storing all the CA data in a data base; and 
     a terminal, connected to said host computer through a public circuit, for identifying a presented IC card, 
     said terminal having readout means for reading out the CA data from the presented IC card, means for encrypting predetermined transaction message data in accordance with the CA data from the presented IC card, and means for transmitting encrypted predetermined transaction message data to said host computer, and said host computer having means for decrypting the encrypted transaction message data by using the CA data stored in the data base, means for discriminating whether or not the decrypted transaction message data is the predetermined transaction message data in said terminal, and means for transmitting a discriminated result to said terminal. 
     According to still further aspect of this invention, there is provided: 
     an IC card incorporating an IC circuit including a memory for storing issuer&#39;s private key (PRK) data preset by a manufacturer in a secret manner; and 
     a terminal for storing issuer&#39;s public key data preset by the manufacturer in a secret manner and for identifying an IC card presented by a card holder, the issuer&#39;s public key data being different from the PRK data but having a correlation with the PRK data in a one-to-one correspondence in accordance with a predetermined function known by only the manufacturer, and 
     said terminal having means for encrypting predetermined test message data in accordance with the public key data and means for transmitting encrypted test message data to said IC card, 
     said IC card having means for receiving the encrypted test message data and decrypting the message data by the private key data stored therein and means for transmitting decrypted test message data to said terminal, and 
     said terminal further including means for comparing the decrypted test message data from said IC card with a predetermined self test message, and means for producing an alarm of a comparison result. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows card identification steps for an IC card to be supplied from a manufacturer to a holder through an issuer; 
     FIG. 2 is a perspective view showing an outer appearance of a POS (point of sales) terminal; 
     FIG. 3 is a block diagram of an IC circuit incorporated in an IC card; 
     FIG. 4 is a block diagram of the POS terminal shown in FIG. 2; 
     FIG. 5 is a flow chart for explaining an operation performed in the IC card manufactured by the manufacturer before the IC card is sent to an issuer; 
     FIG. 6 is a flow chart for explaining an operation performed in the IC card before the IC card is issued from the issuer to the holder; 
     FIG. 7 is a flow chart for explaining an operation performed in the IC card before the holder himself issues the IC card sent from the issuer; 
     FIG. 8 is a flow chart for explaining an identification operation in the IC card when the IC card is used; 
     FIG. 9 is a flow chart for explaining an identification operation of the IC card at the POS terminal; 
     FIG. 10 is a flow chart for explaining an on-line identification operation of the IC card at the POS terminal; 
     FIG. 11 is a flow chart for explaining an on-line identification operation of an IC card at a host computer; 
     FIG. 12 shows a ROM table for storing data representing correspondence between a public key code stored in the POS terminal and the issuer code; and 
     FIG. 13 is a representation schematically showing a data base configuration at the host computer. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A preferred embodiment of the present invention will be described with reference to the accompanying drawings. The overall system will be described with reference to FIG. 1. FIG. 1 shows the relationship between a manufacturer 1 for manufacturing an IC card, an issuer 2 such as a bank for issuing an IC card, and a card holder 3 who uses the IC card. The manufacturer 1 manufactures an IC card 11 which will be described in detail later. The manufacturer 1 manufactures the IC card 11 and writes a predetermined code on the IC card 11 using an IC card issuing machine 12. The IC card 11 incorporates an IC circuit to be described in detail later. A connector 11a is arranged on the upper surface of the IC card 11. When the IC card 11 is mounted in the IC card issuing machine 12, the IC card 11 is connected to an internal circuit of the IC card issuing machine 12 through the connector 11a. The IC card issuing machine 12 has a card insertion port 13, a keyboard 14, a display panel 15 and a printer 16. Various codes such as &#34;CA&#34;, &#34;IPIN&#34;, &#34;PMK&#34; are selectively written on the IC card 11 in accordance with input data entered by an operator at the keyboard 14. The code &#34;CA&#34; (Card Authenticator) comprises a random 64-bit code which can be used as the key for encryption/decryption. The code &#34;IPIN&#34; (Initialization Personal Identification Number) comprises a random 6-bit code which is used until a personal identification number (PIN) is used. The code &#34;PMK&#34; (Production Master Key Code) represents a random code assigned to each manufactured group. The code &#34;PMK&#34; is kept secret even within the manufacturing plant. The code &#34;PMK&#34; (Private Key Code) comprises a decryption code which has a relationship in one-to-one correspondence with the encryption code &#34;Public Key Code&#34; assigned to a POS terminal (to be described later). When a predetermined code is written by the IC card issuing machine 12 on the IC card 11, only the code &#34;PMK&#34; is printed by the printer 16 on a printing paper sheet 17. The manufacturer 1 separately seals the IC card 11 recorded with the predetermined code and the paper sheet 17 printed with the code &#34;PMK&#34;. The IC card 11 and the paper sheet 17 are sent to the issuer 2. The issuer 2 loads the IC card 11 in an IC issuing machine 22 and reads the content of the code &#34;PMK&#34; on the paper sheet 17 sent from the manufacturer 1 and enters the content in the IC card issuing machine 22. Furthermore, the issuer 2 enters a code number &#34;PAN&#34; (Primary Account Number) for the IC card 11 in the IC card issuing machine 22. The code number is constituted by numerals. This may also be constituted by alpha-numeric characters. The IC card issuing machine 22 comprises a card insertion port 23, a keyboard 24, a display panel 25 and a printer 26 in the same manner as the IC issuing machine 12. When the IC card is entered to the IC card issuing machine 22, the code &#34;PMK&#34; written in the IC card 11 is compared with input data &#34;PMK&#34; entered at the keyboard 24 in the IC card. Only when a coincidence between the code &#34;PMK&#34; written in the IC card 11 and the input data &#34;PMK&#34; is established, is the account number &#34;PAN&#34; written in the IC card 11. The code &#34;IPIN&#34; is read out from the IC card 11 and is printed on a printing paper sheet 27. The IC card 11 written with the account number &#34;PAN&#34; and the paper sheet 27 printed with the &#34;IPIN&#34; are separately sealed and are sent to the card holder 3. When the card holder 3 receives the IC card 11 and the paper sheet 27 from the issuer 2, the card holder 3 goes to a card holder IC card issuing machine 32 which is installed on the issuer&#39;s premises. The card holder 3 then loads the IC card 11 into the IC card issuing machine 32, and the content of the code &#34;IPIN&#34; printed on the paper sheet 27 sent from the issuer 2 is read and entered in the IC card issuing machine 32. The card holder 3 enters any personal identification number &#34;PIN&#34;. The IC card issuing machine 32 comprises a card insertion port 33, a keyboard 34, a display panel 35 and a printer 36 in the same manner as in the IC card issuing machine 22. When the IC card is put into the IC card issuing machine 32 the code &#34;IPIN&#34; stored in the IC card 11 is compared with the input data &#34;IPIN&#34; entered at the keyboard 24 in the IC card. Only when a coincidence is established, is the personal identification number &#34;PIN&#34; written in the IC card 11. In this manner, the IC card issuing procedures are completed, and this IC card is then ready for use. 
     FIG. 2 shows the outer appearance of a POS terminal 41 in which the IC card 11 is used. The POS terminal 41 comprises a card insertion port 42, a keyboard 43, a display panel 44 and the like. The keyboard 43 has numeric keys 46, an enter key 47 and a cancel key 48. The internal circuit of the POS terminal 41 will be described in detail later. 
     An IC circuit incorporated in the IC card 11 will be described in detail with reference to FIG. 3. Referring to FIG. 3, a serial interface 51 is arranged between the connector 11a and an internal system bus 52. When the IC card 11 is loaded in the POS terminal 41, the IC card 11 receives a reset signal RESET and a system clock CLOCK from the POS terminal 41 through the connector 11a, and is connected to a Vcc power supply, a Vpp power supply and a ground line GND. The Vcc power supply serves as a system drive power supply and is set at a voltage of +5 V. The Vpp power supply serves as a data write power supply for an EP-ROM (Erasable-Programmable ROM) 61 (to be described later) and is set at a voltage of +25 V. A working RAM block 53, a system programming ROM block 54, a system controller 55, an ALU 56 for RSA decryption, a data latch 57, a cancel latch 58, an EP-ROM write controller 59, and an EP-ROM read controller 60 are connected to the system bus 52. The programming ROM block 54 stores various types of system programs and a test program 54a for testing the function of the IC card 11. The system controller 55 has a judgment area 55a therein. The system controller 55 supplies operation instructions a to i to respective circuits in response to a data reception signal from the interface 51 and in accordance with the operating conditions of the respective circuits. The EP-ROM write controller 59 controls the write operation of the EP-ROM 61 in accordance with an instruction from the system controller 55. The EP-ROM 61 is a memory to which data can be written only once and which comprises a programmable memory which has three memory areas 61a, 61b and 61c. The memory area 61a stores the codes &#34;CA&#34;, &#34;IPIN&#34;, &#34;PAN&#34;, &#34;CHN&#34;, &#34;EPD&#34;, &#34;PRK&#34; and &#34;RTN&#34;. The memory area 61b stores the codes &#34;PMK&#34;, &#34;IPIN&#34; and &#34;PIN&#34;. The memory area 61c has flags of &#34;Select 1&#34;, &#34;Select 2&#34; and &#34;Invalid&#34;. The code &#34;CHN&#34; stored in the memory area 61a represents a &#34;card holder&#39;s name&#34;. The code &#34;EPD&#34; represents an &#34;Expiration Date&#34;. The code &#34;RTN&#34; represents the number of reentry operations when wrong data is entered. A plurality of memory area portions are provided for the code &#34;RTN&#34; to reenter the data a plurality of times. The &#34;Select 1&#34;, &#34;Select 2&#34; and &#34;Invalid&#34; flags stored in the memory area 61c are initially set at logic &#34;1&#34;. When a control signal i1 is supplied from the system controller 55 to the EP-ROM write controller 59, the EP-ROM write controller 59 sends out data onto a data bus DB1 for the memory areas 61b and 61c. However, when a control signal i2 is supplied from the system controller 55 to the EP-ROM write controller 59, the controller 59 sends out data onto a data bus DB2 for the memory area 61a. The codes &#34;IPIN&#34; and &#34;PIN&#34; stored in the memory area 61b are selected by a first selector 62 and are supplied to a second selector 63. The code &#34;PMK&#34; stored in the memory area 61b is read out and supplied to the second selector 63. The first and second selectors 62 and 63 are selectively operated in accordance with the logical states of the flags &#34;Select 1&#34; and &#34;Select 2&#34;. More particularly, when the &#34;Select 1&#34; flag is set at logic &#34;1&#34;, the first selector 62 selects the code &#34;IPIN&#34;. However, when the &#34;Select 1&#34; flag goes to logic &#34;0&#34;, the first selector 62 selects the code &#34;PIN&#34;. Similarly, when the &#34;Select 2&#34; flag is set at logic &#34;1&#34;, the second selector 63 selects the code &#34;PMK&#34;; but when the &#34;Select 2&#34; flag goes to logic &#34;0&#34;, the second selector 63 selects the output from the first selector 62. An output from the second selector 63 together with data held by the data latch 57 is supplied to a comparator 64. The comparator 64 compares the output from the second selector 63 and the data from the data latch 57 in response to the control signal h from the system controller 55. A comparison result is supplied to an OR gate 65 and the system controller 55. The OR gate 65 also receives cancel data Can from the cancel latch 58. An output from the OR gate 65 is supplied to an AND gate 66. The OR gate 65 is controlled in accordance with the logical state of the &#34;Invalid&#34; flag held in the memory area 61c. The output from the OR gate 65 is supplied as an enable signal to the EP-ROM write controller 59 and the EP-ROM read controller 60. The EP-ROM read controller 60 reads out data from the memory area 61a in the EP-ROM 61 in response to the instruction from the system controller 55. The readout data is supplied to the system bus 52 or the ALU 56. The ALU 56 is provided for performing the decryption based on &#34;RSA&#34; algorithm and decrypts the input data in response to the instruction d from the system controller 55, and the decrypted data is sent onto the system bus 52. 
     The circuit arrangement of the POS terminal 41 will be described with reference to FIG. 4. Referring to FIG. 4, reference numeral 71 denotes a system bus. A sound controller 72, a working RAM 73, a system programming ROM 74, a data ROM 75 for storing test messages, a main controller 76, a key controller 77, a display driver/controller 78, a card reader driver/controller 79, an IC card interface 80, a comparator 81, an &#34;RSA&#34; encrypter 82, a latch 83 for latching the code &#34;CA&#34;, a &#34;DES&#34; encrypter 84, a &#34;DES&#34; decrypter 85, and a communication controller 86 are connected to the system bus 71. The encrypter 82 is the &#34;RSA&#34; type for performing encryption based on the &#34;RSA&#34; algorithm. The encrypter 84 encrypts data based on &#34;Data Encryption Standard&#34;. A loudspeaker 87 is connected to the sound controller 72 so as to generate an alarm sound as needed. The working RAM 73 has memory areas 73a, 73b, 73c and 73d which respectively store an &#34;on-line flag&#34;, a &#34;PAN&#34;, a &#34;CHN&#34;  and an &#34;EPD&#34;. The main controller 76 is connected to the IC card interface 80, the comparator 81, the communication controller 86 and the like and supplies control instructions to the respective circuits in accordance with the operating state of the system. The key controller 77 supplies a key sampling signal to the keyboard 43 to detect a key input signal. The display driver 78 performs display control on the display panel 44. The card reader driver/controller 79 controls a card reader mechanism 88. The card reader mechanism 88 has a card feed motor 88M to feed to a predetermined position the IC card 11 inserted from the card insertion port 42. The card reader mechanism 88 also causes the processed IC card 11 to return to the card insertion port 42. The IC card interface 80 controls data exchange between the POS terminal 41 and the IC card 11 in response to an instruction from the main controller 76. The interface 80 transmits data from the IC card 11 to the system bus 71 and the comparator 81. The interface 80 also transmits encrypted data from the encrypter 82 to the IC card 11. The encrypter 82 receives the data supplied from the data ROM 75 through the system bus 71 and encrypts the data in accordance with the public key code supplied from a public key code memory 89 consisting of a data ROM for the issuer. 
     The public key code is a code in one-to-one correspondence with &#34;PRK&#34; stored in the IC card at the issuer 2 and is provided for the encryption based on the RSA-algorithm. While, the &#34;PRK&#34; is a code for the decryption based on the RSA-algorithm. The public key code and the &#34;PRK&#34; are key codes selected to have a one-to-one relation by predetermined one-way functions based on the RSA-algorithm. According to this encryption method based on the RSA-algorithm, data encrypted by the public key data can hardly be decrypted by the same public key code. It is only possible to decrypt by the &#34;PRK&#34; having the relation provided by the one-way functions. This encryption method based on the RSA-algorithm is described in detail in the &#34;CRYPTOGRAPHY&#34; by Carl H. Meyer and Stephen M. Matyas, published in 1982, by John Wiley &amp; Sons, Inc. 
     In a public key code memory 89 in the POS terminal 41, public key codes whose number corresponds to the number of issuers or the sorts of &#34;PRK&#34; may be stored. Assuming now that IC cards manufactured by a manufacturer 1 are distributed to twenty issuers 2, twenty &#34;PRK&#34; codes are determined at the issuer 2. Public key codes corresponding to the &#34;PRK&#34; codes are communicated to a manufacturer of the terminal. The terminal and the manufacturer set the twenty public key codes communicated from twenty issuers to the public key memory 89 of the terminal 41. The data ROM in the public key code memory 89 has an internal configuration as shown in FIG. 12. One of public key codes such as &#34;public 1&#34;, &#34;public 2&#34;, . . . &#34;public 20&#34; can be determined by an issuer code included in the &#34;PAN&#34; code capable of reading from the IC card 11. 
     In the public key code memory 89 are preset public key codes corresponding to the &#34;PRK&#34; in the IC card 11. The public key code memory 89 generates a storage code when it receives an instruction from the main controller 76. When a destructive signal is supplied to the memory 89, the storage content is automatically destroyed. The destructive signal is supplied from the main controller 76 to the memory 89 when the access of the memory 89 by, for example, the POS terminal 41 is invalid. The public key code corresponding to the respective issuers stored in the public key code memory 89 cannot be externally read out. The code &#34;CA&#34; latched by the latch 83 is supplied to the &#34;DES&#34; encrypter and decrypter 84 and 85. The &#34;DES&#34; encrypter 84 receives predetermined data through the system bus and performs encryption processing in response to an instruction from the main controller 76. The encrypted code is then supplied to the communication controller 86. When the communication controller 86 is on-line connected with a data base, i.e., the host computer, the controller 86 sends the encrypted base to the host computer. The communication controller 86 also sends out onto the system bus 71 data which is supplied from the host computer and which is decrypted by the &#34;DES&#34; decrypter 85. 
     The operation of the circuit shown in FIG. 4 will be described with reference to flow charts. First, the operation for issuing the IC card 11 from the manufacturer 1 to the issuer 2 will be described. As shown in FIG. 1, the manufacturer 1 loads the IC card 11 in the IC card issuing machine 12. The manufacturer 1 enters a start instruction and a circuit test instruction at the keyboard 14. When the start instruction is supplied to the IC card 11 from the IC card issuing machine 12, the operation is started, as shown in FIG. 5. In step A1 shown in FIG. 5, a signal of logic &#34;1&#34; is written in the cancel latch 58 shown in FIG. 3. The cancel signal Can (&#34;1&#34;) latched by the cancel latch 58 is supplied to the AND gate 66 through the OR gate 65. The output from the comparator 64 is cancelled in response to the cancel signal Can. The &#34;Invalid&#34; flag in the memory area 61c in the EP-ROM 61 is set at logic &#34;1&#34;, so that an output signal from the OR circuit 65 goes to logic &#34;1&#34; and an enable signal is supplied to the EP-ROM write controller 59 and the EP-ROM read controller 60. In step A2 in FIG. 5, the system controller 55 checks whether or not the test command is entered. If YES in step A1, the flow advances to step A3. In step A3, the circuit test operation is started. More particularly, the test program 54a is read out from the programming ROM block 54, and the circuit test is performed. When the circuit test is completed, the test result is supplied to the IC card issuing machine 12 in step A4. The test result is displayed on the display panel 15 so as to signal the result to the operator. A control signal i2 is supplied from the system controller 55 to the EP-ROM write controller 59 in step A5. When the EP-ROM write controller 59 receives the control signal i2, the controller 59 selects the data bus DB2. On the other hand, when the test result is displayed on the display panel 15 and the operator does not notice any failure, the operator enters codes &#34;CA&#34;, &#34;IPIN&#34;, at the keyboard 14 in step A6. In this case, the EP-ROM write controller 59 selects the data bus DB2 as described above, and the data entered at the keyboard 14 is written in the memory area 61a. In this case, other storage contents in the memory area 61a are held at logic &#34;0&#34;. When data writing is completed, the flow advances to step A7, and the system controller 55 supplies the control signal i1 from the system controller 55 to the EP-ROM write controller 59. As a result, the EP-ROM write controller 59 selects the data bus DB1. In this state, the operator enters the codes &#34;PMK&#34; and &#34;IPIN&#34; at the keyboard 14 in step A8. Since the EP-ROM write controller 59 has selected the data bus DB1, the input data is written in the memory area 61b in the EP-ROM 61. The code &#34;PMK&#34; entered at the keyboard 14 is supplied to the printer 16 and is printed on the paper sheet 17. Thereafter, in step A9, data of logic &#34;0&#34; is written in the cancel latch 58, thereby completing the issuing operation of the IC card 11 by the manufacturer 1. The manufacturer 1 separately seals the IC card 11 having the predetermined code and the paper sheet 17 printed with the code &#34;PMK&#34;. The IC card 11 and the paper sheet 17 are then separately sent to the issuer 2. 
     When the issuer 2 receives the IC card 11 and the paper sheet 17 with the code &#34;PMK&#34; from the manufacturer 1, the issuer 2 loads the IC card 11 in the IC card issuing machine 22, as shown in FIG. 1. The code &#34;PMK&#34; is then entered at the keyboard 24. When the IC card 11 having the arrangement described in detail with reference to FIG. 3 is loaded in the IC card issuing machine 22, the operation is performed in accordance with the flow chart shown in FIG. 6. In step B1, the control signal i2 is supplied from the system controller 55 to the EP-ROM write controller 59. The EP-ROM write controller 59 selects the data bus DB2. In step B2, the system controller 55 checks whether or not the data is entered at the keyboard 24. When the data is entered at the keyboard 24, the interface 51 supplies a data reception signal to the system controller 55. The system controller 55 checks whether or not the data is entered at the keyboard 24 in accordance with the presence/absence of the data reception signal. If YES in step B2, the system controller 55 supplies a latch instruction to the data latch 57. In step B3, the input data from the keyboard 24 is latched in the data latch 57. When the system controller 55 causes the data latch 57 to latch the key input data, the system controller 55 supplies the control signal h to the comparator 64 in step B4. The comparator 64 compares the data latched by the data latch 57 with the code &#34;PMK&#34; stored in the memory area 61a in the EP-ROM 61 in step B5. Since the &#34;Select 2&#34; flag in the memory area 61c in the EP-ROM 61 is set at logic &#34;1&#34;, the second selector 63 selects the code &#34;PMK&#34; held in the memory area 61b. The selected code &#34;PMK&#34; is supplied to the comparator 64. For this reason, when the comparator 64 receives the operation instruction from the controller 55, the comparator 64 compares the code &#34;PMK&#34; selected by the second selector 63 with the key input data latched by the data latch 57. The comparison result of the comparator 64 is supplied to the system controller 55. When a coincidence signal is not generated from the comparator 64, the system controller 55 writes data of logic &#34;1&#34; in the cancel latch 58 in step B6 so as to generate the cancel signal Can. As a result, an output signal from the OR gate 65 is set at logic &#34;1&#34;, and this output is supplied to the AND gate 66. In this case, the flag &#34;Invalid&#34; in the memory area 61c is set at logic &#34;1&#34;, so that an output from the AND gate 66 is set at logic &#34;1&#34;. As a result, an enable signal is supplied to the EP-ROM write controller 59 and the EP-ROM read controller 60. The system controller 55 supplies the control instruction to the EP-ROM write controller 59. In step B7, the count of the code &#34;RTN&#34; stored in the memory area 61a in the EP-ROM 61 is incremented by one. Subsequently, the system controller 55 causes the EP-ROM read controller 60 to transfer the code &#34;RTN&#34; from the memory area 61a to the judgment area 55a. In step B9, the cancel latch 58 is reset. In step B10, the system controller 55 checks whether or not the count of the code &#34;RTN&#34; in the judgment area 55a has reached 5. If NO in step B10, the flow returns to step B2, and the above operation is repeated. Even if the above operation is repeated, and the coincidence signal is not generated but the count of the code &#34;RTN&#34; has reached 5, the judgment result in step B10 becomes YES. The flow advances to step B11, and the flag &#34;Invalid&#34; in the memory area 61c is reset to logic &#34;0&#34;. In step B12, the invalid signal is supplied to the IC card issuing machine 22 so as to signal to the operator that the IC card 11 has become invalid. The above operation is performed to confirm that the issuer 2 knows the proper code &#34;PMK&#34;, i.e., to check the validity of the issuer 2. 
     When the proper code &#34;PMK&#34; is entered at the keyboad 24, the comparator 64 generates the coincidence signal which is then supplied to the system controller 55 and to the AND gate 66 through the OR gate 65. As a result, the judgment result in step B5 becomes YES, and the flow advances to step B13. In step B13, the count of the code &#34;RTN&#34; stored in the memory area 61a in the EP-ROM 61 is reset to zero. In other words, when the coincidence output from the comparator 64 is supplied to the AND gate 66 through the OR gate 65, data of the flag &#34;Invalid&#34; (&#34;1&#34;) in the memory area 61c is supplied to the EP-ROM write controller 59 and the EP-ROM read controller 60, thereby starting the EP-ROM write controller 59 so as to reset the count of the code &#34;RTN&#34; in the memory 61a at &#34;0&#34; in accordance with the control instruction from the system controller 55. This resetting operation of the code &#34;RTN&#34; is performed by address updating in step B7 wherein an address is incremented from that for the memory area with data to that for a memory area without data. In this state, the operator enters the codes &#34;PAN&#34;, &#34;CHN&#34;, &#34;PRK&#34; and &#34;EPD&#34; at the keyboard 24. The key input data is written by the EP-ROM write controller 59 in the memory area 61a in the EP-ROM 61 in step B14. In step B15, the codes &#34;PAN&#34;, &#34;CA&#34;, &#34;CHN&#34; and &#34;EPD&#34; are read out from the memory area 61a and are suplied to the IC card issuing machine 22. These codes are encrypted and are supplied to the host computer through the signal line. The encrypted codes are thus registered in the data base. As shown in step B16, the code &#34;IPIN&#34; is read out by the EP-ROM read controller 60 from the memory area 61a and is supplied to the IC card issuing machine 22. The code &#34;IPIN&#34; is printed on the paper sheet 27. Thereafter, the flag &#34;Select 2&#34; in the memory area 61 c in the EP-ROM 61 is set at logic &#34;0&#34; in step B17, and the access of the code &#34;PMK&#34; in the memory area 61b is inhibited. The issuing operation of the IC card 11 at the issuer 2 is completed. The issuer 2 separately seals the IC card 11 having the predetermined data and the paper sheet 27 printed with the code &#34;IPIN&#34;. The IC card 11 and the paper sheet 27 with the code &#34;IPIN&#34; are separately sent to the card holder 3. 
     When the card holder 3 receives the IC card 11 and the paper sheet 27 with the code &#34;IPIN&#34;, he goes to the issuer 2. The card holder 3 then writes the code &#34;PIN&#34; in this own IC card 11 by using the IC card issuing machine 32 installed on the issuer&#39;s premises. The card holder 3 inserts the IC card 11 from the card insertion port 33 in the IC card issuing machine 32, and enters the code &#34;IPIN&#34; printed on the paper sheet 27 at the keyboard 34. The IC card 11 loaded in the IC card issuing machine 32 performs the operation in accordance with the flow chart shown in FIG. 7. The IC card 11 having the arrangement described in detail with reference to FIG. 3 causes the system controller 55 to supply the control signal i2 to the EP-ROM write controller 59 so as to select the data bus DB2 in step C1. In step C2, the system controller 55 then checks whether or not the data is entered at the keyboard 34. The system controller 55 checks the presence/absence of key input data in accordance with the presence/absence of the data reception signal from the interface 51. If YES in step C2, the system controller 55 supplies a latch instruction to the data latch 57. In step C3, the input data from the keyboard 34 is latched by the data latch 57. When the key input data is latched by the data latch 57, the system controller 55 supplies the control signal h to the comparator 64 in step C4. The comparator 64 compares the data latched by the data latch 57 with the code &#34;IPIN&#34; stored in the memory area 61b in the EP-ROM 61. More particularly, since the flag &#34;Select 1&#34; in the memory area 61c in the EP-ROM 61 is initially set at logic &#34;1&#34;, the first selector 62 selects the code &#34;IPIN&#34; stored in the memory area 61b. The code &#34;IPIN&#34; is then supplied to the second selector 63. Although the second selector 63 selects the input data in response to the logic state of the flag &#34;Select 2&#34; in the memory area 61c, the flag &#34;Select 2&#34; is set by the issuer 2 at logic &#34;0&#34;, so that the second selector 63 selects the code &#34;IPIN&#34; from the memory area 61b, and the code &#34;IPIN&#34; is supplied to the comparator 64. When the comparator 64 receives the operation instruction h from the system controller 55, the comparator 64 compares the code &#34;IPIN&#34; selected by the first and second selectors 62 and 63 with the key input data latched by the data latch 57. A comparison result from the comparator 64 is supplied to the system controller 55. When a coincidence signal is not generated from the comparator 64, the system controller 55 writes data of logic &#34;1&#34; in the cancel latch 58 in step C6, thereby generating the cancel signal Can. As a result, an output from the OR gate 65 is set at logic &#34;1&#34;, and this signal of logic &#34;1&#34; is supplied to the AND gate 66. In this case, the flag &#34;Invalid&#34; in the memory area 61c is set at logic &#34;1&#34;, so that the output from the AND gate 66 goes to logic &#34;1&#34;, and an enable signal is supplied to the EP-ROM write controller 59 and the EP-ROM read controller 60. Subsequently, the system controller 55 supplies the control instruction to the EP-ROM write controller 59, and the count of the code &#34;RTN&#34; stored in the memory area 61a in the EP-ROM 61 is incremented by one in step C7. The system controller 55 causes the EP-ROM read controller 60 to transfer the code &#34;RTN&#34; from the memory area 61a to the judgment area 55a in step C8. Thereafter, in step C9, the content of the cancel latch 58 is reset. In step C10, the system controller 55 checks whether or not the count of the code &#34;RTN&#34; has reached 5. If NO in step C10, the flow returns to step C2, and the same operation as described above is repeated. If the above operation is repeated, and the coincidence signal is not generated from the comparator 64 but the count of the code &#34;RTN&#34; has reached 5, the judgment result in step C10 becomes YES, and the flow advances to step C11. In step C11, the flag &#34;Invalid&#34; in the memory area 61c is reset at logic &#34;0&#34;. In step C12, the invalid signal is supplied to the IC card issuing machine 32 so as to signal to the card holder 3 that the IC card 11 has become invalid. The above operation is performed to confirm that the card holder 3 knows the proper code &#34;IPIN&#34;, i.e., to check the validity of the card holder 3. 
     When the card holder 3 enters the proper code &#34;IPIN&#34;, the comparator 64 generates the coincidence signal so that the judgment result in step C5 becomes YES. In step C13, the count of the code &#34;RTN&#34; stored in the memory area 61a in the EP-ROM 61 is reset at zero. In step C14, the system controller 55 supplies the control signal i1 to the EP-ROM write controller 59 to select the data bus DB1. On the other hand, the card holder 3 enters any PIN code at the keyboard 34 after the code &#34;IPIN&#34; is entered. The input code &#34;PIN&#34; is written by the EP-ROM write controller 59 in the memory area 61b in the EP-ROM 61. Thereafter, the system controller 55 causes the EP-ROM write controller 59 to set the flag &#34;Select 1&#34; (in the memory area 61c in the EP-ROM 61) at logic &#34;1&#34;. The issuing operation of the IC card 11 is completed, and the IC card 11 thus can be used. 
     The identification operation at the POS terminal 41 will be described when the card holder 3 uses the IC card 11. When the card holder 3 uses the IC card 11, he inserts the IC card 11 from the card insertion port 42 in the POS terminal 41 of FIG. 2 and enters the code &#34;PIN&#34; registered in the IC card 11 at the keyboard 43. When the IC card 11 is loaded in the IC card issuing machine 32, the operation will be performed in accordance with the flow chart of FIG. 8. The IC card 11 having the arrangement described in detail with reference to FIG. 3 causes the system controller 55 to supply the control signal i2 to the EP-ROM write controller 59 so as to select the data bus DB2, in step D1. The system controller 55 then checks in step D2 whether or not data is entered from the keyboard 34. The system controller 55 checks the presence/absence of the data entered at the keyboard 34 in accordance with the presence/absence of a data reception signal from the interface 51. If YES in step D2, the system controller 55 supplies a latch instruction to the data latch 57, and the input data from the keyboard 34 is latched by the data latch 57 in step D3. When the key input data is latched by the data latch 57, the system controller 55 supplies the control signal h to the comparator 64 in step D3. When the key input data is latched by the data latch 57, the system controller 55 supplies the control signal h to the comparator 64 in step D4. In step D5, the comparator 64 compares the data latched by the data latch 57 with the code &#34;PIN&#34; stored in the memory area 61b in the EP-ROM 61. Since both the flags &#34;Select 1&#34; and &#34;Select 2&#34; in the memory area 61c in the EP-ROM 61 are set at logic &#34;0&#34;, the code &#34;PIN&#34; stored in the memory area 61b is selected and supplied to the comparator 64. When the comparator 64 receives the control signal h from the system controller 55, the comparator 64 compares the code &#34;PIN&#34; selected by the first and second selectors 62 and 63 with the key input data latched by the data latch 57. A comparison result is supplied to the system controller 55. When a coincidence signal is not generated from the comparator 64, the system controller 55 writes data of logic &#34;1&#34; in the cancel latch 58 in step D6 so as to generate the cancel signal Can. As a result, an output from the OR gate 65 is set at logic &#34;1&#34;, and is supplied to the AND gate 66. When the IC card 11 is normal, the flag &#34;Invalid&#34; in the memory area 61c is set at logic &#34;1&#34;, so that an output from the AND gate 66 becomes logic &#34;1&#34; to supply an enable signal to the EP-ROM write controller 59 and the EP-ROM read controller 60. The system controller 55 supplies the control signal to the EP-ROM write controller 59. In step D7, the count of the code &#34;RTN&#34; stored in the memory area 61a in the EP-ROM 61 is incremented by one. Subsequently, the system controller 55 causes the EP-ROM read controller 60 to transfer the code &#34;RTN&#34; from the memory area 61a to the judgment area 55a. Thereafter, in step D9, the content of the cancel latch 58 is reset. Subsequently, the system controller 55 checks in step D10 whether or not the count of the code &#34;RTN&#34; has reached 5. If NO in step D10, the flow advances to step D12, wherein the system controller 55 supplies a Bad signal to the POS terminal 41. The display panel 44 then displays that the input &#34;PIN&#34; code is wrong. Even if the above operation is repeated and the coincidence signal is not generated from the comparator 64 but the count of the code &#34;RTN&#34; has reached 5, the judgment result in step D10 becomes YES. The system controller 55 then supplies the invalid signal to the POS terminal 41, and the flow returns to step D2. When the POS terminal 41 receives the Bad signal from the IC card 11 in step D12, the POS terminal 41 signals to the card holder 3 that the IC card 11 has become invalid to be described in detail later. The above operation is made to confirm that the card holder 3 knows the right code &#34;IPIN&#34;, i.e., to check the validity of the card holder 3. 
     When the card holder 3 enters the right code &#34;PIN&#34;, the judgment result in step D5 becomes YES. The system controller 55 supplies an OK signal to the POS terminal 41 in step D13. In step D13, the system controller 55 waits for the encrypted data from the POS terminal 41. When the POS terminal 41 receives the OK signal from the IC card 11, the POS terminal 41 decrypts the test message to be described in detail later. The encrypted data is supplied to the IC card 11. When the IC card 11 receives the encrypted data from the POS terminal 41, the flow advances from step D14 to step D15, and the encrypted data is supplied to the ALU 56. The system controller 55 causes the EP-ROM read controller 60 to read out the code &#34;PRK&#34;  from the memory area 61a in the EP-ROM 61, and the readout code and the operation instruction d are supplied to the ALU 56. The ALU 56 is started to decrypt the encrypted data from the POS terminal 41 in accordance with the code &#34;PRK&#34;. The decrypted result is supplied to the POS terminal 41 in step D18. The operation at the side of the IC card 11 is completed. 
     The POS terminal 41 having the arrangement described in detail with reference to FIG. 4 performs the operation in accordance with the flow chart in FIG. 9 when the IC card 11 is inserted in the card insertion port 42. When the IC card 11 is inserted in the card insertion port 42, the POS terminal 41 detects the IC card 11, and the main controller 76 supplies an operation instruction to the card reader driver/controller 79. In step E1, the IC card 11 is conveyed by the card reader mechanism 88 to a predetermined position. The main controller 76 waits until the code &#34;PIN&#34; is entered at step E2. When the code &#34;PIN&#34; is entered, the code is supplied to the IC card 11 through the IC card interface 80 in step E3. Thereafter, in step E4, the main controller 76 waits until a response signal is received in step D12 or step D13 in FIG. 8. When the response signal from the IC card 11 is supplied to the main controller 76, the controller 76 checks in step E5 whether or not the response signal is the OK signal. If NO in step E5, the flow returns to step E2, and the above operation is repeated. When the OK signal is supplied from the IC card 11 to the main controller 76, the main controller 76 reads out the test message from the data ROM 75 in step E6. The test message is supplied to the &#34;RSA&#34; encrypter 82. At the same time PAN is read from the IC card 11 and is determined the public key code corresponding to IC card 11 from the public key code memory 89 by the issuer code included in the PAN thus read out. In step E7, the main controller 76 supplies an operation instruction c to the &#34;RSA&#34; encrypter 82. The &#34;RSA&#34; encrypter 82 is started to encrypt the test message in accordance with the determined public key code from the public key code memory 89. The encrypted data is supplied to the IC card 11 in step E8. The IC card 11 detects the encrypted data in step D14 in FIG. 8, and the encrypted data is decrypted in step D18, and the decrypted data is supplied to the POS terminal 41. The POS terminal 41 keeps waiting in step E9 until the decrypted data is supplied from the IC card 11. When the decrypted data is received by the POS terminal 41, the flow advances to step E10. In step E10, the main controller 76 sends the decrypted data to the comparator 81. Subsequently, in step E11, the main controller 76 reads out the test message from the data ROM 75, and the readout test message is supplied to the comparator 81. The main controller 76 supplies the operation instruction d to the comparator 81 in step E12, so that the comparator 81 is started. The comparator 81 compares the decrypted data from the IC card and the test message stored in the data ROM 75. A comparison result is supplied to the main controller 76. The main controller 76 detects in step E13 whether or not a coincidence signal is generated from the comparator 81. When the comparator 81 does not generate the coincidence signal, the flow advances to step E14. In step E14, the invalid message from the IC card 11 is supplied to the display driver/controller 78 which causes the display panel 44 to display the invalid message. Subsequently, in step E15, the main controller 76 supplies the operation instruction to the sound controller 72 to produce an alarm at the loudspeaker 87. Thereafter, the main controller 76 supplies the operation instruction to the card reader driver/controller 79 in step E16, thereby dispensing the IC card 11 from the card insertion port 42 by means of the card reader mechanism 88. However, when the coincidence signal is generated from the comparator 81, the judgment result in step E13 becomes YES, and the flow advances to step E17. The main controller 76 checks in step E7 whether or not the on-line flag is set. If NO in step E17, the flow advances to step E18. The OK message is displayed on the display panel 44 to complete identification operation for the IC card 11. However, if YES in step E17, an on-line identification shown in the flow chart of FIG. 10 is performed. 
     In step E21 in FIG. 10, the code &#34;CA&#34; stored in the memory area 61a in the EP-ROM 61 is supplied from the IC card 11 to the POS terminal 41. The code &#34;CA&#34; is written in the latch 83 in step E22. The codes &#34;PAN&#34;, &#34;CHN&#34; and &#34;EPD&#34; stored in the memory area 61a in the EP-ROM 61 of the IC card 11 are read out therefrom in step E23, and are stored in the working RAM 73 in step E24. In step E25, the code &#34;PAN&#34; is read out from the working RAM 73 and is supplied to the host computer through the on-line transmission line under the control of the communication controller 86. The main controller 76 then reads out the codes &#34;PAN&#34;, &#34;CHN&#34; and &#34;EPD&#34; from the working RAM 73 in step E26, and these codes are supplied to the &#34;DES&#34; encrypter 84. The &#34;DES&#34; encrypter 84 is started in response to the operation instruction e to encrypt the data from the working RAM 73 in accordance with the code &#34;CA&#34; held by the latch 83. The encrypted data are supplied to the host computer in step E28. When the host computer receives the encrypted data from the POS terminal 41 to be described later, the host computer decrypts the encrypted data. The host computer then sends back the OK message or the invalid message to the POS terminal 41 in accordance with the decrypted result. The POS terminal 41 is kept waiting in step E29 until the encrypted data is send back from the host computer, the encrypted data is supplied from the communication controller 86 to the &#34;DES&#34; decrypter 85 in step E30. Subsequently, the main controller 76 supplies an operation instruction f in step E31 to the &#34;DES&#34; decrypter 85 in step E31. The encrypted data is decrypted by the &#34;DES&#34; decrypter 85 in accordance with the code &#34;CA&#34; stored in the latch 83. The decrypted result is displayed on the display panel 44 in step E32. Thereafter, in step E33, the main controller 76 checks whether or not the decrypted data comprises the OK message. If YES in step E33, the operation is ended. However, if NO in step E33, the IC card 11 is dispensed from the card insertion port 42 in step E34. 
     On the other hand, when data is transmitted from the POS terminal 41 to the host computer, the host computer performs the operation in accordance with the flow chart in FIG. 11. In step F1, the host computer receives the code &#34;PAN&#34; from the POS terminal 41. In step F2, the host computer performs search operation throughout a file. The host computer reads out the code &#34;CA&#34; corresponding to the code &#34;PAN&#34;. Thereafter, in step F4, when the host computer receives the encrypted data from the POS terminal 41, the encrypted data is decrypted in accordance with the code &#34;CA&#34;. In step F6, the codes &#34;PAN&#34;, &#34;CHN&#34; and &#34;EPD&#34; in the decrypted data are compared with the codes &#34;PAN&#34;, &#34;CHN&#34; and &#34;EPD&#34; in a file corresponding to the code &#34;CA&#34;. The host computer checks in step F7 whether or not their coincidence is established. If YES in step F7, the flow advances to step F8, and the OK message is encrypted by the code &#34;CA&#34;. However, if NO in step F7, the flow advances to step F9, and the invalid message is encrypted by the code &#34;CA&#34;. When the operation in step F8 or F9 is completed, the encrypted data is supplied from the host computer to the POS terminal 41. The POS terminal 41 decrypts the encrypted data from the host computer. The decrypted content is displayed as a result representing of the validity or invalidation of the IC card 11. In this manner, all identification operations are ended. 
     Throughout the above description, it is stated that the printed papers with the &#34;PMK&#34; and &#34;IPIN&#34; codes thereon are sent separately to the issuer and card holder, respectively. Preferably, these codes are printed in sealed mailers of the type in which the contents are not known until the sealed mailers are opened. Such mailers are well known in the art. This prevents access to the &#34;PMK&#34; and &#34;IPIN&#34; codes by intermediaries in the issuance procedures, and increases security. 
     At issuance of the IC card by the issuer, in addition to the &#34;PAN&#34; code, the issuer preferably enters other data such as account name, expiration date, use limitation, etc., or any combination of these data items, as desired. 
     In the foregoing description, codes such as &#34;PAN&#34;, &#34;CA&#34; and &#34;IPIN&#34; are input by manual keyboard operation. Alternatively, this information can be input automatically by a data processing system. The code &#34;CA&#34; can be randomly generated by a random data generator and automatically input into the IC card 11. At the issuer station 2, the code &#34;PAN&#34; can be pre-set in the issuer&#39;s data bank, and can be read out from the issuer&#39;s data bank, and automatically stored in the IC card 11. This would eliminate the necessity of the operator keying in the &#34;PAN&#34; at the keyboard 24 of the issuing machine 22. Also, at the time of issuance, the code &#34;CA&#34; can be automatically loaded into the issuer&#39;s data base after entry of the &#34;PMK&#34; code. In another modification, the &#34;PMK&#34; code can be written into a card, such as an IC card, which can be sent from the manufacturer to the issuer, and the card can be inserted into a card issuing machine, such as machine 22. At that point, the &#34;PMK&#34; code in the card can be automatically set into the machine 22 for comparison with the &#34;PMK&#34; code already stored in the IC card 11. This eliminates the necessity of manual insertion of the &#34;PMK&#34; code at the keyboard 24, and also increases security since an operator will not know the &#34;PMK&#34; code. Issuing a separate card with a &#34;PMK&#34; code stored therein is efficient since the &#34;PMK&#34; code is used for batches of IC cards 11. Since the &#34;IPIN&#34; code generated by the card holder is unique to an individual card, it is not efficient to use a separate card to store the &#34;IPIN&#34; code, and it is more efficient to generate the &#34;IPIN&#34; code on paper, such as in a sealed, secret type mailer. 
     When the IC card 11 is used in a transaction, such as purchasing items at a merchant store, obtaining cash advances from a bank, etc., the transaction data transmitted to the issuer after the identification process is completed is transmitted in encrypted form by using the &#34;CA&#34; code as the key for the &#34;DES&#34; encryption. At this time, during sending of transaction data to the issuer, the &#34;PAN&#34; code is not encrypted in a preferred arrangement. The &#34;PAN&#34; code is received by the issuer, and the issuer&#39;s data bank retrieves the information corresponding to the &#34;PAN&#34; code, such as the &#34;CA&#34; code and any other pertinent information, as desired. After the &#34;CA&#34; code is retrieved from the issuer&#39;s data bank, it is used as a key for &#34;DES&#34; decryption of the transaction data. After decryption of the transmitted transaction data, the issuer sends a response message to the terminal issuing the transaction data which could be a positive or negative response, depending upon whether or not the information has been correctively received, whether or not the user&#39;s credit line is exceeded, or any other established criteria. The response from the issuer is also preferably encrypted using the &#34;CA&#34;  code as the key for &#34;DES&#34; encryption. At the receiving terminal, the response signal is decrypted using the &#34;CA&#34; code from the user&#39;s card as the decryption key. Thus, the transaction is completed and the issuer uses the transaction data in the normal manner. 
     While the invention has been described above in connection with specific implementations, it should be clear that various modifications and alterations can be made within the scope of the appended claims.