Pseudo-random binary sequency generator
This is a continuation of application Ser. No. 562,384, filed Dec. 16, 1983, now abandoned. 
    
    
     The present invention relates to a pseudo-random binary sequence generator applicable to the digital coding of television pictures. 
     The principle of the digital coding of television pictures consists in making a cutting in each scanning line at a randomly addressable point, and rotating the segments located on both sides of the cutting point. This digital coding principle was described in the French patent application No. 78 21 888 filed on 20th July 1978 in the name of the French Public Broadcasting Corporation &#34;Telediffusion de France&#34; relating to its application to a black and white video signal or a composite colour signal with frequency-division multiplexing of the SECAM, PAL and NTSC type, for example. The French patent application No. 82 15 533 filed on 14th Sept. 1982 in the name of the company La Radiotechnique describes a novel application of this principle to a video colour signal with time-division multiplexing of analog components, of the type MAC, for example. In this latter case the different components are treated separately, that is to say each are separately subjected to the operations of cutting and permutation. The addresses of the cutting points to be supplied must therefore be equal in number to the number of components: two in the case of MAC coding (the luminance Y and, alternatively, one or other of the colour difference components U and V), three in the case where the three components Y, U and V, etc. are transmitted with each line. 
     The addresses of the cutting points are supplied by a pseudo-random binary sequence generator operating with a clock having the line frequency and thus varying pseudo-randomly from one line to the next. Identical generators are used at the transmitting and the receiving ends, and synchronization between transmission and reception can take place either with each frame or after a certain whole number of frames (every 50 frames for example, that is to say every second in Europe), a synchronization pulse being sent out by the transmitter in a particular picture line (the last line of a frame for example) or by way of data transmission during the picture blanking periods (see the systems Teletext, DIDON, etc.). The generators used for transmission and reception are initialized by a starting key, comprising a certain number n d  of bits, and the user may either buy this key directly in the form of a passive key pad, or buy the means of decoding a coded key sent out by the transmitter by way of data transmission. The latter solution makes it possible to change the key as often as one wishes and thus gives a system with greater security but it implies at the receiving end the use of an active initialization circuit using a passive or active access card (memory-type or micro-processor). 
     In endeavouring to realize a television picture coding system it is very important to take into account the properties of the eye in regard to the recognition of shapes. It is found, for example, that if the picture lines are shifted in relation to each other by less than one cm in the case of a picture with a total width of 52 cm (which is the width of present television sets using cathode ray tubes with a screen diagonal of 66 or 67 cm), the picture is perfectly interpretable and only appears as slightly fuzzy when it is viewed from a sufficient distance. If on the other hand the cutting addresses are such that the line shifts which they involve have values of the order of 2 to 30 cm, distributed in an erratic way, the picture is seen as shifted over its entire width and is difficult to interpret. But if, on average, the same shift is repeated more than 10% of the time, the eye is capable, in the case of pictures of simple structure (a close-up for example), of recognising this picture which appears against a cluttered background. From the latter remark it may be deduced that the number of positions of possible cutting points must be greater than 10 in order that none of the positions will have more than a 10% chance of being occupied. It is therefore necessary to express the addresses with digital sequences having a number of independent significant bits equal at least to 4. The foregoing remark also shows that it is not necessary, from the point of view simply of visual observation, for the number of bits of these sequences to exceed 6, since 52 cm/2 6  =0.8 cm. 
     A classical pseudo-random binary sequence generator comprises, in its simplest form, a shift register with n stages numbered 1 to n from the input to the output (see FIG. 1), comprising at least one intermediate output of rank k of which the result of the modulo 2 addition with the output of rank n is fed back to the input. The generating polynomial of this circuit is written: 
     
         x.sup.n +x.sup.n-k +x.sup.n-k&#39; . . . +1=0                  (1) 
    
     When this polynomial is irreducible and primitive, the generator delivers a pseudo-random sequence with a maximum length equal to 2 n  -1, which comprises all the possible combinations of n bits with the exception of that composed of n consecutive zeros, which would cause blockage of the system, the latter delivering no more than zeros. 
     The use of this type of generator, however, presents two disadvantages in regard to coding effectiveness: 
     (1) to obtain an address comprising a number R of bits equal at least to 4, it is necessary either to provide for a number R of register outputs using intermediate taps, or to operate the register with a clock whose frequency is equal to the product of R by the line frequency f 1 . In both cases the successive outputs, in the space or time domain, are very strongly correlated, since they are derived one from the other by a simple translation in the register, which greatly facilitates decoding when the key is not known. It may be remarked that, when R is less than or equal to the number of register cells n and when it is not a divisor of the length 2 n  -1 of the sequence, the two solutions, in the space domain and time domain, are equivalent because, in R successive sequences, each time-domain output supplies all the bits of the sequence. In general there would be every interest in using a space-domain solution which requires the lowest clock frequency, equal to the line sweep frequency f 1 . 
     (2) the complete sequence supplied by a psuedo-random sequence generator of this type can be found by solving a system of n linear equations with n unknowns when n address values are known, which can be done if one succeeds in identifying the position of n lines in the picture, having reference for example to a picture element containing a well-isolated vertical line. 
     To overcome the latter drawback, it is possible to use nonlinear operations over and above the modulo 2 addition (see the article by P. R. Geffe: &#34;How to protect data with ciphers that are really hard to break&#34;, published in the journal Electronics, 4th Jan. 1973, pages 99 to 101). A particularly interesting version of such a circuit, referred to as a Geffe generator and described in particular in the article by E. L. Key: &#34;An analysis of the structure and complexity of nonlinear binary sequence generators&#34;, published in the IEEE Transactions on Information Theory review, volume IT-22, No. 6, Nov. 1976,  pages 732 to 736, consists in using three registers A, B, C, and using for example output a of the first register to switch the output of the system either on the output b of the second register, or on the output c of the third. FIG. 2a shows this generator, whose logic equation may be written: 
     
         S=ab+ac                                                    (2) 
    
     (we recall here in FIG. 2b the truth tables of the principal logic operations: logic addition a+b, logic product ab, and modulo 2 addition or OR excluding a⊕b, which latter operation may be written a⊕b=ab+ab, noting a and b as the complements to 1 of a and b). 
     This Geffe generator has two important advantages. On the one hand, its output comprises a mean distribution equal to 0 and 1, which is very rarely the case when logic operations of the product type are introduced. On the other hand, to decode this device without knowing the key, it would be necessary to solve a system of n d  equations, with n d  =n a  +n b  +n c  (n a , n b , n c  designating the number of register stages A, B and C respectively), but these equations are nonlinear and the solution of the system is difficult. It has been demonstrated, in the article by E. L. Key referred to above, that these n d  nonlinear equations could be reduced to a system of linear equations, whose number however is in the neighborhood n a  (n b  +n c ), which is a much larger number than n d  =n a  +n b  +n c . 
     The use of a Geffe generator to obtain a pseudo-random address generator for the digital coding of television pictures has an extra advantage in the sense that a device comprising several simple generators is much more interesting than a device comprising a single simple generator having the same total number of n d  stages. Instead of having n d  correlated outputs, one has in effect three non-correlated sets of outputs which may be combined amongst each other. 
     Of course, in order for a Geffe generator to be maximally effective the generating polynomials of the three registers A, B, C must be irreducible and primitive, such that the sequences of bits a, b, c have maximum lengths, that is to say equal respectively to 2 n .sbsp.a -1, 2 n .sbsp.b -1, 2 n .sbsp.c -1, which three lengths must in addition be first among them in order that the length of a pseudo-random sequence, a combination of bits a, b and c, can be maximum and equal to (2 n .sbsp.a -1)·(2 n .sbsp.b -1)·(2 n .sbsp.c -1), a product whose value is of the order of magnitude of 2 n .sbsp.d. 
     The lengths n c , n b , n a  of the three registers may for example be chosen equal respectively to: 
     3, 4, 5, when one has a key of 12 bits, the length of the sequence then being about 3,000: 
     3, 4, 7, when one has a key of 14 bits, the length of the sequence then being about 13,000: 
     3, 5, 7, when one has a key of 15 bits, the length of the sequence then being about 27,000; 
     3, 5, 8 or 4, 5, 7, when one has a key of 16 bits, the length of the sequence then being about 60,000; 
     4, 5, 9 or 5, 6, 7, when one has a key of 18 bits, the length of the sequence then being about 240,000; 
     4, 5, 11 or 5, 7, 8, when one has a key of 20 bits, the length of the sequence then being about 1,000,000. 
     The use of Geffe generators combining the different outputs of three identical registers A, B, C to generate address bits of cutting points with a view to encoding a television picture does, however, have one serious drawback: because of the properties of the eye in the matter of recognising shapes, and in particular because of its capacity to identify a picture the probability of whose presence is greater than about 10%, it is possible, by successive approximations, to decipher the device by first seeking in successive trials the (n b  +n c ) bits corresponding to the initial word used to charge the registers B and C. 
     This statement can be verified by taking an example, that of a key of 16 bits, choosing n a  =7, n b  =5, n c  =4, such that the order of complexity of the Geffe generators is of the order of: 7(4+5)=63. It is assumed that the 9 bits of the key corresponding to the initial word of the registers B and C (4 and 5 bits respectively) are known, and that the output of the generator A is unknown. For a bit with a given address one thus has one chance in two to have at the receiving end the same output as at the transmitting end (and thus of having the identity of the corresponding address bit), but equally there is one chance in two that these bits a will be opposed, which means that upon transmission the chosen address bit is for example a bit b, whereas that chosen at the receiving end is a bit c. Since these two bits are not correlated, there is one chance in two that they will be identical. On average, one thus has during half the time a probability of identity equal to one, whereas during the other half of the time one has a probability of identity equal to 1/2, which gives an average probability of identity equal to 3/4 for an address bit. 
     In the case of R address bits calculated on the basis of R Geffe generators using different outputs of the same three registers A, B, C, the probability of the same address being identical is thus equal to (3/4) R . As it was shown in the foregoing that, according to the properties of the eye, the number of significant address bits is equal at the most to 6, the maximum probability of address identity cannot in practice drop below (3/4) 6  =0.18, which gives a picture perfectly identifiable by the eye. 
     In practice, the situation is even worse since the probability of 0.18 corresponds to the case where different outputs are used for the six address bits. This means that one has necessarily employed generators comprising a number of stages equal at least to 6, and thus a total number of key bits equal to 21 if one is satisfied with a non-maximum sequence (n a  =8, n b  =7, n c  =6) or equal to 24 (n a  =9, n b  =8, n c  =7) if one wishes a maximum sequence. In the case where on chooses n b  =5 and n c  =4 (key of 16, 18 or 20 bits, as indicated above), one is obliged to use again, for the fifth address bit, a bit of C already used previously and, for the sixth address bit, two bits of B and C already used, which leads to a probability of identity in the order of 0.26 for 6 bits. 
     To decipher the system in a fraudulent manner and find again the 16 bits of the key, it thus suffices to operate in two steps: (1) to try successively the different combinations of 9 bits of the initial words of the registers B and C, which requires at the most 2 9  =512 attempts, on average 256 attempts only; (2) once these 9 bits have been found, to try successively the different combinations of the remaining 7 bits, which requires at the most 2 7  =128 attempts and, on average, 64 attempts. Since about one second is sufficient for trying each key, one can thus find the 16 bits of the key in 320 seconds on average (256+64), i.e. in about five minutes. This delay is comparable with the delay needed for finding 16 bits when it cannot be done in two steps: 2 16  =65,536 attempts at the most, or on average 32,768 attempts, which would require more than 9  hours on the basis of one attempt per second. 
     The result is that, given the same difficulty of deciphering by successive attempts with keys, a pseudo-random address generator using Geffe generators requires a number of key bits between 1, 7 and 2 times greater than would be necessary in a device not using the principle of the Geffe generator, and not permitting the recognition of bits in two successive steps. For example, if one estimates that an average time of the order of two hours is sufficient to discourage attempts at deciphering, this time can be obtained without a Geffe generator with a key of 14 bits, whereas with a Geffe generator as many as 26 bits would be necessary after choosing lengths of the registers A, B and C equal respectively to 13, 7 and 6. 
     SUMMARY OF THE INVENTION 
     A primary object of the invention is therefore to propose a pseudo-random binary sequence generator capable of providing addresses of at least 4 bits with probabilities of identical addresses being less than 10%, these addresses being at the same time much more difficult to decode, when the key is not known, than those provided by the generators known up to the present time, the generator simultaneously coping with the drawbacks of the Geffe generators when these are applied to the digital coding of television pictures. 
     To this end the invention relates to a pseudo-random binary address generator intended in particular for supplying cutting point addresses of a composite video signal, in the case of a frequency-division multiplexing system of the types SECAM, PAL or NTSC for example, or luminance and chrominance video signals in the case of a time-division multiplexing system using the analog components of the MAC type, for example, with a view to deciphering these video signals by rotation of the segments situated on both sides of each cutting point, in which there are three feedback shift registers and the generating polynomials of each of these registers are irreducible and primitive in order that the bit sequences a, b, c which they deliver shall be of maximum length, in which the number of the cells n a , n b , n c  of the said registers are different, in which the three registers comprise several outputs a i , b j  and c k , and in which the addresses of the cutting points are constituted by the sums of N terms of weight 2 0  to 2 N-1  and of the respective coefficients S 0  to S N-1  of which at least the four heaviest weight coefficients are deduced from logic equations comprising at least one modulo 2 addition of three outputs a i , b j  and c k , denoted (a i  ⊕b j  ⊕c k ), the ranks i, j and k being chosen different as far as the degrees n a , n b , n c  of the registers so permit, and the other coefficients being chosen either fixed and equal, as the case may be, either 0 or 1 or deduced for one or several of them from outputs a i , b j  and c k  with the aid of equations not comprising modulo 2 addition of three outputs. 
     The structure thus defined is advantageous for the following reasons. It has been seen that in the case of the Geffe generator the probability of address identity in the case of an address bit is 3/4 when bits b and bits c are known, by reason of the fact that, when the values of bits b and c are equal, the output S is equal to that common value (see equation (2)), so that the value of bit a does not enter into it. The choice of a logic equation in which the change of one bit in three changes the output, whatever the values of the two bits not affected, overcomes this disadvantage because with this equation, for 1 address bit, the probability of address identity is equal to 1/2. If the limitation of the addresses, examined later, has no effect on the efficacity of each address bit, and if the length of each register is equal at least to 4, the probability of address identity for 4 address bits is equal to (1/2) 4  =6.25%, that is to say situated below the limit for the distinction of structure in a picture. The generator proposed is thus very well protected against deciphering attempts by making successive trials of the different keys. 
     Another nonlinear combination of three registers A, B and C has been proposed by Jan-Olof Bruer in a report from the University of Linkoping (Sweden), No. LITH-ISY-I-0572, dated 31st Mar. 1983, entitled &#34;On nonlinear combinations of linear shift register sequences&#34;. This combination, shown in FIG. 3, consists in making a modulo 2 addition or a logic addition (they both lead to the same result here) of three products: 
     
         S=ab⊕bc⊕ca=ab+bc+ca                                (3) 
    
     This Bruer generator, like the Geffe generator, offers a mean distribution equal to 0 and to 1, but its equivalent linear complexity is even greater because it is equal to (n a  n b  +n a  n c  +n b  n c ). However, it presents the same drawback as the Geffe generator in that it permits deciphering by successive approximations. This derives from the fact that, the moment two outputs of two generators (A and B, or B and C, or C and A) are identical, the result no longer depends on the output of the third generator, as happened in the Geffe generator when the outputs of generators B and C were identical. Consequently the probability of decoding, that is to say the probability that two independent outputs will be identical, is 3/4 per address bit, whereas it is only 1/2 when only a modulo 2 addition is applied (a⊕b⊕c), for example. 
     In this patent application a solution is described which makes it possible to obtain, starting from three registers A, B and C, an equivalent linear complexity close to that of the Geffe generator without presenting the same drawback. The characteristic features of this solution are that the three registers have several outputs a i , b j  and c k , and that the addresses of the cutting points are constituted by the sums of N terms of weights 2 N-1  to 2 0  and of respective coefficients S 0  to S N-1  of which at least the four coefficients of greatest weight are deduced from logic equations comprising at least one modulo 2 addition of three outputs a j , b j  and c k , denoted (a i  ⊕b j  ⊕c k ), the ranks i, j and k being chosen different in so far as permitted by the degrees n a , n b , n c  of the registers, and the other coefficients being optionally fixed and then equal to 0 or to 1, or deduced for one or several among them from the outputs a i , b j  and c k  with the aid of equations not involving a modulo 2 addition of three outputs. 
     When the number of bits of the key is not very high, when it is less than or equal to 20, for example, the same outputs of the registers may be used for several address bits, which reduces the effectiveness of the coding and increases the probability of decoding. 
     A second object of the invention is to remedy this reduction of effectiveness by calculating the M address bits of greatest weight successively starting from the values of outputs a i , b j , c k  delivered at M different moments by the clock control in the registers. 
     In this respect the invention relates to a psuedo-random binary sequence generator designed in particular to deliver cutting point addresses of a composite video signal, in the case of a frequency-division multiplexing system of the types SECAM, PAL or NTSC for example, or cutting point address bits of luminance and chrominance video signals in the case of a time-division multiplex system of analogue components of the type MAC for example, with a view to implementing the encoding of these video signals by changing the order of the points of the two segments situated on either side of each cutting point, this generator comprising three feedback shift registers A, B and C in which the number of cells n a , n b  and n c  are different and in which the generating polynomials are irreducible and primitive in order that the bit sequences a, b, c which they deliver shall be of maximum length, the addresses of the cutting points being deduced from the sums of N terms of weights 2 N-1  to 2 0  and or respective coefficients S 0  to S N-1 , in which the M coefficients S 0  to S M-1  of greatest weight are delivered successively by the output of the generator, which operates at a clock frequency equal to or greater than M times the video signal line frequency, and in which this output is the result of a logic equation comprising at least two modulo 2 additions of three outputs a i , b j , c k  of the three registers. 
     The structure of the generator thus proposed leads effectively to greater protection against deciphering attempts by successive trials of different keys. Of course, the lengths (2 n .sbsp.a -1), (2 n .sbsp.b -1), (2 n .sbsp.c -1) of the sequences delivered by the three registers, which are maximum, may here to be chosen first among them in order that the length of the pseudo-random sequences performed by the combinations of bits a, b, c shall itself be maximum. 
     The particularities and advantages of the invention will now be shown more exactly in the description which follows and in the appended drawings. 
    
    
     DESCRIPTION OF THE FIGURES 
     FIG. 1 represents a pseudo-random binary sequence generator of the classic type with n cells; 
     FIG. 2 represents a Geffe generator with three registers; 
     FIG. 3 represents a Bruer generator with three registers; 
     FIGS. 4, 5 and 6 schematize the circuits used in the case of address limitation; 
     FIGS. 7a and 7b gives an example of an embodiment of a pseudo-random binary sequence generator in accordance with the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The truth tables of the logic operations of addition, of product and of modulo two addition are recalled as being: 
     
                       TABLE 1                                                     
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a + b                                                                     
               a                                                          
b                0     1                                                  
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0                0     1                                                  
1                1     1                                                  
______________________________________                                    
 
    
     
                       TABLE 2                                                     
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a · b = ab                                                       
               a                                                          
b                0&#39;    1                                                  
______________________________________                                    
0                0     0                                                  
1                0     1                                                  
______________________________________                                    
 
    
     
                       TABLE 3                                                     
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a ⊕ b                                                                 
               a                                                          
b                0     1                                                  
______________________________________                                    
0                0     1                                                  
1                1     0                                                  
______________________________________                                    
 
    
     Table 4 illustrates schematically the decoding probabilities of the first, second, third and fourth modes of implementation of the invention proposed hereinafter, as a function of the number of address bits utilized, in the case where the degrees n a , n b , n c  of the registers are such that n a  =at least 7, n b  =5, n c  =4, and when there is no loss of efficacity due to limitation of the addresses; 
     
                                           TABLE 4                                 
__________________________________________________________________________
                     Number of address bits                               
                     3    4    5   6                                      
__________________________________________________________________________
Decoding probability                                                      
             Solutions 1, 2, 4                                            
                      12,5%                                               
                            6,25%                                         
                                3,1%                                      
                                    1,6%                                  
for same b and c                                                          
             Solution 3                                                   
                     &#34;    &#34;    &#34;   3,1 or 1,6*                            
Decoding probability                                                      
             Solution 1                                                   
                     12,5  6,25                                           
                               6,25                                       
                                   6,25                                   
for same a and b                                                          
             Solution 2                                                   
                     12,5 9,4  6,25                                       
                                   6,25                                   
or same a and c                                                           
             Solution 3                                                   
                     18,7 12,5 9,4 6,25                                   
             Solution 4                                                   
                     12,5 9,4  6,25                                       
                                   6,25                                   
__________________________________________________________________________
 *when 8 outputs of register A are used (n.sub.a &gt; 7)                     
 
    
     Table 5 illustrates schematically the decoding probabilities of the first, second, third and fourth modes of implementation of the invention, as a function of the number of the address bits utilized, in the same case as that of Table 4, but with a loss of efficacity due to limitation of the addresses. 
     
                                           TABLE 5                                 
__________________________________________________________________________
                     Number of address bits                               
                     3    4    5    6                                     
__________________________________________________________________________
Decoding probability                                                      
             Solution 1, 2, 4                                             
                      15,6%                                               
                            8,8%                                          
                                4,4%                                      
                                     2,2%                                 
for same b and c                                                          
             Solution 3                                                   
                     15,6  8,8 4,4  3,5 or 2,2*                           
Decoding probability                                                      
             Solution 1                                                   
                     15,6  8,8 7,8-7                                      
                                     6,25                                 
                               (a and b)                                  
                               (a and c)                                  
for same a and b                                                          
             Solution 2                                                   
                     15,6 12,2 8,3  8,3                                   
or same a and c                                                           
             Solution 3                                                   
                     20,3 14,8 11   7,4                                   
             Solution 4                                                   
                     15,6 12,2 8,3  8,3                                   
__________________________________________________________________________
 *when 8 outputs of register A are used (n.sub.a &gt; 7).                    
 
    
     In a first form of embodiment of the invention, the generator is thus a Geffe generator with three feedback shift registers A, B, C whose generating polynomials are irreducible and primitive, such that the bit sequences a, b, c which they deliver are of maximum length, that is to say equal respectively to 2 n .sbsp.a -1, to 2 n .sbsp.b -1, and to 2 n .sbsp.c -1, where n a , n b  and n c  are the numbers of the respective cells or degrees, the registers A, B and C, and being conventionally chosen such that n a  is greater than n b , itself being greater than n c . The lengths of the three registers, which are maximum, have been chosen here as first among them, in order that the length of the pseudo-random sequences formed by the combinations of bits a, b, c shall themselves be maximum and equal to the product (2 n .sbsp.a -1)·(2 n .sbsp.b -1)·(2 n .sbsp.c -1). 
     An arbitrary cutting point address S being expressed by the sum S of N terms of weight 2 0  to 2 N-1  affected by the respective coefficients S 0  to S N-1 , written as: ##EQU1## an object of the invention is achieved if at least the four coefficients of greates weight, S N-1 , S N-2 , S N-3  and S N-4 , are derived from logic equations each consisting of a modulo 2 addition of the type S h  =a i  ⊕b j  ⊕c k , where S h  is the generic term of the sum S defining the address and a i , b j , c k  are the outputs of the three registers A, B and C. Preferentially, the ranks i, j, k are chosen differently, in so far as permitted by the degrees n a , n b , n c . The latter address coefficients are either fixed or chosen equal to 0 or to 1, or deduced for several of them from among the outputs a i , b j  and c k  with the aid of equations not comprising modulo 2 addition of the three outputs. The probability of address identity is now, for four address bits equal to (1/2) 4  =6.25%, a value which is much lower than the 10% noted in the foregoing as the limit value for recognising a structure in a picture. 
     The modulo 2 addition: 
     
         S.sub.h =a.sub.i ⊕b.sub.j ⊕c.sub.k                 (5) 
    
     can thus be written, explaining the logic operations: 
     
         S.sub.h =a.sub.i (b.sub.j c.sub.k +b.sub.j c.sub.k)+a.sub.i (b.sub.j c.sub.k +b.sub.j c.sub.k)                                 (5 bis) 
    
     These equations (5) or (5 bis) represent a linear system, and an attempt at deciphering only requires the solution of a number of linear equations equal to the number of bits n d  of the key (n d  being equal to n a  +n b  +n c ). To make this mathematical solution more difficult, it is possible, in a second mode of embodiment of the invention, to employ, for the first address bit of greatest weight, a logic equation containing for example two different modulo 2 additions of the type (a⊕b⊕c), the choice of which is dictated by the value of another bit a or b or c. If one chooses n a  greater than n b , itself being greater than n c , this multiplier bit results from the longest register A. To avoid using more than two register outputs per address bit, one can use the same output a in the two sums. 
     In this second mode of embodiment, the logic equation of the first strongest weight coefficient can thus be written: 
     
         S.sub.N-1 =a.sub.i (a.sub.i&#39; ⊕b.sub.j ⊕c.sub.k)+a.sub.i (a.sub.i&#39; ⊕b.sub.j&#39; ⊕c.sub.k&#39;)                              (6) 
    
     or 
     
         S.sub.N-1 =a.sub.i (a.sub.i&#39; ⊕b.sub.j ⊕c.sub.k)+a.sub.i (a.sub.i&#39; ⊕b.sub.j&#39; ⊕c.sub.k&#39;)                              (6 bis) 
    
     These two expressions (6) and (6 bis), in which we have used the same output a i&#39;  in the two sums in order to avoid employing three outputs a for one single address bit, differ only in the fact that one uses either a i  or its complement a i&#39;  in the second sum. If the complexity of the circuit is not significantly increased, it is preferable to use expression (6 bis) because the fact of using a i&#39;  diminishes the similitude between the two sums. 
     The logic equations giving at least three of the following strongest weight coefficients remain in the form: 
     
         S.sub.h =a.sub.i&#34; ⊕b.sub.j&#34; ⊕c.sub.k&#34;              (7) 
    
     the ranks i&#34;, j&#34;, k&#34; being here again chosen differently, in so far as the degrees n a , n b  and n c  permit. The latter address coefficients are fixed and chosen equal to 0 or to 1, as the case may be. 
     In a third mode of embodiment of the invention, the logic equation of the second strongest weight coefficient S N-2  is also the type of equations (6) or (6 bis), with the coefficients i j k chosen differently, and the logic equations giving at least two of the strongest weight coefficients following the type of equation (7). The other coefficients are fixed and are equal to 0 or 1. This third mode of embodiment offers greater protection against mathematical deciphering, since the two strongest weight coefficients contain products and their order of complexity is thus close to that of n a  (n b  +n c )=63, for example, since n a , n b  and n c  are respectively 7, 5 and 4. 
     However, the two coefficients of greatest weight, S N-1  and S N-2 , each use two outputs of register A, two outputs of register B and two outputs of register C. If the length of the shortest register C is only 4, for example, one will thus find in the following address coefficients some outputs of C that have already been used, which will increase the probability of address identity and, consequently, the risk of deciphering by successive trials with keys. 
     To overcome this drawback one can, in a fourth mode of embodiment of the invention, choose as multiplicative terms the register outputs of least length, taking for example an output of register B for the first coefficient and an output of register C for the second. The logic equations of the strongest weight coefficients may then be written: 
     
         S.sub.N-1 =b.sub.j (a.sub.i ⊕b.sub.j&#39; ⊕c.sub.k)+b.sub.j (a.sub.i&#39; ⊕b.sub.j&#39; ⊕c.sub.k&#39;)                              (8) 
    
     or 
     
         S.sub.N-1 -b.sub.j (a.sub.i ⊕b.sub.j&#39; ⊕c.sub.k)+b.sub.j (a.sub.i&#39; ⊕b.sub.j&#39; ⊕c.sub.k&#39;)                              (8 bis) 
    
     and 
     
         S.sub.N-2 =c.sub.k&#34; (a.sub.i&#34; ⊕b.sub.j&#34; ⊕c.sub.k&#34;&#39;)+c.sub.k&#34; (a.sub.i&#34;&#39; ⊕b.sub.j&#34;&#39; ⊕c.sub.k&#34;&#39;)                 (9) 
    
     or 
     
         S.sub.N-2 =c.sub.k&#34; (a.sub.i&#34; ⊕b.sub.j&#34; ⊕c.sub.k&#34;&#39;)+c.sub.k&#34; (a.sub.i&#34;&#39; ⊕b.sub.j&#34;&#39; ⊕c.sub.k&#34;&#39;)                 (9 bis) 
    
     In this case, as in the foregoing, the logic equations giving at least two of the strongest weight coefficients, are of the type: 
     
         S.sub.h =a.sub.i&#34;&#34; ⊕b.sub.j&#34;&#34; ⊕c.sub.k&#34;&#34;           (10) 
    
     taking the ranks i j k as different as the degrees of the registers permit, and the latter coefficients are fixed and equal to 0 or 1. 
     With the fourth mode of embodiment, the orders of complexity of the two first coefficients approximate respectively to n b  (n a  +n c ) and n c  (n a  +n b ), or, respectively 55 and 48 in the example chosen above (n a  =7, n b  =5, n c  =4). These orders of complexity are thus slightly inferior to those of the second mode of embodiment. This system however, is better protected against deciphering by successive attempts with keys, since it may be noted that the coefficient S N-1  always depends on b j , and that the coefficient S N-2  always depends on C k&#34;&#39; , which makes it possible to use again the outputs b j  and c k&#34;  for the third or fourth coefficient S N-3  or S N-4  without reducing their effectiveness. 
     In the four modes of embodiment proposed in the foregoing the protection is maximum relative to deciphering by successive stages that would begin by the shortest bits of the registers B and C. However, the protection relative to deciphering beginning with the bits of the registers A and B or of registers A and C should also be investigated. In the case where the degrees of the registers are for example equal to 5, 4 and 3, deciphering beginning with bits A and C would require no more, on average, than 1/2(2 5+3  +2 4 )=(128+8) attempts, or about two minutes, whereas if this deciphering were not possible on the basis of A and C, an average of 2,048 attempts or 34 minutes, would be required; in the case where the degrees of the registers are equal to 7, 5, 4, an average of 17 minutes would be required instead of 9 hours. By way of example, the abovementioned table 4 indicates the decoding probabilities of the four modes of embodiment proposed, as a function of the number of address bits utilized, in the case where the degrees n a , n b , n c  are such that n a  =at least 7, n b  =5 and n c  =4, and when there is not, of course, any loss of effectiveness due to limitation of addresses (which will now be discussed). 
     The generator described in the foregoing, in four possible forms of embodiment, is capable of delivering 2 N  different addresses of value 0 to 2 N  -1 (it has already been shown that any cutting point address was expressed by a sum S of N terms S h  2 h  of weight 2 0  to 2 N-1  given the respective coefficients S 0  to S N-1 ). When the number M of samples stored each line in the memory is slightly greater than a power of 2, there is no problem of exceeding the limits if N is chosen equal to the power of 2 just lower than M. It may happen, however, that the number M will be very slightly lower than a whole power of 2: in this case, the preceding choice of N will lead to permutations corresponding to line translations maximally equal to about the half-width of the picture, which would cause a loss of scrambling effectiveness. This eventuality may occur in particular in the case of the scrambling of a standard European PAL coded signal, when a sampling frequency is chosen equal to four times the colour subcarrier frequency (i.e. 17,734 Megahertz for this sampling frequency) to avoid interference between these two frequencies. 
     In this case, the number of points stored each line in the memory does not in practice exceed 990, taking into account the part of the signal sacrificed to permit the repetition of a zone in the neighbourhood of the cutting point (a redundancy characteristic). To obtain translations approximating to the width of the picture without exceeding it, one may thus choose for example N=10, or 1,024 possible addresses, and cause 2 p  of these addresses, comprised between 2 N  -2 p  and 2 N  -1, to undergo a reduction by a quantity 2 q , p being chosen such that 2 N  -2 p  is less than M and q being chosen equal to or greater than p but such that 2 q  is less than 2 N  -2 p . In the example quoted, one may choose for example p and q both equal to 6, which amounts to reducing by 64 the 64 addresses greater than or equal to 960. This operation amounts to forcing the coefficient S 6  to the value 0 when the coefficients S 7 , S 8  and S 9  are all three equal to 1, which can be obtained very simply by means of the circuit indicated in FIG. 4 which uses an AND gate with two inputs and a NAND gate with three inputs, verifying the equation: 
     
         S*.sub.6 =S.sub.6 ·(S.sub.7 ·S.sub.8 ·S.sub.9) (11) 
    
     It should be noted that this operation reduces the effectiveness of the coefficient S 6 , which only influences the delivered address during 7/8ths of the time. 
     In any case, the television signals stored in the memory always comprise an initial reference period containing either the black level where it relates to a black- and -white signal or a luminance signal, or a reference threshold superimposed on the black level when it relates to a composite colour signal of the type PAL, SECAM or NTSC, or a reference level corresponding to the colour difference zero level when it relates to a colour difference signal U or V (in the case of MAC coding for example). As this reference level could be referred to relatively easily in the enciphered signal, it is important, in order to avoid deciphering of the picture, not to apply the permutation in this period, which amounts to inhibiting the cutting point addresses that fall in these reference periods. 
     A simple means of realizing this inhibition consists in augmenting the 2 r  addresses supplied by the generator, comprised between 0 and 2 r  -1, by a quantity 2 s , r being chosen such that 2 r  is greater than the length L of the reference segment, and s being chosen equal to or greater than r such that 2 s  is less than M-2 r . In the example quoted, the length L does not exceed 100 sampled elements. One may thus choose, for example, r and s both equal to 7, which amounts to adding 128 to 128 first addresses, comprised between 0 and 127. This operation amounts to forcing the coefficient S 7  to the value 1 when the coefficients S 8  and S 9  are both equal to 0, which can be obtained very simply by means of the circuit indicated in FIG. 5, which uses an OR gate and a NOR gate with two inputs, verifying the equation: 
     
         S*.sub.7 =S.sub.7 +(S.sub.8 +S.sub.9)                      (12) 
    
     Here again, it should be noted that this operation reduces the effectiveness of the coefficient S 7 , which only influences the supplied address during 3/4 of the time. 
     In the case of the first form of embodiment described (see equations (5) and (5 bis)), the probability of address identity for four significant address bits S 6  to S 9  thus becomes equal, in the example quoted and in the case where the smallest register comprises at least four cells, to: ##EQU2## By way of example, the abovementioned table 5 indicates as a function of the number of address bits the probabilities of address identity calculated in the case of lower and higher preceding limits, for the first, second, third and fourth forms of embodiment proposed, in the case where the lengths of the registers are respectively 4 for C, 5 for B and greater than or equal to 7 for A. 
     It can be seen that the probability of decoding is equal to the minimum probability when the bits of B and C are known at the same time (9 bits). On the other hand, when the bits A and B are known at the same time (at least 12 bits) or A and C at the same time (at least 11 bits), the probability of decoding is greater than the minimum probability, and only drops below the 10% threshold of perception when one uses at least four address bits in the solution 1, five bits in the solutions 2 and 4, and six bits in solution 3. It may be noted in addition that the example of the limits quoted applies equally to the PAL and SECAM systems in Europe, when the clock frequency f H  is chosen at about 17,734 MHz, as well as to the NTSC system in the countries using the 525 lines standard, with 30 pictures per second, when a clock-frequency is chosen about five times the colour subcarrier frequency of NTSC, i.e. 17.9 MHz. 
     In the case of a time-division multiplexing system of analog components, the generator has to supply as many cutting point addresses as there are components in each line, that is to say for example two in the case of the MAC system (where the components are Y and, alternatively, U and V). As the luminance and chrominance components comprise information of comparable form, no element of secrecy is lost when analogous rotations are applied to these components, that is to say when the two addresses are calculated on the basis of the same outputs of the same shift registers and using the same logic equations. This makes it possible to have an address generator whose complexity is in practice no greater than in the preceding case, except that the problem of the limits may differ depending on the components. 
     If one assumes, for example, that the generator supplies six variable coefficients A 0  to A 5  deduced from the foregoing operations and taking N=6, and also that we have the case of a MAC signal such that the duration of the luminance component is about twice that of the chrominance component, with a clock frequency such that the useful capacity of the luminance and chrominance memories is slightly less than 512 and 256, respectively, we can then take for the luminance N Y  =9 and for the chrominance N C  =8, choosing as coefficients the address expression (formed, it will be recalled, from a sum of N terms S h  2 h ): ##EQU3## after having subjected A 2  and A 3  to the same operations as those described in the foregoing for S 6  and S 7  (FIGS. 4 and 5) to inhibit the address segments situated at the extremities. 
     One might also have the case of a MAC signal with a clock frequency such that the useful capacity of the luminance memory is closer to 768 than to 512 (=2 9 ) or to 1024 (=2 10 ). A first solution consists then in choosing N Y  =10 and in forcing to 0 the coefficient S Y .sbsb.8, as well as possibly a weaker weight coefficient (S Y .sbsb.6 or S Y .sbsb.5) when the strongest weight coefficient S Y .sbsb.9 is equal to 1, but this solution has the drawback of reducing by a factor of 1/2 the effectiveness of the second strongest weight coefficient S Y .sbsb.8 and of equally reducing the effectiveness of the two other coefficients, taking account of the lower limit. A second solution consists in choosing N Y  =9, which gives 512 possible addresses, and in choosing, for the translation of the addresses comprised between 0 and 2 r  -1, a quantity 2 s  =2 9  =512, which is possible, for example, when the length of the reference level is less than 128 and when the length M of the signal is comprised between 640 and 896. 
     The luminance address coefficients are then chosen as follows: ##EQU4## This amounts to choosing 
     
         S.sub.Y.sbsb.9 =S.sub.Y.sbsb.8 +S.sub.Y.sbsb.7,            (14) 
    
     which can very easily be obtained with a NOR gate with two inputs as indicated in FIG. 6. This second solution offers the advantage that the effectiveness of the six coefficients A 0  to A 5  remains intact. The probabilities of decoding are then as indicated in table 4. This latter type of solution can also be applied in the case of a MAC signal with a clock frequency such that the useful capacity of the chrominance memory is closer to 384 than to 256 (=2 8 ) or to 512 (=2 9 ). The chrominance address coefficients would then be chosen as follows: ##EQU5## and 
     
         S.sub.C.sbsb.8 =S.sub.C.sbsb.7 +S.sub.C.sbsb.6.            (15) 
    
     FIG. 7, made by the association of the parts of FIGS. 7a and 7b, shows an example of the practical embodiment of a pseudo-random binary address generator adapted to PAL, SECAM and NTSC signals. The lengths of the three registers A, B, C have been chosen respectively equal to 11, 5 and 4, which permits about 950,000 different keys of 20 bits. The irreducible and primitive generating polynomials, chosen in order to avoid having to have more than one intermediate tap on each register, are the following: 
     
         x.sup.11 +x.sup.2 +1=0 
    
     
         x.sup.5 +x.sup.2 +1=0 
    
     
         x.sup.4 +x+1=0 
    
     Use is made of eight outputs a 1  to a 8  of A, four outputs b 1  to b 4  of B and four outputs c 1  to c 4  of C, which are applied respectively to the 16 inputs of a programmable logic network PLN, for example of the type 82 S 100, made by the Signetics company. This PLN provides eight outputs A 0  to A 7 , used for supplying 8 variable address bits S 2  to S 9 , the two address bits with the lowest weight S 0  and S 1  being equal to 0. As seen in the foregoing, to inhibit the addresses comprised between 0 and 127 and those comprised between 960 and 1,023, the coefficients S 6  and S 7  are deduced from the outputs A 5 , A 6 , A 7  in accordance with the programmed schemata such that they provide, in conformity for example with the fourth form of embodiment of the invention, an output A.sub. 7 according to equation (8 bis), an output A 6  according to equation (9 bis), and six outputs A 0  to A 5  according to equation (10). By way of example, the following equations have been chosen: 
     
         A.sub.7 =b.sub.1 (a.sub.3 ⊕b.sub.4 ⊕c.sub.1)+b.sub.1 (a.sub.7 ⊕b.sub.4 ⊕c.sub.4) 
    
     
         A.sub.6 =c.sub.3 (a.sub.4 ⊕b.sub.3 ⊕c.sub.2)+c.sub.3 (a.sub.8 ⊕b.sub.2 ⊕c.sub.2) 
    
     
         A.sub.5 =a.sub.1 ⊕b.sub.1 ⊕c.sub.3 
    
     
         A.sub.4 =a.sub.5 ⊕b.sub.3 ⊕c.sub.1 
    
     
         A.sub.3 =a.sub.6 ⊕b.sub.2 ⊕c.sub.4 
    
     
         A.sub.2 =a.sub.2 ⊕b.sub.4 ⊕c.sub.2 
    
     
         A.sub.1 =a.sub.3 ⊕b.sub.1 ⊕c.sub.3 
    
     
         A.sub.0 =a.sub.8 ⊕b.sub.3 ⊕c.sub.1 
    
     The two first equations necessitate 8 products, the following ones 4. Thus, use is made of 40 products among the 48 available from the network 82 S 100. As seen, the two address bits S 2  and S 3 , deduced from A 0  and A 1 , correspond to translations that are too weak to make any significant contribution to scrambling as perceived by the eye. Their use, however, reinforces the encoding vis-a-vis an attempt at mathematical decoding; it makes it more difficult to identify the sets of addresses introduced by the coefficients S 4  to S 9  since they introduce three possible supplementary addresses between each of the addresses supplied by S 4  to S 9 . 
     In the generator shown in FIG. 7A, the registers A, B and C are loaded at regular intervals with their respective initial words of lengths n a , n b  and n c . These words, placed end to end, constitute the key of length n d  =20 bits. This key is supplied either by a decoder pad or is sent out by the transmitter in encoded form, then decoded by an access circuit which is not shown. When a new key arrives, it is transferred to a shift register D of 20 stages, the key being accompanied by 20 pulses of a clock H c  through the intermediary of multiplexers MUX 1  and MUX 2 , beginning for example with the bits destined for registers C, then B, then A. At the end of the 20 pulses from the clock H c , one thus finds in register D the initial word of register A at the outputs Q 0  to Q 10 , the initial word of register B at the outputs Q 11  to Q 15  and the initial word of register C at the outputs Q 16  to Q 19 . 
     At regular intervals, equal here to 48 frames, the output of register D is fed back to its input through the intermediary of the multiplexer MUX 1 . The outputs Q 19 , Q 10  and Q 15  are connected to the inputs of registers A, B and C through the intermediary of the multiplexers MUX 3 , MUX 4 , MUX 5 , the loops of these registers being opened at the same time, and one applies to register D through the intermediary of MUX 2 , during 20 consecutive clock pulses, the same clock H L  having the frequency of the line scan as that which is permanently applied to registers A, B and C. At the end of the 20 pulses of the clock H L , the words stored in the registers A, B and C then correspond to the bits initially stored in register D between the outputs Q 0  and Q 10  for A, Q 11  and Q 15  for B, Q 16  and Q 19  for C respectively. Moreover, because of the output of D being fed back to its input during this operation, this register is returned to its initial state at the end of the 20 clock pulses and thus plays the role of memory for the key. 
     The operation of loading registers A, B and C, starting from register D, is effected during a flyback period (registered by the clock H T  at the scanning frequency) during all the 48 frames, that is to say at about every second in the example quoted, synchronization with the transmitter being obtained with the aid of a starting pulse SP sent out by the transmitter either by way of data transmission, or in a special picture line. Outside these periods during which A, B and C are loaded, the register D is connected to the access control circuit through the intermediary of the multiplexers MUX 1  and MUX 2 , and is thus ready to receive any new key from this circuit. Of course, for large-scale production the set of circuits represented in FIG. 7 can be integrated on a single silicon chip with a chip area of a few mm 2 . 
     The abscissas x of the cutting points are deduced from the sum S of N terms of weight 2 N-1  to 2 0  effected by respective coefficients S 0  to S N-1  : ##EQU6## the M coefficients S 0  to S M-1  of greatest weight being calculated starting from the outputs of registers A, B and C, the other coefficients being chosen optionally zero or equal to 1. In the case of a PAL, SECAM or NTSC signal sampled at a frequency of the order of 18 MHz, it is wise to choose N=8 
     
         x=4S+128 when S&lt;32 
    
     
         x=4S-64 when S≧240 
    
     in order to prevent the cutting point from falling in the reference signal which precedes the useful signal or coming above the last useful point of the line. 
     In the case of a MAC signal sampled at 13.5 MHz for the luminance Y and at 6.75 MHz for the chrominance C, it is again wise to choose N=8 and to take respectively for the cutting addresses in luminance and in chrominance either: 
     
         x.sub.y =2S+128 
    
     and 
     
         x.sub.c =S+64 
    
     or 
     
         x.sub.y =2S+64 
    
     and 
     
         x.sub.c =S+32 
    
     In three modes of embodiment of the invention, referred to as the fifth, sixth and seventh, each of the M coefficients is calculated on the basis of several outputs of the registers A, B and C measured at the same instant. The clock frequency F which has to be used is then equal to at least M times the video signal line frequency F 2 . For a line period of (1/F2)=64 μs, in Europe, the coefficients may be calculated, for example, starting from values of the outputs at the instants: 
     
         t.sub.o +k64 μs for S.sub.0 
    
     
         t.sub.o +(1/F)+k64 μs for S.sub.1 
    
     
         t.sub.o +(2/F)+k64 μs for S.sub.2, . . . , etc. 
    
     In the fifth mode of embodiment proposed, the three registers each have two outputs denoted a 0 , a 1 , b 0 , c 0  and c 1  and the logic equation is derived from the Geffe generator, introducing modulo 2 additions, and is of the form: 
     
         a.sub.1 (a.sub.0 ⊕b.sub.0 ⊕c.sub.0)+a.sub.1 (a.sub.0 ⊕b.sub.1 ⊕c.sub.1)                                             (17) 
    
     or 
     
         a.sub.1 (a.sub.0 ⊕b.sub.0 ⊕c.sub.0)+a.sub.1 (a.sub.0 ⊕b.sub.1 ⊕c.sub.1)                                             (18) 
    
     the second expression offering the advantage over the first that the second modulo 2 sum is made even more different from the first by using the complement to 1 of a 0  instead of a 0  itself. 
     In the sixth mode of embodiment proposed, the register A has three outputs denoted a 0 , a 1  and a 2 , the registers B and C each have two outputs denoted b 0 , b 1 , c 0  and c 1  and the logic equation, derived from the Geffe generator, is of the form: 
     
         a.sub.2 (a.sub.0 ⊕b.sub.0 ⊕c.sub.0)+a.sub.2 (a.sub.1 ⊕b.sub.1 βc.sub.1)                                            (19) 
    
     in which expression the two modulo 2 sums do not have a common element. 
     In the seventh mode of embodiment proposed, the three registers each have three outputs denoted a 0 , a 1 , a 2 , b 0 , b 1 , b 2 , c 0 , c 1  and c 2  and the logic equation is derived from the Bruer generator, introducing modulo 2 additions, and comprises the logic addition of the three logic products effected between two modulo 2 additions of different outputs: 
     
         (a.sub.0 ⊕b.sub.0 ⊕c.sub.0)(a.sub.1 ⊕b.sub.1 ⊕c.sub.1)+(a.sub.1 ⊕b.sub.1 ⊕c.sub.1)(a.sub.2 ⊕b.sub.2 ⊕c.sub.2)+(a.sub.2 ⊕b.sub.2 ⊕c.sub.2)(a.sub.0 ⊕b.sub.0 ⊕c.sub.0) 
    
     In an eighth mode of embodiment, in accordance with the invention, the three registers have only one output and the logic equation, derived from the Geffe generator, is a function of three outputs a 0 , b 0 , c 0  at the instant t 0  and of three outputs a 1 , b 1 , c 1  at the instant t 0  +1/F or t 0  -1/F and is of the form: 
     
         a.sub.1 (a.sub.0 ⊕b.sub.0 ⊕c.sub.0)+a.sub.1 (a.sub.0 ⊕b.sub.1 ⊕c.sub.1)                                             (17) 
    
     or 
     
         a.sub.1 (a.sub.0 ⊕b.sub.0 ⊕c.sub.0)+a.sub.1 (a.sub.0 ⊕b.sub.1 ⊕c.sub.1)                                             (18) 
    
     In a ninth mode of embodiment, in accordance with the invention, the register A has two outputs, the registers B and C each have one output and the logic equation, derived from the Geffe generator, is a function of the values a 0 , b 0 , c 0  of three outputs at the instant t 0 , of the values a 1 , b 1 , c 1  of these three same outputs at the instant t 0  +1/F and of the value a 2  of the second output of register A at the instant t 0  or t 0  +1/F, and is of the form: 
     
         a.sub.2 (a.sub.0 ⊕b.sub.0 ⊕c.sub.0)+a.sub.2 (a.sub.1 ⊕b.sub.1 ⊕c.sub.1)                                             (19) 
    
     In the eighth and ninth modes of embodiment, for a line period of (1/F2)=64 μs, the coefficients may be calculated, for example, starting from output values at the instants: 
     
         t.sub.0 +k64 μs and t.sub.0 +(1/F)+k64 μs for S.sub.0 
    
     
         t.sub.0 +(2/F)+k64 μs and t.sub.0 +(3/F)+k64 μs for S.sub.1 
    
     
         t.sub.0 +(4/F)+k64 μs and t.sub.0 +(5/F)+k64 μs for S2, . . . etc. 
    
     The clock frequency F which must be used in these eighth and ninth modes of embodiment is thus equal at least to 2M times the frequency F 2 . 
     In a tenth mode of embodiment, in accordance with the invention, the three registers have only one output and the logic equation, derived from the Geffe generator, is a function of three outputs a 0 , b 0 , c 0  at the instant t 0 , of three outputs a 1 , b 1 , c 1  at the instant t 0  +(1/F) and of one output a 2  at the instant t 0  +(2/F) or t 0  -(1/F) and is of the form: 
     
         a.sub.2 (a.sub.0 ⊕b.sub.0 ⊕c.sub.0)+a.sub.2 (a.sub.1 ⊕b.sub.1 ⊕c.sub.1)                                             (19) 
    
     In an eleventh and last mode of embodiment, in accordance with the invention, the three registers have only one output and the logic equation, derived from the Bruer generator, is a function of three outputs a 0 , b 0 , c 0  at the instant t 0 , of three inputs a 1 , b 1 , c 1  at the the instant t 0  +(1/F) and of three output a 2 , b 2 , c 2  at the instant t 0  +(2/F) and is of the form: 
     
         (a.sub.0 ⊕b.sub.0 ⊕c.sub.0)(a.sub.1 ⊕b.sub.1 ⊕c.sub.1)+(a.sub.1 ⊕b.sub.1 ⊕c.sub.1)(a.sub.2 ⊕b.sub.2 ⊕c.sub.2)+(a.sub.2 ⊕b.sub.2 ⊕c.sub.2)(a.sub.0 ⊕b.sub.0 ⊕c.sub.0)                                             (20) 
    
     In these two latter modes of embodiment, for a line period of (1/F)=64 μs, the coefficients may be calculated, for example, starting from output values at the instants: 
     
         t.sub.0 +k64 μs, t.sub.0 +(1/F)+k64 μs and t.sub.0 +(2/F)+k64 μs for S.sub.0 
    
     
         t.sub.0 +(3/F)+k64 μs, t.sub.0 +(4/F)+k64 μs and t.sub.0 +(5/F)+k64 μs for S.sub.1 
    
     
         t.sub.0 +(6/F)+k64 μs, t.sub.0 +(7/F)+k64 μs and t.sub.0 +(8/F)+k64 μs for S.sub.2, . . . etc. 
    
     The clock frequency F which must be used in these tenth and eleventh modes of embodiment is thus equal at least to 3M times the frequency F 2 . 
     Of course, in the foregoing equations (17) to (20), one is entirely at liberty to choose for outputs a i , b j , c k  either direct outputs of the registers or, for part or the whole of these coefficients, complements to 1 of these direct outputs, complements which are equally available in the majority of practical realisations of shift registers. 
     In the fifth to eleventh modes of embodiment of the invention, it is desirable that the psedo-random address sequences should be as long as possible, in order to make the encoding more effective. A primary condition is to choose the lengths n a , n b  and n c  of the registers such that the lengths of the sequences which the latter supply, respectively equal to (2 n .sbsp.a -1), (2 n .sbsp.b -1) and (2 n .sbsp.c -1), shall be the first among them. The length of the sequences of combinations of bits deriving from the three registers is then maximum and equal to the product: 
     
         (2.sup.n.sbsp.a -1)(2.sup.n.sbsp.b -1)(2.sup.n.sbsp.c -1)  (9) 
    
     whose value is close to 2 n .sbsp.a +n .sbsp.b 30  n.sbsp.c =2 n .sbsp.d. 
     In the fifth, sixth and seventh modes of embodiment of the invention, the coefficients of the addresses are calculated starting from M successive outputs of the registers. One could therefore find the same addresses at the outputs upon every ##EQU7## if the numerator of this fraction were divisible by M. One can therefore improve the security of the system against illicit deciphering by ensuring that M is not a divisor of (2 n .sbsp.a -1) (2 n .sbsp.b -1) and (2 n .sbsp.c -1). This condition is always verified when M is equal to a power of 2 (M=4, 8, . . . ); it will be verified when M is divisible by 3, if n a , n b  and n c  are not divisible by 2; it will be verified when M is divisible by 5, if n a , n b  and n c  are not divisible by 4; it will finally be verified when M is divisible by 7, if n a , n b  and n c  are not divisible by 3. Indeed 
     
         2.sup.2p -1 is divisible by 2.sup.2 -1=3 
    
     
         2.sup.2p -1 is divisible by 2.sup.3 -1=7 
    
     
         2.sup.4p -1 is divisible by 2.sup.4 -1=15=5×3 
    
     and so on. 
     In the eighth and ninth modes of embodiment of the invention, the same addresses could recur every ##EQU8## if the numerator were divisible by 2M. If the numerator is never divisible by 2, the conditions of maximum security are thus identical to what they are in the fifth, sixth and seventh modes of embodiment. 
     In the tenth and eleventh modes of embodiment of the invention, the same addresses could recur every ##EQU9## if the numerator were divisible by 3M. The conditions of maximum security thus correspond to those described in the foregoing, with the supplementary condition that the numerator shall never be divisible by 3, which amounts to requiring that n a , n b  and n c  shall be odd. 
     Since it may happen that some of these conditions cannot be fulfilled, for example in the case where the number of bits of the key n d  =n a  +n b  +n c  is fixed and, in particular, when this number is even, one can still make the security of the system maximum by choosing a sampling frequency F equal to the product of the frequency F 2  by a number which is first with (2 n .sbsp.a -1), (2 n .sbsp.b -1) and (2 n .sbsp.c -1), this number of course being equal to or greater than M, for the fifth, sixth and seventh modes of embodiment, to 2M for the eighth and ninth modes and to 3M for the tenth and eleventh modes of embodiment of the invention. 
     If one takes the case of the two latter modes of embodiment, with M=8 for example, the weakest frequency one may choose is: 
     
         F=3M·F.sub.1 =24·F=375 kHz. 
    
     If the length n d  of the key is even, one of the registers will also have an even length and its sequence will be divisible by 3; one may then choose the frequency 
     
         F=25·F.sub.1 =390.625 kHz. 
    
     However, if one cannot avoid the length of one of the registers being divisible by 4, its sequence will be divisible by 5; one may then prefer to choose: 
     
         F=26·F.sub.1 =406.250 kHz. 
    
     In fact, one may equally well choose a frequency which is not a multiple of F 1  but is equal to the product of F 1  by a simple fraction; the security of the system will then be maximum if the numerator of this fraction is first with (2 n .sbsp.a -1), (2 n .sbsp.b -1) and (2 n .sbsp.c -1). In the preceding example one may choose, for example, a numerator equal to the power of 2: 
     
         F=(128/5)F.sub.1 =400 kHz. 
    
     The period 1/F is then equal to 2.5 μs. To avoid ambiguities in counting the clock bits starting from the front of the synchronization line, it suffices for example to ensure a delay of the order of 0.25 μs between the front of F 1  and that of F for a given line. This same delay will reoccur every five lines and, for the intermediate lines, it will take one of the values 0.75, 1.25, 1.75 and 2.25 μs without ever being zero. One will then have no difficulty in counting, after each front of a synchronisation line for example, the 24 first values of the necessary outputs for calculating the eight coefficients of the addresses using equation (19) or equation (20), not using the 25th value and, for three lines in five, the 26th value of the outputs. 
     Finally, one may choose the fraction by which F 1  is multiplied to obtain F in such a way that the clock frequency F is equal to the clock frequency F&#39; used for decoding binary audio channels, or is in a simple relationship with this frequency F&#39;. The pseudo-random binary address generator could then be common for the deciphering of the video channel and for deciphering one or more audio channels associated with the picture.