Frequency divider
FIELD OF THE INVENTION 
     The present invention relates to a frequency divider. 
     DESCRIPTION OF THE PRIOR ART 
     The frequency of conventional ac power, i.e. fifty or sixty hertz, is excessively high for specific ac appliances. For example, ac electric razor cuts off hairs into pieces when hairs are insufficiently inserted between the cutters of the ac electric razer. If the cutters are vibrated ten cycles per second, hairs are cut off when they are sufficiently inserted. The frequency of conventional ac power is excessively high for use in vibrating chair. In order to lower the frequency, so far cycloconverter or other relatively large-scale converter was used. 
     SUMMARY OF THE INVENTION 
     Accordingly, the major object of the present invention is to pick up ac sine waves at desirable wave intervals, which are then supplied to load: For example, six or ten hertz ac can be obtained from sixty hertz ac power by picking up every tenth or sixth sine wave respectively. 
     This object can be attained with an apparatus, comprising a thyristor connected in series to main current circuit; means for counting the wave number of alternating current; a trigger circuit for the thyristor, associated with the counting means; and means for resetting the counting means. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will hereinafter be explained with reference to the accompanying drawings: 
     FIG. 1 shows the basic circuit of an embodiment according to the invention; 
     FIG. 2 shows a frequency divider according to the invention; 
     FIG. 3 shows the waveform charts of the circuits as shown in FIGS. 1 and 2; 
     FIGS. 4 and 5 show reset signal generating-circuits wherein diodes are used; 
     FIG. 6 shows the waveform charts of the circuits as shown in FIGS. 4 and 5; 
     FIG. 7 shows a reset signal generating-circuit wherein load voltage is utilized; 
     FIGS. 8 and 9 show frequency dividers wherein a bidirectional triode thyristor is used; 
     FIG. 10 shows the waveform charts of the circuits as shown in FIGS. 8 and 9; 
     FIG. 11 shows the basic circuit of another embodiment according to the invention; 
     FIG. 12 shows the waveform charts of the circuit as shown in FIG. 11; 
     FIG. 13 shows a frequency divider according to the invention; 
     FIG. 14 shows a frequency divider wherein a transformer is used; 
     FIG. 15 shows the waveform charts of the example as shown in FIG. 14; 
     FIG. 16 shows the basic circuit of still another embodiment according to the invention; 
     FIG. 17 shows the waveform charts of the circuit as shown in FIG. 16; 
     FIG. 18 shows the basic circuit of further embodiment according to the invention; 
     FIG. 19 shows the waveform charts of the circuit as shown in FIG. 18; and 
     FIG. 20 shows an example wherein a bidirectional triode thyristor is used. 
    
    
     In the Figures, C indicates capacitance; D, diode; A, trigger circuit; R, resistance; T, transistor; E, waveform-modifier; SCR, reverse-blocking triode thyristor; F, decimal counter; DCR, bidirectional triode thyristor; J, voltage regulator diode; Z, load; P, current-detector; S, switch; and H, transformer. 
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows the basic circuit of an embodiment according to the invention. 
     In this circuit, the current from ac power source AC comes into IC decimal counter F through waveform-modifier E. Output terminals 0, 1, 2, . . . , 8, 9 can be desirably selected with switch S to couple decimal counter F with trigger circuit A. For example, when output terminal 5 is switched on, trigger circuit A is applied with the fifth sine wave counted from the switching-on. The output of trigger circuit A is applied to gate G of thyristor SCR to bring it into conduction. Thus, ac power source AC is coupled to load Z through bolt thyristor SCR and current-detector P. Resistance and diode are feasible as current-detector P. The voltage between current-detector P is applied to reset terminal 15, in order to return decimal counter F into the first state for subsequent counting. 
     In the circuit as shown in FIG. 2, ac sine wave is modified by resistance R and voltage regulator diode J 2  into voltage-regulated square wave which is then applied to input terminal 14 of IC decimal counter F. Instantly upon switching-on of output terminal 4, IC decimal counter F starts counting, and generates an output signal when the fourth sine wave comes. The current change appearing at resistance R 3  instantly produces a voltage signal at the emitter of transistor T 1 . This voltage signal is applied through resistance R 6  to gate G of thyristor SCR to bring it into conduction. Thus, ac current comes into load Z. 
     Simultaneously, resistance R 5  receives current to generate a voltage drop with a waveform as shown in upper &#34;R 5  &#34; chart, FIG. 6. Such voltage drop is differentiated at capacitance C into a pulse wave with a waveform as shown in lower &#34;R 5  &#34; chart, FIG. 6. Counting with decimal counter F is restarted by applying the pulse wave to reset terminal 15. 
     By successive repetition these operations, the load circuit can be conducted at desirable wave intervals. 
     Resistances R 1  and R 2 , diode D, capacitance C 2 , and voltage regulator diode J 1  form a dc power supply. 
     FIG. 3 shows the current waveforms appearing in these circuits: Chart &#34;AC&#34; shows the waveform appearing at input terminal AC. Chart &#34;Z&#34; shows the waveform of load current wherein ac sine wave is conducted at intervals of two positive half-cycles, e.g. first-, third-, and fifth-half-cycle. Chart &#34;DCR&#34; shows the full-sine wave output by bidirectional triode thyristor. Chart &#34;B&#34; shows a conduction at intervals of two positive half-cycles. By setting the time constant of trigger circuit A at a longer level, successive two positive half-cycles can be conducted at desirable intervals as particularly shown in chart &#34;D&#34;. 
     FIG. 4 shows an example wherein series diodes D 1  and D 2  are inserted in the current circuit to form a reset signal generating-circuit. This example is characterized in that the voltage between series diodes D 1  and D 2  remains unchanged even when circuit current is varied. Such voltage is amplified by grounded-emitter transistor T 2  to obtain square wave as particularly shown in chart &#34;M&#34;, FIG. 6. The square wave is differentiated by capacitance C and resistance R 8 , and the resultant pulse wave is then used to reset IC decimal counter F. 
     FIG. 5 shows the circuit diagram of a frequency divider wherein the mode of transistor connection is reverse to that of shown in FIG. 4: The voltage between series diodes D 1  and D 2  is amplified by grounded-base transistor T 2  to obtain a pulse wave with a waveform as shown in chart &#34;N&#34;, FIG. 6; such pulse being reverse in polarity to that as shown in chart &#34;M&#34;. The output signal of the circuit as shown in FIG. 4 is reverse in phase to ac power source because the transistor is emitter-grounded, while with the circuit as shown in FIG. 5 an in-phase signal can be obtained because transistor T 2  is base-grounded. These signals are feasible to control the reset time of IC decimal counter F. 
     FIG. 7 shows an example wherein the voltage between load Z is supplied to voltage regulator diode J 3  through resistance R 10  and then voltage-regulated. For the use as the reset signal, the voltage is applied to the gate of thyristor SCR while insulating the voltage from the primary circuit with transformer H. 
     FIG. 8 shows the circuit diagram of a frequency divider wherein bidirectional triode thyristor DCR is used. The output current waveform is given in chart &#34;C&#34;, FIG. 10. 
     FIG. 9 shows the circuit diagram of a frequency divider using bidirectional triode thyristor DCR, wherein the voltage between diodes D 3  and D 4  is utilized to reset decimal counter F. Since the thyristor is bidirectional, diodes D 3  and D 4  are connected in reverse-parallel, and the voltage therebetween is amplified by transistor T 2  and then used to reset decimal counter F. 
     FIG. 11 shows the basic circuit of another embodiment according to the invention. 
     In this circuit, ac power source AC charges capacitance C through diode D 1  and resistance R 1 . As shown in chart &#34;A&#34;, FIG. 12, the voltage between capacitance C increases every positive half-cycle dependently on the time constant determined by capacitance C and resistance R 1 . the positive half-cycle from the first- to the fourth-positive half-cycles charge capacitance C. When the fifth positive half-cycle comes, capacitance C is discharged through thyristor SCR 2  dependently on the time constant determined by capacitance C and resistance R 2 . When the voltage between capacitance C reaches a prescribed level, then the partial voltage determined by the ratio of resistances R 4  and R 5  is applied to voltage regulator diode J or a neon discharge lamp to bring either discharge device into conduction through resistance R 3 . The voltage drop between resistance R 3  triggers thyristor SCR 2  to instantly discharge capacitance C through resistance R 2 , while the voltage drop between resistance R 2  triggers thyristor SCR 1 . Thus, load Z is supplied with a current having a waveform as shown in chart &#34;Z&#34;, FIG. 12. 
     Chart &#34;A&#34; in FIG. 12 shows the waveform of an integrated voltage which has been charged in capacitance C through diode D 1  and series resistance R 1 . This voltage increases stepwise dependently on the time constant determined by capacitance C and resistance R 1 . In such waveform, the voltage reaches the conduction voltage of voltage regulator diode J and current comes into resistance R 3  when the fifth positive half-cycle comes. Thus, thyristor SCR 2  is triggered, and capacitance C is discharged in accordance with curve &#34;CR 2  &#34;. The voltage drop generated between resistance R 2  by the discharge current is applied to the gate of thyristor SCR 1  to bring it into conduction. Thus, current comes into load Z. 
     FIG. 13 shows the circuit diagram of a frequency divider wherein thyristor SCR 1  is triggered by utilization of the ac voltage therebetween. 
     In this circuit, when thyristor SCR 1  is not in conduction, ac power source AC is applied to thyristor SCR 1  to charge capacitance C through resistance R 1  and diode D 1  in accordance with curve &#34;CR 1  &#34; as shown in FIG. 12. The charge voltage between capacitance C is divided by resistances R 4  and R 5 , and the partial voltage between resistance R 4  is then applied to voltage regulator diode J. When the voltage between voltage regulator diode J reaches a prescribed level, current comes into voltage regulator diode J to give a voltage drop between resistance R 3 . This voltage drop is applied to the gate of thyristor SCR 2  to bring it into conduction. Consequently, capacitance C is discharged through resistance R 2  in accordance with curve &#34;CR 2  &#34; in FIG. 12. The voltage drop generated at resistance R 2  by the discharge triggers thyristor SCR 1 , connected in the main current circuit, supplies to load Z with a current consisting of positive half-cycles as shown in chart &#34;Z&#34;, FIG. 12. 
     Capacitance C T  in FIG. 11 circuit may be used as the timing capacitance. 
     FIG. 14 shows an example wherein transformer H is used to supply trigger signal to thyristor SCR 1 . This example has a merit that ac phase can be freely chosen. Ac power source AC charges capacitance C through load Z, diode D 1  (connected in reverse parallel to thyristor SCR 1 ) and resistance R 1 . Voltage regulator diode is arranged in such a manner that the current across it triggers thyristor SCR 2 , and that its output is applied to thyristor SCR 1  through transformer H. Thus, either positive- or negative-half-cycle can be freely conducted by desirably selecting the polarity of either primary- or secondary-coil of transformer H. 
     FIG. 15 illustrates such operation. A discharge, as shown with curve &#34;CR 2  &#34;, generates a voltage signal as shown with curve &#34;H&#34; at the secondary coil of transformer H. Since the current across transformer H is in-phase to the voltage between thyristor SCR 1 , the polarity of load current, i.e. &#34;Z-&#34; or &#34;Z+&#34;, can be freely set by desirably selecting the polarity of transformer H. 
     FIG. 16 shows the basic circuit of still another embodiment. 
     In this circuit, the main current circuit is connected to ac power source AC through load Z, thyristor SCR 1 , and series diodes D 2  and D 3 . The primary coil of transformer H is connected to ac power source AC, while the secondary coil is connected in reverse polarity to ac power source AC to charge capacitance C through resistance R 1  and diode D 1 . As shown in FIG. 17, the charge voltage between capacitance C is increased stepwise, and then divided by variable resistance VR. When the partial voltage reaches the conduction voltage of voltage regulator diode J, thyristor SCR 2  is triggered and capacitance C is discharged through resistance R 5 , thyristor SCR 2 , and resistance R 2  connected in series. Thus, the circuit current continuously generates a voltage drop at resistance R 2 . Such voltage drop brings thyristor SCR 1 , connected with the main current circuit, into conductive state, and thyristor SCR 1  stands ready for the next cycle. 
     Chart &#34;A&#34; in FIG. 17 shows the waveform of ac power source AC, wherein symbols 1, 2, 3, . . . , and 7 indicate positive half-cycles, while symbols 11, 12, 13, . . . , and 17 indicate negative half-cycles. As shown in chart &#34;B&#34;, FIG. 16, when the voltage between capacitance C reaches level &#34;E&#34; and the partial voltage divided by variable resistance VR increases to the conduction voltage of voltage regulator diode J, the current across voltage regulator diode J conducts thyristor SCR 2 , followed by discharge of capacitance C through resistance R 5  to retain conduction. Although the voltage drop generated between resistance R 2  by the discharge current conducts in part the gate of thyristor SCR 1  connected with the main current circuit, thyristor SCR 1  connected with the main current circuit is still not triggered because the node voltage of thyristor SCR 1  remains negative. Thus, thyristor SCR 1  stands ready for the next negative half-cycle, i.e. those as shown in chart &#34;A&#34; with symbols 13 and 16. 
     Instantly after application of negative half-cycles 13 and 16 to the anode of thyristor SCR 1 , load Z is applied with these negative half-cycles in a manner as shown in FIG. 17 with chart &#34;C&#34;. The current across the main current circuit generates at series diodes D 1  and D 2  a voltage drop which then triggers thyristor SCR 3  to instantly discharge capacitance C. Thus, the whole circuit is resetted. 
     By successive repetition of these operations, an ac current with a desirable frequency can be supplied to load. 
     FIG. 18 shows the basic circuit of further embodiment according to the invention. 
     In this circuit, ac power source AC is appropriately phase-shifted by the circuit consisting of resistance R 2  and capacitance C 2 . The phase-shifted voltage is applied to the base of grounded-emitter transistor T through resistance R 3 . FIG. 19 illustrates these operations. Chart &#34;A&#34; in FIG. 19 shows the alternating waveform of ac power source AC. Chart &#34;B&#34; indicates the ac power source AC is phase-shifted by θ. When the phase-shifted voltage is applied to transistor T through R 3 , then the output waveform at the collector is changed as shown in FIG. 19 with chart &#34;C&#34;. A large input signal comes into transistor T to give a saturated waveform. The collector output of transistor T is supplied to the gate of thyristor SCR 1 , connected with the main current circuit, through variable resistance VR. Thus, a current with a waveform as shown with chart &#34;D&#34; comes into load Z. 
     The integrating circuit consisting of series resistance R 1 , diode D, and capacitance C is arranged to form dc power supply for transistor T. The time constant determined by series resistance R 1  and capacitance C is associated with the swiching-timing of the current circuit: Capacitance C is charged in accordance with the time constant determined by series resistance R 1  and capacitance C. As shown in in chart &#34;E&#34;, FIG. 19, positive half-cycles stepwise increase the charge voltage between capacitance C. When the voltage reaches a prescribed level, the output voltage of transistor T is supplied to the gate of thyristor SCR 1  through variable resistance VR in a manner as shown in FIG. 19. In the waveform as shown in chart &#34;C&#34;, variable resistance VR is set in such a manner that thyristor SCR 1  is triggered when the third positive half-cycles comes. By desirably adjusting variable resistance VR, ac sine waves can be conducted, e.g. every cycles, every second cycles, or every third cycles. 
     If the output of transistor T is set in such a manner that thyristor SCR 1  is triggered every third cycles, then a divided ac current with a waveform as shown in chart &#34;D&#34; comes into load Z. Such current generates a voltage between series diodes D 2  and D 3  connected in series to thyristor SCR 1 , and the voltage is then applied to thyristor SCR 2 . Thyristor SCR 2  instantly discharges capacitance C through R 6  to give a waveform as shown in chart &#34;E&#34;, FIG. 19. Thus, the whole circuit is resetted. 
     By successive repetition of operations, the main current circuit is continually conducted. 
     FIG. 20 shows an example wherein bidirectional triode thyristor DCR is used to conduct whole cycles. 
     The frequency divider according to the invention is simple and usable, if necessary, in combination with half wave- or full wave-rectifier, to supply 1-120 hertz ac to ac appliances from lamp wire. As in the case of ac electric razor, electric hair clipper, and vibrators as disclosed in Japan Patent Application Nos. 67,013/84 and 69,929/84, the frequency divider according to the invention can be favorably used for ac appliances wherein an alternating frequency lower than that of conventional ac power is desirable. 
     Having described the invention according to the embodiments shown in the accompanying drawings, it is my intention that the invention be not limited by any of the details of description, but rather be construed broadly within its spirit and scope as set out in the accompanying claims.