Staircase ramp voltage generating apparatus with energy reuse
BACKGROUND OF THE INVENTION 
     This invention relates to apparatus for generating ramp voltages. More particularly, it is concerned with apparatus for repeatedly providing an ascending and descending staircase ramp voltage to a capacitive load. 
     Capacitive type displays, such as thin film electroluminescent displays, waste a large portion of the total addressing power simply in the charging and subsequent discharging of elements which are not addressed. Typically in order to minimize charging currents a ramp voltage is applied to row and/or column address buses to charge the buses and their associated capacitive load to the appropriate voltage. The ramp voltage may be produced by selectively connecting an array of voltage sources in sequence to a bus in order to produce a staircase ramp voltage. After the appropriate time interval following the end of the ramp voltage buildup the bus is returned to ground potential. Discharging the charge stored in the capacitive load to ground is a primary cause of power loss in the operation of conventional addressing arrangements. 
     SUMMARY OF THE INVENTION 
     Apparatus in accordance with the present invention repeatedly provides an ascending and descending staircase ramp voltage to a capacitive load with improved efficiency. The apparatus comprises a conductive bus adapted to be coupled to a capacitive load. A plurality of voltage source means, each of which has an output terminal, are arranged in order. Each voltage source means except the first in order produces at its output terminal a voltage greater than that of the preceding voltage source means in the order. The apparatus includes an equal plurality of charge storage means, each being coupled to the output terminal of a different one of the voltage source means. Each of an equal plurality of switch means is connected between the output terminal of a different one of the voltage source means and the bus. Timing means are coupled to the plurality of switch means for actuating each of the switch means in order and subsequently in reverse order during each operating cycle of a series of operating cycles. The bus is charged to a voltage approximately equal to the voltage of each voltage source means when the associated switch means is being actuated in order, thereby providing an ascending staircase ramp voltage on the bus as the switch means are actuated in order. The bus discharges to a voltage greater than the voltage of each voltage source means except for the last voltage source means in the order when the associated switch means is being actuated in reverse order, thereby producing a descending staircase ramp voltage on the bus as the switch means are actuated in reverse order. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is a schematic circuit diagram of apparatus in accordance with the present invention for repeatedly providing an ascending and descending staircase ramp voltage to a capacitive load; 
     FIG. 2 illustrates the timing signals employed in controlling the operation of the apparatus of FIG. 1; and 
     FIG. 3 illustrates the staircase ramp voltage output pulse produced during one operating cycle of the apparatus of FIG. 1. 
    
    
     For a better understanding of the present invention together with other and further objects, advantages, and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings. 
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 illustrates apparatus for producing an ascending and descending staircase ramp voltage in accordance with the present invention. The apparatus includes a conductive bus 10 which is connected to a capacitive load C L , as indicated in phantom in FIG. 1, by a semiconductor switch or driver Q S . The capacitive load may be provided, for example, by the row and/or column of elements being addressed in a thin film electroluminescent display. 
     The apparatus includes a set of DC voltage sources 12, 13, 14, and 15 (four being shown for illustrative purposes only), each being connected to an output terminal by way of a diode. The V 0 , V 1 , V 2 , and V 3  voltages produced at the output terminals by the voltage sources 12, 13, 14, and 15, respectively, increase in order, preferably in equal increments. The output terminal associated with each of the voltage sources 12, 13, 14, and 15 is connected through a semiconductor switching device, for example FET&#39;s Q B , Q C , Q D , and Q E , respectively, to the bus 10. An additional FET Q A  is connected between the bus 10 and ground. The output terminal associated with each of the voltage sources 12, 13, 14, and 15 is connected to ground through a capacitor C B , C C , C D , and C E , respectively, which serves as a charge storage reservoir as will be explained hereinbelow. 
     The gates of each of the FET&#39;s Q A , Q B , Q C , Q D , and Q E , labeled A, B, C, D, and E, respectively, are connected to a timing circuit 11 which controls operation of the FET&#39;s. FIG. 2 illustrates the control pulses produced by the timing circuit 11 to each of the gates A-E during an operating cycle of the apparatus. For purposes of this discussion, each FET will be assumed to be actuated during a positive-going pulse, providing a closed switch. 
     FIG. 3 illustrates the voltages produced on the bus 10 during an operating cycle of a sequence of control voltages illustrated in FIG. 2, while the bus 10 is connected to a capacitive load C L  as by actuation of a switching FET Q S . In the example shown and described the voltages V 1 , V 2 , and V 3  increase in increments, in this case each increment being equal to V 0 , from the preceding voltage in the order, V 0  being the first voltage in the order. The capacitors C B , C C , C D , and C E  are charged to the voltage V 0 , V 1 , V 2 , and V 3  produced at the output terminals of the voltage sources 12, 13, 14, and 15, respectively. 
     At time t 0  the bus 10 is at ground. Between time t 0  and t 1  voltage source 12 is connected to the bus 10 by actuating FET Q B . The bus 10 and associated capacitive load C L  are charged to voltage V 0 . During the period t 1  to t 2  the timing circuit 11 provides signals whereby the voltage source 13 is connected to the bus 10 and the voltage on the bus increases to voltage V 1 . During the period t 2  to t 3  the voltage on the bus 10 increases to V 2 , and during the period t 3  to t 4  to V 3 . Thus, an ascending staircase ramp voltage is produced on the bus 10 charging up the capacitive load C L . As indicated previously, this pulse shape is desirable for addressing the elements in capacitive load apparatus such as electroluminescent displays in order to limit the current through row or column drivers represented by Q S  in this example and thereby control I 2  R losses in these devices. 
     When it is desired to discharge the capacitive load, the switching FET&#39;s are actuated in reverse order (Q D , Q C , Q B , and Q A ) At time t 4  when FET Q D  is actuated, the voltage stored in the capacitive load C L  and consequently the voltage on the bus 10 is V 3 . This voltage is applied to the capacitor C D  which is connected to the output terminal associated with voltage source 14. During the period t 4  to t 5  while FET Q D  is actuated, the voltage stored in the capacitive load C L  and on the bus 10 drops from V 3  toward the voltage V 2  of the voltage source 14. At time t 5  the capacitive load C L  has discharged such that the voltage on the bus 10 has dropped to a value of V 2  +ΔV 2  as indicated in FIG. 3. This voltage remains stored across capacitor C D . 
     Similarly, during the period t 5  to t 6  the voltage on the bus 10 drops from V 2  +ΔV 2  to V 1  +ΔV 1 , as illustrated in FIG. 3, with the capacitor C C  storing a voltage of V 1  +ΔV 1 . From time t 6  to t 7  the voltage on the bus 10 drops to V 0  +ΔV 0  and a voltage of V 0  +ΔV 0  is stored in capacitor C B . During the period t 7  to t 8  when FET Q A  is actuated, the capacitive load C L  and the bus 10 are discharged to ground. 
     Thus, the apparatus produces a descending staircase ramp voltage as illustrated in FIG. 3 storing an increment of voltage ΔV i  above the voltage V i  of its associated voltage source in each of the storage capacitors. As each switching FET is actuated in order during the next operating cycle, the voltage on the associated capacitor drops from V i  +ΔV i  to V i  as the bus 10 and capacitive load C L  are charged to V i . Thus the energy represented by the incremental voltage ΔV i  stored during the descending portion of the previous pulse is reused. The incremental voltage ΔV i  is given by ##EQU1## The energy stored and reused and, therefore, saved in each storage capacitor C i  during each operating cycle is C i  (V i  +1/2ΔV i )ΔV i . The associated voltage source provides the remainder of the energy required to raise the bus 10 and capacitive load C L  to the appropriate voltage V i  of the step. In the exemplary apparatus shown in FIG. 1 four storage capacitors are shown to provide a four-step staircase ramp pulse. More storage capacitors together with associated circuitry may be employed to increase further the amount of energy saved during each operating cycle while further limiting maximum values of current through driver Q S . The costs involved in increasing the complexity of the apparatus must be balanced against the improvement in current peaks and in energy savings to determine the optimum number of storage capacitors for each particular situation. 
     While there has been shown and described what is considered a preferred embodiment of the present invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention as defined by the appended claims.