SP sound synthesizer
BACKGROUND OF THE INVENTION 
     The present invention relates to an LSP sound synthesizer which can singly synthesize a human voice and the notes of birds or insects, which have different distribution functions, resulting in a high quality effect. 
     In the field of sound synthesizing, a line spectrum pair (LSP) system has been developed and put to practical use. The LSP can synthesize sounds with a less amount of the sound data than the known PARCOR system, and can keep the synthesized sound at a predetermined quality level or at a higher level. 
     In synthesizing voices by the LSP system, the voices are nonlinearly quantized using the distribution functions of LSP parameters which differ with the kinds of the voices used. The quantized voice data is used for synthesizing the original voices. This method, which quantizes the sounds using the distribution functions of LSP parameters, is advantageous is that a small number of bits are required for forming a specific sound, that is, the sound information is reduced. However, it has some disadvantages. 
     When sounds with different distribution functions of LSP parameters, for example, a human voice and the notes of birds or insects, a quality of the sound synthesized by a single synthesizer is remarkably poor. FIG. 1A shows a graph illustrating voice distribution functions obtained from LSP parameters w of a female voice. FIGS. 1B and 1C show sound distribution functions of the notes of a bird and an insect, respectively. As seen from these figures, characteristic curves representing voice distribution functions of the human voice are uniformly distributed with respect to frequency. If the case of the bird&#39;s notes, the characteristic curves are distributed mainly in the middle frequency region. In the case of the insect&#39;s notes, the characteristic curves are chiefly in the high frequency region. Obviously, the frequency distributions of the characteristic curves differ according to the kinds of sounds used. Hardware for the synthesizer, which is designed so as to nonlinearly quantize voices using voice distribution functions based on the frequency distributions of a human voice, requires some modification if it is used to achieve hardware for the nonlinear quantization of the notes of birds or insects. If it is applied for such without any modification, the conversion of the LSP parameters w is inevitably accompanied by the inversion of the parameters. This parameter inversion deteriorates the synthesized sound quality so much that the synthesized and reproduced notes of birds or insects have no resemblance to the original ones. For these reasons, the technique for synthesizing the human voice and the notes of birds or insects by means of a single synthesizer is considered inappropriate. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention is to provide an LSP sound synthesizer which can singly perform a sound synthesization, of a human voice and the notes of birds or insects, resulting in a high quality effect. 
     To achieve this object, an LSP sound synthesizer according to the present invention comprises: 
     sound data memory means for storing sound data including sound source reference value data, parameter data, frame data, pitch data and amplitude data; 
     parameter converting means connected to the sound data memory means, for producing, on the basis of an inverse transform, converted parameter outputs; 
     sound source circuit means connected to the sound data memory means for receiving the pitch data and sound source reference value data from the sound data memory means and producing a predetermined sound source output; and 
     digital filter means connected to the parameter conversion means and the sound source circuit means, the digital filter means synthesizing sounds on the basis of the frame data and the converted parameter outputs. 
     The parameter conversion means of the sound synthesizer of the invention stores a plurality of inverse transform functions and reads out an inverse conversion function which is most suitable for a sound to be synthesized. Since such a function for the sound synthesizing is used, the sound synthesizer can singly synthesize sounds having different distribution functions into a high quality effect. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A to 1C are graphs showing the frequency distributions of distribution functions of the voice of a human, and the notes of birds and insects; 
     FIG. 2 is a block diagram of an LSP sound synthesizer which is an embodiment of the present invention; 
     FIG. 3 is a block diagram of the key section used in the device shown in FIG. 2;, 
     FIG. 4 illustrates the inverse transform functions stored in a parameter conversion circuit 6 shown in FIG. 2; 
     FIG. 5 is a flow chart illustrating the operation of this invention; 
     FIG. 6 is a block diagram of an interpolation circuit 10 and a timing control circuit 3, which are shown in FIG. 2; 
     FIG. 7 graphically illustrates a relationship of a vocalizing rate and a parameter interpolation; 
     FIG. 8 is a block diagram of the sound circuit shown in FIG. 2; 
     FIG. 9 shows a waveform of pitch impulses produced by the sound source circuit shown in FIG. 8; 
     FIG. 10 is a table illustrating impulse sound source data selected by sound source reference values A and B; 
     FIG. 11 is a block diagram of the digital filter shown in FIG. 2; 
     FIG. 12 shows a block diagram of another digital filter which may be used in the device shown in FIG. 2; 
     FIG. 13 shows a table showing generation timings of various types of timing signals for use in controlling key portions in the circuit of FIG. 12; 
     FIGS. 14A and 14B show a circuit diagram of the multiplier 90 shown in FIG. 12; 
     FIGS. 15A and 15B show a table showing input and output data in key portions of the circuits of FIG. 12 and FIGS. 14A and 14B; 
     FIG. 16 illustrates a divided state of multiplying data; 
     FIG. 17 shows input and output data in key portions in the multiplier section shown in FIG. 12; 
     FIG. 18 shows a circuit arrangement of the clip shifter 91 shown in FIG. 12. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     An embodiment of the present invention will be described referring to the accompanying drawings. In FIG. 2, a timing signal generator 1 produces timing signals, which are supplied to a controller 2 and a timing control circuit 3. Control command signals are transferred from the controller 2 to a sound data ROM 4, an initial data address table ROM 5 (hereinafter referred to as an INA table ROM) and a parameter converter 6. The controller 2 controls the operations of the necessary portions in response to the input information externally applied. The sound data ROM 4 and INA table ROM 5 are addressed by the controller 2, so that the contents (i.e., sound data) of the sound data ROM 4 and the contents (i.e., initial data including address data) of the INA table ROM 5 are read out and loaded into editing buffers 7a and 7b, respectively. The data loaded into the buffer 7b is transferred to the controller 2, the sound data ROM 4 and the parameter converter 6. Sound reference values A and B from the editing buffer 7b are transferred to a sound source 8. The sound source reference values A and B take a combination of two bits. Four combinations, &#34; 0,0&#34;, &#34;1,0&#34;, &#34;0,1&#34; and &#34;1,1&#34; are properly combined to provide four reference values, in the case of a voiced sound. The sound data held in the editing buffer 7a is transferred to the parameter converter 6 and an amplitude circuit 9. Of the sound data, the pitch data is transferred to the sound source 8 and the frame data to the timing control circuit 3 and an interpolator 10. The output signals I 1  to I 10  from the parameter converter 6 and the amplitude circuit 9 are interpolated by the interpolator 10 and supplied as parameter outputs O 1  to O 10  to a digital filter 11. In the case of the voiced sound, the sound source 8 selects one of the four reference values and produces sound data Z 1  to Z 15  of 15 bits, which are to be transmitted to the digital filter 11. The timing control circuit 3 generates a timing signal according to the frame data delivered from the buffer 7a and supplies it to the interpolator 10 and the digital filter 11. The digital filter 11 performs an LSP sound synthesization using the sound parameter outputs O 1  to O 10  coming through the interpolator 10 and the sound data Z 1  to Z 15  derived from the sound source 8. A digital sound signal produced from the digital filter 11 is converted into an analog sound signal by a digital-to-analog (D/A) converter 12. 
     A combination of the sound data ROM 4, INA table ROM 5, parameter converter 6, and amplitude circuit 9 will be described in detail referring to FIG. 3. In the figure, a latch circuit 21 latches address data for the sound data ROM 4 which is delivered from the controller 2. The 4-bit data is read out from the sound data ROM 4 and the INA table ROM 5 and then temporarily stored in the editing buffers 7a and 7b. The 4-bit data held in the buffer 7b is transferred to the latch circuit 21 and two bits of the 4-bit data is transferred to the parameter converter 6. The parameter converter 6 is comprised of latch circuits 22 to 24, a ROM 25, and a tristate bus buffer 26. By a command from the controller 2, 2-bit data derived from the buffer 7b is latched in the latch circuit 22. The 4-bit data from the buffer 7a is latched in the latch circuit 23. The address data from the controller 2 is latched in the latch circuit 24. The data held in the latch circuits 22 to 24 are input as address data A 9  to A 1  to the ROM 25. As shown in FIG. 4, the ROM 25 has four memory areas 25a to 25d. The first memory, area 25a stores a reverse conversion, (i.e. inverse transform) function 1 whose frequency distribution is uniform so as to adapt for a human voice. The second to fourth memory areas 25b to 25d store reverse conversion functions 2 to 4 whose frequency distributions are concentrated in the middle and high frequency regions so as to be adapted for the notes of birds and insects. These memory areas 25a to 25d of the ROM 25 are selectively specified by the address bits A 9  and A 8  held in the latch circuit 22. For example, as shown in FIG. 4, when A 9  and A 8  are &#34;00&#34;, the first memory area 25a is specified. When they are &#34;01&#34;, the second memory area 25b is selected. With &#34;10&#34; of the address bits, the third memory area is specified. With &#34;11&#34;, the fourth memory area is specified. Further, from the ROM 25, 10-bit data is read out after the ROM is addressed by the bit data A 9  to A 1  and then temporarily stored in the buffer 26. The buffer 26 reads out data from the ROM 25 by a read command applied via an inverter 27 from the controller 2. 
     The amplitude circuit 9 is composed of a tristate bus buffer 32 for temporarily storing amplitude data representing a stress of a sound in the form of an amplitude, which is produced from the amplitude generator 31 for converting the 4-bit amplitude data from the editing buffer 7a into 10-bit amplitude data. The buffer 32 temporarily stores data coming from the amplitude generator 31 by a read command delivered from the controller 2. In this case, the read command is applied to the buffer 26 in the parameter converter 6 by way of the inverter 27, so that either of the buffers 26 and 32 is specified and the data stored therein is transferred as I 1  to I 10  to the interpolator 10. The parameter converter 6 as mentioned above is designed such that the parameter number is &#34;8&#34; and a 4-bit parameter is converted into a 10-bit parameter. 
     The operation of the above-mentioned embodiment will be described with reference to a flowchart in FIG. 5. The controller 2, when externally applied with input data, makes an access to the INA table ROM 5 to read out the initial data and a start address therefrom and to load them into the buffer 7b. Then, the synthesizer starts synthesizing sounds. The signals A and B for setting the sound source reference values are read out from the INA table ROM 5, transferred to the parameter converter 6 and set in the latch circuit 22. With the data latched in the latch circuit 22, one of the memory areas 25a to 25d of the ROM 25 is selectively specified. At this point, the setting of the initial condition is completed. The controller 2 advances the control step to a step S2. In the step S2, sound data is read out from the sound data ROM 4. In the next step S3, the preprocessing for the sound synthesizing is executed. In this synthesizer, the data of 4 bit-word is read out from the sound data ROM 4 and loaded into the buffer 7a. The editing is performed under the gate-control. The frame data is expressed by 12 words, 11 words or 2 words. In the step S3, it is determined whether the sound data read out from the format stored in the sound data ROM 4 is the sound data of the soundless frame or the sound frame. When it is the sound data of the soundless frame, the number of the soundless frames of the sound data is detected in the timing control circuit 3. On the other hand, when it is the sound data of the sound frame, it is determined whether the sound data is the initial data of the pitch data, pitch difference data of the pitch data, or unvoiced sound. Further, in the step S3, it is determined how long the frame data is, 128 sounds/frame, 256 sounds/frame or 512 sounds/frame long. Then, it is input to the interpolator 10 to perform a differential value control. If an end code is detected, the control flow ends at the step S3. Then, the controller 2 advances the control step to a step S4. In this step, when the pitch data is the pitch difference data, it is added to the value previously sent to the interpolator 10. When the sound data is the unvoiced sound, the pitch data is output as &#34;0&#34; to the sound source 8. Then, the controller 2 advances the control step to a step S5. In this step, the voice parameter of eight words (i.e., the parameter w i ) is read out from the sound data ROM 4 and transferred to the parameter converter 6 and latched in the latch circuit 23. The controller 2 sends the address data of the lower three bits for the ROM 25 to the parameter converter 6. This address data is latched the data in the latch circuit 24 of the parameter converter 6. The ROM 25 is addressed by the address data set in the latch circuits 22 to 24. An inverse transform function of 10 bits is read out from the ROM 25. In this case, one of the memory areas 25a to 25c is specified by the data latched in the latch circuit 22 to specify one of the inverse transform functions 1 to 4, which is adaptable for a human voice or the notes of a bird or insect. The data read out into the buffer 26 is sent to the interpolator 10 and interpolated as indicated in a step S6. The output signals O 1  to O 10  are sent at predetermined timings to the digital filter 11. A voice/unvoiced sound and a sound source value corresponding to the pitch data, which are derived from the sound source 8, and the amplitude data from the amplitude circuit 9 are transferred to the digital filter 11 at a predetermined timing. Then, the digital filter 11 performs the sound synthesization on the basis of a predetermined algorithm, as in the step S7. In the step S8, the sound data ROM 4 is incremented and the control flow returns to the step Sl. The above operation is repeated to execute the sound synthesization. The output of the digital filter 11 is converted into an analog sound signal by the digital to analog converter 12. 
     In the above-mentioned embodiment, four distribution functions are stored in the ROM 25 of the parameter converter 6. For further improving the quality of the sound synthesized, it is sufficient to increase the number of distribution functions. 
     A practical arrangement of the interpolator 10 will be described referring to FIG. 6, in connection with the timing control circuit 3. A control circuit 40 in the timing control circuit 3 is supplied with a timing signal from the timing signal generator 1 in FIG. 1 and the frame data from the controller 2. The control circuit 40 selects one of the reference frame lengths, i.e., 128 sounds, 256 sounds or 512 sounds long, according to the frame data derived from the controller 2 and applies it via an output line a to a coincidence circuit 41. At the same time, the control circuit 40 applies a target frame length to a coincidence circuit 42 via an output line b. The control circuit 40 produces a clock pulse CLK at 8 KHz, for example, which is in synchronism with one sound frame and applies it to a frame counter 43. The frame counter 43 counts the clock pulse CLK and applies the count to the coincidence circuits 41 and 42. The coincidence circuit 41 compares the reference frame length with the contents of the frame counter 43. When both data coincide with each other, it produces and applies a coincidence signal to an AND circuit 44. The coincidence circuit 42 compares the target frame length with the contents of the frame counter 43. When both data coincide with each other, it produces and applies a coincidence signal to an AND circuit 44 via an inverter 45 and also produces a target frame clock φ BE . The output of the AND circuit 44 is produced as a reference frame clock φ AF . The frame clocks φ AF  and φ BF  are transferred to the interpolator 10. An inverted signal φ BF  of the target frame clock φ BF  is applied to the reset terminal R of the frame counter 43. The frame counter 43 is reset only at the leading edge of the clock φ BF . 
     The interpolator 10 contains an adder 46 whose input terminal a is supplied with the data I 1  to I 10  from the parameter converter 6 or the amplitude circuit 9 in FIG. 2. The output of the adder 46 is applied through a gate 47 to a RAM 48 and is applied through a gate circuit 49 en route to a shifter 50 in synchronism with the frame clock φ BF . Further, the output of the RAM 48 is applied to the shifter 50 through the gate circuit 49 at the timings of the clocks φ AF  and φ BF . Further a logical &#34;0&#34; signal is applied to the shifter 50 at the timing of the clock φ AF . The shifter 50 shifts the 10-bit input data by 7 to 9 bits according to a variable frame signal of 2 bits from the buffer 7a, and applies it to the input terminal a of an adder 51. The output signal of 19 bits from the adder 51 is loaded into a RAM 52. The 19-bit data read out from the RAM 52 is input to the input terminal b of the adder 51 and the upper 10 bits data is input to the input terminal b of the adder 46 at the timing of the frame clock φ BF . The adder 46 subtracts the data input to the input terminal b from the data input to the input terminal a to have a difference therebetween. Of the 19-bit data read out from the RAM 52, the upper 10 bits are supplied as the output of the interpolator 10 to the digital filter 11. The control circuit 40 produces and applies the target frame length through an output line b to the coincidence circuit 42. Further, it produces and applies a clock pulse CLK through an output line c to the frame counter 43. Upon receipt of the clock pulse CLK, the frame counter 43 performs the count-up operation. When the count of the frame counter 43 becomes coincident with the reference frame length, the coincidence circuit 41 produces a coincident signal. When this signal is coincident with the target frame, the coincidence circuit 42 produces a coincident signal. When the target frame length is longer than the reference frame length, that is to say, the sounding rate is lower than the reference value (SLOW), the coincidence circuit 41 produces a coincident signal. At this time, the output of the coincidence circuit 42 is logical &#34;0&#34; and the output of the inverter 45 is logical &#34;1&#34; which is applied to the AND circuit 44. Accordingly, the output of the coincidence circuit 41 is output as the frame clock φ AF  through the AND circuit 44. Then, the frame counter 43 counts the clock CLK up to the target frame length. At this time, the coincidence circuit 42 produces a frame clock φ BF . When the target frame length is equal (NORMAL) to or shorter (FAST) than the reference frame length, the coincidence circuit 42 produces a coincidence signal as the frame clock φ BF . When the coincidence circuit 42 produces a coincidence signal, the output of the inverter 45 is logical &#34;0&#34; and the AND circuit 44 is prohibited from producing an output signal. Then, when the frame counter 43 is incremented by one, the output φ BF  of the coincidence circuit 42 is logical &#34;0&#34; and the output φ BF , is logical &#34;1&#34; thereby to reset the frame counter 43. 
     In the interpolator 10, the interpolated data are sequentially loaded into the RAM 52. When the frame clock φ BF  is produced from the coincidence circuit 42, the target value in the frame is already stored into the RAM 52. The upper 10-bit value is input to the input terminal b of the adder 46 in synchronism with the frame clock φ BF . At this time, the output signals I 0  to I 10  of the parameter converter 6 or the amplitude circuit 9 shown in FIG. 2 are supplied to the input terminal a of the adder 46. The adder 46 subtracts the preset value supplied to the input terminal b from the next target value supplied to the input terminal a, thereby to obtain a difference thereof. The difference data output from the adder 46 is loaded into the RAM 48 in synchronism with the frame clock φ BF  and sent to the shifter 50 via the gate circuit 49. The shifter 50 shifts the difference data by 7 to 9 bits according to a variable frame signal of two bits. When the variable frame signal is &#34;00&#34; , the difference data is shifted by 7 bits (128); when it is &#34;01&#34;, the data is shifted by 8 bits (256); when it is &#34;10&#34;, the data is shifted by 9 bits (512). In this way, a difference value D is obtained which depends on the reference frame length,. The difference value D can be obtained, at any sounding speed, by ##EQU1## The difference value D produced from the shifter 50 is sent to the adder 51 and added to the data stored in the RAM 52. Then, till either of the frame clocks φ AF  and φ BF  is produced from the timing control circuit 3, the differential data held in the RAM 48 is read out through the gate circuit 49, shifted to the shifter 50 and then transferred to the adder 51. In this way, the difference value D is sequentially added to the data stored in the RAM 52, thereby to perform an interpolation processing of the parameter. The parameter loaded into the RAM 52 varies, as shown in FIG. 7, according to the target frame length produced from the output line b of the control circuit 40, that is, the vocalizing rate, NORMAL, FAST or SLOW. In FIG. 7, a solid line a indicates NORMAL of the vocalizing rate, a one-dot chain line b FAST, and a broken line c NORMAL. When the vocalizing rate is NORMAL, the target frame length is equal to the reference frame length. In the case of &#34;128&#34; of the reference frame length, when the count of the frame counter 43 reaches &#34;128&#34;, the coincidence circuit 42 produces a frame clock φ BF . The value stored in the RAM 52 is input to the adder 46 which in turn obtains a difference of it from the target value (I 1  to I 10 ) and writes the difference value into the RAM 48. In this way, the interpolation processing is continued till the target value is reached. 
     When the vocalizing rate is FAST, that is, the target frame length is &#34;120&#34;, for example, the coincidence circuit 42 produces a frame clock φ BF  when the count of the frame counter 43 reaches &#34;120&#34;. Upon this, a difference of the &#34;120&#34; from the next target is obtained in the adder 46, as described above, and is loaded into the RAM 48 where it is subjected to the interpolation processing. In this way, the difference value of the present parameter value from the next target value is obtained every 120 sounds, as indicated by the one-dot chain line. The interpolation processing is performed in a similar manner to that in the NORMAL vocalizing rate. 
     When the vocalizing rate is SLOW, that is, the target frame is &#34;140&#34;, for example, the frame clock φ AF  is produced from the coincidence circuit 41 through the AND circuit 44 when the count of the frame counter 43 reaches the reference frame length, &#34;128&#34;. When the frame clock φ AF  is produced, the data transfer from the RAM 48 to the shifter 50 is prohibited, and a logical &#34;0&#34; signal is input through the gate circuit 49 en route to the shifter 50. Accordingly, the shifter 50 produces the data of all 0&#39;s and applies it to the adder 51. The data read out from the RAM 52 to the adder 51 is written into the RAM 52. Thus, when the vocalizing rate is SLOW, the addition of the difference value D is stopped when the number of sounds reaches the reference value, &#34;128&#34;, as indicated by a broken line c. The parameter stored in the RAM 52 is held as it is. Then, when the count of the frame counter 43 reaches the target frame length, &#34;140&#34;, the coincident circuit 42 produces a frame clock φ BF . In response to the frame clock φ BF , the adder 46 produces a difference value of the present parameter value from the next target value and writes it into the RAM 48. As described above, the interpolator 10 can interpolate the voice parameter according to the vocalizing rate, thereby realizing a high quality sound synthesization. 
     Practical arrangements of the sound source 8 will be described referring to FIGS. 8 to 11. In FIG. 8, a latch circuit 60 latches the pitch data of 7 bits coming from the editing buffer 7a shown in FIG. 2 in synchronism with a predetermined timing signal. The bits of the data latched in the latch circuit 60 are respectively input to exclusive (EX) NOR circuits 61a to 61g. The 1-bit outputs of a 7-bit counter 62 are also applied to the exclusive (EX) NOR circuits 61a to 61g, respectively. The output signals from the exclusive (EX) NOR circuits 61a to 61g are supplied to an AND circuit 63. The output signals from the exclusive (EX) NOR circuits 61a to 61g are applied to an AND circuit 64. The output signals from the AND circuits 63 and 64 are applied through an AND circuit 65 en route to a flip-flop 66. The flip-flop 66 fetches the input signal in synchronism with a clock pulse φ 1  and applies a reset signal to the counter 62. The counter 62 counts a clock pulse at 8 KHz, for example. The 1-bit outputs of the counter 62 are applied to the exclusive (EX) NOR circuits 61a to 61g, respectively. Of those output bits, the three upper order bits are applied through a NOR circuit 68 to a NAND circuit 69. The four lower order bits are applied to the NAND circuit 69 through a NOR circuit 70. The output T of the NAND circuit 69 is applied directly or through an inverter 71 and NOR circuits 72 to 74 to an inverting buffer 75. The inverting buffer 75 has a 15-bit width. Of those 15 bits, the 1st to 5th bits are coupled with an output of the inverter 71; the sixth to eighth bits with outputs of NOR circuits 72 to 74; the 11th to 15th bits with an output of the NAND circuit 69; the 9th and 10th bits are grounded. Sound source reference values A and B coming through the buffer 7b shown in FIG. 2 are applied to the NOR circuits 72 to 74 via a NOR circuit 76, an inverter 77 and a NOR circuit 78. The reference values A and B are applied via the NOR circuit 76 to the NOR circuits 72 to 74 and further through the NOR circuit 78 to the NOR circuit 74. The reference value A is supplied via the inverter 77 to the NOR circuit 73. Of the pitch data stored in the latch circuit 60, the four upper order bits are supplied to a NOR circuit 79 and the three lower order bits to a NOR circuit 80. The outputs command to the inverting buffer 75 via the NAND circuit 81, and applied as an output command from the NAND circuit 81 to a white noise generator 83 through the inverter 82. With the output of the NAND circuit 81, the inverting buffer 75 or the white noise generator 83 is specified, and the output signal of the circuit 81 or generator 83 specified is transferred as sound data Z 1  to Z 15  to the digital filter 11. 
     When the sound source 8 shown in FIG. 8 receives a voice signal, it produces pitch impulses. When the pitch data is latched in the latch circuit 60, the counter 62 is reset and starts the counting operation again. When the counter 62 proceeds with the count-up operation and its contents are equal to the pitch data held in the latch circuit 60, the outputs of the exclusive (EX) NOR circuits 61a to 61g are all &#34;1&#39;s&#34;. Then, the outputs of the AND gates 63 to 65 are all &#34;1&#39;s&#34;, and a logical &#34;1&#34; is loaded into the flip-flop 66. The output of the flip-flop 66 resets the counter 62. In this way, the pitch period is set. When the counter 62 is reset, the outputs of the NOR circuits 68 and 70 are logical &#34;1&#34; and the output T of the NAND circuit 69 logical &#34;0&#34;. When the counter 62 produces one shot of the next clock pulse CLK, the 1st bit output of the counter 62 produces a logical &#34;1&#34; and the output of the NOR circuit 70 is logical &#34;0&#34;, and the output T of the NAND circuit 69 returns to the original logical state &#34;1&#34;. The output T of the NAND circuit 69 is held at logical &#34;0&#34; till the counter 62 is reset. The output I of the inverting buffer 75 takes a high level (positive) I H  as shown in FIG. 9 when the output T of the NAND circuit 69 is logical &#34;0&#34;. The period during which the output T is kept at logical &#34;0&#34; corresponds to one frame period, 125 μsec. The output I of the inverting buffer 75 is at low level (negative) I L  when the T is logical &#34; 1&#34;. Thus, the value I L  is invariable irrespective of the reference values A and B, but the value I H  is switched among four values according to the combination of the reference values A and B. FIG. 10 tabulates values of the I H  (when T=logical &#34;0&#34;) and I L  (when T=logical &#34;1&#34;) for the combinations of the reference values A and B. When the reference values A and B are both logical &#34;0&#34;, the outputs of the NOR circuits 76 and 78 and the inverter 77 are logical &#34;1&#34;, which are inverted into logical &#34;0&#34; by the NOR circuits 72 to 74 and are applied to the 6th to 8th bits of the inverting buffer 75. When T=logical &#34;0&#34;, logical &#34;0&#34; signals are applied to the 11th to 15th bits of the inverting buffer 75. The inverted output of logical &#34;1&#34; from the inverter 71 is input to the 1st to 5th bits of the inverting buffer 75. Since the 9th and 10th bits of the inverting buffer 75 are grounded, they are always logical &#34;0&#34;. Accordingly, when the reference values A and B are both logical &#34;0&#34;, the output I H  of the inverting buffer 75 is logical &#34;1&#34; for the 6th to 15th bits and provides &#34;1023&#34;. Likewise, when A=logical &#34;0&#34; and B=logical &#34;1&#34;, I H  =&#34;255&#34;. When A=logical &#34;0&#34; and B=logical &#34;1&#34;, I H  =&#34;511&#34;. When A=logical &#34;1&#34; and b=logical &#34;1&#34;, I H  =&#34;127&#34;. When T=logical &#34;1&#34;, the values of the NOR circuits 72 to 74 are kept at logical &#34;0&#34; irrespective of the values A and B. Therefore, the value of I L  is fixed. The polarity, positive or negative, of the I H  and I L  is specified by the 1st bit used as a sign bit. In this way, the I H  is selected to any of four values according to the combination of the reference values A and B, i.e. the kind of sounds to be synthesized. For example, for a human voice, I H  =511 and for the notes of a bird, I H  =127. 
     When the data latched in the latch circuit 60 takes other logical states than all &#34;0&#39;s&#34;, the output of either of the NOR circuits 79 and 80 is logical &#34;1&#34;. When the output of the NAND circuit 81 is logical &#34;1&#34;, the inverting buffer 75 is specified and the inverting buffer 75 transfers a pitch impulse to the digital filter 11. At this time, the output of the inverter 82 is logical &#34;0&#34; and the white noise generator 83 is prohibited from producing an output and is held in a high impedance state. When the data in the latch circuit 60 is all &#34;0&#39;s&#34;, the outputs of the NOR circuits 79 and 80 are logical &#34;1&#34; while the output of the NAND circuit 81 is logical &#34;0&#34;. Therefore, the outputting of the inverting buffer 75 is prohibited and the output of the inverter 82 is logical &#34;1&#34;. And further the output of the white noise generator 83 is applied as unvoiced sound source data to the digital filter 11. The switch between the voiced sound source and unvoiced sound source is performed every frame period. 
     In the above-mentioned embodiment, in the inverting buffer 75, the value of the impulse sound source is switched according to the conversion of the reference values A and B. Alternatively, as shown in FIG. 11, a shifter 84 is provided between the white noise generator 83 and the inverting buffer 75, and the digital filter 11. By the reference values A and B, the contents of the inverting buffer 75 are shifted to the right 0 to 3 bits, thereby to switch the noise sound source as well as the impulse sound source. In this case, a sign of the most significant bit is held as it is. As seen from the above, in the present embodiment, the sound source reference values are switched according to the kind of the sound. Therefore, many voices can be synthesized by a single synthesizer without producing an overflow, ensuring a high quality of the synthesized sounds. 
     A practical arrangement of the digital filter 11 will be described with reference to FIGS. 12 to 18. 
     The seven upper order bits O 1  to O 7  from the interpolator 10 shown in FIG. 12 and the three lower order bits O 7  to O 10  are respectively applied to the input terminal A of a multiplier section 90 in synchronism with timing signals φ A  and φ B . The outputs X 1  to X 16  are input to a clip shifter 91. The shift outputs Y 1  to Y 16  are input to the multiplier section 90 in synchronism with the timing signal φ B . When the fixed point is doubled, the multiplier section 90 overflows for &#34;0.5&#34; of absolute value or more, so that even the sign of the data is probably inverted. To avoid this, the input is clipped at its approximated value by the clip shifter 91. The output of the multiplier section 90 is input into a shift register 92 of 8 bits in synchronism with the timing signal φ A , into a buffer 93 in synchronism with a timing signal φ C  and to the input terminal A of an adder/subtractor circuit 94 in synchronism with the timing signal φ H . The buffer 93 transfers the final value of the sound synthesizing to the digital to analog converter 12 in FIG. 2. The output of the shift register 92 is supplied to the input terminal B of the adder/subtractor circuit 94 in synchronism with a timing signal φ D . The sound source data Z 1  to Z 15  are applied from the sound source 8 in FIG. 2 to also the input terminal B in synchronism with a timing signal φ E . The output of the adder/subtractor circuit 94 is supplied to the input terminal B in synchronism with a timing signal φ G  and to the input terminal A through a one-bit shift register 95 in synchronism with a timing signal φ I . Further, the output of the one-bit shift register 95 is supplied to the input terminal B of the multiplier section 90 in synchronism with timing signals φ K  and φ B , and to an 11-bit shift register 96 in synchronism with the timing signal φ I . The outputs Q 1  to Q 16  of the 11-bit shift register 96 are supplied to the multiplier section 90 in synchronism with the timing signal φ B . The output signal from the adder/subtractor circuit 94 is supplied to the input terminal B of the multiplier section 90 in synchronism with the timing signals φ G  and φ B , and is taken out through a one-bit delay circuit 97. The output of the one-bit delay circuit 97 is supplied to the input terminal B of the adder/subtractor circuit 94 in synchronism with a timing signal φ F , and further taken out via a delay circuit 98 and then supplied to the input terminal B of the multiplier section 90 in synchronism with timing signals φ L  and φ B . The output of the delay circuit 98 is input into the 11-bit shift register 96 in synchronism with a timing signal φ J . In the digital filter 11, one cycle consists of timings T1 to T20. The timing signals φ A  to φ L  are generated at time points, as shown in FIG. 13. The adder/subtractor circuit 94 performs a substraction operation (b-a) at the even-numbered timings T2, T4, T6, . . . , T20 and performs an addition operation at the odd-numbered timings. 
     The multiplier section 90 will be described in detail, with reference to FIGS. 14A and 14B. In FIGS. 14A and 14B, reference numeral 100 designates a gate circuit for fetching the data O 1  to O 7  of those data applied from the interpolator 10 to the input terminal A in synchronism with the timing signal φ A . Reference numeral 101 designates a gate circuit for fetching the data O 7  to O 10  of those data applied from the interpolator 10 to the input terminal A in synchronism with the timing signal φ B . The gate circuit 101 has seven 1-bit input terminals. The input terminals of three lower order bits are grounded. The first to third output bits of the gate circuit 100 and the fifth to seventh output bits of the gate circuit 101 are coupled to a one-bit delay circuit 102. The 4th bit output of the gate circuit 100 and the first bit output of the gate circuit 101 are supplied to an AND circuit 103. The fifth and sixth bit outputs of the gate circuit 100 and the second and third bit outputs of the gate circuit 101 are supplied to the AND circuit 103 through a NAND circuit 104. The output of the AND circuit 103 is suppliled to the one-bit delay circuit 102. Outputs of the fourth to sixth bit outputs of the gate circuit 100 and the first to third bit outputs of the gate circuit 101 are suppliled to a booth judging circuit 105. The sixth to eighth bit outputs of the gate circuit 100 and the third, fourth, seventh bit outputs of the gate circuit 101 are supplied to a booth judging circuit 106. Data P 1  to P 15  applied to input terminal B are also supplied to the booth judging circuits 105 and 106. Outputs of the booth judging circuits 105 and 106 are sent to a full adder 107 of 18 bits. The sixth output bit of the gate circuit 100 and the third bit output of the gate circuit 101 are directly supplied to an AND circuit 107. The seventh and eighth bit outputs of the gate circuit 100 and the fourth and seventh bit outputs of the gate circuit 101 are also supplied to the full adder 107 via a NAND circuit 108. The output of the AND circuit 99 is given to the full adder 107 as a round operation command. The output of the full adder 107 is supplied to a 18-bit full adder 110 through a one-bit delay circuit 109. Data P 1  to P 15  supplied to the input terminal B are supplied to a booth judging circuit 112 through one-bit delay circuit 111. The three upper order output bits of the one-bit delay circuit 102 are supplied to the booth judging circuit 112. The fourth output bit of the one-bit delay circuit 102 is applied to the full adder 110 as a round operation command, and the first bit is directly supplied to the AND circuit 113. Further, the second and third bits are supplied to the AND circuit 113 via a NAND circuit 114. The output of the AND circuit 113 is transferred to the full adder 116 as a round operation command through a one-bit delay circuit 115. The output of the booth judging circuit 112 is supplied to the full adder 110 of, whose output is supplied to a gate circuit 117 as data Y 1  to Y 16  from the clip shifter 91. The gate circuit 117 selects only the output of the full adder 110 at the timing of φ A , and the outputs of the full adder 110 and the clip shifter 91 at the timing of φ B , and transfers them to the input terminal A of the full adder 116. Outputs of the full adder 110 are supplied to a gate circuit 119 via a one-bit delay circuit 118. The gate circuit 119 transfers the data output from the delay circuit 118 to the input terminal B of the full adder 116 in synchronism with the timing signal φ A . The input terminal B of the full adder 116 is supplied with the data Q1 to A16 from the 11-bit shift register 96 at the timing of φ B  through the gate circuit 120. The output of the full adder 116 is used as the output of the multiplier section 90. The multiplier section 90 is arranged such that a circuit section ranging from the input terminals A and B to the full adder 110 forms a multiplier MUL and another section ranging to the full adder 116 forms an adder FA. 
     The digital filter 11 containing the multiplier section 90 performs an operation using a predetermined algorithm. FIGS. 15A and 15B show input and output data at timings T1 to T20 in the multiplier MUL, adder FA, adder/subtractor circuit 94, shift register 92 (8 bit S.R), 11-bit shift register 96 (11 bit S.R), and buffer 93. In FIGS. 15A and 15B, of the inputs of the shift registers 92 and 96, those marked with a triangle (Δ) are the inputs of the shift register 92 and those with no marks are the inputs of the 11-bit shift register 96. The multiplier section 90 divides each of the 10-bit parameters C1 to C8 into groups C 1U  to C 8U  of upper order bits and groups C 1L  to C 8L  of lower order bits, each group consisting of seven bits. More specifically, the gate circuit 100 forms the groups C 1U  to C 8U  and the gate circuit 101 forms the groups C 1L  to C 8L . The gate circuits 100 and 101 also divide the voice amplitude data A transferred from the amplitude circuit 9 through the interpolator 10 into a group of seven upper bits and a group of seven lower bits. It produces the lower order voice amplitude data A L  at T17 and the upper voice amplitude data A U  at T18. The sound source data V(n) (Z1 to Z15) coming from the sound source 8 is supplied to the input terminal B of the adder/subtractor circuit 94 at T6 in response to the timing signal φ E . The output e 1  (n)=e 2  (n) of the delay circuit 98 of 2 bits (2T) is supplied to the input terminal B of the multiplier MUL at T1 to T16. In this case, e 1  (n)=e 2  (n)=1/2O 10  (n-1). The output O 10  (n-1) of the adder/subtractor circuit 94 at T1 is shifted to the right by the one-bit shift register 95 and thus divided into two outputs e1(n) and e2(n). These outputs e1(n) and e2(n) are supplied to the input terminal A of the adder/subtractor circuit 94 at the timing (T1, T3) of the φ I  and to the input terminal B of the multiplier MUL at the timing (T1 to T4) of the φ K . The sound source data V(n) is first supplied to the input terminal A of the adder/subtractor circuit 94 at the timing of T6, and the operation processing starts. The output of the adder/subtractor circuit 94 returns directly or through the one-bit delay circuit 97 to the input terminal B of the multiplier MUL. Then, the multiplier MUL multiplies the voice parameters C1 to C8 by the amplitude data A. The data O 1  to O 10  supplied to the input terminal A of the multiplier MUL are divided into groups of upper order bits and groups of lower order bits, each group consisting of seven bits, as shown in FIG. 16, by the gate circuits 100 and 101. Of the seven upper order bits of each group, bits O 1  to O 3  are supplied to the AND circuit 112 (B3), bits O 2  to O 5  to the booth judging circuit 105 (B1), and bits O 5  to O 7  to the booth judging circuit 106 (B2). Of the seven lower order bits of each group, bits O 7  to O 9  are transferred to the booth judging circuit 106 (B2), bits O 9  and O 10  and a &#34;0&#34;  signal are transferred to the booth judging circuit 105 (B1), and three lower order bits, &#34;000&#34;, are supplied to the booth judging circuit 112 (B3). The booth judging circuits 105 and 106 are supplied with 15-bit data P1 to P15 at the timing of the φ B  by way of the input terminal B. The outputs of the booth judging circuits 105 and 106 respectively are transferred to the input terminals X 1  and X L  of the full adder 107 and are added together. In this case, the data applied to the input terminal X 1  of the full adder 107 is such that the most significant bit thereof is a sign bit S and the two lower order bits are logical &#34;1&#34;, as shown in FIG. 17(1). The data applied to the input terminal Y 1  of the full adder 107 is such that the three upper order bits are sign bits S and the least significant bit contains a rounding bit R of the booth, as shown in FIGS. 17(1) and 17(2). The data shown in FIGS. 17(1) and 17(2) are added together in the full adder 107 and the result of the addition is input from its output terminal Z 1  through the one-bit delay circuit 109 to the input terminal Y 2  of the full adder 110. In this case, the two lower order bits of the data output from the output terminal Z1 of the full adder 107 are discarded, as shown in FIG. 17(4). All &#34;0&#39;s&#34; data is supplied from the booth judging circuit 112 at the timing of the lower order bits to the input terminal X 2  of the full adder 110, as shown in FIG. 17(3). Further, a logical &#34;1&#34;  signal is attached to the two lower order bits. The data shown in FIGS. 17(3) and 17(4) are added by the full adder 110 and the sum is output from the output terminal Z2, as shown in FIG. 17(5). In this case, the two lower order bits of the data output from the output terminal Z2 are discarded. FIGS. 17(1) to 17(5) show the data processing of the lower order bits. The upper order bits likewise are processed as illustrated in FIGS. 17(6) to 17(10). FIGS. 17(10) to 17(12) show states of the data at the input terminals X 3  and Y 3  and the output terminal Z 3  of the full adder 116. 
     The multiplier MUL requires an operation time of 2-bit time. The result of the operation C 1L  ·e 1  (n) of the data input at the timing of T1 in FIG. 15A is output at the timing of T3. The result of the operation C 1U  ·e 1  (n) of the data which is output at T3 and input at T2 is produced at T4. The result of the operation of the data C 1L  ·e 1  (n) which is produced from the full adder 110 in the multiplier MUL, is delayed one bit in the delay circuit 118 and is supplied to the input terminal B of the full adder 116 in an adder FA at T4 through the gate circuit 119. The data C 1U  ·e 1  (n) output from the full adder 110 at T4 is supplied to the input terminal A of the full adder 116 via the gate circuit 117. Accordingly, the full adder 116 adds both the input data and delays the sum of the addition C 1  ·e 1  (n) by one-bit time and delivers it at T5. The result of the addition C 1  ·e 1  (n) is doubled by the clip shifter 91 to be 2C 1  ·e 1  (n), which returns to the input terminal A of the adder FA. The data e 1  (n-1) is supplied from the 11-bit shift register 96 through the gate circuit 120 to the input terminal B of the adder FA, i.e. the input terminal B of the full adder 116. The result of the addition performed by the adder FA at the timing of T5 is produced as e 1  &#39;(n) at the timing T6 and is applied to the input terminal of the adder/subtractor circuit 94. In this way, at the timings T1 to T20, the processing shown in FIGS. 15A to 15B is performed. Then, the output of the multiplier section 90 is loaded into the buffer 93 in synchronism with the timing signal φ C , i.e. the timing of T1. At the timings of T17 and T18, the data O 10  (n-1) after the filter operation is multiplied by the amplitude data A L  and A U , and the products are added together to have [A·O 10  (n-1)]. The final composed result [A·O 10  (n-1)] is produced from the adder FA in the form of [U(n-1)] at T1 in the next cycle. The composed output is loaded into the frame counter 43 in synchronism with the timing signal φ C . The data [U(n-1)] loaded into the buffer 93 is held as a voice output till T20 in the next cycle, suppliled to the digital-to-analog converter 12 and converted into an analog signal. 
     The clip shifter 91 will be described in detail with reference to FIG. 18. Of the data X 1  to X 15  derived from the multiplier section 90, the sign bit X 1  is supplied to NOR circuits 121 and 122, and the X 2  bit is supplied to NOR circuits 123, 124 1  and 124 16  and NOR gates 122 and 123 via the NOR circuit 121. The output of the NOR gate 122 is supplied to NOR circuits 124 2  to 124 16 . The bits X 3  to X 16  are supplied to the NOR circuits 124 2  to 124 15 , respectively. The output of the NOR circuit 123 is applied through the NOR gate 124 1  to a NOR circuit 125 1 , and to NOR circuits 125 2  to 125 16 . The outputs of the NOR circuits 124 1  to 124 16  are passed through the NOR circuits 125 1  to 125 16  and used as outputs Y 1  to Y 16  of the clip shifter 91, which are supplied, to the multiplier section 90. 
     The clip shifter 91 thus arranged has a data shift function when the bits X 1  and X 2  are &#34;0,0&#34; or &#34;1,1&#34;, and outputs the bits X 3  to X 16  as Y 2  to Y 15 . In this case, when the sign bit X is logical &#34;0&#34;, Y 1  and Y 16  are logical &#34;0&#34;. When the sign bit X 1  is logical &#34;1&#34;, Y 1  and Y 16  are logical &#34;1&#34;. When the bits X 1  and X 2  are &#34;0,1&#34; or &#34;1,0&#34;, if it is shifted, an overflow occurs. To avoid this, the clip function is provided and when the sign bit X 1  is logical &#34;0&#34;, Y 1  is logical &#34;0&#34; and Y 2  to Y 16  are all &#34;0,s&#34;. When the overflow occurs due to the shift operation, it is clipped at its approximate value. 
     In the above-mentioned embodiment, the multiplier factor applied to the multiplier is divided into the upper order bits and the lower order bits by the digital filter 11. The partial products of the upper and lower order bits are obtained. The lower order bits or those with a specified bit attached thereto are added to the partial products. The two lower order bits of the result of the addition are discarded. This eliminates a deviation of an error in positive or negative direction, improving the operation accuracy.