TTL circuits generating complementary signals
TECHNICAL FIELD 
     This invention relates to new and improved TTL circuits for generating from an input signal complementary output signals useful in integrated circuit applications. The invention provides new internal buffer circuits for generating complementary data signals while resolving the problem of current hogging. The invention also provides new enable circuits which generate complementary enable control signals for TTL output devices. In the latter application the invention provides an improved TTL tristate output device with reduced output capacitance. 
     BACKGROUND ART 
     A prior art TTL tristate output device with reduced output capacitance is described in the Ferris U.S. Pat. No. 4,311,927 issued Jan. 19, 1982, entitled &#34;Transistor Logic Tristate Device with Reduced Output Capacitance&#34; with a related improvement described in the Ferris, et al. U.S. patent application Ser. No. 586,671 filed Mar. 6, 1984. The latter tristate output device 10, illustrated in FIG. 1, is provided with an input 12 for receiving binary data signals Vi of high and low potential and for transmitting output signals Vo to a common bus, not shown, coupled at the tristate device output 14. For operation in the bistate mode, the tristate device includes a pull-up transistor element comprising Darlington transistor pair Q2 and Q3 for sourcing current to the output 14 from high potential source Vcc and a pull-down transistor element Q4 for sinking current from the output 14 to low potential or ground. Phase splitter transistor element Q1 with collector resistor R1 is coupled at the input 12 to control the states of the pull-up and pull-down transistor elements in response to data signals Vi at the input. The pull-down transistor element Q4 includes a conventional squaring network at its base comprised of transistor Q5 with base and collector resistors R3 and R4. 
     For the tristate mode of operation, a prior art enable gate 20 illustrated in FIG. 2, is operatively coupled at the enable input 15 of tristate device 10. The high impedance third state is established at the output 14 of the tristate device when the enable gate output signal E is at low potential and the pull-up and phase splitter transistor elements are deprived of base drive current through diodes D1 and D2. For reducing the effective output capacitance during the high impedance third state, an active discharge sequence consisting of transistors Q7 and Q6 and diode cluster D3, D4, and D5 is operatively coupled between the base of pull-down transistor element Q4 and the enable input 15. The active discharge sequence affords a low impedance route to ground from the base of the pull-down element through transistor Q7 when the enable gate maintains a low potential enable signal E at enable input 15 and the tristate device is in the high impedance third state. As a result, low to high potential transitions on a common bus coupled at the tristate output 14 will not incidentally drive the pull-down transistor element Q4 to conduction. Any capacitive Miller feedback current through the collector to base capacitance of transistor Q4 is rapidly diverted and discharged to ground through active discharge transistor element Q7. During the bistate mode of operation when the enable signal E is at high potential, the active discharge sequence blocks current flow from high potential to the pull-down transistor element Q4. 
     The active discharge sequence as described in U.S. Pat. No. 4,311,927 comprises a sequence of three active element transistors in a double inversion series coupling between the enable gate and the base of the pull-down transistor. As a result of the double inversion, the collector potential of the active discharge transistor coupled at the base of the pull-down transistor element follows in phase the high or low potential of the enable signal E, discharging the base of the pull-down transistor when the enable signal E is at low potential and the tristate device 10 is in the high impedance third state. In the circuit of FIG. 1, one of the transistors in the active discharge sequence next to the enable input 15 is replaced with the passive diode cluster D3, D4, D5, coupled in a delta configuration and power supply resistors R5, R6, R7 coupled in a Y network. The passive diode cluster is operatively arranged for delivering base drive current to the base of the second transistor Q6 thereby depriving the active discharge transistor Q7 of base drive current when the enable signal E at the enable input 15 is at high potential for operation of the tristate device in the bistate mode. The passive diode cluster also operatively diverts base drive current away from the base of the second transistor Q6 when the enable signal E is at low potential so that active discharge transistor Q7 actively conducts away from the base of the pull-down transistor Q4 for operation of the device with reduced output capacitance during the high impedance third state. 
     In either case there is double inversion. The collector potential of transistor Q6 follows out of phase with the enable signal potential E, and the collector potential of active discharge transistor Q7 follows in phase requiring two inversions of the enable signal E. The silicon area taken up by the active discharge sequence in either of the prior art tristate devices with low output capacitance is relatively large and this large area is multiplied when many tristate devices are tied to a common bus. Furthermore, either tristate device consumes power during bistate operation of the output device. 
     The prior art enable gate 20 shown in FIG. 2 is a bistate device with generates the enable signal E at enable gate output 16 from an enable gate input signal E at the enable gate input 18. The enable gate includes the enable pull-up Darlington transistor element Q22 and Q23, enable pull-down transistor element Q24, enable phase splitter transistor element 21 and collector resistor R21 operatively coupled to control the states of the enable pull-up and pull-down transistor elements, and a first enable input transistor element Q28 with collector resistor R28 and input diodes D21 and D22 operatively coupled for following and applying the enable gate signal input E to the base of the enable phase splitter transistor element 21. Because the collector potential of the active discharge transistor Q7 must follow in phase the enable gate output signal E with intermediate elements to block current flow from high potential during bistate operation, the double inversion sequence is required in the tristate device 10. 
     A prior art TTL internal buffer circuit for generating complementary data signals such as true and false data signals D and D from an input data signal D is illustrated in FIG. 3. The internal buffer circuit 30 is a bistate device with pull-up Darlington transistor element Q32 and Q33, pull-down transistor element Q34 and dual phase splitters Q31 and Q31a for controlling the state of the pull-up and pull-down transistor elements to provide high and low level output data signals D at the buffer output 36 in response to input data signals D at the buffer input 38. Input transistor element Q38 with collector resistor R38 and input diodes D31 and D32 are operatively coupled to apply an input data signal D to the bases of the dual phase splitter transistors Q31 and Q31a. Dual phase splitter transistor Q31a. is added to generate the complementary data signal and the collector potential of Q31a is tapped to provide the complementary input signal D to complementary buffer 40, a similar bistate buffer device which inverts the complementary input D to the complementary output data signal D. The collector potential of dual phase splitter Q31a may be used to provide the input to multiple complementary buffers such as buffer 40 although only one is shown by way of example in FIG. 3. 
     A schematic block diagram of this conventional buffer circuit for generating true and false data signals is illustrated in FIG. 4. The TTL bistate buffer 30 is inherently inverting at the output 36. The dual phase splitter Q31a is also inherently inverting at its collector 31a which is tapped to provide the complementary inputs D to one or more complementary buffers 40 which also inherently invert the complementary inputs at outputs 46 to provide the complementary output signals D. The complementary buffers 30 and 40 therefore provide the complementary true and false signals D and D from the single input signal D. A disadvantage of this arrangement using dual phase splitters however, is the problem of current hogging. The current mirror configuration of the dual phase splitters requires that the emitter currents equalize and a greater collector to emitter current in one phase splitter results in &#34;hogging&#34; of the base drive leaving insufficient current in the other, for example to drive multiple complementary buffers. 
     OBJECTS OF THE INVENTION 
     It is therefore an object of the present invention to provide new TTL circuits for generating from a single input signal complementary output signals for a variety of applications. For example, one object of the invention is to provide new enable gates for generating complementary enable control signals for application in TTL. tristate output devices with reduced output capacitance, and another to provide new internal logic buffers for generating complementary true and false data signals. 
     Another object of the invention is to provide enable gates and improved TTL tristate output devices with reduced output capacitance having faster operation, reduced integrated circuit fabrication area, and reduced power consumption. The invention also provides internal IC buffer circuits which generate complementary data signals without the disadvantage of &#34;current hogging&#34; experienced in conventional dual phase splitter buffer circuits. 
     A further object of the invention is to provide a variety of TTL circuits for generating from a single input signal complementary output signals over complementary signal current paths of substantially equal impedance and equal potential drops for integrated circuit applications. 
     DISCLOSURE OF THE INVENTION 
     In order to accomplish these results the present invention provides an improved enable gate for generating complementary enable signals E and A from an enable gate input signal E. The enable gate includes the conventional pull-up and pull-down transistor elements operatively coupled to provide high and low level signals E at the enable gate output, phase splitter transistor element operatively coupled to control the states of the pull-up and pull-down transistor elements, and a first input transistor element for applying the enable gate input signal E to the base of the phase splitter. In the improved enable gate, according to the invention, an alternate enable transistor element is coupled in emitter follower configuration in the enable gate with the base of the alternate enable transistor coupled to follow the enable gate input signal E and provide through the emitter circuit of the alternate enable transistor element an alternate enable signal A in phase with the enable gate input signal E and complementary to the enable signal E at the output of the enable gate. 
     In the preferred embodiment the alternate enable transistor element comprises a second input transistor coupled in emitter follower configuration with the base of the second input transistor element tied to the base of the first input transistor element. Thus, the bases of the first and second input transistors are coupled to follow the enable input signal E. The alternate enable signal A may be used as hereafter described in the control of multiple output gates increasing the current drawn through the alternate enable signal path. It is therefore preferable to tie the base of the emitter follower to the first input transistor so that the emitter follower cannot be turned off as readily by the voltage drop across D23 which increases exponentially with current. However, the base of the emitter follower may also be tied to other stages of the enable gate such as the base of the phase splitter transistor element or the base of the pull-down transistor element. 
     A voltage level shifting component is coupled in the emitter circuit of the alternate enable transistor element in the improved enable gate so that the impedance of the current path of enable signal E through the enable gate and the impedance of the current path of the alternate enable signal A through the alternate enable transistor element emitter circuit are substantially equal. The voltage level shifting component in the emitter circuit of the alternate enable transistor element may comprise, for example at least one diode. 
     The invention also provides an improved TTL tristate output device with reduced output capacitance incorporating the new enable gate. The tristate output device includes the conventional features of an output, a bistate mode of operation, a pull-down transistor element for sinking current from the output to low potential, an enable input for establishing a high impedance third state at the output of the tristate device, and an active discharge transistor element coupled to the base of the pull-down transistor for providing a route to ground when the active discharge transistor element is conducting. According to the invention the enable signal E at the improved enable gate output is coupled to the enable input of the tristate device and the alternate enable signal A from the emitter circuit of the alternate enable transistor element of the improved enable gate is coupled to the base of the active discharge transistor element in the tristate device through a limiting resistor. Miller feedback current through the collector to base capacitance of the pull-down transistor element caused by low to high potential transitions on the common bus is rapidly diverted and discharged to ground through the conducting active discharge transistor element. 
     A feature and advantage of the TTL tristate output device with reduced output capacitance, according to the invention, is that the double inversion active discharge sequence is replaced by a single active discharge transistor thereby increasing the speed of operation of the device, greatly reducing the required silicon fabrication area for reducing the output capacitance for IC tristate devices, and eliminating power consumption by active discharge elements during the bistate mode of operation. 
     According to another embodiment, the invention provides new and improved TTL buffer circuits for generating complementary data signals. Such internal buffer circuits include the conventional features of an input and an output, pull-up and pull-down transistor elements operatively coupled to provide high and low level voltage output data signals D at the output, phase splitter transistor element operatively coupled to control the states of the pull-up and and pull-down transistor elements, and an input transistor element operatively coupled for applying an input data signal D to the base of the phase splitter transistor element. According to the invention, a complementary data signal transistor element is operatively coupled in emitter follower configuration in the buffer circuit with the base of the complementary data signal transistor element coupled to follow the input data signal D and provide through the emitter circuit of the complementary data signal transistor element a complementary output data signal D in phase with the input signal D and complementary to the output data signal D at the output of the buffer circuit. 
     In the preferred embodiment the base of the complementary data signal transistor element is tied to the base of the phase splitter transistor element and a voltage level shifting component is coupled in the emitter circuit of the complementary data signal transistor to equalize substantially the impedance of the current paths of the output data signals D and the complementary output data signals D. A feature and advantage of the new buffer circuit is that one of the current mirror configuration dual phase splitters of conventional complementary data signal buffer circuits is eliminated or rather displaced and instead is coupled to the emitter circuit of the complementary data signal emitter follower transistor element to provide a complementary output transistor. Alternately, this complementary output transistor may be viewed as an inverting input to a complementary output buffer for delivering the complementary output data signal D in phase with the input signal D and complementary to the output data signal D of the original internal buffer circuit. 
     Thus, the invention contemplates providing a complementary data signal transistor element operatively coupled in emitter follower configuration in a conventional inverting TTL buffer circuit for following the input data signals D. The emitter circuit of the complementary data signal transistor element is then appropriately coupled to a double inverting complementary buffer circuit for providing the complementary output data signals D in phase with the input data signals D but complementary to the single inverted output data signals D. A feature and advantage of this arrangement is that the use of current mirror configuration dual phase splitters in the original internal buffer circuit is eliminated thereby also eliminating the problem of &#34;current hogging&#34; between the dual phase splitter experienced with conventional complementary data signal buffer circuits. 
     Other objects, features, and advantages of the invention are apparent in the following specification and accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a prior art TTL tristate output device with reduced output capacitance. 
     FIG. 2 is a schematic diagram of a prior art enable gate for generating enable signals E for the enable input of a tristate output device. 
     FIG. 3 is a schematic diagram of a prior art TTL buffer circuit for generating from an input data signal complementary output data signals. 
     FIG. 4 is a simplified block diagram of the prior art TTL buffer circuit of FIG. 3 for generating complementary data signals. 
     FIG. 5 is a schematic diagram of a TTL tristate output device with reduced output capacitance according to the present invention. 
     FIG. 6 is a block diagram of an enable gate according to the present invention for generating complementary enable signals for the TTL tristate output device of FIG. 5. 
     FIG. 6A is a schematic diagram of an alternative embodiment of the new enable gate for generating complementary enable control signals. 
     FIG. 7 is a schematic diagram of a TTL internal buffer circuit for generating from an input data signal D complementary output data signals D and D according to the present invention. 
     FIG. 8 is a simplified block diagram of the internal buffer circuit for generating complementary data signals shown in FIG. 7. 
    
    
     DESCRIPTION OF PREFERRED EXAMPLE EMBODIMENTS AND BEST MODE OF THE INVENTION 
     An improved TTL tristate output device 50 with reduced output capacitance according to the present invention is illustrated in FIG. 5. The new tristate device 50 of FIG. 5 incorporates the primary operational elements and features heretofore described with reference to the prior art tristate device 10 of FIG. 1 and the same operating components are designated by the same reference numerals and letter designations. However, a feature and advantage of the present invention is that the double inversion active discharge sequence has been eliminated. In its place the present invention provides the single active discharge transistor element Q7 at the base of pull-down transistor Q4. Active discharge transistor Q7 provides a low impedance path to ground from the base of pull-down transistor Q4 for reducing the effective output capacitance when the enable signal E is at low potential and the tristate device 50 is in the high impedance third state. 
     This is accomplished by applying an alternate enable control signal A complementary to the enable signal E to the base of active discharge transistor Q7 at alternate enable input 55 through limiting resistor R56. According to the invention the alternate enable signal A is derived from an improved enable gate illustrated in FIG. 6. The enable gate of FIG. 6 incorporates the primary operational elements and features described with reference to the prior art enable gate 20 of FIG. 2 and the same operating components are designated by the same reference numerals and letter designations. In the improved enable gate of FIG. 6, however, an alternate enable circuit portion 60 is incorporated in the enable gate including an alternate enable transistor element 26 coupled in emitter follower configuration with the base of alternate enable transistor Q26 coupled to follow in phase with the enable gate input signal E. A voltage level shifting component, diode D23 is included in the emitter circuit of the emitter follower Q26 leading to the alternate enable terminal 55 to equalize substantially the voltage drops and therefore the impedance through the current paths of enable signal E and alternate enable signal A. The voltage drop through the enable signal current path shown in FIG. 6 equals 
     
         V.sub.be Q28+V.sub.be Q21+V.sub.be Q24 
    
     while the potential drop through the signal path of the alternate enable signal A shown in FIGS. 6 and 5 equals 
     
         V.sub.be Q26+V.sub.sd D23+V.sub.be Q7 
    
     neglecting the resistance of limiting resistor R56. The intrinsic voltage drop V be  of typical IC transistor devices is in the order of 0.8 volts while the intrinsic voltage drop V sd  of a typical Schottky diode device D23 is in the order of 0.6 volts. As a result, inclusion of diode D23 in the emitter circuit of emitter follower Q26 substantially equalizes the impedance of the two signal paths. 
     In the preferred embodiment the alternate enable transistor element Q26 forms a second input transistor but coupled in emitter follower configuration with the base tied to the base of the first input transistor Q28. The bases of both transistors therefore follow in phase the enable input signal E. The alternate enable signal A from the emitter of alternate enable transistor Q26 may be used in the control of multiple output gates 50 of the type illustrated in FIG. 5. Control of multiple output gates increases the current drawn through the alternate enable signal path increasing the voltage drop across voltage level shifting diode D23 according to the diode law. Because of the emitter follower configuration of the alternate enable transistor, a sufficient voltage drop across diode D3 may turn off transistor Q26. Tying the base of emitter follower transistor Q26 to the base of the input transistor Q28 maximizes the current which may be drawn through node or terminal 55 and therefore the number of tristate output devices 50 which may be controlled by the alternate enable signal A without effecting the operation of the emitter follower Q26. 
     However, for smaller current applications where fewer output devices are controlled by the alternate enable signal A, the alternate enable circuit portion 60 may be coupled in emitter follower configuration at any of the stages of the enable gate, for example, as shown in FIG. 6A. In FIG. 6A is illustrated an enable gate of the type shown in FIG. 6, however the alternate enable circuit portion 60A is tied to the second stage of phase splitter transistor Q21 of the enable gate. Thus, alternate enable transistor element Q26 is coupled in emitter follower configuration to follow in phase the enable gate input signal E with the base of emitter follower Q26 tied to the base of phase splitter transistor element Q21. Voltage level shifting diode D23 is no longer required. Emitter follower Q26 is coupled to the alternate enable terminal or node 55 and is separated from ground by leakage resistor R27 as heretofore described. 
     A feature and advantage of the emitter follower configurations 60 and 60A according to the present invention is that the emitter circuit and signal path of the alternate enable signal A follows in phase with the enable gate input signal E and is out of phase and complementary to the enable gate output signal or enable signal E. Furthermore, the enable signal E and alternate enable signal A follows signal paths of substantially similar impedance. Another feature and advantage of the improved enable gate of FIGS. 6 and 6A is that the complementary enable control signals E and A may be applied directly in an improved TTL tristate output device 50 for reduced output capacitance without requiring the double inversion active discharge sequence of the prior art. 
     Thus, as shown in FIG. 5 an alternate enable signal A of high potential may be applied directly to drive the base of active discharge transistor Q7 when the enable signal E at enable input 15 is at low potential and the tristate output device is in the high impedance third state. In this condition active discharge transistor Q7 is conducting providing a low impedance path to ground for diverting and dissipating Miller feedback current at the pull-down transistor element Q24 caused by potential transitions on the common bus. This is accomplished according to the present invention by &#34;reaching back&#34; into a preferred stage of the enable gate with an emitter follower alternate enable transistor element and emitter circuit which follows in phase the enable gate input signal E. 
     The limiting resistor or stabilizing resistor R56 at the base of active discharge transistor Q7 is required for stabilizing operation of the emitter follower alternate enable circuit of the present invention. Limiting resistor R56 moderates the potential at the alternate enable signal node or terminal 55, limits current to the base of active discharge transistor Q7, and prevents damage to the transistor which may otherwise occur by use of the emitter follower configuration. Stabilizing resistor R56 may be selected typically in the order of 200 ohms. 
     An internal TTL buffer circuit 80 for generating complementary data signals according to the present invention is illustrated in FIG. 7. The internal TTL buffer 80 incorporates the major operational components of the prior art TTL buffer circuit 30 illustrated in FIG. 3 and similar components are designated by the same reference numerals and letter designations. The circuit for generating complementary data signals shown in FIG. 7 also includes a complementary buffer 90 which incorporates the major operational components of the complementary buffer circuit 40 illustrated in FIG. 3. 
     The coupling circuitry between the internal TTL buffer circuit 80 and complementary buffer 90 indicated in dashed outline designated by the reference numeral 70, however, provides substantial improvement over the prior art. Rather than coupling the input of the complementary buffer to the collector of a dual phase splitter transistor Q31a as shown in the prior art circuit of FIG. 3, the present invention incorporates a complementary data signal transistor element Q70 into the TTL buffer circuit 80 in emitter follower configuration. The base of the complementary data signal transistor Q70 is coupled to follow the input data signal D at the input 38 of buffer circuit and provide through the emitter circuit of transistor element Q70 a complementary output data signal D in phase with the input data signal D and complementary to the output data signal D at the output of buffer circuit 80. The prior art coupling of the buffer circuit 40 to the collector of a clamped dual phase splitter transistor Q31a inverts the input data signal D and provides the inverted data signal D at the input of the complementary buffer 40. However, the dual phase splitters Q31 and Q31a of the prior art buffer circuit 30 are subject to the disadvantage of &#34;current hogging&#34;. The base and emitter terminals of dual phase splitter transistors Q31 and Q31a are tied together in parallel so that a greater collector to emitter current through one of the dual phase splitters will disproportionately draw and &#34;hog&#34; the base drive current. This may particularly arise when the dual phase splitter of the internal buffer circuit 30 drives a plurality of complementary buffers 40. 
     This problem is eliminated according to the present invention by coupling the complementary buffer 90 to the internal buffer circuit 80 through an emitter follower complementary data signal transistor element Q70 as heretofore described with reference to FIG. 7. The base of complementary data signal transistor Q70 is tied to the base of the buffer circuit phase splitter transistor element Q31. However, because of the emitter follower coupling, the emitter circuit of transistor Q70 provides a complementary data signal D in phase with the input data signal D at the input 38 of buffer circuit 80. The input to complementary buffer 90 is therefore a complementary data signal D which must be doubly inverted. In order to provide a double inverting complementary buffer 90 according to the invention, a transistor stage Q71 is added which may be viewed as a complementary output transistor of the emitter circuit 70 of complementary data signal transistor element Q70 or as an input transistor or input stage of complementary buffer 90. The input to the base of the phase splitter of complementary buffer 90 is therefore coupled to the collector terminal or node 71 of input stage transistor element Q71 to provide a first inversion while a second inversion is provided at the output node 46 of the complementary buffer. 
     A block diagram summarizing the improved buffer circuit for generating complementary data signals is illustrated in FIG. 8 showing the internal buffer circuit 80 which delivers an output data signal D from input data signal D with a single inversion and the complementary buffer circuit 90 which delivers a complementary data signal D in phase with the input data signal D through a double inversion. The limiting or stabilizing resistor R70 stabilizes operation of the emitter follower transistor Q70 by moderating the potential at the input to the complementary buffer and by limiting current to the base of complementary buffer input transistor Q71. 
     Thus, according to the present invention, the dual phase splitter transistor Q31a of the prior art buffer circuit 30 is eliminated in favor of a complementary data signal emitter follower Q70. Furthermore, the inversion afforded by coupling the complementary buffer to the collector of the dual phase splitter transistor is displaced by using the collector terminal or node 71 of a new complementary buffer input transistor Q71 so that the complementary buffer 90 according to the present invention is doubly inverting. The emitter follower coupling of complementary data signal transistor element Q70 eliminates the problem of &#34;current hogging&#34; of the prior art dual phase splitters. Furthermore, approximately the same impedance is maintained along the signal path of the output data signal D through Q38, Q31, and Q34 and the signal path of the complementary data signal D through Q38, Q70, and Q71. 
     While the invention has been described with reference to particular example embodiments, it is intended to cover all variations and equivalents within the scope of the following claims.