Color index conversion system in graphic display device
BACKGROUND OF THE INVENTION 
     The present invention relates to a color graphic display device for converting color index information to color information on a screen to perform graphic display and, more particularly, to a color index conversion system for interarea copy. 
     FIG. 1 shows a conventional graphic display device for performing graphic display by using frame memories 11 through 14. According to this device, for example, color index data B0 through B3 and position data (not shown) on the screen are specified to store pixel data in the frame memories 11 through 14. In this case, the frame editing and read/write operation are performed under the control of a frame editing block 15. Each bit of color index data CI corresponds to one pixel on a display monitor 16. The color index data divided and stored in these frame memories 11 through 14 are read out therefrom and are converted by a display conversion device 17 to a color information on the screen. Color display appears on the display monitor 16 in accordance with this color information. In addition, according to the conventional device, the frame memories 11 through 14 are divided into a plurality of groups (e.g., a group of frame memories 11 and 12, and a group of frame memories 13 and 14). In this case, the frame memories 11 and 12 serve as a display memory independently of a display memory constituted by the frame memories 13 and 14. For this reason, the graphic display by the frame memories 11 and 12 can be superposed on the graphic display by the frame memories 13 and 14 on the display monitor 16. 
     This conventional device can perform interarea copy processing for copying the contents of areas A of the frame memories 11 and 12 to areas B of the frame memories 13 and 14. This interarea copy operation is controlled by the frame editing block 15 in the following manner. Color index data (RCI) B3B2B1B0 corresponding to the areas A are sequentially read out from the frame memories 11 through 14. The bit data B3B2 of the copy source frame memories 11 and 12 (the frame memories subjected to a real read operation) of the readout color index data B3B2B1B0 are selectively extracted. This extraction operation is performed by the frame editing block 15. Subsequently, the bit data B3B2 are set in bit positions of bit data B1B0 of the copy destination frame memories 13 and 14 (i.e., the frame memories subjected to a real write operation). Next, the color index data xxB3B2, are updated (x represents that the corresponding bit can be logic &#34;1&#34; or &#34;0&#34;). This data updating is also performed by the frame editing block 15. Finally, the updated color index data (xxB3B2) is supplied to the frame memories 11 through 14, and the bit data B3B2 corresponding only to the frame memories 13 and 14 is written therein by the frame editing block 15. 
     In this manner, according to the conventional color graphic display device, the bit data corresponding to the copy source frame memories is selected from the corresponding color index data when interarea copy is performed. The selected bit data is then set in the bit positions corresponding to the copy destination frame memories so as to update the color index data. These two operations are an obstacle against high-speed copy between the areas. In addition, the firmware of the frame editing block 15 is overloaded. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a color index conversion system for performing high-speed color index data conversion required for interarea copy in a color graphic display device. 
     In order to achieve the above object of the present invention, there is provided a color graphic display device for converting to color information on a screen color index data which are read out from a plurality of frame memories and for performing graphic display, comprising: 
     a first register for holding a group number determined in accordance with a combination of areas between a copy source memory of said plurality of frame memories and a copy destination memory of said plurality of frame memories for an interarea copy; 
     a second register for holding write enable/disable data which represents a write enable/disable state of said plurality of frame memories; 
     a read only memory table for storing conversion color index data at a plurality of addresses of the group number and for receiving as address data linked data of an output from said first register and the color index data from said plurality of frame memories; and 
     means for supplying a read output from said ROM table as converted color index data to said plurality of frame memories. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and features of the present invention will be apparent from the following description taken in connection with the accompanying drawings, in which: 
     FIG. 1 is a block diagram showing the overall configuration of a conventional color graphic display device; 
     FIG. 2 is a block diagram showing the overall configuration of a color graphic display device according to an embodiment of the present invention; 
     FIG. 3 is a memory map showing the contents of a ROM table 22 of FIG. 2; and 
     FIG. 4 is a graphic representation for explaining interarea copy. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 2 shows the overall configuration of a color graphic display device according to an embodiment of the present invention. A frame editing block 21 specifies 4-bit color index data CI and position data (not shown) of a display monitor 30 so as to control the graphic display. In this case, the frame editing block 21 reads out the color index data from frame memories 25 through 28 so as to perform interarea copy. When the interarea copy is performed, color index data b3b2b1b0 read out from a copy source area of the frame memories 25 through 28 is supplied as, for example, lower address bits to a ROM table 22 for color index conversion. The ROM table 22 receives as upper address bits the 5-bit output data from a first register 23. When interarea copy is performed, group number data of bits G4 through G0 is supplied from the frame editing block 21 to the register 23. The group number data of bits G4 through G0 are predetermined in accordance with combinations of the copy source frame memory and the copy destination frame memory. 
     The combinations are prepared such that, for example, the frame memories 25 and 26 are defined as copy source memories and the frame memories 27 and 28 are defined as copy destination memories, or the frame memories 25 and 27 are defined as the copy source memories and the memories 26 and 28 are defined as the copy destination memories, or the frame memory 25 is defined as the copy source memory and the frame memories 26 through 28 are defined as copy destination memories. In this embodiment, the contents of the source and destination frame memories are represented, as shown in Table I. 
     
                       TABLE I                                                     
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Copy source         Copy                                                  
Group Input data            destination                                   
No    from Host frame memory                                              
                            frame memory                                  
(Hex) Computer  25    26  27  28  25  26  27  28                          
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01    b3 - b0                                 *                           
      (4 bit)                             *                               
                                      *                                   
                                  *                                       
02    bi+1,bi                             *   *   i=0,1,2                 
      (2 bit)                     *   *                                   
03    bi (1 bit)                      *   *       i=0,1,2,3               
04    bi (1 bit)                      *   *   *   i=0,1,2,3               
05    bi (1 bit)                  *   *   *       i=0,1,2,3               
06    bi+1,bi                     *   *   *       i=0,1,2                 
      (2 bit)                     *   *   *   *                           
                              *               *                           
                          *               *                               
                      *               *                                   
                *                 *                                       
                          *   *           *   *                           
                      *   *           *   *                               
                *     *           *   *                                   
                      *   *   *       *   *   *                           
                *     *   *       *   *   *                               
                *     *   *   *   *   *   *   *                           
07                    *   *   *       *   *   *                           
                      *   *   *   *   *   *   *                           
08    bi+1,bi                         *   *       i=0,1,2                 
      (2 bit)                         *   *   *                           
                *     *   *       *   *   *   *                           
09                        *   *           *   *                           
                          *   *       *   *   *                           
                          *   *   *   *   *   *                           
0A                    *   *           *   *   *                           
                      *   *       *   *   *   *                           
0B              *     *           *   *   *   *                           
0C                            *               *                           
                              *           *   *                           
                              *       *   *   *                           
                              *   *   *   *   *                           
0D                        *               *   *                           
                          *           *   *   *                           
                          *       *   *   *   *                           
0E                    *               *   *   *                           
                      *           *   *   *   *                           
0F              *                 x   *   *   *                           
                *                 *   *   *   *                           
10                            *       *   *   x                           
                              *   *   *   *   x                           
11              *                 x   *   *                               
12                            *           *   x                           
                              *       *       x                           
                              *   *           x                           
13                        *               x   *                           
                          *           *   x                               
                          *       *       x                               
                          *   *       *   x   x                           
                          *   *   *       x   x                           
14                    *               x       *                           
                      *               x   *                               
                      *           *   x                                   
                      *   *           x   x   *                           
                      *   *       *   x   x                               
                      *   *   *   *   x   x   x                           
15    b3 - b0                                 *                           
      (4 bit)                             *                               
                                      *                                   
                                  *                                       
                *                 x           *                           
                *                 x       *                               
                *                 x   *                                   
                *     *           x   x       *                           
                *     *           x   x   *                               
                *     *   *       x   x   x   *                           
16                        *   *   *   *   x   x                           
17    bi+1,bi                             *   *   i=0,1,2                 
      (2 bit)                     *   *                                   
                *     *           x   x   *   *                           
18                            *   *   *       x                           
                      *               x   *   *                           
19                        *       *   *   x                               
                *                 x       *   *                           
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     In Table I, &#34;*&#34; indicates any copy source frame memory that has been designated and also any copy destination frame memory that has been designated. In this embodiment, the data input at the host computer may be copied, stored in the copy destination frame memories 25-28 and displayed. The ROM table 22 is a conversion table storing the color index data representing copying relations shown in Table I in the form of a pattern of &#34;0&#34; and &#34;1&#34; bits. This conversion table is so designed that the maximum value represented by the designated bit number of the copy source is stored at the copy destination when the primitive operation is performed to copy the data from the host computer and the number of designated bits of the copy source is greater than that of the copy destination. It is also so designed that the designated bits of the copy destination are taken from the designated bits of the copy source and are stored at the copy destination when the pixel operation is performed to copy the data from the frame memory and the number of designated bit number of the copy source is greater than that of the copy destination. 
     When the number of designated bit number of the copy source is less than that of the copy destination, the data defined by the designated bits of the copy source is stored at the lower bits of the copy destination and logic &#34;0&#34; is stored at the upper bits of the copy destination which define the difference between the number of designated bits of the copy source and that of the copy destination. In Table I, a plurality of copying relations are represented in a single group No. This means that the plurality of copying relations may be represented (controlled) with the same contents of the Table I. 
     The respective areas of the ROM table 22 which are designated by the upper five bits of the 9-bit address of the ROM table 22, or the group numbers G4 through G0 are used in combinations shown in Table I. These areas have 16 types of color index data, as shown in FIG. 3 stored therein. The relative address of each area comprises four remaining bits of a 9-bit address (i.e., the color index data b3 through b0 of the frame memories 25 through 28). In this embodiment, for example, when the frame memories 25 and 26 are copy source memories and the frame memories 27 and 28 are copy destination memories in accordance with the group number data of bits G4 through G0, the following 4-bit conversion color index data is stored in the 16 addresses of the areas within the ROM table 22 which are indicated by the bits G4 through G0 of the group number data. More specifically, when the 4-bit relative address representing the area of the ROM table 22 is given to be b3b2b1b0, the 4-bit color index data xxb3b2 (x is logic &#34;1&#34; or &#34;0&#34;) is stored at the address b3b2b1b0. Similarly, when the frame memories 25 and 27 are copy source memories and the frame memories 26 and 28 are copy destination memories in accordance with the group number data of bits G4 through G0, the corresponding areas of the ROM table 22 which are specified by the group number data of bits G4 through G0 store color index data b3&#39; through b0&#39; (xb3xb1) at the address b3b2b1b0. 
     As shown in FIG. 4, assume that the contents of the areas A of the frame memories 25 and 26 are copied in the areas B of the frame memories 27 and 28. In this case, the contents of the ROM table 22 are shown in Table II below. 
     
                       TABLE II                                                    
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Source data       Destination data                                        
Group b3     b2     b1   b0   b3&#39;  b2&#39;  b1&#39;  b0&#39;                          
No    (25)   (26)   (27) (28) (25) (26) (27) (28) HEX                     
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17    0      0      0    0    0    0    0    0    0                       
      0      0      0    1    0    0    0    0    0                       
      0      0      1    0    0    0    0    0    0                       
      0      0      1    1    0    0    0    0    0                       
      0      1      0    0    0    1    0    1    5                       
      0      1      0    1    0    1    0    1    5                       
      0      1      1    0    0    1    0    1    5                       
      0      1      1    1    0    1    0    1    5                       
      1      0      0    0    1    0    1    0    A                       
      1      0      0    1    1    0    1    0    A                       
      1      0      1    0    1    0    1    0    A                       
      1      0      1    1    1    0    1    0    A                       
      1      1      0    0    1    0    1    1    F                       
      1      1      0    1    1    0    1    1    F                       
      1      1      1    0    1    0    1    1    F                       
      1      1      1    1    1    0    1    1    F                       
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     In Table II, the number in the bracket represents a reference number of the frame memory. In this case, the frame editing block 21 sets 5-bit group number data (&#34;10111&#34;=&#34;17&#34; H  where H is the hexadecimal notation) in the register 23 and 4-bit write enable-disable data E3 of bits E3 through E0 in a second register 24. The second register 24 generates a write enable/disable prohibit pulse to the frame memories 25 to 28 in units of bits. In the case shown in FIG. 4 wherein the frame memories 27 and 28 are the copy destination frame memories, the frame editing block 21 sets the write enable/disable data of bits E3 through E0 as &#34;0011&#34; in the second register 24. Therefore, a signal of logic &#34;0&#34; is supplied to the frame memories 25 and 26, and a signal of logic &#34;1&#34; is supplied to the frame memories 27 and 28, so that the write mode is set. When the frame editing block 21 completes the data setting operation of the registers 23 and 24, the color index data b3b2b1b0 are sequentially read out from the areas A of the frame memories 25 and 26 and the corresponding areas from the frame memories 27 and 28 in units of pixels. The bits b3 through b0 of the color index data CI are linked with the 5 bits G4 through G0 of the group number data, and the resultant data is supplied as the ROM address to the ROM table 22. The conversion color index data having bits b3&#39; through b0&#39; whose content is given to be xxb3b2 is stored in the address of the ROM table 22 which is accessed in response to the data (G4 through G0 and b3 to b0). For example, when the color index data as the source data which is read out from the frame memories 25 to 28 and which has bits b3 to b0 is &#34;0100&#34;, the conversion color index data (destination data) read out from the ROM table 22 has bits b3&#39; through b0&#39; of &#34;0101&#34;. Similarly, when bits b3 through b0 are set to be &#34;1110&#34;, conversion color index data has bits b3&#39; through b0&#39; of &#34;1011&#34;. In other words, outputs b1&#39; and b0&#39; (&#34;01&#34; or &#34;11&#34;) are produced so as to copy outputs b3 and b2 (&#34;01&#34; or &#34;11&#34;) from the frame memories 25 and 26 into the frame memories 27 and 28. As a result, when the address data is supplied to the ROM table 22, the color index data having bits b3&#39; through b0&#39; whose content is converted to &#34;xxb3&#39;b2&#39;&#34; is read out. This color index data is supplied to the frame editing block 21. The frame editing block 21 supplies to the frame memories 25 through 28 the color index data which has the bits b3&#39; through b0&#39; and which is read out from the ROM table 22. In this case, the write operation is enabled in the frame memories 27 and 28 of the frame memories 25 through 28 in response to write enable bit data of the bits E3 through E0 of the write enable/disable data set in the register 24. Therefore, the bits b3&#39; and b2&#39; of the color index data having the bits b3&#39; through b0&#39; whose content is given to be xxb3&#39;b2&#39; are written in the accessed frame memories 27 and 28. The 4-bit data from the frame memories 25 through 28 is supplied to the display monitor 30 through a display conversion block 29 and is displayed on the display monitor 30. 
     According to the present invention as described above, since data predetermined by combinations of the copy source frame memories and the copy destination frame memories is set in the predetermined register, the color index data from the image memory can be directly converted into the corresponding color index data. For this reason, the interarea copy required in the color graphic display device can be performed at high speed. In addition, special processing can be performed merely by updating the content of the ROM table. In the above embodiment, the contents of the ROM table 22 are limited to the most frequent 32 combinations. However, the number of combinations stored in the ROM table is not limited to this, but can be increased to all possible combinations.