Multi-step parallel analog-digital converter
BACKGROUND OF THE INVENTION 
     This invention relates to apparatus for converting an electric analog signal into a corresponding digital signal, and more particularly to a high speed, high resolution analog/digital converter especially useful in a data acquisition system. 
     There are numerous devices available for converting an analog quantity into a corresponding digital quantity. One of the early A/D conversion techniques is the full parallel A/D converter in which an analog input signal to be converted is applied in parallel to a plurality of comparators, each comparator being referenced to a potential derived from a resistor chain comprising a plurality of equal value resistors which divide down a reference voltage so as to derive a comparator reference level for each possible quantization level. For any level of analog input signal, all comparators referenced to quantization levels below the input signal will be actuated, whereas those comparators referenced to levels above the input signal level will not be actuated. The outputs of all of the comparators are applied to a logic decoder which yields the corresponding parallel output digital signal. This type of converter is very fast, but it is obviously also very expensive since, for an n-bit converter it requires 2 n  -1 comparators and a relatively large and complex decoder. A 10-bit A/D converter will require 1,023 comparators. Other disadvantages are that the power dissipation is very high and it exhibits a large input capacitance due to the large number of comparators connected to the input terminal. 
     Another approach to the A/D conversion problem is the successive approximation analog/digital converter, the basic theory of which is described at pages 407-408 of the IEEE Transactions on Circuits and Systems, Vol. CAS-25 No. 7, July 1978. In a successive approximation register (SAR) method, the analog input voltage may be converted to a current and in each clock cycle this current is compared in a comparator with one bit of current from a digital/analog converter (DAC), starting with the most significant bit (MSB) of current. The comparator output represents the corresponding output bit of the A/D converter. Thus, an analog signal is converted into an n-bit digital signal in n clock cycles. The advantages of this approach are that the converter requires far less components, e.g. only one comparator, and that the power dissipation is much lower than the all-parallel method. A major disadvantage is that the conversion process is much slower in that it requires at least n clock cycles for an n-bit digital signal output. 
     A modification of the SAR method is the subranging A/D converter. The theory underlying this type of converter is described at pages 20-22 of the Analog-Digital Conversion Handbook, copyright 1964 by the Digital Equipment Corp. of Maynard, Mass. FIG. 18 of this handbook shows a subranging converter including a resistor chain, a series of comparators each with one input connected to the analog signal input terminal and second inputs connected to respective equally spaced tap points on the resistor chain. It also includes first and second DAC&#39;s connected respectively to the upper and lower ends of the resistor chain and a parallel decoder coupled to the outputs of the comparators. The subranging method operates by dividing the total input signal range into a number of subranges, selecting the appropriate subrange by means of the comparators and resistor chain, and then dividing this subrange into further subranges as before, and repeating the process until the desired resolution is achieved. 
     During a first clock cycle, the first DAC is set to the maximum voltage and the second DAC is set to zero. The outputs of the comparators indicate in which subrange the input signal falls, e.g. between the reference voltages applied to two adjacent comparators C.sub. k and C k+1 . During the next clock cycle, the reference voltage for comparator C k  is applied to the second DAC and the reference voltage for comparator C k+1  is applied to the first DAC so as to produce a second set of subranges between the values of the reference voltages for C k  and C k+1 . This is repeated until the desired resolution is obtained. A more sophisticated form of subranging A/D converter is shown in U.S. Pat. No. 3,298,014 in the name of B. W. Stephenson. A major disadvantage of these subranging A/D converters is that they require two digital/analog converters, which increases the size and cost of the apparatus, and presents additional problems in that the two DAC&#39;s must be accurately matched. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing, it is an object of this invention to provide an analog/digital converter that overcomes the disadvantages of the known converters. 
     Another object of the invention is to provide a subranging A/D converter that uses only a single DAC to convert an analog input into a digital output. 
     A further object of the invention is to provide a smaller and more efficient A/D converter that maintains a constant load on a source of reference voltage. 
     A still further object of the invention is to provide a general purpose, high speed, high resolution A/D converter that uses a multi-step parallel conversion process. 
     The foregoing objects are achieved in accordance with the invention by utilizing a single novel three-position-switchable current-output DAC in a sub-ranging type of A/D converter. In a preferred embodiment of the invention an analog quantity is converted into a corresponding digital quantity by quantizing two bits per clock cycle by means of a parallel encoder. 
     A further advantage of the invention is that a single array of comparators and a single resistor chain (voltage divider) is used during each successive parallel conversion step, thereby further simplifying the apparatus and reducing its cost and size. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects and advantages of the invention will become apparent upon consideration of the following detailed description of a preferred embodiment thereof, when read in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a preferred embodiment of the invention; 
     FIG. 2 is a schematic diagram of the D/A converter 12 of FIG. 1; 
     FIG. 3 is a schematic diagram of the decoder of FIG. 1; 
     FIG. 4 is a block diagram of the successive approximation of FIG. 1; 
     FIGS. 5A, 5B, 5C are a timing waveform diagram illustrating the operation of the SAR of FIG. 4; 
     FIG. 6 is a block diagram of the control logic module of FIG. 1; and 
     FIG. 7 is a timing waveform diagram useful in describing the operation of the logic of FIG. 6. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows a block diagram of the new multi-step parallel A/D converter utilizing a single three-position-switchable current output DAC. An input terminal 1 is provided for receiving an analog input voltage to be converted into a corresponding digital signal, e.g. a 10-bit digital representation. First, second and third comparators 2, 3 and 4, respectively, have their non-inverting (+) inputs connected to input terminal 1. A resistor chain (voltage divider) consistino of three equal value resistors 5, 6 and 7 is connected at one end to a terminal 8 adapted to receive a reference voltage (V ref ). 
     The resistor chain 5-7 has tap points 9, 10 and 11 connected to the inverting (-) inputs of comparators 2, 3 and 4, respectively. A ten-bit three-position-switchable current output digital/analog converter 12 has a first terminal connected to a junction point between resistor 5 and terminal 8 at which a current I 0  can be switched. The DAC 12 has a second terminal for a switchable current I 02  connected to tap point 9 on the resistor chain and a third terminal for a switchable current I 01  connected to tap point 11. This maintains a constant load on the source of reference voltage. 
     The comparators 2, 3 and 4 have output lines connected to inputs of a decoder 13. The decoder converts the comparator outputs into a ten-bit digital representation thereof two bits at a time, starting with the two MSB&#39;s designated D 10  and D 9 . Thus, the analog input signal is quantized two bits at a time in the parallel decoder 13 during each step of a conversion cycle. Each pair of bits appear on the decoder output lines designated DD 1  and DD 2 . 
     In the present embodiment, in each step the total input signal range is divided into four subranges which provide two data bits on output lines DD 1  and DD 2 . Thus, an analog input voltage is converted into its digital representation in five steps of a conversion cycle. In each step, the subrange containing the input voltage is selected. In each succeeding step the selected subrange is further divided into smaller subranges until the desired resolution is achieved. 
     The two data bits on decoder output lines DD 1  and DD 2  are applied to a successive approximation register (SAR) 14, the operation of which will be described in greater detail below. The SAR 14 is a modified form of the SAR that is used in a conventional SAR type A/D converter. It includes a shift register, data latches and decoding circuitry. The shift register in SAR 14 provides the proper timing sequence for latching the data from the decoder into the data latches, which in turn directly drive the output buffers 15. The shift register and data latch outputs are decoded by means of AND gates so as to control the switches in the DAC 12. The digital output signal appears at the output terminals of the output buffers 15. Only two of the ten output terminals are shown, i.e. terminal 16 for the MSB (D10) and terminal 17 for the LSB (D1). A further output terminal 18 provides a logic signal EOC which signals the end of a conversion cycle. 
     The operation of the analog/digital converter is controlled by means of a control logic module 19 which in turn is controlled by four microprocessor derived digital input control signals labeled CLK, START, CS and OE. The CLK input is the system clock connection for synchronizing the various elements of the converter. The operation of the converter is initiated by the START pulse, i.e. the negative going edge of this pulse initiates a conversion cycle. A high voltage level at the CS input inhibits the system from responding to the START pulse. A low level voltage at input OE enables the output buffers, whereas a high voltage level forces the output buffers into a three-state (high impedance) condition. The control logic 19 generates a pair of control signals SPA and SPB which are applied to the SAR 14 over control lines 20 to initiate a conversion cycle. The control logic also receives a signal over line 21 from the SAR, and in turn provides a signal over line 22 to the EOC buffer unit in output buffer 15 so as to indicate the end of a conversion cycle. 
     In one embodiment of my invention I use a DC supply voltage of +5V and -5V and a reference voltage, V ref , of 2.5V. On receipt of an external START signal, the control logic resets the A/D converter to an initial condition. Each of the resistors 5, 6 and 7 are of equal value, R. Initially, i.e. in the reset state, the two MSB currents (bits 10 and 9) of the DAC 12 are switched to the current line I 0 , the current in the line I 01  of DAC 12 is, ##EQU1## and the current in the line I 02  =0. The derivation of these currents will be explained in detail below in connection with the individual system modules. The current which then flows through the resistor chain 5∝7 produces voltage drops across the equal resistors such that the voltage levels at tap points 9, 10 and 11 are ##EQU2## respectively. In other words, the current flowing in the resistor chain produces a voltage drop across each resistor of 1/4 of the total range of the A/D converter, i.e. a voltage drop of V ref  /4 appears across each of the resistors 5-7. 
     Let us assume that the input analog voltage, V in , at terminal 1 is at a level between the reference voltage levels V 1  and V 2  as shown in the Table below. For example, assume V in  is 1.761V. With a reference voltage, V ref  =2.5V, then ##EQU3## at tap point 9 on the resistor chain voltage divider, ##EQU4## at tap point 10, and ##EQU5## at tap point 11. The resistance R of each of the resistors 5-7 is 625 Ohms. 
     
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CONVERSION TABLE                                                          
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 ##STR1##                                                                 
 ##STR2##                                                                 
 ##STR3##                                                                 
 ##STR4##                                                                 
 ##STR5##                                                                 
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     The analog input voltage, V in  is compared with these three voltage levels by the latching comparators 2-4 (positive edge triggered). The decoder 13 then converts the comparator outputs into the first two data bits, i.e. the two MSB&#39;s D 10  and D 9 , which appear on output lines DD 1  and DD 2 , respectively of the decoder. During the first step of the conversion cycle, the input voltage is located within one of four sub-ranges, i.e. V in  will be located either between OV and ##EQU6## or V 1  and V ref . In the example assumed, V in  has been located as being in the subrange between voltage levels V 1  and V 2 , i.e. between ##EQU7## shown in the Table. A binary &#34;1&#34; signal appears at decoder output line DD 1  and a binary &#34;0&#34; signal appears at output line DD 2 . These two MSB data bits are latched into the successive approximation register 14 on the following negative edge of the clock signal. Thus, the first conversion step has selected one of the four subranges. At the same time, the SAR 14 transfers the two MSB&#39;s thus derived, D 10  and D 9 , to the D 10  and D 9  output buffers, where they are stored. 
     In order to determine the next two bits (D 8  and D 7  ) of the digital signal, it is necessary to expand the previously determined subrange into four smaller subranges separated by equally spaced voltage levels lying between the previously determined voltage levels V 1  and V 2 . During the next (second) step of the conversion cycle, the switches in the DAC 12 are controlled by SAR 14 to cause currents of bits 8 and 7 of DAC 12 to switch from the current line I 01  to the current line I 0 , thereby decreasing I 01  to V ref  /16R, i.e. to a value 1/4 of its value during the first step. This causes the voltage drops across each of the resistors 5-7 to be V ref  /16. 
     Also the complement of data bits D 10  and D 9  determined in the first step are now switched to current line I 02  of DAC 12, i.e. I 02  =D 10  ×I 10  +D 9  ×I 9 . In the example chosen, since it was determined that D 10  =1 and D 9  =0; I 02  =0×I 10  +1×I 9  =I 9  =V ref/  4R. The current I 02  causes an additional voltage drop of V ref  /4 across resistor 5. 
     The combined effect of I 01  and I 02  is to set V 1  at tap point 9 to a value of V 1  =V ref  -V ref  /16-V ref  /4 =11V ref  /16, which is below the top of the selected subrange by a value of V ref  /16. The voltage drop of value V ref  /16 occurring across resistors 6 and 7 due to I 01  develops voltages at tap points 10 and 11, respectively, of V 2  =11V ref  /16-V ref  /16 =10V ref  /16 and V 3  =10V ref  /16-V ref  /16 =9V ref  /16. In other words, the previously determined subrange, bounded by V ref  /2 and 3V ref  /4 has been divided into four smaller subranges by setting the voltages at tap points 9, 10 and 11 to V 1  =11V ref  /16, V 2  =10V ref  /16 and V 3  =9V ref  /16. 
     As in step 1, the comparators and the decoder determine the next two data bits, D 8  and D 7 , of the digital output signal corresponding to the analog input voltage, V in . At the end of step 2, decoder output lines DD 1  and DD 2  each produce a binary &#34;1&#34; signal (see the Table) for the assumed value of V in . 
     This process is repeated for steps 3, 4 and 5 to determine the remaining data bits, D 6  and D 5  (step 3), D 4  and D 3  (step 4), and D 2  and D 1  (step 5). In each successive step a smaller subrange is selected so as to successively converge towards V in . The Table illustrates the first three steps of the conversion cycle for the assumed value of V in  and shows the output currents of DAC 12, the voltages at the tap points on the resistor chain (V 1 , V 2  and V 3 ), and the output data bits of the decoder 13 (DD 1  and DD 2 ). The current in current line I 0  is: I 0  =I FS  -I 01  -I 02 , where I FS  (i.e. I full  scale) of DAC 12 is V ref  /R. 
     The digital/analog converter 12 will now be described in greater detail with reference to FIG. 2. The DAC consists of two levels of interleaved, equal value current sources that generate the six MSB&#39;s, D 10  -D 5 . The technique of interleaving current sources is used to statistically average the errors due to component matching and thereby improve the accuracy. The first level includes the eight transistors Q A  and the second level includes the seven transistors Q B . The transistors Q A  form seven interleaved equal valued current sources connected in a 4:2:1 ratio to generate the three MSB currents I 10 , I 9  and I 8  of the DAC 12. The eighth current source, transistor 32, is connected to the second level of seven intervleaved equal valued current sources, transistors Q B , also connected in a 4:2:1 ratio to generate the next three current bits, I 7 , I 6  and I 5 . The last four bit currents (I 4  -I 1 ) of the DAC are generated by a so-called R/2R ladder that includes the four transistors Q D1  -Q D4  and the ladder network of resistors R B . The individual bit currents are selectively connected to the three output current lines I 01 , I 02  or I 0 , by means of three position switches consisting of differential amplifiers 23 that are switched between the on and off states under the control of signals received from SAR14 via the control lines 24. 
     The DAC includes a circuit for shifting the voltage level to provide the required base voltages for the transistors Q A , Q B  and Q D1  -QD 5  of the current sources. This circuit includes a reference control amplifier 25, e.g. a conventional op-amp such as the μA 741, having its inverting (-) input connected to analog ground and its non-inverting input (+) coupled via a resistor, R ref  (R ref  =4R), to an input terminal 26 for the voltage V ref . Transistors Q c , Q R1  and Q R2  form a negative feedback loop between the output of reference control amplifier 25 and its non-inverting input. A bias current source 27 provides bias current for the various transistors, e.g. transistors Q c , Q B  etc. 
     Under steady state conditions the negative feedback loop of amplifier 25 forces the positive (non-inverting) input terminal of the amplifier to be at a potential very close to the negative (inverting) input terminal thereof, which, as shown, is at analog ground potential. The current flowing through resistor R ref  is therefore V ref  /R ref . The input bias current of the amplifier is negligibly small so that the collector current of transistor Q c  is also V ref  /V ref . Neglecting any base currents, the collector currents of transistors Q R1  and Q R2  are each equal to V ref  /2R ref . It can therefore be said that the reference control amplifier drives the bases of the transistors Q R1  and Q R2  so that their collector currents are each equal to V ref  /2R ref . 
     All of the transistors Q A  are identical to the transistors Q R1  and Q R2  and each transistor also has an equal valued resistor R A  connected in its emitter lead. The transistors are all driven with the same base potential so that the collector current of each of these transistors is also equal to V ref  /2R ref . 
     The collectors of four of the transistors Q A  are connected together forming a current source which provides a current I 10  in the line 28 equal to ##EQU8## This current I 10  forms the MSB (bit 10) current source. 
     Similarly, the two Q a  transistors 29 and 30 together form the next MSB (bit 9) current source, ##EQU9## A single transistor 31 forms the third MSB (bit 8) current source ##EQU10## The current in the remaining Q A  transistor 32 is fed to the network composed of transistors Q B  connected in parallel and followed by an R/2R ladder network. 
     It can be shown that the network to the right of the circuit points labeled 33 and 34, including the five transistors Q D1  -Q D5  and the ladder network including resistors R B , is equivalent to a single transistor Q B  with a resistor R B  connected in its emitter lead. The overall circuit in the second level is therefore equivalent to eight transistors Q B  with eight respective emitter resistors R B . Thus, it can be seen that the collector current flowing through each of the transistors Q B  is one-eighth of the current fed by the collector of the Q A  transistor 32. Therefore, the collector current of each of the transistors labeled Q B  is equal to V ref  /16R ref . 
     The collectors of four of the transistors Q B  are connected toqether to form the fourth MSB (bit 7) current source so that ##EQU11## Similarly, the two Q B  transistors 35 and 36 together form the bit 6 current source, ##EQU12## A single Q B  transistor 37 forms the bit 5 current source, ##EQU13## 
     The network shown to the right of circuit points 33 and 34 is a R-2R ladder network which is typical of that used in many D/A converters. The current flowing into node 34 is divided in a binary fashion through each of the transistors. 
     Thus, the following currents flow in the collector circuits of the transistors Q D1  -Q D5  : ##EQU14## 
     The transistors labeled Q D1  through Q D5  are identical to the transistors labeled Q B . The collector currents flowing through transistors Q D1  -Q D5  is not the same as the current flowing through transistor Q B . The ratio of the currents flowing through the transistors is as follows: ##EQU15## 
     Since the current densities in the transistors differ by a factor of 2, the base/emitter voltage, V BE , of these transistors will be different by a factor of ##EQU16## This could create errors in the binary weighting of the currents. One solution to this problem is to include resistors R c  in the base circuits of the transistors, as shown in FIG. 2. A voltage drop of ##EQU17## is generated across the resistors which appears between the bases of the transistors. This compensates for the V BE  difference due to the current densities being different by a factor of two. 
     If a current equal to ##EQU18## flows through these resistors, it will create a voltage drop equal to ##EQU19## between the bases of the transistors. This will correct for the unequal values of V BE  due to unequal current densities of the transistors. 
     The circuit for generating the current ##EQU20## is composed of transistors Q E , Q F  and the two identical transistors labeled Q G . The emitter area of transistor Q F  is twice the emitter area of transistor Q E . Hence, the saturation current of transistor Q F  is twice the saturation current of transistor Q E , i.e. I S  (Q F )=2I s  (Q E ). Neglecting base currents, the collector current of the two transistors labeled Q G  is the same. Therefore, their V BE  is the same. Applying Kirchhoff&#39;s voltage law: 
     
         V.sub.BE (Q.sub.E)+V.sub.BE (Q.sub.G)=I.sub.F R.sub.c +V.sub.BE (Q.sub.F)+V.sub.BE 
    
     
         V.sub.BE (Q.sub.E)-V.sub.BE (Q.sub.F) 32 I.sub.F R.sub.C 
    
     Since the collector currents of QE and QF are the ##EQU21## 
     The following Table summarizes the individual bit currents. The specific values shown are for a reference voltage, V ref  =2.5V and R ref  =2.5 Kohms, where R ref  =4R. 
     
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Table of Current Bit Values                                               
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 ##STR6##                                                                 
 ##STR7##                                                                 
 ##STR8##                                                                 
 ##STR9##                                                                 
 ##STR10##                                                                
 ##STR11##                                                                
 ##STR12##                                                                
 ##STR13##                                                                
 ##STR14##                                                                
 ##STR15##                                                                
 ##STR16##                                                                
 ##STR17##                                                                
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     The bit currents I 10 , I 9  and I 2  +I 1  are each connected to the emitters of respective groups of two of the transistors 23. All of the remaining bit currents, I 3  through I 8 , are each connected to the emitters of respective groups of three transistors 23. The transistors 23 function as switches under control of the output signals of the SAR 14 and which are applied to the base electrodes thereof via the input terminals 38 and the lines 24. The transistors 23 selectively divert the bit currents to the output lines I 0 , I 01  and I 02  of the DAC 12 under control of the SAR 14, which in turn is controlled by the resistor chain, the comparators and the decoder 13. In any step of a conversion cycle, nine transistors of the total array of transistors 23 will be turned on, but only one transistor 23 in each of the nine groups of transistors will be turned on. For example, if the middle transistor 23 of the bit 8 current line is turned on, the other two transistors connected to line I 8  are cut-off so that the bit 8 current, I 8 , only flows in the output line I 02 . 
     In the first step of a conversion cycle, the left-hand transistors 23 of current bits 10 and 9 are turned on so that the output line I 0  carries a current, I 0  =I 9  +I 10  =1ma+2ma=3ma for the values V ref  =2.5V and R ref  =2.5K. At the same time, the right-hand transistors 23 of each group of three transistors connected to current bit lines I.sub. 3 through I 8  are turned on so that bit currents I 3  -I 8  flow in output line I01. Similarly, the right-hand transistors 23 of the pair of transistors connected to bit line I 2  +I 1  is turned on so this current too flows in output line I 01 . The termination current I t  from transistor Q D5  also flows in output line I 01 . The output line I 02  carries no current in step 1 of the conversion cycle. This will set the voltages on the voltage divider 5, 6 and 7 as follows ##EQU22## respectively. 
     With these values the A/D converter will determine the two MSB&#39;s (bit 10 and bit 9) of the digital signal that corresponds to the analog input voltage. For the example assumed above, D 10  =1 and D 9  =0. 
     Having determined the two MSBs of the A/D conversion process in the first step, the voltages V 1 , V 2  and V 3  on the voltage divider must now be changed in step two to a new set of values to determine the next two bits, bit 8 and bit 7, of the digital signal. Using the same example as before, since the analog input voltage falls between 3/4 V ref  and 1/2 V ref , the voltages are ##EQU23## Regardless of the analog input voltage, the voltage drop across resistors 6 and 7 of the resistor chain is V ref  /16 during the second step of a conversion cycle, i.e. 1/4 of its value in the previous step (step 1). 
     As described above in connection with FIG. 1, during the second step the SAR 14 switches the current bits I 8  and I 7  of DAC 12 from output line I 01  to output line I 0 , thereby decreasing I 01  to V ref  /16R to which causes the voltage drop across each resistor of the resistor chain to be the aforesaid V ref  /16. In step 2 the SAR 14 turns off the right hand transistors of each group of three transistors 23 connected to current bit lines I 8  and I 7  and turns on the left hand transistors thereof so that bit currents I 8  and I 7  now flow in output line I 0 . The current in output line I 0  =D 10  ×I 10  +D 9  ×I 9  +I 8  +I 7  =1×I 10  +0×I 9  +I 8  +I 7  =I 10  +I 8  +I 7  =2+0.5 +0.25=2.75ma. The left hand transistor of the pair of transistors 23 connected to current bit line I 10  stays on, and the right hand transistor stays off. 
     At the same time, the complement of bits D 10  and D 9  determined in step 1 are switched to output line I 02 , i.e. ##EQU24## Thus, the right hand transistor of the pair of transistors 23 connected to current bit line I 9  is switched on, and the left hand transistor of this pair is switched off. In addition, output current line I 01  now carries the current bits I 1  through I 6  +I terminmation  (I 01  =I 1  +I 2 . . . +I 6  +I T ). As in step 1, the right hand transistors of each group of three transistors 23 connected to current lines I 3  through I 6  stay on, as does the right hand transistor of the pair of transistors 23 connected to current bit line I 2  +I 1 . 
     In summary, for step 2, I 0  =I 10  +I 8  +I 7  ; I 01  =I 1  +I 2  . . . I 6  +I T  ; and I 02  =I 9 . As in the first step, the comparators 2-4 and the decoder 13 determine the values of the two bits, D 8  and D 7 , which for the assumed example are D 8  =1 and D 7  =1. The currents I 01  and I 02  set the voltages V 1 , V 2  and V 3  at tap points 9, 10 and 11, respectively, of the resistor chain 5-7 to the values: ##EQU25## respectively. The conversion process described is repeated for steps 3, 4 and 5 to determine the remaining bits, D 1  -D 6 , two bits per step. In each consecutive step, a narrower voltage subrange is selected so as to successively converge towards the value of V in . 
     In each successive step, I 01  is reduced to 1/4 of its previous value (e.g. ##EQU26## in step 3). The current I 02  is determined by the data bits derived in the earlier steps. The DAC bit currents that flow in line I 02  are those for which the corresponding derived output bit has been determined to be a zero during all of the previous steps in a conversion cycle. 
     FIG. 3 illustrates in schematic form a simplified version of the decoder 13. The output lines from the comparators 2 (C 1 , C 1 ), 3 (C 2 , C 2 ) and 4 (C 3 , C 3 ) are connected to the base electrodes of respective ones of three differential amplifiers composed of transistors Q 1  -Q 2 , Q 3  -Q 4  and Q 5  -Q 6 . The output lines C 2 , C 2  from comparator 3 are also connected to respective base electrodes of a differential amplifier composed of transistors Q 7  and Q 8 . The MSB of each pair of bits decoded appears at decoder output lines 39 (DD 1 ) and 40 (DD 1 ), whereas the LSB appears at output terminals 41 (DD 2 ) and 42 (DD 2 ). 
     The collector electrodes of transistors Q 1 , Q 4  and Q 5  are connected together and via a resistor 43 to the positive supply voltage terminal V(+). The collector electrodes of transistors Q 2 , Q 3  and Q 6  are connected together and via a resistor 44 to the positive DC voltage V(+). Output terminal 39 is connected to the lower end of resistor 44 and output 40 is connected to the lower end of resistor 43. 
     The emitter electrodes of transistors Q 1  and Q 2  are directly connected together and via a current source 45 to the negative DC voltage supply terminal, V(-). Similarly, the emitters of transistors Q 3  and Q 4  are connected together and via a current source 46 to the supply terminal V(-). The connected emitters of transistors Q 5  and Q 6  are coupled via current source 47 to the negative supply voltage terminal. Each of the current sources 45, 46 and 47 suoply identical currents, I. In view of the collector connections shown, either a current I or a current 2I will flow through resistors 43 and 44 thus creating a differential output signal. A differential signal can be used to signify a logic state. 
     The transistors Q 9 , Q 10 , Q 11  and Q 12  perform the reset function. The collector of transistor Q 9  is connected to the junction point between resistor 44 and the collectors of transistors Q 2 , Q 3  and Q 6 , while the collector of transistor Q 10  is directly connected to the positive DC supply voltage terminal V(+). The emitters of Q 9  and Q 10  are connected together and via a current source 48 to the negative supply terminal V(-). 
     The collector electrodes of transistors Q 7  and Q 8  are connected via respective resistors 49 and 50 and a common resistor 51 to the positive terminal V(+). Output terminal 41 for the DD 2  data bit is connected to a junction point between resistor 50 and the collector electrodes of transistors Q 8  and Q 11 , while output terminal 42 (DD 2 ) is connected to a junction point between resistor 49 and the collector of transistor Q 7 . 
     The collector of transistor Q 12  is connected to a junction point between resistors 49, 50 and 51. The emitters of Q 7  and Q 8  are connected together and via a current source 52 to the negative DC supply terminal, while the emitters of Q 11  and Q 12  are similarly connected together and via a current source 53 to said negative terminal. The current sources 48 and 53 each supply a current 2I and the current source 52 provides a current I. 
     The base electrodes of transistors Q 10  and Q 12  are connected together and to the output of an inverting amplifier 54. The input of amplifier 54 is connected to an input terminal 55 which receives a signal SPB from the control logic module 19. The base electrodes of transistors Q 9  and Q 11  are connected to input terminal 55. 
     The decoder of FIG. 3 operates in accordance with the following Truth Table: 
     
                       TRUTH TABLE                                                 
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SPB    C.sub.1    C.sub.2                                                 
                        C.sub.3 DD1  DD2                                  
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0      1          1     1       1    1                                    
0      0          1     1       1    0                                    
0      0          0     1       0    1                                    
0      0          0     0       0    0                                    
1      x          x     x       0    0                                    
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     As long as the SPB signal received at terminal 55 from SAR 14 is high, an additional current 2I flows through resistor 44 via transistor Q 9  and current source 48. Similarly, an additional current 2I flows through resistor 50 via transistor Q 11  and current source 53. This forces the DD1 and DD2 outputs of the decoder into a low state. The Truth Table indicates that there can be only four possible combinations of the output states of the comparators 2-4, due to the way they are connected in the circuit. 
     For the assumed input voltage V in  discussed above, during step 1 the comparators 3 (C 2 ) and 4 (C 3 ) each produce a logic &#34;1&#34; output, whereas comparator 2 (C 1 ) produces a logic &#34;0&#34; output. This is because V in  falls between the voltage levels V 1  (tap 9) and V 2  (tap 10) of the voltage divider 5-7. The Truth Table shows that the output lines DD 1  and DD 2  of the decoder now provide a logic &#34;1&#34; and a logic &#34;0&#34; signal, respectively (also see step 1 in the conversion table). 
     Referring to step 2 in the conversion table, it can be seen that V in  falls within the uppermost of the four voltage levels so that all three comparators produce a logic &#34;1&#34; output, i.e. the top line of the Decoder Truth Table now prevails. Therefore, decoder output lines DD1 32 1 and DD2 32 1, which is the same as was described earlier and as shown in the conversion table under step 2. The third and fourth data bits, D 8  and D 7 , are each a logic &#34;1&#34; and are stored in output buffer 15. A similar analysis will confirm that the last six data bits derived in steps 3-5 of the conversion cycle will produce the following values: D6=0 and D 5  =1 (step 3); D 4  =0 and D 3  =0 (step 4); and D 2  =0 and D 1  =1 (step 5). 
     A diagram of the successive approximation register (SAR) 14 is shown in FIG. 4. It comprises a 6-stage shift register made up of D-type flip-flops 56-61 and ten data latch flip-flops 62-71. The D-flip-flops 56-61 are negative edge triggered. If the Set input is at a logic 0, the Q outputs will attain the same logic state that was present at the D-input just prior to the clock signal going from logic 1 to logic 0. At all other times, the D-input has no effect on the Q-output. A logic 1 at the Set input of the D-flip-flop forces the Q-output to be a logic 1 regardless of the state of the clock and D-input. 
     The data latch flip-flops 62-71 are fall through type flip flops, which means that as long as the LE input is a logic 0, the D-output of the latch will attain the same logic state that is present at the D-input. When the LE input is a logic 1, the D-output of the latch will retain the logic state that it was in just prior to the LE input going from logic 0 to logic 1. The D-output of the latch does not change as long as the LE input is a logic 1 regardless of any changes in the D-input. 
     The SAR also includes decoding circuitry consisting of NOR gates 72-79 and AND gates 110-115. The SAR is controlled by input signals at input terminals 80 and 81 for the DD1 and DD2 output signals of decoder 13, and at terminals 82, 83, 84 and 85 by the control logic output signals SPA, CLK, SPB and CLK, respectively. 
     The D-input terminal of flip-flop 56 is permanently connected to a terminal 86 at which a logic &#34;0&#34; signal is maintained. The output terminals 87a through 87x (only certain ones of said terminals being labeled) provide the control signals that are applied to the base electrodes of switching transistors 23 of DAC 12 via the DAC input terminals 38 (FIG. 2). The pair of data bits DD1 and DD2 from decoder 13 appearing at input terminals 80 and 81 are latched into data latch flipflops 62-71. The data latch outputs D 10  -D 1  directly drive the output buffers. The connections to the output buffers are only shown for data bits D 10  (terminals 90a, 90b), D 2  (terminals 88a, 88b) and D 1  (terminals 89a, 89b). Output terminals 88a, 88b and 89a, 89b and 90a, 90b couple these data bits to respective stages D 10 , D 2  and D 1  of the output buffer 15. 
     The SPA signal at terminal 82 is coupled to one input of each of the NOR gates 72-75. A second input of the NOR gates 72-75 is connected to a respective output of the NOR gates 76-79. One input of each of the three-input NOR gates 76-79 is coupled to terminal 83 which receives the CLK signal from the control logic module 19. 
     The SPB signal appearing at terminal 84 is connected to the Set input terminals of shift register flipflops 56-61 and the CLK signals at terminal 85 are coupled to the clock input terminals of the flipflops. The Q outputs of flipflops 56, 58, 59 and 60 are connected to respective second inputs of NOR gates 76, 77, 78 and 79, respectively. The Q outputs of flipflops 57, 58 and 59 are coupled to third inputs of NOR gates 77, 78 and 79, respectively. The SPB terminal 84 is coupled to a third input of NOR gate 76. 
     The output of NOR gate 72 is connected to the LE input of data latch flipflops 62 and 63. Similarly, the respective outputs N 6 , N 7  and N 8  of NOR gates 73, 74 and 75 are connected to LE inputs of data latch flipflops 64-65, 66-67, and 68-69, respectively. The D-inputs of data latch flipflops 62, 64, 66, 68 and 70 are coupled to input terminal 80 (DD1 bit), whereas the D-inputs of data latch flipflops 63, 65, 67, 69, and 71 are coupled to input terminal 81 (DD2 bit). 
     One input of the AND gates 110-115 is connected to a respective D output of the data latch flipflops 64-69. A second input of AND gates 110 and 111 is each connected to the Q output of flipflop 56. Similarly, second inputs of AND gates 112, 113 are connected to the Q output of flipflop 58 and second inputs of AND gates 114, 115 are connected to the Q output of flipflop 59. 
     In addition, the Q output of flipflop 56 is connected to output terminals 87e and 87h of the SAR 14, the Q output of flipflop 58 is connected to output terminal 87k and 87n, the Q output of flipflop 59 is connected to output terminal 87q and 87t, and the Q output of flipflop 60 is connected to output terminal 87w and the Q output of flip-flop 60 is connected to output terminal 87x. The Q outputs of flipflops 56-60 are successively connected to the D inputs of flipflops 57-61. The Q output of flipflop 61 is coupled to the LE inputs of data latch flipflops 70 and 71. 
     The operation of the SAR 14 can be readily understood by consideration of the timing diagram in FIG. 5, which will serve as a basic explanation thereof. The shift register (flipflops 56-61) provides the proper timing sequence for latching the data bits (DD1 and DD2) from the decoder into the data latches (flipflops 62-71). The data latch outputs D 10  -D 1  directly drive the output buffers. 
     The SAR operates to decode the input signals applied to it thereby to provide the output signals labeled A-X which appear at terminals 87a-87x for selectively operating the switches (transistors 23) in the DAC 12. The SAR is preferably implemented in current mode logic. 
     At time T 1  on the timing diagram, FIG. 5, the START input waveform goes negative and the SPA and SPB waveforms each go positive, whereby all of the shift register flipflops are set so that the Q outputs are a logical &#34;1&#34; and the Q outputs are a logical &#34;0&#34;. Thus, the Q 4  -Q 8  outputs of flipflops 56-60 go positive and the Q 9  of flipflop 61 goes negative at time T 1 . The positive going edge of the SPA signal at terminal 82 produces the negative going edges of the waveforms N 5  -N 8  at the outputs of NOR gates 72-75. Since at least one input to each of NOR gates 76-79 is high at time T 1 , therefore the NOR gate output waveforms N 1  -N 4  are all low. 
     Prior to time T 1 , the comparators 2-4 (C 1  -C.sub. 3), decoder 13 (DD1, DD2), data latches (D 10  -D 1 ) and AND gates 110-115 outputs are in particular states determined by the last conversion cycle, which is indicated by the diagonal lines on the waveform diagram. Since comparators 2-4 only respond when the CLK waveform goes high, they remain in the same state because time T 1  occurs somewhere in the middle of a clock pulse. Also at time T 1 , the data latches 62-69 (D 10  -D 3 ) assume the state where the D outputs are positive (logic one) and the D outputs are negative (logic 0), since DD1 and DD2 are both in a low state. 
     The foregoing causes the transistor switches in DAC 12 to be switched so that current bits I 10  and I 9  are switched to output line I 0  and all of the remaining current bits are switched to output line I 01 . As a result, the voltages at tap points 9, 10 and 11 are V 1  =1.875V, V 2  =1.25V and V 3  =0.625V, respectively (with each resistor 5, 6 and 7 having a resistance R=625 ohms). At time T 2 , the CLK signal goes high, whereby comparators 2-4 (waveforms C 1  -C 3 ) can now respond to the voltage levels established at their input terminals. For the assumed value of V in  =1.761V, the output of comparator 2 (waveform C 1  in FIG. 5) will now be low (logic 0), whereas the outputs of comparators 3 (waveform C 2 ) and 4 (waveform C 3 ) are each high (logic 1). Therefore, in accordance with the decoder truth table, since C 1  =0, C 2  =1 and C 3  =1, the output DD1 is primed to go high (logic 1) and output DD2 is primed to go low (logic 0). At time T 3  the SPB signal goes low at terminal 55 of decoder 13, releasing the decoder so output DD1 then goes high (logic 1). 
     The time period between T 1  and T 3  is provided to give time for the currents to settle in the DAC 12. During this period, the SPA signal goes low, whereupon NOR gate outputs N 5  -N 8  all go high because the SPA input and the N 1  -N 4  inputs to NOR gates 72-75 are then all at logic 0. 
     The positive edge of the clock pulse at time T 3  latches the comparators 2-4 so that they can no longer respond to changes in the analog input voltage, V in . Also at T 3 , the decoder 13 is released so that it can respond to the output signals of the comparators. On the negative edge of the next CLK signal, output N 1  of NOR gate 76 goes high and so the output N 5  of NOR gate 72 goes low. This enables flip-flops 62 and 63 so that these Data Latches for bits D 10  and D 9  can now respond to the signals DD1 and DD2 from the decoder received at terminals 80 and 81. The waveforms D 10  and D 9  are now high (logic 1) and low (logic 0), respectively. 
     At this time, none of the other data latches can respond because output terminals N 6 , N 7  and N 8  of NOR gates 73, 74, and 75, respectively, are all still in the high (logic 1) state. Since the D 9  output is low and the D 9  of data latch 63 is high, (see waveforms B and D) the left-hand transistor 23 connected to output line I 9  in DAC 12 is cut-off and the right-hand transistor connected to output line I 9  is conductive. As a result, the current I 9  (1 ma) is now switched over from output line I 0  to output line I 02  of the DAC 12. Also, as output D10 is high, the left hand transistor 23 coupled to current bit line I 10  is still conductive so that the current I 10  still flows in output line I 0 . This does not affect comparator output waveforms C 1 , C 2  and C 3  since the comparators 2-4 are in the latch mode. At time T 4 , the CLK waveform goes positive, driving NOR gate 76 to produce a logic 0 at output terminal N 1 , which in turn allows NOR gate 72 to produce a logic 1 signal at output N 5  since both of its inputs, N 1  and SPA, are both logic 0 (low) at T 4 . The data bits DD1 and DD2 are now latched into the D 10  and D 9  Data Latches 62 and 63, respectively. This completes step 1 with DD 1  =D 10  =1 and DD2=D 9  =0 stored in flip-flops 62 and 63 and, via the flip-flop output lines, coupled to the D 10  and D 9  stages of the output buffer 15 and stored therein. 
     At time T 4 , the negative edge of the CLK signal at terminal 85 causes the logic 0 signal at terminal 86 (D-input of flip-flop 56) to appear at the Q 4  output of flip-flop 56, i.e. the Q 4  waveform goes low (logic 0). As a result, output lines 87e and 87h of SAR 14 go negative, which cuts off the right-hand transistors of each group of three transistors 23 connected to current bit lines I 8  and I 7  in DAC 12. At this time, the D 8  outputs of data latch flip-flop 64 and 65 are each low (logic 0) so that the middle transistors 23 connected to current bit lines I 8  and I 7  in DAC 12 are also cut off. However, since the Q 4  output of flip-flop 56 is high, as are the D 8  and D 7  outputs of flip-flops 64 and 65, AND gates 80 and 81 each have a logic 1 (high) output. The outputs of gates 80 and 81 (waveforms F and I) are coupled to the left-hand transistors 23 of current bit lines I 8  and I 7 , respectively, which makes these transistors conductive. Therefore, the current bits I 8  and I 7  in DAC 12 are switched from output line I 01  to output line I 0 . 
     In step 2 of the conversion cycle, the D 10  output of data latch 62 is low (logic 0) and the D 9  output of data latch 63 is high (logic 1), see waveforms B and D. Therefore, the right transistor of the pair of transistors 23 connected to current bit line I 9  in the DAC 12 will conduct so that the current I 9  flows in output line I 02 . Also, as mentioned above, since output D 10  is high, the current I 10  still flows in output line I 0 . Step 2 now sees I 0  =I 10  +I 10  +I 8  +I 7  =1ma +0.5ma +0.25ma=1.75ma. Also, I 02  =I 9  =1ma and I 01  =I 1  +I 2  . . . +I 6  +I t  =0.25ma. As a result, the voltages at tap points 9, 10 and 11 are V 1  =1.71875V, V 2  =1.5625V and V 3  = 1.40625V, respectively. 
     The time period between T 5  and T 6  is similar to the time period T 3  -T 4 . The comparators are latched on the positive edge of the clock signal. Since V in  &gt;V 1  &gt;V 2  &gt;V 3 , C 1  =1, C 2  =1 and C 3  =1. From the decoder Truth Table, DD1=1 and DD2=1. On the negative edge of waveform N 6 , the D 8  and D 7  data latches (flip-flops 64 and 65) are enabled. Since both D 8  and D 7  are logic &#34;1&#34;, no change in I 02  occurs. The positive edge of waveform N 6  latches D 8  and D 7  to complete step 2. 
     In a manner similar to that occurring at time T 4 , at time T 6  the negative edge of the CLK signal at terminal 85 causes the Q and Q outputs of flip-flop 58 to change state i.e. Q 6  =0 and Q 6  =1. As a result of which, the current bits I 6  and I 5  of DAC 12 are switched from output line I 01  to output line I 0 , reducing I 01  to 0.0625ma, changing the voltages at tap points 9, 10 and 11 to V 1  =1.83594V, V 2  =1.79688V and V 3  =1.75781V, respectively. There is no additional time provided for the DAC currents to settle. The time period T 6  -T 7  is similar to the time periods T 3  -T 4  and T 5  -T 6 . The comparators are again latched on the positive edge of the clock signal and since V 1  &gt;V 2  &gt;V in  &gt;V 3 , then C 1  =0, C 2  =0  and C 3  =1. From the Truth Table, decoder outputs DD1=0 and DD2=1. On the negative edge of waveform N 7 , the D 6  and D 5  data latches 66 and 67 are enabled so that current bit I 6  is now switched to output line I 02 . The comparator outputs cannot change since they are in the latched mode. Therefore, I 02  =I 9  +I 6  =1.125ma. The positive (rising) edge of waveform N 7  latches D 6  and D 5  and so completes step 3. 
     Similar to time points T 4  and T 6 , at time T 7  the current bits I 4  and I 3  of DAC 12 are switched from output line I 01  to output line I 0 , reducing the current I 01  to 0.015625ma and the voltages at tap points 9, 10 and 11 to V 1  =1.78711V, V 2  =1.77734V and V 3  =1.76758V, respectively. The time period T 7  -T 8  is similar to the time periods T 3  -T 4 , T 5  -T 6  and T 6  -T 7 . Since V 1  &gt;V 2  &gt;V 3  &gt;V in , the comparator outputs are C 1  =0, C 2  =0 and C 3  =0, which are latched on the positive edge of CLK. From the decoder Truth Table, DD1=0 and DD2 =0. On the negative edge of waveform N 8 , the D 4  and D 3  Data Latches are enabled. Since D 4  =0  and D 3  =0, current bits I 4  and I 3  are switched to output line I 02 , i.e. I 02  =I 9  +I 6  +I 4  +I 3  =1.171875ma. The comparator outputs cannot change since they are in a latched mode. The positive going edge of waveform N 8  latches D 4  and D 3  to complete step 4. 
     Similar to time points T 4 , T 6  and T 7 , at time T 8  the current bits I 2  and I 1  of DAC 12 are switched from output line I 01  to output line I 0 , thereby reducing the current I 01  to the 
     termination current, I T  =0.00390625ma. The voltages at tap points 9, 10 and 11 are now V 1  =1.76514V, V 2  =1.7627V and V 3  =1.76025V, respectively. Since V 1  &gt;V 2  &gt;V in  &gt;V 3 , the 
     comparator outputs are C 1  =0, C 2  =0 and C 3  =1, which are latched on the positive edge of CLK. The decoder truth table shows DD1 =0 and DD2 =1 for these values. On the positive edge of the of Q 9  flip-flop 61, the data bits D 2  and D 1  are latched to complete step 5. 
     The output Q 8  of flip-flop 60 is coupled to the control logic module which, in response thereto, produces the EOC signal indicating the end of a conversion cycle. 
     FIG. 6 is a block schematic diagram of the control logic module 19 and FIG. 7 is a timing diagram useful in explaining the operation of FIG. 6. The START, CLK, CS, OE control signals are applied to input buffer stages 91, 92, 93 and 94, respectively. The input buffers convert the standard TTL level signals to the internal logic levels of the A/D converter. They also generate the complement of the signal, i.e. the CLK input buffer 92 generates two complementary signals for internal use, CLK and CLK. 
     The CLK input provides the system clock connection. When the START input signal goes to a low level, the conversion process is started. A high level input at the CS input will inhibit the system from responding to a START signal pulse and thereby prevent a conversion from taking place. A low level signal OE enables the output buffers and a high level OE signal forces the output buffers into a 3-state mode. 
     At time T 1 , the START waveform goes low (logic 0). Since the CS waveform is then also low, the output N 9  of NOR gate 95 goes high (logic 1). The logic 1 signal at terminal N 9  triggers flip-flop 96 at its CLK input so that the logic &#34;1&#39; permanently coupled to the D in  terminal from terminal 97 sets the flip-flop so that the Q 1  output goes high. The Q 1  output of flip-flop 96 provides the SPA signal at output terminal 98. The Q 1  output is also applied to SPB output terminal 99 via OR gate 100, so the SPB and SPA waveforms both go positive when the START waveform goes negative. 
     At the same time, input terminal 101 receives a logic 1 signal from the Q 8  output of flip-flop 60 in SAR 14 (see FIGS. 4 and 5). The logic 1 signal at terminal 101 produces a logic 0 signal at output terminal N 10  of NOR gate 102. Since the OE and CS inputs to NOR gate 103 are now also at logic 0, output N 11  of this gate goes high (logic 1). This produces a logic 0 signal at the Set input of D-type flip-flop 104 via an inverter 105. 
     At time T 2 , the CLK signal from buffer 92 triggers the CLK input of D-type flip-flops 106 and 104. Since the Q 1  output of flip-flop 96, connected to the D-input of the flip-flop 106 is in a high-state (logic 1), the Q 2  output of flip-flop 106 goes high. Also, since the Q 8  output of flip-flop 60 in SAR 14 (see FIGS. 4 and 5) is in a high state and is connected to the D input of flip-flop 104, the Q 10  output of flip-flop 104 goes high. 
     At the next negative going edge of the CLK signal from CLK buffer 92, the D-type flip-flop 107 transfers the logic 1  signal at its input D in  to output Q 3 , i.e. output Q 3  goes high. The logic 1 signal at Q 3  is coupled to the Reset input of flio-flop 96, which is immediately reset. The Q 1  output of flip-flop 96, and hence the SPA signal, goes low when output Q 3  of flip-flop 107 goes high. However, the SPB signal remains high as it still receives the logic 1 signal from the Q 2  output of flip-flop 106, via OR gate 100. 
     As the input D in  of flip-flop 106 is now low, the next negative edge of the CLK signal causes flip-flop 106 to switch over and cause output Q 2  to go low. This occurs at time T 3  and causes the SPB waveform to go low. At the next negative going edge of the CLK signal, the flip-flop 107 transfers the logic 0 signal at its D in  input to its Q 3  output, so waveform Q 3  goes low. 
     At time T 8 , the Q 8  output of flip-flop 60 in SAR 14 goes low (see FIG. 5), so terminal 101 goes to logic 0. Since output terminal N 11  of NOR gate 103 is still a logic 1, the output N 10  of NOR gate 102 remains at logic 0. However, the D in  terminal of flip-flop 104 is now at logic 0. The next negative edge of the CLK signal occurs at time T 9  and triggers flip-flop 104 so that its Q 10  output goes negative. This is the EOC signal and it is transferred via output terminal 22 to the EOC buffer stage in output buffer 15, thus signalling the end of conversion. 
     After the EOC signals the end of the conversion, at a time determined by the user, the OE input is set to a logic 0. The OE signal goes to a logic 1. This releases the output buffers from the three-state (high impedance) condition so that the output buffers are enabled and the result of the A/D conversion appears at the output terminals of the A/D converter. Since the OE line is connected to the input of NOR gate 103 its output N11 goes to logic 0. This output is connected to the input of NOR gate 102. The other input of NOR gate 102 is connected to terminal 101 which receives a logic 0 signal from the Q 8  output of flip-flop 60 in SAR 14 (see FIGS. 4 and 5). Since both inputs of NOR gate 102 are logic 0, the output N10 of this gate goes to logic 1. The logic 0 signal at the output of gate 103 produces a logic 1 signal at the set input of flip-flop 104 via the inverter 105. The Q 10  output of flip-flop 104 therefore goes to logic 1, which is transferred via terminal 22 to the EOC buffer stage. This puts the A/D converter in a state suitable for the next conversion to take place. 
     Although the invention has been described in connection with a particular preferred embodiment thereof, it will be apparent that various other embodiments and modifications thereof will become obvious to persons skilled in the art. For example, while I have described my A/D converter as a 10-bit converter in which the analog input signal is converted into digital form in five steps, with two bits converted per step, it will be clear that with suitable modifications of the apparatus in accordance with the above disclosure, more than two bits can be converted in each step, and more or less steps can be used to provide a complete conversion cycle. The scope of the invention is therefore to be limited only by the appended claims and not by the specific details of the preferred embodiment described herein. 
     In the timing diagrams of FIG. 5, the cross-hatched areas for the voltages V 1 , V 2  and V 3  indicate that these voltages are at an intermediate value which is then irrelevant. The values shown in the Table of FIG. 5 occur at the points in time indicated by the vertical arrows at the top of the Table. Prior to time T 1 , the values of I 01 , I 02 , V 1 , V 2  and V 3  are determined by the results of a previous conversion cycle.