Input circuit of MOS-type integrated circuit elements
This invention relates to an improved input circuit of MOS-type integrated circuit elements and more particularly to such an input circuit having improved delay characteristics. 
     An object of this invention is to provide an input circuit of MOS-type integrated circuit elements with reduced power consumption and improved delay characteristics. 
     The above and other objects of this invention are attained by providing an input circuit with MOS-type integrated circuit elements comprising a first enhancement-mode MOS field-effect transistor (hereinafter abbreviated into EMOSFET) to the gate of which a power source is connected and to the drain of which a first action signal is adapted to be applied, a second EMOSFET to the drain of which the power source is connected, and a depletion-mode MOS field-effect transistor (hereinafter abbreviated into DMOSFET) the gate and the source of which are connected, the source of the first EMOSFET and the gate of the second EMOSFET being connected, the source of the second EMOSFET and the drain of the DMOSFET being connected, and a boost capacitor being connected between the gate of the second EMOSFET and a second action signal. 
    
    
     The foregoing objects and the invention will be more clearly understood from the following description which is provided by way of example and not of limitation, wherein: 
     FIG. 1 is a circuit diagram according to an embodiment of the invention; 
     FIG. 2 is a signal waveform diagram for explaining its operation; and 
     FIG. 3 is a diagram showing the delay characteristics of an input circuit. 
    
    
     In FIG. 1, there is shown a circuit diagram according to an embodiment of the present invention, wherein numerals 2, 3, 4, 10 and 11 indicate respectively an EMOSFET and numeral 12 indicates a DMOSFET. The source of the EMOSFET 3 is grounded, the drain of the EMOSFET 3 and the source of the EMOSFET 2 are connected and this joint is connected to the source of the EMOSFET 4. The gates of the EMOSFETs 2 and 3 are joined and connected to an input terminal φ IN . The drain of the EMOSFET 2 and the source of the DMOSFET 12 are connected and this joint is connected to the gate of the EMOSFET 4, the drain of which is connected to a power source V CC , to form an output terminal φ OUT . The source and the gate of the DMOSFET 12 are connected, its drain is connected to the source of the EMOSFET 11 and the drain of the EMOSFET 11 is connected to the power source V CC . The drain of the EMOSFET 10 is connected to a first action signal terminal φ A , its gate is connected to the power source V CC  and its source is connected to the gate of the EMOSFET 11, a MOS capacitor 13 for boosting being connected between this joint (node 20) and a second action signal terminal φ B . The EMOSFETs 10 and 11, the DMOSFET 12 and the boost MOS capacitor 13 form the load 14 for the input circuit. 
     The circuit described above is further so designed that the driving capability of the EMOSFET 11 (or its current amplification factor) is sufficiently larger than that of the DMOSFET 12. This can be accomplished, for example, by increasing the width of the gate of the EMOSFET 11 or reducing its length. The timing waveform diagram of FIG. 2 will be used next to explain the operation of the input circuit of the present invention. 
     During a wait period, both the first and second action signals φ A  and φ B  are low and since the node 20 is also low through the EMOSFET 10, the EMOSFET 11 is cut off and power is not consumed. When the circuit enters an active period, the first action signal φ A  becomes high as shown in FIG. 2 and the charging of the MOS capacitor 13 is started. This charging time is indicated by t 1  in FIG. 2. When charging is completed, the second action signal φ B  is inputted (as shown by t 2 ) and the potential at the node 20 is boosted to a level higher than the source voltage V CC . At this point, the EMOSFET 11 is completely conductive and an output signal with reversed polarity is outputted at the output terminal φ OUT  in response to an input signal φ IN  after a delay time of t d . 
     Since the driving capability of the EMOSFET 11 is set to be sufficiently larger than that of the DMOSFET 12, the potential at the node 21 is maintained approximately at the level of the source voltage V CC , and since the circuit composed of the EMOSFETs 2, 3 and 4 and the DMOSFET 12 is similar to a conventional input circuit, the delay characteristics also show weak dependency on the source voltage. The dependency of the delay time t d  of this embodiment on the source voltage is shown by the curve 9 in FIG. 3. 
     In summary, an input circuit according to the present invention can reduce the power consumption during the wait period and provides favorable delay characteristics with weak dependency on the source voltage during the active period, thereby contributing significantly to the improvement of the capabilities of MOS integrated circuit elements.