Method and apparatus for testing shielded cable assemblies
The invention pertains generally to a method and apparatus for testing shielded cable assemblies and is more particularly directed to an automated test apparatus which can test the integrity of a connector shield at either end of a cable assembly. 
     In the data processing and computer control field when information is transferred between processors, or between a processor and a peripheral device, it conventionally is communicated by means of a shielded I/O cable assembly. A cable assembly of this type consists of a length of shielded cable which is terminated on either end by a shielded connector. The connectors at each end of the assembly can be the same or different, depending upon the interface needs of the system being connected. 
     The cable and connectors are shielded for at least two reasons, both of which are related to the high speed digital data which is being transmitted through the assembly. First, the data being transmitted through the cable assembly creates electrical and magnetic fields (EMI) which if not shielded from the other computer equipment could cause loss of data in the memories of these devices. There are strict standards for the amount of EMI that can be generated by a device in the computer field and thus, assemblies without adequate shielding cannot be used for these purposes if their radiated emissions are greater than a certain amount. Such standards are imposed by Governmental agencies, for example, the Federal Communications Commission, industrial agencies, and even specific customers. 
     Further, these shielded cables may be used in an environment where the electrical and magnetic fields are such that if given the opportunity to interact with the fields of the cable assembly, could cause a disruption of the communication or faulty data transmission. Thus, a shielded cable can be used in a noisy environment to ensure that high speed digital data can be transferred between devices without compromising its integrity. 
     A cable connector is usually comprised of a shell or connector body which interfaces the individual conductors of the cable to predetermined connector pins which mate with pins of an oppositely posed connector of the device being joined. The connector also includes a connector shield to dissipate any electro-magnetic interference at the connector shell. The cable comprises the individual conductors and insulation which are surrounded by a cable shield. The most critical areas for guarantying shield integrity for the cable assembly are the interfaces or mechanical connections between the connector shield and connector shell and the connector shield and the cable shield. Should these interfaces exhibit a high impedance characteristic over certain portions of the RF frequency band, the result could be leakage of the fields of the cable into the environment and a high level of EMI. Additionally, such high impedance paths could create a entry point for outside electrical and magnetic fields to enter the cable assembly. 
     In general, the high impedance interfaces are due to poor bonding between the conductive elements forming the separate shields. Poor bonding can be the result of procedures in the manufacturing process when improper techniques and materials are used. Otherwise, poor interface bonding may appear in cable assemblies over a extended period of time as a result of such environmental conditions as temperature-humidity cycling, vibration, flexing, or chemical corrosion. Whatever the reason for these leakage paths, the EMI that these high impedance interfaces generate can cause a cable assembly to be unacceptable in a digital communications environment. 
     The injection of a radio frequency into a cable during manufacture to test the strength of its shielding has been been previously accomplished by others such as apparatus shown in U.S. Pat. No. 3,839,672 issued to Anderson and U.S. Pat. No. 3,803,484 issued to Grey. The apparatus test single conductor shielded cable and not the multiconductor cables of an assembly terminated at each end by a connector. Thus, the art is deficient of a method and apparatus for testing the shield effectiveness of a cable assembly. 
     It would be highly advantageous to provide a device for testing such assemblies either in a production environment, for in-service testing of assemblies, or for design evaluation in the laboratory. The difficulty with providing such a testing apparatus include being able to measure the shielding effectiveness against a reference for different lengths of a cable assembly and for different connectors on the ends of a cable assembly. Further, there exists a problem of how to separate the measurement of the shielding effectiveness of the cable shield from the shielding effectiveness of the connector shields and their interfaces. 
     SUMMARY OF THE INVENTION 
     The invention provides a method and apparatus for evaluating the effectiveness of the shielding of a cable assembly. The effectiveness of a connector shield at either end of the cable assembly can be evaluated along with the effectiveness of the interfaces between the connector shields and the cable shield. 
     The apparatus includes a means for injecting one connector of a cable assembly with a radio frequency test signal while terminating the other end of the cable assembly; means for electrically isolating the injection means and the other end of the cable assembly from the injected connector; means for sensing a radio frequency leakage signal radiated on the surface of the cable assembly shield located between the isolation means; and means for comparing the leakage signal with a threshold and for generating a pass/fail signal indicating whether the leakage signal is in excess of the threshold. 
     In the illustrative embodiment the isolation is performed by a shielded adapter box having a connector mating with the injected connector at one end of the cable assembly thereby isolating the injection means from the connector and a test fixture having an toroidal shield for isolating the other end of the cable assembly from the injected connector. The adapter box is fed with a radio frequency test signal which transmits it through to the connector and between the connector and the isolation means on the other end of the cable assembly, is located a sensing means which detects RF leakage due to the defects in the shielding of the injected connector and its interface with the cable assembly shield. A similar arrangement allows the opposite end of the cable assembly to be tested for the effectiveness of its shield and its connector termination point. 
     A microprocessor based control selects which cable connector is injected and tested by the RF frequency. Further, the control provides for a selection from several frequencies for use in the injection and thereby several tests of a connector at the different frequencies. The testing of each cable connector termination point by several frequencies is equivalent to sweeping a frequency range containing the several test frequencies. Thus, an overall shielding characteristic can be developed over this range of frequencies. Advantageously, the several frequencies which cover the range are chosen such that common failure modes of the tested cable assemblies will be sure to fail at least one test frequency. 
     One of the more important advantages of a cable assembly testing apparatus constructed in this manner is the directivity and localization of the tested area. The arrangement of the sensors and isolation means creates a directive measurement device which can separate a connector shield evaluation at one end of the assembly from the effects produced by the cable shield and the other connector. This directive characteristic is also advantageous in eliminating the effects on a test calibration reference level if the cable assemblies are not of the same length. 
     Such an arrangement permits the shielding effectiveness at one end of the assembly to be tested against a reference developed for the particular type of connector terminating that end. Thus, the device contemplates using different reference levels for the type of connector terminating each end even if they are different from the other and for different reference levels for each of the test frequencies. 
     These and other objects, features and advantages of the invention will become more fully apparent and clearly understood from a reading of the following detailed description with reference to the accompanying drawings in which: 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a system block diagram of an apparatus for testing shielded cable assemblies constructed in accordance with the invention; 
     FIG. 2 is a perspective view, partially broken, of the test fixture apparatus and adapter box structure for the testing apparatus illustrated in FIG. 1; 
     FIG. 3 is a perspective view, partially disassembled, illustrating the test fixture apparatus for the testing system illustrated in FIG. 1; 
     FIG. 4 is a bottom perspective view, partially disassembled, of the test fixture apparatus for the testing apparatus illustrated in FIG. 1; 
     FIG. 5 is an enlarged perspective view of a current sensor used in the test fixture apparatus illustrated in FIGS. 1, 2, 3 and 4; 
     FIG. 6 is a pictorial representation of the front panel of the control unit for the testing apparatus illustrated in FIG. 1; 
     FIG. 7 is a detailed schematic diagram of the control unit for the testing apparatus illustrated in FIG. 1; 
     FIG. 8 is a detailed flow chart of the program stored within the microprocessor illustrated in FIG. 7; 
     FIG. 9 is a pictorial representation in tabular form of the commands producing selection of the test frequencies and test points for the output port shown in FIG. 7; 
     FIG. 10 is a detailed flow chart of the subroutine DBM which is called from the main routine illustrated in FIG. 8; 
     FIG. 11 is a detailed flow chart of the subroutine BLINK which is called by the main routine illustrated in FIG. 8; 
     FIG. 12 is a detailed flow chart of the subroutine TEST called by the main routine illustrated in FIG. 8; 
     FIG. 13 is detailed flow chart of the subroutine LEVEL called from the subroutine TEST illustrated in FIG. 12; 
     FIG. 14 is a pictorial representation of the register RO illustrating the pass/fail flags stored therein; 
     FIG. 15 is a detailed flow chart of the subroutine DISPLAY which is called by the subroutines DBM and LEVEL; and 
     FIG. 16 is a pictorial representation of the characteristic attenuation curves for a cable assembly. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows a system diagram of a shielded cable assembly test apparatus constructed in accordance with the invention. The apparatus includes generally a test fixture 10 and adapter boxes 12 and 14. Tested within the fixture 10 is a shielded cable assembly comprising a connector 11, a cable 13, and a connector 15. The cable 13 is a multiconductor shielded cable terminated on either end by the shielded connectors 11, 15. The shields of the connectors and cable are electrically coextensive and comprise one shield by their junction at several interfaces. The adapter boxes 12, 14 provide oppositely posed connectors into which connectors 11, 15 can be plugged. Further, the test apparatus comprises a sense circuit 16 for receiving RF leakage signals sensed by current sensors of the test fixture 10. The leakage signals are the result of injected RF frequencies from a source circuit 18 which provides a test signal for the cable assembly. The sense circuit 16 and source circuit 18 are controlled by a microprocessor based control unit 20 which directs the injected frequency into one end or the other of the cable assembly through cables 38, 40 and senses the leakage currents from the injected end of the assembly through cables 48, 50. 
     The source circuit 18 includes a plurality of RF frequency oscillators 22, 24 and 26 which can be connected selectively to a coaxial cable node 30 by means of a coaxial cable switch 28. The microprocessor based control unit 20 selects which RF oscillator output is connected to the node by generating control signals J1, J2 and J3 via signal line 32. If the J1 signal is generated then a 100 MHz injection frequency is coupled to the node 30, while if the J2 signal is generated a 250 MHz signal is coupled to the node 30. When the J3 signal is generated, the coaxial switch will connect the 400 MHz signal from oscillator 26 to the node 30. Thus, the control unit 20 can selectively couple any of the injection frequencies to the node 30 and thus sweep over the range of those frequencies for test purposes. It is readily evident that by this type of digital control that a sweep of more than three frequencies or a continuous sweep of a range of frequencies can be made available for test purposes. 
     The common coaxial output node 30 of the switch 28 is input to a balanced modulator 33. The balanced modulator 33 superimposes on the selected RF test frequency an amplitude modulation of approximately 17 KHz. The modulation is combined with the test frequency for the purpose of providing the sense circuit with a means to reject RF signals picked up by the sensors which are not due to the injection of the test frequencies. The 17 KHz frequency is not critical and other frequencies and even other types of modulation can be used to differentiate the test signals from other RF signals which may be present in the environment. The choice of the AM frequency should be such to make it unlikely that a similar AM modulation would be found from a common RF source, such as a carrier of a UHF broadcast station, in the test frequency range of 100-500 MHz. If the power levels received at the sense circuit are due only to the injected test frequencies then a much more precise comparison can be accomplished. Preferably, the balanced modulator can comprise a modulating amplifier commercially available from the Motorola Corp. of Schaumberg, Ill. as Model No. MHW 590. 
     The output of the balanced modulator 33 is switchable between two outputs A, B of a second coaxial switch 34 by means of control signals A, B generated over signal line 36 by the control unit 20. Output A is a coaxial coupler which carries the RF test signal through cable 38 to the adapter box 12. Output B is a coaxial coupler which transmits the RF test frequency through cable 40 to the adapter box 14. The test frequencies are transmitted through the adapter boxes and applied to the connectors of the cable assembly. When a test frequency has been selected by a control signal A, B, the other unconnected output is terminated with a nominal impedance, for example, 50 ohms, by switch 34. Terminating the unconnected outputs of switch 34 in the same impedance removes another source of error from the measurement of the leakage signal. 
     The control unit 20 by selectively generating the control signals A, B, J1, J2, and J3 can therefore control the direction of an injected test frequency either to connector 11 or connector 15, and the frequency thereof by selecting the particular RF oscillator source. The signals A, B therefore control the direction of the injected test frequency and the signals J1, J2, and J3 control the value of the source frequency selected. 
     Sense circuit 16 is comprised of a coaxial switch 42 which has two inputs A, B which are coupled to coaxial cables 48 and 50, respectively. The coaxial cables 48 and 50 carry RF leakage signals from current sensors as will be more fully explained hereinafter. Power values for the leakage signals in excess of a specified attenuation characteristic are the result of faulty cable connector shielding or interface connection shielding which has been sensed as a result of the injection of the source test frequencies. The coaxial cable 48 receives the leakage signal for the end of the cable assembly coupled to adapter box 12 and the coaxial cable 50 receives the leakage signal for the end of the cable assembly coupled to adapter box 14. 
     The inputs A, B of the coaxial switch 42 are switchable to a common output 43 which is coupled to a filter 47 and a logarithmic amplifier 44. The filter 47 selects those RF signals having the 17 KHz modulation thereon and then removes the modulation from the test frequency. The amplifier 44 is termed logarithmic because its gain varies as the log 10  of the voltage input thereby producing a conversion of the leakage signals into their power equivalents. The power level output from the logarithmic amplifier 44 is referenced to 1 milliwatt and is given in -dbmw. This signal is output as a DC voltage level because of an internal detection circuit which rectifies the described sensed RF leakage signals. A logarithmic amplifier having the capabilities is commercially available from RHG Electronics of Deerpark, N.Y., as Model No. ICLW 300 and has a frequency range of 100-500 MHz. The selection of which input is coupled to the amplifier 44 is provided by control signals A, B via signal line 52 from the control unit 20. The output of the amplifier 44, a power signal Pw, is received by the control unit 20 over signal line 54. Thus, the sense circuit 16 and control signals A, B provide a means for sensing the leakage current from at either connector side shielded cable assembly 11, 13, and 15. 
     With respect now to FIG. 2 the test fixture 10, the adapter boxes 12 and 14, and the coaxial transmission cables 38 and 40 will be more fully described. The test fixture 10 is actually two identical measurement devices mounted on either side of a common frame. Each measurement device evaluates one end or connector of the cable assembly and the excess of the cable passed between a slot 56 which physically separates the two devices. The test fixture 10 comprises an upper fixture piece 58 and a lower fixture piece 60 which are coupled together along one edge by a hinge 62. 
     Each of the fixture pieces 58, 60 has a channel 64 and 66, respectively, in which are mounted a plurality of ferrite toroids which have been split or halved. The split toroids mounted in the upper channel 64 are arranged into two groups 68 and 70, while the split toroids in the lower channel 66 are arranged into similar matching groups 72 and 74. When the upper piece 58 of the text fixture 10 is closed the oppositely opposed groupings of half toroids can be clamped around a cable of a cable assembly placed in the channel 66. The toroids when they are clamped together form full toroids which isolate the connectors 11, and 15 from the cable portion 13 of the cable assembly. 
     Additionally, the invention provides two groups of isolation toroids 76 and 78 mounted around the coaxial input cables 38 and 40 prior to their coupling to the adapter boxes 12 and 14. The isolation of the connectors from either direction is then ensured because any leakage currents moving along the shield of the input cables 38, 40 or along the cable portion 13 of the cable assembly itself will be attenuated by the lossy inductive coupling with the ferrite toroids. 
     The ferrite toroids on each end of the test fixture are diametrically split and mounted in the hinged frame so that the fixture clamps over the cable assembly under test. This feature permits the measurement to be nondestructive of the cable assembly and further conducive to a rapid insertion and removal of the tested assemblies. When the test fixture 10 closes, it also operates a limit switch 80 to generate a CLAMP signal via signal line 46 to the control unit 20. 
     As can be better seen in FIGS. 3, 4 and 5, the groups of split toroids are separated into two portions. A first portion, for example, 84 is for isolation of the connector of the cable assembly mounted on that side. A second portion 86 which is shown in an enlarged in FIG. 5 produces a sensing of the leakage signal. The coaxial cable 50 used for sensing the current has its end wrapped around three pick-up toroids forming the portion 86 which is physically separated from the group 84 in the channel 66 by a small space. The end of the cable 50 forms a pick-up structure by shorting the central conductor of the coaxial cable to its shielding at 88. This will produce a signal representative of the RF current flowing along the shield of the cable assembly at that point. The leakage signals detected by the system are the result of many contributing sources such as gaps or poor contact between mating pieces of the shield and signal attenuation through the shielded material. Whatever the source, the result is that standing waves are created on the surface of the shield. The currents developed as a result of the standing waves induce a field around the cable which excites the sensing toroids, for example 86, through inductive coupling. 
     Two leakage effects, local and global, are measured by the apparatus using the present structure. The local effects are defined as the RF signal picked up concentrically within the sensing toroids. The global effects are the result of any shield leakage occurring in proximity but not within the sensing toroids. Therefore, the leakage signals detected by the present apparatus are a composite of the global and local effects. The local effect is contributed by the small sections of the cable within the sensing toroids and the global effect is contributed by the portion of the cable and connector shield immediately adjacent the sensing toroids. To localize the global effect to the area of interest, i.e., the connector shield-cable shield interface and the connector shield, the isolation toroids 72, 74, 76, and 78 are used to attenuate spurious signals before they reach the sensing toroids. 
     Each sensing cable, for example the cable referenced 50, is mounted through a bore 90 which communicates to a channel 92 on the bottom of the lower fixture piece 60. Further isolation toroids 94 are provided for the sensing cable 50 before it couples into the coaxial switch 42. Likewise, on the opposite end of the fixture 10, sensing cable 48 has isolation toroids 96 slipped over cable 48. The opposite end of the fixture 10 is also provided with a current sensor 98 of similar construction as that discussed at 86. The sensor 98 is physically separated from isolation toroids 100 of group 72 by a small space. 
     Returning now for a moment to FIG. 2, the adapter boxes 12 and 14 are constructed to specifically mate with individual styles of multiconductor connectors. Each adapter box, for example 14, may be mounted on the test frame prior to the cable assembly test to match the particular manufacturing run of assemblies. It is evident that a cable assembly may have a different type of connector on either end and, thus, the adapter boxes will have a connector 102 which mates with the particular connector of the cable assembly under test. Within each adapter box all the signal conductors 104 of the connector 102 are bussed together and connected to the center conductor of a coaxial jack 106. The coaxial jack 106 mounts the coaxial coupler 108 of the test cable 40. The adapter box 12 is similarly constructed. This coupling permits the shield of the coaxial cable to be continuous with the adapter box and with the connector shield of the sample cable assembly. 
     It is crucial to preserve the shield continuity from the adapter box through the connector interface onto the connector shield. In many multiconductor connectors, such as the D subminiature type, insufficient contact surface area creates leakage through gaps, slots or just poor DC contact. The result is a high impedance leaky connection showing up as a substandard shielding even though the cable assembly shielding itself may be performing per specification. 
     The adapter boxes are constructed of copper or brass with all their outside seams soldered. On the front plate of each adapter box, for example adapter 12, a resilient RF gasket 110 is used to obtain optimum contact surface area, as well as consistent contact resistance with the connector of the cable assembly. Leakage due to the critical interface area at the adapter to connector coupling is thereby minimized. This insures that any signal detected by the current sensors is actually representative of the performance of the connector shield and not merely a poor coupling to the adapter boxes 12, 14. 
     Generally, a test on a cable assembly is accomplished by placing the cable within the channel 66 of the lower fixture piece 60 and then closing the upper fixture piece 58 over it. A display on the control unit 20 will thereafter indicate what the leakage measured by the sensor toroids is and provide an indication of whether the connector on one end or the other of the assembly is below specification. 
     To more fully understand the test method, reference is directed to FIG. 6 where the operator interface to the control unit 20, including several displays and input controls, is illustrated. The front panel of the control unit 20 includes five LEDs 200-208 which are used for indicating test points and test frequencies. For example, if LED 200 is lit, then the left side connector is being tested with the frequency indicated on LEDs 204, 206 and 208. Similarly, if the LED 202 is lit, then the right side connector is being tested at the frequency displayed by the LEDs 204, 206 and 208. The designation left and right side is relative and in this application will be used to indicate the side of the test fixture 10 that the operator faces as he operates the apparatus. Thus, the figures illustrate the apparatus in the same sense as the sides are designated. 
     Further, the front panel of the control unit has test lamps 210, 212, 214 and 216 which indicate the result of a cable assembly test. Lamps 210 and 214 are lit with a green light to indicate the passage of a test by the left side connector and the right side connector, respectively. Lamps 212 and 216 are lit with a red light to indicate a failure of the test by the left side connector and right side connector, respectively. Additionally, if a switch 218 is in the on position, then a horn 220 will be sounded if either the left connector or right connector has failed a test. The failure of a test at any one of the frequencies causes a failure light. For a pass light to be lit, all of the test frequencies must be attenuated sufficiently. 
     A pair of digital thumb-wheel switches 222 are used to input a ones digit and a tens digit for indicating a reference level for each of the tests. Test reference levels for each of the frequencies 100 MHz, 250 MHz and 400 MHz for both the left and the right side connectors are entered on these switches. An enter button 224 is used to enter the reference levels when the LEDs 200-208 are lit indicating a particular test point. Further, the front panel of the control unit 20 includes a run/step switch 226 which may be positioned to automatically run all six tests sequentially with just the combination of the results of all tests being shown in the pass/fail lights or in a step mode where each test is run separately and the results displayed individually on the lamps and as power levels on the display 228. The program is stepped through sequentially by hitting the enter button 224 when the apparatus is in the step mode. Additionally, the two digits of the 7 segment LED display 228 are used to output the power levels of the reference input levels and the power levels of the sensed leakage current in db. 
     An electrical schematic of the control unit 20 will now be more fully described with respect to FIG. 7. The control unit 20 is based on a microprocessor 230 which has a stored program executing within. The microprocessor 230 inputs all the needed data and outputs all needed control signals to accomplish the functions set forth herein. In connection with these operations, the microprocessor 230 receives inputs from the operator controls to develop the commands and modes for operating the apparatus. The T0 input is normally tied to a positive voltage +V through a pull-up resistor 232. The enter signal is generated at the T0 input by grounding the end of the resistor 232 with an enter switch 224. Similarly, the software accessible pin T1 is generally at a high logic level because it is tied to a source of positive voltage +V through pull-up resistor 234. The run/step signal is generated by grounding input T1 with a switch 226. A closed switch 226 is indicative of a step mode and an open switch 226 is indicative of an automatic mode. Likewise, the interrupt terminal INT is generally at a high level by being pulled up by resistor 236 connected to a source of positive voltage +V. An interrupt signal can be generated to the terminal INT by grounding the end of the resistor 236 through the clamp switch 46. The closure of the clamp switch 46 indicates that the upper fixture piece 58 has been closed onto the lower fixture piece 60. 
     Further input to the microprocessor 230 is provided by the digital switches 222. The ones digit of the switches may be set by the operator and thereafter input to the microprocessor 230 by reading the port 1 pins P10-P13 with the software. In a similar manner, the tens digit can be set by the operator and thereafter input to the microprocessor 230 by reading the port 1 pins P14-P17. 
     From these inputs, the microprocessor 230 executes its stored program and provides control signals through outputs on its data bus D0-D7, port pins P20-P23, and the read control line RD. Control of the display 228 is provided by a latch 238 which has its latch enable input LE connected to pin P20 of the microprocessor 230. The data inputs of the latch 238 are connected to the data bus D0-D7. Outputs of the latch 238 are used in four bit groups to drive the 7-segment displays 242 and 246 through driver chips 240 and 244, respectively. The Q0-Q3 outputs of latch 238 are decoded as the A-D inputs of the driver 240 to produce signals on the a-g outputs forming the numbers in the display 242. Likewise, the Q4-Q7 outputs of the latch 238 drive the tens digit 246 of the display 228. The microprocessor 230, therefore, displays a number in the 7 segment displays 242 and 246 by outputting a data byte on the data bus and enabling the latch 238 to input that data byte with the pin P20 control line. 
     The select inputs J1, J2 and J3 of the coaxial switch 34 and the LEDs 200-208 are controlled in a similar manner. The select inputs J1, J2 and J3 are output from the outputs Q0-Q2 of a latch 248 and the LEDs 200-208 are lighted in response to low logic levels on the outputs Q3-Q7 of the latch. The output levels Q0-Q7 of latch 248 are set by storing a data byte from the data bus D0-D7 of the microprocessor 230 in response to a latch enable signal from the port 2 pin P21. The microprocessor 230 thereby selects the particular frequency desired and indicates the test points by outputting different data bytes to the latch 248. 
     The selected direction switches 34 and 42, the pass/fail lamps 210-216, and the buzzer 220 are controlled in a similar manner. A latch 250 receives data bytes from the data bus of the microprocessor 230 and latches them onto its outputs Q0-Q7 in response to a latch enable signal from port 2 pin P22. This latched output data is buffered by a line driver 252 before being output at a higher voltage level to become the A, B source and sense selection signals, respectively, on outputs A0-A3. The pass/fail lamps 210-216 are commonly connected to ground at one terminal and at the other terminal to the outputs A4-A7 of the line driver 252. Thus, the line driver 252 is driven by the latch 250 to select the direction of the test and to indicate whether a certain connector on one side has passed or failed a test reference level. Further, the horn 220 is connected to the outputs A5-A7 of the line driver 252. These levels are combined in diodes 254 and 256 forming an OR gate for buzzer 220. The buzzer can be disconnected from the system by opening the switch 218. 
     The microprocessor 230 further controls an A/D converter 258 to provide a data byte on the data bus D0-D7 indicative of the power level of the sensed leakage signal. The A/D converter 258 is enabled for conversion by outputting a low logic level on port 2, pin P23, which is communicated to the chip select *CS input of the converter. Thereafter, a conversion may be initiated by lowering the read output RD of the microprocessor 230 which enables the WR input of the converter 250. The signal input to the converter Vin (+) is the buffered and scaled output of the logarithmic amplifier 44. Resistor 272 forms a termination impedance for the logarithmic amplifier. This analog signal, which is representative of the leakage power, is converted to a digital number by the A/D converter 258 and can be input to the microprocessor 230 by strobing the read input RD of the converter. When the read input RD is strobed, the A/D converter 258 will output a data byte onto the data bus for receipt by the microprocessor 230. 
     The amplifier 49 is comprised of an operational amplifier 270 which is configured as a noninverting scaling amplifier having gain resistors 262 and 260 connected between ground in the output of the amplifier. The junction of the resistors 260 and 262 is connected to the inverting input of the operational amplifier 270. The gain characteristic of the amplifier 49 is such that the detected power level from logarithmic amplifier 44 is scaled for correct A/D conversion. A low pass filter comprising a resistor 264 and a capacitor 266 is inserted between the amplifier output and A/D input to attenuate any noise on the DC power level to be converted. Diodes 267, 268 clamp the input voltage of the A/D converter to a safe level 0 V-5 V. Preferably, the gain of the amplifier 49 is adjusted by resistor 262 so that a one milliwatt signal will correspond to a Odbmw output from the sense circuit. In this manner, the smallest measured signal will be -72 dbmw in steps of -1/2 dbmw when the digital signal from converter 258 is zero. 
     FIGS. 7 and 8 will now be referenced to more fully describe the operation of the microprocessor 230 during a test. FIG. 8 is a detailed flow chart of the program stored within the microprocessor 230 and controls the peripheral devices for input and output of the parameters and control signals needed to operate the system. The program begins in block A10 where the microprocessor 230 resets the input and output ports. Port 1 and port 2 are the ports used on the microprocessor 230 and are initialized by this block. Next, the microprocessor 230 in block A12 turns on the 7-segment display 228, turns on the LEDs 200-208 in block A14, and turns on the lamps 210-216 in block A16. These operations are performed by outputting the requisite data bytes to the latches 238, 248 and 250, respectively. The lamps, displays and LEDs are turned on as a test to insure that all are operable at the beginning of a test sequence. 
     After all the displays have been lighted, the program waits at block A18 until the operator presses the enter button. This is an indication to the program to continue and in blocks A20, A22 and A24 the 7-segment display, the LEDs and the lamps are turned off, respectively. Thereafter, the program delays one second in block A26 to provide a separation of the program parts and to allow the operator response time. Next, in block A28, the address of the first test point, the left side connector at the frequency of 100 MHz is stored in the accumulator. Thereafter, the subroutine DBM is called in block A30. The subroutine DBM, as will be more fully explained hereinafter, lights the particular test point whose address is in the accumulator and, thus, requests the operator to input a reference level through the digital switches 228 against which the leakage signal can be tested. 
     Once the operator has set the digital switches 228 to the desired reference level, he will press the enter button 224 and the subroutine DBM will store the switch settings into memory. The subroutine DBM returns to the main program after it stores the reference level into register R2. The next sequence of program steps, from blocks A32-A50, are the entry of the next five reference levels. The address of the left side connector and the 250 MHz LED is stored in the accumulator in block A32 and the subroutine DBM again called in block A34. The entered reference level for this access is stored in register R3. Similarly, the reference level for the left side connector at 400 MHz is stored in register R4 by blocks A36 and A38. The reference level for the right side connector at 100 MHz is stored in register R5 by blocks A40 and A42. The reference level for the right side connector at 250 MHz is stored in register R6 by blocks A44 and A46. The reference level for the right side connector at 400 MHz is stored in register R7 by blocks A48 and A50. It is noted that this operation provides a reference level for each connector at each frequency used. 
     After entry of the reference levels, the programs begins a main testing loop. The main testing loop begins at block A52 where the microprocessor 232 will test for an interrupt. If an interrupt is found, it continues to block A56, while if an interrupt is not present, then control is transferred to block A54. In block A54, the microprocessor 230 will blink the db display 228. The interrupt is provided to the microprocessor by the CLAMP signal which indicates that the upper fixture piece is closed on the cable and the test should begin. This is the automatic test initiation signal and must be present before the operation of the apparatus can proceed. Therefore, if the operator has forgotten to close the test fixture, the db display 228 blinks as a reminder. 
     When the fixture is closed, the next block A56 clears the step flag and then in block A58 tests to determine whether the step switch 226 is closed. If the step switch is not closed, then the apparatus is in automatic mode and the program continues immediately to block A62. However, if the step switch is closed, then block A60 is executed before control is transferred to block A62 and the step flag is set to indicate that this is a manual test. 
     Next, in block A62, the operational testing of the cable assembly is accomplished by the subroutine TEST. This subroutine steps through six tests where three are provided at the different frequencies of 100 MHz, 250 MHz, and 400 MHz for each connector side. The test routine also will provide operation of the pass/fail lights and the horn 220. 
     Upon return from the test routine, the program enters an infinite loop in block A64 while testing for an interrupt. If the interrupt is present, it will continually loop through the decision block A64, until it finds the interrupt is terminated. This is an indication to terminate a test and the operator must open the test fixture 10 and the limit switch 46. Once the switch 46 is open, the interrupt is removed from the microprocessor 230 and the program will sequence to block A66. In that step, the program turns off the pass/fail lights and proceeds to the beginning of the test procedure. 
     Thus, in an automatic mode, many cable assemblies can be rapidly tested by mounting the cable assembly in the test fixture and merely closing the upper fixture piece. Faulty cable assemblies may be discarded upon an audible indication of failure from the horn or a visual indication from the pass/fail lights. The operator merely has to open the test fixture and discard the failed cable assembly and reinsert the next cable assembly for another test. This provides an advantageous automatic mode of operation which generates a great facility and throughput for a production run of cable assemblies. 
     The subroutine DBM which allows entry of the reference levels will now be more fully explained, if attention will be directed to FIG. 10. The subroutine begins in block A68 where the test point LED whose address is in the accumulator is lighted to indicate which test point for which the reference level should be input. FIG. 9 illustrates a table of the port 21 commands in hexadecimal and binary illustrating those commands which light the test point LEDs. The hex commands D0, B0, 70, C8, A8, and 68 are used to select the test points one-by-one as the DBM subroutine is called in the main loop. After the particular test point is lit, the program enters a waiting loop in block A70 until the operator hits the enter button. This allows him to recognize the lighted LED and go to a chart or other reference documents where he has a reference level written down. He will then input this reference level to the digital switches and thereafter press the enter button to sequence the program to block A72. 
     The input switches are read through the port 1 pins P10-P17 in block A72 and the lower four bits are masked off by anding the accumulator with hexadecimal F0 in block A74. In block A76 the upper and lower nibbles are swapped in the accumulator and the result is multiplied by ten in block A78. This converts the tens digit of the switch input to binary and the result is saved in an intermediate storage location. Next, the ones switch byte is input in block A80 and the higher four bits masked off of the byte by logically anding the accumulator with hexadecimal OF. The ones digit and tens digit are then combined in block A84 to provide a binary representation of the reference level which can be used in further calculations in the microprocessor. 
     Next, the reference level is checked to determine whether it is less than -7 dbmw in block A86. If it is, and the operator has input an invalid reference level, and in block A88 the variable db is set equal to 72. Next, the reference level is subtracted from 72 in block A90 to give an indication of the relative reference measured by the apparatus. In block A92 the value is then multiplied by two and stored in register R0 in block A94. The value is then displayed in block A96 which provides an echo of the input to insure that the operator has entered the right reference level. The system displays the reference level for one second by delaying that amount of time in block A98. Thereafter, in block A100 the display is blanked and the reference level loaded back into the accumulator in block A102 before the program exits back to the main routine for the next reference level entry. 
     The subroutine BLINK is shown in FIG. 11 and is an input/output routine used to turn off and turn on the display alternately between delays of 250 milliseconds. Blocks A104 and A108 turn the display on and turn the display off, respectively, and blocks A106 and A110 delay program execution 250 milliseconds. 
     The subroutine TEST will now be more fully explained, if reference will be directed to FIG. 12. In block A150, the program delays one second after its entry and then clears register R0 in block A152. Register R0 will be used as a intermediate storage location for an indicator of the pass/fail test and, thus, is initialized in this step. Next, in block A154 the left source output from coaxial switch 34 is commanded. The left input to the coaxial switch 42 for the sense circuit 16 is selected in block A156 thereafter. These selections are made by outputting the correct data byte to the latch 250 which provides output signals A on the source and sense control lines. In block A158, the flag F1 is cleared to indicate that this part of the control routine is testing the left side connector. 
     The next sequence of operations in blocks A160-A200 are the actual tests for the leakage signals for each connector at the three different frequencies and compared against the stored reference levels. Block A160 produces the hexadecimal output D1 to port 21 which loads the latch 248 With that value. From the table in FIG. 9, it is seen that a hexadecimal value of D1 will select the J1 output and light the diode for the left connector side and the 100 MHz test frequency. The J1 selection signal causes the coaxial switch 28 to select the RF oscillator 22 which injects the 100 MHz signal into the connector on the left side of the test fixture. Next, in block A162, the reference level that has previously been stored by the DBM subroutine in register R2 is loaded into the accumulator. Thereafter, the subroutine LEVEL is called in block A164 to compare that reference level to the input from the logarithmic amplifier. As indicated previously, the pass/fail indication for this test is stored in register R0 for output at a later time if the apparatus is in an automatic mode or will be display immediately, if the apparatus is in a manual or step mode. 
     Thereafter, in blocks A166, A168 and Block A170, the 250 MHz test is performed for the left connector side. Block A166 outputs the hexadecimal value B2 to port 21 thereby selecting with the J2 signal the oscillator 24 and lighting the left side connector LED 200 and the 250 MHz LED 206. The reference level for this test, stored in R3, is placed in the accumulator in block A168 before the subroutine LEVEL is called in block A170. Blocks A172-A176 perform the 400 MHz test for the left side connector in a similar manner. 
     This completes the three tests for the left connector side and leaves the three tests for the right connector side yet to be performed. Therefore, in block A178 and A180 the right source output and right sense input for the coaxial switches 34 and 42 are selected. The selection takes place in the same manner as the left source and sense selection did by setting the signals A on the output of the latch 238. 
     Thereafter, the flag F1 is set in block A182 to provide an indication to the microprocessor 230 that the right side connector is being tested. In blocks A184-A188 the 100 MHz test for the right side connector is accomplished in the same manner as the three previous tests for the left side connector. The hexadecimal output command C9 from block A184 selects the J1 output on the coaxial cable switch 28 and lights the right side connector LED 202 and 100 MHz LED 204. The reference level for the right side connector at 100 MHz is loaded into the accumulator from its intermediate storage in register R5 in block A186 and the subroutine LEVEL is called in block A188. Blocks A190-A194 and blocks A196-A200 perform a similar task for the right side connector for the frequencies of 250 MHz and 400 MHz, respectively. 
     After all the tests have been accomplished the LEDs 200-208 at port 21 are blanked in block A202. Thereafter, in block A204, the register R0 which contains the accumulation of whether either the left or right side connector failed any of the frequency tests used to turn on the pass/fail lamps 210-212. At this time, if switch 218 is closed, the horn will also sound if either lamp 212 or lamp 216 is lit thereby providing an audible backup for the visual indication of a failure of either one or both connectors of the cable assembly. The program then continues in block A206 by shutting the display off and then testing the step flag to determine whether the apparatus is operating in a manual or automatic mode. If the apparatus is in an automatic mode, then the TEST subroutine is done and the program exits. On the other hand, if the step mode flag is present, then control is transferred to block A210 where the program loops waiting for the enter button to be pressed. After the enter button has been pressed, the program will turn off the pass/fail lights in block 212 before exiting. 
     FIG. 13 will now be more fully described to illustrate the operation of the subroutine LEVEL. The program is used for comparing input leakage signal for a particular test to one of the stored reference levels. In block A112 the program begins by storing the pass/fail level that was transferred in the accumulator when the subroutine was called. The program then delays 100 milliseconds in block A114 before starting the A/D convertor in block A116. The A/D convertor is allowed to settle by delaying one millisecond in block A110. Thereafter, the result from the A/D conversion is input over the data bus in block A120. As mentioned before, the starting of the A/D conversion and the input of the converted byte is provided by producing a low level chip select signal CS on pin P23 of the microprocessor and strobing the RD output of the microprocessor 230. The result of the A/D conversion then has the reference level subtracted from it in block A122. The sign of the result is tested in block A124 to determine whether the particular connector has passed at the tested frequency. If the leakage signal level is greater than the reference level, then a path indicating a failure is taken to block A134. However, if the test is passed, then the sequence is to block A126. 
     The accumulator has stored in it the A/D result before calling the subroutine DISPLAY to output that value to the 7 segment display 228. Next, the step flag is tested in block A130 to determine whether it is a manual or automatic mode. If the step flag is present, the system waits in block A132 until the operator presses the enter button and then exits. 
     On a failure, in block A134, the left/right side flag F1 is tested to determine which connector has failed the test. If F1 is present, then the right side connector has failed and in block A136 an indicator of that failure is stored in register RO. If, however, the flag Fl is not present, then in block A138 an indication that the left side connector has failed is inserted into register RO. These failure indications are combined in block A140 with previous failure indications to store an overall status word in register RO. The status word is shown in pictorial form in FIG. 14. Thereafter, the program sequences to the completion blocks of the routine A126-A130 where the failure value is displayed in the 7 segment display before exiting for the next test routine. 
     The subroutine DISPLAY will now be more fully explained with reference to the detailed flow chart in FIG. 15. Initially, the A/D value is divided by two in block A214 because of the multiplication of that in the input routine which doubled the value. Next, this value is subtracted from the 72 db and the result is applied to the accumulator in block A216. This result is complemented in block A218 and its sign tested in block A220. If the result is less than zero, then the accumulator is set to zero in block A22. Otherwise, the program continues immediately to block A224 where the accumulator is again complemented. 
     The sequence from block A218 to block A224 is a test for a negative result of the subtraction. If the result is negative, then the db level is set equal to zero in block A222. After this test has been made, the input value is converted from the binary number system to a BCD representation in block A226 before being output to the 7 segment display in block A228. The output to the display is accomplished by writing the accumulator to the latch 238. The display routine then returns to the calling routine. 
     The method of using this apparatus to test a cable assembly will now be more fully described with respect to FIG. 16. In that figure there is shown a number of reference levels A, B, and C. These reference levels indicate in -dbM the amount of attenuation which should be produced by the connector shielding if it is to meet specification. The reference levels define a test curve 400 which is a sweep of all frequencies from 100 MHz to 500 MHz. The test frequencies at which the reference levels are chosen are situated such that common failure modes of the type of cable assemblies tested will be sure to exceed at least one reference level. 
     For example, curve 402 is characteristic of a cable assembly with a broken interface between the cable shield and the connector shield while curve 404 is characteristic of a poorly constructed connector shield, perhaps with the shield tape unwrapped. Thus, it is seen that if reference levels A, B, C are chosen at 100 MHz, 250 MHz, and 400 MHz that characteristics 402 and 404 will fail at least one reference level. Thus, because of the relatively well behaved characteristics of the cable assemblies in their failure modes, the entire test frequency range does not have to be scanned but merely simulated by a small preselected number of frequencies thereby saving considerable cost over a system which sweeps all the frequencies of a range. 
     The reference levels, after the frequencies have been chosen, are selected by first testing the leakage signals from an unshielded cable assembly in the test apparatus. The result is then added to the levels of attenuation required by the specification for the assembly tested. The test apparatus advantageously measures the unshielded levels in the manual mode of operation as previously described by mounting the unshielded cable in the test fixture 10 and stepping through the test frequencies by hitting the enter button 224. The power levels developed from the unshielded cable are read from the dbM level display 228 and recorded. The nominal power level output from the three RF oscillators 22, 24 and 26 is -10 dbmw and is approximately the level which will be recorded for an unshielded cable assembly. 
     The attenuation specification for a typical cable assembly of the type under test is then examined to determine the attenuation needed at each test frequency. These amounts are added to the measured levels for the unshielded cable assembly to yield the reference levels. Once the reference levels have been developed, the operator causes the apparatus to revert back to automatic mode where the reference levels are input and the automated test performed for a large manufacturing run of cables. 
     While a preferred embodiment of the invention has been illustrated, it will be obvious to those skilled in the art that various modifications and changes may be made thereto without departing from the spirit and scope of the invention as defined in the appended claims. ##SPC1##