Semiconductor memory device having sense amplifiers with different driving abilities
BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device (memory device) whose respective pair of bit lines is divided into a plurality of blocks each comprising memory cells, a sense amplifier, and switching elements. 
     Recently, memory devices have a great deal of memory capacity, so that the amount of memory cells in a device tremendously increases with a lot of word lines and bit lines connected to the memory cells. Accordingly, the stray capacitance distributed along the word and bit lines increases, which lowers the operation speed of the memory device. This problem with the bit line (usually a pair of bit lines) has been improved by dividing the pair of bit lines into a plurality of blocks. One improvement has been disclosed in Japanese Laid-open Patent Application No. 59-101093 in 1984. One difference between the present invention and the Laid-open Patent Application is that the driving ability of the sense amplifier in respective blocks is changed in the present invention. On the otherhand, in the Laid-open Patent, all the sense amplifiers have an equal driving ability. 
     FIG. 1 is a block and circuit diagram of a part of a usual memory device. Memory cells in the usual memory device, having the memory capacity of 64 kilo (K) bits or 256 K bits are arranged in a matrix as shown in FIG. 1, in which reference symbols C 00 , C 01 , - - - , and C 0n  are memory cells in a 0-th column; C 10 , C 11 , - - - , C 1n  are memory cells in a 1-st column; C i0 , C i1 , - - - , and C in  are memory cells in an i-th column; and C n0 , C n1 , - - - , and C nn  are memory cells in an n-th column. Each memory cell is positioned at each cross point of a respective word line and a pair of bit lines where reference symbols WD 0 , WD 1 , - - - , and WD n  are the 0-th, the 1-st, - - - , and the n-th word line respectively, and BL 0 , BL 0  ; BL 1 , BL 1  ; - - - ; BL i , BL i  ; - - - ; BL n  , BL n  are the 0-th, the 1-st, - - - , the i-th, - - - , and the n-th pair of bit lines respectively. Each pair of bit lines has a respective column decoder where a reference symbol CD i , shown in FIG. 1, is a column decoder for the i-th pair of bit lines. Similarly, each word line has a respective word decoder where a reference symbol WD i , in FIG. 1, is a word decoder for the i-th word line. When the memory device is in a read mode and word line select signals X 0 , X 1 , - - - , and X n  and column select signals Y 0 , Y 1 , - - - , and Y n  are applied to the word and the column decoders, a designated memory cell is selected and a data signal stored in the designated memory cell is read out. For example, when word decoder WD i  and column decoder CD i  function together by the word line and column select signals X i  and Y i  respectively, the data signal stored in memory cell C ii  is read out and column decoder CD i  functions for sending the read out data signal to a pair of data bus DB, DB. The read out data signal sent to the data bus DB, DB is amplified by a sense amplifier SA placed in data bus DB and DB. 
     However, when the memory capacity of the memory device increases as much as mega (M) bits, the number of memory cells also increases, and the stray capacitance distributed along each pair of bit lines also increases when compared with the memory capacitance provided in each memory cell. Thus, the operation speed of the memory device for writing or reading a data signal into or out from the memory cell is lowered and it becomes difficult to obtained a good signal to noise ratio. This causes a reduction in the operational reliability of the memory device. To obliterate the problem, the technique of dividing each pair of bit lines into a plurality of blocks has been developed. FIG. 2 shows a case of dividing the i-th pair of bit lines BL i , BL i  into k blocks like BK i0 , BK i1 , - - - , and BK ik . In FIG. 2, each block comprises a pair of divided bit lines, a plurality of parted memory cells, a block sense amplifier, and a pair of switching elements. For example, block BK ik  has a pair of divided bit lines BL ik , BL  ik , a plurality of parted memory cells C ik0 , C ik1 , - - - , and C ikm , a block sense amplifier SA ik , and a pair of switching elements S ik , S ik , where, the number &#34;m&#34; is set so that the number &#34;n&#34; shown in FIG. 1 is equal to &#34;k&#34; times as many as &#34;m&#34;. 
     In FIG. 2, when one of the parted memory cells is selected by one of the word select signals X 0  ˜X n  (see FIG. 1), one of the block select signals BS i0 , BS i1 , - - - , and BS ik  is designated, and the designated block select signal activates a block sense amplifier in the selected block. Then, the selected block sense amplifier amplifies a data signal stored in the selected memory cell. Pairs of switching elements S i0 , Si0; S i1 , S i1  ; - - - ; and S ik , S ik  are inserted in the pairs of bit lines in the blocks respectively for connecting the blocks in series. Column decoder CD i  is inserted between a block (BK ik ), which is nearest to the pair of bus lines DB, DB, and the pair of bus lines DB, DB. When column select signal Y i  designates the i-th column, transfer gates Q 1  and Q 2 , provided in column decoder CD i , turn ON for sending the data signal, which is amplified by the selected block sense amplifier, to the pair of bus lines DB, DB. 
     Further detail of circuits in the block and its operation will be explained with reference to FIG. 3 when the memory device is in the read mode. 
     FIG. 3(a) is a bit line pre-charge circuit provided in respective block, while FIGS. 3(b) and 3(c) are the switching elements either one of which is provided in the respective block. FIGS. 3(a), 3(b), and 3(c) show a block BK i0 . FIG. 3(a) shows a pre-charge circuit PRE i0  which comprises transistors Q i01 , Q i02 , and Q i03  for applying equally pre-charging potential (V cc  -V th ) onto pair of bit lines BL i0 , BL i0  when a pre-charge signal p is applied to the gates of transistors Q i01 , Q i02 , and Q i03 . A transistor Q i04  shown in FIG. 3(b) is for switching element S i0  or Si0 shown in FIG. 2. The transistor Q i04  turns ON when a clock signal φ is applied to its gate. FIG. 3(c) also shows another type of the switching element which consists of a transistor Q i04 , which is the same as the one in FIG. 3(b), and a transistor Q i05 , which is connected in parallel to the transistor Q i04 . Transistor Q i05  is a reverse conduction type transistor when compared to transistor Q i04 . The switching element turns ON when clock signals φ, φ are simultaneously applied to the gates of transistors Q i04  and Q i05  respectively. 
     The circuit of FIG. 2 sequentially operates in following steps: (1) one word line is selected by a word line select signal X 0 , X 1 , - - - , or X n  (see FIG. 1); for example, a word line WL 0  is selected by word line select signal X 0  ; (2) one column is selected by a column select signal Y 0 , Y 1 , - - - , or Y n  ; for example, column i is selected by column select signal Y i  ; (3) a memory cell located at a cross point of the selected word line and column is selected; for example, memory cell C i00  in block BK i0  is selected; (4) one block select signal is provided when a word line and a column are selected; for example, block select signal BS i0  is selected; (5) one block sense amplifier is activated by the block select signal, so that a voltage difference appearing between bit lines in the selected block is amplified; for example, block sense amplifier SA i0  is activated by block select signal BS i0 , so that a voltage difference appearing between bit lines BL i0 , BL i0  is amplified; (6) after the voltage difference is amplified by the selected block sense amplifier, all switching elements in the selected column are turned ON so that all blocks of the selected column are connected in series; for example, after the voltage difference appearing between bit lines BL i0 , BL i0  is amplified by block sense amplifier SA i0 , all switching elements S i0 , S i0  ; S i1 , S i1  ; - - - ; and S ik , S ik  are turned ON so that all blocks BK i0 , BK i1 , - - - , and BK ik  are connected in series; and (7 ) the transfer gates in a column decoder belonging to the selected column are turned ON by a column select signal for feeding the amplified data signal onto data bus DB, DB; for example, transfer gates Q i1 , Q i1  in column decoder CD i  are turned ON by column select signal Y i  for feeding the amplified data signal onto data bus DB, DB. 
     In the above explanation (6), &#34;all switching elements&#34; are not always turned ON, but at least the switching elements in the selected block and in the blocks locating between the selected block and column decoder CD i  are turned ON. 
     In addition, in the prior art, all other block sense amplifiers can be activated after the selected block sense amplifier has been activated and the switching elements have been turned ON. 
     As explained above, in the prior art, the load capacitance for the sense amplifier can be kept small the first time the block sense amplifier in the selected block is activated. However, when the blocks locating between the selected block and column decoder CD i  are connected to the data bus, the load capacitance for the selected block sense amplifier increases. For example in FIG. 2, when block BK i0  is selected and sense amplifier SA i0  is activated and the switching elements connect the all blocks, the load capacitance becomes a total sum of capacitance along the bit lines in column i. Accordingly, the sense amplifier in the farthest block from the data bus, for example sense amplifier SA i0  in block BK i0 , must have a great enough driving ability to amplify the voltage difference in a short enough time. Furthermore, each sense amplifier has an equal driving ability, so if a sense amplifier in the nearest block from the data bus, for example sense amplifier SA ik  in block BK ik , is selected, the sense amplifier (SA ik ) wastes too much power, which has been a problem in the prior art. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to increase the operation speed of a semiconductor memory device. 
     Another object of the present invention is to decrease the power consumption of the semiconductor memory devise. 
     Yet another object of the present invention is to increase the operational reliability of the semiconductor memory device. 
     The above objects are achieved by changing the driving ability of the block sense amplifier in respective blocks so that the driving ability increases as the block is located farther from the data bus while the driving ability decreases as the block is located closer to the data bus. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block and circuit diagram of a prior art memory device whose column part is not divided into blocks; 
     FIG. 2 is a block and circuit diagram of a column part in the prior art memory device; 
     FIG. 3(a) is a circuit diagram of a conventional pre-charge circuit used in a divided block of the column part in the memory device of the prior art or the present invention; 
     FIG. 3(b) is a circuit diagram of a conventional switching element used in a block of the column part in the memory device of the prior art or the present invention; 
     FIG. 3(c) is a circuit diagram of another conventional switching element used in a block of the column part in the memory device of the prior art or the present invention; 
     FIG. 4 is a block and circuit diagram of a column part in a memory device embodying the present invention; 
     FIG. 5 is a circuit diagram of a modified clock signal generator embodying the present invention; 
     FIG. 6 is a circuit diagram of a block sense amplifier embodying the present invention; 
     FIG. 7(a) is a plan view of the pattern of a block sense amplifier embodying the present invention in a block located farthest from the data bus of the semiconductor memory device embodying the present invention; 
     FIG. 7(b) is a plan view of the pattern of a block sense amplifier embodying the present invention in a block located nearest to the data bus of the semiconductor memory device embodying the present invention; and 
     FIG. 8 is a time chart for illustrating the operation of the memory device embodying the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 4 is a block and circuit diagram of a part of the memory device embodying the present invention. The block and circuit diagram in FIG. 4 has the same configuration of the prior art shown in FIG. 2, and in FIG. 4, those parts having the same symbol as those in FIG. 2 function equivalent to those in FIG. 2. Symbols VSA i0 , VSA i1 , - - - , VSA ik  are the block sense amplifiers similar to the block sense amplifiers in FIG. 2 but their driving ability are individually different so that a block sense amplifier located farthest from column decoder CD i  or data bus DB, DB has the maximum driving ability and a block sense amplifier located nearest to data bus DB, DB has the minimum driving ability. 
     In FIG. 4, for example, when a data signal stored in memory cell C i10  located in the i-th column and block BK i1   is read out, the memory device functions as follows: (1) the i-th column is selected when column select signal Y i  is applied to column decoder CD i  (see FIG. 1); (2) a word line WL m+1  relating to memory cell C i10  is selected and block select signal BS i1  is provided, so that sense amplifier VSA i1  is activated by block select signal BS i1 , then a voltage difference appearing between bit lines BL i1 , BL i1  due to the data signal stored in memory cell C i10  is amplified; and (3) switching elements S i1 , S i1  ; S i2 , S i2  ; - - - , and S ik , S ik  in the selected block BK i1  and blocks BK i2 , Bk i3 , - - - , and BK ik  located between the selected block BK i1  and column decoder CD i  are turned ON for connecting bit lines BL i1 , BL i1  to data bus DB, DB through column decoder CD i . (Switching elements S ik , S ik  in the nearest block BK ik  to the data bus can be omitted because they are always used.) The above control for the switching elements are made by modified clock signals which are generated in a modified clock signal generator shown in FIG. 5. 
     The modified clock signal generator shown in FIG. 5 generates modified clock signals φ 0 , φ 1 , - - - , and φ k  for controlling switching elements S i0 , S i0  ; S i1 , S i1 , - - - ; and S ik , S ik  ON or OFF respectively. The modified clock signals are similar to clock signal φ shown in FIGS. 3(a) and (b), however, they control the switching elements as follows: all of the modified clock signals are required only when the farthest block (block BK i0 ) from data bus DB, DB is selected. When a block nearer than block BK i0  to the data bus is selected, modified clock signals, for blocks located farther from the data bus than the selected block, become unnecessary. For example, when block BK i1  is selected, it is not necessary to generate a modified clock signal φ 0  for switching elements S i0 , S i0  in block BK i0 , and when block BK ik  is selected, only clock signal φ k  is necessary. The above selection of the modified clock signals is made in the modified clock signal generator by properly combining the block select signals BS i0 , BS i1 , - - - , and BS ik . In FIG. 5, OR gates OG 1 , OG 2 , - - - , and OG k  create the above logic, and AND gates AG 0 , AG 1 , - - - , and AG k  produce the modified clock signals every time when clock signal φ is applied to the AND gates. 
     Thus, applying the modified clock signal generator to the memory device, the bit lines in the selected block and the blocks located between the selected block and the data bus can be connected. Accordingly, the load capacitance of the activated sense amplifier can be reduced as small as possible. For example, when block BK i1  is selected, the stray capacitance appearing along bit lines BL i0 , BL i0  cannot influence sense amplifier SA i0 . 
     Since upper blocks, meaning the blocks located farther from the data bus than the selected block, are not used, the pre-charge circuits (or a bit line reset circuit), explained in FIG. 3(a), in the upper blocks can be controlled so that their operation is excluded. This will also contribute to saving power consumption. 
     As explained before, the sense amplifier in the selected block operates first. Then, the switching elements in the lower blocks, which are the blocks located between the selected block and the data bus, turn ON. Accordingly, when the pairs of bit lines in the lower blocks are connected to the pair of bit lines in the selected block, the voltage difference, which appears between the bit lines in the selected block, decreases due to the stray capacitance and the potential of the bit lines in the lower blocks. This causes an increase in the time needed to access the memory device. Accordingly, the access time depends on the location of the selected block. For example, when the selected block is located far from the data bus, the access time increases. The load capacitance for the sensing amplifier in the selected block is actually the sum of the stray capacitance of the lower blocks and the data bus. Therefore, when the sensing amplifier in each block has the same driving ability, like the prior art, the load capacitance of the sensing amplifier, in a block placed farther from the data bus, becomes hard to drive in a short access time due to its load capacitance. If the driving ability is made large enough to sufficiently shorten the access time, each sense amplifier must have as large a driving ability as the farthest sense amplifier has. This causes a large waste in power when the sense amplifiers nearest to the data bus are selected. Accordingly, the present invention improve this problem by changing the driving ability of the sensing amplifier in the respective block. This is done so that the farther block from the data bus has more driving ability. For example, in FIG. 4, sense amplifier VSA i0  has the maximum driving ability and the driving ability becomes smaller as the block is located nearer to the data bus. By doing so, the increase of the load capacitance can be compensated by the increase in the driving ability so that the access time in all block can be equalized. 
     FIG. 6 shows a circuit diagram of the block sense amplifier with a pair of switching elements in block BK i0  for example. In FIG. 6, symbols Q 1  and Q 2  are p-channel MOS (Metal Oxide Semiconductor) transistors, symbols Q 3 , Q 4 , and Q 5  are n-channel MOS transistors, symbol V SS  is a low power supply voltage (usually ground (GND)), symbol V CC  is a high power supply voltage, symbol BS is a block select signal, and other symbols are equal to those in FIG. 2 and function similar to those in to FIG. 2. Transistors Q 1  and Q 3 , and transistors Q 2  and Q 4  compose a CMOS (Complementary MOS) invertor respectively, and the two CMOS invertors intersect each other forming a flip-flop circuit. Transistor Q 5  turns ON by receiving a block select signal BS, activating the sense amplifier. Symbols Q 6  and Q 7  are n-channel MOS transistors composing the switching elements in which each are the same type to that shown in FIG. 3(b). In the present invention, the driving ability of the respective block sense amplifier is different, and the difference is made by changing the channel size of transistors Q 1 , Q 2 , Q 3 , and Q 4 . FIGS. 7(a) and (b) show the plan views of the IC (Integrated semiconductor Circuit) pattern for the circuit of FIG. 6. FIG. 7(a) shows the block sense amplifier having the maximum driving ability, and FIG. 7(b) shows the block sense amplifier having the minimum driving ability. In FIGS. 7(a) and (b), a dotted area is a pattern for a limited diffusion zone, a shadowed area is a pattern for the gate material made of Poly-Silicon, an X-marked portion shows a window for an Al (Aluminum) contact, and an area enclosed by the thick line is a pattern of an Al wiring. In FIGS. 7(a) and (b), symbol w 1  shows the channel size for transistors Q 1  and Q 2 , symbol w 2  shows the channel size for transistors Q 3  and Q 4 , and symbol w 3  shows the channel size for transistor Q.sub. 5. For example, when the memory device is a class having a M-bit memory capacity and each size of a middle block sense amplifier, which is a block sense amplifier in a block locating at the middle of the column, is set as a standard, the ratio of each channel size against the respective standard becomes as follows: when the driving ability is the maximum, size w 1 , w 2 , and w 3  increase as much as forty percent in length respectively when compared with those of the middle block sense amplifier as shown in FIG. 7(a); when the driving ability is the minimum, size w 1 , w 2 , and w 3   decrease to as small as sixty percent of those of the middle block sense amplifier respectively as shown in FIG. 7(b). 
     FIG. 8 is a time chart for illustrating the operation of the memory device shown in FIG. 4. When the amplitude of an address signal A dd  changes at time t 0 , a pre-charge signal p is generated so that the all pairs of bit lines BL i0 , BL i0  ; BL il , BL i1  ; - - - ; and BL ik , BL ik  shown in FIG. 4 are charged to an equal value like V cc  -V th  for example. Then when word line WL 0  is selected (see FIGS. 3 and 4) at time t 1 , memory cell C i00  in the column i is selected, and a small voltage difference on bit lines BL i0 , BL i0  in block BK i0  appears because of the data signal stored in memory cell C i00 . At time t 2 , block select signal BS i0  becomes high (H) by which sense amplifier VSA i0  is activated (transistor Q 5  becomes ON in FIG. 6) for amplifying the small voltage difference. After the voltage difference on bit lines BL i0 , BL i0  is sufficiently amplified by sense amplifier VSA i0 , clock signals φ 0 , φ 1 , - - - , and φ k  become H at time t 3  and all switch elements S i0 , S i0  ; S i1 , S i1  ; - - - ; and S ik , S ik  turn ON (because the farthest block BK i0  from the data bus is selected in this example). 
     In the above example, at the time immediately after the all switch elements are ON, the potential on the bit lines in all other non-selected blocks is a middle value of the pre-charged potential. Accordingly, the H side of bit lines BL i0 , BL i0  in selected block BK i0  decreases and the L side of them increases. However, since the driving ability of sense amplifier VSA i0  is great, the voltage difference appearing on bit lines BL i0 , BL i0  (also on other bit lines in the non-selected blocks) rapidly returns back to the value at just before time t 3  though the load for sense amplifier VSA i0  has the maximum value as stated. The dotted lines in FIG. 8 are the voltage differences on the bit lines in the prior art, which shows the merit of the present invention. As a result, time t 5  for changing address A dd  can be hastened, which is effective to raise the operation speed of the memory device. 
     There may be another method in which the sense amplifiers in related other non-selected blocks are activated after related switching elements are turned ON if the selected block is further from the data bus. However, the control of the sense amplifiers in the non-selected blocks becomes too complicated. In the present invention, the control of the sense amplifier can be simply fabricated and complicated control is not required. 
     Instead of changing the driving ability of each sense amplifier, if all sense amplifiers in all blocks have equal driving ability, the sense amplifier must have the maximum driving ability, otherwise the sense amplifier would have insufficient driving ability when the sense amplifier in the farthest block from the data bus is required to be driven. In the above case however, when the nearest block to the data bus is selected, all sense amplifiers are driven, which allows a waste of power and produces electrical noise because the amplification of the voltage difference is made too much quickly. The noise produces incorrect operation of the memory device. 
     The above explanation has been made based on a static RAM. However, the present invention can be also applied to the dynamic RAM.