Logic full adder circuit
BACKGROUND OF THE INVENTION 
     The invention relates to a logic full-adder circuit for adding two binary numbers a and b which each consist of n bits, n being a natural number larger than or equal to 2. The full adder comprises an inverting OR-gate and an inverting AND-gate for each bit a i , b i  of the numbers a and b, where 0≦i≦n, said gates receiving the bit signals a i  and b i  in order to form an inverted OR-signal a i  +b i  and an inverted AND-signal a i  ·b i . 
     A summing circuit forms a sum signal s i  from the bit signals a i  and b i  and an associated carry signal c i  and/or the inverse c i  thereof. The full-adder circuit also comprises a carry look-ahead signal circuit for generating a carry look-ahead signal c n+1  having the significance n+1 from all inverted OR-signals and AND-signals a i  +b i  and a i  ·b i  where 0≦i≦n. 
     Such full-adder circuits are marketed in the form of integrated circuits by various firms, for example Signetics type SN 7483 or Motorola type MC14008. These circuits utilize the principle of forming a carry look-ahead signal from the carry signals produced during the various additions of bits of ascending significance. The carry look-ahead signal has the correct logic value for being applied to the adder gates of the bits of higher significance than the next-higher significance. If the bits of ascending significance of the signals a and b are successively denoted as a o , a 1 , a 2  etc. and b o , b 1 , b 2  etc. the carry signal c 1  would, before the introduction of the carry look-ahead principle, have been formed from the addition a o  +b b , said carry signal being applied to the adder gate of the signals a 1  and b 1 , the carry signal c 2  formed during this addition being subsequently applied to the adder gate of the signals a 2  and b 2  etc. so that the addition in the n th   gate of the signals a n  and b n  could not be started before completion of the additions in all preceding gates. By generating the carry look-ahead signal c n  in advance in some other way in accordance with the carry look-ahead principle, the speed of calculation can be substantially increased. 
     To this end, the known circuits utilize a separate arithmetic unit containing a truth table such that when the signals a o , a 1  . . . a n-1  and b o , b 1 , . . . b n-1  are inputted, the output directly supplies the carry look-ahead signal c n . In order to generate the carry look-ahead signal, the signals a i  +b i  and a i  ·b i  are generated by means of inverting OR-gates and AND-gates. In addition to this carry look-ahead signal circuit, a full-adder circuit comprise, for each bit of a binary number to be added, a summing circuit for generating a sum signal and a carry circuit for generating a carry signal which is required for obtaining the desired higher-order sum signal. It will be apparent that a substantial number of logic gates is required for this purpose. 
     SUMMARY OF THE INVENTION 
     It is the object of the invention to provide a full-adder circuit in which the number of logic gates and the number of components (transistors) in these gates can be substantially reduced whilst the result of the addition can become available sooner because the number of delay times has been reduced. 
     To this end, a full-adder circuit in accordance with the invention is characterized in that each summing circuit comprises a logic gate which receives the bit signals a i  and b i  and the inverted AND-signal a i  ·b i  in order to form a logic signal a i  ·b i  ·(a i  +b i ) on a first output thereof and the inverted logic signal a i  ·b i  ·(a i  +b i ) on a second output thereof, and also comprises electronic switches which connect, under the control of the carry signal c i  and/or the inverse c i  thereof, either the first output or the second output of the logic gate to a first junction in order to generate an inverted sum signal s i  on the first junction. 
     In addition to the OR-gate and AND-gate already present for the carry look-ahead signal, a full-adder circuit in accordance with the invention may comprise, for each bit of a binary number to be added, only one further logic gate (which needs to comprise only eight transistors in the CMOS transistor technique) and some electronic switches (each of which can comprise, as is known, a field-effect transistor or e.g. in the CMOS technique a parallel connection of a P- and an N-channel transistor). The number of components required is thus substantially reduced, and the delays occuring in the full adder are reduced. 
     The invention will be described in detail hereinafter with reference to embodiments shown in the drawings. 
    
    
     BRIEF DESCRIPTION OF THE FIGURES 
     FIG. 1 shows the construction of a section of a full-adder circuit in accordance with the invention, 
     FIG. 2 shows an example of a logic gate for a full-adder circuit in accordance with the invention, and 
     FIG. 3 shows a carry look-ahead signal circuit for a full-adder circuit in accordance with the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows a section 10 for a full-adder circuit in accordance with the invention for the processing of one of the bits of the n-bit binary numbers a and b, for example bit a i , b i . For each bit i there is required a circuit section 10 as shown in FIG. 1. The section 10 comprises an inverting OR-gate 1 and an inverting AND-gate 3 which generate the inverted OR-signal a i  +b i  and the inverted AND-signal a i  ·b i . Such gate circuits are known in the state of the art. The section 10 furthermore comprises a sum circuit 20 which comprises a logic gate 5 and electronic switches 7 and 9. The logic gate 5 receives the signals a i , b i  and a i  ·b i , on the first output 11 and the second output 13 of the logic gate 5 there being generated the signals (a i  ·b i )·(a i  +b i ) and (a i  ·b i )·(a i  +b i ) respectively, as will be described in detail hereinafter (with reference to FIG. 2). The outputs 11 and 13 are connected to a first junction 15 via the switches 7 and 9. The switches 7 and 9 are controlled by the carry signal c i  and/or the inverse c i  thereof, so that on the junction 15 there is formed the sum signal s i  which is converted by an inverter 17 connected to the junction 15, into the sum signal s i  on an output 19. 
     In order to obtain the carry signal c i+1  and its inverse c i+1  which serve to control the switches in a summing section for the summing of bits of the next-higher order, the inverted OR-signal a i  +b i  and AND-signal a i  ·b i  are applied to a second junction 25 via switches 21 and 23. On the junction 25 there is obtained the inverted carry signal c i+1  which is converted into the carry signal c i+1  on output 29 via an inverter 27. 
     The switches 9 and 21 are N-channel field-effect transistors which are controlled by the carry signal c i , the switches 7 and 23 each being a parallel connection of an N- and a P-channel field-effect transistor whose N-channel transistor and P-channel transistor are controlled by the inverted carry signal c i  and the carry signal c i , respectively. 
     FIG. 2 shows a logic gate 5 for a full-adder circuit 10 as shown in FIG. 1. The gate 5 is composed of complementary field-effect transistors and comprises an input section 30 and an inverter 40 which is connected to the output which is also shown in FIG. 1. The input section 30 comprises a series connection of two P-channel transistors 31, 32 which are controlled by the signals a i  and b i  respectively and whereto there is connected in parallel a third P-channel transistor 33 which is controlled by the inverted AND-signal a i  ·b i . The input section 10 furthermore comprises two parallel-connected N-channel transistors 34, 35 which are controlled by the signals a i  and b i  respectively and which are connected in series with a third N-channel transistor 36 which is controlled by the inverted AND-signals a i  ·b i . The junction of the N- and P-channel transistors 32, 33, 34, 35 forms the first output 11 of the logic gate 5 which also comprises a known inverter 40 which comprises complementary transistors 37, 38 and whose input is connected to the first output 11 while its output constitutes the second output 13 of the logic gate 5. On the first output 11 and the second output 13 there are generated the signals (a i  ·b i )·(a i  +b i ) and (a i  ·b i )·(a i  +b i ), respectively. 
     FIG. 3 shows a carry look-ahead signal circuit 50 for a full-adder circuit in accordance with the invention. In an n-bit full-adder circuit the circuit 50 receives the inverted OR- and AND-signals a i  +b i  and a i  ·b i  wherefrom a carry look-ahead signal c n+1  can be derived. This is because: 
     
         c.sub.1 =a.sub.o ·b.sub.o +c.sub.o ·(a.sub.o +b.sub.o)=a.sub.o +b.sub.o +c.sub.o ·(a.sub.o +b.sub.o) 
    
     
         c.sub.2 =a.sub.1 +b.sub.1 +c.sub.1 ·(a.sub.1 ·b.sub.1) 
    
     
         c.sub.3 =a.sub.2 +b.sub.2 +c.sub.2 ·(a.sub.2 ·b.sub.2) etc. 
    
     It will be apparent from the foregoing that the carry look-ahead signal circuit 50 for the full-adder in accordance with the invention is preferably constructed with complementary field-effect transistors comprising insulated gate electrodes. 
     The following holds true for a four-bit carry look-ahead signal circuit. The signals a i  +b i  and a i  ·b i  are already generated on the outputs of the gates 1 and 3 in the circuit shown in FIG. 1, where 0≦i≦3.  The above logic formulae are realized in practice in a simple manner by applying the products a i  ·b i  of the bits of the input signals a i , b i  to the inputs of the series-connected N-channel transistors 52-55 with an ascending significance, the sums a i  +b i  of these bits being applied with an ascending significance to the N-channel transistors 56-59, each of which is connected in parallel with an each time larger section of this series connection. An inverted carry signal c o  (carry-in) is applied to the transistor 51. On the connection between the transistor 51 and a P-channel field-effect transistor 60 there is now generated the carry look-ahead signal c 4  which is converted, via a known inverter 70 (comprising a P- and an N-channel field-effect transistor) into an inverted carry look-ahead signal c 4  which could be applied as an input signal to a subsequent cascade-connected full adder.