Multi-channel, controlled amplification factor electronic amplifier construction, particularly for color TV contrast adjustment
The present invention relates to a controlled amplification factor amplifier for multi-channel use, and more particularly for such an amplifier suitable for controlling the contrast setting in a color TV monitor or receiver. 
     BACKGROUND 
     Contrast adjustment in color TV receivers, particularly those which have inputs for chroma signals red, green and blue (RGB), require amplifiers in which the amplification of respective channels for the respective colors are the same over the entire adjustment range. The frequency band width of wide-band RGB monitors requires circuits which uniformly amplify the wide frequency signals, independently of the respectively set adjustment of the contrast amplification. 
     Contrast amplifiers of the type to which the present invention relates have, for each channel, a pair of emitter coupled transistors, formed of first and second transistors, and a third transistor, the collector of the third transistor being coupled to the emitter of the first and second transmission of the pair. The emitter of the third transistor is coupled through an emitter-resistor to one terminal of a source of operating voltage. 
     THE INVENTION 
     It is an object to provide a circuit in which, over the entire adjustment range, the amplification factors of the amplifiers formed by the transistors remain uniform over the entire adjustment range, while being capable of handling wide-band signals, that is, signals extending over a substantial frequency range, the amplification factor being independent of the particular frequency involved. 
     Briefly, in accordance with the invention, the amplifier comprises a construction in the form of a hybrid circuit, in which some elements are located on common substrates, the substrates all being taken from the same wafer or chip. The amplifier has emitter coupled transistor pairs as well as a third transistor, the emitter coupled transistor pairs and the third transistor for each channel being located on a common substrate to thereby provide, for three channels, three substrates which are all taken from the same wafer. The three substrates are connected into a hybrid circuit network, which may include other elements such as resistors and the like, also taken from the same wafer. Preferably, a source of control voltage is provided, coupled to the base terminals of one of the transistors of the pair of each channel so that the control voltage will be connected, in common, to all the channels. The arrangement insures homogeneous temperature response of the elements of the amplifier, with temperature drift between channel amplifiers being effectively eliminated. The amplifier stages are connected in parallel. Aging of the amplifier stages also will be uniform. 
     The circuit has the advantage that the amplification factors of the amplifiers for the respective channels, typically the three channels for red, green and blue (RGB) operate in unison. Control of the amplification factor is by a d-c voltage, which is a substantial advantage since it eliminates conducting video signals over connections or conducting lines to an operating adjustment knob, console or the like, which may be remote from the display unit of a monitor. The adjustment can readily be controlled by a computer via a digital/analog converter. Additionally, a control signal can be derived from the monitor in order to limit the average beam current, and this control signal can readily be coupled to the circuit. 
     The circuit network has the additional advantage that it can be used universally, has low power dissipation and can be constructed in a very small space. Frequencies of over 100 MHz can be handled thereby. 
    
    
     DRAWINGS 
     FIG. 1 is a schematic circuit diagram of the circuit which is preferably placed on a single silicon chip; and 
     FIG. 2 is a circuit diagram of the circuit in a network for providing additional control signals and deriving output signals, and in which the circuit of FIG. 1 is shown in block form. 
    
    
     Detailed Description 
     Referring first to FIG. 1: Three amplifiers, one each for a channel R, G and B, are provided, the amplification factor of which can be controlled. The circuits of the three channels R, G, B are identical, and the details of the circuit will be described in connection with the red or R channel. 
     The amplification factor is controlled by a pair of transistors 21, 22, which have their emitters coupled together to a common junction. The two transistors 21, 22, forming a first and second transistor of the pair, have their emitters connected, via the common junction to the collector of a third transistor 23. The third transistor has its emitter connected through an emitter resistor 25 to one terminal, for example reference, ground or chassis, of a current supply source. The first transistor 21 of the pair has its collector connected to a collector-resistor 26, the second terminal of which is connected to the positive supply terminal 17 of the operating source, the negative terminal of which is connected to ground, chassis or reference. The collector of the second transistor 22 is coupled directly to the positive terminal 17 of the operating source. The base of the second transistor 22 is coupled in common to the bases of transistors 32, 42, that is, the second transistors of the respective channels G, B, and then to a terminal 20. Terminal 20 is coupled to a voltage source, not shown in FIG. 1, which provides a fixed, constant bias voltage. The collector of the first transistor 21 of the pair is connected to the base of a fourth transistor 24, connected as an emitter-follower, the output of which is connected to the output terminal 2 of the channel R. The base of the fourth transistor 24 is, also, connected to a further input 1 of the R channel. 
     The circuits for the channels G and B are identical, and include the transistors 31, 32, 33 and 34, and resistors 35, 36 for the G channel; and transistors 41, 42, 43 and 44, and resistors 45, 46 for the channel B. 
     The base connections of the second transistors 22, 32, 42 are not only connected to the bias supply source 20 but also over resistor 47 to ground or chassis. The base terminals of the transistors 21, 31, 41 are connected to a common supply line which is connected through a resistor 49 to a terminal 18 which provides a d-c supply voltage to control the amplification, and, in a color monitor, the contrast. A further resistor 50 is connected between the junction of terminal 18 and resistor 49 to ground or chassis. 
     A capacitor 53 is provided, blocking the operating voltage with respect to ground or chassis. Ground or chassis is connected to terminal 5. A voltage divider 51, 52 provides a bias voltage, available at terminal 16, for a clamping circuit, to be described in connection with FIG. 2. 
     OPERATION 
     Current through the third transistor 23 (33, 43 for the other two channels) is controlled in accordance with the voltage connected to terminals 3, 8, 13, respectively. The negative feedback resistor 25 (35, 45, respectively) provides for necessary linearity. The current, corresponding to the chroma value signal, is split between the emitter-collector main current paths of the transistors 21, 22 of the pair. The portion flowing through the first transistor 21 causes a voltage drop across the collector-resistor 26 which multiplies the chroma signal with the portion of the current corresponding to the transistor 21. This portion can be controlled by controlling the base of transistor 22, as well as the base terminals of transistors 32, 42, by a constant voltage connected to terminal 20. The base of the transistor 21, together with the base terminals of transistors 31, 41, receives a control voltage applied by terminal 18 and, reduced, by the voltage divider 48, 49. To control the transistors 21, 22 from one end condition of the adjustment range to the other requires only a minute voltage difference. For constructional reasons within monitors, it is desirable to provide a higher voltage than necessary to control the circuit in accordance with the present invention and, therefore, the voltage divider 48, 49 is used. 
     Terminal 20 receives a constant voltage, thus applying a control voltage at 18 and through the voltage divider network 47, 48, 49, 50, as shown, will affect the voltage applied to the bases of the transistors 21, 31, 41 only to a minor extent, to insure linearity, without, however, essentially affecting the operation of the circuit as described. 
     The output signals are derived at the terminals 2, 7, 12, respectively, from the emitters of the fourth transistors 24, 34, 44,connected as emitter-followers. 
     It is frequently necessary to introduce signals already available in a circuit, for example a reference level signal derived from a cut-off automatic circuit. The circuit as described can readily accept additional modulating or modifying signals by simply applying such modulating or modifying signals to the terminals 1, 6, 11. If, for example, the control voltage at terminal 18 is placed on ground potential, only the additional signals applied to terminals 1, 6, 11 will reach the output terminals 2, 7, 12. If, however, the input terminal 18 is placed at a voltage other than ground, chassis or reference, the signals applied to terminals 1, 6, 11 are mixed with the signal applied to terminal 18. For example, to introduce a reference level, terminals 1, 6 and 11 can be connected to ground potential; the output terminals 2, 7, 12 then will have the reference level thereon, entirely independently of the adjustment of the value of the control voltages applied to the bases of the transistors 23, 33, 43 over the terminals 3, 8, 13. 
     In accordance with a modification of the present invention, the base of the transistor 21 may be supplied with a fixed bias voltage and the base of the transistor 22 may have a control voltage applied thereto. It is also possible to provide control voltages to the two transistors of the pair, in opposite direction. 
     FIG. 2 shows a network in which the circuit of FIG. 1 is shown schematically as a hybid 61. The terminals of the hybrid 61 are the same terminals having the reference numerals shown in FIG. 1. 
     Operating voltage is connected to terminal 17 of the hybrid 16 from a terminal 62 of an external voltage supply. Two capacitors 63, 64 provide filtering against ground or chassis. The chroma signals R, G, B are connected to inputs 65, 66, 67, which are connected to ground or chassis via respective resistors 68, 69, 70 to form dropping resistors, and are additionally connected to a clamping circuit formed, in well known construction, of a respective capacitor 71, 72, 73 and a clamping diode 74, 75, 76. Clamping voltage is derived from the hybrid circuit 61, terminal 16 - see also FIG. 1, which shows the terminal 16 connected to the voltage divider of the main supply circuit. A capacitor 77 provides filtering to ground or chassis. Terminals 2, 7, 12 of the hybrid circuit 61 are connected to the final output terminals 78, 79, 80 to provide amplitude controlled chroma signals R, G, B. Dropping resistors 81, 82, 83 are connected between the respective output terminals and ground or chassis. 
     Two further transistors 84, 85, each having the collector connected to the positive terminal of the operating source and the emitter to the respective terminal of the hybrid circuit 61, are provided in order to supply the control circuits for biassing. The base of transistor 84 is supplied with a constant voltage by the voltage divider 86, 87. The base of the transistor 85 is connected to a control voltage derived at terminal 90 via a low-pass filter formed by resistor 88 and capacitor 89, in standard low-pass filter connection. 
     Various other changes and modifications may be made within the scope of the inventive concept.