Gain selectable amplifier with resonance compensation
FIELD OF THE INVENTION 
     This invention generally relates to feedback amplifiers. More particularly, this invention relates to circuitry for compensating for oscillation and instability associated with such amplifiers at high frequencies. 
     BACKGROUND OF THE INVENTION 
     The unity gain buffer amplifier is a feedback amplifier that provides unity voltage gain at its output. The unity gain buffer is commonly used in many applications because of its superior characteristics. These characteristics include a relatively low output impedance and high input impedance, gain stability with respect to temperature, and an improved linearity. 
     This amplifier, as any feedback amplifier, suffers from a tendency to oscillate at higher frequencies. The simplest and most common method of compensating for oscillation is to reduce the bandwidth of the amplifier by adding capacitance. The capacitance introduces a dominant pole within the amplifier to force the phase shift of the gain to be less than -180° and thus the phase margin to be greater than 0° when the loop gain T is unity. This addition will satisfy the Nyquist criterion for stability. However, the trade-offs in amplifier performance are considerable. For one, the frequency capability of the amplifier is sacrificed. For another, the introduced phase margin causes peaking in the overall gain at the resonant (unity loop gain) frequency of the amplifier. The smaller the phase margin, the larger the gain peak becomes until the gain approaches infinity and oscillation occurs for a phase margin of 0°. For a third reason, increasing the capacitance to increase the phase margin lowers the slew rate of the amplifier. The lower the slew rate, the longer the amplifier takes to respond to a large input signal. 
     The need to preserve stability is especially important in gain selectable amplifiers, where the current gain can be varied upon command. Such amplifiers may be stable at one level of current gain and yet be unstable at another level because of the change in feedback caused by changing resistance therein. The change in feedback within the amplifier affects the peaking of the gain at the resonant frequency. 
     SUMMARY OF THE INVENTION 
     An object of the invention, therefore, is to improve the stability of a unity gain amplifier without sacrificing bandwidth. 
     A second object of the invention is to compensate for the gain peaking of the amplifier. 
     A third object of the invention is provide a simple means for determining the required compensation. 
     A fourth object of the invention is to provide compensation that minimizes the effect of slew rate on the performance of the amplifier. 
     A fifth object of the invention is to provide compensation that can be designed into an integrated circuit. 
     Still another object of the invention is to provide such compensation for a selectable gain amplifier. 
     To achieve these objects, a resonance compensated amplifier is disclosed herein. The amplifier includes a differential input stage for receiving the input signal and an output stage for amplifying the signal. The output voltage of the output stage is fed back to the input stage to cause the output voltage to match the input signal voltage. Instability in the amplifier created by the feedback is compensated for by a series resonance circuit, the reactance of the circuit adjusted to be substantially zero at the resonant (unity loop gain) frequency of the amplifier. 
     In one embodiment of the invention, the series resonance circuit comprises an inductor-resistor-capacitor branch coupled between the input and output stages of the amplifier, the value of the capacitor minimized by the addition of the inductor. In another embodiment of the invention, the inductor is a transistor connected in series with the capacitor and the resistor, the collector of the transistor coupled to the capacitor and resistor, the base coupled to the collector through a biasing base resistor and the emitter coupled to the input and output stages. The resistance of the base resistor is adjusted according to a conventional formula to provide in combination with the transistor an inductive reactance. This reactance is combined with the reactance of the capacitor to be substantially zero at the amplifier&#39;s resonant frequency. 
     Means are further disclosed for adjusting the current gain of the amplifier by varying the resistance across which the output voltage is applied. 
     The foregoing and other objects, features, and advantages of the invention will become more apparent from the following detailed description of a preferred embodiment which proceeds with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a first embodiment of a compensated amplifier according to the invention. 
     FIG. 2 is a schematic diagram of a second embodiment of the compensated amplifier. 
     FIG. 3 is a schematic diagram of a selectable gain amplifier embodying the compensated amplifier of FIG. 2. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1, a resonance compensated amplifier 10 embodying the invention is shown. The compensated amplifier includes a unity gain buffer 11 having a differential input stage for receiving an input signal and an output stage for providing an output signal V o  with unity voltage gain. The differential input stage comprises a pair of emitter-coupled transistors Q 1 , Q 2  biased by a conventional current source 16. The transistors Q 1  and Q 2  are matched so that equal currents are drawn by the current source 16 from each transistor when the voltages at each base are equal. 
     Coupled to the collector of transistor Q 2  is an output stage such as a transistor Q 3 . Transistor Q 3  provides at its emitter an output voltage V o  Biasing current source 20 biases Q 3 . V o  is applied across resistor R L  connected to the emitter of the transistor Q 3  to control the amount of current I o  drawn through its collector. 
     As can be seen in FIG. 1, transistor Q 3  is basically an emitter follower connected in feedback to the differential input stage. As an emitter follower, it would provide about unity voltage gain at its emitter (less the voltage drop across the base emitter junction) and substantial current gain if no feedback were present in the buffer 11. Its performance is improved, however, by applying V o  to the base of transistor Q 2  along a feedback path 24. At the base, V o  is compared by the input stage against the input signal voltage V in  on the base of transistor Q 1 . If V in  exceeds V o , the base emitter voltage across transistor Q 2  decreases, causing the transistor to draw less current from current source 26 formed by a resistor R 1  and voltage source V s . The drop in current drawn into the collector of transistor Q 2  raises the voltage at the base of transistor Q 3  and via the base-emitter junction raises V o . If V in  drops below V o , on the other hand, the opposite result occurs. The voltage across the base emitter junction of transistor Q 2  increases, causing more current to be drawn from current source 26. The increased current lowers the voltage at the base of transistor Q 3  and via the base-emitter junction lowers V o  as well. V o  therefore changes to match V in  as V in  varies. 
     This feedback, although it improves the linearity of the buffer 11, introduces a tendency for it to oscillate at high frequencies because of the phase shift that feedback causes in the overall gain. According to the Nyquist criterion, oscillation will occur at radian frequency ω o  if the phase margin is 0° or less when the loop gain T is one. This frequency ω o  is a function of the parameters of the buffer 11 such as the transconductance, output admittance, input impedance, parasitic capacitances, and resistances, etc. With these values known or estimatable, ω o  is readily determined by simulating the performance of the unity gain buffer 11 on SPICE or a similar circuit simulation program. At this frequency, the output signal V o  of the buffer 11 will &#34;resonate&#34; or oscillate independently of V in . 
     To compensate for the effect of feedback on buffer 11, a series resonance circuit 28 is coupled between the output and input stages of the buffer 11. In FIG. 1, the circuit 28 comprises a capacitor C 1 , resistor R 2 , and inductor L 1  connected in series. The value of the capacitor C 1  is chosen to be large enough to introduce sufficient phase margin via movement of a pole to prevent oscillation and yet as small as possible to preserve maximum bandwidth. This value can be determined from the parameters of the buffer 11 by calculation or more easily from SPICE. The peaking that results at the unity gain frequency ω o  as observed on a Bode plot is then reduced by the addition of inductance through inductor L 1 , which is chosen to provide a zero at the resonant frequency to cancel the corresponding pole of the capacitor. This inductor also improves the slew rate of the buffer 11 by effectively increasing the capacitive effect without increasing the capacitance. The value of resistor R 2  is chosen to match the gain peak at or near the resonant frequency. It effectively counters the magnitude of the gain peak at resonance. Its value can be calculated but is more easily determined through observation on SPICE of its effect on the gain peak. With all three element values chosen properly, the gain peaking should be removed at the resonant frequency and replaced by a smooth roll-off on the Bode plot. 
     Fabricating of an inductor such as L 1  in an integrated circuit, however, is difficult. FIG. 2 shows in place of the inductor L 1  transistor Q 4  biased through a base resistor R b . Using a technique well known in the integrated circuit art, transistor Q 4  and resistor R b  are chosen to provide an inductance according to the following formula: 
     
         L=R.sub.b /2πf.sub.T 
    
     where f T  is the transition frequency of the transistor, the frequency at which the magnitude of the short circuit, common emitter current gain falls to unity. 
     FIG. 3 shows the compensated amplifier 10 in combination with a variable load resistance to create a selectable current gain amplifier 52. Two compensated amplifiers 10 and 10&#39; are shown because of the use of a differential input signal in this particular embodiment. In this amplifier 10, the output current I o  on the collector of transistor Q 3  is linearly proportional to V in . An additional transistor 54 has been added to Q 3  in a Darlington configuration to boost the current gain of the amplifier 10 at the collector of Q 3 . 
     In place of a single emitter resistor, a resistive network having branches 22a through 22f is connected to the emitter of Q 3 . The resistance decreases from branch 22a to 22f. Each resistive branch is connected to an independent biasing current source 20a through 20f, at least one of which is selected to be active at a time by an input signal (not shown). The resistive branches are isolated from each other by diodes 56a through 56f and 58a through 58f and a voltage applied by an associated voltage source 60a through 60f when the respective source is switched off. The selectable current source 20a through 20f and the resistive network form a means for adjusting the gain of the amplifier 10 according to the following equation: 
     
         I.sub.o =V.sub.o /R.sub.L =V.sub.in /R.sub.L 
    
     where R L  is the resistance of the branch selected. By selecting a specific current source, the resistance on Q 3  across which V in  is applied via V o  may be selectively varied to change the current gain of the amplifier. The current gain of Q 3  is therefore inversely proportional to the load resistance coupled to the emitter across which V in  is applied. 
     Amplifier 52 is shown with inputs for receiving a differential signal. If a time differential signal is receive V o  is applied across half of the branch resistance. If one of the signal inputs is ground, then V o  is applied across the entire branch. 
     Two biasing current sources are shown connected to the emitter-coupled transistors Q 1 , Q 2  of the differential input stage. Source 16a is activated to bias the input stages when any of the resistive branches 22b through 22f are selected. However, source 16b is selected when branch 22a is selected because of the change in the amount of feedback produced by the higher resistance. The emitters coupled to source 16b include emitter degeneration resistors for reducing the open loop gain of the amplifier 10, thereby preserving its stability. 
     Having illustrated and described the principles of the invention in a preferred embodiment, it should be apparent to those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. We claim all modifications coming within the spirit and scope of the following claims.