Method and apparatus for eliminating short pulses in a doppler radar
BACKGROUND OF THE INVENTION 
     The present invention is directed to an apparatus and method for eliminating short pulses in a Doppler radar, whether or not the pulses are pulse compressed. 
     In radars intended for the detection and location of ground mobile vehicles, it is necessary to operate in short and spaced sound strokes in order to reduce the probability of destruction by an anti-radiation missile and to reduce its susceptibility to counter-measures. The echoes of a target vehicle must be detected and localized very rapidly. This requires the provision of automatic means to avoid a radar operator being subjected to many false alarms coming from the residue of clutter and from active or passive interference signals. This indispensable automatic control of the amount of false alarms should take into account the particular nature of the targets and the characteristics of various stray current signals that may exist. 
     A false alarm is caused by the presence, in a resolution cell of the radar, of a stray current signal exceeding the previously established threshold of detection. This stray current signal can arise, either from a stray current echo from an exterior source, or from a range sidelobe due to pulse compression and resulting from the presence of a useful signal of a significant level in a resolution cell near the resolution cell in which the stray current signal manifests itself. 
     The presence of a short pulse, i.e., present only in a given range gate, involves the appearance in the treatment (signal processing) chain of the signal, Doppler filter and integrator, of a transient state corresponding to a pulse response of the chain. For an amplitude of stray current signal more than twenty decibels above the normal noise of the radar, this transient state is detected and causes a false alarm. In the presence of strong fixed echoes, or normal noise, this false alarm causes a degradation of the radar&#39;s elimination capability, which reduces its operational usefulness. 
     SUMMARY OF THE INVENTION 
     To avoid this transient state, it is appropriate after having detected it, to eliminate this short pulse before its introduction into the treatment chain of the signal and to replace it, for example, by the information present during the preceding repetition. The suppression of this signal, of very brief duration compared to the time of observation, does not affect the quality of the measurement. 
     The present invention therefore provides a process for detecting these short pulses and a device using this process. The device is placed at the input of the treatment chain of the signal. It operates to detect and eliminate short pulse and replace it by information present in the same range gate during the preceding repetition. 
     According to the present invention, the process for the elimination of a short pulse consists, successively for each of j=1 to N range gates given a repetition period, of index i, to delay the non-delayed components a ij  and b ij , of the sample V ij , of the vector signal V i  (t), associated with the range gate having index j of the i th  period of repetition, of the duration Tr of the repetition period; to calculate starting with preceding delayed components a i-1  j and b i-1  j and non-delayed components a ij  and b ij , the square of the modulus Δρ ij   2  of the vector difference ΔV ij  =V ij  -V i-1  j ; to delay this square of the modulus Δρ ij   2  of the duration Tr of the repetition period; and to compare the square of the non-delayed modulus Δρ ij   2  with the square of the delayed modulus Δρ i-1  j 2 . If the relation Δρ i-1  j 2  -K≦ρ ij   2  ≦Δρ i-1  j 2  +K is satisfied, K being a measurement noise threshold, then one stores the information &#34;no short pulse&#34; PIB ij  =0 and one delays twice the duration Tr of the repetition period, this information &#34;no short pulse&#34;. One transmits finally the non-delayed components a ij  and b ij . If this relationship is not satisfied, one tests from the very first the two preceding information PIB i-2  j and PIB i-1  j. Now if PIB i-2  j =0 and PIB i-1  j =0 one stores the information &#34;short pulse detected&#34;  PIB ij  =1 and one transmits the delayed components a i-1  j and b i-1  j. If PIB i-2  j =0 and PIB i-1  j =1, one stores the information &#34;short pulse detected&#34; PIB ij  =1 and one transmits the components a ij  and b ij . If PIB i-2  j =1 and PIB i-1  j =1, one stores the information &#34;no short pulse detected&#34; PIB ij  =0 and one transmits the components a ij  and b ij . 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be further explained by the following description with reference to the attached drawings wherein: 
     FIG. 1 is a block diagram of a treatment chain of the radar signal (receiver signal processor) including a means for eliminating short pulses in accordance with the invention; 
     FIG. 2 is a vector diagram explaining the principle of jamming elimination as it applies to the present invention; 
     FIG. 3 is a block diagram of the means for eliminating short pulses in accordance with the present invention; and 
     FIG. 4 is a more detailed block diagram of block D of FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to FIG. 1, there is shown a block diagram of the treatment chain including a correlator COR, a Doppler filter FD, an integrator INT, or integrator detector, and a system S operating at a threshold k 0 . To eliminate false alarms caused by short pulses, a means of elimination EI of the short pulses is provided at the input of this treatment chain of the signal. This means of elimination of short pulses according to the present invention receives, from a buffer memory MT, the components a ij  and b ij  of the sample V ij , of the signal vector received, at the time t ij , in the range gates of index j in the course of the i th  repetition period. The sampling and the coding of these received signal vectors V i  (t) are obtained by the coders COD1 and COD2, respectively, of the phase channel and of the quadrature channel. These coders receive from the outputs of mixers MEL1 and MEL2, respectively the components a i  (t) and b i  (t) of this analog video signal V i  (t). 
     The principle of this jamming elimination can be understood using the vector diagram of FIG. 2. For a range gate, of index j, this index being, to simplify the notations, omitted in this Figure, one has represented the samples V i-2  j, V i-1  j, V ij  and V i+1  j, noted i-2, i-1, i and i+1, of the signal vectors V i-2  (t), V i-1  (t), V i  (t) and V i+1  (t) received in the course of successive repetition periods Tr i-2 , Tr i-1 , Tr i  and Tr i+1 . At each repetition period, and in particular for the range gate j, one calculates the square of the modulus Δρ ij   2  =(a ij  -a i-1  j) 2  +(b ij  -b i-1  j) 2  of the vector difference ΔV ij  =V ij  -V i-1  j. Taking into account the speed of rotation of the antenna and the beamwidth in bearing, the amplitude modulation of parameter Δρ  ij   2  is very slow. That means that one can consider this parameter as being practically constant from one recurrence to the next. 
     For a given range gate, of index j, this index being omitted to simplify the notations, the criterion of detection of a short pulse selected is the following: 
     (a) If the parameter Δρ i   2  is such that the relationship Δρ i-1   2  -K≦Δρ i   2  ≦Δρ i-1   2  +K is satisfied, K being a measurement noise threshold, then one can state that there is no short pulse and one performs the following operations: 
     storing the squared modulus Δρ i   2  in place of the delayed squared modulus Δρ i-1   2  ; 
     storing the information &#34;no short pulse&#34; or PIB i  =0; 
     introducing the components a i  and b i  of vector V i , in fact V ij , in the treatment chain of the signal, 
     (b) If the parameter Δρ i   2  is such that the preceding relationship is not satisfied, or that one or the other of the relationships Δρ i   2  &gt;Δρ i-1   2  +K or Δρ i   2  &lt;Δρ i-1   2  -K is satisfied, short pulses may exist and one tests the states of preceding binary elements PIB: 
     if PIB i-2  =0 and PIB i-1  =0, then the two preceding repetitions do not contain any short pulse; and one would then perform the following operations: 
     storing the squared modulus Δρ i   2  in place of the delayed squared modulus Δρ i-1   2  ; 
     storig the information &#34;short pulse detected&#34;, or PIB i  =1; 
     introducing delayed components a i-1  and b i-1  of the vector V i-1 , by replacing components a i  and b i  of the vector V i , in the treatment chain of the signal. 
     if PIB i-2  =0 and PIB i-1  =1, then the preceding repetition contains, only, a short pulse; and one would perform the following operations: 
     storing the squared modulus Δρ i   2  in place of the delayed squared modulus Δρ i-1   2  ; 
     storing the information &#34;short pulse detected&#34;, or PIB i  =1; 
     introducing components a i  and b i  of the vector V i  in the treatment chain of the signal, 
     if PIB i-2  =1 and PIB i-1  =1, then the two preceding repetitions already contain an effect of a short pulse on the associated squared modulus; then one would perform the following operations: 
     storing the squared modulus Δρ i   2  in place of the delayed squared modulus Δρ i-1   2  ; 
     storing the information &#34;no short pulse detected&#34;, or PIB i  =0; 
     introducing components a i  and b i  of the vector V i  in the treatment chain of the signal. 
     These operations will be carried out for each of the successive range gates of a given repetition period, or for all the possible values of j. 
     The device which operates to eliminate a short pulse according to the above process is described with reference to FIG. 3. The device includes a delay memory MP for an in phase component a ij  and a delay memory MQ for a quadrature phase component b ij . The delay Tr introduced by these memories is exactly equal to the duration Tr of the repetition period of the radar. To simplify, we will only consider here the treatment effected in the range gate of index j and in the course of the repetition period of index i considered, it being understood that the treatment of various components received in the various range gates is effected successively, from the gate j=0 to the gate j=N, using the same material. The use of internal memories MP, MQ, Mm, M1 and M2 which introduce delays Tr equal to the duration of the repetition period permits a change of the repetition period while preserving the same range gate. Thus, all indices j relating to a particular range gate have been suppressed in the FIG. 3 arrangement and the description of this Figure will relate only to this range gate without doing harm to the generality of the treatment. 
     An electronic switch AI receives finally the components a i  and b i  provided at the input of memories MP and MQ as well as the delayed components a i-1  and b i-1  provided by these memories. This electronic switch AI transmits then, either the received components a i  and b i , or the delayed components a i-1  and b i-1  following the state of its input control. The decision of validation of one or the other of these pairs of components is carried out starting with the calculation of the squared modulus 
     
         Δρ.sub.i.sup.2 =(a.sub.i -a.sub.i-1).sup.2 +(b.sub.i -b.sub.i-1).sup.2 
    
     of the vector difference ΔV i  =V i  -V i-1 . This squared modulus is obtained by a calculator of modulus CM receiving the components a i  and b i  of vector V i  and the delayed components a i-1  and b i-1  of vector V i-1 . This calculation can be carried out for example by two first binary adder-subtractors effecting, respectively, the operations (a i  -a i-1 ) and (b i  -b i-1 ) followed each by a programmable memory, preferably a PROM, permitting to effect a rise to the square. These memories are then followed by a third binary adder-subtractor effecting the summation of the output variables (a i  -a i-1 ) 2  and (b i  -b i-1 ) 2  of these two memories. 
     When starting with this squared modulus Δρ i   2  the decision circuit D will command the electronic switch AI. A delay memory Mm of this squared modulus is moreover interposed between the calculator of the modulus CM and this decision circuit D and provides the delayed squared modulus Δρ i-1   2 . The delay introduced by this delay memory is equal to the duration of the repetition period Tr. 
     When starting with received squared modulus Δρ i   2  and delayed squared modulus Δρ i-1   2  this decision circuit elaborates its output variable, but it can only do it after having tested the information &#34;no short pulse&#34; or preceding PIB. These PIB informations are elaborated by the decision circuit D. A first delay memory M1 of this PIB information provides to this decision circuit the delayed PIB i-1  information starting with the PIB i  information which has been furnished to it one instant t-Tr sooner. A second delay memory M2 of this PIB information provides to this decision circuit the twice delayed PIB i-2  information starting from the received PIB i-1  delayed information of the first delay memory MI. 
     A more detailed block diagram of this decision circuit D is shown in FIG. 4, showing also a treatment relating to the range gate of index j and by not showing this index on the figure. This decision circuit has two adder-subtractors Σ +  and Σ -  receiving on the one hand the delayed squared modulus Δρ i-1   2  and on the other hand the constant K, K being a measurement noise threshold. These adder-subtractors effect respectively the sum (Δρ i-1   2  +K) and the difference (Δρ i-1   2  -K) and provide respectively this sum and this difference to the inputs B of first and second comparators C +   and C - . 
     The inputs A of this first and this second comparators receive the squared modulus Δρ i   2  provided by the calculator of modulus CM (FIG. 3). If the squared modulus Δρ i   2  furnished is greater than the quantity (Δρ i-1   2  +K), the first comparator C +   will furnish on its output A&gt;B a binary element at logic level 1. If the squared modulus Δρ i   2  furnished at the input A of comparator C -   is lower than the quantity (Δρ i-1   2  -K) this second comparator C -   will furnish at its output A&lt;B a binary element at logic level 1. The outputs of first and second comparators C +   and C -  are furnished to a logic circuit L which tests whether one or the other of these outputs is at logic level 1 and, in this case, to test also the state of the test delayed binary element of short pulse PIB i-1  furnished by the first memory M1 and twice delayed binary element PIB i-2  furnished by the second memory M2. 
     Each of memories MP and MQ should be able to store as many memory words, a ij  or b ij  as these are range gates cut off based on the duration of the repetition period of the radar. The number of binary elements that have these memory words will depend from the step of numerization of the components a ij  and b ij  chosen. The calculator of modulus CM furnishes to the memory modulus Mm the successive values of squared modulus Δρ ij   2  of the vector difference ΔV ij  =V ij  -V i-1  j. It will be the same for this memory which should also be able to store as many memory words as there are range gates. The first and second memories M1 and M2 contain the binary elements PIB ij . They must be able to contain as many binary elements as there are range gates. 
     While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not to be limited to the disclosed embodiments but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures.