Electronic digitized proportional-integral controller
FIELD OF THE INVENTION 
     The present invention relates to an electronic proportional-integral controller for controlling the speed of an electric motor, more particularly a d.c. motor, in accordance with the frequency of a reference signal. Controllers of this kind are used for controlling the various drive units in a copying machine. 
     BACKGROUND OF THE INVENTION 
     It is important that the movements of various units in a copying machine such as the optical scanning system, the image recording medium, the paper transport system and the like, should be accurately synchronized with one another to produce high quality copies. Generally, this synchronization is achieved by driving all the units or components of the copying machine by a common drive unit having a single transmission. Since, however, this necessitates an expensive transmission design, it is desirable to separate the drives for the various units so that the copying machine construction is simplified, the ease of servicing is increased and the inert masses required to be moved during the operation of the copying machine are reduced. The separate drivves for the various units, however, have to be synchronized electronically. One way this can be achieved is by sensing the speed of one of the drive units, such as the motor for the image recording medium, and using it to generate a reference signal, which is used to control the speeds of the drives of the other units. 
     Separate drives for the various units necessitate controllers which can easily be adjusted at any time to the conditions of the control system such as the power of the drive motor, the inertia of driven parts and the like. The controllers also need to allow substantially immediate adjustment of the speed of the controlled motor or drive to the reference frequency within close tolerances. 
     Typically these controllers have a speed sensor for generating a speed signal the frequency of which represents the motor output speed, a proportional circuit which generates a proportional control (P-control) signal corresponding to the difference between the frequencies of the reference signal and of the speed signal, an integrator which generates an integral control (I-control) signal corresponding to the time integral of the difference between the frequencies of the reference signal and of the speed signal, an adder, which generates an output signal corresponding to the sum or the weighted sum of the two control signals (P-control and I-control), and an output stage for controlling the motor in accordance with the adder output signal. Controllers of this kind can be made using either analog or digital components. 
     Although analog controllers allow rapid signal processing and hence a low delay time for the control system, they have the disadvantages that the accuracy of the control is limited and the adjustment to the conditions of use at any time is a relatively laborious operation requiring the balancing of resistors and the like. 
     In contrast, digital control systems have high accuracy and little liability to trouble while being relatively cheap. In digital control systems, the input variables such as the frequency of the reference signal and the scanned actual speed signal are usually quantified and then arithmetic operations are carried out to form the set-value/actual-value difference used to generate the proportional component and the integral component, and to form the final control signal. Since these operations require some computer time, the control time is relatively long. It would be desirable, therefore, to have a digital control system which had a short control time. 
     SUMMARY OF THE INVENTION 
     Generally, the present invention provides a versatile digital proportional-integral controller having a short control time and a high long-term stability, and which can be adjusted to different conditions of use within a wide range. As a result of these properties, the controller according to the present invention makes it possible to provide a copying machine with separate drives for the various subsystems while guaranteeing accurate synchronization of the subsystems. 
     According to the present invention, a proportional-integral controller uses a speed signal from the controlled motor and a reference signal from a reference signal generator, preferably a reference drive, to generate a motor control signal. The controller has a proportional circuit and an integrator circuit which are each formed by a logic circuit and an up/down counter. The counters receive the up and down counting pulses from the preceding logic circuit which directly utilizes the speed signal and the reference signal. 
     The proportional circuit is based on the operating principle that the speed signal and the reference signal are converted to standardized signals, wherein the pulse width of each corresponds to the cycle time of the original speed signal or reference signal, respectively. If, during the speed signal cycle, the reference signal cycle has not yet started or has already ended, the counter counts up at a predetermined clock frequency. If, conversely, during the reference signal cycle, the speed signal cycle has not yet started or has already ended, the counter counts down at the same frequency. On completion of the last of the two cycles, the contents of the counter is used for further signal processing and the counter is reset so that a new counting cycle can start. In this way, an output signal proportional to the difference between the cycle times is generated at very short intervals on the order of magnitude of the speed signal and reference signal cycles. 
     The counter of the integrator circuit counts up on each rising flank of the speed signal and counts down on the rising flank of the reference signal. As a result, the content of the integrator counter at any time indicates the integral value of the difference between the frequency of the speed signal and the frequency of the reference signal. 
     If required, the logic circuits of the proportional circuit and the integrator circuit may contain suitable buffer means to prevent the counter capacity from being exceeded or undershot, (i.e. contents of the counter less than zero) and to prevent the simultaneous feed of an up and down counting pulse to the counter. 
     With its simple circuit construction and short control time, the present invention uses steps which guarantee reliable and trouble-free signal processing and increases the adjustability of the controller to different requirements and operating conditions. Preferably, different sets of coordinated adjustment parameters for the control system can be stored and selected at any time according to different requirements by means of suitable control commands. 
     Other advantages of the present invention will become apparent from the following detailed description and accompanying drawings of a presently preferred embodiment of the best mode of carrying out the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram of a control system using a proportional-integral controller according to the present invention. 
     FIG. 2 is a block schematic of the controller shown in FIG. 1. 
     FIG. 3 is a circuit diagram of an asynchronous/synchronous converter. 
     FIG. 4 is a circuit diagram of a proportional circuit for the controller shown in FIG. 2. 
     FIG. 5 is a time diagram of signals of the proportional circuit. 
     FIG. 6 is a circuit diagram of an integrator circuit for the controller shown in FIG. 2. 
     FIG. 7 is a time diagram of signals of the integrator circuit. 
     FIG. 8 is a circuit diagram of a multiplier network. 
     FIG. 9 is a circuit diagram of a frequency divider and a chain of shift registers for controlling the frequency divider and other components of the controller. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In a preferred embodiment of the present invention a command unit compatible with a two-wire bus system is provided for the storage of the adjustment parameters and for transmitting the control commands. A bus system of this kind is described in U.S. Pat. No. 3,889,236 and in European Pat. No. 0,051,332 and is known as an I 2  C bus. In addition, to commands for the basic adjustment, start of operation, controller operation interruption and the like, commands for switching the controller to test operation can also be input via the bus system and via the command unit connected as a receiver to the bus system, so that the controller can be tested for correct operation. 
     The entire controller is preferably constructed as an integrated component. This reduces manufacturing costs and gives a compact construction and facilitates controller installation. 
     FIG. 1 diagrammatically illustrates a control system containing a proportional-integral controller (PI-controller) 100 according to the present invention wherein a d.c. motor 102 is used, for example, to drive a subsystem such as a shaft 108 in a copying machine. A speed sensor 104 senses the speed of motor 102 and generates a speed signal f m  in the form of a pulse signal whose frequency is proportional to the motor speed. The speed signal f m  is used by the PI-controller to generate the signal for controlling motor 102. The output frequency of speed sensor 104 should as far as possible be greater than 500 Hz. Another speed sensor 110 senses the speed of a shaft 112 of another subsystem of the copying machine. The subsystem containing shaft 112 constitutes a guide or reference system such that the speed of motor 102 is to be synchronized with the speed of shaft 112. 
     The output frequency of speed sensor 110, which is also about 500 Hz, is increased by a given factor, such as the factor 224, in a frequency multiplier 114. Frequency multiplier 114 is preferably formed by two phase locked loops (PLL) which successively multiply the frequency by the factors 14 and 16. The output signal of frequency multiplier 114 forms a reference signal f r  which is used by the PI-controller to generate the signal for controlling motor 102. 
     PI-controller 100 receives speed signal f m  and reference signal f r  and delivers a binary signal U D , which represents the desired direction of movement of motor 102, and a pulse signal U p  of variable pulse width, to a bridge circuit 106 (H-bridge) which controls motor 102. The speed of motor 102 is adjusted to a value proportional to reference signal f r  by means of PI-controller 100 by variation of the useful width of pulse signal U p . In this way the movement of shaft 108, driven by motor 102, is synchronized with the movement of shaft 112. 
     The frequency of reference signal f r  is reduced by a suitable factor, such as 224, by a frequency divider 115 integrated in PI-controller 100. This allows for finely graduated adjustment of the transmission ratio between the speeds of shafts 112 and 108. The rotation of motor 102 can be synchronized with the rotation of shaft 112 with an accuracy of 0.2%. 
     PI-controller 100 is formed by an integrated circuit (3 μm C-MOS) constructed in the standard cell technique. Referring to FIG. 2, PI-controller 100 comprises: a frequency divider unit FRD by means of which the frequency of reference signal f r  is reduced in accordance with a preset frequency ratio; a controller unit CNT for processing speed signal f m  and frequency-supported reference signal f rl  ; an output stage ET, which delivers the output signals U D  and U p  to bridge circuit 106; a clock generator D; and a command unit COMM for controlling the function and operation of PI-controller 100. 
     Reference signal f rl  processed by frequency divider unit FRD is fed to an asynchronous/synchronous converter C 1  which synchronizes reference signal f rl  with a clock signal f sl  generated by clock generator D and transmits synchronized reference signal f ru  to a proportional circuit P and an integrator I. Referring to FIG. 3, the asynchronous/synchronous converter C 1  is formed by a flip-flop which is controlled by clock signal f s1 . An asynchronous/synchronous converter C 2  of identical construction to converter C 1  synchronizes speed signal f m  with clock signal f s1  and delivers synchronized speed signal f mu  to proportional circuit P and integrator I. 
     Proportional circuit P generates a proportional signal d p  in the form of an eight-bit two-complement signal which is dependent upon the difference in the cycle lengths of signals f ru  and f mu . Integrator I generates an integral signal d I  in the form of an eight-bit signal which is dependent upon the difference in frequency between signals f ru  and f mu . Integral signal d I  is multiplied by the factor 2 0 , 2 1  or 2 2  in a multiplier (shifter) S 1  depending upon the state of two binary control signals c and d. The multiplication results in the bits of integral signal d I  being moved to the left by 0, 1 or 2 digits. The integral signal multiplied in this way is added to the proportional signal d p  in an adder A 1 . The 9-bit line of proportional circuit P can be so switched to adder A 1  that the proportional signal is shifted by one or two binary places, corresponding to a multiplication of this signal by a factor 2 1  or 2 2 . The sum signal d A1  generated by adder A 1  is fed to output stage ET in response to a read command e 2  generated by proportional circuit P. 
     Output stage ET comprises a latch L 1  which receives and stores (latches) the sum signal d A1  of adder A 1  and in due course transmits it to a pulse width modulator PWM. An amplitude register A contains a preset amplitude signal d A  in the form of an 8-bit signal which is fed to pulse width modulator PWM via a shifter S 2 . Shifter S 2  corresponds to shifter S 1  in construction and function. 
     Pulse width modulator PWM generates direction signal U D  and output signal U p . The pulse width of output signal U p  is proportional to signal d L  taken from the latch L 1  and the cycle time of output signal U p  is proportional to the amplitude signal d S2  prepared by shifter S 2 . During the data transmission from latch L 1  to pulse width modulator PWM, a signal cprop prevents proportional circuit P from generating read command e 2 . 
     The preferred construction and operation of proportional circuit P will now be explained with reference to FIGS. 4 and 5. Preferably, proportional circuit P uses an up/down counter 200 and a logic circuit 202 which delivers the up and down counting commands for counter 200 depending upon synchronized speed signal f mu  and reference signal f ru . In addition to the synchronized speed and reference signals, the input signals received by logic circuit 202 include cprop, a reset signal R 3 , clock signal f s1  and another clock signal f s2 . The two clock signals f s1  and f s2  have the same frequency but are phase-shifted by a half-cycle as will be apparent from FIG. 5. The two clock signals may, for example, be produced from a rectangular signal of twice the frequency and with a clock ratio of 0.5. 
     As shown in FIG. 4, synchronized speed signal f mu  is fed as a clock signal to flipflop 1, whose input is connected to the inverting output Q 1 . Thus, output Q 1  of flipflop 1 changes its state on each rising flank of speed signal f mu . The pulse width of output signal Q 1  is independent of the pulse width of speed signal f mu  and coincides with the cycle length of speed signal f mu . Output signal Q 1  should therefore be designated as a standardized speed signal. Flipflop 4 functions in the same manner as flipflop 1. Flipflop 4 receives synchronized reference signal f ru  as a clock signal and generates a standardized reference signal Q 4 . 
     The upward counting input UP of counter 200 is connected to the output of a NAND gate 204 which receives as an input signal: standardized speed signal Q 1  ; inverted standardized reference signal Q 4 , clock signal f s2  and a signal ov. Signal ov normally has the value 1 and is set to 0 by a logic circuit 206 only when counter 200 has reached its top capacity limit (i.e.&gt;+255). NAND gate 204 thus generates an upward counting pulse (logic 0) in synchronism with clock signal f s2  when standardized speed signal Q 1  has the value 1 and standardized reference signal Q 4  has the value 1. 
     The downward counting input DOWN of counter 200 is connected to the output of a NAND gate 208 which receives signals f s2 , Q 4  Q 1  and uv as input signals. Input signal uv is generated by a logic circuit 210 and is used to protect counter 200 against falling below the bottom capacity limit (i.e.&lt;-256). NAND gate 208 generates a downward counting pulse in synchronism with clock signal f s2  when standardized reference signal Q 4  has the value 1 and standardized speed signal Q 1  has the value 0. The details of logic circuit 202 described hereinafter serve to terminate the counting operation after a complete cycle of both speed signal f mu  and reference signal f ru  have occurred. 
     A flipflop 3 receives signal Q 1  as its input signal and delivers output signal Q 3  which resets flipflop 1. Flipflop 3, however, is controlled by clock signal f s2 , while speed signal f mu  is synchronized with clock signal f s1 . Reset signal Q 3  therefore does not occur until some delay after the completion of one cycle of speed signal f mu , that is after the decay of standardized signal Q 1 . See FIG. 5. A flipflop 2 controlled by clock signal f s1  receives input signal Q 1  +Q 3  (where &#34;+&#34; represents a logic OR) via a NAND gate 212. Flipflop 3 is reset by the inverted output signal Q 2  of flipflop 2. Output signal Q 2  of flipflop 2 assumes the value 1 as soon as signal Q 1  assumes the value 1. When signal Q 1  falls again, Q 2  retains the value 1 since then Q 3  =1. Flipflop 2 remains in the set state until it is reset by a signal R b  . Signal Q 2  thus indicates that signal Q 1  has occurred once. 
     Flipflops 5 and 6 are in the same relationship to flipflop 4 as flipflops 2 and 3 are to flipflop 1 and function in the same way as described above. Output signal Q 5  of flipflop 5 indicates that standardized reference signal Q 4  had the value 1 once. 
     When both speed signal f mu  and reference signal f ru  have passed through a complete cycle, signals Q 1  and Q 4  have the value 0 while signals Q 2  and Q 5  have the value 1. Under this condition the output of an AND gate 214 has the value 1. If signal cprop also has the value 1, a flipflop 7 controlled by clock signal f s2  is set. An AND gate 216 receives output signal Q7 of flipflop 7 and when the next clock signal f s1  arrives, generates read command e 2  by means of which the contents d p1  -d p9  of counter 200 are taken over by latch L 1  after addition with the signal d s1  of shifter S 1  as shown in FIG. 2. At the same time, a flipflop 8 controlled by clock signal f s1  is set by output signal Q 7 . On coincidence of output signal Q 8  of flipflop 8 with clock signal f s2  a signal R a  is generated which is combined with signal R 3  by a logic OR and is fed as a signal R b  to the reset inputs of counter 200 and flipflops 2 and 5. The next counting operation can thus begin as soon as either a pulse of speed signal f mu  or a pulse of reference signal f ru  arrives and the corresponding standardized signal Q 1  or Q 4  resumes the value 1. 
     The preferred construction and operation of integrator I will now be explained with reference to FIGS. 6 and 7. Preferably, integrator I uses an up/down counter 300 with 8 bits and a logic circuit 302 for generating the up and down counting pulses. The input signals received by logic circuit 302 are clock signals f s1  and f s2 , synchronized speed signal f mu , synchronized reference signal f ru , a reset signal R 2  and signals c and d which control the multiplication factor of shifters S 1  and S 2 . 
     Clock signal f s2  controls flipflops 11 and 13 which respectively receive speed signal f mu  and reference signal f ru . Clock signal f s1  controls flipflops 12 and 14 which respectively receive output signal Q 11  of flipflop 11 and output signal Q 13  of flipflop 13. Upward counting input UP of counter 300 is connected to a circuit of logic gates 304 which have a NAND function. The input signals of circuit 304 are: inverted output signal Q 12  of flipflop 12; clock signal f s2  ; speed signal f mu  ; a signal b; and a signal ov&#39;. The significance of signals b and ov&#39; will be discussed later. At this stage it will be assumed that these signals have the value 1. When the state of signal f mu  changes from 0 to 1, an upward counting pulse of logic 0 is generated on the next clock pulse f s2 . Before the arrival of the next clock pulse f s2 , signal Q 12  drops so that the other counting pulses are suppressed until the associated cycle of signal f mu  is over. Thus only exactly one counting pulse is generated for each speed signal cycle. 
     Similarly, a circuit of logic gates 306 which have a NAND function generate exactly one downward counting pulse for each cycle of reference signal f ru  if input signals a and uv&#39; have the value 1. Logic circuit 306 functions in a similar manner to logic circuit 304. 
     The signals a=f mu  ·Q 12  and b=f ru  ·Q 14  (where represents a logic AND) prevent counter 300 from simultaneously receiving an upward and a downward counting pulse. Signal a assumes the value 0 when the conditions for an upward counting pulse are present, and in that case blocks the generation of a downward counting pulse. Signal b assumes the value 0 when the conditions are present for a downward counting pulse and in that case blocks the generation of the upward counting pulse. In addition, signals a and b control the transmission of read command e 1  to output stage ET. Read command e 1  is generated by an AND gate 310 which receives clock signal f s1  and signals a and b after they have been processed through a NAND gate 308. 
     Signals ov&#39; and uv&#39; are generated by logic circuits 312 and 314, respectively, and are intended to protect counter 300 from exceeding the top capacity limit or bottom capacity limit, respectively. Signal ov&#39; generated by logic circuit 312 is dependent not only upon output signals d I1  -d I8  of counter 300, but also upon signals c and d. When the multiplication factor in shifter S 1  is set to 2 1  or 2 2  by signals c and d, the capacity of counter 300 is artificially reduced by one or two binary digits respectively to prevent the capacity from being exceeded in shifter S 1 . If the capacity of counter 300 is exceeded or undershot, a NAND gate 316 delivers a signal L which is transmitted as a fault signal to the superior control system. 
     Shifter S 1  is built substantially of NAND gates. The circuit details and configuration are typical and will be clear from FIG. 8. 
     If controls signals c and d both have the value 0 or 1, the 8-bit signal d I  indicating the contents of the counter 300 remains unchanged (i.e. d S1  =d I ). If, however, signal c has the value 0 and signal d has the value 1, integral signal d I  is multiplied by the factor 2 1  (i.e. d S11  =0, d S12  =d I1 , d S13  =d I2 , etc). If signal c has the value 1 and signal d has the value 0, integral signal d I  is multiplied by the factor 2 2  (i.e. d S11  =0, d S12  =0, d S13  =d I1 , d S14  =d I2 , etc). 
     Shifter S 2  also receives control signals c and d and causes amplitude signal d A  to vary in accordance with the variation of integral signal d I . Control signals c and d, therefore, provide a simple means for adjusting the weighting of the proportional component and the integral component in the controller according to the present invention in order to adapt the control characteristic to the specific control system. 
     The present controller also affords the possibility of setting different speeds for the controlled motor. The division ratio of the frequency divider unit FRD can be varied, thereby reducing the frequency of reference signal f r . As can be seen in FIG. 2, frequency divider unit FRD comprises a frequency divider D 1 , which can be operated with selectable division ratios between 1:1 and 1:255. Two different division ratios for frequency divider D 1  can be stored in two shift registers D f1  and D f2 . Switching between the two shift registers D f1  and D f2  is possible by means of a binary control signal a 1  so that frequency divider D 1  operates either with the division ratio stored in shift register D f1  or with the division ratio stored in shift register D f2 . 
     Clock generator D comprises an oscillator OSC which delivers a signal f c1  at a frequency of 10 MHz to a frequency divider D 2 . Frequency divider D 2  delivers a number of parallel frequency signals which are produced by frequency division with different division ratios in the range from 1:4 to 1:56 from the frequency of signal f c1 . A multiplexer M 1  receives seven different frequency signals from frequency divider D 2  and selects one of these frequency signals depending upon a 3-bit signal DFm 1 . 
     The selected frequency signal f pwm  is fed as a clock signal to output stage ET. Another multiplexer M 2  receives fifteen different signals from frequency divider D 2  and selects one of these fifteen frequency signals depending upon a 4-bit signal DFm 2 . The selected frequency signal is fed to a frequency divider D 3 . Frequency divider D 3  comprises a flipflop which halves the frequency of the selected frequency signal delivered by multiplexer M 2 . Phase-shifted clock signals f s1  and f s2  are generated by a NOR combination of the output signal of multiplexer M 2  and the inverting and non-inverting output of the flipflop in frequency divider D 3 . 
     Signals DFm 1  and DFm 2 , which determine what frequencies are selected as the outputs of multiplexers M 1  and M 2 , are delivered either by a shift register Df 3  or a shift register Df 4 . The selection of shift register Df 3  or Df 4  is controlled by a signal a 1  which also controls the selection of shift registers Df 1  and Df 2  of frequency divider unit FRD. 
     In this way, when PI-controller 100 is switched to a different speed, clock signals f pwm , f s1  and f s2  are also automatically adapted to the new conditions so that controller adjustment is maintained. In particular, the change of clock frequencies f s1  and f s2  also adjusts the proportionality factor in proportional circuit P since clock frequency f s2  forms the counting frequency of counter 200 in proportional circuit P. 
     As can be seen in FIG. 9, shift registers Df 1 , Df 2 , Df 3 , Df 4  and amplitude register A are connected in series and to a common clock signal SCL. On initialization of the controller, the data to be stored in these registers is fed in the form of a serial data signal SDA and is transmitted through shift registers Df 1  -Df 4  and A. Upon operation of controller 100, the contents of shift registers Df 1  or Df 2  are transmitted to frequency divider D 1  and signals DFm 1  and DFm 2  which control multiplexers M 1  and M 2  are transmitted from shift register Df 3  or Df 4 . The transmission of signals from Df 1  or Df 2  and Df 3  or Df 4  is effected via electronic switches which are controlled alternately by signal a 1 . 
     An advantageous modification of the preferred embodiment described herein is possible by forming shift registers Df 1  -Df 4  and amplitude register A as parallel registers to which the data is fed for storage in parallel via a bus. 
     Command signal a 1 , serial data signal SDA and clock signal SCL are generated by command unit COMM. Command unit COMM also generates control signals c and d for shifters S 1  and S 2  and reset signals R 1  -R 5  for resetting the individual controller components, and a signal h which controls the direction of rotation of the motor. 
     Command unit COMM communicates with a superior control system via an I 2  C-bus. This bus is a two-wire data transmission system over which a data signal and a clock signal, or a control signal are transmitted. During transmission of data, the data and clock signal are so modulated that the signals in the two wires of the bus always have opposite polarity. However, during transmission of control signals which, for example, indicate the start or the end of a data transmission, the signal is so modulated that the two wires of the bus have the same polarity. In this way it is possible to distinguish between data signals and control or command signals. 
     Command unit COMM comprises an I 2  C interface which during data transmission recovers the clock signal and the data signal from the modulated signals of the two bus channels. On initialization of the controller, the clock signal is transmitted to shift registers Df 1  -Df 4  and A and the next five data bytes are read serially into these shift registers. Further commands such as commands for switching the controller on and off, changing the speed (change of state of signal a 1 ) and for changing the multiplication factor of shifters S 1 , S 2  (change of state of signals c and d) can then be transmitted via the I 2  C bus. The commands or data transmitted to the command unit COMM can also be acknowledged via the I 2  C bus. Similarly, status signal L which indicates the status of counter 300 of integrator I can be sent back to the superior control unit. 
     Command unit COMM also comprises I/O ports h, i, j and k. Controller 100, therefore, can alternatively be controlled via parallel lines connected to I/O ports h, i and j. I/O ports h, i, j and k also serve for carrying out test operations. If the signal 1 is applied to port i, command unit COMM delivers clock signals f s1 , f s2  and f pwm  to ports h, k and j, respectively. If the signal 0 is applied to the port i, synchronized speed signal f mu  and reference signal f ru  are sent back via ports h and k, respectively. 
     The controller can also be adjusted to operate only as a P-controller or only as an I-controller. 
     The invention is not limited to the above-described presently preferred embodiment. With the teachings disclosed herein, one skilled in the art will be able to carry out numerous modifications of the present invention which has been shown and described with particularity. Such modifications are also embodied within the scope and protection of the following claims.