High-resolution A/D converter
BACKGROUND OF THE INVENTION 
     The present invention relates to an analog-to-digital converter. 
     The invention of this type has heretofore been proposed comprising, as shown in FIG. 2, an adder or a subtractor 3 which adds or substracts an input signal from an analog signal input terminal 1 and an analog output from a D/A converter 7, an amplifier 4 for amplifying the analog output of said adder or said subtractor 3, an A/D converter 5 which converts the analog output of said amplifier 4 into a digital value, and a processor 6 which reads the digital output of said A/D converter 5 and which determines a digital output for said D/A 7 converter. 
     According to the above-mentioned prior art as is widely known, there is no guarantee that a bit width of the D/A converter at a minimum resolution is maintained perfectly uniform. Namely, any variance in the bits from the D/A converter is amplified through the amplifier, and the continuity of data is lost in the final output of the A/D converter. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide a high-resolution A/D converter. 
     Other and further objects, features and advantages of the invention will become apparent from the following description. 
     The present invention was developed in order to accomplish the above-mentioned object, and is chiefly comprised of a first D/A converter, a switch for selecting an analog output signal from said first D/A converter and an analog signal from an analog signal input terminal, a second D/A converter, a subtractor which performs the addition or subtraction of an analog signal that has passed through said switch and an analog output signal from said second D/A converter, an amplifier for amplifying the analog output signal of said subtractor, an A/D converter for converting the analog output signal of said amplifier into a digital signal, and a processor which reads the digital output signal of said A/D converter and provides digital input signals to said first and second D/A converters. 
     In the above-mentioned structure, the processor, first, selects the first D/A converter as an input through the switch, and alternatingly and successively changes the output values to the first and second D/A converters. The processor further reads the digital outputs from the A/D converter to store minimum bit widths of the first and second D/A converters. Based upon the thus stored values, the processor corrects the output from the second D/A converter when the analog signal from the analog signal input terminal is selected as an input through the switch, and combines it with the digital signal output from the above A/D converter to form a digital signal in order to accomplish a high degree of resolution. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram illustrating an embodiment of the present invention; and 
     FIG. 2 is a circuit diagram illustrating the prior art. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The invention will now be described in detail with reference to an embodiment shown in FIG. 1, wherein reference numeral 7a denotes a first D/A converter, 7b denotes a second D/A converter, and 1 denotes an analog signal input terminal. Reference numerals 2 denotes a switch for selecting an analog signal from the analog signal input terminal 1 or an analog output signal from the first D/A converter 7a, and reference numeral 3 denotes a subtractor for subtracting the analog signal selected by the switch 2 and the analog output signal of the second D/A converter 7b. Reference numeral 4 denotes an amplifier for amplifying the analog output signal of the subtractor 3, 5 denotes an A/D converter for converting the analog output signal of the amplifier 4 into a digital signal, and 6 denotes a processor which reads the digital signal input from the A/D converter, and sends digital signals to the first D/A converter 7a and to the second D/A converter 7b. 
     First, the analog output signal of the first D/A converter 7a is selected by the switch 2 and is sent to the subtractor 3 which produces an analog signal that is obtained by subtracting an analog input signal of the second D/A converter 7b from the analog signal of the first D/A converter 7a. The analog output signal of the subtractor 3 is amplified by B times through the amplifier 4, input to the A/D converter 5, converted into a digital signal, and is read by the processor 6. Digital signal outputs from the processor 6 are fed to the first D/A converter 7a and to the second D/A converter 7b and the digital signal outputs are alternatingly and successively changed from 0 to a maximum value m as tabulated below, and digital output values from the A/D converter 6 that are read are denoted by A 0  to A 2m . From the relationships of this table, the bit widths d n   1  and d n   2  of the first D/A converter 7a and the second D/A converter 7b are given by the following equations. 
     
                                           TABLE                                   
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Digital output                                                            
         0 1 1 2 2 3 3 . . .                                              
                         n - 1                                            
                             n   n  n + 1 . . .                           
                                          m - 1                           
                                              m   m                       
to the first                                                              
D/A converter 7a                                                          
Digital output Z                                                          
         0 0 1 1 2 2 3 . . .                                              
                         n - 1                                            
                             n - 1                                        
                                 n  n . . .                               
                                          m - 1                           
                                              m - 1                       
                                                  m                       
to the second                                                             
D/A converter 7b                                                          
Digital input Y                                                           
         A.sub.0                                                          
           A.sub.1                                                        
             A.sub.2                                                      
               A.sub.3                                                    
                 A.sub.4                                                  
                   A.sub.5                                                
                     A.sub.6 . . .                                        
                         A.sub.2n-2                                       
                             A.sub.2n-1                                   
                                 A.sub.2n                                 
                                    A.sub.2n+1 . . .                      
                                          A.sub.2m-2                      
                                              A.sub.2m-1                  
                                                  A.sub.2m                
from the A/D                                                              
converter 5                                                               
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         d.sub.n.sup.1 =A.sub.2n-1 -A.sub.2n-2 (n=1, 2 . . . ,m)    (1) 
    
     
         d.sub.n.sup.2 =A.sub.2n -A.sub.2n-1 (n=1, 2 . . . ,m)      (2) 
    
     The bit widths are found from d 1   1  to d m   1  and from d 1   2  to d m   2  in compliance with the above equations (1) and (2) and are stored, whereby the bit widths of the first D/A converter 7a and of the second D/A converter 7b are learned, and the accuracy for reading the bit widths becomes equal to that of the A/D converter 5. 
     Next, an analog input signal applied to the analog signal input terminal 1 is selected by the switch 2 and is input to the subtractor 3 which produces an analog signal obtained by substracting the analog input signal of the second D/A converter 7b from the analog input signal of the analog signal input terminal 1. The analog output signal of the subtractor 3 is amplified by B times by the amplifier 4, input to the A/D converter 5, converted into a digital signal, and is read by the processor 6 which applies an offset to the analog signal that is input through the analog signal input terminal 1, so that the analog signal of the second D/A converter 7b amplified by B times through the amplifier 4 will lie within an input range of the A/D converter 5. The analog signal input to the analog signal input terminal 1 is converted by the processor 6 into a digital signal in accordance with the following equation, ##EQU1## where X: output signal obtained by digitizing an analog input signal, 
     y: output signal of the A/D converter 5, 
     Z: input signal to the second D/A converter 7b. 
     As described already, the reading accuracy of (A 2n  -A 2n-1 ) on the right side of the equation (3) is equal to the output (y) of the A/D converter 6. Therefore, the accuracy of output signal X is nearly the same as the output (y) of the A/D converter 6. By using an i-bit A/D converter and an amplifier of B times as described above, there is realized an A/D converter having a high resolution of up to i+(bit conversion value of B). According to experiments conducted by the inventors, there is obtained a high-resolution A/D converter having more than 20 bits when i=16 and B=64. 
     (Effects of the Invention) 
     According to the present invention which learns and corrects the characteristics of the D/A converters, difference of the individual D/A converters and change by the aging can be neglected, and a high degree of resolution can be achieved without impairing the continuity.