Electric power measuring devices
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to electrical power measuring devices. 
     More particularly the invention relates to such devices of the kind comprising: input means for producing first and second analogue signals respectively representative of the instantaneous values of a voltage and current supplied to a load; multiplier means for producing in response to said first and second signals a third analogue signal representative of the produce of said first and second signals; and converter means for producing in response to said third signal an output pulse signal having a pulse rate representative of the product of said voltage and current. Such a device is hereinafter referred to as a device of the kind specified. 
     It will be appreciated that by totalling the output pulses of such a device a measure of the energy consumed in the load may be obtained. 
     2. Description of Related Art 
     One feature of the design of known devices of the kind specified in the compensation of offsets in the output of the multiplier means. 
     To compensate for such offsets it has been proposed that the polarity of one of the first and second signals be periodically reversed at the input of the multiplier means, with a corresponding reversal in the device subsequent to the output of the multiplier means. Such an arrangement is described, for example, in U.S. Patent Specification No. 4,500.973. 
     In known applications of this technique it is found that where the product of the first and secondn signals is small, i.e. the level of power consumption in the load is small, the pulse rae in the output signal becomes iregular. As a result calibration of the device becomes a slow process since at low power levels it is necessary to wait for a large number of outputs pulses to establish their average rate. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to overcome this problem. 
     According to the present invention, in a device of the kind specified to compensate for offset errors in said multipler means the polarity of one of said first and second signals is periodically reversed at the input to said multiplier means and corresponding reversals are effected at the input of said converter means. 
     A known form of converter means suitable for use in a device according to the present invention includes a capacitor which during successive charging periods of equal duration is charged by an input signal and by a much larger reference signal, the direction of which reference signal reverses at the end of each perriod until the charge on the capacitor does not reverse polarity during a charging period. The direction of the reference signal is then not reversed for the next charging period to ensure a reversal of the polarity of the capacitor charge during that next period, whereafter the direction of the reference signal is again reversed at the end of each charging period. The frequency of the occurrence of two successive charging periods in which the reference signal is of the same direction is then representative of the magnitude of the input signal. 
     Such a converter means is hereinafter referred to as a converter means of the kind specified. 
     One problem which arises when a converter means of the kind specified is used in a device according to the present invention is that the converter means input signal, i.e. the third analogue signal, is likely to be subject to variations due to manufacturing variations in the parameters of the circuits producing the third analogue signal, and variations due to ambient temperature variations in use, with consequent errors in the output pulse rate of the converter means. 
     To overcome this problem, in a device according to the present invention wherein said converter means is of the kind specified, said reference signal of the converter means is arranged to be effectively constituted by a bias signal component included in the output of said multiplier means in addition to said third analogue signal. 
     The said bias signal component included in the output of the multiplier means is suitably produced as a result of the application of bias signals to the inputs of the multiplier means so that athe multiplier means operates with signals of appreciable value irrespective of the values of said first and second signals i.e. the values of the voltage and current supplied to the load. This technique is known in devices of the kind specified. 
     Another problem which can arise when a converter of the kind specified is used in a device according to the present invention is that the offset compensation polarity reversals may not occur entirely randomly with respect to the charging periods of the converter capacitor. 
     To overcome this problem, in a device according to the present invention wherein said converter means is of the kind specified, the intervals between successive said reversals are varied in a predetermined manner with respect to the period of said successive charging periods of the converter capacitor so that, when said third analogue signal has a zero value, over two reversal cycles one reversal of each sense occurs during each of the two possible directions of charging of the converter capacitor. 
     A further feature of the design of known devices of the kind specified in the provision of means to ensure that no output pulse signal is produced when either one of said first and second signals is zero. It will be appreciated that this requirement is equivalent to the requirement that the disc of a Ferraris electricity meter should not creep round whilst the current input to the meter is zero. 
     In a device according to the present invention this function is suitably achieved by provioding inhibit means for inhibiting the output of said device unless the converter means output pulse rate exceeds a value corresponding to a predetermined value of the product of said first and second signals. Said inhibit means suitably comprises means for inhibiting the production of a pulse at the output of said device if the time which has elapsed since the last pulse at the output of the converter means is more than a predetermined value. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     One electrical power measuring device according to the invention will now be described, by way of example, with reference to the accompanying drawings in which: 
     FIG. 1 is a block schematic diagram of the whole device, and 
     FIG. 2 illustrates the operation of a current to frequency converter incorporated in the device of FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, the device comprises three basic sections 1, 3 and 5. 
     The first section 1 includes a voltage to current converter 7 which, in response to an input voltage v x  representative of the instantaneous value of the current supplied to a load, produces a pair of signals at terminals 9 and 11 respectively of the form I x  +i x  and I x  -i x , where i x  is a current which is representative of the input voltage v x  and I x  is a bias current derived from a source 13 having a value significantly greater than the maximum expected value of i x . 
     The first section further includes a current converter 15 which, in response to an input current i y  representative of the instantaneous value of the voltage at which the load is supplied with current, a pair of signals of the f orm I y  +i y  and I y  -i y , where I y  is a bias current derived from the source 13. 
     The first section further includes a reversing switch 17 operated at a freqqency f rev whereby the signals I y  -i y  and I y  -i y  are supplied either to a pair of terminals 19 and 21 respectively, or respectively to the terminals 21 and 19. 
     The second section of the device includes a Gilbert cell transconductance multiplier 23 having the currents at terminals 9, 11, 19 and 21 as inputs so as to produce at terminals 25 and 27 output currents I y  ±i xy  and I y  ∓i xy  respectively where i xy  is the product of current i x  and i y , the upper or lower signs occurring in dependence on the condition of the reversing switch 17. 
     The currents at terminals 25 and 27 are mirrored at a pair of terminals 29 and 31 by a current miroring circuit arrangement 33. The currents at terminals 29 and 31 are therefore K(I y  ±i xy ) and K(I y  ±i xy ) where K is approximately unity but varies with the manufacturing parameters of the relevant circuits and thereafter with ambient temperature. 
     The third section of the device comprises a current to frequency converter utilising the Delta-Sigma technique to produce an output pulse train in which the pulse rate is proportional to the current i xy . 
     The converter includes an integrating capacitor 35 which is connected across the terminals 29 and 31 via a reversing switch 37 operated in synchronism with the reversing switch 17. A reference current I sw  derived from the source 13 is selectively applied to the terminal 29 or 31 via a switch 39. The value of the reference current I sw  is controlled so as to have a value equal to the sum of the currents at terminals 29 and 31. 
     The charge on the capacitor 35 is monitored by a comparator 41, the comparator 41 producing a digital output indicating the polarity of the charge on the capacitor 35. The comparator output constitutes a data input to a latch 43 which has a clock input at a frequency f. The condition of the latch 43 determines the condition of the switch 39 via an exclusive -OR gate 45. The switch 39 is also operated in synchronism with the reversing switches 17 and 37 by application of a signal f rev to a second input of the exclusive -OR circuit 45. The converter further includes a reversible counter 47 which counts in response to an inut at the clock frequency f in a direction determined by the output of the latch 43. 
     The operation of the current to frequency convert will now be explained with reference to FIG. 2, ignoring at first the existance of the reversing switches 17 and 37, and the f rev input to the exclusive -OR gate 45. 
     Referring to FIG. 2, with the switch 39 in the position shown in FIG. 1, and the reference current I sw  set at a value 2KI y , the capacitor 35 is effectively charged by the current from terminal 31 only, (i.e. the difference between I sw  and the current from terminal 29), say K(I y  +o xy ), the capacitor voltage thus ramping in, say, an upward direction as indicated at 51 in FIG. 2A. 
     When the next clock pulse occurs this is counted by the counter 47 in a direction set by the output condition of latch 43, say in the up direction, as showon at 53 in FIG. 2D. In addition, if the comparator 41 monitors a positive charge on capacitor 35, the comparator 41 will apply `true` data to the latch 43, and the clock pulse will transfer this `true` data to the output of the latch. As a result, the counter 47 is set to count in the down direction and the position of the switch 39 is changed via gate 45. 
     The capacitor 35 is now charged in the reverse direction by the current K(I y  -i xy ) from terminal 29 (i.e. the capacitor is charged by a current K(-I y  ±i xy )) so that the capacitor voltage ramps downwards as shown at 55 in FIG. 2A. At the next clock pulse the counter 47 counts one in the down direction as indicated at 57 in FIG. 2D, and the comparator 41 monitors a negative charge on the capacitor 35. The comparator will therefore apply `false` data to the latlch 43, and the clock pulse will transfer this `false` data to the output of the latch, thus changing the position nof switch 39 via gate 45 and resetting the counter 47 to count in the up direction. The converter is thus returned to its orginal state except that the capacitor 35 has a charge greater than its original charge by the integral of K(i xy ) over two clock periods. 
     The above described procedure then repeats until the accumulated value of the charge due to K(i xy ) on capacitor 35 is such that when the latlch 43 is clocked the comparator 41 does not monitor a change in the polarity of the charge on capacitor 35 and latch 43 does not change its state. As a result the counter 47 counts in the up direction for a second time, as indicated at 59 in FIG. 2, and the switch 39 does not change its position. As a result the capacitor voltage ramps down for a second clock period, as indicated at 61 in FIG. 2A, thus ensuring that the above described procedure starts again at the next clock pulse. 
     The counter 47 is arranged to provide an output pulse each time its count reaches a predetermined value, whereupon the counter is reset to a second, lower, predetermined value. 
     The rate of advance of the counter, and hence the pulse rate of the output of the counter may be deduced as follows: 
     Take the charge on capacitor 35 at time t to be Q 1 . Considering N+M clock periods each Δt long for N of which the switch 39 is in the position shown in FIG. 1 so that the capacitor charging current ic is K(I y  +i xy ) and for M of which the switch 39 is in its other position so that the capacitor chargign current i c  is K(-(I y  -i xy )) =K(-I y  +i xy ). The charge Q 2  on the capacitor 35 at the end of the N +M clock periods is given by the expression ##EQU1## The accumulated increase ΔQ of charge on the capacitor is therefore ##EQU2## Since, in the long term, the value ofo Q is negligible the advance of the counter M-N is given by 
     
         ∫i.sub.xy dt/I.sub.y Δt 
    
     Hence the counter 47 provides an output pulse signal at a rate determined by 
     
         f.i.sub.xy /I.sub.y 
    
     It can be seen that by using as a reference current in the current to frequency converter a current KI y  which is the same as the output from the mirroring circuit 33 when its input is I y , i.e. the bias current component of the output of the mirroring circuit, the constant of proportionality K of the output of the multiplier and mirroring circuit arrangement 23, 33 has no effect on the calibration of the device. Thus, since both measured and reference terms pass through the mirroring arrangement, any scaling changes caused by the mirroring arrangement apply equally to each. In order that this be the case, the reference current I sw  is controlled by a signal derived from the comparator 41 so as to have a value equal to the sum of the currents at the terminals 29 and 31, i.e. a value equal to twice the value of the bias current component KI y  in the currents at terminals 29 and 31. 
     The operation of the reversing switches 17 and 37 will now be considered. 
     The operation of the switches 17 and 37 together effects cancellation of any offsets occurring in the i xy  component of the output of the multiplier 23. This is achieved as follows. If, for example, the offset effectively causes an increase in the value of the i xy  component when the reversing switch 17 is in one position, the offset will cause a corresponding decrease in ni xy  when the reversing switch 17 is in its other position so that offset error cancels over successive operation of the switch 17. The second reversing switch 37 operates in synchronism with the switch 17 to cancel the reversals in the polarity of the output of the multiplier produced by the switch 17. 
     A similar effect could be achieved if the reversing switch 37 were omitted and the direction of count of the counter 47 reversed in synchrronism with operation of the switch 17 as described in U.S. Pat. No. 4,500,793. However, this has the disadvantage that for a given load, each time the reversing switch 17 operates, the polarity with which the capacitor 35 accumulates charge due to i xy  reverses. As a result the pulse rate in the output of counter 47 becomes irregular. Such an irregular count has the disadvantage that for low levels of power consumption in the load, a long time is required to check that the average output rate is consistent with the level of power consumption, i.e. it takes a long time to calibrate the device at low levels of power consumption. 
     It will be appreciated that the period of reversal of the switches 17 and 37 is arranged to be long compared with the clock pulse period. 
     It will be understood that since the switch 37 reverses the direction of charging of the capacitor 35, a corresponding change in the position of the switch 39 is required each time the switch 37 is reversed. To this end the gate 45 is provided with an input at the frequency f rev. It will also be appreciated that the counter 47 is not required to reverse its counting direction each time the reversing switches 17 and 37 are operated. 
     It will be understood that whilst the above switching techniques will result in satisfactory operation of the device if the switching operations occur instantaneously at the precise times required, in practice there will be slight imperfections in the timing of the switching operations. The effect of such imperfections on the charging of the capacitor 35 and hence on the rate of counting of the counter 47 will vary according to the relative timings of the operation of the reversing switches 17 and 37 and the switch 39. To minimise this problem the times of operation of the switches 17 and 37 are arranged to occur at predetermined times relative to the operation of the switch 39. In particular the time between successive operations of the switches 17 and 37 varies over a two cycle period in the sequency (n -1) t f  ; n t f  ; (n +1) t f  ; n t f  where t f  is the clock cycle period and n=f/2f rev. As a result, with zero power consumed in the load of each set of four successive operations of the switches 17 and 37, one operation of one sense occurs whilst the capacitor 35 is charging positively, the other operation of that one sense occurs when the capacitor 35 is charging negatively, one operation of the other sense occurs when the capacitor 35 is charging positively, and the other operation of the other sense occurs when the capacitor is charging negatively. This regime also ensures the cancellation of charges injected by the operation of the switches 17 and 37. Any errors producd by switching errors thus tend to cancel out. It will be appreciated that whilst the desired relation between the timings of the operation of the switches 17 and 37 and the switch 39 will increasingly not be achieved as the power consumed in the load increases, the switching errors are then increasingly of less significance. 
     In order to prevent the occurrence of any spurious pulses at the output of the counter 47 when the power consumed in the load is zero, the opeation nof the counter is inhibited unless the power cosumed exceeds a small threshold value. 
     This is conveniently effected by preventing the propagation of count pulses from an inermediate bit stage of the counter 47 to the next more significatn bit stage of the counter 47 if the time which has elapsed since the last count pulse from the intermediate stage exceeds a predetermined value. 
     Referring to FIG. 1, to thi end the counter 47 is associated with a time out circuit 63 which produces a latched time out signal alt its output after the receipt of a predeterminend number of clock pulses at its input. The time ou signal serves to prevent the propagation of count pulses in the counter 47 as described above. The time ou circuit 63 is reset on each occurence of sucha count pulse. The output of the counter 47 is thus inhibited if the time between successive count pulses at the output of othe intermeidate bit counter stage is greater than the time taken for the predetermined number of clock pulses to occur. 
     It will be appreciated that a device in accordance with the invention, since it operates in response to instantaneous value of voltage and current may be used to measure power both in direct current circuits and alternating current circuits, and in the latter case takes account of power factor. In a device for se in a 50 Hz alternating current circuit, the value of f if typically 8000 per second and the value of f reve 256 per second.