High security evolutive coding process and device for carrying out this process
BACKGROUND TO THE INVENTION 
     This invention relates to an improvement to evolutive codings utilizing a pseudo-random discontinuous function. 
     Electronic codings for security devices, especially for remote control, belong to one of three main groups: 
     1. Fixed codes. 
     2. Codes that vary according to a continuous law. 
     3. Codes that vary according to a discontinuous law. 
     The first two types of code suffer from the serious disadvantage of permitting relatively easy violation by recording of the signal transmitted for the first group and by recording several signals in order to deduce the law of variation for the second group. 
     The codes of the third type possess a much higher level of security, because the code changes after each use in accordance with a discontinuous mathematical function as a result of the generating pseudo-random numbers, this law being different for each transmitter-receiver assembly and being linked to a specific base code. 
     Nevertheless, such discontinuous mathematical functions which generate pseudo-random numbers are of necessity restricted functions that draw lots between a minimum and a maximum value. The maximum value may be deduced relatively easily according to the number of bits transmitted. Systematic scanning of all the values up to the maximum value will generally enable the security device to be unlocked. 
     OBJECT OF THE INVENTION 
     An object of the present invention is to improve considerably the security of devices using such codings. 
     SUMMARY OF THE INVENTION 
     According to the invention there is provided an evolutive coding process utilizing a pseudo-random discontinuous function, wherein a message containing at least two pseudo-random values calculated by said function is transmitted. Preferably, said pseudo-random values are successive values of said pseudo-random discontinuous function. With advantage, the message contains, in addition, a code deduced by a continuous function from a specific base code for each system. 
     DESCRIPTION OF PREFERRED EMBODIMENT 
     If the specific base code of the system is termed C, it will be possible to obtain this code C by wiring (matrix) or by electronic memorisation of a number. 
     A transformation of continuous function T(C) of the code C is created electronically. 
     A discontinuous, pseudo-random function FA (C,N), dependent upon the code C and upon the number N of transmissions, is also created. 
     According to one example of embodiment of the invention, the message transmitted and which must be read to enable the system to be unlocked will be composed as follows. 
     
         T(C)+FA(C,n-1)+FA(C,n). 
    
     That is to say this message will comprise on each occasion a first portion T(C), which is the value of continuous function of the base code C, a second portion FA(C,n-1), which is the value of the pseudo-random, discontinuous function corresponding to the base code C for the (n-1)th transmission, and a third portion FA(C,n), which is the value of the same function for the nth transmission. 
     Since the function FA(C,n) is programmed into the transmission and reception microcomputers, it is known only to the designer, and the transmission number N, which is also memorised by the microcomputers, if no longer accessible. 
     If the upper limit of the pseudo-random draw is sufficiently high, for example 999,999 the probability of discovering the two values FA(C,n-1) and FA(C,n) by repeated attempts is extremely low, of the order of 10 -12  in this example. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The present invention includes a transmitter/receiver circuit for carrying our the process disclosed above, which circuit will now be described by way of example with reference to be accompanying circuit diagrams, FIGS. 1 and 2. 
    
    
     Referring to FIG. 1, the transmitter portion of the circuit comprises a logic unit 10 controlled by a clock generator 11, an EEPROM 12, an arithmetic unit 13, a half random function unit 14 between said logic unit 10 and the arithmetic unit 13, a parallel/serial converter 15 connected to the output of the arithmetic unit 13, and a driver 16 controlled by the output from the converter 14. 
     Referring to FIG. 2, the receiver portion comprises a serial/parallel converter 20 for receiving an input signal, an arithmetic unit 21, an EEPROM 22, a logic unit 23, the functions of which are controlled by a clock generator 24 and an output interface 25, said logic unit having control outputs connected respectively to the EEPROM, arithmetic unit, converter and the output interface 25 respectively.