Feedback source coupled FET logic
FIELD OF INVENTION 
     The present invention pertains to differential amplifiers and particularly to source coupled Field Effect Transistor (FET) logic gates having true and complement outputs. More particularly, the invention pertains to source coupled FET logic gates having feedback connections. 
     RELATED ART 
     Differential amplifiers and some applications of them to logic circuits are known in the art. Source coupled FET logic (SCFL) as implemented in differential amplifiers of logic circuits is known in the art as shown in FIG. 1. The latter circuits exhibit certain disadvantages including a low level of integration because of additional circuitry required to generate a reference voltage and of effects due to drifting voltage levels at varying high temperatures. The present invention obviates these disadvantages. 
     SUMMARY OF THE INVENTION 
     The present invention comprises feedback source coupled FET logic (FSCL), that is, an SCFL gate having a feedback path from an output to a voltage reference input. Additional circuitry is not needed to generate a reference voltage for the gate thus permitting a high level of circuit integration resulting in much higher chip density than that of conventional SCFL circuitry. The invention is self-thresholding with respect to inputs in that there is little voltage drifting with temperature change, which is a feature very desirable in high temperature applications. Also the invention has a noise to signal margin that is almost an order of magnitude better than conventional SCFL circuitry. The FSCL circuity of the invention may be constructed with FET&#39;s of any type of process including depletion, enhancement, or a combination of depletion and enhancement FET&#39;s. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an SCFL gate of the related art. 
     FIG. 2 is a gate incorporating the present invention. 
     FIG. 3a is an FSCL OR/AND amplifier circuit incorporating the present invention. 
     FIG. 3b is a logic diagram of the circuit shown in FIG. 3a. 
     FIG. 4a is a graph of an SCFL transfer curve. 
     FIG. 4b is a graph of an FSCL transfer curve. 
     FIG. 5 is a timing diagram illustrating various measured parameters in Tables 1 through 4. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The basic feature of the present invention 20 is illustrated in FIG. 2. A comparison of FIGS. 1 and 2 reveal a distinction which is an electrical connection 18 from node 12 to gate 16 of FET 14. FIG. 1 is an SCFL circuit which is a preferred circuit family for high speed digital systems. In FIG. 2, connection 18 is a feedback path from Q output at node 12 to V R  (reference voltage) input 16. Connection 18 avoids the need to generate the reference voltage for each gate. The circuit, with the feedback path 18, is self-thresholding with respect to inputs 16 and 22, and thus resulting in negligible voltage drift with temperature variation. The reference voltage is regulated. The reference voltage is a threshold voltage or a switching point for the input voltage at input 22 of FET 24. FET&#39;s 14 and 24 are the essentials of a differential amplifier or comparator. FET&#39;s 14 and 24 are preferably enhancement mode FET&#39;s. FET&#39;s 26 and 28 are pull-up loads for input FET&#39;s 14 and 24, respectively. FET&#39;s 26 and 28 have their drains connected to a positive voltage V DD  and have their gates and sources connected to the drains of input FET&#39;s 14 and 24, respectively. The sources of FET&#39;s 14 and 24 are connected to a drain of current sink FET 32. FET 32 has a gate and source connected to negative voltage V SS . Voltages V DD  and V SS  either may be both positive or both negative, or one positive and one negative, or one may be a zero voltage; as long as V DD  is sufficiently more positive than V SS  as to allow circuit 20 to function appropriately. The drain of FET 14 is connected to the gate of source-follower FET 34. The drain of FET 24 is connected to the gate of source-follower FET 36. The source of FET 34 is connected to series-connected voltage-level shifting diodes 44 which in turn are connected to output node 48 and to the drain of pull-down FET 38. The source of FET 36 is connected to series-connected voltage-level shifting diodes 46 which in turn are connected to output node 12 and to the drain of pull-down FET 42. FET 38 has a gate and a source connected to voltage V SS . FET 42 has a gate and a source connected to voltage V SS . 
     As to the operation of the invention, as illustrated in FIG. 2, one may initially assume V IN  at input 22 to be low or a logic &#34;0&#34;. FET 24 is off an the drain of FET 24 is high or a logic &#34;1&#34;, due to pull-up FET 28 connected to V DD . The input to the gate of FET 36 is high and FET 36 is on with current flowing through diodes 46 resulting in a high or a logic &#34;1&#34; at node 12. The output Q at node 12 is the complement of signal Q at the input node 22. The high signal at node 12 is presented to input 16 by connection 18. FET 14 is thereby on resulting in a current flow through FET&#39;s 26 and 32. The drain of FET 14 and the gate of FET 34 are low. FET 34 is off and the output Q at node 48 is held low by pull-down FET 38. The output Q at output node 48 and input 22 are similarly low. 
     On the other hand, one may assume V IN  at input 22 to go from a low to a high signal. The level at which FET 24 is effectively turned on is determined by the level of voltage at the sources of FET&#39;s 14 and 24 which in turn is determined by the reference voltage at gate 16 from connection 18. As the temperature of FET 24 varies, the switching threshold voltage remains constant because any variation of pinch-off voltage of FET 24 due to temperature variation is compensated for by variation of drain-to-gate voltage of FET 14 due to the same temperature variation. FET&#39;s 26, 28 and 32 are preferably depletion mode FET&#39;s. 
     The high signal at input 22 turns on FET 24 resulting in a low signal on the drain of FET 24 and on the gate of FET 36. FET 36 turns off and pull-down FET 42 pulls node 12 down resulting in a low signal on connection 18 and gate 16 of FET 14. FET 14 turns off with its drain going high and presenting a high signal to the gate of FET 34. FET 34 turns on thus resulting in node 48 going high with an output Q like input Q. 
     When V IN  voltage at input 22 goes low, FET 24 is switched off at a point according to the level of the reference voltage at gate 16. Temperature variation has little effect on the voltage level requirement to switch FET 24. The voltage level at the sources of FET&#39;s 32 and 42 compensate for each other in that the variations of drain to source voltages are the same at given temperatures. 
     The present invention may be extended or applied to logic circuitry 30 of FIGS. 3a and 3b. FIG. 3a illustrates a realization of the invention (FSCL) in a multiple input OR/AND gate 30. FIG. 3b is a logic diagram of the schematic of FIG. 3a. Since the feedback SCFL provides only one self-reference voltage level, other reference levels are still needed in the case of making an R-S flip-flop or an exclusive OR circuit using a series-gating approach. FIG. 3a shows another option to implement multi-level logic in this FSCL to perform logical functions at the front end without using any reference voltages. 
     Inputs 52 through 56 are connected to gates of FET&#39;s 54 through 58. FET&#39;s 54 through 58 have their drains connected together and their sources connected together. The drains are connected to voltage V DD  as defined above. The sources are connected to the drain of pull-down FET 62. The gate and source of FET 62 are connected to voltage V SS  as defined above. Line 64 is the output which is the disjunction or logic OR result of inputs 52 through 56 of OR gate 60. 
     Inputs 66 through 68 are connected to gates of FET&#39;s 72 through 74. FET&#39;s 72 through 74 have their drains connected together and their sources connected together. The drains are connected to V DD  as defined above. The sources are connected to the drain of pull-down FET 76. The gate and source of FET 76 are connected to voltage V SS  as defined above. Line 78 is the output which is the disjunction or logic OR result of inputs 66 through 68 of OR gate 70. 
     Gates 60 and 70 are only two of a multitude of OR gates represented by FIGS. 3a and 3b. The outputs 64 through 78 are connected to the inputs of AND gate 80. Output 64 is connected to the cathode of Schottky diode 82 and output 78 is connected to the cathode of Schottky diode 86. The other outputs of the remaining multitude of OR gates are respectively connected to cathodes of Schottky diodes. The anodes of all Schottky diodes 82 through 86 are connected to line 88. Line 88 is connected to the base and source of pull-up FET 84 which has a drain connected to voltage V DD . Line 88 is the output of AND gate 80 and is the conjunction or logic AND result of lines 64 through 74. Line 88 is connected to the FSCL gate amplifier-driver 90. 
     FSCL gate amplifier-driver 90 in FIGS. 3a and 3b comprises FSCL circuit 20 of FIG. 2 and FET source follower driver 40. FSCL circuit 20 is described above. Source follower driver 40 is optional and incorporated as a current driver in applications having high capacitance loading. The Q output at node 48 goes into the gate of source follower FET 92. The drain of FET 92 is connected to voltage V DD  and the source of FET 92 is connected to the drain of pull-down FET 96. The gate and source of FET 96 are connected to voltage V SS . The Q output of driver 40 is connected to the source of FET 92. The Q output at node 12 goes into the gate of source follower FET 94. The drain of FET 94 is connected to voltage V DD  and the source of FET 94 is connected to the drain of pull-down FET 98. The gate and source of FET 98 are connected to voltage V SS . The Q output of driver 40 is connected to the source of FET 94. The above circuit is preferably implemented in gallium arsenide (GaAs) integrated circuit technology. 
     FIGS. 4a and 4b show simulated direct circuit (DC) transfer curves of SCFL (FIG. 1) and FSCL (FIG. 2) respectively, at nominal temperature. FIG. 4a (SCFL) shows a reference voltage of 0.4 volt at the cross-over point of Q and Q, at an input voltage of 0.3 volt. A point of Q or Q above 0.4 volt represents a logic 1 or high and such point below 0.4 volt represents a logic 0 or low. The voltage gain of the SCFL circuit is: 
     
         A.sub.V =V.sub.OUT /V.sub.IN =0.60/0.15=4 
    
     FIG. 4b (FSCL) shows a reference or threshold voltage of 0.3 volt at the cross-over point of Q and Q, at an input voltage of 0.33 volt. A point above 0.3 volt represents a logic 1 or high and such point below 0.3 volt represents a logic 0 or low. The levels for high and low signals are much more distinct and stable for FSCL circuitry than for SCFL circuitry. The voltage gain of the FSCL circuit is: 
     
         A.sub.V =V.sub.OUT /V.sub.IN =0.60/0.02=30 
    
     This high voltage gain is a very much desired advantage for a high noise margin circuit. 
     
                       TABLE 1                                                     
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SIMULATED RESULTS OF SCFL                                                 
IN DEPLETION MODE GaAs I (.sup.--Q OUTPUT)                                
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PU     Q,SF,PD     CS      V.sub.H                                        
                                  V.sub.L                                 
                                        V.sub.SW                          
(um.sup.2)                                                                
       (um.sup.2)  (um.sup.2)                                             
                           (V)    (V)   (V)                               
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L × W                                                               
1 × 20                                                              
       1 × 30                                                       
                   1 × 60                                           
                           0.630  0.016 0.600                             
1 × 10                                                              
       1 × 15                                                       
                   1 × 30                                           
                           0.850  0.041 0.810                             
1 × 5                                                               
        1 × 7.5                                                     
                   1 × 15                                           
                           1.050  0.010 0.950                             
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P      t.sub.R     t.sub.F t.sub.ON                                       
                                  t.sub.OFF                               
                                        t.sub.PD                          
(mw)   (ns)        (ns)    (ns)   (ns)  (ns)                              
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18.50  0.15        0.15    0.13   0.12  0.125                             
10.10  0.18        0.21    0.13   0.11  0.120                             
 5.32  0.18        0.21    0.13   0.11  0.120                             
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                       TABLE 2                                                     
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SIMULATED RESULTS OF FSCL                                                 
IN DEPLETION MODE GaAs I (.sup.--Q OUTPUT)                                
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PU     Q,SF,PD     CS      V.sub.H                                        
                                  V.sub.L                                 
                                        V.sub.SW                          
(um.sup.2)                                                                
       (um.sup.2)  (um.sup.2)                                             
                           (V)    (V)   (V)                               
______________________________________                                    
L × W                                                               
1 × 20                                                              
       1 × 30                                                       
                   1 × 60                                           
                           0.616  0.016 0.600                             
1 × 10                                                              
       1 × 15                                                       
                   1 × 30                                           
                           0.860  0.040 0.820                             
1 × 5                                                               
        1 × 7.5                                                     
                   1 × 15                                           
                           1.025  0.050 0.970                             
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P      t.sub.R     t.sub.F t.sub.ON                                       
                                  t.sub.OFF                               
                                        t.sub.PD                          
(mw)   (ns)        (ns)    (ns)   (ns)  (ns)                              
______________________________________                                    
18.10  0.23        0.21    0.17   0.13  0.150                             
9.78   0.21        0.21    0.17   0.13  0.150                             
5.20   0.15        0.21    0.15   0.13  0.140                             
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                       TABLE 3                                                     
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SIMULATED RESULTS OF SCFL                                                 
IN ENHANCEMENT MODE GaAs II (.sup.--Q OUTPUT)                             
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PU     CS,PD     Q,SF     V.sub.H                                         
                                 V.sub.L                                  
                                       V.sub.SW                           
(KΩ)                                                                
       (KΩ)                                                         
                 (um.sup.2)                                               
                          (V)    (V)   (V)                                
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                 L × W                                              
 5     10        2 × 20                                             
                          -1     -1.97 0.97                               
10     20        2 × 10                                             
                          -1     -1.97 0.97                               
20     40        2 × 5                                              
                          -1     -1.97 0.97                               
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P      t.sub.R   t.sub.F  t.sub.ON                                        
                                 t.sub.OFF                                
                                       t.sub.PD                           
(mw)   (ns)      (ns)     (ns)   (ns)  (ns)                               
______________________________________                                    
3.300  0.26      0.26     0.14   0.12  0.13                               
1.655  0.26      0.26     0.14   0.12  0.13                               
0.827  0.26      0.26     0.14   0.12  0.13                               
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                       TABLE 4                                                     
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SIMULATED RESULTS OF FSCL                                                 
IN ENHANCEMENT MODE GaAs II (.sup.--Q OUTPUT)                             
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PU     CS,PD     Q,SF     V.sub.H V.sub.L                                 
                                        V.sub.SW                          
(KΩ)                                                                
       (KΩ)                                                         
                 (um.sup.2)                                               
                          (V)     (V)   (V)                               
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                 × W                                                
 5     10        2 × 20                                             
                          -1.06   -1.94 0.88                              
10     20        2 × 10                                             
                          -1.06   -1.94 0.88                              
20     40        2 × 5                                              
                          -1.06   -1.94 0.88                              
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P      t.sub.R   t.sub.F  t.sub.ON                                        
                                  t.sub.OFF                               
                                        t.sub.PD                          
(mw)   (ns)      (ns)     (ns)    (ns)  (ns)                              
______________________________________                                    
3.400  0.26      0.26     0.28    0.28  0.28                              
1.670  0.26      0.26     0.28    0.28  0.28                              
0.847  0.26      0.26     0.28    0.28  0.28                              
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     Tables 1 through 4 reveal simulated results of SCFL and FSCL circuitry. Tables 1 and 2 present results of GaAs SCFL and FSCL circuits using depletion mode (GaAs I) FET&#39;s along with the scaling of device size and power. Tables 3 and 4 present results of SCFL and FSCL circuits using enhancement mode (GaAs II) FET&#39;s along with the scaling of device size and power. The first column of Tables 1 and 2 shows the various areas of the pull-up (PU) FET&#39;s. The second column states the various areas in square micrometers for the different switching (Q) FET&#39;s, source-follower (SF) FET&#39;s, and pull-down (PD) FET&#39;s. In the third column are the various areas for the current-sink (CS) FET. The first and second columns of Tables 3 and 4 indicate resistances in kilo-ohms of the loads presented by the PU, CS and PD FET&#39;s, respectively. The third column of Tables 3 and 4 indicates the various areas in square micrometers of the Q and SF FET&#39;s. The other columns from left to right for all four tables reveal high and low voltages, swing voltage, power in milliwatts, and rise time, fall time, times to turn on and off, and average on and off switching time (t PD  =(t ON  +t OFF )/2) in nanoseconds. The swing voltage (V SW ) generally equals V H  -V L . FIG. 5 illustrates the measurement of various time parameters for Tables 1  through 4, such as times to turn on (t ON ) and off (t OFF ), and rise (t R ) and fall (t F ) times. The t ON  and t OFF  times are measured at midpoint 102 of the voltage amplitude change. The t R  and t F  times are measured at the 10% points 104 and the 90% points 106 of the voltage waveform amplitude. 
     In summary, the tables reveal that the FSCL circuit with its own internal reference voltage performs with approximately the same power requirements and nearly the same speed as the SCFL circuit for a given size chip area, not including the area required to provide the required reference voltage for the SCFL circuit. Thus the FSCL circuit has a much higher level of chip integration than that of the SCFL circuit because of the additional circuitry required to generate the SCFL reference voltage, thereby increasing high yield processes for manufacturing FSCL integrated circuits. 
     FSCL circuit 20 has a much higher signal to noise margin than conventional SCFL circuitry. The temperature compensation of FSCL circuit 20 is much superior than the temperature compensation of the conventional SCFL circuitry. FSCL circuit 20 has a push-pull option 40 at the output (12 and 48) for high fanout loading. (See FIG. 3a). 
     The FSCL circuit may be made with FET&#39;s using any type of process including depletion, enhancement, or a combination of processes. FSCL circuit 20 using both depletion and enhancement FET&#39;s requires only one power supply voltage (V DD ) having a ground reference (V SS ). 
     The FSCL circuit is applicable to any solid state semiconductor materials for high speeds and high levels of circuit integration. The FSCL circuit may be implemented in integrated circuit technology comprising a material of a group consisting of gallium arsenide, silicon, and indium phosphide. FSCL circuitry is applicable to flip-flops, latches, Schmitt triggers, voltage comparators, programmable logic arrays, memories, registers, clocks, processors, and so on.