Digital voltmeter
TECHNICAL FIELD 
     The present invention relates, in general, to the measurement of electrical signals and, in particular, to a digital voltmeter which measures the amplitude of a signal by producing an indication of the duty cycle of a pulse-width modulated signal developed from the signal being measured. 
     BACKGROUND ART 
     Digital Instrumentation, by A. J. Bowens and published by McGraw Hill, describes at pages 223 through 226 circuitry which develops an indication of the amplitude of a signal being measured from the duty cycle of a series of pulses produced in response to the difference in amplitudes between the signal being measured and a signal having an amplitude dependent upon the duty cycle of the series of pulses. This amplitude measuring technique is identified as &#34;delta pulse modulation.&#34; 
     The &#34;delta-pulse modulation&#34; circuitry described in Digital Instrumentation suffers from a serious shortcoming. In this circuitry, the signal representative of the duty cycle of the pulses and against which the amplitude of the input signal is compared is derived from a series of pulses which can have as many transitions in the generation of the series of pulses as there are elements of resolution. This is due to the fact that each clock signal from the clock oscillator which defines the resolution of the circuitry has the potential for causing the development of a pulse which contributes to the development of the indication of the amplitude of the signal being measured. As a result, errors due to imbalance and asymmetry in the rise and fall times of the pulse duty cycle are introduced for each such pulse. The cumulative effect can produce erroneous indications of the amplitude of the signal being measured. 
     DISCLOSURE OF THE INVENTION 
     The present invention provides a significant improvement over circuitry, such as the &#34;delta-pulse modulation&#34; circuitry described in Digital Instrumentation, in that there is a significant reduction in the transitions in the generation of the pulses from which the output indication is developed. As a result, the present invention develops a very accurate indication of the amplitude of the signal being measured. 
     A digital voltmeter, constructed in accordance with the present invention, includes means for supplying an input signal having an amplitude to be measured and means for supplying a digital reference signal representative of a fixed value. Also included are means responsive to the input signal for developing a digital signal representative of the amplitude of the input signal and pulse generating means responsive to the digital reference signal and the digital signal for developing an alternating series of oppositely directed first and second pulses. The first pulses have durations proportional to the fixed value of the digital reference signal plus the amplitude of the input signal and the second pulses have durations proportional to the fixed value of the digital reference signal minus the amplitude of the input signal. The digital voltmeter further includes a digital-to-analog converter responsive to the series of first and second pulses for (a) developing an analog signal having an amplitude proportional to the difference in durations between the first and the second pulses divided by the sum of the durations of the first and the second pulses, and (b) supplying the analog signal to the digital signal developing means to increase the value of the digital signal when the amplitude of the analog signal is less than the amplitude of the input signal and decrease the value of the digital signal when the amplitude of the analog signal is greater than the amplitude of the input signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Referring to the drawings: 
     FIG. 1 is a block diagram of a first preferred embodiment of a digital voltmeter constructed in accordance with the present invention; 
     FIG. 1A is a block diagram of a modification which can be made to the FIG. 1 embodiment; 
     FIG. 2 is block diagram of a second preferred embodiment a digital voltmeter constructed in accordance with the present invention; and 
     FIG. 3 is a block diagram of a modification which can be made to the FIGS. 1 and 2 embodiments. 
    
    
     BEST MODE FOR CARRYING OUT THE INVENTION 
     A digital voltmeter, constructed in accordance with the present invention, provides a measurement of the amplitude of an input signal (V I ) when the amplitude of the input signal (V I ) is equal to the amplitude of the output signal (V X ) of a digital-to-analog converter arranged as an averaging differential integrator and functioning according to the following relationship: ##EQU1## T 1  and T 2  in equation (1) are the durations of an alternating series of oppositely directed pulses having a relationship to the amplitude of the input signal (V I ) which will be explained below. Applicant&#39;s copending application Ser. No. 925,022, filed Nov. 6, 1986 and entitled &#34;Digital-to-Analog Converter,&#34; now U.S. Pat. No. 4,709,124 is directed to a preferred digital-to-analog converter which can be adapted for use in the present invention. 
     If in equation (1): 
     
         t.sub.1 =M+N and T.sub.2 =M-N 
    
     where M and N are digital numbers, then equation (1), after substitution, becomes: ##EQU2## Simplifying equation (2): ##EQU3## If M is a constant, then the amplitude of the analog output signal (V X ) varies directly with the digital number N and when the amplitude of the analog output signal (V x ) is equal to the amplitude of the input signal (V I ), the digital number N provides a measure of the amplitude of the input signal (V I ). 
     Referring to FIG. 1, which shows a first preferred embodiment of the present invention, an input signal (V I ) having an amplitude to be measured supplied to a servo amplifier 10. A second input signal (V X ) to servo amplifier 10 is supplied from the output of a digital-to-analog converter 12, such as the one to which the above-identified copending application is directed. Servo amplifier 10 is a high-gain unit which develops an output signal of one polarity when the amplitude of the input signal (V I ) is greater than the amplitude of the output signal (V X ) from digital-to-analog converter 12 and an output signal of opposite polarity when the amplitude of the input signal (V I ) is less than the amplitude of the output signal (V X ) from the digital-to-analog converter. 
     The output signal from servo amplifier 10 is supplied to an up/down counter 14 which counts clock pulses (F R ) supplied by a clock oscillator 15. Up/down counter 14 counts in one direction for a given polarity of the output signal from servo amplifier 10 and in an opposite direction when the output signal from the servo amplifier is of the opposite polarity. The combination of servo amplifier 10 and up/down counter 14 develops a digital signal representative of the amplitude of the input signal (V I ) and this digital signal corresponds to the digital number N identified above. 
     The digital signal (N) and a digital reference signal (M), representative of a fixed value, are supplied to an adder/subtracter 16 which, for a first time period, adds the digital signal (N) to the digital reference signal (M) to produce an (M+N) output and, for a second time period, subtracts the digital signal (N) from the digital reference signal (M) to produce an (M-N) output. The state of adder/subtracter 16 is controlled, in a manner to be described below, to alternately develop the (M+N) and (M-N) outputs. 
     The outputs from adder/subtracter 16 are supplied to a comparator 18 which also receives the output from a binary counter 20 to which the clock pulses (F R ) are supplied from clock oscillator 15. Comparator 18 develops an output which triggers a D-FF (flip-flop) 24 when the output of binary counter 20 is equal to the output of adder/subtracter 16. After binary counter 20 has counted a number of clock pulses (F R ) equal to the (M+N) output from adder/subtracter 16, comparator 18 develops a first trigger signal which changes the state of D-FF 24 to define a first pulse developed by the D-FF having a duration proportional to (M+N). The change in state of D-FF 24 changes the state of adder/subtracter 16, so that now it is conditioned to subtract the digital signal (N) from the digital reference signal (M). Comparator 18 also triggers a RS-FF (flip flop) 26 which, in turn, resets binary counter 20. 
     After binary counter 20 counts a new number of clock pulses (F R ) equal to the (M-N) output from adder/subtracter 16, comparator 18 develops a second trigger signal which changes the state of D-FF 24 to define a second pulse developed by the D-FF having a duration proportional to (M-N). This change in state of D-FF 24 changes the state of adder/subtracter 16 to return it to its initial state in which it is conditioned to add the digital signal (N) to the digital reference signal (M). Comparator 18 also triggers RS-FF 26 which, in turn, resets binary counter 20. 
     The state of adder/subtracter 16 is controlled by the output of a NOR gate 28 which responds to the sign of the digital signal (N) and changes in the state of the output of D-FF 24. As the output of D-FF 24 changes, the state of adder/subtracter 16 switches between adding and subtracting the two inputs to the adder/subtracter. The digital signal (N) is supplied to NOR gate 28 to accommodate both positive and negative input signals. 
     The alternating sequence just described keeps repeating to produce, at the output of D-FF 24, a series of oppositely directed pulses having durations proportional to the (M+N) and (M-N) outputs from adder/subtracter 16. The output from D-FF 24 passes through a latch 30 to digital-to-analog converter 12. Latch 30 serves to reduce the effects of propagation time delays. The transition time in changing from the (M+N) output to the (M-N) output is not necessarily the same as the transition time in changing from the (M-N) output to the (M+N) output. Latch 30 overcomes this problem by synchronizing the output from D-FF 24 with clock oscillator 15. 
     Digital-to-analog converter 12 develops an analog signal (V X ) having an amplitude proportional to the difference in durations between the (M+N) and (M-N) pulses divided by the sum of the durations of the (M +N) and (M-N) pulses. This corresponds to equation (1). So long as the amplitude of the analog signal (V X ) is less than the amplitude of the input signal (V I ), the output signal from servo amplifier 10 controls up/down counter 14 to continue to develop an increasing count of clock pulses (F R ) and the amplitude of the analog signal (V X ) increases. If the amplitude of the analog signal (V X ) becomes greater than the amplitude of the input signal (V I ), the polarity of the output signal of servo amplifier 10 reverses and controls up/down counter 14 to count clock pulses (F R ) in an opposite direction to decrease the count, thereby decreasing the amplitude of the analog signal (V X ). In this way, the output of up/down counter 14, namely the digital signal (N), stabilizes and represents the amplitude of the input signal (V I ). A suitable display device 32 provides an indication of the value of the digital signal (N). 
     As previously indicated, Applicant&#39;s copending application Ser. No. 925,022, now U.S. Pat. No. 4,709,224, is directed to a preferred digital-to-analog converter which can be adapted for use as digital-to-analog converter 12. The contents of this copending application are incorporated by reference as if fully set forth herein. 
     FIG. 1A illustrates one way of modifying the FIG. 1 embodiment of the present invention to adapt the digital-to-analog converter of application Ser. No. 925,022, now U.S. Pat. No. 4,705,224, for use in the present invention. This is accomplished by introducing a divider 31 between comparator 18 and D-FF 24. Adder/subtracter 16 in FIG. 1 corresponds to pulse source 10 in application Ser. No. 925,022 and comparator 18, divider 31 and D-FF 24 in FIG. 1A correspond to counter 12 in application Ser. No. 925,022, now U.S. Pat. No. 4,709,224. 
     With divider 31 set to divide by a factor of three, D-FF 24 changes state only after every third trigger signal developed by comparator 18. The division factor of divider 31 is selected to be three because the digital-to-analog converter of application Ser. No. 925,022 has, during each charge and discharge portion of its operation, a first charge (or discharge) period, a sample period, and a second charge (or discharge) period. With D-FF 24 changing state after only every third trigger signal developed by comparator 18, the state of adder/subtracter 16 is changed only after every third trigger signal developed by the comparator so that the (M+N) or (M-N) outputs from the adder/subtracter continue to be supplied until the D-FF 24 changes state. In this way, an (M+N) output is supplied during the first charge period of the digital-to-analog converter, during the charge sample period of the digital-to-analog converter, and during the second charge period of the digital-to-analog converter and an (M-N) output is supplied during the first discharge period of the digital-to-analog converter, during the discharge sample period of the digital-to-analog converter, and during the second discharge period of the digital-to-analog converter. As a result, the output of D-FF 24 still is a series of oppositely directed first and second pulses having durations proportional to (M+N) and (M-N), except that the durations of these pulses are three times longer than the durations of the pulses produced by the D-FF without the introduction of divider 31 between comparator 18 and the D-FF. 
     FIG. 2 shows a second preferred embodiment of digital voltmeter constructed in accordance with the present invention. The FIG. 2 embodiment operates in a generally similar manner to the FIG. 1 embodiment, except that in the FIG. 2 embodiment, the time intervals T 1  and (T 1  +T 2 ) are measured instead of the time intervals T 1  and T 2  as in the FIG. 1 embodiment. This is accomplished by not resetting binary counter 20 after the (M+N) count for time interval T 1  has been reached, but rather permitting the binary counter to continue counting until it reaches a total count equal to 2M for time interval (T 1  +T 2 ). As a result, time interval T 2  corresponds to an (M-N) count. Elements in FIG. 2 corresponding to elements in FIG. 1 have been given the same reference numerals. 
     As in the FIG. 1 embodiment, the output of up/down counter 14 is a digital signal (N) representative of the amplitude of the input signal (V I ). The digital signal (N) and the digital reference signal (M) are supplied to an adder 34 which adds the digital signal to the digital reference signal to produce an (M+N) output. The output from adder 34 is supplied to a data multiplexer 36 which, for a first time period, passes the (M+N) output to comparator 18. 
     After binary counter 20 has counted a number of clock pulses (F R ) equal to the (M+N) output from data multiplexer 36, comparator 18 develops a trigger signal which changes the state of D-FF 24 to define a first pulse developed by the D-FF having a duration proportional to (M+N). The changing state of D-FF 24 changes the state of multiplexer 36, so that it is conditioned to pass a 2M output to comparator 18. 
     The trigger signal developed by comparator 18 also is supplied to an AND circuit 38 which is also connected to the output of D-FF 24. Because AND circuit 38 requires two similar inputs, only every second trigger signal developed by comparator 18 causes RS-FF 26 to reset binary counter 20. As a result, binary counter 20 continues to count during time interval T 2  until it has counted during time interval (T 1  +T 2 ) a total number of clock pulses (F R ) equal to 2M. When the total count of binary counter 20 is equal to 2M, comparator 18 develops a trigger signal which changes the state of D-FF 24 to define a second pulse developed by the D-FF having a duration proportional to (M-N). This change in state of D-FF 24 changes the state of data multiplexer 36 to return it to its initial state in which it is conditioned to pass the (M+N) output from adder 34 to comparator 18. This trigger signal from comparator 18 also is effective in resetting binary counter 20 because a second change in state of D-FF 24, along with the trigger signal, cause AND circuit 38 to condition RS-FF 26 to reset the binary counter. 
     The 2M output from data multiplexer 36 can be derived a number of ways. As shown in FIG. 2, the digital reference signal (M) is supplied to data multiplexer 36. By shifting this digital signal by one bit in wiring, as represented by reference numeral 40, the 2M output is derived during each time interval T 2  as a result of D-FF 24 conditioning data multiplexer 36 to pass the 2M output during these time intervals. 
     The remainder of the FIG. 2 embodiment of the present invention operates in the same manner as the FIG. 1 embodiment. Display device 32 provides an indication of the amplitude of the input signal (V I ) which is developed from the digital signal (N). As with the FIG. 1 embodiment, the digital-to-analog converter of application Ser. No. 925,022, now U.S. Pat. No. 4,709,224, can be adapted for use in the FIG. 2 embodiment. 
     FIG. 3 shows a modification which may be made to either the FIG. 1 or FIG. 2 embodiments of the present invention to overcome the introduction of errors which have more of an effect when operating such circuits at high speeds. FIG. 3 indicates how the added components would be connected to components in the FIG. 1 and FIG. 2 embodiments. 
     Initially, the circuitry of FIG. 3 is inoperative, so that the FIG. 1 and FIG. 2 embodiments operate at high speed, as previously described, to quickly reach a point where the amplitude of the analog signal (V X ) from digital-to-analog convertor 12 is approaching the amplitude of the input signal (V I ). At a prescribed point, the circuitry of FIG. 3 becomes operative and reduces the repetition rate of the clock pulses (F R ) supplied by clock oscillator 15 to slow down the operation of the digital voltmeters shown in either FIG. 1 or FIG. 2. In other words, in each embodiment, the digital voltmeter operates at high speed to get within the range of the amplitude of the input signal (V I ), during which time errors are of no concern, and then operates at a slower speed in actually obtaining an indication of the amplitude of the input signal (V I ), at which time errors are of great concern. 
     The circuitry of FIG. 3 includes a differential amplifier 40 which is a low-gain unit that develops a signal representative of the difference in amplitudes between the input signal (V I ) and the analog signal (V X ). The output of differential amplifier 40 is supplied to a window comparator 42 which is set to produce an output signal when the difference signal developed by the differential amplifier falls within a prescribed range indicative of the amplitude of the analog signal (V X ) approaching the amplitude of the input signal (V I ) being measured. The output signal from window comparator 42 controls clock oscillator 15 to reduce the repetition rate of the clock oscillator. A window comparator is used rather than a level comparator to accommodate opposite polarity differences in the amplitudes between the input signal (V I ) and the analog signal (V X ). 
     It should be understood that, although the present invention has been described as a digital voltmeter, in the broadest sense, the present invention is directed to apparatus for converting a digital input signal to an analog output signal. The output signal from up/down counter 14 can be considered as a digital input signal representative of a variable value to downstream circuitry, so that the output signal from D/A converter 12 is an analog output signal corresponding to the digital input signal from the up/down counter. As a result, the circuitry between up/down counter 14 and servo amplifier 10 can receive and process other digital input signals besides one representative of the amplitude of the input signal (V I ) and produce analog output signals (V X ) representative of these other digital input signals. 
     The foregoing has set forth exemplary and preferred embodiments of the present invention. It will be understood, however, that various alternatives will occur to those of ordinary skill in the art without departure from the spirit and scope of the present invention.