Clock distribution circuit having minimal skew
FIELD OF THE INVENTION 
     This invention relates in general to a clock distribution circuit, and more particularly to a circuit for distributing a clock signal to a plurality of other circuits, wherein the skew between the input signal and the plurality of output signals is substantially reduced. 
     BACKGROUND OF THE INVENTION 
     Complex circuitry such as high speed computer systems, automatic test equipment, VLSI chips, synchronous machines, self timed RAMS, wafer scale integration circuits and module or board level designs all require clock signals to synchronize the components of the complex circuitry. Because of the difference of the times of propagation of the various elements of a clock distribution circuit for high-to-low and low-to-high transitions, the pulse widths of a clock signal are distorted (skew) by each element through which the clock signal passes. Clock skew is one of the major concerns in high speed digital system design. If two circuits are clocked by two outputs of the same clock drive with relatively large skew, they receive the clock signal at different times. Clock skew system timing problems can then be encountered unless the clock period is much larger than the skew. Consequently, clock skew sets an upper limit on the frequency and the operating speed of the system. At high frequencies the ability of the designer fanout and low skew can be used to improve matching and reduce the physical size of the system. 
     Thus, what is needed is a circuit for distributing a clock signal to a plurality of other circuits, wherein the skew between the input signal and the plurality of output signals is substantially reduced. 
     SUMMARY OF THE INVENTION 
     A monolithically integrated chip comprises a substrate having a planar surface with input and output pads disposed at the periphery of the chip. A plurality of transistors and resistors formed in the planar surface comprise a clock distribution circuit, having an input gate disposed near the center of the planar surface and a plurality of output gates, each disposed between the center of the planar surface and one each of the output pads. A plurality of metalization strips are disposed substantially radially from the input gate at the center of the planar surface to one each of the output gates and from each of the output gates to the respective output pad for transmitting signals thereto. 
     Accordingly, it is an object of the present invention to provide an improved clock distribution circuit. 
     Another object of the present invention is to provide a clock distribution circuit having minimal skew. 
     The above and other objects, features, and advantages of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic of a clock distribution circuit in accordance with the present invention. 
     FIG. 2 is a partial block diagram of the cross sectional top plan view of a monolithically integrated circuit of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, a schematic of a clock distribution circuit comprises enable circuit 11, input circuit 12 and output circuit 13. Output circuit 13 as shown in FIG. 1 is one of a plurality of output circuits, each receiving the same signals QI and QI from input gate 12. For example, FIG. 2 illustrates nine output gates 13 all connected to input gate 12. Enable circuit 11 includes differentially connected transistors 14 and 15 having collectors coupled to the bases of transistors 16 and 17, respectively, and to resistor 18 by resistors 19 and 21, respectively, and bases coupled to terminals 22 and 23, respectively. Resistor 18 is further connected to supply voltage terminal 24. Current source transistor 25 has its collector connected to the emitters of transistors 14 and 15, its emitter coupled to supply voltage terminal 26 by resistor 27, and its base coupled to terminal 28. Emitter follower transistors 16 and 17 have collectors connected to supply voltage terminal 24, and emitters connected to the base and collector of diode connected transistors 29 and 31, respectively. Current source transistor 32 and 33 have collectors connected to the emitters of transistor 29 and 31, respectively, their emitters coupled to supply voltage terminal 26 by resistors 34 and 35, respectively, and their bases connected to terminal 28. Resistor 36 is coupled between enable terminal 22 and supply voltage terminal 26. 
     A digitally high enable signal applied to enable terminal 22 bias transistors 14 and 17 on, causing enable signals EN and ENP to go high and complementary enable signals EN and ENP to go low. 
     Input circuit 12 includes differentially connected transistors 41 and 42 having their collectors connected to the bases of emitter follower transistors 44 and 43, respectively, and coupled to resistor 45 by resistors 46 and 47, respectively, and their bases connected to input terminals 48 and 49, respectively. Differentially connected transistors 51 and 52 have their collectors connected to the bases of transistors 44 and 43, respectively, and their bases connected to the emitters of transistors 16 and 17, respectively. Differentially connected transistors 53 and 54 have their collectors connected to the emitters of transistor 41 and 42, and 52 and 52, respectively, and their bases connected to the emitters of transistors 29 and 31, respectively. Current source transistors 55 has a collector connected to the emitters of transistors 53 and 54, a base connected to terminal 28, and an emitter coupled to supply voltage terminal 26 by resistor 56. Current source transistors 57 and 58 have their collectors connected to the emitters of transistor 43 and 44, respectively, their emitters coupled to supply voltage terminal 26 by resistors 59 and 60, respectively, and their bases connected to terminal 28. 
     When a digitally high input signal INPUT is applied to input terminal 48, transistors 41 and 43 are biased on, and when enable signal ENABLE is also high, signal QI is high and signal QI is low. 
     Output circuit 13 includes differentially connected transistors 61 and 62 having their collectors connected to the bases of emitter follower transistor 63 and 64 and coupled to supply voltage terminal 24 by resistors 65 and 66, respectively, and their bases connected to the emitters of transistors 43 and 44, respectively, for receiving signals QI and QI. Current source transistor 67 had a collector connected to the emitters of transistors 61 and 62, respectively, a base connected to terminal 28, and an emitter coupled to supply voltage terminal 26 by resistor 68. Diode connected transistor 69 has a base and collector connected to the collector of transistor 62 and to the emitter of diode connected transistor 70. Transistor 70 has its base and collector coupled to the collector of transistor 61 by resistor 71. Transistors 63 and 64 have their collectors connected to supply voltage terminal 72 and their emitters connected to output terminals 73 and 74 for providing output signals OUTPUT and OUTPUT, respectively. 
     When signal QI is digitally high, transistors 61 and 64 are biased on, causing output signal OUTPUT to go high and output signal OUTPUT to go low. 
     The clock distribution circuit of FIG. 1 is completely differential. The two gate design increases the level of gain and also makes it easier to disable the outputs. Furthermore, the skew is reduced by balancing the parasitic capacitive effects on the bases of transistors 43 and 44 by the arrangement of transistors 41, 42, 51, 52, 53 and 54. 
     Referring to FIG. 2, the layout of the present invention is shown and comprises substrate 81 having input pads 22, 24, 26, 48, 49, and 72 and output pads 73 and 74 disposed on the periphery of the substrate 81. These pads are numbered similarly to the pads of FIG. 1 for which they represent. In addition to output pads 73 and 74, sixteen additional output pads and OUTPUT 0  and OUTPUT 0 , OUTPUT 1  through OUTPUT 8  and complementary OUTPUT 1  through OUTPUT 8  are disposed on the periphery of the substrate. The location of these pads is pertinent to reducing skew. Input pads 48 and 49 are located at a substantially equal distance from and on opposite sides of supply voltage pad 24. Output pads OUTPUT 1  and OUTPUT 1 , OUTPUT 4  and OUTPUT 4 , and OUTPUT 7  and OUTPUT 7  are all located at a substantially equal distance from and on opposite sides of supply voltage pads 72. Additionally, other output pads are placed at a substantially equal distance from and on opposite sides of power supply pads, i.e., output pads 73 OUTPUT 0   and 74 OUTPUT 0 ,and OUTPUT 2  and OUTPUT 2 . The placing of complementary outputs in close proximity to each other on the same side of the chip in this manner creates a virtual ground plane therebetween, thus minimizing the inductive effects on performance. The location of supply voltage pads 24, 26 and 72 in the middle of the side of the substrate aids in reducing the inductive effects. Three supply voltage pads V CCO  72 maintain balanced loading and symmetry. 
     Enable gate 11, input gate 12 and OUTPUT GATE 0  through OUTPUT GATE 8  and OUTPUT 0  through OUTPUT 8  are coupled together electrically as shown in FIG. 1. The bias driver 82 is additional circuitry for providing voltages to the other circuits. For ease of understanding the layout of the clock distribution circuit, the metalization providing the voltages from supply voltage pads 24, 26 and 72 are not shown. 
     The signals QI and QI from input gate 12 is provided to metal strips 83 84,85,86,87 and 88. The lengths of metal strips 83, 84, 85, 86, 87 and 88 may be trimmed to adjust parasitic capacitance. Signal QI is then transmitted radially along metal strips 89, 90, 91, 92, and 93, and signal QI is transmitted radially along metal strips 94, 95, 96, 97 and 98 to respective output gate. Output signals OUTPUT and OUTPUT from each of the output gates OUTPUT GATE 0  through OUTPUT GATE 8  are coupled to power output transistors 101 through 118, respectively. The power output transistors 101 through 118 are coupled to the respective output pad by metal strips 119 through 136, respectively. 
     Skew is the propagation delay between the plurality of outputs 73 and 74 relative to a common input 48 and 49. Skew minimization is attained through careful layout of the chip, pinout selection and circuit architectural symmetry. Layout enhancements provided by this invention include even distribution of signals and loading through radial layout, avoidance of sharp signal interconnect metalization angles and matched interconnect path lengths. Minimizing switching current effects on the package inductanceresistance-capacitance parasitics is obtained by pad placement. To further reduce skew, circuit architecture is totally differential, including the internal enable signal path, with attention given to transistor parasitic matching. 
     By now it should be appreciated that there has been provided a circuit for distributing a clock signal to a plurality of other circuits, wherein the skew between the input signal and the plurality of output signals is substantially reduced.