High voltage MOS field effect semiconductor device
This is a continuation, of U.S. application Ser. No. 819,216, filed Jan. 15, 1986 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device (hereinafter referred to as &#34;high voltage MOS IC&#34;) comprising a high voltage MOS field-effect transistor and a usual low voltage MOS field-effect transistor for driving the transistor which are formed on a single semiconductor substrate. 
     2. Description of the Prior Art 
     Drivers for display panels such as EL panel, PDP, etc. or other high voltage drivers comprise a plurality of high voltage MOS field-effect transistors and low voltage logic circuits as disclosed in U.S. Pat. No. 4,194,214. These components are usually arranged in such a pattern that the transistors are disposed at the peripheral portion of a die, with the circuits positioned at the center of the die. 
     With high voltage MOS IC&#39;s of such a construction, a high voltage is applied to the die peripheral portion surrounding the low voltage logic circuits, so that a groove of potential occurs on the pattern of low voltage logic circuits, and external charges accumulate in this portion. This influences the IC substrate, leading to the drawback of inverting the field portion of the low voltage MOS field-effect transistor constituting the logic circuit and inducing a malfunction of the circuit. 
     Although Examined Japanese Patent Publications SHO 48-14153 and SHO 48-28826 disclose a technique for electrically shielding the device region within semiconductor substrates, the technique is still unable to completely eliminate the influence of high voltage applied to the logic circuit-surrounding peripheral portion of an MOS IC of the above construction. 
     SUMMARY OF THE INVENTION 
     In a semiconductor device comprising a high voltage MOS field-effect transistor and a low voltage logic circuit both provided on a single semiconductor substrate, the pattern of low voltage logic circuit C as positioned at the center of a die A is covered with an aluminum or other conductor layer D according to the present invention as shown in FIG. 1 of the drawing to assure the logic circuit of stable operation free of the influence of external charges. A circuit B of high voltage MOS field-effect transistor is provided at the peripheral portion of the die A. 
     Thus, by substantially completely covering the logic circuit C with an aluminum or other conductor layer from above, with an insulating layer interposed therebetween, and electrically connecting the layer to the IC substrate, GND terminal, low voltage power supply or the like, the influence of external charges on the IC substrate can be potentially completely blocked, whereby the high voltage MOS IC can be made highly reliably free of the likelihood that the field portion of the low voltage MOS field-effect transistor constituting the logic circuit will be inverted to induce a malfunction of the circuit. 
     The conductor layer, which is characteristic of the present invention, is prepared usually from aluminum. When the conductor layer is formed of aluminum containing about 1% of silicon, the layer covers the semiconductor portion with improved adhesion thereto. Although the process for forming the conductor layer is not specifically limited, vacuum evaporation is convenient and effective. While the conductor layer substantially completely covers the semiconductor portion (logic circuit C), the term &#34;substantially completely&#34; covering layer with respect to the is to be interpreted as also meaning a plurality of conductor layers which are maintained at electrically the same potential. 
     With the above-mentioned high voltage MOS field-effect transistor, it is desirable that the region of high resistance layer present between the source electrode and the drain electrode be covered with a conductor extending from the source electrode, as well as from the drain electrode, and further with a plurality of floating conductors. The high resistance layer can then be free of the influence of external charges and maintain high voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a plan view schematically showing the structure of a semiconductor chip according to the present invention; 
     FIGS. 2 (a) to (f) are sectional views for illustrating a process for fabricating a semiconductor device embodying the present invention; 
     FIG. 3 is a plan view schematically showing another embodiment of a semiconductor chip of the present invention; and 
     FIGS. 4 (a) and (b) are sectional views showing semiconductor substrates for illustrating high voltage MOS FETs of the invention and a the prior art, respectively. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following description, it is assumed that the left side region of the substrate provides a high voltage MOS FET, and the right side region thereof a low voltage logic circuit as seen in FIG. 2. 
     The semiconductor substrate 1 to be used is a P-type substrate having a low impurity concentration.  31  P +  ions are implanted in the surface of the substrate through a thin oxide film 18, using a resist 19 for masking, followed by diffusion to form a high resistance layer (FIG. 2 (a)). 
     Next, the thin oxide film 18 is etched away from the substrate, a thin oxide film 20 is grown again, and a silicon nitride film 21 is deposited on the film by the vapor phase growth process. Subsequently, openings are formed for channel, source and drain regions by photoetching. With the resulting substrate locally covered with a resist 22,  11  B +  ions are implanted by a self-alignment process to form P +  regions 6 (FIG. 2 (b)). 
     With use of the silicon nitride film 21 for masking, the substrate is then subjected to selective oxidation to form a thick oxide film 10. The silicon nitride film and the underlying thin oxide film are thereafter removed, and a thin oxide film 23 is grown again over the removed area. Further with use of a resist 24 for masking,  31  P +  ions are implanted to form a channel portion 16 of a depression type transistor (FIG. 2 (c)). 
     Polycrystalline silicon is then deposited by the vapor phase growth process, the deposit is removed from unnecessary areas, and gate electrodes 9 and 9&#39; and floating electrodes 14 are formed. Next, the resulting surface is locally masked with a resist 25, and  11  B +  ions are implanted, followed by diffusion to form P +  regions 4 and 4&#39; (FIG. 2 (d)). 
     The substrate is further doped with phosphorus by self-alignment diffusion or ion implantation to form source regions 2, 2&#39; and drain regions 3, 3&#39;. A thick insulating film 11 is then deposited by the vapor phase growth process, and drain contact portions and source contact portions are opened by etching. An aluminum or like conductor layer is thereafter deposited over the entire surface by vacuum evaporation or sputtering, and the undesired portions are removed to form source electrodes 8, 8&#39;, drain electrodes 7, 7&#39; and floating conductors 14&#39; (FIG. 2 (e)). 
     A thick insulating film 12 is further deposited by the vapor phase growth process. Through holes are then formed in the film for the drain electrode, source electrode and like portions of the high voltage MOS FET. A conductor layer of aluminum containing 1% of silicon is deposited again by vacuum evaporation over the entire surface, except where unnecessary, to form a field plate 8&#34; extending from the source electrode 8, a field plate 7&#34; extending from the drain electrode 7, and a shield plate 17 potentially shielding the logic circuit and characterizing the present invention. Finally, a protective film 13 is formed to complete the high voltage MOS IC (FIG. 2 (f)). 
     As another embodiment of the present invention, the selective oxide film, for example, may be replaced by an insulating film formed by the vapor phase growth process. Although the shield plate 17 is connected to the source of the high voltage MOS FET and the substrate according to the above embodiment, the plate may be connected to the power supply for applying low voltage to the logic circuit. The shield plate 17 may be divided into a plurality of segments D as seen in FIG. 3 corresponding to FIG. 1. In this case, each plate segment needs to be connected to the source of the high voltage MOS FET, to the substrate or the low voltage power supply. 
     FIGS. 4 (a) and (b) show high voltage MOS FETs of the present invention and the prior art, respectively. 
     The conventional high voltage MOS FET shown in FIG. 4 (b) has a P-type substrate 1 which is formed with an N+ source region 2 and an N+ drain region 3. A P +  region 4 for the gate channel of the FET is formed around the source region 2 by a self-alignment process. Further connected to the drain region 3 is a high resistance layer 5 of the same conduction type. 
     When the semiconductor substrate having impurities diffused therethrough as above is provided with a source electrode 8 connected to the N +  source region 2 and a drain electrode 7 connected to the N +  drain region 3, there is a region 5&#39; of high resistance layer between the gate electrode and the drain electrode which region is not covered with a conductor such as aluminum or polycrystalline silicon. The uncovered region 5&#39; of high resistance layer is susceptible to the influence of external charges and results in the problem that when checked by a high-temperature bias test or the like, the device undergoes variations in electric characteristics such as voltage resistance, drain current, on resistance, etc. during operation. To assure improved reliability by overcoming this problem, the high voltage MOS FET fabricated by the process of FIG. 2 has a construction which withstands high voltage and in which the high resistance layer is made free of the influence of external charges. With reference to FIG. 4 (a) showing this construction, the corresponding region of the high resistance layer is completely covered with a source electrode 8, a drain electrode 7 and a plurality of floating conductors 14&#39;.