Semiconductor device
This is a continuation of co-pending application Ser. No. 839,525 filed on Mar. 14, 1986, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device. More particularly, it relates to a semiconductor device wherein source and drain regions having three regions formed by three different types of impurity doping steps are formed to prevent the occurrence of hot electrons which otherwise cause deterioration of the device performance. 
     2. Description of the Related Art 
     With the miniaturization of the semiconductor device the length of the gate electrode of a MIS FET has been shortened. The supply voltage is generally maintained at 5 V, and does not have a lowering tendency. This causes the problem that particularly in an n channel MIS transistor, the drain electric field is greater than in a conventional device, and a portion of the electrons accelerated by the increased electric field are injected into a gate insulating film: this is well known as a channel hot electron phenomenon. Further, a portion of the electrons generated by the impact ionization are injected to the gate insulating film and changes the characteristic of the MIS transistor; this is well known as an avalanche hot electron phenomenon. 
     In order to solve the problem of the hot electron phenomena, a double diffused drain (DDD) structure and a lightly doped drain (LDD) structure have been proposed since an electric field is not concentrated in the DDD structure, and thus the hot electron phenomenon is reduced. However, in the DDD structure, the effective channel length is decreased and thus a punch through phenomenon is generated. Further, problems of deterioration of the mutual conductance (g m ) or breakdown voltage arise. 
     On the other hand, although the LDD structure has an effect on the channel hot electron phenomenon, it has little effect on the avalanche hot electron phenomenon, in which electrons generated at a deeper portion of the substrate due to the high electric field strength are accelerated so that the electrons are moved to the gate electrode through the gate insulating film. In addition, in the LDD structure, deterioration of the mutual conductance also occurs. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention is to provide a semiconductor device, particularly MIS FET, wherein the occurrence of the channel hot electron phenomenon and the avalanche hot electron phenomenon are decreased. 
     Another object of the present invention is to provide a semiconductor device, wherein the mutual conductance (g m ) thereof is improved. 
     According to the present invention there is provided a semiconductor device formed in a semiconductor substrate and having a gate electrode formed on said semiconductor substrate, and source and drain regions formed in said semiconductor substrate wherein the source and drain regions comprise: a first impurity region doped with impurities of an opposite conductivity type to that of the semiconductor substrate formed at portions adjacent to the edge of the gate electrode; a second impurity region doped with impurities an opposite conductivity type to the semiconductor substrate formed at portions under the first impurity region, the impurities of the second impurity region having larger diffusion coefficient than that of the impurities of the first impurity region; a third impurity region doped with impurities of an opposite conductivity type to the semiconductor substrate formed at portions spaced apart from the edge of the gate electrode, the third impurity region having a higher concentration than that of first and second impurity regions and the impurities of the third impurity region having a diffusion coefficient smaller than that of the second inpurity region. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects, features and advantages of the invention will be understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: 
     FIG. 1A is a cross-sectional view of a conventional DDD structure; 
     FIG. 1B is an equivalent circuit view of FIG. 1A; 
     FIG. 2 is a cross-sectional view of a conventional LDD structure; 
     FIG. 3 is a cross-sectional view of another conventional example; 
     FIG. 4 is a cross-sectional view of still another conventional example; 
     FIG. 5A is a cross-sectional view of an example of an n channel MIS FET according to the present invention; 
     FIG. 5B is an equivalent circuit view of FIG. 5A; and 
     FIGS. 6A to 6D and FIGS. 7A to 7D are cross-sectional views explaining two production processes according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Before describing the preferred embodiment of the present invention, the related art will be explained in more detail with reference to the drawings. 
     FIG. 1A is a cross-sectional view of a conventional DDD structure. 
     In FIG. 1A, an insulating film 2 and a gate electrode 3 are provided on a p-type semiconductor substrate 1. In the substrate 1 an n +  region 4 and an n -  region 5 are formed by doping, for example, an arsenic ion (As + ) and a phosphorus ion (P + ), followed by annealing. Since the diffusion coefficient of phosphorus is remarkably larger than that of arsenic, a double diffused drain (DDD) region, i.e., n +  region (As + ) and n -  region (P + ), is formed. The structure formed before the DDD structure is formed has only the n +  region 4, wherein As +  is diffused, so that a step-junction is formed. Thus, in the prior structure, an electric field was concentrated at a portion 6 in the n +  region 4 where the step-junction is formed, and this led to the problem of the occurrence of the above-mentioned hot electron phenomenon. 
     Therefore, by forming the above mentioned n -  region (P + ) 5 of the DDD structure in such a manner that the n -  region (P + ) 5 is underneath the n +  region 4, a graded junction formed by the diffusion of a P +  electric field is shifted to a portion 7 in the n -  region. Consequently, the concentration of an electric field in the portion 7 is considerably decreased compared to that in the portion 6. 
     However, the DDD structure has an effective channel length (C2) shorter than that (C1) of one prior structure not having an n -  region, as shown in FIG. 1A. Consequently in the DDD structure, a punch through phenomenon often occurs between the source and drain region. Further, in the DDD structure, the properties of an FET are determined by the concentration of P +  in the n -  type region 5. When the concentration of P +  is low, a parasitic series resistance is generated, as shown by a reference number 8 in FIG. 1A. Further, the mutual conductance (g m ) of the device cannot be increased. On the other hand, when the concentration of P +  is high, the breakdown voltage is lowered. 
     An equivalent circuit of the device shown in FIG. 1A is shown in FIG. 1B. 
     Referring to FIG. 2, a lightly doped drain (LDD) structure is shown in which a gate insulating film 2, a gate electrode 3, and a side wall 10 are formed on a p-type semiconductor substrate 1. In the substrate 1 an n -  region 5 and an n +  region 4 is formed by doping As +  and then performing an annealing process. In the formation process of the n -  and n +  regions, As +  having a low concentration is doped into the subtrate 1 to form the n -  region 5, and As +  having a high concentration is doped therein to form an n +  region 4. Since the diffusion depth (x j ) of the doped impurities is determined by the root of the concentration (C) thereof, i.e., √C∝x j , an LDD structure as shown in FIG. 2 is obtained. The LDD structure can prevent occurrence of channel hot electrons at a portion 11 in FIG. 2. However, the LDD structure cannot prevent the occurrence of avalanche hot electrons which are generated at a deeper portion 12 of the substrate 1, due to the high electric field strength, and accelerated to move into the gate electrode 3 through the gate insulating film 2. Further, the deterioration of the mutual conductance (g m ) occurs as in the DDD structure. 
     FIG. 3 shows a semiconductor device as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 60-136376. This device (Hitachi structure) has an n +  region 4, an n 1   -  region 5a and an n 2   -  region 5b in the source and drain regions. Each region is produced by a process wherein P +  is doped to a dosage of 1×10 12  cm -2  using a polycrystalline layer of a gate electrode 3 formed on a gate insulating film 2 as a mask, side walls of SiO 2  are formed so that the gate electrode 3 is sandwiched, therebetween, P +  is doped to a dosage of 1×10 14  cm -2  using the gae electrode 3 and the side walls 10 as a mask, P +  doped portions are annealed while the doped P +  is diffused so that the n 1   -  region 5a (P +  doped to a dosage of 1×10 12  cm -  2) and n 2   -  region 5b (P +  doped to a dosage of 1×10 14  cm -2 ) are formed, As +  is doped to a dosage of 5×10 15  cm -2  using the gate electrode 3 and the side walls 10 as a mask, and the n +  region 4 is formed by annealing the As +  doped portion. 
     Since the n 1   -  region 5a is formed by doping P + , which has a large diffusion coefficient, into the substrate 1, the distance C3 between the edges of the n 1   -  regions 5a, i.e., channel length, becomes short and the above-mentioned punch through phenomenon occurs. Further, as explained for the DDD structure, the Hitachi structure is subjected to a resistance due to the diffused n 1   -  region 5a, so that the mutual conductance (g m ) is lowered. These disadvantages in the Hitachi structure become greater as the semiconductor device become smaller. 
     FIG. 4 shows a semiconductor device disclosed at a Symposium on VLSI Technology, 14 to 16 May, 1985. This device (Toshiba structure) also has three regions, i.e., n 1   - , n 2   - , and n +  regions. 
     Each region is produced by a process wherein P +  and As +  are doped using a gate electrode 3 as a mask, the P +  and As +  doped portions are annealed to form the n 2   -  region 5b and n 1   -  region 5a, respectively, side walls 10 are formed, As +  is doped using the gate electrode 3 and the side walls 10 as a mask, and the second As +  doped portion is annealed to form the n +  region 4. Since the n 2   -  region is formed by annealing the P +  doped portion, as explained for the Hitachi structure, the Toshiba structure also has the disadvantage of the occurrence of a punch through phenomenon and the mutual conductance (g m ) becomes small. 
     Preferred embodiments of the present invention will now be explained. 
     FIG. 5A shows a cross-sectional view explaining an example of an n channel MIS FET according to the present invention. 
     As shown in FIG. 5A, a source (S) and a drain (D) region in a P-type semiconductor substrate or p-type well 11 each consist of an n 1   -  region 15a, an n 2   -  region 15b, and an n +  region 14. An insulating film 2 of, for example, SiO 2 , a gate electrode 3 of polycrystalline silicon, and side walls 10 of an insulating material are provided on the semiconductor substrate 11. The n 1   -  region 15a is formed by doping impurities having a low concentration on outside edge A of the gate electrode 3. 
     On the other hand, the n 2   -  region 15b and the n +  region 14 are formed by doping impurities having a low and a high concentration, respectively, an outside the edge B of the side walls 10. The distance between the N +  region 14 and the gate electrode 3 is preferably equal to the width of one of the sidewalls 10. The diffusion coefficient of impurities doped in the n 2   -  region is larger than that of impurities doped in the n 1   -  and n +  regions. Although the electric field is concentrated in portion 13 duplicated by the n 1   -  region 15a and the n 2   -  region 15b, the electric field concentration is reduced due to the graded junction of the n 2   -  region. This gives an improvement of the deterioration of properties by two orders, compared to a previous example wherein the hot electron phenomenon could not be avoided. Further, since the n 2   -  region has a graded junction, a depletion layer is expanded and thus the stray capacitance of the source and drain regions is decreased and the switching speed of the device can be increased. 
     Resistance in the structure is shown in FIG. 5B. Namely, the resistance in, for example, a source region, which is generated by the n 1   -  and n 2   -  regions is equivalent to total resistance of n 1   -  and n 2   -  regions connected in parallel to each other (not in series) and is reduced, thus allowing an increase in the mutual conductance (g m ). 
     The process for producing an embodiment according to the present invention will now be described with reference to FIGS. 6A to 6D and FIGS. 7A to 7D respectively. 
     As shown in FIG. 6A, p type channel cut regions 16, a field insulating film 12 of, for example, SiO 2 , and a gate insulating film 2 of, for example, SiO 2 , are formed on a p type semiconductor substrate 11 which has an impurity concentration of 10 15  -10 16  cm -3 , and then a gate electrode 3 having a thickness of 2000 to 5000 Å is formed. The gate electrode 3 is made of polycrystalline silicon, a high melting point metal or high melting point metalsilicide, etc. Then, As +  is doped to a dosage of 1×10 13  to 1×10 15  cm -2  at an accelerating energy of 60 to 120 KeV so that the first lightly doped n -  regions, i.e., n 1   -  regions, 15a are formed. 
     Then, as shown in FIG. 6B, an insulating layer 17 having a thickness of 500 to 5000 Å is formed on the obtained structure. The insulating layer is made of SiO 2  or Si 3  N 4  obtained by a chemical vapour deposition (CVD) process, etc. 
     Next, the insulating layer 17 of, for example, CVD-SiO 2 , is entirely removed by a reactive ion etching (RIE) process using CHF 3  gas or a mixed gas of CHF 3  and CF 4  under a pressure of 0.1 to 0.2 torr so that side walls 10a are formed in such a manner that they sandwich the gate electrode 3. 
     Then, as shown in FIG. 6C P +  having a larger diffusion coefficient than As +  is doped to a dosage of 1×10 13  to 1×10 15  cm -2  at an accelerating energy of 60 to 80 KeV to form a second lightly doped n -  region, i.e., n 2   -  region 15b, and As +  is doped to a dosage of 3×10 15  to 5×10 15  cm -2  at an accelerating energy of 60 to 120 KeV to form a heavily doped or high concentration n +  region 14. The obtained structure is then annealed at a temperature of 900° C. to 1100° C. in an inert gas atmosphere. 
     The n 2   -  region has a graded junction formed between the n 2   -  region and the substrate 11. The graded junction surface formed between the n 2   -  region 15b and the substrate 11 forms a surface substantially tangential with a junction surface formed between the n 1   -  region 15a and the substrate 11. 
     Then, as shown in FIG. 6D, an insulating layer 20 of, for example, phospho-silicate glass (PSG), boron silicate glass (BSG), etc., is formed, and an aluminum source drawing electrode 21a, an aluminum gate drawing electrode 21b, and an aluminum drain drawing electrode 21C are formed by a usual process thus producing a first embodiment of the present invention. 
     A process for producing a second embodiment of the present invention will now be described. 
     As shown in FIG. 7A, P type channel cut regions 16, a field insulating film 12, and a gate insulating film 2 are formed on a p type semiconductor substrate 11. Then a gate electrode 3 having a thickness of 2000 to 5000 Å and a width longer than the width of the first embodiment explained above is formed using a mask 22 of CVD SiO 2  having a thickness of 500 to 2000 Å. The material of the gate electrode is the same as that used in the first embodiment. Then, P +  is doped to a dosage of 1×10 13  to 1×10 15  cm -2  at an accelerating energy of 60 to 80 KeV to form a lightly doped n 2   -  region 15b. Then As +  is doped to a dosage of 3×10 15  to 5×10 15  cm -2  at an accelerating energy of 60 to 120 KeV to form a heavily doped or high concentration n +  region 14. 
     Then as shown in FIG. 7B both sides of the gate electrode 3 are removed by a side plasma etching process using a mixed gas of CF 4  and O 2  (5%) in a polycrystalline silicon gate electrode so that a width of 1000 to 4000 Å is removed from each side thereof. 
     Then, as shown in FIG. 7C, the mask 22 of CVD SiO 2  is removed and As +  is doped to a dosage of 1×10 13  to 1×10 15  cm -2  at an accelerating energy of 60 to 120 KeV to form lightly doped n 1   -  region 15a. Then, an annealing process is carried out at a temperature of 900° C. to 1100° C. in an inert gas atmosphere. 
     Finally, as shown in FIG. 7D, an insulating layer 20 and aluminum electrodes 21a, 21b, and 21c are formed as described in the first embodiment, thus, producing a second embodiment of the present invention.