Double direct injection dual band sensor readout input circuit
This invention relates to an electronic circuit for processing information from sensors and more particularly to circuitry for simultaneous and separate integration of current from two sensors. 
     BACKGROUND OF THE INVENTION 
     Dual band detector arrays comprising a medium wave (MW) diode and a long wave (LW) diode require simultaneous and separate integration of diode current to accurately provide a signal representative of incident radiation. The prior art does not show such a circuit. 
     Sebastian R. Borrello et al. U.S. Pat. No. 4,956,686 entitled &#34;Two Color Infrared Focal Plane Array&#34; issued Sep. 11, 1990 discloses using a matrix array so that two detectors have a single set of readout lines. Electronic addressing selects the color to be read and multiplexing is done on the detector chip to obtain the desired color. The array uses HgCdTe diodes which provide a lower noise readout. Borrello et al. do not show the process of simultaneously integrating the output from two diodes. 
     Therefore, it is a motive of the invention to provide a double direct injection dual band multiplexer circuit. 
     SUMMARY OF THE INVENTION 
     In contrast to the prior art, the present invention provides a signal processing apparatus. A first signal detector has a first signal output. A second signal detector has a second signal output. Signal integration means for integrating the first signal a plurality of times while the second signal is being integrated once is coupled to the first signal output and the second signal output. 
     In another aspect, the invention provides a double direct injection input circuit for use as a dual band infrared focal plane array readout input circuit that simultaneously and separately integrates current from two sensors with a common connection. The dual band sensor circuit comprises a medium wave photodetector having a medium wave photocurrent output and a long wave photodetector having a long wave photocurrent output. The long wave photocurrent output is connected to the medium wave photocurrent output. A medium wave voltage bias circuit biases the medium wave photocurrent output, wherein the medium wave voltage bias circuit has a medium wave biased photocurrent output and a medium wave voltage input connected to the medium wave photocurrent output and a long wave voltage bias circuit connected to bias the long wave photocurrent output. The long wave voltage bias circuit has a long wave biased photocurrent output and a long wave voltage input connected to the long wave photocurrent output. A medium wave photocurrent integration circuit integrates the medium wave biased photocurrent output, wherein the medium wave photocurrent integration circuit has a reference voltage input. A long wave photocurrent integration circuit that integrates the long wave biased photocurrent output is connected to the long wave biased photocurrent output and the medium wave biased photocurrent output. A long wave reset circuit resets the long wave photocurrent integration circuit to a predetermined long wave reset voltage. A medium wave reset circuit resets the medium wave photocurrent integration circuit to a predetermined medium wave reset voltage; and a switch floats the medium wave photocurrent integration circuit with a float control output connected to the reference voltage input. 
     During each integration cycle sensor currents are integrated and read by following circuits as a voltage. The integration voltage is reset to prepare for the next integration cycle. The sensors may be constant voltage, variable current sensors with the common connections and one independent connection connected to the input circuit and the other independent connection set by an external bias. The bias voltage for the sensors can be independently adjusted. In one embodiment, these sensors are composed of two back-to-back Mercury Cadmium Telluride infrared photodiodes, one of which responds to infrared radiation in the medium wavelength (MW) band (3 to 5 um wavelength) and one of which responds to infrared radiation in the long wavelength (LW) band (8 to 12 um wavelength). The diode structure and input circuit can be made compactly and hybridized using indium bump technology to form staring dual band infrared focal plane arrays. In one embodiment of the invention, multiple LW integration cycles can be performed in a single MW integration cycle, allowing flexibility in transimpedance gain without lowering the percentage of an integration cycle in which integration is performed. The circuit of the invention can also be used with more than two sensors by the addition of multiple floating integration circuit sections and associated sensors. 
     Other objects, features and advantages of the present invention will become apparent to those skilled in the art through the description of the preferred embodiment, claims and drawings herein wherein like numerals refer to like elements. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     To illustrate this invention, a preferred embodiment will be described herein with reference to the accompanying drawings. 
     FIG. 1 shows a schematic circuit diagram of the double direct injection dual band multiplexer input circuit of the invention. 
     FIGS. 2A, 2B, 2C, 2D, 2E and 2F are timing diagrams which show examples of timing periods employed in one embodiment of this invention. 
     FIG. 3 shows a circuit schematic of the invention used in a multiband configuration. 
     FIG. 4 shows a circuit timing diagram of the multiband configuration. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows a schematic circuit diagram of the double direct injection dual band input circuit 10 of the invention. The circuit 10 uses two direct injection input circuits to integrate current from a medium wave (MW) photodiode and a long wave (LW) photodiode simultaneously. In one embodiment the sensors may be constant voltage, variable current sensors with one common connection, one independent connection connected to the input circuit and another independent connection set by an external bias. In one preferred embodiment of the invention, the medium and long wave photodiode may be a HgCdTe type photodiode or equivalent, for example. The outputs of each photodiode, LW and MW, are integrated on separate capacitors, a medium wave integration capacitor 30 and a long wave integration capacitor 36. 
     A first N channel field effect transistor, FET 25, has its source 27 connected to a common node 19 which connects a medium wave detector 16 and a long wave detector 14. The common node 19 may advantageously be fabricated as an indium bump, or equivalent structure, for example. The FET 25 has its gate 26 connected to a first bias voltage V BM . The drain 29 of the FET 25 is connected to cascode node 28. Cascode node 28 is connected to a first terminal of the long wave integration capacitor 36. 
     The second terminal of the long wave integration capacitor 36 is connected to the drain 34 of a first P channel field effect transistor, FET 31. The FET 31 has a gate 32 connected to a bias voltage V CSL . The first P channel FET 31 further has a source 33 connected to both the output of a reset switch RSL 43 and an LW output line 55. The medium wave integration capacitor 30 is connected to the drain 45 of a second N channel FET 39, which is the medium wave output. The medium integration capacitor 30 has a reference voltage supply 44, labeled V DA , controlled by reset switch RSM 42. 
     A second P channel field effect transistor, FET 21, has its source 23 connected to the anode of the long wave detector 14 at node 17. Node 17 may also be fabricated as an indium bump. The FET 21 has its gate 22 connected to a second bias voltage V BL . The drain of the FET 21 is connected to LW output line 55. Those skilled in the art will appreciate that other well known alternatives may be employed to connect the detectors to the processing circuitry of the invention, such as wire, cable, metal, printed wiring board interconnections and the like. 
     Two resets are provided by the circuit 10. A medium wave signal reset is provided by reset switch RSM 42 which couples in V DA  reset voltage from voltage supply 44. The long wave reset switch RSL 43 is connected to V RSL  reset voltage 40. The long wave output, on LW output line 55, is provided at the common terminal of the long wave integration capacitor 36 and the long wave reset switch RSL 43. 
     Medium wave diode 16 characteristically has a high impedance. The circuit 10 exploits the low impedance of the direct injection input 27 by operating to allow a long wave photocurrent to be integrated on the long wave integration capacitor 36 and a medium wave photocurrent to be integrated on a medium wave integration capacitor 30. The detector bias is determined by voltage source V BL  for the long wave FET 21 and voltage source V BM  for the medium wave FET 2S. 
     In operation the invention provides a circuit that has a dual band input design with a reduction in LW to MW crosstalk. The CSL transistor FET 31 may advantageously comprise a cascode transistor that isolates most of the stray capacitance from the LW integration node of drain 34. Such stray capacitance is the cause of crosstalk from the LW to the MW bands. 
     The circuit of the invention also permits multiple LW integrations for each MW integration, thereby allowing more flexibility in choice of MW and LW transimpedance gains. An MW cascode transistor, CSM transistor FET 39, isolates the non-integrating side of the LW integration capacitor 36 from the integrating side of the MW integration capacitor. The LW integration capacitor may be DC referenced using cascode reference switch CRF 52 without resetting the integrating node of the MW integration capacitor 30. One terminal of cascode reference switch CRF 52 is connected to a reference voltage VRF. The MW integration cycle resumes where it left off when an LW readout cycle is complete. 
     The invention also provides a test input circuit for the dual band input. It is desirable to be able to test readout circuits prior to hybridization to avoid connecting good detectors to defective readout circuits. The test input circuit comprises transistor 37 which connects the LW and MW inputs and is controlled by impressing a voltage TG on the base of transistor 37 through line 41. If the circuit operates normally, the current through transistor 37 is integrated in the LW integration capacitor 36. If the LW reset switch RSL 43 is left on, then the current through the test transistor 37 will be integrated in the MW integration capacitor 30. Thus both inputs can be tested prior to hybridization with one transistor. Line 41 provides a test current by turning transistor 37 on. For normal operation of the circuit 10 transistor 37 is turned off. 
     Timing diagrams illustrating timing employed in one example of the invention are shown in FIGS. 2A-2F which coincide in time as viewed from left to right. 
     FIG. 2A shows the status of reset switch RSM 42 which is used to reset the MW integration capacitor 30. 
     FIG. 2B shows the readout period for the MW signal at MW output 50. FIG. 2C shows the status of RSL reset switch 43 which is engaged to reset the LW integration capacitor 36. FIG. 2D shows the status of cascode reference switch CRF 52. FIG. 2E shows the status of CSL voltage on gate 32 of FET 31. FIG. 2F indicates readout and reset times for MW signals and LW signals. 
     An integration time begins with the following signals at the indicated states: RSM on at state 201 resets MW, LW reference CRF on at state 203, the LW cascode CSL control set several volts below ground to turn the CSL cascode transistor FET 31 on as a switch at state 205, and reset switch RSL 43 on at state 207. The LW reset voltage should be at ground and V RF  should be set just high enough to insure that no current will flow through the CSM transistor FET 39. The LW integration begins first. CSL transistor FET 31 may advantageously be set to operate as a cascode transistor for the LW integration capacitor by setting CSL to approximately 3.5 Volts indicated at state 211. Then the reset switch RSL 43 can be turned off as indicated by state 213. Once the LW cascode node is charged to its operating value and LW integration begins on the LW integration capacitor 36, MW integration can begin. 
     If it is desired to expedite this charging at node 24, the LW reset voltage, V RSL , may be clocked up several volts after CSL has risen to state 211 but prior to RSL going off at state 213. V RSL  would return to ground after RSL was turned off at state 213. Reset switch RSM 42, the MW switch, is turned off as indicated by RSM off state 215. The reference switch, CRF switch 52, is turned off as indicated at state 217. When the MW cascode node settles, MW integration begins as generally indicated by state 220. 
     To read out only the LW signal, the CRF reference switch 52 is turned on at state 222 to shut down the MW integration at state 224 and provide a DC reference to the LW integration capacitor 36. Then CSL transistor FET 31 is turned on by bringing it below ground at state 230. The LW signal can now be read out at LW output 24 as indicated by state 232. After read out, the LW capacitor 36 may be reset at state 234 by switching reset switch RSL 43 on at state 236. LW integration may then be resumed with transistor FET 31 operating as the cascode, and RSL off. After the LW cascode node settles, MW integration resumes at state 240 by turning CRF switch 52 off at state 240 and waiting for the reference node to settle. 
     To read out MW and LW, the procedure is the same as detailed above except for the addition of a MW read and reset shown at states 250 and 252 respectively. The readout process begins by turning CRF off at state 242. The MW capacitor 30 may now be read out in MW output 50. CSL control voltage is set to about -2 V in one example to enable readout of the LW capacitor. Then reset switch RSM 42 and reset switch RSL 43 are turned on as indicated by states 260 and 261 respectively to reset the MW and LW integration capacitors at state 252. The timing then repeats as shown in FIGS. 2A-2F. 
     It is also possible to read out the MW signal during LW integration. Timing is not critical since the MW cascode CSM transistor FET 39 isolates the MW integration capacitor 30 from the LW integration capacitor 36. The MW signal may be read out at any time at MW output 50. Following a read the MW signal may be reset by turning RSM on. MW integration begins again when RSM is turned off. LW integration will continue through the MW read and reset. 
     Since the invention allows multiple long wave integrations for each medium wave integration, the medium wave voltage crosstalk is reduced by the ratio of the integration times. This occurs because only a fraction of the medium wave integration occurs in each long wave integration cycle. 
     In one preferred embodiment of the invention, the circuit may be constructed using CMOS processing technology. When compared to other conventional circuit technology the resulting CMOS circuit has smaller input cells with improved dynamic range sensitivity and much lower crosstalk. 
     Those skilled in the art will appreciate that while the specific application for this invention is a dual band infrared focal plane array having a medium wave (MW) infrared detector diode connected to detector common and a long wave (LW) infrared detector diode connected to the non-common side of the MW diode, it is not necessary that the detector input have one MW detector and one LW detector. The circuit will work with any type of constant voltage, variable current and stacked detectors whatever their response, in the optical range or in other ranges. 
     A stacked detector configuration is any detector configuration where two detectors share a common node and where the common node is not the detector common node. The detector common node is the node that is shorted together across the detector array and connected to an external bias supply voltage. A constant voltage, variable current detector is a configuration where the detectors are kept at a constant bias voltage and the current through them is integrated to generate their response. 
     Now referring to FIG. 3, a schematic diagram illustrates the invention detecting four separate bands. Above line AA, the circuit is similar to the circuit shown in FIG. 1. D1 and D2, and accompanying circuitry, are used to separately detect two separate bands in the manner corresponding to FIG. 1. 
     Below line AA, FIG. 3 illustrates the manner in which current from additional sensors detecting separate bands may be simultaneously and separately integrated. Detectors D3 and D4, and accompanying circuitry, each constitute a floating stage. Each floating stage detects an added separate band. The operation of the floating stages is similar to the circuit of FIG. 1. The polarity of the stages must be alternated in order to allow the current and shared nodes to flow in the same direction. 
     Reset voltages V RS1  through V RS4  must be clocked so the voltage is used both to reset the integration capacitor of its associated stage, and to serve as a reference to reset and read the integration capacitor for each stage as well. This reset timing is shown in more detail with reference to FIG. 4. For example, V RS2  is used to reset integration capacitor C2, and as a reset and reference for integration capacitor C3. When the signal for integration reset switch RS2 is first on and CS2 is on (low), V RS2  is low, for example, at zero volts, to reset C2. Then, after CS2 goes high, for example, to 3.5 volts, as a cascode and RS2 is still on, V RS2  goes higher, for example, up to 5 volts, to serve as a reset reference for capacitor C3. The other side of C3 is reset by V RS3  high, for example, at 10 volts, with CS3 high, for example, at 12 volts, as a switch. RS2 turns off to allow C2 integration to begin. When C3 is ready to read out, RS2 must be turned on again to allow V RS2  high, for example, at 5 volts, to be used as a reference for integration capacitor C3. 
     As with the circuit of FIG. 1, the readout is accomplished by turning on the cascode FET for the output as a switch. In the case of C3, this implies bringing CS3 high, that is to about 4 volts. Those skilled in the art will recognize that it is not necessary to reset all the integration capacitors to readout any of the others, however, integration must be stopped on the lower number outputs to reset and read a higher number one. The circuit allows integration in any of the bands to extend across multiple integrations of the other bands. 
     The multiplex output buffers are included in order to illustrate how the apparatus of the invention would be used in an array of detectors. The output from detectors D1 to D4 are fed into the gate of output source follower FET O1 to O4. The source of each FET are connected through an associated switch S1 to S4. Switches S1 to S4 are used to select a particular row for which an output is to be placed on a column output bus. In an array of detectors, the column output busses may be shared by all the unit cells in a column to allow the entire column to readout onto one line. The selected row is determined by which unit cell is using the bus at any given time. The current source load V DD  for the source followers O1-O4 is located at the end of a column of cells, not in each cell. The columns would then be multiplexed in the following circuit to generate a small number of output lines for the multi-colored array. 
     The invention has been described herein in considerable detail in order to comply with the Patent Statutes and to provide those skilled in the art with the information needed to apply the novel principles and to construct and use such specialized components as are required. However, it is to be understood that the invention can be carried out by specifically different equipment and devices, and that various modifications, both as to the equipment details and operating procedures, can be accomplished without departing from the scope of the invention itself.