Method and apparatus for testing semiconductor devices at speed
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to semiconductor devices and, more particularly, to a method and apparatus for testing semiconductor devices at their operating speed. 
     2. Description of the Related Technology 
     Semiconductor integrated circuits are produced by manufacturing a wafer (a disk of silicon) having many copies, each copy called a &#34;die&#34; (plural &#34;dice&#34;), of the integrated circuit. Typically, not all the dice of a wafer work properly. Thus, the first thing that must be done after the wafer is processed is to determine which dice are good. Each die on the wafer must be tested to determine whether it functions correctly. This testing activity is called &#34;wafer sort&#34;. Only the dice that pass wafer sort testing are packaged. 
     During testing, parameters such as propagation delay and drive currents are checked, a process called &#34;parametric testing&#34;. Whether or not the die carries out the function it was designed for is also checked by a process called &#34;functional testing&#34;. The cost of doing functional testing is increasing rapidly. This is due to the fact that the ratio between the number of semiconductor devices on a die to the number of connection pads or I/O pins is rising. In fact, functional testing may be the most expensive part of manufacturing an integrated circuit. 
     Automatic test equipment that functionally tests semiconductor dice has become very expensive. In addition, the computing time required to calculate input test patterns to be applied to the die during these tests is extremely costly. What the integrated circuit manufacturers have done to reduce functional testing costs is to include circuitry on each semiconductor die to facilitate testing thereof. 
     There are two types of functional tests that are utilized in computer systems. The first is &#34;implicit&#34; or concurrent testing or &#34;checking&#34;. This test refers to on-line testing to detect errors that occur during normal system operation. The second is &#34;explicit&#34; testing. Explicit testing is carried out while the tested circuit (die) is not in use. Explicit testing includes the tests performed on dice while still on a wafer, production tests on packaged dice on boards, acceptance tests, maintenance tests, and repair tests. 
     In order to make testing of a resulting product economical, the semiconductor die must have a &#34;design for testability (DFT)&#34;. DFT is utilized to increase the observability or controllability of a circuit design on a semiconductor die. The most direct way to do this is to introduce test points, i.e., additional circuit inputs and outputs to be utilized during testing. There is a cost, however, associated with adding test points. This cost may be justified, but the cost of test points soon becomes prohibitive because of the limited number of integrated circuit package pins available. 
     DFT requires additional logic and extra connections to the die, and it is desirable to limit these additions to those absolutely necessary to assure adequate testability of the design. The integrated circuit manufacturers have utilized various methods of estimating a design&#39;s testability. A straight forward method for determining the testability of a circuit is to use an Automatic Test Pattern Generation (&#34;ATPG&#34;) program to generate the tests and the fault coverage. The running time of the program, the number of test patterns generated, and the fault coverage then provides a measure of the testability of the circuit. 
     In order to permit access to internal nodes of a circuit without requiring a separate external connection for each node requiring access, additional internal logic circuitry may be utilized primarily for the testing function. Using this test logic, it is possible to introduce scan-path test methods. Scan-path design is a DFT circuit design technique that partitions the circuit, as well as increases the observability and controllability of internal circuit nodes. Scan path design is suitable for synchronous, sequential circuits. 
     With scan-path design, testing of the semiconductor die is simpler and yet results in effective fault testing coverage. The scan-path technique requires that a circuit under test have two modes of operation: a normal functional mode and a test mode. The change from one mode to the other is controlled by a mode-select signal and/or by a separate test clock signal. 
     In the test mode, the scan elements shift data along the scan chain (as in a shift register). Thus, a test pattern can be scanned (shifted) into the scan chain, filling all scan elements with data. When the circuit under test returns to its normal functional mode, a system clock causes the test pattern to be stored in the system flip-flops and applied at the primary circuit inputs to be processed by the combinational logic part of the circuitry. 
     The results of the processing are stored back to the system flip-flops by the single system clock pulse. When the circuit is next placed into test mode, the resulting pattern, stored in the shift register, is then shifted out for comparison with the expected response. The ATPG program models of the scan flip-flops and latches aid the semiconductor die test designer in creating and verifying the resulting test patterns shifted out with the expected response generated from the ATPG program. A more detailed introduction to scan-path design techniques is given in Logic Design Principles, by Edward J. McCluskey, Prentice-Hall, 1986, and is incorporated by reference herein for all purposes. 
     Another important test is delay fault. The delay fault test uses the scan test to test for high speed faults. It is important in high speed semiconductor devices that not only do the circuits therein properly perform the required logic functions, but also that these circuits perform these logic functions correctly at the required speed. The combination of these tests may be called delayed ATPG. 
     A typical delayed ATPG test has four cycles in sequence as follows: a) scan in/out, b) strobe output, c) stabilize, and d) input. The scan in/out cycle is where data is scanned into and out of the scan chain of the semiconductor devices under test. The strobe output cycle is where the test data is strobed out of the scan chain in preparation for testing of the devices. The stabilize cycle is where the strobed data stabilizes in the semiconductor device circuits so as to avoid race conditions and internal bus conflicts before the input cycle. The input or capture cycle is where the strobed and stabilized data is transferred through the semiconductor device circuit logic by a system clock pulse at the desired operating speed of the logic devices. 
     After the input cycle, the next scan in/out cycle begins. The previous test results are shifted out while a new test pattern is shifted in. A comparison of the test results is made against an expected pattern and if there is a match, then the device has passed this part of the test. In the scan in/out cycle, data may be shifted into and out of the semiconductor device under test at a relatively slow speed such as, for example, 10 MHz. 10 MHz is high enough in frequency to allow shifting of the data test patterns into and out of the circuit devices without undue delay, but not so fast as to prevent standard digital logic test circuits from easily handling the data transfers. A more detailed description of this test methodology is detailed in Chip-Level Full Scan Design Methodology Guide, LSI Logic Corporation, January 1992, and incorporated herein by reference for all purposes. 
     Circuit devices of present technology semiconductor integrated circuit dice may operate at upwards of 200 MHz, and the promise of even faster devices is not too far in the future. 200 MHz devices must be tested in some fashion at their intended operating speed for the test to be meaningful. Therefore, at 200 MHZ operating speed, the input cycle must use a system clock having a 5 nanoseconds pulse width. The 5 nanosecond clock pulse causes the test pattern already scanned into the devices under test to propagate therethrough. The data pattern propagates through the test device logic and is held in the output scan register until the next scan in/out cycle. During the next scan in/out cycle, this pattern will be shifted out and compared to verify proper circuit operation. 
     A single system clock pulse, however, only &#34;bangs&#34; the previously setup data through the test device logic circuits, and the result of whatever propagates through is shifted out during the next scan in/out cycle. The aforementioned test only checks combinational logic function and does not test if the logical operations propagate through the logic being tested within a desired time period. Thus, logic operation may be correct but the time in which the logic circuits under test perform the logic operation is still unverified. 
     Attempts have been made to verify correct propagation time of logic devices by correlation. Correlation is when at least one path of a semiconductor device is clocked at operating speed, and correct operation of this path is verified. Thus, the device is correlated to function at a desired test speed. 
     What is needed is a method and apparatus which tests semiconductor devices at their operating speed. It is, therefore, an object of the present invention to test semiconductor devices at a desired operating speed with standard integrated circuit testers. 
     SUMMARY OF THE INVENTION 
     The present invention provides a method and apparatus for testing semiconductor devices at their maximum operating speed with readily available integrated circuit test equipment. The present invention accomplishes this by utilizing test circuit devices deposed on the semiconductor die. The present invention consists of integrated scan-path logic circuits, a phase-lock-loop buffered local clock, and multiplexing clock control logic with clock burst control. 
     In an embodiment of the present invention, a semiconductor die such as, for example, an application specific integrated circuit (&#34;ASIC&#34;) or a microprocessor integrated circuit (&#34;CPU&#34;) is designed utilizing DFT logic circuits adapted for scan-path delayed ATPG testing. The semiconductor die is adapted for connection to a standard logic testing system utilizing, for example, a 10 MHz test clock (&#34;TCK&#34;). The semiconductor device has a test data input connection, a test data output connection, a TCK input connection, and a test/normal control connection. These connections may be, for example, die connection pads or pins of an integrated circuit package. 
     The phase-lock-loop of the semiconductor die runs at the frequency of the system clock. On-chip phase-lock-loop circuits are typical in high speed integrated circuits for reducing clock insertion delay in the distribution of the system clock and for synchronizing all clock signals throughout the die. The phase-lock-loop of the present invention is synchronized or &#34;phase locked&#34; to the test system TCK frequency. As an example, a phase-lock-loop system clock may operate at 200 MHz and would be phase locked to the 10 MHz TCK frequency. The synchronized system clock and TCK frequencies are connected to the clock control logic with clock burst control. 
     During the scan in/out cycle, the test system loads new test pattern data into the data input connection and receives the previous test data results from the data output connection of the semiconductor die under test. The input/output test data transfers at the 10 MHz rate by the TCK signal. The test/normal control is in the test state during the scan in/out cycle. 
     The test pattern data is next strobed out of the DFT shift register and into the semiconductor device input logic circuits during the strobe output cycle. The test pattern data is allowed to stabilize during the stabilization cycle, and to settle and be stable for the next cycle, the input cycle. Each cycle time period may be about 1000 nanoseconds. 
     During the input cycle, the high speed phase-lock-loop system clock is utilized to exercise the semiconductor die device logic. The burst control logic of the clock control circuit guarantees that no more than two high speed system clock pulses occur during the input cycle. These two clocks insure that any transition propagating through the device under test must occur within a certain amount of time. In this way, the device logic under test is verified for both correct logic operation and correct logic operation occurring within a desired time, i.e., the logic is functioning at speed. 
     In one aspect of the invention, the phase-lock-loop system clock, clock control and burst control logic are synchronized with the TCK signal from the test system. In this way, the TCK controls all cycle functions synchronously so that only two system clocks are applied to the device logic circuits during the input cycle. Even though the phase-lock-loop is running continuously, the test/normal control signal and TCK control all test functions without glitches or other undesired clock pulses. 
     An advantage of the present invention is that commonly available and inexpensive test systems may be utilized with ever increasing speed semiconductor devices. 
     Another advantage is that the semiconductor device logic is tested for correct logic transition within a certain amount of time without requiring a high speed test system. 
     Still another advantage is that the present invention utilizes substantially standard scan-path registers, phase-lock-loop clock and easily implemented logic circuits to control the test cycle clocks. 
     A feature of the present invention is utilizing two high speed clock pulses that are synchronized with the test system clock so that precise and repeatable control of the logic test occurs. 
     Another feature is testing semiconductor device logic for proper test pattern propagation during a desired time period. 
     Yet another feature is using delayed ATPG with an inexpensive testing system and a high speed semiconductor die. 
    
    
     Other and further objects, features and advantages will be apparent from the following description of presently preferred embodiments of the invention, given for the purpose of disclosure and taken in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a test system for an embodiment of the present invention; 
     FIG. 2 is a block diagram of an embodiment of the present invention; and 
     FIG. 3 is a scan-path test timing diagram of the present invention. 
    
    
     DESCRIPTION OF A PREFERRED EMBODIMENT 
     Referring now to the drawings, the details of a preferred embodiment are schematically illustrated. Like elements are numbered the same, and similar elements are represented by the same number and a different lower case letter suffix. 
     Referring now to FIG. 1, a block diagram of a test system for an embodiment of the present invention is illustrated. A standard digital logic tester 102 is connected to a semiconductor die test jig 104. The semiconductor die jig 104 is adapted to hold and probe a semiconductor integrated circuit die or dice. The dice may still be in the form of a silicon wafer, separate dice, or a die encapsulated in an integrated circuit package. The logic tester 102 may be any general purpose tester as is widely used in the semiconductor industry and well know to those skilled in the art of testing semiconductor devices. 
     Test signals connect between the logic tester 102 and the semiconductor die test jig 104. These signals are scan data input (&#34;SDI&#34;) 106, scan data output (&#34;SDO&#34;) 108, test clock (&#34;TCK&#34;) 110, and test/normal control (&#34;CTL&#34;). 
     Referring now to FIG. 2, a schematic block diagram of a preferred embodiment of the present invention is illustrated. The present invention is a method and apparatus for testing a semiconductor die and is generally referenced by number 202. Semiconductor die 202 consists of combinational logic 212, scan-path logic 214, voltage controlled oscillator clock 204, phase detector and reference multiplexer 206, frequency divider 210, and clock and burst controller 208. The combinational logic 212 is the device logic of the semiconductor die 202 to be tested. The scan-path logic 214 is logic added to the semiconductor die 202 to enable scan-path delayed ATPG testing of the combinational logic 212. 
     The voltage controlled oscillator clock 204 is typically part of an on chip phase-lock-loop driven by a system clock 220 and operating at a designated frequency. The output of the voltage controlled oscillator clock 204 is clock output 222, which is used to drive clock nodes of the semiconductor die 202 and is utilized during normal operation to reduce clock insertion delay and to synchronize all clock signals on the semiconductor die 202. 
     The frequency of the voltage controlled oscillator clock 204 is controlled by phase detector and reference multiplexer 206. During normal operation, the phase detector and reference multiplexer 206 locks the frequency of the voltage controlled oscillator clock 204 to either the system clock 220 frequency or some multiple thereof. A modulo-N frequency divider 210 divides the clock output 222 frequency. Divided frequency output 218 is connected to the phase detector and reference multiplexer 206 and is used as the error reference. The modulo-N frequency divider 210 may have a divide ratio N of any positive integer number, and may be programmed for different values of N. Operation of phase-lock-loops are well known to those skilled in the art of communications and digital circuit design. 
     The phase detector and reference multiplexer 206 is also utilized to select a different reference oscillator during the test mode controlled by CTL 112. The test mode reference oscillator is TCK 110 from the logic tester 102. In the test mode, voltage controlled oscillator clock 204 is phase-locked to the frequency of TCK 110. This allows synchronous glitch free operation during the scan-path test cycles because every event during a cycle, and each cycle change, occurs on a positive edge of the TCK 110. Setup and settling transitions do not create false signals nor glitches because they occur during the time TCK 110 is at a low logic level. Thus, all logic control during the test mode is dependant on and in time sync with the logic levels of TCK 110. 
     The clock output 222 is connected to the input of clock and burst controller 208. The burst controller 208 is utilized to gate off and control the number of clock pulses to the combinational logic 212 during testing thereof. During normal operation, burst controller 208 allows output clock 222 to pass through to controlled clock output 224. Thus, the burst controller 208 does not interfere with normal operation of the semiconductor die 202. The burst controller 208, however, is utilized during scan-path testing for a specific purpose in the presently disclosed invention. 
     During scan-path testing, the scan-path logic is utilized to shift test pattern scan data into shift registers through SDI 106. After completion of shifting the scan-path data into the registers (not illustrated), the scan-path data is parallel loaded over bus 216 into the combinational logic 212 to be tested. While the scan-path data for a pending test is being shifted into registers of scan-path logic 214, the resulting test pattern scan data from the previous test run is being shifted out of the registers through SDO 108 and to the logic tester 102 for analysis thereof. Test data is obtained from the operation of the combinational logic 212 over the bidirectional bus 216. 
     The CTL 112 controls whether the semiconductor die logic circuits are in a normal operational mode or in a test mode. During inputting of scan-path data through the SDI 106, and outputting of resulting logic operation test data through the SDO 108, the CTL 112 has the semiconductor die 202 in test mode. During the test mode, the phase detector 206 uses the TCK 110 as the reference frequency and locks the frequency of the voltage controlled oscillator clock 204 thereto. The TCK 110 is normally at a lower frequency than the frequency of the voltage controlled oscillator clock 204. 
     As an example, the voltage controlled oscillator clock 204 may operate at a frequency of 200 MHz and TCK 110 may operate at a frequency of 10 MHz. The frequency divider 210 will therefore divide by N, where N=200/10 or 20. The purpose of the phase-lock-loop formed by the voltage controlled oscillator clock 204, frequency divider 210 and phase detector and reference multiplexer 206 is to synchronize the frequency and phase of the internal clock output 222 to the frequency and phase of TCK 110. The clock output 222 connects to the input of burst controller 208. 
     The burst controller 208 consists of logic that synchronously controls the number of pulses of controlled clock output 224 allowed to pass therethrough during the test mode. During the test mode, and after scan-path data has settled and is available for testing the logic circuits of combinational logic 212, the burst controller 208 allows only two clock pulses from controlled clock output 224 to be applied to combinational logic 212. The purpose of the two pulses is as follows: the first pulse clocks the scan-path test data into the combinational logic 212, and the second pulse signals the end of the time in which combinational logic 212 may correctly operate on this test data. If the signal has not settled by the second clock pulse then the combinational logic 212 cannot perform at speed. 
     By using two clock pulses at the operating frequency, such as in the above example of 200 MHz, a more deterministic test of actual device operation is obtained. Previously, scan-path testing utilized only one clock pulse which only tested the combinational operation of the combinational logic 212 without a quantitative analysis of the time in which the logic took to operate on the scan-path test data. The method and apparatus of the present invention, therefore, adds a new, novel and non-obvious quantitative time dimension to the testing of semiconductor devices with standard low speed logic testers. 
     Referring now to FIG. 3, a scan-path test timing diagram of the present invention is illustrated. A delayed ATPG test utilizing the present invention may consist of four test cycles: scan in/out cycle 302, strobe output cycle 304, stabilize cycle 306, and input cycle 308. During the scan in/out cycle 302, scan-path data to be used in the next test is scanned into the scan-path logic 214 as SDI 106 data values 320. While the data values 320 of SDI 106 are shifting into the scan-path shift registers of the scan-path logic 214, scan-path data resulting from the previous test of the combinational logic 212 is shifted out of the scan-path registers as output data values 322 of SDO 108. The output data values 322 are compared in the logic tester 102 with an expected test pattern, and if there is correlation therebetween, the combinational logic 212 is assumed to be functioning correctly. 
     During scan in/out cycle 302, the scan-path data for testing the combinational logic 212 is shifted into the scan-path registers of scan-path logic 214. After scan in/out cycle 302 has completed shifting the scan-path data into the registers, the scan-path data is strobed out of the registers into the combinational logic 212 by the TCK 110 during the strobe output cycle 304. The scan-path data settles in the input part of the combinational logic 212 during the stabilize cycle 306, in preparation for testing of the combinational logic 212 during the input cycle 308. 
     After the scan-path data settles in the stabilize cycle 306 the input cycle 308 begins. During input cycle 308, the coincidence of CTL 112 a logic low, and leading edge clock pulses 316 and 312 at time 318 begins the scan-path data test of the combinational logic 212. Nothing happens when the clock pulse 316 is at a logic low so that the logic in the clock and burst controller 208 may be set for the pending clock pulses 310a and 310b. Clock pulses 312 of SCK-1 222 are at a higher frequency (faster speed) than the TCK 110 clock pulses 316. The clock pulses 312 and 316 are phase locked in frequency and phase, therefore each clock pulse leading edge, when going from a logic low to a logic high, will occur at substantially the same time as is indicated by the number 318. 
     CTL 112 signal 314 indicates to the burst controller 208 that input cycle 308 is in progress. When TCK 110 goes from a logic low to a logic high, during input cycle 308, the burst controller 208 allows only two clock pulses 310a and 310b to pass therethrough. The clock pulses 310a and 310b are derived from the clock pulses 312 of SCK-1 222. The clock pulses 310a and 310b are applied as G-SCK-1 224 to the combinational logic 212 at time 318. The first clock pulse 310a causes the combinational logic 212 to start processing the scan-path data, and the second clock pulse 310b to stop the data processing. 
     In this way, the present invention tests for proper operation of the combinational logic 212 during a time period determined by the time between clock pulses 310a and 310b. Thus, the combinational logic 212 may be tested at its normal operating speed with a standard low speed logic tester 102. One skilled in the art of testing semiconductor device will readily appreciate that two or more clock pulses 310 may be utilized to test semiconductor devices at speed, and that the test cycles 304 and 306 may be combined, or additional test cycles added during testing of the combinational logic 212. Various high speed logic tests may be performed on the combinational logic 212 by appropriately designed test scan-path logic 214 in combination with control, and phase locked test and system clock signals. The present invention quantitatively performs high speed tests on combinational logic 212 with a standard low speed logic tester 102 that includes testing of both the logic functions and the time in which these functions are performed. 
     The present invention, therefore, is well adapted to carry out the objects and attain the ends and advantages mentioned, as well as others inherent therein. While a presently preferred embodiment of the invention and various aspects thereto has been given for purposes of disclosure, numerous changes in the details of construction, interconnection and arrangement of parts will readily suggest themselves to those skilled in the art and which are encompassed within the spirit of the invention and the scope of the appended claims.