Apparatus and method for testing an integrated circuit using a voltage reference potential and a reference integrated circuit
The present application is a continuation-in-part of a parent application entitled &#34;An IC Selectable Failure Count Testing Device with an Analog Comparator&#34; filed on Jan. 13, 1993 and having Ser. No. 08/003,902. The inventors of this parent application are Robert L. Canella, Greg D. Stevenson, Dave E. Charlton, and Scott A. Earnest. 
     FIELD OF THE INVENTION 
     The invention relates to an apparatus and method for testing integrated circuits. 
     SUMMARY OF THE INVENTION 
     The invention is an integrated circuit testing apparatus and method of testing. 
     In a first embodiment an amplifier amplifies the difference in a reference integrated circuit (RIC) response and a device under test integrated circuit (DUTIC) response to an electrical stimulus. The electrical stimulus is provided at an input of the DUTIC and the RIC by a stimulus circuit. A analog comparator determines when the amplified differences exceeds an adjustable threshold value. The sensitivity of the comparator is adjustable and the desired threshold value is adjusted before testing begins. If the amplified difference exceeds the threshold value of the comparator an error signal is generated. The apparatus of the invention includes a presetable counter which generates a device fail signal if a predetermined number of error signals are generated by the comparator. An initialization circuit loads a selectable value into the counter to provide a variable number of allowable errors before a DUTIC fails the test. A latch circuit latches the device fail signal generated by the counter. 
     In a second embodiment a precision voltage reference potential is adjusted to select a desired minimum potential for a high logic signal and a desired maximum potential for a low logic signal. The integrated circuit testing apparatus this second embodiment also utilizes a RIC. The DUTIC and the RIC respond to the same electrical stimulus. The responses of the DUTIC and the RIC to the electrical stimulus are compared. If the responses have different logic levels the DUTIC automatically fails the test. If the responses have the same logic levels, the test circuit then compares the value of the DUTIC response to the minimum and maximum potentials of the precision voltage reference potential. If the DUTIC response does not lie either above or below the desired minimum and maximum potentials, respectively, the DUTIC fails the test since its potential falls within a failure window lying between the desired minimum and maximum values. On the other hand if the DUTIC response falls above or below either of the desired minimum or maximum values, respectively, and has the same logic state as the RIC the DUTIC passes the test. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic of a first embodiment of the invention. 
     FIG. 2 is a schematic of a second embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The inventions is an integrated circuit testing apparatus and method of testing. 
     A first embodiment is shown schematically in FIG. 1. The invention shown in FIG. 1 depicts the parallel testing of several device under test integrated circuits (DUTICs) 14A-14N. An amplifier 18A-18N amplifies the difference in the RIC 12 response and the DUTIC 14A-14N response to an electrical stimulus. The electrical stimulus is provided at an input of the DUTIC 14A-14N and the RIC 12 by a stimulus circuit 39. The RIC 12 is selected to have a desired response to the electrical stimulus. A analog comparator 22A-22N determines when the amplified differences exceeds an adjustable threshold value. The sensitivity of each comparator 22A-22N is adjustable and the desired threshold value is adjusted before testing begins. If the amplified difference exceeds the threshold value of the comparator an error signal is generated. The apparatus of the invention includes a presetable counter 26A-26N which generates a device fail signal if a predetermined number of error signals are generated by the comparator 22A-22N. An initialization circuit 34 loads a selectable value into the counter 26A-26N to provide a variable number of allowable errors before a DUTIC 14A-14N fails the test. Latch circuit 30A-30N latches the device fail signal generated by the counter 26A-26N. 
     In a second embodiment of the invention allows the user to detect proper output voltage levels at a high rate of speed, between 5-10 ns. Former circuits may have passed a high voltage of 2 volts when current specifications called for the minimum high voltage to be 2.5 volts. The circuit of the invention quickly tests the DUTIC to determine if its response to an electrical stimulus actually meets a desired maximum or minimum potential for the appropriate logic level. 
     In this second embodiment a precision voltage reference potential is adjusted to select a desired minimum potential for a high logic signal and a desired maximum potential for a low logic signal. The integrated circuit testing apparatus this second embodiment also utilizes a RIC. The DUTIC and the RIC respond to the same electrical stimulus. The responses of the DUTIC and the RIC to the electrical stimulus are compared. If the responses have different logic levels the DUTIC automatically fails the test. If the responses have the same logic levels, the test circuit then compares the value of the DUTIC response to the minimum and maximum potentials of the precision voltage reference potential. If the DUTIC response does not lie either above or below the desired minimum and maximum potentials, respectively, the DUTIC fails the test since its potential falls within a failure window lying between the desired minimum and maximum values. On the other hand if the DUTIC response falls above or below either of the desired minimum or maximum values, respectively, and has the same logic state as the RIC the DUTIC passes the test. 
     It is possible to use the test circuit for multiple tests on the DUTIC. In this case each response of the DUTIC to a specific test stimulus is compared to a corresponding response of the RIC to the same test stimulus. It is then possible to utilize a counter circuit to count the number of specific tests failed by the DUTIC. 
     FIG. 2 is one test circuit of the invention. A window voltage reference circuit 300 is presetable to set the limiting voltages of the failure window. The supply potential of the window voltage reference circuit 300 is a precision supply circuit 305 which is capable of providing a voltage at a presetable precise level. In this embodiment the precision supply circuit 305 is adjusted to the desired minimum potential of the high logic level at node 306. A voltage divider circuit 310 is adjustable to determine the maximum potential of the low logic level at node 311. 
     A comparator circuit 315 is used to compare the DUTIC response to the reference potentials set by the window voltage reference circuit 300. A first operational amplifier 320 compares the DUTIC response to the minimum potential set by the window voltage reference circuit 300, and a second operational amplifier 325 compares the DUTIC response to the maximum potential set by the window voltage reference circuit 300. A LT1016 may be selected as the operational amplifiers because of its high speed capabilities. When the outputs of both operational amplifiers 320 and 325 indicate that the DUTIC response falls within the failure window the DUTIC fails the circuit test. However, if the output signal of one of the operational amplifiers 320 and 325 indicates that the DUTIC response is not in the failure window the DUTIC passes the test if the RIC and the DUTIC response to the same electrical stimuli are a logic match. 
     A response of the DUTIC and a RIC are compared in exclusive or gate 330. If the responses have different logic states the DUTIC immediately fails the test. This failure is indicated by a logic high at the output of exclusive OR gate 330. The logic high is an input to a NOR gate 335 which generates a logic low in response to the logic high input. The logic low on the output node of the NOR gate 335 indicates a bad bit. 
     In the case where the DUTIC and RIC response match, either both a logic high or both a logic low, the exclusive XOR 330 generates a logic low. The logic low enables the NOR gate 335. However, if the DUTIC response falls in the fail window the comparator circuit 315 generates a logic high to a second input node of the enabled NOR gate 335, and the NOR gate 335 generates a logic low (test failed). On the other hand, if the DUTIC response is not inside the fail window, the comparator 315 generates a logic low to the second input of the enabled NOR gate 335, and the enabled NOR gate 335 generates a logic high (test passed). 
     It is possible for one skilled in the art to add clocking circuitry and latch circuitry without departing from the spirit and scope of the invention. In addition other enhancements may be used in place of the presently described components. For example, serially programmable digital analog counters(DACs) may provide the voltage reference levels at the comparator inputs. In the case where there are no signal lines available for DAC programming, switches can be used to increment parallel loaded DACs by predetermined amounts, such as 0.1 volt per switch a programmable logic device may also be used in a counter section to reduce the number of devices used. 
     In a more elaborate scheme, two comparator circuits may be used. In this case the first comparator circuit ascertains whether the DUTIC response falls within a high window, i.e. between 2.5 volts and 5 volts, and the second comparator circuit ascertains whether the DUTIC response falls within a logic low window, i.e. between 1.5 and 0 volts. When the DUTIC response falls within either window and the reference circuit and DUTIC have matching logic states the DUTIC passes the circuit test. However, if the DUTIC response falls outside both the high and low windows or if the reference circuit and the DUTIC have mismatched responses the DUTIC fails the circuit test.