Method for the computer-controlled generation of pulse interval sequences with periods of repeating pulse intervals
The application is a continuation of application Ser. No. 08/095,618, filed Jul. 21, 1993, abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a method for the computer-controlled generation of pulse intervals with periods of repeating pulse intervals. 
     2. Background Art 
     A method of this type is disclosed, for example, in German Patent No. 27 46 743 commonly owned by the applicant. 
     The essential feature of the method described in the aforementioned patent is that no dead times occur between the pulse intervals to be generated. The length of the pulse intervals is determined by a decrementer. Before the decrement procedure is run (i.e. before status &#34;0&#34; is reached) the decrementer is loaded with a new value (for the next pulse cycle), so that the new decrement procedure follows on from the previous one immediately. 
     A processor is generally used in implementing this procedure. Most processors operate on the &#34;von Neumann principle&#34;: a controller is supplied with instructions contained in a (program) buffer for execution. Once an instruction has been executed, the processor turns to the next address in the program buffer where the next instruction is stored, and so on. 
     The cycle time of the processor in high speed computers is determined by the storage access time and by the controller unit processing time in equal measure. 
     The generation of pulse interval sequences, particularly for the purposes of testing high-speed storage units and logic circuits, requires the generation of extremely short pulse intervals (in which the test pulses may be placed). 
     According to the state of the art, there are test systems, as illustrated in FIG. 3, which incorporate sub-storages 81, 82, and 83 in addition to a main processor 80 with a central storage. The main processor 80 is connected both directly and through a sub-storage to an address generator (84), data generator (85) and clock pulse generator (86) which, for their part, are connected to a circuit 87 generating pulse interval sequences. 
     The sub-storages hold various special instruction sequences. The generator circuit 84, 85 and 86 obtains its information on the one hand directly from the central storage (general data, e.g. program start addresses, start, stop) and on the other hand (special data, e.g. pulse time relation, interval time, ALU Opcodes (ALU=arithmetic and logical unit)) from the appropriate sub-storages. The provision of sub-storages with various different, special instruction sequences gives a significant advantage from the point of view of programming: the various instruction sequences in the sub-storages may easily be combined together. 
     In this context it should, however, be mentioned that the intermediate circuit of a sub-storage causes a further time overhead. 
     SUMMARY OF THE INVENTION 
     The aim of the present invention is to generate pulse interval sequences with periods of cyclically repeating pulse intervals of the shortest possible pulse duration (e.g.&lt;10 nsec). 
     Said aim of the invention is achieved by means of the following steps. First, data is provided indicating the number and duration of immediately successive identical pulse intervals within a pulse interval sequence. In addition, data is provided indicating the number of repetitions of the pulse interval period within a pulse interval sequence and marking the first and the last pulse interval within the period to be repeated. This data is sequentially cycled under clock control in n stages (n=1, 2, 3, . . . to n) of a processor with a data input stationed at the first stage and a data output station at the nth stage. The data reaching the output station by clock control cycling is supplied to a pulse interval generator for generating the pulse interval sequence, with the clock controlled cycle being interrupted in response to a tag in the output station marking the start of a period to be repeated. After this, the data stages are cyclically addressed under processor control from the first to the last pulse interval of the period to be repeated in accordance with the number of repetitions. The data of each addressed stage is supplied to a pulse interval generator. Finally, after completion of the cyclical addressing, the data input at the input station and the cycling of the data continue. 
     The invention makes it possible effectively to save on the processing time required by the control unit in a processor. The time saving involved is approximately 50%. It results, following an initial phase, from the fact that the measures necessary for processing are executed in a unit separate from the processor simultaneously with the memory accesses in the processor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Embodiments of the invention are revealed in the drawings and will be described in more detail below. 
     FIG. 1 shows a diagrammatic representation of a sequence of repeating pulse intervals to be generated; 
     FIG. 2 shows a diagrammatic representation of the computercontrolled generation of a pulse interval sequence as illustrated in FIG. 1, using a preprocessor, a revolver processor, a postprocessor and a pulse cycle generator; 
     FIG. 3 is a summary view of a system complying with the state of the art showing a main processor and sub-storages; 
     FIG. 4A is a diagrammatic representation of the function sequence in the revolver processor at clock time t1; 
     FIG. 4B is a diagrammatic representation of the function sequence in the revolver processor taking into account clock times t1, t2, t3; 
     FIG. 4C is a diagrammatic representation of the function sequence in the revolver processor taking into account clock times t1 to tn with the output of data to the postprocessor first completed at the start of a multiple repetition of a sequence embracing three records; 
     FIG. 4D is a diagrammatic representation of the function sequence in the revolver processor at a clock pulse following the illustration in FIG. 4A; 
     FIG. 4E is a diagrammatic representation of the function sequence in the revolver processor at a clock pulse following the illustration in FIG. 4D; 
     FIG. 4F is a diagrammatic representation of the function sequence in the revolver processor at a clock pulse following the illustration in FIG. 4E; 
     FIG. 5A is a diagrammatic representation of the data flow in the postprocessor with data output to the pulse cycle generator for the generation of the first successive identical pulse intervals of duration T1; 
     FIG. 5B is a diagrammatic representation of the data flow in the postprocessor with data output following on from that illustrated in FIG. 5A to the pulse cycle generator for the generation of further successive identical pulse intervals of duration T2; 
     FIG. 5C is a representation of the functions of the postprocessor; 
     FIG. 6 is a diagrammatic representation of the synchronization of the total system consisting of the preprocessor, revolver processor and postprocessor. 
    
    
     FIG. 1 shows, in a diagrammatic representation, a sequence of repeating intervals to be generated: three pulse intervals of duration T1 (3×T1) are followed by five pulse intervals of duration T2 (5×T2) and two pulse intervals of duration T3 (2×T3). Said sequence of pulse intervals 3×T1-5×T2-2×T3 is to be repeated 1024 times (indicated by 1024 x). Let it be assumed that the factor 3 and the value of time duration T1 is stored at address 1, that the factor 5 and the value of time duration T2 is stored at address 2 and that the factor 2 and the value of time duration T3 is stored at address 3 and that the start and end of the cycle of 1024 repetitions is stored at address 1 and 3. 
     FIG. 2 shows a diagrammatic representation of the computer-controlled generation of a pulse interval sequence as revealed in FIG. 1 using a preprocessor 1, a revolver processor 2, a postprocessor 3 and a pulse cycle generator 4. 
     The tasks for the pulse interval sequence to be generated are available (stored) in preprocessor 4. 
     Indirect addressing is not possible in high-speed processors complying with the state of the art for reasons of speed, high-speed processors of this type are, thus, generally programmed in machine language and not in a higher programming language (which would make use of indirect addressing). 
     The preprocessor in the system embodied in this invention, however, does permit use of a higher programming language with indirect addressing. The disadvantages resulting from this are avoided by other measures, as revealed hereinafter, and are outweighed by further advantages. In addition to control information, the preprocessor supplies the revolver processor with records containing data regarding the number of pulse intervals of the same duration following immediately on from one another (such as 3×T1, 5×T2, 2×T3) and information regarding the cyclical repetition (e.g. 1024 times) of pulse interval sequences, all accomplished, however, without indirect addressing. 
     The function of the revolver processor 2 is described in detail in conjunction with FIGS. 4A to 4F. As soon as record 1 has passed through the input station after n-clock cycles to the hypothetical nth stage (output station) of the revolver processor in the example given, the further input of data at the input station is suspended until output of 1024 repetitions of the pulse interval period 3×T1, 5×T2, 2×T3 is concluded. Data input and the phased further switching of the information (in the direction of the arrow in FIG. 4) will then be continued. Although data input from preprocessor 1 is stopped at revolver processor 2 during the 1024 repetitions of the pulse interval period, this time may be used by preprocessor 1 for indirect addressing (execution of pointer address instructions) prior to the output of data records to the revolver processor. 
     In this manner, once the initial phase has been completed, that is the one-time loading of all stages of revolver processor 2, the times necessary for the execution of address instructions no longer have any effect on time requirements in the system as a whole. 
     The preprocessor marked 1 in FIG. 2 has, thus, a special functional task. As already mentioned, its particular purpose is to supply the revolver processor 2 with records in sequence. 
     Such a simple function could, however, also be undertaken by units less complex than a processor, were it not necessary to satisfy a particular requirement which can only be met by a processor. This results from the requirement in the generation of pulse interval sequences for test purposes, in particular, for addressing through variable indirect addressing `pointers`. In the absence of such `pointers`, for example, it would only be possible to branch from one record address to another, e.g. 
     from address A1 (where record 1 is located) 
     to address A2 (where record 2 is located) and then 
     to address A3 (where record 3 is located), etc. 
     Frequently, however, it is necessary to make an intermediate branch to a `pointer` address AX (where an address value variable by the program is located). This address value could have the value for address 10 on the first execution of the branch command, and have a value increased by ten, for instance, that is address 20 in this case, on the second execution. 
     FIGS. 4A to 4F show a diagrammatic representation of the functional procedure of the revolver processor; FIG. 4A being at clock time t1. This simplified representation interprets the records (which contain information such as 3×T1, beginning or end of a repetition cycle) as the content of the chambers of a magazine in a `revolver` processor rotating in the direction shown by the arrow. The preprocessor supplies the records to the input station. The records are output at the station marked output to the postprocessor 3, from where the information is passed further to the pulse cycle generator 4. The revolver processor should have n stages (`revolver magazine chambers`) to accommodate the records. At the time of clock cycle t1, the record is input by preprocessor 1 into the revolver processor 2. This record contains, as already mentioned, information from address 1 of the preprocessor: 3×T1 and start of a cycle of 1024 repetitions. With each further clock pulse, the contents of the `stages of the revolver processor` move one stage further in the direction shown by the arrow and a new record is also input by preprocessor 1 at the input station into revolver processor 2 with each new clock cycle. 
     FIG. 4B shows the status of the revolver processor at clock cycles t1, t2 and t3. Record 1 has moved on from position 1 in FIG. 4A to position 3 in FIG. 4B. Record 2, which has since been input at clock cycle t2 has moved through the input station (position 1) to position 2, whilst record 3 is input to position 1 at clock cycle t3. 
     The records sent from the preprocessor to the revolver processor no longer contain any branching or similar operations. The actual task of the preprocessor is to process the original data flow, in which branch operations still occur, so that only records are output to the revolver processor (and corresponding control information such as start tag of a program (sub-)loop via a number of addresses; number of loop cycles; end tag for the program (sub-)loops; additional data ultimately to be processed in the postprocessor, such as cycle time and number of cycles or pointer address for sub-storage in the postprocessor). 
     FIG. 4C shows a diagrammatic representation of the functional procedure of the revolver processor at a later time, at which record 1 has reached the output station. At this time, record 1 is located in position n of the revolver processor, record 2 in position n-1 of the revolver processor, and record 3 in position n-2. The clock cycles at which these records were input at the input station are indicated by t1, t2 and t3. Record 1 in position n includes, amongst other data, the information that the cycle of 1024 repetitions begins here. Record 3 in position n-2 shows that the end of the cycle to be repeated 1024 times is located at this point. This information constitutes a data flow control for records 1, 2 and 3 which takes into account the 1024 repetitions of the cycle 3×T1, 5×T2 and 2×T3. First, as illustrated in FIG. 4C, the information in record 1 will be supplied to the postprocessor. Then (FIG. 4D) record 2 will be transferred from position n-1 to position n and record 3 from position n-2 to position n-1. Record 1 from position n in FIG. 4C is passed into the position released by record 3 at n-2 (FIG. 4D). As now (FIG. 4D), record 2 is located in the output position n, its information is supplied to the postprocessor. Then a further cyclical shift of the records takes place (as shown in FIG. 4E) with the effect that record 3 now moves from position n-1 (FIG. 4D) to position n (FIG. 4E), record 1 from position n-2 (FIG. 4D) to position n-1 (FIG. 4E) and record 2 from position n (FIG. 4F) to position n-2) to position n-2 (FIG. 4D). At the time illustrated in FIG. 4D, record 2 in the output station is transferred into the postprocessor. Then a new cyclical shift occurs (as is clear from FIG. 4E) of records 1, 2, and 3 analogous to the previous shift, so that, as can be seen from FIG. 4F, record 1 once again is located in position n. At this time, the first of the 1024 repetitions of the cycle 3×T1, 5×T2 and 2×T3 is complete, so that only a subsequent 1023 repetitions (controlled by the decrementer) remain to be processed. Data input from the preprocessor into the revolver processor is locked during the repetitions of the cycle in the revolver processor. Data input can only be continued once the 1024 repetitions of the cycle 3×T1, 5×T2 and 2×T3 have been completed. The content of the output station in the revolver processor is transferred to the first stage of the postprocessor, without repetition data, with every &#34;shift&#34; at the output station; in this way the information transferred is serialised and further simplified. 
     FIGS. 5A and 5B show a diagrammatic representation of the data flow in the postprocessor 3. In the simplified representation, the postprocessor receives the individual data records (e.g. 3×T1, 5×T2 and 2×T3) sequentially from the output station of the revolver processor. This information is then pushed through the individual stages of the postprocessor in a manner specific to the record, as in a shift register. As soon as, as is illustrated in FIG. 5A, the information 3×T1 from record 1, i.e. three consecutive pulse intervals of duration T1, reaches the output of the postprocessor, this information is passed to the pulse cycle generator, in which these pulse cycles are generated under the control of the counter. The preferred embodiment of a pulse cycle generator of this nature is described in German patent application P 28 79 709 by this applicant. 
     The postprocessor is not, however, only required to fulfil the function of a shift register, it must (and this is what requires a processor) be able to execute branches to specific addresses. In order to assign 3×T1, the pulse interval generator 4 must be supplied with the value for T1, which is stored at a specific address in the postprocessor, three times in succession. 
     With the next clock cycle of the postprocessor the situation arises as is shown diagrammatically in FIG. 5B. The information originating from record 2 is now found at the output to the postprocessor, i.e. 5×T2. This information is now supplied to the pulse cycle generator 4, in order now to follow the three-fold generation of pulse intervals of duration T1 with a five-fold generation of pulse intervals each of duration T2. This process will then be continued with a double generation of pulse intervals with pulse duration T3, in its turn followed by a three-fold generation of pulse intervals with a duration T1, a five-fold generation of pulse intervals with a pulse duration T2, a double generation of pulse intervals with pulse duration T3, and so on, until the 1024 repetitions of the 3×T1, 5×T2 and 2×T3 cycle have been completed. 
     FIG. 5C shows a detailed functional illustration of postprocessor 3 in connection with the pulse cycle generator 54. 
     The records arriving from the revolver processor 2 (in addition to the appropriate control information, they each include the number and duration of pulse intervals, e.g. 3×T1) are clock-driven (c) and shifted in the direction of the arrow through the register stages 31, 32, 33, 34, 35 and 36. These register stages are clocked by the revolver processor clock on line 37. Also exploiting the advantage from the point of view of programming of sub-storage 41 known from the prior art at this point, too, it is possible to connect the intermediate circuit 40 of a sub-storage 41 and a delay element 42 between two register stages. Specific data is passed through sub-storage 41: e.g. cycle time, number of identical consecutive cycles. Other information (preferably control data, e.g. read/write commands, control signals for any subsequent processors connected such as signal generators, timing generators, etc.) are passed direct to the next register level through the delay element 42. The delay is used to compensate for the additional access time caused by sub-storage 41. The time delay between register stages 35 and 36 caused by the intermediate circuit 40 is compensated for by a delay element 38. Register stages 31 to 35, in particular, hold the addresses of the memory locations at which the desired values, e.g. pulse interval duration, are stored. Access to a value of this kind is possible via the memory address held in the register. 
     The register of postprocessor 3 identified as 50 allows extremely rapid processing in accordance with the invention. It does not hold address data, as do the register stages 31-35 referred to above, but the values that may be called at these addresses, amongst other data, e.g. the value for pulse duration T1. If it is necessary to access this value a number of times during the course of processing, this may now take place directly and not indirectly through memory area addresses. An advantageous time saving is created in this way. The value for T1 is passed from this register 50 (for example, it carries data such as 3×T1 and corresponding control data) via line 51 to the pulse cycle generator 4 and the factor 3 is passed via line 53 to the decrementer 55, the control data being passed via line 52 to the sub-processors not illustrated here (e.g. signal generator, timer generator). 
     An oscillator 56 provides the clock signal for pulse cycle generator 4 and to revolver processor 2 via lines 64, 65. This clock signal may optionally also be used for the preprocessor through line 66, unless it has its own, independently running oscillator. The output 61 from the AND circuit with the three inputs 
     59 activate postprocessor 
     60 counter status 0 on decrementer 55 
     58 pulse interval generated by cycle generator 4 
     is used to clock register 50 via line 62 and to synchronize the revolver processor via line 63. All lines 65, 66 and 63 lead to a synchronization circuit for the entire system shown in FIG. 6. 
     FIG. 6 shows a diagrammatic representation of the synchronization of the complete system, consisting of preprocessor, revolver processor and postprocessor. As in FIG. 2, the preprocessor is identified as 1, the revolver processor as 2 and the postprocessor as 3. The information flows from the processors are indicated diagrammatically as broad arrows. The preprocessor 1 and the revolver processor 2 are clocked via lines 66 and 65 (see FIG. 5). The output clock signals of the revolver processor are sent on line 37 to an incrementer/decrementer 71. 
     Said clock signals increment said counters, whilst output signals from the postprocessor on line 63 decrement the counters. A signal on line 63 means that repetitions on the postprocessor have been concluded, i.e. that the information 3×T1 has lead to a three-fold repetition of the generation of a pulse interval with the pulse duration T1. The count on counter 71 is applied as value D to a comparator circuit 72 in which said value is compared with value E on line 73, which stands for the number of register stages in the postprocessor. As soon as the comparator circuit 72 determines that there is agreement between D and E, it stops the revolver processor clocking via its output line 77. 
     In cases where D&lt;E, revolver processor clocking is released again. 
     The output clock signals of preprocessor 1 are sent to an incrementer/decrementer 74. These clock signals increment the counter, whilst the output clock signals of the revolver decrement this counter 74. The value A of counter 74 is sent to a comparator circuit 75, in which said value is compared with the value B on line 76, the number of revolver processor stages (76). Where the two values are equal, the preprocessor clocking is halted via the output line 79 of the comparator circuit 75. Said clocking is released again in cases where A&lt;B. 
     It is clear from the above that the processors are synchronized from &#34;bottom to top&#34;, i.e. postprocessor 3 determines the time at which revolver processor 2 may supply data to postprocessor 3 and revolver processor 2 determines the time at which preprocessor 1 may supply data to revolver processor 2.