Address generating circuit and CD-ROM device using the same
This is a continuation of application Ser. No. 07/794,147 filed Nov. 19, 1991 now abandoned. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to an address generating circuit and a compact disk read only memory (CD-ROM) device using the same, and more particularly to, an address generating circuit which generates an address of a memory in case of error correction and a CD-ROM device using the same. 
     BACKGROUND OF THE INVENTION 
     A conventional CD-ROM device includes a central processing unit (CPU), processing unit and a random access memory (RAM). 
     In error correction of data transferred from a CD-ROM to the RAM, the signal processing unit supplies the CPU with an error correction process starting signal. The CPU supplies the signal processing unit with an address signal calculated in accordance with the error correction process starting signal. The signal processing unit supplies the RAM with the calculated address signal as a RAM address signal, at which stored data are corrected in the RAM. 
     According to a conventional address generating circuit, however, there is a disadvantage in that many steps are required to generate addresses, because the RA address signal is supplied from the signal processing unit as a result of logic calculations by the CPU. Therefore, the probability of correcting a data error may remain low. Further, the CPU can not preform properly, because the CPU is burdened with heavy loads including generating addresses in accordance with a logic calculation. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the invention to provide an address generating circuit in which the probability of data error correction is high, and to provide a CD-ROM device using the same. 
     It is another object of the invention to provide an address generating circuit in which the load an a CPU is reduced, and to provide a CD-ROM device using the same. 
     According to a first feature of the invention, an address generating circuit comprises: 
     a line counter for counting lines of addresses of a RAM, said RAM addresses being defined by line and column coordinates; 
     a column counter for counting column addresses of the RAM: 
     a first logic circuit for making a sum of outputs of the line and column counters; 
     an address generator for operating on the output of the logic circuit; 
     a first selector for selecting an output from outputs of the line and column counters and the modulator; 
     a ROM in which start addresses of the lines of addresses are stored: 
     second selector for selecting an output from outputs of the line and column counters; and 
     a second logic circuit for making a sum of outputs of the ROM and the second selector to be supplied to the RAM as an address. 
     According to a second feature of the invention, a CD-ROM device comprises: 
     RAM for storing data to be read from a CD-ROM; 
     a CPU for controlling operation of reading data from the CD-ROM; and 
     a signal processing unit for processing signals between the RAM and the CPU, the signal processing unit comprising an address generating circuit which comprises a line counter for counting a line number of addresses of a RAM, a column counter for counting a column number of addresses of the RAM, a first logic circuit for making a sum of outputs of the line and column counters, a modulator for modulating an output of the logic circuit, a first selector for selecting an output from outputs of the line and column counters and the modulator, a ROM in which start addresses of the lines of addresses are stored, a second selector for selecting an output from outputs of the line and column counters, and a second logic circuit for making a sum of outputs of the ROM and the second selector to be supplied to the RAM as an address. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be explained in more detail in conjunction with appended drawings wherein: 
     FIG. 1 is a block schematic diagram of a conventional CD-ROM device: 
     FIG. 2 is a block schematic diagram of a signal processing unit of a CD-ROM device including an address generating circuit in a preferred embodiment according to the invention; 
     FIG. 3 is an address map showing addresses, of a RAM generated by the address generating circuit in the preferred embodiment according to the invention; 
     FIG. 4 is a list showing contents of elements of the address generating circuit in case of generating Q-system addresses; and 
     FIG. 5 is a list showing contents of elements of the address generating circuit in case of generating P-system addresses. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before describing an address generating circuit and a CD-ROM device in a preferred embodiment according to the invention, the conventional address generating circuit described before will be explained in conjunction with FIG. 1. 
     A conventional CD-ROM device includes a CPU 7, a signal processing unit 8 and a RAM 9. The RAM 9 is filled with data read from a CD-ROM device (not shown). The stored data is processed in the signal processing unit 8. In this operation, error data may have been stored in the RAM 9. In such a case, the error data should be corrected with as high probability as possible. For this purpose, an address of RAM 9 in which the error data is stored must be generated in address signal generating circuit. In the CD-ROM device, the RAM address signal is supplied from the signal processing unit 8 as a result of logical calculation process by the CPU 7, as explained before, so that the probability of error data correction is relatively small, and the CPU 7 is burdened with heavy loads including such address generation. 
     Next, an address generating circuit in a preferred embodiment according to the invention will be explained. FIG. 2 shows an address generating circuit in a preferred embodiment. The address generating circuit includes a line counter 1 which counts line values, a column counter 2 which counts column values thereof, a first arithmetic logic unit 3 which makes a sum of outputs of the line and column counters 1 and 2, a ROM address generator 4 which operates on the output of the first arithmetic logic unit 3, a first selector 11 which selects an output from outputs of the line and column counters 1 and 2 and the address generator 4 in accordance with P- and Q-addressing selecting signals 101 and 102 and a Q-parity selecting signal 103, a ROM 5 which stores start addresses of the address lines and supplies an output in correspondence with an output of the first selector 11, a second selector 12 Which selects an output from outputs of the line and column counters 1 and 2 and the ROM 5 in correspondence with a Q-parity selecting signal 103 and P-OR-Q addressing selecting signal 101 or 102, and a second arithmetic logic-unit 6 which makes a sum of outputs of the ROM 5 and the second selector 12. The ROM address generator 4 generates an output signal of 0 to 25 corresponding to an input signal supplied from the first arithmetic logic unit 8, as indicated in the below Table I. 
     
                       TABLE I                                                     
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INPUT SIGNAL   OUTPUT SIGNAL                                              
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 0˜25    0˜25                                                 
26˜51    0˜25                                                 
52˜77    0˜25                                                 
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.              .                                                          
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     The ROM 5 stores a start address &#34;0000&#34;, &#34;0043&#34;, &#34;0086&#34;, . . . of each line in the RAM 9 at a counted number of &#34;0&#34; of the column counter 1, as illustrated in an address map of the RAM 9 shown in FIG. 3, in which Q- and P-addressing systems of address generation are indicated by arrows. 
     Next, operation of the address generating circuit will be explained in conjunction with FIGS. 3 to 5. First, the operation of generating addresses of a Q-addressing system will be explained in conjunction with FIG. 4. In operation, the first arithmetic logic unit 3 makes a sum of outputs of the line and column counters 1 and 2. The ROM address generator 4 generates a number based on the output of the first arithmetic logic unit 3. When its input is &#34;26&#34;, then the address generator 4 outputs &#34;0&#34;, and increases the number again from zero, i.e., 0,1,2 . . . out. When the column value of the column counter 2 becomes &#34;48&#34; or &#34;44&#34;, these values are identified as Q-parities, so that predetermined addresses of &#34;1118&#34; and &#34;1144&#34; are designated in the ROM 5. Then, the column values output of the column counter 2 is set to be &#34;0&#34;. The first selector 11 selects the output of the address generator 4 in response to the Q-addressing system selecting signal 101 which is supplied to the ROM 5 when the column value of the address column is not more than &#34;42&#34;. The ROM 5 supplies the start address of the address lines, the addresses to be supplied to the second arithmetic logic unit 6. On the other hand, the second selector 12 selects an output of the column counter 2 in correspondence with the P-OR-Q-addressing selecting signal 101 or 102 to be supplied to the second arithmetic logic unit 6. The second arithmetic logic unit 6 makes a sum of the start address read from the ROM 5 and the counted values of the column counter 2, the sum to be supplied to the RAM 9 as the RAM address signal 106. When the counted value of the column counter 2 is &#34;43&#34;  or &#34;44&#34;, then the first selector 11 selects the output of the column counter 2 to be supplied to the ROM 5 in correspondence with the Q-parity selecting signal 103, so that the ROM 5 supplies the addresses of &#34;1118&#34; or &#34;1144&#34; to the second arithmetic logic unit 6, respectively. The second selector 12 selects the output of the line counter 1 to be input to the second arithmetic logic unit 6 in correspondence with the Q-parity selecting signal 103. The second arithmetic logic unit 6 makes a sum of the predetermined address of &#34;1118&#34; or &#34;1144&#34; and the counted number of the line counter 1 to be supplied to the RAM 9 as the RAM address signal 106. 
     Next, the operation of generating addresses of a P-addressing system will be explained in conjunction with FIG. 5. In operation, the first selector 11 selects the output of the line counter 1 in accordance with the P-addressing system selecting signal 101 supplied to the ROM 5 when the column number of the address column is at most &#34;42&#34;. The ROM 5 supplies the start address of the address lines to be supplied to the second arithmetic logic unit 6. On the other hand, the second selector 12 selects an output of the column counter 2, in correspondence with the P-OR-Q-addressing selecting signal 101 or 102, to be supplied to the second arithmetic logic unit 6. The second arithmetic logic unit 6 makes a sum of the start address read from the ROM 5 and the counted value of the column counter 2, the sum to be supplied to the RAM 9 as the RAM address signal 106. 
     When the counted value of the column counter 2 is &#34;43&#34; or &#34;44&#34;, then the first selector 11 selects the output of the column:counter 2 to be supplied to the ROM 5 in correspondence with the Q-parity selecting signal 103, so that the ROM 5 supplies the addresses of &#34;1118&#34; or &#34;1144&#34; to the second arithmetic logic unit 6, respectively. The second selector 12 selects the output of the line counter 1 to be supplied to the second arithmetic logic unit 6 in accordance with the Q-parity selecting signal 103. The second arithmetic logic unit 6 makes a sum of the predetermined address of &#34;1118&#34; or &#34;1144&#34; and the line number of the address line, the sum to be supplied to the RAM 9 as the RAM address signal 106. 
     In a CD-ROM device, the signal processing unit 8 includes the address generating circuit as explained above, so that the RAM address signal 106 is directly supplied to the RAM 9 from the signal processing unit 8 without using the CPU. Therefore, fewer steps are required to generate addresses than those required in the conventional CD-ROM device, so that the probability of the error correction increases. Further, the load of the CPU is reduced, so that the CPU can to perform properly. 
     Although the invention has been described with respect to a specific embodiment for complete and clear disclosure, the appended claims are not to be thus limited, and alternative constructions that may occur to one skilled in the art fairly fall within the basic teaching herein set forth.