Circuit for generating accurate voltage levels below substrate voltage
FIELD OF THE INVENTION 
     The present invention relates to circuits using bipolar transistors for generating voltage levels below substrate voltage levels for use in video display applications. The present invention is particularly suited to generating a negative voltage swing for the gate driver of a Liquid Crystal Display (LCD) system. 
     BACKGROUND OF THE INVENTION 
     It is known in the prior art to provide voltage supplies below ground for various applications. However, these methods do not disclose how to provide the needed voltage supplies using a reduced number of integrated circuit (IC) chips, where each chip has its substrate connected to a ground potential. In such cases, providing an additional IC chip clamped to a specific voltage below ground would increase the size and cost of the overall device. 
     Furthermore, the prior art methods for providing below ground voltages on a substrate which is connected to ground result in forward-biased diodes located between the epitaxial layer and the substrate. The problem with using such forward biased diodes is that the overall device cannot span as great a voltage range because the voltage swing on one end will be limited by the forward voltage of the diode. 
     Also, other circuits are known in the prior art for generating voltages above ground, but these circuits have not been used to generate voltages below ground, in the manner contemplated by the present invention. 
     Other prior art circuits have employed diodes or transistors to clamp voltages in overload conditions, but not to provide a below-substrate voltage that is well defined. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a circuit for providing below-substrate voltages on an IC chip. The below-substrate voltages are achieved without the limitations resulting from forward biasing diodes connected between an epitaxial layer and the substrate. For example, a voltage swing between +12 V and -10 V can be achieved on the same substrate employing a process designed for 12 V. 
     According to an embodiment of the invention, the below substrate voltages are obtained by employing a circuit that utilizes a simple operational amplifier coupled to a pair of resisitors such that a positive reference voltage is reliably converted to a negative voltage. The op amp includes a differential pair of pnp transistors to which an npn transistor is connected as an emitter follower. The op amp is constructed and operated such that the bases of the pnp transistors and the collector of the npn transistor never fall below ground voltage. 
     A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set for an illustrative embodiment in which the principles of the invention are utilized. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram illustrating a circuit utilizable for generating below substrate voltages according to one embodiment of the present invention. 
     FIG. 2 is a schematic diagram illustrating another circuit utilizable for generating below substrate voltages according to another embodiment of the present invention. 
     FIG. 3 is a schematic diagram illustrating a circuit for generating below substrate voltages according to a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 illustrates a circuit for generating below substrate voltages employing a voltage multiplier circuit having an output voltage (Vo, at output terminal 50) defined by the following equation: 
     
         Vo=(1+R.sub.1 /R.sub.2)×V.sub.BEQ1                   (1), 
    
     where V BEQ1  is the base-emitter voltage of transistor Q 1 . 
     As shown in FIG. 1, three resistors R 1 , R 2  and R 3  are connected in series. NPN transistor Q 1  is connected such that its collector is grounded, its base is connected to the node at which resistors R 1  and R 2  intersect, and its emitter is connected to the node at which resistors R 2  and R 3  intersect. The end of resistor R 3  that is not connected to resistor R 2  is at a potential equal to V-. The value of resistor R 3  determines the emitter current of transistor Q 1  and is chosen such that the following equations are satisfied: 
     
         I.sub.R3 =[ABS(V-)-ABS(Vo)]/R.sub.3                        (2); 
    
     
         I.sub.R3 &gt;V.sub.BE /R.sub.2                                (3) 
    
     The circuit of FIG. 1 has limited application because of the large temperature coefficient of V BE . Thus, it is sometimes impractical to use V BE  as a reference. 
     Another circuit for generating below substrate voltages is shown in FIG. 2. This circuit is very similar to the circuit of FIG. 1 except that a zener diode Z 1  is located in series with the base-emitter junction of transistor Q 1 . Like numerals are used in FIG. 2 for elements equivalent to those in FIG. 1 (ie. resistors R 1 , R 2 , R 3 , and transistor Q 1 ). Thus, with the circuit of FIG. 2, Vo is defined as follows: 
     
         Vo=(1+R.sub.10 /R.sub.20)×(V.sub.BE +V.sub.Z1)       (4), 
    
     where V Z1  is the voltage drop across diode Z 1 . 
     Unfortunately, zener diode characteristics are not predictable with a number of processes. Therefore, the output voltage Vo is not completely reliable in all cases and, thus, the FIG. 2 circuit also has limited application. 
     FIG. 3 illustrates a circuit for generating a negative reference voltage from a positive reference voltage V REF , which may be produced from a bandgap reference voltage or an external supply voltage. 
     As shown in FIG. 3, a simple op amp is formed by transistors Q 10 , Q 20  and Q 30  and resistors R 30  and R 40 . Transistors Q 10  and Q 20  form a differential amplifier having a one-sided load represented by resistor R 30 . Transistors Q 10  and Q 20  are pnp transistors having a current source 100 connected to the emitter of each transistor. Current source 100 transmits a current I x . The collector of transistor Q 20  is coupled with the base of transistor Q 30 . 
     In closed loop form, resistor R 20  provides negative feedback from the emitter of transistor Q 30  to the base of transistor Q 20 . With the feedback loop thus closed, resistor R 30  draws a current equal to the V BE  of transistor Q 30  divided by the resistance value of resistor R 30 . The current through resistor R 30  sets the current flowing through transistor Q 20 . As a result, the current which flows the transistor Q 10  is as follows: 
     
         IQ.sub.10 =I.sub.x -IQ.sub.20                              (5) 
    
     The current flowing through transistor Q 30 , is set in large part by the current flowing through resistor R 40  minus I x , except for any residual current flowing through transistor Q 20 . Generally speaking, the circuit is designed such that most of the current flowing through resistor R 40  also flows through transistor Q 30 . 
     Current gain is provided by using the emitter follower transistor Q 30 . The emitter follower transistor Q 30  must be an npn transistor to avoid forward biasing any diodes. Therefore, excess current must be drawn through resistor R 40  so that transistor Q 30  has enough current for proper biasing. It is possible to implement transistor Q 30  as a Darlington amplifier. 
     A reference voltage (V REF ) may be set at any desired voltage. In the preferred embodiment, a voltage of 2.5 volts may be used (of course, 1.25 V and 5 V may also be used). A pair of resistors R 10  and R 20  are connected in series between V REF  and an output voltage Vo. With the arrangement shown in FIG. 3, Vo satisfies the following equation: 
     
         Vo=-(R.sub.20 /R.sub.10)×V.sub.REF                   (6) 
    
     The FIG. 3 circuit is provided with optional components, e.g. resistor R 60  for electro-static discharge (ESD) protection; resistor R 60  compensates for the error due to the input bias current. Transistor Q 40  and resistor R 50  act as a voltage clamp. Transistor Q 50  acts as a clamp diode for transistor Q 40 , but is not absolutely necessary. Capacitor C c  provides frequency compensation. Voltage V GL  is the deselect gate bias for an active matrix liquid crystal display. 
     Ideally current source I x  should satisfy the following equation for minimum temperature variation of offset voltage: 
     
         I.sub.x =2×V.sub.BEQ3 /R.sub.3                       (7) 
    
     However, satisfying this equation is not a strict requirement. 
     With the embodiment shown in FIG. 3 and the equations associated therewith, it is apparent that the collector of npn transistor Q 30  and the bases of pnp transistors Q 10  and Q 20  never swing below ground. 
     The resistance values of the resistors may be selected depending upon the system requirements. Resistance values that may be used in the circuit of FIG. 3 are hereby noted by way of example: R 10  =50k; R 20  =94K; R 30  =60k; R 40  =50k; and R 60  =10k. 
     Although the present invention has been disclosed with particular reference to the preferred embodiment, one of ordinary skill in the art would be enabled by this disclosure to make various modifications to this invention and still be within the scope and spirit of the present invention as embodied in the appended claims.