Automatic identification system for objects or persons by remote interrogation
BACKGROUND OF THE INVENTION 
     The present invention relates to an automatic identification system for objects or persons by remote interrogation. It has numerous applications, particularly in the field of detecting persons carrying badges or in the accounting and/or checking of stocked goods or goods sold in stores. 
     In known automatic identification systems, it is possible to recognize an object or a person carrying respectively a tag or a badge provided with a code circuit and passing under or in the vicinity of a monitoring gate. This gate then emits RF (radio frequency) pulses towards the tag or badge. These pulses are used for energizing the tag and interrogating the code stored therein. The code of the tag or badge carried by the object or person is in this way recognized. Such a device is described in EP-A-241 148. 
     Such systems do not make it possible to recognize in a quasi-simultaneous manner a plurality of objects or persons by the successive determination of each bit constituting the code contained in the tag or badge of said objects or persons and therefore do not make it possible to process a large number of objects. 
     SUMMARY OF THE INVENTION 
     The object of the invention is to make it possible to detect and recognize in a quasi-simultaneous manner all the objects or persons in a group by simultaneously interrogating them and thus making it possible to process a large number of objects. 
     The invention consists of the emission of RF signals by a gate, said RF signals being questions to which the tags reply by a consent signal or by the absence of a signal, thus enabling the gate to determine the elements of codes contained in said group of objects. When a code has been found, the tag containing said code is inhibited in order to permit the detection of other codes. 
     Use will be made throughout the description and interchangeably of the terms tag, badge or answering E/R (emitter/receiver) means, as well as the terms gate or interrogating E/R (emitter/receiver) means. 
     In addition, throughout the description, the term &#34;inhibit&#34; will be understood to mean the passage into a silent or inactive mode, i.e. where a tag or answering means no longer reacts. 
     The invention more specifically relates to an automatic identification system for objects or persons by remote interrogation comprising: 
     interrogating E/R (emitter/receiver) means incorporating a device for emitting RF (radio frequency) signals having a modulator generating different wave shapes and a RF (radio frequency) signal reception device and 
     answering E/R means having a circuit for receiving coded information coming from the interrogating E/R means and the emission of an answer, a supply device and storage means in which is stored a digitized code linked with each object or person, 
     characterized in that: 
     said answering E/R means has at least one emitting/receiving antenna forming part of said reception and emission circuit, a checking and sequencing circuit controlling all the signals necessary for a complete code search sequence and inhibiting means connected to said checking and sequencing circuit and able to inhibit the answering E/R means, and said interrogating E/R means being able to continuously emit a high frequency signal, control by processing means the tasks necessary for the search of the digitized codes delivered by the answering E/R means and store in a memory said digitized codes. 
     Advantageously, the inhibiting means comprise at least two flip-flops, the first flip-flop being a temporary inhibiting flip-flop able to inhibit the answering E/R means during a search sequence. The second flip-flop is a definitive inhibiting flip-flop ensuring the inhibition of the answering E/R means when the sought digitized code has been correctly received and stored by the interrogating E/R means. 
     These inhibiting means remain active for as long as the answering E/R means are energized. When the power supply is interrupted, the answering E/R means are again able to respond to a new interrogation sequence. 
     The digitized code also has an identification code of the object or person type, an optional random subcode ensuring the unitary identification of the person or object in question and optionally a check code for checking the good integrity of the transmitted information. These codes are not necessarily following one another and can instead be interleaved, particularly the check code, in order to check the validity of information transmitted during the interrogation. 
     According to a feature of the invention, the storage means of the answering E/R means comprise a code memory and an address counter able to indicate or select each element constituting the digitized code stored in the memory, said counter being connected to the checking and sequencing circuit by a &#34;clock&#34; connection for controlling the advance of the counter and a zeroing connection for indicating or selecting the first element of the digitized code. 
     According to the invention, the modulator of the interrogating E/R means generates at least two wave shapes combined together to form at least four coded information types. 
     The supply or energizing device comprises a circuit for recovering energy coming from the interrogating E/R means. 
     Advantageously, the processing means of the interrogating E/R means ensuring the control of the tasks necessary for the search of the digitized codes make it possible to perform the following stages: 
     a) transmitting a &#34;start of search sequence&#34; information corresponding to the interrogation of the first element of the digitized code, 
     b) awaiting the answer supplied by the answering E/R means, 
     c) storing in the memory of the interrogating E/R means a logic state corresponding to the element being processed of the digitized code and transmitting &#34;type&#34; information corresponding to the answer received in order to interrogate the following code element, 
     d) return to stage b) up to the end of the search sequence when the final code element is identified, 
     e) verification of the validity of the digitized code received, 
     f) storage in said memory of the digitized code received when said received code is valid and rejection of the said digitized code in the opposite case with the transmission of a &#34;sequence start and erroneous preceding code&#34; information and return to stage b), and 
     g) return to stage a) when the received code is valid in order to interrogate other codes until a zero code is obtained. 
     According to another feature of the invention, the checking and sequencing circuit of the answering E/R means makes it possible to perform the following stages: 
     a) reception of the &#34;start of search sequence&#34; pulse transmitted by the interrogating E/R means, 
     b) zeroing the address counter of the storage means of the answering E/R means, 
     c) temporary inhibiting of the answering E/R means or frequency emission up to the reception of the next coded information coming from the interrogating E/R means, as a function of the activity of the answering E/R means, the logic state of the code element being processed and the type of the last information received, activity being the opposite to inhibition, 
     d) incrementation of the address counter of the code storage means and checking the value of said address with the passage to stage g) when said value corresponds to the final element of the processed code, 
     e) reception of the information transmitted by the interrogating means corresponding to the answer emitted by the answering E/R means in the first stage c) or the reception of a start of sequence information, 
     f) temporary inhibition of the answering E/R means up to the reception of a &#34;start of search sequence&#34; information coming from the interrogating E/R means in the case when the information received in c) by the interrogating E/R means is different from the information stored at the corresponding address in the memory of the answering E/R means or, in the opposite case, return to stage c), and 
     g) definitive inhibition of the answering E/R means when the final element of the digitized code has been correctly transmitted or reactivation of said answering E/R means and return to stage b) in the opposite case. 
     The start of sequence information of stage e) can be received by the answering means as a result of a transmission fault. In addition, the number of elements of the code is N, said elements carrying the addresses from 0 to N-1. 
     In a preferred embodiment, the digitized code consists of a string of bits. Moreover, the interrogating E/R means have at least three emitting antennas, each connected upstream to an emitter, said antennas functioning in pairs, and at least three receiving antennas each connected to a receiver and a demodulator downstream of which a decision member generates a reception signal of at least one antenna. 
     According to the same final embodiment, the processing means of the interrogating E/R means ensuring the control of the tasks necessary for the search of the digitized codes make it possible to perform the following supplementary stages: 
     choice of an emission configuration consisting of choosing the emitting antennas to be combined with one another during the putting into operation of the identification system, 
     change of emission configuration and resumption of the search sequence when the digitized code has not been correctly transmitted, 
     storage of the digitized code when said code has been considered as erroneous for at least three different emission configurations, 
     successive performance of all the search sequences linked with the different emission configurations in order to check the total inhibition of the answering E/R means. 
     By thus permitting the quasi-simultaneous detection of a large number of objects, the present invention consequently leads to a considerable time gain compared with the aforementioned, prior art devices. 
    
    
     Other advantages and features of the invention can be gathered from the following illustrative, but non-limitative description. As an example and for describing the invention, the case of goods provided with tags and grouped in a trolley which the customer passes under a detection gate will be used. In this example, the system according to the invention makes it possible to quasi-instantaneously determine and bill the goods collected in bulk within the said trolley. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The description refers to the following drawings, wherein: 
     FIG. 1 diagrammatically shows the electronic circuit of the gate according to the invention. 
     FIG. 2 shows the same circuit according to a preferred embodiment of the invention. 
     FIG. 3 diagrammatically shows the electronic circuit of a tag. 
     FIG. 4 shows the stages of the control of the tasks necessary for the search of the digitized codes. 
     FIG. 5 shows the stages performed by the checking and sequencing circuit of the tag according to the invention. 
     FIGS. 6A, 6B and 6C are a table showing examples of gate/tag dialog. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows the electronic circuit of the gate, which is constituted by an emission system 2, an emitting/receiving antenna 4 and a reception system 6. Processing means such as a sequencing circuit 8 are responsible for the control of the emitted signals and the received signals. 
     In the embodiment shown in FIG. 1, the gate comprises two antennas, namely an emitting antenna 4a and a receiving antenna 4b, it being understood that the said gate can have one or more antennas able to ensure both emission and reception. 
     When a trolley carrying objects with tags arrives below the monitoring gate, the sequencing circuit 8 gives the order to modulate, by a modulator 2a, and then transmit, by an emitter 2b and the antenna 4a, an interrogation signal to the tags. This interrogation signal is advantageously constituted by two successively emitted bits, which phase or frequency modulate the signal continuously emitted by the emitter 2b to the gate antenna 4a. This signal can therefore assume four states having the following meanings: start of search sequence, 
     type 1 information signifying that at least one still active tag had a code bit at 1 at the sought address during the preceding interrogation, 
     type 0 information signifying that no still active tag had a code bit at 1 at the sought address during the preceding interrogation, 
     start of search sequence, the previously received code not corresponding to a valid code. 
     The tags answer or respond by supplying an answer signal, which is intercepted by the antenna 4b and a receiver 6a and then demodulated by the demodulator 6b in order to be interpreted by the sequencing circuit 8. 
     Thus, the gate can determine the values of the different bits or elements of the codes of the objects in the trolley. When a complete code has been found, the corresponding tag is inhibited and the sequencing circuit 8 orders the recording of the code found in a memory 10. The memory is the link between the electronic circuit of the gate and a not shown data processing system which permits, in the chosen application, the finding of the wording and the price of each article by means of its digitized code and then produces the bill therefrom. The processing means 8 and memory 10 are advantageously constituted by a microprocessor. 
     FIG. 2 shows the same electronic circuit according to a different embodiment. Thus, this embodiment has the advantage, compared with that of FIG. 1, of limiting the risk of poor coupling between the gate and the tags. For this purpose use is made of three emitting antennas 4Aa, 4Ba and 4Ca and three receiving antennas 4Ab, 4Bb and 4Cb orthogonal to one another. 
     The three receiving antennas 4Ab, 4Bb and 4Cb are connected to three receivers 6aA, 6aB and 6aC and three demodulators 6bA, 6bB, 6bC, downstream of which there is a decision member 6c generating the detection signal of the emission of one or more antennas 4Ab, 4Bb, 4Cb. Thus, the decision member generates a detection signal when at least one of the three demodulators has detected an emission signal. 
     The three emitting antennas 4Aa, 4Ba and 4Ca are connected to three emitters 2bA, 2bB and 2bC and operate in emission configurations of two antennas. The two operating antennas are energized by two signals in quadrature coming from the emitters. An emission configuration is chosen and retained for as long as informations are correctly transmitted. As soon as the transfer takes place incorrectly, another emission configuration is chosen. The components of FIG. 2, identical to their homologs of FIG. 1, operate in the same way and are not described again. 
     FIG. 3 diagrammatically shows the electronic circuit of a tag. It more particularly comprises a receiving/emitting antenna 18 and a microcircuit having a decoder system 12 for the reception of signals from the gate, a system 14 for emitting response or answer signals, a system 16 for recovering the energy from the gate, a checking and sequencing circuit 20, storage means 22,24 and inhibiting means 26. Advantageously, the system 16 is a rectifier bridge associated with a storage capacitor. In addition, this recovery system 16 is connected to the different elements of the answering means. The storage means incorporate an address counter 22 and a memory 24 and the inhibiting means are formed from flip-flops 26a,26b. The address counter 22 is connected to the sequencing circuit 20 by a clock input CK and a zeroing input RESET. 
     In the embodiment shown in FIG. 3, the tag comprises two antennas, namely an emitting antenna 18a and a receiving antenna 18b. These antennas can either be directly produced on the microcircuit, or can be deposited on the printed circuit on which the microcircuit is placed. 
     The checking and sequencing circuit 20 makes it possible to control the information received and the information to be transmitted. This circuit 20 also increments the address counter 22 and ensures the operation of the inhibiting flip-flops 26. The code memory 24 containing the digitized tag code is connected at its input to the address counter 22 and at its output to the checking and sequencing circuit 20. 
     An interrogation signal transmitted by the gate is received by the receiving antenna 18b, decoded by the decoder 12 and the thus decoded information is transmitted to the checking and sequencing circuit 20, which controls and checks the information received. The sequencing circuit 20 decides on the answer to be transmitted, the incrementation of the address counter 22 and the passage of the tag into the inhibited mode. The answer to be emitted is then transmitted to the emitter 14, which delivers the answer signal to the gate. In parallel, the energy recuperating means 16 transforms the energy received from the gate into a supply voltage for the tag electronic circuit. 
     FIG. 4 shows the control stages with regards to the tasks necessary for the search for the digitized codes, such as are used by the gate. 
     A first stage 100 consists of starting the search sequence. This search sequence for a code starts at 102 when the presence of a trolley is detected beneath the gate. This sequence can start automatically or by mechanical actuation. A &#34;start of search sequence&#34; signal 104 corresponding to the interrogation of the first code element is then supplied to the tags. At 106 the system awaits the answer from said tags. 
     A second, choice stage 200 is then initiated as a function of the answer received. The choice 202 takes place in the following way. If the answer received is positive, a 1 is stored 204 in the gate memory 10 and then a type 1 information 206 is transmitted to the tags. If the answer received is negative, a 0 is stored 208 in the memory 10 and a type 0 information 210 is transmitted. 
     A third stage 300 consists of checking 302 if the received code is complete. If the code is complete and valid 304, then said code is stored at 310 in the gate memory 10. If it is complete and erroneous, said code is rejected 306 and a &#34;start of sequence-erroneous code&#34; message 308 is transmitted as the answer at 106. When the received code is incomplete, the search sequence continues at 106. 
     A fourth stage 400 consists of the reception of the code following its storage. The code is checked 402. Then the code is zero, the search sequence ends in 404. When it is not zero, the search sequence continues with the transmission of a new &#34;start of search sequence&#34; signal at 104. 
     In the embodiment according to FIG. 2, a few supplementary stages are necessary. An antenna emission configuration is adopted during the first stage 100 and retained whilst the transfer of the codes takes place correctly. As soon as this transfer is no longer correct, the configuration is modified. However, if the same erroneous code is transferred with the three different emission configurations, the corresponding tag is assumed to be incorrectly programmed and the received code is assumed to be valid and the tag is then inhibited. 
     This embodiment of the invention permits a supplementary check of the end of the search sequence, namely the performance of three complete search sequences according to the three emission configurations in order to check whether all the tags have been inhibited. 
     FIG. 5 shows the different stages performed by the checking and sequencing circuit 20 on each tag. 
     A first stage 500 consists of starting 502 the search sequence on energizing the tag and the reception 504a of the &#34;start of search sequence&#34; signal and the zeroing of the address counter in 504b. A second stage 600 consists of choosing 602 the bit of information of the code at address Ad to be emitted 604 in response to the interrogation 602 from the gate. 
     A third stage 700 consists of checking 704 which bit of the code is being processed. The address counter Ad is incremented 702, Ad=Ad+1. At the end of the processing in 704 of the last bit of the code, if the processed code has been validated by the gate, the tag receives 708 from the gate a start of sequence information with passage 710 into the definitive inhibiting mode of the processed tag, in order to permit the interrogation of the other tags. If the processed code is not validated by the gate, the tag receives 712 from the gate a start of sequence information with erroneous acquisition, which brings about a return to stage 504b. 
     When the processed bit is not the final bit of the code, the tag receives a type 1 information 718 emitted by the gate if the latter has detected an answer 604 of at least one tag during the interrogation of the address (Ad-1), or a type 0 information 716 emitted by the gate, if the latter has detected no answer during the interrogation of the address (Ad-1). If the information received here is neither of type 1, nor of type 0, but a start of sequence information 714 as a result of a transmission fault, there is a return to stage 504b in order to reinitialize the interrogation. 
     If the code bit at the previously processed address (Ad-1) does not contain the information of the received type 720, 722, the tag is temporarily inhibited 724 up to the reception of a start of sequence information 504a. In the opposite coarse, there is a return to stage 600, where the tag transmits an answer in the form of a signal when the code bit at the processed address Ad contains a 1 does not transmit a signal in the opposite case. 
     On the attached table, FIGS. 6A, 6B and 6C, is shown the gate/tag dialog in an example of three tags E1, E2 and E3 with a respective code having five elements 01100, 01010 and 00111, the first bit, e.g. being the left-hand bit. The gate electronic circuit modulator 2a generates two wave shapes. The combination of these two wave shapes makes it possible to define four information types. In the considered example, the informations 00, 01, 10, and 11 respectively signify, as stated hereinbefore, &#34;start of search sequence&#34;, &#34;type 0 information&#34; indicating that the bit processed during the preceding interrogation is not equal to 1 for any active tag, &#34;type 0 information&#34; indicating that the bit processed during the preceding interrogation is not equal to 1 for any active tag, &#34;type 1 information&#34; indicating that at least one tag processed during the preceding interrogation has its bit at 1, and &#34;start of search sequence with erroneous preceding code&#34;. 
     The gate emits a given information signal in the first column of the attached table. The tags reply to this signal by a binary answer meaning yes or no, i.e. the tags transmit a signal for yes or transmit no signal for no. The interpretation of each gate/tag exchange is given in the final column of the table. 
     In a more practical manner and with a view to detecting the presence of transmission errors and possibly for correcting these errors, it is possible to add correction bits to the bits defining the tag code. 
     The tags associated with such a gate can be of different types, i.e. can have different electronics for &#34;conversing&#34; with the gate. For example, said tags can have an E/R device able on the one hand to respond, on a frequency F/k (k being a prime number) to the signals transmitted by the gate on a frequency F, and on the other hand, can be inhibited when its code has been found by the gate in order to permit the search for other codes. 
     Apart from the advantages described hereinbefore, in the special case of an application to the sale of goods in a large area, the invention enables customers to record the chosen articles. Therefore the invention avoids waiting in long lines at the checkouts, where the cashier has to identify each article individually. Clearly this application has only been given in an illustrative manner. The invention is applicable to numerous other fields for the identification of a person or an object.