All-N-logic high-speed single-phase dynamic CMOS logic
FIELD OF THE INVENTION 
     This invention relates in general to high speed CMOS dynamic circuits, and more particularly to VLSI circuits implemented using an all-N-logic (ANL) high-speed single-phase dynamic CMOS logic. 
     BACKGROUND OF THE INVENTION 
     CMOS dynamic circuits are widely used in VLSI design when high speed operation is required. However, CMOS dynamic circuits suffer from problems relating to race, clock skew and slew rate, charge redistribution, and DC power consumption. One type of CMOS logic, referred to herein as &#34;Domino&#34;, is disclosed in R. H. Karambeck, C. M. Lee, H-S. Law, &#34;High-speed Compact Circuits with CMOS,&#34; IEEE I. Solid-State Circuits, Vol. 17, pp. 614-619, June 1982. The Domino CMOS logic suffers from a significant disadvantage in that it is non-inverting. 
     Another prior art CMOS logic is disclosed in N. F. Goncalves and H. J. De Man, &#34;NORA: A Race-free Dynamic CMOS Technology for Pipelined Logic Structures&#34; IEEE J. Solid-State Circuits, Vol-18, pp.261-266, June 1983. Both NORA and Domino CMOS logic suffer from charge redistribution problems. 
     Further prior art CMOS logic designs are described in J. Yuan and C. Svensson, &#34;High-speed CMOS Circuit Technique&#34;, IEEE J. Solid-State Circuits, Vol-24, pp. 62-70, February 1989 and C. M. Lee, and E. W. Szeto, &#34;Zipper CMOS&#34;, IEEE Circuits Devices Mag., pp 10-16, May 1986. Each of the NORA, single phase design of Yaun et al and the Zipper CMOS methodology require the use of low-speed P-Logic blocks. Furthermore, the Zipper CMOS consumes DC power and requires a proprietary Zipper driver. 
     Yet another prior art CMOS logic is disclosed in C. Y. Wu. K. H. Cheng and J. S. Wang, &#34;Analysis and Design of a New Race-free Four-phase CMOS Logic&#34;, IEEE J. Solid-State Circuits, Vol. 28, pp. 18-25, January 1993. This four-phase dynamic logic also consumes DC power and requires a complicated clock distribution system. 
     SUMMARY OF THE INVENTION 
     According to the present invention, a new high speed all-N-logic single-phase dynamic CMOS logic (ANL CMOS) is provided. One embodiment of applicants&#39; invention is disclosed in R. X Gu and M. I. Elmasry, &#34;An All-N-Logic High-Speed Single-Phase Dynamic CMOS Logic&#34;, Proc. ISCAS, Vol. 4, pp7-10, London, England, May 1994. As will be discussed in greater detail below, the ANL CMOS design of the present invention overcomes the problems of prior art CMOS logic by eliminating the need for low-speed P-Logic blocks. The use of all-N-logic results in speed improvements in the order of 2 to 3 times the speed of conventional CMOS dynamic circuits. 
     According to a first embodiment of the present invention, a 2:1 frequency divider is provided, using the ANL CMOS logic of the present invention, implemented in 0.8 μm CMOS technology and operating with a clock frequency as high as 1.5 GHz. According to a second embodiment, a pipelined 8-bit carry generator is provided utilizing five-stacked NMOS gates for the N-logic portion, which operates at a clock rate of over 710 MHz. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A detailed description of various embodiments of the invention, and a comparison with prior art CMOS dynamic circuits, is provided herein below with reference to the following drawings, in which: 
     FIG. 1, which comprises parts a, b and c, is a circuit schematic diagram and clock signal diagram of a prior art single-phase CMOS dynamic circuit; 
     FIG. 2 is a schematic block diagram of a pipeline system according to prior art CMOS designs; 
     FIG. 3, which comprises parts a, b and c, shows a circuit schematic and clock signal diagram for the all-N-logic (ANL1) single-phase CMOS dynamic circuit according to a first embodiment of the present invention; 
     FIG. 4 is a graph comparing the output voltage levels for the prior art CMOS dynamic circuit of FIG. 1 and the ANL1 CMOS dynamic circuit of FIG. 3 at a clock slew rate of 5 V/3 ns when all inputs are &#34;1&#34;; 
     FIG. 5 is a graph comparing node voltage levels for the prior art circuit of FIG. 1 and the circuit of FIG. 3 when all inputs are &#34;1&#34;; 
     FIG. 6, which comprises parts a, b and c, forms a circuit schematic diagram and clock signal diagram for a second embodiment of the all-N-logic (ANL2) single phase CMOS dynamic circuit according to the present invention; 
     FIGS. 7a and 7b are circuit schematic diagrams of revised N2-blocks of the ANL1 and ANL2 embodiments of the present invention; 
     FIG. 8 shows a pipeline system for the all-N-logic single-phase CMOS circuit according to the present invention; 
     FIG. 9 is a schematic diagram of a pipeline of all-N-logic single-phase CMOS dynamic circuits according to the present invention; 
     FIG. 10 is a schematic representation of the trapezoidal scaling of MOS devices for the P- and N2-blocks of the dynamic circuit according to the present invention; 
     FIG. 11 is a graph showing the rise and fall time delay of the prior art circuit of FIG. 1 for different numbers of stacked MOS devices; 
     FIG. 12 is a graph showing the rise and fall time delay for the circuit of FIG. 3 for different numbers of stacked MOS devices; 
     FIG. 13 compares the maximum operating frequency versus number of stacked MOS devices for the prior art using N- and P- blocks and the system of the present invention using all N- blocks; 
     FIG. 14 is a graph showing the maximum operating frequency versus number of stacked MOS devices for the ANL2 embodiment of the present invention; 
     FIG. 15 is a graph showing delay versus supply voltage with four stacked MOS transistors and a fanout of 1, for the N1 and N2 blocks for the ANL1 and ANL2 embodiments of the present invention; 
     FIG. 16 is a circuit schematic diagram of a 2:1 frequency divider implemented using N1 and N2-blocks according to a first successful prototype implemented in accordance with the present invention; 
     FIG. 17 is a graph showing output voltage levels for the 2:1 frequency divider of FIG. 16 at a clock frequency of 1.5 GHz; 
     FIG. 18 is a circuit schematic diagram of an 8-bit carry generator implemented using the N1- and N2-blocks according to the present invention; 
     FIG. 19 is a graph showing output voltage levels for the 8-bit carry generator of FIG. 18 at a clock frequency of 714 MHz; and 
     FIG. 20 is a graph showing output voltage levels of the 8-bit carry generator of FIG. 18 with optimized and non-optimized conditions. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT AND OF THE PRIOR ART 
     The prior art NORA dynamic CMOS technique discussed above uses a true two-phase clock signal instead of a four-phase clock signal in order to overcome the race problem caused by clock skew. According to the prior art NORA pipeline system, N- and P-C e  MOS latches are alternately used. 
     However, the successful application of CMOS dynamic circuits requires the use of a minimum number of clock signals. For example, FIG. 1 shows the CMOS dynamic circuit of Yuan et al which uses a single-phase clock signal (CL) which is not inverted. Since only a single-phase clock signal is utilized, no clock skew exists and a higher clock frequency can be used than with prior art two-phase and four-phase clock signal designs. Thus, single-phase CMOS circuits can complement static CMOS, and in most cases, can replace NORA logic, since the single-phase CMOS circuits are faster than NORA circuits. 
     As shown in FIG. 2, both NORA circuits and the prior art single-phase CMOS circuits of FIG. 1 are used to implement a pipelined structure, by successively alternating N-logic and P-logic blocks. The use of low-speed P-logic blocks in these prior art designs limits the applied clock frequency (i.e. due to the slow precharging and discharging time of the P-logic blocks). Thus, the advantage of using the fast N-logic blocks is not fully utilized in these prior art designs. 
     Turning now to FIG. 3, a pair of all-N-logic (ANL1) circuits are shown for use in a pipeline system. The N1-block (FIG. 3a) is a revised version of the N-block of FIG. 1a. The logic operation of the N1-block circuit in FIG. 3 is non-inverting. The operating principles of the N1-block are as follows: When &#34;CL&#34; is &#34;0&#34;, PMOS transistor P1 is ON, node &#34;a&#34; is &#34;HIGH&#34;, and PMOS transistor P2 is shut OFF. Because NMOS transistor N3 is OFF, the output node &#34;OUT&#34; holds its previous state. When &#34;CL&#34; is &#34;1&#34;, NMOS transistors N1 and N3 are ON, and node &#34;b&#34; is discharged to ground. If the &#34;N-logic&#34; block is &#34;1&#34;, node &#34;a&#34; is also discharged to ground and node &#34;OUT&#34; is &#34;1&#34;. If the &#34;N-logic&#34; block is &#34;0&#34;, node &#34;a&#34; remains &#34;HIGH&#34; and causes the signal at node &#34;OUT&#34; to fall to ground. 
     For the purpose of this disclosure the terms &#34;N-logic&#34; and &#34;P-Logic&#34; denote conventional logic functions (e.g. AND, OR, NAND, NOR, NOT), implemented using NMOS and PMOS transistors, respectively, In FIGS. 1, 3, 6 and 7, the logic functions provided by the &#34;N-logic&#34; and &#34;P-logic&#34; blocks are not specified, but may be any of the above-mentioned conventional functions. 
     The prior art circuit in FIG. 1a suffers from charge redistribution problems in the evaluating/holding blocks if the clock transition is not very short. More particularly, when &#34;CL&#34; is &#34;1&#34; and &#34;N-logic&#34; is &#34;1&#34;, node &#34;a&#34; is discharged to &#34;0&#34; and node &#34;OUT&#34; rises to &#34;HIGH&#34;. In this case, NMOS transistor N3 of FIG. 1a is turned ON, first strongly, then weakly, so that node &#34;c&#34; takes a long time to reach a voltage of &#34;V DD  -V th  &#34;. For a high clock frequency, node &#34;c&#34; can only reach approximately 2.5 V. Thus, it is clear that the signals at the node &#34;OUT&#34; and the node &#34;c&#34; are at different voltage levels when the evaluating period ends. When &#34;CL&#34; switches from &#34;1&#34; to &#34;0&#34; and the clock slew rate is longer than 5 V/2.5 ns, NMOS transistor N3 of FIG. 1a does not totally shut OFF, and the voltage at node &#34;OUT&#34; goes low, due to charge redistribution, and thus the noise margin and speed are reduced. 
     This disadvantage is overcome in the present invention by adding one PMOS transistor P3 as shown in FIG. 3a. When &#34;CL&#34; is &#34;1&#34;, and &#34;N-logic&#34; is &#34;1&#34;, node &#34;a&#34; is &#34;LOW&#34; and node &#34;OUT&#34; is &#34;HIGH&#34;, PMOS transistor P3 is ON which causes node &#34;c&#34; to charge to &#34;V DD  &#34;. Hence the signals at node &#34;OUT&#34; and at node &#34;c&#34; are at the same voltage level. Thus, when the clock signal switches, no charge redistribution occurs. Testing has shown that the circuit of the present invention operates correctly at any clock skew rate. 
     FIG. 4 shows a comparison of the output nodes of the two circuits of FIGS. 1a and 3a at a clock slew rate of 1.67 V/ns. It is clear from FIG. 4 that the prior art Yuan circuit does not hold the output level at 5 V whereas the N1-block of FIG. 3a is capable of sustaining the output level at 5 V. Another advantage of using PMOS transistor P3 is that it speeds up the charging process as shown in FIG. 4. 
     In a pipeline system, the N-block and P-block are alternately used due to their complementary evaluating and holding periods, thereby resulting in race free operation. In order to achieve high operating frequency, the number of PMOS transistors are minimized in the low speed P-logic devices, and in most cases, the p-logic blocks are used only as a latch. Thus, most logic operations are carried out in the N-block and a half clock cycle is wasted, such that a longer pipeline is needed, resulting in slower operating speed. 
     For the N-logic block of FIG. 3, the logic output is normally from node &#34;a&#34; since node &#34;a&#34; is a full-swing node, whereas node &#34;b&#34; is only a half-swing node. However, by converting node &#34;b&#34; to a full-swing node, all N-logic operations can be accomplished. Based on the above considerations, an N2-block is provided as shown in FIG. 3b, which is the complementary circuit of the N1-block of FIG. 3a. The operating principle of the N2-block is as follows: When &#34;CL&#34; is &#34;1&#34;, NMOS transistor N1 is ON, node &#34;b&#34; is &#34;LOW&#34;, and NMOS transistor N2 is OFF. Because the PMOS transistor P4 is OFF, the output node &#34;OUT&#34; holds its previous state. When &#34;CL&#34; is &#34;0&#34;, PMOS transistors P1 and P4 are ON, and node &#34;a&#34; is &#34;HIGH&#34;. If the &#34;N-logic&#34; block is &#34;1&#34;, node &#34;b&#34; is charged to &#34;HIGH&#34; and node &#34;OUT&#34; is discharged to ground. &#34;N-logic&#34; is &#34;0&#34; , node &#34;b&#34; remains &#34;LOW&#34; and causes node &#34;OUT&#34; to charge to &#34;HIGH&#34;. However, when the N-logic block is &#34;1&#34; and &#34;CL&#34; is &#34;0&#34;, node &#34;b&#34; quickly goes to 2 V and slowly goes from 2 V to &#34;V DD  -V th  &#34;, which is equal to 3.5 V if the body effect is active. For high speed operation, the voltage on node &#34;b&#34; can go only rise to about 2.5 V. Hence, it is difficult to extract logic signals from node &#34;b&#34; by a CMOS inverter (see FIG. 5). Therefore, according to the present invention, a positive feedback PMOS transistor P4 is provided to make the voltage on node &#34;b&#34; quickly rise to V DD , if necessary. Thus, a half-logic swing becomes a logic swing at node &#34;b&#34;. FIG. 5 shows that a full logic swing is obtained using PMOS transistor P4. The ratio of the inverter comprising transistors P2 and N2 should preferably be designed so that W P2  /W N2  &lt;1.5 so that the inverter switches when the voltage on node &#34;b&#34; passes through 2 V. 
     The purpose of using NMOS transistor N3 is to avoid charge redistribution. It is an essential feature of the present invention that all-N-logic be used in the pipeline embodiment of the present system. If the output node of the N2-block can not stay at 0 V in the holding period, the noise margin is reduced, and a fault logic can possibly occur. By using NMOS transistor N3 in the circuit as shown in FIG. 3b, if &#34;CL&#34; is &#34;0&#34;, &#34;N-logic&#34; is &#34;1&#34;, node &#34;b&#34; is &#34;HIGH&#34; and node &#34;OUT&#34; is &#34;LOW&#34;, NMOS transistor N3 is open and causes node &#34;c&#34; to discharge to ground. Therefore, node &#34;OUT&#34; and node &#34;c&#34; are at the same voltage level. Thus, when the clock signal switches, the output node stays at 0 V during the holding period. The speed of this circuit is also improved by adding another discharging path; that of NMOS transistor N3. The logic operation of the N2-block circuit in FIG. 3b is inverting. 
     Another high speed version of the all-N-logic 2 (ANL2) circuitry of the present invention is shown in FIG. 6. This version of logic is faster than the ANL1 embodiment under operating conditions of sharper clock slew rate. In this embodiment, the output is charged or discharged by two PMOS or two NMOS transistors rather than three PMOS or three NMOS transistors. However, the clock slew rate must be higher than 1.6 V/ns. This means that the clock rise and fall time is 3 ns, in which case the clock hold time is at least equal to 5 ns. Thus, the circuits of FIGS. 6a and 6b can operate at a clock frequency of as low as 60 MHZ. From testing, it has been confirmed that the N1-block of the ANL2 embodiment of FIG. 6a has almost the same clock slew rate tolerance as the prior art N-block of FIG. 1a. However, the operating speed of the N1-block of the ANL2 embodiment is higher than the N-block of FIG. 1a. If the clock slew rate is high, NMOS transistors N3 of the N2-blocks of the ANL1 and ANL2 embodiments can be eliminated, as shown in FIG. 7. 
     The pipeline system using the all-N-logic blocks of the present invention is shown in FIG. 8. The non-inverting N1-block and the inverting N2-block are connected in series, in alternating fashion. 
     A circuit example of a pipeline constructed using the N1-blocks and N2-blocks of the present invention is shown in FIG. 9. When &#34;CL&#34; is &#34;0&#34;, node &#34;a&#34; of the non-inverting N1-block is charged to high, thus the N1-block is in the holding period and the inverting N2-block is in the evaluating period. When &#34;CL&#34; is &#34;1&#34;, node &#34;b&#34; of the inverting N2-block is discharged and the N1-block is in the holding period, while the output is latched and stable, and the non-inverting N1-block is in the evaluating period. The alternative evaluating and holding periods ensure that the system operates race-free. 
     Static CMOS gates can be inserted between the N1-block and N2-block in the pipeline system of the present invention, provided the clock delay is less than the gate delay. As shown in FIG. 9, a CMOS inverter is used between the N1 and N2 blocks. Since the delay of the inverter is very small (i.e. negligible) the pipeline system of FIG. 9 can be implemented with all of the required logic operations with no seriously increased delay. 
     EXPERIMENTAL RESULTS 
     Circuit simulation of the circuits according to the present invention was carried out using an HSPICE simulator with a 0.8 μm CMOS technology parameter. The technology parameters are shown in Table 1, as follows: 
     
                       TABLE 1                                                     
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NMOS                  PMOS                                                
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Vtn        0.78 V         Vtp      -0.88 V                                
Gate Oxide 175Å       Gate Oxide                                      
                                   175Å                               
Thickness                 Thickness                                       
Uo         502 cm.sup.2   Uo       165 cm.sup.2                           
           V.sup.-1 sec.sup.-1     V.sup.-1 sec.sup.-1                    
Cgso       273P F/m       Cgso     215P F/m                               
Cgdo       273P F/m       Cgdo     215P F/m                               
Cj         25w F/m        Cj       450U F/m                               
Cjsw       205P F/m       Cjsw     212P F/m                               
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     The trapezoidal scaling method was used for the MOS transistors using well known techniques (M. Shoji, &#34;CMOS Digital Circuit Technology&#34;, Prentice Hall, 1988). 
     The circuit simulation showed that there is no significant improvements for circuits evaluating at node &#34;a&#34;, and that there is a 10% improvement for circuits evaluating at node &#34;b&#34; (see FIG. 10). Therefore, equal width for MOS transistors in logic blocks for circuits evaluating at node &#34;a&#34; and unequal width as shown in FIG. 10 for circuits evaluating at node &#34;b&#34; are used in the circuit simulation discussed herein below. The circuits can also operate in a ratioless case. 
     A minimum size CMOS inverter is used at the output of the block circuits during testing. The worst case rise time at the output node for the circuits evaluating at node &#34;a&#34; is defined so that all of the intermediate nodes are charges to &#34;HIGH&#34; before they are discharged. Time delay t r  is determined as the worst case rise time of the output node as it rises from 0 to 4.5 V. The worst case fall time at the output node for the circuits evaluating node &#34;b&#34; is defined so that all the intermediate nodes are discharged to &#34;LOW&#34; before they are charged. The delay t f  is determined as the worst case fall time of the output node as it falls from 5 V to 0.5 V. HSPICE simulation results of the time delay versus number of stacked MOS transistors for the circuits of FIGS. 1 and 3 are shown in FIGS. 11 and 12, respectively. In FIGS. 11 and 12, the W/L ratios of transistors P2, P3 and N2 of the latched stages are set at ##EQU1## respectively. The purpose of PMOS transistor P3 of the N1-block and NMOS transistor N3 of the N2-block is to solve the charge sharing problem at node &#34;c&#34;. Transistors P3 and N3, with a minimum size, can not charge or discharge node &#34;c&#34; efficiently. The W/L ratios of transistors P3 and N3 are chosen to be ##EQU2## For the same reason, the W/L ratios of transistor P4 of the N2-block are optimized as ##EQU3## for charging node &#34;b&#34; quickly. 
     FIGS. 11 and 12 show that the rise times of the P-block of FIG. 1b and the N2-block of the ANL1 embodiments are constants. The P-logic of the P-block and N-logic of the N2-block are open circuits during the evaluating period (&#34;CL&#34; is &#34;0&#34;). Thus, node &#34;b&#34; remains &#34;0&#34;, and the rise time is only determined by charging PMOS transistors P2 and P4. The number of stacked MOS transistors in the P- and N2-blocks does not affect the rise time delay. This is also the reason why the fall times of the N-block of FIG. 1a and the N1-block of the embodiment ANL1 are constants. 
     It is obvious that the slow P-block reduces the speed of the pipeline system by a factor of 2 to 3. The operating speeds of the N1- and N2-blocks are similar. Thus, the pipeline system for FIG. 9 alternatively using the N1- and N2-blocks operates race-free at a high clock rate without the requirement of a complementary P-block. 
     The maximum operating frequency of the pipeline systems shown in FIGS. 2 and 8 is defined as ##EQU4## FIG. 13 shows the maximum operating frequency of the two pipeline systems of FIGS. 2 and 8 versus the number of stacked MOS transistors based on FIGS. 11 and 12. The worst case operating speed of the N1- and N2- blocks are also similar. For the prior art NORA and Yuan circuits, the worst case operating speed is determined by the slow precharge and discharge of the P-logic. The advantage of using all-N-logic becomes increasingly significant when the number of stacked NMOS transistors exceeds two. Since the speed of the ANL1 and ANL2 circuits is 2-3 times faster than prior art circuits, the pipelined all-N-logic is 2-3 times faster than the pipelined N- and P-blocks, as verified by the HSPICE simulation results. The operating speed of the proposed pipelined circuits of the ANL1 blocks can reach 1.5 GHz. 
     As shown in FIGS. 12 and 13, the rise time delay of the N2-block is long because the output is charged through three PMOS transistors P1, P2 and P3. This limits the maximum operating frequency when the number of stacked NMOS transistors is equal to or less than two. By way of contrast, the ANL2 embodiment minimizes the rise delay, since the output of the N2-block of ANL2 (FIG. 6) is charged through only two series PMOS transistors P2 and P3. The circuit blocks can be further optimized by sizing the MOS transistors for different numbers of stacked MOS transistors. The optimization for the latch part of the circuit blocks is given as follows: 
     (a) Small load (fanout equal to or less than three inverters). 
     In this case, the driving capability is not a concern. For all the N1-blocks, the fall time is very small. Thus, the minimum size is chosen for NMOS transistors N2 and N3 and a large size is chosen for PMOS transistor P2. For the N2-block, with a small number of stacked NMOS transistors, the rise time delay is dominant. A large size for PMOS transistors P2 and P3 is used in order to quickly charge the output to &#34;1&#34;. With a large number of stacked NMOS transistors, the fall time delay is dominant due to the slow charging at node &#34;b&#34;. In order to reduce the fall time delay, a small size is chosen for PMOS transistors P2 and P3 in order to lower the switch point of the output-input transfer function of the inverter which is composed of transistors P2, P3, and N2. Thus, the minimum voltage at node &#34;b&#34; to pull the output voltage down is lower. Furthermore, this also reduces the parasitic capacitance at node &#34;b&#34;. The optimized circuit parameters are as shown in Tables 2 and 3 for a fanout equal to one inverter. The rise and fall time delays are found to be similar for the N1- and N2-blocks. 
     
                       TABLE 2                                                     
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Optimized circuit parameters of the N1-block, F.sub.out = 1               
No. of stacked MOS&#39;s                                                      
             1       2       4     6     8                                
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W.sub.P2 (μm)                                                          
             10      10      10    10    10                               
W.sub.N2,N3 (μm)                                                       
             2.4     2.4     2.4   2.4   2.4                              
t.sub.r (ns) 0.31    0.42    0.64  0.91  1.17                             
t.sub.f (ns) 0.28    0.28    0.28  0.28  0.28                             
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                       TABLE 3                                                     
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Optimized circuit parameters of the N2-block, F.sub.out = 1               
No. of stacked MOS&#39;s                                                      
             1       2       4     6     8                                
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W.sub.P2,P3 (μm)                                                       
             10      8       6     4     3                                
W.sub.N2 (μm)                                                          
             8       10      12    12    12                               
t.sub.r (ns) 0.33    0.39    0.45  0.60  0.86                             
t.sub.f (ns) 0.335   0.42    0.62  0.86  1.03                             
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     (b) Large load (fanout equal to or greater than four inverters). 
     In this case, not only does the delay of the circuit blocks have to be minimized, but the driving capability must be considered. For the N1-block, small sized NMOS transistors N2 and P3 should be increased with the increase in the number of stacked MOS transistors. For the N2-block, with a large number of stacked NMOS transistors, if the fanout is equal to four inverters, the minimum size of W P2 ,P3 should be 5 μm. The maximum operating frequency of the ANL2 embodiment, with different loads, is shown in FIG. 14. With fanout equal to 1, the maximum operating frequency can reach as high as 1.5 GHz for the pipelined system with the ANL2 blocks. 
     Dynamic circuits enhance the operating speed of digital systems due to their small parasitic capacitances. However, one main drawback of dynamic circuits is that they consume high power due to their high clock frequencies. The dynamic power of a circuit is given by: 
     
         Pd=C.sub.L V.sup.2.sub.dd f.sub.op                         (2) 
    
     where C L  is the load capacitance and f op  is the operating frequency. The dynamic power is proportional to the square of the supply voltage V. Low supply voltage and low power are considered advantageous in modern VLSI technology. For dynamic circuits, if the power supply is scaled down, the dynamic power consumption can be greatly reduced. HSPICE simulations show that the proposed all-N-logic dynamic circuits of the present invention can operate well when the supply voltage is as low as 2.5 V. The relationship of delay versus supply voltage is shown in FIG. 15. Basically, the time delays of the ANL1 and ANL2 circuits increase by 70% when the supply voltage drops from 5 V to 3.3 V. At the same time, the dynamic power of the 5 V supply is four times higher than a 3.3 V supply considering the factor of lower operating frequency. The operating speed of all-N-logic dynamic systems at 3.3 V supply is 30% faster than the conventional latched dynamic systems at a 5 V supply. However, the power consumption of the ANL circuits is only half that of the conventional circuits. 
     EXEMPLARY EMBODIMENTS 
     Two circuits using the ANL2 embodiment have been designed and simulated using HSPICE. The first is a 2:1 frequency divider formed by the N1- and N2-blocks with one NMOS transistor in each N-logic block as shown in FIG. 16, wherein the clock signal is a step pulse. The output voltage signal shown in FIG. 17 indicates that the circuit can operate at a clock frequency of 1.5 GHz. 
     The second exemplary embodiment is in the form of an 8-bit carry generator, implemented by the pipelined N1- and N2-blocks, as shown in FIG. 18. This circuit uses five stacked NMOS transistors. The longest delay occurs when the input signal is applied to P3 and all other P i  =1,G i  =0(i=1,2, . . . ,7) and c0=1. The clock signal is constructed as follows: 0.1 ns rise and fall time and 0.6 ns for the holding time. Optimized conditions which are addressed in Tables 2 and 3 are used for the HSPICE simulation. The transient analysis of node waveforms (see FIG. 19) shows that the circuit can operate at a clock frequency of 714 MHz. Another advantage of using the optimized parameters of the latch stages as shown in Tables 2 and 3 is to reduce the amplitude of signal voltage dips. While the output signal of the N1-block is held at V DD  for two consecutive clock cycles, the output signal voltage experiences dips because node &#34;a&#34; drops from V DD  to V SS , during the evaluating period. From FIG. 20, it is seen that the non-optimized latch stages, with W N2 ,N3 =4 μm in the N1-block and W P2 ,P3 =8 μm in the N2-block, not only are slower bet also are characterized by larger dips. This is because the switching point of the optimized latches of the N1- and N2-blocks shifts upward toward V DD  and downward to V SS  more than do the non-optimized latches, respectively. Therefore, the latches with the optimized operating conditions switch earlier and thus, have smaller dips than non-optimized circuits. 
     In summary, the all-N-logic high speed single-phase CMOS dynamic circuits of the present invention are 2 to 3 times faster than conventional prior art circuits. The 2:1 frequency divider of FIG. 16, using the ANL2 embodiment, can operate at a clock frequency of 1.5 GHz using 0.8 μm CMOS technology. The 8-b carry generator of FIG. 18, implemented by the pipelined N1- and N2-blocks, has been simulated to operate at a clock frequency of over 710 MHz. These new circuits achieve high speed by avoiding the use of low-speed P-logic blocks. The inventive circuits are race-free and use a single-phase clock. Some common problems related to dynamic circuits, such as dc power, charge redistribution in the evaluating/holding blocks and clock skew rate, are also overcome in the proposed all-N-logic dynamic circuits of this invention. 
     Alternative embodiments and variations of the invention are possible without departing from the sphere and scope as defined by the claims appended hereto.