Delay generator for phased array ultrasound beamformer
FIELD OF THE INVENTION 
     This invention relates to ultrasound imaging systems which utilize phased array beam steering and focusing and, more particularly, to a delay generator for dynamically controlling focus in a receive beamformer. 
     BACKGROUND OF THE INVENTION 
     In a phased array ultrasound imaging system, an ultrasound transducer includes an array of N transducer elements. The system includes N parallel channels, each having a transmitter and a receiver connected to one of the transducer array elements. Each transmitter outputs an ultrasound pulse through the transducer element into an object being imaged, typically the human body. The transmitted ultrasound energy is steered and focused by applying appropriate delays to the pulses transmitted from each array element so that the transmitted energy adds constructively at a desired point. The transmitted ultrasound energy is partially reflected back to the transducer array by various structures and tissues in the body. 
     Steering and focusing of the received ultrasound energy are effected in a reverse manner. The reflected ultrasound energy from an object or structure arrives at the array elements at different times. The received signals are amplified and delayed in separate processing channels and then combined in a receive beamformer. The delay for each channel is selected such that the receive beam is steered at a desired angle and focused at a desired point. The delays may be varied dynamically so as to focus the beam at progressively increasing depths, or ranges, as the ultrasound energy is received. The transmitted beam is scanned over a region of the body, and the signals generated by the beamformer are processed to produce an image of the region. 
     In order to effect focusing and steering of the receive beam, delays must be applied to the received signals in each processing channel. The required delays vary with the steering angle of the receive beam, the position of each transducer element in the array, and with focal depth. Dynamic focusing is effected by varying the delays with time during reception of ultrasound echoes from progressively increasing depths. A typical phased array ultrasound transducer may include 128 elements or more. Thus, the computation and control of the required delay for each transducer element to effect dynamic focusing at a desired steering angle is difficult. 
     In one prior art approach, disclosed in U.S. Pat. No. 4,949,259 issued Aug. 14, 1990 to Hunt et al, the region being imaged is divided into zones at different depths from the transducer, and a delay is associated with each transducer element in each zone. This approach reduces the required number of delay coefficients compared to an ideal continuously-adjusted delay. However, since each delay is exactly correct at only one depth in the zone, the image quality is somewhat degraded. 
     U.S. Pat. No. 4,173,007, issued Oct. 30, 1979 to McKeighen et al., discloses an ultrasound imaging system using a memory with separate read and write capabilities to produce a dynamically variable delay. The delay can be varied by modifying the write or the read address pointer. 
     U.S. Pat. No. 5,111,695, issued May 12, 1992 to Engeler et al, discloses a method for dynamic phase focus of received energy for coherent imaging beam formation. The channel time delay is adjusted by apparatus with means for counting range clock signals, responsive to the initial steering angle, and a logic means for issuing fine time delay adjustment signals responsive to a phase control algorithm. Because of an approximation, the delays are not determined exactly. 
     Other prior art techniques for dynamic focusing are disclosed in U.S. Pat. No. 4,974,211 issued Nov. 27, 1990 to Corl; U.S. Pat. No. 5,113,706 issued May 19, 1992 to Pittaro; U.S. Pat. No. 4,870,971 issued Oct. 3, 1989 to Russell et al.; U.S. Pat. No. 4,707,813 issued Nov. 17, 1987 to Moeller et al.; and U.S. Pat. No. 4,227,417 issued Oct. 14, 1980 to Glenn. 
     SUMMARY OF THE INVENTION 
     According to the present invention, a delay generator for a beamformer in a phased array ultrasound imaging system is provided. The beamformer processes received signals from an array of transducer elements to form a receive beam. The beamformer includes a delay generator corresponding to each transducer element for delaying the received signal and a combiner for combining the delayed signals to form the receive beam. The delay generator comprises a delay unit for delaying the received signal, and a delay controller. The delay caused by the delay unit is variable in response to a change delay signal supplied by the delay controller at discrete times during reception of ultrasound energy to steer and dynamically focus the receive beam. Preferably, the delay controller includes means for generating the change delay signal in binary form such that an active state of the change delay signal causes the delay to change by one delay quantum. 
     According to one aspect of the invention, the change delay signal represents an exact solution, within the quantization error of the delay unit, to the equation for the delay at a given steering angle, transducer element and focal depth. The delay controller may include a plurality of registers for storing values representative of a delay curve for the selected steering angle and means for updating the registers at discrete times during reception of ultrasound energy. The change delay signal is generated each time the values in the registers meet a predetermined condition. 
     According to another aspect of the invention, the change delay signal represents a solution to the delay equation for the delay at a given transducer element to steer the receive beam to a dynamically variable steering angle and to dynamically focus the receive beam during reception of ultrasound energy. The delay controller may include a plurality of registers for storing values representative of a delay curve for steering the receive beam to the dynamically variable steering angle and for dynamically focusing the receive beam, and means for updating the registers at discrete times during reception of ultrasound energy. The change delay signal is generated each time the values in the registers meet a predetermined condition. In the preferred embodiment, the delay coefficients received by the delay controller contain information representative of a selected steering angle Θ and deviations ΔΘ from the selected steering angle. The deviations ΔΘ are specified for a predetermined number of zones in the region being imaged. The delay controller includes means for causing the receive beam to have a specified deviation ΔΘ Z  from the selected steering angle Θ in each zone Z. This process is referred to below as &#34;warping&#34;. 
     In one implementation, the delay generator is used in a digital beamformer, and the delay unit includes means for delaying digital representations of the received signals. In a second implementation, the delay generator is used in a continuous analog beamformer, and the delay unit includes means for delaying continuous analog representations of the received signals. In a third implementation, the delay generator is used in a discrete time analog beamformer, and the delay unit includes means for delaying sampled analog representations of the received signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a better understanding of the present invention, reference is made to the accompanying drawings which are incorporated herein by reference and in which: 
     FIG. 1 is a block diagram of a phased array ultrasound beamformer; 
     FIG. 2 is a simplified block diagram of the delay generator in accordance with the invention; 
     FIG. 3 is a block diagram of the delay generator for one processing channel of a digital ultrasound beamformer incorporating the present invention; 
     FIG. 4 is a block diagram of an analog ultrasound beamformer incorporating the delay generator of the present invention; 
     FIG. 5 is a block diagram of a discrete time analog ultrasound beamformer incorporating the delay generator of the present invention; 
     FIG. 6 is a graph of delay as a function of elapsed time for different transducer elements at a beam steering angle of 22.5°; 
     FIG. 7 is a graph that illustrates the geometry of a transducer array having an arbitrary shape; 
     FIG. 8 is a graph of elapsed time as a function of delay, which illustrates the optimum discrete delay values; 
     FIG. 9 is a block diagram of a first embodiment of the delay controller in accordance with the present invention; 
     FIG. 10 is a block diagram of a second embodiment of the delay controller in accordance with the present invention; and 
     FIGS. 11-1 and 11-2 show a block diagram of the hardware that is common to each group of eight channels in the delay generator with warping; 
     FIGS. 12-1 and 12-2 show a block diagram of the additional hardware that is added to the delay controller in each channel in the delay generator with warping; and 
     FIGS. 13-1 and 13-2 show is a timing diagram that illustrates the calculation of deviation ΔΘ in one zone in the delay generator with warping. 
    
    
     DETAILED DESCRIPTION 
     A simplified block diagram of an ultrasound transducer array and a phased array ultrasound beamformer is shown in FIG. 1. The phased array ultrasound transducer 10 includes transducer elements 10 1 , 10 2 , . . . 10 N . The transducer elements are typically arranged in a linear or curvilinear array. The ultrasound transducer typically includes 128 transducer elements, but any number of transducer elements can be utilized. 
     The ultrasound transducer 10 transmits ultrasound energy into an object being imaged and receives reflected ultrasound energy. The transmitter portion of the ultrasound scanner is omitted from FIG. 1 for simplicity. By appropriately delaying the pulses applied to each transducer element, a focused ultrasound beam is transmitted into the object. The transmitted beam is focused and steered by varying the delays associated with each transducer element. 
     In a medical ultrasound imaging system, reflections, or echoes, are received from various structures and organs within a region of the human body. The reflected ultrasound energy from a given point within the patient&#39;s body is received by the transducer elements at different times. Each of the transducer elements 10 1 , 10 2 , . . . 10 N  converts the received ultrasound energy to an electrical signal. The electrical signals are conditioned by signal conditioning units 20 1 , 20 2 , . . . 20 N , and the conditioned signals are input to a beamformer 12. The beamformer 12 includes a separate processing channel for each transducer element. The beamformer 12 processes the electrical signals so as to control the receive sensitivity pattern and thereby effect focusing and steering of the received ultrasound energy. The depth and direction of the focal point relative to the ultrasound transducer 10 is varied dynamically with time by appropriately delaying the received signals from each of the transducer elements. The delayed signals are combined to provide a beamformer output 14. 
     The ultrasound transducer, the transmitter and the receive beamformer are parts of a phased array ultrasound scanner which transmits and receives ultrasound energy along a plurality of scan lines. Sector scan patterns, linear scan patterns and other scan patterns known to those skilled in the art can be utilized. The output 14 of the beamformer represents the received ultrasound energy along each scan line. The beamformer output 14 is processed according to known techniques to produce an ultrasound image of the region being scanned. 
     Respective electrical signals from the transducer elements 10 1 , 10 2 , . . . 10 N  are applied to individual processing channels of the beamformer 12. The beamformer 12 includes a delay unit 22 i  and a delay controller 24 i , where i varies from 1 to N, for each processing channel, and also includes a combining unit 26. The output of transducer element 10 i  is applied to the input of signal conditioning unit 20 i , and the output of signal conditioning unit 20 i  is applied to the input of delay unit 22 i . The outputs of delay units 22 1 , 22 2 , . . . 22 N  are applied to the inputs of combining unit 26. A controller 28 supplies delay coefficients and other control information to each processing channel. 
     Each signal conditioning unit 20 i  amplifies and filters the analog signal from the associated transducer element. Typically, the signal conditioning unit 20 i  also performs time gain control (TGC), as known in the art. The signal conditioning unit 20 i  may also perform digital or analog sampling of the analog signal. The delay unit 22 i  and the delay controller 24 i  form a delay generator which dynamically varies the delay in each channel as described in detail below. The combining unit may perform a simple summing of the delayed signals, weighting and summing of the delayed signals, or a more complex combining algorithm to provide the beamformer output 14. 
     A simplified block diagram of a delay generator 30 in accordance with the invention is shown in FIG. 2. The delay generator 30 includes delay unit 22 i  for applying a required delay to the received signal and delay controller 24 i  for controlling the required delay. The delay controller 24 i  supplies a Change Delay signal to the delay unit 22 i . The received signal applied to the delay unit 22 i  can be a continuous analog signal, a sampled analog signal or a digital signal. Suitable delay units for each type of signal are described below. The delay controller 24 i  operates in a discrete time mode and supplies a binary Change Delay signal (change or no change) to the delay unit 22 i  in synchronism with a clock. 
     The controller 28 (FIG. 1) supplies delay coefficients to the delay unit 22 i  and to the delay controller 24 i . The delay coefficients supplied to the delay unit 22 i  represent the required initial delay for a particular transducer element to obtain the required steering angle of the receive beam. The initial delay may be specified for zero depth or for the shallowest depth of interest in the ultrasound image. The delay coefficients supplied to the delay controller 24 i  represent the position of the transducer element in the array, typically referenced to the center of the array, the desired steering angle for the received beam and the time at which dynamic focusing is to start. It will be understood that different delay coefficients are supplied for each different steering angle. 
     During reception of ultrasound energy, the delay unit 22 i  initially delays the received signal by the initial delay value. Thereafter, the delay controller 24 i  operates in real time to determine the times when the delay must be changed in order to dynamically focus the receive beam. The Change Delay signals are supplied to the delay unit 22 i  at discrete times so as to increment the delay applied by the delay unit 22 i . 
     A block diagram of the delay unit 22 i  and the delay controller 24 i  for a digital ultrasound beamformer is shown in FIG. 3. The signal conditioning unit 20 i  (FIG. 1) converts the received signal to a series of digital data samples. The data samples from the signal conditioning unit 20 i  are input to a two port random access memory (RAM) 40, which permits simultaneous writing and reading of data. The two-port RAM 40 and associated circuitry delay each of the data samples by selected delays that are quantized in increments equal to the sampling-clock period. The delayed data samples are supplied on output 42 of two-port RAM 40 to a delay interpolator 46. 
     The two-port RAM 40 operates as a &#34;circular&#34; memory. Locations in the RAM 40 are sequentially addressed by a write address counter 50, and the data samples are written into the addressed locations. The data samples are delayed by reading data from addresses that are offset from the write addresses. The read addresses are sequenced to provide a continuous stream of output data that is delayed with respect to the input data. The delay in sampling-clock periods is equal to the number of memory locations between the read address and the write address. 
     In order to perform dynamic focusing during receive, the delay applied to the data samples must be varied dynamically. In the delay generator of FIG. 3, changes in delay are effected by changing the difference between the write address and the read address in two-port RAM 40. Typically, the required delay remains constant for several clock cycles and then is incremented by one clock cycle. 
     The read address for the two-port RAM 40 is supplied by a read address counter 54. Locations in the two-port RAM 40 are addressed by the read address counter 54, and the data samples stored in the addressed locations are supplied on read data output 42 to the delay interpolator 46. The required delay is established by the difference between the write address and the read address. During periods when the delay is constant, locations in the RAM 40 are sequentially addressed by read address counter 54 in synchronism with write address counter 50, with a fixed difference between the read address and the write address. When the delay is to be incremented by one clock cycle, the read address counter 54 is held constant (stalled) for one clock cycle. The stalling of the read address counter 54 effectively changes the difference between the write address and the read address, because the write address counter 50 is not stalled. The STALL signal in FIG. 3 thus corresponds to the Change Delay signal in FIG. 2. 
     STALL signals for the read address counter 54 are supplied by the delay controller 24 i . The delay controller 24 i  receives delay coefficients from the controller 28 as described above. The delay coefficients are also supplied to the read address counter 54 so as to preset the read address counter at an address which represents the required initial delay for the given transducer element and steering angle. The delay controller 24 i  then controls the read address counter during reception of ultrasound energy by transducer array 10 in accordance with the delay equation, as described in detail below. During reception of ultrasound energy, the read address counter 54 is incremented by each clock pulse, except when a STALL signal is given by the delay controller 24 i . When a STALL signal is given, the read address counter 54 is stalled for one clock cycle. Since the write address counter 50 advances on each clock cycle, the STALL signal effectively increases the delay applied to the data samples by one clock cycle. 
     Examples of required delay as a function of elapsed time after transmission of an ultrasound pulse are shown in FIG. 6. The example shown in FIG. 6 illustrates the required delay for different transducer elements to achieve a steering angle of 22.5°. The read address counter 54 and the delay controller 24 i  cause the RAM 40 to apply a delay which increases as a function of time as shown in FIG. 6. It will be understood that different delay curves are utilized, depending on the steering angle and the position of the transducer element in the array. 
     As noted above, the two-port RAM 40 delays the data samples by selected delays that are quantized in increments equal to one sampling-clock period. The output of RAM 40 is supplied to delay interpolator 46, which delays each data sample by a selected subdelay that is quantized in increments of less than the sampling period. Thus, for example, each sample in the data stream can be delayed by 0, 1/4τ, 1/2τ, or 3/4τ, where τ is the sampling period. The delay interpolator 46 permits generation of high quality images without increasing the sampling clock rate. The subdelay control information for delay interpolator 46 is received from read address counter 54. The delay interpolator 46 is preferably implemented as a finite impulse response (FIR) digital filter having different selectable delays that are quantized in delays less than the sampling period. 
     A block diagram of an analog beamformer incorporating a delay generator in accordance with the present invention is shown in FIG. 4. The architecture of FIG. 4 is based on the principles of U.S. Pat. No. 4,140,022 and employs a so-called mix and delay (i.e., fine delay added to coarse delay) mechanism for focusing and steering. In the beamformer of FIG. 4, the fine delay in each channel is provided by delay unit 22 i  and delay controller 24 i , and the coarse delay is provided by a switch matrix 60 and a summing delay line 62. The switch matrix 60 receives delay coefficients representative of the steering angle and focal depth and selects a tap on the summing delay line 62 for the received signal in each channel. 
     In the delay unit 22 i , a mixer 64 is used to heterodyne selected clock phases Φ 1 , Φ 2 , . . . Φ M  with the received signal. The selection of clock phases is controlled by a multiplexer 68, a counter 70 and the delay controller 24 i . The multiplexer 68 selects one of the clock phases based on the state of counter 70. A delay coefficient loaded into the counter 70 represents a required initial delay to obtain a desired steering angle. The delay controller 24 i  then increments the counter 70 to maintain the required delay during reception of ultrasound energy. As described above, the delay controller 24 i  increments the counter 70 only when a change in delay is required. 
     A third embodiment of a beamformer incorporating the delay generator in accordance with the present invention is shown in FIG. 5. The embodiment of FIG. 5 is a discrete time analog beamformer. The analog signal representative of the received ultrasound energy from each transducer element is sampled at discrete times by a sampler 80 i . The analog samples in each channel are input to a variable analog delay 82 i , which can be a charge coupled device (CCD), bucket brigade or other analog charge storage and transfer device. The variable analog delay 82 i  delays the analog samples such that the receive beam is dynamically focused along a line at a prescribed steering angle. The delay coefficients from controller 28 preset an initial delay value in the variable analog delay 82 i . The delay is then controlled during reception of ultrasound energy by the delay controller 24 i . Each time the delay must be incremented, the delay controller supplies a Change Delay signal to the variable analog delay 82 i  to increment the delay to the next value. The output of each variable analog delay 82 i  is input to the combining unit 26. In the embodiment of FIG. 5, the combining unit 26 is shown as including a multiplier 86 i  for each processing channel. The multipliers 86 i  adjust the signal level in each channel, typically for apodization and gain control. The outputs of multipliers 86 i  are input to a summing unit 88, which provides the beamformer output 14. 
     In the beamformers described above, each sample of the received signal in a given channel is delayed in a delay unit 22 i  before being combined with signals from the other channels. The amount of delay for each channel must be controlled to produce a receive focus at a desired, time-varying point in the object. The ideal required delay can be derived from the imaging geometry as shown in FIG. 7. Given a finite sampling-clock period and a finite delay resolution (delay quantum), optimum beamformer performance requires that the delay applied to each sample be the nearest value to the ideal delay, chosen from the available discrete set of possible delay values. The function of the delay controller 24 i  is to control the delay unit 22 i  such that this optimum delay is achieved. 
     The delay unit 22 i  in the described beamformers maintains a constant delay until it receives a STALL signal from the delay controller 24 i . When the STALL signal is received, then the delay applied to the next sample is increased by one delay quantum. This new delay is maintained until the next STALL signal arrives. Thus the delay controller 24 i  must emit a STALL signal whenever the required delay for the next sample increases by one quantum. 
     Consider the geometry of FIG. 7. The coordinate system has its origin at point O on a multi-element transducer whose surface S may be of arbitrary shape. The transducer has N elements E 1  through E N . 
     In order to produce a focus at point P, the round-trip propagation time for ultrasound energy from O to P to a transducer element E i , plus the delay applied to the signal from that element, must be equal for all N elements, For the element at O, the round-trip propagation time is 2R/C (where C is the speed of sound in the object). We define the delay applied to the signal from this element to be zero for reference. Thus the following equation must be satisfied for each element E i  : ##EQU1## where T i  is the delay applied to the signal from the i th  element. 
     Using the law of cosines, this condition can be expressed in terms of Θ, the steering angle with respect to a normal to the transducer, and the coordinates (x i , y i ) of element E i  as: ##EQU2## We define τ 0  to be the delay quantum and T 0  to be the sampling-clock period. We require T 0  =kτ 0 , with k an integer ≧1. We can then re-express Equation (2) by taking τ 0  as our unit of time. 
     With the following definitions: 
     t   elapsed time since transmit, in units of ##EQU3## d   delay required by (2) in units of ##EQU4## S   (x i  sinθ+y i  cosθ)/Cτ 0  X (x i   2  +y i   2 ) 1/2  /Cτ 0   
     we have: ##EQU5## where d, S, and X are understood to be the values applicable at a particular element E i . 
     Equation (3) can be solved for t, giving: ##EQU6## 
     This equation can be understood as specifying, for the i th  element, the elapsed time since transmit at which a given focal delay d is applicable. Equations (3) and (4) represent the ideal delay vs. elapsed-time function, in which both elapsed time and delay are continuous variables. 
     In the described beamformers, the delay value can be updated at each sampling-clock period. The delay controller 24 i  is required to decide, in each sampling-clock period, whether the applied delay value should be kept constant or be incremented by one unit of τ 0  for the next sample. If an increment is required, the delay controller 24 i  must output a STALL signal. The algorithm for arriving at this discrete-time decision will now be derived from the continuous-time ideal-delay equations given above. 
     In FIG. 8, Equation (4) is plotted for a small range of d. With reference to FIG. 8, we define: 
     a) the integer delay values D 0 , D 1 , . . . where D i  =D i-1  +1; 
     b) the elapsed time values (in general not integers) t 0 , t 1 , . . . where t i  is the solution of Equation (4) at d=D i  +1/2; and 
     c) the integer elapsed time values n 0 , n 1 , . . . where n i  =GI {t i  } (i.e., n i  is the Greatest Integer in t i ). 
     As can be seen from FIG. 8, the set of integer elapsed-time values for which D i  is the nearest integer value to the ideal delay required by Equation (4) is n i-1  +1 . . . n i . Thus when n is equal to any n i , the delay must increase by one quantum for the next sample (i.e., at these times the delay controller 24 i  must emit a STALL signal). 
     From the definitions above (see FIG. 8) it is apparent that: 
     
         n.sub.i -n.sub.i-1 =GI{t.sub.i -n.sub.i-1 }                (6a) 
    
     
         and t.sub.i -n.sub.i =FP{t.sub.i -n.sub.i-1 }              (6b) 
    
     Where GI is defined above, the FP means &#34;Fractional Part&#34;, i.e., FP{x}=x-GI{x}. 
     We can write (see FIG. 8): 
     
         t.sub.i -n.sub.i-1 =(t.sub.i -t.sub.i-1)+(t.sub.i-1 -n.sub.i-1)(7) 
    
     From Equation (4) and the definitions above, it can be shown that the change in t resulting from a change in d from (D i-1  +1/2) to (D i  +1/2) is: ##EQU7## 
     Substituting this result into Equation (7), and using the definition D i  =D i-1  +1, we obtain: ##EQU8## In Equation (8), t i  -n i-1  is obtained as the result of a division operation. This division can be carried out by repeatedly subtracting the denominator in Equation (8) from the numerator, until the residue of the numerator is less than the denominator. Then the number of such subtractions is equal to GI{t i  -n i-1  }, and therefore, by Equation (6a), to n i  -n i-1 . Defining R i  to be the residue of the numerator in the operation just described (R i  =RES{t i  -n i-1  }), we have: ##EQU9## 
     Combining this result with Equation (6b), we have: 
     
         R.sub.i =(t.sub.i -n.sub.i) (S-D.sub.i -1/2)               (10) 
    
     Since n i-1  will have been generated from n i-2  by an equivalent division process, the residue R i-1  from that division must be: 
     
         R.sub.i-1 =(t.sub.i-1 -n.sub.i-1) (S-D.sub.i-1 -1/2)       (11) 
    
     Thus, substituting Equation (11) into Equation (8), we obtain: ##EQU10## 
     Equations (6a) and (12), the definition of D i , and the discussion of division by repeated subtraction yield the following recursion rules for obtaining n i , R i , and D i  from their predecessors: 
     
         D.sub.i =D.sub.i-1 +1                                      (13a) ##EQU11## 
    
     This recursive algorithm, starting from suitably chosen initial values of n, R, and D, generates the required sequence n 1 , n 2 , . . . of times at which the delay must be incremented (i.e., the delay controller 24 i  must emit a STALL signal). 
     A hardware embodiment of the recursion in Equation (13) is based on repeated subtraction, as in the discussion of Equation (8). In principle such a hardware embodiment calculates n i  from n i-1  as follows. 
     At n=n i-1 , a register N is loaded with the numerator in Equation (13b), and a second register A is loaded with the denominator. At n=n i-1  +1, A is subtracted from N. At n=n i-1  +2, a second such subtraction occurs. Each subtraction consumes one sampling-clock period. This process repeats until N&lt;A. At that time, the number of sampling-clock periods consumed is equal to n i  -n i-1 , in accordance with Equation (13b), so n=n i . At the same time, the quantity remaining in N is R i , in accordance with Equation (13c). Since n=n i , the delay controller 24 i  outputs a STALL signal (causing D to be incremented from D i  to D i+1 ). The calculation of n i  is complete, and registers N and A must be prepared for the calculation of n i+1 . 
     In practice, the following modifications of this process are necessary: 
     1. The loading of register N with the numerator of Equation (13b) must be combined in a single sampling-clock period with the first subtraction of A from N. This combined result is loaded into N when n=n i-1  +1. 
     2. Another register, B, is needed to prepare the quantity to be loaded into N at the beginning of each calculation cycle. 
     In addition, one more modification is expedient: 
     3. The contents of A are made equal to the negative of the denominator in Equation (13b), so that A can be added to rather than subtracted from N. The condition for incrementing D thus becomes N+A&lt;0. 
     From Equation (13) and point 1 above, the quantity which must be loaded into register N at n=n i-1  +1 is: ##EQU12## 
     At n=n i-1 , N contains R i-1 , so the bracketed quantity in Equation (14) must be added to N at n=n i-1  +1. This is the quantity to be supplied by register B. Register B&#39;s value is generated by a recursive process. From Equation (14), the change in B from n=n i-1  to n i  is: 
     
         ΔB=(n.sub.i -n.sub.i-1)+(1-2/k)                      (15) 
    
     Thus, after appropriate initialization, B can be made to have the correct value at each n i  by incrementing B at each sampling clock, and, in addition, adding (1-2/k) to B each time D is updated. 
     Register A is constant between D updates; the change in A from n=n i-1  to n=n i  is: 
     
         ΔA=+[-(S-D.sub.i -1/2)]-[-(S-D.sub.i-1 -1/2)]=1      (16) 
    
     Thus A must be incremented by 1 each time D is updated. 
     The contents of registers A, B and N can be summarized as follows; at n=n i-1 , 
     
         A=-(S-D.sub.i-1 -1/2)                                      (17a) 
    
     
         B=n.sub.i-1 +1/2-S+(1-2/k)D.sub.i                          (17b) 
    
     
         N=R.sub.i-1                                                (17c) 
    
     The recursion rules for A, B, D, and N developed above can be summarized as follows: 
     If N+A≧0 (no D update): 
     
         N←N+A                                                 (18a) 
    
     
         A←A                                                   (18b) 
    
     
         B←B+1                                                 (18c) 
    
     
         D←D                                                   (18d) 
    
     If N+A&lt;0 (D update required): 
     
         N←N+B                                                 (19a) 
    
     
         A←A+1                                                 (19b) 
    
     
         B←B+(2-2/k)                                           (19c) 
    
     
         D←D+1 [emit a STALL signal]                           (19d) 
    
     The &#34;D update required&#34; condition occurs when n=n i  for any i; the &#34;no D update&#34; condition occurs for all other values of n. 
     The recursion rules in Equations (18) and (19) are embodied directly in the circuit shown in block diagram form in FIG. 9. The circuit includes a register 110 which holds the quantity A, a register 112 which holds the quantity B and a register 114 which holds the quantity N. Each register is clocked by the sampling clock. Adder 136 generates a signal equal to N+A. The sign bit of this signal, which has the logical value (N+A) &lt;0, is the STALL signal. Thus, STALL=TRUE indicates that the Equation (19) update rules should be used; STALL=FALSE indicates that the Equation (18) rules should be used. In addition, the STALL signal is sent to the delay unit 22 i  where it causes the delay D to be incremented. 
     A multiplexer 120 supplies inputs to register 110 on each clock pulse. The multiplexer 120 is controlled by the STALL signal. When the STALL signal is true, the multiplexer 120 supplies the output of an adder 122 to the register 110. The adder 122 adds 1 to the output of register 110. When the STALL signal is false, the multiplexer 120 supplies the output of register 110 to its input. 
     The register 112 receives inputs on each clock pulse from an adder 124, which sums the output of register 112 and the output of a multiplexer 126. The multiplexer 126 is controlled by the STALL signal. When the STALL signal is true, the multiplexer 126 supplies the value (2-2/k) to one input of adder 124. When the STALL signal is false, the multiplexer 126 supplies the value 1 to adder 124. 
     The register 114 receives inputs from an adder 130 on each clock pulse. The adder 130 sums the output of the register 114 and the output of a multiplexer 132. The multiplexer 132 is controlled by the STALL signal. When the STALL signal is true, the multiplexer 132 supplies the output of register 112 to one input of adder 130. When the STALL signal is false, the multiplexer 132 supplies the output of register 110 to adder 130. An adder 136 sums the outputs of registers 110 and 114 and outputs the STALL signal. 
     The registers 110, 112 and 114 receive appropriate bits of the delay coefficients which contain the initial values of A, B and N for a given steering angle. The registers 110, 112 and 114 also receive a Hold signal. When the Hold signal is active, the clock has no effect on the registers. The hold function is utilized to inhibit the operation of the delay controller until signals corresponding to a predetermined minimum image depth are being received. 
     The delay controller shown in FIG. 9 can be simplified by delaying the Equation (18) vs (19) update decision by one sampling clock. This second, simplified embodiment of the delay controller is shown in FIG. 10. The value in the N register 114 is allowed to become negative, and its sign (here labeled NEG) replaces STALL as the update-rule-selection control signal for A, B, and N. STALL itself, which now controls only the D update (in the delay unit), equals the sign of the output of adder 130. As shown in FIG. 10, the logical value of STALL in this embodiment of the delay controller is: ##EQU13## 
     The update rules embodied in this embodiment of the delay controller are: 
     If STALL=FALSE 
     
         D←D (no update)                                       (20) 
    
     If STALL=TRUE 
     
         D←D+1 (D update required)                             (21) 
    
     If N≧0 
     
         N←N+A                                                 (22a) 
    
     
         A←A                                                   (22b) 
    
     
         B←B+1                                                 (22c) 
    
     If N&lt;0 
     
         N←N+B                                                 (23a) 
    
     
         A←A+1                                                 (23b) 
    
     
         B←B+(2-2/k)                                           (23c) 
    
     This second delay controller embodiment produces exactly the same sequence of STALL signals as the one shown in FIG. 9. 
     The delay controller described above has been shown to implement the ideal-delay Equation (4) exactly, within the elapsed-time and delay quantization limits. To achieve this exact solution, the values in the A, B, and N registers must be of infinite precision. In practice, a finite number of bits must be used. A fractional part of 3 bits (resolution of 1/8) has been found to assure maximum errors much smaller than the delay quantum. Thus in a preferred embodiment of the delay controller, the number of fractional bits is three in each register 110, 112 and 114. 
     The length of the integer part of the A, B, and N registers depends on maximum probe size (aperture length), wavelength, maximum steering angle, minimum focal distance of interest, and sampling-clock period. In a preferred embodiment, which encompasses many cases of practical interest, the lengths are: 
     A: 10 bits (integer)+3 bits (fraction)+1 bit (sign)=14 bits total 
     B: 14 bits (integer)+3 bits (fraction)=17 bits total 
     N: 14 bits (integer)+3 bits (fraction)+1 bit (sign)=18 bits total 
     If k=1, this delay controller is capable of operation for all n&gt;0. For k&gt;1, there exists minimum value of n, n min , (dependent on X and S) below which the controller cannot function correctly. For values of n&gt;n min , the delay controller gives the correct, non-approximate solution (within the error limits set by finite register resolution). This limit on minimum n is imposed by the method chosen for controlling D: since STALL is only available once per sampling-clock period, then the maximum change in D is one delay quantum per sampling-clock period. For large X and S and k&gt;1, this rate is exceeded for small n. 
     In a practical imaging system based on this delay controller, with k&gt;1, a fixed focus can be used for n&lt;n min  and dynamic focus used for larger n. For small n, only transducer elements near the center of the transducer (having small X and S) are useful due to other effects, so in many cases the limit imposed by the delay controller is not of practical significance. For small n, only a small part of the transducer (&#34;active aperture&#34;) is used to form the image, and the active aperture is expanded as n grows, until all elements are in use. This expanding-aperture technique is widely used in existing ultrasound imaging systems. 
     The delay controllers shown in FIGS. 9 and 10 and described above generate delays for a steering angle Θ that is constant during reception of ultrasound energy along each scan line. In some cases, it may be desirable to vary the steering angle Θ dynamically during reception of ultrasound energy, in addition to dynamic focusing as described above. The steering angle Θ of the receive scan line is varied by a deviation ΔΘ, which is a function of time, during reception of ultrasound energy. As a result, the receive scan line, or scan path, may not be a straight line. As used herein, the term &#34;warping&#34; refers to dynamically varying the steering angle Θ by a deviation ΔΘ during reception of ultrasound energy. As described below, the deviation ΔΘ is controlled by varying the delays applied to the received signals in each channel of the beamformer. 
     Equation (2) above gives the round trip travel time T i  for element E i  of the transducer array. In order to obtain the round trip time for a small deviation in the steering angle, Θ+ΔΘ is substituted for Θ in Equation (2). Using the small angle approximations sin ΔΘ approximately equal ΔΘ and cos ΔΘ approximately equal 1, we obtain ##EQU14## For a flat array, y i  =0, and the round trip travel time T i  is ##EQU15## 
     Equation (25) has the same form and dependence on t as Equation (24). If we can find a solution for Equation (20), we can solve Equation (24) by substituting: 
     
         x.sub.i (sinθ+Δθcosθ)→x.sub.i (sinθ+Δθcosθ)+y.sub.i (cosθ-Δθsinθ)                     (26a) 
    
     
         x.sub.i.sup.2 →x.sub.i.sup.2 +y.sub.i.sup.2         (26b) 
    
     Therefore, we will base the following discussion on Equation (25). 
     A comparison of Equation (25) with Equation (2) for the case where y i  =0 indicates that Equation (25) is identical to Equation (2) with the substitution 
     
         sinθ→sinθ+Δθcosθ      (27) 
    
     The above derivation can be used to determine the contents of registers A (110), B (112), and N (114) (FIGS. 9 and 10) for the delay generator with warping in terms of the contents of the registers A, B and N in the delay generator without warping. The delay generator with warping is one in which the steering angle Θ can be varied dynamically by a small deviation ΔΘ during reception of ultrasound energy, as described above. By making the substitution of Equation (27) in Equations (17a), (17b) and (17c) for A, B and N, respectively, the following results are obtained. 
     
         [A].sub.warped =[A].sub.nonwarped -Δθcosθx.sub.i(28) 
    
     
         [B].sub.warped =[B].sub.nonwarped -Δθcosθx.sub.i(29) 
    
     
         [N].sub.warped =[N].sub.nonwarped                          (30) 
    
     where x i  is in units of Cτ o . 
     Since the same term (ΔΘcos Θe) is subtracted from the A register and from the B register, it may be equivalently subtracted from the N register. Thus, the operation of the warped delay generator is based on the operation of the non-warped delay generator described above, with ΔΘcos Θe subtracted from the N register. 
     The desired values of steering angle deviation ΔΘ to control the delay generator with warping are received from the controller 28 (FIG. 1). The values of steering angle deviation ΔΘ vary with depth as a function of time during reception and also vary with transmit focal depth, steering angle and transducer element position. The ΔΘ values are stored and then are supplied to each channel of the beamformer on a dynamic basis during imaging. In order to keep the data storage and handling requirements within practical limits, the region being imaged is preferably divided into zones. Each zone is defined by start depth and a stop depth from the transducer array. Within each zone, a constant value of ΔΘ is utilized. In a preferred embodiment, the region being imaged is divided into 16 zones. In zone 0, closest to the transducer array, ΔΘ is arbitrarily set at 0. The value of ΔΘ in zone 15 is used for all depths greater than zone 15. 
     The delay generator with warping is implemented as a modification of the delay generator without warping. As described above, warping can be implemented by subtracting the value of ΔΘcos Θe from the N register in the delay controller 24i of each channel. The calculation is performed on a zone-by-zone basis so that the value of ΔΘ for the following zone is correct at the end of each zone. The times when the STALL commands are issued are modified by the ΔΘ values to result in warping of each receive scan line. As a further simplification, the calculation of ΔΘ for each zone is preferably performed for groups of eight beamformer channels, and the same ΔΘ values are used by the eight channels in each group. 
     Changing the N register instantaneously by ΔΘcos Θe does not instantaneously change the scan angle by ΔΘ. To change the scan angle at any point in the line, all the changes muse be added to the N register that would have occurred if the angle had been changed at the beginning of the line. Consider the case where the scan angle changes at the end of each focal zone and we want the scan path to have the correct angle at the end of the zone. From Table 1 below, we see that to change the scan angle from ΔΘ 1  to ΔΘ 2  during zone 2, we must use the angle ΔΘ 1  +3(ΔΘ 2  -ΔΘ 1 ) because we are making the change during one zone instead of three zones from the start of the line. 
     
                       TABLE 1                                                     
______________________________________                                    
                       Required change                                    
Zone    Deviation ΔΘ                                          
                       during zone                                        
______________________________________                                    
0       ΔΘ.sub.0                                              
                       ΔΘ.sub.1                               
1       ΔΘ.sub.1                                              
                       Θ.sub.0 + 2(ΔΘ.sub.1             
                       - ΔΘ.sub.0)                            
2       ΔΘ.sub.2                                              
                       ΔΘ.sub.1 + 3(ΔΘ.sub.2 -    
                       ΔΘ.sub.1)                              
3       ΔΘ.sub.3                                              
                       ΔΘ.sub.2 + 4(ΔΘ.sub.3 -    
                       ΔΘ.sub.2)                              
.       .                .                                                
.       .                .                                                
.       .                .                                                
______________________________________                                    
 
    
     In general, a change of Z+1 times the difference in the start and end zone angles is applied in zone Z. 
     The above scheme gives exactly the desired changes at the end of the focal zones. At any point along the scan line, the effective deviation angle γ(t), is given by ##EQU16## Integrating up to zone Z gives ##EQU17## where T is the time duration of a focal zone. Finishing the integration yields ##EQU18## Changing the origin of time from the start of the line to the start of zone Z gives ##EQU19## The above equation shows that the scan path between zone ends is not a straight line. Simulations show that the scan angle changes faster at the start of a zone than at the end. The exact path does not matter. The important feature is that the delay generator keeps all the channels focused. 
     Since simulations indicate that 16 zones of warping are adequate, the warped scan path can be specified by 15 numbers. Each number specifies the amount of warping at the end of the zone. To simplify the hardware and software, the amount of warp at the end of zone 0 is 0, and the warp after zone 15 is the same as at the end of zone 15. Simulations also show that the warp angle can be specified by a 4 bit 2&#39;s complement number. Without loss of any desired scan modes, groups of eight channels can share a common scan path specification. FIGS. 11-1 and 11-2 show the hardware which groups of eight channels can share, and FIGS. 12-1 and 12-2 show the additional hardware which must be added to each delay controller to perform warping. Appendix A contains the hardware control equations. In Appendix A, the symbol &#34;:=&#34; means set equal on the next clock cycle. 
     Unlike the normal delay generator which is held off until the F number is large enough, the delay generator with warping hardware begins its calculations at time t=0 for the center channel. A delay (DL) register 200 and its associated hardware, including multiplexer 202, decrementer 204 and zero detector 206, form a programmable delay from the rising edge of the SUM-ENABLE signal to t=0. DL register 200 is loaded at the start of each line. 
     A focal zone length (FZL) register 212 and its associated hardware, including multiplexer 214, decrementer 216 and zero detector 218, provide variable length focal zones. Zero detect circuitry 218 provides a pulse at the end of each zone. These pulses are counted by a zone address (ZA) counter 220, which includes ZA register 222, multiplexer 224, incrementer 226 and 15 detector 228. The FZL register 212 is loaded at the start of each line and at the end of each zone. The ZA register 222 is cleared at the start of each line. 
     The delay generator with warping calculates the warp as 
     
         warp=-(Δθ.sub.Z-1 -(Z+1) (Δθ.sub.Z -Δθ.sub.Z-1))x.sub.i cosθ               (35) 
    
     Expressing the warp angle as an integer times a scale factor, s, gives 
     
         warp=-(alpha.sub.Z-1 -(Z+1) (alpha.sub.Z -alpha.sub.Z-1)) (s cosθx.sub.i)                                        (36) 
    
     where alpha ranges from -7 to +7. Alpha 1  is stored in alpha[0], location 0 of alpha register bank 250. Table 2 below shows the value of the alpha factors in the warp equation for each zone. 
     
                       TABLE 2                                                     
______________________________________                                    
ZONE       ALPHA FACTOR                                                   
______________________________________                                    
0          0                                                              
1          2*alpha[0]                                                     
2          alpha[0] + 3*(alpha[1] - alpha[0])                             
3          alpha[1] + 4*(alpha[2] - alpha[1])                             
4          alpha[2] + 5*(alpha[3] - alpha[2])                             
5          alpha[3] + 6*(alpha[4] - alpha[3])                             
6          alpha[4] + 7*(alpha[5] - alpha[4])                             
. . .                                                                     
15         alpha[13] + 16*(alpha[14] - alpha[13])                         
16         alpha(14]                                                      
______________________________________                                    
 
    
     FIGS. 13-1 and 13-2 show the timing for the calculation of the zone 6 alpha factor assuming alpha[4]=6 and alpha[5]=7. Since the calculation must be complete at the start of zone 6, it is performed during zone 5. In FIGS. 13-1 and 13-2, the contents of the indicated registers are shown during each clock cycle. Associated with an S-ANG register 240 are a multiplexer 242 and an adder/subtractor 244. At the start of zone 5, the S-ANG register 240 contains -6*alpha[4]=-36 and the FZL counter 210 generates a pulse. After the pulse increments the ZA counter 220, alpha[5] becomes available at the output of the alpha register bank 250. The contents of the ZA register 222 are clocked into mul count (MC) register 262. Under control of MC counter 260, which includes MC register 262, multiplexer 264, decrementer 266 and zero detector 268, the output of the register bank 250 adds to the S-ANG register 240 for 7 cycles. The S-ANG register 240 now contains 7*alpha[5]-6*alpha[4]=13. The GOOD-S-ANG signal then loads this result into an angle count (AG) register 280 (FIG. 12-1), and a SIGN register 292. Associated with AG register 280 are multiplexer 282, decrementer 284, incrementer 286 and zero detector 288, and associated with SIGN register 292 is multiplexer 290. The MC register 262 is reloaded and the S-ANG register 240 is cleared. Under control of the MC counter 262, the output of the register bank 250 now subtracts from the S-ANG register 240 for 7 cycles. The S-ANG register 240 now contains -7alpha[5]=49. 
     By repetitive addition in the per channel hardware, x i  cos Θs is multiplied by -(7*alpha[5]-6*alpha[4]). The angle count register 280 serves as the count register, and a new warp (NW) register 300 serves as the accumulator. A multiplexer 302 and an adder/subtractor 304 are associated with NW register 300. The x i  cos Θs term has 3 more bits of precision than the other delay generator presets to reduce the magnification of truncation error generated by repetitive addition. The extra precision is removed in rest of the calculations by loading a warp (W) register 310 with only the top 15 bits of the final NW register 300 results. A multiplexer 312 is associated with the W register 310. 
     As a final item of interest, the delay generator with warping accesses alpha[14] during the 15th zone and calculates the alpha factor, 17*alpha[14]-16*alpha[14]=alpha[14]. This value is then used for the rest of the scan line. 
     To implement the delay generator with warping, the per channel hardware shown in FIGS. 12-1 and 12-2 is added to the per channel hardware shown in FIG. 9 or FIG. 10. The two input adder 130 shown in FIGS. 9 and 10 is replaced with a three input adder 130&#39; shown in FIG. 12-2. The common hardware shown in FIGS. 11-1 and 11-2 is replicated for each group of 8 channels. 
     In one example of the delay generator with warping, the DL register 200 has 14 bits, the FZL register 212 has 10 bits, the MC register 262 and the ZA register 222 each have 4 bits, the alpha register bank 250 has 15 words by 4 bits, and the S-ANG register 240 has 9 bits. In the per channel additional hardware, the AG register 280 has 8 bits, the NW register 300 has 18 bits and the W register 310 has 15 bits. It will be understood that different register sizes can be used, depending on the system requirements and the required precision. 
     The presets provided by the controller 28 to the common warp generator hardware shown in FIG. 11 include the alpha values for the alpha register bank 250 (15 words by 4 bits), the required delay for DL register 200 (14 bits) and the focal zone length for FZL register 212 (10 bits). The preset for the additional per channel hardware shown in FIGS. 12-1 and 12-2 includes the contents of NW register 300 (10 bits). The external control signals for the delay generator with warping are as follows: 
     (1) SUM-ENABLE is a timing signal which enables the start of the delay generator with warping; 
     (2) LOAD-DL is a control pulse to load the delay register 200 before the start of a line; 
     (3) LOAD-FZL is a control pulse to load the FZL register 212 before the start of the line; 
     (4) LOAD-BANK is a control bus to load the alpha register bank 250 before the start of the line; 
     (5) WARP-ON is a control bit that enables warping; and 
     (6) PDATA is a data bus for loading registers. 
     While there have been shown and described what are at present considered the preferred embodiments of the present invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims. 
     APPENDIX A 
     CONTROL LOGIC EQUATIONS FOR COMMON WARP GENERATOR HARDWARE 
     COUNT-FZL:=SUM-ENABLE*(DL=0)+COUNT-FZL*SUM-ENABLE 
     LATER-DL:=(DL=0)+LATER-DL*SUM-ENABLE 
     LOAD-MC:=/LATER-DL*(DL=0)+(FZL=0)+ADD-ALPHA*/COUNT-MC 
     COUNT-MC:=LOAD-MC+SUM-ENABLE*COUNT-MC*/(MC=0) 
     SUM-ALPHA:=LOAD-MC+SUM-ENABLE*SUM-ALPHA*COUNT-MC 
     DFZL:=/LATER-DL*(DL=0)+(FZL=0) 
     ADD-ALPHA:=DFZL+SUM-ENABLE*ADD-ALPHA*COUNT-MC 
     GOOD-S-ANG:=ADD-ALPHA*/COUNT-MC 
     DGOOD-S-ANG:=GOOD-S-ANG 
     SUM-WARP:=DGOOD-S-ANG*/(AG=0)+SUM-ENABLE*SUM-WARP*/(AG=0) 
     UPDATE:=/LATER-DL*(DL=0)+SUM-ENABLE*UPDATE*/((FZL=0)*(ZA=15))