Two mode sense amplifier with latch
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates generally to sense amplifier circuits, and, more particularly, to sense amplifier circuits for use in memory arrays using transistor memory cells. More specifically, the present invention relates to a two mode sense amplifier for use in a memory array using either static RAM or dynamic RAM transistors that includes a latch for driving the output data. 
     2. Description of the Related Art 
     Sense amplifiers for use in memory arrays are well-known. A typical sense amplifier is used to detect low-level signals received from the cells within the memory array and convert the signals to levels compatible with the rest of the system in which the memory is used. As memory density increases, the memory cell size and the corresponding cell output signal is reduced, thereby making the sense amplifier critical for high-speed applications. The sense amplifier should be highly sensitive and still meet the speed requirements of the high-density memories. 
     A conventional sense amplifier detects the memory cell output through a differential amplifier, which is highly sensitive, but has very small voltage gain. The sense amplifier requires a biasing circuit that uses static power and is also supply voltage and process sensitive. 
     Separate latch circuits are also provided to hold the output data to drive the next stage. These additional circuits typically induce added delay in the sense amplifier. 
     SUMMARY OF THE INVENTION 
     It is therefore one object of the present invention to provide sense amplifier circuits. 
     It is another object of the present invention to provide sense amplifier circuits for use in memory arrays using transistor memory cells. 
     It is yet another object of the present invention to provide a two mode sense amplifier for use in a memory array using either static RAM or DRAM transistors that include a latch for driving the output data. 
     The foregoing objects are achieved as is now described. According to the present invention, a sense amplifier apparatus for use in a memory array having a plurality of memory cells is provided. The sense amplifier apparatus includes a differential sense amplifier mode and a dynamic sense amplifier mode. A complementary pair of input lines and output lines are provided as well as a sense enable line and a latch enable line. A latch is also provided, which is coupled to the output lines and is used to drive these lines. Separately, a precharge circuit is connected to the input lines for precharging the complementary pair of input lines and an output precharge circuit is also provided for precharging the complementary pair of output lines. The differential sense amplifier mode has a first set of switches for driving the voltages of the sense amplifier apparatus and are coupled to the complementary pair of outputs. Also provided are a second set of switches, which are coupled to the complementary pair of input lines and sense enabling line (SE) so as to amplify the input signal on either of the pair of input lines to a first signal level at a first rate of amplification. The dynamic sense amplifier shares the first set of switches with the differential sense amplifier and further includes a third set of switches that are coupled to the output lines and also to the latch enable line (LE). This allows the first signal level to be amplified to a second signal level at a second rate of amplification faster than the first rate of amplification. The latch is used to maintain the amplified signal at about the same level as the second signal level. The amplifiers are designed so that a pair of switches within the second set of switches are coupled one to another and to the complementary pair of input lines so as to greatly reduce the impedance normally seen by the input signal. The sense amplifier provides means to support precharging of the complementary pairs of output and input lines in preparation for the next operation cycle. 
     In one embodiment, the memory array is a CMOS memory array and has a memory signal output line and a circuit for sensing and amplifying the output on the memory signal output line. The circuit for sensing and amplifying also includes a differential amplifier circuit, which is precharged to a predetermined level prior to a sense operation. A dynamic amplifier is also provided, which incorporates a latch circuit and is coupled to an output from the differential output circuit. Means are also provided, being coupled to the differential amplifier and responsive to the memory output signal, for initiating a sense operation and for driving the differential amplifier circuit. Additionally, the dynamic amplifier circuit is coupled to means for driving the dynamic amplifier circuit. The sense amplifier also includes means to use the amplifier drivers to drive test signals during chip testing by turning off the amplifier mode and supplying test signals to the input of the sense amplifier output drivers. The switches are typically N-FET and P-FET CMOS gate transistors. 
     The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
     FIG. 1 depicts in accordance with a preferred embodiment of the present invention a SRAM, which includes a plurality of precharged circuits; 
     FIG. 2 illustrates a prior art sense amplifier; 
     FIG. 3 is a schematic diagram of a sense amplifier according to the present invention; 
     FIG. 4 depicts a timing relationship between signals and data. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention is directed to an improved sense amplifier used within a static random access memory (SRAM) or dynamic RAM (DRAM). FIG. 1 depicts SRAM 10, which includes a plurality of precharged circuits 12, which are used to restore or precharge the bit line (BL) and the inverted bit line (BL) to VDD at the end of each array access. Each bit line and its complementary line, BL and BL, are further connected to a plurality of cells 14 within the array. Each cell along a row is controlled by a word line (WL). There are n word lines for n rows of cells. Each bit line BL and BL further connect to column decoder 16. The output from column decoder 16 further connect to sense amplifier 18 via data line DL and DL. Sense amplifier includes further outputs OUT and OUT. The DL and DL and OUT and OUT lines are precharged to VDD at the end of each cycle in preparation for the next cycle. Whenever the word line WL goes high, it selects a particular memory cell on that row. Depending upon the data stored in the memory cell 14, one bit line BL or BL will stay high while the other bit line will discharge. Additionally, one of the column decoders 16 is selected, such as, for example, in a 8:1 decoding arrangement, and BL and BL drive the respective DL and DL lines. 
     Sense amplifier 18 is used to amplify the differential signal from memory cell 14 in the array design of SRAM 10. A typical SRAM 10 uses a six transistor cell. Each memory cell 14 must be able to drive a long column decoder IN, IN. For example, in the case of the present invention, it is desired that the bit lines be able to develop a 250 millivolt (mv) difference on the data lines within a 10 to 600 picosecond time frame once the word line goes high. Next, the 250 millivolts differential voltage is then further amplified in a short time period. The time period for 250 millivolt differential voltage is established for the input to set the sense amplifier since if the process deviates toward the slower process time, there would still be a large enough differential voltage on the input to the sense amplifier. Additionally, a latch is used after the sense amplifier to keep driving the data from the array, amplified by the sense amplifier 18, to a comparator, MUX, or Array Built In Self-Test (ABIST) or a combination of the three, while the bit lines are precharged and the inputs to sense amplifier 18 are readied for the next cycle. Prior sense amplifiers were incapable of driving other circuits whose total capacitance is more than one picofarad of load; therefore, drivers were necessary to drive the signal from the sense amplifiers. A prior art sense amplifier 19 is illustrated in FIG. 2. Sense amplifier 19 includes a pair of precharge circuits 21 and 23, which further connect to a pair of latch circuits 25 and 27. Coupled between latch circuits 25 and 27, are the transistors comprising the sense amplifier portion of sense amplifier 19. 
     Both precharge circuits use a 3-transistor design, with precharge circuit 21 prestaging control or equalization LEX line and further driving OUT and OUT lines. Precharge circuit 23 prestages equalization EQ line and is further connected to the sense amplifier circuitry, which comprises transistors T3, T4, T5, T29, T31, and T30. Transistors T23, T29, T30, and T31 are P channel field effect transistors (FET) while transistors T4 and T5 are N channel FETs. IN and IN lines are precharged by precharge circuit 23 and further connect to the sense amplifier portion of sense amplifier 19. IN line is further connected to latch circuit 25 and IN line is connected to latch circuit 27. Unfortunately, sense amplifier 19 suffers from several problems. 
     One problem is that sense amplifier 19 has infinite gain. Accordingly, if sense amplifier 19 senses the wrong data, it never recovers. This leads to wrong data being sent to the output. A second problem is that it is slow because of high input capacitance, which is developed by the input capacitance from the gate and junction of the transistors. Once the word line goes high, about 913 picoseconds pass before it develops the adequate 250 millivolt differential voltage on the input of the sense amplifier by the memory cell. Once the sense amplifier reaches 250 millivolts differential voltage on the inputs, another 220 picoseconds is required to establish a 1.7 volt difference on the outputs (IN and IN) of the sense amplifier. Third, this particular arrangement for the sense amplifier dissipates quite a bit of power. Once the amplifier is turned on, the inputs of the amplifier go to full rail, or IN input goes to VDD while its complement goes to ground. This then feeds back to the bit lines, which then dissipates more power to precharge the bit lines in the input of the sense amplifier. Furthermore, latch circuits 25 and 27 are separate elements of sense amplifier 19, and are used to drive the output data to the comparator and MUXs. This requires additional circuits that induce added delay in the sense amplifier. 
     Accordingly, a sense amplifier, which overcomes the problems and difficulties found in the prior art solutions, is illustrated in the schematic diagram of FIG. 3. Sense amplifier 18 in FIG. 3 is a detailed schematic diagram of the sense amplifier 18 illustrated in FIG. 1. Transistors T1, T2, T3, T4, T5, T6,and 77 form a differential sense amplifier, while transistors T1, T2, T3, T4, T8, T9, and T10 are arranged to serve as a dynamic sense amplifier. Transistors T1, T2, T3, T4 are pull-up P channel devices, or field effect transistors, while transistors T5-T10 are N channel MOSFETS. A latch circuit is incorporated in the dynamic sense amplifier and comprises transistors T1, T2, T3, T4, and T8, T9, T10. Transistors T8, T9, T10 hold data inside the latch circuit as received from the dynamic sense amplifier, This provides three different sets of transistors that interact to form a two mode sense amplifier having a latch integrated therein. The first set of transistors or switches is comprised of T1, T2, T3, and T4, while the second set of switches comprises transistors T5, T6, and T7, and the last, or third set of switches comprise transistors T8, T9, and T10. 
     Transistors T 1 and T2 are connected together through their gates, which are tied to a Logic Built-In Self-Test (LBIST) control line. One end of transistors T1 and T2 are tied to VDD, with T1 being further connected in series to T3 and with T2 being further connected in series to T4. T3 is further connected in series to T5 and T9 while T4 is further connected in series to T6 and T10. The gate of T3 is connected between T4 and T6 and T10, while the gate of T4 is connected between T3 and T5 and T9. T5 is further connected in series to T7, which has its gate tied to the sense enable or SE line. T5 is also further connected to the other end of T6. The junction between T3 and T5 forms node 9 (NET9). Node 9 is further connected to OUT line by invertors 11 and 12. The latch enable (LE) line connects to the gate of transistor TB, which has one end tied to ground and another end tied to the parallel combination of T9 and T10. T9 has its gate tied to the other end of T10 and the gate of T3, while T10 has its gate tied to the other end of T9 and to the gate of T4. The connection between T4 and T6 form node 16 (NET16), which also serves as OUT line, which is further connected to invertors 13 and 14 which then drive the OUT line. 
     The gate of T5 serves as the IN line and the gate of T6 serves as the IN line, each further connects to a precharge circuit 20, which uses a trio of pull-up P channel FETs for precharging the IN and IN lines when activated by the EQ2 line. A second precharger 22, arranged in the same fashion as precharger circuit 20, is used to precharge OUT and OUT lines at nodes 9 and 16, respectively. Precharge circuit 22 is activated by the LEX signal. 
     The output drivers of the sense amplifier is further used for testing comparators, MUXs, drivers, etc., by ON CHIP test logic. LBIST is asserted and control line C1 and its complement provided by invertor 15 are used to force data out to ABDATA and ABDATA lines. Node 9 connects to an N channel and P channel pair of FETs driven by the C1 line for outputting ABDATA line, while node 16 connects to a like N channel and P channel FET pair, which is driven by C1 line as well. Node 16 provides the output for ABDATA line. 
     At the beginning of a cycle, the LE and LEX lines are low and the EQ2 line is high. This action forces IN and IN lines, node 9 and node 16, and OUT and OUT lines to be precharged to VDD. As IN and IN lines are connected to the memory cells through the column decoder 16, when the word line goes high, the memory cells begin to drive the bit lines BL and BL. Both bit lines are precharged to VDD at the beginning of the cycle. As soon as the word line goes high, one of the bit lines goes low; this depends on the data stored in the memory cell such that the high side node of the memory cell keeps its bit line high and the low side node of the memory cell forces the bit line to begin discharging. The IN and IN lines follow the bit line and complement bit line, respectively, since they are connected together through the column decoder. As soon as the word line goes high, the signal EQ2 line then goes low, thereby releasing the IN and IN lines. 
     Just before there is a 250 millivolts differential voltage developed on IN and IN lines, the LEX line is forced high and then at the 250 millivolts differential level the SE line is forced high. When LEX goes high, the precharge circuit turns off and releases node 9 and 16 and lines OUT and OUT. When SE goes high, node 9 and 16, which were precharged to VDD, begin to develop differential voltage, which is shown in the graph in FIG. 4. As a small differential voltage develops on nodes 9 and 16, the control signal LE goes high, at approximately 300 picoseconds after the small differential voltage is developed. Once LE goes high, two paths to ground are formed. The first path is through transistor T9 and the second path is through T10. Depending upon the inputs, either node 9 or node 16 is pulled low very fast, while the others stay high, which is shown in the graph in FIG. 4. This action forces the OUT and OUT lines to follow node 16 and node 9, respectively. This results in OUT and OUT lines driving other circuits whose total capacitance is about 1 picofarad. 
     After a given time, about 1.1 nanoseconds, SE is turned off (FIG. 4), or goes low, and EQ2 goes high. When SE goes low, it turns off T7. The EQ2 signal then precharges the IN and IN lines to VDD. The control signals LE and LEX are still high and the latch is activated to drive both OUT and OUT signals. At this time, the latch is driving the data and the input of the sense amplifier is precharged to VDD. 
     After approximately 900 picoseconds (which varies with the clock cycle), first the LE and then the LEX signals go low. LE and LEX are forced low by the CLUG going low to high. Once the CLUG goes low, approximately 900 picoseconds later, LE and LEX will go low. When LE goes low, the latch is turned off and is ready to receive new data. When LEX goes low, it precharges node 9 and 16 and also OUT and OUT signals to VDD. The sense amplifier is now in a condition to receive new data. The 250 millivolt difference on the inputs of sense amplifier 18 requires about 610 picoseconds, while another 300 picoseconds passes before the sense amplifier develops 1.7 volts differential voltage on nodes 9 and 16. These results were based on a simulation of the sense amplifier 18 using a circuit simulator. 
     In the testing mode, the LBIST signal is controlled by a coprocessor on chip (COP). In the functional mode, the LBIST stays low. When the COP tests the comparators, MUXs, and drivers, the COP forces the LBIST to go high. This then forces the LE and SE signals to be low. LEX then goes high. This action then disables sense amplifier 18 and allows nodes 9 and 16 to float. C1 line then goes high, and COP forces the test data to node 9 and 16 through ABDATA and ABDATA lines, respectively. The signal OUT and OUT will then follow nodes 16 and 9, respectively. This sends the data to the comparators, MUXs, and drivers from the COP for testing. The advantages for the design for sense amplifier 18 is that it acts as both a differential sense amplifier and as a dynamic sense amplifier. During initial power up, sense amplifier 18 turns on slowly and then after about 300 pico seconds, it turns on harder. This allows sense amplifier 18 to recover from any noise or transient at the input of amplifier at the beginning of the cycle, since the gain is very low. This allows sense amplifier 18 to work as a differential sense amplifier. 
     Once LE goes high, 300 pico seconds after SE goes high, by this time, there is enough differential voltage developed on node 9 and node 16, sense amplifier 18 is turned on hard and pulls either node 9 or node 16 low very quickly. LE line engages the latch portion of sense amplifier 18, which allows it to work like a dynamic sense amplifier. The dynamic amplifier allows the gain to be infinite when the LE signal goes high, after the SE signal is high. Once the SE signal goes low, the latch is used to retain the data and keep driving the outputs. At this time, the inputs of sense amplifier 18 and the bit lines are precharged to VDD in preparation for the second cycle without losing any performance. This allows sense amplifier 18 to eliminate the additional latches that were previously required in the prior art sense amplifier of FIG. 2. 
     Another advantage of sense amplifier 18 is that it has low power dissipation since the inputs are not allowed to pull all the way to ground as in a typical dynamic sense amplifier. This is because the inputs sit at approximately VDD and 300 millivolts. At this time, the word lines are turned off and the bit lines and the input of sense amplifier are equalized to VDD. This further aids in reducing power dissipation as compared to a standard dynamic sense amplifier. 
     Also, since sense amplifier 18 has its own drivers, the ON CHIP tests of the comparator, MUXs and drivers, is able to use the sense amplifier drivers, rather than add additional circuits as in other prior art designs. This is accomplished by merely turning off the sense amplifier portion while allowing the data to be driven by the sense amplifier drivers. 
     Yet another benefit in the design used for sense amplifier 18 is that the input capacitance on the input signal has been greatly reduced. This is accomplished by the amplifier presenting a 20 picofarad load by the 10 micron gate as its only load on the input signal, as compared to a capacitive load of 135 picofarad in the prior art circuit of FIG. 2. This allows for a large differential voltage to be developed on the input of sense amplifier 18 before the SE signal goes high. This also allows for a faster operation by sense amplifier 18. 
     While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.