Power-on reset circuit and method
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to electronic circuits used to generate a power-on reset signal and more specifically to an electronic circuit used to generate a power-on reset signal with adjustable hysteresis. 
     2. Description of the Relevant Art 
     The problem addressed by this invention is encountered by systems which depend on a good voltage source for the reliable operation of the system. Common examples of such systems are a microprocessor based system such as a personal computer, an automobile, or a radio. In fact, most consumer and non-consumer products which use electronics have a way to enable the operation of the electronics, such as a power-on reset circuit, when a reliable power source is available and disabling the operation of the electronics when the reliable power source is not available. 
     In a personal computer, a power supply converts alternating current voltage into a direct current voltage, typically 5 volts. When the computer is turned on, the power supply may take hundreds of milliseconds to reach a stabilized voltage of around 5 volts. However, the microprocessor in the personal computer can operate unreliably at voltages below 4.5 volts. Since the microprocessor is capable of operating thousands of instructions in a single millisecond and can run unreliably at voltages below 4.5 volts, running the microprocessor at voltages below 4.5 volts could yield disastrous results. Data could be corrupted or lost. Erroneous messages or command signals could be sent. The possibilities for disaster are endless. Consequently, system designers typically disable the microprocessor until the power supply has reached a sufficient and stable voltage for the microprocessor to operate reliably. By disabling the microprocessor with a power-on reset circuit until the power supply provides a known good voltage, errors in the microprocessor due to low voltage and/or noise are avoided. 
     FIG. 1 shows a typical power-on reset circuit 12 as known in the prior art. In this circuit, Vcc voltage 2 represents the voltage from a power supply which is not shown and POR 10 represents the power-on reset signal which is generated by a Schmitt trigger 8. Before the power supply is turned on, the POR 10 is low since capacitor 6 is discharged and since the Schmitt trigger 8 does not have any source of power (since it is also powered by the power supply). When the power supply is turned on, the Vcc voltage 2 rises and begins to charge capacitor 6 through resistor 4 and power the Schmitt trigger 8. Until the Schmitt trigger 8 has sufficient voltage to operate, its output is in an indeterminate state. When the voltage on capacitor 6 reaches the threshold voltage of the Schmitt trigger 8, the output of the Schmitt trigger changes to a high state and thus the POR signal 10 swings to a high state. 
     Prior art power-on reset circuit 12 in FIG. 1 is limited to situations where Vcc has a rise time at turn-on that is much faster than the RC time constant. As a result, large resistors and capacitors are required for those power supplies which have long rise times. The large capacitors can use a significant amount of area on an integrated circuit. Additionally, the POR output is indeterminate at VCC voltages below the operating voltage of the Schmitt trigger 8. 
     FIG. 2 shows a second power-on reset circuit 28 as known in the prior art. In this circuit, Vcc voltage 14 represents the voltage from a power supply and POR signal 27 represents the power-on reset signal which is generated by the comparator 26. In operation, POR signal 27 is initially at a low voltage as Vcc voltage begins to rise from a power supply off condition. The voltage at the non-inverted input of comparator 26 is controlled by the voltage divider created by resistor 22 and resistor 24. The voltage at the inverted input of comparator 26 is controlled by the voltage divider created by resistor 16 and diodes 18 and 20. As Vcc 14 rises, the non-inverted input rises proportional to Vcc 14 as defined by the resistance of resistor 22 and 24. The inverted input rises in voltage with the Vcc voltage 14 until Vcc 14 reaches the threshold voltage of diodes 18 and 20, typically 0.7 volts each. POR 27 goes high when: 
     
         (Vcc *r.sub.24)/r.sub.22 +r.sub.24 &gt;V.sub.18 +V.sub.20 
    
     Where 
     Vcc is the voltage of Vcc 14, 
     r 22  is the resistance of resistor 22, 
     r 24  is the resistance of resistor 24, 
     V 18  is the forward voltage drop of diode 18, 
     V 20  is the forward voltage drop of diode 20. 
     The problem with this prior art circuit is that signal POR 27 is indeterminate when the Vcc voltage 14 is below the operating voltage of the comparator 26. Additionally, the circuit does not have any hysteresis or is limited to the hysteresis of comparator 26 which is not easily modified. Additionally, the component count is high when the components which are required to make a comparator are included. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the invention to provide a power-on reset circuit which has no dependence on Vcc rise times. 
     It is further an object of this invention to have a determinate output at low Vcc voltages. 
     It is further an object of the invention to have programmable hysteresis. 
     It is further an object of the invention to have a simple power-on reset circuit with a low component count and therefore high reliability. 
     It is further an object of the invention to minimize the area required to implement the circuit on an integrated circuit. 
     These and other objects, features, and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read with the drawings appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a power-on reset circuit using a resistor, capacitor, and schmitt trigger as known in the prior art. 
     FIG. 2 is a power-on reset circuit using voltage dividers and a comparator as known in the prior art. 
     FIG. 3 is the power-on reset circuit in accordance with the preferred embodiment of the invention. 
     FIG. 4 is a graphical representation of the current flowing through two transistors as a function of the Vcc voltage. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A power-on reset circuit 30 constructed according to the preferred embodiment of the invention will be described relative to FIG. 3. The power-on reset circuit 30 includes three circuits: a low voltage stage, a high voltage stage, and a hysteresis circuit. The low voltage stage includes resistor 44, NPN transistor 46, and NPN transistor 50. The high voltage stage includes PNP transistors 34 and 48, diode 36, resistor 38 and resistor 42. The hysteresis stage includes n-channel transistor 40. 
     More specifically, FIG. 3 shows a Vcc voltage 32 connected to an emitter of a PNP bipolar transistor 34, an emitter of a PNP bipolar transistor 48, and a first end of a resistor 44. The base of transistor 34 is connected to its collector, to an anode of a diode 36, and to the base of transistor 48. The cathode of diode 36 is connected to a first end of resistor 38. A second end of resistor 38 is connected to a drain of an n-channel transistor 40 and a first end of resistor 42. The source of transistor 40 and a second end of resistor 42 are connected to voltage reference, ground. The second end of resistor 44 is connected to a collector of a NPN bipolar transistor 46. The emitter of transistor 46 is connected to ground. The Collector of transistor 48 is connected to a collector of a NPN bipolar transistor 50 and to a gate of transistor 40, and drives node 52 to provide the output of the power-on reset circuit 30. The base of transistor 50 is connected to the base and collector of transistor 46 and to the second end of resistor 44. The emitter of transistor 50 is connected to ground. 
     In operation, transistor 46 turns on when Vcc rises above the V be  voltage of transistor 46, typically 0.7 volts. Since the base of transistor 46 is coupled to the base transistor 50, transistor 50 mirrors the current in transistor 46 and thus sinks current from node 52 and holds the POR signal low. Consequently, this circuit is advantageous over the prior art since the POR signal 52 is not indeterminate at Vcc voltages greater than around 0.7 volts. 
     As Vcc continues to rise, Vcc reaches a voltage sufficient to turn on transistor 34 and diode 36, typically around 1.4 volts. Since the base of transistor 34 is connected to the base of transistor 48, current begins to flow through transistor 48 and into node 52. The POR will signal stay low until the current in transistor 48 is equal to the current in transistor 50. At that point, the POR signal will quickly switch to a high state which will turn on transistor 40. With transistor 40 on, resistor 42 is bypassed which allows even more current to flow through transistor 34 and 48 which creates hysteresis in the circuit. 
     In the preferred embodiment, resistor 38 has a resistance of 25K ohms, resistor 42 has a resistance of 4K ohms, and resistor 44 has a resistance of 43K ohms. With these resistor values, the current through the collectors of transistors 48 and 50 are shown in FIG. 4 as a function of the Vcc voltage. More specifically, the graph in FIG. 4 shows the current in transistor 50 beginning to flow when Vcc is about 0.7 volts. The current in transistor 48 begins to flow when the Vcc voltage reaches 1.4 volts. The current through transistor 48 equals the current through transistor 50 when Vcc is around 3.5 volts. 
     In equation form, the circuit changes states when: 
     
         (Vcc-V.sub.be46)/R.sub.44= (Vcc-V.sub.be34 V.sub.be36)/(R.sub.38 +R.sub.42) 
    
     where 
     V be46  is the base to emitter voltage threshold for transistor 46, 
     V be34  is the base to emitter voltage threshold for transistor 34, 
     V be36  is the base to emitter voltage threshold for transistor 36 
     R 38 , R 42 , and R 44  are the resistance of resistors 38, 42, and 44, respectively. 
     The equation can be rewritten as: 
     
         Vcc (at the transition)=[V.sub.be46 (R.sub.38 +R.sub.42)-R.sub.44 (V.sub.be34 +V.sub.be36)]/(R.sub.38 +R.sub.42 -R.sub.44) 
    
     Additionally, for V be34  =V be36  =V be46  =V be   
     
         VCC (at the transition)=V.sub.be [(R.sub.38 +R.sub.42 -2R.sub.44)/(R.sub.38 +R.sub.42 -R.sub.44)] 
    
     As explained above, the circuit has hysteresis since transistor 40 is turned on when the POR signal goes high. With transistor 40 on resistor 42 is bypassed which effectively increase the current through transistor 34 and 48. Consequently, Vcc will have to drop to a lower threshold voltage for the POR signal to change state than when Vcc was rising. The hysteresis of this circuit is described by the following equation: 
     
         V.sub.hys =Vbe[(R.sub.38 +R.sub.42 -2.sub.44)/(R.sub.38 +R.sub.42 -R.sub.44)-(R.sub.38 -2R.sub.44)/(R.sub.38 -R.sub.44)] 
    
     A designer skilled in the art can select resistor values to provide a hysteresis voltages which matches his application. 
     This preferred embodiment provides a power-on reset circuit which has no dependence on Vcc rise times and has a determinate output at the low Vcc voltage of 0.7 volts. Additionally, the hysteresis of the circuit is easily programmed by selecting resistor values, as described above. The preferred embodiment also offers the advantages of being a simple power-on reset circuit with a low component count and therefore high reliability. Also, the invention use a minimum area on an integrated circuit since the component count is low and no large capacitors are required. 
     Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.