Analog to digital converter circuit
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an analog/digital converter circuit (hereinafter abbreviated as an A/D converter circuit) for converting an analog signal to a digital signal, and more particularly the present invention relates to a serial/parallel type A/D converter circuit for converting an analog signal to a digital signal with two stages that form an upper data part and a lower data part. 
     2. Description of the Related Art 
     Various types of analog-to-digital conversion systems have been proposed, in one such system known as a parallel-type (flash-type) A/D converter the circuit quantizes the amplitude of the analog signal and converts the quantized signal to a digital code. 
     In such a parallel-type A/D converter circuit, high speed operation is possible, however when the number of the conversion bits is n, at least (2 n  -1) comparators are necessary for implementation of the circuit. A total of 255 comparators are necessary to obtain an 8-bit conversion code, and it is necessary to form several tens of thousands active elements by integration into a circuit in order to obtain a digital code having higher resolution. 
     For this reason, a parallel-type A/D converter circuit has the advantage that high speed processing is possible, but it is undesirable due to increases in which is required power consumption and the large surface area for the chip. 
     Therefore, a so-called serial/parallel type A/D converter circuit has been proposed in which, for conversion of the analog signal to n bits of resolution. In this circuit first the analog signal is digitized by rough quantization, so that an &#34;a&#34; bit conversion code including the most significant bit (MSB) is obtained, and in order to reduce the error of this upper data conversion code, that is, the quantization noise, the upper data quantization range is finely divided and digitized, so that the lower data [b (n-a)] bit conversion code including the lower significant bit (LSB) is obtained. 
     FIG. 1 is a structural view showing an outline of one such serial/parallel type A/D converter circuit which illustrates the circuit configuration for converting an analog signal to a 4-bit digital code. 
     In FIG. 1, R 1  to R 16  denote reference resistance elements serially connected between terminals of reference voltages V RT  to V RB  (0 to -2 V); C u1  to C u3  denote upper data comparators which have one input terminal connected to an input line of an input analog signal V IN  to be converted and the other input terminal connected to the input line of the reference voltages (V 4 , V 8 , V 12 ) of the rough quantization level divided by reference resistance elements R 1  to R 16  ; B u1  to B u3  denote buffers for obtaining the complementary outputs of the outputs of upper data comparators C u1  to C u3  ; A u1  to A u4  denote AND gates; S a1  to S a12  denote switching blocks arranged in the form of a matrix comprising four rows and three columns; C d1  to C d3  denote lower data comparators with one input terminal connected to the input line of the analog signal V IN  and the other side input terminal connected to the output terminals of the switching blocks S a1  to S a12  ; E u1  denotes an upper data encoder which encodes the result of differentiation of binary signals output from the upper data comparators C u1  to C u3  and converts the same to for example a 2-bit binary code (or complementary code of 2); and E d1  denotes a lower data encoder which converts the result of differentiation of the binary signals output from the lower data comparators C d1  to C d3  to a 2-bit binary code; respectively. 
     The switching blocks S a1  to S a12  are controlled to turn on or off in accordance with the data &#34;1&#34; and &#34;0&#34; of the output level of the AND gates A u1  to A u4 . 
     For example, when a signal of the &#34;1&#34; level is output from the AND gate A u1 , control is performed so that the switching blocks S a1  to S a3  become an ON state; when the signal of the &#34;1&#34; level is output from the AND gate A u2 , control is performed so that the switching blocks S a4  to S a6  become an ON state; when the signal of the &#34;1&#34; level is output from the AND gate A u3 , control is performed so that the switching blocks S a7  to S a9  become an ON state; and when the signal of the &#34;1&#34; level is output from the AND gate A u4 , control is performed so that the switching blocks S a10  to S a12  become an ON state; 
     In the serial/parallel type A/D converter circuit having such a structure, as shown in for example FIG. 2, the input analog signal V IN  is sampled at the using point of the sampling pulse P S , and the sampling voltage V S  thereof is supplied to the upper data encoder E u1  and the lower data encoder E d1 . 
     At the upper data encoder E u1 , when the sampling voltage V S  is supplied, the binary signal outputs of the upper data comparators C u1  to C u3  are converted to the code signals D 0  and D 1  of the upper significant 2 bits at the point of time T H  of trailing edge (point of time lagged by τ A ) of the clock signal CLK and output. 
     At the lower data encoder E d1 , when the sampling voltage V S  is supplied, the binary signal outputs of the lower data comparators C d1  to C d3  are converted to the code signals D 2  and D 3  of the lower significant 2 bits at the point of time T L  of trailing (point of time lagged by τ B ) of the clock signal CLK, 
     Explaining this more concretely, reference voltages V 4 , V 8 , and V 12  of the rough quantization level, divided by the reference resistance elements R 1  to R 16  and the input analog signal V IN  are compared by the upper data comparators C u1  to C u3 . 
     As a result of this comparison, for example, when V 4  &lt;V IN  &lt;V 8 , the output of the upper data comparator C u3  becomes the high level at a high potential (&#34;1&#34;), and the outputs of the upper data comparators C u2  and C u3  become the low level at a low potential (&#34;0&#34;). 
     Thus, at the output of the AND gates A u1  to A u4 , only the output of the AND gate A u2  becomes &#34;1&#34;, and the outputs of the other AND gates A u1 , A u3 , and A u4  become &#34;0&#34;. 
     As a result, the code [01] is output as the upper significant 2 bits of the conversion code from the upper data encoder E u1 . 
     Next, in a state where the upper significant 2 bits of the conversion code are latched, the signal of the &#34;1&#34; level output from the AND gate A u2  is input to the switching blocks S a4  to S a6 . By this, the switching blocks S a4  to S a6  become an ON state. 
     Along with the switching blocks S a4  to S a6  becoming the ON state, the sampled analog signal V IN  existing at the level represented as V 4  &lt;V IN  &lt;V 8  is further divided by the resistance elements R 4  to R 6 , and regulated reference voltages V 5 , V 6 , and V 7  are input via the switching blocks S a4 , S a5 , and S a6  to the other input terminals of the lower data comparators C d3 , C d2 , and C d1 , respectively. 
     In the lower data comparators C d3 , C d2 , and C d1 , the input reference voltages V 5 , V 6 , and V 7  are compared with the analog signal V IN  which is input to the one side input terminals of the same and the result of comparison is output to the lower data encoder E d1 . 
     As a result of this comparison, when for example V 6  &lt;V IN  &lt;V 7 , the lower significant 2 bits of the conversion code [10] are output from the lower data encoder E d1 . 
     As a result of the above, a 4-bit conversion code [0110] of the analog signal V IN  will be output from the upper data and lower data encoders E u1  and E u2 . 
     This serial/parallel type A/D converter circuit outputs the conversion code while dividing the same to upper significant and lower significant 2 bits and therefore can reduce the number of comparators required when performing the A/D conversion of 4 bits to 6. 
     Also, when for example A/D conversion of 8 bits is to be carried out, as mentioned above, in the parallel type A/D converter circuit, 255 comparators are necessary, but this serial/parallel type A/D converter circuit has an advantage in that only (2 4  -1)×2=30 comparators are sufficient to provide four upper significant bits and lower significant bits, respectively. 
     However, since the code conversion is carried out by two stages, during this time, it is necessary to provide a sample and hold circuit so that the input signal voltage is not changed, but is held at a fixed value, consequently leading to inducing complication of the circuit control etc. 
     In the above-mentioned A/D converter circuit, when increased resolution thereof is desired, a large number of taps from a voltage-division resistance element group becomes necessary, and finer processing of the semiconductor material becomes necessary. The reference voltage value of adjoining comparators becomes smaller if miniaturization is further increased, whereby a so-called offset voltage of the comparator becomes equivalent to the difference, thereby producing problems such as the loss of the comparator characteristics. 
     Therefore, as a means solving this problem and improving the resolution, a comparator circuit adopting a so-called interpolation construction has been proposed. 
     FIG. 3 is a schematic circuit diagram showing a conventional comparator circuit adopting this interpolation construction. In FIG. 3, comparators 24 and 25 denote complementary output type comparators; v in  denotes an input analog signal; and v r1 , v r2  (v r1  &lt;v r2 ) denote reference voltages; respectively. 
     In this comparator circuit, an imaginary voltage at an intermediate point between two reference voltages v r1  and v r2  is obtained from the positive output of the comparator 24 and the negative output of the comparator 25, and the result of comparison of this imaginary voltage with the input analog signal v in  is successively obtained. 
     This structure has an advantage in that the error resulting from of, for example, the processing precision can be easily absorbed in comparison with a case where a large number of independent taps are adopted as mentioned above. This design however, can merely perform an equal weight between two reference voltages v r1  and v r2 , and only can obtain an excessive result of comparison with the voltage at an intermediate point between two reference voltages. This design cannot freely obtain an imaginary voltage or a plurality of imaginary voltages. 
     Accordingly, there are problems in that the resolution of the above-mentioned conventional A/D converter circuit can be raised to only twice its level and improvement exceeding this is difficult, and furthermore, the application range is restricted. 
     A detailed description will be further made particularly of another design in the related art, which is a modification of the lower data encoder. 
     FIGS. 4A and 4B illustrate a circuit diagram showing an example of the structure of a conventional A/D converter circuit and shows a circuit structure for converting an analog signal V IN  to a 4-bit digital code. 
     In FIG. 4A, reference numeral 30 denotes a matrix circuit; 61 to 60 denote upper data comparators; 63 denotes an upper data encoder; 31 to 37 denote lower data comparators; 40 denotes a lower data encoder; 64 an inverted gate; 65 an inhibit gate; 66 a selection gate; and 67 an inverter; respectively. 
     The matrix circuit 30 is comprised of 28 switching blocks S b11  to S b17 , S 21  to S b27 , S b31  to S b37 , and S b41  to S b47  arranged in the form of a matrix comprising 4 rows and 7 columns. 
     The switching blocks S b11  to S b17 , S b21  to S b27 , S b31  to S b37  and S b41  to S b47  are comprised of differential-type amplifiers comprising npn-type transistors Q 1 , Q 2 , and Q 3 . 
     Except for parts, reference voltages obtained by dividing the reference voltages V RT  -V RB  by the reference resistance elements R 31  to R 46  are supplied to the base of one transistor Q 1  constituting a so-called differential pair, and the analog signal V IN  to be converted to the digital code is supplied to the base of the other transistor Q 2 , respectively. 
     Also, emitters of the transistors Q 1  and Q 2  are connected to each other, and the middle point of connection thereof is connected to the current source I via the transistor Q 3  which is switched by the control signal mentioned later. 
     Also, a power source voltage V DD  is supplied to the collectors of the transistors Q 1  and Q 2  via the resistor r. The output terminals thereof are connected to the inputs to the comparators C D1  to C D7  of seven lower data comparators 31 to 37, respectively. Joint use is made of the first stage amplifiers of the lower data comparators 31 to 47. 
     In the figure, switching blocks S b11 , S b12 , S b16 , S b17 , S b21 , S b22 , S b26 , S b27 , S b31 , S b32 , S b36 , S b37 , S b41 , S b42 , S b46 , and S b47  further output 2LSB redundant bits with respect to 2-bit lower data conversion code. Particularly, among them, S b11 , S b12 , S b41 , and S b42  are given fixed input signals so that a constant binary signal &#34;H&#34; or &#34;L&#34; is output when activation is made by the control signal. 
     Also, particularly, a system is devised so that the collectors of the transistors Q 1  and Q 2  at the second row and fourth row of the switching block are connected to the line in an opposite direction to the collector outputs of the transistors Q 1  and Q 2  at the first row and the third row of the switching block, whereby the lines of the serially connected reference resistance elements R 1  to R 16  applied with the reference potentials (voltages) V RT  -V RB  can be formed by folding-back. 
     Each of the three upper data comparators 61, 62, and 63 is provided with the comparators C U5  to C U7 , complementary-type output amplifiers CA, and AND gates A u5  to A u8 , respectively. 
     An analog signal V IN  is supplied to one side inputs of the respective comparators C U  of the upper data comparators 61 to 63, and reference voltages V 1 , V 2 , and V 3  obtained by dividing the reference potentials V RT  to V RB  by the rough quantization are supplied to the other side inputs. 
     The outputs of the respective comparators C U  of the upper data comparators 61 to 63 become the level of &#34;H&#34; or &#34;L&#34; corresponding to the level of the sampled analog signal and are set so that only one of the respective AND gates A U  outputs the &#34;1&#34; level. 
     The output signals of the respective AND gates A U  are wired-connected and converted to a binary code via the upper data encoder 60. In the selection gate 66 mentioned later, correction is applied to the upper significant two bits of the codes D 1  and D 2 . 
     Also the lower data comparators 31 to 37 are formed in the same way as the upper data comparators 61 to 63. Particularly, the lower data comparators 33, 34, and 35 further finely digitize the inside of the quantization level selected by the upper data comparator and output the lower significant 2 bits of the codes D 3  and D 4  via the lower data encoder 40. 
     Further, this A/D converter circuit is designed so that comparators 31, 32, 36, and 37 produce the redundant code of 2LSB which are provided on the left and right of this lower data comparator, and the code conversion operation is carried out also for the analog signal V IN  out of the conversion range of the lower data comparator, specified by the upper data comparators 61 to 63. 
     In such a structure, for example when the sampling voltage V S  of the sampled analog signal is represented as V RB  &lt;V S  &lt;V 3 , the outputs of comparators C U  of the upper data comparators 61, 62, and 63 become all &#34;L&#34;, so that the binary signal output, is &#34;0&#34; which output from the AND gates A u5  to A u7 , and &#34;1&#34; is output from A u8 , respectively. 
     As a result, a binary signal [0001] is input to the upper data encoder 63, and by a so-called wired-OR circuit, [00] is output to the first two lines [LN 5  ]; [00] is output also to the next two lines [LN 6  ], and [01] is output to the next two lines [LN 7  ]. 
     When the sampling voltage V S  is represented as V 3  &lt;V S  &lt;V 2 , similarly the binary signal of &#34;0&#34; is output from the upper data side AND gates A U5 , A U6 , and A U8 , and the binary signal &#34;1&#34; is output from the gate A U7 , respectively. 
     As a result, a binary signal such as [0010] is input to the upper data encoder 63, so that [00] is output from the line [LN 5  ]; [01] is output from the line [LN 6  ]; and [10] is output from the line [LN 7  ]. 
     Below, the relationship between the input and output of the upper data encoder 60 including the case where V 2  &lt;V S  &lt;V 1  and V 1  &lt;V S  &lt;V RT  is as shown in FIG. 5. 
     In parallel to this, the transistors Q 3  of the respective switching blocks connected to the control lines (x 5 , x 6 , x 7 , and x 8 ) at which the binary output signal has become &#34;1&#34;, among the respective AND gates A U (5, 6, 7, 8), is set to ON, and further the fine digitization of the quantization level is executed. 
     For example, when only the output of the AND gate A U7  becomes a &#34;1&#34; level, the transistors Q 3  of the switching blocks S b31  to S b37  turn ON, so that the reference voltage divided by the reference resistance elements R 37  to R 43  and the sampling voltage V S  are differentially amplified at the switching blocks S b31  to S b37  and compared by the lower data comparators 31 to 37. 
     Similarly, the switching blocks S b21  to S b27  are activated when the output of the AND gate A U6  is at the &#34;1&#34; level, a differential amplification operation is carried out, and the comparison by the lower data comparators 31 to 37 is carried out. 
     In this way, in the lower data code, the sampled voltage V S  and the reference voltage divided by the reference resistance element of that row are compared in units of rows of the switching block, the binary signals are output from the AND gates A D1  to A D7  and A D8  of the lower data comparators 31 to 37 as shown in FIG. 6, and these binary signals are encoded at the lower data encoder 40, whereby the lower significant 2 bits of the conversion codes D 3  and D 4  are output from the lower data code line [LN 1  ]. 
     Moreover, the output levels of the selection lines LN 2 , LN 3 , and LN 4  are changed as shown in FIG. 6. 
     Then, as indicated below by a, b, and c, when a signal of the &#34;1&#34; level is output to either of these selection lines LN 2 , LN 3 , and LN 4 , the upper significant 2 bits of the conversion codes D 1  and D 2  from the lines LN 5 , LN 6 , and LN 7  in the upper data encoder 30 are selectively output via the OR gates OR 1  and OR 2 . 
     (a) When the conversion code with which &#34;1&#34; is produced in the selection line LN 3  (0 line), that is, the lower significant 2 bits of the conversion codes D 3  and D 4  become [00], [10], and [11] corresponding to the upper data conversion codes, the outputs of the AND gates A 1  and A 2  constituting the inhibit gate 65 become &#34;0&#34;, and therefore the outputs of the AND gates A 1 , A 3 , A 4 , and A 6  existing inside the selection gate 66 become &#34;0&#34;. 
     As a result, the upper data D 1  and D 2  codes of the line [LN 6  ] output from the upper data encoder 63 are output as they are via the AND gates A 2  and A 5  of the selection gate 66 and the OR gates OR 1  and OR 2 . 
     This case of (a) indicates a case where the level of the analog signal when performing the conversion of the upper significant 2 bits is not changed from the analog signal when performing the conversion of the lower significant 2 bits, and the correction is not carried out. 
     (b) Where the selection line LN 2  is &#34;1&#34; and the AND gate A U5  or A U7  is &#34;1&#34;, and where the selection line LN 4  is &#34;1&#34; and the AND gate A U8  or A U6  is &#34;1&#34;, the AND gate A 1  constituting the inhibit gate 65 is opened. As a result, the upper significant 2 bits of the codes D 1  and D 2  of the line LN 5  input to the AND gates A 1  and A 4  are output via the OR gates OR 1  and OR 2 . 
     This case of (b) performs the correction where the level of the analog signal when digitizing the upper significant 2 bits D 1  and D 2  is higher than the analog signal when digitizing the lower significant 2 bits D 3  and D 4 . 
     For example, as shown in FIG. 7, when the truth value of the sampling value V S  of the analog signal is V A , and when the conversion code of the upper significant 2 bits is erroneously output at [10] and output at a correct lower significant 2 bits of the conversion code [11] from the lower data comparator, &#34;1&#34; is subtracted from the upper significant 2 bits of the conversion code [10], and corrected to [01], thereby obtaining a correct code output [0111]. 
     Namely, this case means that the control line erroneously selects the line of the switching block, but since the lower data comparator 46 on the right side detecting the redundant bit outputs [00], the upper significant 2 bits of the conversion code will be corrected. 
     (c) Where the selection line LN 4  is &#34;1&#34; and the AND gate A U5  or A U7  is &#34;1&#34;, and where the selection line LN 2  is &#34;1&#34; and the AND gate A U8  or A U6  is &#34;1&#34;, the output of the AND gate A 2  constituting the inhibit gate 65 becomes &#34;1&#34;, and the AND gates A 3  and A 6  of the selection gate 66 are opened. 
     As a result, the upper significant 2 bits of the codes D 1  and D 2  of the line LN 7  input to these AND gates A 3  and A 6  are output via the OR gates OR 1  and OR 2 , and &#34;+1&#34; is added to the upper significant 2 bits of the codes. 
     Namely, in this case of (c), where the sampling level of the analog signal when digitizing the upper significant 2 bits of D 1  and D 2  is lower than the quantization level range at that time, a correction is applied. 
     For example, when the truth value of the analog signal V IN  exists at the point of V B , when the upper significant 2 bits become [00], if the numerical value of the lower significant 2 bits is output as [00], &#34;+1&#34; is added to the upper significant 2 bits [00], to obtain [01], and the [0100] corresponding to the sampling voltage  VB  of the correct analog signal is output. 
     This A/D converter circuit adds a comparator for detecting the redundant bit to the lower data comparator as described above, outputs, when the lower data conversion code out of the range of the upper data conversion code (region indicated by a hatching in FIG. 7), a signal of the &#34;1&#34; level to the selection line LN 2  or LN 4 , and performs the correction of the upper data conversion code, and therefore has an advantage that a correct conversion code detected at the point of time of lower data can be obtained by high speed sampling even when the settling characteristic of the sampling circuit is poor. 
     As mentioned above, in the conventional circuit, for correcting the upper data code, a correction is carried out based on the concept of adding &#34;1&#34; and subtracting &#34;1&#34;. 
     For this reason, it is constituted so that, in the upper data, normal data and lower redundant data (data obtained by subtracting &#34;1&#34; from the normal data) and the upper redundant data (data obtained by adding &#34;1&#34; to the normal data) are settled into respective groups, and one is selected from among the three groups by a selection signal from the lower data encoder. 
     Nevertheless, there alternately exists a column in which the right part of the resistance column becomes the lower redundancy and a column in which it becomes the upper redundancy. Accordingly, there is a case where the lower data encoder connected to the right part of the resistance column selects the lower redundant data and a case where it selects the upper redundant data. 
     Accordingly, the data to be selected differs for each column, and therefore the inverted gate 64 and inhibit gate 65 were necessary for controlling this. 
     However, the selection signal from the lower data encoder 50 (LN 2 , LN 3 , and LN 4  in the diagram) passes through the inverted gate 64 and the inhibit gate 65, and then is transferred to the selection gate 66, and therefore the selection signal is input to the selection gate 66 with a time lag relative to the upper data output from the upper data encoder 63. 
     For this reason, a delay due to the existence of the inverted gate 64 and the inhibit gate 65 occurs in the output processing of the conversion code, consequently leading to a problem that the conversion time of the A/D converter circuit is increased. 
     Moreover, there also exists a problem in that increases of the chip area and power consumption are induced since an excessive quantity of inverted gates and inhibit gates become necessary. 
     Further, there also exists another problem in that, in addition to the necessity of an excessive quantity of inverted gates and inhibit gates, three selection signals become necessary, and three sets of upper data codes to be selected become necessary too, and also the number of input gates in the selection gate is increased, and therefore resulting in increases of the chip area and power consumption. 
     Further, so as to obtain the upper significant &#34;a&#34; bits, (2 a  -1) upper data comparators are necessary, and 2 a  rows become necessary too also for a row of the switching block. This is one of the causes of an increase of the chip area and the power consumption. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an A/D converter circuit which provides greatly improved resolution. 
     Another object of the present invention is to provide an A/D converter circuit in which prevents an increase of the power consumption and chip area, but also one in which it is not necessary to provide a sampling and holding circuit, and thus the complication of the circuit control etc. can be prevented. 
     Still another object of the present invention is to provide an A/D converter circuit with which the increase of speed of the conversion processing, reduction of the surface area of the chip, and reduction of the power consumption can be achieved. 
     According to the present invention, there is provided an analog/digital converter circuit including: a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by an upper data conversion output signal in units of rows, comparing the respective reference voltages divided by the reference resistance elements with an input signal to be converted, and detecting the presence/absence of lower significant bit data and redundant bit data, thereby providing a differential output; an upper data encoder comparing the reference voltage supplied to a switching block positioned at a specific position of the switching block matrix with the input signal to be converted, and providing a plurality of conversion codes of the upper significant bits in accordance with the result of this comparison; a lower data comparator circuit including first and second comparators with weights of outputs set to N and which provides the complementary output; a third comparator with a weight of output set to n 1  and which provides the complementary output; a fourth comparator with a weight of output set to n 2  (note, n 1  +n 2  =N) and which provides the complementary output; a first adder which adds one output of said third comparator and one output of said fourth comparator; and a second adder which adds the other output of third comparator and the other output of fourth comparator, wherein a differential output of one row of the switching block being connected to the inputs of the first comparator and third comparator, and the differential output of the other row of the switching block being connected to the inputs of the second comparator and said fourth comparator; a lower data encoder, providing a predetermined lower data conversion code for the complementary outputs of the respective comparators of the lower data comparator in accordance with the presence/absence of the lower significant bit data and redundant bit data, and generating a selection signal for selecting one conversion code from among the conversion codes of the upper significant bits of the upper data encoder; and a selection gate selectively outputting one conversion code from among a plurality of conversion codes of the upper significant bits output from the upper data encoder based on the selection signal output from the lower data encoder. 
     Preferably, the lower data comparator circuit may include a ring comparator comprising a plurality of comparator circuit, each including a first comparator or second comparator and a third comparator and fourth comparator corresponding to respective row of the switching blocks, inputs of the respective comparators being connected to the differential outputs of the switching blocks of the corresponding row and the outputs of the third and fourth comparators of each comparator circuit being connected to the output of the third comparator or fourth comparator of the other comparator circuit. Also, the lower data comparator circuit may include a suppression circuit which cuts a predetermined position of the ring comparator in accordance with the upper data conversion output signal, and suppresses the unnecessary input of the output of the comparator to the lower data comparator. 
     Specifically, the weights of outputs of third and fourth comparators are set as n 1  =n 2  =N/2. 
     Also, according to the present invention, there is provided an analog/digital converter circuit including: a plurality of switching blocks, arranged in the form of a matrix, comparing the respective reference voltages provided by dividing said reference potential by serially connected a plurality of (n) resistance elements with an input signal to be converted; an upper data comparator comparing the reference voltage applied to the specific position of switching block in the row direction with the input signal to be converted, thereby providing the conversion code of the upper significant bit; a determining circuit determining whether the number of the switching blocks obtaining a comparison result that the level of the input signal to be converted is larger than the reference voltage level is even or odd; and a lower data encoder providing the conversion code of a lower significant bit in accordance with the result of determination of the determining circuit. 
     Preferably, the respective switching blocks are constituted by differential type amplifiers, each having a pair of transistors the base of which being supplied with the input signal to be converted and the divided reference voltage; and the determining circuit is constituted in that the transistor output to which the input signal is supplied and the transistor output to which the reference voltage is supplied are alternately connected for each row and are connected to a load element. 
     Also, preferably, the determining circuit includes a means which performs the exclusive-OR of the adjoining switching blocks for each row and outputs the total sum thereof to the lower data encoder. The determining circuit may have a plurality of exclusive-OR gates performing the exclusive-OR of the outputs of the adjoining switching blocks and constituted so that the outputs of the respective exclusive-OR gates are connected. 
     Preferably, the plurality of n reference resistance elements are arranged in a plurality of rows by folding-back so that the direction of application of the reference voltage becomes reverse for each predetermined number of reference resistance elements. Also, provision is made of an inverted gate which inverts, when a direction of application of voltage of a predetermined row is used as a reference, the obtained lower significant data conversion code obtained based on the reference voltage by the reference resistance elements of the row in the direction of application which is reverse to the former and outputs the same. 
     According to the present invention, there is further provided an analog/digital converter circuit including: a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by an upper data conversion output signal for each row, comparing the respective reference voltages divided by said reference resistance elements with an input signal to be converted, and detecting the presence/absence of the lower significant bit data and redundant bit data for each predetermined row; an upper data encoder, comparing the reference voltage at a specific portion in the row direction of the switching block with the input signal to be converted, and providing the conversion code of the upper significant bit in accordance with a redundant mode or non-redundant mode which are set in advance in accordance with the result of this comparison; a lower data encoder, providing the conversion code of the lower significant bit and the conversion code of the redundant bit out of the conversion range specified by the upper data encoder from the outputs of the respective switching blocks in accordance with the presence/absence of the lower significant bit data and the redundant bit data, and generating a selection signal in accordance with the redundant mode or non-redundant mode in accordance with the presence/absence of the redundant bit data; and a selection gate selectively outputting the conversion code of the upper significant bit in accordance with the redundant mode or non-redundant mode from among the conversion codes of the upper significant bit in accordance with the redundant mode or non-redundant mode output from the upper data encoder based on the selection signal in accordance with the mode output from the lower data encoder. 
     According to the present invention, there is provided an analog/digital converter circuit including: a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by the upper data conversion output signal for each row, comparing the respective reference voltages divided by reference resistance elements with an input signal to be converted, and detecting the presence/absence of the lower significant bit data and redundant bit data; at least one data change point detection circuit comparing the reference voltage generated between mutually adjoining rows excluding at least the uppermost row or lowermost row of switching block matrix with the input signal to be converted, and detecting the change point of data; an upper data encoder providing the conversion code of the upper significant bit in accordance with 2 modes set in advance in accordance with the result of detection of the data change point detection circuit; a lower data encoder dividing the outputs of the respective switching blocks in units of rows into two groups in accordance with said 2 modes, providing the predetermined lower data conversion code in accordance with the presence/absence of the lower significant bit data and redundant bit data for each of the respective divided groups, and generating a selection signal for selecting one selection code from among the two upper significant bits of conversion codes of the upper data encoder; and a selection gate selectively outputting one conversion code selected from among two upper significant bits of conversion codes output from the upper data encoder based on the selection signal output from the lower data encoder. 
     According to the present invention, there is provided an analog/digital converter circuit including: a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by the upper data conversion output signal for each row, comparing the respective reference voltages divided by the reference resistance elements with an input signal to be converted, and detecting the presence/absence of the lower significant bit data and redundant bit data; an upper data encoder, comparing the reference voltage applied to the specific position of the switching block in the row direction with the input signal to be converted, and providing the two conversion codes of the upper significant bit excluding the predetermined bits among the upper significant bits in accordance with the 2 modes set in advance in accordance with the result of this comparison; a lower data encoder, dividing the outputs of said respective switching blocks in units of columns into two groups in accordance with said 2 modes, providing the predetermined lower data conversion code in accordance with the lower significant bit data and the presence/absence of the redundant bit data for each of divided groups, and generating the selection signal for selecting one conversion code from among 2 upper significant bits of conversion codes of the upper data encoder; and a selection gate selectively outputting one conversion code selected from among 2 upper significant bits of conversion codes output from said upper data encoder based on the selection signal output from the lower data encoder. The selection signal is output as the predetermined bit of the upper significant conversion code excluded at the upper data encoder. 
     According to the present invention, there is provided an analog/digital converter circuit including: a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by the upper data conversion output signal for each row, comparing the respective reference voltages the by the reference resistance elements with an input signal to be converted, and detecting the presence/absence of the lower significant bit data and redundant bit data; an upper data encoder, comparing the reference voltage applied to the specific position of switching block in the row direction with the input signal to be converted, and providing the conversion code of the upper significant bit in accordance with the 2 modes set in advance in accordance with the result of this comparison; a lower data encoder dividing the outputs of said respective switching blocks in units of columns into two groups in accordance with 2 modes, providing the predetermined lower data conversion code in accordance with the lower significant bit data and the presence/absence of the redundant bit data for each of divided groups, and generating the selection signal for selecting one conversion code from among 2 upper significant bits of conversion codes of the upper data encoder; and a selection gate selectively outputting one conversion code selected from among 2 upper significant bits of conversion codes output from the upper data encoder based on the selection signal output from the lower data encoder. 
     According to the present invention, there is provided an analog/digital converter circuit including: a plurality of reference resistance elements connected in series between two reference potentials; a plurality of switching blocks, arranged in the form of a matrix and activated by the upper data conversion output signal for each row, comparing the respective reference voltages divided by the reference resistance elements with an input signal to be converted, and detecting the presence/absence of the lower significant bit data and redundant bit data; an upper data encoder comparing the reference voltage supplied to the switching block positioned intermediate in the rows excluding at least the uppermost row or lowermost row with the input signal to be converted, and providing the conversion code of the upper significant bit in accordance with the 2 modes set in advance in accordance with the result of this comparison; a lower data encoder dividing the outputs of said respective switching blocks in units of columns into two groups in accordance with the 2 modes, providing the predetermined lower data conversion code in accordance with the lower significant bit data and the presence/absence of the redundant bit data for each of divided groups, and generating the selection signal for selecting one conversion code from among 2 upper significant bits of conversion codes of the upper data encoder; and a selection gate selectively outputting one conversion code selected from among 2 upper significant bits of conversion codes output from the upper data encoder based on the selection signal output from the lower data encoder. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objects and features and other objects and features of the present invention will be described more in detail with reference to the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a serial/parallel A/D converter of a first related art; 
     FIG. 2 is a timing chart of the A/D converter shown in FIG. 1; 
     FIG. 3 is a view of a comparator used for the comparator of the A/D converter etc. of a second related art; 
     FIGS. 4A and 4B are a circuit diagram of another serial/parallel A/D converter of a third related art; 
     FIG. 5 and FIG. 6 show logical values of the A/D converter shown in FIG. 4; 
     FIG. 7 is an explanatory view of the operation of the A/D converter shown in FIG. 5; 
     FIGS. 8A and 8B are a block diagram of a serial/parallel A/D converter of a first embodiment of the present invention; 
     FIG. 9 is a structural view of the comparator of a second embodiment of the present invention; 
     FIG. 10 is an explanatory view of the comparator shown in FIG. 9; 
     FIG. 11 is a structural view of an A/D converter of a third embodiment of the present invention; 
     FIG. 12 shows the logical value of the A/D converter shown in FIG. 11; 
     FIG. 13 is a block diagram of a serial/parallel A/D converter of a fourth embodiment of the present invention; 
     FIG. 14A to FIG. 14C are structural views of the circuit of the switching block of the A/D converter shown in FIG. 13; 
     FIG. 15 and FIG. 16 are views showing input/output characteristics of the A/D converter shown in FIG. 13; 
     FIG. 17 is a block diagram of a serial/parallel A/D converter of a fifth embodiment of the present invention; 
     FIG. 18 shows the operation of the A/D converter shown in FIG. 17; 
     FIGS. 19A and 19B are a block diagram of a serial/parallel A/D converter of a sixth embodiment of the present invention; 
     FIG. 20 and FIG. 21 show the logical values of the respective blocks for explaining the operation of the A/D converter shown in FIG. 19; 
     FIGS. 22A-22C are block diagrams of a serial/parallel A/D converter of a seventh embodiment of the present invention; 
     FIG. 23 and FIG. 24 show the logical values for explaining the logical value and redundancy of the A/D converter shown in FIG. 22; 
     FIGS. 25A-25C are block diagrams of a serial/parallel A/D converter of an eighth embodiment of the present invention; 
     FIGS. 26A-26C are block diagrams of a serial/parallel A/D converter of a ninth embodiment of the present invention; 
     FIG. 27 and FIG. 28 are views of showings the logical values for explaining the operation concerning the redundancy of the A/D converter shown in FIG. 26; 
     FIGS. 29A-29C are block diagrams of a serial/parallel A/D converter of a 10-th embodiment of the present invention; 
     FIGS. 30A-30C are block diagrams of a serial/parallel A/D converter of an 11th embodiment of the present invention; 
     FIG. 31 and FIG. 32 are views showing the logical values for explaining the operation concerning the redundancy of the A/D converter shown in FIG. 30; 
     FIGS. 33A-33C are block diagrams of a serial/parallel A/D converter of a 12-th embodiment the present invention; 
     FIGS. 34A and 34B are a block diagram of a serial/parallel A/D converter of a 13th embodiment of the present invention; 
     FIG. 35 and FIG. 36 are vies showing the logical values for explaining the operation of the A/D converter shown in FIG. 34; 
     FIGS. 37A and 37B are a block diagram of a serial/parallel A/D converter of a 14th embodiment of the present invention; and 
     FIGS. 38A and 38B are a block diagram of a serial/parallel A/D converter of a 15th embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the present invention will be explained in detail referring to the drawings. 
     An explanation will be made of a first embodiment of the present invention. 
     FIG. 8 is a circuit diagram showing one embodiment of an A/D converter circuit according to the present invention. 
     Reference numeral 100 denotes a matrix circuit; 151 to 153 denote upper data comparators; 130, an upper data encoder; 141, a selection gate; 142, an inverter; 101 to denote interpolation-type lower data comparators; 111 to 118 denote latch circuits; 121 and 122 denote suppression circuits; 130, a lower data side AND gate circuit; 140, a lower data encoder; R 1  to R 16  denote reference resistance elements; r denotes a resistance element for a load; B U1  to B U3  and B D0  to B D33  denote multiple output pin buffers; AD U1  to AD U5  denote 2-input AND gates on the upper data side; and OR 1  denotes a 2-input OR gate for the conversion code output; respectively. 
     The present circuit shows a circuit configuration for converting the input analog signal V IN  to 6 bits of a digital code. 
     The positive outputs of the comparators CU 9  of the upper data comparator 151 are connected to the two inputs of the 2-input AND gates AD U9 , and the negative outputs are connected to one input of the AND gate AD U9 . 
     The positive output of the comparator CU 10  of the upper data comparator 152 is connected to both inputs of the 2-input AND gate AD U10 , and the negative output is connected to the two inputs of the AND gate AD U4 . 
     The positive output of the comparators CU 11  of the upper data comparator 153 is connected to the other input of the 2-input AND gates AD U11 , and the negative output is connected to the two inputs of the AND gate AD U5 . 
     The output of the AND gate AD U9  is supplied as the control signal x 1  to the base of the transistor Q 3  of the switching blocks S C12 , S C14 , S C16 , and S C18  ; the output of the AND gate AD U10  is supplied as the control signal x 2  to the base of the transistor Q 3  of the switching blocks S C21 , S C23 , S C25 , and S C27  ; the output of the AND gate AD U11  is supplied as the control signal x 3  to the base of the transistor Q 3  of the switching blocks S C32 , S C34 , S C36 , and S C38  ; the output of the AND gate AD U12  is supplied as the control signal x 4  to the base of the transistor Q 3  of the switching blocks S C41 , S C43 , S C45 , and S C47  ; and the output of the AND gate AD U13  is supplied as the control signal x 15  to the base of the transistor Q 103  of the switching blocks S C52 , S C54 , S C56 , and S C58 . 
     In these AND gates AD U9  to AD U13 , the mutually adjoining two output levels simultaneously become &#34;1&#34;. 
     Concretely, the binary output signal levels of the AND gates AD U9  and AD U10 , AD U10  and AD U11 , AD U11  and AD U12 , and AD U12  and AD U13  simultaneously become &#34;1&#34;, the transistors Q 3  of the respective switching blocks of the matrix circuit 100 connected to the control lines (x 11 , x 12 , x 13 , x 14 , and x 15 ) which have become the &#34;1&#34; level are controlled to turn ON in units of two rows, and the fine digitization of the quantization level is carried out. 
     The lower data comparators 101 to 108 are respectively constituted by comparators C N1  with gains which are set to N, comparators C N1  with gains which are set to n 1  (n 1  &lt;N), and comparators C n1  with gains which are set to n 2  (note, n 1  =n 2  &lt;N, n 1  +n 2  =N). 
     The collector outputs of the transistors Q 1  of the switching blocks S C21  and S C41  at the first column of the matrix circuit 10 are supplied to one side inputs of the comparators C N1 , C n1 , and C n2  of the lower data comparator 101, and the collector outputs (differential outputs) of the transistors Q 2  of the switching blocks S C21  and S C41  are supplied to the other side inputs. 
     The collector outputs of the transistors Q 1  of switching blocks S C12 , S C32 , and S C52  at the second column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C N1 , C n1 , and C n2  of the lower data comparator 102, and the collector outputs (differential outputs) of the transistors Q 102  of the switching blocks S C12 , S C32 , and S C52  are supplied to the other side inputs. 
     The collector outputs of the transistors Q 1  of the switching blocks Sc23 and Sc43 at the third column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C N1 , C n1 , and C n2  of the lower data comparator 103, and the collector outputs (differential outputs) of the transistors Q 102  of the switching blocks S C23  and S C43  are supplied to the other side inputs. 
     The collector outputs of the transistors Q 1  of the switching blocks S C14  and S C34  at the fourth column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C N1 , C n1 , and C n2  of the lower data comparator 104, and the collector outputs (differential outputs) of the transistors Q 102  of the switching blocks S C14  and S C34  are supplied to the other side inputs. 
     The collector outputs of the transistors Q 101  of the switching blocks S C25  and S C45  at the fifth column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C N1 , C n1 , and C n2  of the lower data comparator 105, and the collector outputs (differential outputs) of the transistors Q 102  of the switching blocks S C25  and S C45  are supplied to the other side inputs. 
     The collector outputs of the transistors Q 101  of the switching blocks S C16  and S C36  at the sixth column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C N1 , C n1 , and C n2  of the lower data comparator 106, and the collector outputs (differential outputs) of the transistors Q 102  of the switching blocks S C16  and S C36  are supplied to the other side inputs. 
     The collector outputs of the transistors Q 1  of the switching blocks S C27  and S C47  at the seventh column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C N1 , C n1 , and C n2  of the lower data comparator 107, and the collector outputs (differential outputs) of the transistors Q 102  of the switching blocks S C27  and S C47  are supplied to the other side inputs. 
     The collector outputs of the transistors Q 101  of switching blocks S C18  and S C38  at the eighth column of the matrix circuit 10 are supplied to one side inputs of the respective comparators C N1 , C n1 , and C n2  of the lower data comparator 108, and the collector outputs (differential outputs) of the transistors Q 102  of the switching blocks S C18  and S C38  are supplied to the other side inputs. 
     The two outputs on the positive side and negative side of the respective comparators C N1 , C n1 , and C n2  of the lower data comparators 101 to 108 are connected to the load resistance element r which is connected to the ground level and, at the same time, connected to the respective latch circuits 111 to 118 and lower data comparators corresponding to the adjoining columns or corresponding to every other column. 
     Namely, the two outputs on the positive side and negative side of the comparator C N1  of the lower data comparator 101 are connected to the latch circuit 111. The positive side and negative side outputs of the comparator C n1  of the lower data comparator 101 are connected to the latch circuit 111 and, at the same time, the positive side output is connected to the positive side output of the comparator C n1  of the lower data comparator 102, and the negative side output is connected to the negative side output of the comparator C n1  of the lower data comparator 102. The positive side and negative side outputs of the comparator C n2  of the lower data comparator 101 are connected to the latch circuit 111 and, at the same time, connected to the positive side output of the comparator C n1  of the lower data comparator 103, and the negative side output is connected to the negative side output of the comparator C n1  of the lower data comparator 103. 
     The two outputs on the positive side and negative side of the comparator C N1  of the lower data comparator 102 are connected to the latch circuit 112, and the positive output of the comparator C n1  is connected to the latch circuit 112. The positive side and negative side outputs of the comparator C n2  of the lower data comparator 102 are connected to the latch circuit 112 and, at the same time, the positive side output is connected to the positive side output of the comparator C n1  of the lower data comparator 104, and the negative side output is connected to the negative side output of the comparator C n1  of the lower data comparator 104. 
     The two outputs on the positive side and negative side of the comparators C N1  and C n1  of the lower data comparator 103 are connected to the latch circuit 113. The positive side output of the comparator C n2  of the lower data comparator 103 is connected to the latch circuit 113, and, connected to the positive side output of the comparator C n1  of the lower data comparator 105, and the negative side output is connected to the negative side output of the comparator C n1  of the lower data comparator 105. 
     The two outputs on the positive side and negative side of the comparator C N1  of the lower data comparator 104 are connected to the latch circuit 114, and the positive output of the comparator C n1  is connected to the latch circuit 114. The positive side and negative side outputs of the comparator C n2  of the lower data comparator 104 are connected to the latch circuit 114 and, at the same time, the positive side output is connected to the positive side output of the comparator C n1  of the lower data comparator 106, and the negative side output is connected to the negative side output of the comparator C n1  of the lower data comparator 106. 
     The two outputs on the positive side and negative side of the comparators C N1  and C n1  of the lower data comparator 105 are connected to the latch circuit 115. The positive side output of the comparator C n2  of the lower data comparator 105 is connected to the latch circuit 115, and, connected to the positive side output of the comparator C n1  of the lower data comparator 107, and the negative side output is connected to the negative side output of the comparator C n1  of the lower data comparator 107. 
     The two outputs on the positive side and negative side of the comparator C N1  of the lower data comparator 106 are connected to the latch circuit 116, and the positive output of the comparator C n1  is connected to the latch circuit 116. The positive side and negative side outputs of the comparator C n2  of the lower data comparator 106 are connected to the latch circuit 116 and, at the same time, the positive side output is connected to the positive side output of the comparator C n1  of the lower data comparator 108, and the negative side output is connected to the negative side output of the comparator C n1  of the lower data comparator 108. 
     The two outputs on the positive side and negative side of the comparators C N1  and C n1  of the lower data comparator 107 are connected to the latch circuit 117. The positive side output of the comparator C n2  of the lower data comparator 107 is connected to the latch circuit 117 and, at the same time, connected to the positive side output of the comparator C n2  of the lower data comparator 108, and the negative side output is connected to the negative side output of the comparator C n2  of the lower data comparator 108. 
     The two outputs on the positive side and negative side of the comparators C N1  and C n2  of the lower data comparator 108 are connected to the latch circuit 118 and, at the same time, the positive side output of the comparator C n1  is connected to the latch circuit 118. 
     In this way, the outputs of the comparators C n1  and C n2  of the lower data comparators 101 to 108 having gains  n1  and  n2  are connected to the comparator C n1  or C n2  of the lower data comparators corresponding to respective adjoining columns or corresponding to every other column, and a comparison circuit having an interpolation construction is constituted by two comparators C N1  of a gain N and comparators C n1  and C n2  having gains n1 and n2, of the connected two lower data comparators. 
     Below, a detailed explanation will be made of the fundamental structure of the comparison circuit having an interpolation construction constituted between two lower data comparators, and the function thereof using FIG. 9 and FIG. 10. 
     FIG. 9 is a structural block diagram showing the fundamental structure of the present comparison circuit of a second embodiment of the present invention. 
     In FIG. 9, CMP 1  (161) denotes a first comparator; CMP 2  (162) denotes a second comparator; CMP 3  (163), a third comparator; CMP 4  (164), a fourth comparator; ADD 1 , a first adder; ADD 2 , a second adder; V IN , an input analog signal (hereinafter simply referred to as an input signal); V R1 , a first reference voltage; V R2 , a second reference voltage; and A to E denote comparison outputs; respectively. 
     The first comparator CMP 1  (161) is constituted by a 2-input and 2-output differential amplifier obtaining a complementary output, for example, the weight of the output of which, that is, the gain of which, being set to N times, one side input terminals of which being connected to the input line of the input signal V IN , and the other side inputs of which being connected to the input line of the first reference voltage V R1 . 
     The first comparator CMP 1  (161) compares the input signal V IN  with the first reference voltage V R1 , outputs the signal S 71  from the negative output, and outputs the signal S 72  from the positive output, respectively. 
     The output A of the comparison circuit is constituted by the positive and negative outputs of this first comparator CMP 1  (161). 
     The second comparator CMP 2  (162) is constituted by a 2-input and 2-output differential amplifier obtaining a complementary output, for example, the weight of the output of which being set to N, one side input terminals of which being connected to the input line of the input signal V IN , and the other side inputs of which being connected to the input line of the second reference voltage V R2 . 
     The second comparator CMP 2  (162) compares the input signal V IN  with the second reference voltage V R2 , outputs the signal S 73  from the negative output, and outputs the signal S 74  from the positive output, respectively. 
     The output E of the comparison circuit is constituted by the positive and negative outputs of this second comparator CMP 2  (162). 
     The third comparator CMP 3  (163) is constituted by a 2-input and 2-output differential amplifier obtaining a complementary output, for example, the weight of the output of which being set to n 1  (n 1  &lt;N), one side input terminals of which being connected to the input line of the input signal V IN , and the other side inputs of which being connected to the input line of the first reference voltage V R1 . 
     The third comparator CMP 3  (163) compares the input signal V IN  with the first reference voltage V R1 , outputs the signal S 75  from the negative output, and outputs the signal S 76  from the positive output, respectively. 
     The fourth comparator CMP 4  (164) is constituted by a 2-input and 2-output differential amplifier obtaining a complementary output, for example, the weight of the output of which being set to n 2  (note, n 2  &lt;N, n 1  +n 2  =N), one side input terminals of which being connected to the input line of the input signal V IN , and the other side inputs of which being connected to the input line of the second reference voltage V R2 . 
     The fourth comparator CMP 4  (164) compares the input signal V IN  with the second reference voltage V R2 , outputs the signal S 77  from the negative output, and outputs the signal S 78  from the positive output, respectively. 
     The first adder ADD 1  finds the sum (S 75  +S 77 ) of the negative output signal S 75  of the third comparator CMP 3  (163) and the negative output signal S 77  of the fourth comparator CMP 4  (164) and outputs the same as the signal S 79 . 
     The second adder ADD 2  calculates the sum (S 76  +S 78 ) of the positive output signal S 76  of the third comparator CMP 3  (163) and the positive output signal S 78  of the fourth comparator CMP 4  (164). and outputs the same as the signal S 80 . 
     The output C of the comparison circuit is constituted by the output signals S 79  and S 80  of these first and second adders ADD 1  and ADD 2 . 
     Also, the output B of the comparison circuit is constituted by the output signal S 79  of the first adder ADD 1  and the positive output signal S 72  of the first comparator CMP 1  (161), and the output D of the comparison circuit is constituted by the output signal S 80  of the second adder ADD 2  and the negative output signal S 73  of the second comparator CMP 2  (162). 
     As mentioned above, in the present comparison circuit, the output of the third comparator CMP 3  (163) and the output of the fourth comparator CMP 4  are subjected to the weight of n 1  :n 2 , and when the two are added, n 1  +n 2  (=N) is obtained, and the gain is set so that the same weight as that for the outputs of the first and second comparators CMP 1  (161) and CMP 2  (162) is obtained. 
     Also, the outputs CA to CE of the present comparison circuit are connected to the not illustrated latch circuit. 
     Here, an explanation will be made of the input/output characteristics of the respective parts of the circuit of FIG. 9 using FIG. 10. 
     Note that, in FIG. 10, an abscissa represents an input voltage, and an ordinate represents a relative output level, respectively. 
     First, the output signal S 79  of the first adder ADD 1  will be considered. 
     The signal S 79  is the sum of the negative output signal S 75  of the third comparator CMP 3  (163) and the negative output signal S 77  of the fourth comparator CMP 4  (164). 
     
         S.sub.79 =S.sub.75 +S.sub.77                               (1) 
    
     Here, for the first comparator CMP 1  (161) and the third comparator CMP 3  (163), the same voltage is supplied to the two inputs thereof, respectively and, the weight of outputs of the both is N:n 1 . Therefore, the following relationship equation is established between the negative output signals S 71  and S 75 . 
     
         N:n.sub.1 =S.sub.71 :S.sub.75                              (2) 
    
     From this equation (2), the signal S 75  can be represented as in the following equation. 
     
         S.sub.75 =(n.sub.1 /N)·S.sub.71                   (3) 
    
     Similarly, for the second comparator CMP 2  (162) and the fourth comparator CMP 4  (164), the same voltage is supplied to the two inputs thereof, respectively and the weight of outputs of the two is N:n 2 . Therefore, the following relationship is established between the negative output signals S 73  and S 77 . 
     
         N:n.sub.2 =S.sub.73 :S.sub.77                              (4) 
    
     From this equation (4), the signal S 77  can be represented as in the following equation. 
     
         S.sub.77 =(n.sub.2 /N)·S.sub.73                   (5) 
    
     Accordingly, by substituting the above-described equations (3) and (5) into equation (1), equation (1) can be rewritten as follows: 
     
         S.sub.79 =(n.sub.1 /N)·S.sub.71 +(n.sub.2 /N)·S.sub.73(6) 
    
     When considering equation (6) using FIG. 10, it represents that the signal S 79  becomes the line obtained by interior division of the signal S 71  and signal S 73  to n 1  :n 2 . 
     Next, consideration will be made of the output signal S 80  of the second adder ADD 2 . 
     The signal S 80  is the sum of the positive output signal S 76  of the third comparator CMP 3  (163) and the positive output signal S 78  of the fourth comparator CMP 4  (164). 
     
         S.sub.80 =S.sub.76 +S.sub.78                               (7) 
    
     As mentioned above, for the first comparator CMP 1  (161) and the third comparator CMP 3  (163), the same voltage is supplied to the two inputs thereof, and the weight of outputs of the two is N:n 1 , and therefore the following relationship is established between the positive output signals S 72  and S 76 . 
     
         N:n.sub.1 =S.sub.72 :S.sub.76                              (8) 
    
     From this equation (8), the signal S 76  can be represented as in the following equation. 
     
         S.sub.76 =(n.sub.1 /N)·S.sub.72                   (9) 
    
     Similarly, for the second comparator CMP 2  (162) and the fourth comparator CMP 4  (164), the same voltage is supplied to the two inputs thereof, respectively, and the weight of outputs of the two is N:n 2 , and therefore the following relationship is established between the positive output signals S 74  and S 78 . 
     
         N:n.sub.2 =S.sub.74 :S.sub.78                              (10) 
    
     From this equation (10), the signal S 70  can be represented as in the following equation. 
     
         S.sub.78 =(n.sub.2 /N)·S.sub.74                   (11) 
    
     Accordingly, by substituting the above-described equations (9) and (10) into equation (7), equation (7) can be rewritten as follows: 
     
         S.sub.80 =(n.sub.1 /N)·S.sub.72 +(n.sub.2 /N)·S.sub.74(12) 
    
     When considering equation (12) using FIG. 3, it represents that the signal S 80  becomes the line obtained by interior division of the signal S 72  and signal S 74  to n 1  :n 2 . 
     By the result of consideration of the above-mentioned equations (6) and (12), in FIG. 10, the cross point P 2  between the signal S 79  and signal S 80  is the point obtained by interior division of the cross point P 1  between the signal S 71  and S 72  and the cross point P 3  between the signal S 73  and the signal S 74  to n 1  :n 2 . 
     Accordingly, the output signals C (S 79 , S 80 ) comprising the signal S 79  and the signal S 80  become the results of comparison between the input signal voltage and the imaginary voltage V C  indicated by the next equation. 
     
         V.sub.C =V.sub.R1 +(V.sub.R2 -V.sub.R1)·(n.sub.1 /N)(13) 
    
     where, N=n 1  +n 2   
     Also, the level of the output signals B (S 72 , S 79 ) comprising the signal S 72  and the signal S 79  change according to whether P 4 , which is the cross point of the two, is high or low. 
     The cross point P 4  between the signal S 72  and the signal S 79  is a point of interior division of the cross point P 1  between the signal S 71  and signal S 72  and the cross point P 2  between the signal S 79  and signal S 80  to 1:1. 
     Accordingly, the output signals B (S 72 , S 79 ) comprising the signal S 72  and the signal S 79  become the results of comparison between the input signal voltage and the imaginary voltage V B  indicated by the following equation: 
     
         V.sub.B =V.sub.R1 +(V.sub.R2 -V.sub.R1)·(n.sub.1 /2N)(14) 
    
     Similarly, the level of the output signals D (S 73 , S 80 ) comprising the signal S 73  and the signal S 80  change according to whether P 5  which is the cross point of the two is high or low. 
     The cross point P 5  between the signal S 73  and the signal S 80  is a point of interior division of the cross point P 2  between the signal S 79  and signal S 80  and the cross point P 3  between the signal S 73  and the signal S 74  to 1:1. 
     Accordingly, the output signals D (S 73 , S 80 ) comprising the signal S 73  and the signal S 80  become the results of comparison between the input signal voltage and the imaginary voltage V D  indicated by the following equation: 
     
         V.sub.D =V.sub.R2 -(V.sub.R2 -V.sub.R1)·(n.sub.2 /2N)(15) 
    
     As mentioned above, the present comparison circuit can obtain the result of comparison of the three interpolation points P 2 , P 4 , and P 5  from the two reference voltages V R1  and V R2 . 
     The imaginary voltages V C , V B , and V D  at the respective interpolation points P 2 , P 4 , and P 5  satisfy the following relationships from the above-described equations (13) to (15) and FIG. 10: 
     
         V.sub.R1 &lt;V.sub.B, V.sub.C, V.sub.D &lt;V.sub.R2              (16) 
    
     Also, it is possible to set the weights n 1  and n 2  of the outputs of the third and fourth comparators CMP 3  and CMP 4  to any value so long as it satisfies the condition of n 1  +n 2  =N. 
     Accordingly, by appropriately selecting the values of n 1  and n 2 , the values of the respective imaginary voltages V B , V C , and V D  can be set to any values between the first reference voltage V R1  and the second reference voltage V R2 . 
     For example, where it is assumed that n 1  =n 2  =N/2 as in the present embodiment, 
     V C  =V R1  +(V R2  -V R1 )·(1/2) is obtained from equation (13); 
     V B  =V R1  +(V R2  -V R1 )·(1/4) is obtained from equation (14); ##EQU1## is obtained from equation (15). 
     They represent that the result of comparison between the imaginary voltage, obtained by dividing the voltages of V R1  and V R2  by four, and the input signal. 
     Where the comparison circuit having such an interpolation construction is applied to the A/D converter circuit, the weights n 1  and n 2  of the outputs of the third and fourth comparators CMP 3  (163) and CMP 4  (164) desirably satisfy the condition of n 1  =n 2  =N/2. 
     In the structure of FIG. 8, as mentioned above, a comparison circuit is constructed having an interpolation construction wherein two interpolation outputs are obtained by two comparators C N1  of the gain N and the comparators C n1  and C n2  of the gains n 1  and n 2  of the two lower data comparators. 
     For example, the first comparator CMP 1  (161) and the third comparator CMP 3  (163) of FIG. 9 are constituted by the comparators C N1  and C n1  of the lower data comparator 101, respectively; and the second comparator CMP 2  (162) and the fourth comparator CMP 4  (164) of FIG. 9 are constituted by the comparators C N1  and C n1  of the lower data comparator 102, respectively. They function as the comparison circuits of FIG. 9. Note, as the output of the comparison circuit in this case, outputs corresponding to outputs CA, CC, and CE in FIG. 8 are obtained. 
     Similarly, the first comparator CMP 1  (161) and the third comparator CMP 3  (163) of FIG. 9 are constituted by the comparators C N1  and C n1  of the lower data comparator 101, respectively; and the second comparator CMP 2  (162) and the fourth comparator CMP 4  (164) of FIG. 9 are constituted by the comparators C N1  and C n1  of the lower data comparator 103, respectively. They function as the comparison circuits of FIG. 9. 
     Below, the first comparator CMP 1  (161) and the third comparator CMP 3  (163) of FIG. 9 are constituted by the comparators C N1  and C n1  of the lower data comparator 102, respectively; and the second comparator CMP 2  (162) and the fourth comparator CMP 4  (164) of FIG. 9 are constituted by the comparators C N1  and C n1  of the lower data comparator 104, respectively. They function as the comparison circuits of FIG. 9. 
     The first comparator CMP 1  (161) and the third comparator CMP 3  (163) of FIG. 9 are constituted by the comparators C N1  and C n2  of the lower data comparator 103, respectively; and the second comparator CMP 2  (162) and the fourth comparator CMP 4  (164) of FIG. 9 are constituted by the comparators C N1  and C n1  of the lower data comparator 105, respectively. They function as the comparison circuits of FIG. 9. 
     The first comparator CMP 1  (161) and the third comparator CMP 3  (163) of FIG. 9 are constituted by the comparators C N1  and C n2  of the lower data comparator 104, respectively; and the second comparator CMP 2  (162) and the fourth comparator CMP 4  (164) of FIG. 9 are constituted by the comparators C N1  and C n1  of the lower data comparator 106, respectively. They function as the comparison circuits of FIG. 9. 
     The first comparator CMP 1  (161) and the third comparator CMP 3  (163) of FIG. 9 are constituted by the comparators C N1  and C n2  of the lower data comparator 105, respectively; and the second comparator CMP 2  (162) and the fourth comparator CMP 4  (164) of FIG. 9 are constituted by the comparators C N1  and C n1  of the lower data comparator 107, respectively. They function as the comparison circuits of FIG. 9. 
     The first comparator CMP 1  (161) and the third comparator CMP 3  (163) of FIG. 9 are constituted by the comparators C N1  and C n2  of the lower data comparator 106, respectively; and the second comparator CMP 2  (162) and the fourth comparator CMP 4  (164) of FIG. 9 are constituted by the comparators C N1  and C n1  of the lower data comparator 108, respectively. They function as the comparison circuits of FIG. 9. 
     The first comparator CMP 1  (161) and the third comparator CMP 3  (163) of FIG. 9 are constituted by the comparators C N1  and C n1  of the lower data comparator 107, respectively; and the second comparator CMP 2  (162) and the fourth comparator CMP 4  (164) of FIG. 9 are constituted by the comparators C N1  and C n1  of the lower data comparator 108, respectively. They function as the comparison circuits of FIG. 9. 
     Note that, in these respective comparison circuits, their functions per se do not change even if the positions of the first and third comparators and the second and fourth comparators are inverted. 
     The latch circuits 111 to 118 are constituted by the 2-input and 2-output amplifiers a to d, respectively. 
     The suppression circuit 121 is constituted by the OR gates OR D1  and OR D2  and the AND gates AD D1  to AD D3 , and the suppression circuit 122 is constituted by the OR gates OR D3  and OR D4  and the AND gates AD D4  to AD D6 . 
     The AND gate circuit 130 is constituted by inverters I 1  (AD 0 ) and I 2  (AD 33 ) and AND gates AD 1  to AD 32 . 
     In the structure of FIG. 8, a so-called ring comparator is constituted by these latch circuits 111 to 118, suppression circuits 121 and 122, the AND gate 130, and the lower data comparators 101 to 108 and constituted so that only either one of the inverters I 1  (AD 0 ) and I 2  (AD 33 ) and AND gates AD 1  to AD 32  outputs of the AND gate circuit 155 outputs the active &#34;1&#34; level. 
     Below, an explanation will be made of the configuration of connection between the outputs of the lower data comparators 101 to 108 and the latch circuits 111 to 118 and the connection configuration between the outputs of the latch circuits 111 to 118, the suppression circuits 121 and 122, and the AND gate circuit 155. 
     The positive output of the comparator C n1  of the lower data comparator 101 is connected to one input of the amplifier a of the latch circuit 111, and the negative output is connected to the other input of the amplifier a  and one input of the amplifier b. 
     The positive output of the comparator C N1  of the lower data comparator 101 is connected to the other input of the amplifier b and one input of the amplifier c of the latch circuit 111, and the negative output is connected to the other input of the amplifier c and one input of the amplifier d. The positive output of the comparator C n2  of the lower data comparator 101 is connected to the other input of the amplifier d of the latch circuit 111. 
     The positive output of the amplifier a of the latch circuit 111 is connected to one input of the AND gate AD 1  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD D1  of the suppression circuit 121; the positive output of the amplifier b is connected to one input of the AND gate AD 2  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD D2  of the suppression circuit 121; the positive output of the amplifier c is connected to one input of the AND gate AD 3  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD D3  of the suppression circuit 121 and one input of the OR gate OR D1  ; and the positive output of the amplifier d is connected to one input of the AND gate AD 4  of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD 3  of the AND gate circuit 155. 
     To other inputs of the AND gates AD D1  to AD D3  and the OR gate OR D1  of the suppression circuit 121, the outputs of the inverter 142 inverting the output level of the upper data side other output buffers B U1  and B U3  (AND gates A U1  and A U3  of the upper data comparators 151 and 153) are connected. 
     The output of the OR gate OR D1  is connected to the input of the inverter I 1  of the AND gate circuit 155; the output of the AND gate AD D1  is connected to one input of the AND gate AD 5  of the AND gate circuit 155; the output of the AND gate AD D2  is connected to the other input of the AND gate AD 1  of the AND gate circuit 155; and the output of the AND gate AD D3  is connected to the other input of the AND gate AD 2  of the AND gate circuit 155. 
     The positive output of the comparator C n1  of the lower data comparator 102 is connected to one input of the amplifier d of the latch circuit 112. The positive output of the comparator C N1  of the lower data comparator 102 is connected to one input of the amplifier b of the latch circuit 112 and one input of the amplifier c, and the negative output is connected to the other input of the amplifier c and the other input of the amplifier d. The positive output of the comparator C n2  of the lower data comparator 102 is connected to one input of the amplifier a of the latch circuit 112, and the negative output is connected to the other input of the amplifier a and the other input of the amplifier b. 
     The positive output of the amplifier d of the latch circuit 112 is connected to the other input of the AND gate AD 5  of the AND gate circuit 155, and the negative output is connected to one input of the OR gate OR D2  of the suppression circuit 121; the positive output of the amplifier c is connected to one input of the AND gate AD 6  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD 7  of the AND gate circuit 155; the positive output of the amplifier b is connected to the other input of the AND gate AD 7  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD 8  of the AND gate circuit 155; and the positive output of the amplifier a is connected to the other input of the AND gate AD 8  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD 13  of the AND gate circuit 155. 
     To the other input of the OR gate OR D2  of the suppression circuit 121, the outputs of the upper data side buffers B U1  and B U3  (AND gates A U1  and A U3  of the upper data comparators 151 and 153) are connected. 
     The output of the OR gate OR D1  is connected to the other input of the AND gate AD 6  of the AND gate circuit 155. 
     The positive output of the comparator C n1  of the lower data comparator 103 is connected to one input of the amplifier a of the latch circuit 113, and the negative output is connected to the other input of the amplifier a and one input of the amplifier b. The positive output of the comparator C N1  of the lower data comparator 103 is connected to the other input of the amplifier b of the latch circuit 113 and one input of the amplifier c, and the negative output is connected to the other input of the amplifier c and one input of the amplifier d. The positive output of the comparator C n2  of the lower data comparator 103 is connected to the other input of the amplifier d of the latch circuit 113. 
     The positive output of the amplifier a of the latch circuit 113 is connected to one input of the AND gate AD 9  of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD 4  of the AND gate circuit 155; the positive output of the amplifier b is connected to one input of the AND gate AD 10  of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD 9  of the AND gate circuit 155; the positive output of the amplifier c is connected to one input of the AND gate AD 11  of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD 10  of the AND gate circuit 155; and the positive output of the amplifier d is connected to one input of the AND gate AD 12  of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD 11  of the AND gate circuit 155. 
     The positive output of the comparator C n1  of the lower data comparator 104 is connected to one input of the amplifier d of the latch circuit 114. The positive output of the comparator C N1  of the lower data comparator 104 is connected to one input of the amplifier b and one input of the amplifier c of the latch circuit 114, and the negative output is connected to the other input of the amplifier c and the other input of the amplifier d. The positive output of the comparator C n2  of the lower data comparator 104 is connected to one input of the amplifier a of the latch circuit 114, and the negative output is connected to the other input of the amplifier a and the other input of the amplifier b. 
     The positive output of the amplifier d of the latch circuit 114 is connected to the other input of the AND gate AD 13  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD 14  of the AND gate circuit 155; the positive output of the amplifier c is connected to the other input of the AND gate AD 14  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD 15  of the AND gate circuit 155; the positive output of the amplifier b is connected to the other input of the AND gate AD 15  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD 16  of the AND gate circuit 155; and the positive output of the amplifier a is connected to the other input of the AND gate AD 16  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD 21  of the AND gate circuit 155. 
     The positive output of the comparator C n1  of the lower data comparator 105 is connected to one input of the amplifier a of the latch circuit 115, and the negative output is connected to the other input of the amplifier a and one input of the amplifier b. The positive output of the comparator C N1  of the lower data comparator 105 is connected to the other input of the amplifier b and one input of the amplifier c of the latch circuit 115, and the negative output is connected to the other input of the amplifier c and one input of the amplifier d. The positive output of the comparator C n2  of the lower data comparator 105 is connected to the other input of the amplifier d of the latch circuit 115. 
     The positive output of the amplifier a of the latch circuit 115 is connected to one input of the AND gate AD 17   of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD 12  of the AND gate circuit 155; the positive output of the amplifier b is connected to one input of the AND gate A D18  of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD 17  of the AND gate circuit 155; the positive output of the amplifier c is connected to one input of the AND gate AD 19  of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD 18  of the AND gate circuit 155; and the positive output of the amplifier d is connected to one input of the AND gate AD 20  of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD 19  of the AND gate circuit 155. 
     The positive output of the comparator C n1  of the lower data comparator 106 is connected to one input of the amplifier d of the latch circuit 116. The positive output of the comparator C N1  of the lower data comparator 106 is connected to one input of the amplifier b and one input of the amplifier c of the latch circuit 116, and the negative output is connected to the other input of the amplifier c and the other input of the amplifier d. The positive output of the comparator C n2  of the lower data comparator 106 is connected to one input of the amplifier a of the latch circuit 116, and the negative output is connected to the other input of the amplifier a and the other input of the amplifier b. 
     The positive output of the amplifier d of the latch circuit 116 is connected to the other input of the AND gate AD 21  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD 22  of the AND gate circuit 155; the positive output of the amplifier c is connected to the other input of the AND gate AD 22  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD 23  of the AND gate circuit 155; the positive output of the amplifier b is connected to the other input of the AND gate AD 33  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD 24  of the AND gate circuit 155; and the positive output of the amplifier a is connected to the other input of the AND gate AD 14  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD 29  of the AND gate circuit 155. 
     The positive output of the comparator C n1  of the lower data comparator 107 is connected to one input of the amplifier a of the latch circuit 117, and the negative output is connected to the other input of the amplifier a and one input of the amplifier b. The positive output of the comparator C N1  of the lower data comparator 107 is connected to the other input of the amplifier b and one input of the amplifier c of the latch circuit 117, and the negative output is connected to the other input of the amplifier c and one input of the amplifier d. The positive output of the comparator C n2  of the lower data comparator 107 is connected to the other input of the amplifier d of the latch circuit 117. 
     The positive output of the amplifier a of the latch circuit 117 is connected to one input of the AND gate AD 25  of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD 20  of the AND gate circuit 155; the positive output of the amplifier b is connected to one input of the AND gate AD 26  of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD 25  of the AND gate circuit 155; the positive output of the amplifier c is connected to one input of the AND gate AD 27  of the AND gate circuit 155, and the negative output is connected to the other input of the AND gate AD 26  of the AND gate circuit 155; and the positive output of the amplifier d is connected to one input of the AND gate AD 28  of the AND gate circuit 155, and the negative output is connected to one input of the OR gate OR D3  of the suppression circuit 122. 
     To the other input of the OR gate OR D3  of the suppression circuit 122, the outputs of the inverter 142 inverting the level of the outputs of the upper data side other output buffers B U1  and B U3  (AND gates A U1  and A U3  of the upper data comparators 151 and 153) are connected. 
     The output of the OR gate OR D3  is connected to the other input of the AND gate AD 27  of the AND gate circuit 130. 
     The positive output of the comparator C n1  of the lower data comparator 108 is connected to one input of the amplifier d of the latch circuit 118. The positive output of the comparator C N1  of the lower data comparator 108 is connected to one input of the amplifier b and one input of the amplifier c of the latch circuit 118, and the negative output is connected to the other input of the amplifier c and the other input of the amplifier d. The positive output of the comparator C n2  of the lower data comparator 108 is connected to one input of the amplifier a of the latch circuit 118, and the negative output is connected to the other input of the amplifier a and the other input of the amplifier b. 
     The positive output of the amplifier d of the latch circuit 118 is connected to the other input of the AND gate AD 29  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD 30  of the AND gate circuit 155; the positive output of the amplifier c is connected to the other input of the AND gate AD 30  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD D4  of the suppression circuit 122 and one input of the OR gate OR D4  ; the positive output of the amplifier b is connected to one input of the AND gate AD 31  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD D5  of the suppression circuit 122; and the positive output of the amplifier a is connected to one input of the AND gate AD 32  of the AND gate circuit 155, and the negative output is connected to one input of the AND gate AD D6  of the suppression circuit 122. 
     To the other inputs of the AND gates AD D4  to AD D6  and the OR gate OR D4  of the suppression circuit 122 are connected the outputs of the upper data side buffers B U1  and B U3  (the AND gates A U1  and A U3  of the upper data comparators 151 and 153). 
     The output of the OR gate OR D4  is connected to the input of the inverter I 2  of the AND gate circuit 155; the output of the AND gate AD D4  is connected to the other input of the AND gate AD 31  of the AND gate circuit 155; the output of the AND gate AD D5  is connected to the other input of the AND gate AD 32  of the AND gate circuit 155; and the output of the AND gate AD D6  is connected to the other input of the AND gate AD 28  of the AND gate circuit 155. 
     The outputs of the respective inverters I 1  and I 2  and the AND gates AD 1  to AD 32  of the AND gate circuit 155 are connected to the lower data encoder 140 via the buffers B D0  tO B D33 , respectively. 
     A ring comparator is constituted by the above connection configuration. Where the ring comparator is constituted using the comparison circuit having an interpolation construction of FIG. 9, it is necessary to cut the left or right of the ring, and the suppression circuits 121 and 122 have this ring cutting function. The suppression circuit 121 is a circuit cutting the left of the ring, and the suppression circuit 122 is a circuit cutting the right of the ring. 
     Here, an explanation will be made of the fundamental operation of the suppression circuit of the third embodiment of the present invention using FIG. 11. 
     In FIG. 11, CN1 to CN8 are comparison circuits comparing the reference voltage divided by the reference resistance element R and the input signal V IN  as they are, and Cn denotes the comparison circuit using interpolation. FIG. 11 indicates a case where the left side of the ring is cut. 
     In this case, the lowest reference voltage is supplied to the comparison circuit CN1, and the highest reference voltage is supplied to the comparison circuit CN8. 
     For this reason, the outputs of the three interpolation comparison circuits of Cn a , Cn b , and Cn c  in FIG. 11 become unnecessary. So as not to input these outputs to the lower data encoder 140, the suppression circuit 121 acts so as to suppress the three outputs of the interpolation comparison circuits Cn a , Cn b , and Cn c . 
     This is the same also in the case where the right of the ring is cut. 
     The lower data encoder 140 is constituted by a data line LN 141  generating conversion code data D 2  to D 6 , a selection line LN 142  generating a selection signal SEL 1  showing that one of the outputs of the AND gates AD 1 , AD 2 , AD 5  to AD 8 , AD 13 , and AD 14  of the AND gate circuit 155 becomes &#34;1&#34;; a selection line LN 143  generating a selection signal SEL 2  indicating that one of the outputs of the inverter I 1 , AND gates AD 2 , AD 3 , AD 4 , AD 9  to AD 12 , AD 17  to AD 20 , AD 25  to AD 28 , AD 31 , and AD 32  of the AND gate circuit 155 becomes &#34;1&#34;; and a selection line LN 144  generating a selection signal SEL 3  indicating that one of the outputs of the AND gates AD 15 , AD 16 , AD 21  to AD 24 , AD 29 , and AD 30  , and the inverter I 2  of the AND gate circuit 155 becomes &#34;1&#34;. 
     FIG. 12 shows the correspondence between the output conversion code data D 2  to D 6  and the selection line data LN 142  to LN 144  which is the result of encoding of the lower data encoder 140 when the outputs of the inverters I 1  and I 2  and AD 1  to AD 32  of the lower data side AND gate circuit 155 are &#34;1&#34;. 
     Next, the operation by the above-described structure will be explained. 
     For example, when the sampling voltage V S  of the sampled analog signal is represented as V RB  &lt;V S  &lt;V 3  (=e 12 ), the outputs of the comparators CU 1  to CU 3  of the upper data comparators 151 to 153 become &#34;L&#34;, and the digital signals of &#34;0&#34; are output from the AND gates AU 1  to AU 3 , respectively. 
     As a result, the digital signal such as [000] is input via the buffers B U1  to B U3  to the upper data encoder 130. The outputs of the AND gates AU 1  and AU 3  pass through the buffers B U1  to B U3 , and then are input to the suppression circuits 121 and 122 directly or after an inversion of the level at the inverter 80. 
     At the upper data encoder 130, the upper significant data of [000] is issued to the three columns of encoder lines [LN 31  ] to [LN 33  ] generating the predetermined data by a so-called wired-OR circuit and is output to the selection gate 141. 
     Also, at this time, only the outputs of the AND gates AD U4  and AD U5  among the upper data side AND gates AD U1  to AD U5  become &#34;H&#34;, and the control signals x 4  and x 5  of &#34;1&#34; are output from the AND gates AD U4  and AD U5 . 
     Also, if the sampling voltage V S  is represented as V 3  &lt;V S  &lt;V 2  (=e 8 ), the outputs of the comparators CU 1  and CU 2  of the upper data comparators 151 and 151 become &#34;L&#34;, and the output of the comparator CU 3  of the upper data comparator 153 becomes &#34;H&#34;, and the digital signal is output, i.e., &#34;0&#34; is output from the AND gates AU 1  and AU 2  of the upper data comparators 151 and 152, and &#34;1&#34; is output from the AND gate AU 3  of the upper data comparator 153, respectively. 
     As a result, the digital signal such as [001] is input via the buffers B U1  to B U3  to the upper data encoder 155, and the outputs of the AND gates AU 1  and AU 3  pass through the buffers B U1  and B U3 , and then are input to the suppression circuits 121 and 122 directly or after being inverted in their levels at the inverter 142. 
     At the upper data encoder 130, the upper significant data of [001] is generated to the encoder lines [LN 31  ] to [LN 33  ] and is output to the selection gate 141. 
     Also, at this time, only the outputs of the AND gates AD U3  and AD U4  among the upper data side AND gates AD U1  to AD U5  become &#34;H&#34;, and the control signals x 13  and x 14  of &#34;1&#34; are output from the AND gates AD U3  and AD U4 . 
     Also, if the sampling voltage V S  is represented as V 32  &lt;V S  &lt;V 31 , the outputs of the comparators CU 2  and CU 3  of the upper data comparators 152 and 153 become &#34;H&#34;, the output of the comparator CU 1  of the upper data comparator 151 becomes &#34;L&#34;, and the digital signal is output, i.e., &#34;1&#34; is output from the AND gate AU 2  of the upper data comparator 152, and &#34;0&#34; is output from the AND gates AU 1  and AU 3  of the upper data comparators 151 and 153, respectively. 
     As a result, a digital signal such as [010] is input via the buffers B U1  to B U3  to the upper data encoder 155, and the outputs of the AND gates AU 1  and AU 3  pass through the buffers B U1  and B U3  and then are input to the suppression circuits 121 and 122 directly or after being inverted in their levels at the inverter 142. 
     At the upper data encoder 130, the upper significant data of [011] is generated to the encoder lines [LN 31  ] to [LN 33  ] and is output to the selection gate 141. 
     Also, at this time, only the outputs of the AND gates AD U2  and AD U3  among the upper data side AND gates AD U1  to AD U5  become &#34;H&#34;, and the control signals x 12  and x 13  of &#34;1&#34; are output from the AND gates AD U2  and AD U3 . 
     Also, if the sampling voltage V S  is represented as V 31  &lt;V S  &lt;V RT , the outputs of the comparators CU 1  to CU 3  of the upper data comparators 151 to 153 become &#34;H&#34;, and a digital signal is output, i.e., &#34;1&#34; is output from the AND gate AU 2  of the upper data comparator 151, and &#34;0&#34; is output from the AND gates AU 2  and AU 3  of the upper data comparators 152 and 153, respectively. 
     As a result, a digital signal such as [100] is input via the buffers B U1  to B U3  to the upper data encoder 155, and the outputs of the AND gates AU 1  and AU 3  pass through the buffers B U1  and B U3  and then are input to the suppression circuits 121 and 122 directly or after being inverted in their levels at the inverter 142. 
     At the upper data encoder 130, the upper significant data of [110] is generated to the encoder lines [LN 31  ] to [LN 33  ] and is output to the selection gate 70. 
     Also, at this time, only the outputs of the AND gates AD U1  and AD U2  among the upper data side AND gates AD U1  to AD U5  become &#34;H&#34;, and the control signals x 11  and x 12  of &#34;1&#34; are output from the AND gates AD U1  and AD U2 . 
     In parallel with this, the transistors Q 103  of the respective switching blocks of the matrix circuit 100 connected to the control lines (x 11 , x 12 , x 13 , x 14  and x 15 ) at which the digital output signal among the respective upper data side AND gates AD U (1, 2, 3, 4, 5) has become &#34;1&#34; are controlled to turn ON in units of two rows, and further a fine digitization of the quantization level is executed. 
     For example, when the outputs of the output control signals x 14  and x 13  of the AND gates AD U4  and AD U3  become the &#34;1&#34; level (at this time, only the output of the AND gate A U3  is the &#34;1&#34; level), respective transistors Q 103  of the switching blocks S C41 , S C43 , S C45 , and S C47  at the second row from the bottom in the diagram, and the switching blocks S C32 , S C34 , S C36 , and S C38  at the third row adjoining them become ON, so that the reference voltages e 7  to e 15  divided by the reference resistors R 7  to R 16  and the sampling voltage V S  are differentially amplified at the respective switching blocks S C41 , S C43 , S C45 , and S C47 , and S C32 , S C34 , S C36 , and S C38 , and the differential output is input to the 2-input ends of the comparators C N1 , C n1 , and C n2  of the lower data comparators 101 to 108. 
     Similarly, when the outputs of the output control signals x 13  and x 12  of the AND gates AD U3  and AD U2  become the &#34;1&#34; level (at this time, only the output of the AND gate A U2  is the &#34;1&#34; level), the switching blocks S C32 , S C34 , S C36 , and S C38  at the third row, and the switching blocks S C21 , S C23 , S C25 , and S C27  at the second row adjoining them are activated, so that the differential amplification operation is performed, and the differential output is input to the 2-input ends of the comparators C N1 , C n1 , and C n2  of the lower data comparators 101 to 108. 
     For example, when the output of the AND gate AU 2  is at &#34;1&#34; level, the lower data conversion code is detected by the switching blocks S C21 , S C23 , S C32 , and S C34 , and the redundant bit of the lower data conversion code is detected by the switching blocks S C25 , S C27 , S C36 , and S C38 . 
     The outputs of the comparators C n1  and C n2  of the respective lower data comparators 101 to 108 having the gain of n 1  (or n 2 ) are connected to the comparators C n1  and C n2  of the lower data comparators corresponding to the adjoining columns or corresponding to every other column, whereby the ring comparator is constituted, and the differential outputs between the sampled voltage V S  obtained at the activated switching block and the reference voltage divided by the reference resistance element are compared between the two comparators C N1  and C n1  of the connected two lower data comparators or by the comparison circuit having an interpolation construction constituted by C n1  and C n2 . As a result, an interpolation output is obtained, which is input to the respective latch circuits 111 to 118. 
     The output of the latch circuit 118 is input to the inverters I 1  and I 2  and the AND gates A D1  to A D32  of the AND gate circuit 130 via the suppression circuits 121 and 122 or directly, whereby a digital signal in accordance with the result of comparison will be output to the lower data encoder 140. 
     Note that, at this time, in the suppression circuits 121 and 122, based on the output signal of the upper data comparators 151 and 153, cutting is carried out on the left side or right side of the ring comparator and, at the same time, the unnecessary input of the output of the interpolation circuit to the lower data encoder 140 is suppressed. 
     At the lower data encoder 140, by the wired-OR circuit, as shown in FIG. 12, the output conversion codes D 2  to D 6  are set at the line LN 141  in accordance with the output level of the inverters I 1  and I 2  and the AND gates AD 1  to AD 32  of the AND gate circuit 155 and output, and at the same time, one line among the selection lines LN 142  to LN 144  is set at &#34;1&#34;, which is input as the selection signals SEL 1  to SEL 3  to the AND gates A 1  to A 3  of the selection gate 70, respectively. 
     At this time, where for example the output of the AND gate AD 1  of the AND gate circuit 155 is at the &#34;1&#34; level, the conversion codes D 2  to D 6  are set at [00110] and output, the selection signal SEL 1  is input to the AND gate A 1  of the selection gate 70 as the &#34;1&#34; level, and the selection signals SEL 2  and SEL 3  are input to the AND gates A 2  and A 3  of the selection gate as the &#34;0&#34; level. 
     At the selection gate 141, along with the fact that only the selection signal SEL 1  is input as the &#34;1&#34; level, only the AND gate A 1  is activated. 
     To the AND gate A 1 , the upper significant data generated in the line LN 31  of the upper data encoder 130 has been supplied. 
     Accordingly, the upper significant data generated in the line LN 31  is selected at the selection gate 141, and as a result, it is output as the upper data conversion code D 1  via the OR gate OR 1 . 
     As explained above, according to the present embodiment, the lower data comparators 101 to 108 corresponding to respective columns of the switching block are constituted by the comparator C N1  having a gain of N and comparators C n1  and C n2  having a gain of n 1  (or n 2 ) and, at the same time, a ring comparator is constituted by connecting the outputs of the comparators C n1  and C n2  to the comparators C n1  and C n2  of the lower data comparators corresponding to the adjoining columns or corresponding to every other column, and constituted so that the differential outputs between the sampled voltage V S  obtained at the activated switching block and the reference voltage divided by the reference resistance element are compared between the two comparators C N1  and C n1  of the connected two lower data comparators or by the comparison circuit having an interpolation construction constituted by C n1  and C n2 , whereby an interpolation output is obtained and, provision is made of suppression circuits 121 and 122 which act as the left side or right side of the ring comparator in accordance with the outputs of the upper data comparators 151 and 153 and, at the same time, suppress the unnecessary input of the output of the interpolation circuit to the lower data encoder 140. Therefore, a great improvement of the resolution can be achieved, and an A/D converter circuit having a high precision can be realized. 
     Also, the restrictions with respect to the emitter size of the reference resistance element and transistor are eased, and as a result, the elements can be made smaller, and thus there is an advantage that a reduction of the surface area of the chip can be achieved and so on. 
     Also, in the above-mentioned embodiment, the structure in which the other output pin buffers B U1  to B U3  and B D0  to B D33  are arranged on the input side of the upper data encoder 30 and the lower data encoder 140 was shown, but these other output pin buffers B U1  to B U3  and B D0  to B D33  are provided so as to reliably drive the upper data encoder 130 and the lower data encoder 140. It is necessary to provide the same according to a certain capacitance of the upper data encoder 130 and the lower data encoder 140 acting as a so-called load. 
     As explained above, according to the present invention, a great improvement of the resolution can be achieved, and an A/D converter circuit having a high precision can be realized. 
     Also, the restrictions with respect to the emitter size of the reference resistance element and transistor are eased, and as a result, the elements can be made smaller, and thus there is an advantage that a reduction of the surface area of the chip can be achieved and so on. 
     An explanation will now be made of a fourth embodiment of the present invention. 
     FIG. 13 is a structural view showing a fourth embodiment of an A/D converter circuit according to the present invention. 
     R 71  to R 86  denote reference resistance elements; CU 11  to CU 13  denote upper data comparators; AU 15  to AU 17  denote upper data side AND gates; E U1  denotes an upper data encoder; S d1  to S d12  denote switching blocks; EOD 1  to EOD 3  denote even/odd determination circuits; B D1  to B D3  denote complementary output buffers; AD 51  to AD 53  denote lower data side AND gates; E D1 , a lower data encoder; RV 1 , an inverted gate; V IN , an input analog signal; and V RT  and V RB  denote reference voltages set with a predetermined differential therebetween; respectively. 
     The reference resistance elements R 71  to R 86  are connected in series between the terminals of the reference voltages V RT  to V RB  (0 to -2 V) and generate the reference voltages V 1  to V 15  obtained by dividing the reference voltage between the adjoining resistance elements, respectively. 
     The upper data comparator CU 15  is connected to the input line of the analog signal V IN  which is to be converted at its one input terminal, is connected to the middle point of connection of the resistance elements R 74  and R 75  generated by the reference voltage V 44  of the rough quantization level divided by the reference resistance elements R 71  to R 86  at its other input terminal, and is connected to one input terminal of the 2-input AND gate AU 15  at its positive output terminal. 
     This upper data comparator CU 15  compares the input analog signal V IN  with the reference voltage V 44  and outputs the signal indicating the result of that comparison at a high level (&#34;1&#34;) when the level of the analog signal V IN  is higher than the reference voltage V 44 , while at a low level (&#34;0&#34;) when the level of the analog signal V In  is lower than the reference voltage V 44 , to the AND gate AU 11  from its positive output terminal. 
     The upper data comparator CU 16  is connected to the input line of the analog signal V IN  which is to be converted at its one input terminal, is connected to the middle point of connection of the resistance elements and R 79  generated by the reference voltage V 48  of the rough quantization level divided by the reference resistance elements R 71  to R 86  at its other input terminal, is connected to one input terminal of the 2-input AND gate AU 16  at its positive output terminal, and is connected to the other input terminal of the 2-input AND gate AU 15  at its negative output terminal. 
     This upper data comparator CU 16  compares the input analog signal V IN  with the reference voltage V 48 , outputs the signal indicating the result of that comparison at a high level when the level of the analog signal V IN  is higher than the reference voltage V 48 , while at a low level when the level of the analog signal V IN  is lower than the reference voltage V 48 , to the AND gate AU 16  from its positive output terminal and outputs the signal obtained by inverting the level of the positive output to the other input terminal of the AND gate AU 15  from its negative output terminal. 
     The upper data comparator CU 17  is connected to the input line of the analog signal V IN  which is to be converted at its one input terminal, is connected to the middle point of connection of the resistance elements R 82  and R 83  generated by the reference voltage V 12  of the rough quantization level divided by the reference resistance elements R 71  to R 86  at its other input terminal, is connected to the two input terminals of the 2-input AND gate AU 17  at its positive output terminal, and is connected to the other input terminal of the 2-input AND gate AU 16  at its negative output terminal. 
     This upper data comparator CU 17  compares the input analog signal V IN  with the reference voltage V 52 , outputs the signal indicating the result of that comparison at a high level when the level of the analog signal V IN  is higher than the reference voltage V 52 , while at a low level when the level of the analog signal V IN  is lower than the reference voltage V 52 , to the AND gate AU 17  from its positive output terminal, and outputs the signal obtained by inverting the level of the positive output to the other input terminal of the AND gate AU 16  from its negative output terminal. 
     The AND gate AU 15  obtains the logical product between the positive output of the upper data comparator CU 15  and the negative output of the upper data comparator CU 16  and outputs the result of the same to the upper data encoder E U1 . 
     The AND gate AU 16  obtains a logical product between the positive output of the upper data comparator CU 16  and the negative output of the upper data comparator CU 17  and outputs the result of the same to the upper data encoder E U1 . 
     The AND gate AU 17  obtains a logical product for the positive output of the upper data comparator CU 17  as a 2-input and outputs the result of the same to the upper data encoder E U1 . 
     The upper data encoder E U1  encodes the output signals of the respective AND gates AU 15  to AU 17  in accordance with the output levels of the same, converts the same to a digital code of 2 bits, and outputs the result as the conversion codes D 0  and D 1  of the upper significant 2 bits. 
     Concretely, where the output levels of the AND gates AU 15  to AU 17  are all &#34;0&#34;, the conversion codes D 0  and D 1  are set to [0,0] and output; where the output level of the AND gate AU 15  is &#34;1&#34;, they are set to [0,1] and output; where the output level of the AND gate AU 16  is &#34;1&#34;, they are set to [1,0] and output; and where the output level of the AND gate AU 17  is &#34;1&#34;, they are set to [1,1] and output. 
     The switching blocks S d1  to S d2  are arranged in the form of a matrix comprising four rows and three columns and constituted by for example differential type amplifiers, which compare one reference voltage among the reference voltages V 41  to V 55  (note, V 44 , V 48 , and V 52  are excluded) divided by the reference resistance elements R 71  to R 86  with the input analog signal V IN , and in accordance with the magnitude of the input analog signal V IN  with respect to the reference voltage. Concretely, in the case of (V IN  &gt;reference voltage V), they output S 1  to S 12  of &#34;1&#34;, and in the case of (level V IN  ≦reference voltage V), S 1  to S 12  of the &#34;0&#34; level to the corresponding even/odd determination circuits EOD 1  to EOD 3  arranged in accordance with the columns. 
     Explaining this in further detail, the switching blocks S d1 , S d6 , S d7 , and S d12  arranged in the first column (left side in the figure) compare the reference voltages V 41 , V 47 , V 49 , and V 55  with the analog signal V IN , respectively, and output the results of this as the signals S 91 , S 96 , S 97 , and S 102  to the even/odd determination circuit EOD 1 . 
     The switching blocks S d2 , S d5 , S d8 , and S d11  arranged in the second column compare the reference voltages V 42 , V 46 , V 50 , and V 54  with the analog signal V IN , respectively, and output the results of this as the signals S 92 , S 95 , S 98 , and S 101  to the even/odd determination circuit EOD 2 . 
     The switching blocks S d3 , S d4 , S d9  and S d10  arranged in the third column compare the reference voltages V 43 , V 45 , V 51 , and V 53  with the analog signal V IN , respectively, and output the results of this as the signals S 93 , S 94 , S 99 , and S 100  to the even/odd determination circuit EOD 3 . 
     The even/odd determination circuit EOD 1  determines whether or not there are an even number of the signals S 91 , S 96 , S 97 , and S 102  which are output from the switching blocks S d1 , S d6 , S d7 , and S d12  and simultaneously input which have an input level of &#34;1&#34;. It outputs the signal S EO1  to the buffer B D1  with the &#34;0&#34; level where it determines that the number is even, while with the &#34;1&#34; level where it determines that the number is not even, that is, an odd number. 
     The even/odd determination circuit EOD 2  determines whether or not there are even number of signals S 92 , S 95 , S 98 , and S 101  which are output from the switching blocks S d2 , S d5 , S d8 , and S d11  and simultaneously input which have an input level of &#34;1&#34;. It outputs the signal S EO2  to the buffer B U2  with the &#34;0&#34; level where it determines that the number is even, while with the &#34;1&#34; level where it determines that the number is odd. 
     The even/odd determination circuit EOD 3  determines whether or not there are an even number of the signals S 93 , S 94 , S 99 , and S 100  which are output from the switching blocks S d3 , S d4 , S d9 , and S d10  and simultaneously input which have an input level of &#34;1&#34;. It outputs the signal S EO3  to the buffer B D3  with the &#34;0&#34; level where it determines that the number is even, while with the &#34;1&#34; level where it determines that the number is odd. 
     FIG. 14 is a view showing an example of the circuit structure of the switching block and even/odd determination circuit for each column, in which FIG. 14A shows an example of the circuit structure of the switching blocks S d1 , S d6 , S d7 , and S d12  and the even/odd determining circuit EOD 1  at the first column; FIG. 14B shows an example of the circuit structure of the switching blocks S d2 , S d5 , S d8 , and S d11  and the even/odd determining circuit EOD 2  at the second column; and FIG. 14C shows an example of the circuit structure of the switching blocks S d3 , S d4 , S d9 , and S d10  and the even/odd determining circuit EOD 3  at the third column; respectively. 
     These circuits have the same fundamental structure and function in each column except the input reference voltage differs, and therefore an explanation will be made here of the structure of the example of FIG. 14A. 
     In FIG. 14A, V CC  denotes a power source voltage; LR 1  and LR 2  denote load resistance elements of the resistance value R; Q 121  to Q 128  denote npn-type transistors; and I C11  to I C14  denote constant current sources supplying the current I; respectively. 
     The constant current source I C11  is connected to the emitter of the transistor Q 121  and the emitter of the transistor Q 122 , so that the switching block S d1  comprising a differential amplifier is constituted; the constant current source I C12  is connected to the emitter of the transistor Q 123  and the emitter of the transistor Q 124 , so that the switching block S d6  comprising a differential amplifier is constituted; a constant current source I C13  is connected to the emitter of the transistor Q 125  and the emitter of the transistor Q 126 , so that the switching block S d7  comprising a differential amplifier is constituted; and the constant current source I C14  is connected to the emitter of the transistor Q 127  and the emitter of the transistor Q 128 , so that the switching block S d12  comprising a differential amplifier is constituted. 
     Then, the system is constituted so that an analog signal V IN  is input to the respective bases of the transistors Q 121 , Q 123 , Q 125 , and Q 127  ; the reference voltage V 41  is input to the base of the transistor Q 122  ; the reference voltage V 47  is input to the base of the transistor Q 124  ; the reference voltage V 49  is input to the base of the transistor Q 126  ; and the reference voltage V 55  is input to the base of the transistor Q 128  ; respectively. 
     The even/odd determining circuit EOD 1  is constituted by the combination of connection of the respective collectors of the respective transistors Q 121  to Q 128  with respect to the load resistance elements LR 1  and LR 2 . 
     Namely, the collectors of the transistors Q 121 , Q 124 , Q 125 , and Q 128  are connected to the power source voltage V CC  via the load resistance element LR 2  ; the collectors of the transistors Q 122 , Q 123 , Q 126 , and Q 127  are connected to the power source voltage V CC  via the load resistance element LR 1  ; and the output terminal of the signal S EO1  is constituted by the connection point between the collector of the transistor Q 127  and the load resistance element LR 1 . 
     Explaining an example of the fundamental operation of the structure of FIG. 14A, for example in the case where V IN  &lt;V 41 , the reference voltages V 41 , V 47 , V 49 , and V 55  are larger than the input analog signal V IN  in all of the switching blocks S d1 , S d6 , S d7 , and S d12 , and therefore the transistors Q 122 , Q 124 , Q 126 , and Q 128  become ON. As a result, a current such as 2I flows through the load resistance elements LR 1  and LR 2 , respectively. 
     Accordingly, the level of the output signal S EO1  becomes (V CC  -2I·R). 
     Also, in the case where V 41  &lt;V IN  &lt;V 47 , the transistors Q 121 , Q 124 , Q 126 , and Q 128  become ON. As a result, a current such as I flows through the load resistance element LR 1 , and a current such as 3I flows through the load resistance element LR 2 . 
     Accordingly, the level of the output signal S EO1  becomes (V CC  -I·R). 
     Namely, when the differential pair (switching block) of (analog signal V IN  &gt;reference voltage V) is even, the level of the output signal S EO1  becomes (V CC  -2I·R) at the low level, while becomes (V CC  -I·R) at the high level when it is the odd number. 
     The complementary output buffer B D1  is connected to the output terminal of the even/odd determining circuit EOD 1  at its input terminal and is connected to one input terminal of the AND gate AD 51  at its positive output terminal. 
     This buffer B D1  performs the predetermined level adjustment of the even/odd determining circuit EOD 1  with respect to the output signal S EO1  and outputs the result to one input terminal of the AND gate AD 51  from its positive output terminal. 
     The complementary output buffer B D2  is connected to the output terminal of the even/odd determining circuit EOD 2  at its input terminal, connected to one input terminal of the AND gate AD 52  at its positive output terminal, and connected to the other input terminal of the AND gate AD 51  at its negative output terminal. 
     This buffer B D2  performs the predetermined level adjustment of the even/odd determining circuit EOD 2  with respect to the output signal S EO2  and outputs the result to one input terminal of the AND gate AD 52  from its positive output terminal; while outputs the inverted input level to the other input terminal of the AND gate AD 51  from its negative output terminal. 
     The complementary output buffer B D3  is connected to the output terminal of the even/odd determining circuit EOD 3  at its input terminal, connected to the two input terminals of the AND gate AD 53  at its positive output terminal, and connected to the other input terminal of the AND gate AD 52  at its negative output terminal. 
     This buffer B D3  performs the predetermined level adjustment of the even/odd determining circuit EOD 3  with respect to the output signal S EO3  and outputs the result to the two input terminals of the AND gate AD 53  from its positive output terminal; while outputs the inverted input level to the other input terminal of the AND gate AD 52  from its negative output terminal. 
     The AND gate AD 51  obtains the logical product between the positive output of the buffer BD 1  and the negative output of the buffer BD 45  and outputs the result thereof to the lower data encoder E D1 . 
     The AND gate AD 52  obtains the logical product between the positive output of the buffer BD 45  and the negative output of the buffer BD 46  and outputs the result thereof to the lower data encoder E D1 . 
     The AND gate AD 53  obtains the logical product between two inputs of the positive output of the buffer BD 46  and outputs the result thereof to the lower data encoder E D1 . 
     The lower data encoder E D1  encodes the output signals of the respective AND gates AD 51  to AD 53  in accordance with the output levels of the same, converts the same to the 2 bits of a digital code, and outputs the same as preceding output codes BD 45  and BD 46  of the conversion codes D 2  and D 3  of the lower significant 2 bits to the inverted gate RV 1 . 
     Concretely, it sets the preceding output codes BD 45  and BD 46  to [0,0] and outputs the same where the output levels of the AND gates AD 51  to AD 53  are all &#34;0&#34;; sets the same to [0,1] where the output level of the AND gate AD 51  is &#34;1&#34; and outputs the result; sets the same to [1,0] where the output level of the AND gate AD 52  is &#34;1&#34; and outputs the result; and sets the same to [1,1] where the output level of the AND gate AD 53  is &#34;1&#34; and outputs the result. 
     The inverted gate RV 1  is constituted by for example parallel-arranged exclusive-OR gates EXO 1  and EXO 2 , obtains the exclusive-OR between the preceding output codes BD 45  and BD 46  output from the lower data encoder E D1  and the output conversion code D 1  of the upper data encoder E D1 , and outputs the same as the conversion codes D 2  and D 3  of the lower significant 2 bits. 
     Concretely, it obtains the exclusive-OR between the preceding output code BD 45  and the upper data conversion code D 1  at the exclusive-OR gate EXO 1 , outputs the result thereof as the lower data conversion code D 2 , obtains the exclusive-OR between the preceding output code BD 46  and the upper data conversion code D 1  at the exclusive-OR gate EXO 2 , and outputs the result thereof as the lower data conversion code D 3 . 
     Next, an explanation will be made of the operation by the above-described structure in sequence dividing the same into the upper data conversion and the lower data conversion and referring to FIG. 15 and FIG. 16. 
     Note that, FIG. 15 shows the correspondence between the output levels of the upper data comparators CU 15  to CU 17 , output levels of the AND gates AU 15  to AU 17 , and the output levels of the conversion codes D 0  and D 1  in accordance with the magnitude of the input voltage (analog signal) level at the time of upper data conversion with respect to the reference voltages V 4  to V 12 . 
     Also, FIG. 16 shows the correspondence between the levels of the output signals S 91  to S 102  of the switching blocks S d1  to S d2 , the levels of the output signals S EO1  to S EO3  of the even/odd determining circuit EOD 1  to EOD 3 , the output levels of the AND gates AD 51  to AD 53 , and the output levels of the conversion codes D 2  and D 3 , in accordance with the magnitude of the input voltage (analog signal) level at the time of lower data conversion with respect to the reference voltages V 1  to V 4 . 
     First, the upper data conversion operation will be explained using FIG. 15. 
     The reference voltages V 4 , V 8 , and V 12  of the rough quantization level divided by the reference resistance elements R 71  to R 86  and the input analog signal V IN  are compared by the upper data comparators CU 15  to CU 17 , respectively. 
     As a result of this comparison, if for example V IN  &lt; V 44 , as shown in FIG. 15, the outputs of the upper data comparators CU 15 , CU 16 , and CU 17  become all the &#34;0&#34; level. 
     By this, also the output levels of the AND gates AU 15  to AU 17  become all &#34;0&#34;. 
     As a result, [00] is output as the upper significant 2 bits of the conversion codes D 0  and D 1  from the upper data encoder E U1 . 
     As a result of comparison, if for example V 44  &lt;V IN  &lt;V 48 , the output of the upper data comparator CU 15  becomes the &#34;1&#34; level, and the outputs of the upper data comparators CU 16  and CU 17  become the &#34;0&#34; level. 
     By this, among the output levels of the AND gates AU 15  to AU 17 , only the output of the AND gate AU 15  becomes &#34;1&#34;, and the outputs of the other AND gates AU 16  and AU 17  become &#34;0&#34;. 
     As a result, [01] is output as the upper significant 2 bits of the conversion codes D 0  and D 1  from the upper data encoder E U1 . 
     As a result of comparison, if for example V 48  &lt;V IN  &lt;V 52 , the outputs of the upper data comparators CU 15  and CU 16  become the &#34;1&#34; level, and the output of the upper data comparator CU 17  becomes the &#34;0&#34; level. 
     By this, among the output levels of the AND gates AU 15  to AU 17 , only the output of the AND gate AU 15  becomes &#34;1&#34;, and the outputs of the other AND gates AU 15  and AU 17  become &#34;0&#34;. 
     As a result, [10] is output as the upper significant 2 bits of the conversion codes D 0  and D 1  from the upper data encoder E U1 . 
     Further, as a result of comparison, if for example V 52  &lt;V IN , the outputs of the upper data comparators CU 15 , CU 16  and CU 17  become all the &#34;1&#34; level. 
     By this, among the output levels of the AND gates AU 15  to AU 17 , only the output of the AND gate AU 17  becomes &#34;1&#34;, and the outputs of the other AND gates AU 15  and AU 16  become &#34;0&#34;. 
     As a result, [11] is output as the upper significant 2 bits of conversion codes D O  and D 1  from the upper data encoder E U1 . 
     Next, an explanation will be made of the lower data conversion operation using FIG. 16. 
     At the time of the conversion operation, all switching blocks S d1  to S d2  are in the ON state, the input analog signal V IN  is compared with the corresponding reference voltages V 41  to V 43 , V 45  to V 47 , V 49  to V 51  and V 53  to V 55  of the fine quantization level divided by the reference resistance elements R 71  to R 86  in the respective switching blocks S d1  to S d2 , respectively. 
     In the respective switching blocks S d1  to S d12 , as a result of comparison, if V IN  &gt;reference voltage V, the output signals S 91  to S 102  are output as the &#34;1&#34; level, while if V IN  ≦reference voltage V, the output signals V 91  to S 102  are output as the &#34;0&#34; level. 
     Accordingly, if for example V IN  &lt;V 41 , the signals S 91  to S 102  of the &#34;0&#34; level are output from all switching blocks S d1  to S d2 . Namely, the number of signals of the &#34;1&#34; level of each column is zero. 
     Accordingly, the signals S EO1  to S EO3  are output as the &#34;0&#34; level from all even/odd determining circuits EOD 1  to EOD 3 , and also the output levels of the lower data side AND gates AD 51  to AD 53  become all &#34;0&#34;. 
     As a result, [00] is output as the preceding output codes BD 42  and BD 43  of the lower significant 2 bits from the lower data encoder. At this time, since also the conversion code D 1  by the upper data encoder E U1  is [0], the preceding output codes BD 42  and BD 43  are not subjected to the inversion function at the inverted gate RV 1  and are output as the lower data conversion codes D 2  and D 3  while holding their level [00] as they are. 
     Also, if V 1  &lt;V IN  &lt;V 2 , only the output signal S 1  of the switching block S d1  is output as the &#34;1&#34; level, and the output signals S 92  to S 102  of the remaining switching blocks S d2  to S d12  are output as the &#34;0&#34; level. Namely, the number of signals of the &#34;1&#34; level in the left first column is (1), and the number of the signals of the &#34;1&#34; level in the second and third columns is zero. 
     Accordingly, the signal S EO1  is output as the &#34;1&#34; level from the even/odd determining circuit EOD 1 , and the signals S EO2  and S EO3  are output as the &#34;0&#34; level from the even/odd determining circuits EOD 2  and EOD 3 . 
     By this, among the output levels of the AND gates AD 51  to AD 53 , only the output of the AND gate AD 51  becomes &#34;1&#34;, and the outputs of the other AND gates AD 52  and AD 53  become &#34;0&#34;. 
     As a result, [01] is output as the preceding output codes BD 42  and BD 43  of the lower significant 2 bits from the lower data encoder E D1 . At this time, since also the conversion code D 1  by the upper data encoder E U1  is [0], the preceding output codes BD 42  and BD 43  are not subjected to the inversion function at the inverted gate RV 41  and are output as the lower data conversion codes D 2  and D 3  while holding their level [01] as they are. 
     Also, if V 42  &lt;V IN  &lt;V 43 , only the output signals S 91  and S 92  of the switching blocks S d1  and S d2  are output as the &#34;1&#34; level, and the output signals S 93  to S 102  of the remaining switching blocks S d3  to S d12  are output as the &#34;0&#34; level. Namely, the number of signals of the &#34;1&#34; level in the first column and second column is one, and the number of the signals of the &#34;1&#34; level in the third column is zero. 
     Accordingly, the signals S EO1  and S EO2  are output as the &#34;1&#34; level from the even/odd determining circuits EOD 1  and EOD 2 , and the signal S EO3  is output as the &#34;0&#34; level from the even/odd determining circuit EOD 3 . 
     By this, among the output levels of the AND gates AD 51  to AD 53 , only the output of the AND gate AD 52  becomes &#34;1&#34;, and the outputs of the other AND gates AU 15  and AU 17  become &#34;0&#34;. 
     As a result, [10] is output as the preceding output codes BD 42  and BD 43  of the lower significant 2 bits from the lower data encoder E D1 . At this time, since also the conversion code D 1  by the upper data encoder E U1  is [0], the preceding output codes BD 42  and BD 43  are not subjected to the inversion function at the inverted gate RV 1  and are output as the lower data conversion codes D 2  and D 3  while holding their level [20] as they are. 
     Further, if V 43  &lt;V IN  &lt;V 44 , only the output signals S 91 , S 92 , and S 93  of the switching blocks S d1 , S d2 , and S d3  are output as the &#34;1&#34; level, and the output signals S 94  to S 102  of the remaining switching blocks S d4  to S d12  are output as the &#34;0&#34; level. Namely, the number of signals of the &#34;1&#34; level of all columns of the first column, second column, and third column is one. 
     Accordingly, the signals S EO1  to S EO3  are output as the &#34;1&#34; level from the even/odd determining circuits EOD 1  to EOD 3 . 
     By this, among the output levels of the AND gates AD 51  to AD 53 , only the output of the AND gate AD 53  becomes &#34;1&#34;, and the outputs of the other AND gates AU 15  and AU 16  become &#34;0&#34;. 
     As a result, [11] is output as the preceding output codes BD 42  and BD 43  of the lower significant 2 bits from the lower data encoder E D1 . At this time, since also the conversion code D 1  by the upper data encoder E U1  is [0], the preceding output codes BD 42  and BD 43  are not subject to the inversion function at the inverted gate RV 1  and are output as the lower data conversion codes D 2  and D 3  while holding their level [11] as they are. 
     In above way, the lower data conversion code is obtained. In the case where the reference voltage V 4  &lt;V IN  as well, the conversion operation of lower significant data is similarly carried out. 
     Note, in the case where V 44  &lt;V IN  &lt;V 48  and V 52  &lt;V IN , due to the restrictions of the circuit structure etc., the direction of application of the reference voltage from the second row to the fourth row of the switching block array from the bottom in FIG. 13 has become reverse to that at the first row and the third row, and therefore the levels of the preceding output codes BD 45  and B 46  are inverted, and thus the level is returned to the normal level at the inverted gate RV 1  and output as the lower data conversion codes D 2  and D 3 . 
     As explained above, according to the present embodiment, by simultaneously actuating all of the switching blocks S d1  to S d12  of the serial/parallel type A/D converter circuit, arranged in the form of matrix, to made the same perform a comparison between the respective reference voltages V 41  to V 55  (note, V 44 , V 48 , and V 52  are excluded) and the input analog signal V IN , it is determined for each column whether the number of the switching blocks for which the result of comparison that the analog signal V IN  is larger than the reference voltage is output is even or odd, and the conversion of lower data is carried out in accordance with the result of determination. Therefore, the conversions of data of the upper significant and lower significant data can be simultaneously carried out. 
     Accordingly, it becomes unnecessary to provide the sampling and holding circuit as in the conventional serial/parallel type A/D converter circuit, and also cumbersome circuit control is not required. 
     Also, the circuit can be constituted by a greatly reduced number of comparators in comparison with the parallel type A/D converter circuit requiring (2 n  -1) comparators so as to obtain the n bits of conversion code, and therefore a reduction of the surface area of the chip and the power consumption can be achieved. 
     An explanation will now be made of a fifth embodiment of the present invention. 
     FIG. 17 is a structural view showing a fifth embodiment of the A/D converter circuit according to the present invention. 
     The essential point of difference of the present embodiment from the above-described embodiments resides in the constitution in which a plurality of sets of block comprising two adjoining switching blocks in the same column treated as one set are provided instead of performing the even/odd determination based on the combination of connection of the collector outputs of the transistor differential pairs constituting the respective switching blocks of the same column, the exclusive-OR of the two switching blocks of respective sets are obtained, respectively, and the results are subjected to so-called a wired-OR, whereby the even/odd determination is carried out. 
     In FIG. 17, EX 1  to EX 6  indicate the exclusive-OR gate constituting the even/odd determining circuit EOD 1a  to EOD 3a . These are connected as follows. 
     Namely, one input terminal of the exclusive-OR gate EX 1  is connected to the output terminal of the switching block S e1 , and the other input terminal is connected to the output terminal of the switching block S e6  ; one input terminal of the exclusive-OR gate EX 6  is connected to the output terminal of the switching block S e7 , and the other input terminal is connected to the output terminal of the switching block S e12  ; and the output terminals of the exclusive-OR gates EX 1  and EX 6  are connected to each other, whereby the even/odd determining circuit EOD 1a  at the first column is constituted. 
     This even/odd determining circuit EOD 1a  performs the wired-OR (logical OR) of the result of the exclusive-OR of the two gates at the middle point of connection between the output terminals of the exclusive-OR gates EX 1  and EX 6  and outputs the result thereof as the signal S EO1  indicating the result of even/odd determination at the first column to the buffer BD 21 . 
     Also, one input terminal of the exclusive-OR gate EX 2  is connected to the output terminal of the switching block S e2 , and the other input terminal is connected to the output terminal of the switching block S e5  ; one input terminal of the exclusive-OR gate EX 5  is connected to the output terminal of the switching block S e8 , and the other input terminal is connected to the output terminal of the switching block S e11  ; and the output terminals of the exclusive-OR gates EX 2  and EX 5  are connected to each other, whereby the even/odd determining circuit EOD 2a  at the second column is constituted. 
     This even/odd determining circuit EOD 2a  performs the wired-OR (logical OR) of the result of the exclusive-OR of the two gates at the middle point of connection between the output terminals of the exclusive-OR gates EX 2  and EX 5  and outputs the result thereof as the signal S EO2  indicating the result of even/odd determination at the second column to the buffer B D2 . 
     Further, one input terminal of the exclusive-OR gate EX 3  is connected to the output terminal of the switching block S B3 , and the other input terminal is connected to the output terminal of the switching block S e4  ; one input terminal of the exclusive-OR gate EX 4  is connected to the output terminal of the switching block S e9 , and the other input terminal is connected to the output terminal of the switching block S e10  ; and the output terminals of the exclusive-OR gates EX 3  and EX 4  are connected to each other, whereby the even/odd determining circuit EOD 3a  at the third column is constituted. 
     This even/odd determining circuit EOD 3a  performs the wired-OR (logical OR) of the result of the exclusive-OR of the two gates at the middle point of connection between the output terminals of the exclusive-OR gates EX 3  and EX 4  and outputs the result thereof as the signal S EO3  indicating the result of even/odd determination at the third column to the buffer BD 23 . 
     Note that, in the structure of FIG. 17, the upper data comparators CU 21  to CU 23  are constituted not by complementary outputs, but by the usual single outputs, and are constituted so that the complementary output buffers BU 21  to BU 23  are provided on the input side of the next stage to this, that is on the input side of the AND gates AU 21  to AU 23 , and further multiple output pin buffers MB U1  to MB U3  are provided between the outputs of the AND gates AU 21  to AU 23  and the inputs of the upper data encoders E U1 , but the upper data conversion function is the same as that of the case of the first embodiment mentioned above. 
     Similarly, the circuit has a structure wherein multiple output pin buffers MB D1  to MB D3  are provided between the outputs of the AND gates AD 61  to AD 63  and the inputs of the lower data encoders E D1 , but the lower significant data conversion function is the same as that of the case of the embodiment mentioned above. 
     Next, the operation by the structure of FIG. 17 will be explained using the timing chart of FIG. 18. Note that, the upper significant data conversion operation is essentially the same as that in the embodiment and therefore an explanation will be omitted. 
     In the same way as the case of the above-mentioned fourth embodiment, all switching blocks S e1  to S e12  are in the ON state at the time of the conversion operation, the input analog signal V IN  is compared with the corresponding reference voltages V 71  to V 73 , V 75  to V 77 , V 79  to V 81 , and V 83  to V 85  of the fine quantization level divided by the reference resistance elements R 91  to R 106  at the respective switching blocks S e1  to S e12 , respectively. 
     In the respective switching blocks S e1  to S e12 , as the result of comparison, the output signals S 111  to S 122  are output as the &#34;1&#34; level if V IN  &gt;reference voltage V, while the output signals S 71  to S 82  are output as the &#34;0&#34; level if V IN  ≦reference voltage V. 
     Accordingly, if for example V IN  &lt;V 71 , the signals S 111  to S 122  of the &#34;0&#34; level are output from all switching blocks S e1  to S e12 . 
     For this reason, the signal levels input to both input terminals of all of the exclusive-OR gates EX 1  to EX 6  are &#34;0&#34;. 
     Accordingly, since the output levels of all of the exclusive-OR gates EX 1  to EX 6  become &#34;0&#34;, signals S EO1  to S EO3  are output from all of the even/odd determining circuits EOD 1a  to EOD 3a  as the &#34;0&#34; level, and also the output levels of the lower data side AND gates AD 61  to AD 63  become all &#34;0&#34;. 
     As a result, [00] is output as the preceding output codes BD 55  and BD 56  of the lower significant 2 bits, from the lower data encoder E D1 , and at this time, also the conversion code D 1  by the upper data encoder E U1  is [0], and therefore the preceding output codes BD 55  and BD 56  are not subjected to the inversion function at the inverted gate RV 1  and are output as the lower significant data conversion codes D 2  and D 3  while maintaining their levels [00] as they are. 
     If V 71  &lt;V IN  &lt;V 72 , only the output signal S 111  of the switching block S e1  is output as the &#34;1&#34; level, and the output signals S 112  to S 122  of the remaining switching blocks S e1  to S e12  are output as the &#34;0&#34; level. 
     For this reason, only the output level of the exclusive-OR gate EX 1  at the first column from the left becomes &#34;1&#34;, and the output levels of the other exclusive-OR gates EX 2  to EX 6  become &#34;0&#34;. 
     Accordingly, the signal S EO1  is output as the &#34;1&#34; level from the even/odd determining circuit EOD 1 , and signals S EO2  and S EO3  are output as the &#34;0&#34; level from the even/odd determining circuits EOD 2  and EOD 3 . 
     By this, in the output levels of the AND gates AD 61  to AD 63 , only the output of the AND gate AD 61  becomes &#34;1&#34;, and the outputs of the other AND gates AD 62  and AD 63  become &#34;0&#34;. 
     As a result, [01] is output as the preceding output codes BD 55  and BD 56  of the lower significant 2 bits from the lower data encoder E D1 . At this time, also the conversion code D 1  by the upper data encoder E U1  is [0], and therefore the preceding output codes BD 55  and BD 56  are not subjected to the inversion function at the inverted gate RV 21  and are output as the lower significant data conversion codes D 2  and D 3  while maintaining their levels [01] as they are. 
     If V 72  &lt;V IN  &lt;V 73 , only the output signals S 111  and S 112  of the switching blocks S B1  and S B2  are output as the &#34;1&#34; level, and the output signals S 113  to S 122  of the remaining switching blocks S e3  to S e12  are output as the &#34;0&#34; level. 
     For this reason, only the output levels of the exclusive-OR gates EX 1  and EX 2  become &#34;1&#34;, and the output levels of the other exclusive-OR gates EX 3  to EX 6  become &#34;0&#34;. 
     Accordingly, the signals S EO1  and S EO2  are output as the &#34;1&#34; level from the even/odd determining circuits EOD 1  and EOD 2 , and the signal S EO3  is output as the &#34;0&#34; level from the even/odd determining circuit EOD 3 . 
     By this, among the output levels of the AND gates AD 61  to AD 63 , only the output of the AND gate AD 62  becomes &#34;1&#34;, and the outputs of the other AND gates AU 21  and AU 23  become &#34;0&#34;. 
     As a result, [10] is output as the preceding output codes BD 55  and BD 56  of the lower significant 2 bits from the lower data encoder E D1 . At this time, also the conversion code D 1  by the upper data encoder E U1  is [0], and therefore the preceding output codes BD 55  and BD 56  are not subject to the inversion function at the inverted gate RV 1  and are output as the lower significant data conversion codes D 2  and D 3  while maintaining their levels [10] as they are. 
     If V 73  &lt;V IN  &lt;V 74 , only the output signals S 111 , S 112 , and S 113  of the switching blocks S e1 , S e2 , and S e3  are output as the &#34;1&#34; level, and the output signals S 24  to S 32  of the remaining switching blocks S e4  to S e12  are output as the &#34;0&#34; level. 
     For this reason, only the output levels of the exclusive-OR gates EX 1 , EX 2 , and EX 3  become &#34;1&#34;, and the output levels of the other exclusive-OR gates EX 4  to EX 6  become &#34;0&#34;. 
     Accordingly, the signals S EO1  to S EO3  are output as the &#34;1&#34; level from the even/odd determining circuits EOD 1  to EOD 3 . 
     By this, among the output levels of the AND gates AD 61  to AD 63 , only the output of the AND gate AD 63  becomes &#34;1&#34;, and the outputs of the other AND gates AU 21  and AU 22  become &#34;0&#34;. 
     As a result, [11] is output as the preceding output codes BD 55  and BD 56  of the lower significant 2 bits from the lower data encoder E D1 . At this time, also the conversion code D 1  by the upper data encoder E U1  is [0], and therefore the preceding output codes BD 55  and BD 56  are not subjected to the inversion function at the inverted gate RV 1  and are output as the lower significant data conversion codes D 2  and D 3  while maintaining their levels [11] as they are. 
     Note that, the case where V 74  &lt;V IN  &lt;V 75  is the same as the case where V 73  &lt;V IN  &lt;V 74 , but at this time, the conversion code D 3  by the upper data encoder E U1  is [1], and therefore the preceding output codes BD 55  and BD 56  are subjected to the inversion function at the inverted gate RV 1  and output as the lower significant data conversion codes D 2  and D 3  with the level [00]. 
     Further, if V 75  &lt;V IN  &lt;V 76 , only the output signals S 111  to S 114  of the switching blocks S e1  to S e4  are output as the &#34;1&#34; level, and the output signals S 25  to S 32  of the remaining switching blocks S e5  to S e12  are output as the &#34;0&#34; level. 
     For this reason, only the output levels of the exclusive-OR gates EX 1  and EX 2  become &#34;1&#34;, and the output levels of the other exclusive-OR gates EX 3  to EX 6  become &#34;0&#34;. 
     Accordingly, the signals S EO1  and S EO2  are output as the &#34;1&#34; level from the even/odd determining circuits EOD 1  and EOD 2 , and the signal S EO3  is output as the &#34;0&#34; level from the even/odd determining circuit EOD 3 . 
     By this, in the output levels of the AND gates AD 61  to AD 63 , only the output of the AND gate AD 62  becomes &#34;1&#34;, and the outputs of the other AND gates AU 21  and AU 63  become &#34;0&#34;. 
     As a result, [10] is output as the preceding output codes BD 2  and BD 3  of the lower significant 2 bits, from the lower data encoder E D1 . At this time, the conversion code D 1  by the upper data encoder E U1  is [1], and therefore the preceding output codes BD 55  and BD 56  are subjected to the inversion function at the inverted gate RV 1  and output as the lower significant data conversion codes D 2  and D 3  with the level [01]. 
     Further, if V 76  &lt;V IN  &lt;V 77 , the output signals S 111  to S 115  of the switching blocks S e1  to S e5  are output as the &#34;1&#34; level, and the output signals S 116  to S 122  of the remaining switching blocks S e6  to S e12  are output as the &#34;0&#34; level. 
     For this reason, only the output level of the exclusive-OR gate EX 1  becomes &#34;1&#34;, and the output levels of the other exclusive-OR gates EX 2  to EX 6  become &#34;0&#34;. 
     Accordingly, the signal S EO1  is output as the &#34;1&#34; level from the even/odd determining circuit EOD 1 , and the signals S EO2  and S EO3  are output as the &#34;0&#34; level from the even/odd determining circuits EOD 2  and EOD 3 . 
     By this, in the output levels of the AND gates AD 61  to AD 63 , only the output of the AND gate AD 61  becomes &#34;1&#34;, and the outputs of the other AND gates AU 22  and AU 23  become &#34;0&#34;. 
     As a result, [01] is output as the preceding output codes BD 55  and BD 56  of the lower significant 2 bits from the lower data encoder E D1 . At this time, the conversion code D 1  by the upper data encoder E U1  is [1], and therefore the preceding output codes BD 55  and BD 56  are subjected to the inversion function at the inverted gate RV 1  and output as the lower significant data conversion codes D 2  and D 3  with the level [10]. 
     If V 77  &lt;V IN  &lt;V 78 , the output signals S 111  to S 116  of the switching blocks S e1  to S e6  are output as the &#34;1&#34; level, and the output signals S 117  to S 122  of the remaining switching blocks S e7  to S e12  are output as the &#34;0&#34; level. 
     For this reason, all of the output levels of the exclusive-OR gates EX 1  to EX 6  become &#34;0&#34;. 
     Accordingly, the signals S EO1  to S EO3  are output as the &#34;0&#34; level from all of the even/odd determining circuits EOD 1a  to EOD 3a . 
     By this, in the output levels of the AND gates AD 61  to AD 63 , the output levels of all of the AND gates AU 1  to AU 3  become &#34;0&#34;. 
     As a result, [00] is output as the preceding output codes BD 55  and BD 56  of the lower significant 2 bits from the lower data encoder E D1 . At this time, the conversion code D 1  by the upper data encoder E U1  is [1], and therefore the preceding output codes BD 55  and BD 56  are subjected to the inversion function at the inverted gate RV 1  and output as the lower significant data conversion codes D 2  and D 3  with the level [11]. 
     Thereafter, in the case where V 78  &lt;V IN  &lt;V 82 , the conversion code D 1  by the upper data encoder E U1  becomes [0], the conversion operation is the same as that in the case where V IN  &lt;V 74  mentioned above, and in the case where V 82  &lt;V IN , the conversion code D 3  by the upper data encoder E U1  becomes [1], and therefore the conversion operation becomes the same operation as that of the case where V 74  &lt;V IN  &lt;V 78 . 
     As explained above, in the fifth embodiment, similar effects to those obtained in the above-mentioned fourth embodiment can be obtained. 
     Note that, in the above-mentioned fourth embodiment and fifth embodiment, an explanation was made taking as an example a circuit structure corresponding to 4-bit conversion, but needless to say the present invention can be applied also to the case of a larger number of bit conversion, and similar effects to those mentioned above can be obtained. 
     As explained above, according to the present invention, there are advantages that the increase of the power consumption and surface area of chip can be prevented, it is not necessary to provide the sampling and holding circuit, and the complication of the circuit control etc. can be prevented. 
     An explanation will be made next of a sixth embodiment of the present invention. 
     FIG. 19 is a circuit diagram showing the sixth embodiment of the A/D converter circuit according to the present invention. 
     Namely, 170 denotes a matrix circuit; 161 to 163 denote upper data comparators; 151 to 157 denote lower data comparators; 167 denotes an inverter; 150, an upper data encoder; 165, a lower data encoder; 166, a selection gate; OR 31  and OR 32  denote OR gates; and EXO 31  and EXO 32  denote exclusive-OR gates; respectively. 
     The upper data encoder 150 is constituted by an encoder line LN 156  generating the data for the redundant L (left) mode, an encoder line LN 157  generating the data for a non-redundant mode, and an encoder line LN 158  generating the data for the redundant R (right) mode. 
     Namely, in the upper data encoder 150, respective encoder lines LN 156  to LN 158  are set corresponding to a structure in which the columns of switching blocks shown with the hatching in the diagram, which detect the redundant bit among the switching blocks S f11  to S f17 , S f21  to S f27 , S f31  to S f37 , and S f41  to S f47  arranged in the matrix circuit 170 are arranged so as to be positioned on both sides, i.e., the left side and right side, of the switching block columns outputting the conversion codes of the lower significant bits in FIG. 1. 
     FIG. 20 shows the correspondence between the outputs of the respective AND gates AU 31 , AU 32 , AU 33 , and AU 34  of the upper data comparators 161 to 163, and the set output data code pattern of the respective encoder lines LN 156  to LN 157  of the upper data encoder 150. 
     The setting of the data is carried out so that, in accordance with the direction of transition of the reference voltage level by the respective reference resistance elements in the rows among the serially connected reference resistance element groups which are folded-back so that the number of rows becomes four, concretely an orientation (hereinafter referred to as a direction) of transition of the reference voltage from the low potential side to the high potential side, so that (data of redundant L mode≦(data of non-redundant mode)&lt;(data of redundant R mode) or (data of redundant L mode)≧(data of non-redundant mode)&gt;(data of redundant R mode) stands. 
     In the structure of FIG. 19, the first row from the bottom comprising the resistance elements R 133  to R 136  and the third row comprising the resistance elements R 125  to R 128  have the same direction, and the second row comprising the resistance elements R 129  to R 133  and the fourth row comprising the resistance elements R 121  to R 124  have the same direction. 
     Accordingly, the data setting level in the case where the AND gates AU 34  and AU 32  corresponding to the first row and the third row are at the &#34;1&#34; level is set so that (data of redundant L mode)≦(data of non-redundant mode)&lt;(data of redundant R mode) stands. 
     Contrary to this, the data setting level in the case where the AND gates AU 33  and AU 31  corresponding to the second row and the fourth row are at the &#34;1&#34; level is set so that (data of redundant L mode)≧(data of non-redundant mode)&gt;(data of redundant R mode) stands. 
     The lower data encoder 165 is constituted by a data line LN 151  generating the lower significant data BD 63  and BD 64  ; a selection line LN 152  generating the selection signal SEL 1  indicating that either of the outputs of the AND gates AD 71  and AD 72  of the lower data comparators 151 and 152 becomes &#34;1&#34;; a selection line LN 153  generating the selection signal SEL 2  indicating that either of the outputs of the AND gates AD 73  to AD 76  of the lower data comparators 153 to 156 becomes &#34;1&#34;; and a selection line LN 153  generating the selection signal SEL 13  indicating that either of the outputs of the AND gates AD 77  and AD 78  of the lower data comparator 157 becomes &#34;1&#34;. 
     FIG. 21 shows the correspondence between the outputs of the AND gates AD 71  to AD 78  of the lower data comparators 151 to 157, output data of the lower data encoder 165, and the selection signal. 
     The selection gate 166 is constituted by AND gates A 41  to A 46 , selects one upper significant data from among the respective upper significant data of the redundant L mode, non-redundant mode, and the redundant R mode output from the upper data encoder 150 using the selection signals SEL 11  to SEL 13  output from the lower data encoder 166, and outputs the same as the conversion codes D 1  and D 2  via the OR gates OR 31  and OR 32 . 
     Concretely, one input terminal of the AND gate A 41  is connected to one line (upper significant side) of the encoder line LN 156  generating the data for the redundant L mode of the upper data encoder 150, and the other input terminal is connected to the selection line LN 152  outputting the selection signal SEL 11  of the lower data encoder 165. 
     One input terminal of the AND gate A 42  is connected to one line (upper significant side) of the encoder line LN 157  generating the data for the non-redundant mode of the upper data encoder 150, and the other input terminal is connected to the selection line LN 153  outputting the selection signal SEL 12  of the lower data encoder 165. 
     One input terminal of the AND gate A 43  is connected to one line (upper data side) of the encoder line LN 158   generating the data for the redundant R mode of the upper data encoder 150, and the other input terminal is connected to the selection line LN 154  outputting the selection signal SEL 13  of the lower data encoder 165. 
     The outputs of these AND gates A 41  to A 43  are connected to the input terminals of the 3-input OR gate OR 31 . 
     Further, one input terminal of the AND gate A 44  is connected to the other line (lower data side) of the encoder line LN 156  generating the data for the redundant L mode of the upper data encoder 150, and the other input terminal is connected to the selection line LN 152  outputting the selection signal SEL 11  of the lower data encoder 165. 
     One input terminal of the AND gate A 45  is connected to the other line (lower data side) of the encoder line LN 157  generating the data for the non-redundant mode of the upper data encoder 150, and the other input terminal is connected to the selection line LN 153  outputting the selection signal SEL 12  of the lower data encoder 165. 
     One input terminal of the AND gate A 46  is connected to the other line (lower data side) of the encoder line LN 158  generating the data for the redundant R mode of the upper data encoder 150, and the other input terminal is connected to the selection line LN 154  outputting the selection signal SEL 13  of the lower data encoder 165. 
     The outputs of these AND gates A 44  to A 46  are connected to respective input terminals of the 3-input OR gate OR 32 . 
     The exclusive-OR gate EXO 31  obtains the exclusive-OR between the lower significant data BD 63  output from one line of the data line LN 151  of the lower data encoder 165 and the signal obtained by inverting the output level of the AND gate AU 31  or AU 33  of the upper data comparators 151 and 153 by the inverter 167 and outputs the result thereof as the lower data conversion code D 3 . 
     The exclusive-OR gate EXO 32  obtains the exclusive-OR between the lower significant data BD 64  output from the other line of the data line LN 151  of the lower data encoder 165 and the signal obtained by inverting the output level of the AND gate AU 31  or AU 33  of the upper data comparators 161 and 163 by the inverter 167 and outputs the result thereof as the lower data conversion code D 4 . 
     In these processings, the direction of application of the reference voltage is reverse between the first row and the third row along with the folded-back arrangement of the reference resistance columns in the second row and the fourth row of the switching blocks in the matrix circuit 170, and, therefore when the second row and the fourth row are selected by the control signal, it is carried out so as to invert the levels of the lower significant data BD 63  and BD 64  and output the same as the lower significant data conversion codes D 3  and D 4 . 
     Next, an explanation will be made of the operation by the above-described structure. 
     For example, when the sampling voltage V S  of the sampled analog signal is represented as V RB  &lt;V S  &lt;V 93 , the outputs of the comparators CU of the upper data comparators 161, 162, and 163 become all &#34;L&#34;, so that the digital signals are output, i.e., &#34;0&#34; is output from the AND gates AU 31  to AU 33 , and &#34;1&#34; is output from the AU 34 , respectively. 
     As a result, a digital signal such as [0001] is input to the upper data encoder 150. At the upper data encoder 150, using a so-called wired-OR circuit, [00] is generated in the two columns of the encoder line [LN 156  ] generating the redundant L mode data; [00] is generated in the two columns of the encoder line [LN 157  ] generating the non-redundant mode data; and [01] is generated in the two columns of the encoder line [LN 158  ] generating the redundant R mode data; respectively, which are output to the selection gate 166. 
     Also, when the sampling voltage V S  is represented as V 93  &lt;V S  &lt;V 92 , similarly the digital signals are output, i.e., &#34;0&#34; is output from the upper significant side AND gates AU 31 , AU 32 , and AU 34 , and &#34;1&#34; is output from the AU 33 , respectively. 
     As a result, a digital signal such as [0010] is input to the upper data encoder 150, and the upper significant data is output, i.e., [10] is output from the line [LN 156  ]; [01] is output from the line [LN 157  ]; and [00] is output from the line [LN 158  ], to the selection gate 166. 
     Further, when the sampling voltage V S  is represented as V 92  &lt;V S  &lt;V 91 , the digital signals are output, i.e., &#34;0&#34; is output from the upper data side AND gates AU 31 , AU 33 , and AU 34 , and &#34;1&#34; is output from the AU 92 , respectively. 
     As a result, a digital signal such as [0100] is input to the upper data encoder 100, and the upper significant data is output, i.e., [01] is output from the line [LN 156  ]; [10] is output from the line [LN 157  ]; and [11] is output from the line [LN 158  ], to the selection gate 166. 
     Similarly, when the sampling voltage V S  is represented as V 91  &lt;V S  &lt;V RT , the digital signals are output, i.e., &#34;0&#34; is output from the upper data side AND gates AU 32 , AU 33 , and AU 34 , and &#34;1&#34; is output from the AU 31 , respectively. 
     As a result, a digital signal such as [1000] is input to the upper data encoder 150, and the upper significant data is output, i.e., [11] is output from the line [LN 156  ]; [11] is output from the line [LN 157  ]; and [10] is output from the line [LN 156  ], to the selection gate 166. 
     In parallel with this, the transistors Q 153  of the respective switching blocks of the matrix circuit 170 connected to the control lines (x 31 , x 32 , x 33 , and x 34 ) at which the digital output signal has become &#34;1&#34; among the respective AND gates AU.sub.(31, 32, 33, 34) are controlled to turn ON in units of rows, and further a fine digitization of the quantization level is executed. 
     For example, when only the output of the AND gate AU 33  becomes the &#34;1&#34; level, the transistors Q 153  of the switching blocks S f31  to S f37  become ON, so that the reference voltages divided by the reference resistors R 127  to R 133  and the sampling voltage V S  are differentially amplified at the switching blocks S 31  to S 37  and compared by the lower data comparators 151 to 157. 
     Similarly, when the output of the AND gate AU 32  is at the &#34;1&#34; level, the switching blocks S f21  to S f27  are activated, so that a differential amplification operation is performed, and the comparison by the lower data comparators 151 to 157 is carried out. 
     In this way, in the lower data conversion codes, the sampled voltage V S  and the reference voltage divided by the reference resistance of that row are compared in units of rows of the switching blocks, so that the digital signal will be output from the AND gates AD 71  to AD 77  and AD 78  of the lower data comparators 151 to 157 as shown in FIG. 21. 
     At this time, where the level of the analog signal outputting the upper significant 2 bits of the conversion code is not changed from that of the analog signal when the lower significant 2 bits of the conversion code are output, the signal of the &#34;1&#34; level is output from one AND gate among the AND gates AD 73  to AD 76  of the lower data comparators 153 to 156 to the lower data encoder 165. 
     In this case, in the lower data encoder 165, only the selection line LN 153  becomes &#34;1&#34;. As a result, the selection signal SEL 12  is input to the selection gate 166 as the &#34;1&#34; level, and the selection signals SEL 11  and SEL 13  are input to the selection gate 166 as the &#34;0&#34; level. 
     In the selection gate 166, along with the fact that only the selection signal SEL 12  is input as the &#34;1&#34; level, only the AND gates A 42  and A 45  are activated. 
     To these AND gates A 42  and A 45 , the upper data side and lower data side of the upper significant data for the non-redundant mode generated in the line LN 157  of the upper data encoder 150 are respectively supplied. 
     Accordingly, in the selection gate 166, the respective bits of the upper significant data at the non-redundant mode are selected, and as a result, they are output as the upper significant data conversion codes D 1  and D 2  via the OR gates OR 31  and OR 32 . 
     Concretely, when the sampling voltage V S  of the analog signal V IN  is defined as V RB  &lt;V S  &lt;V 93 , the upper data conversion codes [D 1 , D 2  ] are output as [00]; when V 93  &lt;V S  &lt;V 92  stands, the upper data conversion codes [D 1 , D 2  ] are output as [01]; when V 92  &lt;V S  &lt;V 91  stands, the upper data conversion codes [D 1 , D 2  ] are output as [10]; and when V 91  &lt;V S  &lt;V RT  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [11]. 
     Also, in the selection gate 165, when the output of the AND gate A D3  of the lower data comparator 153 is &#34;1&#34;, the lower significant data BD 63  and BD 64  are generated as [11]; when the output of the AND gate AD 73  of the lower data comparator 154 is &#34;1&#34;, the lower significant data BD 63  and BD 64  are generated as [10]; when the output of the AND gate AD 75  of the lower data comparator 155 is &#34;1&#34;, the lower significant data BD 63  and BD 64  are generated as [01]; when the output of the AND gate AD 76  of the lower data comparator 156 is &#34;1&#34;, the lower significant data BD 63  and BD 64  are generated as [00]; and the data BD 63  is output to the exclusive-OR gate EXO 31 , and the data BD 64  is output to the exclusive-OR gate EXO 32  . 
     In the exclusive-OR gates EXO 31  and EXO 32 , when V RB  &lt;V S  &lt;V 93  and V 92  &lt;V S  &lt;V 91  stand, that is where the switching blocks S f41  to S f47  and S f21  to S f27  of the first row and third row from the bottom of the matrix circuit 170 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D 3  and D 4  while inverting the output level of the lower data encoder 165. 
     Contrary to this, when V 93  &lt;V S  &lt;V 92  and V 91  &lt;V S  &lt;V RT  stand, that is where the switching blocks S f31  to S f37  and S f11  to S f17  of the second row and fourth row from the bottom of the matrix circuit 170 are selected, since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 165 as they are and output as the lower significant data conversion codes D 3  and D 4 . 
     Also, at the time of conversion, in a case where V 93  &lt;V IN  &lt;V 92  when the upper significant 2 bits D 1  and D 2  are digitized and V 92  &lt;V IN  when the lower significant 2 bits D 3  and D 4  are digitized; or in a case where V 92  &lt;V IN  &lt;V 91  when the upper significant 2 bits D 1  and D 2  are digitized and V IN  &lt;V 92  when the lower significant 2 bits D 3  and D 4  are digitized, a signal of the &#34;1&#34; level is output from one AND gate among the AND gates AD 71  and AD 72  of the lower data comparators 151 and 152 to the lower data encoder 165. 
     In this case, in the lower data encoder 165, only the selection line LN 152  becomes &#34;1&#34;. As a result, the selection signal SEL 11  is input to the selection gate 166 as the &#34;1&#34; level, and the selection signals SEL 12  and SEL 13  are input to the selection gate 166 as the &#34;0&#34; level. 
     In the selection gate 166, along with the fact that only the selection signal SEL 11  is input as the &#34;1&#34; level, only the AND gates A 41  and A 44  are activated. 
     To these AND gates A 41  and A 44 , the upper data side and lower data side of the upper significant data for the redundant n mode generated in the line LN 156  of the upper data encoder 150 are respectively supplied. 
     Accordingly, in the selection gate 166, the respective bits of the upper significant data at the redundant n mode are selected, and as a result, they are output as the upper significant data conversion codes D 1  and D 2  via the OR gates OR 31  and OR 32 . 
     Concretely, when the sampling voltage V S  of the analog signal V IN  is defined as V RB  &lt;V S  &lt;V 93 , the upper data conversion codes [D 1 , D 2  ] are output as [00]; when V 93  &lt;V S  &lt;V 92  stands, the upper data conversion codes [D 1 , D 2  ] are output as [10]; when V 92  &lt;V S  &lt;V 91  stands, the upper data conversion codes [D 1 , D 2  ] are output as [01]; and when V 91  &lt;V S  &lt;V RT  stands, the upper data conversion codes [D 1 , D 2  ] are output as [11]. 
     Namely, at this redundant L mode, when V 93  &lt;V S  &lt;V 92  (when the output of the AND gate AU 33  is &#34;1&#34;), the upper data conversion code [D 1 , D 2  ] is corrected to a code [10]  which is larger than the output code [01] in the case of the non-redundancy by &#34;1&#34; and output; and when V 92  &lt;V S  &lt;V 91  (when the output of the AND gate AU 32  is &#34;1&#34;), the upper data conversion code [D 1 , D 2  ] is corrected to a code [01] which is smaller than the output code [10] in the case of the non-redundancy by &#34;1&#34; and output. 
     Also, in the selection gate 165, when the output of the AND gate AD 71  of the lower data comparator 151 is &#34;1&#34;, the lower significant data BD 63  and BD 64  are generated as [01]; and when the output of the AND gate AD 72  of the lower data comparator 152 is &#34;1&#34;, the lower significant data BD 63  and BD 64  are generated as [00], so that the data BD 63  is output to the exclusive OR gate EXO 31 , the data BD 63  is output to the exclusive-OR gate EXO 32 , which is subjected to the predetermined level adjustment function here and output as the lower data conversion codes D 3  and D 4 . 
     Also, at the time of conversion, in a case where V IN  &lt;V 93  when the upper significant 2 bits D 1  and D 2  are digitized and V 93  &lt;V IN  when the lower significant 2 bits D 3  and D 4  are digitized; or in a case where V 93  &lt;V IN  &lt;V 92  when the upper significant 2 bits D 1  and D 2  are digitized and V IN  &lt;V 93  when the lower significant 2 bits D 3  and D 4  are digitized; or in a case where V 92  &lt;V IN  &lt;V 91  when the upper significant 2 bits D 1  and D 2  are digitized and V 1  &lt;V IN  when the lower significant 2 bits D 3  and D 4  are digitized; or in a case where V 1  &lt;V IN  when the upper significant 2 bits D 1  and D 2  are digitized and V IN  &lt;V 91  when the lower significant 2 bits D 3  and D 4  are digitized, a signal of the &#34;1&#34; level is output from one AND gate among the AND gate AD 77  and AND gate AD 78  of the lower data comparator 157 to the lower data encoder 165. 
     In this case, in the lower data encoder 165, only the selection line LN 154  becomes &#34;1&#34;. As a result, the selection signal SEL 13  is input to the selection gate 166 as the &#34;1&#34; level, and the selection signals SEL 11  and SEL 12  are input to the selection gate 166 as the &#34;0&#34; level. 
     In the selection gate 166, along with the fact that only the selection signal SEL 13  is input as the &#34;1&#34; level, only the AND gates A 43  and A 46  are activated. 
     To these AND gates A 43  and A 46 , the upper data side and lower data side of the upper significant data for the redundant R mode generated in the line LN 103  of the upper data encoder 150 are respectively supplied. 
     Accordingly, in the selection gate 166, the respective bits of the upper significant data at the redundant R mode are selected, and as a result, they are output as the upper significant data conversion codes D 1  and D 2  via the OR gates OR 31  and OR 32 . 
     Concretely, when the sampling voltage V S  of the analog signal V IN  is defined as V RB  &lt;V S  &lt;V 93 , the upper data conversion codes [D 1 , D 2  ] are output as [01]; when V 93  &lt;V S  &lt;V 92  stands, the upper data conversion codes [D 1 , D 2  ] are output as [00]; when V 92  &lt;V S  &lt;V 91  stands, the upper data conversion codes [D 1 , D 2  ] are output as [11]; and when V 91  &lt;V S  &lt;V RT  stands, the upper data conversion codes [D 1 , D 2  ] are output as [10]. 
     Namely, at this redundant R mode, when V RB  &lt;V S  &lt;V 93  (when the output of the AND gate A U4  is &#34;1&#34;), the upper data conversion code [D 1 , D 2  ] is corrected to a code [01] which is larger than the output code [00] in the case of the non-redundancy by &#34;1&#34; and output, and when V 93  &lt;V S  &lt;V 92  (when the output of the AND gate AU 33  is &#34;1&#34;), the upper data conversion code [D 1 , D 2  ] is corrected to a code [00] which is smaller than the output code [01] in the case of the non-redundancy by &#34;1&#34; and output; and when V 92  &lt;V S  &lt;V 91  (when the output of the AND gate AU 32  is &#34;1&#34;), the upper data conversion code [D 1 , D 2  ] is corrected to a code [11] which is larger than the output code [10] in the case of the non-redundancy by &#34;1&#34; and output, and when V 91  &lt;V S  &lt;V RT  (when the output of the AND gate AU 31  is &#34;1&#34;), the upper data conversion code [D 1 , D 2  ] is corrected to a code [10] which is smaller than the output code [11] in the case of the non-redundancy by &#34;1&#34; and output. 
     Also, in the selection gate 165, when the output of the AND gate AD 77  of the lower data comparator 157 is &#34;1&#34;, the lower significant data BD 63  and BD 64  are generated as [11]; and when the output of the AND gate AD 78  of the lower data comparator 152 is &#34;1&#34;, the lower significant data BD 63  and BD 64  are generated as [10], so that the data BD 63  is output to the exclusive OR gate EXO 31 , the data BD 64  is output to the exclusive-OR gate EXO 32 , which is subjected to the predetermined level adjustment function here and output as the lower data conversion codes D 3  and D 4 . 
     As explained above, according to the present embodiment, so as to correct the upper significant data, the output data level of the encoder 150 and the output level of the selection signal of the lower data encoder 165 were set in advance so as to select an appropriate data from among three data, i.e., the left redundant data (data to be selected by the lower data encoder in the left part of the resistance column), normal data, and the right redundant data, and therefore it is possible to use the selection signal directly for the selection of the upper significant data without the use of the inverted gate and inhibit gate as in the conventional circuit. 
     Accordingly, an A/D converter circuit with which the input of the selection signal to the selection gate 166 is not delayed in relative to the output of the upper data encoder 150, the increase of speed of conversion processing can be achieved, and the decrease of the chip area and reduction of the power consumption can be achieved can be realized. 
     Note that, in the present embodiment, an explanation was made taking as an example an A/D converter circuit for four bits, but needless to say the present invention can be applied to a A/D converter circuit for more bits. 
     As explained above, according to the present invention, there are advantages that the inverted gate and inhibit gate which have been conventionally necessary become unnecessary, the increase of speed of conversion processing can be achieved, and the decrease of the chip area and reduction of the power consumption can be achieved. 
     An explanation will be made next of a seventh embodiment of the present invention. 
     FIGS. 22A-22C are circuit diagrams showing the seventh embodiment of the A/D converter circuit according to the present invention. 
     In FIG. 22, 180 denotes a matrix circuit; 181 and 182 denote upper data comparators as the data change point detection circuits; 183, an upper data encoder; 191 to 197 denote lower data comparators; 185, a lower data encoder; 186, a selection gate; 184, an inverter; R 141  to R 156  denote reference resistance elements; B U41  to B U43  and B D51  to B D58  denote multiple output pin buffers; OR 41  and OR 42  denote OR gates; and EXO 41  and EXO 42  denote exclusive-OR gates; respectively. 
     The matrix circuit 180 is constituted by the arrangement of 21 switching blocks S g11  to S g17 , S g21  to S g27 , and S g31  to S g37  in the form of a matrix comprising three rows and seven columns. 
     The respective switching blocks S g11  to S g17 , S g21  to S g27 , and S g31  to S g37  are constituted by differential type amplifiers comprising the npn-type transistors Q 161 , Q 162 , and Q 163 . 
     A reference voltage obtained by dividing the reference voltages V RT  to V RB  by the reference resistance elements R 141  to R 156  is supplied to the base of one side transistors Q 161  constituting a so-called differential pair of the respective switching blocks, and analog signals V IN  which are to be converted to the digital code are supplied to the base of the other side transistors Q 162 , respectively. 
     Also, the emitters of the transistors Q 161  and Q 162  are connected to each other, and the middle point of connection thereof is connected to the current source I via the transistor Q 163  switched by the control signals x 41  and x 42 , respectively. 
     To the collectors of the transistors Q 161  and Q 163 , the power source voltage V DD  is supplied via the resistance element r, the output of which is input to the comparators C D51  to C D57  of the seven lower data comparators 191 to 197 as mentioned later, which act also as the initial stage amplifiers of the lower data comparators 191 to 197. 
     Also, the collectors of the transistors Q 161  and Q 162  of the switching block at the second row from the bottom of the diagram are connected to the line in an opposite direction to that for the collector output of the transistors Q 161  and Q 162  of the switching blocks at the first row and third row, and a measure is devised so that the line of the serial reference resistance elements R 141  to R 156  to which the reference potentials V RT  to V RB  are applied can be formed by folding-back. 
     The reference resistance elements R 141  to R 156  are serially connected between the two reference potentials V RT  and V RB  and arranged by folding-back so as to extend over a predetermined number of rows, e.g., five rows in the present embodiment, to correspond to the matrix arrangement of the switching blocks in the matrix circuit 184. 
     Concretely, each two resistance elements R 156  and R 155  and R 142  and R 141  are serially connected to the first row and the fifth row from the bottom in the diagram, and the resistance elements R 154  to R 151 , R 150  to R 147 , and R 146  to R 143  are serially connected to the second row to the fourth row, respectively. 
     Viewing this folding-back arrangement of the resistance element columns from the reference potential V RB  terminal side positioned on the left end and lower end side of the matrix circuit 180, the wiring pattern extended in the right direction in the diagram is folded-back between the switching block column of the fourth column from the left in the diagram and the switching block column of the fifth column, and two resistance elements R 156  and R 155  are connected in series, whereby the first row of the resistance column is constituted. 
     The resistance column at the first row is folded-back between the switching block column of the third column and the switching block column of the second column, and four resistance elements R 154  to R 151  are connected in series between the switching block rows of the first row and the second row and, corresponding to the arrangement position of the switching blocks S g33  to S g36  of the first row, whereby the resistance column of the second row is constituted. 
     The resistance column of the second row is folded-back between the switching block column of the fifth column and the switching block column of the sixth column, and four resistance elements R 150  to R 147  are connected in series between the switching block rows at the first row and the second row and, corresponding to the arrangement position of the switching blocks S g26  to S g23  at the second row, whereby the resistance column of the third row is constituted. 
     The resistance column of the third row is folded-back between the switching block column of the third column and the switching block column of the second column, and four resistance elements R 146  to R 143  are connected in series corresponding to the arrangement position of the switching blocks S 13  to S 16  at the third row, whereby the resistance column of the fourth row is constituted. 
     The resistance column of the fourth row is folded-back between the switching block column of the fifth column and the switching block column of the sixth column, four resistance elements R 142  to R 141  are connected in series corresponding to the arrangement position of the switching blocks S g16  to S g15  at the third row, and one end of the resistance element R 1  is connected to the terminal of the reference potential V RT , whereby the resistance column of the fifth row is constituted. 
     Namely, the resistance columns at the first row and the fifth row are arranged at a deviation of a half cycle with respect to the resistance columns at the second row to the fourth row so that the position exhibiting the lowest value of the reference voltage (connection point between the reference potential V RB  terminal and the resistance element R 156 ) and the position exhibiting the highest value (connection point between the reference potential V RT  terminal and the resistance element R 141 ) are positioned at an intermediate point in the row direction of the switching blocks arranged in the form of the matrix. 
     Such a structure of arrangement of the resistance columns is made for the purpose of dividing the switching block columns comprising seven columns into the group comprising the switching block columns from the first column to the fourth column and the group of the switching block columns from the fifth column to the seventh column of the switching point between the upper data and lower data as will be mentioned later. 
     Also, the voltages V 128  and V 127  generated between the rows of the fourth row and the third row and between the rows of the third row and the second row of the resistance columns are supplied to the upper data comparators 181 and 182 as the reference voltages obtained by dividing the reference potentials V RT  to V RB  by rough quantization, respectively. 
     In the structure of FIG. 1, when assuming that the voltage between the reference potentials V RT  to V RB  is V REF , the respective reference voltages V 128  and V 127  become the following values, respectively: 
     
         V.sub.128 =(10/16)·V.sub.REF 
    
     
         V.sub.127 =(6/16)·V.sub.REF 
    
     Further, wiring is carried out so that the respective reference voltages V 111  to V 125  divided by the reference resistance elements R 141  to R 156  are supplied to the base of the transistor Q 161  of the predetermined switching block. 
     Concretely, a reference voltage V 111  [=(15/16)·V REF  ] generated at the middle point of connection between the resistance elements R 141  and R 142  is supplied to the base of the transistor Q 161  of the switching block S g17 . 
     A reference voltage V 112  [=(14/16)·V REF  ] generated at the connection between the resistance elements R 142  and R 143  is supplied to the base of the transistor Q 161  of the switching block S g16 . 
     A reference voltage V 113  [=(13/16)·V REF  ] generated at the connection between the resistance elements R 143  and R 144  is supplied to the base of the transistor Q 161  of the switching block S g15 . 
     A reference voltage V 114  [=(12/16)·V REF  ] generated at the connection between the resistance elements R 144   and R 145  is supplied to the base of the transistor Q 161  of the switching block S g14 . 
     A reference voltage V 115  [=(11/16)·V REF  ] generated at the connection between the resistance elements R 145  and R 146  is supplied to the bases of the transistors Q 161  of the switching blocks S g13  and S g21 . 
     A reference voltage V 116  [=V 128  =(10/16)·V REF  ] generated at the connection between the resistance elements R 146  and R 147  is supplied to the bases of the transistors Q 161  of the switching blocks S g12  and S g22 . 
     A reference voltage V 117  [=(9/16)·V REF  ] generated at the connection between the resistance elements R 147  and R 148  is supplied to the bases of the transistors Q 161  of the switching blocks S g4  and S g23 . 
     A reference voltage V 118  [=(8/16)·V REF  ] generated at the connection between the resistance elements R 148  and R 149  is supplied to the base of the transistor Q 161  of the switching block S g24 . 
     A reference voltage V 119  [=(7/16)·V REF  ] generated at the connection between the resistance elements R 149  and R 150  is supplied to the bases of the transistors Q 161  of the switching blocks S g25  and S g37 . 
     A reference voltage V 120  [=V 127  =(6/16)·V REF  ] generated at the connection between the resistance elements R 150  and R 151  is supplied to the bases of the transistors Q 161  of the switching blocks S g26  and S g36 . 
     A reference voltage V 121  [=(5/16)·V REF  ] generated at the connection between the resistance elements R 151  and R 152  is supplied to the bases of the transistors Q 161  of the switching blocks S g27  and S g35 . 
     A reference voltage V 122  [=(4/16)·V REF  ] generated at the connection between the resistance elements R 152  and R 153  is supplied to the base of the transistor Q 161  of the switching block S g34 . 
     A reference voltage V 123  [=(3/16)·V REF  ] generated at the connection between the resistance elements R 153  and R 154  is supplied to the base of the transistor Q 161  of the switching block S g33 . 
     A reference voltage V 124  [=(2/16)·V REF  ] generated at the connection between the resistance elements R 154  and R 155  is supplied to the base of the transistor Q 161  of the switching block S g32 . 
     A reference voltage V 125  [=(1/16)·V REF  ] generated at the connection between the resistance elements R 155  and R 156  is supplied to the base of the transistor Q 161  of the switching block S g31 . 
     The upper data comparators 181 and 182 respectively are provided with comparators C U41  and C U42 , complementary-type output amplifiers CA 58 , 59, and AND gates AU 41  and AU 42 . Note that, for the reasons described later, the upper data comparator 181 acts also as the upper data comparator for the uppermost row, and the upper data comparator 182 acts also as the upper data comparator for the lowermost row. 
     An analog signal V IN  is supplied to one input of the comparator CU 41  of the upper data comparator 181, and a reference voltage V 128  [=(10/16)·V REF  ] obtained by dividing the reference potentials V RT  to V RB  by the rough quantization is supplied to the other input. 
     The analog signal V IN  is supplied to one input of the comparator CU 42  of the upper data comparator 182, and a reference voltage V 127  [=(6/16)·V REF  ] obtained by dividing the reference potentials V RT  to V RB  by the rough quantization is supplied to the other input. 
     The output of the comparator CU 41  of the upper data comparator 181 is connected to the input of the output amplifier CA 58 , the positive output thereof is connected to both inputs of a 2-input AND gate AU 41 , and the negative output is connected to one input of the 2-input AND gate AU 42  of the upper data comparator 182. 
     The output of comparator CU 42  of the upper data comparator 182 is connected to the input of the output amplifier CA 42 , the positive output thereof is connected to the other input of the 2-input AND gate AU 42 , and the negative output is connected to the both inputs of the 2-input AND gate AU 43 . 
     The outputs of the respective comparators CU 41  and CU 42  of the upper data comparators 181 and 182 constituted in this way become the level of &#34;H&#34; or &#34;L&#34; corresponding to the level of the sampled analog signal V IN , and only one among the respective AND gates AU 41  to AU 43  outputs the &#34;1&#34; level. 
     The output of the AND gate AU 41  of the upper data comparator 181 is connected via the buffer BU 41  to the upper data encoder 183 and, at the same time, connected to the bases of the transistors Q 163  of the switching blocks S g11  to S g17 . 
     The output of the AND gate AU 42  of the upper data comparator 182 is connected via the buffer BU 42  to the upper data encoder 183 and, at the same time, connected to the bases of the transistors Q 163  of the switching blocks S g21  to S g27  and connected to the input of the inverter 184 via the buffer. 
     The AND gate AU 43  of the upper data comparator 183 is connected via the buffer BU 43  to the upper data encoder 183 and, at the same time, connected to the bases of the transistors Q 163  of the switching blocks S g31  to S g37 . 
     The upper data encoder 183 is constituted by an encoder line LN 161  generating the data for an L (left) mode, and an encoder line LN 162  generating the data for an R (right) mode. 
     Namely, in the upper data encoder 183, respective encoder lines LN 161  and LN 162  are set up corresponding to a first group of from the first column to the fourth column arranged on the left side from the center of the matrix circuit 180, and a second group of from the fifth column to the seventh column arranged on the right side among the switching blocks S g11  to S g17 , S g21  to S g27  and S g31  to S g37  arranged in the matrix circuit 180. 
     FIG. 23 shows the correspondence between the outputs of the respective AND gates AU 41 , AU 42 , and AU 43  of the upper data comparators 181 and 182 and the set output data code pattern of the respective encoder lines LN 161  and LN 142  of the upper data encoder 183. 
     The data is set in a manner that, in accordance with the direction of transition of the reference voltage level by the respective reference resistance elements in the first row to the fifth row (the second row to the fourth row in the present embodiment) from the bottom among the serially connected reference resistance element groups which are folded-back so that the number of rows becomes five, concretely an orientation (hereinafter referred to as a direction) of transition of the reference voltage from the low potential side to the high potential side, so that (data of L mode)&lt;(data of R mode) and (data of L mode)&lt;(data of R mode) stand. 
     In the structure of FIG. 22, the first row from the bottom comprising the resistance elements R 156  and R 155 , the third row comprising the resistance elements R 150  to R 147 , and the fifth row comprising the resistance elements R 142  and R 141  have the same direction, and the second row comprising the resistance elements R 154  to R 151  and the fourth row comprising the resistance elements R 146  to R 143  have the same direction. 
     Accordingly, the data setting level in the case where the AND gate AU 42  corresponding to the third row is at the &#34;1&#34; level is set so that (data of L mode)&gt;(data of R mode) stands. 
     Contrary to this, the data setting level in the case where the AND gates AU 43  and AU 41  corresponding to the second row and the fourth row are at the &#34;1&#34; level is set so that (data of L mode)&lt;(data of R mode) stands. 
     The lower data comparators 191 to 197 are respectively provided with comparators CD 51  to CD 57 , complementary-type output amplifiers CA 51  to 57, and AND gates AD 81  to AD 87 . 
     To one input of the comparator CD 51  of the lower data comparator 191 is supplied the collector output of the transistor Q 161  of the switching block S g21  at the first column of the matrix circuit 180 and the collector output of the transistor Q 162  of the switching blocks S g11  and S g31 , and to the other input is supplied the collector outputs of the transistors Q 161  of the switching blocks S g11  and S g31  and the collector output of the transistor Q 162  of the switching block S g21 . 
     To one input of the comparator CD 52  of the lower data comparator 192 is supplied the collector output of the transistor Q 161  of the switching block S g22  at the second column of the matrix circuit 180 and the collector output of the transistor Q 162  of the switching blocks S g12  and S g32 , and to the other input is supplied the collector outputs of the transistors Q 161  of the switching blocks S g12  and S g32  and the collector output of the transistor Q 162  of the switching block S g22 . 
     To one input of the comparator CD 53  of the lower data comparator 193 is supplied the collector output of the transistor Q 161  of the switching block S g23  at the third column of the matrix circuit 180 and the collector output of the transistor Q 162  of the switching blocks S g13  and S g33 , and to the other input is supplied the collector outputs of the transistors Q 161  of the switching blocks S g13  and S g33  and the collector output of the transistor Q 162  of the switching block S g23 . 
     To one input of the comparator CD 54  of the lower data comparator 194 is supplied the collector output of the transistor Q 161  of the switching block S g24  at the fourth column of the matrix circuit 180 and the collector output of the transistor Q 162  of the switching blocks S g14  and S g34 , and to the other input is supplied the collector outputs of the transistors Q 161  of the switching blocks S g14  and S g34  and the collector output of the transistor Q 162  of the switching block S g24 . 
     To one input of the comparator CD 55  of the lower data comparator 195 is supplied the collector output of the transistor Q 161  of the switching block S g25  at the fifth column of the matrix circuit 180 and the collector output of the transistor Q 162  of the switching blocks S g15  and S g35 , and to the other input is supplied the collector outputs of the transistors Q 161  of the switching blocks S g15  and S g35  and the collector output of the transistor Q 162  of the switching block S g25 . 
     To one input of the comparator CD 56  of the lower data comparator 196 is supplied the collector output of the transistor Q 161  of the switching block S g26  at the sixth column of the matrix circuit 180 and the collector output of the transistor Q 162  of the switching blocks S g16  and S g36 , and to the other input is supplied the collector outputs of the transistors Q 161  of the switching blocks S g16  and S g36  and the collector output of the transistor Q 162  of the switching block S g26 . 
     To one input of the comparator CD 57  of the lower data comparator 197 is supplied the collector output of the transistor Q 161  of the switching block S g27  at the seventh column of the matrix circuit 180 and the collector output of the transistor Q 162  of the switching blocks S g17  and S g37 , and to the other input is supplied the collector outputs of the transistors Q 161  of the switching blocks S g17  and S g37  and the collector output of the transistor Q 162  of the switching block S g27 . 
     The output of the comparator CD 51  of the lower data comparator 191 is connected to the input of the output amplifier CA 51  , the positive output thereof is connected to both inputs of the 2-input AND gate AD 81 , and the negative output is connected to one input of the 2-input AND gate AD 82  of the lower data comparator 192. 
     The output of the comparator CD 52  of the lower data comparator 192 is connected to the input of the output amplifier CA 52 , the positive output thereof is connected to the other input of the 2-input AND gate AD 82 , and the negative output is connected to one input of the 2-input AND gate AD 83  of the lower data comparator 193. 
     The output of the comparator CD 53  of the lower data comparator 193 is connected to the input of the output amplifier CA 53 , the positive output thereof is connected to the other input of the 2-input AND gate AD 83 , and the negative output is connected to one input of the 2-input AND gate AD 84  of the lower data comparator 194. 
     The output of the comparator CD 54  of the lower data comparator 194 is connected to the input of the output amplifier CA 54 , the positive output thereof is connected to the other input of the 2-input AND gate AD 84 , and the negative output is connected to one input of the 2-input AND gate AD 85  of the lower data comparator 195. 
     The output of the comparator CD 55  of the lower data comparator 195 is connected to the input of the output amplifier CA 55 , the positive output thereof is connected to the other input of the 2-input AND gate AD 85 , and the negative output is connected to one input of the 2-input AND gate AD 86  of the lower data comparator 196. 
     The output of the comparator CD 56  of the lower data comparator 196 is connected to the input of the output amplifier CA 56 , the positive output thereof is connected to the other input of the 2-input AND gate AD 86 , and the negative output is connected to one input of the 2-input AND gate AD 87  of the lower data comparator 197. 
     The output of the comparator CD 57  of the lower data comparator 197 is connected to the input of the output amplifier CA 57 , the positive output thereof is connected to the other input of the 2-input AND gate AD 87 , and the negative output is connected to the both inputs of the 2-input AND gate AD 88 . 
     The outputs of the respective comparators CD 51  to CD 57  of the lower data comparators 191 to 197 constituted in this way become the level of &#34;H&#34; or &#34;L&#34; corresponding to the level of 2 inputs, and only one of the respective AND gates AD 81  to AD 88  outputs the &#34;1&#34; level. 
     The outputs of the AND gates AD 81  to AD 87  and AD 88  of the lower data comparators 191 to 197 are connected via the buffers B D1  to B D8 , to the lower data encoder 185. 
     [0060] 
     The lower data encoder 185 is constituted by a data line LN 163  generating lower significant data BD 73  and BD 74  ; a selection line LN 164  generating the selection signal SEL 21  indicating that either of the outputs of the AND gates AD 81  to AD 84  of the lower data comparators 191 to 194 becomes &#34;1&#34;; and a selection line LN 165  generating the selection signal SEL 22  indicating that either of the outputs of the AND gates AD 85  to AD 87  and AD 88  of the lower data comparators 195 to 197 becomes &#34;1&#34;. 
     FIG. 24 shows the correspondence between the outputs of the AND gates AU 41  to AU 43  on the upper data side and the outputs of the AND gates AD 81  to AD 88  on the lower data side, and the output conversion code data. 
     As mentioned above, in the matrix circuit 180 in the present embodiment, the respective switching blocks are divided to two in the row direction. At this division point C, as seen from FIG. 24, when paying attention to the upper significant 2 bits of the output conversion codes D 1  to D 4 , division is made at the point at which the value of the upper significant 2 bits is switched. 
     Also, originally, it is necessary to make also the number of the upper data side AND gates (number of the upper data comparators) five, i.e., the same number in accordance with the number five of rows of the resistance columns, but in the present embodiment, two AND gates A L  and A H  corresponding to the resistance columns at the first row (lowermost stage) and the fifth row (uppermost stage) are omitted. As a result, two rows worth of the switching blocks which are to be arranged in the lowermost stage and uppermost stage are omitted. 
     An explanation will be made below of the reason why the AND gate and the switching block can be omitted using FIG. 24. 
     Here, at first, assume a structure in which a single row of the switching blocks is provided at the uppermost stage and, at the same time, corresponding to this, an upper data comparator having an AND gate A H  and a buffer for driving the upper data encoder 183 are provided. 
     In such a structure, when considering a case where the input analog signal V IN  is larger than the reference voltage V 112  (V IN  &gt;V 112 ), the comparator output becomes &#34;H&#34; and the output of the AND gate A H  becomes the &#34;1&#34; level. The output of this case is one among four types of from [1111] to [1100] as shown in FIG. 24. 
     When paying attention to these four types of data, the data are similar to the data obtained where the output of the AND gate AU 41  of the upper data comparator 111 in one lower stage is at the &#34;1&#34; level and either of the outputs of the lower significant side AND gate AD 85  to AD 88  is at the &#34;1&#34; level. 
     Accordingly, where the AND gate A H  in the upper most stage becomes the &#34;1&#34; level, this means that it is sufficient if one lower stage of the switching blocks S g11  to S g17  and the buffer BU 41  are activated instead of activation of the switching block at the uppermost stage and the buffer for driving the upper data encoder 183. 
     This means that if the sum of the output of the AND gate A H  and the output of the AND gate AU 41  is given to the switching blocks S g11  to S g17  and the buffer BU 41 , the switching block corresponding to the uppermost stage and the buffer for driving the upper data encoder become unnecessary. 
     Namely, in a case where V IN  &gt;V 128  (=V 116 ), it is sufficient if the switching blocks S g11  to S g17  and the buffer BU 41  are activated as in the present embodiment, and it is not necessary to compare the input analog signal V IN  with the reference voltage V 112 , and therefore also the upper data comparator corresponding to the uppermost stage becomes unnecessary. 
     Similarly, assume a structure in which a single row of the switching blocks is provided in the lower most stage, and the upper data comparator having the AND gate A L  is provided corresponding to this. 
     In such a structure, when considering a case where the input analog signal V IN  is smaller than the reference voltage V 124  (V IN  &lt;V 124 ), the comparator output becomes &#34;L&#34; and the output of the AND gate A L  becomes the &#34;1&#34; level. The output of this case is one among four types of from [0011] to [0000] as shown in FIG. 24. 
     Paying attention to these four types of data, these data are similar to the data obtained in a case where the output of the AND gate AU 43  in one upper stage is at the &#34;1&#34; level and one of the outputs of the lower data side AND gates AD 81  to AD 84  is at the &#34;1&#34; level. 
     Accordingly, where the AND gate A L  in the lowermost stage becomes the &#34;1&#34; level, this means that it is sufficient if one upper stage of the switching blocks S g31  to S g37  and the buffer BU 43  are activated instead of activation of the switching block at the uppermost stage and the buffer for driving the upper data encoder 183. 
     This means that if the sum of the output of the AND gate A L  and the output of the AND gate AU 43  is given to the switching blocks S g31  to S g37  and the buffer BU 43 , the switching block corresponding to the lowermost stage and the buffer for driving the upper data encoder become unnecessary. 
     Namely, in a case where V IN  &lt;V 127  (=V 120 ), it is sufficient if the switching blocks S g31  to S g37  and the buffer BU 43  are activated as in the present embodiment, and it is not necessary to compare the input analog signal V IN  with the reference voltage V 124 . Therefore, also the upper data comparator corresponding to the lowermost stage becomes unnecessary. 
     The selection gate 186 is constituted by AND gates A 51  to A 54 , selects a single upper significant data from among the respective upper significant data of the L mode and R mode output from the upper data encoder 183 using the selection signals SEL 21  and SEL 22  output from the lower data encoder 185, and outputs the same via the OR-gates OR 41  and OR 42  as the conversion codes D 1  and D 2 . 
     Concretely, one input terminal of the AND gate A 51  is connected to one line (upper data side) of the encoder line LN 161  generating the data for the L mode of the upper data encoder 183, and the other input terminal is connected to the selection line LN 164  outputting the selection signal SEL 21  of the lower data encoder 185. 
     One input terminal of the AND gate A 42  is connected to one line (upper significant side) of the encoder line LN 162  generating the data for the R mode of the upper data encoder 183, and the other input terminal is connected to the selection line LN 165  outputting the selection signal SEL 22  of the lower data encoder 185. 
     The outputs of these AND gates A 51  and A 52  are connected to the respective input terminals of the 2-input OR-gate OR 41 . 
     One input terminal of the AND gate A 53  is connected to the other line (lower data side) of the encoder line LN 161  generating the data for the L mode of the upper data encoder 183, and the other input terminal is connected to the selection line LN 164  outputting the selection signal SEL 21  of the lower data encoder 185. 
     One input terminal of the AND gate A 54  is connected to the other line (lower significant side) of the encoder line LN 162  generating the data for the R mode of the upper data encoder 183, and the other input terminal is connected to the selection line LN 165  outputting the selection signal SEL 22  of the lower data encoder 185. 
     The outputs of these AND gates A 53  and A 54  are connected to the respective input terminals of the 2-input OR-gate OR 42 . 
     The exclusive-OR gate EXO 41  obtains the exclusive-OR between the lower significant data BD 73  output from one line of the data line LN 163  of the lower data encoder 185 and the signal obtained by inverting the output level of the AND gate A U2  of the upper data comparator 182 by the inverter 184 and outputs the result thereof as the lower data conversion code D 3 . 
     The exclusive-OR gate EXO 42  obtain the exclusive-OR between the lower significant data BD 74  output from the other line of the data line LN 163  of the lower data encoder 185 and the signal obtained by inverting the output level of the AND gate AU 42  of the upper data comparator 182 by the inverter 184 and outputs the result thereof as the lower data conversion code D 4 . 
     Next, an explanation will be made of the operation by the above-described structure. 
     For example, when the sampling voltage V S  of the sampled analog signal is represented as V RB  &lt;V S  &lt;V 127 , the outputs of the comparators CU 41  and CU 42  of the upper data comparators 181 and 182 become all &#34;L&#34;, so that the digital signals are output, i.e. , &#34;0&#34; is output from the AND gates AU 41  to AU 42 , and &#34;1&#34; is output from the AND gate AU 43 , respectively. 
     As a result, a digital signal such as [001] is input to the upper data encoder 183. At the upper data encoder 183, using a so-called wired-OR circuit, [00] is generated in the two columns of encoder lines [LN 161  ] generating the L mode data; and [01] is generated in the two columns of encoder lines [LN 162  ] generating the R mode data; respectively, which are output to the selection gate 183. 
     Also, when the sampling voltage V S  is represented as V 127  &lt;V S  &lt;V 128 , the output of the comparator CU 1  of the upper data comparator 181 becomes &#34;L&#34;, and the output of the comparator CU 2  of the upper data comparator 182 becomes &#34;H&#34;, so that the digital signals are output, i.e., &#34;0&#34; is output from the AND gates AU 41  to AU 43  of the upper data comparator 181, and &#34;1&#34; is output from the AND gate AU 42  of the upper data comparator 182, respectively. 
     As a result, a digital signal such as [010] is input to the upper data encoder 183. At the upper data encoder 183, using a so-called wired-OR circuit, [10] is generated in the two columns of encoder lines [LN 161  ] generating the L mode data; and [01] is generated in the two columns of encoder lines [LN 162  ] generating the R mode data; respectively, which are output to the selection gate 183. 
     Also, when the sampling voltage V S  is represented as V 128  &lt;V S  &lt;V RT , the output of the comparator CU 41  of the upper data comparator 181 becomes &#34;H&#34;, and the output of the comparator CU 42  of the upper data comparator 182 becomes &#34;L&#34;, so that the digital signals are output, i.e., &#34;1&#34; is output from the AND gate AU 41  of the upper data comparator 181, and &#34;0&#34; is output from the AND gates AU 42  and AU 43  of the upper data comparator 182, respectively. 
     As a result, a digital signal such as [100] is input to the upper data encoder 183. At the upper data encoder 183, using a so-called wired-OR circuit, [10] is generated in the two columns of encoder lines [LN 161  ] generating the L mode data; and [11] is generated in the two columns of encoder lines [LN 162  ] generating the R mode data; respectively, which are output to the selection gate 183. 
     In parallel with this, the transistors Q 163  of the respective switching blocks of the matrix circuit 180 connected to the control lines (x 41 , x 42 , and x 43 ) at which the digital output signal has become &#34;1&#34; among the respective AND gates AU.sub.(41, 42, 43) are controlled to turn ON in units of rows, and further a fine digitization of the quantization level is executed. 
     For example, when only the output of the AND gate AU 43  becomes the &#34;1&#34; level, the transistors Q 163  of the switching blocks S g31  to S g17  become ON, so that the reference voltages V 119  to V 125  divided by the reference resistors R 149  to R 156  and the sampling voltage V S  are differentially amplified at the switching blocks S g31  to S g37  and compared by the lower data comparators 191 to 197. 
     Similarly, when the output of the AND gate AU 42  is at the &#34;1&#34; level, the switching blocks S g21  to S g27  are activated, so that the differential amplification operation is performed, and the comparison by the lower data comparator 191 to 197 is carried out. 
     In this way, in the lower data conversion codes, the sampled voltage V S  and the reference voltage divided by the reference resistance of that row are compared in units of rows of the switching blocks, so that a digital signal in accordance with the results of comparison will be output from the AND gates AD 81  to AD 87  and AD 88  of the lower data comparators 191 to 197. 
     At this time, in a case where the input analog signal V IN  when converting the upper significant 2 bits D 1  and D 2  is defined as V IN  &lt;V 127 , and the analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as V IN  &lt;V 122 , or in a case where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 127  &lt;V IN  &lt;V 128 , and the analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as V 118  &lt;V IN , or in a case where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 128  &lt;V IN , and the analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as V IN  &lt;V 114 , and the signal of &#34;1&#34; level is output from a single AND gate among the AND gates AD 81  to AD 84  of the lower data comparators 191 to 194 to the lower data encoder 185, in the lower data encoder 185, the selection line LN 164  becomes &#34;1&#34;. 
     As a result, the selection signal SEL 21  is input to the selection gate 186 as the &#34;1&#34; level, and the selection signal SEL 22  is input to the selection gate 186 as the &#34;0&#34; level. 
     In the selection gate 186, along with the fact that only the selection signal SEL 21  is input as the &#34;1&#34; level, only the AND gates A 51  and A 53  are activated. 
     To these AND gates A 51  and A 53 , the bit data of the upper data side and lower data side of the upper significant data for the L mode generated in the line LN 121  of the upper data encoder 183 are respectively supplied. 
     Accordingly, in the selection gate 186, the respective bits of the upper significant data at the L mode are selected, and as a result, they are output as the upper significant data conversion codes D 1  and D 2  via the OR gates OR 41  and OR 42 . 
     Concretely, when the sampling voltage V S  of the analog signal V IN  is defined as V RB  &lt;V S  &lt;V 127 , the upper data conversion codes [D 1 , D 2  ] are output as [00]; when V 127  &lt;V S  &lt;V 128  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [10]; and when V 128  &lt;V S  &lt;V RT  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [10]. 
     Also, in the lower data encoder 185, when the output of the AND gate AD 81  of the lower data comparator 191 is &#34;1&#34;, the lower significant data BD 73  and BD 74  are generated as [11]; when the output of the AND gate AD 82  of the lower data comparator 192 is &#34;1&#34;, the lower significant data BD 73  and BD 74  are generated as [10]; when the output of the AND gate AD 83  of the lower data comparator 193 is &#34;1&#34;, the lower significant data BD 73  and BD 74  are generated as [01]; and when the output of the AND gate AD 84  of the lower data comparator 194 is &#34;1&#34;, the lower significant data BD 73  and BD 74  are generated as [00], and the data BD 73  is output to the exclusive-OR gate EXO 41 , and the data BD 74  is output to the exclusive-OR gate EXO 42 . 
     In the exclusive-OR gates EXO 41  and EXO 42 , when V RB  &lt;V S  &lt;V 127  and V 128  &lt;V S  &lt;V RT  stand, that is where the switching blocks S g31  to S g37  and S g11  to S g17  at the first row and third row from the bottom of the matrix circuit 180 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D 3  and D 4  while inverting the output level of the lower data encoder 185. 
     Contrary to this, when V 127  &lt;V S  &lt;V 128  stands, that is where the switching blocks S g21  to S g27  at the second row from the bottom of the matrix circuit 180 are selected, since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 185 level and output as the lower significant data conversion codes D 3  and D 4 . 
     Also, in a case where the input analog signal V IN  when converting the upper significant 2 bits D 1  and D 2  is defined as V IN  &lt;V 127 , and the analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as V 122  &lt;V IN , or in a case where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as  127  &lt;V IN  &lt;V 128 , and the analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as V IN  &lt;V 118  ; or in a case where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 128  &lt;V IN , and the analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as V 114  &lt;V IN , and the signal of &#34;1&#34; level is output from a single AND gate among the AND gates AD 85  to AD 87  and AND gate AD 88  of the lower data comparators 195 to 197 to the lower data encoder 185, in the lower data encoder 185, the selection line LN 165  becomes &#34;1&#34;. 
     As a result, the selection signal SEL 22  is input to the selection gate 186 as the &#34;1&#34; level, and the selection signal SEL 21  is input to the selection gate 186 as the &#34;0&#34; level. 
     In the selection gate 186, along with the fact that only the selection signal SEL 22  is input as the &#34;1&#34; level, only the AND gates A 52  and A 54  are activated. 
     To these AND gates A 52  and A 54 , the bit data of the upper data side and lower data side of the upper significant data for the R mode generated in the line LN 162  of the upper data encoder 183 are respectively supplied. 
     Accordingly. in the selection gate 186, the respective bits of the upper significant data at the R mode are selected, and as a result, they are output as the upper significant data conversion codes D 1  and D 2  via the OR gates OR 4  1 and OR 42 . 
     Concretely, when the sampling voltage V S  of the analog signal V IN  is defined as V RB  &lt;V S  &lt;V 127 , the upper data conversion codes [D 1 , D 2  ] are output as [01]; when V 127  &lt;V S  &lt;V 128  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [01]; and when V 128  &lt;V S  &lt;V RT  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [11]. 
     Also, in the lower data encoder 185, when the output of the AND gate AD 85  of the lower data comparator 195 is &#34;1&#34;, the lower significant data BD 73  and BD 74  are generated as [11]; when the output of the AND gate AD 86  of the lower data comparator 196 is &#34;1&#34;, the lower significant data BD 73  and BD 74  are generated as [10]; when the output of the AND gate AD 87  of the lower data comparator 197 is &#34;1&#34;, the lower significant data BD 73  and BD 74  are generated as [01]; and when the output of the AND gate AD 88  is &#34;1&#34;, the lower significant data BD 73  and BD 74  are generated as [00], and the data BD 73  is output to the exclusive-OR gate EXO 41 , and the data BD 74  is output to the exclusive-OR gate EXO 42 . 
     In the exclusive-OR gates EXO 41  and EXO 42 , when V RB  &lt;V S  &lt;V 127  and V 128  &lt;V S  &lt;V RT  stand, that is where the switching blocks S g31  to S g37  and S g11  to S g17  of the first row and third row from the bottom of the matrix circuit 180 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D 3  and D 4  while inverting the output level of the lower data encoder 185. 
     Contrary to this, when V 127  &lt;V S  &lt;V 128  stands, that is where the switching blocks S g21  to S g27  at the second row from the bottom of the matrix circuit 180 are selected. since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 185 as they are and output as the lower significant data conversion codes D 3  and D 4 . 
     As explained above, according to the present embodiment, the lower data codes are divided to two groups, signals SEL 21  and SEL 22  for selecting the L mode data and R mode data are output from the lower data encoder 185 obtaining this group of conversion codes, so that the L mode data and R mode data output from the upper data encoder 183 are selected, thereby obtaining the upper data conversion codes D 1  and D 2 , and therefore it is possible to use the selection signal directly for the selection of the upper significant data without the use of the inverted gate and inhibit gate as in the conventional circuit. 
     Accordingly, the input of the selection signal to the selection gate 186 is not delayed relative to the output of the upper data encoder 183, and thus the increase of speed of conversion processing can be achieved. 
     Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, the number of selection signals can be reduced to two, and also the number of the upper data codes to be selected and the number of the input gates of the selection gate can be reduced to two. 
     Further, the upper data comparator 181 detecting the change of the data between the third row and second row acts also as the upper data comparator for the uppermost stage of the matrix circuit 180, and the upper data comparator 182 detecting the change of the data between the second row and first row acts also as the upper data comparator for the lowermost stage of the matrix circuit 180, and therefore the number of the upper data comparators and the number of rows of the switching blocks which conventionally had to be (2 a  -1) and 2 a , respectively can be reduced to (2 a  -2) and (2 a  -1) rows, respectively. 
     Accordingly, there is an advantage that an A/D converter circuit with which the reduction of the chip area and the reduction of the power consumption can be achieved can be realized. 
     An explanation will next be made of an eighth embodiment of the present invention. 
     FIGS. 25A-25C are circuit diagrams showing the eighth embodiment of the A/D converter circuit according to the present invention. 
     The point of difference of the present embodiment from the above-mentioned seventh embodiment resides in the constitution that the number of the selection lines of the lower data encoder 205 is reduced to only one line, i.e., LN 174 , to generate only one selection signal SEL 31  from among the selection signals, and a signal obtained by inverting the level of the selection signal SEL 31  at the inverter 218 is supplied as the signal in place of the selection signal SEL 22  to the other inputs of the AND gates A 62  and A 64  of the selection gate 260. 
     According to the present eighth embodiment, in addition to the effect of the above-described seventh embodiment, a simpler structure can be realized, and the chip area can be further reduced. 
     Note that, in the above-mentioned first and second embodiments, an explanation was made taking as an example an A/D converter circuit for four bits, but needless to say the present invention can be applied to an A/D converter circuit for more bits as well. 
     Also, in the above-mentioned seventh and eighth embodiments, the structure in which the other output pin buffers are arranged on the input side of the upper data encoder and the lower data encoder was shown, but these other output pin buffers are provided so as to reliably drive the upper data encoder and the lower data encoder, and it is necessary to provide the same according to a certain capacitance of the upper data encoder and the lower data encoder acting as a so-called load. 
     As explained above, according to the present invention, there are advantages such that the inverted gate and inhibit gate which have been conventionally necessary become unnecessary, and the increase of speed of conversion processing can be achieved. 
     Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, the number of the selection signals can be reduced, the number of the upper significant codes to be selected and the number of the input gates of the selection gates can be reduced, and further the number of the upper data comparators and the number of switching block rows of the data change point detection circuit can be reduced, and therefore there is an advantage that a reduction of the chip area and a reduction of the power consumption can be achieved. 
     FIGS. 26A-26C are circuit diagrams showing a ninth embodiment of the A/D converter circuit according to the present invention. 
     In FIG. 26, 230 denotes a matrix circuit; 231 to 234 denote upper data comparators; 235, an upper data encoder; 241 to 247 denote lower data comparators; 236, a lower data encoder; 237, a selection gate; 238, an inverter; R 201  to R 216  denote reference resistance elements; BU 101  to BU 105 , BD 101  and BD 107  denote multiple output pin buffers; OR 101  and OR 102  denote OR gates; and EXO 101  and EXO 102  denote exclusive-OR gates; respectively. 
     The matrix circuit 230 is constituted by the arrangement of 35 switching blocks S i11  to S i17 , S i21  to S i27 , S i31  to S i37 , S i41  to S i47 , and S i51  to S i57  in the form of a matrix comprising five rows and seven columns. 
     The respective switching blocks S i11  to S i17 , S i21  to S i27 , S i31  to S i37 , S i41  to S i47 , and S i51  to S i57  are constituted by differential type amplifiers comprising the npn-type transistors Q 201 , Q 202 , and Q 203 . 
     Excluding the switching blocks S i11  to S i14  and S i54  to S i57 , reference voltage obtained by dividing the reference voltages V RT  to V RB  by the reference resistance elements R 201  to R 216  are supplied to the base of one side transistors Q 201  constituting a so-called differential pair of the switching blocks, and analog signals V IN  to be converted to the digital code are supplied to the base of the other side transistors Q 202 , respectively. 
     Also, the emitters of the transistors Q 201  and Q 202  are connected to each other, and the middle point of connection thereof is connected to the current source I via the transistor Q 203  switched by the control signals x 101  to x 105 , respectively. 
     Also, to the collectors of the transistors Q 201  and Q 202 , the power source voltage V DD  is supplied via the resistance element r, the output of which is input to the comparators CD 101  to CD 107  of the seven lower data comparators 241 to 247 as mentioned later, which act also as the initial stage amplifiers of the lower data comparators 241 to 247. 
     Also, the collectors of the transistors Q 101  and Q 102  of the switching block at the second row and the fourth row from the bottom of the diagram are connected to the line in an opposite direction to that for the collector output of the transistors Q 101  and Q 102  of the switching blocks of the first row and third row, and steps are taken so that the line of the serial reference resistance elements R 201  to R 216  to which the reference potential V RT  -V RB  is applied can be formed by folding-back. 
     The reference resistance elements R 201  to R 216  are serially connected between the two reference potentials V RT  and V RB  and arranged by folding-back so as to extend over each predetermined number of rows, e.g., five rows in the present embodiment, to correspond to the matrix arrangement of the switching blocks in the matrix circuit 230. 
     Concretely, each two resistance elements R 216  and R 215  and R 202  and R 201  are serially connected at the first row and the fifth row from the bottom in the diagram, and the resistance elements R 214  to R 211 , R 210  to R 207 , and R 216  to R 213  are serially connected at the second row to the fourth row, respectively. 
     Viewing this folding-back arrangement of the resistance element columns from the reference potential V RB  terminal side positioned on the left end and lower end side of the matrix circuit 180, the wiring pattern extended in the right direction in the diagram is folded-back between the switching block column of the fourth column from the left in the diagram and the switching block column of the fifth column, and two resistance elements R 216  and R 215  are connected in series corresponding to the arrangement position of the switching blocks S i54  and S i53  of the first row from the bottom, whereby the first row of resistance column is constituted. 
     The resistance column of the first row is folded-back between the switching block column of the third column and the switching block column of the second column, and four resistance elements R 214  to R 211  are connected in series between the switching block rows of the first row and the second row and corresponding to the arrangement position of the switching blocks S i43  to S i46  of the second row, whereby the resistance column of the second row is constituted. 
     The resistance column of the second row is folded-back between the switching block column of the fifth column and the switching block column of the sixth column, and four resistance elements R 210  to R 207  are connected in series between the switching block rows of the second row and the third row and corresponding to the arrangement position of the switching blocks S i36  to S i33  at the third row, whereby the resistance column of the third row is constituted. 
     The resistance column of the third row is folded-back between the switching block column of the third column and the switching block column of the second column, and four resistance elements R 206  to R 203  are connected in series between the switching block rows of the fourth row and the fifth row and corresponding to the arrangement position of the switching blocks S i23  to S i26  of the fourth row, whereby the resistance column of the fourth row is constituted. 
     The resistance column of the fourth row is folded-back between the switching block column of the fifth column and the switching block column of the sixth column, two resistance elements R 202  and R 201  are connected in series between the switching block rows at the fourth row and the fifth row and corresponding to the arrangement position of the switching blocks S i16  to S i15  at the fifth row, and one end of the resistance element R 201  is connected to the terminal of the reference potential V RT , whereby the resistance column of the fifth row is constituted. 
     Namely, the resistance columns at the first row and the fifth row are arranged with a deviation of a half cycle with respect to the resistance columns of the second row to the fourth row so that the position exhibiting the lowest value of the reference voltage (connection point between the reference potential V RB  terminal and the resistance element R 216 ) and the position exhibiting the highest value (connection point between the reference potential V RT  terminal and the resistance element R 1 ) are positioned at an intermediate point in the row direction of the switching blocks arranged in the form of the matrix. 
     Such an arrangement structure of resistance columns is made for the purpose of dividing the switching block columns comprising seven columns into two groups, i.e. the group comprising the switching block columns of from the first column to the fourth column and the group of the switching block columns of from the fifth column to the seventh column at the switching point between upper data and lower data as will be mentioned later. 
     Also, the voltages V 221  and V 224  generated between the rows of the respective resistance columns are supplied to the upper data comparators 231 to 234 as the reference voltages obtained by dividing the reference potentials V RT  to V RB  by rough quantization, respectively. 
     In the structure of FIG. 26, when assuming that the voltage between the reference potentials V RT  to V RB  is V REF , the respective reference voltages V 221  to V 224  become the following values, respectively: 
     
         V.sub.221 =(14/16)·V.sub.REF 
    
     
         V.sub.222 =(10/16)·V.sub.REF 
    
     
         V.sub.223 =(6/16)·V.sub.REF 
    
     
         V.sub.224 =(2/16)·V.sub.REF 
    
     Further, wiring is carried out so that the respective reference voltages V 201  to V 215  divided by the reference resistance elements R 201  to R 216  are supplied to the base of the transistor Q 201  of the predetermined switching block. 
     Concretely, a reference voltage V 201  [=(15/16)·V REF  ] generated at the connection point between the resistance elements R 201  and R 202  is supplied to the bases of the transistors Q 201  of the switching blocks S i15  and S i27 . 
     A reference voltage V 202  [=V 221  =(14/16)·V REF  ] generated at the connection point between the resistance elements R 202  and R 203  is supplied to the bases of the transistors Q 201  of the switching blocks S i16  and S i26 . 
     A reference voltage V 203  [=(13/16)·V REF  ] generated at the connection point between the resistance elements R 203  and R 204  is supplied to the bases of the transistors Q 201  of the switching blocks S i17  and S i25 . 
     A reference voltage V 204  [=(12/16)·V REF  ] generated at the connection point between the resistance elements R 204  and R 205  is supplied to the base of the transistor Q 201  of the switching block S i24 . 
     A reference voltage V 205  [=(11/16)·V REF  ] generated at the connection point between the resistance elements R 205  and R 206  is supplied to the bases of the transistors Q 201  of the switching blocks S i23  and S i31 . 
     A reference voltage V 206  [=V 222  =(10/16)·V REF  ] generated at the connection point between the resistance elements R 206  and R 207  is supplied to the bases of the transistors Q 201  of the switching blocks S i22  and S i32 . 
     A reference voltage V 207  [=(9/16)·V REF  ] generated at the connection point between the resistance elements R 207  and R 208  is supplied to the bases of the transistors Q 201  of the switching blocks S i21  and S i33 . 
     A reference voltage V 208  [=(8/16)·V REF  ] generated at the connection point between the resistance elements R 208  and R 209  is supplied to the base of the transistor Q 201  of the switching block S i34 . 
     A reference voltage V 209  [=(7/16)·V REF  ] generated at the connection point between the resistance elements R 209  and R 210  is supplied to the bases of the transistors Q 201  of the switching blocks S i35  and S i47 . 
     A reference voltage V 210  [=V 223  =(6/16)·V REF  ] generated at the connection point between the resistance elements R 210  and R 211  is supplied to the bases of the transistors Q 201  of the switching blocks S i36  and S i46 . 
     A reference voltage V 211  [=(5/16)·V REF  ] generated at the connection point between the resistance elements R 211  and R 212  is supplied to the bases of the transistors Q 201  of the switching blocks S i37  and S i45 . 
     A reference voltage V 212  [=(4/16)·V REF  ] generated at the connection point between the resistance elements R 212  and R 213  is supplied to the base of the transistor Q 201  of the switching block S i44 . 
     A reference voltage V 213  [=(3/16)·V REF  ] generated at the connection point between the resistance elements R 213  and R 214  is supplied to the bases of the transistors Q 201  of the switching blocks S i43  and S i51 . 
     A reference voltage V 214  [=V 224  =(2/16)·V REF  ] generated at the connection point between the resistance elements R 214  and R 215  is supplied to the bases of the transistors Q 201  of the switching blocks S i42  and S i52 . 
     A reference voltage V 215  [=(1/16)·V REF  ] generated at the connection point between the resistance elements R 215  and R 216  is supplied to the bases of the transistors Q 201  of the switching blocks S i41  and S i53 . 
     Upper data comparators 231, 232, 233 and 234 respectively are provided with comparators CU 101  to CU 104 , complementary-type output amplifiers CA 101  to CA 105 , and AND gates AU 101  to AU 104 . 
     An analog signal V IN  is supplied to one input of the comparator CU 101  of the upper data comparator 231, and a reference voltage V 221  [=(14/16)·V REF  ] obtained by dividing the reference potentials V RT  to V RB  by rough quantization is supplied to the other input. 
     The analog signal V IN  is supplied to one input of the comparator CU 102  of the upper data comparator 232, and a reference voltage V 222  [=(10/16)·V REF  ] obtained by dividing the reference potentials V RT  to V RB  by rough quantization is supplied to the other input. 
     The analog signal V IN  is supplied to one input of the comparator CU 103  of the upper data comparator 233, and a reference voltage V 223  [=(6/16)·V REF  ] obtained by dividing the reference potentials V RT  to V RB  by rough quantization is supplied to the other input. 
     The analog signal V IN  is supplied to one input of the comparator CU 104  of the upper data comparator 234, and a reference voltage V 224  [=(2/16)·V REF  ] obtained by dividing the reference potentials V RT  to V RB  by rough quantization is supplied to the other input. 
     The output of comparator CU 101  of the upper data comparator 231 is connected to the input of the output amplifier CA 108 , the positive output thereof is connected to both inputs of a 2-input AND gate AU 101 , and the negative output is connected to one input of the 2-input AND gate AU 102  of the upper data comparator 232. 
     The output of comparator CU 102  of the upper data comparator 232 is connected to the input of the output amplifier CA 109 , the positive output thereof is connected to the other input of the 2-input AND gate AU 102 , and the negative output is connected to one input of the 2-input AND gate AU 103  of the upper data comparator 233. 
     The output of comparator CU 103  of the upper data comparator 233 is connected to the input of the output amplifier CA 110 , the positive output thereof is connected to the other input of a 2-input AND gate AU 103 , and the negative output is connected to one input of the 2-input AND gate AU 104  of the upper data comparator 234. 
     The output of comparator CU 104  of the upper data comparator 234 is connected to the input of the output amplifier CA 111 , the positive output thereof is connected to the other input of a 2-input AND gate AU 104 , and the negative output is connected to the two inputs of the 2-input AND gate AU 105 . 
     The outputs of the respective comparators CU 101  to CU 104  of the upper data comparators 231 to 234 constituted in this way become the level of &#34;H&#34; or &#34;L&#34; corresponding to the level of the sampled analog signal V In , and only one among the respective AND gates AU 101  to AU 104  outputs the &#34;1&#34; level. 
     The output of the AND gate AU 101  of the upper data comparator 231 is connected via the buffer BU 101  to the upper data encoder 235 and, at the same time, connected to the bases of the transistors Q 203  of the switching blocks S i11  to S i17  and connected to the input of the inverter 238 via the buffer. 
     The AND gate AU 102  of the upper data comparator 232 is connected via the buffer BU 102  to the upper data encoder 235 and, at the same time, connected to the bases of the transistors Q 203  of the switching blocks S i21  to S 127 . 
     The output of the AND gate AU 103  of the upper data comparator 233 is connected via the buffer BU 103  to the upper data encoder 235 and, at the same time, connected to the bases of the transistors Q 203  of the switching blocks S i31  to S i37  and connected to the input of the inverter 238 via the buffer. 
     The AND gate AU 104  of the upper data comparator 234 is connected via the buffer BU 104  to the upper data encoder 235 and, at the same time, connected to the bases of the transistors Q 203  of the switching blocks S i41  to S i47 . 
     The output of the AND gate AU 105  is connected to the input of the buffer BU 105  and, at the same time, connected to the bases of the transistors Q 203  of the switching blocks S i51  to S i57  and connected to the input of the inverter 238 via the buffer. 
     The upper data encoder 235 is constituted by an encoder line LN 201  generating the data for an L (left) mode, and an encoder line LN 202  generating the data for an R (right) mode. 
     Namely, in the upper data encoder 235, respective encoder lines LN 201  and LN 202  are set corresponding to a first group of from the first column to the fourth column arranged on the left side from the center of the matrix circuit 230 and a second group of from the fifth column to the seventh column arranged on the right side among the switching blocks S i11  to S i17 , S i21  to S i27 , S i31  to S i37 , S i41  to S i47  and S i51  to S i57  arranged in the matrix circuit 230. The data for the bits excluding the least significant bit (lower data side bit of the upper significant bits) among the upper significant 2 bits, in the case of the present embodiment, for the most significant bit (upper data side bit of the upper significant bits) among the upper significant 2 bits are set. 
     FIG. 27 shows the correspondence between the outputs of the respective AND gates AU 101 , AU 102 , AU 103 , AU 104 , and AU 105  of the upper data comparators 231 to 234 and the set output data code pattern of the respective encoder lines LN 201  and LN 202  of the upper data encoder 235. 
     The setting of data is carried out as shown in FIG. 28 in accordance with the most significant bit in the output data of the left side column group (corresponding to the L mode) and the right side column group (corresponding to the R mode) when dividing the same to two groups around the intermediate point C. 
     The lower data comparators 241 to 247 respectively are provided with comparators CD 101  to CD 107 , complementary-type output amplifiers CA 101  to 107, and AND gates AD 101  to AD 107 . 
     To one input of the comparator CD 101  of the lower data comparator 241 is supplied the collector outputs of the transistors Q 201  of the switching block S i11 , S i31 , and S i51  at the first column of the matrix circuit 230 and the collector outputs of the transistors Q 202  of the switching blocks S i21  and S i41 , and to the other input is supplied the collector outputs of the transistors Q 201  of the switching blocks S i21  and S i41  and the collector outputs of the transistors Q 202  of the switching blocks S i11 , S i31 , and S i51 . 
     To one input of the comparator CD 102  of the lower data comparator 242 is supplied the collector outputs of the transistors Q 201  of the switching block S i12 , S i32 , and S i52  at the second column of the matrix circuit 230 and the collector outputs of the transistors Q 202  of the switching blocks S i22  and S i42 , and to the other input is supplied the collector outputs of the transistors Q 201  of the switching blocks S i22  and S i42  and the collector outputs of the transistors Q 202  of the switching blocks S i12 , S i32 , and S i52 . 
     To one input of the comparator CD 103  of the lower data comparator 243 is supplied the collector outputs of the transistors Q 201  of the switching block S i13 , S i33 , and S i53  at the third column of the matrix circuit 230 and the collector outputs of the transistors Q 202  of the switching blocks S i23  and S i43 , and to the other input is supplied the collector outputs of the transistors Q 201  of the switching blocks S i23  and S i43  and the collector outputs of the transistors Q 202  of the switching blocks S i13 , S i33 , and S i53 . 
     To one input of the comparator CD 104  of the lower data comparator 244 is supplied the collector outputs of the transistors Q 201  of the switching block S i14 , S i34 , and S i54  at the fourth column of the matrix circuit 230 and the collector outputs of the transistors Q 202  of the switching blocks S i24  and S i44 , and to the other input is supplied the collector outputs of the transistors Q 201  of the switching blocks S i24  and S i44  and the collector outputs of the transistors Q 202  of the switching blocks S i14 , S i34 , and S i54 . 
     To one input of the comparator CD 105  of the lower data comparator 245 is supplied the collector outputs of the transistors Q 201  of the switching block S i15 , S i35 , and S i55  at the fifth column of the matrix circuit 230 and the collector outputs of the transistors Q 202  of the switching blocks S i25  and S i45 , and to the other input is supplied the collector outputs of the transistors Q 201  of the switching blocks S i25  and S i45  and the collector outputs of the transistors Q 202  of the switching blocks S i15 , S i35 , and S i55 . 
     To one input of the comparator CD 106  of the lower data comparator 246 is supplied the collector outputs of the transistors Q 201  of the switching block S i16 , S i36 , and S i56  at the sixth column of the matrix circuit 230 and the collector outputs of the transistors Q 202  of the switching blocks S i26  and S i46 , and to the other input is supplied the collector outputs of the transistors Q 201  of the switching blocks S i26  and S i46  and the collector outputs of the transistors Q 202  of the switching blocks S i16 , S i36 , and S i56 . 
     To one input of the comparator CD 107  of the lower data comparator 247 is supplied the collector outputs of the transistors Q 201  of the switching block S i17 , S i37 , and S i57  at the seventh column of the matrix circuit 230 and the collector outputs of the transistors Q 202  of the switching blocks S i27  and S i47 , and to the other input is supplied the collector outputs of the transistors Q 201  of the switching blocks S i27  and S i47  and the collector outputs of the transistors Q 202  of the switching blocks S i17 , S i37 , and S i57 . 
     The output of the comparator CD 101  of the lower data comparator 241 is connected to the input of the output amplifier CA 101 , the positive output thereof is connected to both inputs of the 2-input AND gate AD 101 , and the negative output is connected to one input of the 2-input AND gate AD 102  of the lower data comparator 242. 
     The output of the comparator CD 102  of the lower data comparator 242 is connected to the input of the output amplifier CA 102 , the positive output thereof is connected to the other input of the 2-input AND gate AD 102 , and the negative output is connected to one input of the 2-input AND gate AD 103  of the lower data comparator 243. 
     The output of the comparator CD 103  of the lower data comparator 243 is connected to the input of the output amplifier CA 103 , the positive output thereof is connected to the other input of the 2-input AND gate AD 103 , and the negative output is connected to one input of the 2-input AND gate AD 104  of the lower data comparator 244. 
     The output of the comparator CD 104  of the lower data comparator 244 is connected to the input of the output amplifier CA 104 , the positive output thereof is connected to the other input of the 2-input AND gate AD 104 , and the negative output is connected to one input of the 2-input AND gate AD 105  of the lower data comparator 245. 
     The output of the comparator CD 105  of the lower data comparator 245 is connected to the input of the output amplifier CA 105 , the positive output thereof is connected to the other input of the 2-input AND gate AD 105 , and the negative output is connected to one input of the 2-input AND gate AD 106  of the lower data comparator 246. 
     The output of the comparator CD 106  of the lower data comparator 246 is connected to the input of the output amplifier CA 106 , the positive output thereof is connected to the other input of the 2-input AND gate AD 106 , and the negative output is connected to one input of the 2-input AND gate AD 107  of the lower data comparator 247. 
     The output of the comparator CD 107  of the lower data comparator 247 is connected to the input of the output amplifier CA 107 , the positive output thereof is connected to the other input of the 2-input AND gate AD 107 , and the negative output is connected to both inputs of the 2-input AND gate AD 108 . 
     The outputs of the respective comparators CD 101  to CD 107  of the lower data comparators 241 to 247 constituted in this way become the level of the two inputs, and only one among the respective AND gates AD 101  to AD 108  outputs the &#34;1&#34; level. 
     The output of the AND gates AD 101  to AD 107  and AD 108  of the lower data comparator 241 to 247 are connected via the buffers BD 101  to BD 108  to the lower data encoder 236. 
     The lower data encoder 236 is comprised of a data line LN 203  generating the lower significant data BD 113 , and DB 114 , a selection line LN 204  generating a selection signal SEL 101  indicating that one of the outputs of the AND gates AD 101  and AD 104  of the lower data comparators 241 to 244 becomes &#34;1&#34;; and a selection line LN 205  generating the selection signal SEL 102  indicating that one of the outputs of the AND gates AD 105  to AD 107  and AD 108  of the lower data comparators 245 to 247 becomes &#34;1&#34;. 
     The selection signal SEL 101  is set for selecting the upper significant data of the L mode mentioned above, and the selection signal SEL 102  is set for selecting the upper significant data of the R mode. 
     FIG. 28 shows the correspondence between the outputs of the upper data side AND gates AU 101  to AU 105  and the lower data side AND gates AD 101  to AD 108  and the output conversion code data. 
     As mentioned above, in the matrix circuit 230 in the present embodiment, the switching blocks are divided into two in the row direction, and at this division point C, as seen from FIG. 28, when paying attention to the upper significant 2 bits of the output conversion codes D 1  to D 4 , division is made at the point at which the value of the upper significant 2 bits is switched. 
     Further, the lower data encoder 236 outputs the selection signal SEL 102  as the conversion code D 2  on the lower data side (least significant bit of the upper significant bits) of the upper significant data excluded from the set data of the upper data encoder 235 based on a fact that, when paying attention to the upper significant 2 bits of the output conversion codes D 1  to D 4 , there is a relationship of inversion of the level in the lower data side bits thereof between the L (left) side and the R (right side) around the intermediate point C. 
     The selection gate 237 is constituted by AND gates AD 101  and AD 102 , selects a single upper significant data (the most significant bit among the upper significant bits) from among the respective upper significant data of the L mode and the R mode output from the upper data encoder 235 using the selection signals SEL 101  to SEL 102  output from the lower data encoder 236, and outputs the same as the conversion code D 1  via the OR gate OR 101 . 
     [0065] 
     Concretely, one input terminal of the AND gate A 101  is connected to the encoder line LN 201  generating the data for the L mode of the upper data encoder 235, and the other input terminal is connected to the selection line LN 204  outputting the selection signal SEL 101  of the lower data encoder 236. 
     One input terminal of the AND gate A 102  is connected to the encoder line LN 202  generating the data for the R mode of the upper data encoder 235, and the other input terminal is connected to the selection line LN 205  outputting the selection signal SEL 102  of the lower data encoder 236. 
     The outputs of these AND gates A 101  and A 102  are connected to respective input terminals of the 2-input OR gate OR 101 . 
     The exclusive-OR gate EXO 101  obtains the exclusive-OR between the lower significant data BD 113  output from one line of the data line LN 203  of the lower data encoder 236 and the signal obtained by inverting the sum of the output levels of the AND Gates AU 101 , AU 103 , or AU 105  of the upper data comparators 231 and 233 by the inverter 238 and outputs the result thereof as the lower significant data conversion code D 3 . 
     The exclusive-OR gate EXO 102  obtains the exclusive-OR between the lower significant data BD 114  output from one line of the data line LN 203  of the lower data encoder 236 and the signal obtained by inverting the sum of the output levels of the AND gates AU 101 , AU 103 , or AU 105  of the upper data comparators 231 and 233 by the inverter 238 and outputs the result thereof as the lower significant data conversion code D 4 . 
     Next, an explanation will be made of the operation by the above-described structure. 
     For example, when the sampling voltage V S  of the sampled analog signal is represented as V RB  &lt;V S  &lt;V 224 , the outputs of the comparators CU 101  to CU 104  of the upper data comparators 231 to 234 become all &#34;L&#34;, so that the digital signals are output, i. e., &#34;0&#34; is output from the AND gates AU 101  to AU 104 , and &#34;1&#34; is output from the AU 105 , respectively. 
     As a result, a digital signal such as [0000] is input to the upper data encoder 235. At the upper data encoder 235, using a so-called wired-OR circuit, the upper significant data of [0] are respectively generated in the encoder line [LN 201  ] generating the L mode data and the encoder line [LN 202  ] generating the R mode data, which are output to the selection gate 235. 
     Also, when the sampling voltage V S  of the sampled analog signal is represented as V 224  &lt;V S  &lt;V 223 , the outputs of the comparators CU 101  to CU 103  of the upper data comparators 231 to 233 become all &#34;H&#34;, so that the digital signals are output i.e., &#34;0&#34; is output from the AND gates AU 101  to AU 103  and AU 105  of the upper data comparators 231 to 233, and &#34;1&#34; is output from the AU 104  of the upper data comparator 234, respectively. 
     As a result, a digital signal such as [0001] is input to the upper data encoder 235. At the upper data encoder 235, using a so-called wired-OR circuit, the upper significant data of [0] is generated in the encoder line [LN 201  ] generating the L mode data, and the upper significant data of [0] is generated in the encoder line [LN 202  ] generating the R mode data, respectively, which are output to the selection gate 235. 
     Also, when the sampling voltage V S  is represented as V 223  &lt;V S  &lt;V 222 , similarly the digital signals are output, i.e., &#34;0&#34; is output from the upper significant side AND gates AU 101 , AU 102 , AU 104 , and AU 105 , and &#34;1&#34; is output from the AND gate AU 103 , respectively. 
     As a result, a digital signal such as [0010] is input to the upper data encoder 235, and the upper significant data are output, i.e.m [1] is output from the line [LN 201  ], and [0] is output from the line [LN 202  ], to the selection gate 235. 
     Further, when the sampling voltage V S  is represented as V 222  &lt;V S  &lt;V 221 , similarly the digital signals are output, i.e., &#34;0&#34; is output from the upper significant side AND gates AU 101 , AU 103 , AU 104 , and AU 105 , and &#34;1&#34; is output from the AND gate AU 102 , respectively. 
     As a result, a digital signal such as [0100] is input to the upper data encoder 235, and the upper significant data are output, i.e. [1] is output from the line [LN 201  ], and [1] is output from the line [LN 202  ], to the selection gate 235. 
     Similarly, when the sampling voltage V S  is represented as V 221  &lt;V S  &lt;V RT , the digital signals are output, i.e., &#34;0&#34; is output from the upper significant side AND gates AU 102 , AU 103 , AU 104 , and AU 105 , and &#34;1&#34; is output from the AND gate AU 101 , respectively. 
     As a result, a digital signal such as [1000] is input to the upper data encoder 235, and the upper significant data are output, i.e., [1] is output from the line [LN 201  ], and [1] is output from the line [LN 202  ], to the selection gate 235. 
     In parallel with this, the transistors Q 203  of the respective switching blocks of the matrix circuit 230 connected to the control lines (x 101 , x 102 , x 103 , x 104 , and x 105 ) at which the digital output signal has become &#34;1&#34; among the respective AND gates AU.sub.(101, 102, 103, 104, 105) are controlled to turn ON in units of rows, and further a fine digitization of the quantization level is executed. 
     For example, when only the output of the AND gate AU 103  becomes the &#34;1&#34; level, the transistors Q 203  of the switching blocks S i31  to S i37  become ON, so that the reference voltages V 205  to V 211  divided by the reference resistors R 206  to R 211  and the sampling voltage V S  are differentially amplified at the switching blocks S i33  to S i36 , and compared by the lower data comparators 241 to 247. 
     Similarly, when the output of the AND gate AU 102  is at the &#34;1&#34; level, the switching blocks S i21  to S i27  are activated, so that a differential amplification operation is performed, and the comparison by the lower data comparators 241 to 247 is carried out. 
     In this way, in the lower data conversion codes, the sampled voltage V S  and the reference voltage divided by the reference resistance of that row are compared in units of rows of the switching blocks, so that the digital signal in accordance with the result of comparison will be output from the AND gates AD 101  to AD 107  and AD 108  of the lower data comparators 241 to 247. 
     At this time, where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 224  &gt;V IN , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as V RB  &lt;V IN  &lt;[(V 224  +V 223 )/2]; or where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 224  &lt;V IN  &lt;V 223 , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as V RB  &lt;V IN  &lt;[(V 224  +V 223 )/2]; or where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 223  &lt;V IN  &lt;V 222 , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as [(V 223  +V 222 )/2]&lt;V IN  &lt;[(V 221  +V 222 )/2]; or where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 222  &lt;V IN  &lt;V 221 , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as [(V 223  +V 222 )/2]&lt;V IN  &lt;[(V 221  +V 222 )/2], in the lower data encoder 236, only the selection line LN 204  becomes &#34;1&#34;. As a result, the selection signal SEL 101  is input to the selection gate 237 as the &#34;1&#34; level, and the selection signal SEL 102  is input to the selection gate 237 as the &#34;0&#34;  level. 
     In the selection gate 237, along with the fact that only the selection signal SEL 101  is input as the &#34;1&#34; level, only the AND gate A 101  is activated. 
     To the AND gate A 101 , the upper data side bit data of the upper significant data for the L mode generated in the line LN 201  of the upper data encoder 235 is supplied. 
     Accordingly, in the selection gate 237, the bits of the upper significant data at the L mode are selected, and as a result, they are output as the upper significant data conversion code D 1  via the OR gate OR 101 . 
     At this time, in parallel with the output of the upper data conversion code D 1 , the selection signal SEL 102  is output as the upper significant data conversion code D 2  while holding its level &#34;0&#34; as it is. 
     Concretely, when the sampling voltage V S  of the analog signal V IN  is defined as V RB  &lt;V S  &lt;V 224 , the upper data conversion code [D 1 , D 2  ] is output as [00]; when V 224  &lt;V S  &lt;V 223  stands, the upper data conversion code [D 1 , D 2  ] is output as [00]; when V 223  &lt;V S  &lt;V 222  stands, the upper data conversion code [D 1 , D 2  ] is output as [10]; and when V 222  &lt;V S  &lt;V 221  stands, the upper data conversion code [D 1 , D 2  ] is output as [10]. 
     Note that, when V 221  &lt;V S  &lt;V RT , the upper significant data conversion code [D 1 , D 2  ] outputs [11], but this code will not be selected. 
     Also, in the lower data encoder 236, when the output of the AND gate AD 101  of the lower data comparator 241 is &#34;1&#34;, the lower significant data BD 113  and BD 114  are generated as [11]; when the output of the AND gate AD 102  of the lower data comparator 242 is &#34;1&#34;, the lower significant data BD 113  and BD 114  are generated as [10]; when the output of the AND gate AD 103  of the lower data comparator 243 is &#34;1&#34;, the lower significant data BD 113  and BD 114  are generated as [01]; and when the output of the AND gate AD 104  of the lower data comparator 244 is &#34;1&#34;, the lower significant data BD 113  and BD 114  are generated as [00], the data BD 113  is output to the exclusive-OR gate EXO 101 , and the data BD 114  is output to the exclusive-OR gate EXO.sub. 102. 
     In the exclusive-OR gates EXO 101  and EXO 102 , when V 224  &lt;V S  &lt;V 223  and V 222  &lt;V S  &lt;V 221  stand, that is where the switching blocks S i41  to S i47  and S i21  to S i27  at the second row and fourth row from the bottom of the matrix circuit 230 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D 3  and D 4  while inverting the output level of the lower data encoder 236. 
     Contrary to this, when V RB  &lt;V S  &lt;V 224 , V 223  &lt;V S  &lt;V 222   and V 221  &lt;V S  &lt;V RT  stand, that is where the switching blocks S i51  to S i57 , S i31  to S i37  and S i11  to S i17  at the first row, third row, and fifth row from the bottom of the matrix circuit 230 are selected, since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 236 as they are and output as the lower significant data conversion codes D 3  and D 4 . 
     Also, where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 224  &lt;V IN  &lt;V 223 , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as [(V 224  +V 223 )/2]&lt;V IN  &lt;[(V 223  +V 222 )/2]; or where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 223  &lt;V IN  &lt;V 222 , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as [(V 224  +V 223 )/2]&lt;V IN  &lt;[(V 223  +V 222 )/2]; or where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 222  &lt;V IN  &lt;V 221 , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as [(V 222  +V 221 )/2]&lt;V IN  &lt;V RT  ; or where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 221  &lt;V IN , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as [(V 222  +V 221 )/2]&lt;V IN  &lt;V RT , in the lower data encoder 236, only the selection line LN 205  becomes &#34;1&#34;. 
     As a result, the selection signal SEL 102  is input to the selection gate 237 as the &#34;1&#34; level, and the selection signal SEL 101  is input to the selection gate 237 as the &#34;0&#34; level. 
     In the selection gate 237, along with the fact that only the selection signal SEL 102  is input as the &#34;1&#34; level, only the AND gate A 102  is activated. 
     To the AND gate A 102 , the upper data side bit data of the upper significant data for the R mode generated in the line LN 202  of the upper data encoder 235 is supplied. 
     Accordingly, in the selection gate 237, the bits of the upper significant data at the R mode are selected, and as a result, they are output as the upper significant data conversion code D 1  via the OR gate OR 101 . 
     At this time, in parallel with the output of the upper data conversion code D 1 , the selection signal SEL 102  is output as the upper significant data conversion code D 2  while holding its level &#34;1&#34; as it is. 
     Concretely, when the sampling voltage V S  of the analog signal V IN  is defined as V 224  &lt;V S  &lt;V 223 , the upper data conversion code [D 1 , D 2  ] is output as [01]; when V 223  &lt;V S  &lt;V 222  stands, the upper data conversion code [D 1 , D 2  ] is output as [01]; when V 222  &lt;V S  &lt;V 221  stands, the upper data conversion code [D 1 , D 2  ] is output as [11]; and when V 221  &lt;V S  &lt;V RT  stands, the upper data conversion code [D 1 , D 2  ] is output as [11]. 
     Note that, when the sampling voltage V S  is defined as V RB  &lt;V S  &lt;V 224 , the upper significant data conversion code [D 1 , D 2  ] outputs [00], but this code will not be selected. 
     Also, in the lower data encoder 236, when the output of the AND gate AD 105  of the lower data comparator 245 is &#34;1&#34;, the lower significant data BD 113  and BD 114  are generated as [11]; when the output of the AND gate AD 106  of the lower data comparator 246 is &#34;1&#34;, the lower significant data BD 113  and BD 114  are generated as [10]; when the output of the AND gate AD 107  of the lower data comparator 247 is &#34;1&#34;, the lower significant data BD 113  and BD 114  are generated as [01]; and when the output of the AND gate AD 108  is &#34;1&#34;, the lower significant data BD 113  and BD 114  are generated as [00], the data BD 113  is output to the exclusive-OR gate EXO 101 , and the data BD 114  is output to the exclusive-OR gate EXO 102 . 
     In the exclusive-OR gates EXO 101  and EXO 102 , when V 224  &lt;V S  &lt;V 223  and V 222  &lt;V S  &lt;V 221  stand, that is where the switching blocks S i41  to S i47  and S i21  to S i27  at the second row and fourth row from the bottom of the matrix circuit 230 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D 3  and D 4  while inverting the output level of the lower data encoder 236. 
     Contrary to this, when V RB  &lt;V S  &lt;V 224 , V 223  &lt;V S  &lt;V 222  and V 221  &lt;V S  &lt;V RT  stand, that is where the switching blocks S i51  to S i57 , S i31  to S i37  and S i11  to S i17  at the first row, third row, and fifth row from the bottom of the matrix circuit 230 are selected, since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 236 as they are and output as the lower significant data conversion codes D 3  and D 4 . 
     As explained above, according to the present embodiment, the lower significant codes are divided to two groups, signals SEL 101  and SEL 102  for selecting the L mode data and R mode data are output from the lower data encoder 236 obtaining the conversion code of the groups, and the L mode data and R mode data output from the upper data encoder 235 are selected, to obtain the upper significant data conversion code D 1 , and output the selection signal SEL 101  and the selection signal SEL 102  inverted in its level as the lower significant side conversion code D 2  of the upper significant bit data. Therefore the selection signal can be used directly for the selection of the upper significant data without the use of the inverted gate and inhibit gate as in the conventional circuit. 
     Accordingly, the input of the selection signal to the selection gate 237 is not delayed relative to the output of the upper data encoder 235, and thus the increase of speed of conversion processing can be achieved. 
     Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, the number of the selection signals can be reduced to two, and also the number of the upper data codes to be selected and the number of the input gates of selection gates can be reduced to two. Therefore an A/D converter circuit with which the reduction of the chip area and the reduction of the power consumption can be achieved can be realized. 
     FIGS. 29A-29C are circuit diagrams showing a 10th embodiment of the A/D converter circuit according to the present invention. 
     The point of difference of the present embodiment from the above-mentioned ninth embodiment resides in the constitution whereby the number of the selection lines of the lower data encoder 255 is reduced to only one line, i.e., LN 214 , to generate only one selection signal SEL 111  selected from among the selection signals, and a signal obtained by inverting the level of the selection signal SEL 111  at the inverter 259 is supplied as the signal in place of the selection signal SEL 102  to the other input of the AND gate A 112  of the selection gate 257 and output as the lower data conversion code D 2  of the upper significant bit data. 
     According to the present 10th embodiment, in addition to the effect of the above-described first embodiment, a simpler structure can be realized, and the chip area can be further reduced. 
     Note that, in the above-mentioned ninth and 10th embodiments, an explanation was made taking as an example an A/D converter circuit for four bits, but needless to say the present invention can be applied to an A/D converter circuit for more bits. 
     Also, in the above-mentioned ninth and 10th embodiments, the structure in which the other output pin buffers are arranged on the input side of the upper data encoder and the lower data encoder was indicated, but these other output pin buffers are provided so as to reliably drive the upper data encoder and the lower data encoder, and it is necessary to provide the same according to a certain capacitance of the upper data encoder and the lower data encoder acting as a so-called load. 
     As explained above, according to the present invention, there are advantages such that the inverted gate and inhibit gate which have been conventionally necessary become unnecessary, and the increase of speed of conversion processing can be achieved. In addition to the fact that the inverted gate and inhibit gate become unnecessary, the number of the selection signals can be reduced, and the number of the upper data codes to be selected and the number of the input gates of selection gates can be reduced, and therefore there is an advantage in that the reduction of the chip area and the reduction of the power consumption can be achieved. 
     FIGS. 30A-30C are circuit diagrams showing an 11th embodiment of the A/D converter circuit according to the present invention. 
     In FIG. 30, 270 denotes a matrix circuit; 271 to 274 denote upper data comparators; 275, an upper data encoder; 281 to 287 denote lower data comparators; 276, a lower data encoder; 279, a selection gate; 278, an inverter; R 241  to R 256  denote reference resistance elements; BU 131  to BU 135  and BD 141  and BD 147  denote multiple output pin buffers; OR 121  and OR 122  denote OR gates; and EXO 121  and EXO 122  denote exclusive-OR gates; respectively. 
     The matrix circuit 270 is constituted by the arrangement of 35 switching blocks S k11  to S k17 , S k21  to S k27 , S k31  to S k37 , S k41  to S k47 , and S k51  to S k57  in the form of a matrix comprising five rows and seven columns. 
     The respective switching blocks S k11  to S k17 , S k21  to S k27 , S k31  to S k37 , S k41  to S k47 , and S k51  to S k57  are constituted by differential type amplifiers comprising the npn-type transistors Q 231 , Q 232 , and Q 233 . 
     Excluding the switching blocks S k11  to S k14  and S k54  to S k57 , a reference voltage obtained by dividing the reference voltages V RT  to V RB  by the reference resistance elements R 241  to R 256  are supplied to the base of one side transistors Q 231  constituting a so-called differential pair of the respective switching blocks, and analog signals V IN  which should be converted to the digital code are supplied to the base of the other side transistors Q 232 , respectively. 
     Also, the emitters of the transistors Q 231  and Q 232  are connected to each other, and the middle point of connection thereof is connected to the current source I via the transistor Q 233  switched by the control signals x 131  to x 135 , respectively. 
     Also, to the collectors of the transistors Q 231  and Q 232 , the power source voltage V DD  is supplied via the resistance element r, the output of which is respectively input to the comparators CD 141  to CD 147  of the seven lower data comparators 281 to 287 as mentioned later, which act also as the initial stage amplifiers of the lower data comparators 281 to 287. 
     Also, the collectors of the transistors Q 231  and Q 232  of the switching blocks at the second row and the fourth row from the bottom of the diagram are connected to the line in an opposite direction to that for the collector output of the transistors Q 231  and Q 232  of the switching blocks of the first row and third row, and steps are taken so that the line of the serial reference resistance elements R 241  to R 256  to which the reference potentials V RT  to V RB  are applied can be formed by folding-back. 
     The reference resistance elements R 241  to R 256  are serially connected between the two reference potentials V RT  and V RB  and arranged by folding-back so as to extend over a predetermined number of rows, e.g., five rows in the present embodiment to correspond to the matrix arrangement of the switching blocks in the matrix circuit 270. 
     Concretely, each two resistance elements R 256  and R 255  and R 242  and R 241  are serially connected at the first row and the fifth row from the bottom in the diagram, and the resistance elements R 254  to R 251 , R 250  to R 247 , and R 246  to R 243  are serially connected at the second row to the fourth row, respectively. 
     Viewing this folding-back arrangement of the resistance element columns from the reference potential V RB  terminal side positioned on the left end and lower end side of the matrix circuit 270, the wiring pattern extended in the right direction in the diagram is folded-back between the switching block column of the fourth column from the left in the diagram and the switching block column of the fifth column, and two resistance elements R 256  and R 255  are connected in series corresponding to the arrangement position of the switching blocks S k54  and S k53  at the first row from the bottom, whereby the first row of resistance column is constituted. 
     The resistance column at the first row is folded-back between the switching block column of the third column and the switching block column of the second column, and four resistance elements R 254  to R 251  are connected in series between the switching block rows of the first row and the second row and corresponding to the arrangement position of the switching blocks S k43  to S k46  of the second row, whereby the resistance column of the second row is constituted. 
     The resistance column of the second row is folded-back between the switching block column of the fifth column and the switching block column of the sixth column, and four resistance elements R 250  to R 247  are connected in series between the switching block rows of the second row and the third row and corresponding to the arrangement position of the switching blocks S k36  to S k33  of the third row, whereby the resistance column of the third row is constituted. 
     The resistance column of the third row is folded-back between the switching block column of the third column and the switching block column of the second column, and four resistance elements R 246  to R 243  are connected in series between the switching block rows of the fourth row and the fifth row and corresponding to the arrangement position of the switching blocks S k23  to S k26  of the fourth row, whereby the resistance column of the fourth row is constituted. 
     The resistance column of the fourth row is folded-back between the switching block column of the fifth column and the switching block column of the sixth column, two resistance elements R 242  and R 241  are connected in series between the switching block rows of the fourth row and the fifth row and corresponding to the arrangement position of the switching blocks S k16  to S k15  at the fifth row, and one end of the resistance element R 1  is connected to the terminal of the reference potential V RT , whereby the resistance column of the fifth row is constituted. 
     Namely, the resistance columns of the first row and the fifth row are arranged with a deviation of a half cycle with respect to the resistance columns of the second row to the fourth row so that the position exhibiting the lowest value of the reference voltage (connection point between the reference potential V RB  terminal and the resistance element R 256 ) and the position exhibiting the highest value (connection point between the reference potential V RT  terminal and the resistance element R 241 ) are positioned at an intermediate point in the row direction of the switching blocks arranged in the form of the matrix. 
     In such an arrangement structure of resistance columns, the switching block columns comprising seven columns are divided into two groups, i.e., the group comprising the switching block columns of from the first column to the fourth column and the group of the switching block columns of from the fifth column to the seventh column at the switching point between the upper data and lower data as will be mentioned later. 
     Also, the voltages V 281  to V 284  generated between the rows of the respective resistance columns are supplied to the upper data comparators 271 to 274 as the reference voltages obtained by dividing the reference potentials V RT  to V RB  by rough quantization, respectively. 
     In the structure of FIG. 30, when assuming that the voltage between the reference potentials V RT  to V RB  is V REF , the respective reference voltages V 281  to V 284  become the following values: 
     
         V.sub.281 =(14/16)·V.sub.REF 
    
     
         V.sub.282 =(10/16)·V.sub.REF 
    
     
         V.sub.283 =(6/16)·V.sub.REF 
    
     
         V.sub.284 =(2/16)·V.sub.REF 
    
     Further, wiring is carried out so that the respective reference voltages V 261  to V 275  divided by the reference resistance elements R 241  to R 256  are supplied to the base of the transistor Q 231  of the predetermined switching block. 
     Concretely, a reference voltage V 261  [=(15/16)·V REF  ] generated at the connection point between the resistance elements R 241  and R 242  is supplied to the bases of the transistors Q 231  of the switching blocks S k15  and S k27 . 
     A reference voltage V 262  [=V 281  =(14/16)·V REF  ] generated at the connection point between the resistance elements R 242  and R 243  is supplied to the bases of the transistors Q 231  of the switching blocks S k16  and S k26 . 
     A reference voltage V 263  [=(13/16)·V REF  ] generated at the connection point between the resistance elements R 243  and R 244  is supplied to the bases of the transistors Q 231  of the switching blocks S k17  and S k25 . 
     A reference voltage V 264  [=(12/16)·V REF  ] generated at the connection point between the resistance elements R 244  and R 245  is supplied to the base of the transistor Q 231  of the switching block S k24 . 
     A reference voltage V 265  [=(11/16)·V REF  ] generated at the connection point between the resistance elements R 245  and R 246  is supplied to the bases of the transistors Q 231  of the switching blocks S k23  and S k31 . 
     A reference voltage V 266  [=V 282  =(10/16)·V REF  ] generated at the connection point between the resistance elements R 246  and R 247  is supplied to the bases of the transistors Q 231  of the switching blocks S k22  and S k32 . 
     A reference voltage V 267  [=(9/16)·V REF  ] generated at the connection point between the resistance elements R 247  and R 248  is supplied to the bases of the transistors Q 231  of the switching blocks S k21  and S k33 . 
     A reference voltage V 268  [=(8/16)·V REF  ] generated at the connection point between the resistance elements R 248  and R 249  is supplied to the base of the transistor Q 231  of the switching block S k34 . 
     A reference voltage V 269  [=(7/16)·V REF  ] generated at the connection point between the resistance elements R 249  and R 250  is supplied to the bases of the transistors Q 231  of the switching blocks S k35  and S k47 . 
     A reference voltage V 270  [=V 283  =(6/16)·V REF  ] generated at the connection point between the resistance elements R 250  and R 251  is supplied to the bases of the transistors Q 231  of the switching blocks S k36  and S k46 . 
     A reference voltage V 271  [=(5/16)·V REF  ] generated at the connection point between the resistance elements R 251  and R 252  is supplied to the bases of the transistors Q 231  of the switching blocks S k37  and S k45 . 
     A reference voltage V 272  [=(4/16)·V REF  ] generated at the connection point between the resistance elements R 252  and R 253  is supplied to the base of the transistor Q 231  of the switching block S k44 . 
     A reference voltage V 273  [=(3/16)·V REF  ] generated at the connection point between the resistance elements R 253  and R 254  is supplied to the bases of the transistors Q 231  of the switching blocks S k43  and S k51 . 
     A reference voltage V 274  [=V 284  =(2/16)·V REF  ] generated at the connection point between the resistance elements R 254  and R 255  is supplied to the bases of the transistors Q 231  of the switching blocks S k42  and S k52 . 
     A reference voltage V 275  [=(1/16)·V REF  ] generated at the connection point between the resistance elements R 255  and R 256  is supplied to the bases of the transistors Q 231  of the switching blocks S k41  and S k53 . 
     Upper data comparators 271, 272, 273, and 274 respectively are provided with comparators CU 131  to CU 134 , complementary-type output amplifiers CA 131  to CA 134 , and AND gates AU 131  to AU 134 . 
     An analog signal V IN  is supplied to one input of the comparator CU 131  of the upper data comparator 271, and a reference voltage V 281  [=(14/16)·V REF  ] obtained by dividing the reference potentials V RT  to V RB  by rough quantization is supplied to the other input. 
     The analog signal V IN  is supplied to one input of the comparator CU 132  of the upper data comparator 272, and a reference voltage V 282  [=(10/16)·V REF  ] obtained by dividing the reference potentials V RT  to V RB  by rough quantization is supplied to the other input. 
     The analog signal V IN  is supplied to one input of the comparator CU 133  of the upper data comparator 273, and a reference voltage V 283  [=(6/16)·V REF  ] obtained by dividing the reference potentials V RT  to V RB  by rough quantization is supplied to the other input. 
     The analog signal V IN  is supplied to one input of the comparator CU 134  of the upper data comparator 274, and a reference voltage V 284  [=(2/16)·V REF  ] obtained by dividing the reference potentials V RT  to V RB  by rough quantization is supplied to the other input. 
     The output of the comparator CU 131  of the upper data comparator 271 is connected to the input of the output amplifier CA 131 , the positive output thereof is connected to both inputs of a 2-input AND gate AU 131 , and the negative output is connected to one input of the 2-input AND gate AU 132  of the upper data comparator 272. 
     The output of the comparator CU 132  of the upper data comparator 272 is connected to the input of the output amplifier CA 132 , the positive output thereof is connected to the other input of the 2-input AND gate AU 132 , and the negative output is connected to one input of the 2-input AND gate AU 133  of the upper data comparator 273. 
     The output of the comparator CU 133  of the upper data comparator 273 is connected to the input of the output amplifier CA 133 , the positive output thereof is connected to the other input of a 2-input AND gate AU 133 , and the negative output is connected to one input of the 2-input AND gate AU 134  of the upper data comparator 274. 
     The output of the comparator CU 134  of the upper data comparator 274 is connected to the input of the output amplifier CA 134 , the positive output thereof is connected to the other input of a 2-input AND gate AU 134 , and the negative output is connected to the both inputs of the 2-input AND gate AU 135 . 
     The outputs of the respective comparators CU 131  to CU 134  of the upper data comparators 271 to 274 constituted in this way become the level of &#34;H&#34; or &#34;L&#34; corresponding to the level of the sampled analog signal V IN , and only one among the respective AND gates AU 131  to AU 134  outputs the &#34;1&#34; level. 
     The output of the AND gate AU 131  of the upper data comparator 271 is connected via the buffer BU 131  to the upper data encoder 275 and, at the same time, connected to the bases of the transistors Q 233  of the switching blocks S k11  to S k17  and connected to the input of the inverter 278 via the buffer. 
     The AND gate AU 132  of the upper data comparator 272 is connected via the buffer BU 132  to the upper data encoder 275 and, at the same time, connected to the bases of the transistors Q 233  of the switching blocks S k21  to S k27 . 
     The output of the AND gate AU 133  of the upper data comparator 273 is connected via the buffer BU 133  to the upper data encoder 275 and, at the same time, connected to the bases of the transistors Q 233  of the switching blocks S k31  to S k37  and connected to the input of the inverter 278 via the buffer. 
     The AND gate AU 134  of the upper data comparator 274 is connected via the buffer BU 134  to the upper data encoder 275 and, at the same time, connected to the bases of the transistors Q 233  of the switching blocks S k41  to S k47 . 
     The output of the AND gate AU 135  is connected to the input of the buffer BU 135  and, at the same time, connected to the bases of the transistors Q 233  of the switching blocks S k51  to S k57  and connected to the input of the inverter 278 via the buffer. 
     The upper data encoder 275 is constituted by an encoder line LN 221  generating the data for an L (left) mode and an encoder line LN 222  generating the data for an R (right) mode. 
     Namely, in the upper data encoder 275, respective encoder lines LN 221  and LN 222  are set corresponding to a first group of from the first column to the fourth column arranged on the left side from the center of the matrix circuit 270 and a second group of from the fifth column to the seventh column arranged on the right side among the switching blocks S k11  to S k17 , S k21  to S k27 , S k31  to S k37 , S k41  to S k47  and S k51  to S k57  arranged in the matrix circuit 270. 
     FIG. 31 shows the correspondence between the outputs of the respective AND gates AU 131 , AU 132 , AU 133 , AU 134 , and AU 135  of the upper data comparators 271 to 274 and the set output data code pattern of the respective encoder lines LN 221  and LN 222  of the upper data encoder 275. 
     The setting of the data is carried out in such a manner that, in accordance with the direction of transition of the reference voltage level by the respective reference resistance elements in the rows among the serially connected reference resistance element groups which are folding-arranged so that the number of rows becomes five, concretely an orientation (hereinafter referred to as a direction) of transition of the reference voltage from the low potential side to the high potential side, so that (data of L mode)≧(data of R mode) and (data of L mode)≦(data of R mode) stands. 
     In the structure of FIG. 30, the first row from the bottom comprising the resistance elements R 256  and R 255 , the third row comprising the resistance elements R 250  to R 247 , and the fifth row comprising the resistance elements R 242  and R 241  have the same direction, and the second row comprising the resistance elements R 254  to R 251  and the fourth row comprising the resistance elements R 246  to R 243  have the same direction. 
     Accordingly, the data setting level in the case where the AND gates AU 135 , AU 133 , and AU 131  corresponding to the first row, third row, and fifth row are at the &#34;1&#34; level is set so that the data of the L mode becomes equal to or larger than the data of the R mode. 
     Contrary to this, the data setting level in the case where the AND gates AU 134  and AU 132  corresponding to the second row and the fourth row are at the &#34;1&#34; level is set so that the data of the L mode becomes equal to or smaller than the data of the R mode. 
     The lower data comparators 281 to 287 respectively are provided with comparators CD 141  to CD 147 , complementary-type output amplifiers CA 141  to CA 147  , and AND gates AD 141  to AD 147 . 
     To one input of the comparator CD 141  of the lower data comparator 281 is supplied the collector output of the transistors Q 231  of the switching blocks S k11 , S k31 , and S k51  at the first column of the matrix circuit 270 and the collector outputs of the transistors Q 232  of the switching blocks S k21  and S k41 , and to the other input is supplied the collector outputs of the transistors Q 231  of the switching blocks S k21  and S k41  and the collector outputs of the transistors Q 232  of the switching blocks S k11 , S k31 , and S k51 . 
     To one input of the comparator CD 142  of the lower data comparator 282 is supplied the collector output of the transistors Q 231  of the switching blocks S k12 , S k32 , and S k52  of the second column of the matrix circuit 270 and the collector outputs of the transistors Q 232  of the switching blocks S k22  and S k42 , and to the other input is supplied the collector outputs of the transistors Q 231  of the switching blocks S k22  and S k42  and the collector outputs of the transistors Q 232  of the switching blocks S k12 , S k32 , and S k52 . 
     To one input of the comparator CD 143  of the lower data comparator 283 is supplied the collector output of the transistors Q 231  of the switching blocks S k13 , S k33 , and S k53  at the third column of the matrix circuit 270 and the collector outputs of the transistors Q 232  of the switching blocks S k23  and S k43 , and to the other input is supplied the collector outputs of the transistors Q 231  of the switching blocks S k23  and S k43  and the collector outputs of the transistors Q 232  of the switching blocks S k13 , S k33 , and S k53 . 
     To one input of the comparator CD 144  of the lower data comparator 284 is supplied the collector output of the transistors Q 231  of the switching blocks S k14 , S k34 , and S k54  of the fourth column of the matrix circuit 270 and the collector outputs of the transistors Q 232  of the switching blocks S k24  and S k44 , and to the other input is supplied the collector outputs of the transistors Q 231  of the switching blocks S k24  and S k44  and the collector outputs of the transistors Q 232  of the switching blocks S k14 , S k34 , and S k54 . 
     To one input of the comparator CD 145  of the lower data comparator 285 is supplied the collector output of the transistors Q 231  of the switching blocks S k15 , S k35 , and S k55  at the fifth column of the matrix circuit 270 and the collector outputs of the transistors Q 232  of the switching blocks S k25  and S k45 , and to the other input is supplied the collector outputs of the transistors Q 231  of the switching blocks S k25  and S k45  and the collector outputs of the transistors Q 232  of the switching blocks S k15 , S k35 , and S k55 . 
     To one input of the comparator CD 146  of the lower data comparator 286 is supplied the collector output of the transistors Q 231  of the switching blocks S k16 , S k36 , and S k56  at the sixth column of the matrix circuit 270 and the collector outputs of the transistors Q 232  of the switching blocks S k26  and S k46 , and to the other input is supplied the collector outputs of the transistors Q 231  of the switching blocks S k26  and S k46  and the collector outputs of the transistors Q 232  of the switching blocks S k16 , S k36 , and S k56 . 
     To one input of the comparator CD 147  of the lower data comparator 287 is supplied the collector output of the transistors Q 231  of the switching blocks S k17 , S k37 , and S k57  at the seventh column of the matrix circuit 270 and the collector outputs of the transistors Q 232  of the switching blocks S k27  and S k47 , and to the other input is supplied the collector outputs of the transistors Q 231  of the switching blocks S k27  and S k47  and the collector outputs of the transistors Q 232  of the switching blocks S k17 , S k37 , and S k57 . 
     The output of the comparator CD 141  of the lower data comparator 281 is connected to the input of the output amplifier CA 141 , the positive output thereof is connected to both inputs of the 2-input AND gate AD 141 , and the negative output is connected to one input of the 2-input AND gate AD 142  of the lower data comparator 282. 
     The output of the comparator CD 142  of the lower data comparator 282 is connected to the input of the output amplifier CA 142 , the positive output thereof is connected to the other input of the 2-input AND gate AD 142 , and the negative output is connected to one input of the 2-input AND gate AD 143  of the lower data comparator 283. 
     The output of the comparator CD 143  of the lower data comparator 283 is connected to the input of the output amplifier CA 143 , the positive output thereof is connected to the other input of the 2-input AND gate AD 143 , and the negative output is connected to one input of the 2-input AND gate AD 144  of the lower data comparator 284. 
     The output of the comparator CD 144  of the lower data comparator 284 is connected to the input of the output amplifier CA 144 , the positive output thereof is connected to the other input of the 2-input AND gate AD 144 , and the negative output is connected to one input of the 2-input AND gate AD 145  of the lower data comparator 285. 
     The output of the comparator CD 145  of the lower data comparator 285 is connected to the input of the output amplifier CA 145  , the positive output thereof is connected to the other input of the 2-input AND gate AD 145 , and the negative output is connected to one input of the 2-input AND gate AD 146  of the lower data comparator 286. 
     The output of the comparator CD 146  of the lower data comparator 286 is connected to the input of the output amplifier CA 146 , the positive output thereof is connected to the other input of the 2-input AND gate AD 146 , and the negative output is connected to one input of the 2-input AND gate AD 147  of the lower data comparator 287. 
     The output of the comparator CD 147  of the lower data comparator 287 is connected to the input of the output amplifier CA 147 , the positive output thereof is connected to the other input of the 2-input AND gate AD 147 , and the negative output is connected to both inputs of the 2-input AND gate AD 148 . 
     The outputs of the respective comparators CD 141  to CD 147  of the lower data comparators 281 to 287 constituted in this way become the level of &#34;H&#34; or &#34;L&#34; corresponding to the level of 2 inputs, and only one of the respective AND gates AD 141  to AD 148  outputs the &#34;1&#34; level. 
     The outputs of the AND gates AD 141  to AD 147  and AD 148  of the lower data comparators 281 to 287 are connected via the buffers BD 141  to BD 148  to the lower data encoder 276. 
     The lower data encoder 276 is constituted by a data line LN 223  generating lower significant data BD 153  and BD 154  ; a selection line LN 224  generating the selection signal SEL 121  indicating that one of the outputs of the AND gates AD 141  to AD 144  of the lower data comparators 281 to 284 becomes &#34;1&#34;; and a selection line LN 225  generating the selection signal SEL 122  indicating that one of the outputs of the AND gates AD 145  to AD 147  and AD 148  of the lower data comparators 285 to 287 becomes &#34;1&#34;. 
     FIG. 32 shows the correspondence between the outputs of the AND gates AD 141  to AD 145  on the upper data side and the outputs of the AND gates AD 141  to AD 148  on the lower data side and the output conversion code data. 
     As mentioned above, in the matrix circuit 170 in the present embodiment, the respective switching blocks are divided into two in the row direction. At this division point C, as seen from FIG. 32, when paying attention to the upper significant 2 bits of the output conversion codes D 1  to D 4 , the division is made at the point at which the value of the upper significant 2 bits is switched. 
     The selection gate 279 is constituted by AND gates A 121  to A 124 , selects a single upper significant data from among the respective upper significant data of the L mode and R mode output from the upper data encoder 275 using the selection signals SEL 121  and SEL 122  output from the lower data encoder 276, and outputs the same via the OR-gates OR 121  and OR 122  as the conversion codes D 1  and D 2 . 
     Concretely, one input terminal of the AND gate A 121  is connected to one line (upper data side) of the encoder line LN 221  generating the data for the L mode of the upper data encoder 275, and the other input terminal is connected to the selection line LN 224  outputting the selection signal SEL 121  of the lower data encoder 276. 
     One input terminal of the AND gate A 122  is connected to one line (upper data side) of the encoder line LN 222  generating the data for the R mode of the upper data encoder 275, and the other input terminal is connected to the selection line LN 223  outputting the selection signal SEL 122  of the lower data encoder 276. 
     The outputs of these AND gates A 121  and A 122  are connected to the respective input terminals of the 2-input OR-gate OR 121 . 
     One input terminal of the AND gate A 123  is connected to the other line (lower data side) of the encoder line LN 221  generating the data for the L mode of the upper data encoder 275, and the other input terminal is connected to the selection line LN 224  outputting the selection signal SEL 121  of the lower data encoder 276. 
     One input terminal of the AND gate A 124  is connected the other line (lower data side) of the encoder line LN 222  generating the data for the R mode of the upper data encoder 275, and the other input terminal is connected to the selection line LN 225  outputting the selection signal SEL 122  of the lower data encoder 276. 
     The outputs of these AND gates A 123  and A 124  are connected to the respective input terminals of the 2-input OR-gate OR 122 . 
     The exclusive-OR gate EXO 121  obtains the exclusive-OR between the lower significant data BD 153  output from one line of the data line LN 223  of the lower data encoder 276 and the signal obtained by inverting the sum of output levels of the AND gates AU 131 , AU 133 , or AU 135  of the upper data comparators 271 and 273 by the inverter 278, and outputs the result thereof as the lower data conversion code D 3 . 
     The exclusive-OR gate EXO 122  obtains the exclusive-OR between the lower significant data BD 154  output from the other line of the data line LN 223  of the lower data encoder 276 and the signal obtained by inverting the sum of output levels of the AND gates AU 131 , AU 133 , or AU 135  of the upper data comparators 271 and 273 by the inverter 278 and outputs the result thereof as the lower data conversion code D 4 . 
     Next, an explanation will be made of the operation by the above-described structure. 
     For example, when the sampling voltage V S  of the sampled analog signal is represented as V RB  &lt;V S  &lt;V 284 , the outputs of the comparators CU 131  to CU 134  of the upper data comparators 271 to 274 become all &#34;L&#34;, so that the digital signals are output, i.e., &#34;0&#34; is output from the AND gates AU 131  to AU 134 , and &#34;1&#34; is output from the AND gate AU 135 , respectively. 
     As a result, a digital signal such as [0000] is input to the upper data encoder 275. At the upper data encoder 275, using a so-called wired-OR circuit, the upper significant data of [00] are generated in two columns of encoder lines [LN 221  ] generating the redundant L mode data and two columns of encoder lines [LN 222  ] generating the redundant R mode data, respectively, which are output to the selection gate 275. 
     Also, when the sampling voltage V S  is represented as V 284  &lt;V S  &lt;V 283 , the outputs of the comparators CU 131  to CU 133  of the upper data comparators 271 to 273 become &#34;L&#34;, and the output of the comparator CU 134  of the upper data comparator 274 becomes &#34;H&#34;, so that the digital signals are output, i.e., &#34;0&#34; is output from the AND gates AU 131  to AU 133  and AU 135  of the upper data comparators 271 to 273, and &#34;1&#34; is output from the AND gate AU 134  of the upper data comparator 274, respectively. 
     As a result, a digital signal such as [0001] is input to the upper data encoder 275. At the upper data encoder 275, using a so-called wired-OR circuit, the upper significant data are generated, i.e., [00] is generated in two columns of encoder lines [LN 221  ] generating the redundant L mode data, and [01] is generated in two columns of encoder lines [LN 222  ] generating the redundant R mode data, respectively, which are output to the selection gate 275. 
     Also, when the sampling voltage V S  is represented as V 283  &lt;V S  &lt;V 282 , similarly digital signals are output, i.e., &#34;0&#34; is output from the upper data side AND gates AU 131 , AU 132 , AU 134 , and AU 135 , and &#34;1&#34; is output from the AND gate AU 133 , respectively. 
     As a result, a digital signal such as [0010] is input to the upper data encoder 275, and the upper significant data are output, i.e., [10] is output from the line [LN 221  ], and [01] is output from the line [LN 222  ] to the selection gate 275. 
     Further, when the sampling voltage V S  is represented as V 282  &lt;V S  &lt;V 281 , the digital signals are output, i.e., &#34;0&#34; is output from the upper data side AND gates AU 131 , AU 133 , AU 134 , and AU 135 , and &#34;1&#34; is output from the AND gate AU 132 , respectively. 
     As a result, a digital signal such as [0100] is input to the upper data encoder 275, and the upper significant data are output, i.e., [10] is output from the line [LN 221  ], and [11] is output from the line [LN 222  ] to the selection gate 275. 
     Similarly, when the sampling voltage V S  is represented as V 281  &lt;V S  &lt;V RT , the digital signals are output, i.e., &#34;0&#34; is output from the upper data side AND gates AU 132 , AU 133 , AU 134 , and AU 135 , and &#34;1&#34; is output from the AND gate AU 131 , respectively. 
     As a result, a digital signal such as [1000] is input to the upper data encoder 275, and the upper significant data are output, i.e., [11] is output from the line [LN 221  ], and [11] is output from the line [LN 222  ] to the selection gate 275. 
     In parallel with this, the transistors Q 233  of the respective switching blocks of the matrix circuit 270 connected to the control lines (x 131 , x 132 , x 133 , x 134 , and X 135 ) at which the digital output signal has become &#34;1&#34; among the respective AND gates AU.sub.(131, 132, 133, 134, 135) are controlled to turn ON in units of rows, and further a fine digitization of the quantization level is executed. 
     For example, when only the output of the AND gate AU 133  becomes the &#34;1&#34; level, the transistors Q 233  of the switching blocks S k31  to S k37  become ON, so that the reference voltages V 267  to V 270  (=V 283 ) divided by the reference resistors R 247  to R 251  and the sampling voltage V S  are differentially amplified at the switching blocks S k33  to S k36  and compared by the lower data comparators 281 to 287. 
     Similarly, when the output of the AND gate AU 132  is at the &#34;1&#34; level, the switching blocks S k21  to S k27  are activated, so that a differential amplification operation is performed, and the comparison by the lower data comparators 281 to 287 is carried out. 
     In this way, in the lower data conversion codes, the sampled voltage V S  and the reference voltage divided by the reference resistance of that row are compared in units of rows of the switching blocks, so that the digital signal in accordance with the result of comparison will be output from the AND gates AD 141  to AD 147  and AD 148  of the lower data comparators 281 to 287. 
     At this time, in a case where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 284  &gt;V IN , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as V RB  &lt;V IN  &lt;[(V 284  +V 283 )/2], or in a case where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as V RB  &lt;V IN  &lt;[(V 284  +V 283 )/2], or in a case where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 283  &lt;V IN  &lt;V 282 , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as [(V 283  +V.sub. 282)/2]&lt;V IN  &lt;[(V 281  +V 282 )/2], or in a case where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 282  &lt;V IN  &lt;V 281 , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as [(V 283  +V 282 )/2]&lt;V IN  &lt;[(V 281  +V 282 )/2], in the lower data encoder 276, only the selection line LN 224  becomes &#34;1&#34;. 
     As a result, the selection signal SEL 121  is input to the selection gate 279 as the &#34;1&#34; level, and the selection signal SEL 122  is input to the selection gate 279 as the &#34;0&#34; level. 
     In the selection gate 279, along with the fact that only the selection signal SEL 121  is input as the &#34;1&#34; level, only the AND gates A 121  and A 123  are activated. 
     To these AND gates A 121  and A 123 , the bit data of the upper data side and lower data side of the upper significant data for the L mode generated in the line LN 221  of the upper data encoder 275 are respectively supplied. 
     Accordingly, in the selection gate 279, the respective bits of the upper significant data at the L mode are selected, and as a result, they are output as the upper significant data conversion codes D 1  and D 2  via the OR gates OR 121  and OR 122 . 
     Concretely, when the sampling voltage V S  of the analog signal V IN  is defined as V RB  &lt;V S  &lt;V 284 , the upper data conversion codes [D 1 , D 2  ] are output as [00]; when V 284  &lt;V S  &lt;V 283  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [00]; when V 283  &lt;V S  &lt;V 282  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [10]; when V 282  &lt;V S  &lt;V 281  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [10]; and when V 281  &lt;V S  &lt;V RT  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [11]. 
     Also, in the lower data encoder 276, when the output of the AND gate AD 141  of the lower data comparator 281 is &#34;1&#34;, the lower significant data BD 153  and BD 154  are generated as [11]; when the output of the AND gate AD 142  of the lower data comparator 282 is &#34;1&#34;, the lower significant data BD 153  and BD 154  are generated as [10]; when the output of the AND gate AD 143  of the lower data comparator 283 is &#34;1&#34;, the lower significant data BD 153  and BD 154  are generated as [01]; and when the output of the AND gate AD 144  of the lower data comparator 284 is &#34;1&#34;, the lower significant data BD 153  and BD 154  are generated as [00], the data BD 153  is output to the exclusive-OR gate EXO 121 , and the data BD 154  is output to the exclusive-OR gate EXO 122 . 
     In the exclusive-OR gates EXO 121  and EXO 122 , when V 284  &lt;V S  &lt;V 283  and V 282  &lt;V S  &lt;V 281  stand, that is where the switching blocks S k41  to S k47  and S k21  to S k27  of the second row and fourth row from the bottom of the matrix circuit 270 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D 3  and D 4  while inverting the output level of the lower data encoder 276. 
     Contrary to this, when V RB  &lt;V S  &lt;V 284 , V 283  &lt;V S  &lt;V 282  and V 281  &lt;V S  &lt;V RT  stand, that is where the switching blocks S k51  to S k57 , S k31  to S k37 , and S k11  to S k17  at the first row, third row, and fifth row from the bottom of the matrix circuit 270 are selected, since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 276 as they are and output as the lower significant data conversion codes D 3  and D 4 . 
     Also, in a case where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 284  &lt;V IN  &lt;V 283 , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as [(V 284  V 283 )/2]&lt;V IN  &lt;[(V 283  +V 282 )/2], or in a case where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 283  &lt;V IN  &lt;V 282 , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as [(V 284  +V 283 )/2]&lt;V IN  &lt;[(V 283  +V 282 )/2], or in a case where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 282  &lt;V.sub. IN &lt;V 281 , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as [(V 282  +V 281 )/2]&lt;V IN  &lt;V RT , or in a case where the input analog signal when converting the upper significant 2 bits D 1  and D 2  is defined as V 281  &lt;V IN , and the input analog signal when converting the lower significant 2 bits D 3  and D 4  is defined as [(V 2  +V 281 )/2]&lt;V IN  &lt;V RT , in the lower data encoder 276, only the selection line LN 225  becomes &#34;1&#34;. 
     As a result, the selection signal SEL 122  is input to the selection gate 279 as the &#34;1&#34; level, and the selection signal SEL 121  is input to the selection gate 279 as the &#34;0&#34; level. 
     In the selection gate 279, along with the fact that only the selection signal SEL 122  is input as the &#34;1&#34; level, only the AND gates A 122  and A 124  are activated. 
     To these AND gates A 122  and A 124 , the bit data of the upper data side and lower data side of the upper significant data for the R mode generated in the line LN 222  of the upper data encoder 275 are respectively supplied. 
     Accordingly, in the selection gate 279, the respective bits of the upper significant data at the R mode are selected, and as a result, they are output as the upper significant data conversion codes D 1  and D 2  via the OR gates OR 121  and OR 122 . 
     Concretely, when the sampling voltage V S  of the analog signal V IN  is defined as V RB  &lt;V S  &lt;V 284 , the upper data conversion codes [D 1 , D 2  ] are output as [00]; when V 284  &lt;V S  &lt;V 283  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [01]; when V 283  &lt;V S  &lt;V 282  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [01]; when V 282  &lt;V S  &lt;V 281  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [11]; and when V 281  &lt;V S  &lt;V RT  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [11]. 
     Also, in the lower data encoder 276, when the output of the AND gate AD 145  of the lower data comparator 285 is &#34;1&#34;, the lower significant data BD 153  and BD 154  are generated as [11]; when the output of the AND gate AD 146  of the lower data comparator 286 is &#34;1&#34;, the lower significant data BD 153  and BD 154  are generated as [10]; when the output of the AND gate AD 147  of the lower data comparator 287 is &#34;1&#34;, the lower significant data BD 153  and BD 154  are generated as [01]; and when the output of the AND gate AD 148  is &#34;1&#34;. the lower significant data BD 153  and BD 154  are generated as [00], the data BD 153  is output to the exclusive-OR gate EXO 121 , and the data BD 154  is output to the exclusive-OR gate EXO 122 . 
     In the exclusive-OR gates EXO 121  and EXO 122 , when V 284  &lt;V S  &lt;V 283  and V 282  &lt;V S  &lt;V 281  stand, that is where the switching blocks S k41  to S k47  and S k21  to S k27  at the second row and fourth row from the bottom of the matrix circuit 270 are selected, since the direction of application of the reference voltage is the forward direction, the levels of the lower significant data are output as the lower significant data conversion codes D 3  and D 4  while inverting the output level of the lower data encoder 276. 
     Contrary to this, when V RB  &lt;V S  &lt;V 284 , V 283  &lt;V S  &lt;V 282  and V 281  &lt;V S  &lt;V RT  stand, that is where the switching blocks S k51  to S k57 , S k31  to S k37 , and S k11  to S k17  at the first row, third row, and fifth row from the bottom of the matrix circuit 270 are selected, since the direction of application of the reference voltage is the inverse direction, the levels of the lower significant data are held at the output level of the lower data encoder 276 as they are and output as the lower significant data conversion codes D 3  and D 4 . 
     As explained above, according to the present embodiment, the lower significant codes are divided into two groups, and the signals SEL 221  and SEL 222  for selecting the L mode data and R mode data are output from the lower data encoder 276 obtaining these groups of conversion code, so that the L mode data and R mode data output from the upper data encoder 275 are selected, thereby obtaining the upper data conversion codes D 1  and D 2 , and therefore it is possible to use the selection signal directly for the selection of the upper significant data without the use of the inverted gate and inhibit gate as in the conventional circuit. 
     Accordingly, the input of the selection signal to the selection gate 275 is not delayed relative to the output of the upper data encoder 270, and thus the increase of speed of conversion processing can be achieved. 
     Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, the number of selection signals can be reduced to two, and also the number of the upper significant codes to be selected and the number of the input gates of the selection gates can be reduced to two, and therefore an A/D converter circuit with which the reduction of the surface area of the chip and the reduction of the power consumption can be achieved can be realized. 
     FIGS. 33A-33C are circuit diagrams showing a 12th embodiment of the A/D converter circuit according to the present invention. 
     The point of difference of the present embodiment from the above-mentioned 11th embodiment resides in the constitution whereby the number of the selection lines of the lower data encoder 306 is reduced to only one line, i.e., LN 252 , to generate only one selection signal SEL 161  selected from among the selection signals, and a signal obtained by inverting the level of the selection signal SEL 161  at the inverter 309 is supplied as the signal in place of the selection signal SEL 122  to the other inputs of the AND gates A 152  and A 154  of the selection gate 307. 
     According to the present 12th embodiment, in addition to the effect of the above-described 11th embodiment, a simpler structure can be realized, and the chip area can be further reduced. 
     Note that, in the above-mentioned 11th and 12th embodiments, an explanation was made taking as an example an A/D converter circuit for four bits, but needless to say the present invention can be applied to an A/D converter circuit for more bits as well. 
     Also, in the above-mentioned 11th and 12th embodiments, the structure in which the other output pin buffers are arranged on the input side of the upper data encoder and the lower data encoder was indicated, but these other output pin buffers are provided so as to reliably drive the upper data encoder and the lower data encoder, and it is necessary to provide the same according to a certain capacitance of the upper data encoder and the lower data encoder acting as a so-called load. 
     As explained above, according to the present invention, there are advantages such that the inverted gate and inhibit gate which have been conventionally necessary become unnecessary, the increase of speed of conversion processing can be achieved. Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, the number of the selection signals can be reduced and the number of the upper data codes to be selected and the number of the input gates of selection gates can be reduced, so there is an advantage that the reduction of the chip area and the reduction of the power consumption can be achieved. 
     FIG. 34 is a circuit diagram showing a 13th embodiment of the A/D converter circuit according to the present invention. 
     In FIG. 34, 330 denotes a matrix circuit; 331 and 332 denote upper data comparators; 333, an upper data encoder; 341 to 348 denote lower data comparators; 334, a lower data encoder; 335, a selection gate; 336, an inverter; R 301  to R 316  denote reference resistance elements; r, a resistance element for load; BU 331  to BU 333  and BD 181  to BD 188  denote multiple output pin buffers; OR U171  to OR U174  denote upper data side 2-input OR-gates; OR D1  to OR D2  denote lower data side 2-input OR-gates; and OR 301  and OR 302  denote 2-input OR-gates for outputting the conversion code; respectively. 
     The matrix circuit 330 is constituted in the form of a so-called zigzag-shaped matrix comprising 4 rows and 8 columns in which two switching blocks selected from among 16 switching blocks S m12 , S m14 , S m16 , S m18 , S m21 , S m23 , S m25 , S m27 , S m32 , S m34 , S m36 , S m38 , and S m41 , S m43 , S m45 , S m47  are arranged in each column. 
     The specific arrangement is one where the switching blocks S m12 , S m14 , S m16 , and S m18  are arranged in the upper stage; the switching blocks S m21 , S m23 , S m25 , and S m27  are arranged in the next stage; the switching blocks S m32 , S m34 , S m36 , and S m38  are arranged in a lower stage than this; and the switching blocks S m41 , S m43 , S m45 , and S m47  are arranged in the lowermost stage, and the switching blocks S m41 , S m43 , S m45  and S m47  and S m21 , S m23 , S m25  and S m27  arranged at the first row and third row from the bottom are formed into sets, whereby the first, third, fifth, and seventh columns are constituted; and the switching blocks S m32 , S m34 , S m36  and S m38  and S m12 , S m14 , S m16  and S m18  are formed into sets, whereby the second, fourth, sixth and eighth columns are constituted. 
     The respective switching blocks S m12 , S m14 , S m16 , S m18 , S m21 , S m23 , S m25 , S m27 , S m32 , S m34 , S m36 , S m38 , and S m41 , S m43 , S m45 , S m47  are constituted by differential type amplifiers comprising the npn-type transistors Q 261 , Q 262  and Q 263 . 
     Reference voltages V 331  to V 345  obtained by dividing the reference voltages V RT  to V RB  by the reference resistance elements R 301  to R 316  are supplied to the base of one side transistors Q 261  constituting a so-called differential pair of the respective switching blocks, respectively, and analog signals V IN  which are to be converted to a digital code are supplied to the base of the other side transistors Q 262 , respectively. 
     Also, the emitters of the transistors Q 261  and Q 262  are connected to each other, and the middle point of connection thereof is connected to the current source I via the transistor Q 263  switched by the control signals x 171   to x 174  of the OR-gates ORU 171  to ORU 174 , respectively. 
     To the collectors of the transistors Q 261  and Q 262 , the power source voltage V DD  is supplied via the resistance element r, the output of which is respectively input to the comparators CD 181  to CD 188  of the eight lower data comparators 341 to 348 as mentioned later, which act also as the initial stage amplifiers of the lower data comparators 341 to 348. 
     The reference resistance elements R 301  to R 316  are serially connected between the two reference potentials V RT  and V RB  and arranged by folding-back so as to extend over a predetermined number of rows, e.g., four rows in the present embodiment, to correspond to the matrix arrangement of the switching blocks in the matrix circuit 330. 
     Concretely, resistance elements R 316  to R 313  are serially connected at the first row from the bottom in the diagrams as to correspond to the switching blocks S m41 , S m43 , S m45  and S m47  ; resistance elements R 312  to R 309  are serially connected at the second row so as to correspond to the switching blocks S m32 , S m34 , S m36  and S m38  ; resistance elements R 308  to R 305  are serially connected at the third row so as to correspond to the switching blocks S m21 , S m23 , S m25  and S m27  ; and resistance elements R 304  to R 301  are serially connected at the fourth row so as to correspond to the switching blocks S m12 , S m14 , S m16  and S m18 . 
     Also, the reference voltage V 331  (=V 351 ) generated at the middle point of connection between the resistance elements R 306  and R 307  constituting the resistance column at the third row from the bottom; and the reference voltage V 340  (=V 352 ) generated at the middle point of connection between the resistance elements R 310  and R 311  constituting the resistance column at the second row are supplied to the upper data comparators 331 and 332 as the reference voltages obtained by dividing the reference potentials V RT  to V RB  by rough quantization, respectively. 
     In the structure of FIG. 34, when assuming that the voltage between the reference potentials V RT  to V RB  is V REF , the respective reference voltages V 351  and V 352  become the following values, respectively: 
     
         V.sub.336 =V.sub.351 =(10/16)·V.sub.REF 
    
     
         V.sub.340 =V.sub.352 =(6/16)·V.sub.REF 
    
     Wiring is carried out so that the respective reference voltages V 331  to V 345  divided by the reference resistance elements R 301  to R 316  are supplied to the base of the transistor Q 261  of the predetermined switching block. 
     Concretely, a reference voltage V 331  [=(15/16)·V REF  ] generated at the connection point between the resistance elements R 301  and R 302  is supplied to the base of the transistor Q 261  of the switching block S M12 . 
     A reference voltage V 332  [=(14/16)·V REF  ] generated at the connection point between the resistance elements R 302  and R 303  is supplied to the base of the transistor Q 261  of the switching block S m14 . 
     A reference voltage V 333  [=(13/16)·V REF  ] generated at the connection point between the resistance elements R 303  and R 304  is supplied to the base of the transistor Q 261  of the switching block S m16 . 
     A reference voltage V 334  [=(12/16)·V REF  ] generated at the connection point between the resistance elements R 304  and R 305  is supplied to the base of the transistor Q 261  of the switching block S m18 . 
     A reference voltage V 335  [=(11/16)·V REF  ] generated at the connection point between the resistance elements R 305  and R 306  is supplied to the base of the transistor Q 261  of the switching block S m27 . 
     A reference voltage V 336  [=V 351  =(10/16)·V REF  ] generated at the connection point between the resistance elements R 306  and R 307  is supplied to the base of the transistor Q 261  of the switching block S m25 . 
     A reference voltage V 337  [=(9/16)·V REF  ] generated at the connection point between the resistance elements R 307  and R 308  is supplied to the base of the transistor Q 261  of the switching block S m23 . 
     A reference voltage V 338  [=(8/16)·V REF  ] generated at the connection point between the resistance elements R 308  and R 309  is supplied to the base of the transistor Q 261  of the switching block S m21 . 
     A reference voltage V 339  [=(7/16)·V REF  ] generated at the connection point between the resistance elements R 309  and R 310  is supplied to the base of the transistor Q 261  of the switching block S m32 . 
     A reference voltage V 340  [=V 352  =(6/16)·V REF  ] generated at the connection point between the resistance elements R 310  and R 311  is supplied to the base of the transistor Q 261  of the switching block S m34 . 
     A reference voltage V 341  [=(5/16)·V REF  ] generated at the connection point between the resistance elements R 311  and R 312  is supplied to the base of the transistor Q 261  of the switching block S m36 . 
     A reference voltage V 342  [=(4/16)·V REF  ] generated at the connection point between the resistance elements R 312  and R 313  is supplied to the base of the transistor Q 261  of the switching block S m38 . 
     A reference voltage V 343  [=(3/16)·V REF  ] generated at the connection point between the resistance elements R 313  and R 314  is supplied to the base of the transistor Q 261  of the switching block S m47 . 
     A reference voltage V 344  [=(2/16)·V REF  ] generated at the connection point between the resistance elements R 314   and R 315  is supplied to the base of the transistor Q 261  of the switching block S m45 . 
     A reference voltage V 345  [=(1/16)·V REF  ] generated at the connection point between the resistance elements R 315  and R 316  is supplied to the base of the transistor Q 261  of the switching block S m43 . 
     Upper data comparators 331 and 332 respectively are provided with comparators CU 171  and CU 172 , complementary-type output amplifiers CA 171  to CA 173  and AND gates AU 171  and AU 172 . 
     An analog signal V IN  is supplied to one input of the comparator CU 171  of the upper data comparator 331, and a reference voltage V 351  [=V 336  =(10/16)·V REF  ] obtained by dividing the reference potentials V RT  to V RB  by rough quantization is supplied to the other input. 
     The analog signal V IN  is supplied to one input of the comparator CU 172  of the upper data comparator 332, and a reference voltage V 352  [=V 340  =(6/16)·V REF  ] obtained by dividing the reference potentials V RT  to V RB  by rough quantization is supplied to the other input. 
     The output of the comparator CU 171  of the upper data comparator 331 is connected to the input of the output amplifier CA 171 , the positive output thereof is connected to both inputs of a 2-input AND gate AU 171 , and the negative output is connected to one input of the 2-input AND gate AU 172  of the upper data comparator 332. 
     The output of the comparator CU 172  of the upper data comparator 332 is connected to the input of the output amplifier CA 172 , the positive output thereof is connected to the other input of the 2-input AND gate AU 172 , and the negative output is connected to one input of the 2-input AND gate AU 173 . 
     The outputs of the respective comparators CU 171  and CU 172  of the upper data comparators 331 and 332 constituted in this way become the level of &#34;H&#34; or &#34;L&#34; corresponding to the level of the sampled analog signal V IN , and only one among the respective AND gates AU 171  to AU 173  outputs the &#34;1&#34; level. 
     The output of the AND gate AU 171  of the upper data comparator 331 is connected via the buffer BU 171  to the inputs of the upper data encoder 333 and inverter 336, and the 2-input OR-gate OR D1  on the lower significant side and, at the same time, connected to both inputs of the 2-input OR-gate OR U171  and one input of the 2-input OR-gate OR U172 . 
     The output of the OR-gate OR U171  is supplied as the control signal x 171  to the bases of the transistors Q 263  of the switching blocks S m12 , S m14 , S m16 , and S m18 , and the output of the OR-gate OR U172  is supplied as the control signal x 172  to the bases of the transistors Q 263  of the switching blocks S m21 , S m23 , S m25  and S m27 . 
     Accordingly, where the output of the AND gate AU 171  of the upper data comparator 331 becomes the &#34;1&#34; level (V 251  &lt;V IN  &lt;V RT ), the switching blocks S m21 , S m23 , S m25  and S m27  of the third row from the bottom and the switching blocks S m12 , S m14 , S m16  and S m18  of the fourth row are activated. 
     The output of the AND gate AU 172  of the upper data comparator 332 is connected via the buffer BU 172  to the inputs of the upper data encoder 333 and, at the same time, connected to the other input of the 2-input OR-gate OR U172  and one input of the 2-input OR-gate OR U173 . 
     The output of the OR-gate OR U172  is supplied as the control signal x 172  to the bases of the transistors Q 263  of the switching blocks S m21 , S m23 , S m25  and S m27  as mentioned above, and the output of the OR-gate OR U173  is supplied as the control signal x 173  to the bases of the transistors Q 263  of the switching blocks S m32 , S m34 , S m36  and S m38 . 
     Accordingly, where the output of the AND gate AU 172  of the upper data comparator 332 becomes the &#34;1&#34; level (V 352  &lt;V IN  &lt;V 351 ), the switching blocks S m21 , S m23 , S m25  and S m27  of the third row from the bottom and the switching blocks S m32 , S m34 , S m36  and S m38  of the second row are activated. 
     The output of the AND gate AU 173  is connected via the buffer BU 173  to the inputs of the upper data encoder 333 and inverter 336, and the 2-input OR-gate OR D1  on the lower data side and, at the same time, connected to the other input of the 2-input OR-gate OR U173  and both inputs of the 2-input OR-gate OR U174 . 
     The output of the OR-gate OR U173  is supplied as the control signal x 173  to the bases of the transistors Q 263  of the switching blocks S m32 , S m34 , S m36  and S m38  as mentioned above, and the output of the OR-gate OR U174  is supplied as the control signal x 174  to the bases of the transistors Q 263  of the switching blocks S m41 , S m42 , S m43  and S m44 . 
     Accordingly, where the output of the AND gate AU 173  becomes the &#34;1&#34; level (V RB  &lt;V IN  &lt;V 252 ), the switching blocks S m32 , S m34 , S m36  and S m38  at the second row from the bottom and the switching blocks S m41 , S m43 , S m45  and S m47  are activated. 
     The upper data encoder 333 is constituted by an encoder line LN 271  generating the data for the first mode, and an encoder line LN 272  generating the data for the second mode. 
     Namely, in the upper data encoder 333, respective encoder lines LN 271  and LN 272  are set in correspondence with a first group comprising switching block columns constituting odd number columns and a second group comprising switching block columns constituting even number columns among switching blocks S m12 , S m14 , S m16 , S m18 , S m21 , S m23 , S m25 , S m27 , S m32 , S m34 , S m36 , S m38 , and S m41 , S m43 , S m45 , S m47  arranged in the matrix circuit 330. 
     FIG. 35 shows the correspondence between the outputs of the respective AND gates AU 171 , AU 172  and AU 173  of the upper data comparators 331 and 332 and the set output data code pattern of the respective encoder lines LN 271  and LN 272  of the upper data encoder 333. 
     The setting of the data is basically determined by the data arrangement of FIG. 36 mentioned later, and the value of the set data is set so that, by using the generation position of the reference potential V RB , reference voltages V 332  and V 340  as the reference, in accordance with whether the direction of transition of the reference voltage level by the respective reference resistance elements, concretely an orientation (hereinafter referred to as a direction) of transition of the reference voltage from the low potential side to the high potential side is the right direction or left direction, so that the data of the first mode&lt;the data of the second mode and the data of the first mode&lt;the data of the second mode stand. 
     Accordingly, the data setting level in the case where the AND gates AU 173  and AU 171  are at the &#34;1&#34; level when V RB  &lt;V IN  &lt;V 340  (V 352 ) and V 336  (V 351 )&lt;V IN  &lt;V RT  is set so that the data of the first mode&lt;the data of the second mode stands. 
     Contrary to this, the data setting level in the case where the AND gate AU 172  is at the &#34;1&#34; level when V 340  (V 352 )&lt;V IN  &lt;V 336  (V 351 ) is set so that the data of the first mode&lt;the data of the second mode stands. 
     The lower data comparators 341 to 348 respectively are provided with comparators CD 181  to CD 188 , complementary-type output amplifiers CA 181  to 188 and AND gates AD 181  to AD 188 . 
     To one input of the comparator CD 181  of the lower data comparator 341 is supplied the collector outputs of the transistors Q 261  of the switching blocks S m21  and S m41  of the first column of the matrix circuit 330, while to the other input is supplied the collector outputs of the transistors Q 262  of the switching blocks S m21  and S m41 . 
     To one input of the comparator CD 182  of the lower data comparator 342 is supplied the collector outputs of the transistors Q 261  of the switching blocks S m12  and S m32  of the second column of the matrix circuit 330, while to the other input is supplied the collector outputs of the transistors Q 262  of the switching blocks S m12  and S m32 . 
     To one input of the comparator CD 183  of the lower data comparator 343 is supplied the collector outputs of the transistors Q 261  of the switching blocks S m23  and S m43  of the third column of the matrix circuit 330, while to the other input is supplied the collector outputs of the transistors Q 262  of the switching blocks S m23  and S m43 . 
     To one input of the comparator CD 184  of the lower data comparator 344 is supplied the collector outputs of the transistors Q 261  of the switching blocks S m14  and S m34  of the fourth column of the matrix circuit 330, while to the other input is supplied the collector outputs of the transistors Q 262  of the switching blocks S m14  and S m34 . 
     To one input of the comparator CD 185  of the lower data comparator 345 is supplied the collector outputs of the transistors Q 261  of the switching blocks S m25  and S m45  of the fifth column of the matrix circuit 330, while to the other input is supplied the collector outputs of the transistors Q 262  of the switching blocks S m25  and S m45 . 
     To one input of the comparator CD 186  of the lower data comparator 346 is supplied the collector outputs of the transistors Q 261  of the switching blocks S m16  and S m36  at the sixth column of the matrix circuit 330, and to the other input is supplied the collector outputs of the transistors Q 262  of the switching blocks S m16  and S m36 . 
     To one input of the comparator CD 187  of the lower data comparator 347 is supplied the collector outputs of the transistors Q 261  of the switching blocks S m27  and S m47  at the seventh column of the matrix circuit 330, and to the other input is supplied the collector outputs of the transistors Q 262  of the switching blocks S m27  and S m47 . 
     To one input of the comparator CD 188  of the lower data comparator 348 is supplied the collector outputs of the transistors Q 261  of the switching blocks S m18  and S m38  at the eighth column of the matrix circuit 330, and to the other input is supplied the collector outputs of the transistors Q 262  of the switching blocks S m18  and S m38 . 
     The output of the comparator CD 181  of the lower data comparator 341 is connected to the input of the output amplifier CA 181 , the positive output thereof is connected to one input of the 2-input AND gate AD 181 , and the negative output is connected to one input of the 2-input OR gate OR D1 . 
     The outputs of the buffers BU 181  and BU 183  receiving the outputs of the AND gates AU 181  and AU 183  on the upper data side are connected to the other input of the OR-gate OR D1 , and the output of the OR-gate OR D1  is connected to one input of the AND gate AD 182  of the lower data comparator 342. 
     The output of the comparator CD 182  of the lower data comparator 342 is connected to the input of the output amplifier CA 182 , the positive output thereof is connected to the other input of the 2-input AND gate AD 182 , and the negative output is connected to one input of the 2-input AND gate AD 184  of the lower data comparator 344. 
     The output of the comparator CD 183  of the lower data comparator 343 is connected to the input of the output amplifier CA 183 , the positive output thereof is connected to one input of the 2-input AND gate AD 183 , and the negative output is connected to the other input of the 2-input AND gate AD 181  of the lower data comparator 341. 
     The output of the comparator CD 184  of the lower data comparator 344 is connected to the input of the output amplifier CA 184 , the positive output thereof is connected to the other input of the 2-input AND gate AD 184 , and the negative output is connected to one input of the 2-input AND gate AD 186  of the lower data comparator 346. 
     The output of the comparator CD 185  of the lower data comparator 345 is connected to the input of the output amplifier CA 185 , the positive output thereof is connected to one input of the 2-input AND gate AD 185 , and the negative output is connected to the other input of the 2-input AND gate AD 183  of the lower data comparator 343. 
     The output of the comparator CD 186  of the lower data comparator 346 is connected to the input of the output amplifier CA 186 , the positive output thereof is connected to one input of the 2-input AND gate AD 186 , and the negative output is connected to one input of the 2-input AND gate AD 188  of the lower data comparator 348. 
     The output of the comparator CD 187  of the lower data comparator 347 is connected to the input of the output amplifier CA 187 , the positive output thereof is connected to one input of the 2-input AND gate AD 187 , and the negative output is connected to the other input of the 2-input AND gate AD 185  of the lower data comparator 345. 
     The output of the comparator CD 188  of the lower data comparator 348 is connected to the input of the output amplifier CA 188 , the positive output thereof is connected to the other input of the 2-input AND gate AD 188 , and the negative output is connected to one input of the 2-input OR gate OR D2 . 
     The output of the inverter 336 inverting the output levels of the buffers BU 171  and BU 173  receiving the outputs of the AND gates AU 171  and AU 173  on the upper data side is connected to the other input of the OR-gate OR D2 , and the output of the OR-gate OR D2  is connected to the other input of the AND gate AD 187  of the lower data comparator 347. 
     A so-called ring comparator is constituted by the lower data comparators 341 to 348 constituted in this way, the outputs of the respective comparators CD 181  to CD 188  become the level of &#34;H&#34; or &#34;L&#34; corresponding to the level of 2 inputs, and only one of the respective AND gates AD 181  to AD 188  outputs the active &#34;1&#34; level. 
     The outputs of the AND gates AD 181  to AD 188  of the lower data comparators 341 to 348 are connected via the buffers B D1  to B D8  to the lower data encoder 334. 
     The lower data encoder 334 is constituted by a data line LN 273  generating lower significant data D 3  and D 4  ; a selection line LN 274  generating the selection signal SEL 171  indicating that one of the outputs of the AND gates AD 181 , AD 183 , AD 185 , and AD 187  of the lower data comparators 341, 343, 345 and 347 becomes &#34;1&#34;; and a selection line LN 275  generating the selection signal SEL 172  indicating that one of the outputs of the AND gates AD 182 , AD 184 , AD 186  and AD 188  of the lower data comparators 342, 344, 346 and 348 becomes &#34;1&#34; 
     FIG. 36 shows the correspondence between the outputs of the AND gates AU 181  to AU 183  on the upper data side and the outputs of the AND gates AD 181  to AD 188  on the lower data side and the output conversion code data. 
     As shown in FIG. 36, the upper data code is determined according to the row in the correspondence table. 
     Namely, in the table, it becomes [00], [01], [10] and [11] in sequence from the lowermost bit row. 
     Contrary to this, the lower bit codes are classified into two types, i.e., [0000] to [0011] and [0100] to [0111] in accordance with the row. 
     From above, the upper data code can be selected from two conditions that which among the upper data side AND gates AU 181  to AU 183  output &#34;1&#34; and which group of AND gate in the first group comprising the odd number of AND gates AD 181 , AD 183 , AD 185  and AD 187  and the second group comprising the even number of AND gates AD 182 , AD 184 , AD 186  and AD 188  among the respective AND gates AD 181  to AD 188  of the lower data comparators 341 to 348 output &#34;1&#34;. 
     For example, where the upper data side AND gate AU 171  outputs &#34;1&#34;, if there is one among the AND gates of the first group of the lower data comparator which outputs &#34;1&#34;, [00] is selected as the upper data code, while if there is one among the AND gates of the second group which outputs &#34;1&#34;, [01] is selected as the upper data code, 
     This selection of the upper data code is carried out at the selection gate 335. 
     The selection gate 335 is constituted by AND gates A 181  to A 184 , selects one side upper significant data from among the respective upper significant data of the first mode and second mode output from the upper data encoder 333 using the selection signals SEL 171  and SEL 172  output from the lower data encoder 334, and outputs the same via the OR-gates OR 301  and OR 302  as the conversion codes D 1  and D 2 . 
     Concretely, one input terminal of the AND gate A 181  is connected to one line (upper data side) of the encoder line LN 271  generating the data for the first mode of the upper data encoder 333, and the other input terminal is connected to the selection line LN 274  outputting the selection signal SEL 171  of the lower data encoder 334. 
     One input terminal of the AND gate A 182  is connected to one line (upper data side) of the encoder line LN 272  generating the data for the second mode of the upper data encoder 333, and the other input terminal is connected to the selection line LN 275  outputting the selection signal SEL 172  of the lower data encoder 334. 
     The outputs of these AND gates A 181  and A 182  connected to the respective input terminals of the 2-input OR-gate OR 301 . 
     One input terminal of the AND gate A 183  is connected to the other line (lower data side) of the encoder line LN 271  generating the data for the first mode of the upper data encoder 333, and the other input terminal is connected to the selection line LN 172  outputting the selection signal SEL 171  of the lower data encoder 334. 
     One input terminal of the AND gate A 184  is connected to the other line (lower data side) of the encoder line LN 272  generating the data for the second mode of the upper data encoder 333, and the other input terminal is connected to the selection line LN 275  outputting the selection signal SEL 172  of the lower data encoder 334. 
     The outputs of these AND gates A 183  and A 184  are connected to the respective input terminals of the 2-input OR-gate OR 302 . 
     Next, an explanation will be made of the operation by the above-described structure. 
     For example, when the sampling voltage V S  of the sampled analog signal is represented as V RB  &lt;V S  &lt;V 352  (=V 340 ), the outputs of the comparators CU 171  and CU 172  of the upper data comparators 331 and 332 become (&#34;L&#34;), so that the digital signals are output, i.e., &#34;0&#34; is output from the AND gates AU 171  and AU 172 , and &#34;1&#34; is output from the AND gate AU 173 , respectively. 
     As a result, a digital signal such as [001] is input to the upper data encoder 333 via the buffers BU 171  to BU 173 . At the upper data encoder 133, using a so-called wired-OR circuit, the upper significant data [00] are generated in two columns of encoder lines [LN 271  ] generating the data for the first mode, and the upper significant data [01] are generated in two columns of encoder lines [LN 272  ] generating the data for the second mode, respectively, which are output to the selection gate 335. 
     Also, if the sampling voltage V S  is represented as V 352  &lt;V S  &lt;V 351  (=V 336 ), the output of the comparator CU 171  of the upper data comparator 331 becomes &#34;L&#34;, and the output of the comparator CU 172  of the upper data comparator 332 becomes &#34;H&#34;, so that the digital signals are output, i.e., &#34;0&#34; is output from the AND gates AU 171  and AU 173  of the upper data comparator 331, and &#34;1&#34; is output from the AND gate AU 172  of the upper data comparator 332, respectively. 
     As a result, a digital signal such as [010] is input to the upper data encoder 333 via the buffers BU 171  to BU 173 . At the upper data encoder 333, using a so-called wired-OR circuit, the upper significant data are generated, i.e., [10] is generated in two columns of encoder lines [LN 271  ] generating the data for the first mode, and [01] is generated in two columns of encoder lines [LN 272  ] generating the data for the second mode, respectively, which are output to the selection gate 335. 
     Also, if the sampling voltage V S  is represented as V 351  &lt;V S  &lt;V RT , the output of the comparator CU 171  of the upper data comparator 331 becomes &#34;H&#34;, and the output of the comparator CU 172  of the upper data comparator 332 becomes &#34;L&#34;, so that the digital signals are output, i.e., &#34;1&#34; is output from the AND gate AU 171  of the upper data comparator 331, and &#34;0&#34; is output from the AND gates AU 172  and AU 173  of the upper data comparator 332, respectively. 
     As a result, a digital signal such as [100] is input to the upper data encoder 333 via the buffers BU 171  to BU 173 . At the upper data encoder 333, using a so-called wired-OR circuit, the upper significant data are generated, i.e. [10] is generated in two columns of encoder lines [LN 271  ] generating the data for the first mode, and [11] is generated in two columns of encoder lines [LN 272  ]  generating the data for the second mode, respectively, which are output to the selection gate 335. 
     In parallel with this, the transistors Q 263  of the respective switching blocks of the matrix circuit 330 connected to the control lines (x 171 , x 172 , x 173 , x 174 ) at which the digital output signal has become &#34;1&#34; among the respective AND gates AU.sub.(171, 172, 173) are controlled to turn ON in units of rows and further a fine digitization of the quantization level is executed. 
     For example, when only the output of the AND gate AU 173  becomes the &#34;1&#34; level, the respective transistors Q 263  of the switching blocks S m41 , S m43 , S m45  and S m47  at the first row from the bottom in the diagram constituting the first group and the switching blocks S m32 , S m34 , S m36  and S m38  at the second row constituting the second group adjoining to them become ON, the reference voltages V 339  to V 345  divided by the reference resistances R 309  to R 316  and the sampling voltage V S  are differentially amplified at the respective switching blocks S m41 , S m43 , S m45  and S m47 , and S m32 , S m34 , S m36  and S m38 , and they are compared by the lower data comparators 341 to 348. 
     Similarly, when the output of the AND gate AU 172  is the &#34;1&#34; level, the switching blocks S m32 , S m34 , S m36  and S m38  at the second row and the switching blocks S m21 , S m23 , S m25  and S m27  at the third row adjoining to them are activated, so that the differential amplification operation is performed, and the comparison by the lower data comparators 341 to 348 is carried out. 
     For example, when the output of the AND gate AU 172  is the &#34;1&#34; level, the lower data conversion code is detected by the switching blocks S m21 , S m23 , S m32  and S m34 , and the redundant bit of the lower significant data conversion code is detected by the switching blocks S m25 , S m27 , S m36  and S m38 . 
     In this way, in the lower data conversion codes, the sampled voltage V S  and the reference voltage divided by the reference resistance elements are compared by the activated switching blocks, so that the digital signal in accordance with the result of comparison will be output from the AND gates AD 181  to AD 187  and AD 188  of the lower data comparators 341 to 348. 
     At this time, where the signal of the &#34;1&#34; level is output from one AND gate among the AND gates AD 181 , AD 183 , AD 185  and AD 187  of the lower data comparators 341, 343, 345 and 347 constituting the first group to the lower data encoder 334, at the lower data encoder 334, the selection line LN 274  becomes &#34;1&#34;. 
     As a result, the selection signal SEL 171  is input to the selection gate 335 as the &#34;1&#34; level, and the selection signal SEL 172  is input to the selection gate 335 as the &#34;0&#34;  level. 
     In the selection gate 335, along with the fact that only the selection signal SEL 171  is input as the &#34;1&#34; level, only the AND gates A 181  and A 183  are activated. 
     To these AND gates A 181  and A 183 , the bit data on the upper data side and lower data side of the upper significant data for the first mode generated in the line LN 271  of the upper data encoder 333 are respectively supplied. 
     Accordingly, in the selection gate 335, the respective bits of the upper significant data at the time of the first mode are selected, and as a result, they are output as the upper significant data conversion codes D 1  and D 2  via the OR gates OR 301  and OR 302 . 
     Concretely, when the sampling voltage V S  of the analog signal V IN  is defined as V RB  &lt;V S  &lt;V 352 , the upper data conversion codes [D 1 , D 2  ] are output as [00]; when V 352  &lt;V S  &lt;V 351  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [10]; and when V 351  &lt;V S  &lt;V RT  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [10]. 
     Also, in the lower data encoder 334, when the output of the AND gate AD 181  of the lower data comparator 341 is &#34;1&#34;, the lower data conversion codes D 3  and D 4  are generated as [00]; when the output of the AND gate AD 183  of the lower data comparator 343 is &#34;1&#34;, the lower data conversion codes D 3  and D 4  are generated as [01]; when the output of the AND gate AD 185  of the lower data comparator 345 is &#34;1&#34;, the lower data conversion codes D 3  and D 4  are generated as [10]; and when the output of the AND gate AD 187  of the lower data comparator 347 is &#34;1&#34;, the lower data conversion codes D 3  and D 4  are generated as [11], which are output. 
     Where the signal of the &#34;1&#34; level is output from one AND gate among the AND gates AD 182 , AD 184 , AD 186  and AD 188  of the lower data comparators 342, 344, 346 and 348 constituting the second group to the lower data encoder 334, at the lower data encoder 334, the selection line LN 275  becomes &#34;1&#34;. 
     As a result, the selection signal SEL 172  is input to the selection gate 335 as the &#34;1&#34; level, and the selection signal SEL 171  is input to the selection gate 335 as the &#34;0&#34; level. 
     In the selection gate 335, along with the fact that only the selection signal SEL 171  is input as the &#34;1&#34; level, only the AND gates A 182  and A 184  are activated. 
     To these AND gates A 182  and A 184 , the bit data on the upper data side and lower data side of the upper significant data for the second mode generated in the line LN 272  of the upper data encoder 333 are respectively supplied. 
     Accordingly, in the selection gate 335, the respective bits of the upper significant data at the time of the second mode are selected, and as a result, they are output as the upper significant data conversion codes D 1  and D 2  via the OR gates OR 301  and OR 302 . 
     Concretely, when the sampling voltage V S  of the analog signal V IN  is defined as V RB  &lt;V S  &lt;V 352 , the upper data conversion codes [D 1 , D 2  ] are output as [01]; when V 352  &lt;V S  &lt;V 351  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [01]; and when V 351  &lt;V S  &lt;V RT  stands, the upper significant data conversion codes [D 1 , D 2  ] are output as [11]. 
     Also, in the lower data encoder 334, when the output of the AND gate AD 182  of the lower data comparator 342 is &#34;1&#34;, the lower data conversion codes D 3  and D 4  are generated as [11]; when the output of the AND gate AD 184  of the lower data comparator 344 is &#34;1&#34;, the lower data conversion codes D 3  and D 4  are generated as [10]; when the output of the AND gate A D6  of the lower data comparator 346 is &#34;1&#34;, the lower data conversion codes D 3  and D 4  are generated as [01]; and when the output of the AND gate AD 188  of the lower data comparator 348 is &#34;1&#34;, the lower data conversion codes D 3  and D 4  are generated as [00], which are output. 
     As explained above, according to the present embodiment, the reference voltages V 336  (=V 351 ) and V 340  (=V 352 ) supplied to the switching block positioned intermediate in the row direction between the second row and third row among the switching blocks arranged in the form of a matrix comprising 4 rows and 8 columns are supplied to the upper data comparators 331 and 332, respectively, the lower significant codes are divided to two groups, signals SEL 171  and SEL 172  for selecting the first mode data and second mode data are output from the lower data encoder 334 obtaining this group of conversion code, so that the first mode data and second mode data output from the upper data encoder 333 are selected, thereby obtaining the upper data conversion codes D 1  and D 2 , and therefore it is possible to use the selection signal directly for the selection of the upper significant data without the use of the inverted gate and inhibit gate as in the conventional circuit. 
     Accordingly, the input of the selection signal to the selection gate 335 is not delayed relative to the output of the upper data encoder 333, and thus the increase of speed of conversion processing can be achieved. 
     Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, an increase of the number of the reference resistance columns can be prevented and, at the same time, the number of selection signals can be reduced to two. Also, the number of the upper significant code to be selected and the number of the input gate of the selection gate can be reduced to two, and further a reduction of the number of the switching blocks can be achieved. 
     Accordingly, there is an advantage that an A/D converter circuit with which the reduction of the surface area of the chip and the reduction of power consumption can be achieved can be realized. 
     FIG. 37 is a circuit diagram showing a 14th embodiment of the A/D converter circuit according to the present invention. 
     The point of difference of the 14th embodiment from the above-mentioned 13th embodiment resides in the constitution wherein, in the upper data encoder 363, in both of the first mode and second mode, the lower data side bit (minimum bit) D 2  of the upper data code is not generated, only the upper data side bit D 1  is generated, and the lower data side bit (minimum bit) D 2  is output as the upper significant data conversion code D 2  using the selection signal SEL 192  generated in the lower data encoder 364 as it is. 
     As seen from FIG. 36, as the upper least significant bit (the second bit from the highest bit of the 4-bit data in FIG. 36), &#34;0&#34; and &#34;1&#34; are alternately repeated for every row. This is similar to the selection signal SEL 192  corresponding to the second group. 
     Accordingly, even if the constitution is made so that the selection signal SEL 192  generated in the lower data encoder 364 is used as it is and output as the upper data conversion code D 2 , it has the same function as that in the case of the above-mentioned 13th embodiment. Not only can similar effects be obtained, but also the reduction of the number of the upper data codes to be selected and the reduction of the OR-gates in the selection gate 366 can be achieved. Thus, there is an advantage that the reduction of the chip area and the reduction of the power consumption can be achieved. 
     FIG. 38 is a circuit diagram showing a 15th embodiment of the A/D converter circuit according to the present invention. 
     The point of difference of the 15th embodiment from the above-mentioned 15th embodiment resides in the constitution whereby the number of the selection lines of the lower data encoder 394 is reduced to only one line, i.e., LN 323 , to generate only one selection signal SEL 201  as the selection signal, and a signal obtained by inverting the level of the selection signal SEL 201  at the inverter 397 is supplied as the signal in place of the selection signal SEL 191  to one input of the AND gate A 201  of the selection gate 395. 
     Namely, in the present 15th embodiment, the upper least significant data is produced at the lower data encoder 394, and that data is added to the selection terminal of a demultiplexer comprising the inverter 397 and the selection gate 395, whereby the selection of the upper significant data is carried out. In appearance, the selection signal is omitted. 
     According to the present 15th embodiment, similar effects to those obtained in the above-described 14th embodiment can be obtained. 
     Note that, in the above-mentioned 13th, 14th and 15th embodiments, an explanation was made taking as an example an A/D converter circuit for four bits, but needless to say the present invention can be applied to an A/D converter circuit for more bits as well. 
     Also, in the above-mentioned 13th, 14th and 15th embodiments, the structure in which the other output pin buffers are arranged on the input side of the upper data encoder and the lower data encoder was indicated, but these other output pin buffers are provided so as to reliably drive the upper data encoder and the lower data encoder, and it is necessary to provide the same according to a certain capacitance of the upper data encoder and the lower data encoder acting as a load. 
     As explained above, according to the present invention, the inverted gate and inhibit gate which have been conventionally necessary become unnecessary, and the increase of speed of conversion processing can be achieved. 
     Also, in addition to the fact that the inverted gate and inhibit gate become unnecessary, the increase of number of the resistance element columns can be prevented. At the same time, the number of the selection signals can be reduced, the number of the upper data codes to be selected and the number of the input gates of selection gates can be reduced, and further the number of the switching blocks can be reduced to the minimum level, and thus there is an advantage that the reduction of the chip area and the reduction of the power consumption can be achieved.