Memory control circuit for reducing the number of row address signals
This application is a continuation of application Ser. No. 07/690,828, filed Apr. 26, 1991, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to a method for accessing a dynamic random-access memory. 
     A conventional method for accessing dynamic random-access memories (hereinafter sometimes abbreviated as &#34;DRAM&#34;) is shown in FIG. 7. In response to the falling of a row address strobe (RAS) signal, an upper address is sent to the DRAM for accessing it. On the other hand, in response to the falling of a column address strobe (CAS) signal, a lower address is sent to the DRAM for addressing it. 
     During the read/write mode of DRAM, the above-described timing is repeated to access the DRAM so that desired data can be written into or read from the DRAM. 
     In order to access the DRAM from a central processing unit (CPU) by the conventional access method described above, respective signals must be sent out for each access in accordance with the timing specified above. With a high-speed 32-bit CPU, a wait time of several cycles is necessary and this inevitably increases the access time. 
     The clock rate of recent models of CPU is very high and in order to cope with this situation, a cache memory is often composed using an expensive static RAM. However, a large-capacity memory composed of a static RAM is expensive and, at the same time, the cache memory requires a complicated control circuit. 
     SUMMARY OF THE INVENTION 
     The present invention has been accomplished under these circumstances and has as an object providing a memory access method that is capable of configuring a large-capacity, high-speed memory at low cost and in a simple way. 
     In order to achieve this object, a method of accessing a dynamic random access memory according to the invention, comprises the steps of: latching an upper address of the most recent address signal supplied from a requesting element; sending out the upper address of the most recent address signal and an active row address strobe signal to the dynamic random access memory; sending out a lower address of the most recent address signal and an active column address strobe signal to the dynamic random access memory; comparing the latched upper address with an upper address of a subsequent address signal supplied from the requesting element at the time of the next access request; outputting a coincidence signal when the latched upper address and the upper address of the subsequent address signal correspond; and sending to the dynamic random access memory a lower address of the subsequent address signal and an active column address strobe signal in response to the coincidence signal. 
     In the memory access method of the present invention, the upper address of a subsequent address signal is compared with the latched upper address and, if the two addresses coincide, the lower address of the subsequent address signal and an active column address strobe signal are sent out to access the dynamic RAM which has earlier been supplied with an active row address strobe signal. 
     In other words, a row address strobe signal need not be sent out if the two upper addresses coincide; thus, contributing to a shorter access time by the CPU. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing an example of the memory access device in which the memory access method of the present invention is implemented; 
     FIG. 2 is a timing chart showing the operation of a dynamic RAM in a page mode; 
     FIG. 3 is a state transition diagram for illustrating the operation of memory accessing in accordance with the present invention; 
     FIGS. 4 and 5 are timing charts showing the procedure of a memory access process; 
     FIG. 6 is a diagram showing the configuration of circuitry incorporating an application of the memory access device shown in FIG. 1; and 
     FIG. 7 is a timing chart showing the typical operation of accessing a dynamic RAM. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of the memory access method of the present invention will be described below with reference to accompanying FIGS. 1-6. 
     FIG. 1 is a block diagram showing an example of the memory access device in which the memory access method of the present invention is implemented. In response to a request for access from a central processing unit (hereinafter sometimes referred to as &#34;CPU&#34;) 2, a memory access device 1 accesses a dynamic random-access memory (DRAM) 3 for reading or writing data. 
     The memory access device 1 has the following components: a latch circuit 11 for latching an upper address sent from the CPU 2; a comparator 12 for comparing the upper address produced from the latch circuit 11 (i.e., the upper address sent at the most recent time of accessing) with the upper address produced from the CPU 2 (i.e., the upper address sent at the subsequent time of accessing; a multiplexer 13 for appropriately selecting the upper or lower address from the CPU 2 in response to an input selection signal and for sending the selected address to the DRAM 3; and a control circuit 14 for controlling the respective components described above. 
     DRAM 3 has a high-speed page mode. Given a fixed upper address, DRAM 3 in the high-speed page mode can be accessed by sending out a row address strobe (RAS) signal and an upper address, and, subsequently, sending out column address strobe (CAS) signals and lower addresses as shown in FIG. 2. 
     FIG. 3 is a state transition diagram showing the operation of memory accessing according to the method of the present invention. In FIG. 3, each of states 1-6 and the condition for making a transition from a certain state to another are denoted by a transition condition/operation (=output signal). 
     In the &#34;transition condition&#34;, AS denotes an address strobe signal supplied from CPU 2, and EQ denotes an equal signal supplied from the comparator 12. The equal signal indicates the coincidence between two compared addresses. Symbols AS and EQ without a bar denote a high level whereas AS and EQ with a bar-above denote a low level. 
     As for the &#34;operation&#34; indicated by an output signal =[LE, SEL, RAS, CAS, ACK), LE denotes a latch enable signal to be supplied into the latch circuit 11, SEL a select signal to be supplied into the multiplexer 13, RAS a row address strobe signal to be supplied into DRAM 3, CAS a column address strobe signal to be supplied into DRAM 3, and ACK a response signal to be supplied into CPU 2. The high level of each output signal is denoted by &#34;1&#34; and its low level by &#34;0&#34;. 
     In FIG. 3 Rst Timer denotes a reset timer and A, B, C and D are constants that are determined by the DRAM. 
     The procedure of accessing DRAM 3 with the memory access device will be described below with reference to FIGS. 4 and 5, in which &#34;negate&#34; is assumed to be &#34;inactive (high level)&#34; whereas &#34;assert&#34; is assumed to be &#34;active (low level)&#34;. 
     The accessing process starts with reset state where a row address strobe (RAS) signal and a column address strobe (CAS) signal are set in a &#34;negate&#34; condition whereas a select (SEL) signal is set in such a way to select an upper address. When a SEL signal is in an &#34;assert&#34; condition, an upper address is selected and if SEL signal is in a &#34;negate&#34; condition,a lower address is selected. Either of these addresses is outputted from the multiplexer 13. 
     In this reset state, the control circuit 14 is supplied with a &#34;negate&#34; address strobe (AS) signal and data strobe (DS) signal from CPU 2 and with a &#34;negate&#34; equal (EQ) signal from the comparator 12. The control circuit 14 supplies the latch circuit 11 with a &#34;negate&#34; latch enable (LE) signal, supplies the multiplexer 13 with a &#34;negate&#34; SEL signal, and supplies DRAM 3 with &#34;negate&#34; RAS and CAS signals. 
     Suppose here that CPU 2 starts the first accessing of DRAM 3 by sending out an upper address (A1) (FIG. 4a), a Lower address (al) (FIG. 4b), an AS signal (FIG. 4e) and a DS signal (FIG. 4f). Then, as shown in FIG. 4i, the control circuit 14 brings the LE signal from a &#34;negate&#34; to &#34;assert&#34; state on the basis of the AS signal asserted at time t 1 . At time t 2 , the latch circuit 11 latches the upper address (A1) on the basis of the asserted AS signal and delivers the same to the comparator 12 in accordance with the timing shown in FIG. 4c. 
     The comparator 12 then compares the upper address (FIG. 4c) from the latch circuit 11 with the upper address from CPU 2 (FIG. 4a). If the two addresses do not coincide, the comparator 12 produces the &#34;negate&#34; EQ signal unaltered. Otherwise, the EQ signal is changed from a &#34;negate&#34; to &#34;assert&#34; state and the comparator 12 produces the resulting EQ signal as shown in FIG. 4h. 
     After the passage of DRAM-prescribed time period from time t 2  when the LE was asserted, the control circuit 14 asserts the RAS signal (FIG. 4k) and negates the SEL signal (FIG. 4j). Then, on the basis of the SEL negated at time t 3 , the presently selected and delivered upper address is replaced by a lower address as shown in FIG. 4d and the multiplexer 13 outputs the selected lower address to DRAM 3. When the lower address is sent out to DRAM 3, the control circuit 14 brings the CAS signal from a &#34;negate&#34; to &#34;assert&#34; state (FIG. 4l) and brings the ACK (response) signal from a &#34;negate&#34; to &#34;assert&#34; state (FIG. 4g). 
     When the DS signal that has been changed from an &#34;assert&#34; to &#34;negate&#34; state (FIG. 4f) is supplied from CPU 2 to the control circuit 14, the latter negates both the CAS signal (FIG. 4l) and the ACK signal (FIG. 4g) on the basis of the negated DS signal. However, the RAS signal is maintained in an &#34;assert&#34; state. 
     As a result of the operation described above, data is read from DRAM 3 in accordance with the timing shown in FIG. 4m and data is written into DRAM 3 in accordance with the timing shown in FIG. 4n. 
     When CPU 2 ends the first accessing of DRAM 3, the next accessing is performed at an address that is composed of an upper address different from the upper address of the first accessed address. The operation of the memory access device for this second accessing will be described below with reference to the timing chart of FIG. 5. 
     The second accessing starts with CPU 2 outputting an upper address (A2) at time t 1  (FIG. 5a). Then, the comparator 12 compares the upper address (A1) from the latch circuit 11 with the upper address (A2) from CPU 2. Since the two upper addresses do not coincide in this case, the EQ signal is brought from an &#34;assert&#34; to &#34;negate&#34; state as shown in FIG. 5h and the comparator 12 outputs the negated EQ signal to the control circuit 14, which negates the RAS signal (FIG. 5k) based on the negated EQ signal. 
     When CPU 2 delivers an AS signal (FIG. 5e) and a DS signal (FIG. 5f), the control circuit 14 asserts the SEL and LE signals based on the AS signal asserted at time t 2 . Then, on the basis of the SEL signal asserted at time t 3  as shown in FIG. 5j, the presently selected and delivered lower address is replaced by an upper address (A2) and the multiplexer 13 outputs the selected upper address to DRAM 3. 
     As shown in FIG. 5c, the upper address (A2) latched on the basis of the LE signal asserted at time t 3  (FIG. 5i) is delivered from the latch circuit 11 to the comparator 12, which compares the address (A2) from the latch circuit 11 with the address (A2) from CPU 2. If the two addresses coincide, the comparator 12 brings the EQ signal from a &#34;negate&#34; to &#34;assert&#34; state. When the latch circuit 11 latches the upper address, the control circuit 14 assets the RAS signal (FIG. 5k) and after the passage of a DRAM-prescribed time period from time t 2  when the LE signal was asserted, the control circuit 14 negates the SEL signal (FIG. 5j) and asserts the CAS signal (FIG. 5l). 
     On the basis of the SEL signal negated at time t 4 , the presently selected upper address is replaced by a lower address (a2) in the multiplexer 13 as shown in FIG. 5d. The lower address (a2) is sent out to DRAM 3 from the multiplexer 13. Then, in order to notify the event of data reading/writing, the control circuit 14 supplies CPU 2 with the ACK signal after it is brought from a &#34;negate&#34; to &#34;assert&#34; state as shown in FIG. 5g. At the same time, on the basis of the &#34;negate&#34; DS signal supplied from CPU 2 in response to the asserted ACK signal, the control circuit 14 brings both the CAS and ACK signals from an &#34;assert&#34; to &#34;negate&#34; state. However, the RAS signal is maintained in an &#34;negate&#34; state. 
     As described above, if the upper address sent in the previous accessing by CPU does not coincide with the present upper address, the state transition shown in FIG. 3 occurs in sequentially order irom state 1 to state 6. 
     When a third accessing is performed at an address composed of the same upper address as the address accessed for the second time, the upper address (A2) latched in the latch circuit 11 is equal to the upper address (A2) delivered from CPU 2. Therefore, the comparator 12 outputs the asserted EQ signal. 
     In this state, the control circuit 14 which is to be supplied with a DS signal that has been changed from a &#34;negate&#34; to &#34;assert&#34; state for accessing from CPU 2 asserts the CAS signal (FIG. 5l) to be sent out to DRAM 3, as well as the ACK signal (FIG. 5g) to be sent out to CPU 2 on the basis of the DS signal asserted at time t 5  (FIG. 5f). At the same time, the control circuit 14 negates both the CAS and ACK signals on the basis of a negated DS signal supplied from CPU 2 in response to the asserted ACK signal. However, the RAS signal is maintained in an asserted state. 
     As a result of the operation described above, data is read from DRAM 3 in accordance with the timing shown in FIG. 5m and data is written into DRAM 3 in accordance with the timing shown in FIG. 5n. 
     As described above, if the upper address sent in the previous accessing by CPU coincides with the present upper address, the state transition shown in FIG. 3 occurs sequentially in the order of from state 1 to state 6 except for states 2 and 3. 
     In short, when the upper address sent in the previous accessing by CPU coincides with the present upper address (i.e., in the case where the EQ signal is in an &#34;assert&#34; state when DRAM is to be accessed by CPU), data is read or written in accordance with the timing that follows time t 5  shown in FIG. 5. On the other hand, if the two upper addresses do not coincide, data is read or written in accordance with the timing that follows time t 2  shown in FIG. 5. 
     In general, for the addresses sent from a CPUf when the CPU sends out a certain address, the CPU subsequently tends to access at a nearby address. For instance, the instruction-fetching event often involves the continuous sending of addresses increasing in 1-word increments and this is also true with data accessing using a stack pointer, which often involves the continuous sending of addresses increasing in 1-word increments or decreasing in 1-word decrements. In these cases, the upper address indicated by RAS signal are often the same. Therefore, as described in the embodiment discussed on the foregoing pages, if the upper address sent out upon a first accessing for processing program or data is stored while the RAS signal is maintained at a low (active) level, a second accessing can be accomplished by sending out the CAS signal and a lower address to DRAM on the condition that the upper address sent during the second accessing coincides with the stored upper address. This contributes to a significant reduction in the access time from CPU. 
     Further, instruction fetching usually alternates with data accessing. Consider, for example, the case where data is continuously read from a stack. In this case, the instruction fetching event occurs alternately with the reading of data from the stack and the RAS cycle will come in on each occasion if the upper address differs between the instruction area and the data area. 
     In order to prevent this problem, the embodiment under consideration may be applied to a system of the type shown in FIG. 6, in which two units of the memory access device described above are provided, one for the program area and the other for the data area, and adapted to operate independently of each other. 
     The system shown in FIG. 6 includes a memory access device 61 for the program area, a DAM 62 for program storage, a memory access device 63 for the data area, and a DRAM 64 for data storage. Each of the memory access devices 61 and 62 has the same configuration as the memory access device 1 shown in FIG. 1. 
     For accessing the program area, CPU 2 supplies the control circuit 14 in the memory access device 61 with a signal S1 that brings the control circuit to an active state. For accessing the data area, CPU 2 supplies the control circuit (not shown) in the memory access device 63 with a signal S2 that brings the control circuit to an active state. CPU 2, on the other hand, is supplied with an ACK (response) signal from either the memory access device 61 or 63 via an OR circuit 65. When one of the two memory access devices is active, the other memory access device retains its own state. 
     As described on the foregoing pages, the method of the present invention permits a DRAM to be accessed, as requested, by sending out a lower address and an active CAS signal to the DRAM if the upper address from the request element (CPU) coincides with the latched upper address. This enables the CPU to access the DRAM with a significantly shortened access time. 
     An obvious advantage of this feature is that an inexpensive and simplified large-capacity, high-speed memory can be provided using a dynamic RAM rather than a static RAM which has heretofore been necessary in the prior art.