Apparatus and process for testing AC performance of LSI components
BACKGROUND OF THE INVENTION 
     a. Field of Invention 
     This invention relates to apparatus and processes for automatically testing of electric circuits. More particularly, the invention relates to apparatus and processes for testing LSI components. 
     B. Description of the Prior Art 
     Data processing machines employ semiconductors to perform logical and memory operation at switching speeds of the order of 10 to 100 nanoseconds. Semiconductor components are fabricated in large scale integration (LSI) technologies. Several thousand circuits may be incorporated into a chip less than a quarter inch by a quarter inch in area. The circuits are combined to achieve the various machine functions. Each component must be tested for steady state or DC operation and dynamic or AC operation to verify that machine functions will be achieved. Testing of LSI components is becoming increasingly difficult because (1) switching states of the various active devices in the component change so fast (nanoseconds) that little or no stable or DC level is achieved to indicate whether a circuit is in a binary `1` or binary `0` condition and (2) the switching states of the active elements in the circuit change differently for identical circuits because of differences in distributed R, L, and C experienced by the circuit. A publication &#34;Digest of Papers 1974 Semiconductor Test Symposium&#34;, of Nov. 5-7, 1974, sponsored by the IEEE Computer Society describes additional problems in dynamic time or AC testing of LSI components. 
     One method of testing is arranged so that the correct operation of the test system is not dependent on rise time, fall time or minimum delay of any individual circuit in a logic unit. The only dependency is that the total delay through a number of stages of logic is less than some known value. Such a test configuration is referred to as level sensitive scan logic as described in U.S. Pat. Nos. 3,761,695 or 3,783,254 or 3,784,907 all assigned to the present assignee. Briefly, the components under test include DC latch circuitry associated with the combinatorial and sequential logic networks. The latch circuitry is positioned along with the combinatorial logic networks and arranged in sets. The sets of latch circuitry are coupled through combinatorial logic to other sets of latches controlled by clock trains. All of the latches are coupled together to form a single shift register having a single input a single output in shift controls. Logic networks associated with different clocks can be isolated from a logic network under test. Test patterns are provided one at a time to the logic units under test. Each set of test patterns is shifted into the register and provided as input signals to the logic unit network. The contents of the shift register latches are measured at the unit outputs against the expected response of the particular test pattern thereby obtaining initial indication of the state of the storage circuits. Repeating this procedure with additional test patterns provides a clear indication of the test status of the individual logic networks and the component as a whole. 
     In another prior art test method, a circuit under test is connected in a close loop with input drive circuitry, delay and decoding circuitry. A test pattern is entered into the circuits as well as to the output of the apparatus. Isolations occur as a result of the closed loop connection. The isolations are measured by sequentially changing the binary signals applied to the apparatus and are an indication of the test status of the apparatus. 
     The prior art test methods either include circuit elements in a chip which take away from the potential logic performance or require complex test systems to determine the AC operation of the circuits. Both test systems are expensive and are limited in the degree to which they can test components. 
     SUMMARY OF THE INVENTION 
     One object of the invention is test apparatus and processes for measuring AC switching performance of circuits that switch at high speeds, typically of the order of 10 to 20 nanoseconds. 
     Another object is test apparatus and processes for measuring AC switching performance of all types of circuits employed in data processing machines. 
     Another object is a simple and inexpensive test apparatus and process that measures AC performance of LSI components by logic control of a counter-voltage integrator. 
     In one illustrative embodiment a circuit element under test is adapted to receive input signals for test patterns at one set of terminal points and provide output signal patterns at another set of terminal points depending upon the switching performance of the active elements included in the element under test. A line counter element is directly attached to each output line. Each counter element includes logic elements responsive to control signals that are correlated with test patterns to the circuit under test. The counter element provides a numerical output indicative of the switching behavior of the line under test during a defined time inverval in which the logic element is operable. A display means presents the numerical output from each logic element as an indication of the AC switching performance of the circuit under test. 
     The testing process for measuring the AC performance of LSI circuits comprises the steps of (a) providing a test pattern to an LSI device under test having a plurality of output terminals, each terminal connected to a line counter logic element, (b) providing set-up signal to activate each counter logic element, (c) providing a begin count and counter pulses to each line counter logic element, a counter element in the line counter logic element increasing in count until an output line switches, (d) providing stop signals to the line counter logic element, and (e) displaying the counter values, the numerical values displayed indicating the AC switching performance of the output terminals for the device under test. 
     A feature of the invention is a line counter logic element that translates the AC switching behavior of a circuit operating at speeds of nanoseconds into a numerical value indicative of the switching performance of the circuit. 
     Another feature of the invention is a plurality of line counter logic elements that respond to suitable control signals to generate numerical values indicative of the relative switching performance of output lines from a LSI device responsive to a test pattern. 
     Another feature of the invention is a process for applying (1) a test pattern to a device under test, (2) begin, count, (3) counting, and (4) reset pulses to a plurality of line counter logic elements responsive to the respective output lines of the LSI device whereby the AC switching performance of the device can be determined. 
    
    
     DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic of an LSI device under test. 
     FIG. 2 is a schematic of a test system of the present invention including a plurality of line counter logic elements. 
     FIG. 3 is a logic representation of a line counter logic element included in the test system of FIG. 2. 
     FIG. 4 is a logic embodiment of another line counter logic element included in the test system of FIG. 2. 
     FIGS. 5A-5K are timing diagrams of input pulses supplied to the test system of FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows an LSI device 10 to be tested. The LSI device 10 may be a logic chip, described for example in U.S. Pat. No. 3,697,318; a memory chip, described for example in U.S. Pat. No. 3,508,209 or a macro device which employs both logic and memory. Test patterns are applied to the plurality of input lines 11 and are intended to functionally test the device 10 in operation, typically at switching performance expected in a data processing machine. Test pattern generation for LSI devices are described in a paper entitled &#34;Algorithms for Detection of False and Logic Circuits&#34; by W. G. Bouricius, et al which was published in Research Report RC 3117, by the IBM Thomas J. Watson Research Center on Oct. 19, 1970. An algorithm for computation of test for failures is described in &#34;Diagnosis of Automata Failures: A Calculus And Method&#34; by J. Paul Roth in the IBM Journal Research and Development, July 1966. These papers describe how to develop program algorithms for test generations and test evaluations. These include the generation of the assumed fault data necessary for the automatic test generation system. It should be understood that the invention of the application does not reside in generation of test patterns for application to a device under test but rather is directed to apparatus and a method of testing the device when the patterns are applied to it. 
     There exists a large number of possibilities of switching processes occurring at different order at the output lines 12. For n output lines the possibilities are given by the relationship: ##EQU1## P = Number of possible cases of switching processes occurring at n output lines 
     q = Counter variable for the recursive formula (1) 
     n = Number of output lines on which switching is to be observed 
     n! = 1.2.3.4 . . . n 
     P includes the switching cases where two or more lines switch simultaneously. The number of instances where two lines switch simultaneously increases rapidly as the number of lines is as given by the following: 
     
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          n         P                                                     
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          2          3                                                    
          3         13                                                    
          4         69                                                    
          5         431                                                   
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     The relative switching times of the output lines is significant to achieve desired data processing functions, particularly as the machine speeds increase. An erroneous switching order from a circuit component may result in the failure of the machine to achieve the desired function. 
     FIG. 2 shows a test system which measures the relative switching order from an LSI chip of the type shown in FIG. 1 operating at switching speeds of the order of 10 to 20 nanoseconds. The chip has one to n output lines 12. Each line is connected to a line counter logic element 14. Each element 14 provides an input to a display unit 16. The elements 14 will be more fully described in conjunction with FIGS. 3, 4, and 5. The display unit is a conventional digital display or volt meter for each line. Alternatively, the outputs may be combined in a single display, as for example a high speed delayed sweep oscilloscope described for example in an article in the &#34;Digest of Papers 1974 Semiconductor Test Symposium&#34;, pages 7-32, supra. Each element is responsive to a set-up; begin count, reset, stop signals and counter pulses, as will be described in more detail hereinafter. 
     In FIG. 3 the line 12 is connected to an AND circuit 20 and an equivalent or not Exclusive OR circuit 24. The AND and equivalent circuits are well known, being described in the text &#34;Pulse and Digital Circuits&#34; by J. Millman and H. Taub, McGraw Hill Book Co., Inc., 1956, Chapter 13. The AND circuit 20 also responds to a set-up signal and provides a set input to a standard latch 22. A reset signal is also provided to the latch 22 which provides the other input to the circuit 24. The latch circuit is the standard flip-flop also described in the text by J. Millman and H. Taub, supra. An AND circuit 26 is responsive to the circuit 24, the latch 28, and the counter pulses. The latch 28 is responsive to the begin count and the reset or stop signal. A counter 30 is responsive to the AND circuit 26 and also to the reset or stop signal. The counter is adapted to count at a rate on the order of a count per nanosecond and is described, for example in the text &#34;Basic Electronic Instrument Handbook&#34;  by C. F. Coombs, McGraw Hill, New York, N.Y., published 1972, specifically page 33.7. 
     In FIG. 5A, the counter pulses are provided as an input to the AND gate 26. The counter 30, however, is not activated until the AND gate 26 responds to signal changes from the circuit 24 and the latch 28. The circuit 24 responds to the output signal on the line 12 from the circuit under test and the latch 22. A set-up pulse to the AND circuit 20, as shown in FIG. 5B together with the signal on the line 12, as shown in 5D, activates the latch 22 to provide an input to the circuit 24, as shown in FIG. 5F. The circuit 24 provides an input to the AND gate 26, as shown in FIG. 5H. Shortly thereafter, a begin count signal, as shown in FIG. 5C, is provided to the latch 28 which provides an up level to the AND gate 26, as shown in FIG. 5I. The up level activates the AND gate 26 which initiates the counting of the counter 30, as shown in FIG. 5J. When the output signal on the line 12 drops, as shown in FIG. 5D, the circuit 24 is deactivated, as shown in FIG. 5H and the counting pulses to the counter 30 are blocked, as shown in FIG. 5J. The number recorded in the counter appears in the display for the particular output line. Correspondingly, numbers appear in their respective displays to indicate the switching time for the particular output line. The relative switching times for the output lines can be determined by observing the respective numerical values in the display. Alternatively, a high speed delay sweep oscilloscope can provide a real time comparisons on all output terminals being compared. 
     A reset signal, shown in FIG. 5G, is provided at the end of the comparsion, or after the displays are read to measure the relative switching times of the output lines to a succeeding test pattern. The reset signal changes the latch 22 from an up state to a down state as shown in FIG. 5F. The reset pulse also returns the counter 30 to the beginning state. The reset pulse can also serve as the stop pulse to the latch 28 to change the output thereof from an up state to a down state as shown in FIG. 5J. The line counter logic element is now ready for the next test pattern. 
     A binary `0` on the line 12 prevents an output from the AND circuit 20 even when a set-up signal is provided thereto, as shown in FIGS. 5B and 5E. The latch 22 remains in a down state, as shown in FIG. 5F but the circuit 24 as an Exclusive OR provides an up state to the AND gate 26 because of both down inputs thereto, as shown in FIGS. 5D and 5F. The begin count pulse, as shown in FIG. 5C results in the latch 28 providing an up level to the AND gate 26, as shown in FIG. 5J. The counting pulses are provided by the AND gate 26 to the counter 30 as shown in FIG. 5J until the output line 12 switches from the binary `0` to binary `1` state, as shown in FIG. 5D. A reset pulse (not shown) is provided to the latch 28. After the displays are read the line counter logic elment is ready for the next test pattern and the set-up, begin count signals are provided to read the switching time of the output line. 
     FIG. 4 shows the same line counter logic element as FIG. 2 except an integrating circuit comprising resistor 40 and capacitor 42 are substituted for the counter 30 of FIG. 3. Each counter pulses increases the charge in the capacitor 42 which builds to a voltage that can be observed on a digital volt meter (not shown). A single shot 44 and AND gate 46 are adapted to discharge the capacitor 42. The single shot 44 responds to the reset signal when the latches 22 and 28 are reset. 
     While the invention has been particularly shown to describe with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the spirit and the scope of the invention.