Fast table lookup apparatus for reading memory
BACKGROUND 
     For many years, persons and firms in the data processing field have sought apparatus to reduce the time necessary to enter memory, withdraw data, and provide that data to a processor. The present application discloses an invention providing such apparatus. 
     SUMMARY 
     Fast table lookup apparatus for reading memory is disclosed which, in the preferred embodiment, operates in conjunction with a logic bus, a memory device, and a microprocessor of the type which provides an output logic signal to the bus comprising the contents of an internal register and which includes apparatus for immediately reading logic signals on the bus into the internal register of the microprocessor. Logic is provided, external to the microprocessor, for recognizing when the microprocessor provides the logic signal output comprising the contents of the internal register and for using the register contents available to address a location within the memory device and for further substituting the contents of the memory location within the memory device, which location conforms to the microprocessor internal register contents, for the microprocessor internal register contents on the bus. All of the above is accomplished in time for the memory location contents to be read into the microprocessor as a part of the next input to the microprocessor. 
     It is thus an object of the present invention to provide novel and efficient lookup apparatus for reading memory. 
     It is a further object of the present invention to provide such apparatus for utilization in a fast table lookup apparatus for reading memory. 
     These and further objects and advantages of the present invention will become clearer in light of the following detailed description of a preferred embodiment of this invention, as described in connection with the drawings for data compaction apparatus as claimed in application Ser. No. 573,571, now U.S. Pat. No. 4,021,732. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIGS. 9, 10, and 12 show block diagrams explaining a preferred embodiment according to and including the present invention. 
     The remaining FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 11, 13, and 14 to 26 of the drawings of the preferred embodiment according to and including the present invention and the remaining disclosure of the preferred embodiment according to and including the present invention are incorporated herein by reference to application Ser. No. 573,571 filed Apr. 30, 1975 by John S. Hoerning and entitled DATA COMPACTION SYSTEM AND APPARATUS, now U.S. Pat. No. 4,021,782.