Driving circuit for a liquid crystal display device
BACKGROUND OF THE INVENTION 
     This invention relates to a liquid crystal display element-driving circuit and more particularly to the digital circuit used in a digital display electronic timepiece. 
     In recent years, an electronic timepiece using liquid crystal as a display element has been developed and marketed. The electronic timepiece contains a large scale integration (abbreviated as &#34;LSI&#34;) circuitry. The LSI circuitry includes various time data-handling circuits such as an oscillating circuit, frequency-dividing circuit, counter circuit, decoder circuit and output circuit. The output circuit supplies liquid crystal-driving pulses to the required segment electrodes of a liquid crystal display element. The output circuit has a plurality of output terminals provided in a number corresponding to that of the segment electrodes, thereby causing the liquid crystal display element to indicate a prescribed time data. 
     Measurement of output voltage and current from the respective segment electrodes of a liquid crystal display element was carried out by a very much complicated process with respect to a prior art output circuit, because some of the segment electrodes were operated at a high logical level &#34;H&#34; and the others at a low logical level &#34;L&#34;. Consequently, said measurement failed to be finished quickly. 
     For example, in the measurement of high or low level output current from arbitrary terminal of a segment electrode, the potential of the terminal must be fixed to logical high or low level by proper means, because each terminal was impressed with A.C. voltage and time-consuming work were required to measure the high or low logical level current of all the terminals of the LSI circuitry for a liquid crystal display element which were provided in as large a number as about 40 to 50. 
     Further, the LSI circuitry of a liquid crystal display timepiece is generally operated by a cell, and is accompanied with the drawbacks that even when a crystal oscillator ceases to carry out oscillation due to a decrease in the power of the cell, a certain level of D.C. voltage continues to be impressed across the segment electrodes of a liquid crystal display element and a common segment electrode facing them; and said D.C. voltage is undesirably applied to liquid crystal sealed between both forms of electrode, thereby deteriorating the liquid crystal and shortening its effective life. 
     SUMMARY OF THE INVENTION 
     It is accordingly the object of this invention to provide a liquid crystal display elment driving circuit in which measurement of the output high or low level current and voltage are easily executed by setting all the output terminal for driving the liquid crystal to the same high or low logical level voltage at the same time, and further, the protection of the liquid crystal is easily realized by preventing it from being impressed with D.C. voltage between the segment electrode when crystal oscillation is stopped as a result of the reduction of the output voltage of the cell. 
     According to an aspect of this invention, there is provided a liquid crystal display element-driving circuit, wherein output signals from a decoder circuit are conducted to a plurality of exclusive OR gates through the corresponding NAND gates; and output signal from a liquid crystal driving pulse generating circuit is supplied in common to the respective exclusive OR gates; and output signals from the exclusive OR gates are delivered to the corresponding segment electrodes of a liquid crystal display element, and which comprises a first logical level voltage-generating circuit connected in common to the input terminals of a plurality of multiinput type NAND gates; a second logical level voltage-generating circuit connected in common to the inputs of the exclusive OR gates; and switch circuits disposed between the driving pulse-generating circuit and second logical level voltage-generating circuit on one hand and the exclusive OR gates on the other and controlled by the first logical level voltage generating-circuit, thereby enabling all segment electrodes to be selectively supplied with liquid crystal-driving pulses or with high &#34;H&#34; or low &#34;L&#34; logical level voltage according to combinations of output signals from the first and second logical level voltage-generating circuits. 
     According to another aspect of this invention, there is provided a liquid crystal display element-driving circuit, which further comprises a crystal oscillation stop-detecting circuit for detecting the stoppage of crystal oscillation when voltage impressed on a crystal oscillator drops for some reason, for example, a decrease in the power of a cell, whereby, at the stop of crystal oscillation, all the segment electrodes of the liquid crystal display element are impressed with voltage having an equal prescribed logic level, thereby preventing direct current voltage from being applied to the liquid crystal to save it from deterioration and shortened life; in a digital timepiece, indication of time at every time is not always necessary, and when said indication is not required, all the segment electrodes of the liquid crystal display element are set to the same logical level voltage causing the prolongation of the life of the liquid crystal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 shows the arrangement of a liquid crystal display element driving circuit according to a first embodiment of this invention which is used with a digital electronic timepiece; 
     FIG. 2 indicates the connections of the segment electrodes of a liquid crystal display element to the LSI circuitry; 
     FIG. 3 presents a modification of the switch circuits 19, 21 of FIG. 1; 
     FIG. 4 sets forth the arrangement of a liquid crystal display element driving circuit according to a second embodiment of the invention; and 
     FIG. 5 indicates the circuit arrangement of a liquid crystal oscillation stop-detecting circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 schematically shows the arrangement of a liquid crystal display element-driving circuit included in the LSI circuitry used with a digital electronic timepiece. The LSI circuitry includes a crystal oscillating circuit, frequency-dividing circuit, counter circuit, decoder circuit and output circuit. Referential numeral 11 denotes a decoder circuit, the output terminals D 1  to D n  of which are connected to the corresponding input terminals of a plurality of 3-input type NAND gates 12 1  to 12 n . The output terminal of a flashing signal-generating circuit 13 and the output terminal of the first logical level voltage-generating circuit 14 are connected in common to the remaining two input terminals of each of said 3-input type NAND gates 12 1  to 12 n . The flashing signal generating circuit 13 is used to flash the desired numerals, for example, indicating seconds to discriminate those from other non-flashing numerals, for example, indicating minutes, when the desired numerals are required to change to others, particularly in the case when correct setting of time is required. The flashing signal-generating circuit 13 produces flashing signals repeated at a frequency of about 2 Hz so as to intermittently indicate said particular display digit position. The flashing signal-generating circuit 13 is formed of a simple gate. When a button switch (not shown) mounted on the outside of the body of a digital electronic timepiece is pulled, the gate is opened to supply 2 Hz pulses from the frequency dividing circuit included in the LSI circuitry to that of the NAND gates 12 1  to 12 n  which corresponds to the aforesaid particular display digit position. The first logical level voltage-generating circuit 14 is generally formed of a connection electrode or inverter. When the output high or low level current and voltage of the LSI circuit is required to measure, the first logical voltage generating circuit 14 is connected to an external power source which supplies high &#34;H&#34; or low &#34;L&#34; level voltage as required. When connected to an external power source for measurement which is capable of selectively impressing high &#34;H&#34; or low &#34;L&#34; level vo tage, the first logical level voltage-generating circuit 14 may be formed of a connection electrode. An output signal A from the first logical level voltage-generating circuit 14 is changed into an A signal while passing through an inverter 25. 
     The output terminals of the NAND gates 12 1  to 12 n  are connected to one input terminal of each of the exclusive OR gates 15 1  to 15 n . The output terminals of the exclusive OR gates 15 1  to 15 n  are connected through the corresponding inverters 16 1  to 16 n  to the segment terminals 17 1  to 17 n  which in turn are connected to the segment electrodes of a liquid crystal display element. 
     As is well known, the segment electrodes are arranged in the form of a numeral 8, as shown in FIG. 2, for each display digit position. A numeral being displayed is determined according to the manner in which the segment electrodes are selectively operated by the LSI circuitry. As seen from FIG. 2, the segment terminals 17 1  to 17 n  connected to the segment electrodes a to g and a common segment terminal 24 connected to a common segment electrode C E  are arranged outside the LSI circuitry. An output from a time-counting circuit included in the LSI circuitry drives the liquid crystal display element. 
     The other input terminal of each of the exclusive OR gates 15 1  to 15 n  is supplied with an output from an inverter 18. The input terminal of the inverter 18 is supplied through a switch circuit 19 with a clock pulse having a frequency of for example, 32 Hz which is produced by a driving pulse-generating circuit 20 and is also impressed through another switch circuit 21 with logical level voltage generated by a second logical level voltage-generating circuit 22 constructed in the same manner as the first logical level voltage-generating circuit 14. Both switch circuits 19, 21 are connected together at a point W A  which acts as wired OR. Output signals from the driving pulse-generating circuit 20 and second logical level voltage-generating circuit 22 are conducted through the switch circuits 19, 21 and another inverter 23 to a common segment terminal 24 connected to a common electrode C E  facing the segment electrodes a to g of FIG. 2 through liquid crystal. 
     The driving pulse-generating circuit 20 issues pulses to drive the liquid crystal by alternating current. This driving pulse-generating circuit 20 is a frequency-dividing circuit which is formed of, for example, a flip flop, supplied with pulses from an oscillating circuit included in the LSI circuitry, and generates clock pulses having a prescribed frequency of, for example, 32 Hz. 
     The switch circuits 19, 21 are clocked inverters, each of which comprises an inverter having a p-channel metal oxide semiconductor (hereinafter abbreviated as &#34;MOS&#34;) transistor Q 1  and on n-channel MOS transistor Q 2  and further comprises a p-channel MOS transistor Q 3  and n-channel MOS transistor Q 4  connected in series to the power supply sides V DD , V SS  respectively so as to be used as transfer gates. 
     With the switch circuit 19, the gate of the n-channel MOS transistor Q 3  is supplied with an output A from the first logical level voltage-generating circuit 14, and the gate of the p-channel MOS transistor Q 4  is supplied with an output A from the first logical level voltage-generating circuit 14. Conversely with the switch circuit 21, the gate of the p-channel MOS transistor Q 3  is supplied with an output A from the first logical level voltage-generating circuit 14, and the gate of the n-channel MOS transistor Q 4  is supplied with an output A from the first logical level voltage-generating circuit 14. 
     There will now be described the operation of the liquid crystal display element-driving circuit constructed as mentioned above. 
     a. First, reference is made to the case where the liquid crystal display element-driving circuit is subjected to an ordinary mode. In this case, the flashing signal-generating circuit 13 produces high level &#34;H&#34; D.C. voltage. An output signal A of logical level voltage from the first logical level voltage-generating circuit 14 is converted into a high level &#34;H&#34; form by an external power source for measurement. Since two of the three input terminals of the respective NAND gates 12 1  to 12 n  are supplied with high level voltage, decoded outputs from the output terminals of the decoder circuit 11 are inverted by the NAND gates 12 1  to 12 n . Inverted outputs are supplied to one input terminal of each of the corresponding exclusive OR gates 15 1  to 15 n . At this time, the two transfer gate type MOS transistor Q 3 , Q 4  of the switch circuit 19 are supplied with output signals A , A respectively from the first logical level voltage-generating circuit 14 and put into operation. As the result, the switch circuit 19 acts as an inverter to invert a clock pulse delivered from the driving pulse-generating circuit 20. The inverted clock pulse is again inverted by the inverter 18 and supplied in common to the other input terminal of the respective exclusive OR gates 15 1  to 15 n . 
     On the other hand, the transfer gate type MOS transistors Q 3 , Q 4  of the switch circuit 21 are supplied with output signals A, A respectively from the first logical level voltage-generating circuit 14 and are rendered inoperative, preventing the switch circuit 21 from acting as an inverter. 
     The above-mentioned event occurs regardless of whether an output signal B from the second logical level voltage-generating circuit 22 represents high &#34;H&#34; or low &#34;L&#34; logical level voltage. In other words, the voltage level of an output from the switch circuit 21 is governed by that of the output from the switch circuit 19. Accordingly, outputs from the exclusive OR gates 15 1  to 15 n  have high &#34;H&#34; or low &#34;L&#34; level voltage according to the voltage level of outputs from the decoder circuit 11. Outputs from the exclusive OR gates 15 1  to 15 n  are inverted by the corresponding inverters 16 1  to 16 n , and supplied to the segment terminals 17 1  to 17 n . A clock pulse from the dirving pulse generating circuit 20 is inverted by the switch circuit 19 acting as an inverter and sent forward to the common segment terminal 24 after being again inverted by the inverter 23. Therefore, where one output terminal D 1  of the decoder circuit 11 generates a low logical level voltage &#34;L&#34; output, the corresponding three-input type NAND gate 12 1  produces a high logical level voltage &#34;H&#34; output (because, the remaining two input terminals of the NAND gate 12 1  are already supplied with high logical level voltage &#34;H&#34;). Where outputs from the switch circuits 19, 21 have low logical level voltage &#34;L&#34; at the point W A , then the common terminal 24 is impressed with high logical level voltage &#34;H&#34; obtained through inversion by the inverter 23. Further, high logical level voltage &#34;H&#34; obtained through inversion by the inverter 18 is supplied to the other input terminals of the exclusive OR circuit 15 1 , which in turn generates low logical level voltage &#34;L&#34; (because both input terminals of said OR circuit 15 1  are supplied with high level logical voltage &#34;H&#34;). Low logical level voltage &#34;L&#34;  generated by the exclusive OR circuit 15 1  is inverted into a high logical level voltage &#34;H&#34; form by the corresponding inverter 16 1 . As the result, the segment terminal 17 1  is impressed with high logical level voltage &#34;H&#34;. Namely, the common terminal 24 and segment terminal 17 1  are impressed alike with high logical level voltage &#34;H&#34;, namely, with D.C. voltage of the same in-phase. As the result, the liquid crystal of the segment electrode section corresponding to the segment terminal 17 1  is turned into a nondisplay mode. Conversely where the output terminal D 1  of the decoder circuit 11 generates high logical level voltage &#34;H&#34;, then an output from the corresponding NAND gate 12 1  has low logical level voltage &#34;L&#34;. Contrary to the above-mentioned case, therefore, the segment terminal 17 1  and the common terminal 24 are impressed with voltage having different logical levels, namely, with D.C. voltage of reverse in-phase. As the result, the liquid crystal of the segment electrode section corresponding to the segment terminal 17 1  is turned into a display mode. As described above, D.C. voltage of the same in-phase (nondisplay mode), or D.C. voltage of reverse in-phse (display mode) are impressed across the segment electrodes of the liquid crystal display element and common electrode, thereby effecting a desired pattern of display. 
     There will now be described the case where rapid measurement on the output high level current and voltage of the segment terminals 17 1  to 17 n  is required to see whether or not the values of these current and voltage are reasonable. Output signals A, B from the first and second logical level voltage-generating circuits 14, 22 are made to have low &#34;L&#34; and high &#34;H&#34; voltage levels respectively by an external power source. Now let it be assumed that an output signal A from the first logical level voltage-generating circuit 14 has low voltage level &#34;L&#34;. Then the NAND gates 12 1  to 12 n  all produce high logical level voltage &#34;H&#34;, regardless of whether outputs from the decoder circuit 11 have high &#34;H&#34; or low &#34;L&#34; voltage level. Said high logical level voltage &#34;H&#34; is supplied to the exclusive OR gates 15 1  to 15 n . 
     Further, where an output A from the first logical level voltage-generating circuit 14 has low logical level voltage &#34;L&#34; as mentioned above, then the switch circuit 19 becomes inoperative unlike the aforesaid ordinary case (a) and ceases to act as an inverter. As the result, an output from the liquid crystal driving pulse-generating circuit 20 is shut off by the switch circuit 19 and is not conducted to the inverters 18, 23. In this case, the switch circuit 21 is put into operation contrary to the switch circuit 19 to act as an inverter. Accordingly, an output sisgnal B from the second logical level voltage-generating circuit 22 which was previously chosen to have high voltage level &#34;H&#34; is inverted by the switch circuit 21 into low level &#34;L&#34; form. This low logical level voltage &#34;L&#34; is supplied to the inverters 18, 23. When inverted by the inverter 23, said low logical level voltage &#34;L&#34; is turned into a high level &#34;H&#34; form, which in turn is conducted to the common terminal 24. A low logical level voltage &#34;L&#34; output from the switch circuit 21 is inverted by the inverter 18 into high logical level voltage &#34;H&#34;, which in turn is supplied in the common to one input terminal of the respective exclusive OR gates 15 1  to 15 n . As the result, the other input terminal of the respective exclusive OR gates 15 1  to 15 n  is supplied with an output from the respective NAND gates 12 1  to 12 n  which are chosen to produce a high logical level voltage &#34;H&#34; output. Therefore, the exclusive OR gates 15 1  to 15 n  generate low logical level voltage &#34;L&#34;. Low logical level voltage &#34;L&#34; outputs from the exclusive OR gates 15 1  to 15 n  are inverted by the corresponding inverters 16 1  to 16 n  into a high level &#34;H&#34; form, causing all the segment terminals 17 1  to 17 n  to be all impressed with high logical level voltage &#34;H&#34;. 
     Where all the segment terminals 17 1  to 17 n  and the common segment terminal 24 are all impressed with high logical level voltage &#34;H&#34;, then the output voltage V OH  and output current I OH  of the respective terminals can be quickly measured etermined in succession by means of a voltmeter and ammeter (not shown). 
     c. There will now be described the case where measurement is made to find whether values of current and voltage fall within the specified range, when the segment terminals 17 1  to 17 n  and the common segment terminal 24 are all impressed with low logical level voltage &#34;L&#34;. Output signals A, B from the first and second logical level voltage are all made to have low logical level voltage &#34;L&#34;. In this case, the first and second logical level voltage-generaing circuits 14, 22 are impressed with prescribed low logical level voltage by controlling the operation of an external power source (not shown) capable of selectively producing high &#34;H&#34; or low &#34;L&#34; logical level voltage. As in the preceding case (b), the NAND gates 12 1  to 12 n  generate high logical level voltage. The switch circuit 19 does not act as an inverter, while the switch circuit 21 acts as an inverter as in (b). Therefore, a low logical level voltage output B from the second logical level voltage-generating circuit 22 is inverted into a high level &#34;H&#34; form by the switch circuit 21 now acting as an inverter, and further supplied to the inverters 18, 23. As the result, the common segement terminal 24 is impressed with low logical level voltage &#34;L&#34; obtained through inversion by the inverter 23. The exclusive OR gates 15 1  to 15 n  supplied with a low level voltage &#34;L&#34; output from the inverter 18 produce high level &#34;H&#34; outputs. These high level &#34;H&#34; outputs from the exclusive OR gates 15 1  to 15 n  are inverted by the corresponding inverters 16 1  to 16 n  into a low level &#34;L&#34; form. Accordingly, the segment terminals 17 1  to 17 n  are all impressed with low logical level voltage &#34;L&#34;. Where all the segment terminals 17 1  to 17 n  and common segment terminal 24 are all impressed with low logical level voltage &#34;L&#34;, then the output voltage V OL  and output current I OL  of the respective terminals can be quickly measured in succession as in the case of (b) by means of a voltmeter and ammeter. 
     The switch circuits 19, 21 of FIG. 1 may be replaced by a switch circuit shown in FIG. 3. With the switch circuits 19&#39;, 21&#39; of FIG. 3, the transfer gate type MOS transistor Q 3 , Q 4  which were spatially connected in series to the inverter jointly constituted by Q 1 , Q 2  in FIG. 1, are now connected in a parallel manner to the output terminal of the inverter formed of both Q 1  and Q 2 . However, the switch circuits 19&#39;, 21&#39; have exactly the same function as those of FIG. 1. 
     FIG. 4 shows the arrangement of a liquid crystal display element-driving circuit according to another embodiment of this invention. The circuits shown in FIG. 4 is partly same as those shown in FIG. 2, and the same number is attached to the corresponding blocks and logical gates, so explanation about the same part is omitted. Only the different parts of FIG. 4 from FIG. 2 will now be described. Referential numeral 41 denotes a crystal oscillation stop-detecting circuit, which acts like the first logical level voltage-generating circuit 14 of FIG. 1 additionally provided with the following function. Namely, said crystal oscillation stop-detecting circuit 41 produces high logical level voltage &#34;H&#34;, while a crystal oscillator containues oscillation and generates low logical level voltage &#34;L&#34; when the oscillation of the crystal is brought to an end. With an ordinary digital electronic timepiece, clock pulses generated by the crystal oscillator are used as a fundamental source of timecounting pulses. The crystal oscillator comprises crystal, and active and passive elements. These elements are partly included in the LSI circuitry. When the LSI circuitry is supplied with power, the crystal oscillator commences oscillation. A power source is generally a cell. When the cell voltage drops, the crystal oscillator ceases oscillation. With a digital electronic timepiece using liquid crystal as a display element, however, even when the crystal oscillator stops oscillation, decreased cell voltage is still supplied to the LSI circuitry, causing a certain amount of D.C. voltage to be impressed on the segement terminals 17 1  to 17 n  and common segment terminal 27. This means that D.C. voltage is supplied to the liquid crystal when the crystal oscillation is brought to an end with the resultant deterioration of the liquid crystal. 
     There will now be described the operation of the crystal oscillation stop-detecting circuit 41 by reference to the above-mentioned facts. FIG. 5 shows the circuit arrangment of said circuit 41. A section enclosed in broken lines denotes an ordinary crystal oscillator 50. The crystal oscillator 50 comprises an oscillation stage consisting of a crystal oscillation element X-tal, capacitors C 1 , C 2 , resitors R f , R o  and oscillation inverter 51, and a frequency dividing stage in which flip-flop circuits 54, 55 divide the frequency of an output carried from the oscillation section through inverters 52, 53 to said flip-flop circuits 54, 55. One end of a high resistor R g  disposed outside of the ordinary crystal oscillator 50 is connected to the input side of the oscillation inverter 51 of said crystal oscillator 50, and the other end of the high resistor R g  is grounded. According to the second embodiment of this invention, the ordinary crystal oscillator 50 is further provided with a monostable circuit 55 formed of transistors Q 1  to Q 4  and an inverter 56. The output terminal of the inverter 52 of the ordinary crystal oscillator 50 is connected to the gate terminal of the transistor Q 1  of the monostable circuit 55. The output terminal of the inverter 53 of the ordinary crystal oscillator 50 is connected to the drain terminal of the transistor Q 1 . When the transistor Q 1  is turned off, the monostable circuit 55 becomes stable, because the point P is impressed with high logical level voltage &#34;H&#34;. An output signal A from the crystal oscillation stop-detecting circuit 41 is supplied in common to the NAND gates 12 1  to 12 n . Referential numeral 42 denotes a transistor Q 5  (FIG. 4) connected to the output side of the switch circuit 19 for its control. 
     There will now be described the operation of a liquid crystal display element-driving circuit according to the second embodiment of FIG. 4, which is constructed as described above. 
     a. When the LSI is supplied with normal cell voltage, and the crystal oscillator 50 (FIG. 5) of the LSI circuitry works in a normal mode, then the gate terminal of the transistor Q 1  of the monostable circuit 55 is supplied for some period, for example, with high logical level voltage &#34;H&#34; and the drain terminal of the transistor Q 1  is impressed with low logical level voltage &#34;L&#34;. Conversely when the gate terminal of the transistor Q 1  is supplied with low logical level voltage &#34;L&#34;, then the drain terminal of the transistor Q 1  is impressed with high logical level voltage &#34;H&#34;. In either case, the point P is supplied with low logical level voltage &#34;L&#34;. As the result, the point S on the output side of the inverter 56 is impressed with high logical level voltage &#34;H&#34;. As the result, an output A from the liquid crystal oscillation stop-detecting circuit 41 has high logical level voltage &#34;H&#34;, causing the transistors Q 1 , Q 2  of the switch circuit 19 jointly constituting an inverter to be rendered operative as previously described in connection with FIG. 1. Since, at this time, the control transistor Q 5  42 becomes inoperative, the switch circuit 19 acts as an ordinary inverter. Therefore, as in the ordinary case (a) of the first embodiment, clock pulses from the driving pulse-generating circuit 20 appear between the segment terminals 17 1  to 17 n  and common segment terminal 24 of the crystal display element-driving circuit of FIG. 4 in the same inphase (nondisplay mode) or reverse in-phase (display mode). These clock pulses are supplied to the segment electrodes of a liquid crystal display element and a common electrode, attaining a desired display of time data. 
     b. Where the cell voltage drops and the crystal oscillator stops oscillation, then an input to the oscillation inverter 51 of the crystal oscillator 50 of FIG. 5 is converted into low logical level voltage by the high resistor R g . As the result, the gate terminal of the transistor Q 1  of the monostable circuit 55 is impressed with low logical level voltage &#34;L&#34; and the drain terminal of the transistor Q 1  is supplied with high logical level voltage &#34;H&#34;, causing the transistor Q 1  to be rendered inoperative. Accordingly, the point P is impressed with high logical level voltage &#34;H&#34;, and the point S is supplied with low logical level voltage &#34;L&#34;. Eventually, an output A from the crystal oscillation stopdetecting circuit 41 has low logical level voltage &#34;L&#34;. As the result, the transistors Q 1 , Q 2  of the switch circuit 19 (FIG. 5) become inoperative and the control transistor Q 5  42 is rendered conducting, causing the switch circuit 19 acting as an inoperative inverter to produce low logical level voltage &#34;L&#34;. The common segment terminal 24 is impressed with the high logical level voltage &#34;H&#34; of an output from the switch circuit 19 which was inverted by the inverter 23. On the other hand, the input terminals of the respective NAND gates 12 1  to 12 n  are supplied with the output A from the crystal oscillation stop-detecting circuit 41 which now has low logical level voltage &#34;L&#34;, causing the NAND gates 12 1  to 12 n  to produce high logical level voltage &#34;H&#34;. Low logical level voltage &#34;L&#34; output from the switch circuit 19 is inverted into a high logical level &#34;H&#34; form by the inverter 18. Thus both input terminals of the respective exclusive OR gates 15 1  to 15 n  are impressed with high logical level voltage &#34;H&#34;, causing said OR gates 15 1  to 15 n  to generate low logical level voltage &#34;L&#34; outputs, which in turn are inverted by the corresponding inverters 16 1  to 16 n . As the result, the segment terminals 17 1  to 17 n  are supplied with high logical level voltage &#34;H&#34;. Namely, when crystal oscillation is brought to an end, the segment terminals 17 1  to 17 n  and common segment terminal 24 are all impressed with the same high logical level voltage &#34;H&#34;. Consequently, the liquid crystal is not impressed with any D.C. voltage, but is saved from deterioration and shortened life. So even when the timepiece is kept in ususual mode, that is to say, in stopping mode due to the decrease of the power of a cell, above mentioned circuit in the timepiece effectively works to prevent liquid crystal from being impressed by D.C. voltage. 
     Where it is desired not to display any time data on a digital electronic timepiece, then all the liquid crystal-driving terminals can be impressed with the same logical level voltage. In this case, the NAND gates 12 1  to 12 n , switch circuit 19 and transistor Q 5  42 are impressed with prescribed logical level voltage by a switch disposed outside of the digital electronic timepiece, thereby carrying out the same function as that of the crystal oscillation stop-detecting circuit and in consequence prominently extending the effective life of liquid crystal. 
     This invention is not limited to the above-mentioned embodiments, and various changes and modifications can be made without departing from the spirit and scope of this invention.