Integrated circuit amplifier
This invention relates to amplifier circuits for incorporation in solid state circuits and, more particularly, to such circuits which may be designed to have a desired gain which will be uniform for all chips of a production run. 
     The use of resistive negative feedback with a high gain amplifier to provide a designed overall gain which is stable and does not vary with the parameters of the components is conventional with circuits having discrete components. A direct application of such circuits to integrated circuits on semiconductor chips is, however, not satisfactory. The required resistors take up an inordinate area of the chip and generate a large heat loss. Also, the use of the feedback resistors involves both a low impedance input and a current drain from the amplifier output, both factors calling for larger, higher power, active components each of which takes more chip area than normal components. 
     It is desirable to have an amplifier circuit which can be designed to have a preset gain over a wide range of production parameters, has a very high input impedance and uses low power components so that it requires only a small chip area for its implementation. 
     It is then an object of this invention to provide an amplifier circuit for an integrated circuit chip, the circuit requiring no passive impedances or large power generating components and hence needing only a small chip area. 
     It is another object to provide an amplifier circuit of field effect transistors of the metal-oxide-semiconductor type (MOSFET) which will occupy a small chip area and which can be designed to have a preset gain despite wide variations in process related parameters between different chips. 
     A further object is to develop an amplifier circuit in MOSFET technology which has a preset gain that is independent of processing variables. 
     Still another object is to develop such an amplifier which presents a very high impedance to an input circuit and has no appreciable output drain for a feedback circuit whereby the circuit may be formed of minimal size components. 
    
    
     Other objects will be set out or will be obvious from the following description of a preferred embodiment of the invention and from the appended drawings. 
     In the drawings: 
     FIG. 1 is a schematic diagram of a field effect transistor and the designation of the operating parameters thereof. 
     FIG. 2 is a diagram showing the preferred embodiment of the amplifier of this invention. 
    
    
     The use of negative feedback with a high gain amplifier to achieve a stable and precise overall circuit gain is conventional in electronic circuitry. For frequency independence and linearity, the negative feedback will be provided by resistors and the gain can be set by the ratio between the feedback resistance and one in the input circuit. Any desired ratio can be easily obtained so the circuit gain can be set quite closely. 
     In integrated circuit design on silicon semiconductor chips, resistors require an inordinate area of the chip. Also, the current drain through the feedback resistor requires that the output stage of the amplifier be designed to provide power which means a larger chip area for the output components. The disclosed circuit provides feedback by the use of active FET&#39;s rather than resistors and can be applied to a chip without wasted area. 
     In the circuit of FIG. 2, the amplifier 10 may be any conventional design-operational amplifier. It may have a very high gain between input and output, e.g., a gain of 1,000 or more, but the gain need not be precisely set and need not be linear. Both factors can vary with manufacturing conditions. Amplifier 10 has two inputs, a lower one 11 which is connected to a ground or reference level voltage and an upper one 12 which is connected to an input signal and is an inverting input with respect to the amplifier output 13. 
     An input signal is applied to input terminals 14 and 15 which are connected to the gate of an FET 16 and to ground respectively. FET 16 has its drain connected to the plus side 17 of a voltage source and has its source connected to input 12 of amplifier 10. A second FET 18 is connected in parallel to FET 16 with its drain also connected to the positive side 17 of the voltage source and its source connected to amplifier input 12 but its gate is connected to output 13 of amplifier 10. The sources of both FET&#39;s 16 and l8 and input 12 are connected through a constant current regulator 20 to the negative side 21 of the voltage source. Both FET&#39;s are preferrably of the depletion type which will be normally conductive when the gate and source are at the same voltage. As is usual in FET&#39;s, the gate impedance of FET 16 is very high so that there is no requirement for input current and the amplifier is well suited for no-load applications such as sample and hold circuits. 
     In operation, the current through regulator 20 and the voltage of the supply are adjusted with inputs 11 and 14 at ground level until the voltage at amplifier input 12 is at the same level as the voltage at input 11 or is at a virtual ground level. Amplifier output 13 will then also be at a ground level so that the gate of FET 18 is also at ground. Both FET&#39;s 16 and 18 are to be operating in their linear operating region. 
     Any increase in the input voltage at terminal 14 will cause FET 16 to exhibit a reduced resistance and, therefore, a lower voltage drop so that the voltage of input 12 becomes positive. This positive voltage at input 12 is amplified in amplifier 10 and inverted to generate a negative voltage on output 13 which is applied to the gate of FET 18 to increase its effective resistance. The voltage at the gate of FET 18 will be such that there is little overall change in the net resistance of the combination of FET&#39;s 16 and 18 and hence the voltage change at input 12 will be negligible so that input 12 is always at a virtual ground level. The output voltage of amplifier 10 will always be inversely related to the input voltage on terminal 14 by a ratio depending upon the relationship to the design parameters of FET&#39;s 16 and 18. 
     To understand the relationship of the parameters to be used in the development of FET&#39;s 16 and 18, it is desirable to consider the mathematical description of the transistors with reference to FIG. 1. The drain current I D  for the linear region is given by the relationship 
     
         I.sub.D = μC(W/L) (V.sub.GS - V.sub.T - V.sub.DS /2) v.sub.DS 
    
     for 
     
         V.sub.GS &gt; V.sub.T 
    
     and 
     
         V.sub.DS &lt; (V.sub.GS - V.sub.T) 
    
     where 
     μ is the effective mobility of channel electrons, 
     C is the gate capacitance per CM 2 , 
     (w/l) is the effective width-to-length ratio of the FET channel, 
     V GS  is the gate voltage with respect to the source voltage, 
     V T  is the threshold voltage for FET conduction, and 
     V DS  is the drain-to-source voltage of the FET. 
     In the case of depletion FET&#39;s such as FET&#39;s 16 and 18 
     
         V.sub.T = K.sub.1 + K.sub.2 (V.sub.S-SUB + ψ)1/2 + K.sub.3 (V.sub.S-SUB + ψ) 
    
     k 1 , k 2 , and K 3  are process-dependent constants, and 
     ψ is twice the Fermi level 
     As we have assumed that amplifier 10 has sufficient gain to make input 12 a virtual ground, we can write the current equations for FET&#39;s 16 and 18 as 
     
         I.sub.16 = 2λ.sub.16 (V.sub.IN - V.sub.T16 - V.sub.REF /2) V.sub.REF 1 
    
     where 
     V REF  = the drain voltage 17 with respect to ground, 
     and 
     
         V.sub.REF ≦ (V.sub.IN - V.sub.T16),                 1-A 
    
     thus insuring operation in the linear region, and 
     
         λ.sub.16 = 1/2μ C(W/L).sub.16                    1-B 
    
     
         i.sub.18 = 2λ.sub.18 (v.sub.out - v.sub.t18 - v.sub.ref /2) v.sub.ref                                                 2 
    
     where 
     
         V.sub.REF ≦ (V.sub.OUT - V.sub.T18) and             2-A 
    
     
         λ.sub.18 = 1/2μ c(w/l).sub.18                    2-b 
    
     equations (1-A) and (2-A) serve as the limiting equation for the range of input and output voltage swings, typical values of V T  are about -1.74 volts for long channel devices, i.e., those where L is in the neighborhood of 0.0005 inches. 
     Now differentiate the equations for I 16  and I 18  with respect to V IN , noting that since the source node is a virtual ground, the V T  &#39;s are constants 
     
         δI.sub.16 /δV.sub.IN = 2λ.sub.16 V.sub.REF and 3 
    
     
         δI.sub.18 /δV.sub.IN = 2λ.sub.18 V.sub.REF δV.sub.OUT /δV.sub.IN                         4 
    
     as I R  is a constant, the current at the source node of FET&#39;s 16 and 18 is 
     
         I.sub.R = I.sub.16 + I.sub.18 and differentiating          5 
    
     
         0 = δI.sub.16 /δV.sub.IN + δI.sub.18 /δV.sub.IN 6 
    
     substituting equations 3 and 4 into equation 6, 
     
         2λ.sub.16 V.sub.REF + 2λ.sub.18 V.sub.REF δV.sub.OUT /δV.sub.IN = 0 
    
     whereby 
     
         δV.sub.OUT /δV.sub.IN = - λ.sub.16 /λ.sub.18 7 
    
     and using equations (1-B) and (2-B) 
     
         δv.sub.out /δv.sub.in = - (w/l).sub.16 /(w/l).sub.18 8 
    
     this equation shows that the voltage gain of the circuit of FIG. 2 is set by the design of the geometries of FET&#39;s 16 and 18. Since these transistors can be located adjacent to each other so that the process-dependent variables are the same for each, the characteristics of the two FET&#39;s will be similar and the W/L ratio of equation 8 will be the only design variables needed to set a desired amplifier gain. Since these ratios can be designed to close tolerances, the V OUT  /V IN  ratio can be accurately designed and will not vary appreciably from chip to chip even though the process parameters and individual FET characteristics vary substantially. 
     This description of a preferred embodiment of my invention is not to be taken as limiting the scope of the invention as set out in the following claims.