Arrangement for distribution of clock signals
The present invention refers to an arrangement for distribution of certain clock signals in a clock signal series by means of signals of lower frequency compared to the frequency of said clock signal series, particularly in order to obtain well-defined pulses from said signals of lower frequency, for control of logic equipment placed at a distance from the clock pulse source. 
     When distributing clock signals to different equipment which are placed at some distance from the clock pulse source, distortion can occur in the transmission lines. This results in that the clock pulses obtain indefinite flanks and can influence the equipment at different times. 
     The purpose of the invention is to achieve a clock distribution arrangement by means of which short, well-defined pulses can be produced in the receiver equipment so that the uncertainty due to the distortion is eliminated. 
     The invention which solves said problem is characterized in accordance with the claim. 
    
    
     The invention is described by means of an embodiment with reference to the appended drawings in which 
     FIG. 1 shows a block diagram of the invention and 
     FIG. 2 shows a diagram of signals generated in the arrangement according to the invention. 
    
    
     In FIG. 1 a clock pulse oscillator CL delivers a clock pulse train K1 to a counter arrangement CE containing two binary counters C1 and C2 and an inversion circuit I. In order to divide the frequency the clock pulse train K1 is connected directly to the input of the binary counter C1 and through the inversion circuit I to the input of the binary counter C2. Thus both counters C1 and C2 are fed from the clock signal K1 but with inverted phase positions. From a determined output on each of the counters C1 and C2 a pulse series PS1 and PS2 is obtained respectively the pulse width of which, compared with the clock pulse, is dependent on the chosen counter step, the phase positions of the two pulse series differing from each other with half a clock pulse length. The two pulse series PS1 and PS2 are each fed to an amplifier S1 and S2 respectively and are transferred from these to associated receivers M1 and M2 on the receiver side. The transmitters S1 and S2 are mounted in the same case, and so are the receivers M1 and M2 which results in that the pulse series will have the same distortion at the receiver side. The pulse series PS1 and PS2 are fed from the receivers M1 and M2 to the inputs of an EXCLUSIVE-OR-circuit LC on the output of which pulses K2 are obtained during the time when the amplitudes of said pulse series differ from each other. The pulses K2 which are obtained at the output of the EXCLUSIVE-OR-circuit are then distributed to a number of units in order to control the same. According to the preferred embodiment said units are composed of memories ME1-ME3. 
     FIG. 2 shows the time sequence for the different pulse series. 
     Line a shows the original clock pulse series K1. 
     Line b shows the pulse series PS1 obtained by dividing by for example six. 
     Line c shows the other pulse series PS2 obtained by dividing by for example six, but which is phase displaced with half a clock pulse length compared to the first pulse series. 
     Line d, finally, shows the pulse series K2 which is obtained when the two transmitted pulse series PS1 and PS2 have been subject to an EXCLUSIVE-OR operation in the circuit LC. 
     The logic circuit LC to which the pulse series PS1 and PS2 are fed must, of course, not be an EXCLUSIVE-OR-circuit but can consist of, for example, an AND-circuit or a circuit which combines different logic functions which makes it possible to produce different pulse series in dependence on amplitudes that are detected in the transmitted pulse series. 
     It is also possible, instead of producing two pulse series on the sender side, to produce three or more pulse series which are transmitted in order to constitute a number of desired pulse series with well-defined pulses on the receiver side.