Electronic timepiece circuit for automatically displaying the day of the week
BACKGROUND OF THE INVENTION 
     This invention is directed to electronic timepiece circuitry for automatically displaying the day of the week, and in particular, to electronic timepiece circuitry for decoding the timekeeping signals produced by the day, date and year counters of an electronic timepiece into bit signals, summing the bit signals, dividing same by a count of seven, and utilizing the remainder to automatically effect a display of the day of the week. 
     Heretofore, in electronic timepieces having calendar displays of the type wherein the day, date and month information are displayed, when the day of the week is also displayed, the electronic circuitry utilized to select the day of the week is operated independently of the other calendar circuitry, in particular, the day, month and year counters. It is noted however that the day of the week can be derived from the timekeeping signals produced by the year counter, month counter and day counter, and accordingly, an electronic timepiece circuit, capable of automatically displaying the day of the week in response to the timekeeping signals produced by the day, month and year counters, is desired. 
     SUMMARY OF THE INVENTION 
     Generally speaking, in accordance with the instant invention, an electronic timepiece circuit for automatically displaying the day of the week, in response to the timekeeping signal respectively produced by a day counter, month counter and year counter, is provided. Each of the timekeeping signals produced by the respective counters is representative of a binary count thereof. The electronic circuitry of the instant invention is particularly characterized by decoder and selection circuitry coupled to each of the counters for receiving the timekeeping signals produced thereby, decoding same and seriatim producing a plurality of binary bit signals, each of which are representative of a binary count of the selected and decoded timekeeping signals. Remainder circuitry is provided for receiving and summing each of the binary bit signals, dividing the summed signals by seven to thereby produce a remainder signal representative of the day of the week. A day of the week decoder circuit and display is provided for decoding the remainder signal and displaying the day of the week in response to the remainder signal being applied thereto. 
     Accordingly, it is an object of the instant invention to provide an improved electronic timepiece circuit for automatically displaying the day of the week. 
     A further object of the instant invention is to provide an electronic timepiece circuit that utilizes the count of the timekeeping signals produced by the day, month and year counters to automatically effect a display of the day of the week. 
     Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification. 
     The invention accordingly comprises the features of construction, combination of elements, and arrangement of parts which will be exemplified in the construction hereinafter set forth, and the scope of the invention will be indicated in the claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a fuller understanding of the invention, reference is had to the following description taken in connection with the accompanying drawings, in which: 
     FIG. 1 is a block circuit of an electronic timepiece circuit for automatically displaying the day of the week constructed in accordance with the preferred embodiment of the instant invention; and 
     FIG. 2 is a wave diagram illustrating the operation of the electronic timepiece circuitry depicted in FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference is first made to FIG. 1, wherein an electronic timepiece circuit for automatically displaying the day of the week is depicted. A decoder/selector circuit 14 is coupled to day counter 13, month counter 12 and year counter 11 to respectively receive the 5-bit, 4-bit and 5-bit timekeeping signals produced thereby. The decoder/selector circuit 14 is adapted in response to receiving the timekeeping signals produced by the day counter, month counter and year counter to produce seven distinct 3-bit output signals, and to apply the seven 3-bit output signals seriatim to an input selector 16. A read only memory 15, having the binary equivalent of the number minus seven stored therein, is also coupled to the input selector 16 at the inputs C.sub.α, C.sub.γ, C.sub.β, C.sub.α of the input selector 16. The binary equivalent of the number -7 (1001) is used because only four bits of information are stored in the read-only memory and read into input selector 16. Thus, the fifth binary bit of information is ignored. Accordingly, the number -7 is selected so that the fourth bit does not become 0 when a binary 8 (1000) is summed with any binary number from 8 to 15 which would normally cause the fourth bit to be changed to a binary 0 and the fifth bit indexed to a binary 1. Specifically, the input selector 16 alternately applies the bit signals and, thereafter, the minus seven binary count stored in the read only memory 15 to the adder 17 to permit the binary count of the bit signal to be divided by seven by the 4-bit adder circuit 17. The adder circuit 17 effects a binary addition of the bit signal and the minus seven signal, which is the equivalent of dividing the count of the binary bit signal by seven, and produces a remainder signal S.sub.α, S.sub.γ, S.sub.β, S.sub.α to latch S circuit 18, which circuit, in turn, applies a day of the week signal W.sub.γ, W.sub.β, W.sub.α to day of the week decoder and display 20, to thereby automatically effect a display of the day of the week. Additionally, the outputs of the latch S circuit 18 are also applied to latch A circuit 19, which circuit stores the remainder signal from the previous division operation performed by the adder circuit 17 and permits the adder circuit 17 to sum the remainder stored in the latch A circuit 19 with the binary count of the next bit signal produced by the decoder/selector circuit 14 that is applied to the adder circuit 17 by the input selector 16. 
     Because the instant invention utilizes the binary count of the timekeeping signals produced by the day, month and year counters to effect a binary operation, the subscripts α, β, γ, α, ε are utilized herein to denote the respective binary outputs of the circuits. 
     For example, as noted above, the day of the week signals W.sub.γ, W.sub.β, W.sub.α produced by the latch S circuit 18, and the manner in which these signals correspond to each of the seven days of the week is illustrated in Table 1 included herein. 
     
                       Table 1                                                     
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Data W                                                                    
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Number    W.sub.γ                                                   
                   W.sub.β                                           
                            W.sub.α                                 
                                    Day                                   
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0         0        0        0       Sun.                                  
1         0        0        1       Mon.                                  
2         0        1        0       Tues.                                 
3         0        1        1       Wed.                                  
4         1        0        0       Thur.                                 
5         1        0        1       Fir.                                  
6         1        1        0       Sat.                                  
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     Accordingly, as illustrated in Table 1, the day of the week signal W.sub.γ, W.sub.β, W.sub.α are binary representations for the numbers 0 through 6 and correspond to each of the days of the week beginning with Sunday (0, 0, 0) and ending with Saturday (1, 1, 0). Thus, the decoder and display 20, in response to receiving one of the seven binary counts illustrated in Table 1, automatically displays the day of the week corresponding to the particular count. 
     The manner in which the 5-bit day counter 13 produces a 5-bit timekeeping signal D.sub.ε, D.sub.α, D.sub.γ, D.sub.β, D.sub.α, which signal is selected and decoded into a first 3-bit signal D 1  and a second 3-bit signal D 2 , by the decoder/selector circuit 14, is illustrated in detail in Table 2, set forth herein. As illustrated in Table 2, the day, having the numerical count of zero is the last day of the previous month. Accordingly, if the date is divisible by seven and leaves a particular remainder, the first 3-bit signal D 1 , produced by the decoder/selector circuit, has a count equal to the number of times that seven divides into the count of the timekeeping signal, and leaves a remainder. As noted above each of the operations of the instant invention is conducted with binary digits, and therefore, division of the date by seven, when translated into binary logic, requires that the binary representation of the number minus seven be added to the binary representation of the particular date count in order to obtain the same result as if a real number were divided by seven. The 3-bit signal D 2  is, in every instance, equal to the binary count of the digits D.sub.α, D.sub.β, D.sub.γ. It is also noted that the first 3-bit signal D 1  is equal to the binary count of the last two digits D.sub.ε, D.sub.α of the timekeeping signal produced by the day counter 13. Thereafter, calculation of the remainder of the day is obtained by summing the first 3-bit signal D 1  and the second 3-bit signal D 2  and dividing same by seven. As detailed above, the signal D 1  (D 1 γ, D 1 β, D 1 α) is obtained from the timekeeping signal by setting D 1 γ equal to 
     
                                           Table 2                                 
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Data D                                                                    
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Date                                                                      
    D.sub.ε                                                       
       D.sub.60                                                           
          D.sub.γ                                                   
            D.sub.β                                                  
                D.sub.α                                             
                  Remainder                                               
                        D.sub.1                                           
                           D.sub.2                                        
                              Date                                        
                                 D.sub.ε                          
                                    D.sub.α                         
                                       D.sub.γ                      
                                          D.sub.β                    
                                             D.sub.α                
                                                Remainder                 
                                                      D.sub.1             
                                                        D.sub.2           
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0  0  0  0  0  0  0     0  0  16 1  0  0  0  0  2     2 0                 
1  0  0  0  0  1  1     0  1  17 1  0  0  0  1  3     2 1                 
2  0  0  0  1  0  2     0  2  18 1  0  0  1  0  4     2 2                 
3  0  0  0  1  1  3     0  3  19 1  0  0  1  1  5     2 3                 
4  0  0  1  0  0  4     0  4  20 1  0  1  0  0  6     2 4                 
5  0  0  1  0  1  5     0  5  21 1  0  1  0  1  0     2 5                 
6  0  0  1  1  0  6     0  6  22 1  0  1  1  0  1     2 6                 
7  0  0  1  1  1  0     0  7  23 1  0  1  1  1  2     2 7                 
8  0  1  0  0  0  1     1  0  24 1  1  0  0  0  3     3 0                 
9  0  1  0  0  1  2     1  1  25 1  1  0  0  1  4     3 1                 
10 0  1  0  1  0  3     1  2  26 1  1  0  1  0  5     3 2                 
11 0  1  0  1  1  4     1  3  27 1  1  0  1  1  6     3 3                 
12 0  1  1  0  0  5     1  4  28 1  1  1  0  0  0     3 4                 
13 0  1  1  0  1  6     1  5  29 1  1  1  0  1  1     3 5                 
14 0  1  1  1  0  0     1  6  30 1  1  1  1  0  2     3 6                 
15 0  1  1  1  1  1     1  7  31 1  1  1  1  1  3     3 7                 
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     0, d 1 β equal to D 1 ε and D 1 α equal to D 1 α. Similarly, the 3-bit signal D 2  (D 2 γ, D 2 β, D 2 α) is obtained as noted above by making D 2 γ equal to D.sub.γ, D 2 β equal to D.sub.β and D 2 α equal to D.sub.α of the timekeeping signal produced by the day counter. It is noted that the signals D 1  and D 2  cannot be said to be, strictly speaking, representations of the number of times that seven divides into the number of the date since several cases exist, specifically, seven, fourteen, twenty-one and twenty-eight, wherein seven divides evenly and would leave no remainder. In any event, as detailed above, by summing the first and second 3-bit signals D 1  and D 2  and dividing same by seven, a remainder is determined. A specific example can be taken for the twenty-ninth day, illustrated in Table 2, wherein D 1  equals three, D 2  equals five, D 1  plus D 2  equals eight, thereby leaving a remainder of one. 
     In order to demonstrate the manner in which the 4-bit timekeeping signals, produced by the month counter 12, are decoded and selected into third and fourth 3-bit signals M 1  and M 2 , Table 3 is provided herein. It is noted that the 3-bit signal M 1  utilizes March or November as the standard month and the second-bit signal M 2  is utilized as a leap year signal. March or November are selected since both months are both thirty-one day months and both months always start on the same day of the week. Accordingly, the third and fourth 3-bit signals M 1  plus M 2  are added in the same manner as the first and second 3-bit signals and divided by seven in order to provide a remainder signal in the same manner detailed above with respect to the 3-bit signals derived from the timekeeping signals produced by the day counter. Nevertheless, the derivation of the 3-bit signals M 1  and M 2  is a bit more complex. Specifically, M 1  (M 1 γ , M 1 β, M 1 α) is obtained by making M 1 γ equal to M.sub.α M.sub.β M.sub.α + M.sub.α M.sub.α, M 1 β equal to 
     
                       Table 3                                                     
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Data M                                                                    
Month M.sub.α                                                       
             M.sub.γ                                                
                    M.sub.β                                          
                         M.sub.α                                    
                              M.sub.1                                     
                                   M.sub.1γ                         
                                        M.sub.1β                     
                                             M.sub. 1α              
                                                  M.sub.2                 
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1     0      0      0    1    4    1    0    0    6                       
2     0      0      1    0    0    0    0    0    6                       
3     0      0      1    1    0    0    0    0    0                       
4     0      1      0    0    3    0    1    1    0                       
5     0      1      0    1    5    1    0    1    0                       
6     0      1      1    0    1    0    0    1    0                       
7     0      1      1    1    3    0    1    1    0                       
8     1      0      0    0    6    1    1    0    0                       
9     1      0      0    1    2    0    1    0    0                       
10    1      0      1    0    4    1    0    0    0                       
11    1      0      1    1    0    0    0    0    0                       
12    0      0      0    0    2    0    1    0    0                       
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     M.sub.β (m.sub.α + m.sub.γ) + m.sub.γ m.sub.β m.sub.α and M 1 α equal to M.sub.γ. The signal M 2  (M 2 γ, M 2 β, M 2 α) is obtained by setting M 2 γ equal to M 2 β, which, in turn, is set equal to l. M.sub.α M.sub.γ (M.sub.β · M.sub.α + M.sub.β M.sub.α, and M 2 α is equal to 0, where l is a signal having a binary value of 1 in each leap year and 0 in the years that are not leap years. 
     The manner in which a fifth 3-bit signal Y 1 , sixth 3-bit signal Y 2  and seventh 3-bit signal Y 3  are derived from the timekeeping signal (Y.sub.ε, Y.sub.α, Y.sub.γ, Y.sub.β) produced by the year counter 11 is illustrated in Table 4, set forth herein. However, it is noted 
     
                       Table 4                                                     
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Data Y                                                                    
Year Y      --    Y.sub.1                                                 
                      Y.sub.2                                             
                           Y.sub.3                                        
                               Year Y    --  Y.sub.1                      
                                                  Y.sub.2                 
                                                      Y.sub.3             
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76   0      0     0   0    0   92   16   6   4    2   0                   
77   1      1     0   0    1   93   17   0   4    2   1                   
78   2      2     0   0    2   94   18   1   4    2   2                   
79   3      3     0   0    3   95   19   2   4    2   3                   
80   4      5     1   0    4   96   20   4   5    2   4                   
81   5      6     1   0    5   97   21   5   5    2   5                   
82   6      0     1   0    6   98   22   6   5    2   6                   
83   7      1     1   0    7   99   23   0   5    2   7                   
84   8      3     2   1    0   2000 24   2   6    3   0                   
85   9      4     2   1    1   01   25   3   6    3   1                   
86   10     5     2   1    2   02   26   4   6    3   2                   
87   11     6     2   1    3   03   27   5   6    3   3                   
88   12     1     3   1    4   04   28   0   7    3   4                   
89   13     2     3   1    5   05   29   1   7    3   5                   
90   14     3     3   1    6   06   30   2   7    3   6                   
91   15     4     3   1    7   07   31   3   7    3   7                   
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     that the binary coded representation of the 5-bit timekeeping signal, produced by the year counter 11, is identical to the binary coded representation of the 5-bit timekeeping signal produced by the day counter 13 and, hence, has been omitted from Table 4 for the sake of simplifying the presentation of same herein. It is noted that the sixth 3-bit signal Y 2  and the seventh 3-bit signal Y 3  are derived in the identical manner utilized to derive the first and second 3-bit signals D 1  and D 2 . Additionally, the fifth 3-bit signal Y 1  is obtained by making Y 1  equal to the last three bits of the timekeeping signal in a manner to be demonstrated in greater detail below. The dividing of a 365 day year by seven provides a remainder of one and the dividing of a 366 day year, during a leap year, by seven provides a remainder of two. Accordingly, the fifth, sixth and seventh 3-bit signals are derived by utilizing the month of March or November of 1976 as a reference standard. The deviation, illustrated in Table 4, is obtained by dividing the sum of the fifth, sixth and seventh 3-bit signals by seven. Specifically, the fifth 3-bit signal Y 1   (Y 1 γ, Y 1 β, Y 1 α) is obtained by making Y 1 γ equal to Y.sub.ε, Y 1 β equal to Y.sub.α and Y 1 α equal to Y.sub.γ. In every other respect the sixth and seventh 3-bit signal Y 2  (Y 2 γ, Y 2 β, Y 2 α) and Y 3  (Y 3 γ, Y 3 β, Y 3 α) are obtained in the identical manner that the first and second 3-bit signals D 1  and D 2  are derived. Accordingly, in the year 2001, Y 1  plus Y 2  plus Y 3  equals six plus three plus one equals ten and the remainder, obtained by dividng ten by seven, is three, which number represents the deviation. 
     As detailed above, the zero day of March or November, otherwise recognized as the last day of February or October of 1976, is a Sunday and this day it utilized as a reference standard for the day of the week electronic circuitry. Accordingly, the remainder obtained by summing the seven 3-bit signal, D 1  plus D 2  plus M 1  plus M 2  plus Y 1  plus Y 2  plus Y 3  by seven, will produce a remainder signal, which remainder signal is representative of the day of the week. In the circuit illustrated in FIG. 1, the respective 3-bit signals are successively applied to the 4-bit adder circuit 17, and after each 3-bit signal is applied, the input selector 16 applies the minus seven binary signal stored in the read only memory 15 the necessary number of times to effect a division of the real number stored in the adder circuit by seven. In actual operation, once the first 3-bit signal D 1  is divided by seven, the remainder, if any, produced thereby will be stored in the latch A circuit 17 and will be applied to the adder 17 to be summed with the next 3-bit digit signal D 2  when same is applied to the adder 17 by the input selector 16. Thereafter, the sum of the remainder stored in latch A circuit 17 and the second 3-bit signal D 2  are divided by seven by applying the minus seven binary code (1 0 0 1) to the adder 17 to thereby establish a new remainder, which remainder is again applied to the latch S circuit 18 and, based thereon, is also stored in the latch A circuit 19 for summing with the next 3-bit signal applied to the adder circuit 17. Accordingly, each of the seven 3-bit signals are seriatim applied to the adder 17 by the input selector 16 until the output signal S.sub.α, S.sub.β, S.sub.γ, S.sub.α  stored in the latch S circuit 18 is a signal representative of all seven of the bit signals having been summed and divided by seven. The remainder produced by the adder, in response to the seventh 3-bit signal being summed therein and divided by seven, represents the remainder signal W.sub.γ, W.sub.β, W.sub.α, the binary representation of the remainder signal representing the day of the week. Accordingly, the remainder signal is applied to the day of the week decoder and display in order to automatically effect a display of the day of the week. As detailed above, the minus seven binary count (C.sub.α, C.sub.γ, C.sub.β, C.sub.α) applied to the adder by the input selector 16 can be obtained by making C.sub.α equal to C.sub.α equal to A.sub.α  + A.sub.γ A.sub.β A.sub.α  and C.sub.γ  equal to C.sub.β  equal to zero. 
     Referring to FIG. 2, a timing diagram, illustrating the operation of the day of the week circuitry described above, is depicted. The calculation of the day of the week is performed when timing pulse 30 is in a positive half cycle. The positive half cycle of the signal 30 can be selected to be performed at a predetermined time in the timepiece, such as once each hour or once each day. Moreover, the duration of the timing signal can be limited to one-thirty-second of a second or any larger time interval. The timing representation 31, illustrated in FIG. 2, demonstrates the eight distinct periods of operation of the input selector 16. Specifically, during the time interval t 1 , each of the respective circuits for automatically producing a day of the week signal are reset. Thereafter, during the time intervals t 2  through t 8 , the respective 3-bit signals, starting with the seventh timing signal Y 1  in the interval t 2  and finishing with the last 3-bit timing signal D 1  during the time interval t 8 , are seriatim applied to the adder 17. Selection of the 3-bit signals by the decoder/selector circuit is effected by utilizing three distinct frequency signals and switching circuitry of the type well known in the art. An input selector timing pulse 32 is applied to the input selector 16 and selects the 3-bit signals produced by the decoder/selector signals to be applied to the adder 17. When the input selector timing signal 32 is in a positive half cycle, a 3-bit signal produced by the decoder/selector circuit 14 is applied to the adder 17. Alternatively, when the input selector timing signal 32 is in a negative half cycle, the input selector 16 applies the minus seven binary representation stored in the read only memory 15 to the adder 17. A latch S circuit write-in pulse signal 33 is utilized to write-in the output S.sub.α, S.sub.γ, S.sub.β, S.sub.α  of the adder 17 when the write-in pulse is a positive going pulse. Similarly, write-in pulse 34 is utilized to write-in to the latch A circuit 19 the binary pulse stored in the latch S circuit 18. By delaying the write-in pulse 34 of the latch A circuit 19 with respect to the write-in pulse 33 of the latch S circuit 18, the latch A circuit 19 is assured of receiving the last remainder stored in the latch S circuit 18 prior to the next interval during which the next 3-bit signal is applied to the adder 17. 
     Accordingly, the instant invention is particularly characterized by circuitry that permits the day of the week to be automatically displayed with the entire calculation being reliably effected in as little as one-thirty-second of a second. Moreover, although the circuitry, described in detail herein, and the manner in which same effects summing of the bit signals can take other forms, the division by seven to obtain the remainder signal is required in order to obtain a day of the week remainder signal that assures a proper display of such information. A further and considerable benefit of the instant invention is that it permits a person wearing an electronic wristwatch having such day of the week selection circuitry to set the day, month and year calendar display either forward or backward to a particular date and thereby ascertain what day of the week that date occurred on. 
     It will thus be seen that the objects set forth above, among those made apparent from the preceding description, are efficiently attained and, since certain changes may be made in the above construction without departing from the spirit and scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense. 
     It is also to be understood that the following claims are intended to cover all of the generic and specific features of the invention herein described and all statements of the scope of the invention which, as a matter of language, might be said to fall therebetween.