Complementary MOSFET device
This is a continuation, of application Ser. No. 706,125, filed July 16, 1976, now abandoned. 
    
    
     This invention relates to a complementary MOSFET (hereinafter called CMOS) device in which an operation of parasitic bipolar transistors is suppressed. 
     Hitherto various circuits constituted by CMOS&#39;s have been known. A typical example is a CMOS inverter circuit. As well known, a CMOS inverter circuit is constituted by a p-channel MOS transistor and an n-channel MOS transistor. The threshold voltage of one of these MOS transistors has the opposite characteristics to that of the other MOS transistor. For this reason, generally only one of the two MOS transistors is switched on in response to input information. Thus no current flows between the power source of the CMOS inverter circuit, except during the transient period of the input information pulse. Thus, almost no operation power needs to be consumed, except that during the transient period of the pulse, both MOS transistors are switched on but for a moment, thereby causing only a transient current for a moment, that a leak current occurs at the PN junction, and that a current flows due to the charge or discharge of a storage capacitor at the output terminal of the CMOS inverter circuit. 
     However, when noise is applied impulsively to the output or input of such a CMOS circuit system, an abnormally large DC current of tens of mA to hundreds of mA flows between the positive and negative power sources of the CMOS circuit. Even after removing the noise, such abnormal current is observed to keep flowing regularly. This regular flow of the abnormally large current sometimes causes the CMOS circuit connection to be melt and thus cut. The impulse corresponding to the noise has both polarities, positive and negative, and serves to generate an abnormal current. To remove this abnormal current it is necessary either to lower the power source voltage below a specific value or to disconnect the CMOS circuit system from the power source. 
     Accordingly, an object of the invention is to provide a CMOS device in which an abnormally large current is prevented from being generated by impulse noise and thus from flowing. 
     Another object of the invention is to provide a CMOS device in which the circuit connection is never melted nor cut even if impulse noise is applied. 
     Still another object of the invention is to provide a CMOS device which can keep operating with a low power consumption even if an impulse noise signal is applied. 
     A further object of the invention is to provide a CMOS device in which an abnormally large current is prevented from being generated by impulse noise even if the product of a current amplification factor of two parasitic bipolar transistors is more than 1. 
     The present invention provides a CMOS device comprising a semiconductor substrate of one conductivity type, a well layer of the opposite conductivity type formed in the substrate, a MOS transistor of one channel type formed in the substrate and another MOS transistor of the opposite channel type formed in the well layer wherein there is formed at least one parasitic bipolar transistor whose base is formed by the substrate or well layer and the operation of the parasitic transistor is suppressed. By controlling a distance from the edge of at least one contact hole on the surface of a contact region formed in the substrate or well layer to the boundary edge between the substrate and the well layer, the operation of the parasitic transistor formed in the substrate or well layer is suppressed, even if a product of a current amplification factor of a first parasitic transistor whose base is formed of the substrate and a second current amplification factor of a second parasitic transistor whose base is formed of the well layer is more than 1. 
    
    
     This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a circuit diagram of an inverter constituted by CMOS&#39;s; 
     FIG. 2 is a cross-sectional side view of one embodiment of the semiconductor device to explain the present invention; 
     FIG. 3 shows an equivalent circuit diagram to a thyristor circuit in the form of a CMOS circuit semiconductor device; 
     FIG. 4 is a diagram indicating the dependence of the current amplification factor of a lateral transistor having an N substrate as its base on the base width thereof; 
     FIG. 5 is a diagram indicating the dependence of the current amplification factor of a vertical transistor having a P well layer as its base on the base width thereof; 
     FIG. 6 is a diagram showing the dependence of the region where a latch up occurs on the base widths of both a parasitic lateral transistor and a parasitic vertical transistor and the location of a contact hole; 
     FIG. 7 is a plan view showing a pattern layout of the semiconductor device according to the present invention to show a location of a contact hole; 
     FIG. 8 is a diagram showing the relationship between a location of a contact hole and a minimum source voltage and input signal voltage to produce an abnormal current; 
     FIG. 9 is a diagram showing the relationship between a base width of a lateral transistor having an N substrate as its base and a minimum source voltage and input signal voltage to produce an abnormal current; and 
     FIGS. 10 to 25 are plan views showing various pattern layouts of the semiconductor device of this invention. 
    
    
     The invention shall now be explained in detail with reference to the accompanying drawings. 
     The CMOS inverter circuit illustrated in FIG. 1 is comprised of a p-channel MOS transistor Q 1  and n-channel MOS transistor Q 2 . The source electrode of the MOS transistor Q 1  is connected to the positive power source V DD , while the drain electrode thereof is connected to the output terminal, jointly with the drain electrode of the MOS transistor Q 2 . The source electrode of the MOS transistor Q 2  is connected to the negative power source V SS . The gate electrodes of the MOS transistors Q 1  and Q 2  are coupled to each other so as to form the input terminal of the CMOS inverter circuit. 
     FIG. 2 shows one embodiment of the semiconductor device according to the invention, wherein the CMOS inverter circuit shown in FIG. 1 is formed in a semiconductor wafer. The substrate 1 of the embodiment is an N type silicon substrate with an N type impurity, for example phosphorus, doped in concentration of about 1 × 10 15  atoms/cm 3 . From the surface of the N type silicon substrate 1 a P type impurity, for example boron, is diffused into a portion of the substrate 1 in concentration of about 2 × 10 16  atoms/cm 3 , thereby forming a P well layer 2. Further, boron is diffused into the N type substrate 1, the P well layer 2 and the junction edges between the N type substrate 1 and the P well layer 2, in concentration of about 10 19  atoms/cm 3 , thereby simultaneously forming in the N type substrate 1 a P +  type source region 3 and a P +  type drain region 4 which constitute a p-channel MOS transistor Q 1 , a P +  type conductive coupling region 6 in the P well layer, and P +  type guard rings 5 in the junction edges between N type substrate 1 and the P well layer 2. Thereafter, phosphorus is diffused into the P well layer 2 and the N type substrate 1 in concentration of about 10 20  atoms/cm 3 , thereby forming simultaneously an N +  type source region 7 and an N +  type drain region 8 which constitute an n-channel MOS transistor Q 2  in the P well layer 2 and an N +  type conductive coupling region 9 in the N type substrate 1. This done, the field silicon oxide 10 is formed on the entire surface of the substrate 1. 
     Thereafter, in order to form gate regions of the MOS transistors Q 1  and Q 2 , photo-etching is conducted on the substrate 1, thereby making holes in the field oxide film 10. At the bottoms of these holes gate oxide films 11 and 12 having a thickness of 1500A are formed by oxidizing the holes at a high temperature. Then in order to effect such a circuit connection as shown in FIG. 1, contact holes of predetermined sizes are bored in the silicon oxide film 10, and a conductive film of, for example, aluminum is deposited all over the surface of the substrate 1. The conductive film is then cut in a specific pattern so as to connect the P +  type drain region 4 and the N +  type drain region 8 to each other and connect the gate regions (or oxide films) 11 and 12 to each other. Thus, the drain regions 4 and 8 form an output terminal, and the gate regions 11 and 12 an input terminal. At the same time the p +  type conductive coupling region 6 and the N +  type conductive coupling region 9 are connected to the negative power source V SS  (ground) and the positive power source V DD , respectively. Further, if necessary, a silicon oxide film may be laid by chemical epitaxial growth on the entire surface, except for desired portions, of the aluminum conductive film so as to protect the aluminum conductive film and enhance the reliability of the semiconductor device. Though not shown in FIG. 2, a stopper may be disposed between the MOS transistor Q 1  and Q 2 . 
     When noise is applied impulsively to the output or input of the semiconductor device which is so constituted as mentioned above and which serves as a CMOS inverter circuit, an abnormal current of 10 mA to 100 mA does flow. The inventors of the present invention have closely observed and studied this phenomenon. Finally the inventors have found out that when an impulse noise current is applied to the semiconductor device, a specific thyristor circuit is formed in the semiconductor device, as depicted by dotted lines in FIG. 2. Namely, four kinds of parasitic bipolar transistors are formed in the semiconductor substrate 1. More specifically, a PNP lateral transistor Tr 1 , whose emitter, base and collector are the source region 3 of the p-channel MOS transistor Q 1 , the N type semiconductor substrate 1 and the P well layer 2, respectively, is formed in the direction parallel to the surface of the substrate 1. An NPN vertical transistor Tr 2 , whose emitter, base and collector are the N +  type source region 7 of the n-channel MOS transistor Q 2 , the P well layer 2 and the N type semiconductor substrate 1, respectively, is formed in the direction perpendicular to the surface of the substrate 1. Similarly, a PNP lateral transistor Tr 3 , whose emitter, base and collector are the P +  type drain region 4 of the p-channel MOS transistor Q 1 , the N type semiconductor substrate 1 and the P well layer 2, respectively, is formed in the direction parallel to the surface of the substrate 1. And an NPN vertical transistor Tr 4 , whose emitter, base and collector are the N +  type drain region 8 of the n-channel MOS transistor Q 2 , the P well layer 2 and the N type semiconductor substrate 1, respectively, is formed in the direction perpendicular to the surface of the substrate 1. 
     In the semiconductor device shown in FIG. 2 the collectors of the lateral transistors Tr 1  and Tr 3  and the bases of the vertical transistors Tr 2  and Tr 4  are constituted commonly by the P well layer 2. Thus, they are connected to one another and to the negative power source V SS  (that is, grounded) through a resistance R Pwell  and the P +  type conductive coupling region 6 both formed in the P well layer 2. On the other hand, the bases of the lateral transistors Tr 1  and Tr 3  and the collectors of the vertical transistors Tr 2  and Tr 4  are constituted commonly by the semiconductor substrate 1. They are therefore connected together and to the positive power source V DD  through a resistance R Nsub  and the N +  type conductive coupling region 9 both formed in the semiconductor substrate 1. Further, the emitters of the transistors Tr 3  and Tr 4  are connected to the output terminal OUTPUT, and the emitters of the transistors Tr 1  and Tr 2  are connected to the positive power source V DD  and the negative power source V SS , respectively. 
     The connection of the lateral and vertical transistors being as such, the thyristor circuit formed in the CMOS circuit device of FIG. 2 and indicated in dotted lines in FIG. 2 can be expressed as such an equivalent circuit as illustrated in FIG. 3. With reference to FIG. 3, it shall be explained how the thyristor formed in the CMOS circuit device shown in FIG. 2 operates. In the following explanation, &#34;α&#34; denotes a current amplification factor which is a bipolar transistor term generally employed to mean the ratio of collector current to the emitter current, &#34;β&#34; a current amplification factor, i.e. the ratio of the collector current to the base current (β=(α/1-α), and &#34;I&#34; current. Similarly, &#34;e&#34;, and &#34;b&#34; and &#34;c&#34; stand for emitter, base and collector, respectively, and employed as suffix signs. Further, suffix numerals are used thereby to denote the transistors indicated by the corresponding numerals. In addition &#34;r&#34; is employed to denote the internal resistance of each transistor. 
     In FIG. 3, when a positive impulse noise current I in  is applied to the output terminal as shown by the solid arrow, current of α 3  × I in  flows in the collector of the transistor Tr 3 . The current of α 3  × I in  then flows through the resistance R P  well of the P well layer 2, which serves as a by-pass. When the voltage across the resistance becomes over the threshold voltage V be2  between the base and emitter of the transistor Tr 2 , the transistor Tr 2  is rendered conductive, and base current I b2  flows through its base. The resistance R P  well in the P well layer is far greater than the internal resistance rbe2 between the base and emitter of the transistor Tr 2 . For this reason, the collector current α 3  × I in  of the transistor Tr 3  hardly flows through the resistance R P  well. Consequently, the base current I b2  of the transistor Tr 2  is almost equal to the collector current α 3  × I in  of the transistor Tr 3 . Namely, 
     
         I.sub.b2 ≈ α.sub.3 I.sub.in (R.sub.Pwell &gt;&gt; rbe2) . . . . . (1) 
    
     
         I.sub.c2 = α.sub.2 I.sub.b2 = β.sub.2 a.sub.3 I.sub.in . . . . . (2) 
    
     Similarly, when the collector current I c2  of the transistor Tr 2  acts as drive current and the voltage at both terminals of the resistance R Nsub  of the substrate rises to the threshold voltageV bel  between the base and emitter of the transistor Tr 1 , the transistor Tr 1  is rendered conductive. Thus a base current I bl  flows through the base of the transistor Tr 1 . The base current I bl  is nearly equal to the collector current I c2  of the transistor Tr 2  since the resistance of the R Nsub  is extremely greater than the internal resistance rbel between the base and emitter of the transistor Tr 1 . That is, 
     
         I.sub.bl ≈ I.sub.c2 (R.sub.Nsub &gt;&gt; rbel) . . . . . (3) 
    
     
         I.sub.cl = β.sub.1 I.sub.bl = β.sub.1 I.sub.c2 = β.sub.1 β.sub.2 α.sub.3 I.sub.in . . . . .             (4) 
    
     When the MOS transistors Tr 1  and Tr 2  are made conductive, current flows between the positive power source V DD  and the ground through these transistors Tr 1  and Tr 2 . In other words, when an impulse noise is applied to the CMOS inverter circuit, an abnormal current flows between the positive power source V DD  and the ground through the semiconductor substrate 1 and the P well layer 2. 
     To keep a current flow between the positive power source V DD  and the ground even after the noise application is stopped, it is required that the loop circuit constituted by the transistors Tr 1  and Tr 2  should perform a positive feedback operation. This is achieved only if the base current I b2  of the transistor Tr 2  which is rendered conductive first when the impulse noise is applied is made equal to or smaller than the collector current I cl  of the transistor Tr 1  which is rendered conductive after the transistor Tr 2 . That is, 
     
         I.sub.b2 ≦ I.sub.cl . . . . .                       (5) 
    
     Namely, 
     
         I.sub.b2 = α.sub.3 I.sub.in ≦ β.sub.1 β.sub.2 α.sub.3 I.sub.in. 
    
     Therefore, 
     
         1 ≦ β.sub.1 β.sub.2 . . . . .             (6) 
    
     From formula (6) it is understood that when the product of the current amplification factors β 1  and β 2  of the transistors Tr 1  and Tr 2  is equal to or larger than 1, an abnormal current keeps flowing between the positive power source V DD  and the ground of the CMOS inverter circuit. 
     So long as the product of β 1  and β 2  is larger than 1, in the loop circuit including the transistors Tr 1  and Tr 2  the base current I b2  in a specific cyclic period becomes greater than the base current I b2  in the preceding cyclic period. Thus, the more times the current flows cyclically in the loop circuit, the greater the current between the power source V DD  and the ground becomes. But the current does not increase indefinitely. The current amplification factor β of a transistor is a function to current, and its value increases with the current. However, it starts growing smaller one when it has reached a maximum value, β max. For this reason, the abnormal current flowing between the positive power source V DD  and the ground of the CMOS inverter circuit is eventually maintained at a specific value, i.e. point of balance between the current increase effected by the loop circuit and the current decrease achieved by the reduction of current amplification factor. Namely, usually the abnormal current comes to have such a value as is defined when the following two conditions are satisfied at the same time: 
     
         a. I.sub.b2 (n-1) = I.sub.b2 (n) 
    
     
         b. β.sub.1 (n).β.sub.2 (n) ≧ 1, 
    
     wherein &#34;n&#34; denotes the number of cyclic periods during which the abnormal current flows in the loop circuit. 
     The size of a transistor does not make a primary factor of the possibility of an abnormal current flow. But when the current amplification factor β of the transistor was measured with the size of the transistor (strictly speaking, the drain area) as parameter, it was ascertained that there existed an interrelationship between the size of the transistor and the current value at which the abnormal current was finally maintained. This fact indicates that the larger is the drain area of a transistor, the greater is the abnormal current. 
     When a negative impulse noise is applied to the output of the CMOS inverter circuit as shown in FIG. 3, such current as indicated by the dotted-line arrow flows between the positive power source V DD  and the output terminal OUTPUT, and the following formulas are established similarly as in case a positive impulse noise is applied to the output terminal: 
     
         I.sub.b1 ≈ α.sub.4 I.sub.in (R.sub.Nsub ≧ rel) . . . . .                                                         (7) 
    
     
         I.sub.c1 = β.sub.1 I.sub.b1 = β.sub.1 α.sub.4 I.sub.in 
    
     
         I.sub.b2 = I.sub.c1 (R.sub.Pwell &gt;&gt; rbe2) and 
    
     
         I.sub.c2 = β.sub.2 I.sub.b2 = β.sub.2 β.sub.1 I.sub.b1 = β.sub.1 β.sub.2 α.sub.4 I.sub.in 
    
     To maintain current in the circuit constituted by the transistors Tr 1  and Tr 2  it is required that the collector current I c2  of the transistor Tr 2  which is rendered conductive after the transistor Tr 1  should be greater than the base current I b1  of the transistor Tr 1 . That is, 
     
         I.sub.b1 &gt; I.sub.c2 . . . . .                              (8) 
    
     In order to maintain an abnormal current in the CMOS inverter circuit in case a negative noise is applied thereto, it is required as in case a positive noise is applied that the following formula be established: 
     
         1 &gt; β.sub.1 β.sub.2 . . . . .                    (6) 
    
     Thus it is ascertained that to avoid generation of an abnormal current and perpetual flow of the same in such a thyristor circuit as illustrated in FIGS. 2 and 3 it is sufficient to keep smaller than 1 the products of the current application factors β 1  and β 2  of the transistors Tr 1  and Tr 2 . To generalize it, in order to prevent generation of an abnormal current and a perpetual flow thereof in a CMOS inverter due to the operation of a thyristor circuit, it is sufficient to hold less than 1 the product of the current amplification factors β of a lateral transistor formed substantially in parallel to the surface of the semiconductor substrate and a vertical transistor formed perpendicular to the surface of the semiconductor substrate. 
     The inventors of the present invention have found that to satisfy this requirement in practice, the following measures are effective: 
     (1) To increase the base width of one or both of the lateral and vertical transistors. 
     (2) To conduct a heat treatment on the semiconductor substrate during the manufacture process, thereby to shorten the life time of the carrier in the substrate. 
     (3) To shorten the life time of the carrier in the semiconductor wafer of which the substrate is formed. 
     (4) To dope the semiconductor substrate with gold. 
     Four embodiments (1) to (4) of the invention shall be explained, in which the above-noted measures (1) to (4) are taken, respectively. 
     Embodiment (1) 
     In the diagram of FIG. 4, plotted on the axis of ordinate is the current amplification factor β 1  of the lateral transistor T M . In logarithmic notation, and plotted on the axis of abscissa is the base width W l  (μ) of the lateral transistor Tr 1 , i.e. the distance between the edge of the P well layer 2 and the edge of the source region 3 of the p-channel MOS transistor Q 1  formed in the portion of the semiconductor substrate 1 other than the P well layer 2. The diagram shows that as the base width W l  increases, the current amplification factor β 1  becomes smaller. The length of each vertical line in FIG. 4 indicates the range within which the current amplification factor β 1  varies according to individual wafers and the position within the same wafer when the factor is measured, though the base width W l  is one and the same. 
     In the diagram of FIG. 5, plotted on the axis of ordinate is the current amplification factor β 2  of the vertical transistor Tr 2  in logarithmic notation, and plotted on the axis of abscissa is the base width W v  (μ) of the vertical transistor Tr 2 , i.e. the thickness of the P well layer 2 minus the thickness of the source region 7 of the n-channel MOS transistor Q 2  formed in the P well layer 2. This diagram teaches that as the base width W v  increases, the current amplification factor β 2  becomes smaller. In FIG. 5 the length of each vertical line indicates the range within which the current amplification factor β 2  varies according to individual wafers and the position within the same wafer where the factor is measured, though the base width W v  is the same. The length of vertical lines further indicate the variation of the current amplification factor β 2  when the doping amount of impurities is so regulated that the impurity concentration may become the same in case the slumping time, i.e. the period during which the wafer undergoes a heat treatment, varies as 20 hours, 40 hours and 60 hours, respectively, thereby causing a change of the base width W.sub. v of the vertical transistor Tr 2 . Since the base width W v  of the vertical transistor Tr 2  much depends on the thickness of the P well layer 2, it is influenced by the variation of the slumping time. 
     The relationship between the base width and the current amplification factor of the lateral or vertical transistor differs since the current amplification factors β 1  and β 2  varies according to the process of manufacturing the semiconductor device. For this reason, the straight lines A and B which show the relationship obtained from different experiments A and B using different semiconductor devices incline at different angles as shown in FIGS. 4 and 5. In FIG. 5, no other current amplification factor of the vertical transistor Tr 2  than indicated by the line B could be measured. 
     In the diagram of FIG. 6, plotted on the axis of abscissa is the base width W v  of the vertical transistor Tr 2 , and plotted on the axis of ordinate is the base width W l  of the lateral transistor Tr 1 . In this embodiment, the P well layer was formed by diffusing, for example, boron into the semiconductor substrate. Its thickness was 12.5μ when the wafer slumping was conducted for 60 hours at 1200° C., 10.2μ when the wafer-slumping was conducted for 40 hours at the same temperature, and 7.2μ when the wafer-slumping was conducted for 20 hours at the same temperature. The product of the current amplification factors β 1  and β 2  was 8.1 in a CMOS inverter circuit wherein the base widths W l  and W v  of the lateral and vertical transistors Tr 1  and Tr 2  were of such values as denoted at point (a) in FIG. 6. It was 4.8 and 1.0 in a CMOS inverter circuit in which the base widths W l  and W v  were of such values as denoted at points (b) and (c) and in a CMOS inverter circuit in which the base widths W l  and W v  were valued at points (d), (e) and (f), respectively. Any CMOS inverter circuit, wherein the base widths W l  and W v  have such values as denoted at a point located above the straight line on which points (d), (e) and (f) are aligned, had the product β 1  and β 2  smaller than 1. Thus no abnormal large current was observed to flow in such CMOS inverter circuit. By contrast, an abnormal current was observed to flow in the CMOS inverter circuits in which the base widths W l  and W v  of the lateral and vertical transistors Tr 1  and Tr 2  were at a point below said straight boundary line in FIG. 6. That is, the so-called &#34;latch up&#34;  phenomenon was seen in these CMOS inverter circuits. 
     Further based on the above-mentioned consideration, the present inventors have discovered that occurrence and sustenance of abnormal current can be suppressed even when product of the current amplification factors β 1 , β 2  is larger than 1, namely, when the base widths W l , W v  of the bipolar transistors are so narrow as to lie below a solid line of FIG. 6 denoting β 1  β 2  = 1. In other words, the present inventors have found that occurrence or nonoccurrence of abnormal current depends on the area and position of a contact hole formed in the surface of a contact region to connect the semiconductor substrate and well layer to a power source. 
     With the CMOS inverter circuit of FIG. 2, a power source V DD  is connected to an N type semiconductor substrate 1 at the same potential through an N +  contact region 9. A power source V SS  (GND) is connected to a P well region 2 at the same potential through a P +  contact region 6. The N +  and P +  contact regions 9, 6 are required for an ohmic contact between the power sources V DD , V SS  and the substrate, P well layer respectively. 
     Where the CMOS circuit is supplied with a trigger signal by an external noise, current never fails to flow across the power sources V DD , V SS  through the N type substrate 1 and P well layer 2 before a parasitic bipolar transistor constituting part of a thyristor circuit of FIG. 3 is operated in the N type substrate 1 or P well layer 2. Only where a potential difference defined by the product of the current and the resistance of the N type semiconductor substrate 1 or P well layer 2 that is, a level of voltage impressed across the base and emitter of a bipolar transistor reaches a sufficiently high level for operation of the bipolar transistor, i.e. a threshold voltage level between the base and emitter of the bipolar transistor, then the parasitic bipolar transistor whose base is formed of the N type semiconductor substrate 1 or P well layer 2 is put into operation to form a thyristor circuit connection shown in FIG. 3. Even if a noise signal is supplied to the CMOS circuit and unless voltage defined by the product arrived at by multiplying the current passing across the power sources V DD , V SS  by the resistance R Nsub  of the N type semiconductor substrate 1 or the resistance R Pwell  of the P well layer 2 reaches the level of the threshold voltage across the base and emitter of the bipolar transistor, the bipolar transistor is not actuated and thus the thyristor circuit is not operated, resulting in that abnormal current is little likely to arise in a sustained state, though some amount of current may momentarily flow through the CMOS circuit. Where, therefore, an amount of current initially flowing between the power sources V DD , V SS  upon the supply of a noise impulse signal is supposed to be constant, then it is necessary to decrease the resistance R Nsub  of the N substrate or R Pwell  of the P well in order to reduce a potential difference between both terminals of said resistance R Nsub  or R Pwell  itself to a lower level than that of the threshold voltage across the base and emitter of the bipolar transistor, thereby suppressing the sustained flow of abnormal current. 
     The resistance R Nsub  and R Pwell  has a maximum value over a path extending from the contact holes formed in the surface of the N +  contact region 9 and P +  contact region 6 to the boundary edge between the P well layer 2 and the N type substrate 1. To minimize the resistance R Nsub , R Pwell , therefore, it is advised to shorten, as prescribed, a distance from the edge of the contact hole of the N +  contact region 9 to the P well layer 2 and a distance from the edge of the contact hole of the P +  contact region 6 to the N type semiconductor substrate 1 or either of said two distances. To suppress the sustained flow of abnormal current, it is desired to shorten a distance between the edge of the contact hole of the N +  contact region 9 and/or P +  contact region 6 and the boundary edge between the P well layer 2 and the N type semiconductor substrate 1 in order to decrease the voltage occurring across the resistance R Nsub  or R Pwell , namely, the voltage applied across the base and emitter of the parasitic bipolar transistor whose base is constituted by the P well  layer 2 or N type semiconductor substrate 1 to a lower level than that of the threshold voltage across the base and emitter of the bipolar transistor. 
     FIG. 7 presents the pattern layout of a CMOS circuit. The portions of said circuit corresponding to the respective regions of the semiconductor substrate of FIG. 2 are denoted by the same numerals as those of FIG. 2, description thereof being omitted. 
     The locations and areas of contact holes A, B, C, D, E are shown in FIG. 7 and Table 1 below. 
     
                                           Table 1                                 
__________________________________________________________________________
                  How contact hole is                                     
Location          spaced from semicon-                                    
                                    Contact                               
of contact                                                                
      Extension of                                                        
                  ductor substrate or                                     
                                    resistance                            
hole  contact hole                                                        
                  well layer  Area  (Ω)                             
__________________________________________________________________________
A     Center of one                                                       
                  Remotest      64 μ.sup.2                             
                                    58                                    
      crosswise edge                                                      
      Extending fully                                                     
      along said one cross-                                               
      wise edge up to two                                                 
B     side edges disposed                                                 
                  Remote       2,700 μ.sup.2                           
                                    &lt;5                                    
      at right angles to                                                  
      said one crosswise                                                  
      edge                                                                
      Extending fully along                                               
      said one crosswise                                                  
      edge and halfway of                                                 
C     each of said two side                                               
                  Slightly near                                           
                               6,787 μ.sup.2                           
                                    &lt;5                                    
      edges disposed at                                                   
      right angles to said                                                
      one crosswise edge                                                  
      Extending fully along                                               
      said one crosswise                                                  
      edge and three quar-                                                
      ters of the total                                                   
D     length of said two                                                  
                  Near         9,440 μ.sup.2                           
                                    &lt;5                                    
      side edges disposed                                                 
      at right angles to                                                  
      said one crosswise                                                  
      edge                                                                
      Extending fully along                                               
      said one crosswise                                                  
      edge and substantial-                                               
      ly the whole length                                                 
E     of said two side                                                    
                  Nearest      10,000 μ.sup.2                          
                                    &lt;5                                    
      edges disposed at                                                   
      right angles to said                                                
      one crosswise edge                                                  
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     As seen from FIG. 7 and Table 1 above, the contact holes A to E formed on one of the MOS transistors Q 1 , Q 2  progressively approach the N type semiconductor substrate 1 or P well layer 2 which constitutes the other of the MOS transistors Q 1  and Q 2  in the order of A to E with the resultant decrease in the resistivity of the resistance R Nsub , R Pwell . Further, since the contact holes A to E are successively increased in area in the order mentioned, the contact resistances of said holes A to E become smaller similarly in succession. Therefore, abnormal current arises with greater difficulty, as expected, in the order of the contact holes A to E. The results of experiments carried out in this connection are set forth in FIG. 8. In FIG. 8, the positions of the contact holes are shown on the abscissa, and input signal voltage and minimum levels V DD  MIN of power source voltage to produce abnormal current are plotted on the ordinate. Where an abnormal input signal having a maximum amount of current of 500 mA was applied to the CMOS circuit as the result of an external noise, it was proved that said abnormal current occurred with progressively greater difficulty in the order of the contact holes A to E. It was further disposed that a minimum level V DD  MIN power source voltage causing the generation of abnormal current depended on the manner in which the contact holes were formed, and progressively increased in the order in which a value obtained by adding the resistance R Nsub , R Pwell  to a contact resistance successively became smaller, that is, in the order of the contact holes A to E. It was also found that where, with the product of the current amplification factors β 1 , β 2  of both transistors taken to be ≧1, it was tried to decrease the current amplification factor β 2  of the vertical transistor Tr 2  by providing a P well layer with a layer depth x j  in forming the contact holes A, B, C, it was still impossible to suppress abnormal current, but that where the contact holes were formed in the same manner as in the case of the contact holes D, E, the formation of the P well with a greater depth was effective to eliminate the occurrence of abnormal current. A solid line, one dot-chain line and two dots-chain line of FIG. 8, as in FIG. 5, respectively denote slumping times of 20 hr, 40 hr and 60 hr used in manufacturing a semiconductor wafer. It is seen from FIG. 8 that with the contact holes A, B, C formed as described in connection with FIG. 7, abnormal current appeared regardless of the slumping time, when the product of the current amplification factors β 1 , β 2  of the bipolar transistors was indicated ≧1; with the contact hole D, abnormal current arose in a semiconductor device prepared by slumping of 20 hr, when the base width W l  of a lateral transistor Tr 1  was chosen to be 50 microns and no abnormal current took place in a semiconductor device manufactured by slumping of 60 hr. 
     Referring to FIG. 9, the base width of a lateral transistor Tr 1  is shown on the abscissa, and an amount of input signal current and a minimum level V DD  MIN of power source voltage to produce abnormal current are plotted on the ordinate. 
     FIG. 9 shows the occurrence or nonoccurrence abnormal current in the contact hole D with the base width of a lateral transistor Tr 1  varied. With the base width W l  of the lateral transistor taken to be 70 microns, no abnormal current occurs, whereas, in case of W l  of 30 microns, abnormal current actually arises. With W l  taken to be 50 microns, abnormal current is or is not produced according to the kind of semiconductor wafer itself or length of slumping time. With the contact hole D, therefore, a critical condition for the emergence of abnormal current is supposed to be that the base width W l  of the lateral transistor is 50 microns. FIG. 9 shows that with W l  taken to be 50 microns, and slumping time to be 20 hr or the depth x j  of the P well layer to be 8 microns, abnormal current is or is not generated according to the kind of semiconductor wafer. Therefore, slumping time of 20 hr is considered necessary. The base of a vertical transistor Tr 2  has a width W v  of 5.24 microns in the case of 20 hr-slumping. With W l  taken to be 50 microns and W v  to be 5.24 microns, a product of current amplification factors β 1 , β 2  determined from FIGS. 4 and 5 is expressed as 2.0 × 10 2  × 2.4 × 10 -  2 = 4.8. Therefore, it is seen in FIG. 6 that with the contact hole D, a boundary region determining the occurrence or no occurrence of abnormal current lies at a point at which a product of the current amplification factors β 1 , β 2  of the bipolar transistors indicates 4.8. This means that with the contact hole D, abnormal current can be suppressed even in the region where the product of β 1 , β 2  is larger than 1. 
     Further experiments show that with the contact hole E, a region where a product of the amplification factors β 1 , β 2  of the bipolar transistors indicates 8.1 as shown in FIG. 6 constitutes a boundary determining the presence or absence of abnormal current. When formation of a contact hole proceeds from D to E, a distance between the contact hole and the semiconductor substrate or well layer is more shortened, with the resultant increase in the area of that portion of the W l , W v  where no abnormal current is generated, thereby enabling a CMOS semiconductor device presenting a larger product of amplification factors to be saved from abnormal current. Namely, depending on the manner in which a contact hole is formed, it is possible to prevent the occurrence of abnormal current even in the case where a product of the amplification factors β 1 , β 2  of the bipolar transistors is larger than 1. 
     The following experimental formula has been obtained to express the relationship between a current amplification factor and the base width of the parasitic transistor: 
     Current amplification factor β = Kexp (-aW) . . . . (10) where: 
     K, a = coefficients 
     W = base width of a parasitic bipolar transistor 
     Further, the present inventors have adopted a parameter δ associated with the manner in which a contact hole is formed, thereby experimentally establishing the following formula showing the relationship between the base width W l  of a lateral transistor Tr 1  and the base width W v  of a vertical transistor Tr 2  which cooperate to suppress abnormal current. ##EQU1## Where: K l , K v  = values of a coefficient K of the formula (10) in the lateral and vertical transistors Tr 1  and Tr 2   
     m, n = values of a coefficient a of the formula (10) in the lateral and vertical transistors Tr 1  and Tr 2   
     There will now be described the above-mentioned formula (11) by reference to FIG. 6. The base width W l  of the lateral transistor Tr 1  is plotted on the ordinate, and the base width W v  of the vertical transistor Tr 2  is shown on the abscissa. The formula 11 denotes a region lying above a straight line whose contact with the ordinate (not shown in FIG. 6) is expressed as ##EQU2## Change of the location of a contact hole or the manner in which a contact hole is formed leads to variation of δ. Where, therefore, formation of a contact hole is shifted from A to E, then the line of the formula 11 denoting the boundary region of the occurrence of abnormal current is shifted downward in parallel with a line representing a product of the current amplification factors β 1 , β 2  = 1 to enlarge a region lying above a line satisfying the formula 11, namely, a region enabling the lateral and vertical transistors to have a base width adapted to suppress abnormal current. 
     Where, therefore, a contact hole is so formed as to satisfy δ given in the above-mentioned formula 11, then the operation of a parasitic bipolar transistor in which a product of current amplification factors is larger than 1 can be so controlled as to suppress abnormal current. Further, even when a product of the current amplification factor β 1  of the lateral transistor Tr 1  and the vertical transistor Tr 2  is larger than 1, the operation of the lateral and vertical transistors Tr 1 , Tr 2  can be suppressed by causing either or both of the P +  source region of a P channel type MOS transistor and the N +  source region of an N channel type MOS transistor to have the same potential as the N type semiconductor substrate and P well layer. 
     As mentioned above, abnormal current can be suppressed by defining a distance from the edge of a contact hole being formed in the N +  contact region of the P channel MOS transistor to the collector of the lateral transistor Tr 1  or P well layer, and a distance from the P +  contact region of the N channel MOS transistor to the collector of the vertical transistor Tr 2  or the N type semiconductor substrate or either of said distances so as to cause a potential difference occurring at both terminals of the resistance R Nsub  and resistance R Pwell  respectively to fall below the level of threshold voltage across the base and emitter of the lateral transistors Tr 1 , Tr 3  and also the level of threshold voltage across the base and emitter of the vertical transistors Tr 2 , Tr 4 . In this case, the threshold voltage is chosen to be about 0.5 volt. 
     FIGS. 10 to 25 set forth the concrete patterns of the CMOS circuit, showing the positions and areas of contact holes formed is the P channel MOS transistor and N channel transistor. Regions enclosed by dotted lines denote contact holes. The parts of FIGS. 10 to 25 corresponding to those of FIGS. 2 and 7 are denoted by the same numerals, description thereof being omitted. 
     This invention is applicable not only to a CMOS inverter circuit but also various forms of CMOS circuit in which a thyristor circuit is formed. The CMOS circuit may obviously be formed by forming an N well layer in a P type semiconductor substrate.