Digital correlator
REFERENCE TO CO-PENDING APPLICATION 
     Reference is hereby made to a co-pending application by Norman L. Stauffer entitled &#34;Digital Auto-Focus&#34;, Ser. No. 696,170 filed June 14, 1976 now U.S. Pat. No. 4,078,171 and assigned to the same assignee as the present application. The digital correlator of the present invention is disclosed but not claimed in this co-pending application. 
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to digital circuitry. In particular, the present invention is a digital correlator which performs digital correlation on two digital words. 
     Digital correlators have found application in a variety of different digital systems. Examples of prior art digital correlators are shown in U.S. Pat. Nos. 3,646,333 by Pryor, Jr.; 3,670,151 by Lindsay et al; 3,717,756 by Stitt; 3,725,689 by Kautz; 3,881,101 by Pederson et al; and 3,942,022 by Stumpf et al. 
     One application which requires a digital correlator is the digital auto-focus system described in the above-mentioned co-pending application by Norman L. Stauffer. In this auto-focus system, two digital words of equal length are produced by two detector arrays. Signal processing circuitry, including a digital correlator, determines the number of bits by which the second word is displaced with respect to the first word. This number may be used to position the taking lens of a camera. 
     For purposes of the system described in the Stauffer application, the digital correlator must be relatively simple and low-cost and use a small number of components. The digital correlator cannot be a high cost item, since this would adversely affect the overall cost of the camera into which it will be incorporated. 
     SUMMARY OF THE INVENTION 
     The digital correlator of the present inventions correlates first and second digital words and determines the number of bits by which the second word is displaced with respect to the first word. The digital correlator includes comparing means, storing means, control means, and search means. 
     The comparing means provides a plurality of comparison cycles. During each comparison cycle, the individual bits of the first and second digital words are compared. The results of each comparison cycle are stored in a different location in the storing means. 
     The control means shift the bits of the second digital word with respect to the first digital word so that the second digital word is displaced by a different number of bits with respect to the first digital word during each comparison cycle. 
     After the comparison cycles have been completed, the search means searches the stored results to find the location of the results indicating the greatest similarity between the bits of the first and second digital word. This location is indicative of the number of bits by which the second digital word is displaced with respect to the first digital word when the greatest similarity between bits occurs. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a preferred embodiment of the digital correlator of the present invention. 
     FIG. 2 shows an alternative embodiment of the comparing means used in the digital correlator of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In FIG. 1, the digital correlator of the present invention repeatedly compares first digital word &#34;A&#34; and second digital word &#34;B&#34; and produces an output signal which is indicative of the number &#34;n&#34;, which is the number of bits by which the second digital word B is displaced with respect to first digital word A. In the particular embodiment shown in FIG. 1, the digital correlator performs digital correlation between two words of equal length (128 bits). The specific implementation of the digital correlator will, of course, differ slightly depending upon the length of the two words. 
     The two digital words are initially shifted into shift registers 10a and 10b. Logic circuits are provided with each shift register to place the shift registers in a RECIRCULATE mode after initial loading. These logic circuits include AND gates 12a, 12b, 14a, and 14b; INVERTERS 16a and 16b; and OR gates 18a and 18b. 
     The two digital words are received by AND gates 14a and 14b. A control signal from control logic 20 is also received by AND gates 14a and 14b. The outputs of AND gates 14a and 14b are inputs to OR gates 18a and 18b, respectively. The control signal from control logic 20 is inverted by INVERTERS 16a and 16b and forms inputs to AND gates 12a and 12b. The outputs of shift registers 10a and 10b are the other inputs to AND gates 12a and 12b, respectively. The outputs of AND gates 12a and 12b are inputs to OR gates 18a and 18b, respectively. 
     In operation, a logic &#34;1&#34; from control logic 20 enables AND gates 14a and 14b and allows new digital words to be entered into shift registers 10a and 10b. The logic &#34;1&#34; disables AND gates 12a and 12b so that the information presently stored in the shift registers 10a and 10b is not re-entered. 
     After the digital words have been entered into shift registers 10a and 10b, the control signal from control logic 20 changes to a logic &#34;0&#34;, thereby enabling AND gates 12a and 12b and disabling AND gates 14a and 14b. Shift registers 10a and 10b therefore, are in a recirculating mode. 
     The contents of shift registers 10a and 10b are then shifted (recirculated) in response to the two clock signals, CLK A  and CLK B , supplied by control logic 20. Clock 22 provides synchronizing signals to control logic 20. Each time a logic &#34;1&#34; occurs at the output of registers 10a and 10b simultaneously, AND gate 24 produces an output coincident with the strobe pulse generated by control logic 20. The output pulses of AND gate 24 are counted by binary counter 26. 
     The number of clock pulses CLK A  and CLK B  correspond exactly to the number of bits in shift registers 10a and 10b. Upon completion of one complete circular shift, the count accumulated in counter 26 is entered into random access memory (RAM) 28 at a location determined by the state of the address counter 30. At the initiation of the correlation sequence, address counter 30 is cleared. This causes the initial memory address and the first entry to occur at the lowest address. The number of counts stored at a particular location in memory 28 is an indication of the similarity between the bits of the first and second digital words during that comparison cycle. 
     Upon completion of the first circular shift of the contents of shift registers 10a and 10b (i.e., completion of the first comparison cycle), one extra clock pulse is produced at the clock input of shift register 10b. This shifts the contents of shift register 10b by one bit with respect to the contents of shift register 10a. At the same time, address counter 30 is incremented by one. Counter 26 is cleared, and the second circular shifts or comparison cycle of the contents of registers 10a and 10b is commenced, and output pulses at gate 24 are again counted in counter 26. This sequence continues until the number of shifts equals the maximum valve of &#34;n&#34; to be considered. Each time a comparison cycle is completed, the contents of counter 26 are placed in memory 28 at the next higher address obtained by incrementing address counter 30 by one for each completed comparison cycle. 
     The best correlation is the address of the largest count stored in memory 28 during the comparison cycles. The final step is the determination of this address. The largest number in memory 28 is determined as follows. 
     Address counter 30 is set to the highest address, which corresponds to all &#34;1&#39;s&#34; in address counter 30. This address is then stored in latch 32. Alternatively, the number stored in latch 32 can be derived from a source other than address counter 30. What is required is that the number stored in latch 30 initially be as high as the highest count possibly contained in memory 28 (i.e., all &#34;1&#39;s&#34;). The number in latch 32 must be decremented by one each time a complete check of memory 28 has found no match. Address counter 30 is a convenient means for providing the number and decrementing the number. 
     After the highest count is stored in latch 32, address counter 30 is sequentially decremented to zero. All locations in memory 28 are addressed in sequence and are compared to the contents of latch 32 by comparator 34. If any of the locations in memory 28 contain all &#34;1&#39;s&#34;, comparator 34 issues an output indicating a match has occured. At this point the correlation process is stopped, and the particular address contained in address counter 30 at that time is entered into latch 32. This address corresponds to the number &#34;n&#34;. 
     If no match is found to the highest count, address counter 30 is decremented by one from its previous highest count and this count is stored in latch 32. The address countdown and comparison is then repeated. The process of decrementing the address and comparing the contents of memory 28 to contents of latch 32 continues until a match is found. At this point, the correlation process is concluded and comparator 34 provides a &#34;Match&#34; output. This particular memory address at which the match occurred is the number &#34;n&#34;, control logic 20 causes the address to be entered into latch 32 when it receives the &#34;match&#34; output from comparator 34. The outpuut of latch 32 represents the number &#34;n&#34;. 
     FIG. 2 shows a modification of a portion of the digital correlator of FIG. 1. In particular, FIG. 2 shows modification to be comparing means used in the digital correlator of FIG. 1. 
     As previously described, AND gate 24 of FIG. 1, together with counter 26, form the comparing means which compare the individual bits of the first and second digital words. The counts which are stored occur only when the bits of both the first and second words are &#34;1&#34;. 
     In the modification of the comparing means shown in FIG. 2, a count is produced if the two bits are either both &#34;1&#34; or both &#34;0&#34;. The embodiment of FIG. 2 includes AND gate 24 and binary counter 26, plus inverter 36, NOR gate 38, and OR gate 40. 
     As in FIG. 1, the outputs of shift registers 10a and 10b are applied, together with the strobe pulse from control logic 20, to the inputs of AND gate 24. The output of AND gate 24 is &#34;1&#34; only when all three inputs are &#34;1&#34;. In addition, however, the outputs of shift registers 10a and 10b are applied to the inputs of NOR gate 38 together with the strobe pulse which has been inverted by inverter 36. The output of NOR gate 38, therefore, is a &#34;1&#34; if all three inputs are &#34;0&#34;. 
     OR gate 40 applies a &#34;1&#34; to binary counter 26 whenever the output of either AND gate 24 or NOR gate 38 is one. The total count in counter 26, therefore, represents the number of times that the bits from the two digital words are identical, whether they are both &#34;1&#34; or both &#34;0&#34;. 
     In conclusion, the digital correlator of the present invention performs correlation on two digital words with relatively small number of electrical components. While this digital correlator is of particular use in a digital auto-focus system of the type described in the previously mentioned co-pending patent applicaton by Norman L. Stauffer, it has application to many other digital systems as well. 
     The present invention has been described with reference to preferred embodiments. It will be understood, however, by those skilled in the art that changes in form and detail may be made without departing from the spirit and scope of the invention.