Semiconductor integrated flip-flop circuit device including merged bipolar and field effect transistors
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor integrated circuit, and more particularly it pertains to a semiconductor integrated circuit including merged transistors constituting a flip-flop circuit. 
     2. Description of the Prior Art 
     Hereinbelow, description will be made in connection with the accompanying drawings. 
     FIGS. 1 and 2 show a conventional semiconductor memory cell proposed in IEEE Journal of Solid State Circuits, October 1973. A memory cell of FIG. 1 is formed with a pair of inverter transistors Q 3  and Q 4  for holding memory, a pair of load transistors Q 1  and Q 2 , and a pair of current source transistors Q 5  and Q 6 . The collectors of the inverter transistors Q 3  and Q 4  are connected to the bases of the inverter transistors Q 4  and Q 3 , respectively. This memory cell is achieved by the structure as shown in FIG. 2. In FIG. 2, a semiconductor wafer 10 is comprised of an n type semiconductor substrate 11 of a low resistivity and an n type epitaxial layer 12 of a relatively high resistivity grown thereon. In this n type layer 12, p type semiconductor regions 13, 14, 15, 16 and 17 of a relatively low resistivity are formed by relying on the selective diffusion technique. Furthermore, in the p type regions 14 and 16 are formed n type semiconductor regions 18 and 19 of a further low resistivity. Metal electrodes 20, 21, 22, 23, 24, 25 and 26 are formed on the respective semiconductor regions 13, 14, 15, 16, 17, 18 and 19. Another electrode 27 is formed on the lower surface of the semiconductor substrate 11. Pairs of the electrodes 21 and 26, and 23 and 25 are electrically connected through metal layers. The electrode 27 is used as the X address electrode, and the electrode 22 as the Y address electrode. The electrodes 20 and 24 are used as the read/write electrodes RW 0  and RW 1 , respectively. 
     Now, the correlation between FIGS. 1 and 2 will be described. The semiconductor regions 12, 14 and 15 constitute the base, the collector and the emitter of the pnp type bipolar transistor Q 1 , respectively. The semiconductor regions 12, 16 and 15 constitute the base, the collector and the emitter of the pnp type bipolar transistor Q 2 , respectively. It will be seen that the emitter and the base regions of the pnp type bipolar transistors Q 1  and Q 2  are common with each other, and connected to the electrodes Y and X. The semiconductor regions 12, 16 and 19 constitute the emitter, the base and the collector regions of the npn bipolar transistor Q 3 , respectively, while the semiconductor regions 12, 14 and 18 constitute the emitter, the base and the collector regions of the npn transistor Q 4 , respectively. Here, the n +  type region 11 is considered as part of the n type region 11. The semiconductor regions 17, 12 and 16 constitute the emitter (or collector), the base and the collector (or emitter) regions of the pnp type transistor Q 5 , respectively, while the semiconductor regions 13, 12 and 14 constitute the collector (or emitter), the base and the emitter (or collector) regions of the pnp type transistor Q 6 , respectively. The p type collector region 14 of the pnp type transistor Q 1  is connected to the n type collector region 19 of the npn type transistor Q 3  through a metal lead, and similarly the p type collector region 16 of the pnp type transistor Q 2  is connected to the n type collector region 18 of the npn type transistor Q 4 . 
     Such a conventional semiconductor memory cell is accompanied by the following drawbacks and inconveniences. 
     The collector loads for the inverter transistors Q 3  and Q 4  for holding the memory content are formed with bipolar transistors Q 1  and Q 2  of the lateral structure as shown in FIG. 2. Therefore, the switching speed of these transistors Q 1  and Q 2  cannot be made very high. Then, the maximum operation speed of this conventional memory cell is limited by the switching speed of the transistors Q 1  and Q 2 . 
     Furthermore, the clocking for this memory cell should be achieved by applying power pulses to the Y address electrode Y. Thus, the power required for clocking is large. 
     In the above structure, the transistors Q 1  and Q 2  inject carriers into the base regions of the transistors Q 4  and Q 3 . In the bipolar transistor of the lateral structure, it is very difficult to reduce the base width W B  from the viewpoint of manufacture, and hence the carrier injection efficiency (equal to the common base current amplification factor) can not be made high. Namely, the leak component of carriers is large, and hence the power dissipation is large. Particularly, when the quantity of injected carriers becomes large, the potentials at the collectors 14 and 16 of the transistors Q 1  and Q 2  rise to cause the reverse injection from these collectors 14 and 16, and the pn-junction between the emitter 15 and the base 12 is forwardly and deeply biased. Thus, the effect of the base resistance becomes large, and the ratio of carriers escaping into the semiconductor substrate 11 increases. Therefore, the carrier injection efficiency α rapidly decreases as the injection current (the current injected from the Y address electrode Y) increases. There is the need of increasing the injection current to inject many carriers for reducing the charging and discharging time period for the parasitic capacitances at respective portions and for increasing the switching speed of the transistors Q 1  and Q 2 . Here, power loss rapidly increases as the injection current is increased. Thus, there is difficulty in integrating the conventional memory cells with a high density. 
     FIGS. 3 and 4 show an example of the conventional semiconductor register cell. A register cell is formed with a master flip-flop MF and a slave flip-flop SF. Each of these flip-flops includes four transistors Q 1  to Q 4 . Each of the inverter transistors Q 3  and Q 4  has two collectors, one of which is connected to the base of the other inverter transistor of the same flip-flop. The load transistors Q 1  and Q 2  also serve to inject carriers into the bases of the inverter transistors Q 4  and Q 3 . Namely, the load transistor Q 1  injects carriers into the base of the inverter transistor Q 4  when the other inverter transistor Q 3  is turned off. 
     A first clock pulse signal φ 1  is applied to the common emitter of the load transistors Q 1  and Q 2  of the master flip-flop MF, while a second clock pulse signal φ 2  in opposite phase to the first clock pulse signal φ 1  is applied to the common emitter of the load transistors Q 1  and Q 2  of the slave flip-flop SF. The second collectors of the inverter transistors Q 3  and Q 4  of the master flip-flop MF are connected to the first collectors of the inverter transistors Q 3  and Q 4  of the slave flip-flop SF through lines L 1  and L 2 , respectively. The inputs to this register cell, e.g. the outputs of another register cell, are supplied to the bases of the inverter transistors Q 4  and Q 3  of the master flip-flop MF through lines L 3  and L 4 , respectively. The outputs of this register cell, i.e. the signals at the second collectors of the inverter transistors Q 3  and Q 4  of the slave flip-flop SF, are supplied to the following register cell or other logic circuit portion through lines L 5  and L 6 , respectively. 
     Since the operation of this register cell is well known, brief description thereof will be made hereinbelow. First, when the clock pulse φ 1  arrives with the lines L 3  and L 4  being held at a high and a low potential, carriers are injected from the load transistor Q 1  to the base of the inverter transistor Q 4 , thereby to turn the inverter transistor Q 4  on. Carriers which may be injected from the load transistor Q 2  are absorbed by the turned-on inverter transistor Q 4 , thereby holding the inverter transistor Q 3  in its turned-off state. If a parasitic capacitance C 1  accompanied by the line L 1  has been charged up, the positive potential of the line L 1  is held as it was. On the other hand, a parasitic capacitance C 2  of the other line L 2  is discharged through the turned-on inverter transistor Q 4  to lower the potential of the line L 2 . 
     Then, when the clock pulse φ 2  arrives (at this moment the clock pulse φ 1  is vanished), the inverter transistor Q 4  is turned on and the state of the inverter transistors Q 3  and Q 4  are stored in the parasitic capacitances C 5  and C 6  of the lines L 5  and L 6 . 
     In this way, the master flip-flop MF and the slave flip-flop SF are alternately clocked by the clock pulses φ 1  and φ 2 , and the information given to the input lines L 3  and L 4  of the register cell are sent out from the output lines L 5  and L 6  of the register at a predetermined timing. 
     As can be seen from FIG. 3, the master flip-flop MF and the slave flip-flop SF may have the same structure. A structure of the master or slave flip-flop is shown in FIG. 4. 
     In the figure, an n type semiconductor wafer 110 is formed with an n-type semiconductor substrate 111 of a low resistivity and an n type epitaxial layer 112 of a relatively high resistivity grown on the substrate 111. In the n type epitaxial layer 112, p type regions 113, 114 and 115 of a relatively low resistivity are formed by, for example, the selective diffusion technique. In the p type regions 113 and 115, n type regions 116, 117, 118 and 119 of a low resistivity are formed by, for example, the selective diffusion. Metal electrodes 120, 121, 122, 123, 124, 125 and 126 are formed on the regions 113, 114, 115, 116, 117, 118 and 119, respectively. Another electrode 127 is formed on the lower surface of the n type semiconductor substrate 111. Pairs of the electrodes 120 and 125, and 122 and 124 are connected by metal leads. 
     Correlation of the structure of FIG. 4 and one flip-flop in the register of FIG. 3 is as follows. Semiconductor regions 112, 113 and 114 constitute the base, the collector and the emitter of the load transistor Q 2 , respectively, while the regions 112, 114 and 115 constitute the base, the emitter and the collector of the load transistor Q 1 , respectively. The regions 112, 115 and 118 and 119 constitute the emitter, the base and the first and the second collectors of the inverter transistor Q 4 , respectively, while the regions 112, 113 and 116 and 117 constitute the emitter, the base and the first and the second collectors of the inverter transistor Q 3 , respectively. Here, the n type region 111 is considered as part of the n type region 112. 
     As can be seen from the above statement, the conventional register cell as described above has similar drawbacks and inconveniences as described above with respect to the memory cell. 
     Namely, since the load transistors Q 1  and Q 2 , which inject carriers to the inverter transistors Q 4  and Q 3  as well as serve as the collector loads for the inverter transistors Q 3  and Q 4 , are formed with bipolar transistors, they have an inherently limited switching speed due to the carrier storage effect therein. 
     Furthermore, since the load transistors Q 1  and Q 2  have lateral structures, it is difficult to reduce the base width W B  thereof, and hence is difficult to increase the carrier injection efficiency α (equal to the common base current amplifiction factor). Namely, the leak component of the carriers is large and the power loss is large. In particular, when the amount of the injected carriers becomes large, the potential at the collectors 113 and 115 of the injector transistors Q 2  and Q 1  rises to cause the reverse injection therefrom. Furthermore, the pn-junction between the emitter 114 and the base 112 becomes forwardly deeply biased, and hence the effect of the base resistance becomes large. Thus, the rate of the carriers escaping into the semiconductor substrate 111 increases. Therefore, the carrier injection efficiency α rapidly falls down with an increase in the injection current I i  (the current flowing into the common emitter of the injector transistors Q 1  and Q 2 ), as shown in FIG. 16. 
     Furthermore, the conventional register cell should be clocked by applying clock pulse φ 1  and φ 2  to the emitters of the injector transistors of the master and the slave flip-flops. Thus, a large power is required for clocking. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a semiconductor integrated circuit device which improves such conventional technical problems as described above. 
     Another object of the present invention is to provide a semiconductor integrated circuit device having an improved operation speed. 
     A further object of the present invention is to provide a semiconductor integrated circuit device having a small power dissipation and a high integration density. 
     Another object of the present invention relates to a semiconductor integrated circuit device requiring a small power for clocking. 
     According to an aspect of the present invention, there is provided a semiconductor integrated circuit device having flip-flop, each flip-flop comprising a pair of inverter transistors for holding the inputted state and a pair of load transistors for serving as the collector load and as the carrier injectors for the inverter transistors, the load transistors being formed with field effect transistors and having channels connected to the bases of the inverter transistors. 
     The above and other objects, the features as well as the advantages of the present invention will become apparent in the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a conventional semiconductor memory cell. 
     FIG. 2 is a partial cross-section of a conventional semiconductor integrated circuit device structure having the circuit connection of FIG. 1. 
     FIG. 3 is a circuit diagram of a conventional semiconductor register cell. 
     FIG. 4 is a partial cross-section of a conventional semiconductor integrated circuit device structure having the circuit connection of FIG. 3. 
     FIG. 5 is a circuit diagram of a semiconductor memory cell according to an embodiment of the present invention. 
     FIG. 6 is a partial cross-section of the semiconductor integrated circuit device structure embodying the circuit of FIG. 5. 
     FIGS. 7A to 7C are a plan view and cross-sectional views of an alternative structure of the semiconductor integrated circuit device embodying the circuit of FIG. 5. 
     FIG. 8 is a circuit diagram of a semiconductor memory cell according to another embodiment of the present invention. 
     FIG. 9 is a partial cross-section of a semiconductor integrated circuit structure embodying the circuit of FIG. 8. 
     FIG. 10 is a partial cross-section of a semiconductor integrated circuit structure according to an embodiment of the present invention. 
     FIG. 11 is a circuit diagram of a memory matrix embodying the memory cells according to an embodiment of the present invention. 
     FIG. 12 is a circuit diagram of a semiconductor register cell according to an embodiment of the present invention. 
     FIG. 13 is a partial cross-section of a semiconductor integrated circuit device structure embodying the circuit of FIG. 12. 
     FIGS. 14A and 14B are a plan view and a partial cross-section of an alternative structure of the semiconductor integrated circuit device embodying the circuit of FIG. 12. 
     FIG. 15 is a partial cross-section of a semiconductor integrated circuit device structure according to an embodiment of the present invention. 
     FIG. 16 is a graph of the carrier injection efficiency vs. injection current curves comparing the present invention with the prior art. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 5 shows a circuit diagram of a semiconductor memory cell, in which load transistors Q 11  and Q 12  are formed with insulated gate type field effect transistors and serve to inject carriers into the inverter transistors Q 13  and Q 14  as well as serve as the collector loads of inverter transistors Q 13  and Q 14 . 
     FIG. 6 shows an example of a semiconductor integrated circuit device structure embodying the circuit of FIG. 5. In the figure, an n type semiconductor wafer 50 is formed with an n type semiconductor substrate 51 of a low resistivity, and with an n type epitaxial layer 52 of a relatively low resistivity grown thereon. In the n type epitaxial layer 52, there are formed p type diffused regions 53, 54 and 55 of a relatively high resistivity. In the p type regions 53 and 55, n type regions 56, 57, 58 and 59 of a low resistivity are formed. Metal electrodes 60, 61, 62 and 63 are formed on the n type regions 56, 57, 58 and 59. Further metal electrodes 64, 65, 66 and 67 are formed on the p type regions 53, 54 and 55 and on the n type semiconductor substrate 51. Insulated gate electrodes 69 are formed on portions of the n type region 52 between the p type region 54 and the p type regions 53 and 55 through gate insulating films 68. Numeral 70 denotes an oxide film. The electrode 65 is used as the injection electrode I, the electrodes 60 and 63 as the read/write electrodes RW 1  and RW 0 , the electrode 68 as the Y address electrode Y and the electrode 67 as the X address electrode X. 
     The correlation between FIGS. 5 and 6 are as follows. The semiconductor regions 52, 53 and 56 and 57 constitute the emitter, the base and the collectors of the npn type multi-collector inverter transistor Q 13 , respectively, while the regions 52, 55 and 58 and 59 constitute the emitter, the base and the collectors of the other npn type multi-collector inverter transistor Q 14 , respectively. The p type regions 53 and 54 constitute the drain and the source of the p-channel insulated gate type field effect transistor Q 12  which serves as the collector load for the inverter transistor Q 14  and as the carrier injector for the inverter transistor Q 13 , respectively. The p type regions 54 and 55 constitute the source and the drain of the other p-channel insulated gate type field effect transistor Q 11  which serves as the collector load for the inverter transistor Q 13  and as the carrier injector for the inverter transistor Q 14 , respectively. The p-channels of these field effect transistors are induced in the surface portion of the n type region 52 below the gate electrodes 68 and 69. 
     The operation of the embodiment of FIGS. 5 and 6 is as follows. 
     a. Cell Selection 
     In the memory cell to be selected, the voltage on the line of the Y address electrode Y is raised, and the voltage on the line of the X address electrode X is lowered. In the semiconductor integrated circuit device, a plurality of such memory cells are generally arranged in a matrix pattern which will be referred to later. 
     b. Write Operation 
     The voltage on one of the read/write electrodes RW 0  and RW 1  of a selected memory cell is lowered in accordance with the information to be written in. For example, if the voltage of the read/write electrode RW 1  is lowered, carriers are drawn into the base 53 of the transistor Q 13 . Then, the line voltage of the Y address electrode Y is lowered to such a degree that carriers are injected from the field effect transistor Q 12  to the base of the transistor Q 13  to hold the transistor Q 13  in its turned-on state. Since the write information is set in the memory cell by the above-stated operation, the line voltage of the read/write electrode RW 1  may be returned to the ordinary value thereafter. 
     c. Read Operation 
     When both the line voltages of the read/write electrodes RW 0  and RW 1  of a selected memory cell are raised, a current is allowed to flow through either one line in accordance with the memory content in the memory cell. Then, the voltage of the read/write electrode connected to this line is lowered. Thus, the memory content of the memory cell can be read out from the polarity of the voltage difference between the two electrodes RW 0  and RW 1 . 
     FIGS. 7A to 7C show an alteration of the above-mentioned embodiment. FIG. 7A shows a plan view and FIGS. 7B and 7C are cross-sections along the lines 7B-7B&#39; and 7C-7C&#39;. In this structure, transistors Q 13  and Q 14  are disposed in parallel to each other, and a common source 54 of field effect transistors Q 11  and Q 12  is disposed on one side of these transistors Q 13  and Q 14 . Reference numerals similar to those of FIG. 6 denote similar parts. 
     FIG. 8 shows another embodiment of a semiconductor memory cell in which read/write terminals RW 0  and RW 1  are derived through common base bipolar transistors Q 15  and Q 16 . FIG. 9 shows a semiconductor integrated circuit device structure embodying the circuit of FIG. 8. In FIG. 9, p type regions 71 and 72 are formed in the n type epitaxial layer 52 to provide pnp type bipolar transistors Q 15  and Q 16  by the use of the n type region 52 and the p type regions 53 and 55. Naturally, the n type regions 56 and 59 for forming the multi-collectors in the structure of FIG. 6 are dispensed with. Other portions are similar to those of the structure of FIG. 6, and accordingly similar reference numerals are used to denote similar parts. 
     The operation of this embodiment will be described briefly. 
     d. Cell Selection 
     The operation of cell selection is similar to that of the foregoing embodiment. 
     e. Read Operation 
     The read operation is also similar to the foregoing embodiment. For example, when the transistor Q 13  is turned on, the transistor Q 15  is also turned on to allow a current to flow through the line of the read/write electrode RW 1  so as to lower the line voltage of the electrode RW 1 . 
     f. Write Operation 
     Operation similar to that of the above-stated embodiment holds true also. For example, the transistor Q 13  is turned on by supplying a current pulse of positive polarity to the line of the read/write electrode RW 0 . 
     The load transistors of the foregoing embodiments are formed with insulated gate type field effect transistors. The load transistors may likewise be formed with junction type field effect transistors. An example of such a structure corresponding to the structure of FIG. 6 is shown in FIG. 10. Namely, n type gate regions 81 and 82 of a low resistivity are formed in a p type region 53. The p type regions 54 and 55 of FIG. 6 are integrated with the p type region 53. Gate electrodes 69 are formed on these n type regions 81 and 82. Furthermore, a source electrode 65 is formed on a portion of the p type region 53 sandwiched or surrounded by these n type regions 81 and 82 either directly or through a p type region of a low resistivity. Other portions are similar to those of the structure of FIG. 6, and therefore similar numerals are used to denote similar parts. Thus, the operations thereof are also similar to those of the structure of FIG. 6. 
     An example of a semiconductor memory cell array including a plurality of memory cells of the above-stated embodiments is partially shown in FIG. 11. In the figure, memory cells M 11  to M 32  having a structure as described in the above-stated embodiments are disposed in a matrix and connected with X address lines X 1  and X 2 , Y address lines Y 1  and Y 2 , and read/write lines B 0  and B 1 . For example, when the memory cell M 21  is to be selected, the potential of the address line X 1  is lowered a little and the address line Y 1  is clocked as can be seen from the foregoing description. Further operations will be apparent from the foregoing description, and hence they are omitted here. 
     FIG. 12 shows an embodiment of a semiconductor register cell formed in an integrated circuit. FIG. 13 shows an example of the structure embodying one flip-flop circuit of FIG. 12. 
     In this embodiment, load transistors Q 21  and Q 22  of the master flip-flop MF and load transistors Q 31  and Q 32  of the slave flip-flop SF are formed with field effect transistors. The field effect transistors may be either one of insulated gate type and of junction type. In these figures, insulated gate type field effect transistors are shown. A first clock pulse signal φ 1  is applied to the common gate of the load transistors Q 21  and Q 22  of the master flip-flop MF, and a second clock pulse signal φ 2  is applied to the common gate of the load transistors Q 31  and Q 32  of the slave flip-flop SF. A predetermined positive voltage +V is applied to the source electrodes of these load transistors Q 21 , Q 22 , Q 31  and Q 32 . As is apparent from the figure, the master flip-flop and the slave flip-flop have the identical structure. 
     A flip-flop structure of FIG. 12 is shown in FIG. 13. In FIG. 13, a semiconductor wafer 150 is formed with an n type semiconductor substrate 151 of a low resistivity and an n type epitaxial layer 152 of a relatively low resistivity. In this n type layer 152, p type regions 153, 154 and 155 of a relatively high resistivity are formed by, for example, the diffusion technique. In the p type regions 153 and 155, n type regions 156, 157, 158 and 159 of a low resistivity are formed. Metal electrodes 160, 161, 162 and 163 are formed on these n type regions 156, 157, 158 and 159. Other metal electrodes 164, 165, 166 and 167 are formed on the p type regions 153, 154 and 155 and also on the n type semiconductor substrate 151. Gate electrodes 169 are formed on such portions of the n type region 152 that are sandwiched between the p type region 154 and the p type regions 153 and 155 through gate insulating films 168. Numeral 170 denotes a passivating oxide film. 
     The p type semiconductor regions 154 and 155 constitute a source and a drain region of the p-channel insulated gate field effect transistor Q 21 , respectively. The p-channel of this field effect transistor Q 21  is induced in the surface portion of the n type region 152 under the gate electrode 169. Similarly, the p type regions 153 and 154 constitute a drain and a source region of the p-channel insulated gate field effect transistor Q 22 , respectively. The p-channel is induced under the gate electrode 169. These p-channel field effect transistors Q 21  and Q 22  serve as the injectors for the driver transistors Q 23  and Q 24 , respectively. The semiconductor regions 152 (including 151), 153 and 156 and 157 constitute an emitter, a base and two collectors of the npn type bipolar multi-collector transistor Q 23 , while the semiconductor regions 152 (including 151), 155 and 158 and 159 constitute an emitter, a base and two collectors of the npn type bipolar multi-collector transistor Q 24 . 
     As described above, the load transistors of the master and the slave flip-flops MF and SF are formed with field effect transistors which inherently have no carrier storage effect. Furthermore, since these injector transistors inject carriers into the base regions of the inverter transistors through channels connected or continuous to the base regions, the carrier injection efficiency α is extremely high, and does not fall by the increase of the injection current I i  as can be seen in FIG. 16. Therefore, the register cell of the above-stated embodiment enables a high speed operation and also a reduction in the power dissipation. Furthermore, the power required for clocking can be largely reduced since clocking is done by applying clock pulses φ 1  and φ 2  to the high impedance gates of the load transistors. 
     An alternative structure of the register cell embodying the circuit of FIG. 12 is shown in FIGS. 14A and 14B in which FIG. 14A is a plan view and FIG. 14B is a cross-section along the line 14B-14B&#39; in this structure, inverter transistors Q 23  and Q 24  (Q 33  and Q 34 ) are disposed in parallel to each other and the source regions 54 for the load transistors Q 21  and Q 22  are located on one side of the inverter transistors Q 23  and Q 24   perpendicularly to the p type regions 53 and 55 as seen in FIG. 14A. This structure is similar to that of FIG. 13 in other respects. Similar numerals are used to denote similar parts to those of FIG. 13, and further description is omitted here. 
     Although the load transistors are formed with insulated gate type field effect transistors in the above embodiments, it will be apparent that they can be formed with junction type field effect transistors. 
     FIG. 15 shows an alternative embodiment of a register cell, in which load transistors are formed with junction type field effect transistors. In FIG. 15, only the master flip-flop is shown since the slave flip-flop may have the identical structure. 
     In this embodiment, n type semiconductor regions 181 and 182 of a low resistivity for constituting the gate regions of the load transistors Q 21  and Q 22  are formed in a p type region 153 and gate electrodes 169 are formed on these n type regions 181 and 182. A source electrode 165 is formed on a portion of the p type region 153 sandwiched between the n type regions 181 and 182, directly or through a p type region of a low resistivity. As can be seen from the figure, this embodiment is similar to that of FIG. 13, excepting the point that the load transistors Q 21  and Q 22  are formed with junction type field effect transistors. Therefore, operation of this circuit is similar to that of the circuit of FIG. 13. Similar reference numerals are used to denote similar parts to those of FIG. 13. 
     As has been described hereinabove, according to the embodiments of the present invention, the load transistors of a flip-flop circuit serving also as the carrier injectors for the inverter transistors are formed with field effect transistors which inherently have no carrier storage effect. Thus, the switching speed of a flip-flop can be remarkably improved. Furthermore, since the load transistor injects carriers into the base region of the inverter transistor through a channel continuously connected to the base region, the carrier injection efficiency is very high, and does not fall down with an increase in the injection current. Thus, a high speed operation is possible by injecting sufficiently many carriers without increasing the ratio of leak carriers to the total of the injected carriers. Thus, a high density integration becomes possible. Furthermore, clocking can be achieved by applying voltage pulses to the gate of the load transistor, and thereby the power required for clocking can be remarkably reduced. 
     As such, there is provided a semiconductor integrated circuit provided with excellent features which can not be achieved by the conventional techniques. It will be apparent that the present invention is not limited to the above embodiments, and that many alterations and/or modifications are possible without departing from the spirit of the present invention. For example, the conductivity types of the respective semiconductor regions can, naturally, be reversed.