Signal coding for compressed pulse code modulation system
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to signal coding for pulse code modulation systems, and more particularly, to encoders and decoders for telephone communication systems using compressed pulse code modulation with logarithmic companding. 
     2. Description of the Prior Art 
     The demand for communication services has been steadily increasing. In meeting this demand, it has proven effective in some communication systems to convert signals presented to the system into encoded digital signals and then reconvert the encoded digital signals into signals corresponding to those originally entered into the system. One example of a communication system in which such transmission of encoded digital signals has proven to have particular utility is a telephone communication system. Several schemes for digitally encoding signals in a telephone system are known. Although these encoding schemes are useful for both digital and analog signals entered into the telephone system, they have particular utility with continuous, time-varying analog signals such as voice signals. 
     In one encoding scheme, the amplitude of a voice analog signal is periodically sampled and each sample is converted into a digitally encoded pulse sequence, or word, representing the sampled analog signal. This operation is called sampling and quantizing of the analog signal. If the range of analog signal amplitudes represented by each quantum level or step of the quanitzing operation is uniform for all analog signal amplitudes, the encoded signal is said to be linear pulse code modulated (hereafter LPCM). Each LPCM signal word may then be decoded to form an analog signal of an amplitude substantially corresponding to the amplitude of the analog signal sample encoded into the LPCM signal word. Since the input analog signal was periodically sampled, the resulting periodic LPCM signal words may be formed into a continuous analog signal substantially corresponding to the continuous input analog signals. 
     In the quantizing process, the exact level of the entered analog signal at the sampling instant is, as described, approximated by one of a number of discrete values or quantum levels digitally encoded as the LPCM signal. The difference between the instantaneous amplitude of the input analog signal and the quantum level actually transmitted is called quantizing error and gives rise to what is variously known as quantizing noise or quantizing distortion. 
     Quantizing distortion is especially objectionable and very often intolerable when the instantaneous amplitude of the input analog signal is small, but is usually of little or no significance when the instantaneous amplitude of the input analog signal is high. This is because the low amplitude of the input signals permits a relatively low level of quantizing noise to significantly degrade the ratio of signal to noise, while a higher amplitude of the input signal can tolerate greater quantizing noise within an acceptable ratio of signal to noise. It is therefore desirable to have smaller quantum levels for lower amplitudes of the input signal to achive closer correspondence between the quantum level of the encoded signal and the actual amplitude of the input analog signal at the lower amplitudes, resulting in an acceptable ratio of signal to noise. Of course the size of the quantum levels for all input signal amplitudes could be decreased, but this produces an undesirable increase in the total number of quantum levels, requiring, for example, more bits to represent the signal as a digitally encoded word. 
     The suggested non-linear redistribution of the size of the quantizing levels is called companding, a verbal contraction of the terms compression and expanding. The purpose of companding is then to reduce the quantizing impairment of the original signal without unduly increasing the total number quantizing levels by quantizing on a non-linear rather than a linear basis. 
     It is current practice with telephone systems to compand encoded analog signals on either a μ-law or an A-law companding scheme as described by H. Kaneko in an article entitled &#34;A Unified Formulation of Segment Companding Laws and Synthesis of Codecs and Digital Companders&#34;, published in The Bell System Technical Journal, September, 1970. The resulting signals are then called compressed pulse code modulated signals (hereafter CPCM) or companded pulse code modulated signals. The μ-law is being generally adopted in the United States. The &#34;gross&#34; continuous formulation for the μ-law is: ##EQU1## for -1≦x≦1. The variable x is the input amplitude normalized to the analog full scale and y the relative output amplitude, which in turn is encoded into a binary number expressing the magnitude of y on a linear basis. An additional bit, the sign bit, indicates the polarity of the signal sample x being encoded. Typically, the magnitude of y is expressed as a 6 or 7 digit binary number, corresponding to what is conventionally referred to 7 or 8 bit resolution (code). Accordingly, y is approximated to one out of 64 or 128 evenly distributed levels (disregarding the sign). Actually, in the &#34;standard&#34; version of CPCM adopted in the U.S., a continuous exponential (or logarithmic) companding law is not normally used. Instead the inverse function, x = f(y), is approximated by 8 linear chords or segments, each sub-divided into 8 or 16 steps, depending upon the number of bits mentioned before (7 or 8). The segmented μ-law is used to avoid implementation difficulties and to facilitate digital linearization features, but the resulting circuits are still somewhat complicated. It might be added that regardless of approach, a constant of μ= 255 has been chosen. Separate studies show that the additional distortion caused by back-to-back operation of a &#34;continuous encoder&#34; and a &#34;segmented decoder&#34;, or vice versa, is acceptable as such said added distortion being of the order of 3% or less. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to provide for conversion between analog and digital signals with simplicity, enabling low cost implementation with standard components including integrated circuits. 
     Another object of the invention is to provide a codec having an encoder section and a decoder section, and a capacitor-resistor type companding generator common to both the encoder section and a decoder section. 
     The present invention has provided conversion apparatus and a method for relating a digital compressed pulse code modulation signal value to an analog signal value in accordance with a predetermined logarithmic companding law. The conversion apparatus includes an encoder portion having encoder counting means, a decoder portion including decoder counting means, and a companding generator common to the encoder portion and the decoder portion. The companding generator includes a capacitor and resistance means connected in series, means to charge the capacitor to a first potential and means effective starting at an initial time to discharge the capacitor through the resistance means toward a second potential. The apparatus further includes means effective starting at the initial time to advance the encoder counting means and to decrement the decoder counting means at a given frequency. The first and second potentials, the given frequency, and the RC time constant of the capacitor and the resistance means, are selected such that the number of steps counted by the encoder and decoder counting means is a simple function related to the ratio of the potential on the capacitor to a &#34;full scale&#34; value in accordance with a predetermined companding law. 
     In a disclosed embodiment, the predetermined logarithmic companding law is the μ-law: ##EQU2## The first potential is equal to the full scale potential of the analog signal value, the second potential is equal to the negative of the first potential divided by μ, and the given frequency is such that the time required to count a predetermined maximum number of steps is equal to RC 11=μ) seconds, where RC is the time constant for the capacitor and the resistance means, and the binary representation of the number of steps advanced by the encoder counting means and by the decoder counting means is the corresponding compressed pulse code modulation signal value. 
     A method of relating a digital compressed pulse code modulation signal value to an analog signal value in accordance with a predetermined logarithmic companding law, comprises the steps of initially charging a capacitor through a resistance toward a second potential, measuring first and second intervals of time by stepping first and second counting means at a given frequency starting at the beginning of the discharge of the capacitor, using the potential on said capacitor to encode a sample of an analog signal value with a digital value by permitting said first counting means to increment until the absolute value of the potential on the discharging capacitor equals the absolute value of the potential of said analog signal sample, and using the potential on the discharging capacitor to simultaneously decode a digital value of an analog signal sample valve by sampling the potential on the capacitor as the capacitor discharges, and holding a decoded sample equal in magnitude to the capacitor potential when the decoder counter has decremented a number of steps determined by the input digital signal word. 
     Thus, in accordance with the present invention, the decaying voltage on a capacitor is used both in encoding an analog signal sample with a digital value, and in decoding a ditigal value to an analog signal value, the encoding and decoding operations being effected concurrently using a single companding generator. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     These and other objects and features of the invention are best described by a description of an exemplary embodiment taken in conjunction with the drawing in which: 
     FIG. 1 is a simplified block diagram for a codec constructed in accordance with the principles of the invention; 
     FIG. 2 is a timing diagram depicting the relevant logic states at various points throughout the system during a single codec operating cycle; and 
     FIGS. 3A, 3B, and 3C, when arranged as shown in FIG. 3D, depict a detailed schematic of the encoder section, companding generator and timing circuitry, and the decoder section, respectively, of the codec of FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1 of the drawings, the codec 10 provided by the present invention has particular utility in communication systems employing pulse code modulation. The codec 10 includes an encoder section 12 for encoding time-varying analog signals, such as audito voice signals, in compressed PCM form, and a decoder section 14 for decoding compressed CPCM signals and providing analog signals representing the encoded information. 
     The analog signals v i  presented to the codec on path 1 are encoded employing a μ-law companding scheme, such that the resulting encoded digital signals are compressed pulse code modulation signals, hereinafter referred to as CPCM signals. The continuous formulation for the μ-law is given by the following relationship: ##EQU3## 
     The variable x is the relative amplitude of the analog input signals, and y is the relative output amplitude, which in turn, is encoded into a multibit binary word representing the magnitude of y on a linear basis. An additional sign bit is provided to indicate the polarity of the signal sample being encoded. 
     Briefly, according to the invention, for analog-to-digital encoding, the continuous time-varying analog input signal v i  is sampled and the analog sample v s  is encoded to a corresponding multibit signal in accordance with the μ-law companding scheme. The analog signal v i  is sampled by a sample and hold circuit 16 of the encoder 12, and a comparator circuit 20 compares the signal sample voltage v s  and its inverted equivalent -v s  with a time-varying reference voltage v r , provided by a companding generator 18. The reference voltage v r  decreases from a known amplitude at a known rate, and the time required for the reference signal v r  to equal the magnitude of the signal sample voltage v s  is measured by a binary digital encoder counter 24 of the encoder 12. The binary count at the time of coincidence, as detected by the comparator circuit 20, represents the CPCM code of the analog signal sample. This conversion gives the magnitude of the analog signal. The sign bit of the CPCM code, which indictaes the polarity of the analog signal being encoded, is obtained in a manner to be shown hereinafter. 
     For decoding a CPCM signal, the multibit binary words representing successive samplings of an audio voice signal, and each corresponding to the magnitude of an encoded analog signal sample, are individually loaded into a digital decoder counter embodied of the decoder 14, over path 76&#39; and the counter 32 is then decremented from the starting count provided by the CPCM word to zero count. While the counter 32 is being decremented, the reference signal v r  provided by the companding generator 18 is followed by a sample and hold circuit 40, operating in the track and hold mode, of the decoder 14. When the counter 32 reaches a zero count, the sample and hold circuit 40 enters the hold mode, and the amplitude of the reference signal v r  corresponding to the amplitude of the encoded analog signal sample is held. A sign bit of the pulse code presented to the system at path 74&#39; is used to assign the proper priority to the decoded signal sample in a manner to be shown hereinafter. The analog signals are supplied to an analog output filter which produces a smooth continuous analog signal at path 116 thereby re-constructing the audio voice signal originally encoded. 
     More specifically,, with reference to the encoder 12, a continuous time-varying analog signal v i  supplied to the encoder is passed over a band-limited filter 17 to the sample and hold circuit 16 which is operable when enabled to sample the analog signal at a predetermined rate. By way of example, it is assumed that the code 10 employs an 8KHz sampling rate defining an operate cycle or frame of 125 microseconds. The analog signal is sampled once during each operate cycle, by the sample and hold circuit 16, which is enabled by the timing control signal TS1 to sample the time-varying analog signal v i  for the sampling time interval. At the end of the sampling interval, the comparator circuit 20 is operable during the holding interval to compare the signal output v s , representative of the charge on capacitor CH1 of the sample and hold circuit 16, and the complement -v s  with the time varying signal v r  which is provided by the companding generator. 
     The time varying signal v r  provided by the companding generator 18, decreases from a predetermined amplitude E in a known interval of time established by the time constant of an RC network. When the amplitude of the reference signal v r  has decreased to a value equal to the absolute value of the signal sample voltage v s , the comparator circuit 20 provides a control output to stop the operation of the encoder counter 24. Thus, the content of the counter is the desired CPCM code. 
     During the holding interval, the encoder counter 24 is incremented by clock pulses at a rate FC provided by timing control 52 and extended to the binary counter 24 over a gate circuit 26 which is enabled by signal TS3 provided by the timing control 52. The gate circuit 26 is disabled when the control output is provided by the comparator circuit 20, inhibiting the passage of further clock pulses to the counter 24. At such time, the multibit output word of the counter 24 appearing at path 241, representing the state of the counter 24, indicates the time elapsed from the start of the holding interval, until coincidence of the signal sample voltage v s  and the reference signal v r , and thus, corresponds to the desired CPCM code representing the magnitude of the analog signal v i  to which only a sign bit need to be added. The sign bit is obtained by a sign circuit 28 which is controlled by the comparator circuit 20 to provide an output indicating the polarity of the signal sample v s . 
     The CPCM code, including the multibit word representing the state of the counter 24 on path 76, and the sign bit on path 74 are extended over a suitable communication line 30, to the decoder section of a similar codec at a receiving location. 
     The decoder section 14 basically operates in the inverse manner of the encoder 12 to convert the CPCM signals representing analog signal samples into a continuous analog signal which is a reconstruction of the encoded time varying analog signal from which the CPCM signals were derived. Each CPCM signal supplied to the decoder 14 is loaded into the counter 32 from path 76&#39; during the sampling interval and before the start of the holding interval under the control timing signal TS0 provided by timing control 52, enabling a new word to be loaded into the counter 32 every 125 microseconds. TS0 is also used to load the sign bit from path 74&#39; into a sign circuit 34 of the decoder. 
     At the start of the holding interval, a capacitor C of companding generator 18 discharges toward the reference potential -dE. In addition, signal TS3 provided by the timing control 52 enables gate control 28 to pass clock pulses at a rate FC to the counter 32 for decrementing the counter 32, concurrently with the incrementing of the encoder counter 24. 
     The decoder counter 32 is initially set to the digital value provided by the CPCM input signal and is decremented from such value to a zero count during the holding interval in response to the clock pulses supplied thereto over gate control 28. 
     When a zero count is reached by the decoder counter 32, the signal output T B  of the counter 32 goes high providing a signal which changes the state of the sample and hold circuit 40 from track to hold, and the hold signal sample v s  &#39; corresponds to the magnitude of the analog signal represented by the CPCM signal being decoded. 
     The signal sample v s  &#39; and its complement, -v s  &#39;, are extended to an output filter 46 via a polarity select network 44. The signal TS4 provided by timing control 52 enables the polarity select network 44 of the decoder 14 to respond to the sign circuit 34 to assign the proper polarity to the signal sample as extended to the output circuit 46. 
     The polarity select network 44 responds to a sign bit indicating positive polarity to permit the signal sample v s  &#39; to be extended directly to the output circuit 46 and to a sign bit indicating negative polarity to permit the signal sample -v s  &#39; to be extended to the output circuit 46. The output circuit 46 includes a low pass filter which produces a smooth continuous analog signal from the analog samples supplied thereto during successive codec operating cycles. 
     The timing logic signals generated by timing control 52 of FIG. 1 and their interrelationship are depicted in timing diagram of FIG. 2, wherein a full 125 microsecond cycle of operation of the illustrative codec is set out. It is to be noted with respect to FIG. 2, that the time periods shown are not drawn to scale, but are set out in a way to describe the successive timing steps utilized in the codec of the instant invention. 
     Referring to FIG. 1 and FIG. 2, the basic clock for stepping encoder counter 24 and decoder counter 32 delivers a 1.544 MHz pulse train, or 193 pulses per 125 microseconds cycle of codec operation, at path FC. 
     At the initiation of the 125 microsecond cycle, a logic ONE signal of 2 microsecond width is presented at path TS0 by timing control 52. This TS0 pulse is used to preload the decoder counter 32 with the input CPCM data word appearing at path 76&#39; and to register the sign bit presented at path 74&#39; into sign circuit 34. 
     At the end of the two microsecond TS0 pulse, an 8 microsecond logic ONE pulse is presented at path TS1 by logic control 52. During this interval, TS1 at logic ONE functions to place sample and hold circuit in the sampling mode to track the system analog inputs v i  to obtain the next potential level for encoding into CPCM format. Additionally, TS1 is utilized to clear the contents of encoder counter 24 in preparation for a new encoding operation. 
     Approximately 2 microseconds after the conclusion of the system input sampling interval defined by TS1, timing control 52 generates a new CPCM 8 microsecond logic ONE pulse at path TS2. The TS2 8 microsecond pulse is used to initialize the reference voltage v r  of companding generator 18 to the maximum value in preparation for capacitive discharge during the encoding and decoding operations. At the conclusion of the TS2 pulse, TS3 goes to logic ONE (point 200 of FIG. 2) for an interval of 89.2 microseconds. At this time, the actual encoding and decoding processes commence at counters 24 and 32, respectively. For the illustrative embodiment, a 7-bit code is utilized for the CPCm code magnitude, corresponding to a maximum count during TS3 of 128 FC pulses at 1.544 MHz, hence the TS3 interval of 89.2 microseconds. During the TS3 pulse, encoder counter 24 increments until the reference voltage v r  from companding generator 18 decays to a value equal to the magnitude of the sampled analog input v s . Simultaneously, during the TS3 pulse, decoder counter 32 decrements from its present value down to zero, at which time a logic ONE state is placed on path TB by counter 32 at a point such as M of FIG. 2. Depending on the initial CPCM word loaded into counter 32, point M may occur as early as point 201 (all zero code word) or as late as point 202 (all 1&#39;s code word). When TB goes to logic ONE, sample and hold circuit 40 is switched from track to hold, dual polarity genertor 42 delivers +v s , and -v s  &#39; at its output -- where v s  &#39; is the magnitude of the decoded signal level. 
     Approximately 2 microseconds after the conclusion of the TS3 pulse, timing control 52 generates a 20 microsecond logic ONE pulse at its path TS4. The TS4 pulse is utilized to enable polarity select circuit 44 gate the properly signed analog voltage level v s  &#39; to the output circuit 46 and thence to the system&#39;s analog output at path 116. At the conclusion of the TS4 pulse, the 125 microsecond cycle of codec operation is complete, and the sequence beginning with the TS0 pulse, is restarted for the next operating cycle. 
     DETAILED DESCRIPTION 
     The detailed description of the codec of the illustrative embodiment is best undertaken in conjunction with the logic level timing diagram of FIG. 2 and the schematics of FIGS. 3A, 3B, and 3C, arranged as shown in FIG. 3D. 
     Encoder Section Structure -- FIG. 3A 
     Referring to FIG. 3A, which includes a schematic representation of the encoder 12, the analog input signal v i  is extended to the sample and hold circuit 16 over low pass filter 17 and its output stage 17&#39;. The filter 17 may be an active filter having a bandwidth corresponding to the limit frequency of the time-varying analog signal v i  to be encoded. In the present example, where it is assumed that the analog signals are voice-frequency signals, the bandwidth of the filter 17 may correspond to the frequency limit of the voice band. 
     The illustrative sample and hold circuit 16 shown in FIG. 3A includes holding capacitor CH1 and sampling switch SW1, which is embodied as a pair of FET transistors Q1, and Q1&#39;, which when enabled, connect one side of the capacitor CH1 to the output of the output stage 17&#39; of filter 17 to receive the voice-frequency signals v i  input to the encoder at path 1. The enabling of the FET devices Q1 and Q1&#39; is controlled by a switch control circuit SC1, including transistors Q11 through Q14 and associated bias resistors 161 through 167. Signal path TS1 from timing control 52 of FIG. 3B is coupled to the emitter of Q14. During the sampling interval, a logic ONE comprising a ground potential low impedance signal on path TS1 causes transistors Q11 through Q14 to be cut off, which biases the FET devices Q1 and Q1&#39; to the low impedance &#34;on&#34; condition permitting sampling of the analog input signal v i  by capacitor CH1. During the holding interval, a logic ZERO comprising an open high impedance signal on path TS1, causes transistors Q11 - Q14 to conduct, thereby biasing the FET devices Q1 and Q1&#39; to a high impedance &#34;off&#34; condition. A compensation capacitor CC1 compensates for charge current via the parasitic capacitance of FET device Q1&#39;. 
     The sampling circuit 16 further includes a pair of operational amplifiers OP1 and OP2, such as the National Semiconductor Types 310 and 318, respectively, which respectively provide complementary output signals v s  and -v s , where v s  corresponds to the magnitude of the signal voltage across the holding capacitor CH1. 
     Amplifier OP1, which is connected for operation as a voltage follower, has a non-inverting input 55 connected at point 56 to one side of capacitor CH1, the other side of which is connected to ground. The output 56 of the amplifier OP1 is connected directly to the inverting input 53 of amplifier OP1 and to biasing resistor 166 of switch control SC1. 
     The output 57 of amplifier OP1 is also connected via path 57A and resistor R1 to the inverting input 58 of amplifier OP2, which has its non-inverting input 59 connected over a resistor R2 to ground, and its output 60 connected over a resistor R3 to the inverting input 58. Resistors R1 and R3 are of equal resistance, providing unity gain for the amplifier OP2 which operates in the inverting mode. 
     The outputs 57 and 60 of respective amplifiers OP1 and OP2 are further respectively connected to inverting inputs 61 and 62 of a pair of operational amplifiers CP1 and CP2, which comprise the comparator circuit 20. The noninverting inputs 63 and 64 of the amplifiers CP1 and CP2 are commonly connected via path 634a to the output of the companding generator 18 of FIG. 3B. The amplifiers CP1 and CP2 may, for the sake of example, be the National Semiconductor Type 311, which are chosen for high speed and small offset voltage. 
     The gate control 26 of FIG. 1 is comprised of NAND gates G1 and G2 and inverter G1&#39; shown in FIG. 3A. The sign circuit 28 of FIG. 1 is comprised of a set-reset flip-flop also designated 28 in FIG. 3A. The output of comparator amplifier CP1 is extended via path 66 to a first input gate G1 and to the S, or SET, input of sign flip-flop 28. The output of comparator amplifier CP2 is extended via path 68 to a second input of gate G1 and to the R, or reset, input of sign flip-flop 28. 
     The output of gate G1 is coupled, by inverter G1&#39;, to a first input on NAND gate G2. The second and third inputs of G2 are respectively coupled to control signal paths FC and TS3 of timing control 52 of FIG. 3B. The output of gate G2 is coupled to the incrementing, or up-count, input (INC CLK) of encoder counter 24. The clear (CLR) input of counter 24 is coupled to control signal path TS1. 
     The encoder&#39;s CPCM output is furnished at system output 30 which comprises the outputs 241 of encoder counter 24, shown collectively at path 76, and a sign bit on path 74 coupled from the true, or &#34;1&#34;, output of sign flip-flop 28. 
     Decoder Section Structure -- FIG. 3C 
     A schematic representation of the decoder section 14 is shown in FIG. 3C. The magnitude bits of the CPCM code word to be decoded are presented via path 76&#39; to the data inputs 321 of decode counter 32, while the sign bit of the word to be decoded is coupled to decoder sign D-type clocked flip-flop 34 at its D input via path 74&#39;. The data at counter inputs 321 of counter 32 is effectively registered at the counter whenever a logic ONE is present on control signal path TS0 from timing control 52 of FIG. 3B. Additionally, TS0 is coupled to the clock, or C, input to gated D-flip-flop 34 to simultaneously register the sign bit appearing on path 74&#39;. 
     Decoder counter 32 is selected such that a negative going pulse at its DEC-CLK input will decrement the preloaded contents by one count. The borrow, or B, output of counter 32 presents a logic ZERO to logic ONE transition when the counter 32 has decremented through an all-zero state. Decrementing pulses are coupled to the DEC-CLK input of counter 32 from the output of NAND gate 38 whose three inputs are respectively couple to signal path FC from timing control 52 of FIG. 3B, signal path TS3 from timing control 52 of FIG. 3B, and the B output of counter 32, inverted by inverter 38A. Gates 38 and 38A OF FIG. 3C are seen to correspond to the gate control circuit 28 of the block diagram of FIG. 1. 
     Decoder section 14 of FIG. 3C further includes a sample and hold circuit 40 which includes a holding capacitor CH2, compensating capacitor CC2, and a sampling switch SW3 and associated switch control SC3. SW3, in turn, is embodied as a pair of field effect transistors Q3 and Q3&#39; and SC3 includes transistors Q16 through Q19 and their associated biasing resistors 401 through 407. A logic level ZERO (comprised of low impedance ground) at the B output of counter 32 is coupled via signal path TB to the emitter of Q19 of SC3, thereby rendering Q16 through Q19 non-conductive which, in turn, biases the FET devices Q3 and Q3&#39; to the low impedance &#34;on&#34; state, thus permitting tracking of the reference voltage v r  appearing on path 624B for the output of companding generator 18 of FIG. 3B. When decoder counter 32 has decremented to the all zero state, the logic ONE is presented via path TB to render Q16 through Q19 conductive, thereby forcing SW3 to the high impedance state to hold the voltage at a level v s  &#39; -- that potential to which v r  from the companding generator 18 of FIG. 3B has decayed during the decrementation of decoder counter 32. 
     The tracked and held potential v s  &#39; across capacitor CH2 is coupled to dual polarity generator 42 which includes a pair of operational amplifiers OP3 and OP4. OP3 and OP4 may, for example, be respectively chosen as National Semiconductor Types 310 and 318. Amplifier Op3, which is arranged for operation as a voltage follower, has a non-inverting input 95 coupled to one side of hold capacitor CH2. The output 97 of OP3 is coupled directly to the inverting input 93 of OP3. 
     The output 97 of OP3 is also coupled via resistor R21 to the inverting input 98 of amplifier OP4, which has its non-inverting input 99 coupled to ground via resistor R22 and its output 100 coupled via resistor R23 to its inverting input 98. R21 and R23 are selected to be of equal resistance, thereby providing OP3 with a gain of -1. Hence, OP3 and OP4 respectively provide the required dual outputs of polarity generator 42 of +v s  &#39; and -v s  &#39; . 
     The polarity select network 44, under the control of sign flip-flop 34, enables the selection of one of the output signals provided by the amplifiers OP3 and OP4 to provide a signal of a desired polarity to the ouput circuit 46. The output select network 44 includes a pair of switches SW4, and sW5, embodied as field effect transistors Q4 and Q5, respectively, which are normally maintained in a high impedance or &#34;off&#34; condition. The FET devices have associated switch control circuits including biasing resistors 441 through 444 and transistors Q6 and Q7, enabling of which is respectively controlled by AND gates G33, G34, and the logic state appearing on control signal lead TS4 from timing control 52 of FIG. 3B. Gate 33 has a first input connected to the true output of the sign flip-flop 34, and a second input connected to control signal path TS4. Gate 33 is enabled by the signal on TS4 whenever the sign flip-flop 34 is set, thereby enabling transistors Q6 to switch FET device Q4 to an &#34;on&#34; or low impedance state to connect the output of amplifier OP3 over resistor R24 to an input 106 of the output circuit 46, extending the positive polarity sample signal v s  &#39; to the output circuit. 
     Similarly, gate G34 has a first input connected to the false output of the sign flip-flop 34 and a second input connected to TS4, to be enabled by TS4 whenever the sign flip-flop 34 is reset. Gate G34, in turn, enables transistor Q7 to switch transistor Q5 to a low impedance state to connect the output of amplifier OP4 over a resistor R25 to the input 106 of the output circuit 46, thereby extending the negative polarity sample signal -v s  &#39; to the output circuit 46. 
     The output circuit 46 comprises an active filter 114 of proper input impedance and operational amplifier OP5. A resistor R26 is connected between the output 112 of the amplifier OP5 and the input 113, and a resistor R27 is connected between input 115 of amplifier OP5 and ground. 
     Resistors R24, R25, R26, and R27 are selected to provide output amplifier OP5 with a gain sufficient to compensate for the fact that the output signal is presented to the filter 114 for only a fraction of the codec&#39;s operating cycle (e.g. 20/125 in the illustrative embodiment). The output 112 of OP5 is coupled to low path filter 114 whose output at path 116 comprises the desired decoded analog signal. 
     Timing Control and Companding Generator -- FIG. 3B 
     Timing control 52 of FIG. 1 is depicted in more illustrative detail in FIG. 3B. There are numerous alternatives available, well known in the art, that may be used to generate the basic logic timing pattern depicted in FIG. 2. For the illustrative embodiment as partially set out in FIG. 3B, it is seen that timing control 52 is, for this example, comprised of a chained set of monopulsers and two basic clock circuits operating at b 1.544 MHz and 8 KHz, respectively. 
     Referring to FIG. 3B, clock circuit CLK1 has its output coupled to control signal path FC for distribution of clock pulses at a 1.544 MHz rate, said pulses used for the bsic counting rates in the encoding and decoding process of the illustrative codec. 
     Clock circuit CLK2 produces a positive-going transition, at a rate of 8 KHz at its output 520 to thereby trigger the input 521 of monopulser MP0, resulting in a 2 microsecond logic ONE pulse at the output 522 of MP0 every 125 microseconds-- the basic cycle time of the codec. MP0 output 522 is coupled to control signal path TS0 and to input 523 of monopulser MP1. 
     Monopulser MP1, in response to the negative-going termination of the MP0 pulse at input 523, delivers an 8 microsecond logic ONE pulse at its output 524, which is coupled to control signal path TS1 and to input 525 of monopulser MPA. 
     Monopulser MPA delivers a 2.05 microsecond logic ONE pulse at its output 526 in response to the negative-going termination of the MP1 8 microsecond pulse. Output 526 of MPA is coupled to the input of 527 of monopulser MP2 which produces an 8 microsecond logic ONE pulse at its output 528, in response to the negative-going termination of the MPS pulse coupled to input 527 of MP2. Output 528 of MP2 is coupled to control signal path TS2 and to input 529 of monopulser MP3. 
     Monopulser MP3 delivers an 82.9 microsecond logic ONE pulse at its output 530 in response to the negative-going termination of the MP2 pulse coupled to input 529 of MP3. Output 530 of MP3 is coupled to control signal path TS3 and to input 531 of monopulser MPB. MPB delivers a 2.05 microsecond logic ONE pulse at its output 532 in response to the negative-going termination of the MP3 pulse coupled to input 531 of MPB. Output 532 of MPB is coupled to input 533 of monopulser MP4. 
     Monopulser MP4 delivers a 20 microsecond logic ONE pulse at its output 534 in response to the negative-going termination of the MPB pulse coupled to iput 533 of MP4. Output 534 of MP4 is coupled to control signal path TS4. Thus, it is seen from the above structure that the 125 microsecond operating cycle timing waveforms of FIG. 2 may be repetitively generated by the monopulser logic and clock circuits comprising the timing control 52 of FIG. 3B. 
     The companding generator 18 includes a reference source 75, control switch SW2, resistor network R, capacitor C, and a buffer amplifier 73. The control switch SW2, which may, for example, be embodied as a Type 2N2904 transistor Q2 operating in the switching mode, is operable and enabled to connect one side of capacitor C at point 65&#39; to a fixed reference potential +E provided by the reference source 75 at node 189. The other side of capacitor C is connected to ground. The reference source 75 comprises an operational amplifier 78, a 9 volt zener diode Z1, and emitter follower utilizing transistor Q15, and associated bias resistors 180 through 185, which derive a constant voltage E of 10 volts from a 15 volt supply. 
     Resistor network R is connected between point 65&#39; and the -dE. potential -dE. Resistor R comprises a voltage divider formed by resistors R15 - R17, resistors R15 - R16 being connected in series between point 65&#39; and ground, and resistor R17 being connected between the junction of resistors R15 and R16, indicated at -dE and a source of -15 vdc. The value of R is equal to: ##EQU4## By making resistor R16 very small compared to resistor R15, and resistor R17, the voltage -DE is approximately equal to: ##EQU5## 
     The enabling of transistor Q2 is controlled by the logic level appearing on control signal path TS2 from the timing control circuit 52 which causes transistor Q2 to conduct for the charging of capacitor C for a predetermined duration. 
     When the switch SW2 is closed, capacitor C charges to the potential +E. When the switch SW2 is opened at the end of the sampling interval, capacitor C discharges over resistance R towards the potential -dE, with a time constant determined by the capacitor C and resistance R. 
     The voltge v r  across the capacitor C may be expressed by: 
     
         v.sub.r = -dE + (1+d)E· e.sup.- t/T. 
    
     where T is the time constant for capacitor C and the resistance R. Rearranging terms, and dividing by dE gives: ##EQU6## The signal sample voltage v s  can be expressed as a relative amplitude &#34;x&#34; out of a full scale voltage v 0 , that is v s  = xv 0 . In accordance with the present invention, the voltage v r  is compared with the signal sample voltage v s , and the time t, as a function of x is determined by the time at which the capacitor voltage v r  has decreased to the value of v s , that is when v r  = xv 0 . Substituting this valve for v r  into equation (3), in taking the natural logarithms that both sides of the equation results in: ##EQU7## 
     The terms v 0 , d, and e are constants, and accordingly, can be chosen such that v 0  /dE = μ. Substituting this value into equation (4) yields: ##EQU8## 
     Transposing terms and substituting d =  v 0  /μ E into equation (5) yields: ##EQU9## 
     Then, choosing E = v 0 , and dividing both sides of the equation (6) by 1n(1+μ) yields: ##EQU10## Introducing the time T&#39; = T·1n(1+μ) gives: ##EQU11## Now, note the previously discussed formula for the μ-Law: ##EQU12## Comparing equations (8) and (1), it is evident that y in the continuous companding law, equation (1), equals complement of the relative time t/T&#39;. In other words, by choosing E equal to the full scale voltage v 0  of the signal to be encoded, setting d = 1/255, and choosing the clock frequency for the digital counters such that the maximum count of the counter, that is 64, 128, etc., is obtained during a time T1n(1+μ), then the contents of the counter at coincidence between v r  and the absolute value of signal sample v s  directly represents the 6 or 7 bits of the desired CPCM code to which only a sign bit need be added. The codec of the illustrative embodiment uses a 1.544 MHz clock rate and a 7-bit magnitude portion for the CPCM code. Hence the maximum count allowable is 2 7  =128, corresponding to a maximum counting interval of 89.2 microseconds, a value which must be equated to RC1n(1+μ) in selecting the various parameters for companding generator 18. 
     Encoder Operation -- FIGS. 2, 3A, 3B 
     A step-by-step description of the encoding procedure for the codec of the illustrative embodiment is best set out with reference to the timing diagram of FIG. 2 and the schematic diagrams of the encoder section 12 and companding generator 18 of FIGS. 3A and 3B, respectively. 
     As seen from FIG. 2, the 125 microsecond codec operating cycle is initiated by the 2 microsecond TSO pulse. During TS0 time, the contents of encoder counter 24 (FIG. 3A) and the value of the sign bit, as determined by the previous operation cycle, may be sent to a distant decoding entity via paths 76 and 74, respectively. 
     At the conclusion of the TS0 pulse, the encoder sampling function is initiated by the logic ONE pulse at path TS1. Logic ONE at TS1 is coupled to the emitter of Q14 (FIG. 3A) to render transistors Q11 through Q15 nonconductive, thereby placing the source to drain states of Q1 and Q1&#39; in the low impedance sampling state, wherein the analog input potential at the output of amplifier 17&#39; is followed by sampling capacitor CH1. Additionally, during the TS1 pulse, encoder counter 24 is reset to the all ZERO condition by coupling TS1 to the CLR input of counter 24 in preparation for encoding of the analog signal presently being sampled. 
     At the termination of the TS1 8 microsecond sampling interval, transistors Q1 and Q1&#39; assume the high impedance state to effectively hold the sample analog input at capacitor CH1. The sampled analog input v s  is presented to the inverting input 61 of comparator amplifier CP1 via operational amplifier OP1, while the complement of the voltage sample -v s  produced at the output of operational amplifier OP2, is presented to the inverting input 62 of comparator amplifier CP2. 
     After a settling time of approximately 2.05 microseconds (provided by monopulser MPA of FIG. 3B), an 8 microsecond logic ONE pulse is coupled via TS2 to initialize companding generator 18 of FIG. 3B. Logic level ONE at TS2 is coupled via resistor 186 to the base of transistor Q2 rendering it conductive. Reference voltage +E at node 189 is developed by reference source 75. Hence, when Q2 is rendered conductive during the TS2 pulse, capacitor C is charged to a initial level of +E volts. 
     At the conclusion of the TS2 pulse, an 89.2 microsecond logic ONE pulse is generated at TS3. At this time, Q2 of companding generator 18 is switched &#34;off&#34; thereby initiating a discharge of capacitor C toward a potential -dE developed by resistor network R at a discharge time constant T=RC. Simultaneously, at the initiation of the TS3 pulse, gate G2 (FIG. 3A) is enabled via path TS3 to pass pulses from FC to begin incrementing encoder counter 24. 
     Durng the encoder counting interval, comparator amplifiers CP1 and CP2 continuously compare the capacitively discharging reference voltage v r , provided by companding generator 18 via path 634A, with +v s  and -v s , respectively. First assume the sample v s  was of positive polarity. Then when v r  discharges to a level substantially equal to v s , the output 66 of CP1 goes low to (1) force the output of NAND gate G1 high which, in turn, via inverter G1&#39;, locks the output of G2 high to inhibit further incrementation of encoder counter 24, and (2) set the sign flip-flop 28 to indicate positive polarity of the analog input sample. Alternatively, if the sample v s  was of negative polarity, then when v r  discharges to a level substantially equal to -v s , the output 68 of CP2 goes low to inhibit further incrementation of encoder counter 24 via G1 and G1&#39; and to reset the sign flip-flop 28 to indicate negative polarity of the analog input sample. 
     Hence, at coincidence of v r  with the magnitude of v s , the contents of encoder counter 24 presented at counter outputs 241, along with the sign indicator bit taken at path 74 from the true output of flip-flop 28 comprise the desired CPCM encoding result which is available at data link 30 until the recurrence of timing control pulse TS1 in the next cycle of codec operation. 
     Decoder Operation -- FIGs. 2, 3B, 3C 
     In accordance with the instant invention, the decoder section 14 (FIG. 3C) operates contemporaneously with the encoder section 12 (FIG. 3A) in conjunction with the shared companding generator 18 (FIG. 3B) and a timing control circuitry 52 (FIG. 3B) which generates the basic logic timing waveforms depicted in FIG. 2. 
     As mentioned in conjunction with the encoder section, at the initiation of the 125 microsecond operation cycle, a 2 microsecond logic ONE pulse is provided by timing control 52 at path TS0. The decoder section 14 of FIG. 3C utilizes logic ONE at TS0 to transfer the magnitude portion of the CPCM code word to be decoded into decoder counter 32 at data inputs 321 and to register the sign bit of the input code word at D flip-flop 34. With the newly-loaded inputs to counter 32 being registered therein, the B output is logic ZERO (low impedance ground) which, via path TB to the emitter of Q19, renders Q16 through Q19 non-conductive, thereby placing the switch SW3 (comprising transistors Q3 and Q3&#39;) in the low impedance tracking state. While in the track state, capacitor CH2 will assume a potential substantially equal to the companding generator reference voltage v r  supplied over path 634B. 
     While the encoder 12 is performing the sampling function during the TS1 pulse, and while the companding generator 18 is being initialized during the TS2 pulse, as described hereinabove, the decoder 14 maintains the state assumed during the TS0 pulse. 
     With the initiation of a logic ONE signal at path TS3, NAND gate 38 is enabled to pass clock pulses at a rate set by signal path FC to the DEC-CLK input of decoder counter 32. Negative-going pulses at DEC-CLK decrement counter 32 from its preset value determined according to the input CPCM code word to be decoded. Hence, it is seen from FIGS. 3A, 3B, and 3C that decoder counter 24 begins incrementation at the same time that decoder counter 32 begins the complementary function of decrementation, while a single reference voltage v r  is monitored by both the decoder and the encoder. 
     When decoder counter 32 has decremented from its originally loaded state to the all-ZERO state, counter output B provides a high-impedance logic ONE signal to path TB which places SW3 in the high impedance hold state by turning on transistors Q16 through Q19, and inhibits further counter decrementation by providing a logic ZERO input to NAND gate 38 via inverter 38A. This time point is shown, by example, to be point M of the TB waveform of FIG. 2. At time M, the voltage across hold capacitor CH2 represents the potential magnitude, v s  &#39;, of the decoded signal. 
     Dual polarity generator 42 of the decoder is comprised of operational amplifiers OP3 and OP4. Positive v s  &#39; is developed at output 97 of OP3, while -v s  &#39; is developed at output 100 and OP4. Signals v s  &#39; and -v s  &#39; are respectively coupled to resistors R24 and R25 of polarity select circuit 44. 
     During the final 20 microseconds of the codec operation cycle, appropriately-signed v s  is gated to output circuit 46 by switch SW4 (transistor Q4) or switch SW5 (transistor Q5). During the said 20 microseconds, logic ONE at TS4 primes AND gates G33 and G34 for operation dependent upon the value of the received CPCM signed bit at flip-flop 34. If the sign bit is ONE, gate G33 is enabled during the  TS4 pulse to close SW4 via transistor Q6, thereby passing +v s  &#39; from OP3 to input 113 of output circuit operational amplifier OP5. Alternatively, if the sign bit is ZERO, gate 34 will be enabled during the TS4 pulse to close SW5 via transistor Q7, thereby passing -v s  &#39; from OP4 to input 113 of OP5. OP5 and low pass filter 114 provide appropriate amplification and smoothing for presenting a suitable decoded continuous analog signal to system output 116 over successive 125 microsecond decoding periods. 
     It should be noted that the invention described herein has been illustrated with reference to a particular embodiment. It is to be understood that many details used to facilitate the description of such a particular embodiment are chosen for convenience only and without limitation on the scope of the invention. Other embodiments may be devised by those skilled in the art without departing from the scope and spirit of the invention. For example, the desired timing waveforms of FIG. 2 may be generated by numerous techniques in addition to the specific chained-monopulser approach described. Furthermore, the illustrative embodiment is arranged to generate a so-called &#34;complementary&#34; CPCM code, wherein maximum analog signal magnitude is represented by the all-ZERO code word, while minimum analog signal magnitude is represented by all-ONE&#39;s. It would be relatively simple to achieve an alternative arrangement wherein a straight binary CPCM representation is encoded -- i.e. where a minimum magnitude would correspond to the all-ZERO code word and the maximum magnitude would correspond to all ONE&#39;s code. This would be accomplished by proper manipulation of the counter outputs (e.g. logical inversion or alternatively, by counting down from a preset maximum rather than counting up from ZERO during the encoding state). 
     Accordingly, the instant invention is intended to be limited only by the scope and spirit of the appended claims.