Display device
BACKGROUND OF THE INVENTION 
     The present invention relates to a display device using liquid crystal display elements, for use in an instrument panel on a vehicle and more particularly to a display device which has improved resolution irrespective of the number of the display elements in the case where the velocity of a vehicle, r.p.m. of the engine, temperature, quantity of residual fuel and current are displayed by the lighting of display elements. 
     The conventional display device using liquid crystals has satisfactory resolution only when the number of liquid crystal elements therein is rather small, but if a relatively large number of liquid crystal elements are used, satisfactory resolution cannot be obtained for each comparision circuit so that the exact control of lighting of the elements is impossible. Moreover, the conventional display device is not preferable in the case where complementary MOS (CMOS) devices having high threshold levels are used as comparison circuits since in such a case the number of display elements capable of being lit is also limited. 
     SUMMARY OF THE INVENTION 
     One object of the present invention is to eliminate the drawbacks of a conventional display device. 
     Another object of the present invention is to provide a display device having high resolution. 
     According to a first aspect of the present invention, each of a number of input analog quantities is divided into plural ranges and the input quantity belonging to each of the plural ranges is amplified over a predetermined amplitude range, e.g., from minimum to maximum of the initial input analog quantity, to improve the resolution over the whole extent of the varying ranges of the input quantities. 
     According to a second aspect of the present invention, there is provided a display device for displaying input analog quantities by lighting luminescent display elements, comprising an input terminal for receiving the input analog quantities; a plurality of display elements for displaying the input analog quantities; an arithmetic circuit for dividing each of the input analog quantities into plural ranges and for amplifying each of the divided input quantities up to a predetermined level; a circuit for dividing the predetermined level into plural levels; comparison circuits each provided for the respective divided levels, for determining the lighting of the display elements by comparing the divided levels with a reference signal; a circuit for generating a clock signal for determining the timing of the lighting of the display elements; and drive circuits for deliverying effective voltages for lighting the display elements in response to the output signals of the comparison circuits and the clock signal. 
     According to a third aspect of the present invention, there is provided a display device for displaying input analog quantities by lighting luminescent display elements, comprising an input terminal for receiving the input analog quantities; a plurality of display elements for displaying the input analog quantities; first operational amplifiers each dividing each of the input analog quantities into plural ranges and amplifying each of the divided input quantities up to a predetermined level; voltage dividing circuits each provided for the respective plural ranges, for dividing each of the outputs of the first operational amplifiers into plural voltage levels: 2-input AND circuits for determining the lighting of the display elements by comparing the plural voltage levels with a reference voltage level; second operational amplifiers connected between the output terminals of the first operational amplifiers and the input terminals of the voltage dividing circuits, for offsetting the threshold voltages of the AND circuits; a circuit for generating a clock signal for determining the timing of the lighting of the display elements; and drive circuits connected between the output terminals of the AND circuits and the display elements, for delivering effective voltages for lighting the display elements in response to the output signals of the AND circuits and the clock signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1a shows a circuit of a display device disclosed in our co-pending U.S. patent application Ser. No. 768,346, filed on Feb. 14, 1977, entitled &#34;A circuit for actuating a display with an improved comparator,&#34; used in the case where the number of display elements being used is relatively small. 
     FIG. 1b illustrates the relationship between the input voltage of the display device and the values to be displayed by lighting the liquid crystal elements of the display elements. 
     FIG. 2 shows in block diagram a circuit of a display device according to the present invention. 
     FIG. 3 shows a circuit of a display device as an embodiment of the present invention. 
     FIG. 4 illustrates the relationship between the output voltages of the operational amplifiers and the values to be displayed by lighting the liquid crystals elements, in the display device shown in FIG. 3. 
     FIG. 5 shows a circuit of a display device as another embodiment of the present invention. 
     FIG. 6 illustrates the relationship between the output voltages of the operational amplifiers and the values to be displayed by lighting the liquid crystal elements, in the display device shown in FIG. 5. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The display device disclosed in the co-pending U.S. patent application Ser. No. 768,346 has a structure as shown in FIG. 1a. For a better understanding of the present invention, the display device shown in FIG. 1a will first be described. 
     In FIG. 1a, reference character Q designates an input terminal, character R 1  a resistor connected at its one end with the input terminal Q, character R 2  a resistor connected with the resistor R 1  at its one end and with another resistor R 3  at its other end. The resistor R n  is connected at its one end with the resistor R n-1  ; and the resistor R n+1  connected at its one end with the resistor R n  and grounded at its other end. 
     The operation of this circuit is as follows. 
     Let the input voltage at the input terminal Q be represented by V in  and let the resistance values of the resistors R 1  -R n+1  be represented respectively by r 1  -r n+1 . Then, the voltages V R1-  V Rm  at the junction points of the resistors are given by the following expressions. ##EQU1## 
     Consequently, the input voltage V in  is divided according to the resistance values of the respective resistors. In FIG. 1a, AND circuits G 1  -G n  each having two inputs serve as comparison circuits. The AND circuit G 1  has its two input terminals connected respectively with one end of the resistor R 1  and one end of the resistor R 2 . The AND circuit G 2  has its two input terminals connected respectively with one end of the resistor R 2  and one end of the resistor R 3 . In like manner, the j-th AND circuit G j  has its two input terminals connected respectively with the resistors R j   and R j+1  and the n-th AND circuit G n  has its two input terminals connected respectively with the resistors R n  and R n+1 . 
     In this comparison circuit constituted of 2-input AND circuits, the operation of the j-th AND circuit G j  is as follows. 
     In general, a digital element has a level (threshold level) at which the states of the element is switched over from one to another and if it is assumed that the threshold level of the j-th 2-input AND circuit G j  is V L  and that the input voltages at the input terminals are V RJ  and V Rj+1  (V Rj  &gt; V Rj+1 ), then the output level of the j-th AND circuit G j  is &#34;High&#34; when V L  &lt; V Rj , V Rj+1 , but &#34;Low&#34; when V Rj+1  &lt; V L  &lt; V Rj  or V L  &gt; V Rj , V Rj+1 . Accordingly, the output signal of the AND circuit G j  is determined in accordance with the relationships among the values V Rj  and V Rj+1  given by the expressions (1) and the threshold level V L . 
     Therefore, if the threshold levels of all the 2-input AND circuits G 1  -G n  are set to be a constant value, the voltages V Rj  and V Rj+1  are varied in accordance with the input voltage V in  so that the output signals of the 2-input AND circuits G 1  -G n  can be sequentially changed in accordance with the relationships of V Rj  and V Rj+1  to the threshold level V L . 
     In FIG. 1a, an oscillation circuit C for generating a clock signal determines the frequency for driving liquid crystal elements used as display elements. A driver circuits is constituted of exclusive OR circuits E 1  -E n . The exclusive OR circuit E 1  has its two input terminals connected respectively with the output terminal of the 2-input AND circuit G 1  and the output of the oscillation circuit C. The exclusive OR circuit E 2  has its two input terminals connected respectively with the output terminal of the 2-input AND circuit G 2  and the output terminal of the oscillation circuit C. Similarly, the j-th exclusive OR circuit E j  has its two input terminals connected respectively with the output terminal of the j-th 2-input AND circuit G j  and the output terminal of the oscillation circuit C. And the n-th exclusive OR circuit E n  has its two input terminals connected respectively with the output terminal of the n-th exclusive OR circuit E n  has its two input terminals connected respectively with the output terminal of the n-th 2-input AND circuit G n  and the output terminal of the oscillation circuit C. 
     The operation of this circuit is as follows. The exclusive OR circuit delivers an output of &#34;Low&#34; level when its two digital input signals are at the same level (of the same phase) and an output of &#34;High&#34; level when the two input signals have different levels. Namely, each exclusive OR circuit delivers the output of &#34;Low&#34; level when the output signal of the associated 2-input AND circuit is in phase with the output signal of the oscillation circuit C, and the output of &#34;High&#34; level when the signals are opposite in phase to each other. 
     In FIG. 1a, members D 1  -D n , LC 1  -LC n  and D&#39; 1  -D&#39; n  constitute liquid crystal display elements. The electrodes D 1  -D n  of the liquid crystals LC 1  -LC n  are connected with the output terminals of the associated exclusive OR circuits E 1  -E n  and the electrodes D&#39; 1  -D&#39; n  of the liquid crystals LC 1  -LC n  are connected with the output terminal of the oscillation circuit C. 
     The operation of this circuit arrangement is as follows. The liquid crystal display elements are operated through the application of ac waveforms. Concerning the j-th liquid crystal LC j  having electrodes D j  and D&#39; j , when the output signal of the j-th exclusive OR circuit E j  connected with the electrode D j  is in phase with the output signal of the oscillation circuit C, that is, when the output signal of the j-th 2-input AND circuit G j  has the &#34;Low&#34; level, the signal applied to the other electrode D&#39; j  is in phase with the output signal of the oscillation circuit C so that the liquid crystal LC j  is not supplied with the effective voltage and the liquid crystal LC j  is not lit. 
     On the other hand, when the output signal of the j-th exclusive OR circuit E j  connected with the elecrode D j  is opposite in phase to the output signal of the oscillation circuit C, that is, when the output of the j-th 2-input AND circuit G j  is at the &#34;High&#34; level while the output of the oscillation circuit C is at the &#34;Low&#34; level, the signal supplied to the other electrode D&#39; j  is in phase with the output signal of the oscillation circuit C, i.e., at the &#34;Low&#34; level, the effective voltage is applied to the liquid crystal LC j  to light it up. 
     Accordingly, in the comparison circuit, the divided voltages derived from the input voltage V in  in accordance with the expression (1) are compared with the threshold voltages of the respective 2-input AND circuits and when the divided voltages applied to the two input terminals of each AND circuit are greater than the threshold voltage of the AND circuit, the effective voltage is applied to the liquid crystal display element associated with the AND circuit to light the liquid crystal while when one of the divided voltages is smaller than the threshold voltage, no effective voltage is applied to the liquid crystal so that the liquid crystal is not lit. 
     FIG. 1b shows the relationship between the input voltage and the values to be displayed when the liquid crystals are lit. 
     In FIG. 1b, reference characters D LC1-  D LCn  may represent, for example, the levels of the input voltage displayed by the lighting of the respective liquid crystal display elements. The same threshold voltage of all the 2-input AND circuits, i.e., the reference voltage level of the comparison circuit, is indicated by the reference character V L , which is 45-50% of the power source voltage in the case of, for example, AND gates. 
     The above description is given to the display device disclosed in the co-pending application with the present invention. With the circuit configuration described above, if there are used a relatively small number of liquid crystal display element to be lit, resolution is satisfactory for all the values to be displayed with respect to the range of the input voltage. However, if a comparatively large number of such elements are used, resolution for the respective comparison circuits is not sufficient so that the exact control of the lighting of the display elements is impossible. The reason for this is that since for a greater number of display elements the threshold level of the logic element, e.g., AND gates, serving as comparison circuits fluctuates within a range of at least 5% as described above, the maximum input level is limited by the maximum allowable input voltages of the logic elements. Moreover, with this circuit configuration, the use of complementary MOS (CMOS) devices having a high threshold level as comparison circuits would further limit, that is, decrease the number of display elements in order to keep the resolution unchanged. 
     FIG. 2 is a block diagram of the circuit configuration of a display device according to the present invention. In FIG. 2, reference numeral 1 indicates an input terminal of the display device; 2 an arithmetic circuit for dividing the input analog quantity of the display device into plural ranges and for amplifying the divided quantities up to predetermined levels; 3 a division circuit for further dividing the output of the arithmetic circuit 2 belonging to each range into plural subranges; 4 comparison circuits each provided for the respective display elements (e.g., liquid crystal device) so as to determine the lighting of the corresponding display elements by comparing the subdivision levels of the division circuit 3 with the reference signal; 5 an oscillation circuit for generating a clock signal applied to the display elements for determining the lighting timing of the display elements; 6 a drive circuit for determining the selective lighting of the display elements on the basis of the output signals of the comparison circuits 4 and the output of the oscillation circuit 5 and for supplying the display elements with the effective voltage for lighting them up; and 7 display elements for being lit in response to the output signals of the oscillation circuit 5 and the drive circuit 6. 
     FIG. 3 shows a concrete example of the preferred embodiment of the present invention shown in the block diagram of FIG. 2. In FIG. 3, reference numeral 1 designates an input terminal of the display device as the embodiment of the present invention; 210 a resistor with its one end connected with the input terminal; 215 an operational amplifier with its non-inverting input terminal connected with the other end of the resistor 210: 212 a resistor with its one end grounded and the other end connected with the inverting input terminal of the operational amplifier 215; 213 a resistor with its ends connected respectively with the inverting input terminal and the output of the operational amplifier 215. The constitution so far described is a first section for identifying the first division range and for generating the varying voltage belonging to the first division range. 
     The operation of the first section is as follows. 
     Let the input voltage be represented by V in  and let the resistance values of the resistors 212 and 213 be denoted by R 212  and R 213 , respectively. Then, it follows for the non-inverting and inverting input terminals of the operations amplifier 215 that 
     
         V.sub.+ = V.sub.in                                         (2) 
    
     for the non-inverting input terminal, and ##EQU2## for the inverting input terminal. 
     Here, V 30 , V -  and V 215out  designate the non-inverting input voltage, the inverting input voltage and the output voltage of the operational amplifier 215, respectively. 
     Therefore, V 215out  is related to V in  by the following equation, as seen from the expressions (2) and (3). ##EQU3## Consequently, it is seen from (4) that the output of the operational amplifier 215 is an amplified version of the input voltage applied to the amplifier. 
     The output signal of the operational amplifier 215 generated by the elements 210-215 is shown by letter (d) in FIG. 4. 
     In FIG. 3, element 220-225 constitute a second section for identifying the second division range and for generating the varying voltage belonging to the second division range. Reference numeral 220 designates an input terminal for receiving a voltage to distinguish between the first and second division ranges; 221 a resistor with its one end connected with the input resistor 220, 222 a resistor with its one end connected with the other end of the resistor 221; 223 a resitor with its one end connected with the input terminal 1; 224 a resitor with its one end connected with other end of the resistor 223 and with its remaining end gounded; and 225 an operational amplifier with its non-inverting input terminal, inverting input terminal and output terminal connected respectively with the other ends of the resistors 223, 221 and 222. 
     The operation of the second section is as follows. Let the input voltage at the input terminal 220, the resistance values of the resistors 221 and 222, and the voltage at the inverting input terminal of the operational amplifier 225 be denoted respectively by V 1 , R 221 , R 222  and V 225- . Then, it follows for the inverting input terminal that ##EQU4## 
     Solution of (5) for V 225-  yields ##EQU5## , where V 225out  is the output voltage of the operational amplifier 225. 
     On the other hand, let the input voltage at the input terminal 1, the resistance values of the resistors 223 and 224, and the input voltage at the non-inverting input terminal of the operational amplifier 225 be denoted respectively by V in , R 223  R 224  and V 225+ . Then, it follows for the non-inverting input terminal that ##EQU6## 
     Accordingly, the following expression (8) is obtained by equating the left-hand sides of the expressions (6) and (7) in accordance with the condition for stability of the operational amplifier 225. ##EQU7## 
     Solution for the output voltage V 225out , with the condition that R 221  = R 223  = R 22  and R 222  = R 224  = R 22A , yields ##EQU8## 
     Since the amplification factor in (9) is determined depending on the resistance values R 22  and R 22A  and since the quantity (V in  - V 1 ) is amplified to be V 225out , the output voltage V 225out  is delivered only after V in  has exceeded V 1 . 
     The output voltage of the operational amplifier 225 generated by the elements 220-225 is denoted by (e) in FIG. 4. 
     In FIG. 3, elements 230-235 constitute a third section for identifying the third division range and for generating the varying voltage belonging to the third range. Reference numeral 230 designates an input terminal for receiving a voltage to distinguish between the second and third ranges; 231 a resistor with its one end connected with the input terminal 230; 232 a resistor with its one end connected with the other end of the resistor 231; 233 a resistor with its one end connected with the input terminal 1, 234 a resistor with its one end connected with the other end of the resistor 233 and with its remaining end grounded; and 235 an operational amplifier with its inverting and non-inverting input terminals and its output terminal connected respectively with the other ends of the resistors 231, 233 and 232. 
     The operation of the third section is similar to that of the first or second section, and it follows that ##EQU9## , where V 235out  is the output voltage of the operational amplifier 235, R 23  and R 23A  are such that R 231  = R 232  = R 23  and R 232  = R 234  = R 23A , and V 2  is a voltage for distinguishing the second and third ranges. 
     The output signal of the operational amplifier 235 generated by the elements 230-235 is denoted by letter (f) in FIG. 4. 
     The arithmetic circuit 2 shown in FIG. 2, for dividing the input into plural ranges, is constituted of a plurality of such sections described above. 
     Therefore, concerning the section for identifying the m-th division range and for generating the varying voltage belonging to the m-th range, it follows that ##EQU10## 
     The output of the operational amplifier 2m5 generated by the elements 2m0-2m5 is denoted by letter (h) in FIG. 4. 
     Consequently, with the constitution described above, the input voltage indicated by letter (p) in FIG. 1b and FIG. 4 is converted into the voltages indicated by letters (d)-(f) in FIG. 4 so that resolution is equivalently improved. 
     The voltages E in FIG. 4 can be set with a relatively large degree of freedom. It may be chosen to be equal to the maximum value of the input voltage, the power source voltage, or a certain constant value. 
     In FIG. 3, R 11  -R 1i+1 , R 21  -R 2j+1 , R 21  -R 2k+1 , . . ., R ml  -R mt+1  are resistors constituting voltage division circuits for further dividing the input voltage so as to generate voltage levels used to determine the lighting of display elements within the respective divided ranges, resistors R 11 , R 21 , R 31 , . . ., R m+1  being connected respectively with the output terminals of the operational amplifier 215, 225, 235, . . ., 2m5. 
     The voltage division circuits will be described with the first voltage division circuit constituted of the resistors R 11  -R 1i+1  taken as an example. Reference character R 11  indicates a resistor with its one end connected with the output terminal of the operational amplifier 215; R 12  a resistor with its one end connected with the resistor R 11  ; . . .; R 1i  a resistor with its ends connected with the resistors R 1i-1  and R 1i+1  ; and R 1i+1  a resistor with its one end connected with the resistor R 1i  and with its remaining end grounded. 
     The operation of the voltage division circuit is as follows. 
     The output signal of the operational amplifier 215 is V 215out  given by the expression (4) and if the resistors R 11  -R 1i+1  have resistance values r 11  -r 1i+1 , respectively, the voltages V 11  -V 1i  at the junction points of the resistors are given by the following expressions. ##EQU11## 
     As seen from the expressions (12), the voltage division circuit divides V 215  as the input voltage to the circuit, in accordance with the resistance values. 
     In FIG. 3, G 11  -G 1i , G 21  -G 2j , G 31  -G 3k , . . ., and G ml  -G mt  designate 2-input AND circuits serving as comparison circuits for determining the lighting of display elements within the respective divided ranges. 
     The comparison circuits will be typified below by the circuit constituted of 2-input AND circuits G 11  -G 1i . The 2-input AND circuit G 11  has its input terminals connected with the resistors R n  and R 12  ; the 2-input AND circuit G 12  has its input terminals connected with the resistors R 12  and R 13  ; and likewise the 2-input AND circuit G 1i  has its input terminals connected with the resistors R 1i  and R 1i+1 . 
     The operation of this comparison circuit is as follows. 
     Now, let the threshold voltage of the q-th 2-input AND circuit G 1q  be V Lq  and let the input voltages at the two input terminals be respectively V 1q  and V 1q+1  (V 1q  &gt; V 1q+1 ). Then, the output level of the AND circuit G 1q  is &#34;High&#34; when V Lq  &lt; V 1q , V 1q+1 , and &#34;Low&#34; when V 1q+1  &lt; V Lq  &lt; V 1q  or V Lq  &gt; V 1q , V 1q+1 . Therefore, the output of the AND circuit G 1q  is determined in accordance with the relationship of the threshold voltage V Lq  to the voltages V 1q  and V 1q+1  given by the expressions (12). 
     Therefore, if the threshold levels of all the 2-input AND circuits G 11  -G 1i  are set equal to a constant value, V 1q  and V 1q+1  vary in accordance with the output voltage V 215out  so that the output signals of the 2-input AND circuits G 11  -G 1i  can be sequentially changed in accordance with the relationship of V Lq  to V 1q  and V 1q+1 . 
     In FIG. 3, reference numeral 5 indicates an oscillation circuit for generating a clock signal to be applied to liquid crystal display elements. 
     In FIG. 3, E 11  -E 1i , E 21  -E 2j  , E 31  -E 3k , . . ., and E ml  -E mt  denote exclusive OR circuits serving as liquid crystal drive circuits for receiving the outputs of the 2-input AND circuits G 11  -G 1i , G 21  -G 2j , G 31  -G 3k , . . ., and G ml  -G mt  and the output of the oscillation circuit 5 so as to determine the conditions for lighting the liquid crystal display elements and for delivering the effective voltages to be applied to the liquid crystal display elements. 
     The liquid crystal drive circuits will be typified below by the circuit constituted of exclusive OR circuits E 11  -E 1i . The exclusive OR circuit E 11  has its two input terminals connected with the output terminal of the 2-input AND circuit G 11  and the output terminal of the oscillation circuit 5; the exclusive OR circuit E 12  has its two input terminals connected with the output terminal of the 2-input AND circuit G 12  and the output terminal of the oscillation circuit 5; and likewise the i-th exclusive OR circuit E 1i  has its two input terminals connected with the output terminal of the i-th 2-input AND circuit G 1i  and the output terminal of the oscillation circuit 5. 
     The operation of the liquid crystal drive circuit is as follows. 
     The operation of each of the exclusive OR circuits E 11  -E 1i  is determined by the input signals to its two input terminals. The exclusive OR circuit E 11  delivers an output signal of &#34;Low&#34; level when the two input signals are in phase with each other and an output signal of &#34;High&#34; level when the two input signals are opposite in phase to each other. Accordingly, the output signals of the exclusive OR circuits E 12  -E 1i  are at the &#34;Low&#34; level when the output signals of the corresponding 2-input AND circuits G 12  -G 1i  are in phase with the output signal of the oscillation circuit 5 and at the &#34;High&#34; level when the output signals of the circuits G 12  -G 1i  are opposite in phase to the output of the oscillation circuit 5. 
     In FIG. 3, members D 11  -D 1i , D 21  -D 2j , D 31  -D 3k , . . . , D ml  -D mt , LC 11  -LC 1i , LC 21  -LC 2j , LC 31  -LC 3k , . . . , LC ml  -LC mt , D&#39; 11  -D&#39; 1i , D&#39; 21  -D&#39; 2j , D&#39; 31  -D&#39; 3k , . . ., and D&#39; ml  -D&#39; mt  constitute liquid crystal display elements. 
     The constitutions and functions of the liquid crystal display elements will be described below with the elements constituted of the members D 11  -D 1i , LC 11  -LC 1i , and D&#39; 11  -D&#39; 1i  taken as examples. Reference characters D 11  -D 1i  designates the electrodes of liquid crystal display elements connected with the corresponding output terminals of the exclusive OR circuits E 11  -E 1i  while characters D&#39; 11  -D&#39; 11  indicate the electrodes of the liquid crystal display elements connected with the output terminal of the oscillation circuit 5. Liquid crystals are denoted by LC 11  -LC 1i . 
     The operation of this constitution is as follows. 
     The operation of the liquid crystal display element constituted of the members D 11 , LC 11  and D&#39; 11  is as follows. The clock signal is applied to the liquid crystal display elements and the amplitude of the effective voltage determines whether the liquid crystal display element is lit or not. 
     When the output signal of the exclusive OR circuit E 11  supplied to the electrode D 11  is in phase with the output signal of the oscillation circuit 5, that is, when the output signal of the 2-input AND circuit G 11  is at the &#34;Low&#34; level, the signal applied to the electrode D&#39; 1  is in phase with the output signal of the oscillation circuit 5. Accordingly, the effective voltage is not applied to the liquid crystal LC 11  so that the liquid crystal LC 11  is not lit. 
     On the other hand, when the output signal of the exclusive OR circuit E 11  supplied to the electrode D 11  is opposite in phase to the output signal of the oscillation circuit 5, that is, when the output signal of the 2-input AND circuit G 11  is at the &#34;High&#34; level, the signal applied to the electrode D&#39; 11  is in phase with the output of the oscillation circuit 5 so that the liquid crystal LC 11  is supplied with the effective voltage for lighting it up. 
     FIG. 4 shows the output characteristic of the arithmetic circuit 2 as an embodiment of the present invention, the portions indicated by letters (d)-(h) being obtained from the arithmetic circuit 2 and connecting the ranges capable of being arithmetically operated. 
     Therefore, the arithmetic circuit 2 converts the linear variation of the input voltage V in  into a saw-tooth waveform. Here, E designates the maximum value of the output signal obtained as a result of aritmetic operation. 
     Moreover, the outputs of the arithmetic circuit 2 is increased up to E at the end of the respective varying ranges so as to smoothly calculate the increment or decrement in the output signal. 
     FIG. 5 shows another embodiment of the present invention, in which digital elements used as comparison circuits have a high threshold voltage, that is, the digital elements are CMOS devices. 
     In such a case, it is only necessary to add to the circuit configuration of the arithmetic circuit 2 shown in FIG. 3 summing mechanisms 2100, 2110-2114, 2200, 2210-2214, 2300, 2310-2314, . . ., 2m00, and 2m10-2m14, as shown in FIG. 5. Namely, the range of arithmetic operation is broadened by the use of the mechanisms by each of which a voltage exactly or nearly equal to the threshold voltage of the corresponding digital element is always added. 
     The additional circuits will be described with the section constituted of the members 2100, and 2110-2114 taken as an example. 
     An input terminal 2100 receives a voltage exactly or nearly equal to the threshold voltage of the corresponding digital element used as a comparison circuit. A resistor 2110 is connected at its one end with the output terminal of the operational amplifier 211, a resistor 2111 is connected at its one end with the input terminal 2100, an operational amplifier 2112 has its non-inverting input terminal connected with the other ends of the resistors 2110 and 2111, a resistor 2113 is connected at its one end with the inverting input terminal of the operational amplifier 2112 and grounded at its other end, and a resistor 2114 is connected between the inverting input terminal and the output terminal of the operating amplifier 2112. 
     The operation of the combination of the parts 2110-2114 is as follows. 
     Let the input voltage at the input terminal 2100 be V Dl  and let the resistance values of the resistors 2110, 2111, 2113 and 2114 be respectively R 2110 , R 2111 , R 2113  and R 2114 . Then, the input voltages V 2112+  and V 2112-  at the non-inverting and inverting input terminals of the operational amplifier 2112 are given by the following expressions. 
     
         V.sub.2112+ =V.sub.215out +V.sub.DL                        (13) ##EQU12## , where V.sub.2112out is the output signal of the operational amplifier 2112. 
    
     As seen from the expressions (13and (14). V 2112out  is related to (V 215out  +V DL ) by the following equation. ##EQU13## 
     Therefore, the output of the arithmetic circuit 2 is increased by the threshold voltage of the digital element. Consequently, the waveforms indicated by letters (i), (j), (k) and (l) in FIG. 6 represent the output voltages V 2112out , V 2212out , V 2312out  and V 2ml2out , respectively. 
     The display device described above enjoys the following effects. 
     (1) The varying range of the input voltage can be made small and satisfactory resolution can be attained even in the case where a large number of liquid crystal display elements are used. 
     (2) Satisfactory resolution can be obtained no matter what kind of digital element may be used as a comparison circuit, and the liquid crystal display elements can be uniformly controlled. 
     The display device according to the present invention can be applied not only to the case where the input voltage increases, but also to the case where the input voltage decreases. 
     Moreover, according to the present invention, the display of what percent each input voltage is of the maximum input voltage, is possible irrespective of the number of liquid crystal display elements to be used and the varying range of the input voltage so that many display items such as velocity, r.p.m., etc., of an automobile can be displayed with satisfactory accuracy.