Frequency discriminators
This application is a continuation-in-part of application Ser. No. 782,082 filed Mar. 28, 1977. 
    
    
     The present invention relates to frequency discriminators. 
    
    
     In the drawing: 
     FIG. 1 is a schematic circuit diagram of one embodiment of the invention; 
     FIG. 2 is a schematic circuit diagram of a second embodiment of the invention; and 
     FIG. 3 is a schematic circuit diagram of a third embodiment of the invention. 
    
    
     The circuit illustrated in FIG. 1 includes two complementary field effect transistors (FET&#39;s) P 1  and N 1 , respectively. The P channel transistor P 1  is connected at its source electrode 10 to the terminal 12 to which the operating voltage B+ is applied and at its gate electrode 14 to input terminal 16. The drain electrode 18 of this transistor is connected to circuit node 20 at one terminal of parallel resonant circuit 22. This circuit, which comprises an inductor L 1  and a tunable capacitor C 1 , is connected at its other terminal 24 through resistor R 1  to circuit node 26. Node 26 is connected to input terminal 16 and gate electrodes 14, 34 via a resistor R F1 . The substrate of the P channel transistor, illustrated schematically at 28, is connected to the B+ terminal 12. 
     N channel transistor N 1  is connected at its source electrode 30 to a point of reference potential, shown as ground, at its substrate connection 32 also to ground and at its gate electrode 34 to input terminal 16. The drain electrode 38 of this transistor is connected to circuit node 40 which, in turn, is connected to one terminal of parallel resonant circuit 42. The other terminal 44 of this resonant circuit connects through resistor R 2  to node 26. Resonant circuit 42 comprises an inductor L 2  and a tunable capacitor C 2 . 
     Node 20 of the circuit is alternating current (AC) coupled via capacitor 46 to a detector comprising diodes D 1   and D 2  and capacitor C 7 . Diode D 1  is connected at its anode to ground and at its cathode to the anode of diode D 2 . The cathode of diode D 2  is connected to one terminal of capacitor C 7  and to one terminal of resistor R 3 . The other terminal of capacitor C 7  is connected to ground. Resistor R 3  can be potentiometer and the tap of this potentiometer connects to the output terminal 48 of the circuit. The detector D 3 , D 4 , C 8  is similar to the one just described, but with the diodes oppositely poled. It is AC coupled to the node 40 by capacitor C 6 , and the common connection of diode D 4  and capacitor C 8  connects to the other terminal of resistor R 3 . 
     Capacitor C 4  connected to terminal 44 and capacitor C 3  connected to terminal 24 are radio frequency (RF) bypass capacitors for the tuned circuits 22 and 42, respectively. They maintain these terminals at RF ground. Capacitor C 9  is also a bypass capacitor, this one for supply terminal 10. 
     The operation of the circuit of FIG. 1 will be discussed in terms of a frequency modulated (FM) signal discriminator. In other words, it is assumed that the input signal applied between terminal 16 and ground is a frequency modulated carrier, where the carrier may be at an intermediate frequency (IF) and the modulation at an audio frequency. The output signal obtained at terminal 48 in this case is this audio frequency component. However, other applications for the circuit are also possible. For example, the signal applied at 16 may be the output signal of an oscillator whose frequency it is desired to control. In this kind of application, the output signal at 48 will be a control signal and it may be fed back to a frequency controlling element of the oscillator for maintaining the oscillator frequency constant. 
     In the operation of the circuit of FIG. 1, the resonant circuit 22 is tuned to a frequency f 0  +Δf where f 0  is the nominal center frequency of the carrier wave applied to 16. If this particular example, f 0  is an intermediate frequency. The frequency Δf is a frequency increment which is small compared to f 0 . As one example, f 0  may be 455 kHz and Δf 4.5 kHz; as another, f 0  may be 10.7 MHz and Δf 75 kHz. The resonant circuit 42 is turned to a frequency f 0  -Δf. 
     The resistors R 1  and R 2  are chosen to have values such that quiescently, the node 26 is at a voltage B+/2, that is, a voltage one half that of the operating voltage B+ applied to terminal 12. If one assumes equal conduction through transistors P 1  and N 1  in the quiescent condition of these transistors, then R 1  and R 2  will have equal values. The purpose of resistor R F1 , is to place the gate electrodes 14 and 34 of the two transistors at this same voltage level B+/2. Thus, the two transistors quiescently operate at the center of the linear region of the transfer characteristic of the circuit. 
     If there is no FM modulation on the IF carrier signal, then the IF voltages developed across the two tuned circuits 22 and 42 will be equal as will the detected components appearing across capacitors C 7  and C 8 . The detected components cause current flows in opposite directions through potentiometer R 3  and as they are equal, they cancel. In other words, the potentiometer operates to subtract one detected component from the other. The tap 50 on the output potentiometer R 3 , is at substantially the center point of the potentiometer and the output voltage produced at output terminal 48 when the two detection components are equal, is zero. 
     If the FM modulation on the carrier should be such as to increase the carrier frequency, then the IF voltage developed across resonant circuit 22 will be greater than that developed across resonant circuit 42. In this event, the detected component produced across capacitor C 7  will be greater than that produced across capacitor C 8 . A net current will then flow through resistor R 3  in the direction from capacitor C 7  toward capacitor C 8  (assuming positive current flow) and the voltage developed at 48 will be relatively positive. By the same token, if the FM modulation on the carrier frequency should be such as to decrease the carrier frequency, the voltage developed across resonant circuit 42 will exceed that developed across the resonant circuit 22, and the output voltage at terminal 48, will be relatively negative. 
     The circuit of FIG. 1 has a number of advantageous operating characteristics. For example, if there should be some undesired amplitude modulation present on the input carrier, the balanced nature of the circuit is such that these components will cancel and not appear at the output terminal 48. Further, the present circuit does not require a special transformer such as employed with many other forms of frequency discriminators. Moreover, if B+ should vary, this does not significantly affect the circuit operation because the bias applied to the gate electrodes still remains B+/2. The circuit also has a large dynamic operating range, say up to 50% or more of the operating voltage B+. This contrasts with the relatively small voltage swing, of the order of a few hundred millivolts, which is available with many other types of transistorized frequency discriminators. Finally, the present circuit is highly linear by virtue of the highly linear combined operating characteristic of the P and N channel devices and the quiescent biasing of the circuit at the center of this characteristic. 
     The circuit of FIG. 1 is expected to operate well at lower frequencies, say in the range up to roughly 100 MHz (the upper part of this range will require circuit layout and packaging suitable for the high frequency operation and may require feedback neutralization); however, at higher frequencies, the circuit may become unstable due to the feedback capacitance between the drain and gate electrodes of each transistor. To obviate this possible instability, two additional transistors may be employed, one connected in cascode with each of the transistors shown in FIG. 1. A suitable circuit of this type is illustrated in FIG. 2. 
     Referring now to FIG. 2, there is an additional P channel transistor P 2  and an additional N channel transistor N 2 . The conduction path of transistor P 2  is connected in series with that of transistor P 1  and the conduction path of transistor N 2  is connected in series with that of transistor N 1 . The gate electrodes 60 and 62 of transistors P 2  and N 2  are maintained at the voltage present at node 26 by resistor R F1 . As in the previous circuit, assuming equal conduction through the P channel transistors as through the N channel transistors, and assuming also equal values of R 1  and R 2 , the voltage at node 26 will be B+/2. Of course here and in the previous circuit, R 1  and R 2  together can be a potentiometer with 26 the tap on the potentiometer, and the circuit adjusted to insure that node 26 is at the B+/2 level. The resistor R F2  places the gate electrodes 14 and 34 of transistor P 1  and N 1 , respectively, also at the same voltage level of B+/2. The bypass capacitor C 10  connects the gate electrodes 60 and 62 of transistors P 2  and N 2 , respectively, to RF ground. In other words, these two transistors operate in the common-gate mode thereby isolating the drain electrode 64 of transistor P 2  from the gate electrode 14 of transistor P 1  and the drain electrode 66 of transistor N 2  from the gate electrode 34 of transistor N 1 , resulting in a high order of circuit stability. 
     Aside from the built-in isolation described above, which reduces the possibility for regenerative feedback and thereby increases the stability of the circuit, the operation of the circuit of FIG. 2 is quite similar to that of FIG. 1. Similar elements in the two circuits are identified by similar reference numerals and characters. 
     The circuit of FIG. 3 is a modification of the circuit of FIG. 1 in which the frequency modulated input signal is applied to the source electrodes of the complementary transistors and the gate electrodes of the complementary transistors are connected to ground. The input signal applied to terminal 16 is coupled to input parallel resonant circuits 80 and 82, respectively, via windings L 15  and L 16 , respectively. Parallel resonant circuit 80 is connected between the B+ terminal and the source electrode 10 of P-channel transistor P 1  and parallel resonant circuit 82 is connected between the source electrode of N-channel transistor N 1  and ground. Capacitor C 9  serves the same function as the similarly-legended capacitor in FIG. 1, namely as an AC bypass to ground. The directions of windings L 15  and L 16  are such that the input carrier wave at source electrode 10 is 180° out of phase with the same wave at source electrode 30. This is indicated schematically by the waveforms 84 and 86, respectively, and the waveforms 84a and 86a indicate the phasing at the respective drain electrodes of transistors P 1  and N 1 . The capacitor C 12  serves to connect the respective gate electrodes 14 and 34 to ground. 
     The operation of the circuit of FIG. 3 should be clear in the explanation given in connection with FIG. 1. As in FIG. 1, tuned circuits 22 and 42 are tuned to f 0  +Δf and f 0  -Δf, respectively, where f 0  is the carrier frequency and Δf is as already described. Optimum gain is available when input tuned circuit 80 is tuned to the same frequency, namely f 0  +Δf, as tuned circuit 22 and similarly when input tuned circuit 82 is tuned to the same frequency, namely f 0  -Δf, as tuned circuit 42. However, the circuit also is operational with the two inut circuits 80 and 82 both resonated to frequency f 0 . 
     The circuit of FIG. 3 can be operated at lower frequencies just as the FIG. 1 circuit but it is particularly advantageous for use at higher frequencies. That is, the FIG. 3 circuit is operative at frequencies in a range in which a common source circuit, such as the one of FIG. 1, may show some tendency toward instability due to the feedback introduced by the drain-gate capacities inherent in the transistors. See in this connection the discussion appearing at the end of the explanation of the operation of FIG. 1. 
     In the circuits of FIGS. 1 and 2 as in previously-known Travis-type discriminators, the diode bridge is driven by &#34;in phase&#34; signals. In the circuit of FIG. 3, however, the diode bridge is driven by signals which are 180° out of phase with one another. Thus, in the case of an FM signal with zero modulation, the waveforms at the carrier frequency f 0 , at 84a and 86a are of equal amplitude but 180° out of phase. Assuming the bridge to be balanced, there is zero signal at output terminal 50 because there is exact signal cancellation. Under this assumed condition, the circuit can function with capacitors C 7  and C 8  of zero value. 
     In contrast to the above, in the circuit of FIGS. 1 and 2 of the present application, the waveforms at points 20 and 40 are in phase. Consequently, on a negative-going half cycle of f 0 , diode D 4  is conductive and charges capacitor C 8  while on the positive-going half cycle of f 0  diode D 2  is conductive and charges capacitor C 7 . Thus, the comparison between demodulated signals is being made on a DC basis, that is, the demodulated signals are not being compared directly but rather the comparison is between the charge stored on capacitor C 7  and that stored on capacitor C 8 . If all elements are balanced, the DC signal at terminal 50 is zero when the input signal is f 0 . In this classical mode of operation, capacitors C 7  and C 8  must be made of finite size, the size depending upon the value of f 0  and the impedance levels at which the circuit is operating. The capacitors, in other words, must be of sufficient size to store their respective charges for an interval sufficient to permit them to be compared. 
     It should be clear from the discussion above that the circuit of FIG. 3, because it supplies out-of-phase signals to the two sets of diodes, requires smaller values of filter capacitors C 7  and C 8  than do the circuits of FIGS. 1 and 2. In practical use of the circuit of FIG. 3, capacitors C 7  and C 8 , of finite size, are employed to filter (integrate) the rectified RF developed by diodes D 2  and D 4 , respectively, for the cases when the input signal is of a value other than f 0 . But the circuit of FIG. 3 operates with significantly lower values of capacitance for C 7  and C 8  than the circuits of FIGS. 1 and 2. The lower value of capacitance is advantageous from at least two standpoints. First, when the circuit is to be integrated either in hybrid or in monolithic form, it is substantially easier as a practical matter, to provide the smaller value of capacitance. Secondly, the use of a smaller capacitance is advantageous in that there is less restriction in base frequency bandwidth, that is, frequency response. 
     A number of modifications are possible in the three circuits described. For example, the purpose of the resistors R 1  and R 2  is to decouple the two parallel resonant circuits 22 and 42, respectively. They can be eliminated, and capacitors C 3  and C 4  combined as a single capacitor if good bypassing of higher frequency signal components to ground can be established. 
     While the circuit has been described in terms of complementary MOS transistors which do have the advantages discussed including large dynamic input signal range, in some circumstances complementary bipolar transistors may be used instead. The circuit modified in this way is useful in applications where the input signal is produced by a bipolar transistor circuit and is of a relatively low amplitude, say up to a few hundred millivolts.