CCD Comparator
BACKGROUND OF THE INVENTION 
     This invention is in the field of CCD devices, and more particularly in charge transfer devices used for comparing an input signal against a reference signal. 
     Although comparators using conventional electronic components are known in the art, no comparator is known which utilizes charge transfer principals. 
     SUMMARY OF THE INVENTION 
     A charge transfer device is provided having a group of electrodes embedded in a slab-like substrate of semiconductor material, and a second group of electrodes embedded in a contiguous layer of electrically insulating material. The device has means for injecting charge which comprises a first additional electrode embedded in-part in the semiconductor material, and a second additional electrode embedded in the insulating material. The first additional electrode is energized by a DC voltage and the second additional electrode is energized by a rectangular clock signal. 
     In addition to the above, the device utilizes three contiguous electrodes within the insulative material, substantially at the device center, with each of the two outer electrodes of the three contiguous electrodes having input voltages applied thereto. The electrode between the two outer electrodes has a ramp clock voltage applied thereto. 
     As a result of the applied voltages, surface potentials are created under these three contiguous electrodes. The surface potentials, in turn, give rise to a charge well located adjacent the electrode between the two outer electrodes at the surface interface between the semiconductor and insulator materials, and also give to two potential barriers, one barrier at each side of the charge well. 
     A substantial charge is injected into the charge well in a direction parallel to one of the sides of the charge well. 
     The ramp clock voltage then rises moving the potential at the bottom of the charge well towards the potential barrier, thus displacing upwards the fixed charge in the charge well. When the top of the charge in the charge well reaches the lowest potential of the two barrier potentials, charge will begin to flow over the barrier having the lower of the two barrier potentials into a low surface potential area so as to receive all the charge initially injected into the charge well. 
     Two outputs are provided so as to enable storing of charge in that particular one of the two low surface potential areas, referred to above. Logic complements therefore exist at two charge mode outputs provided by the device. 
     Power dissipation in the device is substantially in the area of the electrode between the two outer electrodes and in the area contiguous the electrodes to which the rectangular clock signal is applied. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a top-plan view of the charge transfer device in accordance with the invention. 
     FIG. 2 is a cross-section view taken at plane 2--2 of FIG. 1 showing certain details of the device structure. 
     FIG. 2a is a surface potential diagram showing charge distribution in the various areas of the device as illustrated in FIG. 2. 
     FIG. 3 is a cross-section view taken at plane 3--3 of FIG. 1 showing additional details of the device structure. 
     FIG. 3a is a surface potential diagram showing charge distribution in various areas of the device as illustrated in FIG. 3. 
     FIG. 4 is a block schematic showing various power sources, clock signals and input voltages used to feed the device, as well as showing input and reference voltages which are applied to the device. 
     FIG. 5 is a waveform diagram showing the various clock signals and voltage input waveforms as well as logic outputs of the device, all drawn to a common time base. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIGS. 1-5 herein, a charge transfer (sometimes referred to as charge coupled) device 10 is provided for comparing a signal input with a reference signal. 
     Device 10 has a semiconductor body 12 generally of silicon, however other semiconductor materials such as germanium could have been utilized as body 12. Body 12 is shown as a P +  conductivity doped silicon material, however it is understood that other conductivity type materials, such as N types may be used. 
     Electrodes 14 spaced from each other and partially embedded within body 12 are hard wire interconnected and fed by DC potential V dd  with respect to ground potential 11. Another DC voltage is powered by battery V s  with the negative side of V s  connected to substrate 12 at point 21, the positive side of battery V s  being at ground potential 11. V s  therefore provides a negative DC bias to substrate 12. 
     Electrodes 16 and 18 are spaced from each other and partially embedded within body 12. Electrode 16 has a hard wire connection for providing an output thereat and thereby providing a waveform output as shown at in FIG. 5. Electrode 18 has a hard wire connection for providing a waveform output as shown at B in FIG. 5. It is to be noted that waveforms A and B are not coincident. 
     An electrically insulating film 32 of SiO 2  is deposited over layer 12 and forms an interface at 22 with layer 12 and with the upper surfaces of each of electrodes 14, 16 and 18. It is understood that other insulating films may be used. 
     Gate electrodes 34, spaced from each other and embedded in film 32, are provided with hard wire connections to a terminal at φ r . The voltages at φ r  is illustrated as waveform C in FIG. 5 and consists of a series of rectangular pulses which provide a RESET function to device 10, thereby resetting outputs Q out  and Q out  to V dd  potential prior to recycling the operation performed by device 10. 
     Electrodes 36 and 38, bound within the confines of film 32 are spaced from each other in substantially a common plane and are respectively electrically connected to voltage sources 37 and 39 of power source 50. Voltages V i  and V r  shown in FIG. 5 as waveforms D and E, respectively, represent the input and reference voltages to the comparator, wherein V r  represented by waveform E is a reference voltage having a specific reference level used to compare with V i . 
     For the comparator of the present invention, the following truth table applies: 
     
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Condition            --Q.sub.out                                          
                               Q.sub.out                                  
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V.sub.i more positive than V.sub.r                                        
                     1         0                                          
V.sub.i less positive than V.sub.r                                        
                     0         1                                          
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     Logic ONE (1) is defined herein as the presence of charge at output Q out  and Q out . Logic ZERO (0) is defined herein as the absence of charge at these outputs. Logic ZERO has a more positive potential than logic ONE, and logic ONE has a potential less positive than the potential giving rise to logic ZERO level. 
     Electrode 42 is embedded substantially at the center of device 10 within film 32 at a plane substantially parallel to the plane in which electrodes 34, 36 and 38 lie. Electrode 42 is hard wire connected to a clock signal φ w  the waveform of which is shown at F, in FIG. 5, for ultimately transferring a charge in well 64 over either barriers 60 or 62 into adjacently located wells, to be hereinafter discussed. Waveform F need not be periodic in its repitition pattern, but under such circumstances the other waveforms namely G and C would have to be shifted in like amount of increase or decrease between one of the patterns of waveform F and another like pattern. 
     Referring to FIG. 3, electrode 20 is also partially embedded in semiconductor material 12, at one side of device 10, in transverse alignment with electrode 42. A DC voltage V c  is coupled to electrode 20 by means of a hard wire connection. Alternatively, a clock voltage providing a repetitive rectangular waveshape may be used instead of voltage V c , if desired. 
     It should be noted that voltages V dd , V c  and V s  are provided by power source 50 shown in FIG. 4. Clock signals φ w , φ r  and φ c  are also provided by another section of source 50. 
     Electrode 40 is embedded within film 32 between electrodes 20 and 42 and has a hard wire connection so as to enable application of clock signal φ c  thereto as illustrated by waveform G. The structure of device 10 which includes electrodes 20 and 40, when combined with the remaining CCD structure hereinabove described, results in a novel means for injecting charge into device 10. 
     In order to further clarify the manner of operation of this device as a comparator it should be emphasized that the device utilizes three contiguous electrodes 36, 38 and 42 within the insulative material, substantially at the device center, with each of the two outer electrodes 36 and 38 of the three contiguous electrodes having input voltages V i  and V r  applied thereto respectively. The electrode 42 between the two outer electrodes 36 and 38 has a ramp clock voltage φ w  represented by waveform F applied thereto. 
     As a result of the applied voltages, surface potentials 60, 62 and 66 are created under these three contiguous electrodes. It should be noted that potentials 60 and 62 are also referred to as potential barriers. The surface potentials, in turn, give rise to a charge well 64 located under electrode 42 at the surface interface 22 between the semiconductor and insulator materials, which give rise to the two potential barriers 60 and 62, one barrier at each side of charge well 64. 
     A substantial charge is injected into the charge well 64 in a direction parallel to one of the sides of the charge well. 
     The ramp clock voltage φ w  then rises moving potential 66 at the bottom of the charge well 64 towards potential barriers 60 and 62, thus displacing upwards the fixed charge in the charge well to potential level 76. When the top of the charge at 76 in charge well 64 reaches the highest potential of the two barrier potentials 60 and 62, charge will begin to flow over the barrier having the higher of the two barrier potentials into a high surface potential area, either area 96 or 108, so as to receive all the charge initially injected into charge well 64. 
     Comparator operation is explained below in detail for substantially two possible cases of input voltages V i  and V r  ; that is, when V i  is greater than V r  and when V i  is less than V r . Those cases are explained in two comparator operations, first when V i  is greater in potential level than V r  during t 0  -t 8  and then when V i  is less in potential level than V r  during period t 8  -t 14 . The case of inputs being equal provides equal outputs of one half of the normal output charge at 98 and 110, the sum of charges at 98 and 110 being equal to the charge in well 64. 
     Thus, before input voltage V i  shown by waveform D changes at t 8  in the form of a step function, the direction of charge motion is in direction of arrow 97, FIG. 2a. Hence, complementary outputs ensue at Q out  and Q out , resulting in comparator behaviour. 
     Referring particularly to FIGS. 2a and 3a, device 10 may be functionally described in terms of its potential profiles and waveforms A through G shown in FIG. 5. 
     Just prior to time t 1 , waveform G representing clock φ c , created a barrier 88 at a potential level 90, as shown in FIG. 3a as being zero potential. At time t 1 , φ c  undergoes a transition changing the barrier to potential level 86 which is at a more positive potential level as compared with potential level 90. 
     At time t 1 , waveform G representing clock φ c  which previously had created barrier 88 at potential level 90, in FIG. 3a, now changes to potential level 86. At potential level 90, the device is turned OFF because the surface potential φ s  at 22 is ZERO. 
     During the period t 1  -t 2 , waveform G provided by clock φ c , is most positive, which condition turns device 10 ON rather quickly providing a low ON-operational mode resistance, thus permitting rapid charging of well 64, previously depleted of charge, from level 66 to level 76 by virtue of the presence of charge 92 at level 78. Therefore, charge transfer direction occurs from left to right as indicated in FIG. 3a by arrow 79. 
     At t 2 , φ c  as shown by waveform G, switches to ZERO volt level, turning OFF the source of charge and thereby disabling the flow of charge into well 64. 
     During periods t 3  -t 5 , the φ w  clock potential shown by waveform F, provides a charging ramp waveform from a positive to a ZERO potential. The charge in well 64 is bounded by wall 68 of barrier 60 and wall 70 of barrier 62 as well as walls 72 and 74. The bottom of well 64 is defined by a potential at 66. Clock φ w  defines potential 66 at the bottom of well 64. Waveform G transition shifts the bottom of well 64 thus displacing surface potential 76 to a less positive direction until such time as potential 76 is equal to the more positive of barriers 60 or 62, during period t 3  -t 5 . Voltage V i  at that period is more positive than voltage V r  with respect to ground 11, as the ramp of waveform F continues to change to a less positive potential and the charge in well 64 will be transferred as shown by arrow 97 to well 96 over barrier 60, as clock φ w  continues to change to a less positive potential. Such potential change thereby increases charge 98 already in well 96, from level 104 to level 106. Well 96 is defined by wall 100 of barrier 94, wall 102 of barrier 60 and by potential charge level at 104. The surface potential at level 106 in indicating the presence of charge thereat in well 96 defines logic ONE for the Q out  which exists at time t 4  and remains in logic ONE state until time t 7 . 
     During period t 5  -t 6 , there is no change in φ w  signal and no change in operation of the device occurs and hence this time period is not critical to CCD operation. 
     At time t 6 , φ w  makes a transition from ZERO voltage to its original positive voltage in readiness for the next-in-sequence comparison period. 
     The function of barrier 94 is to disconnect or turn OFF the reset mechanism, consisting of gate electrodes 34 and electrode 14, during period t 2  -t 7 . Barrier 94 is bounded by potential 95, wall 100 and wall 136 thereof. 
     At t 7 , waveform G switches from ZERO to a positive voltage thereby switching the potential level at 95 to the level shown at 138. Such switching produces a low resistance path between well 96 and potential level V dd  and 134 thereby providing the required mechanism to reset well 96 from level 106 to level 104 which is at the same potential level as shown at 134. 
     It should be noted that potential area 132 is created by a DC voltage V dd  and is not a well because charge cannot be stored thereat since the 132 area is essentially a charge drain or sink. This is also true for areas 92 and 122. 
     During t 7  -t 9 , output wells at 96 and 108 are reset to V dd  potential, coincident with the presetting of well 64 which restarts the operational cycle of the device in the same manner described hereinabove in connection with period t 1  -t 2 . 
     It may be noted that input signal V i  at t 8  is illustrated to show the change in voltage level the purpose of which is to illustrate the operation of the device as a comparator wherein an input signal V i  is less positive than reference input signal V r . 
     Hence, during time period defined by t 7  -t 14 , the charge in well 64 is now transferred in the opposite direction over barrier 62 into well 108 thereby providing a logic ONE output at Q out , between t 11  -t 14 , in accordance with the foregoing truth table. Consequently, numerical identifiers 108, 110, 112, 114, 116, 118, 120, 121, 122, 124, 126 and 128 may be defined in the same terms as heretofore defined and described in connection with numerals 96, 98, 102, 100, 104, 106, 94, 95, 132, 134, 136 and 138 respectively.