Pattern generating system and method
RELATED APPLICATION 
     This application relates to my copending U.S. Pat. Application Ser. No. 677,196, filed Apr. 15, 1976 and entitled &#34;Test Signal Generating System and Method&#34; and now U.S. Pat. No. 4,093,960. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to a pattern generating system and method and, more particularly, relates to a system and method for producing patterns useful in servicing T.V. receivers and the like. 
     BACKGROUND OF THE INVENTION 
     As electronic equipment, have become more complicated, it has been necessary to provide units to facilitate, or in some cases make possible, the servicing of such electronic equipment to keep the same in good operational condition. This has been particularly true of electronic equipment used to receive T.V. signals, including the now common T.V. receiver and closed-circuit T.V. monitor, and the need for such service equipment has become even more acute with the increased use of color T.V. receivers and monitors. 
     Servicing of television receivers and closed-circuit T.V. monitors, and particularly color television receivers, often requires the use of special signal generating apparatus for producing stable test patterns such as a plurality of color bars each of different hue, a crosshatch pattern of white vertical and horizontal lines, or an orderly array of white dots to be displayed on the image-producing device of the T.V. receiver or closed-circuit monitor. 
     These patterns are useful for checking and correctly adjusting linearity and pincushion distortions in scanning circuits, for checking and correctly adjusting operation of electron beam convergence, and for checking and adjusting color phasing and matrixing circuits in color television receivers. 
     While the need for more complex servicing equipment exists in view of the more complicated electronic equipment to be serviced, there obviously also exists a need to minimize such complexity to the extent possible in view of the seemingly ever increasing needed functions. To this end, it is desirable that servicing equipment be, and be maintained, lightweight, portable, reliable, versatile, and yet capable of simple operation. 
     Servicing equipment for T.V. receivers have been heretofore suggested and/or utilized. Included among such known equipment is equipment generally directed to producing test patterns for servicing T.V. receivers, and some said suggested equipment has included such features as digital circuitry, color bar pattern generation, and dot and crosshatch generation, as well as various frequency divider systems. Among patents showing one or mre of these features are U.S. Pat. Nos. 3,019,289; 3,529,079; 3,250,853; 3,188,383; 2,836,717; 3,493,673; 3,430,067; 2,975,229; 3,634,612; 2,943,144; 3,586,755; 3,334,178; 2,824,225; and 2,683,187. 
     Such servicing equipment now suggested and/or utilized has not, however, proved to be completely successful at least in accomplishing all of many and diverse desired ends. For example, known servicing equipment, while providing test patterns, has not provided fully satisfactory patterns and/or has not produced the number of various patterns that might be needed. In accordance, known servicing equipment has not fully provided needed simplicity, versatility and/or reliability, and circuitry problems related to such equipments have not been eliminated or satisfactorily reduced in many instances. 
     Thus, even though much servicing equipment has been heretofore suggested and/or utilized, a need still existed for a system that could eliminate, or at leat substantially reduce, many of the problems in equipment of this type. 
     In my above-referenced copending U.S. Pat. Application Ser. No. 677,196, I have described and claimed an improved system and method for generating test signals for servicing a T.V. receiver and the like which has the capability of producing a number of test patterns that were unobtainable prior to my invention. This invention expands upon my previous invention and provides a further improvement in the system and method as well as providing more test patterns that have been heretofore not available and yet are useful in servicing of T.V. receivers and the like. 
     SUMMARY OF THE INVENTION 
     This invention provides an improved lightweight and portable pattern generating equipment that is reliable, versatile, and yet simple to operate with said equipment being particularly well suited for servicing of T.V. receivers and monitors including color equipment. This invention provides an improvement in available patterns, as well as a method for producing such patterns for servicing of T.V. receivers and the like. 
     It is therefore an object of this invention to provide an improved system and method for producing patterns suitable for servicing of electronic equipment such as T.V. receivers. 
     It is another object of this invention to provide an improved system for controlling the polarity of output signals utilized for causing test patterns to be produced for use in servicing T.V. receivers and the like. 
     It is yet another object of this invention to provide a system having improved circuitry utilizing a digital technique for controlling the phase of chroma output signals. 
     It is still another object of this invention to provide a system capable of producing a GRAY QUAD pattern for checking and adjusting the video and display circuits of a T.V. receiver. 
     It is yet another object of this invention to provide a system capable of producing a COLOR QUAD pattern for checking and adjusting the chroma and display circuits in a T.V. receiver or monitor. 
     It is still another object of this invention to provide a system capable of providing a HATCHDOTS pattern that has improved versatility for making beam convergence, linearity, and pincushion checks and adjustments in addition to checks of video peaking. 
     It is yet another object of this invention to provide a system having an output trigger to enable chroma cycles to be externally viewed as, for example, on a single trace oscilloscope using a color bar pattern generator with chroma frequency phase locked at an odd harmonic of one-half the line frequency. 
     It is still another object of this invention to provide an improved system for producing patterns suitable for servicing of an electronic unit having an image display device with the system including mutiplexer means utilized in forming said pattern. 
     With these and other objects in view, which will become apparent to one skilled in the art as the description proceeds, this invention resides in the novel construction, combination, method, and arrangement of parts substantially as hereinafter described, and more particularly defined by the appended claims, it being understood that such changes in the precise embodiment of the herein disclosed invention are meant to be included as come within the scope of the claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings illustrate complete embodiments of the invention according to the best mode so far devised for the practical application of the principles thereof, and in which: 
     FIG. 1 is a perspective view of the test signal generating system of this invention shown connected to a conventional T.V. receiver for servicing of the same; 
     FIGS. 2 through 4, taken together, constitute an electrical functional block diagram of the test signal generating system of this invention as shown in FIG. 1; 
     FIG. 5 is a functional block diagram relating to the quad former unit shown in FIG. 3; 
     FIG. 6 is a functional block diagram relating to the DOTS, HATCHDOTS, and CROSSHATCH pattern generating circuitry; 
     FIG. 7 is a functional block diagram relating to the weighted video multiplexer section shown in FIG. 3; 
     FIG. 8 is a color quad pattern that may be produced on a T.V. receiver connected with the test signal generating system of this invention; 
     FIG. 9 is a gray quad pattern that may be produced on a T.V. receiver connected with the test signal generating system of this invention; 
     FIG. 10 is a HATCHDOTS pattern that may be produced on a T.V. receiver connected with the signal generating system of this invention; 
     FIG. 11 is a functional block diagram relating to an alternate embodiment of this invention for producing an NSTC type color bar pattern; and 
     FIG. 12 is a color bar pattern that may be produced on a T.V. receiver connected with the test signal generating system of this invention as modified and shown in FIG. 11. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawings, FIG. 1 shows the test signal generating system 15 of this invention connected typically, as by lead 16, with a conventional electronic unit (shown as T.V. receiver 17) having an image-producing, or display, device (shown as a T.V. tube) upon which appears test patterns under the control and by selection of signal generating system 15. As indicated in FIG. 1, signal generating system 15 has a plurality of controls and jacks at the front face thereof with plug 19, connected with lead 16, being shown inserted into a jack (not shown) at the lower right portion of the front face of unit 15. Pattern select switch 20 is preferably centrally located on the front face of unit 15, video level control switch 21 and chroma level control switch 22 are preferably located at the top left side of the front face, and RF/IF -- volume control switch 23 is preferably located at the top right side of the front face of unit 15. Switches 21 through 23 are preferably of the push-pull type and also rotatable switches with the rotatable portion controlling the level of signal and the push-pull portion controlling the type of signal (i.e., negative or positive video for switch 21, interlace or non-interlace for switch 22, and RF or IF for switch 23). 
     A plurality of jacks 25 through 28 are also located at the lower left portion of the face of unit 15 with jack 25 being a video output jack, jack 26 being a vertical trigger jack, jack 27 being a 1/2 line frequency trigger jack, and jack 28 being a line frequency trigger jack. 
     FIGS. 2 through 4, taken together, constitute an electrical functional block diagram of unit, or system, 15, while FIGS. 5 through 7 show particular portions of elements depicted in FIG. 3 in more detail. As indicated in the drawings, the components, or elements, utilized are preferably solid state digital logic elements and the system of this invention can thus be packaged in a relatively small and thus portable unit as indicated in FIG. 1. 
     Unit 15 is similar, in many respects, to the signal generating system as set forth in my copending U.S. Pat. application, Ser. No. 677,196, which reference may be made for the details thereof. 
     In the FIGURES illustrating the invention by functional block diagram, where the name of a function is indicated, it is implied to be a &#34;1&#34; level (standard logic) unless a line appears above the name or a circle appears at the point where the connection is made, both of which indicate that it is a NOT (inverted) function. Where several outputs from a counter or switch are bracketed together and are connected via a dashed line to one or more other blocks or elements, this is an indication that one or more of the outputs are used by the respective block in order to provide an appropriate input for the task to be accomplished. Being for illustrative purposes, there is not meant to be an implication in this situation that the number of outputs shown from the generating subsystem or the number of inputs shown to the receiving subsystem are indicative of the actual number that are used. Thus, each may consist of several sub-parts and one or more of these sub-parts may also serve a dual purpose as part of another subsystem, as would be obvious to one skilled in the art. A typical example is pattern select switch 20 and the manner by which this switch supplies control inputs to the color preselect multiplexer 40. The select switch, as illustrated in FIG. 1, could be a 12 position rotary selector switch. A switch of this type can be readily wired, as would be obvious to one skilled in the art, to produce three lines of binary pattern select data to a circuit element such as the color preselect multiplexer 40 of the weighted multiplexer 45 as shown in FIG. 2 of the drawings to produce the proper outputs as set forth in Table I, which table illustrates the respective address inputs to the color preselect multiplexer. 
     As shown in FIG. 2, two master clock oscillators 30 and 31 are employed, but only one is enabled for any specified test condition. Crystal oscillators 30 and 31 may be conventional and are coupled to the three flip-fops 33, 34 and 35 in such a manner that either oscillator (whichever is enabled) acts as a suitable clock for these flip-flops. With RED RASTER. BLUE RASTER, GREEN RASTER, or COLOR QUAD selected, the 14.318182 MHz oscillator 31 (four times the required 3.579545 MHz chroma (frequency) is enabled, whereas, with COLOR BARS, 3.58 MONITOR, or VECTOR selected, the 14.255245 MHz oscillator 30 (four times the required 3.563811 MHz offset carrier) is enabled. With any black and white pattern, GRAY QUAD, HATCHDOTS, or DOTS selected, either clock frequency can be used providing it is consistent with the counting modulus selected. 
     A 2× chroma-to-line frequency variable modulus counter 37, receiving the output from flip-flop 35, is illustrated in FIG. 3, but a conventional separate oscillator and fixed modulus counter could be used if increased interference levels and reduced versatility are tolerable, and if there is no requirement for a 1/2 line frequency oscilloscope trigger. When a synchronous countdown from 2× chroma-to-line frequency is employed, as illustrated, the counting modulus must be made compatible with the selection of master clock oscillator, i.e., with a 14.318182 MHz master clock oscillator 31 and a required line scanning frequency of 15.734265 KHz, the 2× chroma-to-line frequency modulus must be 455, etc. 
     The subsystem set forth in FIG. 2 for producing the three primary colors is similar to the system set forth in my copending U.S. Patent Application Ser. No. 677,196 which produces a single primary color raster. The subsystem as depicted in FIG. 2 of this application, however, has the capability of producing all of three primary colors individually and collectively (as a COLOR QUAD pattern) under the control of a simple switch selection. To this end, the unit of this invention employs a pair of cascaded dual-channel multiplexers, 39 and 40, an AND gate 41, and a quad former 42 (as illustrated in FIGS. 3 and 6). Multiplexers 39 and 40 may be conventional, and may be, for example, dual 4 input multiplexers designated as 74153.  The multiplexers designated as 74153 and of the 7400 series are commercially available and may be obtained, for example, from Texas Instruments, Incorporated or other semiconductor manufacturer. 
     Referring again to FIG. 2, divide-by-two (÷2) flip-flop 35 divides the clock frequency by two to produce the 2× chroma frequency output which produces synchronizing inputs to chroma reference generator flip-flop 34 and to AND gate 41. Chroma reference generator 34 provides further division by two to produce the chroma reference frequency. Flip-flop 34 is slaved to flip-flop 35 and is synchronized with the clock which also synchronizes flip-flop 33. This enables flip-flops 33 and 34 to generate chroma signals having accurately controlled phase relationships of 0, 90, 180, or 270 degrees providing the proper steering signals are supplied to the J and K inputs of flip-flop 33. It should be noted that 0, 90, 180, and 270 degree phase relationships correspond to green (G-Y) red (R-Y), blue (B-Y), and cyan -(R-y), respectively. 
     As illustrated in FIG. 2, gray (flip-flop 33 in a static condition) is preferably substituted for the cyan that would be produced if the X 0  and Y 0  inputs of the chroma phase multiplexer 39, were connected to the Q and Q outputs of flip-flop 34 respectively, as indicated in dotted lines in FIG. 2. 
     Assuming the most simple case (RED RASTER selected by pattern select switch 20), the STROBE, A 1  and A 0  inputs to the color preselect dual multiplexer 40 are 0, 0, 1, respectively, as shown in the following pattern select truth table: 
     
                       TABLE I                                                     
______________________________________                                    
Pattern Select Truth Table                                                
PATTERN         ST--       A.sub.1  A.sub.0                               
______________________________________                                    
GREEN RASTER    0          0        0                                     
RED RASTER      0          0        1                                     
BLUE RASTER     0          1        0                                     
COLOR QUAD      0          1        1                                     
ALL OTHERS      1          X        X                                     
______________________________________                                    
 
    
     This causes the X 1  and Y 1  inputs to this preselect multiplexer to be addressed resulting in a &#34;1&#34; and a &#34;0&#34; appearing at the Q x  and Q y  outputs, respectively. The &#34;1&#34; from Q x  causes OR gate 44 to supply a &#34;1&#34; to the Y 1  input to the weighted video multiplexer 45 (illustrated in FIGS. 3 and 7) to indicate that a primary color is being produced. Multiplexer 45 may be conventional and may be, for example, two eight input multiplexers of the 7400 series. 
     The &#34;0&#34; output from Q y  of the color preselect multiplexer 40 appears at the STROBE input to the chroma phase multiplexer 39 to be enabled. The &#34;1&#34; and &#34;0&#34;, respectively, which appear at the A 0  and A 1  inputs to the chroma phase multiplexer 39 cause the X 1  and Y 1  inputs to be addressed. This causes the chroma phase multiplexer to pass the Q and Q outputs of the reference chroma generator 34, to the J and K inputs, respectively, of the slaved chroma flip-flop 33. 
     It can be seen from the foregoing that the Q and Q outputs of the slaved chroma flip-flop 33 lag in phase the Q and Q outputs, respectively, of the reference chroma generator 34 by exactly one clock cycle. In this example, these flip-flops can be thought of as two successive stages of a shift register. It should be noted that, since the clock frequency is exactly four times the chroma frequency, the phase lag between these two flip-flops is exactly 90 degrees at the chroma frequency, i.e. they operate in quadrature producing an R-Y output. 
     Assuming now a slightly more difficult case (BLUE RASTER selected), 0, 1, 0 appears at the respective STROBE, A 1  and A 0  inputs of the color preselect multiplexer causing the X 2  and Y 2  inputs to be addressed and &#34;1&#39;s&#34; to appear at both Q x  and Q y . The &#34;1&#34; output of Q y  again causes OR gate 44 to indicate that a primary color is being produced. The &#34;1&#34; from Q y  also appears at an input of AND gate 41 allowing the Q output of flip-flop 35 to control the STROBE input to the chroma phase multiplexer 39. The &#34;1&#34; inputs to both A 0  and A 1  of the chroma phase multiplexer address the X 3  and Y 3  inputs. It can be seen from this that, if it were not for the additional delay introduced by the STROBE input, a red raster would be produced since the operation would be identical to the case analyzed above with RED RASTER selected (note that the X 3  and Y 3  inputs correspond exactly with the X 1  and Y 1  inputs, respectively). 
     An additional clock cycle of delay is introduced by the Q output of flip-flop 35 which appears via AND gate 41 at the STROBE input to the chroma phase multiplexer 39. This results from the fact that the same clock cycle which causes the reference chroma generator to change state also causes the Q output of flip-flop 35 to transfer to the &#34;1&#34; state. This disables the chroma phase multiplexer causing &#34;0&#39;s&#34; to appear at both its Q x  and Q y  outputs, thus placing the slaved chroma flip-flop 33 in its &#34;hold&#34; state. On the next clock cycle (90 degrees phase delay), the chroma phase multiplexer is again enabled when the Q output of flip-flop 35 transfers to the &#34;0&#34; state causing the Q and Q outputs of the reference chroma generator to appear at the J and K inputs of the slaved chroma flip-flop 33. On the next clock cycle (180 degrees phase delay), the state of the outputs of the slaved chroma flip-flop 33 will transfer. A blue (B-Y) chroma output is produced by this 180 degree phase delay from the reference (burst) signal. 
     The GREEN RASTER pattern (360 degrees phase delay from burst) is produced in the same manner as the BLUE RASTER pattern (180 degrees phase delay) except that an additional 180 degrees phase shift is introduced by reversing the phase of the X 2  and Y 2  inputs to the chroma phase multiplexer 39 as compared to the respective phases of the X 3  and Y 3  inputs. 
     With the COLOR QUAD pattern selected by pattern select switch 20, the STROBE, A 1  and A 2  inputs to the color preselect multiplexer are 0, 1, 1, respectively. The preselector is thereby enabled and the X 3  and Y 3  inputs are addressed. This causes the split line and split field outputs of the quad former subsystem 42 to appear at Q x  and Q y  outputs, respectively, of the color preselect multiplexer. The field and line splitter waveforms shown at the F and G inputs to FIG. 2 are seen to transfer from &#34;1&#34; to &#34;0&#34; in the center of the field and from &#34;0&#34; to &#34;1&#34; in the center of a line, respectively. Since a TV scans the field from top to bottom of the screen and the lines from left to right, it can be seen that these field and line splitting waveforms are &#34;1&#34; and &#34;0&#34;, respectively, in the upper left quadrant since both scans are just starting out. It can be seen from this that a &#34;0&#34; and a &#34;1&#34; appear at the respective X 3  and Y 3  inputs to the color preselect multiplexer thus causing a &#34;0&#34; and a &#34;1&#34; to appear at the Q x  and Q y  outputs, respectively. This &#34;0&#34; and &#34;1&#34; appear at the A 0  and A 1  inputs, respectively, of the chroma phase multiplexer thus addressing the X 2  and Y 2  (green) inputs. It can be seen from this that the upper left quadrant of the T.V. screen will therefore be green and an extension of this analyses will show that the upper right quadrant will be blue and that the lower right quadrant will be red, as indicated in FIG. 8. 
     During scanning of the lower left quadrant of the T.V. screen, the split line and split field inputs arriving at X 3  and Y 3  of the color preselect multiplexer are both &#34;0&#39;s&#34; and these &#34;0&#39;s&#34; therefore appear at the Q x  and Q y  outputs. These &#34;O&#39;s&#34; arriving at the A 0  and A 1  inputs of the chroma phase multiplexer 39 cause the X 0  and Y 0  (black and white) inputs to be addressed. The &#34;1&#34; and &#34;0&#34; at the X 0  and Y 0  inputs, respectively, therefore appear at the Q x  and Q y  outputs. This &#34;1&#34; and &#34;0&#34; thus appear at the J and K inputs, respectively, of the slaved chroma flip-flop 33, causing its Q output to hold in the &#34;1&#34; state. It can be seen from this that no chroma is produced in the lower left quadrant as shown in FIG. 8. 
     A study of the video multiplexer/matrixing subsystem will show that the lower left quadrant is light gray. Note that if the X 0  and Y 0  inputs to the chroma phase multiplexer were alternately connected to the Q and Q outputs, respectively, of the reference chroma generator 34, a chroma signal would be produced in the lower left quadrant of the T.V. screen. Since this chroma signal would be out of phase with the red chroma signal (X 1  and Y 1  inputs) it would be -(R-Y) which is cyan. 
     During retrace of the vertical and horizontal scanning subsystems in the T.V., the slaved chroma flip-flop 33 is disabled by the composite retrace blanking output of OR gate 46 causing the Q output of the slaved chroma flip-flop 33 to hold in the &#34;1&#34; state. 
     When any color pattern is selected, a burst gate signal (the burst portion of the burst and rainbow gate) arrives at an input to NAND gate 48, enabling it to pass a sample of the reference chroma signal to the CHROMA LEVEL control 22 through NAND gate 49. This burst is generated during the &#34;back porch&#34; interval which follows the horizontal sync pulse and is used by the AFPC (automatic frequency and phase control) circuit in the T.V. to synchronize the color sync oscillator. 
     With either gated rainbow pattern (COLOR BARS or VECTOR) selected, a composite burst and rainbow gate signal arrives at NAND gate 48 to gate the 3.563811 MHz offset carrier, whereas with 3.58 MONITOR selected the burst is deleted in order to make the color sync oscillator in the T.V. free-run as described in my copending U.S. Patent Application Ser. No. 677,196. Note that the offset carrier is generated by the reference chroma generator 34. It is one-fourth the frequency of the 14.255245 MHz master clock oscillator 30, and is used as a chroma signal for producing the familiar gated rainbow patterns. This 3.563811 MHz chromas signal is &#34;offset&#34; by an amount exactly equal to the 15.734265 KHz line scanning frequency. 
     It might also be noted that, with the slaved chroma flip-flop 33 in its hold state, a &#34;0&#34; from its Q output clamps the CCW end of the CHROMA LEVEL control to ground and enables the control to adjust the level of the gated rainbow, 3.58 MONITOR, and color burst signals. When a primary color is being produced, however, identical chroma signals arrive in phase at both the CW and CCW ends of the CHROMA LEVEL control. Through this highly effective and low cost method of combining the burst and primary color chroma signals it is possible to adjust the relationship of their amplitudes in such a manner (primary color signals greater amplitude than burst signals) that highly saturated colors are produced. This feature is extremely useful in checking the bandpass amplifier and automatic chroma control circuits, and in comparing the dynamic range of the separate electron guns in the picture tube, and also in checking and adjusting color purity. 
     In FIG. 3, the interrelationships of the various timing place control subsystems are depicted with little detail being included relative to the internal composition of these blocks illustrating conventional subject matter, since such blocks, as well as the interfaces therebetween, are thought to be well known and self explanatory. The blocks illustrated as quad former 42, weighted video multiplexer 45, and HATCHDOTS subsystem 50, have, however been presented in greater detail in FIGS. 6 through 8. 
     Wherever a dashed line appears in the drawings, in place of a conductor, it is used to represent a data bus with unspecified number of conductors. Data flows over the bus from a generating source such as the pattern selector switch or a counter and is received by the various subsystems. Data flow is in the direction indicated by the arrows, and there is no implication that the number of lines used is equal to the number shown leaving the generator or arriving at the receiver. In all cases, data bus or single conductor, the arrows indicate the direction of data flow (not current flow). 
     Referring to FIG. 3, the reference phase chroma gate generator 51 can be seen to receive data from the pattern selector switch 20, the 2× chroma-to-line frequency variable modulus counter 37, and the vertical sync generator 52. Actually, two inputs are shown from counter 37, one of which is specified to be 12 times the line frequency. The burst and rainbow gate outputs consist of a burst gate which follows the horizontal sync pulse during the horizontal blanking interval and/or 10 rainbow pattern gates, each 15 degrees wide with 15 degree interpulse spacing. The significance of the 12× line frequency square wave is that it spaces the color bars at 30 degree (360/12) intervals to produce the familiar gated rainbow pattern. The most simple implementation for the reference phase chroma gate generator uses some NAND gates, but other configurations are possible. It should be noted that the vertical sync is applied as an inhibit (NOT) input and, therefore, no color burst is generated when the vertical sync is present. 
     The horizontal blanking generator 54 and the vertical blanking generator 55 generate retrace blanking outputs that override the weighted video multiplexer outputs and blank the respective beam retrace lines in the conventional manner by producing the black level during these respective intervals. 
     The horizontal sync generator 56 and the vertical sync generator 52 produce these respective functions in the conventional manner. These occur during the respective retrace intervals (black level as described above) and are summed with the black level to produce the blacker-than-black (sync) level video output. 
     As shown in FIG. 3, the line frequency output from counter 37 is coupled by a divide-by-two circuit 57 to supply a 1/2 line frequency trigger output, with the output from counter 37 also being coupled to line-to-field frequency counter 58 which provides outputs to quad former 42 and a vertical trigger output. 
     FIG. 3 also shows the quad former subsystem 42 in brief form to illustrate its interfaces with other subsystems. The purpose of the quad former is to produce outputs which divide the T.V. screen into four equal quadrants as required to produce the GRAY QUAD and COLOR QUAD patterns as shown respectively in FIGS. 9 and 8. 
     The quad former subsystem 42 is set forth in greater detail in FIG. 5. As shown in FIG. 5, AND gate 59 receives digital inputs from the pattern selector switch 20 and enables the quad former subsystem 42 when either the GRAY QUAD or the COLOR QUAD pattern is selected. At all other times latch 60 and flip-flop 61 are held in a quiescent state with &#34;1&#39;s&#34; appearing at the Q outputs of the latch and the flop-flop. 
     Line splitter 60 is a conventional asynchronous latch that includes NAND gates 62 and 63. This latch is reset upon receipt of each horizontal retrace blanking pulse as it arrives at the input of NOT gate 64. The Q output of the latch is in the &#34;0&#34; state during the first half of the line-scanning interval. NAND gate 65 receives inputs from the 2 × chroma-to-line frequency counter subsystem 37. When the count indicates that the T.V. scanning beam is in the center of the screen from left to right (midway between retrace blanking pulses), the output of NAND gate 65 charges state from a &#34;1&#34; to a &#34;0&#34; level causing the Q output of the latch to transfer from a &#34;0&#34; to a &#34;1&#34; level at the center of the T.V. screen and to remain at the &#34;1&#34; level for the scanning of the right half of the line. This action repeats for each scanning line. 
     The action of the field splitter flip-flop 61 is essentially like that of the line splitter latch except it is reset (Q transferred to the &#34;1&#34; state) by the vertical sync pulse and is enabled to set (transfer of Q to the &#34;0&#34; state) in the center of the field by the output of AND gate 66. The actual transfer of Q to the &#34;0&#34; state is synchronized to the line-scanning by the horizontal retrace blanking pulse at the clock input to the field splitter. This synchronization is required in an interlaced system since on alternate fields the center of the field scanning occurs in the center of a line causing a displeasing appearance. 
     It can be observed that the field splitter is actually another latch. If it is used in a non-interlaced generator, it can be asynchronous; whereas, if it is used in a generator that produces interlaced scanning, it must be synchronized to the line-scanning circuits. The outputs of the line splitter and field splitter are employed with a binary weighting of one and two, respectively, in both the color preselect multiplexer and the weighted video multiplexer to produce the GRAY QUAD and the COLOR QUAD patterns. Note that the four binary combinations (0, 1, 2, and 3) suffice to define the four quadrants of the T.V. screen for the purposes of producing four shades of gray or four colors as shown in FIGS. 8 and 9. The unit weighting of the line splitter and the double weighting of the field splitter outputs, respectively, could be reversed if expedient. 
     Referring again to FIG. 3, the vertical lines generator 68 and the horizontal lines generator 69, each generate two sets of lines. The (A) set of vertical lines consists of 10, vertical lines equally spaced throughout the visible portion of the T.V. screen. The (B) set of vertical lines is generated with a 15, degree offset so that they are accurately centered between the (A) set. The same type of interspacing is used in generating the (A) and (B) sets of horizontal lines. The (A) set of vertical and horizontal lines is not actually brought out to the T.V. screen as a crosshatch. Instead, their intersections are used to produce dots that are accurately centered within the squares of the crosshatch produced by the (B) set of vertical and horizontal lines. The DOTS generator 71 and the HATCHDOTS generator 72 are shown in FIG. 3, but the subsystem 50 is set forth in greater detail in FIG. 6. 
     Referring to FIG. 6, it can be seen that outputs from the countdown circuits that produce the line and field scanning synchronizing signals are also used as inputs to the subsystem that produces the convergence patterns. A plurality of digital signals which are frequency and phase correlated with the line and field scanning are thus supplied as inputs to gates 74 through 82. AND gates 74 and 75, respectively, produce the vertical lines (A) and horizontal lines (A) patterns. Notice that these patterns are not displayed on the T.V. screen in the preferred embodiment of the invention, but could be if they were supplied to the video multiplexer and two additional pattern selections were added to the pattern selector switch 20. The vertical and horizontal lines functions (not actual  patterns) are supplied to NAND gate 84 to produce an array of 100 dots which correspond with the 100 intersections of these vertical and horizontal lines functions. The NOT (inverted) sense is used for these dots since that is the sense required for causing a white dot or other white pattern element to appear on the black T.V. screen background. 
     AND gates 76 through 80 produce outputs which enable certain columns and rows of dots plus the center dot to be displayed as the dots portion of the HATCHDOTS patterns as shown in FIG. 10. The outputs of all these gates are supplied through OR gate 85 to NAND gate 86. The 100 dots output through NOT gate 87 is also supplied as an input to NAND gate 86. The output of NAND gate 86 is therefore an array of inverted (white) dots which pass through AND gate 88 to become part of the HATCHDOTS pattern. 
     The vertical lines (B) and horizontal lines (B) functions produced by NAND gates 81 and 82 respectively, are OR&#39;ed together, in a negative sense, to produce the 10× 10 crosshatch pattern at the output of AND gate 89. The actual use of this pattern as a crosshatch on the T.V. screen is optional, but it is generated as an interim function so that it can be OR&#39;ed in a negative sense, with the frame and center dots output of NAND gate 86, to produce the HATCHDOTS pattern output resulting in the HATCHDOTS pattern as shown in FIG. 10. The HATCHDOTS pattern is a composite convergence pattern, and, as shown in FIG. 10, has a single center dot, a crosshatch, and a frame of dots pattern. The pattern is useful for size, linearity, centering, and pincushion checks and/or adjustments. 
     It might be noted that, if there is no requirement for displaying the crosshatch pattern, AND gates 88 and 89 can be combined into a single three-input AND gate, but are shown as two separate gates in FIG. 6 for simplicity of understanding. Other hardware simplifications could be achieved by combining certain of these gates with other subsystems, if desired. 
     Referring again to FIG. 3, the video multiplexing subsystem which includes weighted video multiplexer 45 and OR gates 91, 92, and 93 can be seen in relationship to their interfaces which include most of the subsystems in the generator. Referring to FIG. 7 for increased detail, it can be seen that the weighted video multiplexer 45 receives inputs from the pattern selector switch 20, which with their 1, 2, 4 binary weighting are more than sufficient to address the six pairs of inputs from the various subsystems. When a pair of X and Y inputs is addressed, the signals present at these inputs appear at Q x  and Q y , respectively. During the scanning of the visible portion of the T.V. screen (no blanking or sync signals), the Q x  and Q y  outputs pass through OR gates 91 and 92, respectively, and appear at the outputs of these gates as unit-weighted video (A) and double-weighted video. These and the unit-weighted video (B) output are later combined in a weighted summing network to produce five levels of video signal in the proportions indicated in a T.V. TRUTH TABLE as follows: 
     
                       TABLE II                                                    
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T.V. VIDEO TRUTH TABLE                                                    
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       0            White                                                 
       1            Light Gray                                            
       2            Dark Gray                                             
       3            Black                                                 
       4            Sync                                                  
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     If a COLOR BARS pattern is selected, the &#34;1&#34; at the double-weighted Y 0  input and the square wave at the unit-weighted X 0  input produce a video output that alternates between dark gray (2) and black (3). Other circuitry causes chroma signals to be produced in synchronism with the dark gray luminance pedestals thus produced. 
     As described previously, if a primary color is being produced, which includes three quadrants of the COLOR QUAD pattern, this is indicated by a &#34;1&#34; appearing at X 2 . With &#34;1&#39;s&#34; thus appearing at both inputs, a black (3) level background is produced. During scanning of the lower left quadrant of the COLOR QUAD pattern, the primary color indicator is a &#34;0&#34; causing the light gray (1) level to be produced. 
     With the GRAY QUAD pattern selected, the outputs of the quad former unit 42 are selected. The X 2  input transfers from a &#34;1&#34; to a &#34;0&#34; level in the center of each line and the Y 2  input transfers from a &#34;1&#34; to a &#34;0&#34; in the center of each field (in synchronism with the beginning of the next line). This causes four luminance levels, white, light gray, dark gray, and black to occupy their respective quadrants of the T.V. screen as illustrated in FIG. 9. The GRAY QUAD pattern illustrated in FIG. 9 is useful in providing a panoramic view of high, medium and low light for checking and adjusting gray scale tracking. The pattern is also useful in conjunction with calibrated RF output for checking receiver sensitivity, as well as providing a check of 60 Hz video response and a convenient check of yoke polarity. 
     Referring again to FIG. 7, with the 3.58 MONITOR or VECTOR pattern selected, both of the selected inputs are &#34;1&#39;s&#34; causing a black level background to be produced. 
     With HATCHDOTS or DOTS selected, the respective X and Y inputs are both &#34;1&#39;s&#34; (black level) when background areas of these convergence patterns are being scanned and both inputs transfer to the &#34;0&#34; level when white pattern elements are being generated. 
     When either of the retrace blanking signals is present at the respective inputs of OR gates 91 and 92, the black level (3) is produced. These signals override the outputs of the weighted video multiplexer. When either of the synchronizing signals is present at a respective input of OR gate 93, the output of this OR gate transfers to the &#34;1&#34; level. Since synchronizing signals always occur during a respective retrace blanking interval (black level already present), the blacker-than-black (sync) level is caused to be produced. The sync signals have a total video weighting of 4. 
     Referring now to FIG. 4, the composite chroma and three weighted video inputs are shown at the left of the diagram. The composite chroma is supplied from the CHROMA control 22, and the weighted video inputs are supplied by the viedo multiplexer subsystem. Four resistors, 95, 96, 97 and 98, are used to sum these inputs into a composite video signal with proper weighting. To this end, resistors 95 and 97 each have a resistance value, R 1 , and 96 has a resistance of one-half this value. Since all three of these resistors are supplied digital (nominally equal amplitude) input signals, the composite video signal thus supplied to the RF modulator 100, which receives an input from RF oscillator 101, is caused to have the proper weighting factors per the &#34;T.V. VIDEO TRUTH TABLE&#34; as set forth hereinabove. The resistance value of R c  (resistor 98) is chosen to provide the proper level of chroma signal in the composite video output. 
     The video polarity control subsystem 103 consists of EXCLUSIVE OR gates 104, 105, and 106, plus selector switch 107. In the preferred embodiment of the invention, this selector switch is ganged with the CHROMA LEVEL control 22. When the POLARITY SELECT switch 107 is pushed in (open), the &#34;1&#34; state exists on the respective control inputs to the three EXCLUSIVE OR gates 104 through 106 causing them to invert their inputs. The digital inputs to the EXCLUSIVE OR gates are the positive &#34;1&#34; level for producing the sync signals as required by the RF modulator. Since the EXCLUSIVE OR gates invert their signal inputs when their control inputs are at the &#34;1&#34; level, the outputs of these EXCLUSIVE OR gates can be seen to be appropriated for producing a negative sync video signal under the stated conditions. With the VIDEO POLARITY SELECT switch in the &#34;pulled&#34; (closed) condition, the EXCLUSIVE OR gates do not invert their signal inputs, and a video signal with positive sync polarity is produced. 
     The video and chroma output summing junction consists of resistors 109, 110, 111 and 112. Their weighted summing action is the same as that for the previously discussed summing junction that supplies the input to the RF modulator 100, except that lower resistance values are used in order to produce a low impedance video output with the proper characteristics for driving a 75 ohm coaxial line. Capacitive output coupling (not shown) is employed in the preferred embodiment of the invention. 
     As shown in the alternate embodiment of FIG. 11, chroma phase angles can also be produced in increments of 360/N degrees by the use of an N-stage shift register (shown as an 8 stage shift register 114 in FIG. 11), if such a shift register is supplied a chroma frequency serial input and clock at N times the chroma frequency. As shown in FIG. 11, shift register 114 is supplied a clock input from the 24× chroma frequency clock input, with the serial input being supplied from the Q output of reference chroma generator 115, which generator receives an input from divide-by-twelve (÷12) circuit 116. 
     The outputs fro shift register 114 are coupled to chroma phase multiplexer 39, the Q output of which is coupled to slaved chroma flip-flop 33. The clock input to flip-flop 33 is supplied from an 85.909 MHz clock oscillator 118 (which also supplies the 24× chroma frequency clock output), and the Q output of reference generator 115 is coupled to NAND gate 48 which is connected with NAND gate 49 in the same manner as described hereinabove in connection with FIG. 2. 
     The A 0 , A 1 , and A 2  inputs to multiplexer 39 are coupled from the Q 0 , Q 1 , and Q 2  outputs from divide-by-eight binary counter 119 which receives a clock input through AND gate 120 as shown in FIG. 11. 
     A tabulation of the chroma phase error for the embodiment as illustrated in FIG. 11 is as follows: 
     
                       TABLE III                                                   
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CHROMA PHASE ERROR TABULATION                                             
       Color  NTSC    Actual  Errors                                      
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       White  --      --      --                                          
       Yellow 12°                                                  
                      15°                                          
                              +3°                                  
       Cyan   256.5°                                               
                      255°                                         
                              -1.5°                                
       Green  299.9°                                               
                      300°                                         
                              +0.1°                                
       Magenta                                                            
              119.9°                                               
                      120°                                         
                              +0.1°                                
       Red    76.5°                                                
                      75°                                          
                              -1.5°                                
       Blue   192°                                                 
                      195°                                         
                              +3°                                  
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     The embodiment of FIG. 11 can be used to produce an NTSC type color bar pattern generator that is more accurate and lower in cost than any units known to have been produced, and a generator thus implemented is completely free of the usual delay lines and phase adjustments. If so utilized, a staircase of illuminates, as is well known in the art, would be included.