Digital exposure display circuit
BACKGROUND OF THE INVENTION 
     This invention relates to exposure information display circuits in cameras, and more particularly to a display circuit in which various inputs are subjected to digital operations, and the resultant outputs are employed to display various pieces of exposure information in the finder. 
     A large number of pieces of information are necessarily displayed in high-grade cameras employing a variety of photographing systems, such as for instance a so-called lens stop priority system in which the lens stop is manually set and the shutter speed is set automatically (hereinafter referred to as &#34;an ES system&#34; when applicable), so-called shutter speed priority photographing system in which the shutter speed is manually set and the lens stop is set automatically (hereinafter referred to as &#34;an ES system&#34; when applicable), and a so-called manual photographing system in which both of the lens stop and the shutter speed are manually set. That is, it is necessary to display characters or symbols by which the automatically set shutter speed in the ES system are indicated, to display characters or symbols by which the automatically set lens stop value in the EE system are indicated, and to display characters or symbols by which the condition indicating whether or not the correct exposure determined by manually setting the shutter speed and the lens stop and the difference from the correct exposure are indicated in the case where the manual photographing system is employed. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to provide a display circuit simple in construction which operates a display element such as a light emitting diode (LED) to display the above-described exposure information. This specific feature of the display circuit according to the invention resides in that voltage information as analog data in various photographing systems is converted into digital data by one common analog-to-digital converter circuit (hereinafter referred to as &#34;an A/D converter circuit&#34; when applicable). 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is a block diagram illustrating one example of a digital exposure display circuit according to this invention; 
     FIG. 2 is a schematic circuit diagram showing a light measuring circuit 1, and S V  calculating circuit 2, an A V  calculating circuit 3, a constant voltage source 4 and a voltage source 5 shown in FIG. 1; 
     FIG. 3 is a schematic circuit diagram illustrating a specific example of selection circuits 6 and 7 and a logic circuit 8 shown in FIG. 1; 
     FIG. 4 is also a schematic circuit diagram showing an another specific example of the selection circuits 6 and 7; 
     FIG. 5 is a block diagram showing an example of an A/D converter circuit 11 shown in FIG. 1; 
     FIG. 6 is a schematic circuit diagram illustrating a specific example of a D/A converter circuit 64 and a comparison circuit 63 shown in FIG. 5; 
     FIG. 7 is a schematic circuit diagram illustrating a specific example of a logic circuit 65, a counter 66, an oscillator 67 and a latch circuit 68 shown in FIG. 5; 
     FIG. 8 is an explanatory diagram illustrating one example of a character and symbol displaying section of a display element 13; and 
     FIG. 9 is a schematic circuit diagram showing one example of a drive circuit for the display element. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     One example of a digital exposure display circuit according to the invention is shown in FIG. 1 in which a light measuring circuit 1 generates the apex value B V  of an object&#39;s brightness, and the output of the light measuring circuit 1 is connected to an S V  calculating circuit 2 operating to generate the apex value S V  of film sensitivity. An A V  calculating circuit 3 is connected to the circuit 2 for generating the apex value A V  of a camera&#39;s lens stop value. The outputs of the circuits 2 and 3 are applied to a selection circuit 6. (Hereinafter, the output of the S V  calculating circuit 2 will be represented by B which has been suitably shifted, and the output of the A V  calculating circuit 2 will be represented by A.) A constant voltage source 4 provides a constant voltage corresponding to the apex value T V  =11 which corresponds to a shutter speed of 1/2000  second in the ES system, and a voltage source 5 generates a voltage corresponding to the apex value T V  in the EE photographing system or in the manual photographing system. The outputs of the constant voltage source 4 and the voltage source 5 are applied to a selection circuit 7. (Hereinafter, the outputs of the constant voltage source 4 and the voltage source 5 will be represented by A&#39; and B&#39;, respectively). The aforementioned outputs A, B, A&#39; and B&#39; satisfy the following relations: A&#39;≧A, B&#39;≧B, and B&#39;≧A. A logic circuit 8 is controlled by switches 9 and 10 operating in association with a mechanism (not shown) which operates to switch between the three photographing systems. The outputs A or B, and A&#39; or B&#39; are applied to an analog-to-digital (A/D) converter 11 through the selection circuits 6 and 7 which are controlled by the logic circuit 8. The A/D converter 11 is so designed as to convert the difference voltage between the two voltages applied thereto into a digital output. An IC memory 12, that is, a read only memory (ROM), is addressed by the A/D converter 11 and the logic circuit 8. A display element 13 displays numbers, characters or symbols and typically consists of a plurality of segments. The display element 13 is driven by the outputs of the ROM 12 and the logic circuit 8. 
     In response to the on-off operations of the switches 9 and 10, the logic circuit 8 operates to apply the outputs A and A&#39; through the selection circuits 6 and 7 to the A/D converter circuit 11, in the case of the ES system. The output A is a voltage obtained by combining the object&#39;s brightness apex value B V , the film sensitivity apex value S V , and the aperture apex value A V , while the output A&#39; is a constant voltage corresponding to T V  11 (=1/2000 second), as was described above. Therefore, the digital data obtained by the difference voltage applied to the A/D converter 11 corresponds to the shutter speed which is automatically set in the ES photographing system. Similarly, in the case of the EE photographing system, the outputs B and B&#39; are applied to the A/D converter circuit 11. The output B is a voltage obtained by combining the object&#39;s brightness apex value B V  and the film sensitivity apex value S V , while the output B&#39; is a voltage corresponding to the shutter speed apex value T V , as was described before. Therefore, the digital data obtained by the difference voltage applied to the A/D converter 11 is the lens stop value which is automatically set in the EE photographing system. In the case of the manual photographing system, the outputs A and B&#39; are applied to the A/D converter circuit 11. The output A is a voltage obtained by combining the outputs B V , S V  and A V , while the output B&#39; is a voltage corresponding to the shutter speed apex T V , as was described before. Therefore, the digital data obtained by the difference voltage applied to the A/D converter 11 will indicate whether or not the exposure is suitable, or a value which differs from the suitable exposure value, in the manual photographing system. Exposure information is obtained from the output of the ROM which is addressed by the outputs of the logic circuit 8 and the A/D converter circuit 11, and is displayed by the display element 13. The output of the logic circuit 8 is applied, as information, to the display element 13 so as to cause the element 13 to display the selected photographing system: the ES system, the EE system, or the manual system. 
     FIG. 2 shows more concretely the light measuring circuit 1, the S V  calculating circuit 2, the A V  calculating circuit 3, the constant voltage circuit 4 and the voltage source 5 shown in FIG. 1. In FIG. 2, the collector of a logarithmic compression transistor 14 is connected to the gate of a field-effect transistor (FET) 16 which forms a self-biasing circuit with a light receiving element 15 and a resistor 17. The source of the FET 16 is connected to the base of a transistor 18 which forms an emitter follower having as a load the parallel connection of a series circuit of an S V  variable resistor 19 corresponding to the film sensitivity apex value S V  and a constant current source 20, a series circuit of a level shifting resistor 32 and a constant current source 22, and a series circuit of an A V  variable resistor 23 corresponding to the aperture apex value A V  and a constant current source 24. The constant current source 20 is connected to the base of the transistor 14. A diode 26 is connected in series with a constant current source 25 across a power supply 35. A T V  variable resistor 29 is manually set corresponding to the shutter speed apex value T V  in the case of the EE photographing system or in the manual photographing system. One terminal of the variable resistor 29 is grounded, while the other terminal thereof is connected to the base of a transistor 31 whose emitter is grounded and to the cathode of a diode 28. The anode of the diode 28 is connected to the emitter of a transistor 27 whose base is connected to a constant current source 30. This constant current source 30 is connected to the collector of the transistor 31 and to the base of a transistor 32 the collector of which is connected to the power supply 35. The emitter of the transistor 32 is connected through a diode 33 to a resistor 34 which is grounded. 
     The operation of the circuit shown in FIG. 2 will be described. Feed-back is effected from the collector of the transistor 14 which is driven in a constant current mode by the photocurrent i p  of the light receiving element 15, through the FET 16, the transistor 18, and the S V  variable resistor 19 to the base of the transistor 14. Therefore, the base-emitter voltage V 1  of the transistor 14 can be expressed by the following equation (1): ##EQU1## where 
     K: Boltzmann&#39;s constant 
     T: absolute temperature 
     q: electric charge 
     V O  : the base-emitter voltage with the collector current i O   
     If it is assumed that the resistance of the variable resistor 19 is represented by R 19 , and the currents of the constant current sources 20, 22 and 24 are represented by i 20 , i 22  and i 24 , respectively then the voltage V 2  at the emitter of the transistor 18 is: 
     
         V.sub.2 =V.sub.1 +i.sub.20 ·R.sub.19              (2) 
    
     If it is assumed that the resistance of the level shifting resistor 21 is represented by R 21 , then the voltage V 3  due to the voltage drop of the resistor 21 is expressed by the following equation (3): 
     
         V.sub.3 =V.sub.2 -i.sub.22 ·R.sub.21              (3) 
    
     The voltage V 3  corresponds to the output B of the S V  calculating circuit 2. If the resistance of the A V  variable resistor 23 is represented by R 23 , then the voltage V 4  due to the voltage drop of the variable resistor 23 is: 
     
         V.sub.4 =V.sub.2 -i.sub.24 ·R.sub.23              (4) 
    
     The voltage V 4  corresponds to the output A of the A V  calculating circuit 3. A voltage V 5  developed across the diode 26 by the current of the constant current source 25 can be expressed by the following equation (5) if the current is represented by i 25  : ##EQU2## The voltage V 5  corresponds to the output A&#39; of the constant voltage source 4. 
     If the resistance of the T V  variable resistor 29 is R 29 , the base-emitter voltage of the transistor 31 is V BE31 , the resistance of the resistor 34 is R 34 , a voltage across the resistor 34 is V 6 , and the collector currents of the transistors 27 and 32 are i 27  and i 32 , respectively, then the following equations (6) and (7) can be established: 
     
         i.sub.27 =V.sub.BE31 /R.sub.29                             (6) 
    
     
         i.sub.32 =V.sub.g /R.sub.34                                (7) 
    
     In addition, if it is assumed that the base potentials of the transistors 27 and 32 are equal to V N , then ##EQU3## Since the variations of the currents i 27  and i 32  due to the variations of the voltage V BE31  and V 6  are slight and can be approximated to V BE31  ≃V 6 , the voltage V 6  can be calculated from the equations (6) through (8) as follows: ##EQU4## where i 30  is the current of the constant current source 30. The voltage V 6  corresponds to the output B&#39; of the voltage source 5. 
     Now, V 5  -V 4 , that is, A&#39;-A will be obtained. 
     From the equations (1), (2), (4) and (5): ##EQU5## As i p  =i p .sbsb.o 2B V , equation (10) can be rewritten into the following equation (11) where i 25  =2 n  i p .sbsb.o and i p .sbsb.o is the photocurrent with B V  =0: ##EQU6## the term ##EQU7## indicates displacement corresponding to the variation of the object&#39;s brightness, and the term ##EQU8## indicates a displacement value per exposure value step (variation of 1EV). In addition, if the displacement values for the terms i 20  ·R 19  and i 24  ·R 23  are set to be ##EQU9## the term i 20  ·R 19  can be rewritten as ##EQU10## while the term i 24  ·R 23  can be rewritten as ##EQU11## Therefore, the above-described equation (11) can be rewritten into equation (12) indicated below: ##EQU12## 
     In general, under the condition that the exposure is correct, the following equation (13) can be established: 
     
         B.sub.V +S.sub.V =A.sub.V +T.sub.V                         (13) 
    
     If equation (13) is substituted into equation (12), then ##EQU13## As the output A&#39; is the constant voltage corresponding to T V  =11 in equation (13) as was described before, n=11 can be obtained by assuming A&#39;=A. Therefore, equation (14) can be rewritten into the following equation (15): ##EQU14## Furthermore, with ##EQU15## from equation (15) 
     
         T.sub.V =11-k.sub.1                                        (16) 
    
     This means that if A&#39;=A, or k=0, then T V  =11 and ##EQU16## if k=1, that is, if the potential of A is lower by the unitary step ##EQU17## than that of A&#39;, then T V  =10, and so fourth. Accordingly, by subjecting the difference voltage between the outputs A&#39; and A to analog-to-digital conversion, the digital data corresponding to the shutter speed can be obtained. Similarly, B&#39;-B can be obtained from the following equation (17): ##EQU18## where i 30  =2 m  i p .sbsb.o. If the term ##EQU19## is replaced by ##EQU20## (k 2  being the constant determined from the ratio of R 29  to R 34 ), and R 34  =R 29 , then ##EQU21## Therefore, k 2  =2 log 2  α is obtained. If this is substituted into equation (17), then ##EQU22## If (i 20  R 19  -i 22  R 21 ) is set so as to change as much as ##EQU23## per step, then (i 20  R 19  -i 22  R 21 ) will become ##EQU24## (where k 3  is a constant). If addition, 2 log 2  α is the shutter speed value T V  which is determined by the T V   variable resistor 29 for α=0.5. If these are substituted into equation (18), then ##EQU25## 
     By substituting equation (13) into equation (19), equation (20) can be obtained: ##EQU26## Therefore, if m and k 3  are set to suitable values, the digital data corresponding to the aperture value can be obtained by subjecting the difference voltage between the outputs B&#39; and B to analog-to-digital conversion. 
     Then, B&#39;-A can be obtained similarly as in the above-described case; that is, B&#39;-A can be expressed by the following equation (21): ##EQU27## Similarly as in the case of equations (12) and (18), equation (21) can be rearranged as follows: ##EQU28## 
     If it is assumed that B V  +S V  -(A V  +T V )=k 4  (where k 4  is positive exposure and the amount of the difference from the correct exposure into account, then ##EQU29## Therefore, the digital data corresponding to the correct exposure and the amount of the difference from the correct exposure can be obtained by subjecting the difference voltage between the outputs B&#39; and A to analog-to-digital conversion. 
     FIG. 3 shows a concrete example of the selection circuits 6 and 7 and the logic circuit 8. In FIG. 3, one contact of switch 9 is connected to the negative terminal or ground of the power supply 35, and the other contact is connected through a resistor 36 to the positive terminal of the power supply 35. One contact of switch 10 is connected to the positive terminal of the power supply 35, and the other contact is connected through a resistor 37 to the negative terminal or ground of the power supply 35. The connection point (S9) of the switch 9 and the resistor 36 is connected to one input of an OR gate circuit 38, the control terminal of a transmission gate (TG) 43, an inverter 40, the address A 1  of the read only memory (ROM) 12, and an input terminal I 1  of the display element 13. The connection point (S10) of the switch 10 and the resistor 37 is connected to the other input of the OR gate circuit 38, the output of which is connected to the control terminal of a transmission gate 41, and inverter 39, the address A 0  of the ROM 12, and the input terminal I 0  of the display unit 13. The outputs of the inverters 39 and 40 are connected to the control terminals of transmission gates 42 and 44, respectively. The aforementioned outputs A and B are applied to the input terminals of the transmission gates 41 and 42, respectively. The outputs of the transmission gates 41 and 42 are connected together to the A/D converter circuit 11. The above-described outputs A&#39; and B&#39; are applied to the input terminals of the transmission gates 43 and 44, respectively, the outputs of which are connected together to the A/D converter circuit 11. 
     In the circuit thus organized, the connection point S9 is at an &#34;H&#34; or high level (which is a voltage higher than the threshold voltage of the transmission gates) when the switch 9 is open, and it is at an &#34;L&#34; or low level (which is a voltage lower than the threshold voltage of the transmission gates) when the switch 9 is closed. The connection point S10 is at the &#34;L&#34; level when the switch 10 is open, and it is at the &#34;H&#34; level when it is closed. Accordingly, the output of the OR gate circuit 38 is at the &#34;L&#34; level only when the switch 9 is closed and the switch 10 is open. In this case, the selection circuit 6 renders the transmission gate 42 conductive to apply the output B to the A/D converter circuit 11, and both the address A 0  of the ROM and the input I 0  of the display element 12 are at the &#34;L&#34; level. With the other combinations of the states of the switches 9 and 10, the output of the OR gate circuit 38 is at the &#34;H&#34; level, and the selection circuit 6 operates to render the transmission gate 41 conductive to apply the output A to the A/D converter circuit 11. In this case, both the address A 0  of the ROM and the input I 0  of the display element have the &#34;H&#34; level. When the switch 9 is open and the connection point S9 is at the &#34;H&#34; level, the selection circuit 7 renders the transmission gate 43 conductive to apply the output A&#39; to the A/D converter circuit 11. When the switch 9 is closed and the connection point S9 is at the &#34;L&#34; level, the selection circuit 7 renders the transmission gate 44 conductive to apply the output B&#39; to the A/D converter circuit 11, and the address A 1  of the ROM and the input I 1  are at the same level (&#34;H&#34; or &#34;L&#34;) as the connection point S9. 
     The operation described above is as indicated in Table 1 below: 
     
                       TABLE 1                                                     
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                  Output of                                               
                           Output of                                      
                                  Photo-                                  
                  selection                                               
                           selection                                      
                                  graphing                                
                                         A.sub.0                          
                                             A.sub.1                      
Switch S9                                                                 
        Switch S10                                                        
                  circuit 6                                               
                           circuit 7                                      
                                  system I.sub.0                          
                                             I.sub.1                      
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open    open      A        A&#39;     ES     H   H                            
open    closed    A        A&#39;     ES     H   H                            
closed  open      B        B&#39;     EE     L   L                            
closed  closed    A        B&#39;     Manual H   L                            
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     FIG. 4 illustrates another example of the selection circuits 6 and 7. The selection circuit 6 will be first described. Transistors 48 and 50 whose collectors are grounded are driven by a constant current source 49, and the emitters thereof are connected to the A/D converter circuit. The aforementioned output B is applied through a resistor 47 to the base of the transistor 48. This base of the transistor 48 is connected to the emitter of a transistor 46 whose base and collector are connected respectively to an OR gate 38 through a resistor 45 and to the positive terminal of the power supply 35. The above-described output A is applied through a resistor 53 to the base of a transistor 50, which is connected to the emitter of a transistor 51, the base and collector of which are connected respectively to an inverter 39 through a resistor 52 and to the positive terminal of the power supply 35. 
     In the selection circuit thus organized, when the output of the OR gate circuit 38 is at the &#34;L&#34; level and the output of the inverter 39 is at the &#34;H&#34; level, the transistors 46 and 51 are rendered non-conductive and conductive, respectively.Therefore, a voltage (B+V S1 ) is obtained at the emitters of the transistors 48 and 50, V S1  being the sum of a voltage developed across the resistor 47 and the base-emitter voltage of the transistor 48. In contrast, when the output of the OR gate circuit 38 is at the &#34;H&#34; level and the output of the inverter 39 is at the &#34;L&#34; level, a voltage (B+V S2 ) is obtained at the emitters of the transistors 48 and 50, V S2  being the sum of a voltage across the resistor 53 and the base-emitter voltage of the transistor 50. In general, in a circuit organized as in FIG. 4 in the form of an integrated circuit, V S1  ≃V S2 . If this data is replaced by V S , an output (B+V S ) or (A+V S ) is produced by the selection circuit 6. 
     The construction of the selection circuit 7 is similar to that of the selection circuit 6 as is apparent from FIG. 4. Therefore, an output (B&#39;+V S ) or (A&#39;+V S ) is produced by the selection circuit 7. The A/D converter circuit 11 is so designed to subject the difference voltages to analog-to-digital conversion, as previously described. 
     FIG. 5 shows an example of the above-described A/D converter circuit 11. In FIG. 5, reference numeral 67 designates an oscillator which is connected to a counter 66 operating to count pulses provided by the oscillator 67. Connected to the counter 66 are a digital-to-analog (D/A) converter circuit 64 for converting the count content of the counter 66 into an analog voltage. A latch circuit 68 is controlled by a logic circuit 65 which receives the outputs of the counter 66 and a comparison circuit 63 compares the information from the selection circuit 6 with that from the D/A converter circuit 64. The ROM 12 is connected to the output of latch circuit 68. 
     In the circuit 11 thus organized, the content of the counter 66 operating to count the output pulses of the oscillator 67 is converted into an analog voltage by the D/A converter circuit 64, the analog voltage being compared with the voltage from the selection circuit 6 in the comparison circuit 63. With the analog voltage reaches the value of the voltage from the selection circuit 6, the content of the counter 66 is stored in the latch circuit 68 through the operation of the logic circuit 65. A part of the ROM address is specified by applying the content of the latch circuit 68 to the ROM 12. 
     Shown in FIG. 6 are concrete examples of the D/A converter circuit 64 and the comparison circuit shown in FIG. 5. In FIG. 6, the output of a constant current source 69 is applied to the collector of a transistor 70 and is fed back to the base thereof through a transistor 72. The emitter regions (areas) of transistors 73, 75, 77 and 79 are set in the ratio of 1:2:4:8. Resistors 74, 76, 78 and 80 are connected to the emitters of the transistors 73, 75, 77 and 79, respectively. An operational amplifier 82 forms a voltage follower circuit for the above-described selection circuit 7. The aforementioned selection circuit 6 is connected to one input terminal of a comparator 83, and the output of the operational amplifier 82 is connected through a resistor 81 to the other input terminal of comparator 83. In the circuit thus organized, the relation (the output of the selection circuit 7)≧(the output of the selection circuit 6) is established. 
     The operation of the circuit shown in FIG. 6 will now be described. If the current of the constant current source 69 is represented by I and the resistance of the resistors 71, 74, 76, 78 and 80 are selected in the relation of 4:8:4:2:1, then the collector currents of the transistors 73, 75, 77 and 79 will be I/2, I, 2I and 4I, respectively. Furthermore, if the resistance of the resistor 81 is represented by R 81  and the voltage drop (I/2)×R 81  across the resistor 81 due to the collector current of the transistor 73 is made to be equal to the voltage per step ##EQU30## which is included in equations (11) through (23), a voltage lower by as much as an integer (0 to 15) multiple of the step voltage ##EQU31## than the voltage of the output A&#39; and B&#39; of the selection circuit 7 is applied to the common collector terminal of the transistors 73, 75, 77 and 79. If this voltage is expressed by V C , the relationships of the voltage V C  and the emitter terminals a, b, c and d of the transistors 73, 75, 77 and 79 are as indicated in Table 2 below: 
     
                       TABLE 2                                                     
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                    V.sub.C + A&#39; or           V.sub.C + A&#39; or             
d   c     b     a   V.sub.C + B&#39;                                          
                              d   c   b   a   V.sub.C + B&#39;                
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H   H     H     H   0         L   H   H   H                               
                                               ##STR1##                   
H   H     H     L                                                         
                     ##STR2## L   H   H   L                               
                                               ##STR3##                   
H   H     L     H                                                         
                     ##STR4## L   H   L   H                               
                                               ##STR5##                   
H   H     L     L                                                         
                     ##STR6## L   H   L   L                               
                                               ##STR7##                   
H   L     H     H                                                         
                     ##STR8## L   L   H   H                               
                                               ##STR9##                   
H   L     H     L                                                         
                     ##STR10##                                            
                              L   L   H   L                               
                                               ##STR11##                  
H   L     L     H                                                         
                     ##STR12##                                            
                              L   L   L   H                               
                                               ##STR13##                  
H   L     L     L                                                         
                     ##STR14##                                            
                              L   L   L   L                               
                                               ##STR15##                  
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     The voltage V C  and the output A or B of the selection circuit 6 are applied to the comparator 83. On the basis of Table 2, and equations (15), (20) and (23), the difference voltages applied in various photographing systems are converted into 4-bit digital signals. In the ES photographing system, the conversion is as indicated in Table 3 below on the basis of Table 2 and equation (15): 
     
                       TABLE 3                                                     
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d    c      b      a    T.sub.V                                           
                             d    c    b    a    T.sub.V                  
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H    H      H      H    11   L    H    H    H     3                       
H    H      H      L    10   L    H    H    L     2                       
H    H      L      H    9    L    H    L    H     1                       
H    H      L      L    8    L    H    L    L     0                       
H    L      H      H    7    L    L    H    H    -1                       
H    L      H      L    6    L    L    H    L    -2                       
H    L      L      H    5    L    L    L    H    -3                       
H    L      L      L    4    L    L    L    L    -4                       
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     Furthermore, if m=12 and k 3  =9 in equations (20) and (23), in the case of the EE photographing system or the manual photographing the following Table 4 can be obtained on the basis of Table 2: 
     
                       TABLE 4                                                     
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                     A.sub.V in EE                                        
                             K.sub.4 (exposure value difference)          
d   c     b     a    system  in manual system                             
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H   H     H     H    11      12 (12EV over)                               
H   H     H     L    10      11 (11EV over)                               
H   H     L     H    9       10 (10EV over)                               
H   H     L     L    8       9 (9EV over)                                 
H   L     H     H    7       8 (8EV over)                                 
H   L     H     L    6       7 (7EV over)                                 
H   L     L     H    5       6 (6EV over)                                 
H   L     L     L    4       5 (5EV over)                                 
L   H     H     H    3       4 (4EV over)                                 
L   H     H     L    2       3 (3EV over)                                 
L   H     L     H    1       2 (2EV over)                                 
L   H     L     L    0       1 (1EV over)                                 
L   L     H     H    -1      0 (correct exposure)                         
L   L     H     L    -2      -1 (1EV under)                               
L   L     L     H    -3      -2 (2EV under)                               
L   L     L     L    -4      -3 (3EV under)                               
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     The above-described operation is in the case where the relation (the output of the selection circuit 7)≧(the output of the selection circuit 6) is established. However, in the case where the relation (the output of the selection circuit 7)≦(the output of the selection circuit 6), the circuit shown in FIG. 6 can be modified in such a manner that the selection circuit 6 is connected to the inverted input terminal of the operational amplifier 82 and the output connection to the comparator 83 is correspondingly changed to perform the same A/D conversion. 
     FIG. 7 illustrates concrete examples of the logic circuit 65, the counter 66, the oscillator 67 and the latch circuit shown in FIG. 5. In FIG. 7, output pulses of the oscillator 67 are counted by flip-flop circuits 84, 85, 86 and 87. Connected to the outputs of these flip-flop circuits are the gates of field-effect transistors (FET) 88, 89, 90 and 91 for controlling the emitters of the transistors 73, 75, 77 and 79 in FIG. 6, the sources thereof being connected to the power supply 35, a NAND gate circuit 92, and D-type flip-flop circuits 94, 95, 96 ad 97. The output of the NAND gate circuit 92 is connected to one input of a NAND gate circuit 93 the other input of which is connected to the output terminal e of the comparator 83 described before. The output of the NAND gate circuit 93 is connected to the terminals CP of the D-type flip-flop circuits 94, 95, 96 and 97. In operation, the flip-flop circuits 84 through 87 which are triggered by the rising part of the pulse produced by the oscillator 67 operate to count the pulses, and the D/A converter shown in FIG. 6 changes its level as described with reference to FIG. 5 in response to the outputs a, b, c and d of the FET&#39;s 88 through 91. When this level reaches the level of the output A&#39; or B&#39; of the selection circuit 6, the level of the output terminal e of the comparator 83 is changed from the &#34;H&#34; level to the &#34;L&#34; level. Since the output of the NAND gate circuit 92 is at the &#34;H&#34; level at all times except the time when all of the inputs thereof are at the &#34;H&#34; level, the level change from the &#34;H&#34; to &#34;L&#34;, of the comparator 83 triggers the D-type flip-flops through the NAND gate circuit 93. As a result, the D-type flip-flops 94 through 97 operate to store the contents of the flip-flop circuits 84 through 87, respectively. When the common collector voltage V C  of the aforementioned transistors 73, 75, 77 and 79 is higher than the output of the selection circuit 6 even with the outputs a, b, c and d at the &#34;H&#34; level, the output e of the comparator 83 remains at the &#34;H&#34; level; however, because of the output level change, from the &#34;H&#34; level to the &#34;L&#34; level, of the NAND gate circuit 92 the contents of the flip-flop circuits 84 through 87 are stored in the D-type flip-flop circuits 94 through 97, respectively. In this connection, the logic levels (&#34;H&#34; or &#34;L&#34;) of the outputs a&#39;, b&#39;, c&#39; and d&#39; of the flip-flop circuits 84 through 87 are equal to those of the emitters of the transistors 73, 75, 77 and 79. 
     As was described before, the addresses A 0  and A 1  of the ROM 12 are determined, as in Table 1, by the switches 9 and 10 and the logic circuit 8 according to the selected photographing system. The outputs Q 94 , Q 95 , Q 96  and Q 97  of the A/D converter circuit described above are applied to the addresses A 2 , A 3 , A 4  and A 5  of the ROM 12. The addresses A 0 , A 1 , A 2 , A 3 , A 4  and A 5  specify the exposure information to be displayed. Therefore, the number display section in the display element 13, comprising for instance a 4-digit 7-segment LED (light emitting diode) display element and a decimal point displaying LED, is energized by the output of ROM 12 to display as indicated in Table 5 based on Tables 3 and 4. 
     
                       TABLE 5                                                     
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                            Mean- Dis-                                    
                            ing   play                                    
                            of ad-                                        
                                  exam- Meaning of                        
A.sub.5                                                                   
    A.sub.4                                                               
          A.sub.3                                                         
                A.sub.2                                                   
                    A.sub.1                                               
                        A.sub.0                                           
                            dress ple   display                           
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L   H     H     L   H   H   T.sub.V.sup.2                                 
                                        Shutter speed 1/4                 
L   H     L     H   H   H   T.sub.V.sup.1                                 
                                        Shutter speed 1/2                 
L   H     H     L   L   L   A.sub.V.sup.2                                 
                                        Lens stop value F2                
L   H     L     H   L   L   A.sub.V.sup.1                                 
                                        Lens stop value F1.4              
L   H     H     L   L   H   k.sub.4 = 3                                   
                                        3EV over                          
L   H     L     H   L   H   k.sub.4 = 2                                   
                                        2EV over                          
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     FIG. 8 illustrates one example of the character or symbol display section of the display element 13, in which the segments a and c are connected to an electrode f, the segment b to an electrode g, and the segment d to an electrode h. 
     FIG. 9 shows one example of a drive circuit for the display element 13 shown in FIG. 8. The segments a through d are light emitting diodes whose anodes are connected to the power supply 35. The electrode f is connected through a resistor 102 to the output of a NAND gate circuit 99, to which the display element input I 0  is directly applied and the display element input I 1  is applied through an inverter 98. The electrode g is connected through a resistor 103 to an AND gate circuit 100 to which the display element inputs I 0  and I 1  are applied. The electrode g is connected through a resistor 104 to an EXCLUSIVE OR gate circuit 101 to which the display element inputs I 0  and I 1  are applied. With the circuit thus organized, in the ES photographing system, I 0  =I 1  =H as indicated in Table 1. Therefore, the output of the EXCLUSIVE OR gate circuit 101 only is at the &#34;L&#34; level, and only the segment d is illuminated, so as to display the character &#34;T&#34;. In the EE photographing system, I 0  =I 1  =L. Therefore, the outputs of the AND gate 100 and the EXCLUSIVE OR gate circuit 101 are at the &#34;L&#34; level, and therefore the segments b and d are illuminated, so as to display the character &#34;f&#34;. In the manual photographing system, I 0  =H and I 1  =L. Therefore, the outputs of the NAND gate circuit 99 and the AND gate circuit 100 emit light, so as to display the character &#34;M&#34;. 
     This invention has been described with reference to a camera incorporating an exposure meter; however, it should be noted that the invention can be applied to a separate exposure meter. 
     As is apparent from the above description, according to the invention, in a variety of photographing systems, two out of the various analog voltages to be converted into digital data are selected, and the difference of the two voltages thus selected are subjected to analog-digital conversion by the A/D converter circuit. Therefore, the digital exposure display circuit according to the invention is simple in construction. Furthermore, not only the shutter speed automatically set, the lens stop value, the conditions indicating whether or not the exposure is correct, and the difference from the correct exposure can be displayed, but also the selected photographing system can be displayed by using the digital display element. Accordingly, the error that the user recognizes the displayed numerals for displays in other photographing systems that the actually selected photographing system can be positively eliminated. In addition, the circuit is free of excessively many pieces of information which are, in general, involved in the high-grade cameras, and the absolutely necessary information can be clearly displayed by the simple circuit according to the invention.