Electronic circuit having its impedance controlled by an external signal
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to electronic circuits having a controllable impedance, and more particularly, to an electronic circuit having a controllable impedance which can be used in noise suppression circuits or in signal compression/expansion circuits. 
     2. Description of the Prior Art 
     In the past, a number of circuits have been developed for compression and/or expansion of the magnitude or amplitude of electrical signals. However, a number of these prior art circuits required the use of capacitors, inductors or other bulky or relatively large components. As a consequence, these prior art circuits could not be readily fabricated in integrated circuit form, but were generally made using discrete components. Additionally, a number of these prior art circuits required the use of high supply voltages for circuit operation. Furthermore, many prior art circuits were basically Input/Output type circuits which were generally much more complex. A number of the prior art circuits also used log or square law type controls to vary the amplification or magnitude of the signal and these circuits therefor were generally complex. Another disadvantage associated with many of these prior art circuits was that they single-ended and therefor unbalanced thereby making these circuits susceptible to distortion and/or hum problems. 
     Accordingly, a need existed to provide an electronic circuit having its impedance controlled by an external signal which would eliminate the above identified problems associated with prior art circuits seeking to control the amplitude or magnitude of generated signals. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of this invention to provide an improved circuit having its impedance controlled by an external signal. 
     It is another object of this invention to provide a circuit whose impedance is controlled by an external signal which circuit can be implemented in a single integrated circuit structure. 
     It is a further object of this invention to provide an integrated circuit whose impedance can be controlled by an external signal where the circuit has an input impedance which is linearly related to the control current. 
     It is still another object of this invention to provide an improved circuit whose impedance can be readily varied over a wide range. 
     It is a still further object of this invention to provide a balanced, integrated differential amplifier circuit with a wide range of impedance control. 
     The foregoing, and other objects, features, and advantages of the invention will be apparent from the following, more particular description of the preferred embodiment of the invention, as illustrated in the accompanying drawing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block diagram of an electronic circuit whose impedance is controlled by an external signal in accordance with this invention; 
     FIG. 2 is a detailed circuit diagram of the block diagram shown in FIG. 1; and 
     FIG. 3 is a graph illustrating the impedance range which can be obtained with the circuit shown in FIG. 2. 
    
    
     THE SPECIFICATION 
     Referring to the block diagram of FIG. 1, a circuit having a variable electronic impedance is generally designated by reference number 1. This circuit 1 has an input terminal 2 connected to an input of a first stage 3 which is a high input impedance voltage-to-current converter circuit generally known as an operational amplifier. The first stage 3 has its output connected to a second stage 4 which is a variable gain current amplifier. The second stage 4 has its output connected via a feedback loop 5 to the terminal 2 and thus to the input of stage 3. A variable &#34;constant-current&#34; source 6 is included in the second stage, but is shown separately to illustrate that presetting or variable control of the second stage 4 can be achieved by means of a variable electrical signal (a current signal in the case of the source 6 although a voltage signal could be used). 
     A typical function of the circuit 1 is to attenuate a voltage signal (V in ) applied to the input between terminal 2 and ground. The first stage 3 detects the voltage signal and converts it into a current output signal (I 1 ) which is amplified by the second stage 4 to produce an output current I 2 . Since the first stage 3 has high input impedance, the current (I 3 ) applied to the first stage 3 can be made negligibly small in comparison with the current output I 2  by suitable presetting of the second stage 4 by means of the source 6. It can then be assumed that I 2  =I in  where I in  is the effective current from the terminal 2 through the circuit 1 due to V in . Thus the effective impedance Z in  of the circuit 1 is given by 
     
         Z.sub.in =(V.sub.in /I.sub.in)=(V.sub.in /I.sub.2) 
    
     Now the second stage 4 is configured so that I 2  /I 1  =±KI control   
     where K is a constant and I control  is the &#34;constant current&#34; obtained by means of source 6. 
     Also I 1  =±G m  V in  where G m  is a constant characteristic of the conversion operation of the first stage 3. 
     Thus ##EQU1## And so ##EQU2## 
     The circuit 1 can provide positive or negative impedance by suitable phasing of the stages 3 and 4, care being taken to achieve the desired input impedance. Hence, the circuit 1 can be used to attenuate (or amplify within limits of stability) a voltage appearing at V in . The important result is that it is possible to determine Z in circuit 1 solely by selection of I control  and the latter can be varied readily in a controlled manner to provide a circuit 1 having an impedance which is variable in a well defined manner. 
     It should be noted that as I control  approaches zero, I 2  also approaches zero and I 3  becomes important. When the value of I control  approaches zero, the maximum value of Z in  approaches V in  /I 3 . 
     Referring also to FIG. 2, one form of the variable electronic impedance circuit 1 of FIG. 1 is shown in schematic form. The stages 3 and 4 of FIG. 1 are shown within dashed boxes in FIG. 2. 
     The first stage 3 comprises a differential amplifier in the form of an emitter-coupled pair of PNP transistors T1, T2 whose emitters are connected via respective, identical resistors R1, R2 through a common connection to a constant bias-current source 10 connected to the supply and bias voltage V CC  at terminal 11. Each of the transistors T1, T2 has a Darlington-connected input PNP transistor T4, T3, respectively. Transistor T3 has its base connected to the circuit input terminal 12 and transistor T4 has its base connected to a reference voltage (V ref ) applied to terminal 13. In some applications, the transistors T3, T4 can be omitted, if desired, since they are provided to ensure that ##EQU3## where the prefix &#34;Δ&#34; indicates changes in the above parenthetical expression. 
     The collectors of the transistors T1, T2 provide the output of the first stage 3. The changes in current from the collectors of T1, T2 are detected by respective matched, forward-biased diodes D1, D2 operating over the exponential range of their current-voltage characteristics. Diodes D1, D2 are located in stage 4. The diodes D1, D2 have their cathodes connected to a common reference voltage (V bias ) at terminal 13&#39;. The anodes of the diodes D1, D2 are connected to respective bases of emitter-coupled, matched NPN transistors T5, T6. The common emitter connection of NPN transistors T5, T6 is connected to ground through a variable &#34;constant current&#34; source (not shown) such as I control  source 6 (see FIG. 1). The collectors of NPN transistors T5, T6 are connected to the supply voltage (V cc ) applied to terminal 11 via the respective PNP transistors, T7, T8 and identical resistors R3, R4. The transistors T7, T8 are matched and the bases of transistors T7 and T8 are electrically connected to the collector of transistor T8. Terminal 12 (terminal 12 is the same as terminal 2 of FIG. 1) is also connected to the collector of transistor T7. 
     OPERATION 
     In operation, I bias  source 10 is chosen so that the diodes D1, D2 operate in the exponential portion of their current-voltage characteristics. If I bias  (source 10) is chosen sufficiently precisely, the maximum permissible current change ΔI&#39; max  in the current I&#39; through each diode is given by 
     
         ΔI&#39;.sub.max ≈I.sub.bias /2 
    
     if the diodes D1, D2 are to operate exponentially as mentioned above. The signal handling capability of the first stage 3 is limited by the need to keep the diodes D1, D2 operating exponentially. Signal handling capability S is given by S=2(V ref  -V in ) max  and since 2ΔI&#39;Rα(V ref  -V in ) defines the voltage-to-current conversion operation of the first stage 3 (apart from a constant depending on the components used), then 
     
         S=2(V.sub.ref -V.sub.in).sub.max α2RΔI&#39;.sub.max =RI.sub.bias 
    
     &#34;R&#34; is the value of the fixed resistance (R1, R2). Thus we have that the signal handling capability of the first stage 3 is proportional to a fixed resistance (R1, R2) and a bias current (I bias ) which can be readily selected on the basis of the known characteristics of the diodes D1, D2. 
     NPN transistors T5, T6 are also arranged to operate in the exponential range of their collector current-base voltage characteristics. This is achieved by appropriate determination of the collector (or emitter) current of the transistors T5, T6. I control  must not be greater than the sum of the maximum permissible collector currents through the transistors T5, T6. 
     Thus, with matching of the operating voltage range of the diodes D1, D2 to the operating base voltage range of the transistors T5, T6, a linear response to changes ΔI&#39; can be obtained in terms of changes in the collector currents of transistors T5, T6. The PNP transistors T7, T8 are arranged to insure that when V in  =V ref  the emitter-collector current through the transistor T7 substantially equals the emitter-collector current through the transistor T5 (assuming that input current I 3  (see FIGS. 1 and 2) can be neglected as mentioned earlier). In other words, the PNP transistors T7, T8 are arranged to minimize the &#34;offset&#34; voltage (the extent by which the graph of Z in  versus I control  (see FIG. 3) fails to pass through the origin). 
     When a signal (V ref  -V in ) is received at the terminal 12, the first stage 3 provides two current signals +ΔI&#39; and -ΔI&#39; (shown by the reversed arrows) to diodes D1 and D2, the relative phases of the current signals depending on the phase or polarity of V in . The diodes D1, D2 supply the current signals +ΔI&#39;, -ΔI&#39; creating substantially equal and opposite voltages to the bases of transistors T5, T6 giving rise to substantially equal and opposite collector current changes through the transistors T5, T6. As mentioned above, these collector current changes are substantially linearly related to the current changes +1/3I&#39; and -αI&#39;. Since the current flowing through the bases of transistors T7,T8 is very small, the linear collector current change of the transistor T6 is equal to the collector current change of the transistor T8 which must therefore be linear. Due to the balanced arrangement, the collector current change of the transistor T7 must be the same as that of the transistor T8. Thus, at the terminal 12, a linear change in the collector current of the transistor T5 must be summed algebraically together with a linear change in the collector current of the transistor T7. the result of this is the current I 2  =I in  (assuming I 3  is sufficiently small enough to be neglected). Hence, variation in V in  gives rise to variation in I in  that is linearly related to V in . This linearity can be expressed in terms of the impedance Z in  of the circuit 1 (see FIG. 3). 
     When V in  =V ref  the differential current gain of the second stage 4 is given by:- 
     
         ΔI.sub.2 /2 ΔI&#39;=I.sub.control /I.sub.bias. 
    
     From the above, it can be seen that changes in I 2  are linearly related to changes in I&#39; so that the differential current gain of the second stage 4 is constant and equal to I control  /I bias . 
     As mentioned above the voltage-to-current conversion operation of the first stage 3 is given by 
     
         2ΔI&#39;Rα(V.sub.ref -V.sub.in). 
    
     Thus we have the impedance Z in  of the circuit 1 is given by:- ##EQU4## Hence Z in  α2ΔI&#39;R/2αI&#39;(I control  /I bias ), i.e., Z in α (RI bias  /I control ). 
     Hence, the impedance characteristic Z in  of this circuit 1 provides many advantages particularly over other electronic impedances which are intrinsically temperature dependent, e.g., intrinsically temperature dependent on kT/q where k is Boltzmann&#39;s constant, T is temperature and q is the electronic charge. 
     Also the impedance Z in  of this circuit can be readily varied (by varying I control ) over a wide range (see the graph of FIG. 3) and the signal handling capability is independent of I control . The signal handling capability S is determined solely by the first stage 3 in accordance with the relationship SαRI bias . 
     A particular advantage results from the balance of the circuit 1 since temperature and other disturbing effects tend to cancel out (i.e., inherently low offsets). Such balance can be optimized by using integrated circuit techniques to manufacture the circuit 1. Also the supply voltages required (such as V cc ) can be kept low (V cc  can be kept as low as 1.2 volts) in comparison with circuits employing a series of diode junctions. 
     The two terminal variable electronic impedance circuit described above has particular application in noise suppression and signal compression circuits (which may be integrated circuits including this variable impedance circuit) although there are many other applications for this variable impedance circuit. 
     The results derived above are dependent on I 3  and upon the base currents of the transistors T7 and T8 being sufficiently small in comparison with the gain of the stages 3 and 4. The circuit 1 shown in FIG. 2 can be improved further by supplying the base currents of transistors T7, T8 with a buffer amplifier (e.g., another single transistor stage) as has been done in the case of I 3  by providing transistors T3, T4. 
     The circuit 1 shown in FIG. 2 may have its linearity enhanced by arranging for &#34;bleeding&#34; of current from the anodes of diodes D1, D2 such that the operating range of the diodes D1, D2 is matched better with that of the transistors T5, T6. 
     However, the currents &#34;bled&#34; from each anode of the diodes D1, D2 must be identical since otherwise an offset will be introduced. 
     BRIEF SUMMARY OF THE SPECIFICATION 
     Thus, the circuit 1 provides a variable electronic impedance which includes a first stage connected to an input of the circuit and having a high input impedance and a second stage connected via a feedback loop to the circuit input. The first stage is arranged to control the second stage in dependence on a voltage signal received at the circuit input. The second stage providing a current in the feedback loop in accordance with the voltage signal received by the first stage so that the second stage presents a predetermined impedance to the circuit input via the feedback loop. The gain of the second stage can be varied by means of an applied electrical signal to enable variation of the predetermined impedance. 
     The first stage of the circuit employs a differential amplifier having one input connected to a reference voltage source and another input connected to the input of the circuit. The differential amplifier has an emitter coupled pair of identical transistors and resistors which are connected in series with the respective emitters of the transistor pair. The collectors of the transistor pair are connected to the second stage by connection through respective matched forward-biassed diodes to a first common bias voltage point. Anodes of the diodes are connected to respective base electrodes of two emitter-coupled matched transistors of the second stage whose combined emitter current is arranged to be variably controllable and one of whose collectors is connected to the device input. 
     Thus, this circuit can be used as a noise suppression circuit, a signal compression circuit and a signal expansion circuit which may each be formed as an integrated circuit. Each circuit displays a variable positive or negative impedance. 
     While the invention has been particularly shown and described in reference to the preferred embodiment thereof, it will be understood by those skilled in the art that changes in the form and details may be made therein without departing from the spirit and scope of the invention. For example, the circuit 1, shown in FIG. 2 is only one example of the general circuit shown in FIG. 1. Additionally, in a particular application, the constant current source 6 of FIGS. 1 and 2 may be fixed so that I control  is constant. In such a case the impedance of circuit 1 would have a fixed value.