Compander system having limiter in compressor and expander
This invention relates to a noise reduction system wherein the emphasis amount and the gain of the system are increased and decreased according to the amplitude of an analog audio signal, and particularly to a noise reduction system wherein a limiter is employed to limit the control voltage on a variable response amplifier for controlling the amplitude and spectrum of an analog audio signal. 
     In case a noise reduction system which has poor improvement of S/N ratio is used for a transmission system such as a recording system and reproduction system which handles sound of high quality, the noise level is not conspicously modulated by the audio signal level. However, if a noise reduction system having a much improvement of S/N ratio of transmission system is used, the noise level is modulated too much to be neglected. In particular, when such a noise reduction system is employed in a transmission system with a poor S/N ratio, the noise level is modulated so much that the noise reduction system becomes ineffective with respect to some specific sound sources. This would occur in such a noise reduction system with a highly improvement of S/N ratio as shown in FIG. 1, as will be explained with reference to FIG. 2. 
     The system shown in FIG. 1 comprises an encoder 2 connected to the input of a recording medium 1, e.g. tape recorder, thereby to compress the dynamic range of an analog audio signal during the recording operation and a decoder 3 connected to the output of the recording medium 1, thereby to expand the compressed analog audio signal and thus restore the dynamic range of the analog audio signal. 
     The encoder 2 is provided with a voltage-controlled amplifier 21, and the decoder 3 with a voltage-controlled amplifier 31. The amplifiers 21 and 31 act as multipliers. If they receive an input signal e 1  and a DC level E, they deliver an output signal e o  which is represented as follows: 
     
         e.sub.o =E.sup.±1 ×e.sub.i                        ( 1) 
    
     The exponent to DC level E is negative when the input signal e i  is to be encoded and is positive when the input signal e 1  is to be decoded. 
     The encoder 2 and decoder 3 are further provided with a level sensor 22 and a level sensor 32, respectively. The level sensors 22 and 32 are to detect the level of a signal and deliver DC level E which corresponds to the level of the input signal e. 
     Thus, when supplied with an input signal e i1 , the encoder 2 supplies to the recorder 1 an output signal e o1  which is represented as follows: 
     
         e.sub.o1 =E.sub.o1.sup.-1 ×e.sub.i1                  ( 2) 
    
     The level E o1  of the output signal e o1  of the encoder 2 is therefore expressed as follows: 
     
         E.sub.o1 =E.sub.o1.sup.-1 ×E.sub.i1 
    
     Hence, 
     
         E.sub.o1 =E.sub.i1.sup.1/2                                 ( 3) 
    
     An equation (3) shows, the level change of the input signal e i1  is compressed to 1/2 in logarithmic scale during the encoding operation. 
     When supplied with an output signal e i2  of the recorder 1, the decoder 3 delivers an output signal e o2  which is represented as follows: 
     
         e.sub.o2 =E.sub.i2 ×e.sub.i2                         ( 4) 
    
     The level E o2  of the output signal e o2  of the decoder 3 is therefore expressed as follows: 
     
         E.sub.o2 =E.sub.i2 ×E.sub.i2 =E.sub.i2.sup.2         ( 5) 
    
     As the equation (5) indicates, the level change of the input signal is expanded double in logarighmic scale. 
     The noise reduction system of FIG. 1 has such an operation characteristic as illustrated in FIG. 2. The encoder 2 compresses the dynamic range of an analog audio signal in such a manner as shown by a straight line A during the recording operation. The encoder converts an input signal of, for example, +20 dB into a signal of +10 dB, which is recorded on a recording medium 1 by the recorder, thereby increasing the peak margin of signal level. Similarly, it converts an input signal of, for example, -60 dB into a signal of -30 dB. As a result, any input signal has its dynamic range compressed to 50% and is then recorded by the recorder on a recording medium 1. 
     The decoder 3 expands the dynamic range of a signal recorded on the recording medium 1 in such a manner as shown by a straight line B during the reproduction operation. Namely the decoder 3 converts the signal of +10 dB recorded on the recording medium 1 into a signal of +20 dB. Similarly, it converts the signal of -30 dB recorded on the recording medium into a signal of -60 dB, thus reducing the noise by 30 dB. Thus, with respect to the input signal of -60 dB applied to the encoder 2, the S/N ratio of the recording medium 1 is improved by 30 dB when the decoder 3 delivers an output signal of -60 dB. Accordingly, the S/N ratio of the recording medium is improved to a degree which is usually expressed as: -1/2×level (dB) of input signal. 
     In the system shown in FIG. 1, however, the noise behind the output signal of the system is modulated according to a change in amplitude of audio signal. For instance, the S/N ratio of the system is improved by as much as 50 dB when an input signal of -100 dB is applied, and the noise in the output signal can be scarecely audible. In contrast, the S/N ratio is not improved at all when an input of 0 dB is applied. 
     Noise behind a sound of a large amplitude is nearly inaudible owing to masking effect. In this case the above-mentioned noise modulation does not make a problem practically. But noise behind sound of simple harmonic structure such as a piano solo cannot be masked and inevitably remains audible. If this is the case, the noise is heard as if changing in accordance with the rhythm of the music played. Such a change of noise level, if considerably intense, would more stimulate the listener&#39;s auditory sensation level than in case the noise has a constant level. 
     To lessen such stimulation to the listener&#39;s auditory sensation level, such a system as shown in FIG. 3 has been invented. This noise reduction system differs from the system shown in FIG. 2 in that there are provided a pre-emphasis circuit 23, a de-emphasis circuit 33 and two weighting circuits 24 and 34. The de-emphasis circuit 33 has such an operation characteristic as the curve B shown in FIG. 4 and serves to lower the gain of high frequency range to reduce much noise of recording medium, thereby to make the noise hard to hear. The de-emphasis circuit 33 inevitably attenuates musical sound of high frequency range, too. The pre-emphasis circuit 23 should therefore be used, which has such an operation characteristic the curve A as is shown in FIG. 4 and inverse to that of the de-emphasis circuit 33. If the gain for a signal of high frequency range is elevated during the recording operation, the peak margin is reduced with respect to the saturation signal level in the recording medium 1, and the waveform of the signal will be distorted. To avoid this distortion of waveform, the weighting circuits 24 and 34 having such an operation characteristic as the curve C shown in FIG. 4 are employed to elevate the sensitivity of level sensors 22 and 32 to the signals of high frequency range, whereby the input signals are compressed to a higher degree. 
     However, if the system of FIG. 3 is used in combination with a compact cassette tape recorder, it fails to reduce effectively the noise behind a signal for the following reason. A cassette tape can record but signals of a narrow frequency range and have a high noise level and a low saturation level. In case the signals represent sounds of a simple spectrum, the audible noise behind them will be modulated conspicuously. Further, if a signal has a spectrum extending all over the audible frequency range and has a high level, its high frequency component will be saturated. As a result, the sound reproduced from the cassette tape would become dull. 
     An ordinary cassette tape recorder has such a frequency characteristic as shown in FIG. 5. Apparently, the higher level a recorded signal has, the more deteriorated is the spectrum of the reproduced sound of high frequency range. That is, the quality of the reproduced sound is poor since the high frequency components of a musical sound cannot be reproduced in case the recorded musical sound has a high level even if it has not been encoded. In case an encoded signal whose high frequency component has been emphasized is recorded, the quality of the sound reproduced from the encoded signal will be deteriorated much more. 
     The object of this invention is to provide a noise reduction system which, when used in combination with a compact cassette tape recorder, can operate stably and minimize the quality deterioration of the sound reproduced by the cassette tape recorder. 
     According to one aspect of this invention there is provided a noise reduction system having an encoder which compresses the dynamic range of an analog audio signal to produce a compressed analog audio signal to be transferred and a decoder which expands the compressed analog audio signal obtained from a recording or transmission medium thereby to restore the dynamic range of the analog audio signal, whereby the noise behind the analog audio signal is reduced, the encoder including a first controlled amplifier by which the gain and the degree of the emphasis of high frequency range of the analog audio signal are controlled in accordance with the amplitude of the analog signal, the decoder having a second controlled amplifier having a transfer function which is substantially inverse to that of the first controlled amplifier of the encoder, the first controlled amplifier comprising a first voltage controlled amplifier (VCA) receiving the analog audio signal and in which the amplification factor thereof is varied by a first controlling voltage, a first high-pass filter receiving the analog audio signal, and means for obtaining a difference between the outputs of the first VCA and the first high-pass filter, the encoder further including a first level sensor for detecting the level of the compressed analog audio signal and a first limiter for limiting the output of the first level sensor to obtain said first controlling voltage in such a manner that the ratio between the gain of the first VCA and the gain of the first high-pass filter at the pass band thereof does not become less than one, and the second controlled amplifier comprises a second voltage controlled amplifier (VCA) rendered to vary the amplification factor in accordance with a second controlling voltage, a second high-pass filter having an input coupled to an output of the second VCA, means for adding the output of the second high-pass filter to the compressed analog audio signal to send forth the added signal to the second VCA to constitute a positive feedback loop, the decoder further including a second level sensor for detecting the level of compressed analog audio signal and a second limiter for limiting the output of the second level sensor to obtain said second controlling voltage in such a manner that the loop gain of the positive feedback loop at the second high-pass filter does not become more than one. 
    
    
     This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a conventional noise reduction system; 
     FIG. 2 shows the operation characteristics of the system shown in FIG. 1; 
     FIG. 3 is a block diagram of another conventional noise reduction system; 
     FIG. 4 shows the operation characteristics of the constituent devices of the system shown in FIG. 3; 
     FIG. 5 shows the frequency characteristics of a cassette tape recorder in ordinary use; 
     FIG. 6 is a block diagram of a noise reduction system according to this invention; 
     FIG. 7 shows the operation characteristics of the constituent devices of the system shown in FIG. 6; 
     FIG. 8 shows the frequency response characteristics of the controlled amplifier used in the encoder of the system shown in FIG. 6; 
     FIG. 9 is a block diagram of the variable response amplifier used in the encoder of the system shown in FIG. 6; 
     FIG. 10 shows the frequency response characteristics of the variable response amplifier shown in FIG. 9; 
     FIG. 11 shows the frequency response characteristics of the controlled amplifier used in the decoder of the system shown in FIG. 6; 
     FIG. 12 shows the frequency response characteristics of the variable response amplifier used in the decoder of the system shown in FIG. 6; 
     FIG. 13 is a block diagram of the controlled amplifier used in the decoder of the system shown in FIG. 6; 
     FIG. 14A is a circuit diagram of a current mode voltage-controlled amplifier; 
     FIG. 14B is a symbol for the current mode voltage-controlled amplifier shown in FIG. 14A; 
     FIG. 15 is a circuit diagram of the variable response amplifier used in the encoder, using the current mode voltage-controlled amplifier shown in FIG. 14A; 
     FIG. 16 is a circuit diagram of the variable response amplifier used in the decoder, using the current mode voltage-controlled amplifier shown in FIG. 14A; 
     FIG. 17 shows the frequency response characteristics of the variable response amplifier shown in FIG. 9 while the gain G remains smaller than 0 dB; 
     FIG. 18 is a block diagram of a noise reduction system according to this invention; 
     FIG. 19 is a circuit diagram of a unilateral limiter of fundamental type; 
     FIG. 20 is a circuit diagram of a sophisticated unilateral limiter; 
     FIGS. 21A and 21B show an input waveform and an output waveform of the limiter shown in FIG. 20, respectively; 
     FIG. 22 shows a variable response amplifier which can operate alternatively for the variable response amplifiers shown in FIGS. 15 and 16; 
     FIG. 23 is a circuit diagram of a controlled amplifier for the encoder, provided with a current-voltage converting circuit having a specific frequency characteristic; 
     FIG. 24 is a circuit diagram of a controlled amplifier for the decoder, provided with a voltage-current converting circuit having a specific frequency characteristic; 
     FIG. 25 shows a controlled amplifier which can act alternatively as such controlled amplifiers as shown in FIGS. 23 and 24; 
     FIG. 26 shows a modification of the controlled amplifier shown in FIG. 25; 
     FIG. 27 shows a modified system with a modification of the controlled amplifier of FIG. 26; 
     FIG. 28 shows one example of the polarity circuit shown in FIG. 27; 
     FIG. 29 shows a modification of the controlled amplifiers shown in FIGS. 25 and 26; 
     FIGS. 30A and 30B show two weighting functions obtained from the front end circuit and the tail end circuit of the variable response amplifier shown in FIG. 29, respectively; 
     FIG. 31 shows a modification of the controlled amplifier shown in FIG. 29; 
     FIG. 32 shows the attenuation characteristics of the front end circuit and the tail end circuit of the variable response amplifier shown in FIG. 31; and 
     FIG. 33 shows a further modification of the controlled amplifier shown in FIG. 31. 
    
    
     Like the conventional noise reduction system shown in FIG. 3, the system according to this invention as shown in FIG. 6 comprises level sensors 22, 32, a pre-emphasis circuit 23, a de-emphasis circuit 33 and weighting circuits 24 and 34. The system is further provided with variable response amplifiers 21 and 31. The variable response amplifier 21, level sensor 22, pre-emphasis circuit 23 and weighting circuit 24 constitute an encoder 2, while the variable response amplifier 31, level sensor 32, de-emphasis circuit 33 and weighting circuit 34 constitute a decoder 3. 
     The output signals of the level sensors 22 and 32 are supplied to the variable response amplifiers 21 and 31, respectively, thereby to control the gains and frequency characteristics of the varaiable response amplifiers 21 and 31 at the same time. In this case the pre-emphasis circuit 23, the de-emphasis circuit 33, and either of the weighting circuits 24 and 34 have such frequency characteristics as shown by curves A, B and C in FIG. 7 respectively. 
     In the encoder 2, the variable response amplifier 21 and the pre-emphasis circuit 23 constitute a controlled amplifier 41. Similarly, in the decoder 3, the variable response amplifier 31 and the de-emphasis circuit 33 constitute a controlled amplifier 42. 
     The controlled amplifier 41 has such a frequency response characteristic as shown in FIG. 8. Namely, when a low control voltage V c  is applied on the variable response amplifier 21 and thus the variable response amplifier 21 has a small gain G, the encoder 2 has a small gain over the entire audible frequency range and the amount of emphasis is not so large as in the following case. In case a high control voltage V c  is applied on the variable response amplifier 21 and thus the variable response amplifier 21 has a high gain G, the gain of the encoder 2 is increased over the entire audible frequency range, and more increased at higher frequencies than at lower frequencies. In the former case the emphasis of high frequency band therefore becomes smaller than that in the latter case. 
     The variable response amplifier 31 of the decoder 3 has a transfer function which is substantially inverse to that of the variable response amplifier 21 used in the encoder 2. 
     The level sensors 22 and 32 are so designed as to produce an output signal of a low potential in response to an input signal of a high level and an output signal of a high potential in response to an input of a low level. Thus, when an input signal V i  of a low level is supplied to the encoder 2, the variable response amplifier 21 amplifies the level of the input signal V i , particularly the high frequency component of the input signal V i . The output of the encoder 2 is then recorded by the recording medium 1 and thus added with noise. The signal obtained from the recording medium 1 is supplied to the decoder 3 and has its level lowered by the variable response amplifier 31 which has a transfer function substantially inverse to that of the variable response amplifier 21 of the encoder 2. Particularly, the high frequency component of the signal has its level lowered more than the low frequency component. As a result, the noise level of the signal is lowered as in the conventional noise reduction system shown in FIG. 3. If the emphasis of high frequency range can be made sufficiently large, the noise is compressed more than otherwise, and the modulation of noise can be made less audible. 
     When an input signal V i  of a high level is applied to the encoder 2, the variable response amplifier 21 lowers the level of the signal V i  relative to the former case thereby to increase the peak margin of signal level, just as in the conventional noise reduction system. Since the high frequency component of the input signal V i  has its level lowered more than the low frequency component, its peak margin becomes larger than that of the low frequency component. Further, the modulation noise generated, for example, by the vibration of the magnetic tape on the recording medium 1 can be reduced. In the decoder 3 the lowered level of the input signal V i  will be elevated to the original level. 
     The variable response amplifier 21 of the encoder 2 may comprise a voltage-controlled amplifier 81 (hereinafter called &#34;VCA 81&#34;), an inversion amplifier 82, a high-pass filter 83 and an adder 84 as shown in FIG. 9. The variable response amplifier 21 has such a frequency-gain characteristic as shown in FIG. 10. The VCA 81 is of such a type wherein the gain G increases and decreases according to the control voltage V c . The adder circuit 84, adds the output of the VCA 81 and the output of the inversion amplifier 82 coming through the high-pass filter 83. Let the gain of the VCA 81 be denoted by &#34;G&#34;, and the transfer function between an input signal V i1  and the output signal V o1  of the adder circuit 84 be denoted by &#34;H e  (ω)&#34;. Then, the following equation will be established: ##EQU1## 
     In equation (6), S=jω, and &#34;ω&#34;, &#34;c&#34; and &#34;r&#34; denote an angular frequency, the capacitance of the capacitor C in the high-pass filter 83 and the resistance of the resistor r in the high-pass filter 83, respectively. 
     If the output of the VCA 81 is applied to the pre-emphasis circuit 23 when the gain G of the VCA 81 is 1 or more, the emphasis of high frequency range becomes smaller in case the gain G of VCA becomes lower with lower control voltage V c . This is well understood from the frequency-gain characteristic of the variable response amplifier 21, which is shown in FIG. 10. When the gain G of the VCA 81 is less than 1, the emphasis of high frequency range becomes larger in case the gain G of VCA is low than in case gain G of VCA is high. This is an undesirable consequence and thus should be prevented. Thus, the VCA 81 should be used in such condition that the gain G of the VCA 81 be never less than 1, whereby the emphasis of high frequency range can be made smaller in case the amplification degree G is low than in case the amplification degree G is high. This is explained precisely afterwards. 
     The controlled amplifier 42 of the decoder 3 is constructed as illustrated in FIG. 13. It comprises a de-emphasis circuit 132 and a VRA 31 for the decoder. The transfer function H d  (ω) between an input signal V i2  and an output signal V o2  of the VRA 31 is represented as follows: ##EQU2## The controlled amplifier 42 has such a frequency-response characteristic as is shown in FIG. 11 and substantially inverse to that of the encoder 2 shown in FIG. 8. To achieve this, the variable response amplifier 31 has transfer function H d  (ω) which is inverse to the transfer function H e  (ω) defined by equation (6). The variable response amplifier 31 with such transfer function H d  (ω) exhibits such a frequency-gain characteristic as shown in FIG. 12, so long as its gain G i  (=1/G) remains less than 1. 
     In FIGS. 9 and 13, the values of the input and output signals of VRAs 21 and 31 are represented in voltage. Thus, the input impedance and output impedance of each block shown are regarded as being infinite and zero, respectively. If the VCA of the controlled amplifier 41 or 42 is to control the current of an input signal according to the control voltage, it requires no adder. It is therefore desired that the VCA be of such a type as could control the current of an input signal without any device for converting current into voltage so that the variable response amplifier 21 or 31 is made simple and can yet have such a frequency gain characteristic as shown in FIG. 10 or 12. 
     FIG. 14A shows a VCA which can control the current of an input signal without any device for converting current into voltage. This VCA comprises transistors Q 1  to Q 4 , a differential amplifier 141 and a constant voltage source 142. The transistors Q 1  and Q 2  serve to control the current of an input signal of the VCA and have their emitters connected mutually. Similarly the transistors Q 3  and Q 4  have their emitters connected mutually. The bases of the transistors Q 2  and Q 3  receive control voltage V c  &#39; while the bases of the transistors Q 1  and Q 4  are grounded. The constant voltage source 142 is connected between the emitters of the transistors Q 1  and Q 3 . The differential amplifier 141 has its input terminal connected to the collectors of the transistors Q 1  and Q 3  and its output terminal connected to the emitters of the transistors Q 1  and Q 2 . 
     Suppose four transistors Q 1  to Q 4  of the VCA have one and same operation characteristic. Then, the following equation is established: 
     
         I.sub.o =-I.sub.i ×ε.sup.(Vc+Vbe)/V.sbsp.T   (8) 
    
     In equation (8), V T  =kT/q and Vbe denotes a bias voltage where k is the Boltzmann constant, T is absolute temperature, and q is the numerical value of the electronic charge. The VCA wherein the relationship between the input and output signals is represented by equation (8) will be identified hereinafter with such a symbol as shown in FIG. 14B. 
     A variable response amplifier which includes such a VCA as shown in FIG. 14A and which exhibits such a frequency gain characteristic as shown in FIG. 10 will be described with reference to FIG. 15, and a variable response amplifier which includes such a VCA as shown in FIG. 14A and which exhibits such a frequency-gain characteristic as shown in FIG. 12 will be described with reference to FIG. 16. 
     The variable response amplifier of FIG. 15 comprises a resistor 151, a VCA 152, a series circuit 153, an operational amplifier 154 and a resistor 155. The resistor 151 is connected between the input terminal n1 of the variable response amplifier and the input terminal n2 of the VCA 152. The series circuit 153 is constituted by a resistor R and a capacitor C connected in series to each other and is connected between the input terminal n1 and the output terminal n3 of the VCA 152. The output terminal n3 of the VCA 152 is connected to the input terminal of the operational amplifier 154 and to the output terminal n4 thereof through the resistor 155. 
     The variable response amplifier of FIG. 16 is complementary to the variable response amplifier shown in FIG. 15. It comprises a resistor 161, a VCA 162, a series circuit 163, an operational amplifier 164 and a resistor 165. The input terminal n1 of this variable response amplifier is connected to the input terminal n2 of the VCA 162 through the resistor 161 and to the output terminal n3 of the operational amplifier 164 through the series circuit 163 which is constituted by a resistor R and a capacitor C connected in series to each other. The output terminal n4 of the VCA 162 is connected to the operational amplifier 164 and to the output terminal n3, i.e. the output terminal of this variable response amplifier, through the resistor 165. 
     It will be described how the variable response amplifier shown in FIG. 15 operates. The voltage V ie  of an input signal is converted by the resistor 151 into current I 1  which is represented as follows: 
     
         I.sub.1 =V.sub.ie /R.sub.11 
    
     where R 11  represents the resistance value of the resistor 151. 
     Current I 1  is then applied to the VCA 152 and multiplied by an amplification degree G which is determined by the control voltage V cl  applied to the VCA 152 and which is expressed as follows: 
     
         G=-EXP[(V.sub.cl +V.sub.be)/V.sub.T ] 
    
     And the output terminal n3 of the VCA 152 is supplied with current G·I 1 . 
     In the meantime, the input voltage V ie  has been converted by the series circuit 153 into current I 2  which is represented as follows: 
     
         I.sub.2 =jωcV.sub.ie /(1+jωcR) 
    
     Thus, current G·I 1  and current I 2  flow together to the output terminal n3 of the VCA 152. In other words, the output terminal n3 is supplied with the following current: ##EQU3## 
     Since both currents G·I 1  and I 2  are made to flow through the resistor 155, the following relationship is established between the input voltage V ie  and the output voltage V oe  : ##EQU4## where R 12  represents the value of the resistor 155. 
     Here, let -(R 12  /R 11  G be denoted as &#34;G&#34;, and R 12  (=R) be denoted as &#34;r&#34;. Then, equation (9) becomes identical with equation (6). To denote -(R 12  /R 11  G as &#34;G&#34; is generally accepted, and to denote R 12  as &#34;r&#34; means that V oe  /V ie  is multiplied by a constant. For this reason equation (9) can be considered equivalent to equation (6), and the variable response amplifier of FIG. 15 is provided to exhibit such a frequency-gain characteristic as shown in FIG. 10. 
     Now it will be described how the variable response amplifier shown in FIG. 16 operates. Let Gi be the gain of VCA 162. The voltage V id  of an input signal is converted by the resistor 161 into current V id  /R 22 , and an output voltage is converted by the series circuit 163 into current jωcV od  /1+jωcR. Thus, the input terminal n2 of the VCA 162 is supplied with current I 1d  which is expressed as follows: 
     
         I.sub.1d =(V.sub.id /R.sub.22)+(jωcV.sub.od /1+jωcR) 
    
     where R 22  denotes the value of the resistor 161. 
     Current I 2d  is amplified by the VCA 162, and the output terminal n4 is supplied with current I 2d  which is expressed as follows: ##EQU5## 
     Current I 2d  is converted by the operational amplifier 164 and the resistor 165 into voltage V od  which is represented as follows: ##EQU6## where R 21  denotes a resistance value of the resistor 165. 
     Equation (10) is transformed into the following equation: ##EQU7## 
     Here, let R 21  and R 22  be changed to R 11  and R 12 , respectively and let G i  be 1/G. Then, the transfer function H dl  (ω) of the variable response amplifier for the decoder is as follows: ##EQU8## Consequently, the variable response amplifier of FIG. 16 is proved to exhibit such a frequency-gain characteristic as shown in FIG. 12. 
     If the variable response amplifiers shown in FIGS. 15 and 16 are used in the noise reduction system shown in FIG. 6, the system becomes simple in construction and yet can improve the S/N ratio, thereby making the modulated noise scarcely audible. In other words, if the variable response amplifiers of FIGS. 15 and 16 which are operated in current mode are used, the noise reduction system can be constituted by less elements in less steps of manufacture. It is therefore possible to provide at a low cost a noise reduction system which operates with a high efficiency. 
     In the variable response amplifier shown in FIG. 9, a characteristic curve of (V o1  -V i1 ), if plotted in a range of -G&lt;R 11  /R, is as shown in FIG. 17 setting R as R 11 . That is, a gain -G is excessively decreased when an input signal of high level is applied, and if the gain -G becomes smaller than R 11  /R, a response of a high frequency range is raised more than that of a middle or low frequency range. As a result, a signal distortion occurs at a high frequency range and there also occurs modulation noise. Since -G is an inverse number to -G 1 , -G 1  is larger than R/R 11  so long as -G remains less than R 11  /R in the VCA of the decoder 3. The operation of the VCA therefore becomes unstable because the imaginary part of the denominator of a transfer function shown in equation (11) of the VCA is made negative. In order to avoid such a state it is desired that voltages V c1 , V c2  for controlling the VCA be restricted to a proper value. 
     FIG. 18 is a block diagram of a noise reduction system according to one embodiment of this invention, which is provided with two limiters 25 and 35 adapted to control voltages V c1  and V c2 , respectively. The limiter 25 is connected between a variable response amplifier 21 and a level sensor 22, and the limiter 35 between a variable response amplifier 31 and a level sensor 32. Each limiter is a unilateral one with such a basic construction as illustrated in FIG. 19. Its concrete construction is shown in FIG. 20. 
     Fundamentally, each limiter is constituted by an input terminal 191, a resistor 192, a diode 193, a power source 194 and an output terminal 195, as shown in FIG. 19. When an input voltage V i  applied to the input terminal 191 is lower than the voltage of the power source 194, it is applied to the output terminal 195 through the resistor 192 and then acts as a control voltage V c . When the input voltage V i  is higher than the power source voltage, the output voltage is clamped by the diode 193 and the source 194. Thus the difference between the input voltage V i  and the power source voltage is by-passed to the power source 194 through the diode 193. In this case, a limited control voltage V c  appears at the output terminal 195. 
     Practically, as shown in FIG. 20, each limiter comprises an input terminal 201, a resistor 202, a diode 203, a transistor 204, a resistor 205, a resistor 206 and an output terminal 207. Here, let the forward voltage drop of the diode 203, the base-emitter voltage and the base voltage of the transistor 204 be denoted by V D , V BE  and V I , respectively. Then the limiter produces the limited control voltage V C  which is expressed as follows: 
     
         V.sub.C =V.sub.I +V.sub.BE +V.sub.D 
    
     If such an input voltage V i  as shown in FIG. 21A is applied to the input terminal 201, the limiter delivers such an output voltage V c  as shown in FIG. 21B. 
     The limiters 25 and 35 need not be limited to such a unilateral one as illustrated in FIG. 20. Any limiter may be used to the noise reduction system of FIG. 18. if it can limit the control voltage on a VCA so as to increase or decrease the emphasis within an optimum range. 
     Instead of two variable response amplifiers, one for the encoder and the other for the decoder, a single variable response amplifier may be so designed as to act alternatively for the encoder or the decoder, thereby further reducing the number of elements constituting a noise reduction system. FIG. 22 shows such a variable response amplifier. As illustrated in FIG. 22, the variable response amplifier is constituted by an input terminal IN, a two-port circuit 220F, serially connected resistors 221 and 222, a capacitor 223, a VCA 224, a capacitor 225, resistors 226 and 227, an operational amplifier 228, a switch 229, another two-port circuit 220G and an output terminal OUT. 
     In the variable response amplifier shown in FIG. 22, the input terminal IN is connected to the two-port circuit 220F and one electrode of the capacitor 223 via the resistors 221 and 222. The other electrode of the capacitor 223 is connected to the output terminal of the VCA 224. The output terminal of the two-port circuit 220F is connected to the input terminal of the VCA 224 and further to one terminal of the resistor 226 through the capacitor 225. The other terminal of the resistor 226 is connected to the output terminal of the operational amplifier 228 through the resistor 227. The resistors 226 and 227 are connected in series to each other. The switch 229 has one movable contact and two stationary contacts e and d. The movable contact is grounded, while the stationary contacts e and d are connected to the junction between the resistors 226 and 227 and the junction between the resistors 221 and 222, respectively. The output terminal of the VCA 224 is connected to the input terminal of the operational amplifier 228 and also to the output terminal of the two-port circuit 220G. The input terminal of the two-port circuit 220G is connected to the output terminal of the operational amplifier 228. 
     When the movable contact of the switch 229 is put into contact with the stationary contact e, the variable response amplifier of FIG. 22 starts working in the same manner as the variable response amplifier shown in FIG. 15 if the two-port circuits 220F and 220G are equivalent to the resistors 151 and 155 of the variable response amplifier of FIG. 15, respectively. Namely, if hot terminal of each part of the two-port circuit 220F and 220G is each connected with the resistors 151 and 155 of the variable response amplifier of FIG. 15, respectively, and the cold terminals thereof are free, the variable response amplifier shown in FIG. 22 is equivalent to that in FIG. 15. Further, the sum of resistivity of the resistors 221 and 222 equals that of the resistor R of the circuit 153 shown in FIG. 15, and the capacitor 223 corresponds to the capacitor C of the circuit 153 shown in FIG. 15. While the movable contact remains in contact with the stationary contact e, the series circuit constituted by the capacitor 225 and the resistor 226 is grounded at one end and coupled to the VCA 224 at the other end. This means that the VCA 224 is applied with ground potential from the capacitor 225. Thus, no current flows through both the capacitor 225 and the resistor 226 and these elements 225, 226 may be regarded as not being provided. Further, the resistor 227, which provides load to the output of the operational amplifier 228, can be regared as not being provided if its resistivity is 100 ohms or more. Consequently, the variable response amplifier becomes equivalent to the amplifier illustrated in FIG. 15. 
     When the movable contact of the switch 229 is put into contact with the stationary contact d, the variable response amplifier of FIG. 22 starts working in the same manner as the amplifier shown in FIG. 16. Under this condition, the resistors 221 and 222 and the capacitor 223 are regarded as not being provided. Thus, if the two-port circuits 220F and 220G are equivalent to the resistors 161 and 165, respectively as in the variable response amplifier of FIG. 16, the variable response amplifier shown in FIG. 22 becomes equivalent to the variable response amplifier of FIG. 16. 
     That is, the two-port circuit 220F corresponds to the resistor 151 of the amplifier of FIG. 15 and the resistor 161 of the amplifier of FIG. 16, and thus resistance R 11  of the resistor 151 is equal to resistance R 22  of the resistor 161. Similarly, since the two-port circuit 220G corresponds to the resistors 155 and 165, resistance R 12  is equal to resistance R 21 . 
     The two-port circuits 220F, 220G may be of circuits represented by the same functions with each other when switched as the encoder or decoder, respectively. When the two-port circuits 220F, 220G are resistors, it is only required the following relations. 
     
         F(S)=R.sub.151 =R.sub.161 
    
     
         G(S)=R.sub.155 =R.sub.165 
    
     When the circuits 220F, 220G are not pure resistors, it is also necessary to switch the F(S) and G(S). Thus, when denoting the F(S) and G(S) in the encode mode as Fe(S), Ge(S), and as Fd(S), Gd(S) in the decode mode, the relations 
     
         Fe(S)=Gd(S) 
    
     
         Ge(S)=Fd(S) 
    
     should be satisfied. 
     As aforementioned, the modulation of noise level becomes problematical when an input signal has a low level, and the saturation of high frequency component of an input signal becomes problematical when the input signal has a high level. Thus it is desired that the emphasis be increased when the input signal has a low level and decreased when the input signal has a high level. In short, the emphasis should be changed according to the level of the input signal. To achieve this, the controlled amplifier which comprises the variable response amplifier and the pre-emphasis circuit for the encoder and the controlled amplifier which comprises the variable response amplifier and de-emphasis circuit for the decoder constructed as shown in FIGS. 23 and 24, respectively may be useful. 
     As shown in FIG. 23, the controlled amplifier for the encoder is provided with an operational amplifier 231 and an VCA 232 using a two part circuit. The VCA 232 is controlled by a control voltage Vc and provides a current G e  times as much as the current flowing to it through the resistor R i . It is constructed as illustrated in FIG. 14A. 
     The transfer function of the controlled amplifier shown in FIG. 23 can be expressed as follows, using the symbols in FIG. 23: ##EQU9## 
     If (R/R i )G e  =G in equation (12), the frequency-gain characteristic indicated by the value in the first factor will be expressed with G as parameter as illustrated in FIG. 10. The right factor of equation (12) shows the static pre-emphasis of high frequency range. The controlled amplifier of FIG. 23 will obtain a desired frequency-gain characteristic if the amplification factor G e  of the VCA 232 is so controlled as to become high when the level of an input signal is low and low when the level of the input signal is high. 
     As shown in FIG. 24, the controlled amplifier for the decoder includes a VCA 241, an operational amplifier 242 and the same two part circuit as one shown in FIG. 23. The VCA 241 is controlled by a control voltage Vc and provides a current G d  times as much as the input current. The inverse transfer function of this controlled amplifier can be represented as follows, using the symbols in FIG. 24: ##EQU10## 
     If G e  /R i  =1/(R f  ·A d ) in equation (13), the V i  /V o  is proved to be exactly inverse to the transfer function of the controlled amplifier for the encoder, shown in FIG. 23. 
     Further, if R/(R f  ·A d )=G in equation (13), the frequency-gain characteristic indicated by the value in the first parentheses in equation (13) will be expressed with G as parameter as shown in FIG. 12. 
     Instead of such two controlled amplifiers as shown in FIGS. 23 and 24, a single controlled amplifier may be used to operate alternatively for the encoder or the decoder. Such a single controlled amplifier may be constructed as shown in FIG. 25. 
     As shown in FIG. 25, the controlled amplifier comprises a first resistor R 1  connected between a first node n1 and a second node n2, a second resistor R 2  connected between the second node n2 and a third node n3, a VCA 250 the same as shown in FIG. 14A and an operational amplifier 251 having its inversion input and its output connected to the fourth node n4 and a fifth node n5, respectively. The controlled amplifier is further provided with a third resistor R 3  connected between the fifth node n5 and a sixth node n6 and a fourth resistor R 4  connected between the sixth node n6 and the fourth node n4. There is further provided a first switch 252, a second switch 253 and a third switch 254. A fifth resistor R 5  and a first capacitor C 1  constitute a serial circuit, which is connected between the first switch 252 and the second switch 253. Similarly, a sixth resistor R 6  and a second capacitor C 2  constitute a series circuit, which is connected between the sixth node n6 and the third switch 254, and a seventh resistor R 7  and a third capacitor C 3  constitute another series circuit, which is connected between the second node n2 and the third switch 254. 
     In the controlled amplifier of FIG. 25, the VCA 250 amplifies an input current by a current amplification factor determined by a control voltage V c . The amplified current flows to the node n4. The switches 252, 253 and 254 have each a movable contact, a stationary contact e for the encoder and a stationary contact d for the decoder. The movable contact, stationary contact e and stationary contact d of the first switch 252 are connected to the fifth resistor R 5 , the first node n1 and the third node n3, respectively. The movable contact, stationary contact e and stationary contact d of the second switch 253 are connected to the first capacitor C 1 , the fourth node n4 and the fifth node n5, respectively. The movable contact, stationary contact e and stationary contact d of the third switch 254 are connected to the ground, the sixth node n6 through sixth resistor R 6  and the second capacitor C 2 , and the second node n2 through the seventh resistor R 7  and the third capacitor C 3 , respectively. 
     The first node n1 and the fifth node n5 act as the input and output terminals of the controlled amplifier of FIG. 25, respectively. The control voltage V c  serves to control the gain and frequency characteristic of the controlled amplifier at the same time. The movable contact of each switch is moved to contact either stational contact e or d. Further, the polarity and bias value of the control voltage V c  are changed over simultaneously. In this way, the variable response amplifier shown in FIG. 25 can obtain two transfer functions which are inverse to each other. 
     More precisely, when the movable contacts of the switches 252, 253 and 254 are put into contact with the respective stationary contact e, the controlled amplifier starts functioning for the encoder. If R 1  +R 2  =R i , R 5  =R r , C 1  =C r , C 2  =C e , R 6  =R e  and R 3  =R 4  =R/2 under this condition, the variable response amplifier becomes exactly equivalent to the amplifier illustrated in FIG. 23. When the movable contacts of the switches 252, 253 and 254 are thrown into contact with the respective stationary contact d, the controlled amplifier starts operating for the decoder. If C 3  =C e , R 7  =R e  and R 1  =R 2  =R/2 under this condition, the variable response amplifier becomes exactly equivalent to the amplifier shown in FIG. 24. 
     In short, the controlled amplifier shown in FIG. 25 can obtain two transfer functions inverse to each other if the polarity and bias value of the control voltage V c  are changed over simultaneously so as to satisfy the following conditions: 
     (1) R 1  =R 2  =R 3  =R 4  =R/2 (R i  =R f  =R) 
     (2) R 5  =R r   
     (3) C 1  =C r   
     (4) C 2  =C 3  =C e   
     (5) R 6  =R 7  =R e   
     (6) G e  =1/G d   
     The resistances R 1 , R 2  and R 7  and capacitor C 3  constitute F(S) 220F shown in FIG. 22 and the resistances R 3 , R 4  and R 6  and capacitor C 2  constitute G(S) 220G shown in FIG. 22 with grounded cold terminals. 
     Thus, it is seen that when the switches 252, 253 and 254 are switched to the &#34;e&#34; position shown in FIG. 25, those circuit elements then connected between the output terminal or n5 and the output VCA 250 at n4 constitute a pre-emphasis circuit. On the other hand, when switches 252, 253 and 254 are switched to the &#34;d&#34; position, those circuit elements between the input terminal or n1 and the input terminal of the VCA 250 at n3 constitute a de-emphasis circuit. 
     FIG. 26 shows another variable response amplifier which can operate alternatively for the encoder and the decoder. This variable response amplifier is similar to the amplifier shown in FIG. 25 except for the following points. First, a first switch 261 may have its stationary contacts e and d connected to the sixth node n6 and the second node n2, respectively and its movable contact grounded through a capacitor C e  and a resistor R e , provided that C 2  =C 3  and R 6  =R 7 . Secondly, a second switch 262 is used for the switches 252 and 253 of the amplifier shown in FIG. 25 which select whether the series circuit constituted by the fifth resistor R 5  and the first capacitor C 1  should be connected between the nodes 1 and 4 or between the nodes 3 and 5. When the movable contact of the second switch 262 is thrown to contact the stationary contact e, the resistors and the capacitor which are connected between the nodes 3 and 5 can be regarded equivalently as not being provided. 
     FIG. 27 shows a modified system with a modification of the controlled amplifier of FIG. 26. Modified two-part circuits F(S), G(S) shown in FIG. 25 may be used in the noise reduction system in such a manner as illustrated in FIG. 27. In this case, the noise reduction system has five switches 271, 272, 273, 274 and 279 each having a movable contact, a stationary contact e for the encoder and a stationary contact d for the decoder. When the movable contacts of these switches are thrown to contact the stationary contact e, the noise reduction system starts operating for the encoder. During the encoding operation, an input signal is supplied from an input terminal 275 to an output terminal 280 through the VCA 250 and the operational amplifier 251. The output signal is supplied further to an level sensor 277 through the switch 274. Under this condition, the VCA 250 and the operational amplifier 251 correspond to the controlled amplifier 21 of the noise reduction system shown in FIG. 18. The level sensor 277 includes the level sensor 22 and weighting circuit 24. 
     The output voltage of the level sensor 277 is applied to a limiter 276 which includes the limiter circuit modified from the limiter illustrated in FIG. 20. The output voltage of the level sensor 277 is amplified by an amplifier 2761 and then attenuated to the original level by an attenuator comprised of resistors 2762, 2763 and 2766. The junction between the resistors 2762 and 2763 is connected to a voltage source -V EE  via a diode D and a resistor 2764. The cathode of the diode D is connected to the emitter of a transistor TR, the base of which is applied with a variable bias from a potentiometer 2765. The limiter 276 amplifies the output of the level sensor 277, and the diode D limits the amplitude of the high level component of the amplfied output of the level sensor 277. Since the attenuator attenuates the output of the level sensor 277 to the original level, the transfer function of the limiter 276 remains 1 while the limiter is set in inoperative condition. The output of the limiter 276 is supplied to the VCA 250 as a control voltage V c  via a polarity circuit 278. A concrete circuit of the circuit 278 is shown in FIG. 28 the construction and operation of which is known and the further explanation thereof is omitted in the specification. 
     When the movable contacts of the switches 271, 272, 273, 274 and 279 are thrown to contact the stationary contacts d, the noise reduction system starts operating for the decoder. During the decoding operation, an analog signal supplied to the input terminal 275 is supplied directly to the level sensor 277 through the switch 274. Then, the control voltage V c  is applied through the polarity circuit 278 to the VCA 250 from the limiter 276. In this case the output polarity of the circuit 278 is opposite to that in the case of the encoder. Under this condition the VCA 250 and the circuits in front of VCA 250 function is the same manner as the controlled amplfier 31 of the noise reduction system shown in FIG. 18, and the level sensor 277 and limiter 276 correspond to the level sensor 32 and weighting circuit 34 and limiter 35 of the system shown in FIG. 18, respectively. 
     The circuit in FIG. 29 is another embodiment of the controlled amplifier alternatively usable as shown in FIG. 25. It comprises an input terminal I, capacitors C and C e , resistors R, R 1 , R 2  and R e , a buffer circuit 281, a variable response amplifier (VRA) for encoder/decoder 282, another buffer circuit 283, a switch 284 and an output terminal O. The input terminal I is connected to the buffer circuit 281 through the capacitor C e  and the resistor R e  which are connected parallel to each other. The output terminal of the buffer circuit 281 is connected to the VRA 282, the output terminal of which is connected to the input terminal of the buffer circuit 283 through the resistor R 2  and to one stationary contact 284A of the switch 284 through the resistor R and the capacitor C. The other stationary contact 284B of the switch 284 is connected to the input terminal of the buffer circuit 281 through the resistor R 1 . The movable contact 284C of the switch 284 is grounded. 
     In case the movable contact 284C is thrown to contact the stationary contact 284B, the front end circuit comprising resistors R 1  and R e  and capacitor C e  serves as the pre-emphasis circuit. The transfer function G P  (S) of the pre-emphasis circuit can be expressed as follows: ##EQU11## 
     In equation (14), Ω denotes an angular frequency, and S=jΩ. Equation (14) indicates that the front end circuit of FIG. 29 exhibits a constant frequency characteristic. Thus, the front end circuit can obtain such a weighting function of high frequency emphasis type as illustrated in FIG. 30A. 
     In case the movable contact 284C is thrown to contact the stationary contact 284A, the tail end circuit comprising resistors R and R 2  and capacitor C serves as the de-emphasis circuit. In this case, the de-emphasis circuit is put in tale of VRA. The transfer function G D  (S) of the de-emphasis circuit can be expressed as follows: ##EQU12## 
     Also in equation (15), Ω denotes an angular frequency, and S=jΩ. Equation (15) shows that the tail circuit of FIG. 29 can obtain such a weighting function of high frequency attenuation type as illustrated in FIG. 30B. If the high frequency component of an input signal is given gain of, for example, 20dB, the following conditions should be satisfied in order to unify the time constant: 
     (1) R e  =10R 
     (2) R 1  =(10/9)R 
     (3) C=C e   
     (4) R 2  =9R 
     As a result, in case the movable contact 284C is thrown to contact the stationary contact 284B, the circuit of FIG. 29 show a frequency characteristic which is inverse to the frequency characteristic obtained in case the movable contact 284C is thrown to contact the stationary contact 284A. 
     The circuit shown in FIG. 29 may be modified as shown in FIG. 31. In the circuit of FIG. 31, a resistor 304 is connected between an input terminal I and the input terminal of a buffer circuit 301. Another resistor 305 and a capacitor 306 are connected in parallel to each other and between the output terminal of the buffer circuit 301 and a VRA for encoder/decoder 300. The input terminal of the VRA 300 is connected to one stationary contact 303B of a switch 303 through a resistor 307. The stationary contact 303B connected to the input terminal of the buffer 301 through a resistor 308 and a capacitor 309. The output terminal of the VRA 300 to the input terminal of another buffer circuit 302 through a parallel circuit constituted by a resistor 310 and a capacitor 311. The input terminal of the buffer circuit 302 is connected to the other stationary contact 303A of the switch 303 through a resistor 312 and a capacitor 313. 
     Being constructed as illustrated in FIG. 31, the front end circuit and the tail end circuit of VRA can obtain such opposite attenuation characteristics as indicated by lines A and B in FIG. 32, merely by throwing the movable contact 303C to contact alternatively the stationary contacts 303A and 303B. The characteristics shown in FIG. 32 are useful when the recording medium, such as a disc record, has high noise level both in high and low frequency ranges. 
     Further, the circuit shown in FIG. 29 may be modified as illustrated in FIG. 33. In the circuit of FIG. 33, an operational amplifier 321 has its output terminal connected to a VRA 322, the output terminal of which is connected to the input terminal of a buffer circuit 324 through a resistor 323. The input terminal of the buffer circuit 324 is connected to one stationary contact 327A of a switch 327 through a resistor 325 and a capacitor 326. The other stationary contact 327B of the switch 327 is connected the junction of a resistor 328 and a capacitor 329 which are connected between inversion input terminal of the operational amplifier 321 and the ground. A resistor 330 is connected between said input terminal and output terminal of the operational amplifier 321. The switch 327 has two movable contacts 327C and 327D which are to contact the stationary contacts 327A and 327B, respectively, and which are grounded. 
     When both movable contacts 327C and 327D are moved to be disconnected from the stationary contact 327A and 327B, the operational amplifier 321 starts working as a pre-emphasis circuit while the tail end circuit of VRA starts as mere resistor. When both movable contacts 327C and 327D are thrown to contact the stationary contacts 327A and 327B, respectively, the operational amplifier 321 starts functioning as an amplifier whose frequency characteristic is constant and the tail end of VRA starts operating as a de-emphasis circuit. 
     Though the level change of the input signal is compressed to 1/2 in logarithmic scale and expanded double in logarithmic scale as shown in FIG. 2, the level change of the input signal can be compressed or expanded at any desired degree, for example, 1.5, in logarithmic scale without degrading the advantages of this invention.