Recording apparatus including analog-digital converter
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to generally apparatus for recording data or information upon a recording medium and more particularly recording apparatus of the type described and incorporating an analog-to-digital (to be referred to &#34;analog-digital&#34; in this specification) converter. 
     2. Description of the Prior Art 
     The recent trend of the recording apparatus is toward the extensive use of computers as disclosed in for instance U.S. Pat. No. 3,936,182. The microcomputers however operate on binary digits &#34;1&#34; and &#34;0&#34; or digitally so that analog electrical signals derived by photo-electric conversion, magneto-electric conversion and thermo-electric conversion for attaining an optimum operation of the recording apparatus must be converted into corresponding digital signals by semiconductor linear integrated circuits and circuits consisting of various combinations of discrete circuit elements such as transistors, resistors, capacitors, inductors and the like, both of which circuits are external to the microcomputer. As a result, the number of electrical elements is in proportion to the number of analog signals to be processed or converted into digital signals so that the principal and fundamental objects of the use of a microcomputer for increasing the packing density, improving the reliability and reducing the cost are adversely affected. 
     In order to overcome the above and other problems, there has been proposed a method wherein analog-digital converters each in the form of an integrated circuit are combined with the photo-electric, magneto-electric and thermo-electric converters. However these analog-digital converters are of CMOS type and of a sequential-comparison type. Therefore because of the difficulty of integrating a large number of circuit elements at a high packing density and because of a small demand for the analog-digital converters themselves, the cost is still very high. Thus the combination of the photo-electric, magneto-electric and thermo-electric converters with the analog-digital converter will result in complex circuitry and an increase in cost of the recording apparatus. 
     SUMMARY OF THE INVENTION 
     Accordingly, one of the objects of the present invention is to provide recording apparatus incorporating an analog-digital converter which is significantly simple in circuit configuration. 
     Another object of the present invention is to provide recording apparatus incorporating a minimum number of analog-digital converters. 
     A further object of the present invention is to provide recording apparatus incorporating an analog-digital converter which can be manufactured at a minumum cost. 
     To the above and other ends, briefly stated the present invention provides recording apparatus incorporating an analog-digital converter wherein a plurality of analog signals may be sequentially transmitted one at a time to a common analog-digital converter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram of a first embodiment of recording apparatus incorporating an analog-digital converter in accordance with the present invention; 
     FIG. 2 is a flow chart used for the explanation of the mode of operation of the first embodiment shown in FIG. 1; 
     FIG. 3 shows a list of instruction codes stored in a read-only memory; 
     FIG. 4 is a circuit diagram of an analog switch of the first embodiment shown in FIG. 1; 
     FIG. 5 is a schematic block diagram of a second embodiment of the present invention; 
     FIG. 6 is a schematic circuit diagram of an instruction decoder thereof; 
     FIG. 7 shows the relation of the circuit shown in FIG. 5 with various peripheral equipment and input and output signals; 
     FIG. 8 is a perspective view of a copying machine implementing the present invention; 
     FIG. 9A is a perspective view of a background density sensor which may be used in conjunction with the present invention; and 
     FIG. 9B is a sectional view taken in the direction indicated by arrows B and B&#39; of FIG. 9A. 
     The same reference numerals are used to designate similar parts throughout the figures. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment, FIGS. 1-4 
     Referring to the accompanying drawings and particularly to FIG. 1, a first embodiment of recording apparatus incorporating an analog-digital converter in accordance with the present invention will be described. A microcomputer generally indicated by the reference numeral 11 is a commercially available product sold under the trade name &#34;μPD546C (μCOM-43)&#34; from NIPPON ELECTRIC CO., LTD., Japan. It includes a program counter 100 for storing an address of a program sequence stored in a read-only memory ROM 105; a stack register STACK 101 for saving the contents of the program counter PC 100 when a subroutine is executed; a data pointer DP 102 which has access to an address of a random access memory RAM 103 which stores data; a timer 104, the read-only memory ROM 105 for storing the program sequences; and arithmetic and logic unit ALU 106 whose outputs are stored in an accumulating storage or accumulator ACC 107 and used to set a carry flip-flop or status flag 108; and input and output ports 109 through 117. The ports 109 and 110 are input ports; the ports 111 and 112 are input-output ports; and the ports 113-117 are output ports. The output port 117 consists of a three-bit flip-flop while the remaining ports 109 through 116 each consist of a four-bit flip-flop. The input ports are connected to terminals PA, PB and A shown in FIG. 7 while the output ports are connected to terminals P1, PH and PE. The microcomputer of the type described and shown in FIG. 1 is called a one-chip microcomputer wherein the circuits or logic 100 through 117 are implemented on a single chip and which may be incorporated in a control circuit for an electronic copying device of the type disclosed in Japanese Patent Application No. 22981/1977 or No. 22982/1977 assigned to the same assignee. Since the present invention however is not directed to the control circuit proper of the type described and for the sake of simplicity, the control circuit will not be described in detail in this specification. 
     Referring still to FIG. 1, analog signals 1, 2 and 3 representing some analog values are applied to terminals 12, 13 and 14, respectively. As shown in FIG. 7, a first analog signal may be generated from a circuit consisting of a resistor R3, a variable resistor VR3 and a thermistor 37&#39;. In a like manner a second analog signal 2 may be generated from a circuit consisting of a resistor R2, a variable resistor VR2, a CdS device 36 and a lamp 38 while a third analog signal 3 may be generated from a circuit consisting of a resistor R1, a variable resistor VR1, a CdS component 34 and a lamp 37. 
     These analog signal input terminals 12, 13 and 14 are connected to analog switches 15, 16 and 17, respectively, which in turn are connected through output lines 18, 19, 20 and 21 to a common analog-digital converter 22 (which may be for instance a product of ANALOG DEVICES CORP. under the trade name of &#34;AD7570&#34;). The ON-OFF operations of the analog switches 15, 16 and 17 are controlled in response to control signals which appear at terminals PE0, PE1 and PE2 of the port 113 of the microcomputer 11. More particularly, the terminal PE0 is connected to a control terminal of the analog switch 15; the terminal PE1, to a control terminal of the analog switch 16; and the terminal PE2, to a control terminal of the analog switch 17. When the control signal at the terminal PE0 is a logical &#34;1&#34;, the analog switch 15 is turned on, whereby the analog signal 1 is applied to the A-D converter 22. In a like manner, in response to the control signal &#34;1&#34; at the terminal PE1 or PE2, the analog switch 16 or 17 is turned on whereby the analog signal 2 or 3 is applied to the A-D converter 22. On the other hand, in response to the control signal &#34;0&#34;, the analog switches 15, 16 and 17 are turned off. It should be noted that only one of these analog switches 15, 16 and 17 is turned on at one time while the remaining two switches are kept turned off. 
     The analog signal applied to the A-D converter 22 may be converted into a digital signal within a very short time period. The A-D converter 22 develops a four-bit output signal to the input port 109 of the microcomputer 11. Thus the resolution of the output is four bits, which means that an analog signal with a maximum value of for instance 10 volts may be divided into 10×1/2 4  discrete steps. 
     Next, referring further to FIGS. 2 and 3, the mode of operation of the first embodiment with the above construction will be described. FIG. 3 shows instruction codes stored in memory locations starting from an address 100 in the read-only memory ROM 105. 
     In order to clearly understand the description of the preferred embodiments in accordance with the invention, the instructions used in the aforementioned microprocessor μPD546C are shown in the following tables. 
     
         __________________________________________________________________________
Instruction Code.                                                         
Mnemonic.                                                                 
      D.sub.7                                                             
        D.sub.6                                                           
          D.sub.5                                                         
            D.sub.4                                                       
              D.sub.3                                                     
                D.sub.2                                                   
                   D.sub.1                                                
                     D.sub.0                                              
                       Bytes.                                             
                           Machine Cycles.                                
                                    Operation.       Condition for        
__________________________________________________________________________
                                                     Skip.                
CLA   1 0 0 1 0 0  0 0 1   1        Acc ← 0                          
CLC   0 0 0 0 1 0  1 1 1   1        C ← 0                            
CMA   0 0 0 1 0 0  0 0 1   1                                              
                                     ##STR1##                             
CIA   0 0 0 1 0 0  0 1 1   1                                              
                                     ##STR2##                             
INC   0 0 0 0 1 1  0 1 1   1/2-3    Acc ← (Acc) + 1                  
                                                     Carry                
                                    skip if Carry                         
DEC   0 0 0 0 1 1  1 1 1   1/2-3    Acc ← (Acc) - 1                  
                                                     Borrow               
                                    skip if Borrow                        
STC   0 0 0 1 1 0  1 1 1   1        C ← 1                            
XC    0 0 0 1 1 0  1 0 1   1        (C) ⃡ (C&#39;)                
RAR   0 0 1 1 0 0  0 0 1   1        (C) → Acc.sub.3, (Acc.sub.a)   
                                    → (Acc.sub.a-1);               
                                    (Acc.sub.n) → C                
INM   0 0 0 1 1 1  0 1 1   1/2-3    [(DP)] ← [(DP)] + 1              
                                                     [(DP)] = 0           
                                    skip if [(DP)] = 0                    
DEM   0 0 0 1 1 1  1 1 1   1/2-3    [(DP)] ← [(DP)] - 1              
                                                     [(DP)] = F           
                                    skip if [(DP)] = F                    
AD    0 0 0 0 1 0  0 0 1   1/2-3    Acc ← (Acc) + [(DP)]             
                                                     Carry                
                                    skip if Carry                         
ADS   0 0 0 0 1 0  0 1 1   1/2-3    Acc, C ← (Acc) + [(DP)] +        
                                                     Carry                
                                    skip if Carry                         
ADC   0 0 0 1 1 0  0 1 1   1        Acc, C ← (Acc) + [(DP)] + (C)    
DAA   0 0 0 0 0 1  1 0 1   1        Acc ← (Acc) + 6                  
DAS   0 0 0 0 1 0  1 0 1   1        Acc ← (Acc) + 10                 
EXL   0 0 0 1 1 0  0 0 1   1        Acc ← (Acc) --V [(DP)]           
LI    1 0 0 1 I.sub.3                                                     
                I.sub.2                                                   
                   I.sub.1                                                
                     I.sub.0                                              
                       1   1        Acc ← I.sub.3 I.sub.2 I.sub.1    
                                    I.sub.0                               
S     0 0 0 0 0 0  1 0 1   1        [(DP)]  ← (Acc)                  
L     0 0 1 1 1 0  0 0 1   1        Acc ← [(DP)]                     
LM    0 0 1 1 1 0  M.sub.1                                                
                     M.sub.0                                              
                       1   1        Acc ← [(DP)]                     
                                    DP.sub.H ← (DP.sub.H) --V        
                                    M.sub.1 M.sub.0                       
X     0 0 1 0 1 0  0 0 1   1        (Acc) ⃡ [(DP)]            
XM    0 0 1 0 1 0  M.sub.1                                                
                     M.sub.0                                              
                       1   1        (Acc) ⃡ [(DP)]            
                                    DP.sub.H ← (DP.sub.H) --V        
                                    M.sub.1 M.sub.0                       
XD    0 0 1 0 1 1  0 0 1   1/2-3    (Acc) ⃡ [(DP)]            
                                    DP.sub.L ← (DP.sub.L)            
                                                     (DP.sub.L) = F       
                                    skip if (DP.sub.L) = F                
XMD   0 0 1 0 1 1  M.sub.1                                                
                     M.sub.0                                              
                       1   1/2-3    (Acc) ⃡ [(DP)]            
                                    DP.sub.H ← (DP.sub.H) --V        
                                    M.sub.1 M.sub.0  (DP.sub.L) = F       
                                    DP.sub.L ← (DP.sub.L) - 1        
                                    skip if (DP.sub.L) = F                
XI    0 0 1 1 1 1  0 0 1   1/2-3    (Acc) ⃡ [(DP)]            
                                    DP.sub.L ← (DP.sub.L)            
                                                     (DP.sub.L) = 0       
                                    skip  (DP.sub.L) = 0                  
XMI   0 0 1 1 1 1  M.sub.1                                                
                     M.sub.0                                              
                       1   1/2-3    (Acc) ⃡ [(DP)]            
                                    DP.sub.H ← (DP.sub.H) --V        
                                    M.sub.1 M.sub.0                       
                                    DP.sub.L ← (DP.sub.L)            
                                                     (DP.sub.L) = 0       
                                    skip if (DP.sub.L) = 0                
LDI   0 0 0 1 0 1  0 1 2   2        DP ← I.sub.6 -I.sub.0            
      0 I.sub.6                                                           
          I.sub.5                                                         
            I.sub.4                                                       
              I.sub.3                                                     
                I.sub.2                                                   
                   I.sub.1                                                
                     I.sub.0                                              
LDZ   1 0 0 0 I.sub.3                                                     
                I.sub.2                                                   
                   I.sub.1                                                
                     I.sub.0                                              
                       1   1        DP.sub.H ← 0                     
                                    DP.sub.L ← I.sub.3 I.sub.2       
                                    I.sub.1 I.sub.0                       
DED   0 0 0 1 0 0  1 1 1   1/2-3    DP.sub.L ← (DP.sub.L)            
                                                     (DP.sub.L) = F       
                                    skip if (DP.sub.L ) = F               
IND   0 0 1 1 0 0  1 1 1   1/2-3    DP.sub.L ← (DP.sub.L)            
                                                     (DP.sub.L) = 0       
                                    skip if (DP.sub.L) = 0                
TAL   0 0 0 0 0 1  1 1 1   1        DP.sub.L ← (Acc)                 
TLA   0 0 0 1 0 0  1 0 1   1        Acc ← (DP.sub.L)                 
XHX   0 1 0 0 1 1  1 1 1   2        (DP.sub.H) = (X)                      
XLY   0 1 0 0 1 1  1 0 1   2        (DP.sub.L) = (Y)                      
THX   0 1 0 0 0 1  1 1 1   2        (DP.sub.H) → X                 
TLY   0 1 0 0 0 1  1 0 1   2        (DP.sub.L) → Y                 
XAZ   0 1 0 0 1 0  1 0 1   2        (Acc) ⃡ (Z)               
XAW   0 1 0 0 1 0  1 1 1   2        (Acc) ⃡ (W)               
JPA   0 1 0 0 0 0  0 1 1   2        PC ← A.sub.3 A.sub.2 A.sub.1     
                                    A.sub.0 00                            
EI    0 0 1 1 0 0  0 1 1   1        INTE F/F ← 1                     
DI    0 0 0 0 0 0  0 1 1   1        INTE F/F ← 0                     
CZP   1 0 1 1 P.sub.3                                                     
                P.sub.2                                                   
                   P.sub.1                                                
                     P.sub.0                                              
                       1   1        (PC) →STACK                    
                                    PC ← 00000P.sub.3 P.sub.2        
                                    P.sub.1 P.sub.0 00                    
CAL   1 0 1 0 1 P.sub.10                                                  
                   P.sub.9                                                
                     P.sub.8                                              
                       2   2        (PC) → STACK                   
      P.sub.7                                                             
        P.sub.6                                                           
          P.sub.5                                                         
            P.sub.4                                                       
              P.sub.3                                                     
                P.sub.2                                                   
                   P.sub.1                                                
                     P.sub.0        PC ← P.sub.10 -P.sub.0           
RT    0 1 0 0 1 0  0 0 1   2        PC ← (STACK)                     
RTS   0 1 0 0 1 0  0 1 1   3-4      PC ← (STACK)                     
                                                     Uncondi-             
                                    PC ← (PC) + 1,2                  
                                                     tional               
SEB   0 1 1 1 0 1  B.sub.1                                                
                     B.sub.0                                              
                       1   2        PORT E(B.sub.1 B.sub.0) ← 1      
REB   0 1 1 0 0 1  B.sub.1                                                
                     B.sub.0                                              
                       1   2        PORT E(B.sub.1 B.sub.0) ← 0      
SPB   0 1 1 1 0 0  B.sub.1                                                
                     B.sub.0                                              
                       1   1        PORT(DT.sub.L,B.sub.1 B.sub.0) ← 
                                    1                                     
RPB   0 1 1 0 0 0  B.sub.1                                                
                     B.sub.0                                              
                       1   1        PORT(DP.sub.L,B.sub.1 B.sub.0) ← 
                                    0                                     
TPA   0 1 0 1 0 1  B.sub.1                                                
                     B.sub.0                                              
                       1   2/3-4    skip if (PORT A(B.sub.1 B.sub.0))     
                                                     (PORT A              
                                    = 1              (B.sub.1 B.sub.0)) = 
                                                     1                    
TPB   0 1 0 1 0 0  B.sub.1                                                
                     B.sub.0                                              
                       1   1/2-3    skip if (PORT(DP.sub.L,B.sub.1        
                                    B.sub.0))        (PORT(DP.sub.L,      
                                    = 1              B.sub.1 B.sub.0)) =  
                                                     1                    
OE    0 1 0 0 0 1  0 0 1   2        PORT E ← (Acc)                   
OP    0 0 0 0 1 1  1 0 1   1        PORT(DP.sub.L) ← (Acc)           
OCD   0 0 0 1 1 1  1 0 2   2        PORT C,D ← I.sub.7 -I.sub.0      
      I.sub.7                                                             
        I.sub.6                                                           
          I.sub.5                                                         
            I.sub.4                                                       
              I.sub.3                                                     
                I.sub.2                                                   
                   I.sub.1                                                
                     I.sub.0                                              
IA    0 1 0 0 0 0  0 0 1   2        (PORT A) → Acc                 
IP    0 0 1 1 0 0  1 0 1   1        (PORT(DP.sub.L)) → Acc         
STM   0 0 0 1 0 1  0 0 2   2        TMF/F ← 0                        
      1 0 I.sub.5                                                         
            I.sub.4                                                       
              I.sub.3                                                     
                I.sub.2                                                   
                   I.sub.1                                                
                     I.sub.0        TIMER ← I.sub.5 -I.sub.0         
NOP   0 0 0 0 0 0  0 0 1   1        No Operation                          
TAZ   0 1 0 0 0 0  1 0 1   2        (Acc) → Z                      
TAW   0 1 0 0 0 0  1 1 1   2        (Acc) → W                      
XHR   0 1 0 0 1 1  0 1 1   2        (DP.sub.H) ⃡ (R)          
XLS   0 1 0 0 1 1  0 0 1   2        (DP.sub.L) ⃡ (S)          
SMB   0 1 1 1 1 0  B.sub.1                                                
                     B.sub.0                                              
                       1   1        [(DP,B.sub. 1 B.sub.0)] ← 1      
RMB   0 1 1 0 1 0  B.sub.1                                                
                     B.sub.0                                              
                       1   1        [(DP,B.sub.1 B.sub.0)] ← 0       
TMB   0 1 0 1 1 0  B.sub.1                                                
                     B.sub.0                                              
                       1   1/2-3    skip if [(DP,B.sub.1 B.sub.0)]        
                                                     [(DP,B.sub.1         
                                                     B.sub.0)]            
                                    = 1              = 1                  
TAB   0 0 1 0 0 1  B.sub.1                                                
                     B.sub.0                                              
                       1   1/2-3    skip if (Acc(B.sub.1 B.sub.0))        
                                                     (Acc(B.sub.1         
                                                     B.sub.0))            
                                    = 1              = 1                  
CMB   0 0 1 1 0 1  B.sub.1                                                
                     B.sub.0                                              
                       1   1/2-3    skip if (Acc(B.sub.1 B.sub.0))        
                                                     (Acc(B.sub.1         
                                                     B.sub.0))            
                                    = [(DP,B.sub.1 B.sub.0)]              
                                                     = [(DP,B.sub.1       
                                                     B.sub.0 0)]          
SFB   0 1 1 1 1 1  B.sub.1                                                
                     B.sub.0                                              
                       1   2        FLAG(B.sub.1 B.sub.0) ← 1        
RFB   0 1 1 0 1 1  B.sub.1                                                
                     B.sub.0                                              
                       1   2        FLAG(B.sub.1 B.sub.0) ← 0        
FBT   0 1 0 1 1 1  B.sub.1                                                
                     B.sub.0                                              
                       1   2/3-4    skip if (FLAG(B.sub.1 B.sub.0) =      
                                                     (FLAG(B.sub.1        
                                                     B.sub.0))            
                                                     = 1                  
FBF   0 0 1 0 0 0  B.sub.1                                                
                     B.sub.0                                              
                       1   2/3-4    skip if (FLAG(B.sub.1 B.sub.0)) =     
                                                     (FLAG(B.sub.1        
                                                     B.sub.0))            
                                                     = 1                  
CM    0 0 0 0 1 1  0 0 1   1/2-3    skip if (Acc) = [(DP)]                
                                                     (Acc) = [(DP)]       
CI    0 0 0 1 0 1  1 1 2   2/3-4    skip if (Acc) = I.sub.3 I.sub.2       
                                    I.sub.1 I.sub.0  (Acc)                
      1 1 0 0 I.sub.4                                                     
                I.sub.2                                                   
                   I.sub.1                                                
                     I.sub.0                         = I.sub.3 I.sub.2    
                                                     I.sub.1 I.sub.0      
CLI   0 0 0 1 0 1  1 0 2   2/3-4    skip if (DP.sub.L) = I.sub.3 I.sub. 2 
                                    I.sub.1 I.sub.0  (DP.sub.L)           
      1 1 1 0 I.sub.4                                                     
                I.sub.2                                                   
                   I.sub.1                                                
                     I.sub.0                         = I.sub.3 I.sub.2    
                                                     I.sub.1 I.sub.0      
TC    0 0 0 0 0 1  0 0 1   1/2-3    skip if (C) = 1  (C) = 1              
TTM   0 0 0 0 0 1  0 1 1   1/2-3    skip if (TM F/F) = 1                  
                                                     (TM F/F) = 1         
TIT   0 0 0 0 0 0  1 1 1   1/2-3    skip if (INT F/F) = 1                 
                                                     (INT F/F) = 1        
                                    INT F/F ← 0                      
JCP   1 1 P.sub.5                                                         
            P.sub.4                                                       
              P.sub.3                                                     
                P.sub.2                                                   
                   P.sub.1                                                
                     P.sub.0                                              
                       1   1        PC ← P.sub.5 -P.sub.0            
JMP   1 0 1 0 0 P.sub.10                                                  
                   P.sub.9                                                
                     P.sub.8                                              
                       2   2        PC ← P.sub.10 -P.sub.0           
      P.sub.7                                                             
        P.sub.6                                                           
          P.sub.5                                                         
            P.sub.4                                                       
              P.sub.3                                                     
                P.sub.2                                                   
                   P.sub.1                                                
                     P.sub.0                                              
__________________________________________________________________________
 Note:                                                                    
 Acc : Accumulator                                                        
 An : Accumulator bit n                                                   
 C : Carry F/F                                                            
 C&#39; : Carry save F/F                                                      
 Carry : Carry bit generated in Acc, (but does not necessarily set C).    
 Borrow : Borrow generated in Acc, (but does not affect C).               
 DP : Data pointer                                                        
 PC : Program counter                                                     
 X : Working register X                                                   
 Y : Working register Y                                                   
 Z : Working register Z                                                   
 W : Working register W                                                   
 R : Working register R                                                   
 S : Working register S                                                   
 FLAG : Flag register                                                     
 TM F/F : Timer F/F                                                       
 TIMER : Timer                                                            
 INT F/F : Interrupt F/F                                                  
 INTE F/F : Interrupt Enable F/F                                          
 STACK : Stack register                                                   
 PORT : Input/output port                                                 
 () : Contents                                                            
 [(XX)] : Memory data addressed by (DP) or the bit of the port specified b
 (DP, B.sub.1 B.sub.0).                                                   
 ← : Transfer or transfer of result.                                 
 ⃡ : Exchange                                                 
 --V :Logical exclusive OR.                                               
 1 : Set                                                                  
 0 : Reset                                                                
 
    
     In the first step, the microcomputer 11 produces the control signal &#34;1&#34; from the terminal PE0 of the port 113, whereby the first analog switch 12 is turned on. To this end, the microcomputer 11 reads the contents &#34;01110100&#34; of the memory location with the address 100 designated by the contents of the program counter 100 and interprets the instruction code so that the control signal &#34;1&#34; appears at the terminal PE0 of the port 113. Then the first analog switch 15 is turned on while the remaining switches 16 and 17 are kept turned off so that the first analog signal 1 is applied to the A-D converter 22 and a four-bit digital signal appears at the output terminal of the A-D converter 22. However it takes some period of time for the A-D converter 22 to convert the analog signal into the digital signal so that &#34;NO OPERATION&#34; code or timing filler is stored in each of the memory locations with the addresses 101 through 104. Therefore the microcomputer 11 waits until the four-bit digital output signal is derived from the A-D converter 22. In the first embodiment a memory read instruction cycle or period is approximately 10 microseconds so that the microcomputer 11 must wait for approximately 40 microseconds before it executes the second step. However a time required for an analog-digital conversion is different from one converter to another, but at least approximately 10 microseconds is required so that at least one no-operation instruction NOP must be inserted. 
     In the second step, the microcomputer 11 reads the contents of the memory location with the address 105 so that the digital signal at the input port 109 is moved into the accumulator ACC 107. 
     Upon completion of the second step, the digital signal A1 which has been converted from the analog signal 1 is stored in the accumulator ACC 107 so that a predetermined processing routine may be started in response to the digital signal A1 in the accumulator 107. The routine may be such that the digital signal A1 is so processed as to derive a desired control signal. 
     In a like manner, in the fourth and fifth steps, the microcomputer 11 produces the analog switch 16 is turned on and consequently the second analog signal 2 is applied to the A-D converter 22. The second digital signal A2 at the port 109 is stored in the accumulator 107. In the sixth step a predetermined processing routine such as deriving a desired control signal from the digital signal A2 may be executed. 
     In a similar manner, in the steps 7 and 8, the control signal &#34;1&#34; appears at the terminal PE 2 of the port 113 so that the third analog switch 17 is turned on and consequently the analog signal 3 is applied to the A-D converter 22. Thereafter the third digital signal A3 at the port 109 is transferred to the accumulator 107, and in the ninth step a predetermined processing routine is executed in response to the contents of or the third digital signal A3 in the accumulator 107. 
     Thus with one A-D converter 22 a plurality of analog signals may be converted into corresponding digital signals which may be sequentially processed in the manner described above. 
     FIG. 4 shows a circuit diagram of the analog switches 15, 16 and 17. Each analog switch comprises P-channel MOS transistors Q1 and Q3 and N-channel MOS transistors Q2 and Q3. When a relative voltage at the control terminal 26 is at a low level &#34;L&#34;, the transistor Q1 is enabled while the transistor Q2 is disabled so that a voltage on a signal line 27 rises to a high level &#34;H&#34;. As a result, the transistor Q3 is disabled. Since the control terminal 26 is at a low level &#34;L&#34;, the transistor Q4 remains disabled. Therefore the analog signal at an input terminal 28 is not transmitted to an output terminal 29. 
     However when the control terminal 26 rises to a high level &#34;H&#34;, the transistor Q1 is disabled while the transistor Q2 is enabled so that the signal line 27 drops to a low level &#34;L&#34;. Consequently both transistors Q3 and Q4 are enabled, whereby the analog signal at the input terminal 28 is transmitted to the output terminal 29. 
     The analog switches 15, 16 and 17 of the type described above with reference to FIG. 4 are compatible with the A-D converter 22 and the microcomputer 11 both of which consist of MOS FETs so that they may be implemented on a single chip as an LSI. 
     Second Embodiment, FIGS. 5-7 
     A second embodiment of the present invention to be described in detail below with reference to FIGS. 5, 6 and 7 includes such an LSI 32 containing the components encircled by the chain line. The LSI 32 includes an analog-digital converter 30 with four-bit resolution (which is substantially similar in construction to the A-D converter COM-43 shown in FIG. 1). The output of the A-D converter 30 is connected to a data bus 31. 
     Terminals A1, A2 and A3 to which are applied the analog signals 1, 2 and 3, respectively, (which may be generated in a manner substantially similar to that described in conjunction with the first embodiment) are connected to the first, second and third analog switches 15, 16 and 17, respectively, which in turn are connected to the A-D converter 30. 
     The transmission of the analog signals 1, 2 and 3 from the input terminals A1, A2 and A3 through the analog switches 15, 16 and 17 to the A-D converter and the transmission of the four-bit digital output signal from the A-D converter 30 to the data bus 31 are controlled in response to the control signals which are derived by the decoding in an instruction decoder ID 118 of instruction codes read out from the read-only memory 105 and transmitted from the instruction decoder ID 118 through signal lines C1, C2, C3 and C4. 
     Therefore in addition to the instruction codes described above in conjunction with the first embodiment, the read-only memory ROM 105 further includes four additional instruction codes: 
     (a) an instruction code for turning on the first analog switch 15 thereby transferring the first analog signal 1 at the terminal A1 to the A-D converter 30; 
     (b) an instruction code for turning on the second analog switch 16 thereby transferring the second analog signal 2 at the second input terminal A2 to the A-D converter 30; 
     (c) an instruction signal for turning on the third analog switch 17 thereby transferring the third analog signal 3 at the third input terminal A3 to the A-D converter 30; and 
     (d) an instruction code for storing the output from the A-D converter 30 into the accumulator 107. 
     Such instruction codes may be selected from not-used codes of the COM 43 converter. For instance, the instruction code (a) may be &#34;11010000&#34;; the instruction code (b), &#34;11010001&#34;; the instruction code (c), &#34;11010010&#34;; and the instruction code (d), &#34;11010011&#34;. 
     Therefore the instruction decoder ID 118 must be modified as shown in FIG. 6. An eight-digit instruction code read out from the read-only memory ROM appears on eight signal lines L1 through L8. The matrix is so arrayed that when the instruction code (a) is read out from the read-only memory ROM 105, a high level &#34;H&#34; signal appears only on the signal line C1 (while the remaining three signal lines C2, C3 and C4 remain at a low level &#34;L&#34;). In a like manner, when the instruction code (b) is read out, only the signal line C2 rises to a high level &#34;H&#34; so that the second analog switch 16 is turned on, whereby the second analog signal 2 is moved into the A-D converter 30. When the instruction code (c) is read out, the signal line C3 rises to a high level &#34;H&#34; so that the third analog switch 17 is turned on and consequently the third analog signal 3 is transmitted to the A-D converter 30. When the instruction code (d) is read out, only the fourth signal line C4 rises to a high level &#34;H&#34;, whereby the digital output signal from the A-D converter 30 is moved into the accumulator ACC 107. 
     In the read-only memory ROM 105, the first instruction code (a) &#34;11010000&#34; is stored in the memory location with the address 100 while the instruction code (d) &#34;00101100&#34; is stored in the memory location with the address 105. Then the instruction codes (a) and (d) are sequentially read out after four timing fillers NOP, whereby the first analog signal 1 at the first input terminal A1 is converted into a four-bit digital signal which in turn is transferred into the accumulator ACC 107. In a similar manner, the second and third analog signals 2 and 3 may be each converted into a four-bit digital signal which in turn is accumulated in the accumulator ACC 107. 
     Copying or Recording Machine, FIGS. 7 through 9 
     FIG. 7 shows schematically a control unit of a copying or recording machine of the type described in U.S. Pat. No. 3,804,512, assigned to the same assignee, and including the LSI described with reference to FIG. 5. Applied to the first analog signal input terminal A1 of the LSI 32 is the output from a background density sensor 33 for detecting the density of the background of an original to be copied. That is, the voltage across the CdS device 34 is applied to the first terminal A1. Applied to the second input terminal A2 is the output or the voltage across the CdS device 36 of a toner density sensor 35 which detects the density of the toner which is used for developing an electrostatic latent image formed on a photosensitive drum into a visible image. Applied to the third input terminal A3 is the output or the voltage across the thermistor 37&#39; which detects the temperature of a fixing heater which fuses the toner transferred onto a copying sheet of paper. 
     Therefore a plurality of analog signals which are applied to the LSI 32 may be sequentially read and converted into a digital signal in response to which a control signal such as CHARGER CONTROL, TONER REPLENISH, FIXING HEATER CONTROL or the like may be derived. 
     FIG. 8 is a perspective view of the copying or recording machine incorporating therein the control unit described above with reference to FIG. 7. The copying machine generally indicated by the reference numeral 40 has a main body 41 upon which is mounted an original holder (not shown) including a pressure plate 43 swingable about a shaft 42. The copying machine 40 further includes among other things a keyboard 44 for setting the number of copies to be reproduced, a start button 45, paper feed cassettes 46 and a copy discharge tray 47. 
     A triangle notch 49 is formed at one corner 48 of the main body 41. As best shown in FIGS. 9A and 9B, the triangle notch 49 is defined by an upper plate 50, a bottom plate 51 and a vertical plate 52 interconnecting them. Coaxial holes 53 and 54 are formed through the upper and bottom plates 50 and 51, respectively. The CdS device or photosensor 34 is mounted on the upper plate 50 and the light source or lamp 37 is mounted on the bottom plate 51 in such a manner that the light emitted from the lamp 37 is transmitted through these holes 54 and 53 to be received by the CdS photosensor 34. When an original 55 is inserted into the triangular notch 49, the output from the CdS photosensor 34 is in proportion to the amount of light transmitted through the original 55, whereby the density of the background of the original 55 can be detected. The output from the CdS photosensor 34 is applied to the first input terminal A1 as described above, whereby the copying machine will be suitably controlled in response to the density of the background of the original 55. 
     A switch 56 is mounted on the upper plate 50 on the side of the vertical plate 52 with its actuating arm 57 extended downward into the triangular notch 49 through a hole formed through the upper plate 50. When the original 55 is inserted into the notch 49, the actuating arm 57 is pushed in the direction indicated by an arrow T, whereby the switch 56 is turned on. The output signal from this switch 56 may be used as a trigger signal for converting the output from the CdS photosensor 34 into a digital signal. For instance, in response to the output from the switch 56, the memory location with address 100 in the read-only memory ROM will be accessed (See FIG. 5). 
     As described above, according to the present invention the combination of a single expensive analog-digital converter with inexpensive analog signal switches results in the hitherto unattainable efficient use of the A-D converter. 
     So far because of integration density, the number of analog-digital converters which may be implemented together with a microcomputer on a single chip has been limited. According to the present invention, however, a single analog-digital converter implemented together with a microcomputer on one chip may virtually accomplish functions of a plurality A-D converters. Thus the present invention will advantageously meet difficulties of packing density in analog circuit integration.