Arithmetic logic unit bit-slice with internal distributed iterative control
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to an integrated circuit arithmetic logic unit and more particularly to an arithmetic logic unit bit-slice implemented on a single semiconductor substrate having logic control also implemented on that substrate for causing the performance of algorithms such as multiply and divide designed so that a plurality of bit-slices may be concatenated to provide any desired word size with appropriate built-in control for causing the performance of the above mentioned algorithms for the entire word. 
     2. Description of the Prior Art 
     In the digital computer art, it was common practice to provide a computer having a fixed word length arithmetic logic unit. That is, the work length might be 32 bits or 64 bits with the computer having the control hardware to cause the arithmetic logic unit to operate. The operations typically included a simple add and subtract and also included iterative sequence algorithms such as multiply and divide. The adders of the arithmetic logic units were provided with circuitry for carry or borrow. 
     As integrated circuitry became commonplace, arithmetic logic units having short word lengths, such as four bits became available. These units are known as bit-slices. These bit slices contained borrow or carry logic and could be concatenated, but logic for algorithms such as multiply, divide and cyclic redundancy character generation had to be provided by outside control. 
     Using Large Scale Integration (LSI) techniques, the arithmetic logic unit bit-slice disclosed herein was implemented. It is of a short word length (four bits in the preferred embodiment) and provided with carry logic, but more importantly is provided with circuitry for identification of the arithmetic logic unit bit-slice within a larger word and with control logic, reactive to the bit-slice position, that enables the performance of algorithms such as multiply, divide, and cyclic redundancy character generation. 
     BRIEF SUMMARY OF THE INVENTION 
     An integrated circuit arithmetic logic unit bit-slice is provided with A and B operand inputs, carry-in and carry-out connections, command inputs and other external functions. An arithmetic unit is connected to receive the A and B inputs and to provide an output resulting from the selected arithmetic operation performed on the A and B inputs together with the carry-in input. The operation of the arithmetic unit is dictated by control logic and the output of a Programmable Logic Array (PLA) for decoding external function inputs including command inputs. Also provided with each bit-slice is a circuit indicating, by digital signals, where the particular bit-slice is located within a given word, such indicating signal being utilized by the control logic. This indicia circuit provides three possible digital outputs with a single input; a program counter and a memory counter, each electrically connected to the output of the arithmetic unit and each having a connection for a counter carry-in from another bit-slice and a counter carry-out for connection to a higher order bit-slice. Also provided are an accumulator register and a multiplier/quotient register, both used in conjunction with the arithmetic unit for various operations. Each bit-slice has control logic for controlling operations and a PLA for decoding operations. The control logic and the PLA, together with the circuitry for indicating the position of the bit-slice within a word, enable the inclusion in the integrated circuit of a means for performing iterative sequencing such as that required in multiply, divide and cyclic redundancy character generation algorithms. 
     The principal object of this invention is to provide an ALU bit-scale implemented on a single semiconductor chip, with control logic included on that chip to enable the bit-slice to perform algorithms including such as multiply and divide alone or when concatenated with a plurality of bit-slices to form a larger word. 
     This and other objects will become more evident in the detailed description that follows. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an illustration, in logic diagram, of an arithmetic logic unit bit-slice. 
     FIG. 2 is a block diagram illustrating three arithmetic logic unit bit-slices connected in series to form an arithmetic logic unit three times the size of the individual bit-slice. 
     FIG. 3a schematically illustrates the source of three potentials for use with the circuit of 3b. 
     FIG. 3b schematically illustrates a conversion of a voltage level to a digital signal. 
     FIG. 4 shows the relative position of FIGS. 4a-4d which, compositely, schematically illustrate the arithmetic unit, the sum bus and the compare and test circuitry of FIG. 1. 
     FIG. 5a is a schematic diagram of the AC register of FIG. 1. 
     FIG. 5b is a schematic diagram of the shift logic of the AC register. 
     FIG. 6a is a schematic diagram of the MQ Register of FIG. 1. 
     FIG. 6b is a schematic diagram of the shift logic of the MQ Register. 
     FIG. 7 is a logic diagram of the control logic portion of control logic and PLA 100 of FIG. 1. 
     FIG. 8 is a chart representing a part of the PLA of FIG. 1. 
     FIG. 9 is a chart representing another part of the PLA of FIG. 1. 
     FIG. 10 is a flowchart illustrating the working of the cyclic redundancy character generation algorithm. 
     FIG. 11 is a flowchart illustrating the unsigned multiply algorithm 
     FIG. 12a-12b is a flowchart representing the unsigned divide algorithm. 
     FIG. 13 is a flowchart representing the signed multiply algorithm. 
     FIG. 14a-14b is a flowchart illustrating the signed divide algorithm. 
     FIG. 15 is a map of the multiply, divide, and CRC generation portion of the PLA of FIG. 1. 
     FIG. 16a-16b is a map of a general instruction portion of PLA of FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The arithmetic logic unit bit-slice 10 (known as Tl-74S481) of this invention is illustrated in FIG. 1. Inputs AI and BI are shown available at inputs 11 and 12 respectively. Latches 13 and 14 receive the AI and BI inputs respectively. These latches (flip-flops) are clocked by a clock that must be brought in from outside the bit-slice 10. An input terminal on bit-slice 10 (not shown) receives the clock signal (at the frequency selected by the user) and distributes that clock signal toselected components of bit-slice 10. Those components generally include flip-flops and registers. 
     Multiplexer 56 receives inputs from both of latches 13 and 14 and also has an input for forcing all 1&#39;s on the output of multiplexer 56. Multiplexer 58 receives inputs from both of latches 13 and 14 and also has an input for forcing all 1&#39;s on the output of multiplexer 58. Multiplexers 56 and 58, in this preferred embodiment, each provide a four bit digital word output and are both of conventional design which is not necessary to be described herein. The four bit signal A from multiplexer 56 and the four bit signal B from multiplexer 58 are sent directly or inverted by devices 43 and 45, respectively, and then sent, as A&#39; and B&#39; to the arithmetic unit 200. In addition to inputs A&#39; and B&#39;, arithmetic unit 200 has an input C IN. Therefore, a full addition of A&#39;+B&#39;+C IN will result in Σ+C OUT, the latter term representing the carry out. The arithmetic unit 200 also provides signals P (propagate) and G (generate) which are useful in carry look-ahead, an optional operation. The output signal Σ from AU 200 is applied to sum bus 41 which provides on its output signal Σ&#39; either directly or shifted one bit to the left or one bit to the right. The output signal Σ&#39; is applied to the inputs of memory address counter register 50, program counter register 54, accumulator 20 and multiplexer/quotient register 30 via line 49. Σ&#39; is also applied to the input of 3-state device 60 whose output is connected to terminal 12 to supply an output BO on that terminal. The 3-state device 60 is enabled an external function signal EN BO (enable B output). The 3-state device 60 is a well known circuit which, when not enabled, provides electrically an open circuit and when enabled applies either a binary &#34;1&#34; or a binary &#34;0&#34; . In this preferred embodiment, Schottky TTL logic is employed where +5 volts and ground are the reference voltages. An arbitrary selection of any voltage over +2.0 volts (usually approximately +3.0 volts) is designated a binary &#34;1&#34; . Any voltage under +0.8 volts (usually at approximately 0.2 volts) is designated a binary &#34;0&#34; . The output Σ&#39; of sum bus 41 is also applied to the input of the data out (DO) multiplexer 42 having external inputs &#34;SEL D01&#34; and &#34;SEL DO2&#34; (Select DO1 and Select DO2) to provide one of four possible data out (DO) outputs. Address out port multiplexer 44 has inputs from the output of memory address counter 50 and from program counter 54 with an outside enable signal &#34;SEL AO&#34; (Select AO) to provide address out (AO). Outputs from counters 50 and 54 are connected together to provide CCO which is the negated counter carry out from either counter, selectively. External function input MA INCR (memory address counter increment) is applied as another input to counter 50 as is CCI (counter carry in) which serves as another input, selectively, to counter 54 as well. Counter 54 has an external function input PC INCR (program counter increment) and has an output connected as an input of multiplexer 58. Input ACR on line 46 is an input for sum bus 41 as is input ACL on line 48 because the respective registers are separately selected. Input ACR is connected to the least significant bit of the accumulator 20 and ACL is connected to the most significant bit of accumulator 20. Input ACL of the Most Significant Digit (MSD) bit-slice is connected to input ACR of the Least Significant Digit (LSD) bit-slice for the various shift modes available. Input MQR is connected to the least significant bit of the multiplier/quotient register 30 and MQL is connected to the most significant bit. Input MQL of the MSD but-slice is connected to input ACR of the LSD bit-slice. An output of accumulator 20 serves as an input to data out multiplexer 42 as does an output from the multiplier quotient register 30. The output from accumulator 20 and also the output from register 30 each serve as inputs to multiplexer 58. Compare and Test 40 is physically a part of the arithmetic unit 200 in the preferred embodiment. The inputs A, S, A&#39; O , B&#39; O , MQ and AC provide signal EQ (when all of the bits in sim 41 are &#34;0&#34; or when all are &#34;1&#34;); OV (overflow); LG (logically greater than); AG (arithmetically greater than). Signals OV, LG and AG are developed in the most significant digit (MSD) bit-slice. In the least significant digit (LSD) bit-slice and in the middle digit(s) (MID) bit slice(s) they are respectively CCO (counter carry out); P (propagate); G (generate). 
     Control logic and PLA 100 has 10 command inputs C I , a position voltage input POS for developing a binary signal indicating the relative position in the word of the particular bit-slice and C IN which is a negated carry-in signal from a lower order stage. The output of logic 100 is C IN F (a forced negated carry-in signal); C I , C J  (alterable input command signals); S (24 control lines for controlling the operation of the arithmetic logic unit bit-slice 10). 
     FIG. 2 illustrates three arithmetic logic unit bit-slices concatenated to form a 12 bit word with bit-slice 10 representing the least significant digit, bit-slice 10&#39; illustrating a middle digit and bit slice 10&#34; illustrating the most significant digit. It should be pointed out that any number of middle digits could be added and illustrating three bit-slices is only for easy illustration. The negation of the counter carry out of bit-slice 10 is connected to the CCI of bit slice 10&#39; by way of connection 78 and CCO of bit-slice 10&#39; is connected to the CCI input of bit-slice 10&#39;. C OUT of bit slice 10 is connected to the C IN of bit-slice 10&#39; and C OUT of bit-slice 10&#39; is connected to C IN of bit-slice 10&#34;. These last connections are optional and represent a ripple carry connection. If desired, the signals P and G from the least significant digit and the middle digit can be connected via lines 74, 76, 84 and 86 to carry-look-ahead unit 89 which may be a TI-74S128 unit. 
     FIG. 3a shows resistors R1 and R2 of equal value, with one end of these connected together and the other end of resistor R1, terminal 62, being connected to +5.0 volts and the other end of resistor R2 being connected to ground, thereby developing a voltage of +2.5 volts at the POSITION terminal which is filtered by capacitor C1, connected to ground. 
     FIG. 3b illustrates a circuit for converting one of three possible voltage inputs (0 volts or ground +2.5 volts or +5.0 volts) applied to a single input 63 into a binary signal MSD (most significant digit), LSD (least significant digit) or MID (middle digit). Input terminal 63 is connected to the positive terminals of comparators 67 and 69 and to the negative terminals of comparators 68 and 71. A voltage divider is comprised of equal value resistors R3 and R5 and resistor R4 which is double the value of resistor R3 or R5. One end of resistor R3 is connected to +5.0 volts at terminal 64 and its other end is connected to one end of resistor R4 at terminal 65 at which +3.75 volts is developed and applied to the negative input of comparator 67 and to the positive input of comparator 68. One end of resistor R5 is connected to ground and the other end is connected to the other end of resistor R4 at terminal 66 at which +1.25 volts is developed and applied to the negative input of comparator 69 and to the positive input of comparator 71. 
     The output of comparator 67 on line 75 is signal MSD. The output of comparator 68 on line 77 serves as an input to AND circuit 83 whose other input on line 79 comes from comparator 69 and whose output on line 85 is signal LSD. Comparator 71 provides on line 81, output signal MID. 
     In operation, when a middle digit position is required, a ground potential is applied to POS in FIG. 1 which is shown as POSITION INPUT terminal 63 in FIG. 3b. This ground potential is applied to the positive input of comparator 67 whose negative input is connected to +3.75 volts, causing a &#34;0&#34; output on line 75. Ground is applied to the negative side of comparator 68 whose positive terminal is connected to +3.75 volts causing a &#34;1&#34; output on line 77, as one input of AND circuit 83. The ground potential is also applied to the positive terminal of comparator 69 whose negative terminal is connected to +1.25  volts causing a &#34;0&#34; output on line 79 which, when combined with the &#34;1&#34; input on line 77, the AND circuit 83 to provide an &#34;0&#34; output on line 85. This ground potential is also applied to the negative terminal of comparator 71 whose positive terminal is connected to 1.25 v thereby causing a &#34;1&#34; output on line 81, which is the MID signal, indicating that the bit-slice is a middle digit. 
     If the bit-slice is to be used as the most significant digit, +5 volts is applied to the POSITION INPUT terminal 63 which is applied to the positive terminal of comparator 67 whose negative terminal is connected to +3.75 volts, causing a &#34;1&#34; output on line 75 indicating an MSD position. The +5 volts is also applied to the negative input of comparator 68 whose positive input is connected to +3.75 volts, causing a &#34;0&#34; output on line 77. The +5 volts is also applied to the positive terminal of comparator 69 whose negative terminal is connected to +1.25 volts causing a &#34;1&#34; output on line 79. AND circuit 83, with a &#34;0&#34; input on line 77 and &#34;1&#34; input on line 79 provides a &#34;0&#34; output on line 85 indicating that it is not an LSD position. The +5.0 volts is also applied to the negative input of comparator 71 whose positive input is connected to 1.25 volts causing a &#34;0&#34; output on line 81 indicating that a MID position has not been selected. 
     Finally, when a least significant digit position is desired, a +2.5 volt potential is applied to POSITION INPUT terminal 63 of FIG. 3b, thereby applying that voltage to the positive terminal of comparator 67 whose negative terminal is connected to +3.75 volts thereby providing a &#34;0&#34; output on line 75 indicating that the bit-slice selected is not the most significant digit (MSD). The +2.5 volts is also applied to the negative terminal of comparator 68 whose positive terminal is connected to +3.75 causing a &#34;1&#34; output on line 77. The +2.5 volts is connected to the positive terminal of comparator 69 whose negative terminal is connected to +1.25 volts causing a &#34;1&#34; output on line 79. AND circuit 83 is thereby activated to provide a &#34;1&#34; output on line 85 indicating a least significant digit (LSD). The +2.5 volts is also applied to the negative input of comparator 71 whose positive input is connected to +1.25 volts, causing a &#34;0&#34; output on line 81 as the MID signal. 
     The above illustrates how a single voltage input applied to terminal 63 provides one of three possible digital outputs, namely, MSD, LSD or MID. 
     FIGS. 4a-4d interconnected as shown in FIG. 4 form a logic representation of the arithmetic unit 200, the compare and test 40 and the sum bus multiplexer 41 of FIG. 1. 
     The arithmetic unit&#39;s operation is controlled by S 8 , S 9 , and S 10 . The operations that are caused to be performed by these control signals and others are defined later. As an example, for an addition of A&#39; plus B&#39; plus C IN, S 8  =0, S 9  =0 and S 10  =0. Signal S 8  is an input to NOR gate 203 for providing an output signal P 0  and also is an input to three identical NOR gates which provide signals P 1  -P 3 , respectively. Signal S 9  is inverted through inverter 201 whose output is an input to AND gate 202 whose output, in turn, is the other input to NOR gate 203. 
     The signal S 9  out of inverter 201 is an input to three other AND circuits identical to AND circuit 202 whose outputs are the other inputs to the NOR circuits providing signals P 1  -P 3 , respectively. Signal A&#39; 0 , the highest order bit of AI input as shown in FIG. 1, is applied to AND gate 202 and to NOR gate 204 whose other input is signal B&#39; 0 , the highest order bit of input signal BI as shown in FIG. 1. The output of NOR circuit 204 provides signal G 0 . In identical fashion, signals A&#39; 1  -A&#39; 3  and B&#39; 1  -B&#39; 3  are applied to identical circuits which provide output signals G 1  -G 3 , respectively. Signals P 0  and G 0  are inputs to exclusive NOR circuit 206. In identical fashion, inputs P1, G1-P3, G3 are inputs to exclusive NOR circuits 207, 208 and 209, respectively. 
     Control signals S 10  is inverted through inverter 205 and is an input to NAND circuit 219. Signals C IN and C INF also are inputs to NAND circuit 219. Exclusive NOR circuit 209 has an output which is an input to exclusive NOR circuit 223 whose other input comes from NAND circuit 219. The output of exclusive NOR circuit 223 is signal Σ 3  which is the sum of the lowest order bits plus the carry-in. C INF is a signal developed internally and is a forced carry. For a normal addition, the carry-in signal C IN should be considered coming from a lower order digit. In such case, the signal from NOR circuit 223 is: 
     
         Σ.sub.3 =CIN·G.sub.3 ·P.sub.3 +CIN·G.sub.3 ·P.sub.3 +CIN.sub.3 ·G.sub.3 ·P.sub.3 +CIN·G.sub.3 ·P.sub.3 
    
     In terms of the input signals this equation can be expressed as: 
     
         Σ.sub.3 =A.sub.3 ·B.sub.3 ·CIN+A.sub.3 ·B.sub.3 ·CIN+A.sub.3 ·B.sub.3 ·CIN+A.sub.3 ·B.sub.3 ·CIN 
    
     Signals C INF and C IN are applied to AND gates 217, 214 and 210, each of which circuits are employed in an array to determine the C IN signal from the bit of lesser significance. The signal S 10  from inverter 205 is applied to AND gates 210-218. Signal G 3  is applied to AND gates 211, 215 and 218. Signal P 3  is applied to AND gates 210, 214 and 217. Signal G 2  is applied to AND gates 212 and 216, Signal P 2  is applied to AND gates 210, 211, 214 and 215. Signal G 1  is applied to AND gates 213. Signal P 1  is applied to AND gates 210, 211 and 219. AND circuits 210-213 all serve as inputs to NOR circuit 220 whose output is the signal C IN 1 , indicating the carry generated from the stage A 1  &#39;, B 1  &#39;. AND circuits 214-216 serve as inputs to NOR circuit 221 whose output is C IN 2 . In like manner, AND circuits 217 and 218 serve as inputs to NOR circuit 222 whose output is signal C IN.sub. 3. Signal C IN 3  from NOR circuit 222 and the output from exclusive NOR circuit 208 serve as the inputs to exclusive NOR circuit 222 whose output is Σ 2 . This signal is represented by: 
     
         Σ.sub.2 =CIN.sub.3 ·G.sub.2 ·P.sub.2 +CIN.sub.3 ·G.sub.2 ·P.sub.2 +CIN.sub.3 ·G.sub.2 ·P.sub.2 +CIN.sub.3 ·G.sub.2 ·P.sub.2 
    
     This equation can be expressed in terms of input signals A&#39; 2  and B&#39; 2 , but it becomes more complex and not necessary to describe this invention. 
     The signal C IN 2  from NOR circuit 215 and the output of exclusive NOR circuit 207 are inputs to exclusive NOR circuit 221 whose output is signal Σ 1 . The signal is represented by: 
     
         Σ.sub.1 =CIN.sub.2 ·G.sub.1 ·P.sub.1 +CIN.sub.2 ·G.sub.1 ·P.sub.1 +CIN.sub.2 ·G.sub.1 ·P.sub.1 +CIN.sub.2 ·G.sub.1 ·P.sub.1 
    
     Signal C IN 1  from NOR circuit 200 and the output of exclusive NOR circuit 206 on the inputs to exclusive NOR circuit whose output is Σ 0 , which signal is expressed as: 
     
         Σ.sub.0 =CIN.sub.1 ·G.sub.0 ·P.sub.0 +CIN.sub.1 ·G.sub.0 ·P.sub.0 +CIN.sub.1 ·G.sub.0 ·P.sub.0 +CIN.sub.1 ·G.sub.0 ·P.sub.0 
    
     C OUT is a negated carry out signal for the bit-slice and is developed from AND circuits 253-256 being the inputs to NOR circuit 277 whose output is an input to AND circuit 262 which is gated by S 10  which itself gates NOR circuit 263 whose other input is C IN. The outputs of AND circuit 262 and NOR circuit 263 are inputs for NOR circuit 264 whose output is C OUT. AND circuit 253 has a G 0  signal input; AND circuit 254 has P 0  and G 1  inputs. AND circuit 257 has as inputs signals P 0 , P 1  and G 2  ; AND circuit 255 has as inputs P 0 , P 1 , P 2 , P 3  ; AND circuit 256 has as inputs P 0 , P 1 , P 2 , P 3 , C IN and C INF. The resultant C OUT signal is the C IN signal for the next most significant bit-slice. 
     Next to be described is the sum bus 41 of FIG. 1, shown in detail in FIGS. 4b and 4d. Considering first the most significant bit Σ 0 , the output of exclusive NOR circuit 220, it can be seen that such signal is applied to AND circuits 275 and 281. Signals P 0  from NOR circuit 203 and signal C IN 1  from NOR circuit 220 are the inputs to AND circuit 269 whose output is an input to NOR circuit 270, the other input to NOR circuit being signal G 0  from NOR circuit 204. The output of NOR circuit 270 is an input to AND circuit 271 which has the signal MSD as another input and control signal S 21  as still another input. AND circuit 272 also has signal MSD as an input and the output from NOR circuit 277 serves as an input as does an output from right shift NOR circuit 226. Control signals S 20  ·S 21  perform still another input. AND circuit 273 has an input from ACL from the signal S 19  ·S 21  +MSD and also from the output of NOR circuit 226. AND circuit 274 has an input from line MQL, from signal S 19 , from signal MSD, from signal S 20  and from the output of NOR circuit 226. AND circuit 275 has a second input from the output of inverter 225 AND circuit 276 has an input from signal Σ 1  from the output of NOR circuit 221 and a left shift signal from the output of NOR circuit 224. 
     Note that AND circuits 271-274 are concerned with right shift while AND circuit 276 is concerned with the left shift and AND circuit 275 is concerned with a direct pass through of Σ 0 . The outputs of all of AND circuits 271-276 serve as inputs to NOR circuit 291 whose output is Σ&#39; 0 . 
     The control signals for left and right shift of the sum bus are S 11  and S 12 , and S 11  being the input to inverter 225 and S 12  being one input to NOR circuit 224 whose other input is the output from inverter 225. Inverter 225 also serves as an input to NOR circuit 226 whose other input is the output of the left shift circuit, NOR gate 224. Another control input to the sum bus is the combination S 19  or S 21  or LSD which serves as one input to left shift AND circuit 289 which has another input from line ACR and a left shift signal input from NOR circuit 224. PASS AND circuit 288 has an input from inverter 225 and Σ 3  from exclusive NOR circuit 223. Right shift AND circuit 287 has a right shift signal input from NOR circuit 226 and signal Σ 2  from exclusive NOR circuit 222. AND circuits 287-289 all serve as inputs to NOR circuit 295 whose output is signal Σ&#39; 3 . Left shift AND circuit 286 has a left shift signal input and input signal Σ 3 . PASS AND circuit 285 has a signal from inverter 225 and a signal Σ 2 . Right shift inverter 284 has a right shift signal input and a Σ 1  input. AND circuits 284-286 serve as inputs to NOR circuit 279 whose output is Σ&#39; 2 . Left shift AND circuit 283 has a left shift signal input and signal Σ 2 . PASS AND circuit 282 has a signal from the output of inverter 225 and also input Σ 1 . Finally, right shift AND circuit 281 has a right signal input and a Σ 0  input. AND circuits 281-283 serve as inputs to NOR circuit 278 whose output is Σ&#39; 1 . As is seen from this structure, the sum bus is capable of shifting by one bit either left or right and also is connected to other registers as will be evident in the description of operation to be described later. 
     Next to be described in detail is the compare and test logic 40 of FIG. 1. NOR circuit 233 has an LAS (left arithmetic shift) input. Control signals S 3  (A complement) and control signals S 7  (B complement) serve as inputs to inverters 230 and 231 respectively whose outputs are inputs to exclusive NOR circuit 232. The output of circuit 232 serves as an input to NOR circuit 233 whose third input is provided by control signal S 10 . The output of NOR circuit 233 serves as an input to inverter 236, AND circuit 260, NOR circuit 289 and AND circuit 240. AND circuit 260 has an input from NOR circuit 264 and signal MSD. AND circuit 259 has an input signal MSD and an input signal from open collector inverter 246 which is the EQ (equal) signal indicating that Σ 0  -Σ 3  are all &#34;1&#39;s&#34; or all &#34;0&#39;s&#34;. The outputs of AND circuits 259 and 260 are inputs to NOR circuits 265 which has a third input from AND circuit 258 whose inputs are signal P 0  - P 3  and signal MSD from inverter 243. NAND circuit 244 has signal MSD as an input from inverter 243 and signal S 10  with its output connected to the input of NAND circuit 266 whose other input comes from the output of NOR circuit 265. The output of NAND circuit 266 is inverted through inverter 267 and is output signal P/LG. NOR circuit 294 and AND circuit 240, in addition to their inputs from the outputs of NOR circuit 233, each have as inputs signals Σ 0  -Σ 3  and both of whose outputs are inputs to NOR circuits 245 which is an input to open collector inverter 246. The open collector wired-AND circuit is well known in the art and enables output connections to perform logic that otherwise would require additional circuits. The output of inverter 246 is one input to AND circuit 248. Signal MSD is another input and the output of inverter 236 is still another input to AND circuit 248. AND circuit 249 has as inputs, signal MSD, the output of inverter 235, and the output of inverter 236. AND circuit 292 has as inputs signal G 1 , P 0  and MSD. AND circuit 251 has as inputs signals P 0 , P 1 , G 2  and MSD. AND circuit 252 has as input signals P 0 , P 1 , P 2 , G 3  and MSD. AND circuits 247 and 252 and 292 are all inputs to NOR circuit 292 whose output is inverted through inverter 261 and serves as an input to NAND circuit 268. The output of NAND circuit 268 is output signal G/AG. 
     FIG. 5a illustrates detail of the accumulator 20 of FIG. 1. External function signal AC LOAD is inverted by inverter 21 and is an input to OR circuit 22 whose other input is command signal S 14 . The output of OR circuit 22 gates multiplexers 26-28 and one other identical multiplexer. Multiplexer 23 has as inputs signal ACR&#39; and signal AC 2 , controlled by command signal S 12 . The output shift signal from device 23 is an input to multiplexer 26 which is further controlled by control signal S 13  and has inputs AC 3 , Σ 3  and AI 3 . Multiplexer 26 has an output which provides an input to flip flop 29 which has an external clock input and whose output serves as the &#34;1&#34; input to shift multiplexer 24 whose &#34;R&#34; input is signal AC 1 . Flip flop 29, together with its associated circuitry shift multiplexer 23 and multiplexer 26 is identical, except for arrangement of inputs with stages of lesser significance each having the identical three components and providing output signals AC 2 , AC 1   and AC 0 , respectively. 
     FIG. 5b illustrates multiplexer 301 having input MQ 0 , (the most significant bit of the MQ register 30); AC 0  (the most significant bit of the AC register 20); Σ 0  (the most significant bit of the sum bus 41). The output of multiplexer 301 is connected to line ACL and to the input of multiplexer 302. 
     Multiplexer 302 also has &#34;0&#34; input; &#34;COUT&#34; input; MQL line input; AC 0  input and Σ 0  input. Multiplexer 302 provides output signal ACL&#39;. 
     Multiplexer 303 has inputs Σ 3  (least significant bit of the sum bus 41) and AC 3  (least significant bit of accumulator register 20, and provides an output on line ACR as an input to multiplexer 304. Multiplexer 304 also has a &#34;0&#34; input and provides output signal ACR&#39;. 
     All of multiplexers are controlled by control signals S 11 , S 12 , S 19 , S 20  and S 21 , depending upon the shift mode that is selected. 
     The ACR line from the LSD bit slice of the AC register 20 is externally connected to the ACL line of the MSD register. 
     The various combinations of the control signals S 11 , S 12 , S 19 , S 20  and S 21  and the resultant shift modes are set out later. 
     The stage providing AC 2  is identical to that providing AC 3  except that the inputs as described to multiplexer 24 are different and the inputs to multiplexer 27 are Al 2 , Σ&#39; 2 , the output of multiplexer 24 and AC 2 . The stage providing the output AC 1  is identical to that providing AC 2  except for the inputs to the shift multiplexer being from AC 0  and AC 2  and the inputs to the second multiplexer being AI 1 , Σ&#39; 1  and AC 1  in addition to the shift input. The lowest order stage providing AC 0  has as an input ACL&#39; to the &#34;R&#34; input and signal AC 1  to the L input of multiplexer 25 whose output, along with signal AC 0 , AI 0 , Σ&#39; 0  are inputs to multiplexer 28 whose output goes through a flip flop identical to flip flop 29 which has an output signal AC 0 . 
     FIG. 6 represents the multiplexer/quotient register 30 in detail. It is very much like the accumulator described above having four identical stages, differing only in the inputs. The stage providing MQ 3  which is the least significant bit has a multiplexer 31 controlled by control signal S 12  which controls identical input stages to the three remaining bits. Multiplexer 31 has for its &#34;L&#34; input signal MQR&#39; and for its &#34;R&#34; input signal MQ 2 . Its output goes to multiplexer 32 as an input, whose other inputs are Σ&#39; 3  and signal MQ 3 . Its output is controlled by control signals S 15  and S 16  which also serve to control the multiplexers of the three remaining bits. The output of multiplexer 32 serves as a D input to flip flop 33 whose Q output is signal MQ 3  and which serves as the &#34;L&#34; input to the next stage. The next stages are identical and at the most significant bit, which is that providing output signal MQ&#39; 0 , signal MQL&#39; is the &#34;R&#34; input signal and is the only difference from the preceding bits. 
     FIG. 7 illustrates the control logic portion of control logic and PLA 100 shown in FIG. 1. This control logic provides signals C I  and C J  as well as the forced carry in signal C INF. The circuitry will be described in detail and its operation will be described in connection with examples of the operation of the bit-slice that will follow. 
     Signals Σ&#39; 0  and AC 0  are inputs to exclusive NOR gate 101 which has an output to AND gate 102 which itself has another input, control signal S 23 . AC 0  input signal also is an input to AND circuit 103 whose other input is S 23 . The outputs of AND circuits 102 and 103 are inputs to OR circuit 106 which is one input to tristate device 108. Command control signals S 15  and S 16  are inputs to AND circuit 104 whose output is an input to OR circuit 107. Control signals S 10 , S 22  and S 23  are inputs to AND circuit 105 whose output is an input to OR circuit 107. The output of OR circuit 107 is the control for multiplexer 108. The output of multiplexer 108 is the D input to flip flop 109 which has an external clock input and whose output serves as a second input to multiplexer 108 and also as an input to open collector NAND circuit 110. The other inputs to NAND circuit 110 are signal MSD and control signals S 22  and S 24 . The output of NAND circuit 110 is the signal C I . 
     Signal AC 0  is an input to multiplexer 111 whose output is the D input to flip flop 112, having an external clock input and having an output which is the second input to multiplexer 111 and which also is an input to NOR circuit 113. The output of NOR circuit, together with control circuit S 10 , serves as input to AND circuit 114 which is an input to NOR circuit 115. AND circuit 125 has signal EQ as one input and the control signal S 19  as the other. The output of AND circuit 125 is the second input to OR circuit 115 which has an output serving as an input to open collector NAND circuit 116. The other inputs to NAND circuit 116 are signal MSD and control signals S 16 , S 22  and S 23 . The output of NAND circuit 116 is the signal C J . AND circuit 122 has EQ signal as one input, signal MSD as another input and control signals S 15 , S 22  and S 23  as the remaining inputs. Its output is the D input to flip flop 123 and also is an input to open collector inverter 124. The output of flip flop 123 is an input to open collector inverter 126 whose output and that of open collector inverter 124 also provides the C J  output. AND circuit 132 has as inputs the SIGN signal, the MQL line, and control signals S 20  and S 21 . NAND circuit 133 has as inputs control signals S 15  and S 16  and has an output which is an input to AND circuit 134. AND circuit 134 has an output to the input of OR circuit 135 whose other input comes from AND circuit 132. OR circuit 135 has an output which is the D input to flip flop 136 which has an external clock input and whose Q output is the second input to AND circuit 134. This second output is one input to exclusive OR circuit 137 whose other input is the MQL line. The output of exclusive OR circuit 137 is an input to open collector NAND circuit 138. The other inputs to NAND circuit 138 are signal MSD and control signals S 22  and S 23 . The output of NAND circuit 138 is C J . 
     AND circuit 140 has input signals A 0 , C J  and S 23 . AND circuit 141 has as inputs signals Σ 0 , C J  and S 23 . The outputs of AND circuits 140 and 141 are inputs to OR circuit 142 whose output is the D input of flip flop 143 which has an external clock input. The Q output of flip flop 143 is an input to OR circuit 144 whose second input is the C OUT signal from the arithmetic unit 200 described in FIG. 4. The output of OR circuit 144 is an input to open collector NAND circuit 145 whose other inputs are signals MSD and control signals S 22  and S 23 . The output of NAND circuit 145 is signal C J . Exclusive NOR circuit 117 has as inputs signals C I  from open collector NAND circuit 110 and C J  from open collector NAND circuits 116, 129, 138 and 145. The output of exclusive NOR circuit 117 is an input to AND circuit 119 whose other inputs are signals LSD and control signals S 5 , S 22  and S.sub. 23. AND circuit 118 has as inputs the signals LSD, C I , and control signals S 21  and S 22 . AND circuit 121 has, as inputs, signals LSD and C I  and control signals S 5 , S 22  and S 23 . AND circuits 118, 119, and 121 are inputs to OR circuit 120 providing the forced carry-in signal C INF. 
     Inverter 146 has an input signal C J  and its output provides inputs to 3-state devices 148 and 149 whose outputs are connected to lines MQL and ACR, respectively. AND circuit 147 has input signals MSD and S 23  and has an output which is the control for 3-state device 148. The control for 3-state device 149 is provided by AND circuit 130. 
     MODE OF OPERATION 
     FIG. 8 illustrates a portion of the PLA of control logic and PLA 100 of FIG. 1. FIG. 8 does not represent the actual map of the PLA but is shown to more readily describe the operation. The actual map of the repetitive algorithms, namely unsigned multiply, signed multiply, unsigned divide, signed divide and cyclical redundancy character generation is shown in FIG. 15. FIG. 9 illustrates the PLA for the signed divide algorithm. The command inputs C A  -C J  and the signal C IN are shown on the left of FIGS. 8 and 9. The control signals S 1  -S 24  are shown to the right. To understand the operation of the invention, the functions of the control signals S 1  -S 24  are set out as follows: 
     
         ______________________________________                                    
A MULTIPLEXER            S.sub.1                                          
                                S.sub.2                                   
One&#39;s  XFER to A             0      1                                     
AI     XFER to A             0      0                                     
BI     XFER to A             1      0                                     
AC     XFER to A             1      1                                     
A COMPLEMENT             S.sub.3                                          
A      XFER to A&#39;            0                                            
 ##STR1##                                                                 
        XFER to A&#39;            1                                           
B MULTIPLEXER            S.sub.4                                          
                                S.sub.5                                   
                                       S.sub.6                            
One&#39;s  XFER to B             0      0    0                                
PC     XFER to B             1      1    1                                
AC     XFER to B             0      1    1                                
MQ     XFER to B             0      1    1                                
BI     XFER to B             0      0    0                                
BI . PC                                                                   
       XFER to B             1      1    0                                
BI . AC                                                                   
       XFER to B             0      1    0                                
BI . MQ                                                                   
       XFER to B             1      0    0                                
B COMPLEMENT             S.sub.1                                          
B      XFER to B&#39;            0                                            
 ##STR2##                                                                 
        XFER to B&#39;            1                                           
ADDER                    S.sub.8                                          
                                S.sub.9                                   
                                       S.sub.10                           
A&#39; NOR B&#39;                0      1      1                                  
A&#39; OR B&#39;                 1      X      1                                  
A&#39; Θ B&#39;            0      0      1                                  
A&#39; + B&#39; + CIN, XFER to Σ                                            
                         0      0      0                                  
Σ SHIFT            S.sub.11                                         
                                S.sub.12                                  
PASS                     0      X                                         
LEFT                     1      0                                         
RIGHT                    1      1                                         
AC                       S.sub.13                                         
                                S.sub.14                                  
AC XFER to AC            0      1                                         
AI XFER to AC            0      1                                         
Σ&#39; XFER to AC      1      0                                         
AC SHIFT XFER to AC      1      1                                         
MQ                       S.sub.15                                         
                                S.sub.16                                  
MQ XFER to MQ            0      0                                         
NOT USED                 0      1                                         
Σ XFER TO MQ       1      0                                         
MQ SHIFT, XFER to MQ     1      1                                         
SHIFT CONTROLS                                                            
RIGHT/LEFT CONTROL       S.sub.12                                         
 SHIFT LEFT              0                                                
 SHIFT RIGHT             1                                                
SINGLE/DOUBLE LENGTH     S.sub.19                                         
 SINGLE LENGTH           0                                                
 DOUBLE LENGTH           1                                                
SHIFT MODE               S.sub.20                                         
                                S.sub.21                                  
 LOGICAL                 0      0                                         
 ARITHMETIC              0      1                                         
 ROTATE                  1      1                                         
 NOT USED                1      1                                         
CRC CONTROL              S.sub.24                                         
DISABLE AUTOMATIC CRC CONTROL                                             
                         0                                                
ENABLE AUTOMATIC CRC CONTROL                                              
                         1                                                
MULTIPLY/DIVIDE CONTROL  S.sub.22                                         
                                S.sub.23                                  
DISABLE AUTOMATIC CONTROL                                                 
                         0      0                                         
UNSIGNED DIVIDE          0      1                                         
UNSIGNED AND SIGNED MULTIPLY                                              
                         1      0                                         
SIGNED DIVIDE            1      1                                         
The operation of other controls shown in FIG. 1                           
is as follows:                                                            
 BI/O CONTROL                                                             
                          ##STR3##                                        
Σ&#39; XFER to BI/O    0                                                
BI/O OPEN                                                                 
                 PC          MA                                           
PC AND MA COUNTERS                                                        
                 PC INCR   S.sub.17                                       
                                 MA INCR S.sub.18                         
NOT USED         1         0     1       0                                
PC/MA XFER to PC/MA                                                       
                 X         1     X       1                                
COUNT            0         0     0       0                                
DO             SEL DO1   SEL DO2                                          
OPEN           1         1                                                
AC XFER to DO  0         1                                                
MQ XFER to DO  1         0                                                
Σ&#39; XFER to DO                                                       
               0         0                                                
AO             SEL AO                                                     
MA XFER to AO  0                                                          
PC XFER to AO  1                                                          
______________________________________                                    
 
    
     As an example of the operation, consider first the generation of the cyclical redundancy character as shown at lines 20 and 21 on FIG. 8. Generation of the cyclical redundancy character is done to check the accuracy of a string of data words usually in the form of eight bit words, known as bytes. The cyclical redundancy character is an arbitrary and satisfactory method of checking the accuracy of the message. 
     Consider the command input for the generation of the cyclical redundancy character (CRC). 
     
         ______________________________________                                    
 C.sub.A                                                                  
         C.sub.B                                                          
               C.sub.C                                                    
                     C.sub.D                                              
                         C.sub.E                                          
                             C.sub.F                                      
                                 C.sub.G                                  
                                     C.sub.H                              
                                         C.sub.I                          
                                             C.sub.J                      
                                                 ##STR4##                 
______________________________________                                    
1       1     1     1   0   0   0   0   0   1   1                         
______________________________________                                    
 
    
     The resultant control signals that equal 1 are S 3 , S 5 , S 6 , S 10 , S 12-16 , S 20  and S 24 . The other S control signals all equal 0. These control signals cause the arithmetic logic unit bit-slice to function in certain prescribed ways: 
     
         ______________________________________                                    
S.sub.1                                                                   
     S.sub.2                                                              
0    0             AI XFER to A                                           
S.sub.3                                                                   
1                  -A XFER to A                                           
S.sub.4                                                                   
     S.sub.5                                                              
            S.sub.6                                                       
0    1      1      AC XFER to B                                           
S.sub.7                                                                   
0                  B XFER to B&#39;                                           
S.sub.8                                                                   
     S.sub.9                                                              
            S.sub.10                                                      
0    0      1      A&#39; Θ B&#39; XFER to Σ                          
S.sub.11                                                                  
     S.sub.12                                                             
0    1             Σ XFER to Σ&#39;                               
S.sub.12                                                                  
1                  SHIFT RIGHT                                            
S.sub.13                                                                  
     S.sub.14                                                             
1    1             AC SHIFT XFER to AC                                    
S.sub.15                                                                  
     S.sub.16                                                             
1    1             MQ SHIFT XFER to MQ                                    
S.sub.17                                                                  
O                  PC XFER to PC                                          
S.sub.18                                                                  
0                  MA XFER to MA                                          
S.sub.19                                                                  
0                  SINGLE LENGTH SHIFT                                    
S.sub.20                                                                  
     S.sub.21                                                             
1    0             ROTATE SHIFT                                           
S.sub.22                                                                  
     S.sub.23                                                             
0    0             DISABLE MULTIPLY DIVIDE CONTROL                        
S.sub.24                                                                  
1                  ENABLE AUTOMATIC CRC CONTROL                           
______________________________________                                    
 
    
     In addition to FIG. 8, also please refer to FIG. 10 which is a flowchart indicating the operation of the CRC generation. The CRC generation algorithm is started at block 301 by the user placing the correct command inputs as illustrated above on the input lines of the bit-slice. Also, he must have a CRC polynomial as the A input (AI). This polynominal is a constant which specifies a particular type of check code. The CRC partial sum is carried in the accumulator 20. The particular data character is held in MQ and during this algorithm is transferred from the right half (the least significant half) to the left half of MQ merely for purposes of preserving the data character as its individual bits are examined. Proceeding to block 302, the least significant digit of registers MQ and ac are considered and specifically the least significant bit of each, that is, MQ 3  and AC 3  are exclusively ORed together to determine whether the result is =1. Note that the S control bits set out above call for AI (the polynomial) to go to A and for A to be inverted. Also, the shift is a rotating shift and of single length. Assume that the output of exclusive OR circuit 128 of FIG. 7=0. Then signal C J  remains a 1 and register AC rotates to the right. AND circuit 130 has as inputs, the binary signal LSD from FIG. 3B signifying the least significant digit, S 22  and S 24 . The least significant digit is selected by reason of the LSD signal, S 22  =0 from the original command input, and S 24  =1 from the original command input. Therefore, the output of AND circuit 130=1 and provides a gate for 3-state element 149 thereby gating in the output of inverter 146 into the ACR line. The output of inverter 146 is C J  =0 and therefore &#34;0&#34; is gated in on ACR which, as shown in FIG. 5a, supplies the signal ACR&#39; to the &#34;L&#34; input of the least significant bit AC 3  of the accumulator 20. 
     Referring back to FIG. 10, it can be seen that the operations of block 303 are thereby performed. Also, the operation of block 305, namely, that of rotating the contents of the register to the right is also performed. 
     The next pair of bits from register MQ and AC are exclusively ORed by exclusive OR gate 128 of FIG. 7. 
     As before, the output of AND circuit 130=1 and now the output of exclusive OR circuit 128 also=1. Therefore, the output open collector NAND gate 129, which is C J  then=0. When C J  =0, the resulting S control output signals from the PLA change. Specifically, S 11  =1 and S 14  =0. Then: 
     
         ______________________________________                                    
S.sub.11     S.sub.12                                                     
1            1                                                            
                         ##STR5##                                         
S.sub.13     S.sub.14                                                     
1            0          Σ&#39; XFER to AC                               
______________________________________                                    
 
    
     As indicated earlier, the original CRC command input resulted in output control signals which caused the exclusive ORing of AC and AI. The new control signals (as shown at line 20 of FIG. 8) also indicate that Σ shifted to the right is transferred to Σ&#39;. Also, a &#34;1&#34; is entered into the most significant bit of Σ&#39;. This is accomplished as shown in FIG. 7. With C J  =0, the output of inverter 146=1 and that output signal is gated through 3-state device 149 to the line ACR. It will be recalled that the line ACR is connected to the line ACL and therefore the &#34;1&#34; impressed on ACR from device 149, in a right shift mode, is entered on ACL as signal ALR&#39;. Σ&#39; now contains the shifted exclusive OR of the new partial sum and a &#34;1&#34; in the most significant bit position. Then this number is transferred into the accumulator 20 by reason of the new combination of control signals as indicated above. The operations performed are those indicated in block 304. The MQ right rotate of block 305 is again performed so that two bits of the original data character are in the most significant positions of MQ while six bits remain in the least significant positions. 
     The next pair of bits from MQ 3  and AC 3  may produce C J  =1 or C J  =0. The operations that follow are identical to those described above, depending upon the resultant state of C J . This operation is performed eight times (eight clocks) at the end of which the updated cyclic redundancy character will be totally within the accumulator 20 and the original data character in the multiplier/quotient register 30 will be shifted to the left half. In this manner, the data character is preserved. 
     A more familiar algorithm, perhaps, is the unsigned multiply. An explanation of its operation may also be helpful in understanding this invention. When the user designates an unsigned multiply, the following input command signals and resultant control signals are as follows: 
     UNSIGNED MULTIPLY 
     
         ______________________________________                                    
 C.sub.A                                                                  
     C.sub.B                                                              
           C.sub.C                                                        
                 C.sub.D                                                  
                     C.sub.E                                              
                         C.sub.F                                          
                             C.sub.G                                      
                                 C.sub.H                                  
                                     C.sub.I                              
                                         C.sub.J                          
                                             ##STR6##                     
1   1     1     1   0   0   1   0   0   1   1                             
S.sub.5, S.sub.6, S.sub.12 -S.sub.16, S.sub.19, S.sub.21, S.sub.22 = 1    
S.sub.1                                                                   
     S.sub.2       AI → A                                          
0    0                                                                    
S.sub.3                                                                   
0                  A → A&#39;                                          
S.sub.4                                                                   
     S.sub.5                                                              
            S.sub.6                                                       
                   AC → B                                          
0    1      1                                                             
S.sub.7                                                                   
0                  B → B&#39;                                          
S.sub.8                                                                   
     S.sub.9                                                              
            S.sub.10                                                      
0    0      0      A&#39; plus B&#39; plus CIN → Σ&#39;                  
 S.sub.11                                                                 
     S.sub.12                                                             
0    1             Σ pass → Σ&#39; and Shift Right         
S.sub.13                                                                  
     S.sub.14                                                             
1    1             AC SHIFT → AC                                   
S.sub.15                                                                  
     S.sub.16                                                             
1    1             MQ SHIFT → MQ                                   
S.sub.17                                                                  
     S.sub.18                                                             
0    0             PC AND MA COUNT                                        
S.sub.19                                                                  
1                  DOUBLE LENGTH SHIFT                                    
S.sub.20                                                                  
     S.sub.21                                                             
0    0             LOGICAL SHIFT                                          
S.sub.22                                                                  
     S.sub.23                                                             
1    0             UNSIGNED AND SIGNED MULTIPLY                           
S.sub.24                                                                  
1                  ENABLE CRC (SPECIFIES UNSIGNED                         
                    MULTIPLY WHEN S.sub.22, S.sub.23 = 1,0)               
______________________________________                                    
 
    
     Referring now to FIG. 11, the unsigned multiply is started with the requirement that the accumulator be loaded with zeros; the multiplier is in the multiplier/quotient register; the multiplicand is in the AI input. Starting at block 307, the unsigned multiply algorithm is initiated. At block 310 it is shown that a determination is made as to whether the least significant bit of the MQ register=1. For an understanding of how this determination is made, refer to FIGS. 5b and 6b. As indicated above, the shift to be made in this unsigned multiply algorithm is a double-length, right logical shift. In essence, a double length register is formed with the AC register being the upper half and the MQ register being the lower half. S 12  and S 19  =1, as shown above, for this shift. These control signals appropriately gate the multiplexers 301-308 to provide the required interconnection. ACR is always connected to ACL and MQR is always connected to MQL. For this particular shift, the control signals provide a hookup of line ACL into multiplexer 306 producing the output signal MQL&#39; which is then available as an input to the multiplier 37 of FIG. 6a. At the least significant end of the MQ register 30, output signal MQ 3  is available and is passed through multiplexer 307 down to line MQR which is connected to line MQL which is itself disabled for this particular shift. The least significant bit of the AC register 20 is shown having an output AC 3  in FIG. 5a which is passed by multiplexer 303 onto line ACR which is connected to line ACL in FIG. 5b. Line ACL, as indicated above is passed by multiplexer 306. Multiplexer 302 passes the input signal &#34;0&#34; as input signal ACL&#39; to multiplexer 25 shown in FIG. 5a. 
     Now, referring to FIG. 7, it can be seen that one input to exclusive OR circuit 137 is &#34;MQL&#34;. The other input from flip flop 136 is forced to a &#34;0&#34; in this particular algorithm. The input MQL carries the least significant bit value MQ 3  as described above. When combined in the exclusive OR circuit 137 with the &#34;0&#34; input from flip flop 136, the result is simply the value of the least significant bit being impressed on open collector NAND circuit 138. If the least significant bit=0, C J  remains a &#34;1&#34;. If the least significant bit=1, then C J  =0. 
     Referring back to FIG. 11, if the least significant bit of MQ does not equal 1, then the operations listed in block 309 take place. That is, the addition of AI+AC is made in AU 200 and the result goes into the sum bus 41. However, the result is not used in this case and the combination of the AC and MQ total double length register is right logical shifted one bit. These operations are dictated by the control bits set out above. 
     Now assume that the next least significant bit in MQ=1. Then C J  =0 and the operations in block 308 take place. When C J  =0, the output control signals are changed. That is, specifically, S 11  goes from 0 to 1 and S 14  goes from 1 to 0. When S 11  and S 12  are both 1&#39;s, the resultant function is: 
     ΣRIGHT, XFER TO Σ&#39;, AND SHIFT RIGHT 
     When S 13  =1 and S 14  =0, the function is: 
     Σ&#39; XFER TO AC 
     The contents of the accumulator 20 are added to the AI input in AU 200, with the sum going into sum bus 41. Keeping in mind that the sum bus 41 and the accumulator 20 have their input leads connected together the combination of the sum bus-MQ register is shifted one bit to the right, logical. In this manner, the shifted sum is entered into the AC register 20 and the shifted MQ 30 is entered into itself. This operation continues for the number of bits in the particular word. An example of this operation, with an 8-bit word, follows. The multiplicand in AI=52 (decimal) and the multiplier in MQ-212 (decimal). The following chart illustrates the changes in the accumulator 20 and the MQ register 30 as the multiplication process takes place: 
     MULTIPLY EXAMPLE 
     
         __________________________________________________________________________
AC              MQ                                                        
__________________________________________________________________________
0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 Setup                                   
0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 Shift                                   
0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 2 Shift                                   
0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 3 Add,Load                                
0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 4 Shift                                   
0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 5 Add,Load                                
0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 6 Shift                                   
0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 7 Add,Load                                
0 0 1 0 1 0 1 1 0 0 0 1 0 0 0 0 8 Add,Load                                
__________________________________________________________________________
 
    
     The resultant binary number in register AC-MQ=25,420 (octal) or 11,024 (decimal). 
     For the above two examples, it can be seen that the user need place only one set of command input bits into the arithmetic logic unit to achieve the generation of a cyclical redundancy character, or to multiply two numbers without regard to the signs of the numbers. In this particular embodiment, the remaining algorithms are the signed multiply, the unsigned divide and the signed divide. 
     In the case of the signed multiply, the following command input is given: 
     
         ______________________________________                                    
 C.sub.A                                                                  
         C.sub.B                                                          
               C.sub.C                                                    
                     C.sub.D                                              
                         C.sub.E                                          
                             C.sub.F                                      
                                 C.sub.G                                  
                                     C.sub.H                              
                                         C.sub.I                          
                                             C.sub.J                      
                                                 ##STR7##                 
______________________________________                                    
1       1     1     1   0   1   1   1   1   1   1                         
______________________________________                                    
 
    
     That is the only input with which the user need concern himself. With that particular configuration of command input signals, the control signals as shown at line 7 of FIG. 8 are generated. Please note that in this algorithm, not only does C J  change, but also C IN and C I . The flowchart of FIG. 13 illustrates the operation of this algorithm. By referring to the logic of FIG. 8 for those items shown in the diamond-shaped blocks 339, 342, 345, 347 and 348, and to the functions dictated by the control signals shown in FIG. 8 in conjunction with the operational blocks shown in FIG. 1, the algorithm can be understood in detail in the same fashion as illustrated above. 
     An example of an eight bit signed multiply, with 52 (decimal) in AI as multiplicand, and -44 (decimal) in the MQ register as multiplier, follows: 
     
         __________________________________________________________________________
AC              MQ                                                        
__________________________________________________________________________
0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 Setup                                   
0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 Shift AC,MQ                             
0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 2 Shift AC,MQ                             
1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 3 Sub,Load AC                             
1 1 0 1 1 0 0 1 0 0 0 0 1 1 0 1 4 Sub,Load AC                             
1 1 1 0 1 1 0 0 1 0 0 0 0 1 1 0 5 Shift AC,MQ                             
1 1 0 1 1 1 0 0 0 1 0 0 0 0 1 1 6 Sub,Load AC                             
1 1 1 0 1 1 1 0 0 0 1 0 0 0 0 1 7 Shift AC,MQ                             
1 1 1 1 0 1 1 1 0 0 0 1 0 0 0 0 8 Shift AC,MQ                             
__________________________________________________________________________
 
    
     The binary result (two&#39;s complement)=-2288 (decimal) 
     In the case of unsigned divide, the user must sequentially apply three input commands as shown: 
     
         __________________________________________________________________________
Command Input                                                             
 C.sub.A                                                                  
   C.sub.B                                                                
     C.sub.C                                                              
       C.sub.D                                                            
         C.sub.E                                                          
           C.sub.F                                                        
             C.sub.G                                                      
               C.sub.H                                                    
                 C.sub.I                                                  
                   C.sub.J                                                
                     ##STR8##                                             
__________________________________________________________________________
1 1 1 1 0 0 0 0 1 1 0                                                     
Unsigned Divide Start                                                     
                        (1 clock)                                         
1 1 1 1 0 0 0 1 1 1 0                                                     
Unsigned Divide Iterate                                                   
                        (n-1 clocks)*                                     
1 1 1 1 0 0 0 1 0 1 0                                                     
Unsigned Divide Finish                                                    
                        (1 clock)                                         
__________________________________________________________________________
 *n = word length in bits                                                 
 
    
     With reference to FIG. 8, the unsigned divide start is shown at line 11, unsigned divide iterate is shown at lines 14 and 13, and the unsigned divide finish, depending upon the results of the unsigned divide iterate, is at lines 16 or 17. An example of unsigned divide, with a divisor of 55 (decimal) in the AI input and a dividend of 1449 (decimal) in AC-MQ, follows: 
     
         __________________________________________________________________________
AC              MQ                                                        
__________________________________________________________________________
0 0 0 0 0 1 0 1 1 0 1 0 1 0 0 1 0 Unsigned Div. Start                     
0 0 0 0 1 0 1 1 0 1 0 1 0 0 1 X 1 Unsigned Div. Operate                   
0 0 0 1 0 1 1 0 1 0 1 0 0 1 X 0 2 Unsigned Div. Operate                   
0 0 1 0 1 1 0 1 0 1 0 0 1 X 0 0 3 Unsigned Div. Operate                   
0 1 0 1 1 0 1 0 1 0 0 1 X 0 0 0 4 Unsigned Div. Operate                   
0 1 0 0 0 1 1 1 0 0 1 X 0 0 0 1 5 Unsigned Div. Operate                   
0 0 1 0 0 0 0 0 0 1 X 0 0 0 1 1 6 Unsigned Div. Operate                   
0 1 0 0 0 0 0 0 1 X 0 0 0 1 1 0 7 Unsigned Div. Operate                   
0 0 0 1 0 0 1 1 X 0 0 0 1 1 0 1 8 Unsigned Div. Finish                    
0 0 0 1 0 0 1 1 0 0 0 1 1 0 1 0 9 Result                                  
__________________________________________________________________________
 X = Don&#39;t Care                                                           
 
    
     The quotient of 26 (decimal) is in the MQ register and the remainder 19 is in the AC register. 
     The signed divide algorithm is quite complex and as a result requires the user to sequentially impress five command inputs to the arithmetic logic unit as shown below: 
     
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Command Input                                                             
 C.sub.A                                                                  
   C.sub.B                                                                
     C.sub.C                                                              
       C.sub.D                                                            
         C.sub.E                                                          
           C.sub.F                                                        
             C.sub.G                                                      
               C.sub.H                                                    
                 C.sub.I                                                  
                   C.sub.J                                                
                     ##STR9##                                             
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1 1 1 1 0 0 1 0 1 1 1                                                     
Signed Divide Start (1 Clock)                                             
1 1 1 1 0 1 0 1 1 1 1                                                     
Signed Divide Iterate (n-1 clocks)*                                       
1 1 1 1 0 1 1 0 1 1 1                                                     
Signed Divide Finish (1 clock)                                            
1 1 1 1 0 1 0 0 1 1 1                                                     
Signed Divide Fix Remainder (1 clock)                                     
1 1 1 1 0 0 1 1 1 1 1                                                     
Signed Divide Adjust Quotient (1 clock)                                   
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 *n = word length in bits                                                 
 
    
     FIG. 9 illustrates the various control bits activated by the signed divide algorithm. At line 1, the control signals for &#34;Signed Divide Start&#34; are shown. At line 6, the control signals for &#34;Signed Divide Iterate&#34; are shown with changed control signals resulting from changes in state of signals C J  and C IN. The control signals for &#34;Signed Divide Finish&#34; are shown in lines 7-10, depending upon the results of the &#34;Signed Divide Iterate&#34;. Control signals for &#34;Signed Divide Fix Remainder&#34; are shown in lines 11-14, depending upon the previous results. The control signals for &#34;Signed Divide Adjust Quotient&#34; are shown in lines 15-18, again dependent upon the previous results. 
     Reference to FIG. 9 and to FIGS. 14a and 14b teaches the actual operation of this algorithm in detail as has been described for the CRC generation and unsigned multiply above. 
     An example of a signed divide, with a divisor of -121 (decimal) in the AI input and a dividend of 3855 (decimal) in the AC-MQ register follows: 
     
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AC              MQ                                                        
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0 0  0                                                                    
      0 1 1 1 1 0 0 0 0 1 1 1 1 S                                         
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X I                                         
0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 I                                         
0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 0 I                                         
1 1 1 1 0 0 0 0 1 1 1 1 X 0 0 0 I                                         
1 1 1 0 1 1 1 1 1 1 1 X 0 0 0 1 I                                         
1 1 1 0 1 1 0 1 1 1 X 0 0 0 1 1 I                                         
1 1 1 0 1 0 0 1 1 X 0 0 0 1 1 1 I                                         
1 1 1 0 0 0 0 1 X 0 0 0 1 1 1 1 F                                         
0 1 1 0 1 0 0 0 0 0 0 1 1 1 1 1 FR                                        
0 1 1 0 1 0 0 0 0 0 0 1 1 1 1 1 AQ                                        
0 1 1 0 1 0 0 0 1 1 1 0 0 0 0 1 Result                                    
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     The quotient of -31 (decimal) is found in register MQ and the remainder of 104 is found in register AC. 
     As stated earlier, FIGS. 8 and 9 are graphic representations of the contents of the PLA of FIG. 1. The illustrations are in expanded form for clarity. The actual map of FIGS. 8 and 9, by way of a minterm process is shown in FIG. 15. 
     The general instructions of the arithmetic logic unit of this invention are mapped in the decode PLA as shown in FIGS. 16a and 16b. 
     Those skilled in the art are aware that the details of this invention are flexible, that various types of logic may be employed, various types of PLA&#39;s and certainly various types of algorithms may be used without departing from the scope of this invention.