Tri-state signal conditioning method and circuit
BACKGROUND OF THE INVENTION 
     There are several techniques for the testing of digital circuits based on compressing bit streams. These include, for example, apparatus for counting the number of logic state transitions of, and apparatus for analyzing the signature of, an unknown logic signal, each during a selected period of time. Logic state transition counting and the associated apparatus is well known in the art and signature analysis is fully described in U.S. Pat. No. 3,976,864 issued on Aug. 24, 1976, to Gary Gordon, et al, and now assigned to the same assignee as the present invention. 
     With many logic circuits, there is the possibility that the output signal will assume a third state. For example, TTL gates have a high state and a low state which are defined by the voltage level of the signal, i.e., typically 2.0 volts and above is a high state and 0.8 volts and below is a low state. The third state occurs when the gate output line is floating or is in a high impedance state, i.e., when neither of the output transistors of the signal generating gate are conducting. If the third state is encountered by the prior art test instruments, it is unpredictable whether the third state will be identified as a high or a low state. Additionally, repeatability of identification of this state as a high or a low state cannot be ensured, i.e., a valid bit stream cannot be characterized by a unique signature if third state data is present. 
     When the gate output line at the point of measurement is not clamped to either of the high or low state levels (output line is floating), attempts were made in the prior art to make the logical signature unique by pulling the point of measurement to the high state through a resistor connected to Vcc. Thus, the output signal could vary from the low state level to the high state level through the intermediate region at a rate which is determined by the RC time constant, where R is the value of the pull-up resistor and C is the value of the stray capacitance to ground of the gate output line where the signal measurement is being made. If transition counting is being used, the transition may be multiply detected if the charging time constant is sufficiently long so that system noise causes the high-low state threshold to be multiply traversed. With a position-sensitive bit stream characterizing system, such as signature analysis, the resulting signature will then vary undesirably. 
     To obtain an accurate measure of a logical signal, some means is therefore required to eliminate the effect of the floating gate output, and to identify the third state repeatably and uniquely as either the high or as the low state, or to determine when each state transition has occurred. 
     SUMMARY OF THE INVENTION 
     In accordance with the illustrated embodiment, the present invention provides a method and apparatus for generating a repeatable binary signal from a tri-state signal. 
     To provide for a repeatable identification of the tri-state signal when the gate output is in the third state, (i.e., the high impedance state) the signal is initially conditioned so that it repeatedly achieves a signal level intermediate the threshold levels that define the high and low states. The conditioned tri-state signal in these time intervals crosses only one of the high and low state signal threshold levels as the stray capacitance of the gate charges or discharges, i.e., the steady state signal level to which the stray capacitance charges (discharges) is intermediate the high and low state signal threshold levels. This conditioning can be performed by coupling the signal input line of the present invention to a selected voltage that is intermediate the first and second threshold voltage levels through a selected value resistor. 
     To generate a binary signal, the initially conditioned tri-state signal is sampled at the clock rate of the original tri-state signal and in any interval wherein the signal has a level intermediate the high and low state threshold levels, the signal is defined to be in the same state as the last previous one of the high and low states of the signal. This is accomplished by the illustrated preferred embodiments in one case by first sampling the conditioned tri-state signal at the clock rate of the tri-state signal by means of a transmission gate followed by a hysteresis amplifier wherein the two threshold levels are selected to correspond to the high and low threshold signal levels of the tri-state signal under test. Thus, the output signal of the hysteresis amplifier will be a binary signal wherein each third state has been identified as above, and each high and low state of the tri-state signal is, correspondingly converted to a high and low state, respectively. The other illustrated embodiments of the present invention combine the sampling and hysteresis functions in a state machine to achieve the same result. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1a shows a portion of a typical logic signal as conditioned by the prior art. 
     FIG. 1b shows the logic waveform of FIG. 1a with the intervals resulting from the high impedance state of the generating gate initially conditioned instead by the preferred embodiment of the present invention. 
     FIG. 1c shows the clock pulse train and its temporal alignment with the logic waveforms of FIGS. 1a, b and c. 
     FIG. 1d shows the logic waveform of FIG. 1a following complete conditioning by the preferred embodiment of the present invention. 
     FIGS. 2a and 2b each show a simplified block diagram of a preferred embodiment of the present invention. 
     FIG. 3 shows another preferred embodiment of a logical third state conditioning circuit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In FIG. 1a there is shown a portion of a typical logic signal waveform 10. This waveform includes a high state region 12 and a low state region 14. High state region 12 is defined as that portion of the signal that assumes a voltage level equal to or greater than the high state threshold voltage level, V H , and low state region 14 is defined as that portion of the signal having a voltage level equal to or less than the low state threshold voltage level, V L . State transition ringing pulses 18 are also shown, and it is not unusual for these noise pulses to overshoot and extend between and into the high and low logic state voltage levels, as shown in intervals t1 and t2. Additionally, an unclamped gate output portion 20 of the signal is shown in intervals t3, t4 and t5. This unclamped portion 20 of the signal is shown varying from the low state to the high state which occurs when the output of a gate is not clamped to either of the high state or the low state voltage levels, and a pull-up resistor is connected between the output terminal of the gate and V cc . The time constant with which the unclamped portion 20 of the signal varies is dependent upon the value of the stray capacitance of the gate and the resistance of its charging path. 
     FIG. 1b shows a logic signal waveform 10&#39;, and FIG. 1c the corresponding clock waveform 22 of the circuit that generated waveform 10&#39;. Waveform 10&#39; is the same as waveform 10 in FIG. 1a with the unclamped portion 20&#39; shown charging toward a voltage level, V M , which is intermediate the voltage threshold levels V H  and V L . This change results from the first step of the signal conditioning of the present invention described below. 
     FIG. 1d shows logic signal 16 which is the completely conditioned logic signal output of the present invention. It can also be seen that the transitions of conditioned signal 16 are in alignment with the trailing edges of the individual pulses of the clock pulse train 22. Thus, the final logic signal is delayed from the original signal 10 by approximately one full time interval. 
     FIGS. 2a and 2b illustrate an analog and a digital circuit, respectively, of the present invention in simplified block diagram form. In each of these figures, and in FIG. 3, there is shown a resistor 24 connected between a voltage source V X  and the input line of the overall circuit for receiving the pulse train of interest (10, FIG. 1a) from the circuit under test. The value of voltage source V X  is selected so that V X  =(V H  +V L )/2 (e.g. V X  =1.4 v for testing TTL gates). Resistor 24 is selected so that the high and low state voltage levels of waveform 10&#39; (FIG. 1b) do not fall below or rise above thresholds V H  and V L , respectively, when the output of the circuit under test is in one of the clamped modes (FIG. 1b intervals t1 and t2 i.e. those portions of waveform 10&#39; in intervals t 1  to t 2  other than ringing pulses 18), and so that the stray capacitance of the circuit under test does not charge from leakage currents to a voltage level that is greater than V L  or less than V H  when the output of the circuit under test is in the unclamped mode (e.g., in TTL circuits R 24  ≃50 K Ω, V X  =1.4 v, V M  =1.4 v, V H  =2.0 v, V L  =0.8 v). Thus, resistor 24 and the V X  voltage level limit the maximum extent of the unclamped gate output portion 20&#39; (FIG. 1b) of the waveform of interest (10&#39;) to the region between V L  and V H . It should be mentioned that a current source could be used instead of R24 to achieve the function R24 performs. 
     The remainder of the circuit illustrated in FIG. 2a comprises a transmission gate 26 (e.g., a field effect transistor) with its input connected to receive the pulse train of interest (10&#39;) from resistor 24, and its gate connected to receive the clock pulses (22) from the circuit under test. The output signal from transmission gate 26 is then a clocked, preconditioned, tri-state signal. This tri-state signal is then applied to a hysteresis amplifier 28 (e.g., an operational amplifier with positive feedback) which generates a two-state output signal wherein a state transition does not occur until the clocked, preconditioned, tri-state signal crosses both hysteresis thresholds in either direction, i.e., when the input signal level is V M , the hysteresis amplifier 28 continues to output the last previous clamped state until the second threshold is also crossed. Thus, by preconditioning the unclamped portions 20 (FIG. 1 intervals t3, t4 and t5) of the input waveform with resistor 24 and voltage source V X , by gating the input signal with the clock pulse 22 of the circuit under test, and by using a hysteresis amplifier 28, the unpredictable effects of the unclamped output (20) of the circuit under test, and the transition ringing (18) are eliminated, and a predictable and repeatable two-state signal is generated making effective and accurate transition counting or signature analysis possible. 
     In addition to resistor 24 and voltage source V X , FIG. 2b also includes a pair of comparators 30 and 32 (e.g., LM710&#39;S) each coupled to receive on one input terminal the preconditioned waveform from resistor 24. The second input terminal of comparators 30 and 32 are coupled to voltage sources having output voltage values of V H  and V L , respectively, for producing an output signal in the high state when the preconditioned input signal (10&#39;) voltage level exceeds the respective threshold level (V H  or V L ) and a low state otherwise. The output signals from comparators 30 and 32 are next applied to a memory 34 (e.g., a flip-flop) for storing the last previous valid (clamped) state of the input signal (10&#39;) in response to the applied clock pulse from the circuit under test. Next, the output signals of comparators 30 and 32 and single bit memory 34 are applied to a combinatorial logic circuit 36 which is designed to produce a logical output signal in accordance with the Table I. 
     
                       TABLE I                                                     
______________________________________                                    
Input     Comp 30  Comp 32   Memory 34                                    
                                      Output                              
State     Output   Output    Output   from 36                             
______________________________________                                    
L         L        L         L        L                                   
L         L        L         H        L                                   
3d        L        H         L        L                                   
3d        L        H         H        H                                   
(impossible)                                                              
          H        L         L        --                                  
(impossible)                                                              
          H        L         H        --                                  
H         H        H         L        H                                   
H         H        H         H        H                                   
______________________________________                                    
 
    
     One digital logic circuit embodiment of the present invention is shown in FIG. 3. This embodiment includes resistor 24 and comparators 30 and 32 connected and operative as described in relation to FIG. 2b. The circuit also includes a J-K Flip-Flop 38 with the output of comparator 30 coupled to the J terminal and the output of comparator 32 coupled to the K terminal through an inverter 40. Also coupled to the J-K Flip-Flop 38 at its clock input terminal is the clock pulse train (22, FIG. 1c) from the circuit under test. The Q output signal of J-K Flip-Flop 38 represents the output signal of the conditioning circuit. Table II illustrates the operation of this circuit. 
     
                       TABLE II                                                    
______________________________________                                    
         Comp          Comp                                               
Input    30            32         Previous Next                           
                                            Out-                          
State    Output  (J)   Output                                             
                             (K)  Q38    Q38  put                         
______________________________________                                    
L        L       L     L     H    L      L    L                           
L        L       L     L     H    H      L    L                           
3d       L       L     H     L    L      L    L                           
3d       L       L     H     L    H      H    H                           
(impossible)                                                              
         H       H     L     H    L      --   --                          
(impossible)                                                              
         H       H     L     H    H      --   --                          
H        H       H     H     L    L      H    H                           
H        H       H     H     L    H      H    H                           
______________________________________