Method and apparatus for suppression of error accumulation in recursive computation of a discrete Fourier transform
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to the calculation of a discrete Fourier transform of a periodically sampled signal. The invention may be utilized in many fields, such as in a frequency domain equalizer for information transmission channels. 
     2. Description of the Prior Art 
     Most prior art computations of a discrete Fourier transform require that all signal samples be available. In such systems, computations must be delayed until the signal of interest has been completely received. There is disclosed in the literature, however, a recursive computation of the discrete Fourier transform using the concepts of &#34;moving window sampling&#34; which need not wait until the end of data transmission prior to commencing the calculations. See, for example, George M. Dillard, &#34;Recursivve Computation of the Discrete Fourier Transform with Applications to a Pulse-Doppler Radar System,&#34; Computers and Electrical Engineering, Vol. 1, pp 143-152, Pergamon, Oxford, 1973 and &#34;Recursive Computation of the Discrete Fourier Transform with Applications to an FSK Communication Receiver&#34;, 1974 National Telemetering Conference Record, pp 263-265. 
     Situations occur in modern technological environments where it is desireable to perform recursive computations on various signals or functions. One such situation is in automatic equalization of transmission channels. When the equalization is carried out in the frequency domain, recursive computation of the discrete Fourier transform provides advantages, such as savings in time and minimization of hardware. Equalization of transmission channels in the prior art is generally conducted, however, in the time domain. The use of frequency domain equalization is not widespread, partly because of the common perception that the initialization of the equalization process must be delayed to allow for the reception of a complete characterization of the signal which is to be equalized. Moreover, prior attempts at applying recursive computations of the discrete Fourier transform to frequency domain equalizers have suffered from a tendency for errors to buildup, a problem common to recursive procedures. If errors occur in early computations, the use of the calculated coefficients in subsequent computations typically leads to amplification of the errors. Such error accumulation and amplification is likely to lead to intolerably erroneous results. 
     SUMMARY OF THE INVENTION 
     This invention overcomes the major disadvantages of using moving window sampling to recursively compute the discrete Fourier transform of an input signal for, say, equalization purposes. 
     It is, therefore, a primary object of the invention to provide a method for accurate computation of the discrete Fourier transform of a signal, while avoiding the problems associated with the prior art. 
     An additional object of the invention is to generally limit error accumulation in a recursive computation. 
     Yet another object of the invention is to provide apparatus for carrying out a recursive computation of the discrete Fourier transform of a signal. 
     It is a further object of the invention to provide means for limiting the accumulation of errors in an apparatus recursively calculating the discrete Fourier transform of a signal. 
     Yet another object of the invention is to provide an apparatus for recursively calculating, with limited recursive calculation error, the discrete Fourier transform of a sampled signal utilizing a moving window sampling approach. 
     The present invention overcomes the disadvantages of the prior art and achieves the foregoing objectives by providing one or more periodically reinitialized channels for recursively calculating, with limited recursive calculation errors, the discrete Fourier transform of an input signal in response to moving window sample sets of that signal. A single channel is sufficient to generate an error limited discontinuous transform, but a plurality of channels are needed if an error limited continuous transform is desired due to the finite amount of time a reinitialized channel requires to recalculate a complete set of the dependent variables which enter into the recursive calculations. 
     One embodiment of this invention generates an error limited continuous discrete Fourier transform of the input signal through the use of duplicate channels which are periodically reinitialized in time shaggered relationship and cyclically connected to and disconnected from the output, one after the other, in timed synchronism with the reinitialization timing. Each of the channels is equipped to recursively calculate the discrete Fourier transform of the input signal in response to moving window sample sets of that signal so that while one channel is on-line feeding transform coefficients to the output, the other channel or channels are off-line being reinitialized and computing fresh transform coefficients. Another embodiment performs essentially the same function by having a main processing channel which remains on-line to feed recursively recalculated transform coefficients to the output on the basis of successive sets of dependent variables which are recursively calculated in and supplied as calculated by a periodically reinitialized off-line auxiliary processing channel. Recursive computation errors are limited in both embodiments by periodically reinitializing the channel or channels which furnish the dependent variables which enter into the recursive calculations of the discrete Fourier transform coefficients. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and features of the invention will become apparent when the following detailed description is read in conjunction with the attached drawings, in which: 
     FIGS. 1-3 are block diagrams of systems for solving a general recursive equation; 
     FIG. 4 is a simplification of FIG. 1 for a special form of recursive equation; 
     FIGS. 5 and 6 illustrate a first embodiment of the invention for limiting the accumulation of error in the recursive calculation of a discrete Fourier transform; 
     FIG. 7, which is composed of FIGS. 7A and b, is a timing chart for the switches shown in FIGS. 5 and 6; 
     FIGS. 8 and 9 show a modification of the invention, providing an alternate means for limiting error accumulation; 
     FIG. 10 is a timing diagram for the switches shown in FIGS. 8 and 9; 
     FIG. 11 illustrates a simplified embodiment of the invention as illustrated in FIGS. 8 and 9; 
     FIG. 12 illustrates another embodiment of the invention; 
     FIG. 13 is a timing diagram for the embodiment of FIG. 12; and 
     FIGS. 14 and 15 show further modifications to the embodiment of FIG. 12. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     While the invention is described hereinafter in some detail with reference to certain illustrated embodiments, it is to be understood that there is no desire to limit it to those embodiments. On the contrary, the intent is to cover all modifications, alternatives, and equivalents falling within the spirit and scope of the invention as defined by the appended claims. 
     FIG. 1 illustrates a system for solving a typical recursive function, such as that described by the equation, 
     
         Z.sub.k, n+1 =p.sub.k [{g.sub.r (Z.sub.r,n)}, {h.sub.i (f.sub.i,n)}](1) 
    
     where 
     r=0, 1, . . . N-1 
     i=0, 1, . . . N; and 
     k=0, 1, . . . N-1 
     Equation (1) describes a particular output Z k , n+1 as a function p k  of two arguments requiring further computations. Specifically, computation involving Z r ,n (where r is an index; 0≦r≦N-1) and a time sampled input function f i ,n. The second subscript, n, used in identifying the symbols relates to the &#34;window&#34; or &#34;frame&#34; in which the first subscript ranges. Thus, where a sampled time function f(t) is observed in specified time &#34;frames&#34;, and where N samples are observed during each frame, the i th  sample in time frame n is denoted by f i ,n. In the broadest sense, Z k , n+1 is a function of the sets of functions denoted by g r  (Z r ,n) and h i  (f i ,n). A different function g r  operates on each argument Z r ,n. Similarly, a different function h i  operates on each of the time samples f i ,n. 
     The import of equation (1) is apparent when consideration is given to the dependence of the k th  Z function in time frame n+1 on (a) the Z functions (used as arguments and N in number) in the n th  frame and (b) the N samples of f(t) in the n th  frame. By definition there are but N samples of the time function in any given frame, as the index i ranges over 0, 1, . . . N-1. Thus, the sample identified by the index i=N is outside a particular frame n, but is equivalent to the N-1 th  sample of the succeeding frame n+1. Thus, 
     
         f.sub.N,n =f.sub.N-1, n+1                                  (2) 
    
     In the recursive technique set forth herein, successive sample frames overlap. Hence, if the samples f are labeled in a continuous manner without renumbering at each frame, the first frame comprises samples f 0 ,f 1  . . . f N-1 , the second frame comprises samples f 1 ,f 2  . . . f N , the third comprises samples f 2 ,f 3  . . . f N+1  and so forth. As will be appreciated, the utilization herein of a continuous sample index i=0,1 . . . N and of a separate frame index n permits the desired mathematical description to be set forth in terms of a recursive formula. 
     Equation (1) assumes that, in the general case, there will be a specific function h i  of each sample. Moreover, it is further assumed that in the general case there will be a separate function g r  of each of the dependent variables, Z. Thus, a specific function h i  of the observed variable is combined with a different, specific function g r  of the dependent variable according to a specific function p k  to provide the current value of one of the dependent variables Z for the current time frame. 
     The apparatus of FIG. 1 may be utilized to implement equation (1) by using an input register or shift register SR1 to store samples of the observed variables. The contents of the register SR1 are shown at a time immediately following the last sample of the n th  frame, so that the stored samples include f o ,n . . . f N-1 ,n. The outputs of the shift register SR1 are provided as inputs to function generator 2 realizing the functions h. Additionally, the next sample f N ,n =f N-1 ,n+1 is fed to function generator 2 as required by equation (1). A second function generator 4, realizing the functions g, receives as inputs the the values of the dependent variables Z for the particular frame of interest. The dependent variables are stored in a feedback register R1. The outputs of the two function generators are provided as inputs to a third function generator 6, which realizes the functions p needed to produce the dependent variables Z k ,n+1. FIG. 1 further shows that the dependent variables Z k , n+1 for the new frame n+1 are input to an output register or shift register SR3. When all the current dependent variables have been calculated and stored in register SR3, switches S o  . . . S N-1  close, thereby providing those variables to feedback register R1 and permitting computation for the next frame. It is noted that, since each of the dependent variables for frame n+1 depend on all the samples of the observed variable for frame n, register SR3 must shift through all N positions for each shift of register SR1. Thus, while the intermediate term in register SR3 is shownas being Z k-N+r , n+1, it could be shown with equal validity as being z k-N+r ,n. 
     FIG. 2 shows an alternate approach to solving a recursive function, utilizing parallel generation of the various dependent variables. Thus, the symbols Z n+1  and p are used to denote the plurality of dependent variables and functions, respectively, generated by function generator 8. The dependent variables are generated simultaneously and made available to feedback register R1 for storage. Register R1 may comprise solid state devices, magnetic core storage or any other means for storing the information which is generated. A plurality of switches S o  . . . S N-1 , shown in the diagram as single-pole, single-throw switches but realizable in terms of any means capable of providing and removing circuit continuity, are used to avoid race conditions and to provide the dependent variables to register R1 at a properly synchronized time. 
     FIG. 3 is a modification of FIG. 1 in which a parallel input/serial output shift register SR2 is used in place of the register R1 shown in the FIG. 1. Thus, a single input is provided to function generator 10 for generating the g functions of the dependent variables of the n th  time frame. The p function generator 6 is the same as in FIG. 1, and provides a serial output of the dependent variables for the (n+1) th  frame, using a shift register SR3 to provide the variables to register SR2. This embodiment provides a more restricted solution to equation (1) by limiting the index r to the same value as the index k such that: 
     
         z.sub.k,n+1 =p.sub.k [{g.sub.k (Z.sub.k,n)}, {h.sub.i (f.sub.i,n)}](2A) 
    
     In keeping with equation (2A), it may be assumed that the recursive function is one in which the k th  dependent variable in the (n+1) th  frame is dependent only on the k th  dependent variable Z k  in the n th  frame and all the sampled values of the independent variables f i  in the n th  frame. Such a relationship is described as follows: 
     
         Z.sub.k,n+1 =p.sub.k [Z.sub.k,n {h(f.sub.i,n)}]            (3) 
    
     where 
     i=0,1, . . . N; and 
     k=0,1, . . . N-1. 
     Inasmuch as the dependent variable Z k  does not &#34;interact&#34; in the recursion, the variable Z k  l need not be calculated for all N possible values of the index k. Indeed, any subset may be chosen. 
     In summary, FIGS. 1 through 3 illustrate three permutations available for computing recursive functions. Specifically, the dependent variables may be computed serially or in parallel and may be provided to the respective function generators g in serial or parallel form. 
     It is known that the discrete Fourier transform (DFT) is described as follows: ##EQU1## where W=exp.(-j2π/N); 
     k=0,1, . . . N-1; 
     f i  are samples of a time function f(t); and 
     Z k  are the discrete frequency components. 
     It is shown in the above-referenced articles by Dillard, that a moving window discrete Fourier transform (MWDFT) may be recursively computed from a sequence of samples of a time function as follows: 
     
         Z.sub.k,n+1 =[Z.sub.k,n +f.sub.N,n -f.sub.0,n ]W.sup.-k    (5) 
    
     When the first time sample of the n th  frame f 0 ,n is used as a reference point and defined as f n , a succeeding i th  sample in the n th  frame may be expressed as: 
     
         f.sub.i,n =f.sub.i+n                                       (6) 
    
     The labeling of samples in succeeding time frames continues sequentially; for example, f i ,n+N =f i+n+N . This provides a single subscript notation for labeling the time samples, thereby permitting the window index to be omitted from the time samples. Accordingly, equation (5) may be rewritten as: 
     
         Z.sub.k,n+1 =[Z.sub.k,n +f.sub.N+n -f.sub.n ]W.sup.-k      (7) 
    
     where 
     k=0,1, . . . , N-1 
     n=0,1,2, . . . 
     Z k ,0 =Z k   
     In contrast to the general situation described by equation (3), equation (7) shows that only two input samples are needed to determine a complete set of DFT spectral coefficients. Inasmuch as a previous DFT transform Z k ,n is always necessary to calculate a subsequent transform Z k ,n+1, a special procedure is necessary to start up when only the i th  sample, f i , is available. 
     Equation (7) is implemented using apparatus 20 of FIG. 4. Apparatus 20 is a modification of the apparatus of FIG. 3, and corresponding elements are identified by common references. Registers SR1 and SR2 are used to store the sampled values of the time function and the computed discrete frequency components, respectively. It is noted that the input register SR1 may have an additional stage to store the first sample f N+n  of the next time frame n+1. The arrangement shown assumes f N+n  is held as a sample long enough to be operated on by the function h and to drive the N th  cell of SR1 at shift time. For convenience, the input register SR1 is hereinafter referred to as having an output for supplying the first sample f N+n  of the next time frame. Thus, it should be understood that such output may be taken from the input as shown or from an additional storage cell. 
     As illustrated in further detail in FIG. 5, the function h is realized by a simple subtractor 12, shown as a difference amplifier. The function p is realized by an adder 14, a multiplier 16, and an end-around or recirculating shift register SR4. Subtractor 12 provides an output equal to the difference f N+n  -f n  as required by equation (7). The difference is sequentially added to the dependent variables Z k ,n and the resultant sums are sequentially multiplied in multiplier 16 by successive one of the exponential factors W -k  stored in the shift register SR4. The factors in the register SR4 shift in synchronism with the dependent variables stored in the feedback register SR2 and N times as fast as the time samples stored in the register SR1. Thus, as required by equation (7), each shift of the sample values in the input register SR1 is followed by N shifts of the feedback register SR2, and each shift of the register SR2 is associated with appropriate arithmetic calculations. The means for synchronization form no part of this invention and therefore need not be illustrated in detail, but may include a conventional shift pulse generator, or other clocking means. 
     FIGS. 4 and 5 illustrate the possibility for the accumulation of error in the recursive computation of the moving window discrete Fourier transform. Once an error creeps into the computation of any of the discrete frequency components, Z k , that component is used again in computation of subsequent components, and the errors thus tend to accumulate. 
     In accordance with this invention, to limit the accumulation of recursive calculation errors, the spectral coefficients Z k  used in the recursive calculations are periodically reconstituted through the use of the recursive formula by periodically reinitializing the calculations with (a) a set of N zeroes (or any other predetermined sequence f i ,i=0,1, . . . , N-1) in the place of the observed sample values f n+i , i=0,1, . . . , N-1, and (b) another set of N zeroes (or the precalculated  and error-free DFT Z k , k=0,1, . . . , N-1, of the f i  (as defined by equation (4) instead of the corresponding MWDFT Z k ,n. This procedure assumes that the errors associated with zeroes (or f i  and Z k ) are negligible. In particular, it is desired to periodically reconstitute the spectral coefficients Z k  from the equation 
     
         Z.sub.k,n+1 =(0+f.sub.N+n +0)W.sup.-k                      (8) 
    
     or, more generally, from 
     
         Z.sub.k,n+1 =(Z.sub.k +f.sub.N+n -f.sub.o)W.sup.-k         (8a) 
    
     which is equation (7) with Z k ,n =f n  =0 or Z k ,n =Z k  and f n  =f o . 
     Using equation (8) one generates an error-limited (in the recursive sense) set of values for the dependent variables Z k ,n+1. However, the dependent Z k ,n+1 values so calculated are not yet the DFT of a sequence of N signal sample values; it being understood that only f N+n  is a signal sample value, the f i  are not. Thus, successive sets of partially reconstituted spectral coefficients are generated while holding f n+i  =f i , for i=1,2, . . . , N-1. For the special case when f n+1  =0: ##EQU2## where, for each equation, k=one or more of 0,1, . . . N-1. For the general case f n+i  =f i  : 
     
         Z.sub.k,n+i+1 =(Z.sub.k,n+i +f.sub.N+n+i -f.sub.i)W.sup.-k (9a) 
    
     The choice f i  =0 and Z k  =0 (all i and k) typically leads to the simplest hardware implementation and is assumed throughout the remainder of the discussion. The advantage of that choice is that only N recursive calculations are required to effectively generate a valid set of spectral coefficients Z k ,n+N to be used as an argument in equation (7). The calculated coefficients Z k ,n+N are the DFT of a sequence of N signal sample values; the f i  having been entirely eliminated. The accumulated computation error does not exceed N recursions, because the precalculated coefficients Z k  are error free within the limits of precision of the hardware. By generating these reconstituted spectral coefficients according to equations (8) and (9) and placing the final set of N values of Z k ,n+N into the feedback shift register SR2, one may proceed to utilize the apparatus of FIGS. 4 and 5 to implement equation (7) in an error-limiting manner. 
     In order to carry out the computations set forth above for f i  =Z k  =0 (all i and k), a switch S z  is employed at the output of the feedback register SR2 in FIG. 5 in order to provide a zero (grounded) reinitializing value to the adder 14. Additionally, the apparatus of FIG. 5 is duplicated and connected in the switching arrangement as shown in FIG. 6. In FIG. 6, devices similar to apparatus 20 are specified by the addition of a third digit, as 201, 202, etc. The switching arrangement is shown as comprising three single-pole-double-throw switches S 1 , S 2 , and S 3 . Any switching means may be used, however, such as FET&#39;s, SCR&#39;s, TRIAC&#39;s, or other devices capable of selectively making and breaking circuit continuity. If there are eight (8) samples per time frame the switches S 1  -S 3  and S Z  are operated in accordance with the timing diagrams shown in FIG. 7. Nevertheless, it will be appreciated that devices utilizing different numbers of samples/frame are also within the scope of the invention inasmuch as the timing for the switches may be adjusted accordingly. Furthermore, it should be understood that it is also possible to provide limited recursive error accumulation using the computing device 201 and the switch S1 of Channel A alone, if the switch S 3  is operated to alternately make and break a connection between the computing device 201 and the output terminal. 
     In operation the apparatus of FIG. 6 provides an output from one of the two computing channels A and B, while the other channel is being reset to zero and reinitialized. After reinitialization, the other channel is used to provide the output and the first is reset and reinitialized. Thus, recursive calculation errors in the output are limited. The timing chart of FIG. 7 illustrates the timing operation of switches S 1 , S 2 , and S 3 , as well as the timing of the switches S z  in channel A (device 201) and channel B (device 202). The signals A in  and B in  which are applied to the first stages of the input shift registers SR1 of channels A and B, respectively, by their associated switches S 1  and S 2  are illustrated as being composed of signal samples (X) and zero or reinitializing values (0). A similar notation has been used to indicate the times at which the switches S z  of channels A and B are set to pass signal values (X) and reinitializing zero values (0). As is seen from the timing diagram, a refresh cycle for a given channel, say, channel A, involves feeding a successive sequence of N=8 zero values into channel A via switch S 1  and then applying N zero values to adder 14 of channel A via the switch S z  of channel A. Thus, at timing interval 38, for example, the input values to subtractor 12 in channel A are, in terms of the recursive equation (7), f 0  =0 and f 8  =X (a sample value), and the input value to adder 14 in channel A is Z k ,0 =0. The recursive equation thus becomes 
     
         Z.sub.k,1 =(0+f.sub.8 +0)W.sup.-k 
    
     which is precisely the desired equation (8) for n=0, N=8 which begins error-limited spectral reconstruction. 
     It is noted that the N zero value inputs produced by switch S z  which correspond to Z k ,0 =0 are produced during one sample interval inasmuch as there are N shifts of the feedback register SR2 for each shift of the input register SR1. Successive shifts of the zero values in the input register SR1 of channel A effectuate equations (9) as desired to rebuild the coefficients to a point where a valid output can be obtained. A valid output is available after all the zero values have been shifted through the register SR1, which occurs after the contents of the register SR1 are shifted during interval 45 in the above example. At this point, switch S 3  may be connected to channel A since valid output coefficients Z k ,n+1 are now available. It should be understood, however, that the output switching between channels A and B may take place at longer intervals than shown in FIG. 7, although larger error buildup may be expected. Alternatively, it is possible to provide more than two channels for the computation, thereby providing for even shorter error accumulation periods, at the expense of added duplication of hardware. 
     At the outset of a suitable start-up procedure, the input registers SR1 in channels A and B are both initially filled with zeroes. Channel A starts operating at zero time as illustrated in FIG. 7. Channel B also starts at zero time, but its input is held at zero during the first 3N-1 actual input samples. Thus, the first actual sample seen by channel B is the 3Nth sample and the first valid output spectrum from Channel B represents the 3N th  through 4N-1 th  input samples. At this time the system output is taken from channel B, while the input of channel A is switched to zero for N samples and then returned to the actual input. When channel A is again providing a valid spectrum, the output is again taken from channel A and channel B is switched to zero for N samples. Thus, each channel is repeatedly and alternately &#34;refreshed&#34; to eliminate accumulated errors and the output is taken alternately from the two channels as appropriate. As a result, no computation error can be carried through more than 2N-1 spectrums or, in other words, 3N-2 recursions. 
     Alternatively, at start-up, the switches S 2  and S 3  may be operated in the same synchronism with the switch S 1  as in normal operation. In that event, as illustrated by dotted lines in FIG. 7, the only special control action required at start-up involves forcing entry into the sequence at the point at which S 1  is set to fill the input register SR1 of channel A with zeroes. In that event, the normal timing of the switch S 2  will ensure that channel B is reinitialized prior to computing a valid output. 
     It is to be understood that with either of the above described startup procedures, the first 2N-1 outputs are invalid and, therefore, should be ignored. 
     In the event that computing device 201 is used alone, in conjunction with switches S 1  and S 3 , it is clear that the device 201 is periodically reinitialized, thus providing a lower error rate at the output. However, the output signal is intermittently interrupted during such reinitialization. This approach is useful where the output is not always needed and may be regularly disconnected. 
     An alternate embodiment of FIGS. 5 and 6 is shown in FIGS. 8 and 9, respectively. Devices 201&#39; and 202&#39; are shown connected together in FIG. 9, much in the same manner as the devices 201 and 202 of FIG. 6. Switches S 1  and S 2  of FIG. 6 are, however, replaced in FIG. 9 by connecting separate switches S f  between the last stage of the shift register SR1 for each channel and the subtractor 12. The switches S f  are periodically connected to zero (ground), thereby avoiding the necessity of shifting zero values into the shift registers SR1 of channels A and B. As before, zeroes are applied to subtractor 12 for N sample intervals, while adder 14 receives initializing zero values via switch Z Z  on the first of the N sample intervals. The utilization of the switches S f  in devices 201&#39; (channel A) and 202&#39; (channel B) of FIG. 9 not only eliminates the need for actually shifting zero values into the input shift registers SR1, but also the necessity of clearing those zero values by subsequently shifting in new sample values. As confirmed by FIG. 10, which is a simplified timing diagram for the devices 201&#39; and 202&#39;, the error accumulation in the embodiment of FIG. 9 is limited to 2N-2 recursions, rather than to 3N-2 recursions as with the embodiment of FIG. 6. 
     Yet another embodiment of the invention is shown in FIG. 11, which essentially eliminates the redundant usage of separate shift registers SR1 and SR4 for each of the channels A and B as in FIGS. 8 and 9. In FIG. 11, the switches and registers are now labeled by a suffix A or B to indicate the associated channel. The timing diagram for the operation of the switches is the same as in FIG. 10. 
     FIG. 12 is a modification of FIGS. 8 and 9 wherein channel A comprises an on-line main computing device or processor 203, and channel B comprises an off-line auxiliary computing device or processor 204. The main computing device 203 of channel A is in the on-line path to the output, but performs only the recursive computation of the MWDFT-viz., the computation of equation (7). The auxiliary computing device 204 of channel B is isolated from the output, but performs the computation of the reconstituted spectral coefficients-viz., the computation of equation (8) and (9). Excessive accumulation of error in channel A is prevented by periodically replacing the spectral values in channel A by newly reconstituted values from channel B. 
     The shift register SR1, as well as the h function generator, are not needed in the auxiliary processor 204. The p function generator for the processor 204 is the same as shown in FIG. 8. Thus, upon connection of switch S z  to ground (zero), equation (8) is implemented by the auxiliary processor 204. The switch S Z  is subsequently connected to receive the contents of the shift register SR2, thereby implementing equation (9), and the reconstruction of the spectral coefficients then continues during the next N-1 sample intervals. As soon as a valid spectrum is available in the auxiliary processor 204, the spectrum is shifted into register SR2 of the main processor 203, thus replacing the existing spectrum within the main processor 203 and the excess accumulated errors associated therewith. The main processor 203 continues with the new or corrected spectrum as its base while the auxiliary processor reinitializes. N valid data samples later, the auxiliary processor 204 once again contains a valid spectrum ready to be transferred into the shift register SR2 of the main processor 203 so that the process may be repeated. Again, single-pole switches S z  and S 5  are shown, but other devices may be used. The shifting of spectrum data from processor 204 to processor 203 is shown as a parallel shift, but other approaches may be utilized. 
     FIG. 13 shows a timing diagram for the operation of the switches of the embodiment shown in FIG. 12. When the auxiliary processor 204 has processed the requisite number of valid samples, switches S 5  are activated to transfer the data from the register SR2 in processor 204 to the register SR2 in processor 203. That transfer is carried out rapidly in the interval between the serial shifts of the registers SR2. 
     Of course, the transfer from Channel B to Channel A must occur after Channel B has first performed equation (8) at least once and then performed equation (9) exactly N-1 times because Channel B is not capable of implementing equation (7). 
     FIG. 14 shows the apparatus of FIG. 12 with a savings in hardware realized by sharing shift register SR4 in function generator p of processor 205 for the computations in auxiliary processor 206. This may be done inasmuch as the sequence of constants contained in shift register SR4 is the same for both of the processors 205 and 206. 
     FIG. 15 illustrates another modification of the embodiment shown in FIG. 12. In FIG. 15, there is a switch S 7  for alternately connecting the system output and the input of the shift register SR2 of a processor 207 to (a) the output of function generator p in the processor 207 or (b) the output of a separate function generator P3 in another processor 208. Accordingly, the output spectrum generated by processor 207 is reinitialized over N shifts of the register SR2 of the processor 208, rather than relying on simultaneous reinitialization as in FIGS. 12 and 14. 
     Having described specific embodiments of the invention, many alternatives, modifications, and equivalents will become apparent to practitioners of ordinary skill in the art.