Digitally controlled servo system
BACKGROUND OF THE INVENTION 
     The present invention generally pertains to servo systems and is particularly directed to a system for continuously controlling a servo motor in response to a digital command signal. 
     In controlling a continuously controlled analog output device, such a servo motor, in response to a digital command signal, a digital-to-analog (D/A) conversion must take place somewhere in the system. The D/A conversion inherently causes phase lag because of the discreet interval sampling process which occurs at a digital signal processor frame rate, even when the D/A conversion is performed within the servo loop; and therefore the sampling phase lag adds directly to system errors. This phase lag is a serious difficulty against obtaining high performance in digitally controlled systems, such as in the implementation of digital controllers to meet tactical missle guidance and control requirements. 
     It is an object of the present invention to provide an improved digitally controlled servo system wherein the phase lag is reduced significantly to enable the system to be used in missle applications, with high performance, low power drain, and minimum cost. 
     SUMMARY OF THE INVENTION 
     The present invention is a servo system wherein a servo motor is continuously controlled in response to a pulse width modulated digital command signal. A servo system in accordance with the present invention includes a servo motor having a variable output that is controlled in response to a variable amplitude error signal; a pulse code converter for providing a pulse width modulated digital command signal for controlling the variable output of the motor, wherein the digital command signal is provided at a predetermined frame rate in response to a frame pulse signal; a feedback transducer and network for sensing the variable output of the servo motor and for providing a variable amplitude feedback signal indicative of the variable output; a synchronous pulse forming network for converting the variable amplitude feedback signal to a proportional pulse width modulated digital feedback signal, wherein the digital feedback signal is provided at the predetermined frame rate and in synchronization with the digital command signal; a summing junction for summing the digital command signal with the digital feedback signal to provide a digital error signal; and a pulse width-to-amplitude demodulator for converting the digital error signal to a continuous variable amplitude error signal for continuously controlling the variable output of the servo motor. 
     Preferably the pulse width-to-amplitude demodulator includes an integrator for integrating the digital error signal to provide an integrated error signal; and a zero order hold sampler for sampling the amplitude of the integrated error signal to provide the continuous variable amplitude output signal, wherein the sampled amplitude is held for a full frame period as defined by the frame pulse signal. 
     It also is preferable that the integrator include a first switch for enabling such integration and for resetting the integrator; that the zero order hold sampler include a second switch for enabling such sampling; and that the pulse width-to-amplitude demodulator include a dual monostable multivibrator for providing a first switching signal having a duration greater than the maximum duration of any pulse in the pulse width modulated digital error signal, and a second switching signal having a duration that is slightly less than the duration of the first switching signal; and an exclusive OR logic element having its inputs connected to receive the first and second switching signals and its output connected to the second switch; wherein the multivibrator also is connected to provide the first switching signal to the first switch for causing the first switch to enable the integrator to integrate the digital error signal over the duration of the first switching signal and to reset the integrator for integrating each successive pulse in the digital error signal upon the termination of the first switching signal, and to provide the first and second switching signal to the exclusive OR logic element in a sequence to cause the second switch to enable the zero order hold sampler to sample the integrated error signal during a short interval just before the integrator is reset. 
     By providing D/A interfacing in the servo loop ahead of the analog power elements, the need to use more complicated, costly, and lower performing stepping motors or incremental mechanical devices is avoided. Thus, the servo system of the present invention offers higher performance at lower cost than an all digital system, with power elements. 
     The D/A interface demodulation process is important to achieve low power drain. The amplitude sensitivity of the continuous variable amplitude error signal with respect to the digital error signal is essentially linear with no dead zone. This feature allows the overall servo system to operate in a linear fashion with no internally generated signal perturbations other than a zero order hold &#34;staircase&#34; granularity in the continuous variable amplitude error signal, which smooths to zero as the digital error signal goes to zero. Linearization of the servo system by such means avoids power consuming, heat generating, limit cycles which can result with other known nonlinear means of pulse width demodulation, such as pulse structuring and on-off power controlling techniques. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block diagram of the servo system of the present invention. 
     FIG. 1A is a timing diagram showing the relationship between the digital command signal, the digital feedback signal and the digital error signal in the servo system of FIG. 1. 
     FIG. 2 is a schematic circuit diagram of the components of the servo loop of FIG. 1. 
     FIG. 3 is a schematic circuit diagram of the pulse code converter of the servo system of FIG. 1. 
     FIG. 4 is a graph showing the improvement in decreased phase lag provided by the servo system of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, the servo system of the present invention essentially includes the analog power elements of a servo motor 10, a feedback transducer and network 12, a synchronous pulse forming network 14, a summing junction 16 and a pulse width to amplitude demodulator 18. The system is controlled in response to a pulse width modulated (PWM) digital command signal provided on line 20 from a pulse code converter 22. The pulse code converter 22 provides the PWM digital command signal on line 20 by converting a pulse code modulated (PCM) digital command signal on line 24. The system input PCM command signal on line 24 typically is encoded with a binary position pulse code (ie. multiple pulse positional representation of a binary number). To provide the PWM digital command signal on line 20 to the servo summing junction 18, the pulse code converter converts the code pulses of a binary number into a single pulse, the width of which represents the value of the number. The PWM digital command signal is provided on line 20 at a predetermined frame rate in response to a frame signal provided the pulse code converter 22 on line 26. The command information is represented by the width of each incoming pulse. The frame pulse signal on line 26 is provided from the same digital processor (not shown) as the pulse code modulated digital command signal on line 24 and is synchronized therewith. The predetermined frame rate is the rate at which digital commands from the digital processor are updated. 
     The servo motor provides a controlled variable analog output 28. The controlled variable output of the servo motor is position, rate-of-change-of position, or torque (force), such as is required for actuation of missile airframe flight controls, stable platforms and antenna gimbals. 
     Within the servo motor, the power elements 10 may be electromechanical, electrohydraulic or electropneumatic analog means of actuation. 
     The feedback transducer and network 12 senses the variable output 28 and provides a variable amplitude feedback signal on line 30 that is indicative of the variable output 28. 
     The synchronous pulse forming network 14 converts the variable amplitude feedback signal on line 30 to provide a proportional pulse width modulated digital feedback signal on line 32. The digital feedback signal on line 32 is provided at the predetermined frame rate in accordance with the frame pulse signal on line 26, and therefore is in synchronization with the pulse width modulated digital command signal on line 20. Alternatively, such synchronization may be achieved by sensing the rate of the digital command signal on line 20 with a pulse detecting network (not shown) and providing the detected pulse rate to the synchronous pulse forming network 14. 
     The feedback transducing element of the feedback transducer and network 10 may consist of a variable resistor, capacitor or inductor situated within the synchronous pulse forming network 14 to directly control the digital feedback signal pulse width. Alternatively, feedback transducing may be accomplished by means of a device to provide signal control of the pulse width formed by the synchronous pulse forming network 14, such as voltage dividing or generating transducers or an analog-to-digital encoder. Configuration of the synchronous pulse forming network 14 is dependent upon the type of feedback transducing element used. Synchronization of the synchronous pulse forming network 14, when the detected incoming pulse option is used, may be mechanized by means of a derivative, or phase lock network. 
     The digital command signal on line 20 is summed with the digital feedback signal on line 32 at the summing junction 16 to provide a digital error signal ε on line 34. 
     The pulse width-to-amplitude demodulator 18 converts the digital error signal ε on line 34 to a continuous variable amplitude error signal ε&#39; on line 36 for continuously controlling the variable output 28 of the servo motor. The digital error signal ε on line 34 is a pulse having a width that is proportional to the difference in widths of the pulses of the digital command signal on line 20 and the digital feedback signal on line 32. The polarity of the digital error signal ε on line 34 depends upon whether the feedback signal pulse width is larger or smaller than the command signal pulse width. The relationship between the digital command signal on line 20, the digital feedback signal on line 32 and the digital error signal on line 34 is shown in FIG. 1A. 
     The digital error signal on line 34 is demodulated by the pulse width-to-amplitude demodulator 18 to provide a continuous variable amplitude error signal, ε&#39; on line 36, which can be handled directly by the analog power elements of the servo motor 10. The demodulation process consists of, integration, sample, hold and re-set, such that the amplitude sensitivity of ε&#39; is effectively linear with no dead zone. The continuous error signal ε&#39; has a zero order hold staircase granularity (as shown at line 36 in FIG. 1) which granularity smooths to zero as the digital error signal goes to zero pulse width. 
     The demodulation phase lag resulting from discreet data sampling in the pulse width-to-amplitude demodulator 18 is contained within the closed servo loop and therefore does not add to overall system phase lag measured between the servo output 28 and the loop input on line 20. 
     A preferred embodiment of the servo loop of the servo system of FIG. 1 is shown in the schematic circuit diagram of FIG. 2. 
     An electric direct drive servo motor 38 is controlled by a power transistor bridge circuit 40 in response to the continuous variable amplitude error signal on line 36. The bridge circuit 40 includes power transistors Q1, Q2, Q3 and Q4. These power transistors are connected so that transistor Q1 and Q4 conduct when transistors Q2 and Q3 are not conducting or vice versa. 
     The continuous error signal on line 36 is amplified by a preamplifier and compensation network 42, and provided on line 43 to a switching amplifier 44. The switching amplifier 44 controls switching within the power transistor bridge 40 by means of a Schmitt trigger circuit 46. 
     The bridge 40 is controlled by the Schmitt trigger 46 to reverse the direction of conduction across the servo motor terminals 48 and 50. Conduction between the power source terminals ±V S , is either through the transistor pair Q1 and Q4, or the transistor pair Q2 and Q3. A closed loop feedback voltage is provided from the motor terminal 48, 50 to the switching amplifier 44 by a feedback amplifier 52 so that a limit cycle is set-up by the action of the Schmitt trigger 46. Limit cycle switching frequency entrainment in the 5 to 10 KHz vicinity is also provided by the triangular wave generator 54 connected by line 56 to the switching amplifier 44. The action of the switching is to use the power transistors Q1, Q2, Q3, Q4 in only the saturated and off conditions to maximize power efficiency and linearize the output. The actual output across the motor terminals 48, 50 is a time modulated voltage square wave at the switching frequency. Linearization of the switching amplifier 44 output is achieved by time modulation such that the effective voltage applied to the servo motor 38 is proportional to the switching amplifier input signal on line 43 from the servo pre-amplifer and compensation network 42. 
     The servo motor output shaft 58 is coupled to the servo motor 38 by a mechanical reduction gear 60. 
     A voltage dividing feedback transducer 62 senses the variable output 28 of the servo motor from the output shaft 58 and provides a variable amplitude signal on line 30 to a monostable multivibrator 64 in the synchronous pulse forming network 14. The monostable multivibrator 64 converts the variable amplitude feedback signal on line 30 to a proportional pulse width modulated digital feedback signal on line 32. The digital feedback signal on line 32 is provided at the predetermined frame rate in response to the frame pulse signal on line 26. At the beginning of each frame, as defined by the frame pulse signal on line 26, the frame pulse switches the output of the multivibrator 64 from binary &#34;0&#34; to binary &#34;1&#34;, to form an output pulse on line 32 having a duration proportional to the voltage amplitude of the signal on line 30 from the feedback transducer 62 as determined by the values of the network components R1 and C1 at the multivibrator control terminals. 
     The digital command signal on line 20 is summed with the digital feedback signal on line 32 at summing junction 16 to provide a digital error signal on line 34. 
     The pulse width-to-amplitude demodulator 18 includes an amplifier 66 for amplifying the digital error signal on line 34, an integrator 68, zero order hold sampler 70, a dual monostable multivibrator 72 and an exclusive OR logic element 74. 
     The integrator 68 integrates the amplified digital error signal on line 67 to provide an integrated error signal on line 69. The zero order hold sampler 70 samples the amplitude of the integrated error signal on line 69 to provide the continuous variable amplitude output signal on line 36. The sampled amplitude is held for a full frame period as defined by the frame pulse signal on line 26. The frame pulse signal on line 26 is provided to the dual monostable multivibrator 72. 
     The integrator 68 includes a first FET switch Q5 for enabling the integration and for resetting the integrator 68. The zero order hold sampler 70 includes a second FET switch Q6 for enabling the sampling. 
     The dual monostable multivibrator 72 responds to the frame pulse signal on line 26 to provide a first switching signal on line 76 and a second switching signal on line 78. The first switching signal on line 76 has a duration greater than the maximum duration of any pulse in the pulse width modulated digital error signal on line 32 and the second switching signal on line 78 has a duration that is slightly less than the duration of the first switching signal on line 76. 
     The exclusive OR logic element 74 has its inputs connected to receive the first and second switching signals on lines 76 and 78 and its output connected via line 80 to the second FET switch Q6. 
     The dual monostable multivibrator 72 provides the first switching signal on line 76 to the first FET switch Q5 for causing the first FET switch Q5 to enable the integrator 68 to integrate the amplified digital error signal on line 67 over the duration of the first switching signal on line 76 and to reset the integrator 68 for integrating each successive pulse in the digital error signal on line 67 upon the termination of the first switching signal on line 76. 
     The integration interval is set by the first switching signal on line 76 such that the first FET switch Q5 is open longer than the maximum design difference pulse width, as defined by the frame pulse signal on line 26. 
     The dual monostable multivibrator 72 also provides both the first and second switching signal on lines 76 and 78 to the exclusive OR logic element 74 in a sequence that causes the second FET switch Q6 to enable the zero order hold sampler 70 to sample the integrated error signal on line 69 during a short interval just before the integrator 68 is reset by closure of the first FET switch Q5. 
     This short interval is the slight difference between the durations of the first and second switching signals on lines 76 and 78. 
     A schematic circuit diagram of a preferred embodiment of the pulse code converter 22 of the servo system of FIG. 1 is shown in FIG. 3. The pulse code converter 22 includes two integrated circuit counters 82 and 84 and four integrated circuit NAND gates 86, 87, 88, 89 connected as shown in FIG. 3. The counters 82, 84 are No. 74193 integrated circuits and the NAND gates 86, 87, 88, 89 are included in a No. 7400 integrated circuit package. The respective &#34;down count&#34;, &#34;load&#34;, &#34;borrow&#34;, &#34;carry&#34;, &#34;clock&#34;, and &#34;up count&#34; terminals of the counters 82 and 84 are interconnected as shown in FIG. 3. The &#34;load&#34; terminals of the counters 82 and 84 also are both connected to one input of the NAND gate 88. The &#34;borrow&#34; terminal of the counter 84 is connected to one input of the NAND gate 89. The &#34;down count&#34; terminal of the counter 82 is connected to the output of the NAND gate 86. 
     The pulse code converter converts a pulse code modulated digital binary signal received on lines 24a-24h to a pulse width modulated signal that is provided on line 20. The least significant bits of the binary signal are received by the counter 82 on lines 24a-24d, and the most significant bits of the binary signal are received by the counter 84 on lines 24e-24h. 
     A high frequency clock signal is provided on line 90 to one input of the NAND gate 87. The frame pulse signal received on line 26 from the same digital processor as the binary signal on lines 24a-24h, is provided to one input of the NAND gate 88 and to the load terminals of the two counters 82 and 84. 
     The PWM digital signal on line 20 has a pulse width proportional to the value of the binary word received by the counters 82 and 84 on lines 24a-24h. Although only two four-bit binary counters 82, 84 are shown in FIG. 3, the system is not limited to the binary word size shown. 
     FIG. 4 illustrates the improvement in decreased phase lag provided by the servo system of the present invention compared to phase lag in an analog servo system wherein the D/A conversion function is performed in series with the servo loop rather than within the loop, as in the present invention. The curves of FIG. 4 are plotted for a frame pulse rate of 250 Hz. The upper curve shows the phase lag with the servo system of the present invention. The lower curve shows the phase lag with a conventional analog servo system with series D/A conversion. The improved system reduces phase lag by about 20 degrees at a typical missle control system stability crossover frequency of 25 Hz.