Frequency dividing circuit of variable frequency dividing ratio type
BACKGROUND OF THE INVENTION 
     1. FIELD OF THE INVENTION 
     The present invention relates to a variable frequency dividing circuit adapted to receive a signal from various types of signal sources operating in different frequency zones or ranges and provide a frequency divided output to synchronize various signal-receiving units such as a car clock, flashers, intermittently operated wipers or the like in which circuit the frequency dividing ratio is electrically controlled. 
     2. DESCRIPTION OF THE PRIOR ART 
     In conventional frequency divider circuits, it has been a common practice to connect a frequency dividing circuit to a specific oscillating source and obtain various timing signals from the various stages of the frequency dividing circuit to synchronize various types of operating units such as a car clock, flasher, intermittently operated wipers and so forth with the aforesaid timing signals. 
     In these conventional frequency dividing circuits, the frequency dividing ratio has been kept fixed, and because timing pulses for the operating units are also specifically designated, the result is that the frequency of the oscillating source must also be specified. Consequently, the aforementioned frequency dividing circuit is not readily adapted to oscillating sources of similar or different type operating in different frequency or ranges. Also, since most frequency divider circuits are fabricated as integrated circuits having a limited number of output pins it is difficult to alter the frequency dividing ratio by changing the connections of the output pins. As a result, it has been necessary to specifically design the frequency dividing circuits for corresponding oscillating sources and with the resultant disadvantage that production efficiency and maintenance efficiency are reduced because full standardization cannot be achieved. 
     SUMMARY OF THE INVENTION 
     In view of this, it is a principal object of the present invention to eliminate the abovementioned shortcomings and provide a unique frequency dividing circuit of variable frequency dividing ratio type arranged to obtain a specifically desired timing pulse by electrically changing the frequency dividing ratio so the circuit is compatible with various kinds of oscillating sources operating in different frequency zones or ranges. 
     It is another object of the present invention to provide a frequency dividing circuit of variable frequency dividing ratio type to provide correctly timed output signals to the various operating units of a car, for example, such as a car clock, flasher, intermittently working wiper and the like. 
     It is a further object of the present invention to provide a frequency dividing circuit of variable frequency dividing ratio type that includes, as part of an integrated circuit, an amplifier and/or buffer amplifier comprising a part of oscillating circuit, frequency dividing circuits and controllable gates for controlling the frequency dividing circuits. 
     It is a still further object of the present invention to provide a frequency dividing circuit of variable frequency dividing ratio type characterized in that a feedback circuit is provided that includes a crystal oscillating element, a resistor and a capacitor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a frequency dividing circuit embodiment wherein a crystal oscillator is used as an oscillating source; 
     FIG. 2 illustrates the circuit embodiment of FIG. 1 wherein a RC oscillator is used as an oscillating source; and 
     FIG. 3 illustrates the circuit embodiment of FIGS. 1 and 2 wherein an oscillating source is connected to the external pins of an integrated circuit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIGS. 1-3 illustrate a variable frequency divider circuit 3 in accordance with the present invention connected to a different type of frequency-source circuit 1, 1&#39;, and 1&#34;. The dividing circuit 3 is preferably fabricated as an integrated circuit (shown enclosed by the dot-dash line in FIGS. 1-3) that includes externally accessible pins 5, 6, and 7 for connection to the external oscillator circuits, 1, 1&#39;, and 1&#34;, a pin 18 from which the circuit output is obtained, and a pin 10 for connection to a control switch 9, which, depending upon its position, selects the frequency division ratio of the circuit 3 as described more fully below. 
     As shown in FIGS. 1-3, the variable frequency divider circuit 3 includes an amplifier 4 having its input connected to the pin 7, a buffer amplifier 8 having its input connected to both the pin 6 and the output of the amplifier 4 and its output connected to the pin 5 and an input 23 of a signal controlling NAND gate 12. A frequency divider 15, having a frequency division ratio N 1 , has its input connected to the output of the signal controlling NAND gate 12 and its output connected to an input 24 of a signal controlling NAND gate 13. The output of the NAND gate 13 is connected to an input 27 of a signal controlling NAND gate 17, the output of which is connected to the input of a second frequency divider 16, having a frequency division ratio N 2 . The inputs 19 and 20 of the NAND gates 12 and 13, which inputs constitute control inputs, are connected to the pin 10, which in turn, is connected to the control switch 9 operable between an open position, as shown in FIG. 1, and a closed position as shown in FIGS. 2 and 3. An input 26 of the NAND gate 17, which constitutes the control input for the gate 17, is connected to the output of a NAND gate 14 which has one of its inputs 25 connected to the pin 5, the output of the buffer amplifier 8, and the input 23 of the NAND gate 12, and the other of its inputs 22 connected to the output of an inverter 11. An input 21 of the inverter 11 is connected to the pin 10 and to the control switch 9. 
     The various NAND gates are adapted to be enabled or inhibited in response to the position of the control switch 9 to control the division rate of the circuit 3. As is known in the logic art, the designation of the logic control states is arbitrary and, as defined herein, the pin 10 becomes logic zero when the control switch 9 is closed, and, conversely, becomes logic one when the control switch 9 is open. 
     In FIG. 1, the frequency dividing circuit 3 is connected to the oscillating signal source 1 that includes a crystal oscillating element 2 and associated resistors and capacitors in which the signal source 1 is connected to the circuit 3 through the pins 6 and 7 such that the amplifier 4 assists in providing circuit feedback. 
     When the control switch 9 is opened, as shown in FIG. 1, to make pin 10 logic one, the input terminals 19 and 20 of the NAND gates 12 and 13 become logic one and the input terminal 21 of the inverter 11 also becomes logic one with the input terminal 22 of the NAND gate 14 becoming logic zero. 
     As a result, the outputs of the NAND gates 12 and 13 are controlled by the signals applied to their input signal terminals 23 and 24, respectively, while the output of the NAND gate 14 becomes logic one irrespective of the signal applied to its signal input terminal 25. 
     Consequently, the control input terminal 26 of the NAND gate 17 becomes logic one with the output of this NAND gate controlled by the signal applied to its signal input terminal 27 from the output of the NAND gate 13. Thus, as can be appreciated by those skilled in the art, when the control switch 9 is operated to make pin 10 logic one, the gates 12, 13, and 17 are enabled while the gate 14 is inhibited. When the circuit 3 is connected to a crystal oscillating source 1 as shown in FIG. 1 through pins 6 and 7, the output sine wave of the crystal oscillator, that is, the output of the amplifier 4 is applied through the buffer amplifier 8 to the signal input terminal 23 of the NAND gate 12. As the square wave of the output of the amplifier 4 passes through the gate 12, it is complemented to a square wave of auxiliary or complementary phase and inputted to the frequency dividing circuit 14 which divides its input signal by its dividing ratio N 1 . The output of the frequency dividing circuit 15 is passed to and through the NAND gate 17 and to and through the NAND gate 13 with each gate, 13 and 17, providing an output that is the complement of its input. The output of the NAND gate 17 is inputted to the frequency dividing circuit 16 which divides its input signal by its dividing ratio N 2 . Therefore, at the timing pulse output pin 18, which is the output terminal of the frequency dividing circuit, a timing pulse of frequency dividing ratio N 1  ×N 2  is obtained. 
     FIG. 2 illustrates an RC oscillator 1&#39; as an oscillating source connected to the frequency dividing circuit 3. As shown in FIG. 2, the RC feedback circuit 1&#39; comprises resistors R 1  and R 2  and a capacitor C connected to the external circuit pins 5, 6 and 7 of the integrated circuit 3 to provide an RC oscillator together with the amplifier 4 and the buffer amplifier 8. The internal circuitry of the integrated circuit 3 is the same as in FIG. 1. 
     Since the control switch 9 is CLOSED, as shown in FIG. 2, the input terminals 19 and 20 of the NAND gates 12 and 13 become logic zero while the input terminal 21 of the inverter 11 becomes logic zero, the input terminal 22 of the NAND gate 14 to become logic one. 
     As a result, the outputs of the NAND gates 12 and 13 are held at logic are independent of the signals applied to their input terminals 23 and 24 and the output of the NAND gate 14 is controlled substantially by the signal applied to its signal input terminal 25. The input terminal 27 of the NAND gate 17 is held at logic 1 because of its connection to the output of the gate 13 and the output of the NAND gate 26 is controlled by the signal applied to the input terminal 26 from the NAND gate 14. In this condition, the output of RC oscillator is passed to the frequency dividing circuit 16 via the NAND gates 14 and 17. Since the output of the NAND gate 12 is held at logic one, the frequency dividing circuit 15 is inoperative. Therefore, at the timing pulse output pin 18, a timing pulse of frequency dividing ratio N 2  is obtained. 
     FIG. 3 shows a crystal clock 1&#34; as an oscillating source connected to the integrated circuit 3. As indicated therein, 1&#34; is an oscillating source connected to the external circuit connecting pin 7 with the amplifier 4 and the buffer amplifier 8 used substantially as a buffer amplifier. The construction of other portions is the same as in FIG. 2. In configuration shown in FIG. 3, in which the control switch 9 is closed to cause the output of the oscillating source 1&#34; to be passed to the frequency dividing circuit 16 through the amplifier 4, buffer amplifier 8, the NAND gate 14 and the NAND gate 17. Therefore, at the timing pulse output pin 18, a timing pulse of frequency dividing ratio N 2  is obtained. 
     It is a simple matter to provide similarly constructed circuits including n frequency dividing circuits to embody the frequency dividing ratio N n  ·N n-1  ·N n-2  . . . N 1 , N n-2  ·N n-3  ·N n-4  . . . N 1 , N n-3  ·N n-4  ·N n-5  . . . N 1 . 
     In accordance with the present invention, as described above, specific timing pulses can be assured by changing the frequency dividing ratio through the operation of the control switch 9 even where oscillating sources operating in different frequency zones such as a crystal oscillator, RC oscillator and/or a desired oscillator connected as the external circuit of the integrated circuit 3, hence the present invention can save the necessity of specially preparing the frequency dividing circuits corresponding to individual oscillating sources. 
     Furthermore, as the integrated circuit 3 contains the amplifier 4, the buffer amplifier 8 and the external circuit connecting pins 5, 6 and 7 acting as the input and output terminals of the amplifiers, various types of oscillating sources can be embodied depending on the nature of feedback circuits for these various types of oscillating sources.