Analog-digital coder comprising a charge transfer device
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to analog-digital coders and, in particular, to coders conforming to the compression laws A and μ defined in the standards of the CCITT (International Telegraph and Telephone Consultative Committee). 
     2. Description of the Prior Art 
     In order to code an analog signal in a series of bits, conventional coders generally effect the sequential operations of sampling the analog signal, quantifying and coding the sample in binary form. The coding establishes a one-to-one correspondence between the values quantified and their expression in binary form. Generally speaking, the conversion time of such devices is proportional to the sum of the sequential operations mentioned above. The times corresponding to the operations of quantifying and coding the samples signal increase as the complexity of the circuits enabling their execution increase. 
     These coders have been improved by means of charge transfer devices (hereinafter CTD) which enable the sampling operation to be effected better and more rapidly (elimination of a capacitor used as a memory), thus improving the conversion time. 
     The known solution is to use coders of the pulse type or successive approximation type (trial and error). 
     However, pulse coders require CTD&#39;s with a very large number of electrodes, this number limiting the conversion speed. They also require a very rapid comparator, with a very low threshold voltage and high dynamic performance; such a comparator is difficult to design. In the case of successive approximation coders, it is necessary, for each bit tested, to record it in the CTD and then to erase it, which also has the disadvantage of limiting conversion time (even if there are fewer electrodes than the minimum required for coders). Furthermore, the structure is still complex. 
     Analog-digital coders of the serial type are also known wherein coding is based on successive comparisons of the voltage to be coded in relation to fractions of a reference voltage, each successive comparison furnishing a bit corresponding to the analog voltage for coding, from the most significant bit to the least significant bit. Among others these different operations necessitate the use of multipliers as well as the storage of the results. These simply structured coders use capacitors for storing the results, which limits the conversion speed (owing to the time constant for charging and discharging the capacitors) as well as precision (since the leakage of the capacitors is not negligible with relatively long storage times). 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to remedy the disadvantages of these known coders (complexity and long conversion time) by using the simple structure of a serial coder wherein a CTD enables the disadvantages due to capacitor memories to be eliminated. 
     According to the invention, there is provided an analog-digital coder intended for the coding of analog information in accordance with a law determining a compression curve constituted by p linear segments, p being a positive integer, each of said segments being quantified in a given number of quanta. Each analog information is coded in a number of M=1+n+k bits characterizing each of said quanta, wherein n (integer greater than -1) is the number of bits whose value characterizes one of the p segments, k (positive integer) is the number of bits whose value characterises a quantum of the segment determined by n, and 1 corresponds to a bit of sign, said coder having an output and including in series: analog switching means having two inputs for receiving respectively said analog information and a first reference voltage, and two outputs; and adder having two inputs respectively coupled to the two outputs of said analog switching means; multiplication and storage means comprising a charge transfer device with k+1 groups of m cells (m positive integer), each cell being constituted by q electrodes (q integer greater than 1 and less than 4) having surfaces which are weighted by a factor that is a function of said law; a comparator for comparing the signal of the multiplication and storage means with a second reference voltage; and logic switching means having an output coupled to the output of said coder. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The invention will be more readily understood and other features will become apparent through the description and the attached figures, wherein: 
     FIG. 1 is a schematic diagram of the device according to the invention; 
     FIG. 2 is a compression curve for the law A; 
     FIG. 3 is a diagram of a first embodiment of a device according to the invention; 
     FIG. 4 is a detailed drawing of a component of FIG. 3; 
     FIG. 5 represents voltage as a function of time for the control signals governing the operation of the device of FIG. 3; 
     FIG. 6 is a compression curve according to the law μ; 
     FIG. 7 is a diagram of a second embodiment of a device according to the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Those components that are identical from one figure to another are identified by the same symbols. 
     In FIGS. 3 and 5, switches are represented as being of the mechanical type to simplify the drawing but they are, in the embodiments described, electronic switches whose associated arrows, generally represented by T, serve to identify their control signals which are positive or zero. These switches are open when their control signal is zero. 
     In FIG. 1, analog switching means, 1, also having an attenuation function, has two input terminals, 10 and 11, receiving respectively signals V A  and V, and two outputs connected respectively to the two input terminals, 12 and 13, of an adder, 2. The output of the adder, 2, is connected to multiplying and storage means, 3, whose output supplies in parallel the input of amplifying means, 6, and a first input of a comparator, 4, a second input of which receives a d.c. voltage V k . The output of comparator 4 is connected to an output terminal, 14, supplying a signal, Q, via logic switching means, 5. The amplifying means 6 has two outputs respectively connected to the two input terminals 12 and 13 of adder 2. 
     Signals V A  and V are respectively a variable voltage to be coded an a d.c. reference voltage, while the signal Q is a binary signal. 
     The principle of serial type analog-digital coding is as follows. A reference voltage which shall be called V R  (to distinguish it from the preceding reference voltage which does not have the same function, as will be seen below) is quantified as a number of quanta equal to the number of states of the binary word that is to represent the coded voltage. As each quantum corresponds to a state of the binary word, the number of quanta is a function of the number of bits desired for the binary word. When coding in a binary word Q b  having 4 bits, the maximum (or full scale) voltage that can be coded is equal to the voltage V R  -(1/16)V R , i.e. V R  less one quantum, and corresponds to Q b  =1111, the half scale voltage V A  =V R  /2 corresponds to Q b  =1000, the quarter scale voltage V A  =V R  /4 corresponds to Q b  =0100, and so on. The voltage for coding is therefore a fraction of the reference voltage and can be expressed by the product of voltage V R  and the significance of the corresponding binary word Q b  (expressed as a sixteenth of the voltage V R  for a 4 bit code). 
     In order to obtain the binary word Q b  it is necessary to establish the quantum of the voltage V R  to which voltage V A  is equal. This is achieved by successive comparisons between the voltage V A  and fractions k (k&lt;1) of voltage V R . If V A  -kV R  is positive, the corresponding bit is equal to &#34;1&#34;, and to &#34;0&#34; if the contrary is true. 
     If the first comparison V A  -(V R  /2) is positive, the first bit (or the most significant bit) is equal to &#34;1&#34;; if it is negative, this bit is equal to &#34;0&#34;; this is a test in relation to half scale. The second comparison will be V A  -(V R  /4) (quarter scale test) if the preceding bit is equal to &#34;1&#34; and V A  -(3V R  /4) (three quarter scale test) if it is equal to &#34;0&#34;. If the result of this second comparison is positive, the second bit will be equal to &#34;1&#34; and if it is negative, this second bit will be equal to &#34;0&#34;. It should be noted that determination of a given bit, other than the most significant bit, takes into account the status of the preceding bit. 
     The process continues up to the least significant bit. 
     This principle applies to linear coding but, for non-linear coding, the transmittance is linear in parts, being composed of p segments (p&gt;0). It is first of all necessary to code the different segments of this transmittance (after determining, if applicable, the sign bit). In order to code 2 n  segments, n bits are used, for example n=3 for 8 segments. A detailed account of the coding of these segments will be given below. Next, it is necessary to code the different quanta of each segment linearly according to the method described above. The analog switching means 1 and the adder 2 enable the alternate injection into the multiplying and storage means 3 of voltages V A  and k 1  V, via terminal 12, and of a voltage k 2  V via terminal 13. Similarly, a voltage k 3  (V A  +k 4  V) (k 1 , k 2 , k 3  and k 4  being positive or negative integral or fractional coefficients) can be injected by means of amplifying means 6 and adder 2. The latter voltage is the one stored, during a preceding operation, in multiplying and storage means 3 and then amplified by amplifying means 6. 
     Certain of these stored voltages make it possible to determine the successive bits of the quantum of a segment (in linear code) that have significance ratios of 2; consequently, the successive voltages injected by the adder for each bit must also have a ratio of 2, which will be obtained by the multiplication function of means 3. The signals supplied by means 3 are then compared, at a voltage V k , in comparator 4, which supplies a logic signal &#34;1&#34; if the difference between these signals and the voltage V k  is positive, and a logic signal &#34;0&#34; if the contrary is true. It should be noted that the function of voltage V k  is to compensate for a bias voltage of the multiplication and storage means 3. These logic signals are transmitted to terminal 14 via logic switching means 5 which furnish the binary signal Q representing the values of the successive bits in the binary word corresponding to the voltage coded, starting with the most significant bit. 
     In the case of linear coding, on the basis of the method described above enabling one bit to be determined in relation to the preceding one, it suffices to add algebraically a fraction of the reference voltage to the voltage previously stored; for this purpose, the analog switching means 1 must effect this algebraic addition and the amplifying means 6 must have a gain k 3  of zero. 
     In the case of non-linear coding, the gain k 3  will be non-zero and will be used to determine the segment to which the voltage for coding belongs. 
     FIG. 2 represents, for positive output values S and output values E, a non-linear transmittance S=F(E) according to the law A, which is the most common compression law in Europe. The real amplitudes E are given on the abscissa, while the compressed amplitudes S are shown on the ordinate axis. The E axis is graduated according to quanta in conformity with the standards of the CCITT (International Telegraph and Telephone Consultative Committee), quanta whose number for the positive and negative portion of the axis of E is equal to 128. For the sake of convenience, the S axis is graduated using an identical scale from 0 to 128, the value 128 having been attributed to the maximum value of S, and a graduation having the same length on both axes. 
     The total curve is naturally symmetrical in relation to the zero. Only the positive portion is represented. It is composed of 8 segments of a line, with the slope of each segment representing half of the slope of the preceding segment, except in the case of the two first segments, Oa and ab, which are co-linear. 
     The points common to two succeeding segments have the following values on the abscissae and ordinate respectively:a: 1 and 16; b: 2 and 32; c: 4 and 48; d: 8 and 64; e: 16 and 80; f: 32 and 96; g: 64 and 112; h: 128 and 128. 
     7 bits are required in order to code 128 quanta; in the present case of an input signal with two polarities, a sign bit with the value &#34;1&#34; is added thereto for a positive signal, and a sign bit with the value &#34;0&#34; for a negative signal. 
     Coding of the different segments of this transmittance, which requires 3 bits, is as follows: Oa=000; ab=001; bc=010; cd=011 and so on up to gh=111. The sixteen quanta of each segment are then coded linearly with 4 bits in the way shown above. 
     In FIG. 3, the input terminal 10, receiving the analog signal for coding V A , is connected to an input, 12, (&#34;+&#34; terminal) of an adder 2, via a switch, 30, actuated by a signal T 1 . Terminal 11 receiving a reference signal V with a value of 3V R  is connected to earth via four series connected resistors, R 1 , R 2 , R 3  and R 4 , whose values are such that R 1  =4R 4  =8R 2  =8R 3 . The reference voltage is used for coding the different segments and for the linear coding of the quanta of each of them. This makes it possible to obtain at terminal 15 common to resistors R 1  and R 2  a reference signal with a value V R , at terminal 16, common to resistors R 2  and R 3 , a reference signal with a value 3/4V R  and, on terminal 17 common to resistors R 3  and R 4 , a reference signal with a value 1/2V R . The reference signals with values 3V R , V R , 3/4V R  and 1/2V R  are connected respectively to the terminal, 12, of the adder 2, via switches 32, 34, 36 and 38, controlled respectively by signals T 22 , T 24 , T 26  and T 28 . These reference signals are also connected to input &#34;-&#34;, 13, of adder 2, respectively via switches 33, 35, 37 and 39; these switches are respectively controlled by signals, T 23 , T 25 , T 27  and T 29 . In addition, a switch, 31, controlled by the signal T 1  serves to connect terminal 13 to earth. This assembly of switches and resistors in association with the &#34;+&#34; and &#34;-&#34; terminals of the adder 2, enables the above-mentioned coefficients k 1  and k 2  to be obtained. 
     The output of adder 2 is connected to the multiplication and storage means, 3, comprising in series a charge transfer device (abbreviated to CTD) composed of five series connected zones, 50, 51, 52, 53 and 54, and a reading device, 9. The CTD is controlled by a clock with two phases, Φ 1  and Φ 2 , and the reading device is controlled by a reading clock Φ L . 
     The output of the reading device 9 supplies in parallel the input of the amplification means, 6, and a first &#34;+&#34; input of a comparator, 4, a second input of which receives a voltage V k . The amplification and switching means, 6, comprise a controlled gain amplifier, 8, controlled by signals T 32 , T 33 , T 34  and T 35 . The latter enable gains of an arithmetical value of 1/2, 3/4, 1 and 3 to be obtained respectively. This controlled gain amplifier, 8, is an operational amplifier whose negative feedback resistance is partially shunted by switches controlled by signals T 32  to T 35 . The output of this controlled gain amplifier 8 is connected to the terminal 12 of the adder 2 via a switch, 40, controlled by a signal T 30 , and to the terminal 13 of the same adder via a switch, 41, controlled by a signal, T 31 . The assembly constituted by the amplification means 6 and adder 2 enables the coefficients k 3  and k 4  mentioned above to be obtained. 
     The output signal of comparator 4 controls the logic switching means, 5, comprising logic circuits, 55 to 64. The output of the comparator is connected to a &#34;data&#34; input, 23, of a D type of asynchronous multivibrator, 55, and to a first input of an AND-gate with two inputs, 56, and to a first complemented input of an AND-gate with two inputs, 57. The multivibrator 55 also receives a signal T 2  at a &#34;clock&#34; input and the signal T 1  at a &#34;set to 1&#34; input; this multivibrator has two outputs, 18 and 19, furnishing respectively signals Q S  and Q S . The two AND-gates 56 and 57, receive respectively at their second inputs signals Q S  and Q S  and have their outputs connected respectively to the two inputs of an OR-gate, 58, the output of which is connected to a &#34;data&#34; input, 24, of an asynchronous multivibrator, 59, of the D type. The multivibrator 59 receives, at a &#34;clock&#34; input, the signal Φ L  and, at a &#34;zero-set&#34; input, the signal T 1  ; the output terminals 14 and 20 of this multivibrator supply signals Q and Q respectively. The output terminal 14 is connected to a &#34;data&#34; input, 25, of a shift register composed of three multivibrators, 60, 61 and 62 of the D asynchronous type and connected in series. This register also receives a signal T 36  at a &#34;clock&#34; input; the inverse outputs of each multivibrator of this register are respectively connected to the three first inputs of an AND-gate, 63, having four inputs, the fourth input of which receives a signal T 12 . The output of AND-gate 63 is connected to a &#34;data&#34; input, 26, of a multivibrator, 64 of the asynchronous D type. The multivibrator 64 receives, at a &#34;clock&#34; input, the signal T 12  and, at a &#34;set to zero&#34; input, the signal T 1  ; this multivibrator furnishes respectively signals α and α to output terminals, 21 and 22. 
     A sequencing generator, 7, generates from a clock signal H, the signals Φ 1 , Φ 2  and Φ L  as well as control signals T 1  to T 21 . 
     Before explaining the operation of the coder in FIG. 3, it is necessary to detail the structure of the CTD as well as describe the control signals. 
     FIG. 4 shows an N channel CTD, composed of five zones, 50 to 54, each comprising 6 cells C 1  to C 6 . Each cell comprises two electrodes respectively controlled by signals Φ 1  and Φ 2  which enable the charges to be transferred from one electrode to another. To simplify the diagram, only the working surface of the electrodes has been illustrated. This working surface must be weighted from one zone to the next but, as the electrodes are identical in width it suffices to weight their lengths. The lengths have a ratio of two to one from one zone to the next; this is equivalent to multiplication factors of 1 for zone 50, 2 for zone 51, 4 for zone 54, and so on. 
     This method of weighting is known and described in the article &#34;Transversal Filtering Using Charge-Transfer Devices&#34; published by Dennis D. BUSS et al. in the IEEE review; Journal of Solid State Circuits, volume SCB, No. 2 of April 1973. 
     FIG. 5 represents the signals Φ 1  and Φ 2 , in phase opposition and with the same recurrence frequency as the clock signal H, as well as the control signals T 1  to T 16 . To enable the latter to be identified, the states of signal Φ 1  have been numbered from S 1  to S 12 , then from W 1  to W 12  and so on. The signals, T 1  to T 10 , and certain of their combinations, which will be explained later on, enable the sign of the voltage for coding to be determined, hence a corresponding bit S, and the segment of the law A in which this voltage is located, hence the corresponding bits A, B and C. They also enable charges corresponding to these bits to be injected underneath the cells C 1  to C 6  of zone 50 of the CTD (FIG. 4). Signals T 11  and T 12  make it possible to establish whether the voltage for coding is in the first segment Oa or in segment ab (of FIG. 2), since, because, these segments being co-linear, the linear coding for segment Oa will be different from the linear coding for the other segments. This linear coding of the different segments is effected with four bits (16 quanta for each segment) which shall be called W, X, Y and Z. The signals T 13  and T 14  enable the most significant bit of the linear coding W to be determined and registered; in the same way, signals T 15  and T 16  have the same function for the bit of the following significance, X. In order to simplify FIG. 5, signals T 17  and T 18 , as well as T 19  and T 20 , have not been represented, but they have respectively the same function as signals T 15  and T 16 , in determining bits Y and Z of the linear code. 
     The other signals are combinations of the preceding signals and other signals supplied by the device of FIG. 3. They are given by the following logic equations: 
     
         T.sub.21 =T.sub.13 +T.sub.15 +T.sub.17 +T.sub.19 
    
     
         T.sub.22 =Q·Q.sub.S ·T.sub.6 
    
     
         T.sub.23 =Q·Q.sub.S ·T.sub.6 
    
     
         T.sub.24 =Q.sub.S ·T.sub.3 +Q·Q.sub.S ·T.sub.9 +T.sub.21 ·Q·.sub.S +I.sub.21 ·Q·Q.sub.S ·α 
    
     
         T.sub.25 =Q.sub.S ·T.sub.3 +Q·Q.sub.S ·I.sub.9 +T.sub.21 ·Q·Q.sub.S +T.sub.21 ·Q·Q.sub.S ·α 
    
     
         T.sub.26 =Q·Q.sub.S ·T.sub.6 
    
     
         T.sub.27 =Q·Q.sub.S ·T.sub.6 
    
     
         T.sub.28 =T.sub.21 ·α·Q.sub.S ·Q+T.sub.9 ·Q.sub.S ·Q 
    
     
         T.sub.29 =T.sub.21 ·α·Q.sub.S ·Q+T.sub.9 ·Q.sub.S ·Q 
    
     
         T.sub.30 =Q·(T.sub.5 +T.sub.8) 
    
     
         T.sub.31 =Q·(T.sub.5 +T.sub.8) 
    
     
         T.sub.32 =Q·T.sub.8 
    
     
         T.sub.33 =Q·T.sub.5 
    
     
         T.sub.34 =Q·T.sub.8 
    
     
         T.sub.35 =Q·T.sub.5 
    
     
         T.sub.36 =T.sub.5 +T.sub.8 +T.sub.11 
    
     
         Φ.sub.L =T.sub.2 +T.sub.4 +T.sub.7 +T.sub.10 +T.sub.14 +T.sub.16 +T.sub.18 +T.sub.20. 
    
     It should be noted that the control signal Φ L  of reading device 9 in FIG. 3 is synchronous, when it is nonzero, with signal Φ 2  of FIG. 5 according to the above logic equation. 
     All these signals are logic signals with two states: &#34;O&#34; and &#34;1&#34;. 
     In addition, the CTD comprises conventional input and output elements, not represented, including an input control electrode which receives the output signal of the adder 2. 
     In order for injection of the charges in the CTD to be in a linear zone, the input control electrode receives a bias voltage V K  and this is this voltage which is applied at the &#34;-&#34; input of comparator 4. This bias voltage also enables positive or negative voltages to be applied to the control electrode. 
     Detailed operation of the device of FIG. 3 is as follows. During state S 1  of signal Φ 1  (FIG. 5), the control signal T 1  closes switches 30 and 31 connecting terminal 13 of the adder 2 to earth via switch 31, and enabling the voltage for coding V A  to be applied to the input control electrode of the CTD via the adder 2 and the switch 30. The signal T 1  sets the outputs Q and α of multivibrators 59 and 64 to &#34;0&#34; and the output Q S  of multivibrator 55 to &#34;1&#34;. Simultaneously, signal Φ 1  enables a quantity of charges proportional to the voltage V A  to be injected beneath the first electrode of cell C 1  in zone 50 of the CTD. During state S 2  (FIG. 5), the signals Φ 1  and Φ 2  enable charges to be transferred from the first electrode to beneath the second electrode of cell C 1 , and, as signals Φ 2  and Φ L  are in state &#34;1&#34; (because Φ L  =T 2  +&#34;0&#34;=T 2  =&#34;1&#34; according to the logic equation above and FIG. 5), they authorize reading of the charges of the CTD by the reading device, 9. The signal read, which has a value of V A  +V K , is compared with the voltage V K  in the comparator 4 which gives a state &#34;1&#34; if V A  is positive and a state &#34;0&#34; if V A  is negative. This logic state is reproduced, at the output terminal 18 of the multivibrator 55 (supplying the signal Q S ) and at the output terminal 14 of the multivibrator 59 (supplying the signal Q), via the gates 56 and 58 because Q S  =&#34;1&#34; during state S 2 , respectively, during the trailing edges of the signal T 2  and the signal Φ L  (clock signals of these multivibrators). The sign bit S thus occurs at terminal 18 and remains there throughout the coding; it therefore also occurs at the output terminal 14 which is that of the coder output. After bit S, bits A, B and C are determined and these bits enable the segments of the compression curve (FIG. 5) to which the voltage to be coded belongs to be determined. 
     The voltages expressed in quanta in FIG. 2 will be related to a reference voltage V R  equal to 8 quanta: thus on the axis of abscissa V a  =1/8V R , V b  =1/4V R , V c  =1/2V R , V d  =V r  and so on up to V h  =16V R . Bit A will be respectively equal to &#34;1&#34; or &#34;0&#34; if voltage V A  is greater than or less than V d . 
     Similarly, bit B, in the case of A=&#34;1&#34;, will be equal to &#34;1&#34; or &#34;0&#34; respectively depending on whether the voltage V A  is greater than or less than voltage V f . If A=&#34;0&#34;, the comparison will be effected in relation to the voltage at point b (FIG. 2). The same procedure will apply to bit C. 
     The process of the corresponding operations is as follows for bit A: unde the first electrode of cell C 1 , in zone 50 of the CTD, during the state S 3  is injected a quantity of charges that is proportional to the voltage -V R  is the sign bit S is equal to &#34;1&#34;, and to +V R  if this is not the case, respectively via switches 35 and 34 controlled respectively by signals T 25  and T 24  (owing to the term T 3  ·Q S  or T 3  ·Q S  of their logic equation). 
     Simultaneously, the signals Φ 1  and Φ 2  enable the charges to be transferred from the second electrode of C 1  to beneath the first electrode of C 2 . 
     During the state S 4 , the charges are displaced by the signals Φ 1  and Φ 2  and are placed underneath the second electrodes of cells C 1  and C 2  (FIG. 4). 
     Simultaneously, as signal Φ L  is in state &#34;1&#34; (because Φ L  =T 4  +&#34;0&#34;=T 4  =&#34;1&#34; according to its logic equation and FIG. 5), it enables reading of the charges of the CTD by the reading device 9. The signal read, the value of which is V A  ±V R  +V K , is compared with the voltage V k  in the comparator 4, which gives a state &#34;1&#34; if V A  ±V k  is positive and a state &#34;0&#34; if this is not the case. This logic state is transmitted to the input of multivibrator 59 by the gates 56 and 58 if the sign bit S is equal to &#34;1&#34;, and the inverse of this state is transmitted by the gates 57 and 58 to the input of the same multivibrator, if the bit S is equal to &#34;0&#34;. In the second case, the output signal of the comparator 4 is inverted, as the voltage V A  is negative, and the result of the comparison has a significance which is inverse to that of the first case (in the second case, if the output signal of the comparator 4 is in state &#34;1&#34;, this means that bit A is in state &#34;0&#34;). 
     In the two cases, the corresponding logic state is reproduced under the terminal 14 of the multivibrator 59, at the time of the trailing edge of the signal Φ L  (or of the signal T 4  in the present case). 
     In order to determine bit B, it is necessary to compare the voltage V A  to the voltage 4V R  if bit A is in state &#34;1&#34;, and with voltage V R  /4 if the contrary is true. As this comparison is effected during a reading of the CTD, the algebraic sum of the new charges injected and of the charges already present must correspond to a voltage read equal to V A  ±4V R  in the first case and to V A  ±1/4V R  in the second case. But it is also possible to effect the above comparisons respectively in the forms 1/4V A  ±V R  and 4V A  ±V R . In FIG. 3, the latter solution has been chosen. 
     These algebraic voltage sums are effected by applying respective voltages -3/4(V A  ±V R )±3/4V R  and 3(V A  ±V R )±3V R  to the input control electrode of the CTD. These operations are effected in two stages; first of all, -3/4(V A  ±V R ) or 3 (V A  ±V R ) is injected, according to the case, and then ±3/4V R  or ±3V R  according to the case. This therefore necessitates two states Φ 1  at &#34;1&#34; which will be separated by a state Φ 2  at &#34;1&#34; only used for charge transfer in the CTD. 
     During the state S 5  of the signal Φ 1 , the voltage V A  ±V R , present at the output of the reading device 9, is applied to the input of the variable gain amplifier, 8, whose gain, k 3 , controlled by the signals T 33  or T 35  (depending on the case) will be respectively equal to 3/4 or 3. The output signal of this amplifier is applied to the terminal 12 for a positive equivalent gain and to the terminal 13 for a negative equivalent gain, via the corresponding switches 40 and 41 (respectively controlled by the signals T 30  and T 31 ). The adder 2 then transmits the voltage received to the input control electrode of the CTD which functions as in the case of injection of voltage ±V r  : injection of new charges and transfer of the charges already present from one electrode to another. 
     During state S 6 , the charges that are present beneath the electrodes are transferred from one electrode to the succeeding one. 
     During state S 7 , one of the signals, T 22 , T 23 , T 26  and T 27 , controlling the corresponding switches 32, 33, 36 and 37, enables one of the voltages, +3V R , -3V R , +3/4V R  and -3/4V R  to be applied to the input control electrode of the CTD, via the adder 2, depending on whether V A  is positive or negative and whether bit A is equal to &#34;1&#34; or to &#34;0&#34;. Simultaneously, the charges present in the CTD are transferred. 
     During state S 8 , the charges are again transferred and are read by the reading device 9 controlled by the signal Φ L  (Φ L  =&#34;0&#34;+T 7  +&#34;0&#34;=T 7  =&#34;1&#34; according to the logic equation of Φ L  and FIG. 5). The output voltage of this device is then compared with the voltage V k  in comparator 4 and, as before, the bit B occurs at terminal 14 of the multivibrator 59. 
     Operation is the same in the case of bit C and the process takes place during states S 9 , S 10 , S 11  and S 12  of signal Φ 1 . 
     There is a special case if the bits A, B and C are equal to &#34;0&#34; in which case the voltage for coding V A  is located on segment Oa. As linear coding in sixteen quanta will be different, it is necessary to detect this combination of bits A, B and C. This is the function of the logic circuits 60 to 64. The shift register, composed of the three multivibrators 60, 61 and 62 and controlled by the clock signal T 36 , successively registers bits A, B and C respectively during states S 5 , S 9  and W 1  via its &#34;information&#34; input 25. The inverse output signals of each multivibrator are transmitted to the &#34;information&#34; input 26 of multivibrator 64 via the AND-gate 63, when the signal T 12  is in state &#34;1&#34; i.e. during the state W 2 . The state thus transmitted will be &#34;1&#34; only if bits A, B and C are in &#34;0&#34; state. This particular case will be reproduced at the terminal 21 of multivibrator 64 by the signal α which will change to &#34;1&#34; with the trailing edge of the clock signal T 12 . 
     During state S 12 , the charges corresponding respectively to the bits C, C, B, B, A and S are stored under the second electrodes of cells C 1  to C 6  in zone 50 of the CTD (FIG. 4) controlled by the signal Φ 2 . 
     During states W 1  to W 12 , the charges stored beneath the electrodes of zone 50 of the CTD (FIGS. 4 and 5) are respectively transferred beneath those of zone 51; as the working surface of the electrodes is doubled, any corresponding voltage that is read by reading device 9 will be doubled. 
     The duration of the latter states is also used to determine, in linear coding, the most significant bit W. 
     In order to determine the bit W, it is necessary to proceed as in the case of linear coding. 
     If, for example, the bits A, B and C are in state &#34;1&#34;, the corresponding point on the compression curve in FIG. 2 is point g, and the bit W is obtained by comparing the voltage V A  with the voltage corresponding to the middle of segment gh (that is to say by carrying out the half- scale test). 
     The comparison to be effected will therefore be V A  -96 quanta i.e. V A  -12V R  (as the voltage V R  is selected as equal to 8 quanta) that is to say 2(1/8V A  -V R )-V R  allowing for the term 2(1/8V A-V   R ) which is stored in zone 51 of the CTD (FIG. 4); the number 2 that is a factor of the term (1/8V A  -V R ) is due to the fact that the ratio of the working surfaces of the electrodes of zones 50 and 51 of the CTD is 2:1. 
     If, for example, bits A and B are in state &#34;1&#34; and if bit C is in state &#34;0&#34;, the corresponding point on the curve of FIG. 2 is point f, and, in this case, bit W is obtained by comparing voltage V A  with the voltage corresponding to the middle of segment fg; this is done by effecting the comparison V A  -48 quanta, or V A  -6V R , or again, 2(1/8V A  -V R )+V R  /2 for the same reason as above. 
     These operations are carried out in the above two zones by injecting respectively into zone 50 of the CTD a voltage -V R  and a voltage +V R  /2. 
     These voltages are applied to the input control electrode of the CTD during the state W 11 , via adder 2 and the respective switches 35 and 38. 
     During state W 12 , the voltages corresponding to the charges stored in the CTD are read by the reading device 9 controlled by the signal Φ L . The output voltage of this device is treated in the same way as before (in the case of bits A, B and C), and supplies the bit W to terminal 14 of the multivibrator 59 during the trailing edge of signal Φ L . 
     During states X 1  to X 12  the charges stored under cells C 1  to C 16  in zone 51 of the CTD (FIG. 4) are respectively transferred beneath those of zone 52, and those stored beneath cells C 1  to C 6  of zone 50 are respectively transferred beneath those of zone 51. 
     In order to determine bit X, it is necessary to carry out the quarter or three-quarter scale test in accordance with the linear coding method described above. 
     But, in the case of bits X, Y and Z of the linear coding, experience has shown and calculations have confirmed that it suffices to apply to the input control electrode of the CTD (zone 50) a voltage ±V R  (+ or - depending on whether the preceding bit is equal to &#34;0&#34; or &#34;1&#34;) if this bit C is equal to &#34;1&#34;, and a voltage +V R  /2 if bit C is equal to &#34;0&#34;. However, in the particular case wherein bits A, B and C are zero, a voltage ±V R  must be applied. 
     When coding of voltage V A  is completed, the charges corresponding to the bits S, A and C are stored in zone 54 of the CTD (FIG. 4), while those corresponding to bit W and stored in zone 53, those corresponding to bit X in zone 52, those corresponding to bit Y in zone 51 and those corresponding to bit Z in zone 50. 
     On the basis of the functioning of this coder according to the compression law A and of its design (FIGS. 3 and 4), the design and operation of a linear code can be deduced as follows. 
     Zones 50 to 54 of the CTD only have one cell each since the bits A, B and C are no longer used. The amplifying means 6, as they are used above only for the coding of bits A, B and C, are now superfluous. 
     One part of the logic switching means 5 including the logic operators 60 and 64 enabling the combination of bits A, B and C in &#34;0&#34; state to be detected are also to be dispensed with. Switches 32, 33, 36 and 37, as well as their respective control signals, are also superfluous. 
     Certain signals are no longer used for this linear coding, these are the following: signals T 3  to T 12  for determining bits A, B and C, signals T 22 , T 23 , T 26 , T 27 , T 30  and T 31  controlling the switches already discarded, signals T 32  to T 35  for controlling the variable gain amplification means 8, the clock signal T 36  of the shift register composed of multivibrators 60 to 62. It should also be noted that signals Φ 2  and Φ L  become identical. 
     The device according to FIG. 1 also allows other compression laws to be obtained, in particular the law μ, which is very common to North America, which is represented in FIG. 6. 
     FIG. 6 represents, for, positive input values E and output values S, a transmittance S=F(E) which is non-linear, in accordance with the μ compression law. The real amplitudes E are represented on the axis of the abscissae, while the compressed amplitudes S are given on the ordinate axis. The E axis is graduated according to standardized quanta (in conformity with the standards of the CCITT) whose number for each polarity of E is equal to 128. These graduations are the same as in the case of law A with a zero displaced by 33 standardized units. The ordinate axis has been graduated in the same way as in the case of the law A. 
     As in the case of law A, the total curve is symmetrical in relation to the zero. The positive portion, which is all that it is necessary to describe, comprises 9 segments of a line; the slope of each segment is half that of the preceding element. 
     The points, a, b, c, d, e, f, g, h, i, common to two succeeding segments, have the following respective abscissae and ordinate values: a: 34/64 and 1; b: 1 and 16; c: 2 and 32; d: 4 and 48; e: 8 and 64; f: 16 and 80; g: 32 and 96; h: 64 and 112; i: 128 and 128. 
     The last eight are coded with three bits. Their coding is identical to that of the law A (000 for the segment ab and so on). Each segment is also coded with four bits (sixteen quanta per segment). 
     The coding of this law is effected using the circuits of the FIG. 7. 
     In FIG. 7, the analog switching means, 1, the adder, 2, the multiplication and storage means, 3, the amplifier means 6, the comparator 4 and the logic switching means, 5, are present as in FIG. 3 and are connected in the same way; in addition, all these sub-assemblies are structurally identical, apart from the following differences. 
     The analog switching means, 1, differ from those of FIG. 3 in that they comprise, in addition to the components of the latter, a resistive divider composed of two series connected resistors, R 5  and R 6 , connecting the input terminal 11 to earth. These resistors have values such that their common terminal, 23, supplies a reference voltage with a value (17/256)V R  which is applied to terminals 12 and 13 of the adder 2 via corresponding switches, 42 and 43, respectively controlled by signals Q S  and Q S . The logic switching means, 5 are different from those in FIG. 3 in that logic operators 60 to 64 and control signals T 12  and T 36  are discarded. 
     This device functions in a way analogous to that of the device in FIG. 3, with the following differences. As law μ does not comprise co-linear segments, it does not require detection of the combination &#34;000&#34; of the bits A, B and C (hence the elimination of logic operators 60 to 64). 
     Consequently, certain switch control signals are modified; these are as follows: 
     
         T.sub.24 =Q.sub.S ·T.sub.3 +Q·Q.sub.S ·T.sub.9 +T.sub.21 ·Q·Q.sub.S 
    
     
         T.sub.25 =Q.sub.S ·T.sub.3 +Q·Q.sub.S ·T.sub.9 +T.sub.21 ·Q·Q.sub.S 
    
     
         T.sub.28 =T.sub.21 ·Q.sub.S ·Q+T.sub.9 ·Q.sub.S ·Q 
    
     
         T.sub.29 =T.sub.21 ·Q.sub.S ·Q+T.sub.9 ·Q.sub.S ·Q 
    
     In addition, the displacement of the zero of the axis of the abscissae (by a value of (17/256)V R ) of the curve of law μ (FIG. 6) in relation to the curve of law A results in the application to the input control electrode of the CTD, during state S 3 , of a voltage -V R  +(17/256)V R  if the voltage to be coded V A  is positive, and a voltage +V R  -(17/256)V R  if the voltage V A  is negative. The additional positive or negative voltage (17/256)V R , in relation to the case of the law A, is transmitted respectively via the switch 42 and the adder 2, or via the switch 43 and the adder 2. 
     Injection of the voltages k z  V and k 3  (V A  +k 4  V) enabling determination of coding bits B and C, has been effected in two stages: that is to say in two semi-periods of the signal Φ 1 . However, it is possible to inject these voltages in a single operation insofar as the error resulting from the interaction of these two voltage sources is disregarded. An improvement can be made, when injecting in a single operation, by providing an adder at each output terminal of the analog switching means, 1. These adders then receive respectively at their &#34;-&#34; inputs one of the output signals of the means 1 and have their &#34;+&#34; inputs connected to earth. 
     The invention is not limited to the form of embodiment described and represented; in particular, the device can comprise variants. 
     It should be noted that these codings have been described as a function of curves of compression with 8 segments, but it is possible to deduce immediately therefrom from the structure necessary for compression curves comprising a number p of segments, characterized by the relationships p=2 n  if n is the number of bits the significance of which enables a segment of the curve of p segments to be determined. In this case a number M of bits is required, with M=1+n+k, wherein k is the number of bits whose significance makes it possible to determine a quantum of each segment, and 1 represents the bit coding the sign. 
     The structure of the CTD is then a function of M and comprises k+1 groups of m cells, one cell being constituted by q electrodes q=2 or 3. In order to apply a voltage to the input control electrode of the CTD in a single operation, m=n+1 cells (n≧0) will be needed and, in order to do so in two stages (counting from the second coding bit of the segment) 2n cells (n≧0) will be required. 
     If the law of compression is such that 2 n  ≧p≧2 n+1 , m=n+1 cells will be required for injection in a single operation and m=2(n+1) cells for an operation in two stages. 
     The different control signals of the CTD relate to an N channel charge transfer device, but the same result will be obtained with a P channel charge transfer device. In addition, if the coder described comprises a CTD controlled by a two-phase clock, it is within the grasp of one skilled in the art to replace it by a CTD controlled by a three-phase clock. 
     It should be noted that the value of the voltage V k  is applied to the &#34;-&#34; terminal of the comparator 4 has not in practice the value V k  but the value k 5  V K  where k 5  is a factor dependent upon the amplification of reading means 9 and upon any compensations of shift voltage for the amplifers of these reading means. 
     An analog-digital coder according to the invention can be used, in particular, in systems for the transmission of information that requires said information to be digitalized. 
     Of course, the invention is not limited to the embodiments described and shown which were given solely by way of example.