Differential linear to digital translator
BACKGROUND OF THE INVENTION 
     The invention relates to interfacing circuitry for converting linear logic signals such as ECL logic to digital logic such as TTL. 
     A common technique employed in large scale integrated (LSI) digital circuits to achieve maximum speed is to utilize linear circuit operation internally which is buffered at the inputs and outputs for digital compatability. The digital to linear operation at the input can readily be achieved by utilizing a common single ended differential amplifier. However, the linear to digital translation at the output is considerably more difficult because the linear logic levels are referenced to the positive supply while the digital logic levels are referenced to the negative supply or ground in the case of TTL type logic. Further, difficulty is encountered with power supply variations which have the effect of varying the linear logic levels and hence makes the linear to digital translation even more difficult. It would thus be advantageous to provide a linear to digital translator which can perform very fast linear to digital translation which is immune from power supply variations. 
     A translation arrangement which provides, independent of power supply variations, interfacing between a linear circuit and TTL logic senses the differential voltage in the linear circuit, which for the purposes of this discussion will be designated as ECL logic. By sensing the differential output voltage of the ECL circuit as compared to sensing only a comparatively large single ended voltage swing, the translator is made insensitive to variations in power supply voltage. Differential sensing of the input also provides the further advantage of excellent common mode rejection making the translator substantially immune to common mode noise signals from the ECL circuit stage. 
     A prior art ECL to TTL converter of the differential type is described in U.S. Pat. No. 4,045,690 issued to Tam on Aug. 30, 1977. The Tam converter or translator as it is sometimes termed is comprised of two parallel current paths terminating in a current mirror. A first current path includes resistor R 1  and transistor Q 3 , with the other current path including resistor R 2  and transistor Q 4 . The resistors are of equal value and transistors Q 3  and Q 4  are matched. These current paths connect to the current mirror comprised of transistors QD and Q 2 . While the Tam device was a step forward in the art of linear to digital translation, it exhibits several deficiencies. For example, the Tam device utilizes a saturating device (Q 1 ) which because it saturates reduces the speed of translator operation. Further, Tam requires biasing of the translator output at the threshold of the TTL gate or buffer in order to achieve high speed operation. That is, the Tam TTL gate, which has a two diode voltage drop threshold level, is interfaced with the translator whose output is maintained at a two diode voltage drop. Switching of the TTL gate is effected by increasing or decreasing the two diode drop voltage output of the translator by ΔV, the differential input voltage. Such a biasing arrangement can result in undesirable oscillation of the translator output as well as degradation of the TTL gate output. A still further drawback of the Tam device involves crossover performance whenever the differential voltage, ΔV, changes. Crossover refers to the switching of the converter output and thus the state of the TTL buffer in response to a reversal of the input differential voltage. Proper crossover response assures that the buffer output transistors turn on in response to a logic low input from the ECL gate and turn off in response to a logic high input. 
     The present invention overcomes the various drawbacks of the Tam type differential ECL to TTL translator to produce a high speed linear to digital translation with improved crossover response and without TTL output degradation, while maintaining the advantages of differential linear digital translation exhibited by Tam. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide an improved, very fast acting linear to digital translator immune from power supply variations. 
     It is a further object of the invention to provide a linear to digital translator which is responsive to a differential input voltage and which optimizes crossover performance when the differential voltage, ΔV, changes. 
     It is still further object of the invention to provide a linear to digital differential translator which will not cause high level degradation of the digital buffer output. 
     It is another object to provide a linear to digital differential translator immune from output oscillations. 
     These and other objects as will become apparent from a reading of the preferred embodiment of the present invention are accomplished with the unique linear to digital differential translator of the present invention. This translator includes parallel current paths with one of the circuit paths including resistance R 1 , the other including resistance R 2 . R 1  and R 2  are of unequal values selected to improve circuit crossover performance. Preferably, the ratio R 2  /R 1  is made equal to 2 V CC  -7θ-ΔV/2 V CC  -6θ-ΔV, where θ=V BE . The parallel circuit paths which include only non-saturating active devices are connected to a current mirror which also includes only non-saturating devices. Since none of the active devices of the translator saturate, delay time is reduced. In a embodiment of the invention a multi-emitter device is used in one of the circuit paths, the emitters being connected across the collector and base inputs of the translator output transistor. This connection assures clamping of the translator output transistor to one diode drop, V BE , when it is in its low level. Saturation of the translator output transistor is thus prevented while assuring the integrity of the TTL buffer logic high level output. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The FIGURE is a schematic diagram of an embodiment of the linear to digital translator of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The FIGURE illustrates the preferred embodiment of the linear to digital translator of my invention. For purposes of explanation, a logic one or high level is defined as a 5.0 volt input to the base of the transistor Q 1 . When 5.0 v are applied to the base of Q 1 , a potential of 4.2 v for example appears at the base of transistor Q 2  by action of the ECL gate. The ECL gate is of conventional construction and thus not illustrated in detail. A logic zero or low level is defined as a 4.2 volt input to the base of this transistor Q 1  with a 5.0 v input to the base of Q 2 . Thus, a linear logic high level is defined as V B1  =5 volts and V B2  4.2 volts and a logic low level as V B1  =4.2 v and V B2  =5.0 v. The differential voltage, ΔV, is defined as V B1  -V B2 . Thus, a logic high level occurs when ΔV=0.8 volts and a logic low level occurs when ΔV equals -0.8 volts. 
     The translator may be viewed as being comprised of two parallel paths terminating in a current mirror comprised of diode D 1  and transistor Q 4 . A first path includes the transistor Q 1 , resistance R 1  and multi-emitter device Q 3 . The second path includes the transistor Q 2 , resistance R 2  and diode D 2 . The transistors Q 1  and Q 2  may be matched. However, the values of resistance R 1  and R 2  are made unequal and preferably the ratio of R 2  /R 1  is made equal to 2 V CC  -7θ-ΔV/2 V CC  -6θ-ΔV, where θ=V BE . Thus R 2  =xR1 where x=(2 V CC  -7θ-ΔV)/(2 V CC  -6θ-ΔV). The ratioing of R 2  to R 1  provides improved crossover performance on the switching of ΔV in response to a logic level change. Crossover is defined as the point when V CE4  goes from 1 V BE  (Q 5  and Q 8  are off) to 2 V BE  (Q 5  and Q 8  are on) or vice versa. Crossover performance improvement realized through the instant invention may be better understood from the following. 
     Let it first be assumed that R 1  =R 2  32 2 K and that ΔV=0.8 V, V CC  =5 V=V B1  and V B2  =4.2 V. 
     When making a transition from V B1  =5 V→4.2 V and V B2  =4.2 V→5.0 V the following occurs: 
     
         At V.sub.B1 =4.8 V and V.sub.B2 =4.4 V ##EQU1## V.sub.CE4 is at 0.8 V with ΔV=0.8 by reason of the clamping action of multi-emitter device Q.sub.3 as previously explained herein. 
    
     Since I 1  &gt;IR 2 , Q 5  and Q 8  remain off, as they would be when 
     
         V.sub.B1 =5 V and V.sub.B1 =4.2 V 
    
     At V B1  =4.6 V and V B2  =4.6 V when the crossover point is balanced meaning V B1  and V B2  have each changed an equal amount but in opposite directions. 
     
         I.sub.1 =(4.6-2.4)/2K=2.2 V/2K=1.1 MA 
    
     
         I.sub.2 =(4.6 V-2.4 V)/2K=2.2 V/2K=1.1 MA 
    
     I 1  now equals I Q2  and Q 5  and Q 8  remain off. 
     Assume next the conditions when the transition has been completed and V B2  =5.0 V and V B1  =4.2 V. V CE4  now equals V BE5  +V BE8  ##EQU2## 
     Thus, when R 1  =R 2  and V B2  =5 v and V B1  =4.2 v transistor Q 5  will be biased exactly at threshold and not have any margin for turn on. To guarantee that Q 5  will turn on fully when V B2  =5 v and V B1  =4.2 v, R 2  &lt;R 1  ; that is R 2  =xR 1 , where 0&lt;=&lt;1. 
     To determine the preferable ratio R 2  /R 1 , consider that the crossover point is balanced when V CE4  =1.5 V BE  since during crossover V CE4  translates between 1 V BE  and 2 V BE  or vice versa. Ideally crossover balance occurs when V B1  and V B2  have changed by equal and opposite values such that V B1  =V B2 . In the case under consideration V B1  =V B2  at 4.6 v. Since V CC  =5.0 v and ΔV =0.8, V B1  =V B2  =V CC  -ΔV/2 
     Therefore; since I 1  =I 2  and V CE  =1.5 V BE  at crossover balance: ##EQU3## 
     Defining θ=V BE  ##EQU4## 
     For θ=0.8 v, ΔV=0.8 v and V CC  =5.0 v, R 2  =0.8R 1  to assure proper crossover performance. 
     The multi-emitter device Q 3  provides a one diode drop, V BE , across the collector-base circuit of Q 4  when this transistor&#39;s output is low. This prevents the transistor from going into saturation but maintains the base of transistor Q 5  at a sufficiently low level to prevent the transistor Q 5  from substantially conducting. 
     More specifically, a ΔV of 0.8 volts results in a collector potential at transistor Q 4  of approximately 0.8 volts, or 1 V BE  which is insufficient to turn transistor Q 5  substantially on. The value of V BE  in a transistor is a function of current density associated with the emitter. In the process of device transistor design the actual size of emitters is easily set depending upon the desired current operation. For purposes of explanation, devices of the inventive circuit will be assumed to have been designed with a V BE  of 0.8 v. However, the invention is not limited to any specific device designs, and devices with other values of V BE  may be substituted without departing from the spirit or scope of the invention. With the transistor Q 5  substantially off, the transistor Q 8  is nonconducting, causing the TTL buffer output, D out , to rise to a relatively high potential corresponding to a TTL logic one or high level. Thus, with the circuit of the present invention, Q 4  conducts without saturating since the potential drop across transistor Q 4  in its low condition is clamped to one diode drop, V BE . This level is sufficiently low that transistor Q 5  is maintained in a substantially nonconducting state and thus preventing oscillation problems which occur if transistor Q 5  was biased at threshold. 
     An ECL logic low input represented by a ΔV of -0.8 volts and which results from V B1  being at 4.2 volts and V B2  at 5 volts, causes the collector of Q 4  to rise sufficiently to bias the transistor Q 5  into substantial conduction, causing transistor Q 8  to also conduct. With Q 8  conducting, the TTL buffer output D out  assumes the TTL logic low level which is substantially ground potential. 
     The transistors Q 5 , Q 6 , Q 7  and Q 8  as well as the resistor R 5 , R 6 , R 7  and R 8  comprise the TTL buffer. Preferably the TTL buffer is integrated into the translator. As a result the achievable delay time is reduced by providing both linear operation of the first portion of the buffer as well as minimizing the sequential logic steps required for switching. 
     The diode D 2  is provided to match the diode drop of Q 4  in the current mirror as well as provide temperature compensation balancing between the two sides of the translator. Diode D 3  is provided to clamp the collector of Q 5  to 2 V BE  to prevent the saturation of Q 5  whenever Q 5  is substantially on. 
     In operation, a TTL logic high level is produced when transistor Q 8  is nonconducting raising the buffer output, D out , to approximately V CC  -2 V BE  which equals approximately 3.4 volts. A TTL logic low level occurs when Q 8  conducts driving the output D out  to near ground potential. The conductive state of the transistor Q 8  follows that of transistor Q 5 . Thus, when transistor Q 5  is made to substantially conduct, transistor Q 8  is conducting producing a TTL logic low output; further, when transistor Q 5  is not substantially conducting transistor Q 8  similarly does not conduct producing a TTL logic high level. 
     For purposes of explaining the operation of the translator it will be assumed that the value of R 1  =2K and R 2  =0.8R1 or 1.6K. These values are typical of those desired to provide fast switching with reasonable power consumption. If an ECL logic high input is received, V B1  =5 volts and V B2  =4.2 volts. Therefore: ##EQU5## 
     However, V CE4  =V BE3  =0.8 v since with V B1  at 5.0 v, the collector and base of Q 3  are at 1.6 v, which is sufficient to render Q 3  conductive. With Q 3  conducting, Q 4  conducts with the drop across its collector-emitter path being clamped to 1 V BE . To understand the clamping effect, consider that when Q 4  is substantially on, and I 1  &gt;I 2 , Q 3  is conducting with current being present in both its emitters E 3A  and E 3B . The calculation of these currents is set out hereinafter. At this point it should be noted that V CE4  can not drop below 1 V BE  without blocking the path for its base current through emitter E 3B  of Q 3 . In other words; V BE3B  +V BE4  must equal V BE3A  +V CE4 . Since B BE3A  =V BE3B , V CE4  =V BE4  or 1 V BE . 
     With V CE4  =0.8 v. 
     
         I.sub.2 =(4.2 v-2.4 v)/1.6×10.sup.3)=1.12 MA 
    
     To determine the emitter currents I E3A  and I E3B  ; I 2  =ID 2 , since diode D 3  is back biased. 
     Since diode D 1  and transistor Q 4  comprise a current mirror, the current ID 1  =ICE 4  =(I 1  +I 2 )/2; the β (current gain factor) of Q 4  being assumed to be much greater than one making the base current negligible. 
     
         (I.sub.1 +I.sub.2)/2=(1.3 MA+1.12 MA)/2=1.12 MA 
    
     Therefore, IE 3A  =1.21 MA-1.12 MA=0.09 MA; IE 3B  =I 1  -IE 3A  =1.3 MA-0.09 MA=1.21 MA=ID 1 . 
     Assume now that VB 2  =5.0 v and V B1  =4.2 v. ##EQU6## 
     Let it now be assumed that V B2  =5.0 v and V B1  =4.2 v with the values of R 1  and R 2  remaining unchanged at 2K and 1.6K, respectively. 
     V CE4  now equals V BE5  +V BE8  for I 2  is now greater than I 1 , and all collector current for Q 4  is derived from D 2 , none from emitter E 3A . Since Q 4  is operating in its linear region, its collector voltage is free to rise up to the point where Q 5  and Q 8  will turn on. At this point a parallel current path exists which clamps the high level of V CE  of Q 4  to 2 V BE . 
     Therefore, with V CE4  =V BE5  +V BE8  ##EQU7## 
     There is substantially no current flow from the emitter E 3A  of Q 3  for when V CE4  raises above 1 V BE , the V BE3A  is debiased. In fact, each 60 MV rise of V CE4  decreases the current in emitter E 3A  of Q 3  by a factor of ten. Thus, if I E3A  =0.2 MA when V CE4  =1 V BE , a rise in V CE4  to V BE  +120 MV reduces I E3A  to 0.002 MA. 
     Since D 1  and Q 4  comprise a current mirror; 
     
         I.sub.CE4 =I.sub.D1 =I.sub.D2 =0.9 MA. (Q.sub.4 being a high β transistor) 
    
     
         I.sub.D3 =I.sub.2 -I.sub.D2 =1.12 MA-0.9 MA=0.22 MA. 
    
     Thus, with Q 4  substantially off and V CE4  being clamped to 2 V BE , Q 5  and Q 8  are on. Q 6  will then be on in its linear mode and Q 7  will be substantially off, causing D out  to assume its low level. To understand the operation of Q 6  and Q 7  consider that whenever Q 5  and Q 8  are on, V C5  of Q 5  equals V BE8  +V BE5  +V D2  -V D3  =2 V BE . 
     V B7  will then be equal to 2 V BE  V BE6  =0.8 v. Since D out  will be a minimum of approximately 0.2 v, (the offset voltage of Q 8 ) the voltage across the base-emitter of Q 7  will be 0.6 v and it will be off in the sense it will minimally conduct relative to the other devices. 
     There has been described an improved differential linear to digital translator to connect ECL level signals to TTL levels. The differential nature of the translator effects voltage compensation. As the power supply varies, the change in V CC  is seen across R 1  and R 2 . As the current increases or decreases in R 1  and D 1 , the current mirror arrangement effects a change in the current required of Q 4  and sinks the increase or decrease in current through R 2 . Temperature compensation is also provided due to the diode matching in the two current branches. Note that three diodes are associated with the current through both R 1  and R 2 . This condition is true because the low level of the collector of Q 4  is clamped to a diode. 
     The inventive circuit is designed to eliminate the need for biasing the translator output at the threshold of the TTL gate to achieve fast action. In fact, the translator output is biased well below the TTL gate threshold preventing undesirable oscillations of the translator output. Very fast acting circuit operation is achieved by minimizing the saturating devices. Q 4  is maintained in a linear mode by the clamping emitter E 3A . Q 5  is maintained linear by the diode D 3 . The output device Q 8  must saturate to provide a low level logic output. The Darlington driver device Q 6  must transiently saturate to prevent the saturation of Q 7 .