Semiconductor memory device
BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device incorporating MOS static RAM cells. 
     In general, each of the MOS static memory cells comprises a bistable flip-flop circuit which uses four or six transistors per bit. That is, the memory cell comprises a pair of driver transistors which are cross-coupled to each other, a pair of load resistors or load transistors, and a pair of transfer transistors connected to one word line and to one pair of bit lines. In this memory cell, only one of the driver transistors is turned on to correspond to memory data &#34;1&#34; or &#34;0&#34;. 
     In order to read the cell, the transfer transistors are turned on by changing the potential of the word line and the data on the driver transistors is transferred to the bit lines. On the other hand, writing is achieved by also turning on the transfer transistors and then applying the proper voltage to the bit lines. 
     One conventional semiconductor memory device of a MOS static type incorporates a large number of such memory cells arranged along rows and columns which are orthogonal to each other. In addition, the device comprises a plurality of word lines each connected to the memory cells belonging to one corresponding row, a plurality of pairs of bit lines, each pair connected to the memory cells belonging to one corresponding column, a plurality of pairs of load transistors, each pair connected to one corresponding pair of the bit lines, and a plurality of pairs of bit drivers, each pair connected to one corresponding pair of the bit lines. In this case, selection of one cell among the memory cells is effected by selecting one of the word lines and one pair of the bit lines. 
     However, in the above-mentioned conventional device, when one memory cell is selected so as to read the data stored in the cell, transfer transistors of other non-selected memory cells belonging to the same word line of the selected cell are also turned on, so that currents flow from a power supply through the non-selected memory cells to another power supply (ground). Therefore, since a large number of non-selected memory cells are connected to one selected word line, power dissipation therefor is high. 
    
    
     SUMMARY OF THE INVENTION 
     It is the principal object of the present invention to provide a semiconductor memory device incorporating MOS static memory cells with low power dissipation. 
     According to the present invention, there is provided a semiconductor memory device comprising: a first power supply; a plurality of word lines; a plurality of word drivers, each connected to a corresponding one of the word lines; a plurality of pairs of bit lines connected to the first power supply; a plurality of pairs of load MOS transistors connected between the first power supply and each of the pairs of bit lines; a plurality of pairs of bit drivers, each pair connected to one of the pairs of bit lines, and controlled by column selection signals; a plurality of memory cells of an MOS static type, each connected to one of the word lines and to one of the pairs of bit lines; and current switching means, connected between the first power supply and each of the pairs of bit lines and controlled by the column selection signals, for supplying a larger current to the pairs of bit lines during the selected mode than the non-selected mode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will now be more clearly understood from the following description contrasted with the conventional device and with reference to the drawings, wherein: 
     FIG. 1 is a block circuit diagram illustrating one conventional semiconductor memory device; 
     FIG. 2 is a circuit diagram of the memory cells C 00  and C 01  of FIG. 1; and 
     FIG. 3 is a block diagram illustrating an embodiment of the semiconductor memory device according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1, which illustrates one conventional semiconductor memory device, a memory device comprises a plurality of memory cells C ij  (i, j=0, 1, . . . , n-1) which are arranged in an n row, n column matrix. Each of the memory cells, for example, the memory cell C 00 , is connected to one word line WL 0  which is selected by a word driver (not shown) and to one pair of bit lines BL 0  and BL 0  which are selected by transistors Q B0  and Q B0  &#39;. In this device the transistors Q B0  and Q B0  &#39; are column selecting gates which are controlled by a column selection signal Y 0 . In addition, all the bit lines BL 0 , BL 0 , BL 1 , BL 1 , . . . , BL n-1 , BL n-1  are connected to a power supply V DD  through load transistors Q L0 , Q L0  &#39;, Q L1 , Q L1  &#39;, . . . , Q L ,n-1, Q L ,n-1 &#39;, respectively, and to a sense amplifier SA through the transistors Q B0 , Q B0  &#39;, Q B1 , Q B1  &#39;, . . . , Q B ,n-1, Q B ,n-1 &#39;, respectively. 
     FIG. 2 is a circuit diagram of the memory cells C 00  and C 01  of FIG. 1. In FIG. 2, each of the memory cells C 00  and C 01 , which are, of course, the same as the other memory cells of FIG. 1, comprises a pair of transistors Q 1  and Q 2  cross-coupled to each other, a pair of load resistors R 1  and R 2 , and a pair of transfer transistors Q 3  and Q 4 . In this case, a drain and a gate of the transistor Q 1  are connected to a gate and a drain of the transistor Q 2 , respectively. In addition, the transfer transistors Q 3  and Q 4  are connected to the bit lines BL 0  and BL 0 , respectively, and the gates of the transistors Q 3  and Q 4  are connected to the word line WL 0 , commonly. In FIG. 2, it should be noted that two gate-drain connected transistors can be used as the load resistors R 1  and R 2 . 
     The write operation for such a memory cell is effected by forcing the potentials as nodes N 1  and N 2  to be high and low, respectively, or vice versa. For example, in the memory cell C 00 , when the potentials at the nodes N 1  and N 2  are forced to be high and low, respectively, the transistors Q 1  and Q 2  remain in the conductive and non-conductive states, respectively. 
     Next, the read operation for such a memory cell will now be explained. For example, when the data stored in the memory cell C 00  is read out, the potential of the word line WL 0  is forced to be high by a word driver (not shown), so that the transfer transistors Q 3  and Q 4  of the cell C 00  conduct. As a result, the potentials at the nodes N 1  and N 2  of the cell C 00 , which potentials are dependent upon the memory data &#34;1&#34; or &#34;0&#34; are transmitted to the bit lines BL 0  and BL 0 , respectively. In addition, in this case, the potential of the column selection signal Y 0  is forced to be high, so that the transistors Q B0  and Q B0  &#39; are conductive. Therefore, the difference in potential between the bit lines BL 0  and BL 0  is amplified by the sense amplifier SA. 
     However, in this state, even in the memory cell C 01 , the transfer transistors Q 3  Q 4  become in the conductive state, since the potential of the word line WL 0  is high. As a result, as illustrated by a dotted line X, a current flows from the power supply V DD , through the transistor Q L1  &#39;, the bit line BL 1 , the transistors Q 4  and Q 2  of the cell C 01 , to the ground V SS , if the potentials at the nodes N 1  and N 2  are high and low, respectively. In other words, when the potential of one word line is high, the same type of a current flows through each of the other non-selected memory cells which belong to said word line. 
     Returning to FIG. 1, usually, the semiconductor device is of a large scale, which is for example, 4,096 or 16,384 bits. Therefore, in the case of a 16,384 bit (256×256) memory device, such a current flows through each of 225 non-selected memory cells belonging to one word line. This results in a high power consumption. 
     FIG. 3 is a block circuit diagram illustrating an embodiment of the semiconductor memory device according to the present invention. In FIG. 3, the elements which are the same as those of FIG. 1 are denoted by the same reference numerals. In FIG. 3, transistors Q D0 , Q D0  &#39;, Q D1 , Q D1  &#39;, . . . , Q D ,n-1, Q D ,n-1 &#39; which serve as current switching means are arranged between the power supply V DD  and each of the bit lines. It should be noted that the transistors Q D0 , Q D0  &#39;, Q D1 , Q D1  &#39;, . . . , Q D ,n-1, Q D ,n-1 &#39; are of a depletion type. The depletion type transistors can not be turned off, even when the gate potentials thereof are low. In other words, the depletion type transistors remain in the conductive state, regardless of the gate potentials. However, in this case, the conductances of the depletion type transistors are changed corresponding to the gate potentials which are determined by the column selection signals Y 0 , Y 1 , . . . , Y n-1 . 
     Therefore, when the memory cell C 00  is selected, that is, when the potentials of the word line WL 0  and the column selection signal Y 0  are high and the potentials of the other word lines and the other column selection signals are low, the currents flowing from the power supply V DD  to the non-selected memory cells C 01 , . . . , C 0 ,n-1 are reduced as compared with the current flowing from the selected memory cell C 00 . This is because the conductances of the transistors Q D1  and Q D1  &#39;, . . . , Q D ,n-1 and Q D ,n-1 &#39; are smaller than those of the transistors Q D0  and Q D0  &#39;. 
     In the above-mentioned embodiment, instead of the depletion type transistors Q D0 , Q D0  &#39;, Q D1 , Q D1  &#39;, . . . , Q D ,n-1, Q D ,n-1 &#39;, enhancement type transistors may be used. However, in this case, the following problem occurs. When the memory cell C 00  is selected, the transistors Q B1 , Q B1  &#39;, . . . , Q B ,n-1, Q B ,n-1 &#39; and the transistors Q D1 , Q D1  &#39;, . . . , Q D ,n-1, Q D ,n-1 &#39; are nonconductive so that the bit lines BL 1 , BL 1 , . . . , BL n-1 , BL n-1  are in a floating state, which invites malfunction and low operation speed. 
     As explained hereinbefore, the semiconductor device according to the present invention has an advantage in that power dissipation is reduced as compared with the conventional device, since the amount of current flowing from the power supply to non-selected memory cells belonging to a selected word line is reduced.