Wide frequency range signal generator including plural phase locked loops
This is a continuation of application Ser. No. 774,812 filed Mar. 7, 1977, which is in turn a continuation of application Ser. No. 561,332 filed Mar. 24, 1975. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to signal generators and more particularly the invention relates to VHF frequency signal generators of the type which permit selection of the generation of frequencies over a wide range. 
     Signal generators of the type to which the invention pertains are used for example as reference signal generators. In order to ensure a rather wide range of application for a single product, the signal generator should permit selection of frequencies to be generated within a wide range, but each selected frequency to be selected should be adjustable to remain within very small tolerances which should be the same for any frequency within the range of interest. Providing for adjustment of any frequency with a range from e.g. 1 MHz to about 500 MHz or higher in steps of, for example, 1 KHz poses a significant problem particularly when each of these signals should remain stable to, say one-thousandth of 1 percent. 
     DESCRIPTION OF THE INVENTION 
     It is an object of the present invention to provide for a new and improved high frequency signal generator meeting the aforementioned requirements. 
     In accordance with the preferred embodiment of the present invention, it is suggested to obtain the desired output frequency by way of multiple frequency mixing and compositioning in that the entire range of frequencies to be covered and the particular frequencies therein are organized on the basis of interdigitized, superimposed scales of differing resolution. Adjustment of the frequency within a larger resolution scale is carried out within any two scale points thereof only, independently from their value and by means of the scale values of next lower resolution. In other words, the frequency to be selected is broken down for representation by &#34;digits&#34; of different significance. The frequency values corresponding to these digits are generated separately and superimposed in a frequency mixing process to generate the desired frequency. The generation may be an indirect one in that the superimpositioning is carried out at the input of a phase lock circuit used to control an oscillator in feedback configuration. By way of example, &#34;digits&#34; within the meaning of the term employed here are multiples of 40 MHz corresponding to low resolution scaling. Megahertz values from 0 to 39 are used as next higher resolution and any kilohertz value (below 1 MHz) provides highest resolution-lowest significant scaling. This constitutes a three-&#34;digit&#34; scale system to cover for example several hundred megahertz at a resolution of 1 KHz. 
     More specifically, the relatively large range of frequencies to be covered by the selection is first subdivided by means of a low or coarse resolution scale in that a plurality of frequencies are generated whose frequencies are equidistantly spaced (e.g. by 40 MHz); one will use here preferably a harmonics generator to provide for the signal representation of that low resolution scale, and these frequencies will be used, so to speak, as an overlay covering the entire band of interest and establishing the low resolution scale. 
     The output element of the signal generator is an oscillator configuration which includes a wide band oscillator for the production of the desired frequency. As far as the low resolution scaling is concerned, that wide band oscillator is controlled by an input frequency selection operating at least to an accuracy so that upon mixing its output with the output of the harmonics generator (or its equivalent) one frequency thereof is selected by operation of a phase lock loop that controls the wide band oscillator. 
     The frequency selection based on higher resolution scales are staggeredly attached to the selected low resolution scale frequency. They are synthesized separately and for a range only in each instance that spans the range between respective two scale points of next lower resolution and, on the other hand, &#34;neglects&#34; the respective &#34;digits&#34; of higher significance. By way of example, a separate phase lock loop establishes a controlled frequency for any selected frequency but having value only within the range defined by two scale points of the lowest resolution scale, under neglect of the next higher resolution scale. If, for example, the low resolution scale points are apart by 40 MHz, then the phase lock loop for frequencies of next higher significance provides thirty-nine different frequencies 1 MHz apart. The resulting signal is mixed with the wide band oscillator output and the resultant is used for mixing with the output harmonics generator to obtain the low resolution scale selection. The open loop control of the wide band oscillator approximates (but does not equal) this next higher resolution scale selection, but the closed loop will track the particular higher resolution frequency (1 MHz) reference in conjunction with the selected and superimposed low frequency scale point. 
     The highest resolution frequency adjustment, such as a selection below 1 MHz and in kilohertz steps defines the third resolution scale and &#34;digit&#34; in an assumed 3 digit scale. That frequency is separately synthesized and is introduced as reference for the phase lock loop whose other input has been scaled down through the aforementioned mixing process involving the frequencies defining the respective lower resolution selection. 
     Generally speaking the frequency selection on the higher resolution scale proceeds with such a scale in each instance in that a voltage controlled oscillator is controlled in a phase lock loop which includes a frequency division of the respective oscillator output, by a number representing the selection within the particular scale range (e.g. below 40 MHz value and KHz value). The output of the respective oscillator represents the respective frequency at the desired accuracy to which is attached (by addition or subtraction) a fixed frequency for purposes of facilitating the combining thereof with other frequencies for use in the phase lock loop of the wide band oscillator. 
     It can thus be seen, that the invention includes plural oscillation circuits each operating over a different range, each being adjusted within a different range to produce one of a plurality of different, selectible discrete frequencies. The selection is digitially controlled from different portions of the input selection circuit. Each of the oscillation circuits includes the particular digital selection as part of a phase lock loop. One of the oscillation circuits receives the outputs of the others as inputs and it receives also the output of a harmonics generator selecting one frequency thereof through the feedback loop and by operation of its connection to the input section. The other frequencies are appended to that selected harmonic to obtain a preliminary output signal of the generator as output of the one oscillation circuit. The final output results from beating the preliminary output with a reference to shift the signal to the desired frequency range. The latter reference may be used for introducing frequency modulation. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which: 
     FIG. 1 is a block diagram outlining the system in accordance with the preferred embodiment by means of major components; 
     FIG. 2 is a more detailed and partial circuit diagram of the system shown in FIG. 1; and 
     FIG. 3 shows several frequency spectrums of signals developed in the circuit of FIG. 2. 
    
    
     Proceeding now to the detailed description of the drawings, FIG. 1 illustrates an input section 10 for selecting the desired output frequency from 1 to 520 MHz, in 1 KHz steps (resolution). The various frequencies needed in the system are generated in a module 20 which is under control of a master-crystal oscillator 21 (FIG. 2). A section 30 provides for establishing and controlling the particular kilohertz value (below megahertz adjustment) in steps of one kilohertz covering 10 3  different steps accordingly. Section 40 establishes analogously the megahertz adjustment steps, but on a modulo 40 basis covering therefor the 520 different megahertz values on a repetitive scale only, within an assumed, low resolution frequency scale having 40 MHz as unit. 
     A section 50 is the primary oscillation stage from which the adjusted frequency can be derived. This wide band oscillation stage is under control of the stages 10, 20, 30 and 40. Oscillation stage 50 covers a range from approximately 1200 MHz to a little over 1700 MHz. A signal combining stage 60 combines the output from stage 50 with a fixed reference to shift the frequency from stage 50 to the desired range from 1 to 520 MHz. Stage 60 accepts also frequency modulation signals if such modulation is desired. 
     Reference numeral 70 refers generally to output amplification, attenuation and amplitude modulation which is not of immediate interest and requires only summary description. The amplitude modulation accepts for example DC to 20 KHz signals from any external source (suitably matched of course). Section 70 includes manual amplitude and output level control. Additionally, the unit may include several oscillators to provide for internal AM or FM modulation to serve as standard. 
     Finally, the unit includes a power supply 80 to obtain regulated d.c. at various levels to serve as driving power for the several active circuit elements. Again, this is a conventional subsystem and does not require elaboration. 
     Turning now to FIG. 2, input section 10 has six adjustment knobs (levers, thumb wheels or the like) three of which are denoted 11 and connected to circuits 12 to provide the selected KHz value in &#34;ones&#34;, &#34;tens&#34; and &#34;hundreds&#34;, each in bcd format. These signals are the primary input for the circuit 30. Analogously, three circuits 14 are respectively connected to the three other input elements, 13, to provide the selected MHz value in &#34;ones&#34;, &#34;tens&#34; and &#34;hundreds&#34; (the latter up to 500, which is an arbitrary limit). These signals are likewise furnished in bcd format, and circuit 14 provides them to circuits 40 and 50. 
     The module 20 includes a 40 MHz crystal oscillator 21 with output amplification to provide the oscillation at a suitable level and as standard from which all other frequencies are derived. A variety of different, phase related signals are needed throughout the system. Therefor, the output signal from oscillator 21 is fed to a plurality of digital processing circuits which divide the frequency in steps. Accordingly, a divide-by-four stage 22 (e.g. two cascaded toggle flip-flops) provide, as an output, a 10 MHz signal. That signal is further divided by 5 in a stage 23 to provide a 2 MHz signal which in turn is divided by 2 in a stage 24 to obtain a 1 MHz signal. Finally, a divide-by-thousand stage 25 provides a 1 KHz signal. 
     The 40 MHz oscillator signal is a.c. processed in a second branch wherein a circuit 26 generates the harmonics of that 40 MHz signal. In other words, circuit 26 provides a composite signal which includes the 40 MHz, (as fundamental), a 80 MHz component, a 120 MHz component etc. Circuit 26 is basically comprised of a diode and an amplifier. This train of harmonics will hereinafter be called the 40 MHz comb. This 40 MHz comb establishes the low resolution frequency scale points to be used in the compositioning of the desired output frequency. 
     A branch circuit taps the comb and particularly a band pass filter 27 separates the 120 MHz harmonic from the comb. A circuit 28, constructed analogously to circuit 26, generates a composite signal which includes 120 MHz as fundamental and the harmonics thereof. A band pass filter 29 separates the 1440 MHz signal component therefrom for use as a particular frequency. 
     The purpose of the remaining circuit of FIG. 2 and to be described next is to generate a signal of particular frequency within a range from 1 MHz to 520 MHz at a 1 KHz resolution and corresponding to the setting of input elements 11, 13 using the signals from stage 20 as &#34;building blocks&#34; while the setting of input elements 10 determines which particular frequency is to be generated. 
     The synthesis of the desired signal proceeds in four steps. In the first step, the input setting of the three elements 11 defining the kilohertz (below megahertz) value for the selected frequency is processed to generate an auxiliary frequency which represents that setting, in a convenient range, and being variable in steps of 1 KHz in accordance with the setting of elements 11. For reasons which will become apparent below, that particular auxiliary signal covers a range from 10 MHz down to 9.001 MHz in steps of 1 KHz, whereby the 10 MHz value is produced for a 000 kilohertz setting of input elements 11, and the 9.001  MHz is produced for a 999 setting of elements 11. This particular auxiliary signal is provided by stage 30 as an output. One could also say, that stage 30 provides a 0 to 999 KHz signal but following a subtraction from 10 MHz for purposes preparing the signal for further processing. 
     The second step, occurring so to speak in parallel with the first one, is provided to generate another auxiliary frequency which represents the megahertz setting on a modulo 40 basis. Specifically, circuit 40 provides an output which is 1448 MHz for a megahertz setting of 000 by elements 13, but the same 1448 MHz is also provided for a megahertz setting of 40, or 80 up to a megahertz setting of 520. The output of circuit 40 is a 1487 MHz signal for a megahertz setting of 39, but also for settings of 79, 119, etc. up to 519. One could also say that stage 40 provides a 0 to 39 megahertz signal to which has been added a 1448 signal for reasons of preparing the signal for further processing. 
     In the third step, these two auxiliary signals from stages 30 and 40 are combined with each other, and with the 40 MHz comb signal to obtain a signal within the range from 1198 to 1718, but having the desired resolution and accuracy. The circuit combining these signals operates additionally in response to the megahertz setting of the switches 13 and using closed loop operation to select the particular comb signal needed as low resolution scale point frequency to which the other frequencies are &#34;appended&#34;. Circuit 50 provides for these functions. 
     The fourth and final step is comprised of beating this 1198-1718 MHz signal with an 1198 signal to obtain the desired signal within the range from 0 to 520 MHz. 
     The first mentioned, auxiliary signal is generated as the output of stage 30. The principal, output-generating element is a voltage controlled oscillator 31 whose d.c. input is derived from a digital-to-analog converter 32. That converter receives signals representing the below-megahertz setting and provided as bcd signals by the three stages 12. The bcd digits represent the kilohertz settings of elements 11. The VCO 31 is designed to provide a 10 MHz output for a 000 setting, and a 9.001 MHz output for a 999 setting; the converter 32 controls VCO 31 accordingly. 
     Aside from being the principle output of stage 30, this output signal of VCO 31 is fed to a frequency divider stage 33, which receives also the bcd equivalent signals for the three lower significance digit settings of elements 11, to control the divisor in stage 33. The output of VCO 31 is provided to frequency divider 33 as &#34;dividend&#34; and the frequency of this particular signal is divided therein by a number (divisor) representing the kilohertz setting, but being scaled to the VCO output. As stated, that output is a signal having one particular frequency that may range from 10.0 to 9.001 MHz. Accordingly, the divisor actually used ranges from 10,000 to 9,001 for the range of kilohertz settings (000 to 999) so that dividing stage 33 provides always a 1 KHz output (± any error). Stage 33 can be realized by a combination of 8 chips traded under the designation 7404, 8290, 82S90, 74H11 and 74H102. 
     The 1 KHz output (± any error) of stage 33 is fed to a phase lock circuit 34 being, for example, of the type traded by the Motorola Company under the description 4044. Circuit 34 receives additionally a reference signal which is the 1 KHz signal from frequency divider 25 in circuit 20. The output of phase lock circuit 34 is added as corrective control to the input of VCO 31 to establish a phase lock loop. 
     The second auxiliary signal being the output of stage 40 is generated somewhat analogously. Stage 40 has a voltage controlled oscillator 41 as principal output element, which receives an input from a digital-to-analog converter 42. The digital input for converter 42 is derived from the megahertz setting of input circuit 10 but on a modulo 40 basis. The analog signal, therefore, has the same value for settings of elements 13 to &#34;0&#34;, &#34;40&#34;, &#34;80&#34; MHz etc. The analog signal for a 1 MHz is also the same for settings of 41, 81, etc. The (same) maximum output is provided by the converter 42 for megahertz settings 39, 79, 119, etc. up to 519. 
     The output signal of d/a converter 42 determines the output frequency of VCO 41, they have the same value for such modulo-40 interrelated megahertz settings. As stated above, the lowest frequency is 1448 for a 000 megahertz setting and the highest frequency is 1487 megahertz for 38, 79 settings etc. The reason for using the 1448 value as low point frequency will become apparent below, it is instrumental in preparing the control for the principle oscillation of the system. 
     The frequency control involves a mixing stage 45 receiving the 1440 MHz signal from circuit 20 (stage 29 thereof) as a first input, and the output of VCO 41 is a second input for mixer 45. A low pass filter 46 with a roll off frequency of 60 MHz eliminates the sum-of-the-frequencies signal so that the effective output is a signal that varies from 8 to 47 megahertz. A digital circuit 47 is connected to the stages 14 of the input section 10 and forms the nines-compliment of the digital, modulo-40 signal representing the megahertz setting, and circuit 47 provides signals representing that number as divisor for a frequency dividing circuit 43. The &#34;dividend&#34; signal is the output signal of filter 46 so that for stationary conditions, a 1 MHz signal issues from that dividing circuit 43. 
     The output of frequency dividing circuit 43 is fed to another phase lock circuit 44, which receives the 1 MHz signal from stage 24 of circuit 20 as reference. The phase lock circuit 44 provides a control signal to the VCO 41 to phase lock the output to the 1 MHz reference. 
     It can thus be seen, that the settings in input section 10 representing the desired frequency have been processed thus far to provide for a first auxiliary signal representing the below-megahertz setting but covering that range by providing a 10 through 9.001 MHz signal in steps of 1 KHz. The second auxiliary signal does not fully represent the megahertz input setting, but on a modulo 40 basis covering that range by providing a 1448 through 1487 MHz signal in steps of 1 MHz. The low points (all zero) of the settings are respectively represented by a 10 MHz and by a 1448 MHz signal. 
     The upper scale range (i.e. the digits of higher significance with regard to the 40 MHz scale points for the megahertz setting) is acquired by means of another digital-to-analog converter 52 of circuit 50, and by introducing the comb which can be regarded as establishing scale points 40, 80, 120, 160 MHz etc. Since the outputs of circuits 30 and 40 are also used in this process of establishing the 40 MHz scale range, it is convenient to consider these outputs for respective low point or zero settings, wherein circuits 30 and 40 respectively provide 10 and 1448 MHz signals. Thus, the input is assumed to be 0 MHz and 000 KHz. 
     Digital-to-analog converter 52 responds to the megahertz setting in total; it could share components with converter 42, but separate block representation is simpler for purposes of explanation. The output of that converter 52 covers a wide range and is for example processed in a stage 53 for a non-linear signal configuration. That signal shaper 53 now drives a wide band oscillator 51 operating within a margin of error of several MHz. Oscillator 51 covers the range from 1198 to 1718 MHz at that accuracy. 
     The various frequency relations are shown in FIG. 3 wherein the various frequencies are shown in megahertz and the figures in parenthesis refer to the element shown in FIG. 2 which produces the respective signal. The output of oscillator 51 is (exactly or approximately) 1198 MHz for a 0 MHz setting. A mixing stage 54 combines that signal with the output of VCO 41 assumed to be 1448 MHz, which is approximately the mid-point between the range limits of 1198 and 1718 MHz. A low pass filter 55 cuts off the sum-of-the-frequencies signal so that only 250 MHz passes which results from frequency subtraction. That signal now beats with the 40 MHz comb signal (40, 80, 120 . . . MHz) in a mixer stage 56. The differences are 250-40; 250-80; 250-120; 250-160; 250-200; 250-240; 280-250; 320-250; . . . etc. A low pass filter 57 eliminates again the sum-of-the-frequencies signal so that differences are formed only. Moreover, not all these differences are wanted. Therefore, the filter 57 has a cut off frequency of 20 MHz, so that only the difference between 250 MHz and the &#34;nearest comb&#34; is formed which presently is the 240 MHz component of the comb, so that the output of filter stage 57 provides a 10 MHz signal. (exactely or approximately) 
     Presently the establishing of the 40 MHz unit, low resolution scale is being considered and briefly, we turn to an input setting of 40 MHz, 80 MHz, 120 MHz etc. In all these cases, circuit 41 furnishes 1448 MHz. While oscillator 51 provides 1238 or 1278 or 1318, etc. MHz as the case may be. Circuits 54, 55 provide accordingly 210, 170, 130 . . . or 10 MHz for outputs of the oscillator 51 having frequency below this center frequency of 1448 MHz; while circuit 54/55 provides one of the frequencies, 30, 70, 110, 150 . . . , when the output of oscillator 51 has frequency above the 1448 MHz reference value. Upon beating these signals with the comb a difference signal of 10 MHz will be established in each of these cases. 
     Thus, it can be seen from FIG. 3 that the oscillator 51 establishes a band from 1198 to 1718 MHz, of which 1448 MHz is the approximate center point with double side bands up to 250 MHz. The beat circuit 54 separates that band and one of the following frequencies of 250, 210, 170, 130, 90, 50, 10; 30, 70, 110, 150, 190 and 230 is established within that MHz band. Filter 55 eliminates the sum-of-the-frequencies in each instance. Each of these frequencies is 10 MHz off the respective nearest comb (to one side or the other) which are the frequencies 0, 40, 80, 120 MHz etc. Any of the frequencies permitted to pass 55 is a side band signal to a comb-frequency whereby the upper side band is used and established (250 or 210, . . . or 10 MHz) for an oscillator 51 signal having frequency below the 1448 MHz reference and the lower band is used and established (30 or 70 or 110 . . . 230 MHz) for an oscillator 51 signal having frequency above the 1448 MHz reference. But in each of these cases, beating the output of the combination of mixer and low pass circuits 54 and 55 with the comb produces a 10 MHz output (and others but the 20 MHz low pass 57 passes only this signal)! 
     The output of filter 57 (presently presumed to be 10 MHz) is now compared in a phase lock 58 using the output of circuit 30 as a reference. This reference is presently presumed to be 10 MHz, as we started these considerations on the basis of an all-zero setting for the kilohertz switches in input section 10. The output of circuit 58, therefor, represents any error deviation of the oscillator 51 from a frequency corresponding to a setting to the scale points 0, 40, 80, 120 etc. That output is provided as second input to oscillator 51 to close the loop accordingly. 
     If we consider a frequency selection to one of the megahertz scale points only (0, 40, 80, etc), then the megahertz circuit 40 produces the 1448 reference frequency at the stated accuracy in all instances by virtue of its own phase lock loop, and circuit 30 produces the 10 MHz reference at the same accuracy. The D/A converter 52 produces a d.c. value for which oscillator 51 approximates the desired frequency so that the feedback loop establishes a 1198, or 1238 or 1278 etc. value, respectively for a megahertz setting of 0, 40, 80, etc. on the basis of the accuracy of the comb frequencies which determine the particular frequency towards which the phase lock loop of oscillator 51 is being controlled. 
     The output of d/a converter 52 fulfills actually two functions which are conveniently combined. The primary function however, is the scale point selection (for which a much lesser resolution were needed if that were the only function). Particularly, the output of converter 52 is used to select the particular frequency from the 40 MHz comb, as already mentioned. This selection is done through feedback of oscillator 51 and in mixer 56. The mixer 54 and, ultimately, the 1440 MHz signal as transmitted through circuit 40 (and augmented to 1448 MHz) prepares the frequency range for the scale point selection (comb frequency). A better resolution in the digital-to-analog conversion of circuit 52 is simply more convenient to permit combining of the feedback signal of oscillator 51 in steps with the outputs of circuits 30 and 40 in one loop which contains phase lock 58 as active control element and does not have to include circuitry covering too large a range for control. This then is the result of another combination of function, namely the scaling range reduction through formation of a band by operation of that 1448 MHz signal as mixed with the output of oscillator 51, and by the use of that 1448 signal as reference in the sense that the below the 40 scale, megahertz selection is appended thereto for introduction into the system and combination with the comb selected 40 MHz scale point. 
     The preceding paragraphs were devoted to the description of establishing the particular frequencies corresponding to the low resolution scale points, while we neglected the 1 to 39 megahertz and the below-megahertz adjustment. That the circuit faithfully produces outputs representing these higher resolution frequency adjustments will be established next. 
     It will be appreciated that the auxiliary signal of circuit 40 as defined above, namely the 1448 to 1487 MHz signal, depends on the megahertz adjustment within any two adjacent 40 MHz scale points; such megahertz adjustment merely shifts the range for the signal with which it is beat by operation of mixer 54. This operation will be described next. 
     Let us assume an adjustment, or a variation in adjustment in megahertz steps (absolute) from 1 to 39 MHz as far as input elements 13 are concerned. The output of VCO 41 reproduces that adjustment faithfully in 1-Megahertz steps but covering the range by signals having frequency from 1449 to 1487 MHz. The output of oscillator 51 reproduces the setting of the input for D/A converter 52 also in like steps, from about 1199 to 1237 (with an assumed error of less than 2 MHz). Thus, the output of mixer 54 stays at approximately 250 MHz, so that upon beating that signal with the 40 MHz comb (56), and upon filtering by means of the 20 MHz low pass filter 57, one will always use the 240 MHz comb component, resulting in a 10 MHz output of mixer 56 and low pass 57 in each instance! 
     For a megahertz setting of 41 and above, but below 80, the outputs of circuits 40 and of oscillator 51 are now apart by more than 40 MHz so that the difference frequency is 210 MHz, and upon beating that signal with the 40 MHz comb the 200 MHz component thereof will be used by 56, 57 to establish the 10 MHz difference frequency as side band from this particular comb frequency. A setting of 81 MHz will cause the use of the 160 MHz comb frequency etc. 
     It can thus be seen, that the circuit 40 stabilizes the output of oscillator 51 (through phase lock 58) so that the output of filter 57 remains 10 MHz (or approximately 10 MHz). The 10 MHz output from circuit 30 serves as reference in phase lock 58 and its operation controls the device to adjust the output frequency accurately to any of the megahertz settings. 
     For the kilohertz setting, the reference signal from circuit 30 is changed within the range from 10 to 9.001 MHz in steps of 1 KHz, as per the three least significant setting by the three elements 11 of input section 10. It can readily be seen that the phase lock loop will tend to establish the value of the particular reference setting as output for oscillator 51, and strictly by feedback operation. 
     It will be recalled that the output of mixer/band pass 54/55 for a 000 setting of the kilohertz input was e.g. 250, or 210, or 170 MHz etc. These particular frequencies resulted from a frequency subtraction in which the feedback frequency (from 51) was subtracted from the signal as provided by circuit 40. Thus, for a non-zero kilohertz setting, the feedback signal will increase, but the output of mixer/filter 54/55 will drop to a value below 250 or below 210 or below 170 as the case may be. The nearest comb frequency in each instance is lower than the filter output. Consequently, upon beating the output signal of filter 55 with the 40 MHz comb, a below-10 MHz difference frequency results commensurate with the kilohertz setting and further commensurate with the below-10 MHz reference signal as presently provided by the circuit 30. On the other side of the megacycle midpoint range, i.e. for feedback frequencies of oscillator 51 larger than the auxiliary output (1448 to 1487 MHz) from 40 (i.e. 41), the output of mixer/filter 54/55 will be 30 or 70 or 110 MHz etc. plus in each instance the value for the kilohertz setting. Those frequencies are below the respective nearest comb frequency, so that again the difference frequency as established by mixer 56 is below 10 MHz; the difference taken down from 10 MHz is equal to the kilohertz setting which is again compatible with the reference from circuit 30. This then is the reason for introducing the set kilohertz frequency on an inverted scale by means of circuit 30. 
     In summary, it can thus be seen, that the output of oscillator 51 results initially from a relatively low resolution digital-to-analog conversion of the input setting, and upon feedback thereof, while mixing it together with a separately synthesized below-40 MHz value, one establishes a signal which remains (by operation of the feedback loop) within a 10 to 9 MHz frequency spacing from the nearest comb frequency thereby establishing the 40 MHz scale points within the range of frequency covered by the wide band oscillator 51 while the MHz &#34;fine&#34; adjustment is added on. Using the comb and combined MHz adjustment, one establishes a 10-9 MHz feedback signal for phase lock control, still in the same loop, but in which the reference signal represents the kilohertz setting. The combination of signals, therefore, controls the wide band oscillator 51 to obtain the desired frequency within the stated accuracy. 
     The output signal of oscillator 51 is, of course, offset from the actually desired output by 1198 MHz, and shifting the range down to the desired range is the function of a mixer 69 beating the signal from oscillator 51 with the output of a narrow band oscillator 61 providing either that frequency of 1198 MHz at maximum spectral purity or as a carrier which is additionally frequency modulated. 
     The narrow band oscillator 61 is controlled as follows. Taking first the situation without modulation, oscillator 61 is controlled by an amplifier 62 establishing a particular d.c. input level for control of the oscillator and being itself controlled by a phase lock circuit 64 (the fourth one in the system) which responds to a feedback and a reference. The reference signal is the 2 MHz signal taken from the divide-by-5 circuit 23 in circuit 20. The feedback signal is generated by beating the output of oscillator 61 with the 120 MHz comb from circuit 28 in a mixer 65. Actually, one needs only the 1200 MHz harmonic so that a filter could be interposed; however, just beating the 1198 MHz output of oscillator 61 with the 120 MHz suffices to extract therefrom the one difference signal needed, namely 2 MHz which is fedback as second input to phase lock circuit 64. The narrow oscillator 61 is, therefore, controlled to produce precisely 1198 MHz which is combined in mixer 69 with the wide band oscillator output. 
     A wide band amplifier 71 amplifies the resulting signal which may have frequency from 0 to 520 MHz. However, the amplifier 71 should have low pass characteristics to reject the sum-of-the-frequencies signal. Also, one will use only frequencies above 1 MHz so that the passing characteristics of that amplifier for signals of lower frequencies does not have to be developed. An amplifier 72 is provided to accept an AM signal, suitably leveled, for amplitude modulation. Circuit 72 may further include resistors for providing for manual adjustment of the output signal through varying signal attenuation. 
     In the case of FM modulation, the position of a switch 68 is changed to separate the 2 MHz reference from the phase lock 64. Instead, a modulation signal covering a band from 1.5 to 2.5 MHz is introduced from a suitable source so that this modulation signal serves as reference. However, the feedback loop should be relieved from carrying out the entire modulation operation. Therefore, the FM modulation signal as such (i.e. 0.5 MHz band) is fed also directly to the oscillator 61 as input thereof, being merely superimposed upon the output of amplifier 62 as controlling oscillator 61. 
     The invention is not limited to the embodiments described above but all changes and modifications thereof not constituting departures from the spirit and scope of the invention are intended to be included.