High speed NXM bit digital, repeated addition type multiplying circuit
BACKGROUND OF THE INVENTION 
     In digital, or binary, multiplication there are three general approaches including: repeated addition, multiple-digit multiplication, and simultaneous multiplication. Generally, the repeated addition approach is the simplest and, while there are a variety of repeated addition methods, to increase the speed of the device it is desirable to minimize the longest propagation path as well as the total number of partial products which must be added. Several of the repeated addition methods, when implemented in combinational hardware, require sign bit extension of low order partial products and, thus, the logic becomes unwieldly. The repeated addition approach commonly referred to as the Burks-Goldstine-VonNeumann method, is implemented herein because it does not require sign bit extension and thereby minimizes hardware. 
     SUMMARY OF THE INVENTION 
     The present invention pertains to a high speed N×M bit digital, repeated addition type multiplying circuit including a plurality of rows and columns of multiply/adder cells interconnected to provide repeated addition multiplication with the carry-bit output of each of said cells connected to the carry-bit input of the corresponding cell in the next highest row. Generally, the multiplying circuit has M rows with N cells in a row and a final carry resolution row having N cells therein with the carry-bit from each previous cell in the resolution row and the carry-bit from the previous cell in the M row being applied thereto for adding to a sum bit from the corresponding cell in the M row. This provides a fast carry propagation time with a layout approach convenient to LSI integration. 
     In order to provide a fast CMOS multiplier featuring small multiply times, small pin counts, low power, and easy application to many problems, several design approaches are combined, including: multiplexed-pipelined input bus and register, multiplexed-pipelined output bus and registers, fast carry circuit topology, and balanced propagation between sum and carry paths so that the total propagation delay is minimized within the constraints of CMOS technology. 
     It is an object of the present invention to provide a new and improved high speed N×M bit digital, repeated addition type multiplying circuit. 
     It is a further object of the present invention to provide a high speed addition type arithmetic logic unit including a new and improved high speed carry propagation line. 
     It is a further object of the present invention to provide a high speed N×M bit digital, repeated addition type multiplying circuit including multiplexed-pipelined input and output with balanced propagation between sum and carry paths and formed on a single semiconductor chip. 
     It is a further object of the present invention to provide a high speed N×M bit digital, repeated addition type multiplying circuit incorporating the Burks-Goldstine-VonNewmann method of repeated addition and formed on a single semiconductor chip. 
     These and other objects of this invention will become apparent to those skilled in the art upon consideration of the accompanying specification, claims and drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Referring to the drawings, wherein like characters indicate like parts throughout the figures: 
     FIG. 1 is a block diagram of a four-by-four bit digital, repeat addition type multiplying circuit embodying the present invention; 
     FIG. 2 is a block diagram of a portion of a sixteen-by-sixteen bit multiplying circuit similar to the circuit illustrated in FIG. 1; 
     FIGS. 3 and 4 are detailed block diagrams of first and second types of combining circuits, both of which are illustrated generally in FIG. 1; 
     FIGS. 5-9 are detailed block diagrams of five different types of combining circuits, all of which are illustrated generally in FIG. 2; and 
     FIG. 10 is a block diagram of another portion of the sixteen-by-sixteen bit multiplying circuit illustrated partially in FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention pertains to a high speed digital, repeated addition type multiplying circuit for multiplying a number represented by N bits times a number represented by M bits of digital information. One of the numbers is the multiplier and the other number is the multiplicand, in accordance with normal mathematical nomenclature. In general, both numbers will be represented by the same number of bits but the letters N and M are utilized herein to indicate that a different number of bits can be utilized if desired. Further, in the following descriptions of the invention it is assumed that the number of leads supplied to a multiplying circuit are the same as the number of leads at the output thereof. However, it will be obvious to those skilled in the art that different numbers of leads might be utilized without materially affecting the invention. Further, it will be obvious to those skilled in the art that the number of bits representing the multiplier and the multiplicand can be reversed and/or varied from the following descriptions without materially affecting the invention. 
     Referring specifically to FIG. 1, a high seed N×M bit digital, repeated addition type multiplying circuit is illustrated wherein the multiplier, Y, is represented by four bits and the multiplicand, X, is represented by four bits. In this embodiment the four bits of the multiplier are Y 0  through Y 3  with Y 3  being the sign bit. The multiplicand is represented by X 0  through X 3  with X 3  being the sign bit. 
     N (M+1), or twenty, combining circuits are utilized to form the multiplying circuit. The combining circuits are mathematically arranged with N, or four, combining circuits per row and M addition rows with one additional final carry resolution row. For ease in following the operation of the multiplying circuit, the combining circuits in the various rows are staggered similar to the way a multiplication problem would be positioned in hand, or human, calculations. Thus, the multiplying circuit provides N+M-1 outputs, or seven, which are designated P 0  through p 6  in FIG. 1. 
     The first row of the M addition rows includes four combining circuit which are simply four AND gates 10, 11, 12 and 13. Each of the AND gates 10 through 13 has two inputs and a single sum output. The first gate 10 receives bits Y 0  and X 0  and the output is connected to the output terminal P 0 . Second gate 11 receives bits X 1  and Y 0 , third gate 12 receives bits X 2  and Y 0 , and fourth gate 13 receives bits X 3  and an inverted Y 0 . In the second row, a first combining circuit 15 includes an AND gate 16 connected to receive bits X 0  and Y 1  and a multiplying/adder cell 17 connected to receive the output of the AND gate 16 and the sum output of the AND gate 11 from the first row. Further, the cell 17 has a carry input connected to a reference potential, in this embodiment ground, and a carry output. The sum output of the cell 17 is connected directly to the P 1  output terminal. A second combining circuit 19 in the second row includes an AND gate 20 connected to receive bits X 1  and Y 1  and a multiply/adder cell 21 connected to receive outputs from AND gates 20 and 12 and including a carry input connected to ground. Cell 21 also supplies a carry output and a sum output. A third combining circuit 23 in the second row includes an AND gate 24 connected to receive bits X 2  and Y 1  and a multiply/adder cell 25 connected to receive the sum outputs from AND gate 24 and AND gate 13 along with a carry input, which is connected to ground. The cell 25 also supplies a carry output and a sum output. The fourth and final combining circuit in row 2 is simply an AND gate 27 having two inputs connected to receive the bits X 3  and an inverted Y 1 . 
     A first combining circuit 29 in the third row includes an AND gate 30 connected to receive bits X 0  and Y 2  and a multiply/adder cell 31 connected to receive the sum outputs of the AND gate 30 and the cell 21 from row 2. The cell 31 also has a carry input connected to the carry output of cell 17 in row 2. Cell 31 includes a carry output and a sum output which is connected directly to the output terminal P 2  of the multiplying circuit. A second combining circuit 33 in the third row includes an AND gate 34 connected to receive bits X 1  and Y 2  and a multiply/adder cell 35 connected to receive the sum output from the AND gate 34 and the sum output from the cell 25 in row 2. Also, the cell 35 has a carry input which is connected to the carry output of the cell 21 in row 2. The cell 35 has a carry output and a sum output. A third combining circuit 37 in the third row includes an AND gate 38 connected to receive bits X 2   and Y 2  and a multiply/adder 39 connected to receive the sum outputs of the AND gates 38 and 27, as well as the carry output from the cell 25 in row 2. The cell 39 also has a carry output and a sum output. A fourth combining circuit in the row 3 is simply an AND gate 40 connected to receive bits X 3  and an inverted Y 2 . 
     A first combining circuit 43 in the fourth row includes an AND gate 44 connected to receive bits Y 3  and an inverted X 0  and a multiply/adder cell 45 connected to receive the sum output of the AND gate 44, the sum output of the cell 35 in row 3 and the carry output of the cell 31 in row 3. The cell 45 also supplies a carry output and a sum output. A second combining means 47 in row 4 includes an AND gate 48 connected to receive bits Y 3  and an inverted X 1  and a multiply/adder cell 49 connected to receive the sum output of the AND gate 48, the sum output of the cell 39 in row 3, and the carry output of the cell 35 in row 3. The cell 49 also supplies a carry output and a sum output. A third combining circuit 51 in the fourth row includes an AND gate 52 connected to receive bits Y 3   and an inverted X 2  and a multiply/adder cell 53 connected to receive the sum outputs of the AND gates 52 and 40 and the carry output of cell 39 in row 3. The cell 53 also supplies a carry output and a sum output. A fourth  combining circuit in row 4 simply includes an AND gate 55 connected to receive bits Y 3  and an inverted X 3 . 
     A first combining circuit in the final carry resolution row includes a multiply/adder cell 57 connected to receive bits X 3  at a first input and the sum output of the cell 45 in row 4 at a second input. A third input of the cell 57 is connected to receive bits Y 3 . The cell 57 provides a carry output and a sum output which is connected to the output terminal P 3  of the multiplying circuit. A second combining circuit of the final carry resolution row includes a multiply/adder cell 59 connected to receive the sum output of the cell 49, the carry output of the cell 45 and the carry output of the cell 57. The cell 59 also provides a carry output and a sum output which is connected to the output terminal P 4  of the multiplying circuit. A third combining circuit in the final carry resolution row includes a multiply/adder cell 61 connected to receive the sum output from the cell 53, the carry output from the cell 49 and the carry output from the cell 59. The cell 61 provides a carry output and a sum output which is connected to the output terminal P 5  of the multiplying circuit. A fourth and final combining circuit of the final carry resolution row includes a multiply/adder cell 63 having inputs connected to receive bits X 3 , the sum output of the AND gate 55, the carry output of the cell 53 and the carry output of the cell 61. The cell 63 has a sum output which is connected to the output terminal P 6  of the multiplying circuit. 
     Each of the multiply/adder cells in the multiplying circuit of FIG. 1 is constructed generally in accordance with the teachings of U.S. Pat. No. 3,843,876, entitled &#34;Electronic Digital Adder Having a High Speed Carry Propagation Line&#34; issued Oct. 22, 1974. Further, the various adder cells are referred to as multiply/adder cells because they are used in a multiplying circuit. All of the combining circuits 15, 19, 23, 29, 33, and 37 are constructed similarly and this construction can be seen more clearly by referring to FIG. 3 wherein a more detailed block diagram of the combining circuit 15 is illustrated. While only six of the adder cells illustrated in FIG. 3 are utilized in the multiplying circuit of FIG. 1, it will be understood by those skilled in the art that more are utilized as N and/or M are increased e.g. if N and M are sixteen, two hundred and ten of the cells illustrated in FIG. 3 will be utilized. The fast carry multiply/adder cells, for a combinational array multiplier circuit, is a crucial element since the organization can dramatically effect both chip size and propagation performance for a single chip multiplying circuit. Minimizing the longest propagation path and the total number of partial products in conjunction with the high speed carry propagation line of the multiply/adder circuits provides the high speed multiplying circuit of the present invention. 
     Referring to FIG. 3, the AND gate 16 of the combining circuit 15 has a pair of inputs connected to receive X 0  and Y 1  bits. The output of the AND gate 16, herein designated B, is applied to an input of a transmission gate 70 and an input of an exclusive OR gate, generally designated 72. A second input of the exclusive OR gate 72, herein designated A, is connected to the output of the AND gate 11 (see FIG. 1). An output of the exclusive OR gate 72 is connected to an input of a second exclusive OR gate, generally designated 75, and to a gate control terminal for the transmission, or pass, gate 70 and for a second transmission, or pass, gate 77. The output of the exclusive OR gate 72 is also supplied through an inverter 78 to a second gate control terminal associated with each of the transmission gates 70 and 77. A second input to the exclusive OR gate 75 is connected directly to an input terminal, herein designated C IN , which for this particular combining circuit 15 is connected to ground. Input terminal C IN  is also connected through the transmission gate 77 to an output terminal, herein designated C OUT , which is connected to the C IN  terminal of the cell 31. The output of the exclusive OR gate 75 is connected to an output terminal, herein designated S OUT , which is connected directly to the output terminal P 1  of the multiplying circuit. While specific block diagrams for the combining gates 72 and 75 are illustrated in FIG. 3, it will be apparent to those skilled in the art that other circuits which perform the same functions might be utilized. Further, many other minor modifications might be incorporated, e.g. providing input signals X N  and Y N  to the input terminals of the AND gate 16 and inverting these inputs prior to application to the AND gate 16, which modifications may be required to standardize parts or render the present circuitry compatible with presently available circuitry. 
     In the operation of the cell 15 illustrated in FIG. 3, the AND gate 16 provides an output signal which is essentially equal to X times Y, i.e. the output is a &#34;1&#34;  only when both of the inputs are a &#34;1&#34; and if either or both of the inputs are a &#34;0&#34; the output is a &#34;0&#34;. The output of the AND gate 16 is then essentially added to the signal at the input A by the exclusive OR gate 72. In a similar fashion the exclusive OR gate 75 adds the signal at the C IN  terminal to the output of the exclusive OR gate 72 and supplies the sum to the terminal S OUT . If the two inputs to the exclusive OR gate 72 are both &#34;1&#39;s&#34; a &#34;0&#34; appears at the output thereof, which opens the transmission gate 70 and allows the &#34;1&#34; from the AND gate 16 to be applied to the C OUT  terminal. Similarly, if the output of the exclusive OR gate 72 is a &#34;1&#34; and the signal at the C IN  terminal is a &#34;1&#34; the transmission gate 77 is opened allowing the &#34;1&#34;  at the C IN  terminal to pass therethrough to the C OUT  terminal. Thus, the combining circuit illustrated in FIG. 3 provides 2&#39;s complement addition and the carry propagation line includes only a single transmission gate in accordance with the U.S. Pat. No. &#39;876, described above. 
     Referring specifically to FIG. 4, a more detailed block diagram for the combining circuits 43, 47, and 51 is illustrated. It will of course be understood by those skilled in the art that if N and M represent larger numbers, such as 16, fifteen of the combining circuits illustrated in FIG. 4 will be utilized. Since the combining circuits 43, 47 and 51 are all identical, only the combining circuit 43 will be described with reference to FIG. 4. Further, the construction and operation of the combining circuit illustrated in FIG. 4 is essentially similar to that described in FIG. 3 except for several modifications and only the modifications will be elaborated upon herein. 
     The combining circuits of row 4 of FIG. 1 require that the X input to the AND gates 44, 48, 52 and 55 be inverted and, accordingly, FIG. 4 illustrates an inverter at the X input of the AND gate 44. Further, the output of the AND gate 44 is inverted and applied to an exclusive NOR gate 80, rather than the exclusive OR gate 72 illustrated in FIG. 3. The inverted output of the AND gate 44 is also supplied through an inverter and inverter amplifier 81 to a transmission gate 82. The transmission gate 82 operates as the transmission gate 70 in FIG. 3. The inverting amplifier 81 and the exclusive NOR gate 80 are included in the circuitry to minimize the capacitive load and to increase the speed of the combining circuit 43. Further by connecting the output signal from the AND gate 44 to the exclusive NOR gate 80 prior to the inverter 81, the full drive capability of the inverter 81 is available at the gate 82 and the C OUT  terminal. 
     Referring specifically to FIG. 1 it will be noted that the carry lines of each of the combining circuits in the addition rows (2nd, 3rd, and 4th) are connected from the carry output of one combining circuit, e.g. combining circuit 15, to the carry input of the corresponding combining circuit, e.g. combining circuit 29, in the next highest row. This connection produces a substantial reduction in the length of the carry path and a substantial improvement in multiplier circuit speed over circuits wherein the carry output of each combining circuit is connected to the carry input of the next adjacent combining circuit in the same row. For an N×N bit multiplying circuit, the improved approach requires (N+1) cell propagations (A input to S OUT ) plus N C IN  to C OUT  propagations. The approach where the carry output is connected to the carry input of the adjacent combining circuit requires 2N C IN  to C OUT  propagations and N cell propagations (A input to S OUT ). 
     It is desirable in the improved approach for the C IN  to C OUT  propagations to be faster than the cell propagation (A input to S OUT ). In the final carry resolution row, all answers from the above columns become valid at approximately the same time but the correct answer must wait on the N carry path propagations. Thus it is highly desirable for the carry path to be extremely fast, as in the cell circuits illustrated in FIGS. 3 through 8. The carry propagation in the combining circuits described (15 in FIG. 3 and 43 in FIG. 4) are the fastest possible circuit requiring no inversion and are capable of approximately 3.3 nanoseconds per stage in 5 micron CMOS technology. Unfortunately, this cascaded pass gate carry propagation path gets slower as the line becomes longer due to increased series resistance. The circuit illustrated in FIG. 4 helps to reduce the tendancy of the carry signal to become slower by regenerating the signal in the inverter 81. 
     A typical block diagram for the combining circuits 57, 59, and 61 in the final carry resolution row is illustrated in FIG. 5. The circuitry of FIG. 5 does not differ from that of FIG. 3 except that the AND gate 16 and the two inputs thereto are eliminated. If N and M represent relative small numbers, e.g. 5 or less, the combining circuit of FIG. 5 will be utilized for all of the combining circuits in the final carry resolution row, except the last or nth combining circuit. If more than approximately five combining circuits (n equals 5 or more) are utilized in the final carry resolution row, then a modification of the final combining circuits may be made to reduce the effect of the increased series resistance on the carry propagation path. 
     Referring specifically to FIG. 2, the nth row and the final carry resolution row of a sixteen-by-sixteen bit digital, repeated addition type multiplying circuit is illustrated. In this embodiment sixteen combining circuits 85 through 100 are included in the final carry resolution row and because of the length of the carry path the carry signal could become extremely slow. However, in this embodiment only the combining circuits 85, 86, 91, 92, 93, 98 and 99 are constructed as illustrated in FIG. 4. It should be noted that the combining circuits 87 and 94 regenerate the carry signal by including an inverter therein. It should be noted that it is not necessary to double invert the carry path in order to regenerate the carry signal and the combining circuits 88 and 89, following the combining circuit 87, and the combining circuits 95 and 96, following the combining circuit 94, utilize an inverted carry signal. After three or four carry path gates the inverted signal is again regenerated in an inverter, as in combining circuit 90 and 97, and the circuits following again utilize a non-inverted carry signal. Since the propagation delay of an inverter regenerator contributes substantially to the total, or average, carry path delay, the use of the inverted carry signal in subsequent combining circuits, rather than a double inverter regenerator, substantially improves the speed of the carry propagation line. Through extensive experimentation it has been determined that the fastest carry propagation line includes an inverter regenerator between every three or four pass gates. It will of course be understood by those skilled in the art that regeneration could be accomplished between as few as two pass gates and as many as five pass gates with only a small reduction in speed. While a double inverter regenerator is slower than the periodic single inversion described above, if the double inversion is limited to every 3rd or 4th adder circuit in a row it will be faster than prior art circuits which used a double inverter in every adder circuit. 
     A typical detailed block diagram for the combining circuits 87 and 94 is illustrated in FIG. 6, wherein the circuitry is the same as the combining circuits illustrated in FIG. 5 except that an inverter 102 is included between the transmission gates and the output terminal. The inverter 102 is the inverter regenerator for the carry signal. 
     A typical detailed block diagram for combining circuits 88, 89, 95, and 96 is illustrated in FIG. 7. The circuitry illustrated in FIG. 7 operates in a fashion substantially similar to the structure of FIG. 6, except that an inverted carry signal is received and an inverted carry signal is supplied to the output terminal C OUT . Because the carry signals are inverted, the signal from the B input terminal is inverted by an inverter 105 and the gate for adding the output of the first exclusive NOR gate to the carry input is an exclusive NOR gate 107. This change in circuitry allows the combining circuit to operate properly on an inverted carry signal input and to provide an inverted carry signal output. 
     A typical detailed block diagram for the combining circuits 90 and 97 is illustrated in FIG. 8. The circuitry of FIG. 8 is substantially similar to the circuitry of FIG. 7 except that an inverter 110 is included in the carry propagation line between the transmission gates and the output terminal. Thus, an inverted carry signal is applied to the circuit illustrated in FIG. 8 and a normal carry signal is available at the output thereof. 
     The final, or nth, combining circuit in the final carry resolution row, combining circuit 63 in FIG. 1 and 100 in FIG. 5, is constructed generally in accordance with the detailed block diagram of FIG. 9. Since the final combining circuit actually receives four inputs which must be added, a circuit containing at least three exclusive OR gates would normally be required. However, through the use of Boolean simplification the circuitry has been simplified to that shown in FIG. 9. A C IN  terminal is connected to one input of an exclusive NOR gate 115, the output of which is connected to one input of a second exclusive NOR gate 116. An input terminal A and an input terminal X 15  are connected to two inputs of an OR gate 117, the output of which is inverted and supplied to a second input of the exclusive NOR gate 115. A second input X 15  is made available and connected through an inverter 120 to the same inputs as the terminal X 15 , in case an inverted input is desired. A fourth input terminal B is connected to a second input of the exclusive NOR gate 116. The output of the exclusive NOR gate 116 is connected to the final output terminal of the multiplying circuit, P 6  in FIG. 1 and P 30  in FIG. 5. The output of the exclusive NOR gate 116 is also connected to one input of an AND gate 125. A second input of the AND gate 125 is connected to the input terminal A and a third input is connected to the input terminal X 15 . The output of the AND gate 125 is inverted and applied through an inverting amplifier 126 to an overflow detect output terminal. 
     Thus, a high speed NxM bit digital, repeated addition type multiplying circuit is disclosed which incorporates the Burks-Goldstine-VonNeumann corrections automatically to provide a relatively simple circuit. A sixteen-by-sixteen bit multiplying circuit can be incorporated on a single semiconductor chip and additional structure for reducing the input lines and the output lines to sixteen without substantially increasing the required time, is disclosed in FIG. 10. It will of course be understood that the sixteen-by-sixteen bit multiplying circuit is utilized as an example and that larger or smaller N and M numbers might be utilized if desired. In each of the above described combining circuits the specific structure disclosed represents a logic function which can be implemented in at least 4 equivalent ways. It will be understood by those skilled in the art that the logic functions described herein are intended to include all of these equivalent structures and not just the structure specified. 
     Referring specifically to FIG. 10, multiplexed-pipelined input and output buses are disclosed for a specific embodiment of a sixteen-by-sixteen bit multiplying circuit and it will be understood by those skilled in the art that many modifications, such as interchanging the components for the multiplier and multiplicand can be provided without substantially effecting the invention. In this embodiment sixteen input pads IN 0  through IN 15  are provided on the semiconductor chip carrying the multiplying circuit. The sixteen input pads are connected to sixteen input latches labelled X 0  through X 15 , for receiving the multiplicand bits. Each of the latches X 0  through X 15  has a slave latch S 0  through S 15  associated therewith. Each of the slave latches S 0  through S 15  has an output for supplying the sixteen multiplicand bits to the multiplying circuit. The input pads are also connected to sixteen latches designated Y 0  through Y 15  each having an output connected to the multiplying circuit for supplying the multiplier bits thereto. An input pad 130 is connected to receive an X or Y selection signal and a second input pad 131 is connected to receive clock pulses thereon. The pad 130 is connected through two inverters to an input of an AND gate 133 and through a single inverter to an input of a second AND gate 135. The pad 131 is connected through two inverters to a second input of the AND gate 133 and through a pair of inverters to a second input of the second AND gate 135. The outputs of the AND gates 133 and 135 are supplied to latch activating circuits 137 and 139, respectively. The latch activating circuit 137 is connected to the latches X 0  through X 15  and the latch activating circuit 139 is connected to the slave latches S 0  through S 15  and the latches Y 0  through Y 15 . 
     When a &#34;1&#34; is applied to the pad 130 and a clock pulse appears on the pad 131, the latch activating circuit 137 receives a &#34;1&#34; which activates the latches X 0  through X 15  and any information on the pads IN 0  through IN 15  is latched into the latches X 0  through X 15 . When a &#34;0&#34; is supplied to the pad 130 and a clock pulse appears on the pad 131, the latch activating circuit 139 receives a &#34;1&#34; and the latches S 0  then S 15  and Y 0  through Y 15  are activated so that all of the information in the latches X 0  through X 15  is moved into the slave latches S 0  through S 15  and any information then on the pads IN 0  through IN 15  is latched into the latches Y 0  through Y 15 . Thus, both the multiplier and the multiplicand, which contain a total of 32 bits, can be supplied simultaneously to the multiplying portion of the chip utilizing only sixteen input lines. 
     Similarly, the N+M-1 outputs are supplied to two sets of latches P 0  through P 14  and P 15  through P 30 . A multiplexing unit 145 having sixteen latches therein has outputs connected through sixteen gates 147 through 162 to sixteen output pads OUT 0  through OUT 15 . The gates 147 through 162 are enabled by a signal on a pad 165, which is connected to the gates 147 through 162 through a series of inverters. The inverters utilized herein, in conjunction with all of the connection pads, are designed to provide proper timing and signal polarity as will be understood by those skilled in the art. A pad 170, adapted to receive a clock signal thereon is connected through a plurality of inverters to the clock inputs of the latches P 0  through P 30 . The latches P 0  through P 30  are connected to the multiplexing circuit 145, which is controlled by means of a signal applied to a pad 171. When a &#34;1&#34; is applied to the pad 171 the bits stored in latches P 0  through P 14  are applied to the multiplexing circuit 145 and, these bits are then supplied to the output pads OUT 0  through OUT 15  in response to a signal applied to the output enable pad 165. When a &#34;0&#34; is applied to the pad 171 the bits contained in the latches P 15  through P 30  are supplied to the multiplexing circuit 145. Thus, an answer containing N+M-1 bits can be carried by means of N lines where N is at least as large as M. By providing the multiplexed-pipelined input and output circuitry described, the number of input and output lines can be substantially reduced and the time for supplying data to the multiplexing circuit and receiving data therefrom is not increased substantially since much of this switching can occur during the time that the multiplying operation is being performed. 
     Thus, an improved high speed N×M bit digital, repeated addition type multiplying circuit has been disclosed which is substantially faster and simplier than prior art structures and which can be incorporated on a single semiconductor chip. This fast multiplier is especially designed to be used in digital signal processing applications which require large numbers of multiply accumulates per second. Examples include dedicated FET boxes for radar processing, speech processing transforms, low power digital filters, etc. With 5 micron CMOS circuitry the multiply operation should be completed in approximately 500 nanoseconds and the circuitry will require only approximately 29 milliwatts at 5 volts. This is a substantial saving in power over prior art multipliers. 
     While I have shown and described specific embodiments of this invention, further modifications and improvements will occur to those skilled in the art. I desire it to be understood, therefore, that this invention is not limited to the particular forms shown and I intend in the appended claims to cover all modifications which do not depart from the spirit and scope of this invention.