Power on restart circuit
BACKGROUND OF THE INVENTION 
     This invention relates in general to power on reset circuits for use in initializing microprocessor-based systems. 
     When operating microprocessor-based systems, it is necessary to provide a logic reset signal to initialize the microprocessor when power is first applied. Various reset circuits for providing this initializing reset signal are known. However, known power on reset circuits consume considerable power when operating which is a disadvantage. 
     In addition, it is advantageous to provide a reliable reset pulse to re-initialize the microprocessor whenever a power line transient or momentary power outage occurs. Known power-on reset circuits for providing such protection are highly complex and/or are available only in the form of an integrated circuit, such as that shown in U.S. Pat. No. 4,013,902--Payne (Mar. 22, 1977). Simple independently adjustable circuitry for providing both initialization at first power &#34;on&#34; and re-initialization reset signals in response to low voltage power transients are believed to be unavailable. 
     SUMMARY OF THE INVENTION 
     Therefore, there is provided a power on reset circuit for generating a reset pulse for initializing a microprocessor-based system upon first power &#34;on&#34; and for generating a reset pulse in response to a low voltage power transient to re-initialize the system. The low voltage threshold and the duration of the reset pulses provided are easily changed so that the circuit is flexible, i.e. it is easily adaptable from system to system. Furthermore, the reset circuit draws little operating current compared to conventional reset circuits. 
     The circuit includes means for providing a threshold voltage related to the power supply voltage; a first inverter having an input coupled to the threshold voltage and having an output; a second inverter; a resistor coupling the output of the first inverter to the input of the second inverter; a third inverter; a second resistor coupling the output of the second inverter to the input of a third inverter; a capacitor, coupled from the input of the third inverter to circuit ground; transistor circuit means, coupled to the threshold voltage and to the input of the third inverter, for rapidly discharging the capacitor when the threshold voltage falls below the voltage on said capacitor by a predetermined amount; and a fourth inverter, having an input coupled to the output of the third inverter, and having an output for providing the reset pulses. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The invention will become better understood by the following detailed description and its appended claims when read with reference to the sole FIGURE. 
     The sole FIGURE is a detailed schematic diagram of the preferred embodiment of the reset circuit according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to the sole FIGURE, there is shown a detailed schematic diagram of the reset circuit according to the present invention. The reset circuit provides a logic level &#34;0&#34; (low) pulse to reset a microprocessor-based system 10. This reset signal is provided upon first power up and whenever there is a low voltage power transient from a power supply 40 providing power to a microprocessor-based system 10, i.e., whenever the power supply voltage drops below a predetermined threshold level. 
     All values shown in the FIGURE represent values for a CMOS implementation. However, by appropriate adjustment, and the use of appropriate active devices, the circuit is easily adapted to other types of technology. 
     The reset circuit includes four CMOS inverters 12, 14, 16, and 18 respectively. Logic power (5 volts) is obtained from a regulator 20 coupled to power supply 40. A threshold voltage is established by a voltage divider comprising a Zener diode 22 and resistor 24. This threshold voltage is coupled to the input of an inverter 12. By using a Zener diode in the voltage divider, the input voltage to inverter 12 will track the output voltage of power supply 40. Zener diode 22 is a six (6) volt diode for typical CMOS operation. 
     The output of inverter 12 is coupled to the input of a second inverter 14 via a resistor 26. A watchdog timer input can be coupled directly to the input of inverter 14. The output of inverter 14 is coupled through a resistor 28 to the input of a third inverter 16. A capacitor 30 couples the input of inverter 16 to circuit ground. The output of inverter 16 is coupled directly to the input of a fourth inverter 18 which provides, at its output, the reset pulses for microprocessor-based system 10. 
     A transistor 32 has its emitter-collector path coupled in parallel with capacitor 30. The base of transistor 32 is coupled to the input of inverter 12 so that it will respond to the difference in voltage between that of capacitor 30 and the threshold voltage established by the voltage divider including Zener diode 22 and resistor 24. 
     When power has been off for a sustained period of time, capacitor 30 is at zero voltage. When power is applied and the power supply voltage increases, the voltage to the input of inverter 12 crosses the CMOS threshold (about 3 volts) when voltage of power supply 40 exceeds approximately +9 volts. When the CMOS threshold of inverter 12 is exceeded, a logic level &#34;0&#34; (low) appears at the output thereof, forcing the output of inverter 14 to go high. When the output of inverter 14 goes high, capacitor 30 charges through resistor 28. The finite time delay provided by the time constant of resistor 28 and capacitor 30 causes a logic level low reset signal to appear at the output of inverter 18 for a predetermined interval of time, on the order of a few milliseconds. Of course, logic power will have already been provided to microprocessor-based system 10 and therefore, the reset signal at the output of inverter 18 will reset the microprocessor-based system to its appropriate initialized state during the time the reset line is held low. 
     After normal operation, there may come a time at which power supply voltage is interrupted. As power supply voltage falls, the voltage at the input of inverter 12 and the base of transistor 32 tracks closely the voltage drop of the power supply. Transistor 32 rapidly discharges capacitor 30 and thereby causes a logic &#34;1&#34; level (high) signal to appear at the output of inverter 16 which in turn causes a logic level &#34;0&#34; (low) signal to appear at the output of inverter 18. Capacitor 30 holds the output reset line low for a predetermined interval of time on the order of a few milliseconds while power is being reapplied through the 12-volt and 5-volt power supply lines. 
     Resistor 24 provides a load for Zener diode 22 so that a well defined voltage threshold is established at the input of inverter 12 and transistor 32. 
     Thus, there is provided a reset circuit providing a reset pulse of predetermined interval of time at initial power up of a microprocessor-based system and also provides a reset pulse upon a low voltage power supply transient for re-initializing the system. The reset circuit utilizes high impedance CMOS devices which in turn permit the use of a small capacitor 30 and a small inexpensive transistor 32 for providing rapid discharge of the capacitor.