Method of and circuit arrangement for automatic signal-level control
FIELD OF THE INVENTION 
     My present invention relates to a method of controlling the level of an incoming signal as well as to a circuit arrangement for implementing that method. 
     BACKGROUND OF THE INVENTION 
     In telecommunication equipment designed to receive incoming signals, especially those of the binary type, it is frequently desirable to stabilize the signal level at a predetermined value. Thus, an incoming signal of magnitude S should be multiplied by a level-controlling modifier X o  =R/S where R is a fixed reference value representing the desired signal amplitude. A direct establishment of modifier X o , however, is difficult since it would require continuous division of the fixed reference level R by the variable magnitude S. 
     Theoretically, the variable modifier X o  could also be determined through successive approximations by the use of an iterative algorithm such as one designed to minimize the squared error (X-X o ) 2  where X is an instant value approaching X o . The value X n  of parameter X at an instant t n  can be derived from an earlier value X n-1  (obtained at a preceding instant) from the relationship 
     
         X.sub.n =X.sub.n-1 -βΔ                          (1) 
    
     where β is a fractional constant designed to insure a stable feedback while Δ is the gradient of the squared error, being thus given by 2(X-X o ). Thus, equation (1) can be rewritten as follows: 
     
         X.sub.n =X.sub.n-1 -2β/S·(S·X.sub.n-1 -R)(2) 
    
     with X n-1  substituted for X in the foregoing expression for Δ. This gradient algorithm has the advantages of simplicity and speed of convergence; however, the need for division by the variable signal level S would again create considerable circuital problems. 
     A prior solution to this problem resides in the provision of a read-only memory (see, for example, Italian Pat. No. 980,804) storing different values for the quotient R/S in as many cells addressable by the incoming signal. Evidently, such a memory must have a large storage capacity if a substantial number of signal levels are to be accommodated. 
     OBJECTS OF THE INVENTION 
     An object of my present invention, therefore, is to provide a relatively simple method of electronically implementing the aforedescribed gradient algorithm without the need for division by the magnitude of a varible signal level. 
     A related object is to provide relatively inexpensive circuitry for putting that method into practice. 
     SUMMARY OF THE INVENTION 
     I have found, in conformity with my present invention, that the problem of circuital implementation can be solved by replacing S in the denominator of the second term of equation (2) with R/X n-1  as a close enough approximation thereof. Equation (2) then becomes 
     
         X.sub.n =X.sub.n-1 -kX.sub.n-1 ·(S·X.sub.n-1 -R) (3) 
    
     where k is a fractional coefficient equal to 2β/R. 
     Thus, the method according to my present invention comprises the steps of (a) multiplying the incoming signal S by a level-controlling modifier X n-1 , (b) differentially combining the thus-modified signal magnitude S·X n-1  with the fixed reference value R to produce an error signal equal to ±(S·X n-1  -R), (c) multiplying the error signal with modifier X n-1  and with the fractional coefficient k to produce a corrective value ±k·X n-1  (S·X n-1  -R), (d) algebraically combining this modifier with the corrective value to produce an updated modifier X n  conforming to equation (3), and (e) repeating steps (a) through (d) with the updated modifier X n . When the error signal disappears, i.e. when the product S·X n-1  becomes equal to R, the corrective term will be zero so that X n  =X n-1 . With periodic sampling of the incoming signal at a time when its level remains substantially constant, this result is generally attained after only a few sampling cycles. The updated modifier X n  produced in step (d) may be delayed by substantially a sampling period before being used to multiply another sample of the incoming signal S in a repeat of step (a). 
     A circuit arrangement designed to carry out the method outlined above includes first multiplier means with inputs connected to one lead carrying the incoming signal S and to another lead carrying the modification signal X n-1 , a first adder with inputs respectively connected to receive the modified signal amplitude S·X n-1  from a further lead together with the fixed reference signal R, second multiplier means with inputs connected to the first adder and to the aforementioned other lead for producing the corrective signal ±k(S·X n-1  -R), a second adder with inputs respectively connected to the second multiplier means and to that other lead for producing the updated modification signal X n , delay means connecting the output of the second adder to the aforementioned other lead for supplying same with the signal X n  after a certain lag enabling interative feedback to the second multiplier and adder, and signal-receiving means connected to one of the two last-mentioned leads for receiving either the modified signal S·X n-1  or the modifier X n-1  as an indication of the presence or absence of signal S. 
     When the incoming signal is absent, i.e. with S=0, equation (3) would yield a corrective value equal to kR·X n-1  resulting in an unstable operation with modifier X progressively incremented. Instability would also be caused with large values of X n-1  which could cancel out X n  or invert its sign. I therefore prefer to set an upper and a lower limit for the dynamic range of the modified signal magnitude S·X n-1  ; a suitable range limiter could be designed as a saturation circuit inserted either upstream or downstream (preferably the former) of a sampler between the first multiplier means and the further lead carrying the modified signal amplitude S·X n-1  to the first adder. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The above and other features of my invention will now be described in detail with reference to the accompanying drawing the sole FIGURE of which diagrammatically illustrates a circuit arrangement for the control of a signal level in accordance with my present improvement. 
    
    
     SPECIFIC DESCRIPTION 
     In the drawing I have shown a lead 1 carrying an incoming signal S to one input of a multiplier M 1  forming part of a level-control assembly CG, the multiplier having another input connected to a lead 2 carrying a modification signal X which at a given instant t n  has a value X n-1  generated at a preceding instant t n-1 . Multiplier M 1  has an output lead 3 extending to a saturation circuit SA which establishes a lower and an upper limit for the dynamic range of the product S·X n-1 , thus simulating a minimum value S min  and a maximum value S max  for signal S with signal X varying between a high value R/S min  and a low value R/S max . Circuit SA may comprise, for example, a two-stage amplifier whose inverting first stage saturates at an upper range limit while its second stage generates a predetermined maximum output voltage; at and below the lower range limit the first stage is cut off while the second stage generates a predetermined minimum output voltage of finite magnitude. The two limiting output voltages are so chosen that the corrective term k·X n-1  (S·X n-1  -R) has an absolute value progressively converging toward zero throughout the operating range. 
     Saturating circuit SA has an output lead 4 shown connected, on the one hand, to a load UT (e.g. a modem or a decoder) and, on the other hand, to a sampler RC driven by a train of periodic pulses CK from a nonillustrated clock. Sampler RC may be a simple gate but could also include an envelope detector of the linear or the RMS type operating on an incoming carrier wave. 
     A first adder SM 1  receives on one input (+) the output pulses of sampler RC, occurring at successive instants t 1 , t 2  . . . t n-1 , t n , t n+1  etc., and on another input (-) a d-c potential representing the fixed reference value R. The resulting error signal S·X n-1  -R is delivered to one input of a second multiplier M 2  whose other input is connected to lead 2 for receiving therefrom the modification signal X which at the instant t n  here considered has the value X n-1 . The product X n-1  ·(S·X n-1  -R) is transmitted to a normalizer NR for further multiplication by the fractional constant k=2β/R; the resulting corrective signal is then fed to one input (-) of a second adder SM 2  for algebraic combination with signal X n-1  from lead 2 to which another input (+) of that adder is connected. Thus, there appears on an output lead 5 of adder SM 2  the updated modification signal X n  delivered to lead 2 via a delay line RT which introduces a lag substantially equal to a sampling cycle corresponding to a period of clock pulses CK. Adder SM 2  and delay line RT could be replaced by an integrating operational amplifier with a time constant on the order of a clock-pulse period. Normalizer NR and multiplier M 2  could also be combined into a single unit. 
     The positive and negative signs on the inputs of both adders S 2  and SM 2  could be interchanged without altering the result. 
     Lead 2 is shown further connected to a signal detector RS with an output lead 6 feeding the modification signal X to another load UT&#39; which may be similar to load UT and may in fact replace same. With incoming signal S=0 and the voltage on lead 4 simulating the chosen minimum value S min , signal X is high; when signal S has an actual magnitude well above this simulated minimum, signal X will lie below the threshold of detector RS so that lead 6 will carry zero voltage. Thus, load UT&#39; receives the complement of the level-controlled binary signal SX fed to load UT via lead 4.