Multiprocessor system
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is related to the commonly assigned U.S. application Ser. No. 310,589, filed Oct. 13, 1981, entitled &#34;Apparatus for Controlling the Access of Processors at a Data Line&#34;. 
     BACKGROUND OF THE INVENTION 
     The present invention relates to a new and improved multiprocessor system. 
     Generally speaking, the multiprocessor system of the present development is of the type composed of a plurality of microprocessors or processors which are connected with a common collecting line serving for data transmission between the individual processors. Each processor or microprocessor is connected by means of a bus composed of address lines, data lines and control lines, with at least one respective read-only memory, read-write memory (RAM) and input-output components. 
     With such type multiprocessor systems each microprocessor or processor monitors the data transmission operations at the collecting line in consideration of data which is intended for such processor. The data transmitted by means of the collecting line or bus-bar contain, in each case, the addresses of those processors for which there is intended the related data. All microprocessors decode the addresses in order to determine the target processor. These state-of-the-art systems are afflicted with the drawback that they need a great deal of time for their operations, since all processors monitor the collecting line and the addresses must be decoded, and only the target processor is controlled. Additionally, this technique requires a relatively large expenditure in software. 
     In German Patent Publication No. 2,913,288 there has been taught to the art a multiprocessor system wherein these drawbacks are intended to be avoided. Between each processor and the collecting line there are arranged transmission or transfer devices structured such that the data exchange with the related processor only is accomplished during a predetermined repetitively occurring time interval. In this way the monitoring devices, instead of monitoring the related processors, monitor the collecting line in consideration of interruption requisitions or demands of other processors, so that in each instance there is only interrupted the course of the data processing of the addressed processor. 
     With the previously described multiprocessor system there can not be optimumly resolved certain data processing functions. If, for instance, there is to be accomplished a comparison of values determined according to the same criteria in the individual processors, then the comparison could be undertaken in each case between two processors, and the result is compared with the value of a further processor. It is possible to work in this fashion until there is determined the processor having, for instance, the smallest value. Depending upon the number of processors this technique requires a great deal of time and there is needed an appreciable expenditure in software. Also, the data transfer by means of the line or bus-bar for other purposes during the comparison interval is markedly limited. 
     SUMMARY OF THE INVENTION 
     Therefore, with the foregoing in mind it is a primary object of the present invention to provide a new and improved multiprocessor system which is not afflicted with the aforementioned drawbacks and limitations of the prior art constructions heretofore discussed. 
     Another and more specific object of the present invention aims at devising a multiprocessor system which is an improvement upon the heretofore described constructions, and which furthermore enables a rapid comparison of processors operating independently of one another, for instance results determined according to the same criteria, and the duration of the comparison operation is independent of the number of processors and the line or bus-bar is not made use of during the data comparison operation. 
     Now in order to implement these and still further objects of the invention, which will become more readily apparent as the description proceeds, the multiprocessor system of the present development is manifested by the features that, the results to be compared are transmitted to counters in connection logic components each of which is associated with a respective microprocessor. The connection logic components are connected via respective outputs to a comparison line which can be simultaneously activated from all outputs at the start of a comparison operation, the counters simultaneously starting to count at a delay from the moment of activation. The comparison line is deactivated again only when a transfer connection is made by that one of the counters with which the longest counting period is associated. For determining the deactivation the comparison line is in communication with respective inputs of all the connection logic components and an interrupt request can be generated by that one of the microprocessors with which that one of the counters is associated which has the longest counting period. 
     Some of the more notable advantages which can be obtained when practicing the invention essentially reside in the fact that by means of a single additional line there can be accomplished a rapid comparison of results determined at independently operating processors, and through the use of relatively modest expenditure in software and within the shortest amount of time it is possible to determine the processor having the best result. An additional advantage of the invention resides in the fact that for the coupling of the processors with the line there can be used standardized interface components which are augmented with relatively small expenditure by a connection logic composed of commercially available components. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be better understood and objects other than those set forth above, will become apparent when consideration is given to the following detailed description thereof. Such description makes reference to the annexed drawings wherein: 
     FIG. 1 is a block circuit diagram of a multiprocessor system according to the invention; 
     FIG. 2 is a block circuit diagram of a connection logic or logic circuit operatively correlated to each processor or microprocessor of the multiprocessor system; 
     FIG. 3 is a diagram showing the course as a function of time of the signals of the connection logic of a first processor (X) and a data comparison line; 
     FIG. 4 is a diagram illustrating the course as a function of time of a part of the signals shown in FIG. 3 of the connection logic of a second processor (Y) and the data comparison line; and 
     FIG. 5 is a diagram showing the course as a function of time of the signals according to FIG. 4 of the connection logic of a third processor (Z) and the data comparison line. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Describing now the drawings, in FIG. 1 reference characters X, Y and Z designate three mutually independent microcomputer systems. The microprocessors CPU of the microcomputer systems X, Y and Z are connected in appropriate fashion by means of a bus B composed of address lines, data lines and control lines, with at least one read-write memory or random access memory RAM and not here further illustrated read-only memories and input-output components. For the purpose of data exchange all of the microcomputer systems X, Y and Z are connected in appropriate fashion with a common bus-bar or collecting line BB. Each microcomputer system X, Y and Z is connected by means of a coupling device composed of a parallel interface component or block IF, a DMA-component DMA, meaning direct memory access component or block, a connection logic or connection logic circuit CONL and a bus driver BD with a line CL, which serves for the comparison of values determined according to the same criteria in the individual microprocessors CPU. 
     As best seen by referring to FIG. 2 the connection logic or connection logic circuit CONL possesses an output CLO connected by means of a bus driver BD with the data comparison line CL, referred to herein also as the cost bus CL. This output CLO is connected by means of a first NOT-gate or circuit 1 with the first output PH1 of a counter PHC, designated hereinafter also as a phase counter, and a second input of a first programmable logic arrangement PRL. The phase counter PHC serves for controlling the comparison which is accomplished during a number of phases. At a second output PH2 of the phase counter PHC, and which output PH2 is coupled with a third input of the first programmable logic arrangement PRL, there appears one-half of the signal frequency which is available at the first output PH1. By means of an input of the phase counter PHC, which is connected with an output REL of the parallel interface component IF, there can be freed the counter control. By means of a further input PHI of the phase counter PHC there is input a counter control signal generated by the first programmable logic arrangement PRL. Reference character CLI designates an input of the connection logic CONL which is coupled with the bus driver BD and by means of such bus driver reads the signal state or condition of the cost bus CL. The connection logic is operatively coupled with an input of a time-delay element DEL. At two outputs I5, I7 of the time-delay element DEL, and which outputs are connected with the first programmable logic arrangement PRL, there appears the step-shaped time-delayed signal of the input CLI of the connection logic CONL. 
     A binary counter, designated hereinafter as the cost counter BC, possesses twelve parallel inputs D0-D11, which are directly connected with the data lines of the bus B of the related microprocessor system X, Y and Z. During a comparison operation there are loaded into the cost counter BC the values to be compared in the form of a 12-bit binary number BK. The cost counter BC possesses an incrementing connection INCR and a transfer or carry connection TRF. The incrementing connection INCR is coupled by means of a second NOT-gate or element 2 with a second output and the transfer connection TRF is connected to a sixth input of the first programmable logic arrangement PRL. An input D15 of the connection logic CONL which transmits during the comparison operation a further bit Co is connected, on the one hand, with a data line of the bus B and, on the other hand, with the inputs J, K of a first JK-flip-flop 3, whose output Q is coupled with an input of a second programmable logic arrangement PRL2. 
     Reference numeral 4 designates a second JK-flip-flop, whose inputs J, K are connected with a further output of the first programmable logic arrangement PRL and whose output Q is connected with an input DMARQ of the DMA-component DMA, this input reading a DMA-requisition or requirement signal. An output DMAOP of the DMA-component DMA, and which signals a continuous DMA-operation, is coupled with a first input of the first programmable logic arrangement PRL and with a set-connection of the JK-flip-flop 4. By means of an output TR of the parallel interface component IF, which is connected by means of a NAND-element or gate 5 with a further input TRI of the first programmable logic arrangement PRL, there can be triggered a DMA-operation. 
     The signal appearing at the outputs of the first programmable logic arrangement PRL connected to the further input PHI of the phase counter PHC, to the DMARQ input of the DMA-component and to the INCR connection serve for controlling the phase counter PHC. The signals appearing at the DMARQ input and at the second ouput of the first programmable logic arrangement PRL, representing the DMA-requisition or demand and the triggering of the incrementing operation of the cost counter BC are generated as a function of the signals appearing at the previously described inputs in accordance with the following logical equations: 
     
         PHI=PH1.15.I7+PH1.PH2.I5.I7+PH1.PH2.I5.I7+CLKA 
    
     wherein 
     
         CLKA=PH1.PH2.TRF+PH1.PH2.DMAOP 
    
     
         ARQO=PH1.PH2.TRI.DMAOP.I7; ENG=PH1.PH2.I7 
    
     A third JK-flip-flop 6, whose output Q is connected with its first input J as well as with the second input of a NAND-gate or element 5 and an input INTRQ of the parallel interface component IF, is coupled by means of its second input K at an output ACT of the second programmable logic arrangement PRL2. By means of the input INTRQ of the parallel interface component IF there can be transmitted an interruption requirement or demand appearing at the output Q of the third JK-flip-flop 6. By means of a set-input S connected with the input TR of the parallel interface component IF there can be again extinguished the interruption requirement or demand. The clock connection CLK of the third JK-flip-flop 6 is connected to a third output DEL3 of the time-delay element DEL, which possesses a further input connected to the first output PH1 of the phase counter PHC, wherein the signal present at its input appears with a time-delay at the third output DEL 3 of the time-delay element. 
     The second programmable logic arrangement PRL2 possesses further inputs connected with the second output PH2 at the phase counter PHC and with the input CLI of the connection logic CONL. The signal appearing at the output ACT is produced as a function of the signals appearing at the previously described inputs in accordance with the following logical equation: 
     
         ACT=PH2.CLI.Co+PH2.CLI.Co 
    
     The terminals and connections which are needed for inputting the clock signal to the connection logic CONL have been omitted from the drawings in order to facilitate the presentation and for clarity in the showing of the circuitry. The described digital logic coupling elements and components are commercially available devices, wherein, for instance, there can be used for the DMA-component, the parallel interface component IF and the bus driver BD those available from Texas Instrument under Type TMS9911, TMS9901 and SN75138. The signals appearing at the different inputs and outputs of the components, and there is to be expressly also understood signal sequences or trains, have been designated with the same reference characters as the related inputs and outputs. 
     Having now had the benefit of the foregoing description of the multiprocessor system of the invention its mode of operation, during a data comparison operation, will be considered and is as follows: 
     It is assumed by way of example and not limitation that the microcomputer system X, Y and Z are correlated to the individual elevators or lifts of a group of elevators composed of three elevators, and the microcomputer systems can serve both for the drive control and regulation and also, for instance, for the timewise optimization of the correlation of elevator cabins to the storey or floor calls. In the last-mentioned case each microcomputer system computes from certain elevator-specific parameters, such as for instance the distance between a considered call storey and the elevator cabin, the number of possible intermediate stops which are to be expected within such distance predicated upon the existing elevator cabins and storey calls already correlated to such elevator cabins as well as the momentary cabin load, a time-proportional sum BK. This sum BK, in the form of a binary number, and corresponding to the service capability of an elevator cabin with respect to the considered call or calling storey, is written into a random access memory or read-write memory RAM of the related microcomputer system X, Y and Z, and wherein the address of the storage place corresponds to the number of the momentarily considered calling storey. During a comparison of the sums BK x , BK y , BK z  of the microcomputer systems X, Y and Z, and which comparison is carried out for such storey or floor, the elevator cabin having the smallest sum BK, corresponding to the smallest loss-time of waiting passengers, is allocated to the considered calling storey or floor of the building or structure service by the elevator cabins. 
     The comparison is accomplished in a number of timewise successive phases. During a first phase A there are controlled all parallel interface components IF by a synchronization signal emanating from a microprocessor CPU and transmitted by means of the bus-bar BB to all other microprocessors of the system. Hence, there appears a signal change at the output REL of the parallel interface components IF at approximately the same time intervals or times I, II, III (FIGS. 3, 4 and 5), whereupon there is released the control of the phase counter PHC. With the initially accomplished release, for instance that of the phase counter PHC of the microcomputer system X, there is activated the cost bus CL, and it is capable of possessing a low potential (time I, FIG. 3). The output CLO and the input CLI of the connection logic CONL, designated hereinafter as the comparison output CLO and the comparison input CLI, are thus set at a high potential. After the release of the last phase counter PHC (time III, FIG. 5) there occurs at a time IV (FIGS. 3, 4 and 5) determined by means of the time-delay element DEL and signalling with a time-delay the activation of the cost bus CL, at all of the microcomputer systems X, Y and Z at the same time a change of the output signal I7. At the DMARQ output of the first programmable logic arrangement PRL there occurs a signal change and there is produced by means of the second JK-flip-flop 4 a DMA-requisition or requirement signal. The individual DMA-components then signal in appropriate fashion to the momentarily correlated microprocessor CPU that they desire the control over the data bus. This is accomplished after a certain latent time, and the DMA-component delivers a signal at the output DMAOP (time V, FIG. 3), at the start of which the further phase counter-control input PHI is set low and the DMARQ output controlling the DMA-requirement is set high. During the duration of the at the output DMAOP the DMA-component delivers an address to the address bus, so that a storage place of the read-write or random access memory RAM containing the sums BK which are to be compared is caused to respond, whereupon the memory or storage place content is transferred by means of the data bus and the inputs D0-D11 into the cost counter BC. At the same time there is transferred by means of the input D15 a control bit Co and stored in the first JK-flip-flop 3. In this context Co=1 signifies that the related microcomputer system X, Y and Z, during the preceding comparison of the same storey or floor, has determined and stored the smallest sum BK. By the same token Co=0 means that the related microcomputer system X, Y and Z does not possess the smallest sum BK. After the, for instance, initially accomplished termination of the data transfer of the microcomputer system X and the disappearance of the signal at the DMAOP output, the control signal at PHI and the first phase signal at PH1 of the phase counter PHC goes high (time VI, FIG. 3), so that the corresponding comparison output CLO of the connection logic CONL is set low. After completion of the data transfer of the last of all of the microcomputer system, for instance the microcomputer system Y, the potential of the cost bus CL is set high and all of the comparison inputs CLI are set low (time VII, FIG. 4). 
     Following a time-delay of the signal CLI, governed by the time-delay element DEL, the signals I5 and I7 successively go to a lower potential, and the phase counter-control signal at PHI first is set at a lower and then at a higher potential. As a consequence the first phase signal at PH1, the second phase signal at PH2 and the signal at CLO of all microcomputer systems X, Y and Z simultaneously change, so that the cost bus CL is again activated and there is initiated a second phase B of the comparison (time VIII, FIGS. 3, 4 and 5). Since at this point in time the cost bus CL changes to a lower potential and all of the comparison inputs CLI to a higher potential, also the signal I7, after a certain time-delay is set high, and by means of the first programmable arrangement PRL there is brought about a change of the signal at INCR and there is simultaneously initiated an incrementing operation of all of the cost counters BC (time IX, FIGS. 3, 4 and 5). 
     It is here assumed that the cost counter BC of the microcomputer system X (FIG. 3) contains the largest sum BK and thus, the smallest complement BK. This cost counter BC therefore will be the first to produce a signal at the transfer connection TRF, and there occurs a double change of the phase counter-control signal at PHI which causes the setting of the first phase signal at PH1 at a high potential, and thus, the comparison output CLO of the related connection logic CONL at a lower potential as well as a change of the signal at INCR which terminates the incrementizing operation (time X, FIG. 3). Furthermore, it is assumed that the microcomputer system X, predicated upon the last comparison, has determined the smallest sum BK, and the control bit Co=1. In this case, since the cost bus CL still exhibits a low potential and all comparison inputs CLI as well as the second phase signal at PH2 controlling the second phase B exhibits a high potential (time X, FIG. 3), there is initiated by means of the second programmable logic arrangement PRL2 a change of the signal ACT at the second input K of the third JK-flip-flop 6. Upon change of the clock signal at DEL 3 appearing with a time delay with respect to the first phase signal at PH1 at the clock connection CLK of the third JK-flip-flop 6 (time XI, FIG. 3) there is produced at its output Q an allocation interruption by means of which the microprocessor CPU of the microcomputer system X, by means of the input INTRQ of the parallel interface component IF, is caused to change the control bit Co which is stored in the random access memory or read-write memory RAM in addition to the sum BK, from a logical state &#34;1&#34; to the logic state &#34;0&#34;. 
     It is further assumed that the microcomputer system Z (FIG. 5), during the preceding comparison, has stored the control bit Co=0, but however during the momentary comparison possesses the smallest sum BK, and thus, the greatest complement BK, so that here the transfer is produced last (time XII, FIG. 5). Consequently, the first phase signal at PH1 and the cost bus CL go to a high potential and the comparison output CLO as well as all comparison inputs CLI go to a low potential. Upon change of the clock signal of the third JK-flip-flop 6 (time XIII, FIG. 5) appearing with a time-delay with respect to the first phase signal at PH1, there is likewise produced at its output Q an allocation interruption by means of which the microprocessor CPU of the microcomputer system Z is caused to change, by means of the input INTRQ of the parallel interface component IF, the control bit Co which has been stored in the read-write or random access memory RAM, in addition to the sum BK, from a logic state &#34;0&#34; to the logic state &#34;1&#34;. Thus, as already previously mentioned, the elevator associated with the microcomputer system Z can be allocated to the considered calling storey or floor and can service such storey of the building. 
     If the comparison during the phase B indicates that a number of systems have determined exactly the same sums BK, then in a further third phase C there can be determined the optimum system by means of a suitable device which determines the priority. 
     While there are shown and described present preferred embodiments of the invention, it is to be distinctly understood that the invention is not limited thereto, but may be otherwise variously embodied and practiced within the scope of the following claims. Accordingly,