Interface circuit for an integrated injection logic circuit
BACKGROUND OF THE INVENTION 
     This invention relates to an interface circuit for an integrated injection logic circuit as used in an interface between the integrated injection logic circuit and the other circuit. 
     A fundamental circuit of the integrated injection logic circuit (I 2  L circuit) comprises, as shown in FIG. 1, a PNP transistor Q I  as an injector and an output NPN transistor Q 0  having at least one open collector. Since a greater load cannot be driven with one transistor Q 0 , an interface circuit is required for the I 2  L circuit to drive the other circuit, for example, a TTL circuit. 
     FIGS. 2 and 3 each show a conventional interface circuit as used in an interface circuit between an I 2  L circuit and a TTL circuit. The interface circuit as shown in FIG. 2 comprises three NPN transistors Q 1  to Q 3 , three resistors R 1  to R 3  and one diode D 1 . An output of an I 2  L inverting gate G as configured in FIG. 1 is applied to the base of the NPN transistor Q 1 . The interface circuit as shown in FIG. 3 comprises two PNP transistors Q 4 , Q 5 , two NPN transistors Q 6 , Q 7  and seven resistors R 4  to R 10 . An output of an I 2  L inverting gate G as configured in FIG. 1 is applied through the resistor R 5  to the base of the PNP transistor Q 4 . In the conventional interface circuit it is not possible to obtain an arbitrary output voltage and there is a disadvantage that high and low level output voltages are fixed to certain levels. In the interface circuit of FIG. 2, for example, a high level output voltage is V CC  -2V F  and a low level output voltage is V CE  (sat) (Q 3 ). In the interface circuit as shown in FIG. 3 the high level output voltage is V CC  -V CE  (sat)(Q 5 )-V BE  (Q 7 ) and the low level output voltage is zero (ground potential). 
     SUMMARY OF THE INVENTION 
     It is accordingly an object of this invention to provide an interface circuit for an integrated injection logic circuit which can freely set the value of an output voltage. 
     According to this invention there is provided an interface circuit for an integrated injection logic circuit comprising a first resistor, a current mirror circuit having its input current value set by a first resistor and having its input controlled by an output signal of the integrated injection logic circuit, a second resistor inserted in an electric current path at the output side of the current mirror circuit, and an output means connected to the output terminal of the current mirror circuit. 
     According to another embodiment of this invention there is provided an interface circuit for an integrated injection logic circuit which comprises a first resistor, a first current mirror circuit having its input current value set by the first resistor and having its input controlled by an output signal of the integrated injection logic circuit, a second current mirror circuit connected to receive an input current set by a second resistor and having its current output terminal connected at a common junction to a current output terminal of said first current mirror circuit, a third resistor connected to a common current path at the output side of the first and second current mirror circuits, and input means connected to the common current path of the first and second current mirror circuits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a fundamental circuit of an I 2  L circuit; 
     FIG. 2 is a conventional interface circuit as used in an interface between an I 2  L circuit and a TTL circuit; 
     FIG. 3 is a conventional interface circuit as used in an interface between an I 2  L circuit and a TTL circuit; 
     FIG. 4 is an interface circuit for an integrated injection logic circuit according to one embodiment of this invention; and 
     FIGS. 5 to 9 each show an interface circuit for an integrated injection logic circuit according to another embodiment of this invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 4 shows an interface circuit for an integrated injection logic circuit according to one embodiment of this invention. The FIG. 4 circuit comprises two current mirror circuits M 1 , M 2 , an NPN transistor Q 15  and four resistors R 11  to R 14 . The current mirror circuit M 1  comprises two NPN transistors Q 11 , Q 12  having their bases connected in common and their emitter areas equal to each other. The emitters of the NPN transistors Q 11 , Q 12  are each connected to ground and the collector-to-base path of the NPN transistor Q 11  is short-circuited. Likewise, the other current mirror circuit M 2  comprises two NPN transistors Q 13 , Q 14  having their bases connected in common and their emitter areas equal to each other. The emitters of the NPN transistors Q 13 , Q 14  are grounded and a collector-to-base path of the NPN transistor Q 14  is short-circuited. To a common junction of the bases of the NPN transistors Q 11 , Q 12  in the current mirror circuit M 1  is connected an output terminal of an I 2  L inverting gate G at an output stage of the I 2  L circuit. A resistor R 11  is connected between the collector of the NPN transistor Q 11  at the input side of the current mirror circuit M 1  and the positive terminal of a power source V CC  to set an input current value I 1  of the current mirror circuit M 1 . Likewise, a resistor R 12  is connected between the collector of the NPN transistor Q 14  at the input side of the other current mirror circuit M 2  and the positive terminal of the power source V CC  to set an input current value I 2  of the current mirror circuit M 2 . The collectors of the NPN transistors Q 12 , Q 13  at the output side of both the current mirror circuits M 1 , M 2  are connected to each other and a resistor R 13  is connected between a junction P of the collectors of the transistors Q 12 , Q 13  and the positive terminal of the power source V CC . The NPN transistor Q 15  and emitter resistor R 14  of the transistor Q 15  constitutes an emitter follower output circuit and the base of the NPN transistor Q 15  in the emitter follower output circuit is connected to the junction point P. An output terminal Out is connected to the emitter of the NPN transistor Q 15  and also to the input terminal of the other circuit such as a TTL circuit. 
     The operation of the interface circuit will be explained below. 
     With the I 2  L inverting gate G ON i.e. the NPN transistor Q 0  of FIG. 1 ON, an electric current I 1  through the resistor R 11  flows into the I 2  L inverting gate G, causing the NPN transistors Q 11 , Q 12  to be cut off. As a result, the current mirror circuit M 1  is not operated. Since an electric current I 2  set by the resistor R 12  flows into the input side of the current mirror circuit M 2 , an electric current I 2   of the same value also flows at the output side of the current mirror M 2 . That is, the electric current I 2  flows through the resistor R 13 . With the base-to-emitter voltage of the NPN transistor Q 15  represented by V BE  (Q 15 ), an output voltage V O  on the output terminal Out is given by the following equation: 
     
         V.sub.O =V.sub.CC -I.sub.2 ·R.sub.13 -V.sub.BE (Q.sub.15) (1) 
    
     That is, the output voltage V O  is equal to value by subtracting a voltage drop I 2  ·R 13  through the resistor R 13  and base-to-emitter voltage V BE  (Q 15 ) of the NPN transistor Q 15  from the power source voltage V CC . At this time, the value of the output voltage V O  corresponds to a value at the high level output time. 
     With the I 2  L inverting gate G OFF, the electric current I 1  through the resistor R 11  flows through the current mirror circuit M 1  and thus flows through the NPN transistor Q 12  at the output side of the current mirror circuit M 1 . As a result, an electric current corresponding to a sum of I 1  and I 2  flows through the resistor R 13  and at this time the output voltage V O  on the output terminal Out can be given by: 
     
         V.sub.O =V.sub.CC -(I.sub.1 +I.sub.2)·R.sub.13 -V.sub.BE (Q.sub.15)                                                (2) 
    
     In this case, a voltage drop through the resistor R 13  becomes greater than the counterpart in the equation (1) and at this time a value of the output voltage V O  corresponds to a value at the low level output time. 
     Here, ##EQU1## with V OL  and V OH  representing the output voltage V O  at the low level time and output voltage V O  at the high level output voltage V O , respectively, the equations (1) and (2) can be rewritten as follows: ##EQU2## where V BE  (Q 11 ): the base-to-emitter voltage of the NPN transistor Q 11   
     V BE  (Q 14 ): the base-to-emitter voltage of the NPN transistor Q 14   
     As evident from the equations (5) and (6) the output voltages at the high and low level output times can be freely set by a ratio of the resistances of the resistors R 11 , R 12  and R 13 . Thus, the output voltage can be adjusted with high accuracy in obtaining an integrated circuit. 
     FIG. 5 shows an interface circuit according to another embodiment of this invention, in which two current mirror circuits M 1 , M 2  are provided, one being constituted of two PNP transistors Q 21 , Q 22  and the other being constituted of two PNP transistors Q 23 , Q 24 . In this case, an output voltage V O  becomes equal to a value as obtained by subtracting a basse-to-emitter voltage V BE  (Q 15 ) of an NPN transistor from a voltage drop through a resistor R 13 . With an I 2  L inverting gate G ON the output voltage V O  becomes a high level V OH  and with the I 2  L inverting G OFF the output voltage V O  becomes a low level V OL . The values of V OH  and V OL  are given by: ##EQU3## where V BE  (Q 21 ): the base-to-emitter voltage of the PNP transistor Q 21   
     V BE  (Q 24 ): the base-to-emitter voltage of the PNP transistor Q 24   
     Even in this circuit, the values of the output voltages V OH , V OL  can be freely set by a ratio of the resistances of the resistors R 11 , R 12  and R 13 . 
     An interface circuit as shown in FIG. 6 corresponds to a circuit as obtained by eliminating a current mirror circuit M 2  and resistor R 12  from the FIG. 4 circuit. In this circuit, with an I 2  L inverting gate G ON an output voltage V OH  at the high level time is fixed at a value V CC  -V BE  (Q 15 ). With the I 2  L inverting gate G OFF the output voltage V OL  at the low level time becomes a value V CC  -I 1  ·R 13  -V BE  (Q 15 ). In this circuit, only the output voltage V OL  at the low level time can be freely varied by setting a ratio of the resistances of resistors R 11 , R 13 . 
     FIG. 7 shows an interface circuit in which the current mirror circuit M 1  of FIG. 6 is replaced by a current mirror circuit comprised of two PNP transistors Q 21 , Q 22 . In this circuit, with the I 2  L inverting gate G OFF an output voltage V OL  at the lower level time is fixed at a low level i.e. at a ground level. With the I 2  L inverting gate G ON, the output voltage V OH  at a high level time becomes a value I 1  ·R 13  -V BE  (Q 15 ). In this circuit, only an output voltage V OH  at the high level time can be freely varied by setting a ratio of the resistances of resistors R 11 , R 13 . 
     This invention is not restricted to the above-mentioned embodiments. Although this invention has been explained in connection with, for example, the case where two transistors of each of the current mirror circuits M 1 , M 2  have the equal emitter areas, a greater or a smaller output current may be taken from the output side of the circuit with the emitter areas of the two transistors set at a predetermined ratio. 
     Instead of setting the ratio of the emitter areas of the pair of transistors constituting the current mirror circuit, a resistor R 15  may be connected to the emitter circuit of one of a pair of transistors in the current mirror circuit as shown in FIGS. 8 and 9 and, by so doing, a greater or a smaller output current may be taken from an output side. Since in the circuit as shown in FIGS. 8 and 9 the resistor R 15  is connected to the emitter circuit of the NPN transistor Q 11  at the input side of the current mirror circuit M 1 , a greater output current is taken from the output side.