Microprocessor bus interchange circuit
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a microprocessor system and more particularly to a bus interchange circuit which allows external systems to gain control of a microprocessor&#39;s busses. 
     2. Description of the Prior Art 
     Older microprocessors, such as Intel&#39;s 8-bit 8080A and 8085A provide bus interchange functions such as hold request and hold acknowledge. These functions are not available in current state-of-the-art microprocessors, such as Intel&#39;s 8086. These microprocessors however, do have a control lead for use by co-processors, such as Intel&#39;s 8089 Input-Output Processor and Intel&#39;s 8087 Numeric Data Processor. This lead can also be used as a bus interchange &#34;handshake&#34; control lead by emulating the pulse sequences produced by the co-processors. Thus, hold request and hold acknowledge functions, can be provided by state-of-the-art microprocessors through use of a circuit which emulates the &#34;handshake&#34; operation of a co-processor. 
     Accordingly it is the object of the present invention to provide a bus interchange &#34;handshake&#34; control circuit for use with a state-of-the-art microprocessor. 
     SUMMARY OF THE INVENTION 
     The present invention is a circuit which converts the co-processor control lead of a microprocessor into a bus interchange &#34;handshake&#34; lead. This circuit performs the &#34;handshake&#34; function through emulation of a co-processor. 
     A two-bit counter and an associated decoder are used to generate pulses in response to an external microprocessor access request and termination of such request. A tri-state gate is used to interface with the microprocessor. Gating circuits and an associated flip-flop are used to generate an acknowledge signal upon detection of a signal from the microprocessor indicating that the access request has been granted. This acknowledge signal informs the external system that it has gained control of the microprocessor&#39;s busses and it also commands the microprocessor to &#34;float&#34; its bus control leads. 
    
    
     DESCRIPTION OF THE DRAWING 
     The single FIGURE of the accompanying drawing is a logic diagram of a microprocessor bus interchange circuit in accordance with the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to the accompanying drawing, the microprocessor bus interchange circuit of the present invention is shown. When an external system requests access to the memories of the system of the present invention it places a logic level 1 hold signal on lead 901a. During the next clock pulse this logic level 1 signal is transferred to the Q output of D-type flip-flop 901. This logic level 1 signal then appears at the D input of D-type flip-flop 902 on lead 902a. At the next successive clock pulse flip-flop 902 transfers this logic level one signal to its Q output and it appears on lead 902b. Thus D-type flip-flops 901 and 902 act as a 2-bit shift register. After flip-flop 901 has clocked in a logic 1 signal to its Q output in response to a hold signal, flip-flop 901 has a logic level 1 on its Q output and flip-flop 902 has a logic 0 on its Q output. Similarly flip-flop 901 will have a logic 0 on its Q output and flip-flop 902 will have a logic 1 on its Q output. Gates 903 and 904 each generates a logic level 0 signal in response to these conditions and gate 905 accordingly generates a logic level 1 signal which turns on tri-state gate 906. When this gate is turned on it places a logic level 0 signal on lead 906b which represents an access request signal to the processing units. 
     This request signal remains applied until the next clock pulse which causes D-type flip-flop 902 to transfer the logic level 1 signal on its D input to its Q output. In this situation gate 903 generates a logic level 1 signal in response to a logic level 1 on both of its inputs. This causes gate 905 to generate a logic level 0 signal thereby turning off tri-state gate 906 and when this gate is turned off it removes the request signal by placing a logic level 1 signal on lead 906b. Thus the request signal is a pulse having the same duration as one clock cycle. 
     When the processing unit has determined that it can release control of its buses and memory it applies a logic level 0 grant signal on lead 906b. This logic level 0 signal is inverted to a logic level 1 signal by inverter 907 and applied to gate 908. Since the Q outputs of both flip-flops 901 and 902 are also at a logic level 1, when the next clock pulse appears gate 908 generates a logic level 0 signal on the pre-set input of D-type flip-flop 910 thereby causing a logic level 0 hold acknowledge signal to appear on lead 910a. This signal is used to inform the external system that it now has control of the internal buses and memory. Gate 911 also responds to the hold acknowledge signal to generate a float signal which is used by the processing units to float the buses and control signals. Gate 911 also generates this float signal in response to a float command on lead 911b from the external system. 
     When the external system is ready to release control of the processing units it removes the hold signal from lead 901a. During the next clock pulse on lead 901b D-type flip-flop 901 transfers the logic 0 signal on lead 901a to its Q output and places a logic level 1 signal on its Q output. Consequently gates 903 and 904 again generate logic level 0 signals causing a logic level 1 signal on the output of gate 905 thereby turning on tri-state gate 906 and applying a second logic level 0 request signal on lead 906b. 
     This second request signal also has a duration equal to the period of one clock cycle. This request signal informs the processing unit that it can regain control of its buses and memory. Since flip-flop 901 is reset and flip-flop 902 is set gate 909 generates a logic level 0 signal at the next clock pulse thereby clocking a logic level 1 signal onto the output of flip-flop 910. Thus the hold acknowledge signal is removed and the external system is informed that the processing unit has regained control of its buses and memory. 
     It will be obvious to those skilled in the art that numerous modifications of the present invention can be made without departing from the spirit of the invention which shall be limited only by the scope of the claims appended hereto.