Switch condition indicator
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The present invention relates to the identification of a single closed switch in a switch array and particularly to the provision of both visual and coded electrical indicia commensurate with such a closed switch. More specifically, this invention is directed to logic circuitry which may be associated with plural, parallel connected switches for providing a coded signal which identifies a closed switch while simultaneously causing energization of a light emitter associated with the closed switch. Accordingly, the general objects of the present invention are to provide novel and improved methods and apparatus of such character. 
     (2) Description of the Prior Art 
     The present invention is particularly useful with circuits known in the art as &#34;tip switch banks&#34;. A &#34;tip switch bank&#34; comprises a plurality of switches wherein actuation of the switch contacts, i.e., making or braking, results from touching or &#34;tipping&#34; only. The switches comprising the &#34;bank&#34; may, for example, be momentary contact type switches or some other type of touch sensitive switch. The switches forming the &#34;bank&#34; may be functionally interrelated such that only the last switch &#34;tipped&#34; by the user is &#34;valid&#34; or enabled while all other, i.e., formerly actuated, switches are rendered &#34;invalid&#34; (disabled or cancelled). In this case, the switches of a &#34;tip switch bank&#34; are electrically mutually latched and only a single switch will at any one time be in the &#34;actuated&#34; state. In any case, however, each switch of the &#34;bank&#34; is provided with a light emitter, for example an indicator lamp, which will visually signal the state of its associated switch. In the typical case, the light emitter associated with the last switch of the &#34;bank&#34; to have been actuated will be energized. 
     &#34;Tip switch banks&#34; of the type briefly described above are frequently employed in electronic organs as the user input which determines the sound coloration when conventional musical instruments of different nature are to be simulated. Thus, a signal which identifies the last actuated switch will be employed to address a controlled circuit such as a filter, memory or the like to cause production of the audible output commensurate with the actuated switch. 
     In prior art &#34;tip switch bank&#34; control circuits the indicator lamp associated with each switch is allocated to one of the parallel outputs of a shift register. Binary data was serially shifted through the register under supervision of a control unit. The contents of the shift register were &#34;permanently&#34; available at the parallel outputs thereof in the form of &#34;high&#34; and &#34;low&#34;, i.e., binary, voltage levels. The light emitting indicators were all also connected to a common bus which had applied thereto either the binary &#34;high&#34; or &#34;low&#34; voltage level. Thus, if the &#34;high&#34; or binary &#34;1&#34; voltage level is applied to the bus, an output of the shift register which has a binary 0 appearing thereon will result in the light emitter connected to that output being energized since there will be a sufficient potential difference across the light emitter to cause current to flow therethrough. With no switch actuated, all of the parallel data outputs of the shift register will be &#34;high&#34; and thus current will not flow through the light emitters associated therewith. The state of the output of the shift register will be read out as address information for a controlled or circuits such as filters, memories or the like. 
     Thus, in accordance with the prior art, upon actuation of one of the &#34;tip switches&#34; a control unit will load the shift register with binary data corresponding to the actuated switch. If another switch is &#34;tipped&#34;, this fact must be signalled back to the control unit so that it may update the loading of the shift register. This signaling has previously been accomplished by individually connecting each switch to the control unit. Alternatively, all of the switches of the &#34;bank&#34; were scanned by means of a separate multiplexer. In either case the resulting circuitry is comparatively complex, particularly when the &#34;bank&#34; comprises a large number of switches. 
     SUMMARY OF THE INVENTION 
     The present invention comprises novel and improved circuitry for identifying and providing an indication of the state of actuation of the individual switches of an array of switches, particularly a &#34;tip switch bank&#34;. A circuit in accordance with the present invention comprises a shift register and a control unit. The parallel data outputs of the shift register are individually connected to first terminals of the switches of the bank and to first terminals of the light emitting devices associated with the respective switches. The control unit causes the sequential loading of the shift register so as to transfer its contents to an output channel whereby the scanning of the switches is accomplished with a minimum of components, particularly wired connections. 
     In accordance with the present invention a first terminal of each of the switches is directly connected to one of the parallel data outputs of a shift register and to a first terminal of an associated light emitter. The second output terminal of all of the switches are connected to a common signaling bus to which a binary voltage level will be applied. The second terminals of each of the lamps are connected to a power bus to which a first binary voltage level is constantly applied. The signal bus serves as the input to a control unit which, via the shift register, periodically applies the second of the binary voltage levels to the switch first terminals. If one of the switches is closed when the said second binary voltage level is applied to its first terminal an input signal will be delivered to the control unit. This input signal will cause the application of bits at the first binary level to the serial data input of the shift register. The reappearance of the said first binary level at the shift register output corresponding to the closed switch will identify that switch. Upon identification of the actuated switch a &#34;word&#34; will be clocked into the shift register which will maintain a potential commensurate with the difference between the binary levels across the light emitter associated with the last closed switch whereby the light emitter will be energized. 
     In apparatus in accordance with the present invention only four, and in some cases only three, connections are needed between the control unit and the switch &#34;bank&#34; and its associated shift register. This is a significant reduction in circuit complexity when compared to the prior art. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The present invention may be better understood and its numerous objects and advantages will become apparent to those skilled in the art by reference to the accompanying drawing wherein like reference numerals refer to like elements in the two figures and in which: 
     FIG. 1 is a schematic diagram of a first embodiment of the present invention; and 
     FIG. 2 is a schematic diagram of a second embodiment of the present invention. 
    
    
     DESCRIPTION OF THE DISCLOSED EMBODIMENTS 
     With reference to FIG. 1, the present invention comprises a control unit 10 which is preferably a micro processor, e.g. type INTEL 8048, a shift register 14, a parallel array of &#34;tip&#34; switches 18 and a plurality of lamps or other light emitters 20. Control unit 10 applies serial input data via conductor 12 to shift register 14. After the shift register has been clocked through a first time, its parallel data outputs 16.1, 16.2, - - - 16n will carry the binary data inputted by control unit 10. Presuming that one of the switches 18 has been actuated, and in the manner to be described in greater detail below, a level 0 will appear on the parallel data output 16 of shift register 14 corresponding to that last-actuated switch 18. The parallel data outputs 16 of shift register 14 are each connected to a first terminal of a switches 18 and to a first terminal of the lamp 20 which are associated with that the switches. The lamps are preferrably housed in the switch keys. The second terminals of all of lamps 20 are connected to a common power bus 22 which carries the high potential level &#34;V&#34;, i.e., the binary voltage level corresponding to a &#34;1&#34;. Thus, in the steady state condition being explained, the lamp 20 connected to the last-actuated switch 18 will have a potential difference thereacross whereby current will flow through the lamp and it will provide a visually perceivable output. 
     The switches 18 will be devices of the type which, when their actuators are touched by a user, will close a circuit between the switch terminals. As noted above, one of the terminals of each of the switches is connected to a respective one of the parallel data outputs 16 of shift register 14. The second terminals of all of the switches 18 are connected to a signal bus 24, the switch terminals being briefly interconnected upon the switch being &#34;tipped&#34;. Signal bus 24 is connected, via a resistor 26, to the power bus 22. Accordingly, when all of the switches 18 are in the open state, i.e., in the time periods between &#34;tipping&#34; of the switches, a binary &#34;1&#34; will appear on signal bus 24. As will also be described in more detail below, upon the &#34;tipping&#34; of one of switches 18, the binary level 0 will be momentarily applied to signal bus 24. 
     In order to determine whether one of the switches 18 has been &#34;tipped&#34;, and to identify the last &#34;tipped&#34; switch, the control unit 10 periodically applies an erase signal via conductor 28 to shift register 14. Upon application of the erase command, all of the parallel data outputs 16 of shift register 14 will be switched to the 0 level. If one of the switches 18 is closed at the time the contents of shift register 14 are erased, the level 0 will be applied via that closed switch to signal bus 24 and thus will appear at the control input to the control unit 10. The appearance of a 0 level on the signal bus input to control unit 10 will result in the control unit shifting &#34;high&#34; level bits, i.e., &#34;1&#39;s&#34;, through the shift register at a rate commensurate with the frequency of the clock input 30 to shift register 14. Such high or V-level shifting will continue until a &#34;1&#34; appears on the data output 16 corresponding to the last-actuated switch. Since the switch will, at this time, still be in the closed state, the &#34;1&#34; level is applied to signal bus 24, i.e., the &#34;0&#34; input level will be removed from the input to control unit 10. The number of high level bits generated since start of the shift cycle by the control unit will identify the position of the last-actuated switch 18 in the serial sequence at the shift register output, the shifting of &#34;1&#39;s&#34; through the shift register being terminated upon reapplication of the high or &#34;1&#34; binary level to signal bus 24. 
     In order to keep the lamp associated with all depressed and not mutually latched switches in the energized state, upon reappearance of the high binary level on signal bus 24, control unit 10 will store the identity of the last-actuated switch and will load a &#34;word&#34;  commensurate with this identity into shift register 14 such that all of the parallel data outputs will be at the &#34;1&#34; level with the exception of the output corresponding to the depressed, non-latched switches which will be at the &#34;0&#34; level. 
     In the mode of operation described above, the signal for testing the status of the switches 18 is applied to the erase line 28. As an alternative, the control unit 10 may, during one shift cycle, deliver &#34;0&#39;s&#34; to the serial data input 12 until the low binary level is applied to the signal bus 24 via the last-actuated switch. While this alternative design reduces the number of connections between control unit 10 and the remainder of the circuitry from four to three, the control unit becomes somewhat more complex because of the increased amount of data to be processed. 
     In the embodiment described above, upon each test or scan of the switch &#34;bank&#34;, the contents of the shift register 14 will be erased and reestablished. This may not be desirable under circumstances where the switches 18 are only occasionally actuated. Under these circumstances the embodiment depicted in FIG. 2 may be employed. In the FIG. 2 embodiment an AND gate 32 is associated with each of the switches 18. The gates 32 are all enabled by the erase output 28&#39; of control unit 10. The FIG. 2 embodiment reduces the quantity of data which must be handled by control unit 10 by permitting the contents of shift register 14 to remain initially unerased during the testing cycle. 
     To summarize the above, the circuit of the present invention operates in two distinctly different modes. Firstly, to detect an actuated switch, all of the data outputs 16 of the shift register are simultaneously set to zero by an &#34;erase&#34; command and thus all of the lamps 20 will be momentarily energized. However, this period of energization is so short that the lamps either will not light or the period of illumination will be so short as to be imperceptible to the human eye. Signal bus 24 will be at the binary level &#34;1&#34;, the voltage being applied to bus 24 via resistor 26, and will remain at this level if none of switches 18 has been actuated. Upon actuation of a switch 18, bus 24 will be connected to the corresponding data output 16 of shift register 14 and signal bus 24 will thus be pulled down to level &#34;0&#34;. The switch which has been actuated is identified by shifting one&#39;s into shift register 14, as explained above, until bus 24 returns to the &#34;1&#34; level. Secondly, to illuminate a lamp 20 commensurate with an actuated switch, the number of that switch is clocked into register 14 whereby a &#34;0&#34; input level is applied to one terminal of the lamp to be illuminated via the shift register data output 16. 
     It will be understood that the number of switches 18 which may be employed in the practice of the present invention is not limited to three or four, as depicted in the drawing, and that the shift register 14, e.g. type F4164 standard TTL, is of a type which is commercially available. It will further be understood that if there are more switches 18 than the number of parallel data outputs of the shift register it is possible to add additional shift registers. 
     Employing the present invention in the environment of an electronic organ, the &#34;test&#34; pulse on the erasing line 28 from the control unit 10 need be generated only every 100 ms. 
     If a plurality of the switches 18 are accidentally simultaneously actuated, the one which is last in the shift sequence will be identified as the &#34;valid&#34; switch. 
     It is to be noted that the &#34;test&#34;, &#34;scan&#34; or &#34;inquiry&#34; pulse will briefly apply a potential difference across all of the light emitters 20. However, the duty cycle is too small to cause the lamp or other light emitter to produce a visual output in response to the testing. 
     A further advantage of the present invention resides in the fact that it does not require the use of circuitry, for example flip-flop circuits, to suppress contact bounce in the case where the switches 18 comprises mechanical switches. 
     Referring again to the FIG. 2 embodiment, it is to be noted that it is possible to employ &#34;tri-state&#34; shift registers, e.g. 74LS374 standard TTL, which include the AND gates 32 thus enabling the more simplified wiring of FIG. 1 to be employed with the circuit of FIG. 2. 
     While preferred embodiments have been shown and described, various modifications and substitutions may be made thereto without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the present invention has been described by way of illustration and not limitation.