Differential amplifier having a compensation current injection selector network
BACKGROUND OF THE INVENTION 
     This invention relates generally to differential amplifiers and more particularly to differential amplifiers having a pair of input transistors. 
     As is known in the art, differential amplifiers have been used in a wide variety of applications including use in the input stage of operational amplifiers. One such differential amplifier includes a pair of input transistors having first electrodes coupled to a common current source, second electrodes providing a pair of inputs for the differential amplifier, and third electrodes coupled either directly to passive resistive loads, or indirectly to such passive resistive loads through an active current mirror circuit to provide an output for the differential amplifier. Such differential amplifiers may include as the input transistors thereof either bipolar transistors or field effect transistors. When bipolar transistors are used, the base electrodes provide the pair of inputs for the differential amplifier with typically the emitter electrodes being connected to the common current source. When field effect transistors are used as the input transistors, the gate electrodes provide the pair of input electrodes and typically the source electrodes are connected to the common current source. In either case, when such differential amplifier is used as the input stage of an operational amplifier, mismatches in the voltages between the base and emitter electrodes (i.e. V be ) in the case of bipolar transistors or in the voltages between the gate and source electrodes (i.e. V gs ) in the case of field effect transistors, result in an undesirable temperature sensitive offset voltage being produced at the output of the operational amplifier (such offset voltage being defined as the voltage required at the pair of input terminals from a zero source impedance to drive the output voltage produced by the operational amplifier to zero volts). It is further noted that since the offset voltage is inversely related to the transconductance of the transistors and since the transconductance of field effect transistors is an order of magnitude lower than the transconductance of bipolar transistors, while it is important to reduce V be  mismatches in bipolar transistors, it is even more critical to reduce the effect of mismatching in V gs  in field effect transistors. 
     As is also known, the V be  of a bipolar transistor is a function of the emitter area and doping concentration while the V gs  of a field effect transistor is a function of gate channel dimensions and doping concentration. Thus, during wafer fabrication, emitter areas, channel dimensions and doping concentrations are controlled and are matched for the pair of input transistors as far as possible to provide a pair of matched input transistors. However, despite this fabrication process control the input transistors may have dimensions and/or doping concentration mismatches. Various techniques suggested to compensate for these fabrication process mismatches include the injecting of a compensating current directly into the passive resistive loads so that the voltages at the outputs of the differential amplifier are equal at the quiescent operating point, i.e. when both transistors pass equal amounts of current produced by the current source. With one technique, a pair of current sources are provided to inject compensating currents into both passive resistive loads, the amount of current injected into each one of the loads being adjusted by trimmable resistors. While such technique may be useful in some applications, imbalances in the compensating currents over the operating range of temperatures because of temperature changes in the trimmed resistors will generally result in concomitant imbalances over the operating range of temperatures. In other one of such techniques, here when an active current mirror is used between the pair of resistive loads and the outputs of the differential amplifier, a single compensating current is injected directly into one of the passive resistive loads. With such arrangement, because the injected current introduces an error in the match of the currents in the current mirror and while balanced at one temperature the balance is not maintained over a relatively wide range of operating temperatures. Thus, the control circuit suggested to direct the injected amount to the proper one of the pair of resistive loads causes an error uncertainty and imbalance of the desired balanced current mirror transistors over a wide range of temperatures. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a differential amplifier is provided having: a pair of input transistors with first electrodes connected to a first voltage potential through a first current source, a second pair of electrodes providing a pair of input terminals for the differential amplifier, and a third pair of electrodes connected to a pair of terminals, the current produced by the first current source passing through the first and third electrodes of the pair of input transistors into the pair of terminals in a ratio related to the difference in voltage of input signals fed to the pair of input terminals and the degree of mismatch in the pair of input transistors. A selector network injects a compensation current substantially equal to the difference in the currents passing through the pair of input transistors when the voltages at the pair of inputs are equal, and which results from a mismatch in such pair of input transistors, into a selected one of the pair of terminals. A balanced current mirror has an input coupled to a first one of the pair of terminals and an output coupled to a second one of the pair of terminals for forcing current passing into the second one of the pair of terminals through the output of the current mirror to be substantially equal to current passing into the first one of the pair of terminals to the input of the current mirror with an output current passing from the second one of the pair of terminals to an output stage, such output current being substantially zero when the voltages at the pair of input terminals are equal to thereby compensate for the difference in the currents passing through the pair of input transistors as a result of the mismatch in the pair of input transistors. 
     In a preferred embodiment of the invention, the selector network includes: a plurality of additional current sources, each one thereof being matched, over a predetermined range of operating temperatures, to the first current source; and means, fed by the plurality of additional current sources for passing a selected portion of the current produced by the additional current sources to a selected one of the pair of outputs as the compensating current and for diverting the remaining unselected portion of the total current produced by the plurality of additional current sources form the pair of outputs to the second voltage potential. The current mirror includes a pair of bipolar transistors with collector electrodes thereof coupled to the pair of outputs, base electrodes connected together and emitter electrodes coupled to the second voltage potential. The selector network includes a transistor having: a plurality of input electrodes coupled to the plurality of additional current sources and, a selected one, or ones thereof, coupled to a selected one of the pair of outputs; a second electrode coupled to the second voltage potential; and a third electrode coupled to the second one of the pair of outputs through a bias circuit. The bias circuit provides a bias voltage between the second and third electrodes of the transistor of the selector network to inhibit current from the selected portion of the total current produced by the plurality of circuit sources from passing through such transistor and for allowing the remaining unselected portion of such total current to pass through the first and third electrodes of such transistor to the second voltage potential. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The aforementioned aspects and other features of the invention are explained in the following description taken in connection with the accompanying drawing in which: 
     FIG. 1 is a schematic diagram of an operational amplifier according to the invention; and 
     FIG. 2 is an equivalent circuit representation of a Zener diode used in the operational amplifier of FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring now to FIG. 1, an operational amplifier 10 is shown to include in the differential amplifier input stage 12. The differential amplifier input stage 12 includes a pair of input transistors, here junction field effect (JFET) transistors J 1 , J 2  having source electrodes thereof connected to a first voltage potential source V+ through a current source 14. The current source 14 includes a junction field effect transistor J 3 , having the gate and source electrodes thereof connected together and to the first voltage source V+ with the drain electrode thereof being connected to the source electrodes of transistors J 1 , J 2  at terminal 16, as shown. The gate electrodes of input JFET&#39;s J 1 , J 2  provide a pair of inputs 15, 17 for the operational amplifier 10. The drain electrodes of the pair of input JFET&#39;s J 1 , J 2  are connected to a pair of output terminals 19, 21 for the differential amplifier input stage 12. A current mirror 20 is coupled betweenn the pair of output terminals 19, 21 and a second voltage potential source -V, as shown. The current mirror 20 has an input coupled to one of the pair of output terminals 21, 19 here to output terminal 21 of the differential amplifier 12, as shown and an output 24 coupled to output terminal 21 of the differential amplifier 12, as shown. More particularly, the current mirror 20 includes a pair of matched bipolar transistors Q 1 , Q 2  having collector electrodes connected to outputs 19, 21, respectively, as shown. The emitter electrodes of the pair of transistors Q 1 , Q 2  are connected to the second voltage source V- through a pair of resistive loads, here matched equal valued resistors R 1 , R 2 , as shown. The base electrodes of transistors Q 1 , Q 2  are connected together, as shown and to the emitter of transistor Q 6 , as shown and to the second voltage source V- through resistor R 3 , as shown. Current mirror 20 hence forces the current passing from terminal 21 into the collector electrode of transistor Q 2  (i.e. the current I d ) to be substantially equal to the current passing from terminal 19 into the collector electrode of transistor Q 1  (i.e. the current I c ). The base electrode of transistor Q 6  is connected tothe collector electrode of transistor Q 1  and the collector electrode of transistor Q 6  is connected to the +V sources, as shown. 
     A selector network 21 is provided. Such network 21 includes a plurality of, here five, current sources I 1  to I 5  provided by a junction field effect transistor J 4 , such transistor J 4  having a plurality of drain electrodes D 1  to D 5 , respectively formed with different areas. The areas of the drain regions of field effect transistor J 4  are scaled in successive 2:1 ratios so that the area of the drain region designated D 2  is twice the area of the drain region D 1 . Likewise, drains D 3 , D 4 , D 5  have drain areas four times, eight times, and sixteen times larger, respectively than the drain region of drain D 1 . The gate and source electrode of transistor J 4  are connected together and to the first voltage source V+, as shown. It is also noted that the field effect transistor J 4  is thermally and physically matched to field effect transistor J 3  so that if the drain current of transistor J 3  is designated as I s , the currents I 1  to I 5  through drains D 1 , D 2 , D 3 , D 4 , D 5  may be represented as AI s , 2AI  s , 4AI s , 8AI s  and 16AI s , respectively where A is a constant less than one, here A is one hundredth (0.01). 
     The selector network 21 is provided to selectively couple the current produced by one or more of the plurality of current sources I 1  to I r  as a compensating current to a selected one of the output terminals 19, 21 of the differential amplifier 12 for reasons to be described in detail hereinafter. Suffice it to say here, however, that the selector network 21 includes a plurality of Zener diodes Z 1  to Z 5  having cathodes thereof connected to corresponding ones of the drain electrodes D 1  to D 5  of field effect transistor J 4 . The anodes of the Zener diodes Z 1  to Z 5  are connected together at a common terminal 40, as shown. The anode electrodes of a pair of Zener diodes Z s1 , Z s2  are connected together at terminal 40. The cathodes of Zener diodes Z s1 , Z s2  are connected to the output terminals 19, 21, respectively, as shown. A multi-emitter, PNP bipolar transistor Q 3 , has the emitter electrodes E 1  to E 5  thereof connected to corresponding ones of the plurality of current sources I 1  to I 5 , respectively, and more particularly to the drain electrodes D 1  to D 5 , respectively, of the field effect transistor J 4 . The collector electrode of transistor Q 3  is connected to the second voltage source V-, as shown. The base electrode of transistor Q 3  is connected to a bias circuit 42, as shown. The bias circuit 42 includes a pair of matched field effect transistors J 6 , J 7  having source and drain electrodes serially connected between the first voltage source V+ and the second voltage source V-, as shown. It is noted that the gate electrode of transistor J 6  is connected to the source electrode thereof and that the gate electrode of transistor J 7  is connected to the output 24 of the current mirror 20, i.e. to the collector electrode of transistor Q 2 . The source electrode of transistor J 7   provides a bias voltage for transistor Q 3  and such source electrode of transistor J 7 , in addition to being connected to the drain electrode of transistor J 6 , is connected to the base electrode of transistor Q 3 , as shown. Completing the operational amplifier 10, an output stage 44 is coupled to the output terminal 21 via a buffer 45 in a conventional manner. Here, the output terminal 24 is coupled to the base of transistor Q 4  through output line 24. The collector of transistor Q 4  is coupled to the V+ source and the emitter of transistor Q 4  is coupled to ground through resistor R 3 . A grounded emitter transistor Q 5  has its base connected to the emitter of transistor Q 4  and its collector to current output stage 44, as shown. The output stage includes biasing circuitry fed by the +V source, as indicated. 
     In order to compensate for any mismatch between the gate-to-source voltages V gs  of the input junction field effect transistors J 1 , J 2 , the selector network 21 injects into one of the output terminals 19, 21 a compensating current. The magnitude of this compensating current is substantially equal to the difference in current flowing through JFET&#39;s J 1 , J 2  when the voltages fed to the inputs 15, 17 are equal to each other. Thus, the compensating current is substantially equal to the difference in currents passing through the input JFET&#39;s J 1 , J 2  as a result of their V gs  mismatch. More particularly, if the current into output terminal 19 from JFET J 1  is designated I a , and the current into output terminal 21 from JFET J 2  is designated I b , it follows that at the quiescent operating point when the voltage at input 15 is equal to the voltage at input 17, I a  will equal I b  if the JFET&#39;s J 1 , J 2  are matched with equal V gs  ; however, in the the practical case the V gs  of the transistors J 1 , J 2  will not be equal and hence at this quiescent operating point I a  ≠I b . In the absence of a compensating current being supplied from selector network 21, the current I a  will flow out of output terminal 19 into the collector of transistor Q 1  and I a  will be equal to I c . Because of the transistors Q 1 , Q 2  of current mirror 20, the current I c  passing out of output terminal 21 and into the collector of transistor Q 2  will equal the current I d . Further, the current passing out of output terminal 21 will be equal to the current I b  passing into output terminal 21. Hence, since the output current I 0  through output line 25 is equal to I d  -I b  and since because of the current mirror 20 I d  =I c  where I c  =I a , it follows that the output current will be equal to I 0  = I b  -I a  thus producing an erroneous output voltage for the operational amplifier. Here, however, a compensating current is formed by short circuiting a selected one or ones of the Zener diodes Z 1  to Z 5  so that a proper portion (substantially equal to |I a  -I b  |) of the total current produced by the plurality of current sources I 1  to I 5  flows into terminal 40. It is noted that because there are only a finite number of current sources, here five current sources I 1  to I 5 , available to form the magnitude of the compensating current, a finite error will result, the magnitude of the error being related to the number of current sources being provided. The short circuiting of a Zener diode is performed by applying a voltage of proper magnitude and polarity across the anode and cathode of the diode to be short circuited from an external voltage source, not shown. This process is described in an article entitled &#34;A Precision Trim Technique for Monolithic Analog Circuits&#34; by George Erdi, published in IEEE Journal of Solid-State Circuits, Vol. SC-10, No. 6, Dec.1975, Pages 412 to 416. Thus, the diodes Z 1  to Z 5 , Z sl , Z s2  may be represented as a switch, a relatively small resistance resistor and diode as shown in FIG. 2 for an exemplary one of the diodes, here Zener diode Z s1 . This compensating current is then steered to a selected one of the output terminals 19, 21 by short circuiting a selected one of the Zener diodes Z s1 , Z s2 . If diode Z s1  is shorted, the compensating current designated I c2  is fed into output terminal 19 whereas if diode Z s2  is shorted, the compensating current designated I c1  is fed into output terminal 21. Thus, the proper amount of compensating current is steered into output terminal 19 or output terminal 21 so that at the quiescent operating point when the voltage at input 15 equals the voltage at input 17, the output current I 0  will be substantially zero even though the V gs  of JFET J 1  does not equal the V gs  of JFET J 2 . That is, if I a  is greater than I b , the compensating current I c1  =I a  -I b  is injected into output terminal 21 by short circuiting Zener diode Z s2  whereas if I b  is greater than I a , the compensating current I c2  =I b  -I a  is injected into output terminal 19 by short circuiting Zener diode Z s1 . Thus, if I a  &gt;I b , I c  =I a , I d  =I b  +I c1 , and since the current mirror forces I d  =I c , it follows that I 0  =(I b  -I a ) +I c1 . But, since I c1  =I a  -I b , I 0  is zero. Likewise, if I b  &gt;I a , I c  =I a  +I c2 , I d  =I b , and since the current mirror forces I c  =I d , it follows that I 0  =I b  -(I a  +I c2 ), but since I c2  =I bc  -I a , I 0  is zero. In any event, the current mirror 20 substantially equalizes the currents I c , I d , passing out of the output terminals 19, 20 so that I c  =I d  when the voltages at the input terminals are equal, in which case I 0  will be substantially zero. In this way, any imbalance in the voltage between the gate and source electrodes of field effect transistors J1, J2 are compensated, and I 0  will be substantially zero when the voltages at inputs 15, 17 are equal. It is noted that since resistors R 1  and R 2  are matched and since the transistors Q 1 , Q 2  are matched, the current mirror 20 is a balanced current mirror and thereby provides temperature tracking over the operating range of temperatures. It is further noted that the remaining portion of the current produced by the plurality of current sources I 1  to I 5  which does not form a portion of the compensating current is diverted from the current mirror 12 and passes through the bipolar transistor Q 3  to the second voltage source V-. In order to ensure that this unused remaining portion of the current produced by the plurality of current sources I 1  to I 5  is diverted from the current mirror 20, a proper bias voltage is applied to the base electrode of transistor Q 3  . To provide this assurance, it is noted that current fed to an emitter of transistor Q 3  will pass to the collector of such transistor Q 3  if the emitter of such transistor Q 3  is at a more positive voltage than the base of such transistor Q 3 . Thus, it is noted that when a selected one of the Zener diodes Z 1  to Z 5  is short circuited and a selected one of the Zener diodes Z s1 , Z s2  is shorted, the voltage at the collector electrode of the one of the transistors Q 1 , Q 2  being fed the compensating current, appears at the emitter electrode of transistor Q 3  connected to such shorted one of the diodes Z 1  to Z 5 , Z s1 , Z s2 . Therefore, since transistors J 6  and J 7  are matched, and since the voltage between the gate and source electrodes of transistor J 6  is zero, the voltage at the source electrode of transistor J 7 , and hence the voltage at the base electrode of transistor Q 3 , will be equal to the voltage at the collector electrode of the one of the transistors Q 1 , Q 2  being fed the compensating current. Therefore, the voltage at the base electrode of transistor Q 3  will be equal to the voltage at the one of the emitter electrodes of such transistor Q 3  connected to the shorted Zener one of the Zener diodes Z 1  to Z 5 . For example, if Zener diodes Z 1  and Z 3  are shorted, a compensating current (I s  +4I s ) passes to terminal 40. If Zener diode Z s2  is shorted, the voltage at the collector electrode of transistor Q 2  appears at emitters E 1  and E 3  of transistor Q 3  and such voltage also appears at the base of transistor Q 3 . Thus, since the voltage at the base of transistor Q 3  will be equal to the voltage at emitters E 1  and E.sub. 3 and circuits I 1 , I 5  will not pass through transistor Q 3  but rather will provide the desired compensating current by passing to terminal 40. It is noted, however, that emitter E 2 , E 4  and E 5  will be at a more positive potential than the potential at the base of such transistor because the Zener breakdown voltage is greater than the base-emitter voltage drop produced across the base-emitter junction of transistor Q 3 . That is, the voltages on the emitter E 2 , E 4  and E 5  will rise until either transistor Q 3  conducts or Zener Z 3  conducts. Transistor Q 3  will conduct when the voltages at the emitters E 2 , E 4  and E 5  are one V be  (i.e. one base to emitter voltage drop, V be ) higher than the voltage at the base electrode of transistor Q 3 , whereas the Zener diode Z 3  will conduct when the voltage between the voltage at the emitter E 2  and terminal 40 is greater than the Zener breakdown voltage of diode Z 3 . Since the Zener breakdown voltage of diodes Z 1  to Z 5  are much greater than the one V be , transistor Q 3  will conduct, and hence currents I 2 , I 4  and I 5  will pass through the collector and emitter electrodes of transistor Q 3  to the second potential voltage source V- and will thereby be diverted from the current mirror 20. On the other hand, if Zener diode Z s1  were shorted rather than Zener Z s2 , the voltage at the emitters E 1  and E 3  would be equal to the voltage at the collector of transistor Q 1  while the base of transistor Q 3  would be at the voltage at the collector of transistor Q 2 . It is also noted that the voltage at the collector of transistor Q 2  will be equal to the V-+(V beQ5  +V beQ4 ) where V- is the voltage of the second voltage potential, V beQ5  is the voltage across the base-emitter junction of transistor Q 5  and V beQ4  is the voltage across the base-emitter junction of transistor Q 4 . Also, the voltage at the collector electrode of transistor Q 1  is equal to V-+(V beQ2  +I e  R 2  +V beQ6 ) where V beQ2  is the voltage across the base-emitter junction of transistor Q 2 , I e  is the current through resistor R 2  (assuming negligible base current for transistor Q 2 ) and V beQ6  is the voltage across the base-emitter junction of transistor Q 6 . Here, V beQ5  =V beQ4  =V beQ2  =V beQ6  and I e  R 2  &lt;&lt;V beQ5 , so that under this condition the voltage at the collector electrode of transistor Q 1  is equal to the voltage at the collector of transistor Q 2  and hence currents I 1  and I 3  are inhibited from flowing through transistor Q 3  and are diverted to terminal 40 while currents I 2 , I 4  and I 5  pass through transistor Q 3  to the second potential source V- and are diverted from terminal 40. 
     It should be noted that with the compensation circuit described, the current mirror remains balanced and the bias circuit 42 ensures that the compensation current passes to the current mirror with the remaining current being diverted from the current mirror. 
     Having described a preferred embodiment of the invention, it is now evident that other embodiments incorporating these concepts may be used. It is felt, therefore, that this invention should not be restricted to the disclosed embodiment but rather should be limited only by the spirit and scope of the appended claims.