MOS Driver circuit having capacitive voltage boosting
TECHNICAL FIELD 
     This invention relates generally to driver circuits and, more particularly, to an MOS driver circuit utilizing a capacitive voltage booster which time sequentially provides a boosted control voltage. 
     BACKGROUND ART 
     Generally, driver circuits which utilize a voltage booster circuit have used a bootstrap circuit. In MOS technology, one of several implementations of a bootstrap circuit embodies the use of enhancement type transistors and a depletion type MOS capacitor. Typically, a transistor is used as a switching device and another transistor is used as a load device which is coupled to an output terminal. Although the bootstrap circuit can provide an output driver voltage which is greater than the supply voltage, the load device is always conductive when the switching transistor is conductive and creates a standby or static current. To avoid an undesirable output voltage for low logic levels, the size of the load and switching devices must be maintained at specific ratios to one another. Further, since a capacitor is generally connected to an output, the driver circuit has a slow output rise time when capacitively loaded. A modification of the bootstrap circuit is a mirrored bootstrap circuit which may be used to improve the output rise time. However, a standby current also exists in such mirrored bootstraps. Also, most bootstrap circuits are limited in that the capacitive boosting voltage is only some fraction of the supply voltage. Charge on a capacitor in bootstrap circuits can also be lost by discharge through a precharge device and by parasitic capacitances coupled to ground potential. As a practical result, the output driver voltage can never attain twice the value of the supply voltage. Further disadvantages include the fact that in order to drive high capacitance loads, bootstrap circuits must use large enhancement type load transistors which increase the power consumed by the circuit. Large device sizes also slow the performance of the driver and impact die size and yield. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention is to provide an improved MOS driver circuit utilizing a capacitive boost circuit. 
     Another object of the invention is to provide an improved MOS driver circuit having time sequential capacitive boosting of transistor gate control voltages. 
     Yet another object of the invention is to provide an improved MOS driver having high speed characteristics and using less power than driver circuits of the prior art. 
     In carrying out the above and other objects of the present invention, there is provided, in one form, an MOS driver circuit comprising active load and switching devices which are coupled between two supply voltages and to an output. The driver devices are controlled by a boosted driver voltage which is substantially above the level of one of the supply voltages and which is provided by a capacitive voltage booster circuit. The capacitive voltage booster circuit comprises two capacitors which are time sequentially precharged by first and second precharge devices, respectively, and also discharged. The first capacitor boosts the control voltage of the second precharge device which is used to charge the second capacitor. The second capacitor boosts the driver voltage thereby reducing both the size of the driver devices and the power dissipation and increasing the speed of the MOS driver. A clamping device restricts the range of the control voltage of the second precharge device to prevent partial discharge of the second capacitor while the second capacitor is providing the boosted driver voltage. Control means are utilized to sequentially vary the charge on the second capacitor in response to the level of an input voltage signal. 
     The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates in schematic form a driver circuit utilizing a bootstrap technique known in the prior art; 
     FIG. 2 illustrates in schematic form yet another driver circuit utilizing a bootstrap technique known in the prior art; 
     FIG. 3 illustrates in schematic form a driver circuit constructed in accordance with the preferred embodiment of the present invention; and 
     FIG. 4 illustrates in graphical form selected voltages associated with the circuit of FIG. 3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Shown in FIG. 1 is an MOS embodiment of a common bootstrap circuit 10 which provides an output voltage in response to an input voltage changing from a high logic level to a low logic level. While specific N-channel MOS devices are shown for all circuits which are discussed, it should be clear that all the circuits could be implemented by completely reversing the processing techniques (E.G. N-channel to P-channel) or by using other types of transistors. A transistor 12 has the gate and drain thereof connected to a supply voltage, say V DD . A driver transistor 14 has a drain connected to supply voltage V DD , a gate connected to a source of transistor 12, and a source connected to an output at a node 16. A capacitor 18 which is fabricated in a conventional manner from a transistor structure has the source and drain thereof connected together to form a first electrode or plate, and has a gate which forms a second electrode or plate. The first plate of capacitor 18 is connected to the source of transistor 14 and to the output at node 16, and the second plate is connected to both the source of transistor 12 and the gate of transistor 14 at a node 20. A switching transistor 22 has a drain connected to the first plate of capacitor 18, to the source of transistor 14 and to the output, a gate connected to an input and a source connected to a ground voltage, say V SS . In a typical embodiment, transistors 12, 14 and 22 are enhancement type transistors and capacitor 18 is made from a depletion type transistor. 
     In operation, switching transistor 22 couples the first plate of capacitor 18 to ground voltage V SS  in response to a positive transition in the input signal, whereby capacitor 18 is charged by transistor 12 to V DD  minus the gate-to-source voltage of transistor 12, V GS  12, and remains charged. When capacitor 18 is charged, transistor 14 is conductive. As a result, transistor 22 must sink all the current produced by transistor 14 in order to produce a valid logic low at node 16. Transistors 14 and 22 must, therefore, be properly ratioed with one another and transistor 22 must be significantly larger. When transistor 22 becomes nonconductive, transistor 14 causes the output voltage at node 16 to rise to nearly supply voltage V DD . Simultaneously, the voltage across capacitor 18 does not substantially change so that the gate voltage of transistor 14 at node 20 is substantially equal to the sum of the output voltage at node 16 and the voltage across capacitor 18. However, some change in voltage across capacitor 18 results from charge redistribution associated with parasitic capacitance. For this reason, a boosted output drive voltage can only approach twice the value of the supply voltage V DD . Unfortunately, since transistor 14 remains conductive for an output logic low, a current exists in driver transistor 14 and some voltage is thus always present at the output. Another disadvantage associated with the use of high capacitance loads on circuit 10 is that the output voltage has a slow rise time. 
     Shown in FIG. 2 is an MOS embodiment of a known mirrored bootstrap circuit 24 which provides a drive voltage and has some advantages over the circuit of FIG. 1. A transistor 26 has the drain and gate thereof connected together to a supply voltage V DD . A capacitor 28 which is fabricated in a conventional manner from a transistor structure has a drain and a source of the transistor structure connected together to form a first electrode or plate. A second electrode or plate of capacitor 28 is a gate of the transistor structure and is connected to the source of transistor 26 at node 30. A transistor 32 has the drain thereof connected to supply voltage V DD , the gate thereof connected to both the source of transistor 26 and the second plate of capacitor 28 at node 30, and the source thereof connected to the first plate of capacitor 28. A transistor 34 has the drain thereof connected to both the source of transistor 32 and the first plate of capacitor 28, the source thereof connected to a ground voltage V SS , and the gate thereof connected to an input terminal. A transistor 36 has a drain connected to supply voltage V DD , and has a gate connected to the source of transistor 26, to the gate of transistor 32 and to the second plate of capacitor 28 at node 30. A source of transistor 36 is connected to an output at node 38. A transistor 40 has the drain thereof connected to both the source of transistor 36 and the output at node 38, the source thereof connected to ground voltage V SS , and a gate connected to both the input voltage and gate of transistor 34. In a typical embodiment, transistors 26, 32, 34, 36 and 40 are enhancement type transistors and capacitor 28 is made from a depletion type transistor. 
     In operation, transistors 26, 32 and 34 and capacitor 28 form the same simple bootstrap portion shown in FIG. 1. As used, the simple bootstrap circuit functions as a pusher circuit for providing a driver voltage which is coupled to the gate of transistor 36 which serves as an enhancement type load device. The slow rise time at the output of circuit 10 of FIG. 1 due to capacitive loading has been removed from circuit 24. Further, the drive voltage present at node 30 is independent of the output voltage. However, circuit 24 also has the other disadvantages which circuit 10 has. A current exists in the circuit because transistors 32 and 36 are conducting while the output is a logic low. Only when an output load is purely capacitive and charged to a logic high will transistor 36 cease conduction. 
     Shown in FIG. 3 is an NMOS embodiment of driver circuit 42 which provides a driver voltage while substantially reducing the amount of current used in prior art circuits. In a preferred embodiment, an active load transistor 44 has a drain connected to a supply voltage V DD  and a source connected to the output at a node 46. A switching transistor 48 has a drain connected to both the output at node 46 and the source of transistor 44, and a source connected to a supply voltage V SS . In the preferred embodiment, a depletion type transistor 50 has a drain connected to supply voltage V DD  and also has both a source and a gate or control electrode connected to the output at node 46. Although transistor 50 serves to sustain the output voltage from falling as a result of leakage current, transistor 50 is not essential to the operation of driver circuit 42. A switching transistor 52 has a drain connected to the sources of transistors 44 and 50, to the drain of transistor 48 and to the output at node 46. A source of transistor 52 is connected to supply voltage V SS . A first capacitor 54, which is fabricated in a conventional manner from a depletion type transistor structure, has the gate thereof utilized as a first electrode or plate which is coupled to the gate of load transistor 44. A source and drain of the transistor structure of capacitor 54 are connected together to form a second electrode or plate. A first precharge transistor 56 has a drain connected to supply voltage V DD  and a source connected to both the first plate of capacitor 54 and the gate of transistor 44. A second capacitor 58 which is also fabricated in a conventional manner from a depletion type transistor has a gate or control electrode thereof utilized as a first electrode or plate which is coupled to the gate of transistor 56. A source and drain of the transistor structure of capacitor 58 are connected together to form a second electrode or plate which is coupled to a gate of switching transistor 52. A second precharge transistor 60 has the drain and gate thereof connected to supply voltage V DD , and the source thereof connected to both a gate of transistor 56 and the first plate of capacitor 58. A clamping transistor 62 has the source thereof connected to supply voltage V DD . A drain and gate of transistor 62 are connected together and are also connected to the gate of transistor 56, to the source of transistor 60 and to the first plate of capacitor 58. A logic gate 64 has a first input connected to both the second plate of capacitor 58 and the gate of transistor 52, a second input connected to both an input signal and the gate of transistor 48, and an output connected to the second plate of capacitor 54. In the preferred embodiment, logic gate 64 is a controller which is implemented physically as an active high NOR gate and the logic performed is equivalent to an active low AND gate. An inverter 66 has an input coupled to the input signal, to the gate of transistor 48 and to the second input of logic gate 64. An inverter 68 has an input connected to an output of inverter 66, and an output connected to the second plate of capacitor 58, to the gate of transistor 52 and to the first input of logic gate 64. A disabling transistor 70 has a drain connected to the first plate of capacitor 54, to the source of transistor 56 and to the gate of transistor 44. A source of transistor 70 is connected to supply voltage V SS  and the gate thereof is connected to the input, to the second input of logic gate 64, to the input of inverter 66 and to the gate of transistor 48. 
     In operation, assume that the input voltage is initially at a high logic level of V DD , as shown in FIG. 4, before transitioning to a low level of V SS . Since transistor 60 has precharged capacitor 58 to substantially V DD , the gate voltage of transistor 56 is at a voltage of V DD  plus the gate-to-source voltage of transistor 62, V GS  62. Since the inputs of logic gate 64 are both at a high logic level, the output is at a low logic level. Transistor 70 has been made conductive by the input signal so that the first or top plate of capacitor 54 is near V SS  potential and thus capacitor 54 is discharged to V SS  as shown in FIG. 4. As a result, transistor 44 is nonconductive and transistor 48 is made conductive by the input signal. Therefore, the output is at a low logic level and no current exists in load transistor 44. 
     When the input voltage changes to a low level, the second input of logic gate 64 is at a low level and transistor 70 is made nonconductive. Thus, the first or top plate of capacitor 54 charges toward V DD  through transistor 56. As a result, the output voltage at node 46 increases slightly as shown in FIG. 4 since transistor 44 is made partially conductive. After an initial delay through inverters 66 and 68, the first input of logic gate 64 becomes low and the output of logic gate 64 rises from V SS  to V DD  potential. 
     However, before the output of logic gate 64 changes, the gate voltage of transistor 56 has dropped below V DD  since the second plate of capacitor 58 was pulled to a low level. Because both the drain voltage and source voltage of transistor 56 exceed the gate voltage thereof, transistor 56 is made nonconductive and therefore cannot discharge capacitor 54. When the voltage on the second or bottom plate of capacitor 58 drops to V SS  potential, the precharge voltage or voltage on the first or top plate of capacitor 58 drops to a potential of V DD  minus the gate-to-source voltage of transistor 60, V GS  60. Capacitor 58 is then recharged by transistor 60. After the second plate of capacitor 54 is raised to a voltage potential near V DD , the voltage on the first plate of capacitor 54 is boosted to substantially 2 V DD . Capacitor 58 is used to increase the charge on capacitor 54 and is relatively small in value in comparison with capacitor 54. 
     When the input voltage changes back to a high logic level, transistors 48 and 70 are made conductive and the output at node 46 falls back to nearly V SS  potential. Also, the first or top plate of capacitor 54 is coupled to V SS  potential via transistor 70. The output of logic gate 64 has also fallen to a voltage which is substantially V SS  so that capacitor 54 is effectively discharged to quickly turn off transistor 44 at the output. After an initial delay determined by the propagation time through inverters 66 and 68, a high voltage level appears on the second or bottom plate of capacitor 58. Since capacitor 58 is partially discharged by transistor 62, the voltage on the first or top plate of capacitor 58 shown in FIG. 4 rises back to a potential equal to the sum of V DD  plus the gate-to-source voltage of transistor 62, V GS  62. Thus, transistor 62 functions as a clamping transistor to limit the range of voltage on the gate of transistor 56. Since capacitor 58 is charged to approximately V DD , the gate voltage of transistor 56 should be limited to approximately one gate-to-source voltage above V DD . This is because the gate voltage of transistor 56 should be quickly lowered below V DD  when the second plate of capacitor 58 is lowered and before the second plate of capacitor 54 is raised so that capacitor 54 is not discharged by transistor 56. Also, if for some reason the drive voltage on the gate of transistor 44 is inadequate, load transistor 50 will pull the output to V DD  potential provided transistors 48 and 52 are not conducting. 
     A gate drive voltage approximating twice the supply voltage V DD  has been provided to the enhancement load transistor 44. It will be appreciated that with the circuit of FIG. 3, load transistor 44 completely stops conducting when the output is intended to be at a low level. Thus no significant average current exists in the output at node 46. Further, the physical size of load transistor 44 is dependent upon the amount of gate voltage applied thereto by a square law proportionality. As a result of the large boosted driver voltage supplied, the output load transistor may be made small. Thus speed is improved and power is conserved. 
     While the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.