Carrier current digital data transceiver
BACKGROUND OF THE INVENTION 
     Microprocessors are finding increasing applications as intelligent control devices in the home as well as in industry. When a plurality of such microprocessors are interconnected by means of a common data bus, various protocols are used for orderly information transfer, such as described within U.S. patent application Ser. No. 561,483 filed 12-14-83 of E. K. Howell et al, which application is incorporated herein for purposes of reference. 
     When the common data bus includes a broadband communication bus, such as a power line communication bus which contains a modulated high frequency carrier signal along with the power frequency, transceivers are used which must be capable of converting the modulated carrier to baseband data for utilization by the microprocessor as well as converting the baseband data from the microprocessor to modulated carrier for transmission on the power line communication bus. State of the art transceiver devices require four terminals for interconnection with a microprocessor to provide input data, output data and control of the transmitter and receiver sections of the transceiver, and hence are not suitable for direct connection to a two-conductor baseband data bus. Such transceiver devices also exhibit a low impedance to the broadband terminals in both receive and transmit modes of operation, hence causing attenuation of the carrier signals when a plurality of transceivers are connected to a two-conductor broadband data bus. 
     A carrier current digital data transceiver requiring only two terminals for interconnection with a microprocessor or a baseband data bus is described within the aforementioned Howell et al application. The Howell et al transceiver is designed using discrete components which, although achieving excellent results in industrial applications, do not readily lend to miniaturization, such as when required to be used with home appliances connected to the power bus by wall outlets. 
     The carrier current digital data transceiver of the instant invention provides transparent interface function between broadband data and baseband data buses along with sufficient logic and impedance control to overcome all the aforementioned problems involved with several microprocessors along a common data bus. The selection of circuit elements and functions allows the transceiver to be fabricated within an integrated circuit in a compact and efficient configuration. 
     SUMMARY OF THE INVENTION 
     A carrier current digital data transceiver is designed for implementation within an analog integrated circuit for communication of data at 1000 bits per second via ASK 100% modulation, i.e., on-off keying, of a carrier frequency in the 100 to 200 kilohertz range. An open collector driver coupled with a NOR gate at the baseband input/output port allows &#34;listen-while-talk&#34; function. A dynamic limiter consisting of a variable transconductance amplifier, low pass filter and dual polarity peak comparator function to remove noise from the carrier signal prior to demodulation of the carrier. A tri-state power amplifier provides a low impedance to the broadband terminals in the transmit mode and a high impedance in the receive mode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagrammatic representation of the transceiver c1rcuit according to the invention; 
     FIG. 2 is a circuit diagram of the external components external to the integrated circuit utilized within the transceiver circuit of FIG. 1; 
     FIG. 3 is a circuit diagram of the dynamic limiter within the transceiver circuit of FIG. 1; 
     FIG. 4 is a circuit diagram of the gated level detector within the transceiver circuit of FIG. 1; 
     FIG. 5 is a circuit diagram of the time domain band pass filter within the transceiver circuit of FIG. 1; 
     FIG. 6 is a circuit diagram of the level detector, fast integrator, dual slope integrator, comparator, hysteresis, I/O baseband driver and T/R control logic within the transceiver circuit of FIG. 1; 
     FIG. 7 is a circuit diagram of the gated power amplifier within the transceiver circuit of FIG. 1; and 
     FIGS. 8-10 are circuit diagram of the integrated circuit utilized within the transceiver circuit of FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     TRANSCEIVER FUNCTION 
     The block diagram of FIG. 1 shows the main functions of the transceiver 10. The baseband I/O port 11 is a single terminal, referenced to the negative DC power supply bus, and is commonly connected through a resistor to a positive supply voltage of 5 V, for example. The baseband port voltage is normally high, corresponding to the absence of carrier at the broadband port, and may be pulled low by the internal open-collector driver 28 in response to presence of a carrier at the broadband I/O port 12, indicating data is received, or it may be pulled low externally, by any one of several digital devices, such as microprocessors suitably connected with similar open-collector drivers, thereby causing a carrier signal to be produced at the broadband port 12 for transmission. 
     The transmit/receive (T/R) control is obtained by a NOR gate 27 which produces high output level only when the baseband port 11 is pulled low externally. The NOR gate output disables the receiving path via inverter 26, line 35 and gated level detector 21 and enables a tristate power amplifier 25 which drives the broadband I/O port 12 with a carrier signal. Although the enable-disable function, line 35, is shown applied to level detector 21, the function can be applied to any of the functional elements 22, 23, 24, 32, 31 or 30 with proper circuit modification. When the baseband port 11 is high, the transceiver 10 is always in the receiving mode and is capable, therefore, of sensing another carrier signal on the broadband bus during that time. This logic technique provides the required transparency characteristic as defined within the aforementioned Howell et al application and the ability to sense a contending signal. 
     The broadband I/O port 12 consists of a pair of terminals, only one of which is shown, capacitively coupled to a high-frequency isolation transformer 13 having an inductive impedance of about 2000 ohms, open circuit. Clamping diodes within voltage surge suppressor 14 on the secondary of transformer 13 limit transient voltages to ±/5 volts. In the receive mode, the output impedance of power amplifier 25 is about 10,000 ohms. A wide-band filter 15 presents a 2000 ohm load to the isolation transformer 13 and couples carrier signals to the input amplifier 17 within dynamic limiter 16. 
     The input amplifier 17 comprises a variable transconductance amplifier which converts the carrier signal voltage to a signal current driving a parallel resonant L/C narrow-band filter 20 through a resistor R A . The sum of filter voltage plus voltage across R A  is sensed by a dual-polarity peak voltage comparator 19 which produces a feedback signal to control the transconductance of the amplifier 17, thereby limiting the L/C filter voltage to a fixed amplitude for all input signal voltages above the minimum. 
     A level detector 21, controlled by the T/R logic as earlier described, passes positive peaks of the filter voltage above 50% of the limited value. These peaks are converted to a square wave at 1/2 carrier frequency by a frequency divider flip-flop 22. The square wave is coupled through a highpass filter 23 to a time domain bandpass filter 24 which passes the square wave to its output if frequency is within the pass band and has no output otherwise. The output square wave of this filter is, in essence, rectified and filtered within a detector and fast integrator 32 which recovers the &#34;modulation envelope&#34; (rectangular wave) of the carrier. 
     In order to minimize the effects of high-amplitude impulse noise, the rectangular wave drives a dual-slope linear integrator 31 to provide a state recognition time (SRT) of about 330 microseconds. The integrated wave is applied to a comparator 30 which reproduces the rectangular wave, delayed by the SRT, without narrow &#34;glitches&#34;. Hysteresis 29 is connected to the comparator reference input via line 39 as a second means of eliminating narrow pulses. 
     Finally, the delayed rectangular wave of baseband data is applied to the inverting open-collector driver 28 of the baseband I/O port 11 and to the T/R NOR gate 27. 
     If the baseband port 11 and the input of driver 28 are both low, indicating that an external device has pulled the baseband port low, the NOR gate 27 disables the gated level detector 21 which establishes a &#34;nocarrier&#34; condition in the filter 23, detector and integrator 32, and comparator 30, hence maintaining the baseband driver input terminal low. The NOR gate 27 also enables the two-stage power amplifier 25 which applies the sinusoidal L/C filter voltage to the isolation transformer 13 with a voltage gain of about 50. The L/C filter 20 is driven to a fixed amplitude by feedback through the dynamic limiter 16, thus establishing the amplitude, frequency and waveshape of the transmitted carrier signal. A current limiting resistor R B  protects the power amplifier from shortcircuit and high voltage transients. Output impedance of the power amplifier in the transmit mode is less than 10 ohms, including R B . When the power amplifier is disabled, its output impedance increases to 10,000 ohms. This provides minimal attenuation of carrier signal and thereby allows a large number of such transceivers to be connected to a common broadband bus. 
     THE TRANSCEIVER 
     The transceiver broadband I/O port terminals T 1 , T 2  of FIG. 2 are connected across a pair of line conductors, or the line and neutral or ground and neutral conductors of a power line which carries modulated carrier communication signals. The baseband I/O port terminals T 3 , T 4  are connected to an I/O port on a microprocessor thereby allowing transparent communication between the microprocessor and any other microprocessor connected to a like transceiver operating on the same power line. The baseband I/O port terminals T 3 , T 4  can also be connected to a baseband data bus containing a plurality of microprocessors whereby any one of the microprocessors can gain control of the bus and transmit to all the other microprocessors on that baseband data bus and through the transceiver onto the power line, serving as a broadband data bus, to all of a plurality of remote microprocessors similarly connected to the baseband I/O port terminals of like transceivers. 
     FIG. 2 shows the external components and power supply circuitry used within the transceiver circuit 10 of FIG. 1 relative to the integrated circuit implementation 40 shown in FIG. 8 of all the components contained within a single chip and which will be described below in greater detail. The broadband I/O port 12 consists of terminals T 1 , T 2  which couple signals with either the line to neutral, neutral to ground, or line to line connections of a power line communication system (not shown) through a small high voltage capacitor C 1  to transformer 13 which is a high frequency isolation transformer which presents a magnetizing impedance of 2000 ohms at carrier frequency to I/O port 12. While a single capacitor C 1  is shown, certain applications may require the use of two capacitors in series. A DC blocking capacitor C 2  couples the transformer through current limiting resistors R 1 , R 2  to output pin B of the IC. Diodes D 1 , D 2  protect the circuit from high voltage transients by limiting the transformer secondary voltage to +/-1/2 Vcc. The positive supply voltage Vcc comprises 9 volts DC and is applied to the IC pins D, E. The negative is applied to IC pins A, U. The dual terminals minimize cross-talk between the output stage and the other circuits in the IC. The paired IC terminals are connected to a single pin in the IC package. Resistors R 5  -R 8  are arranged in a resistive divider string to provide a reference voltage V R , applied to pin G, bypassed by capacitor C 3 , at 1/2 Vcc. The divider also supplies a bias voltage 20 millivolts above V R  applied to pin L and a second bias voltage 600 millivolts above V R  applied to pin O. 
     DYNAMIC LIMITER 
     The input to the dynamic limiter 16, shown in FIG. 1, is the carrier signal output of the wideband filter 15, comprised of capacitors C 4 , C 5 , C 6  and resistors R 9 , R 10  and R 11 , referenced to V R  through resistor R 10  as shown in FIG. 3. Although wideband filter 15 is shown as an R/C filter, an L/C filter is advantageous in certain applications. Signal amplitude ranges from 2 millivolts to 2 volts. Since noise pulses may exceed +/-Vcc, the voltage of amplifier input IC pin H is limited by transistors Q 1  and Q 101  in order to avoid overdriving the variable transconductance amplifier 17. 
     The dynamic limiter 16 comprising variable transconductance differential amplifier 17 provides a high output impedance current drive to parallel resonant L/C filter circuit 20. The transconductance amplifier 17 comprises transistors Q 2  -Q 7  and Q 102  and Q 103  within the dynamic limiter circuit 16 shown in FIG. 3. Transistors Q 4  and Q 5  are connected as a differential amplifier with the input signal and DC reference voltage V R  applied to IC pin H, the base of Q 4 , and with offset-correcting DC feedback from the output IC pin J applied through lowpass filter R 12 , C 7  to IC pin I and the base of Q 5 . Emitter current for this amplifier is supplied by resistors R 15  and R 16  from Vcc to IC pin F and current mirror Q 2  and Q 3 . The differential current output IC pin J is obtained from Q 102  and Q 103  through current mirror Q 6  and Q 7 . Amplifier output current drives the tuned circuit L 1 , C 8 , through a resistor R.sub. 13 in order to develop a voltage signal proportional to current, which is added to the voltage developed across the tuned circuit. This composite signal is applied to the dual-polarity peak detector 19 of FIG. 1 at IC pin J pursuant to developing a feedback signal to control the current gain of the amplifier 17. 
     Various operating currents within the IC are established by current I B  through resistor R 14  to pin S and transistor Q 63  shown in FIG. 8, wherein emitter follower transistor Q 64  supplies the base voltage V B  required to establish this current in Q 63  and also supplies V B  to the bases of all the other transistors within the IC to establish the same current magnitude I B . Capacitor C 16  in FIG. 2 provides a bypass of high frequencies at IC pin S and suppresses parasite oscillations. 
     Transistors Q 9  and Q 12  with internal resistors R 1  and R 4  form a differential comparator with emitter degeneration. Emitter current for this comparator is derived from bias voltage V B  applied to the base of Q 11  and reduced to 0.7 I B  by emitter resistor R 3 . Collector currents of Q 9  and Q 12  are applied to a pair of Wilson current mirrors, Q 104 , Q 105 , Q 106  and Q 107 , having a common output equal to two times the higher of the two collector currents from the comparator. When the collector currents are equal (0.35 I B ), the mirror output current is 0.7 I B . This output current is applied to the collector of transistor Q 1O  which is driven by bias voltage V B  to sink I B . Hence, at balance, Q 10  is saturated, base current is limited by R 2 , and no base drive is applied to Q 8 . When the comparator is unbalanced by approximately 50 millivolts by a signal of either polarity at the base of Q 9 , one of the two collector currents exceeds 0.5 I B  resulting in mirror output current in excess of I B  which pulls Q 10  out of saturation and drives the base of feedback transistor Q 8 . This action causes Q 8  to bypass some of the amplifier emitter current supplied at IC pin F to current mirror Q 2  and Q 3 . Resistors R 14 , R 15  and R 16  and capacitors C 9  and C 10  control the frequency response of this gain control feedback path in order to obtain the desired transient response to step changes in carrier signal strength and noise impulses. 
     LEVEL DETECTOR 
     The limiter output signal developed across the L/C resonant circuit, consisting of variable inductance L 1  and capacitor C 8 , is applied to IC pin K of the gated level detector 21 as shown in FIG. 4. Transistors Q 13  and Q 15  form a differential comparator of this signal with respect to a DC level on IC pin L 20 millivolts above the reference voltage V R . When positive signal voltage peaks exceed this threshold level, the output is driven by current mirror Q 108  producing a current in excess of I B , the current sinking capability of Q 17 . Emitter current of 2 I B  for the comparator is produced by bias voltage V B  applied to the bases of Q 14  and Q 16 , as well as sink Q 17 , through resistor R 5 . In the transmit mode, the transmit/rece1ve control logic drives the base of Q 18  positive, causing Q 18  collector current to pull down the base voltages on Q 14 , Q 16 , and Q 17 , thereby disabling the level detector with no output voltage. Transistor Q 18  thus senses the function of inverter 26 of FIG. 1. 
     TIME DOMAIN BANDPASS FILTER 
     Additional frequency selectivity is provided by the time domain bandpass filter 24, shown in FIG. 5, which is an &#34;ideal&#34; filter with flat pass-band and infinite attenuation. This filter measures the period of alternate cycles of signal frequency and produces a fixed output signal only when the period fits within a prescribed time window. Since each period measurement is independent of prior events, the response is fast and not related to width of the pass-band. 
     Signal frequency is halved to produce a fixed amplitude square wave with a half-period equal to signal period as follows. The output of the gated level detector 21 of FIG. 4 drives, through emitter follower Q 21 , a conventional master-slave flip-flop frequency divider comprised of transistors Q 19 , Q 20 , Q 22 , Q 23  and resistors R 6-12 . The square wave output of this frequency divider is obtained at the collector of Q 23 . 
     Since this output can be left in either the high or the low state when the input signal ceases at the end of a carrier burst, and since the succeeding filter circuit requires a low input for zero signal, the frequency divider output must be coupled to the time domain filter 24 through a high-pass filter 23 as shown in FIG. 1. Transistors Q 24  and Q 25 , with resistors R 13  and R 14  and capacitor C 11  connected to IC pin M provide this function within the time doma1n bandpass filter circuit 24 of FIG. 5. When flip-flop output transistor Q 23  is turned on, Q 24  discharges capacitor C 11  and Q 25  is off. When Q 23  is turned off, the output at its collector is high and is applied to the time domain filter through resistor R 14 , and charges capacitor C 11  through resistor R 13 . If R 23  stays off longer than about 12 microseconds, Q 25  is turned on and the time domain filter input is pulled low. 
     The time window between a time t 1  and a time t 2  for filter 24 is produced by adjusting R 17  to charge C 12  to reach 4.5 volts (V R ) at IC pin N in time t 1  and to reach 5.1 volts (V R  +0.6 V) in time t 2  after the input (collector of Q 25 ) goes low. The lower cutoff frequency is defined by t 2  and the upper cutoff frequency by t 1 . The timing capacitor C 12  is discharged by Q 28  when input is high, or is discharged after t 2  by Q 29  and held discharged until Q 28  turns on. At time t 1 , transistors Q 35 , Q 37 , Q 112 , Q 113  and Q 38 , arranged as a comparator, enable the setting of the output flip-flop Q 39  and Q 40 , if the input goes high between t 1  and t 2  by comparing the voltage on C 12  with the reference voltage V R . At time t 2 , C 12  voltage reaches the higher potential of IC pin O, transistors Q 32 , Q 34 , Q 110 , and Q 111 , also arranged as a comparator, set flip-flop Q 30  and Q 31 , thereby turning on Q 29 , discharging capacitor C 12 , and removing the output enable produced by the comparator consisting of transistors Q 35  and Q 37 . When input goes high, C 12  is discharged, flip-flop Q 30  /Q 31  is reset by Q 26 , and output flip-flop Q 39  /Q 40  is set by Q 27  and Q 41  if enabled by Q 38 , that is, if between t 1  and T 2 . When input goes low, C 12  is allowed to charge, and the output flip-flop is reset. Emitter currents for all the comparators and supply currents for the two flip-flops are provided by Q 33  and Q 36  driven at bias voltage V B  to produce current I B . The output flip-flop Q 39  /Q 40  drives output transistor Q 42  to provide inversion and current asymmetry for the fast-integrating level detection function. 
     DETECTOR, INTEGRATOR, COMPARATOR, BASEBAND I/O DRIVER, AND TRANSMIT/RECEIVE CONTROL LOGIC 
     The circuits for functions 27-32 of the transceiver 10 depicted in FIG. 1 are shown in FIG. 6. Adding a bypass capacitor C 13  to IC pin P, as shown in FIG. 6, converts transistor Q 42  in the time domain bandpass filter 24 of FIG. 5 and transistor Q 79  of FIG. 6 to a detector by integrating the asymmetric output. This integration must be fairly fast in order to minimize stretching of the carrier burst time interval. Subsequent symmetrical integration is provided by capacitor C 14  connected to IC pin Q which is supplied with a constant sourcing current of I B  by current mirror Q 122  and Q 123  from Q 78 , as established by V B . The detector transistor Q 79  controls a sinking current of 2 I B  supplied by Q 76  and Q 77  in parallel. Thus, absence of signal charges capacitor C 14  at a rate set by I B , and presence of signal discharges C 14  at the same rate. The voltage on C 14  can swing from essentially zero (saturation of Q.sub. 76 and Q 77 ) to V CC  minus V BE  of Q 123  and V SAT  of Q 122 . Since this swing is not symmetrical about V R , the voltage on C 14  is compared, by Q 73  and Q 75 , with a reference that swings about 1/2 (V CC  -V BE ) established by Q 70 , R 39 , and R 40 . Hysteresis of +/-2 volts about this reference is provided by R 41  with current from Q 120  or from Q 121  through current mirror Q 72  and Q 71  which comprise the hysteresis circuit 29 of FIG. 1. 
     Differential output current of the comparator 30 of FIG. 1 is reproduced by Q 119  and Q 69  and applied to the baseband I/O driver Q 65  and to T/R logic transistor Q 68  through resistors R 36  and R 37  respectively, as shown in FIG. 6. When carrier signal is absent, capacitor C 14  charges, raising the voltage at IC pin Q above reference, providing current in Q 75 , Q 121 , Q 72 , Q 71  and Q 69 , thus turning off Q 68  and Q 65 . An external resistor R 20  connected to IC pin R can then pull the I/O port 11 to a positive voltage. This voltage at pin R applied to emitter follower Q 66  turns on T/R logic transistor Q 67 . In the presence of carrier signal, C 14  discharges, reducing the voltage at IC pin Q below the changed reference voltage, causing current to switch to Q 73 , Q 120  and Q 119  which turns on Q 65  and Q 68 . Driver transistor Q 65  within the I/O driver 28 of FIG. 1 pulls I/O port 11 and IC pin R low which turns off Q 66  and Q 67  which comprise the T/R control logic NOR GATE 27. 
     In the receiving mode, the T/R control line 36 is being pulled down either by Q 67  when the baseband I/O port 11 is high (no carrier) or by Q 68  when the baseband I/O port is pulled low (by carrier). If the baseband I/O port 11 is pulled low externally, and not internally, both Q 67  and Q 68  are off and the T/R control line 36 is released. 
     GATED POWER AMPLIFIER 
     When the gated power amplifier 25 of FIG. 1 is turned on, a power oscillator is formed in combination with feedback through the dynamic limiter 16 which establishes oscillator amplitude, and the L/C narrow band filter 20 which determines the oscillation frequency and sinusoidal waveform. 
     Operating current for the gated power amplifier 25, shown in detail in FIG. 7, is provided from V CC  by resistor R 18  to IC pin T whenever the T/R control line 41 is released. Capacitor C 15  provides a few microseconds delay to allow for some capacitive loading on the baseband I/O port which causes a time delay between turn-off of T/R logic transistor Q 68  and turn-on of Q 67  in the transition from a received low state at IC pin R as best seen in FIG. 6. 
     When the baseband I/O port 11 is pulled low externally, the T/R control line 41 is released, the potential at IC pin T rises until Q 58  emitter current is sufficient to cause Q 59  to sink the current supplied by R 18 . The potential at the emitter of Q 58  is then 2.0 V BE  of Q 59 , as established by R 29  and R 30 . This voltage creates a current through R 28  to drive Q 18  within the gated level detector 25 of FIG. 4 to inhibit the gated level detector, thereby blocking the receiving path. 
     The base-emitter voltage of Q 59  drives four other current sources--Q 52 , Q 55 , Q 57  and Q 61 . Q 61  supplies operating current to the first-stage differential amplifier Q 60 , Q 62  and Q 118  which has a voltage gain of 5, established by feedback resistors R 31  and R 32 , for signal frequency appearing on the parallel resonant circuit L 1 , C 8  at IC pin K. 
     The second stage amplifier, Q 56 , Q 53 , Q 117  and Q 52  operates at twice the emitter current of the first stage, supplied by Q 55  and Q 57  in parallel. The current differential of Q 117  and Q 52  drives the darlington &#34;totem pole&#34; output stage consisting of Q 49  and Q 50  driving the large 200 mA power transistors Q 43  and Q 44 . Capacitor C 17  connected between pins B and V stabilizes the amplifier. Feedback resistors R 3  and R 4  set the noload voltage gain of this stage at 10, and short-circuit gain at 20. Resistors R 1  and R 2  provide current limiting during high amplitude transient voltages and the mid-point connection for feedback reduces the amplifier output impedance as partial compensation for these resistors. 
     In the receiving mode, with the T/R control logic pulling IC pin T low, the output impedance of the gated power amplifier 25 is established by R 3  and R 4  at 11 K ohms. High voltage transients coming in to the isolation transformer 13 are clamped, at lower current levels, by zener diodes Q 47  and Q 48  driving Q 45  and Q 46  and the power output transistors Q 43 , Q 44 . Diodes D 1  and D 2  provide transient clamping at higher current levels, as determined by R 1  and R 2  and the magnitudes of V CC , V EB  and V BE . Diode Q 54  clamps the base of Q 50  low in the receiving mode in order to prevent high frequency current in compensating capacitor C 17  from turning on the lower power output stage. 
     TRANSCEIVER IC 
     The transceiver circuit elements contained within the integrated circuit 40 are shown in FIG. 8 with IC pins A-V arranged for connection with the other components within the carrier current digital data transceiver circuit 10 depicted schematically in FIG. 2. All of the circuit elements shown in FIG. 8 and their operation have been described in detail earlier with reference to FIGS. 3-7, with like reference numerals. 
     Although the carrier current digital data transceiver of the invention is described for connecting between a power line communication system and a microprocessor data bus, this is by way of example only since the transceiver can communicate over any medium providing suitable carrier propagation, and with any source of baseband data, such as micro and mini computers. The transceiver integrated circuit is embodied within a 20 pin IC configuration. It is to be clearly understood that other IC configurations having a lesser number of terminal pins can also be employed depending upon user requirements and economics. 
     One such transceiver integrated circuit having a 14 pin IC configuration is shown at 41 in FIGS. 9 and 10. This is accomplished in part by placing resistors R 11  -R 14  external to the 20 pin integrated circuit 40 of FIG. 2 within the 14 pin integrated circuit. In addition, DC feedback in the dynamic limiter 16 shown in FIGS. 1 and 3 has been eliminated and current limiting resistors are added to the zener diodes Q 47  and Q 48  as best seen in FIG. 10. The high pass filter 23 between the frequency divider 22 and the time domain bandpass fiter 24 shown in FIG. 1 has been revised, adding transistor Q 124  and deleting transistor Q 24  seen by comparing the circuits shown in FIGS. 8 and 10. This simplification in circuitry is accomplished by using the characteristics of the fast integrator function of capacitor C 13  within the detector and integrator circuits depicted in FIGS. 1 and 6 to reset the time domain filter output flip flop Q 39  and Q 40  shown in FIG. 5 when, in the absence of signal, transistor Q 42  remains conducting longer than about 12 microseconds. Capacitor C 13  is discharged to a voltage low enough to turn on transistors Q 124  and Q 25 . FIG. 9 also shows the use of an LC tuned circuit L 2  and C 6  for the wide band filter 15 of FIG. 1 as described earlier and shown as an RC filter C 4  -C 6  and R 9  -R 11  in FIG. 2. 
     Although the inventions have been described with reference to a specific embodiment thereof, numerous modifications thereof are possible without departing from the inventions and it is desirable to cover all modifications falling within the spirit and scope of these inventions.