H-bridge power amplifier and method for controlling the same
CROSS-REFERENCE 
     This application is a continuation-in-part of application Ser. No. 471,370 filed 3/01/83 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to control systems and methods for controlling an inductive load, such as a motor. More particularly, the invention relates to an improved power amplifier and control method for controlling the angular velocity and angular acceleration of a DC motor. The system and method disclosed maintain a low ripple current in the motor, simplify the motor control circuitry, conserve power used within the motor, and provide improved motor braking capability. 
     Switching Servo Amplifiers (SSA) are commonly used in the prior art to supply the drive current to an inductive load, such as a DC motor. Often the output stage used for the SSA is the &#34;H&#34; or &#34;transistor/diode&#34; bridge. An H-bridge comprises 4 power transistors interconnected to form a bridge, with the servo motor being positioned in the center of the bridge, as depicted in FIG. 1. Each transistor Q1-Q4 has a &#34;free wheeling&#34; diode D1-D4 connected, in a reverse current direction, from the emitter to collector. The base voltages of the transistors are controlled by the SSA to turn the transistors Q1-Q4 on and off in the appropriate manner so as to cause a drive current, I M , to flow through the motor M in the desired direction. A current sense resistor R1 is positioned so that the current I M  flows therethrough. A differential amplifier A1 senses the voltage across R1 and converts this voltage to an output signal that indicates the polarity and magnitude of the current I M . The most common method of switching the power transistors of the H-bridge is through the Pulse Width Modulation (PWM) method. In this method, a fixed frequency is typically used and the duty cycle of the waveform is varied to supply the desired drive current I M  to the motor. 
     Using the prior art scheme shown in FIG. 1, two diagonal power transistors in the H-bridge, such as Q1 and Q4, are simultaneously switched on, thereby causing current I M  to flow through the motor in the direction shown by the arrow. After a period of time, determined by the duty cycle of the PWM waveform, transistors Q1 and Q4 are turned off, and transistors Q2 and Q3 of the H-bridge are turned on, switching the direction of the voltage applied to the motor. Transistors Q2 and Q3 remain on for a period of time, again determined by the duty cycle of the PWM waveform. After this period of time, the second pair of transistors Q2-Q3 is turned off, and the first pair Q1-Q4 is turned on. This &#34;on&#34; and &#34;off&#34; cycle of alternate pairs of transistors is continuously repeated as the servo system controls the acceleration of the motor. 
     Because a DC motor is an inductive load, the current flowing therethrough cannot be changed instantaneously when an alternate pair of transistors in the H-bridge is turned on. Thus, even though the voltage applied across the motor may approximate an instantaneous change (at the time the transistor pairs switch), the current flowing through the motor assumes a more triangular, or saw tooth waveform. Further, because the torque, and therefore the acceleration, of a DC motor is proportional to the average, or DC, current flowing through the motor (the direction of the acceleration being determined by the direction of the DC current), the servo system achieves the desired torque or acceleration by monitoring the motor current I M  and controlling the duty cycle of the PWM wafeform until the desired average DC current is obtained. Unfortunately, this switching action causes a large ripple current to be ever present in the motor, even though the average current may be the desired amount. That is, while the motor is in motion, drive current is continually being supplied by alternately switching the desired transistor pairs. Even when the motor is not accelerating or decelerating, motor current is beng supplied with the duty cycle of the PWM waveform being 50%, thereby causing the average motor current supplied to the motor to be zero. 
     Unfortunately, the constant frequency PWM type of controller commonly used in the prior art suffers from several disadvantages: (1) the alternate &#34;on&#34; and &#34;off&#34; cycle of alternate transistor pairs causes a large ripple current to be ever present in the motor, unless the switching frequency is increased; in which case more power is lost in the switching transistors; (2) the large ripple currents in the motor may cause acoustical noise by coupling to the mechanical support members of the servo motor; (3) the AC component of the ripple current dissipates power in the motor, causing the motor to be unduly heated up; and (4) the drive current I M  must be sensed at all times, which sensing consumes still additional power. Further, because the drive current will change directions in the sensing resistor whenever the motor current direction is changed, the differential amplifier must respond to this alternating current direction without introducing undesirable offsets. It is apparent, therefore, that a need exists in the art for an improved PWM amplifier and method for controlling the same wherein the above described disadvantages are not present. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide an improved power amplifier and method of controlling the same for controlling the current delivered to an inductive load wherein the aforecited disadvantages are either eliminated or minimized. 
     More specifically, it is an object of the present invention to provide such a power amplifier and control system for driving a motor wherein the ripple current flowing through the motor is minimized, thereby conserving power and reducing heat dissipation. 
     It is a further object of the present invention to provide such an improved power amplifier and control system that is efficient, reliable, and simple to operate, yet that can be readily realized from standard, inexpensive components and parts. 
     It is still a further object of the present invention to provide an improved H-bridge power amplifier configuration for use with a DC motor wherein the motor current flows through a sensing resistor in the same direction regardless of the direction of the motor current, and further wherein the motor current need only be sensed for a fraction of the time of the power amplifier cycle. 
     The above and other objects of the present invention are realized with an improved version of an H-transistor/diode bridge. Advantageously, the power sensing resistor is uniquely positioned within the bridge circuit, especially in relation to the free wheeling diodes, so that only the drive current that needs to be measured flows through it. Moreover, this drive current always flows through the sensing resistor in the same direction, thereby obviating the need for sophisticated circuitry that must sense a signal of either polarity. Further, the drive current is switched by the power transistors of the improved H-bridge circuit in a manner that significantly reduces the ripple current in the motor. This is achieved by keeping one of the two selected transistors of the H-bridge circuit on, while selectively switching the other on and off. This selective one-transistor switching is combined with a &#34;plug inhibit&#34; operating mode for braking the motor. During &#34;plug inhibit&#34;, the power transistors of the H-bridge are selectively switched so as to convert the motor into a generator, thereby allowing the motor to dissipate its own energy in performing the braking function without introducing additional power from the power source. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, features, and advantages of the present invention will be better understood from the following more particular description of the invention presented in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a schematic drawing of an H-power amplifier circuit of the prior art; 
     FIG. 2 is a simplified timing diagram of the motor current versus time for the prior art circuit of FIG. 1; 
     FIG. 3 is a schematic drawing of an improved H-power amplifier circuit built in accordance with the present invention; 
     FIG. 4 is a logic/block diagram of a controller circuit in accordance with the present invention that could be used to selectively control the circuit of FIG. 3; 
     FIGS. 5A, 5B, and 5C are simplified timing diagrams of the motor current or motor velocity versus time for the circuit of FIG. 3, showing various modes of operation that might exist in connection with the operation of the circuit of FIG. 3; 
     FIG. 6 is a simplified flow chart illustrating the operation of the circuit of FIG. 3; 
     FIG. 7 is a partial schematic diagram of an alternative embodiment of the H-power amplifier of the present invention, showing the preferred placement of additional components that are used to measure the motor velocity; 
     FIG. 8 is a logic/block diagram of the Plug Inhibit Timing Logic of FIG. 4; and 
     FIG. 9 is a timing diagram of the various control signals used during the operation of the circuits of FIG. 3 ad FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following is a description of a preferred embodiment or embodiments of the present invention. This description is given only to illustrate the principals, objectives, and advantages of the invention, and is not to be taken in a limiting sense. The true scope of the invention can be ascertained by referring to the appended claims. 
     In the description that follows, like numerals will be used to describe like parts throughout. This is true even with respect to a comparison of FIG. 1, the prior art, and FIG. 3, the present invention. 
     Referring first to FIG. 1, there is shown a schematic diagram of an H-bridge power amplifier in accordance with a typical embodiment of the prior art. As explained previously, the H-bridge comprises four power transistors interconnected to form a bridge. The motor M is positioned in the center of the bridge. The current flowing through the motor, I M , is controlled by selectively switching transistor pairs Q1 and Q4, or Q2 and Q3. Thus, in order for the motor current I M  to flow in the direction indicated by the arrow in FIG. 1, transistors Q1 and Q4 would both be turned on. If it is desired to reverse the direction of the motor current I M , then the transistor pair Q1 and Q4 would be turned off, and the transistor pair Q2 and Q3 would be turned on. 
     The motor current I M  flows through the sensing resistor R1 regardless of which transistor pair is turned on. A differential amplifier A1 is connected across R1 to sense the current flowing therethrough. The amplifier A1 thus generates a current sense signal that indicates both the polarity and magnitude of the current I M . 
     Referring next to FIG. 2, there is shown a simplified timing diagram of the motor current I M  versus time associated with the operation of the circuit of FIG. 1. Because the motor M is a large inductive load, the current cannot change instantaneously when the transistor pairs are selectively turned on or off. Hence, when Q1 and Q4 are turned on, thereby connecting +V and -V across the motor, the current begins to build up exponentially in the motor according to well known principles. However, for the purposes of this application, and in order to simplify the discussions and figures that follow, this exponential increase in the motor current is represented as a linear increase in FIG. 2. (As will be apparent to those skilled in the art, this simplification will not cause a significant distortion for purposes of the discussion that follows.) 
     The circuit of FIG. 1 operates with a variable duty cycle in conjunction with a fixed period in order to selectively control the motor M. Thus, the transistor pair Q1 and Q4 will be turned on for a first portion of a control cycle T. The transistors Q1 and Q4 will then be turned off, and the transistors Q2 and Q3 will be turned on for the remaning portion of the switching period T. Hence, in FIG. 2, during a first portion of the period T, identified as T 1 , Q1 and Q4 are on and Q2 and Q3 are off. During the remaining portion of the period T, identified as T 2 , Q1 and Q4 are off, and Q2 and Q3 are on. The sum of time periods T 1  and T 2  equal the fixed operating period T. 
     In order to better appreciate and understand the advantages and features of the present invention, it will be helpful to first understand the operation of the prior art circuit of FIG. 1. Thus, referring to FIG. 2, there is shown, as a dashed line, a curve I d  representing the desired average current that is to flow through the motor M. In order to realize this desired current, the duty cycle is varied as indicated in FIG. 2. That is, during a first period, Q1 and Q4 are left on for almost the entire period, thereby allowing the current I M  to build up towards the desired value I d . During a second period, the duty cycle is varied again in order to cause the average current to be approximately equal to the desired current at the end of the time period 2T. During the third and fourth cycles, the duty cycle is approximately 65%, Q1-Q4 on, which duty cycle maintains the average current at a value approximately equal to the desired current I d . (Note that a duty cycle greater than 50% is required because the negative (decaying) current slope is greater than the positive current slope.) At time 4T, the desired current steps to a negative value. Accordingly, the duty cycle is again varied in order to allow the current I M  to ramp down to the desired value as quickly as possible. The duty cycle is adjusted appropriately so at the end of the 7th period the duty cycle may be approximately 60%, Q2-Q3 on. 
     As thus described, it is seen that the desired average current I d  is realized by varying the duty cycle in order to force or maintain the actual current I M  in the needed direction. Unfortunately, this process produces a large ripple current that can cause undesirable effects as described previously. Further, the motor current I M  is continuously flowing through the sense resistor R1. 
     As those skilled in the art will recognize, the diode pairs D2 and D3, and D1 and D4, provide a path for the motor current I M  to flow until the direction of the current can be changed as desired. Thus, referring to both FIGS. 1 and 2, during the first switching period T, the current I M  flows in the direction indicated through a path provided by Q1, R1, and Q4 during the time T 1 . During the time T 2 , Q1 and Q4 are turned off and Q2 and Q3 are turned on. However, the motor current I M  cannot flow through Q2 and Q3 until the current I M  has decreased sufficiently to allow a change in direction. Thus, during the time T 2  the current path is from the negative supply through the diode D3, the motor M, the resistor R1, and the diode D2 back to the positive supply. When the actual current does go negative, such as between the times 5T and 6T, then the diodes D4 and D1 provide a similar path for the motor current when Q2 and Q3 are turned off. In all situations, however, the motor current I M  flows through the sense resistor R1, thereby dissipating power therein. 
     Referring next to FIG. 3, there is shown a schematic diagram of an improved H-bridge power amplifier according to the present invention. Four power transistors Q1-Q4 are used as in the prior art and perform the same function as in the prior art (thus, they are given the same numerals or designators as in FIG. 1). The motor M is likewise positioned in the center of the bridge as in the prior art. The free wheeling diodes D3 and D4 are likewise positioned as in FIG. 1. The current sense resistor R2, however, is connected between the collectors Q1 and Q2 and the positive supply. Free wheeling diodes D5 and D6 are then connected as shown between the motor terminals and the upper side of resistor R2. A differential amplifier 10 is connected so as to sense the voltage developed across the resistor R2. The output of the amplifier 10 is compared in a comparator circuit 11 to a current command signal. If the current command signal exceeds the sensed signal, then the output of the comparator 11 is a positive signal, indicating that the drive current to the motor has not been satisfied. As soon as the sense signal exceeds the current command signal, then the output of the comparator 11 goes negative, indicating that the drive current to the motor has been satisfied. 
     In an alternative embodiment, it would be possible to place the sense resistor R2 between the emitters of transistors Q3 and Q4 and the negative supply -V. If this alternative configuration were used, the cathodes of the free wheeling diodes replacing D3 and D4 would be connected to the negative supply -V rather than to the emitters of transisors Q3 and Q4. 
     The present invention turns off the drive or motor current I M  in a manner distinct from that of the prior art. For example, assuming that the motor current I M  is flowing in the direction shown as a result of having the transistor pair Q1 and Q4 turned on, Q1 is then turned off for a fixed period of time while Q4 is left on. Hence, by leaving Q4 on, the inductive motor current decays through the path from the motor, through Q4, through diode D3, and back to the motor. During this fixed off-time period while Q1 is off, the motor current I M  is not flowing through the sense resistor R2. 
     The advantages of using a fixed off-time period as above described are apparent from the timing diagrams of FIGS. 5A and 5B. In these Figures, which show a simplified timing diagram of the motor current I M  versus time, it is seen that the amount of ripple present in the motor current is much smaller than achieved in the prior art for approximately the same switching frequency. To illustrate, consider FIG. 5A. In this Figure a desired current I d  is shown as a dashed line. In order to achieve the desired current, transistors Q1 and Q4 are first turned on as in the prior art, allowing the motor current I M  to ramp up to the desired value. Unlike the prior art, however, once the desired value has been reached, transistor Q1 is turned off for a fixed time period T F . During this fixed off period, the motor current decays through the transistor Q4, which is left on, and through diode D3 back to the motor M. However, the rate of decay is much less than with the prior art circuit because the voltage applied across the motor during this time is zero rather than the 2V applied in the prior art. After the fixed off period, Q 1  is again turned on, thereby allowing the current I M  to ramp back up above the desired value I d , at which time Q1 is again turned off for the fixed off-time T F . This process repeats itself, thereby causing the average motor current I M  to approximate the desired current I d . Thus, the basic operating mode of the present invention is to select the appropriate pair of transistors (Q1 and Q4, or Q2 and Q3) for the desired direction as in the prior art. However, unlike the prior art the lower transistor (Q3 or Q4) of the selected pair is turned on and left on, and the upper transistor (Q1 or Q2) is turned on until the desired current is achieved, and then turned off for a fixed period of time. 
     The present invention further advantageously includes a feature for controllably braking the motor should it be desired to slow down the speed thereof. This feature, called &#34;plug inhibit,&#34; ensures that a dynamic brake current path is provided through the sense resistor R2, thereby allowing the brake current to be sensed and the desired control to be maintained. (Without the plug inhibit feature, upon receipt of a current command of a polarity to slow down the motor, the circuit would provide a dynamic brake path through a lower diode and lower transistor without being measured in resistor R2. The result would be a larger than desired current until the motor slows down or the command changes polarity.) This plug inhibit feature is described below in connection with the discussion of FIG. 5B. 
     Referring to FIG. 5B, the desired current I d , shown as a dashed line, steps from a first positive value to a lower negative value at time t 14 . Prior to time t 14 , Q4 is on and Q1 is selectively turned on and off as above described, resulting in an increasing motor velocity as shown in FIG. 5C. At time t 14 , the desired current steps to a negative value. According to the present invention, when a change in polarity of the drive current is commanded, all four of the transistors Q1, Q2, Q3, and Q4 are turned off for a prescribed period of time, T p , thereby protecting against an overlap condition (wherein Q1 and Q3, or Q2 and Q4 might be on at the same time) that could possibly damage the transistors. During this time, T p , the motor current, I M , decays toward zero through a path that includes diode D3, the motor M, and diode D6. Also note that during this time period, as during the fixed off-time T F , the motor current does not flow through the sensing resistor R2. 
     After the overlap protection time T p  has elapsed, at time t 15 , transistor Q3 turns on according to the previously described rules. When the motor current reaches zero, just before t 16 , the back emf of the motor causes current to increase slowly in the negative direction through transistor Q3, diode D4, and the motor M. At time t 16 , the off-time T F  expires and transistor Q2 also turns on, allowing &#34;plugging&#34; current to increase to the new value of I d . Transistor Q2 then turns off at t 17  for the fixed off-time period T F  ; and, because there is now a path for dynamic brake current to flow through transistor Q3 and diode D4 (note that motor velocity shown in FIG. 5C is still positive), current continues to increase beyond I d , without being measured by R2. At the end of the fixed off-time T f , at time t 18 , Q2 is turned on according to the regular patter. However, because the motor current is already greater than I d , the &#34;plug inhibit&#34; mode is enabled. That is, the comparator 11 will switch very quickly to the &#34;drive satisfied&#34; state whenever the motor current is greater than I d . The &#34;plug inhibit&#34; mode is enabled whenever the &#34;drive satisfied&#34; line (the output of the comparator 11) is set in a time less than some limit, such as ten microseconds, after one of the upper transistors, Q1 or Q2, is turned on. During, the plug inhibit mode, the lower transistor of the selected transistor pair is turned off in order to increase the rate of decay of current during the off-time period T F  so that the desired current is not exceeded. 
     Still referring to FIG. 5B, the plug inhibit mode begins at time t 19 , some ten microseconds (or other suitable period) after Q2 is turned on. At t 19 , Q2 turns off according to the usual rule: the upper transistor turns off as soon as current sensed through R2 exceeds the desired current I d . Moreover, at t 19  Q3 is also turned off by the enabling of the &#34;plug inhibit&#34; mode. With the lower transistor turned off, the upper transistor is selectively turned on and off according to its usual rule, thereby modulating the motor current until the desired current is obtained. 
     During the plug inhibit mode the source of voltage to provide motor current is the motor back emf rather than an external power supply. When all transistors are off, the current decay rate is greater than normal, and when only an upper transistor is on, the current buildup rate is lower than when the external voltage is applied. It may therefore be beneficial to reduce the off-time T F  during plug inhibit mode as shown in FIG. 5B between t 19  and t 20  in order to minimize the ripple current and keep the switching rate up near normal. 
     The decision to exit the plug inhibit mode is made by measuring the time from turn on of the upper transistor, at time t 20 , to turn off, at time t 21 . If this turn-on time exceeds some prescribed limit, such as 300 microseconds, the plug inhibit mode ends and the system reverts to normal (non-plug inhibit) operation. That is, an on-time of the upper transistor greater than 300 microseconds indicates that the remaining back emf is not adequate to provide the current desired, and the normal operating mode (lower transistor on, upper transistor selectively turned on and off) is then used to achieve the desired current. 
     A simplified flow chart that describes the process explained above in connection with FIGS. 5A and 5B is shown in FIG. 6. Operation of the circuit hinges on making three determinations. The first determination, shown in block 40, is to determine the polarity of the desired motor current. If positive, as shown in FIG. 3, then Q2 and Q3 will be disabled and may not be turned on until there has been a polarity reversal. Once the polarity has been determined, a second decision must be made as to whether or not the polarity has changed from what it was previously, as indicated in the decision block 42. If yes, then all of the transistors are disabled for the overlap protection time T P . After the overlap protection time T P , or after a decision has been made that no polarity change has occurred, a third decision is made, at decision block 44, as to whether the off timer is running. (The off timer is used to define the fixed off-time period T F  ; and, as will be explained more fully below in connection with FIG. 4, the off-timer starts running whenever a Drive Satisfied signal is received from the comparator 11 indicating that the measured motor current I M  flowing through resistor R2 exceeds the desired current I d .) 
     If the off-timer is running, i.e., if the time T F  has not yet expired, the upper transistor is turned off. If the off-timer is not running, i.e., if the time T F  has expired, the appropriate upper transistor is turned on (block 46). 
     Once the upper transistor has been turned on for at least a set time period, such as 5 microseconds (block 48), a decision is made at block 50 as to whether the measured motor current I M  is greater than the desired motor current I d . This minimum time period is used to mask out turn-on transients associated with Q1 or Q2. If yes, the off-timer starts running (block 52). In addition, if the on-time of the upper transistor was less than 10 microseconds (block 54), then the plug inhibit mode is enabled (block 56) and the lower transistors are turned off (block 58). If the on-time of the upper transistor is greater than 10 microseconds (block 54), then the flow chart returns to a polarity check (block 42). 
     Should it be determined that the motor current I M  is not greater than the desired current I d  (block 50), then a determination is made as to whether the on-time of the upper transistor has exceeded a longer time limit, such as 300  microseconds (block 60). If so, plug inhibit is disabled (block 62), the appropriate lower transistor is turned on (block 64), and a determination is again made as to whether I M  is greater than I d  (block 50). If, at block 60, it is determined that the on-time of the upper transistor has not exceeded 300 microseconds, then that indicates the back emf of the motor is adequate to provide the desired current, and the plug inhibit mode is continued. 
     Referring next to FIG. 4, there is shown a logic/block diagram of a controller circuit that could be used to control the operation of the circuit shown in FIG. 3 as described above in connection with FIGS. 5 and 6. The outputs of the amplifiers 31 are connected to the bases BQ1-BQ4 of the transistors Q1-Q4. These amplifiers 31 are driven by four 3-input NAND gates 27-30. The particular details associated with the amplifiers are not important to the present invention, and those skilled in the art will readily be able to design appropriate amplifiers for driving the transistors Q1-Q4. The microprocessor 20, or equivalent, provides an indication of the desired mode of operation. An ENABLE signal is used to enable all four NAND gates 27-30. In the absence of an ENABLE signal, all four transistors Q1-Q4 will be turned off. The microprocessor 20 also provides a POLARITY signal that determines the direction of the drive (or motor current) or the direction of braking. An inverter 21 has an open collector output, with a pull-up resistor 36, which allows the RC network 37-38 to be used in conjunction with the inverters 22-23, AND gate 24, and NOR gate 25 to insure that the transistors Q1-Q4 are turned on and off in the proper sequence without causing damage to any of them. That is, the RC network 37-38 is responsible for generating the overlap protection time T P  referred to earlier. Note that the POLARITY signal allows either NAND gates 27, 28 or NAND gates 29, 30 to be enabled, but never both pairs at the same time. Thus, the polarity signal controls which pair of transistors in the H-bridge amplifier circuit (FIG. 3) may be enabled. 
     The microprocessor 20, or equivalent control module, also provides a CURRENT COMMAND signal indicating the desired motor current I d . In the preferred embodiment, this signal is a binary signal which is supplied to a digital-to-analog converter (DAC) 32. The analog output of the DAC 32 is compared to the SENSE value (the output of the amplifier 10 in FIG. 3) by the comparator circuit 11. When the two inputs agree, the output of the comparator 11 will go low, presetting the flip flop 34. The D output of the flip flop 34 starts running the off-timer 33. While the off-timer 33 is timing out, the -D output of the flip flop 34 will go low, disabling NAND gates 27 and 29. This turns off the appropriate upper transistor Q1 or Q2. When the delay 33 times out for its fixed tme, T F , the flip-flop 34 is cleared and the -D output again enables NAND gates 27 and 29, which thus allows the appropriate upper transistor to be turned on. 
     The PLUG INHIBIT signal is used to cause controlled braking. The PLUG INHIBIT Timing Logic 39, provides the timing signals needed to make the decisions referred to in blocks 54 and 60 of FIG. 6. In practice, therefore, the Timing Logic 39 either enables or disables the PLUG INHIBIT signal depending upon the interval between the drive satisfied pulses generated by the comparator 11. When the PLUG INHIBIT signal is high, the motor is controlled as shown in FIG. 5A. When the signal is low, the NAND gates 28 and 30 are disabled, thereby turning off the lower transistors. The ENABLE and POLARITY signals then control the operation of NAND gates 27 and 29, which in turn control the turn on and turn off of Q1 and Q2 respectively. As explained, when only the upper transistor is on, the motor is being braked. When braking, the CURRENT COMMAND, signal DAC 32, comparator 11, flip-flop 34 and delay 33 all function as previously described. 
     A more detailed logic/block diagram of The Plug-Inhibit Timing Logic 39 (see FIG. 4) is shown in FIG. 8. FIG. 8 is best understood with reference to the timing diagram of FIG. 9, as well as to the controller circuit of FIG. 4. Hence, in the discussion that follows, reference should be made to all three figures. 
     The output signal from the comparator 11 is labeled -DRIVE in the figures. This signal goes low when the drive is satisfied (when the sensed or measured motor current exceeds the desired motor current), and it goes high when the drive is not satisfied (when the sensed motor current is less than the desired motor current). Two timers, identified as Timer 69 and Timer 71 in FIG. 8, are triggered by the rising edge 73 of the -DRIVE signal. Timer 69 generates a timing pulse 70 that occurs a prescribed time T A  after the rising edge 73 of the -DRIVE signal. Similarly, Timer 71 generates a timing pulse 72 that occurs a prescribed time T B  after the rising edge 73 of the -DRIVE signal. In the preferred embodiment, timer T A  is approximately 10 microseconds and time T B  is approximately 300 microseconds. The occurrence of the two timing pulses 70 and 72 is compared against the occurrence of a falling edge 75 of the -DRIVE signal at a T A  Test circuit 76 and a T B  Test circuit 78, respectively. If the -DRIVE signal has gone back to a high level prior to the lapse of the relatively short T A  time period (e.g., 10 microseconds), then the Plug Inhibit mode is enabled and only the upper transistor (FIG. 3) may be turned on. This Plug Inhibit condition is realized in FIG. 8 by the T A  Test circuit 76 generating a trigger pulse 80 whenever the specified condition occurs (-DRIVE goes high prior to occurrence of T A  pulse). This pulse 80 resets a flip flop 82, or equivalent circuit, so that the plug inhibit signal, identified as -PLUG INHIBIT in the figures, goes low. 
     If the -DRIVE signal remains at a high level after the lapse of the relatively long T B  time period (e.g., 300 microseconds), then the Plug Inhibit mode is disabled and the lower transistor (FIG. 3) may operate in normal fashion. Disabling of the plug inhibit mode is realized in FIG. 8 by the T B  Test circuit 78 generating a trigger pulse 84 whenever the specified condition occurs (-DRIVE goes high after T B  occurs). This pulse is used to set the flip flop 82, thereby causing the -PLUG INHIBIT signal to go high. 
     As indicated in FIG. 8, two additional control signals from the microprocessor 20 (FIG. 4) may be used to set/reset the Plug Inhibit mode. A first signal, on signal line 86, identified as DISABLE -PLUG INHIBIT, is combined with the trigger pulse 84 in an OR gate 88 prior to being directed to flip flop 82. Hence, either the trigger pulse 84 or a signal sent from the microprocessor over signal line 86, may be used to disable the Plug Inhibit mode. A second signal, on signal line 90, is ANDed with the output of flip flop 82 in an AND gate 92. Hence, the microprocessor 20 can directly force the enabling of the Plug Inhibit mode by controlling the signal on signal line 92. In the preferred embodiment, where the motor being controlled is used in a high performance tape drive system, such as the 4600 Tape Subsystem manufactured by Storage Technology Corporation of Louisville, Colo., the control signals on signal lines 86 and 90 are used to control Plug Inhibit only in special situations, such as in a low current situation as might occur during an automatic tape threading operation, and in a tape rewind situation. At all other times, Plug Inhibit is controlled as above described. 
     FIG. 9 depicts some of the waveforms and signals associated wit the operation of the circuits shown in FIG. 3, FIG. 4, and FIG. 8. No fixed scale is used with respect to the horizontal axis. The current waveform shown in FIG. 9 is a simplified equivalent to the current waveform shown in FIG. 5B, and the various timing references, e.g. t 11 , t 12 , t 16  indicated thereon are the same for both figures. Accordingly, the previous discussion describing the various events that occur in connection with the description of FIG. 5B also applies to FIG. 9. Included in FIG. 9 is an indication of when current is flowing through each of the four diodes D3, D4, D5, and D6 (FIG. 3), as well as when each of the four transistors Q1, Q2, Q3, and Q4 are turned on. (A diode has current flowing therethrough whenever its respective signal is high; a transistor is turned on whenever its respective base signal, identified as BQ1, BQ2, BQ3, or BQ4, is high). 
     Advantageously, the velocity of the motor can be determined as part of this invention by sensing the back EMF of the motor when all four transistors of the H-bridge are off and the motor current I M  is 0. This technique of sensing the back EMF voltage to determine motor velocity is not new. However, this technique in combination with the improved H-bridge power amplifier of the present invention is believed to be a novel combination. FIG. 7 shows one side of the motor being connected to ground by a resistor R3. In the preferred embodiment this resistor would be on the order of 2,000 ohms, so that within a few milliseconds of having all four transistors turned off, the voltage on the other side of the armature can be sensed, indicating the back EMF directly without the need for differential sensing with its common mode problems. 
     As thus described, an improved H-bridge power amplifier and method for controlling the same has been disclosed. The circuit and control method described provide a motor current that has a much lower ripple than has been realized in the prior art at approximately the same switching frequency. Further, the current command and current sense circuits may both be unipolar, thereby simplifying the analog circuitry associated therewith. The polarity of the sensed motor current I M  is inferred from knowledge of which of the two transistors Q1 or Q2 is turned on. More significantly, the motor current flows through the sensing resistor only when one of the upper transistors of the H-bridge power amplifier is turned on, which is the only time that the current needs to be sensed. Thus, the power is not dissipated in the sensing resistor when not needed as occurs in the prior art. The control circuitry (FIG. 4) associated with the present invention is relatively simple as compared to the complex circuits used to vary the duty cycle used in the prior art. Advantageously, this circuitry may be realized using conventional components that are readily available from many manufacturers. Advantageously, the constant off-time, T F , associated with the present invention may be readily modified by merely adjusting the delay of the timer 33 (FIG. 4). In fact, multiple constant off-times could be selectively used depending upon the particular mode of operation. By selectively choosing T F , the frequency of the ripple in the motor current can be controlled to a large degree, thereby allowing a low switching rate if desired. 
     Attached hereto and filed as a part hereof is Appendix A, containing a microprocessor program listing (&#34;code&#34;) of a representative program that could be used to control a microprocessor 20 for a tape drive system that uses a motor controlled by the H-bridge power amplifier of the present invention. This representative program comprises the best mode contemplated for carrying out the control of a high performance tape drive subsystem, such as the 4600 Tape Subsystem manufactured by Storage Technology Corporation of Louisville, Colo. In the preferred embodiment, the microprocessor used is a model Z8000, commercialy available from Zilog Inc. of Cupertino, Calif. It is noted that only a small portion of the code included in Appendix A, such as as p. 16 line 1018, and p. 39, lines 2263, 2264, relate directly to the invention as herein described and claimed. Other portions of the code are used to generate the CURRENT COMMAND words that are fed into the DAC 32 (FIG. 4) in order to generate the desired current reference signal. Still other parts define the ENABLE and POLARITY signals described in connection with FIG. 4 and FIG. 9. As such, it is to be emphasized that the invention can be practiced without the aid of a microprocessor. Any suitable controller would suffice. 
     While the present invention has been described by reference to a particular embodiment thereof, those skilled in the art will recognize numerous variations and modifications that could be made thereto to perform equivalent functions. Accordingly, the scope of the present invention is to be ascertained by reference to the appended claims. ##SPC1## ##SPC2## ##SPC3## ##SPC4## ##SPC5## ##SPC6## ##SPC7## ##SPC8##