Comparator circuit operable for a wide range of input signal
BACKGROUND OF THE INVENTION 
     The present invention relates to a comparator circuit for comparing an input signal with a reference voltage. 
     A comparator circuit basically comprises a differential amplifier provided with a pair of input terminals (a non-inverting input terminal and an inverting input terminal) and an output terminal. 
     An input signal and a reference voltage are applied to the pair of input terminals, respectively and the differential amplifier compares the input signal with the reference voltage. As is well known in the art, the reference voltage is set at approximately center of high and low levels of the input signal, and the differential amplifier produces a first level (e.g. a power voltage V DD ) of output when the input signal is larger or higher than the reference voltage and a second level (e.g. a ground potential) of output when the input signal is smaller or lower than the reference voltage thereby to achieve the comparison of the input signal and the reference voltage. 
     The above-mentioned comparator circuit operates accurately as far as the reference voltage is at the approximately center of the high and low levels of the input signal. However, in the case where the input signal is shifted in level due to noise or the like and both of the high and low levels of the input signal are higher or lower than the reference voltage, the differential amplifier always produces a first or a second level of output irrespective of the state of the input signal, resulting in failure in the comparison between the input signal and the reference voltage. Also in the case where the reference voltage is shifted above the high level of the input signal or lower the low level of the input signal due to fluctuation of the power voltage, the differential amplifier fails to achieve the comparison between the input signal and the reference voltage. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a comparator circuit operable for a wide range of input signal. 
     It is another object of the present invention to provide an improved comparator circuit operable without being influenced by noise or fluctuation of a power voltage. 
     The comparator circuit according to the present invention comprises a signal input terminal, a differential amplifier having first and second input terminals and an output terminal, a capacitor coupled between the signal input terminal and the first input terminal, a first diode coupled between the second input terminal and a first voltage terminal, a second diode coupled between the first and second input terminals, and means coupled to the first input terminal for gradually changing the potential at the first input terminal towards the potential at the second input terminal. 
     According to the present invention, the second input terminal of the differential amplifier is set at a constant voltage determined by the first voltage and the potential at the first input terminal of the differential amplifier is clamped by the second diode and swung with respect to the potential at the second input terminal. 
     Therefore, the comparative relation between the potentials at the first and second input terminals of the differential amplifier can be laid in a desired state. Thus, stable comparison operation can be achieved without influence of noise or fluctuation in a power voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram of a comparator circuit according to a prior art; 
     FIGS. 2A, 2B and 2C are timing diagrams showing operations of the comparator circuit of FIG. 1; 
     FIG. 3 is a schematic block diagram showing a comparator circuit according to a first embodiment of the present invention; 
     FIG. 4 is a timing diagram showing operation of the comparator circuit of FIG. 3; 
     FIG. 5 is a schematic block diagram of a comparator circuit according to a second embodiment of the present invention; 
     FIG. 6 is a schematic block diagram showing a comparator circuit according to a third embodiment of the present invention; 
     FIG. 7 is a schematic block diagram of a comparator circuit according to a fourth embodiment; 
     FIG. 8 is a timing diagram showing operation of the circuit of FIG. 7; and 
     FIG. 9 is a schematic circuit diagram showing an example of the differential amplifier. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIGS. 1 and 2, a conventional comparator circuit and its operation are explained. 
     As shown in FIG. 1, the comparator circuit basically comprises a differential amplifier 8 supplied with a power voltage V DD  from a power source 7 and a ground potential (GND) as power supply. An input terminal 1 is connected to a non-inverting input terminal (+) of the differential amplifier 8 via a capacitor 2. A pull-down resistor R IN  is connected between the input terminal 1 and the ground potential. Resistors R1 and R2 coupled between the power voltage V DD  and the ground potential form a voltage divider to generate a reference voltage V ref  from the intermediate junction of the resistors R1 and R2. The reference voltage is applied to an inverting input terminal (-) of the differential amplifier 8. A comparison result is outputted from an output terminal 9. 
     FIG. 2A shows a normal comparison operation of the comparator circuit of FIG. 1. The reference voltage V ref  is at approximately center of high and low level of the input signal V 1  applied at the input terminal 1. When the level of the input signal V 1  is above the reference voltage V ref , the differential amplifier produces a high level of output V 9 . When the input signal V 1  below V ref , a low level of output signal V 9  is produced. 
     FIG. 2B shows the case where the low level of the input signal V 1  is shifted above V ref  due to noise or the like superposed on the input signal V 1 . In this case, the differential amplifier 8 always produces a high level of the output V 9  irrespective of the state of the input signal V 1 . Thus, the comparison between the input signal V 1  and the reference voltage V ref  cannot be achieved. 
     FIG. 2C shows the case where the reference voltage V ref  is shifted above the high level of the input signal V 1  due to fluctuation in the power voltage V DD  or the like. In this case, the input signal V 1  is always below V ref  and therefore, high and low levels of the input signal V 1  cannot be distinguished by the output V 9  of the amplifier 8. 
     Referring to FIG. 3, a comparator circuit according to a first embodiment of the invention is explained. 
     In FIG. 3, elements corresponding to those shown in FIG. 1 are denoted by the same references. 
     The present embodiment is featured by a diode 3 having an anode connected to a node A, i.e. the non-inverting input terminal (+) of the amplifier 8 and a cathode connected to a node B, i.e. the inverting input terminal (-) of the amplifier 8, a diode 4 having an anode connected to the node B and a cathode connected to the ground, a resistor 6 connected in parallel with the diode 3, and a resistor 5 connected between the power voltage V DD  and the node B. 
     Referring to FIG. 4, operation of the circuit of FIG. 3 is explained. 
     The potential V B  serving as the reference voltage V ref  at the node B is determined by a forward voltage V fl  of the diode 4 which passes a current from V DD  via the resistor 5 to the ground. Thus, the potential V B  is set at V fl  with respect to the ground potential. 
     When the signal V 1  at the input terminal 1 is raised in potential by an amplitude V at a time t 1 , this rise in potential V 1  is transmitted to the node A through the capacitor 2 so that the potential V A  at the node A is raised by a forward voltage V f2  of the diode 3 from V B  so that the potential V A  becomes a high voltage (V fl  +V f2 ) with resect to the ground. In this instance, the potential V A  applied to the non-inverting input terminal (+) is higher than the potential V B  applied to the inverting input terminal (-), and therefore the output V 9  at the output terminal 9 changes from the ground potential to V DD . This shows that the high level of the input signal V 1  is applied to the comparator. 
     When the input signal V 1  falls from the high level to the low level at a time t 2 , the potential V A  at the node A rapidly falls in potential by the amplitude V from the level of (V fl  +V f2 ) through the capacitor 2. However, immediately after the potential fall of V A , the potential V A  is raised gradually according to a time constant determined by the capacitor 2 and the resistor 6 towards the potential V B  until a time t 3  when the input signal V 1  is again raised in potential. In this instance, the potential V A  applied to the non-inverting input (+) of the amplifier 8 is below the potential V B  applied to the inverting input terminal (-) of the amplifier 8 so that a low level output V 9  is produced. During the period from t 2  to t 3 , if some noise is applied to the input terminal 1, the output V 9  is not affected by the noise unless the potential of the noise exceeds the sum of the forward voltage V fl  and a potential difference V C  illustrated, i.e. V fl  +V C . The operation after t 3  is performed similarly. 
     In the embodiment, any known differential amplifier can be employed as the amplifier 8. One example is illustrated in FIG. 9. As shown in FIG. 9, the amplifier 8 is composed of P-channel transistors Q P1  and Q P2  forming a current mirror type load circuit, N-channel input transistors Q N1  and Q N2  and an N-channel constant current transistor Q N3 . 
     Referring to FIG. 5, a comparator circuit according to a second embodiment is explained. 
     The circuit of the present invention is obtained by replacing the diodes 3 and 4 in FIG. 3 with a series connection of diodes 3l-3n and a series connection of diodes 4l-4n, respectively. By adjusting the numbers m and n, V fl  and V f2  in FIG. 4 can be set at optional values. 
     Referring to FIG. 6, a comparator circuit according to a third embodiment of the present invention is explained. 
     This embodiment is obtained by P channel MOS field effect transistors 11 to 13 and a resistor 14 in place of the resistors 5 and 6 of FIG. 3. The transistors 11 to 13 and the resistor 14 form a known current mirror circuit and the transistors 12 and 13 provide constant values of currents to the nodes A and B, respectively. The current from the transistor 13 makes the diode 4 conductive to set the potential V B  at the forward voltage V fl  with respect to GND. 
     The transistor 12 has the smaller dimension than that of the transistor 13 to flow the smaller amount of current to the node A. this current from the transistor 12 is used to charge the capacitor 2. 
     The operation of this embodiment is similar to that of the circuit of FIG. 3. Only difference is that the curve of V A  from t 2  to t 3  in FIG. 4 is not exponential but linear. This embodiment is advantageous in forming the comparator circuit at high density because the transistors 11 to 13 can be formed by a small area on a semiconductor substrate as compared to the formation of the resistors 5 and 6. 
     FIG. 7 shows a fourth embodiment of the present invention. 
     This embodiment corresponds to the case where the polarity of the power voltage and the inputs of the amplifier 8 in FIG. 3 is reversed. 
     Namely, the input terminal 1 is coupled to the inverting input (-) of the amplifier 8 through the capacitor 2. A diode 4&#39; is connected between the power voltage V DD  to a node A&#39; connected to the non-inverting input (+) and a resistor 5&#39; is coupled between the node A&#39; and the ground potential to make the diode 4&#39; conductive. Therefore, the node A&#39; is biased at the potential &#34;V DD  -V fl&#34;  (V fl  being the forward voltage of the diode 4&#39;). A diode 3&#39; is coupled between the nodes A&#39; and B&#39; to clamp the lower level at the node B&#39; to the potential &#34;V DD  -V fl  -V f2  &#34; (V f2  being a forward voltage of the diode 3&#39;). 
     Thus, the comparator circuit according to this embodiment detects the fall of the input signal V 1  at the input terminal and generates a high (V DD ) level of output V 9  at the output terminal 9 upon the fall of V 1 , as illustrated in FIG. 8. 
     As has been explained above, the comparator circuit according to the present invention can operate without influence of noise or fluctuation in a power voltage.