Digital FM demodulator signal-to-noise improvement
BACKGROUND OF THE INVENTION 
     The invention relates to FM demodulators, and more particularly to digital FM demodulators, and most particularly to such demodulators employing the quadrature technique. 
     The principle of the quadrature demodulator is well-known in the art. In summary, the technique involves mixing an FM radio frequency signal with a version of the same signal which has been delayed 90° at the center frequency (f o ) of the FM signal. The resulting signal contains a DC component whose time varying level is representative of the original modulating signal. The digital version of the quadrature FM demodulator was disclosed by David Ludington in Electronic Design, Apr. 12, 1976, p. 126, which article is incorporated herein by reference. 
     The digital versions of the quadrature FM demodulator are subject to audio noise due to the use of clocked shift registers to provide the required 90° phase shift. The noise results from an interaction between the shift register clock rate and the period of the FM signal being demodulated to produce beat frequencies, as will be more fully described hereinafter. This noise is, of course, detrimental to the operation of the demodulator, and it is desirable that it be removed. 
     It is therefore an object of the present invention to provide a digital FM demodulator which reduces the amplitudes of beat frequencies caused by digital sampling. 
     SUMMARY OF THE INVENTION 
     Beat notes produced by square wave sampling in a digital FM demodulator are alleviated by adding random noise, or dither, to the square wave signal to randomly vary the width of successive pulses in the square wave signal. This eliminates repetitive sampled bit patterns resulting from lack of an integral multiple relationship between the frequency of the square wave and the sampling frequency, which produces an audio beat note in the demodulator output. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention may be more fully understood by reading the following description of a preferred embodiment thereof in conjunction with the appended drawings, wherein: 
     FIG. 1 is a block diagram of a digital quadrature FM demodulator as practiced in the prior art; 
     FIGS. 2a, 2b, and 2c are a series of waveforms produced in the demodulator of FIG. 1; 
     FIG. 3 is a schematic diagram of a digital quadrature FM demodulator with dither added in accordance with the present invention; and 
     FIGS. 4a, 4b, and 4c are a series of waveforms produced in the demodulator of FIG. 3. 
    
    
     DESCRIPTION OF A PREFERRED EMBODIMENT 
     A simplified version of a digital quadrature FM demodulator of the type used in the present invention is shown in FIG. 1. An FM signal in the form of an input limited FM wave is applied at terminal 10 and is coupled to one input 12 of an exclusive-OR gate 14. The FM signal is also applied via line 16 to a delay device 18 which may be implemented as a digital shift register comprising a serial combination of D-type flip-flops 20, 22 and 24. While only three flip-flops are shown, the dotted interconnections between flip-flops 22 and 24 are intended to indicate that a larger number required to provide a 90° phase delay is provided in delay device 18. A clock signal is applied to terminal 26 and is in turn coupled to the &#34;C&#34; input of each of flip-flops 20, 22, 24, etc. Further, the &#34;Q&#34; output of each flip-flop, say 20 for example, is coupled to the &#34;D&#34; input of the succeeding flip-flop, say 22 for example. The &#34;Q&#34; output of the final, or Nth, flip-flop 24 is coupled to input 13 of exclusive-OR gate 14. The output of exclusive-OR gate 14 is applied to a low-pass filter (LPF) 28 whose output 30 is the demodulated signal. 
     When shift register 18 is clocked by a stable frequency source at terminal 26, the incoming FM signal is sampled at the clock rate, and the contents of the register become a binary time representation of the FM signal. The bit pattern in register 18 is, of course, a function of the frequency ratio between the FM input signal at terminal 10 and the clock signal at terminal 26. When the length of register 18 in flip-flop stages is such that one quarter cycle of the center frequency of the FM input signal is stored at any instant, the digital register is equivalent to an analog 90° delay line. When the input and output of the line are applied to a phase detector, the detector output varies with frequency as the delay line shift varies around 90°. Exclusive-OR gate 14 is the digital equivalent of an analog doubly balanced mixer. Its output is a 50% duty cycle wave when the square wave inputs are 90° apart. Low-pass filter 28 passes the average value of the comparator output which is linearly proportional to the difference between the clock frequency and a harmonic of the FM input frequency. 
     For a 90° time delay, the shift register length, N, is related to the clock frequency, fc, and modulated frequency, fm, by the relation: 
     
         N=fc/4fm 
    
     The ratio of the average output voltage change to input frequency change may be increased by using additional multiples of N stages in the shift register at the expense of increased complexity and operating power demand. The output stability of the demodulator is determined by the clock accuracy, which may be very high, and by the logic &#34;0&#34; and &#34;1&#34; voltage stability of the exclusive-OR gate. The latter is excellent for CMOS logic whose output transistors saturate to either ground or to the drain supply voltage. 
     The waveforms produced by the operation of the circuit of FIG. 1 are shown in FIGS. 2a, 2b, and 2c. The waveforms are shown in three groups (a), (b) and (c), each comprising three waveforms. Group (a) illustrates the waveforms, at the points marked A, B and C in FIG. 1 when the FM input signal is equal to the center, or carrier, frequency f o  of the input signal. Group (b) illustrates the waveforms at the same points, when the input frequency f is greater than f o . Lastly, group (c) illustrates the waveforms at points A, B and C when the input frequency f is less than f o . The signal at point A is the unaltered FM input signal originally applied at terminal 10, and the signal at point B is the FM input signal delayed by a time corresponding to 90° at frequency f o  by passage through shift register delay device 18, as shown in each of groups (a), (b) and (c). The signal at B is delayed by 90° based upon the center frequency f o . The signal appearing at point C is the resultant waveform after the A and B waveforms have been exclusive-OR&#39;ed by gate 14. 
     When f=f o  as in group (a), the duty cycle of waveform (c) is essentially 50%, i.e., the waveform has a high, or a logical &#34;1&#34; value equally as long as it has a low, logical &#34;0&#34; value. When f is greater than f o , the duty cycle increases as shown in group (b); and when f is less than f o , the duty cycle decreases. Thus, the average value of waveform C in group (b) is larger than waveform C in group (a). Conversely, the average value of waveform C in group (c) is smaller than that of waveform C in group (a). Thus, the average value of the waveform at C derived by LPF 28 (FIG. 1) is representative of the instantaneous frequency of the FM input signal, and consequently is representative of the original modulating signal. 
     Since the clock signal applied at terminal 26 causes shift register 18 to sample the input FM signal at discrete intervals, the bit pattern in shift register 18 will vary slightly from each 90° sample to the next even when the frequency of the input signal is constant unless the clock frequency is an integer multiple of the input signal frequency. If there were an integer relationship between the clock and the input signal, one would expect for every 100 clock transitions to see 100 &#34;1&#34;&#39;s followed by 100 &#34;0&#34;&#39;s, assuming a 50% duty cycle, i.e., f=f o . But, if the clock is not an integer multiple of the input signal, one might see 100 &#34;1&#34;&#39;s followed by 100 &#34;0&#34;&#39;s, and then in the next round see 101 &#34;1&#34;&#39;s and 100 &#34;0&#34;&#39;s. As the phase relationship slides back and forth, a pattern such as 100, 100, 101, 100, 100 101.... might be observed. This is a digital beat frequency pattern which may manifest itself in the demodulated signal as a slightly varying output voltage in the audio range. 
     It has been found that the audible beat note can be eliminated by randomizing the transitions of the FM input signal to destroy the beat pattern in shift register 10. This is accomplished by adding random noise, or dither, to the FM input signal in the manner illustrated in FIG. 3. 
     In the circuit of FIG. 3, a sinusoidal FM input signal (usually an IF) signal is applied at terminal 10 to a limiter 40 which produces at its output a non-symmetrical square wave. This square wave is applied to a divide-by-two counter 42 which produces a symmetrical square wave at node 44 through resistor 43 as illustrated in FIG. 4(a). The square wave at node 44 is applied to a series of inverters 46, 48 and 50, the first of which 46 is operated as a voltage comparator as will be described in detail hereinafter. From inverter 50 the signal is applied to shift register delay circuit comprising a multiplicity of DC flip-flops configured as described in connection with FIG. 1. The flip-flops are operated by a clock 52 whose pulses are delivered to the respective flip-flops through a clock tree 54. As previously discussed the undelayed portion of the square wave created from the RF input at terminal 10 is applied via line 12 to exclusive-OR gate 14, and the portion of the square wave delayed by shift register delay circuit 18 is applied to exclusive-OR gate 14 via line 13. It should be noted that the &#34;undelayed&#34; signal is actually slightly delayed by picking the signal off after the first stages 20 of delay shift register 18. It has been found that this immediately reduces beat note amplitude by one-half compared to the circuit of FIG. 1. The output from exclusive-OR gate 14 is applied to one input of another exclusive-OR gate 56 which acts as an inverter depending upon the presence or absence of a voltage applied to the second input of gate 56 at terminal 58. The output of gate 56 is applied to LPF 28 which produces a voltage on line 30 which is representative of the original modulating signal. 
     As previously described, beat notes are present in the output on line 30 since the rate at which data is shifted through shift register delay circuit 54 is not usually an exact multiple of the frequency of the square wave which is being shifted through it. The beat note could be removed from the audio range if the duration of each square wave input pulse could be slightly varied from pulse to pulse such that the regularity of the non-integral division by delay circuit 18 is eliminated. This is accomplished by the addition of a capacitor 60 at node 44 and the previously described comparator 46. 
     Capacitor 46 is successively charged and discharged by the square wave appearing at node 44. As shown in FIG. 4(b) the charging of capacitor 44 causes the front edge 404 of a typical square wave pulse in waveform 400 to be rounded in its transition from zero to +V volts. Similarly, the trailing edge 406 is rounded as the voltage transitions from +V to zero volts. Comparator 46 is used as a level detector which switches from zero to +V volts, and vice versa, when the input level attains some threshold voltage Vc. If a positive DC voltage level is added to waveform 400, it is shifted upwardly to the position shown by waveform 402. When the position of the waveform is thus shifted, the time at which the waveform attains the voltage Vc required to cause comparator 46 to switch changes due to the rounded leading edge 404. Waveform 400 attains voltage Vc at time t 2 , while shifted waveform 402 attains Vc slightly earlier at time t 1 . Similarly, on trailing edge 406, waveform 400 decreases to Vc at time t 3  while waveform 402 reaches the same voltage at time t 4 . As shown in FIG. 4(c) the results in waveforms at the output of comparator 46 which are different for waveform 400 as compared to waveform 402. Specifically, waveform 400&#39;, which corresponds to waveform 400 in FIG. 4(b), has a pulse width which is slightly shorter than that of waveform 402&#39;, which corresponds to waveform 402 in FIG. 4(b). Clearly, waveform 402&#39; requires more samples in shift register delay circuit 18 than waveform 400&#39;, and they will thus produce different bit patterns in shift register 18. If the voltage added to waveform 402 were random as in the present invention, the pulse width as shown in FIG. 4(c) would vary from pulse to pulse, and thus produce a slightly different bit pattern in shift register 18 from pulse to pulse. This varying bit pattern destroys the repetitive bit patterns normally appearing in shift register 18 and thus eliminates the beat notes from the output by shifting them out of the audible range. The previously described comparators 48 and 50 act to square the waveform produced by comparator/level detector 46. 
     The random voltage, or &#34;dither&#34; which shifts waveform 400 to the position of waveform 402, or other random positions, may be provided by pseudorandom noise generator 62. The clock signal for noise generator 62 is derived from clock 52 and is reduced to a suitable rate by a divider 64 comprising a series of flip-flops 66, 68 and 70, each of which divides the clock signal by 2. It should be understood that any number of flip-flops could be used as indicated by the dotted connection between flip-flops 66 and 68, and flip-flops 68 and 70. Multiple taps 72 and 74 may be taken off divider 64 and passed through a switch 76 to provide a selectable division rate. The clock frequency applied to noise generator 62 is chosen to provide pseudorandom noise above the audio band, but below the radio IF. 
     Pseudorandom noise generator 62 operates by shifting data through a long shift register. The clock signal selected by switch 76 is applied via line 78 through an inverter 79 to a multiplicity of flip-flops 80, 82, 84, 86 88, 90, 92, 94 and 96. Not all flip-flop stages are shown in FIG. 3 as indicated by the dotted connection between flip-flops 94 and 96. A DC signal applied at terminal 98 to the reset terminal of flip-flop 80 through an inverter 100 acts to turn generator 62 on and off. As the clock signal is applied to the &#34;C&#34; inputs of flip-flops 80-96 by line 101, the contents thereof are shifted from flip-flop to flip-flop via their respective &#34;D&#34; inputs and &#34;Q&#34; outputs. A new bit to be shifted through flip-flops 80-96 is provided to the &#34;D&#34; input of flip-flop 80 by exclusive-OR gate 102 as hereinafter described. 
     In order to eliminate the possibility that the flip-flops will not lock into a state in which all flip-flops contain a binary &#34;1&#34; as often occurs when power is first applied to the circuit, a binary divider comprising interconnected flip-flops 110, 112, 114, 116 and 118 provides a reset signal on line 120 every 32 clock pulses when five divide-by-two stages are used as illustrated. The reset signal on line 120 and the Q output of flip-flop 96 are applied to an exclusive-OR gate 122 whose function is to invert the shift register output when a reset signal is present on line 120. The output from exclusive-OR gate 122 is applied to exclusive-OR gate 102 whose second input is derived from taps from the various stages of the shift register along line 124. 
     When the circuit for pseudorandom generator 62 is properly implemented, a maximally long random sequence of binary 0&#39;s and 1&#39;s is produced and applied from line 124 to capacitor 60. Resistors 130, 132, 134, 136, 138, 140, and 141 provide a D/A converter such that an 8 level pseudorandom voltage is applied to capacitor 60. It should be understood that any other design for random noise generator 62 would be equally suitable. The application of the random noise voltage to capacitor 60 has the effect of shifting the level of the square wave appearing at node 44 as previously described in connection with FIG. 4(b). 
     It should be noted that flip-flop divider 42 is not necessary to operation of the invention. The primary advantage of flip-flop 42 is that it assures a 50% duty cycle waveform at node 44. Otherwise, the IF signal feeds through and a better LPF 28 would be required. Further, dither can be optionally applied prior to divider 42 without departing from the invention. 
     While particular embodiments of the present invention have been shown and described, it is obvious that changes and modifications may be made therein without departing from the true scope and spirit of the invention. It is the intent in the appended claims to cover all such changes and modifications.