High capacity current mirror circuit
FIELD OF THE INVENTION 
     This invention relates to a high capacity current mirror circuit of a type which comprises an operational amplifier having one input connected to both a reference current source and a power supply pole through a first resistor, and having another input connected to said power supply pole through a second or feedback resistor, its output being connected to the base of a transistor, whereby it can supply a reflected current proportional to the reference current. 
     BACKGROUND OF THE INVENTION 
     A current mirror circuit is a circuit which enables transfer from one circuit leg to another of a current supplied, for example, by a reference current source. 
     Current mirror circuits have many applications in the field of integrated circuits, being particularly useful to bias differential circuits, in the oscillating circuit sector, and in sampling circuits of the sample-and-hold type. 
     Especially with sample-and-hold circuits, there exists a requirement for currents of large magnitudes, to discharge at a fast rate the capacitances which are typical of such circuits. 
     It has been proposed to employ, in an IC environment, conventional design current mirrors comprising transistors of the pnp type which occupy, within the integrated circuit itself, a surface area which is at least five times as large as that of a pnp transistor of minimum surface area. This expedient is dictated by the need to transfer high currents, in excess of 1 mA, but involves the serious drawback that a large silicon surface area must be reserved on the integrated circuit, at variance with the trend toward integrating an increasingly higher number of circuits per unit surface area. 
     A second expedient is that of integrating high capacity current mirrors, of the type comprising an operation amplifier having one input connected to both a reference current source and a power supply pole through a first resistor, and having another input connected to said power supply pole via a second, socalled &#34;feedback&#34;, resistor; the amplifier has its output connected to the base of a transistor of the pnp type which supplies a reflected current I O  proportional to the reference current I R . The proportionality of the current to be transferred to the reference current will depend on the relation between the first resistance in the circuit and the feedback resistance, as well as directly on the α parameter of the pnp-type transistor which supplies the reflected current. 
     This second mirror type, while substantially achieving its objectives, has the disadvantage of involving a diminished α parameter of the pnp transistor and a consequent, not negligible error in the reflected current I O . 
     SUMMARY OF THE INVENTION 
     The technical problem underlying this invention is that of providing a current mirror circuit which affords accuracy and reduced silicon surface area requirements on the integrated circuit, thus overcoming the above-mentioned shortcomings of comparable prior circuits. 
     This problem is solved by a high capacity current mirror circuit as indicated being characterized in that said transistor is of the npn type and has its collector connected to said pole via said feedback resistor 
    
    
     Further features an the advantages of this invention will be apparent from the following description of an exemplary embodiment thereof, given by way of illustration and not of limitation with reference to the accompanying drawing figures. 
     BRIEF DESCRIPTION OF THE DRAWING 
     In the drawing: 
     FIG. 1 is a diagramatic view of a current mirror circuit according to the invention; and 
     FIG. 2 is a more detailed diagramatic view of a current mirror circuit according to the invention in a preferred modification thereof. 
    
    
     DETAILED DESCRIPTION 
     With reference to the drawing figures, generally designated at 1 is a high capacity current mirror according to this invention. 
     Advantageously herein, the current mirror circuit 1 includes an operational amplifier circuit 2 of the differential cell transconductance type, which has a first input connected through a first electric connection 3 to both a reference current I R  source and power supply pole V C  through a first resistor R1. The amplifier 2 has a second input connected, via a second electric connection 4, to both said power supply pole V C  via a feedback resistor R2, and to the collector C8 of a transistor T8 of the npn type which supplies, in accordance with this invention, a reflected current I O  from its emitter E8 to a node A at a voltage of V O . 
     An operational amplifier of the transconductance type is one which is controlled by voltage at its inputs to supply a required base current for the transistor T8. The transconductance of the amplifier is due to the ratio between the output current and the input voltage. 
     In on embodiment of the invention, the amplifier 2 has its output connected directly to the base B8 of said transistor T8 through an electric connection indicated at 5, as depicted in FIG. 1. 
     With particular reference to the example of FIG. 2, said amplifier 2 comprises a differential cell structure composed of a pair of transistors T1 and T2 of the npn type having their emitters E1 and E2 connected to each other and to ground through a current I G  source. The bases B1 and B2 of said transistors T1 and T2 constitute the inputs of the amplifier 2, and connected thereto are the aforesaid electric connections 3 and 4, respectively. 
     The collectors C1 and C2 of the transistors T1 and T2 are respectively connected to the power supply V C  through diodes D1 and D2 and to the base B3 of a transistor T3 and the base B4 of a transistor T4, respectively. 
     The transistor T3 is of the pnp type, and has its emitter E3 connected directly to the power supply V C , while its collector C3 is grounded with the interposition of a diode D3. 
     The transistor T4 is also of the pnp type and has its emitter E4 connected directly to the power supply V C , its collector C4 being connected to the collector C6 of a transistor T6 which is of the npn type and has its emitter E6 grounded and its base B6 connected to the collector C3 of said transistor T3. 
     The collector C6 of the transistor T6 constitutes the output of said amplifier 2, and said electric connection 5 extends therefrom. 
     Advantageously in a preferred embodiment of this invention, as shown in FIG. 2, the transistor T8 of the npn type, which supplies the reflected current I O  from its emitter E8, is connected in a so-called Darlington configuration 6 through a second transistor T7 of the npn type. The transistor T7 in the conventional Darlington configuration 6 has respectively its emitter E7 connected directly to the base B8 of the transistor T8 and its collector C7 connected to the collector C8. 
     The transistor T7 in the Darlington arrangement 6 has its base B7 connected directly to the collector C6 of the transistor T6, at the amplifier 2 output, via the electric connection 5. 
     The reflected current I O  is controlled by the transconductance operational amplifier stage which supplies the required base current for the transistor T8 of the npn type. 
     The high capacity current mirror circuit of this invention maintains a proportional relationship between the reflected current I O  and reference current I R , being defined by the ratio of the first resistor R1 to the feedback resistor R2. Accordingly, higher or lower reflected currents become obtainable by merely changing the ratio of said resistors R1 and R2. 
     In the preferred modified embodiment employing the Darlington arrangement 6 of the transistors T7 an T8, the aforesaid proportionality will also be dependent on that α parameter of the Darlington arrangement 6, which is, however, quite close to unity. Thus, I O  =I R  ·(R1/R2)·α. 
     The voltage across the resistor R1 should be no less than 300 mV, to avoid saturating (SAT) the transistor T1 forming a part of the transconductance operational amplifier stage. Despite this limitation, the dynamic range at the output of the inventive current mirror is, even where a Darlington arrangement is used, nearly identical to that of a conventional current mirror, on account of the voltage V O  which appears at the terminal A being equal to the supply voltage V C  less just 1.3 Volts. While the values of V C , R1 and R2 are not important for the embodiment shown, the maximum voltage V O  at the terminal A is due to the relationship V O  max=V C  -V 1  -V CE/SAT  -V BE , where V 1  is the voltage drop across the resistor R1, V CE/SAT  is the voltage drop across the collector/emitter junction of the transistor T1 and V BE  is the voltage drop across the emitter junction of the transistor T8. V O  max will be equal to V C  -1.3 volts when V 1  =300 mV. 
     A first, self-evident advantage of this invention is that, in respect of the transistors in the integrated circuits, a transistor of the npn type, as integrated on a minimal surface area, operates, while retaining good characteristics, on a current which is about ten times as high as with a transistor of the pnp type occupying the same area of silicon. Thus, with high currents above 1  mA, the current mirror according to the invention will occupy a reduced silicon surface area in the integrated circuit, which is of high significance in economical terms. 
     Another advantage is that this high capacity current mirror circuit affords higher accuracy than conventional high capacity current mirror circuits.