Method and apparatus for feedback control loop bandwidth and phase margin regulation
BACKGROUND OF THE INVENTION 
     This invention relates to feedback control loop systems. More particularly, it relates to feedback control loop systems for controlling elements which have a variable gain and frequency response and which produce an output signal proportional to the element gain and its frequency response. 
     In most feedback control loop systems, the basic problem to be solved is simply that of generating and feeding back an error correction signal whose parameters are essentially independent of any effects of gain or frequency response by the element to be controlled. In such a situation the gain and frequency response to be applied to the error correction signal remains at all times substantially constant, regardless of the output of the controlled element, since the controlled element has no impact upon the bandwidth of the feedback control loop. Conversely, in a conventional automatic gain control circuit the problem addressed is that of amplifying or attenuating a signal utilized in an open-loop control system. In that situation the applied gain is utilized for stabilization of another parameter of operation of the controlled element which does not itself affect the applied gain or frequency response. 
     As an example of servo control systems illustrating the closest-known current understading of the adaptive control problem, reference is made to an article by Richard L. Melton of Industrial Drives, A Kollmorgen Company, entitled &#34;Real-Time Adaptive Velocity Control,&#34; appearing in Powerconversion &amp; Intelligent Motion, Volume 12, No. 5, May 1986, page 40-44.  This article is based in part on the Technical Report TR-85-CO2, &#34;Real-Time Adaptive Control,&#34; March 1985, by Wayne T. Culberson, Research Scientist, Kollmorgen Corporation, Industrial Drives Division. The article teaches of the need for optimum servo compensation over a wide range of load parameter variations. However, the article fails to recognize the existence or possibility of a critical low-frequency pole shift in the disclosed design which moves concurrently with a zero of interest. Moreover, a critical analysis reveals that hardware disclosed in Appendix C and Appendix D of the article do not correspond to the block diagram shown in FIG. 3 of the article. Furthermore, the block diagram of FIG. 3 cannot be realized in practice because of the missing pole at the block labeled KI/S. Consequently, the teachings of the article are inadequate for a solution of the problem addressed. 
     Heretofore, except for U.S. Pat. No. 4,092,530 to the present inventor, it has not been deemed necessary to address the compound problem of a second-order stabilization in which it is necessary to stabilize the loop gain and frequency response of the system stabilizing feedback loop, wherein the controlled element itself causes variations in the loop gain and frequency response and in which the operating parameters of the controlled element thus affect the gain and bandwidth of the feedback control system. In such a compound feedback control system, it is necessary to stabilize simultaneously the feedback loop gain, bandwidth and phase margin to compensate for variations in the gain and frequency response of the controlled element in order to suppress noise and potential system oscillation and stabilize the operating parameters of interest, such as output frequency, output signal level, and feedback control loop bandwidth and phase margin. 
     One such variable gain and frequency response element for which compounded feedback control is desirable is an electromechanical actuator (such as a DC- or AC-driven motor or thruster) whose higher-frequency gain and frequency response is inverse to loading inertia related directly to the actuator, with or without gearing. Most succinctly, the inertia, or mechanical &#34;pole&#34;, P J , which is inverse to directly relate loading inertia to the actuator, if variable because of loading inertia changes, will cause proportional changes in feedback-controlled loop bandwidth and phase margin in which it is a dominant, or controlling, factor. 
     To illustrate the stabilization problem more specifically, reference is made to FIG. 1 which shows that the loop-bandwidth affects the changes in loading inertia (and, therefore, pole P J ) related to the actuator have on a typical actuator feedback control loop. The example given illustrates two-to-one variation in loading inertia, as manifest by displacement of the pole P J . Variation in loading inertia may occur upon the change of a weight of controlled arm of an actuator. This causes a similar two-to-one variation in the loop bandwidth and, therefore, step-response time and following error, or FE, (if rate-stabilized). If this is not compensated for, these changes could be totally unacceptable in the context of overall system performance. But loading inertia and P J  variations of over 100 times-to-nominal occur and should be accommodated from the viewpoint of a system user; this is what has brought about this invention. 
     SUMMARY OF THE INVENTION 
     According to the invention, a method and apparatus are provided for automatically stabilizing the total loop gain, bandwidth and phase margin of a feedback control loop system. The method and apparatus provide control via a compensating control loop of a compensating element having variable gain and frequency response to produce an output signal inversely proportional to loading and frequency response of a controlled element (load) controlled by a principal feedback control loop. Stated in the terminology of servo controls, a compensating feedback control loop provides an automatic frequency-tracking zero, Z V , versus an independently variable load pole, P J , within the forward path of the principal feedback control loop in common with the compensating feedback control loop such that Z V  &#34;cancels&#34; P J  wherever it is within the design frequency range of operation. Both the principal feedback control loop and the compensating feedback control loop exhibit regulated gain and regulated bandwidth, so that the principal feedback control loop possesses regulated dynamic and static performance. 
     In accordance with the present invention, a feedback control loop system is disclosed for controlling a compensating element which includes means for generating a compensating feedback signal corresponding to the difference between a desired value of an element operating parameter and a measured value of the operating parameter in the controlled-element output signal, and means for compensating a principal feedback signal for variations in the controlled element gain and frequency response. The compensating feedback signal generating means includes means for injecting into the principal feedback loop a relatively low-level synchronously detectable signal at a frequency near the controllable bandwidth of the principal feedback signal, means for synchronously detecting the injected signal to produce a variable DC signal indicating magnitude and direction of the movement of the pole P J , and means for comparing the variable DC signal with a fixed DC reference signal for developing a compensating error signal. The feedback compensating means comprises programmed means responsive to the compensating error signal to control a variable zero Z V  in an inverting feedforward network of an operational amplifier. In the preferred embodiment, the operational amplifier is a differential amplifier with an inverting output and controlled frequency response and gain characteristics. The differential amplifier receives as an input the principal feedback control signal mixed with a principal command signal to produce a principal error signal, and the programmed means comprises voltage controlled resistors or switchable resistors in a network programmed to change the time constant and gain of the operational amplifier at the frequency of the injected signal. In an alternative embodiment, the feedback compensation means comprises programmed means responsive to the compensating error signal as for example generated by a digital zero-algorithm in a computer and signal path located following a digital differencing up-down counter provided for feedback subtraction from a command input. 
     By means of this method and apparatus, the total loop gain, bandwidth, and phase margin of the principal feedback control loop, as well as all other feedback control loops subsequently placed in the system may be stabilized, or regulated, despite variations in the gain and frequency response of the controlled element or load, thus providing controlled loop gain-bandwidth-phase margin regulation over the design-allowable frequency range of the variable load pole P J , as described hereinbelow. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows in three parts A, B and C three log-magnitude versus log-frequency plots of closed-loop gain versus changes in the independently-variable loop inertia pole, P J  from its nominal value (Part A), to half the nominal frequency (Part B), and to twice the nominal frequency (Part C). (For clarity, the higher-frequency poles, i.e., higher than the bandwidth F BW   MAX , are not shown). 
     FIG. 2 is a block diagram of a typical prior art velocity motion control system. 
     FIG. 3 is a block diagram of a velocity motion control system in accordance with one digital embodiment of the invention. 
     FIG. 4 is a block diagram of a velocity motion control system in accordance with one analog embodiment of the invention. 
     FIG. 5 is a partial detailing of the control of an exemplary programming resistor R PRO  as employed in the embodiment of FIG. 3. 
    
    
     REVIEW OF SERVO CONTROL 
     THEORY AND OPERATION 
     Much of the understanding of the invention depends upon a correct understanding of servo control theory and correct and thorough analyses of actual servo control systems. Therefore, in order to provide a uniform basis for understanding the underlying concept of the invention, it is helpful to consider the following tutorial about servo control theory. 
     Following Error, FE. Following Error is used by a number of Computer Numerical Control devices (CNCs) to command and regulate Axis Speed. In the simpler static case. 
     
         FE=Speed×(2π×Bandwidth).sup.-1, 
    
     where FE is in Counts, if Speed is in Counts per second. This relationship is important for two totally different reasons: 
     (1) For Axis Speed based on FE, any change in Bandwidth causes a Commanded Speed error; and 
     (2) Should the capacity of a digital Counts Register for the FE be relatively low, then if the Count capacity is exceeded, either by excess Commanded Speed or by too-low Bandwidth or both, then a CNC Fault Condition will result, ending Axis control and operation, even though no true &#34;fault&#34; as such exists. 
     Poles and Zeros. 
     Definitions: 
     Pole-a discontinuity (a point of infinity) in a complex frequency plane manifest by a break frequency in a frequency-amplitude diagram where the asymptote of the signal transmission response toward higher frequency decreases by 6 dB per octave relative to a symptotes of the signal transmission response below the break point. 
     Zero-a null (a point of zero) in a complex frequency plane manifest by a break frequency in a frequency-amplitude diagram where the asymptote of the signal transmission response toward higher frequency increases by 6 dB per octave relative to asymptotes of the signal transmission response below the break point. 
     An example of the coding used for poles is as follows: ##EQU1## An example of the coding used for zeros is as follows: ##EQU2## For example, the signal characteristic in magnitude and phase, T(f) at 5 Hz of a network having two poles and one zero is as follows: ##EQU3## at -19.690° phase, where zero magnitude(s) multiply and pole magnitudes divide, and zero phase(s) add(s) and pole phase(s) subtract(s). 
     A 45-plus pole-and-zero equation can, therefore, be easily evaluated for both magnitude and phase at any given frequency. Arranging poles and zeros in equations from left to right shown in &lt;Z Y  &gt; and &lt;P X  &gt; form from lowest-to-highest frequencies, as shown above, allows convenient assessment of a servo system. 
     Frequency Domain to Time Domain Conversion. Since it is much easier to design closed-loop systems in the frequency domain, yet far easier to proof-test both hardware and software in the time domain, the following two headings rigorously &#34;connect&#34; frequency and time domains so that performance design predictions can be precisely made and then precisely test-confirmed. 
     (1) For a Step-Command Input (or square-wave), closed-loop: ##EQU4## where rise/fall time is measured from 10% to 90% levels and where the electrical EE terms and mechanical ME terms are much less than the closed-loop C-L term in the following more precise equation: ##EQU5## where the maximum acceleration attainable is: 
     
         acc.sub.max =(K.sub.To I.sub.max -[T.sub.F +T.sub.load ]-K.sub.D W)·(J.sub.R +J.sub.load).sup.-1 
    
     where these terms are defined hereinbelow. 
     (2) For a step-command input (or square-wave), closed-loop, the governing phase margin and damping ratio directly relate to the step-response overshoot, SRO, of the C-L output according to the following TABLE I: 
     
                       TABLE I                                                     
______________________________________                                    
(o)              (X)            (%)                                       
Phase     vs     Damping    &amp;   Step-Response                             
Margin           Ratio          Overshoot                                 
______________________________________                                    
+45              0.4204         23.32                                     
50               .4777          18.12                                     
54               .5276          14.21                                     
58               .5825          10.53                                     
62               .6443          7.088                                     
66               .7162          3.979                                     
70               .8034          1.443                                     
72               .8554          0.558                                     
+74              0.9155         0.079                                     
______________________________________                                    
 
    
     Commentary on (1) and (2) above. 
     Statements (1) and (2) are exactly correct for first- and second-order closed-loop systems only. However, every closed-loop system showing step-response overshoot of less than about 18% behaves like a second-order system--even if it contains 45 or more poles and zeros. Therefore, the closed-loop bandwidth, and the regulation thereof according to the invention, can always be easily checked by measuring the rise-times and fall-times of the closed-loop output in response to an appropriate input square wave drive. Test of the step-response overshoot, SRO, checks the phase margin of the closed loop. 
     Loop stabilization versus loop type and number of loops: 
     Single feedback control loops. 
     Two poles and one zero &lt;P V  &gt;, &lt;Z V  &gt;, and &lt;P FO  &gt;, are illustrated below. This system can be implemented in either hardware or software. In lower-performance loops or where &lt;P J  &gt; is much lower in frequency than the nominal loop bandwidth F BW , then the pole &lt;P V  &gt; and the zero &lt;Z V  &gt; are sometimes omitted. 
     The &#34;type&#34; number of a control loop, which is zero, 1 or 2, is also the exponent of the Laplacian operator s, where 
     
         s=jw or j2πf. 
    
     The operator s is a part of the denominator of the non-frequency-dependent gain term. It is also a multiplier of minus ninety degrees, which deducts directly from phase margin. 
     a. For Type Zero control loops (such as a velocity loop, FIGS. 1 and 2), the gain GH VEL  is given by: ##EQU6## where, for &lt;Z V  &gt;=&lt;P J  &gt;, 
     
         F.sub.BW.sup.VEL ≈(Kdc.sub.o)×(P.sub.v), 
    
     where F BW   VEL  ≦(P EE  or P FO )/2, 
      such that: 
     
         PhaseMargin.sub.VEL =180°-90°·&lt;0&gt;-a tan (F.sub.BW /P.sub.V)-SUM(a tan (F.sub.BW /P.sub.X)). 
    
     Usually PhaseMargin VEL  ≧+58°, 
     and, therefore, 
     usually Overshoot≦10.5%. 
     In real systems of Type Zero, the term &lt;P EE  &gt; is an electrical pole; the term &lt;P FO  &gt; is the dominant loop filter pole; the term &lt;P DR  &gt; is the pole determining the power amplifier loop bandwidth, F BW   PA  ; and &lt;P HI  &gt; is the hardware-high-frequency pole, which is the gain-bandwidth of the amplifier divided by the high-frequency gain. 
     The Type Zero loop is a very easy loop to stabilize and very easy to obtain relatively high performance. 
     (b) Type 1 (such as a typical actuator-driven motion control position loop): ##EQU7## where, for &lt;Z V  &gt;=&lt;P J  &gt;, ##EQU8## so 
     
         PhaseMargin.sup.POS =180°-90°(1)-a tan (F.sub.BW /P.sub.V)+a tan(F.sub.BW /Z.sub.C)-SUMa tan (F.sub.BW /P.sub.X), 
    
     usually PhaseMargin POS ≧+58°, 
     and, therefore, Overshoot is usually ≦10.5%. 
     The term &lt;Z C  &gt; is an added loop-compensation zero (hardware or software) and the term &lt;P C  &gt; is the required high-frequency pole of &lt;Z C  &gt;, which is required for hardware and usually software implementation). (Other high-frequency poles are as in a Type Zero system above.) 
     The Type 1 loop usually requires considerable care to stabilize, especially to obtain relatively high performance (i.e., high bandwidth, high phase margin and low overshoot), since it has lost 90° of operating phase margin relative to Type 0 Loops prior to adding phase compensation, &lt;Z C  &gt;. 
     (c) Type 2 (such as closely-approximated by a very high inertia load antenna positioning drive, where the high inertia pole &lt;P J  &gt; goes to near zero, i.e., to μHz): ##EQU9## where &lt;P V  &gt; and &lt;Z V  &gt; ARE NOT ALLOWED at frequencies greater than P J , or limit-cycling will occur after a drive command goes to zero in a system without dithering; however such terms are allowed with dithering, such as used in accordance with the invention). 
     One of the conditions of proper operation is that the bandwidth should be four times removed from the zero &lt;Z C  &gt; and four times removed from the nearest pole &lt;P EE  &gt;, &lt;P FO  &gt; or &lt;P C  &gt;, that is: 
     
         (4X)&lt;Z.sub.C &gt;≦F.sub.BW.sup.POS.sub.(ACCEL) ≦(P.sub.EE,P.sub.FO, or P.sub.C)/4X. 
    
     Thus, 
     
         PhaseMargin.sup.POS.sub.(ACCEL) =180°-90°(2)+a tan (F.sub.BW /Z.sub.C -SUMa tan (F.sub.BW /P.sub.X) 
    
     Usually, PhaseMargin POS .sub.(ACCEL) ≦+58°, and, therefore, overshoot is usually ≦10.5% and &lt;Z C  &gt; and &lt;P C  &gt; are the same as in a Type 1 system as shown above. 
     The Type 2 loop requires the most care of any loop to stabilize, especially to obtain relatively high performance, since it has lost all 180° of operating phase margin relative to a comparable Type Zero loop prior to adding phase compensation, &lt;Z C  &gt;. The invention as disclosed hereinbelow is nevertheless still operative under conditions of changing load inertia. 
     Referring now to FIG. 2, there is shown a block diagram of a typical prior art velocity motion control system 10 with sample values. A conventional inverting input high gain differential amplifier 8 operative as an error sensing operational amplifier is provided with a feedforward network 50 to introduce a variable zero &lt;Z V  &gt; and a dominant fixed pole &lt;P V  &gt; in an error amplifier subsystem 21 formed by a forward impedance scaling element (R FWD ) 13, a variable impedance scaling element (R L ) 12, and a capacitor 11. The capacitor 11 in conjunction with the impedance scaling element 12 is for incrementally setting the variable zero &lt;Z V  &gt;. The capacitor 11, together with the very high impedance resistance R FWD  13 introduces the required constant low frequency pole &lt;P V  &gt;. The output of the amplifier subsystem 21 is coupled to a power amplifier 6 which in turn is coupled to an actuator 2, or motion controller, which in turn is coupled to drive a load 4 and a velocity sensor 18. The velocity sensor 18 is in a feedback loop and is coupled to a feedback scaling element 16 which in turn is coupled to a zero-seeking summing junction 17 or its equivalent. The summing junction 17 is also coupled to receive a control signal E C  attenuated by a drive scaling element (R C ) 14. The forward impedance of the error amplifier 19 comprises the combination of the effects of forward impedance scaling element 13 in parallel with series-coupled zero-setting scaling element 12 and integrator 11. In an analog hardware implementation, the scaling elements 12, 13, 14 and 16 are fixed resistances. In a digitally implemented realization or in software, the scaling elements may be counters or division functions (all of which are conventional). 
     The error amplifier 8 provides a high frequency pole P HI , the dominant pole P V  and the compensating zero Z V . The complete transfer function of the error amplifier 8 with its associated feedback elements 11, 12, 13, and 14 in a conventional hardware implementation as referenced to the input command E C  is given by: ##EQU10## As an example: ##EQU11## In an example where the feedback scaling element R V  16 is set equal to the drive scaling element R C  14, then: 
     
         V.sub.E /E.sub.VEL =V.sub.E /E.sub.C. 
    
     If in an analog hardware implementation, the forward impedance scaling element 13 is very much greater in value than the zero-setting scaling element 12, that is 
     
         R.sub.FWD.sup.D &gt;&gt;R.sub.L.sup.MAX ; 
    
     if the fixed dominant pole P V  is set to a defined value which is equal to the bandwidth divided by the DC loop gain GH DC , that is, 
     
         P.sub.V =F.sub.BW /GH.sub.DC =(2π×R.sub.FWD.sup.D ×C1).sup.-1 ; 
    
     and if the correction zero Z V  is set to another defined value which is equal to the nominal inertia pole P J , that is, 
     
         Z.sub.V =P.sub.J =(2π×R.sub.L ×C1).sup.&lt;1 ; 
    
     then the high frequency pole P HI  is simply the gain-bandwidth of the differential amplifier 8 divided by the high-frequency gain of the feedback transfer function, V E  /E VEL , that is: 
     
         P.sub.HI =(Open-Loop Gain×BW)/{(R.sub.FWD.sup.D /R.sub.V)(P.sub.V /Z.sub.V){, 
    
     since V E  /E VEL  =(R FWD   D  /R V )(P V  /Z V ). The value of the zero-setting scaling element R L  will be significant in the embodiments according to the invention, as explained hereinafter. 
     The power amplifier 6 usually comprises a subsystem providing at least two poles within its operational bandwidth, namely, the electrical pole P EE  associated with loop inductance and resistance, and the drive pole P DR  associated with the bandwidth of the power amplifier (which usually is quite high relative to the bandwidth of interest). In this example, the power amplifier is a supplier of current output I A  in response to an input voltage V E  and thus has a transfer function as follows, with exemplary values: ##EQU12## 
     The constant C1 is a multiplying constant, a function of the type of power amplifier 6 and actuator 2 employed. 
     The pole &lt;P DR  &gt; is the pole at the zero dB response of the control loop of the power amplifier. 
     The constant K I  is the voltage to current conversion constant of the power amplifier 6. 
     The actuator 2 in the present example may be a current to motion converter, such as a rotary or linear motor or a thruster, driven by AC power, DC power or fluidic power. The generalized transfer function of the actuator 2 with a specific example is given by: ##EQU13## where: ω in this example is output rotary speed in rad/s (varying between zero and ±2π, ω=S·θ); 
     I A  is the drive current of the actuator 2, in Amperes; 
     K TO  is the torque constant of the actuator 2, in lb-ft/A; 
     K D  is the viscous torque constant of the actuator 2, in lb-ft/rad/s; 
     the mechanical pole &lt;P J  &gt;, with the terms used in the example, has a nominal value of 84.1 milliHz and is given by the expression: ##EQU14## where: C2 is a multiplying constant, a function of the power amplifier and actuator employed; 
     J rotor  is the inertia of the actuator 2, in lb-ft-s 2 , which in this example is 0.738; 
     J load  is the inertia of the load 4 as coupled directly to the moving element of the actuator, in lb-ft-s 2 , which in this example is 6.64 NOM  (as hereinafter explained the pole must be compensated for according to the invention); and 
     where ε is the torque-loading &#34;stiction&#34; ratio given by the expression: ##EQU15## where T friction  is the friction torque in lb-ft, which in this example is 5.4 lb-ft. 
     The value of ε varies between zero and 0.003 in this example. 
     The load 4 is manifest in two terms, T load , torque in lb-ft, which in this example is zero, and J load , inertia in lb-ft-s 2 , which is nominally 6.64. 
     The velocity sensor 18 provides an output voltage in response to input motion. In the example here, the motion is rotary and is given by the expression: ##EQU16## where: K Ta  is the speed-to-voltage conversion constant of the sensor 18; and 
     &lt;P FO  &gt; is the pole of a lowpass filter to suppress out-of-band noise, spikes and undesired pickup on the output voltage signal of the sensor 18. 
     Therefore in summary, the plant transmission of the elements 6, 2 and 18, i.e., E VEL  /V E , is given by: ##EQU17## 
     Finally, the loop gain equation for the feedback loop of FIG. 2, with sample values, is given by: ##EQU18## For the sample values given, ##EQU19## 
     A system designed in the frequency domain with the following values: 
     F BW   VEL  =36.47 Hz NOM  at PhaseMargin=+57.864° NOM . will exhibit the following respective parameters in the time domain: 
     
         T.sup.Rise.sub.Fall =9.60 msec.sub.NOM ; 
    
     Step response overshoot or SRO=10.65%. 
     DESCRIPTION OF SPECIFIC EMBODIMENTS 
     Referring to FIGS. 3 and 5 there are shown implementations of a first preferred embodiment according to the invention. 
     Referring now to FIG. 3, there is shown a block diagram of a velocity motion control system 100. A conventional inverting input high gain differential amplifier 8 operative as an automatically compensating error amplifier 21&#39; is coupled to power amplifier 6 which in turn is coupled to actuator 2, or motion controller, which in turn is coupled to drive load 4 and velocity sensor 18. The velocity sensor 18 is in a feedback loop and is coupled to a feedback scaling element 16 which in turn is coupled to a zero-seeking summing junction 17 or its equivalent. The summing junction 17 is also coupled to receive a control signal E C  attenuated by a drive scaling element (R C ) 14. The forward impedance of the error amplifier 21 comprises the combined effects of a forward impedance scaling element (R FWD ) 13 in parallel with a series-coupled controlled zero-setting scaling element (R PRO ) 12&#39; and integrator (C1) 11. In an analog hardware implementation, the scaling elements 12&#39;, 13, 14 and 16 are fixed resistances. In a digitally implemented realization or in software, the scaling elements may be counters or division functions. 
     The error amplifier 21&#39; elements provide a high frequency pole P HI , a fixed dominant pole P V  and the compensating zero Z V . The differential amplifier 8, which is typically a high-gain operational amplifier, is operative to invert input signals applied at an input summing means 17 whose output is provided to the input of the differential amplifier 8. 
     According to the invention, the differential amplifier 8 is provided with a controlled element 50 operative to produce an automatic frequency-tracking (and gain-tracking) zero &lt;Z V  &gt; and a fixed dominant low-frequency pole &lt;P V  &gt;. The transfer function in the principal feedback control loop of the differential amplifier 8, ignoring command and compensation inputs, is given by: ##EQU20## 
     Command signals are applied to the control system 100 at a command input 110 in the form of a (voltage) control signal E C  through first scaling element (resistor R C ) 14 to the summing means 17. According to the invention, a synchronously-detectable signal E SD  is injected via second scaling element (R SD ) to the summing junction 17 at a signal level which is relatively low compared to other signals at the summing junction and at a set frequency near the preset closed-loop bandwidth of the principal feedback control loop. 
     The power amplifier 6, the actuator 2, the load 4 and the velocity sensor 18 have the characteristics and transfer functions as described hereinabove and therefore no further explanation is necessary. 
     According to the invention, there is provided a controlling feedback control loop comprising a regulated oscillator 20 for generating a synchronously detectable signal E SD  at a frequency F SD , which signal is coupled to a fixed phase shifter 26 as well as to a signal scaling element (R SD ) 24 (via a first optional voltage blocking capacitor (C BLK1 ) 22). The output signal of the fixed phase shifter 26, designated E1, is coupled to one signal input 30B of a synchronous detector (with an output lowpass filter) 30. The output of the velocity sensor 18, namely, signal E VEL  (without regard to linear scaling) is also coupled (via an optional second blocking capacitor (C BLK2 ) 28) to a second signal input 30B of the synchronous detector 30. The synchronous detector 30 is operative to provide as an output signal a varying DC voltage E2 whose level is proportional to the degree of phase synchronism between the signals applied at the inputs 30A and 30B and the combined magnitude of the signals, which is a function of the value of R PRO  and &lt;P J  &gt;. 
     The varying DC voltage E2 is provided to one input 32A of a level shifter and low-frequency gain amplifier 32. A reference DC voltage E REF  is provided to amplifier 32 at a second input 32B. Amplifier 32 shifts and scales the varying DC voltage E2 relative to E REF  to condition it as a signal E4 to drive an analog to digital converter (ADC) 34. The ADC 34 is for example an eight-bit analog voltage to digital octal-value converter whose output is applied to an eight-conductor bus 35. The ADC 34 produces a correction signal ranging from zero (at E4 equal to zero volts) to 2 N  (where N is the digital resolution) at for example E4 equal to ten volts. The signal on bus 35 is provided to the programmed scaling element 12&#39;, which is preferably a switched resistor network of the type shown in FIG. 5. 
     Referring to FIG. 5, a switched resistor ladder 12&#39; is shown. It comprises a plurality of resistors R1,R2,R3, . . . RN having one terminal coupled in common to an output port 114 (which is coupled to the input of amplifier 8 of FIG. 2 or 3), and the other terminal of each resistor R1, . . . RN coupled to one terminal of respective single-pole switches S1,S2,S3, . . . SN. The other terminal of each of the switches S1,S2,S3, . . . SN is coupled to a common node 116, which in turn is coupled to the integrator (C1) 11. The values of the resistors are programmed so that the combined parallel combination at each binary switch setting adjusts the zero &lt;Z V  &gt; to track the mechanical pole &lt;P J  &gt;, thereby cancelling the frequency response effects of that pole over substantially the entire useful operating range of the control system. The values for an exemplary system are given below. 
     Referring to FIG. 4, there is shown an alternative embodiment 100&#39; of the control system of FIG. 3. All of the elements are substantially identical, except as follows: In the control system 100&#39;, the output voltage E4 of the gain amplifier 32 is provided directly to the controlled element 12&#34;, which in this embodiment is an analog voltage controlled resistance means (VCR) 12&#34;. A simple example is a high-input-impedance field effect transistor (FET) controlled by a voltage signal at its gate terminal G. A conventional bias network (not shown) may be provided to the FET to assure operation in its nonsaturating operating range. 
     By thus controlling the zero &lt;Z V  &gt; in the error amplifier 21&#34;, the controlled-feedback control loop of interest has essentially a constant loop bandwidth and phase margin. 
     The desired ideal loop response and pole/zero placement in accordance with the invention are shown in FIG. 1, Part A. The zero Z V  is placed directly in line with the pole P J  in reference to the frequency. As the pole moves, the zero is moved under system control to track the frequency of the pole. 
     The embodiments shown in FIGS. 3 and 4 provide to the internal or controlling-feedback control loop including the velocity sensor 18 essentially a constant loop gain and bandwidth. This, in turn, provides to the controlled-feedback control loop of interest, including the synchronous detector 30 a constant static and dynamic response over the entire design frequency range of operation of the independently variable pole P J . 
     In a system according to the invention, there are just three specifics: 
     (1) Regulation of the partly digital implementation (accounting for digital resolution): Given the implementation of the invention in accordance with the structure of FIGS. 3 and 5, and for easily-obtained GH VEL   DC  ≧50,000 in the circuit of FIG. 2 and GH SD   DC  ≧1000 in the circuit of FIG. 3, then the velocity bandwidth, F BW , will be held at F BW   NOM , within ±E%, for a design-accommodating Max-to-Min ratio R in P J , (FIG. 1) of 
     
         R=(1+E/100).sup.2N, 
    
     where N is the number of correction bits used. The various resolutions are set forth in the following table, designated TABLE II: 
     
                       TABLE II                                                    
______________________________________                                    
       ± E% Velocity Bandwidth Regulation                              
R     vs     8-BITs  10-BITs                                              
                            12-BITs                                       
                                   14-BITs                                
                                          16-BITs                         
______________________________________                                    
 2            4.427   3.527  2.930  2.506  2.190                          
 5           10.58    8.380  6.936  5.916  5.158                          
 7           12.93   10.22   8.446  7.197  6.270                          
 10          15.48   12.20  10.07   8.571  7.461                          
 14          17.93   14.11  11.62   9.884  8.597                          
 20          20.59   16.16  13.30  11.29   9.814                          
 50          27.70   21.60  17.70  15.00  13.00                           
100          33.35   25.89  21.15  17.88  15.48                           
200          39.26   30.33  24.70  20.83  18.01                           
Regulation factor:                                                        
@ 2          31.95X  40.10X 48.27X 56.43X 64.58X                          
@ 20         21.72X  27.67X 33.63X 39.61X 45.57X                          
@ 200        36.02X  46.63X 57.26X 67.89X 78.52X                          
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     (2) Proximity of the carrier at the synchronously detectable frequency F SD  to the loop bandwidth F BW  : 
     The choice of frequency F SD  is a compromise relative to the bandwidth F BW  of the controlled loop. 
     (a) The frequency of the synchronously detectable carrier signal should be high to minimize the rejection factor (1+[F BW  /F SD  ] 2 ) 0 .5 of the signal of the controlled loop, and the operation of the controlling loop should be maximized by maintaining the ratio of bandwidths of F SD  -to-controlling loop at greater than about five times. 
     (b) The frequency of the synchronously detectable carrier signal should be low, as low as ten times the maximum frequency of the pole, P J   MAX , to minimize required synchronous detection drive signal at V E  to less than about 25% of V E   MAX  at P J   MIN  operation. 
     (c) The frequency of the synchronously detectable carrier signal should be close to F BW  so that its regulation effects by the second, controlling, loop effectively transfer to the controlled loop of interest related to F BW . 
     A good compromise usually is to set F SD  equal to 75% to 95% of the setting of F BW  for the controlled loop. 
     In summary, the bandwidth of the controlled loop F BW  is effectively frequency-regulated by proximity-transfer of actual voltage-regulation of E VEL  at the frequency F SD  of the synchronously detectable signal E SD . Regulation depends upon causing the &#34;tracking zero&#34; Z V  to follow the variable pole, P J . Similarly the controlled loop bandwidth F BW  depends upon the same &#34;tracking zero&#34; Z V . 
     (3) Frequency Domain Boundary Conditions. 
     For the above pole-tracking concept to operate without further compensation, the following conditions should be fully met: 
     (a) P J   max  =Z V   max  to be ≦10% of F SD  or F BW  of controlled loop, whichever is lower in frequency. 
     (b) P J   min  =Z V   min  to be ≧10 times the frequency of P V , which is equal to F BW  /GH DC . 
     (c) In the frequency range from the frequency of P V  to approximately 1.5 times the bandwidth F BW  of the controlled loop, no poles or zeros other than P J  and Z V  are allowed. 
     These three conditions are usually easy to meet. 
     Referring now to FIG. 4, the regulated oscillator 20 is shown. The regulated oscillator 20 provides the signal +E SD  at the frequency F SD  within about ±0.5% regulation from nominal of both its frequency and output signal level. Elements 22 and 28 are each blocking capacitors whose reactance is very much less than the resistance of R SD  24 at the frequency F SD . Element 24 is an input scaling resistor R SD  to differential amplifier 8. In a specific embodiment R SD  (at f=F SD ) may be set to: ##EQU21## 
     Element 26 is a phase shifter. This element matches its output E1 in phase to E VEL  at F SD . 
     Element 30 is a synchronous detector and lowpass filter. Besides providing a DC gain of about 100 times, so that operating output E2 is made equal to E REF , this element is for providing conventional synchronous detection of inputs 30A and 30B at F SD  as well as for creating a dominant pole P o  of the controlling loop. The controlling loop has a bandwidth F BW  =GH SD   DC  (2X P o ). Therefore, the block transfer function: ##EQU22## 
     The element 32 is a differential level shifter and low-frequency gain element. This block compares input E2 to E REF  at for example +1.00 V. E REF  then provides sufficient gain to bring synchronous detection loop gain GH SD  to approximately 10,000 times at DC. It also incorporates a DC level-shift so that its output E4 is always positive, as required by the load. The block transfer function is given by: 
     E4/(E REF+E2 )=-K LS  /&lt;P HI   SD  &gt;=(-19.49KX/&lt;12.5 Hz&gt;) 
     Element 34 is an N-bit linear-input analog-to-digital converter. This element provides an output conversion X versus linear-input voltage E4 as follows: 
     
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BIT #                                                                     
vs-              E4, volts                                                
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1                0                                                        
X                +10(X - 1)(N - 1).sup.-1, 1 ≦ X ≦ N        
(N = 12)         (+0.9091(X - 1)), (1 ≦ X ≦ 12)             
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     In order to understand the function of the several functions of the element 12&#34;, it necessary to first consider the loop gain GH SD  of the controlling loop. The closed-loop gain GH SD  of the controlling loop is given by: ##EQU23## where: G r/v  is the incremental change in resistance of element 12&#34;, given as dR PRO , divided by the incremental change in error drive voltage of element 32, given by dE4. 
     Using exemplary values at G r/v  X P J  equaling 5.739 kΩ X Hz/Volts: ##EQU24## so the controlling loop bandwidth BW SD  is 2X(GH SD   DC )(P o ) or 4.90 Hz, and the phase margin is equal to +76.68 degrees; 
     which leads to a rise time of 71.4 msec and an overshoot SRO of zero percent, based on the calculations of TABLE I, hereinabove. 
     Element 12&#34; is a programmable/controlled resistor. This element is the controlled element of this invention. It does the following: 
     (1) provides pole-tracking zero &lt;Z V  &gt; (together with C1 11) versus load-caused variable pole &lt;P J  &gt;. This renders the open-loop operation illustrated in FIG. 1 Part B and FIG. 1 Part C to a closed-loop operation with a characteristic as shown in FIG. 1 Part A. 
     (2) provides constant E VEL  at F SD  when &lt;Z V  &gt;=&lt;P J  &gt;, thereby providing constant bandwidth F BW  and phase margin, as illustrated in FIG. 1 Part A, by voltage regulation on the controlling feedback control loop. 
     (3) provides constant DC gain for controlling the gain GH SD  of the feedback control loop, since the incremental product of the transfer functions of the elements 34, 12 and 2 is a constant, where these three terms are the only variables of consequence in GH SD . In other words: 
     
         V.sub.E.sup.SD /E4=(G.sub.r/v)(P.sub.J /F.sub.SD)(E.sub.SD /R.sub.SD)→constant, 
    
     Since R PRO  X P J  is constant at each bit, and dE4, incrementally from bit to bit, is also constant, the value (dR PRO  /dE4)×P J  is constant. This observation is especially true as the number of bits increases. 
     (4) is consistent with the easily-met frequency-domain boundary conditions of the pole-tracking concept, listed above, and the condition producing the constant transfer function V E   SD  /E4 for function (3) immediately above. R PRO , in context with its position in-loop and other explained parameters, provides constant static and dynamic performance of the controlling closed, which provides the desired dynamic parameter maintenance. 
     The values for R PRO  are given in accordance with the following relationship: 
     
         R.sub.PRO =(1+E/100).sup.2X-1 /(2πXP.sub.J.sup.max XCl) 
    
     where 
     
         P.sub.J =P.sub.J.sup.max /(1+E/100).sup.2X-1 
    
     and X is the specific bit number from 1 to N and N is the number of correction bits. 
     In a specific embodiment, P J   max  =841 mHz; N=12 and the range of P J  is selected to be 100X, so E=42.51% and C1=11.73 uF. For 1≦N≦12, R PRO  =13.568 kΩ X Hz/P J . The following TABLE III illustrates the choice of resistors for a twelve bit A/D converter and a 100 to 1 design range of the pole P J  : 
     
                       TABLE III                                                   
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Bit         vs.     (kΩ)                                            
                              (milliHz)                                   
@ BIT N             R.sub.PRO P.sub.J                                     
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1                   19.55     694.2                                       
2                   28.69     473.0                                       
3                   42.11     322.2                                       
4                   61.80     219.5                                       
5                   90.71     149.6                                       
6                   133.1     101.9                                       
7                   195.4     69.44                                       
8                   286.8     47.31                                       
9                   420.9     32.23                                       
10                  617.8     21.96                                       
11                  906.8     14.96                                       
12                  1,331     10.19                                       
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     It has been found that regulating the output of the controlling loop E VEL   SD  to within 0.01% of its 10 mV nominal value according to the invention provides cross regulation of the controlled loop to within the error calculated from designs using TABLE II such that the bandwidth of the controlled loop F BW   VEL  is regulated within the percentage given in TABLE II of its nominal value of 36.47 Hz used in the example of the above specific embodiment of FIG. 3. 
     The embodiment shown in FIG. 4 is substantially identical to the embodiment shown in FIG. 3 with the deletion of the analog to digital converter 34. The programming resistor R PRO  12 has been changed from a digitized resistor matrix, as shown in FIG. 5, to an analog-type truly hyperbolic resistance, such as a voltage-controlled resistor or a FET (Field Effect Transistor) having a voltage vs. resistance characteristic appropiate to the application. The value R PRO   Analog  ×P J  =(2π×C1) -1 , as before, is designed to be a constant. This hyperbolic resistance is the equivalent of allowing the number of bits of resolution N-BITS in the digital example of FIG. 3 go to infinity: The elimination of granularity has the immediate effect of closing the error gap, E%, of the digital approximation of finite segment-slopes fitted to the hyperbolic curve required of R PRO  (TABLE II), so that regulation can be enhanced by more than two orders of magnitude in Bandwidth Regulation. 
     The transfer response of G r/v  is identical for both the embodiment of FIG. 3 and the embodiment of FIG. 4, as are the GH and System Equations. 
     In summary, the invention has some of the following advantages: 
     The controlled feedback control loop of interest has its bandwidth F BW  and its phase margin Om held essentially constant for large variations in the load-caused mechanical pole P J  by a second controlling feedback control loop (with loop-gain GH SD ) sharing common pole tracking and providing regulation of the controlled loop bandwidth F BW   VEL  and controlled loop phase margin Om VEL  via the close proximity of the synchronously detectable frequency F SD  to the controlled loop bandwidth F BW   VEL  where E VEL   SD  is closely regulated by the second, controlling, loop. This is true since: 
     A. The DC loop gain GH VEL   DC  of the controlled loop is fixed. 
     B. The dominant pole &lt;P V  &gt; of the controlled loop is fixed. 
     C. The frequency domain boundary conditions are easy to meet. 
     Although a Type 0 (Velocity) loop has been shown in FIG. 1 and discussed throughout this disclosure, the concept of regulation of bandwidth and of phase margin is equally valid for Type 1 (Position) and Type 2 (Acceleration) loops. Moreover, if the controlled loop according to the invention is stabilized, all loops added around the stabilized loop will also be stabilized. A stabilization scheme according to the invention simplifies outer-loop design and operation, since all outer loops &#34;see&#34; an essentially fixed mechanical pole, &lt;P J  &gt;. Of crucial importance for multi-loop systems, the pole-tracking zero Z V  is in the common path with tracked variable pole P J . 
     The foregoing description of illustrative embodiments of the method and apparatus of this invention is intended to be illustrative only of the principles of the invention and not to be limitative thereof, especially in view of the applicability of the invention to numerous types of control systems unrelated to motion control, such as lasers, meteorology, power conditioning and the like. Accordingly, since numerous variations of the methodology and apparatus of this invention, within the scope of the invention, will readily become apparent to those skilled in the art, the scope of this invention is limited, not by the foregoing description, but solely by the claims appended hereto.