Method of producing a Schottky gate field effect transistor
FIELD OF THE INVENTION 
     The present invention relates to a method of producing a Schottky gate field effect transistor (MESFET), and more particularly to a method capable of producing a self-aligning gate electrode with high impurity concentration source and drain regions. 
     BACKGROUND OF THE INVENTION 
     A prior art method of producing a GasAs MESFET is disclosed in Japanese Laid-open Patent Publication No. 60-120574. FIGS. 2(a) to (g) show cross-sectional views of gate electrode production flow of such a method. 
     In FIG. 2, reference numeral 1 designates a semi-insulating GaAs substrate. An n type GaAs layer 2 is formed in and at a surface of the semi-insulating GaAs substrate 1, for example, by as ion implantation. An SiO 2  pattern 3 is formed at a gate electrode production region on the n type GaAs layer 2. N +  regions 4 are formed in the semi-insulating GaAs substrate 1 by ion implantation. A photoresist 6 is disposed on the entire surface of the substrate bearing the SiO 2  pattern 3. The SiO 2  pattern 3 is removed to expose region 2 and separate the photoresist into two regions. A metal 8 and 8a is disposed on and between the photoresist regions. The metal 8 forms a Schottky junction with the n type GaAs layer 2. Reference numeral 9 designates a gate electrode that is left when the excess metal 8 is removed by a lift-off technique. 
     The production flow will be described. 
     First of all, n type GaAs layer 2 is produced in a surface region of semi-insulating GaAs substrate 1, for example, by as ion implantation, and SiO 2  pattern 3 is deposited at the gate electrode production region on the n type GaAs layer 2 (FIG. 2(a)). Next, N +  regions 4 are produced in the semi-insulating GaAs substrate 1 by ion implantation, and are activated by annealing (FIG. 2(b)). Next, photoresist 6 is applied on the entire surface of the substrate bearing the SiO 2  pattern 3, to such a thickness that the surface thereof becomes flat (FIG. 2(c)). The photoresist 6 is etched, for example, by reactive ion etching, to gradually thin the photoresist 6 until the top portion of the SiO 2  pattern 3 is exposed (FIG. 2(d)). Thereafter, the SiO 2  pattern 3 is etched and removed using hydrofluoric acid or the like (FIG. 2(e)). Next, a metal which can form a Schottky junction with the n type GaAs layer 2 such as aluminum, or titanium series metal is deposited over the entire surface of the substrate (FIG. 2( f)). Then, the metal 8a lying outside the gate electrode production region is lifted off, together with the photoresist 6, by an organic solvent such as acetone, thereby producing the gate electrode 9 (FIG. 2(g)). Thus, the gate electrode 9 is produced self-aligned with the n +  regions 4. 
     In this prior art MESFET, the photoresist 6 is used both in producing the gate electrode 9 and in making the surface thereof flat. The photoresist 6 is apt to deteriorate at the reactive etching step, thereby resulting in difficulty in its removal in the final lift-off process. Furthermore, since the shapes of internal surfaces of the photoresist 6 are uniquely determined by SiO 2  pattern 3, wing-like tips are likely to occur at the both side surfaces of the gate electrode 9 during its production. Furthermore, since the gate electrode 9 is rectangular, no means is available for suppressing the gate resistance such as shortening the gate length. Furthermore, since the top portion of SiO 2  pattern 3 is exposed by thinning the photoresist 6, that SiO 2  exposure is difficult to detect. This means that the margin for process error and process controllability are poor. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a method of producing a self-aligned Schottky gate field effect transistor self-alignment production with a high degree of process controllability. 
     Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
     According to the present invention, since different photoresists are used for the purposes of producing a gate electrode and making the surface thereof flat, the shapes of photoresist side surfaces are easily controlled and the photoresist can be easily removed. The top portion of first thin film pattern can be exposed by removing the whole of the photoresist for making the surface thereof flat. This means that the exposure of top portion of first thin film can be easily detected, resulting in a high degree of process controllability. Furthermore, the cross-section of gate electrode is Y-shaped because the lower portion and the upper portion thereof are determined by the shapes of apertures produced at the second thin film and at the photoresist pattern for producing a gate electrode, respectively. Therefore, gate resistance can be suppressed even when the gate length is shortened. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1(a) to 1(i) are cross-sectional views showing a production method for a MESFET according to an embodiment of the present invention; and 
     FIGS. 2(a) to 2(g) are cross-sectional views showing a production method for a MESFET according to the prior art. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of the present invention will be described with reference to FIG. 1. 
     In FIG. 1, the same reference numerals designate the same elements as those shown in FIG. 2. Reference numeral 5 designates an SiN film, reference numeral 7 designates photoresist for determining the size of upper portion of gate electrode 9, and reference numeral 8 designates a metal comprising such as aluminum, or titanium series metal, which can form a Schottky junction with n type GaAs layer 2. 
     The production method will be described. 
     First of all, n type GaAs layer 2 is formed in a region of semi-insulating GaAs substrate 1 at a surface by, for example, ion implantation, and a first thin film pattern, for example, SiO 2  pattern 3 is deposited at a gate electrode production region on the n type GaAs layer 2 (FIG. 1(a)). Next, n +  regions 4 are formed in the semi-insulating GaAs substrate 1 by ion implantation and are activated by annealing (FIG. 1(b)). Next, a second thin film, for example, SiN film 5, is produced on the entire surface of the substrate having SiO 2  pattern 3 to the same thickness as the SiO 2  pattern 3 (FIG. 1(c)). Thereafter, photoresist 6 is applied on the entire surface of the substrate having SiN film 5 (FIG. 1(d)). Furthermore, photoresist 6 is etched and removed, for example, by reactive ion etching, under conditions such that photoresist 6 has the same etching speed as does SiN film 5 (FIG. 1(3)). Since SiN film 5 has the same thickness as SiO 2  pattern 3 and has the same etching speed as photoresist 6, when the etching end point of photoresist 6 is detected, the top portion of SiO 2  pattern 3 is reliably exposed. Thereafter, SiO 2  pattern 3 is removed by etching with hydrofluoric acid or the like (FIG. 1(f)). Next, photoresist 7 for producing a gate electrode is deposited only on SiN film 5 using conventional photolithography techniques (FIG. 1(g)). Then, a metal (gate metal) which can form a Schottky junction with n type GaAs layer 2 is deposited over the entire surface of the substrate (FIG. 1(h)). Photoresist 7 and the metal 8a thereon are removed with an organic solvent such as acetone, thereby producing a gate electrode 9 (FIG. 1(i)). Since photoresist pattern 7 is not exposed to a plasma or the like and the shapes of internal side surfaces thereof can be controlled by the photolithography processing condition, no wing-like tips produced at the side surfaces of gate electrode 9, i.e., - - - ; where gate electrode 9 contacts with the internal, vertical surfaces of photoresist pattern 7. This process enables easy production of a gate electrode. In this way, a gate electrode 9 can be produced that is self-aligning with n +  regions 4 with a high degree of control. Furthermore, since the cross-section of gate electrode 9 is of Y-shaped, gate resistance can be suppressed even when the gate length is shortened. 
     Wile in the above-illustrated embodiment SiO 2  and SiN are employed as the first and second thin films, respectively, other combinations of materials, for example, SiO 2  and SiON, SiON and SiN, and AlN and SiO 2  or SiON can also be used for the first and second thin films, respectively. Furthermore, while in the above-illustrated embodiment a GaAs series MESFET is described, it will be appreciated that the present invention may also be applied to production methods for MESFETS made of other materials, such as InP or Si. 
     As is evident from the foregoing description, there are provided steps of producing a first thin film pattern at a gate electrode production region on a first conductivity type semiconductor layer which is produced in a surface region of a semiconductor substrate, producing a first conductivity type high impurity concentration regions in the semiconductor substrate by impurity ion implantation, producing a second thin film on the semiconductor substrate having the first film pattern to the same thickness as the first thin film, applying a photoresist on the second thin film such that the surface thereof becomes flat, which has the same etching speed as the second thin film, etching the photoresist until the top portion of the first thin film pattern is exposed, removing the first thin film pattern by etching, producing photoresist patterns on the second thin film to have a larger aperture than that of the second film, and producing a gate electrode which has portions disposed on the second thin film by vapor deposition and lifting off the photoresist patterns. By this method, a self-aligned gate electrode can be produced with high impurity concentration regions with a high degree of control, and the gate resistance can be suppressed even when the gate length is shortened.