Image signal binary circuit with a variable-frequency clock signal generator for driving an image sensor
BACKGROUND OF THE INVENTION 
     The present invention relates to a binary circuit where image signal outputted from an image sensor is converted into a binary signal. 
     In the prior art, binary circuits to obtain an image signal using an image sensor and to convert the image signal into a binary signal have been used in may fields. FIG. 1 is a block diagram illustrating a binary circuit in the prior art. In FIG. 1, numeral 1 designates an image pick-up element for converting optical information into electric signals, e.g., a one-dimensional image sensor, and numeral 2 designates a circuit for generating drive clocks of fixed frequency to read the light receiving signal in sequence from the image sensor 1. The image sensor 1 outputs image signals in synchronization with clocks from the drive clock generator 2. Numeral 3 designates an amplifier for amplifying the image signals, and numeral 5 designates a reference voltage generator for generating reference voltage to discriminate level of white or black of the image signals. A variable resistor 6 adjusts and determines the reference voltage. A comparator 4 compares the reference voltage and the image signal, and generates a binary signal. The comparator 4 serves to emphasize the dark and pale state of the original picture by utilizing the binary signal. In a circuit of the prior art, for example, disclosed in Japanese patent application laid-open (Kokai) No. 60-158769, the reference voltage to convert the image signal of the dark and pale state into binary signal is adjusted using the variable resistor 6. 
     In such constitution of the prior art, the semi-fixed resistor 6 for adjusting the reference voltage must be arranged at position to make the adjustment easy and a method to facilitate the adjustment must be considered, resulting in the limitation that the circuit can not be made into a compact and simple structure. 
     Also in a color image signal binary circuit where optical information being indicent to an image sensor is color image, there exists a similar problem and adjustment of the reference voltage corresponding to color component image signals of plural colors is further complicated. 
     SUMMARY OF THE INVENTION 
     An object of the invention is to provide an image signal binary circuit wherein constitution is compact and the adjustment is simplified. 
     Another object of the invention is to provide a color image signal binary circuit which is simplified. 
     A further object of the invention is to provide a binary circuit wherein adjustment of binary reference level at binary coding of monochromatic image signal or color image signal is made easy. 
     In order to attain the above objects, the invention is provided with a frequency variable type drive clock generator where the frequency of pulse wave generated in response to a color signal is variable, and a clock signal generated by the drive clock generator is supplied to an image sensor. 
     The frequency variable type clock generator varies the frequency of the clock signal in response to the control signal. If the variable range of the clock signal is set in a range including a frequency higher than the cut-off frequency of a circuit installed between the image sensor and the comparator, the circuit between the image sensor and the comparator varies gain corresponding to the control signal, thereby the level of the input signal of the comparator is varied corresponding to the control signal. Consequently, the binary level of the comparator is varied corresponding to the control signal. 
     Or, the variable range of the clock signal may be set to a frequency lower than the cut-off frequency of a circuit installed between the image sensor and the comparator, and the reference voltage may be varied corresponding to the frequency of the drive clock, thereby the binary level in the comparator can be varied. 
     Further the invention, in order to attain the above objects, is provided with a constitution where the frequency of the clock pulse from the drive clock generator is automatically adjusted corresponding to the color components being incident to the image sensor so as to deal with the fact that the spectral sensitivity characteristics of the image sensor are different depending on the color components of the incident light in the color image signal binary circuit having the comparator. That is, the drive clock generator is installed so that the frequency of the drive clock supplied to the image sensor is varied corresponding to the color components being incident to the image sensor, thereby a color image binary circuit that does not require adjustment is a compact and simple structure is obtained. 
    
    
     BRIEF DESCRIPTION Of THE DRAWINGS 
     FIG. 1 is a block diagram illustrating circuit constitution of an image signal binary circuit in the prior art; 
     FIG. 2 is a block constitution diagram illustrating an image signal binary circuit as an embodiment of the invention; 
     FIG. 3 is a graph illustrating frequency-gain characteristics of an amplifier 3 in the embodiment of FIG. 2; 
     FIG. 4 is a circuit diagram ilustrating a concrete circuit example of a reference voltage generator in the embodiment of FIG. 2; 
     FIGS. 5A, 5B, 6A, 6B are waveform charts illustrating relation of image signal, reference voltage and comparator output in a comparator 4 in the embodiment of FIG. 2; 
     FIG. 7 is a circuit constitution diagram of an image signal binary circuit as another embodiment of the invention; 
     FIG. 8 is a graph illustrating output-frequency characteristics of an amplifier 3 and a reference voltage generator 5 in the embodiment of FIG. 7; 
     FIGS. 9A, 9B, 9C are waveform charts illustrating relation of image signal, reference voltage and comparator output on a comparator 4 in the embodiment of FIG. 7; 
     FIG. 10 is a circuit constitution diagram illustrating an example of a frequency variable type drive clock generator in FIG. 2 and FIG. 7; 
     FIGS. 11A, 11B, 11C are waveform charts illustrating output waveforms in the drive clock generator in FIG. 10; 
     FIG. 12 is a circuit constitution diagram illustrating the invention applied to a color image signal binary circuit; 
     FIG. 13 is a diagram illustrating spectral sensitivity characteristics of an image sensor 1 in the embodiment of FIG. 12; 
     FIG. 14 is a diagram illustrating transmittivity characteristics of color component filters installed in front of an image sensor 1 in the embodiment of FIG. 12; 
     FIGS. 15A, 15B, 15C are waveform charts illustrating signal waveforms in respective parts of the image sensor 1 in the embodiment of FIG. 12; 
     FIG. 16 is a circuit constituting diagram of an embodiment of the invention applied to a color image signal binary circuit; 
     FIG. 17 is a circuit constitution diagram of another embodiment of the invention applied to a color image signal binary circuit; and 
     FIG. 18 is a block diagram illustrating a concrete circuit constitution of a frequency variable type drive clock generator 10 in circuit constitution of FIGS. 12, 16 and 17. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the invention will now be described in detail referring to the accompanying drawings. FIG. 2 is a block diagram illustrating a first embodiment of the invention. An image signal read circuit of the first embodiment comprises an image sensor 1, an amplifier 3 for amplifying output signals of the image sensor 1 which may be at least a one-dimensional solid image pick-up element, a comparator 4, a reference voltage generator 5, and a frequency variable type drive clock generator 10. The image sensor 1, the amplifier 3, the comparator 4, and the reference voltage generator 5 are similar to those in FIG. 1. 
     The output voltage of the reference voltage generator 5 is applied directly to the comparator 4. The drive clock generator 10 varies frequency of the output clock signal in response to frequency control signal applied to a control terminal 11. The drive clock generator 10 will be described below. Optical information being incident to the image sensor 1 in response to clock signal from the drive clock generator 10 is outputted as pulse signal by the image sensor 1 and then supplied to the amplifier 3. The frequency of the signal outputted from the image sensor 1 varies depending on a frequency control signal applied to the control terminal 11. 
     Since the amplifier 3 has gain characteristics depending on the frequency of the input signals, even if signals of the same amplitude level are inputted, the signal level of the output signals varies depending on the frequency. Accordingly, even if the output voltage of the reference voltage generator 5 is constant, and since the level of the image signals 7 inputted to the comparator 4 varies in response to the frequency control signals inputted to the control terminal 11, the binary level in the comparator 4 also varies similar to the case where the reference voltage is varied. 
     FIG. 3 is a graph of the frequency-gain characteristics of the amplifier 3. The gain of the amplifier 33 gradually decreases when the frequency of the input signal exceeds the cut-off frquency f c . Although the gain is A v1  at the frequency f 1  lower than the cut-off frequency f c , it decreases to A v2  at the frequency f 2  higher than the cut-off frequency f c . 
     In the invention, the region where the gain varies at prescribed rate corresponding to the frequency of the input signals (the region from the frequdncy f a  to the frequency f b ) it utilized. The frequency control signal applied to the control terminal 11 of the drive clock generator 10 is varied, thereby the frequency of the image signal outputted from the image sensor 1 is varied in the region from f a  to f b . Then the gain of the amplifier 3 varies in the region from A va  to A vb , thereby the voltage level of the output of the amplifier 3 varies. When the output voltage level of the amplifier 3 varies, the binary level of the comparator 4 varies even if the reference voltage generated by the reference voltage generator 5 is constant. 
     FIGS. 5A, 5B, and FIGS. 6A, 6B show the relation of the output voltage of the amplifier 3 to the reference voltage and the relation of the output signal of the comparator 4 when the frequency of the input signals of the amplifier 3 are f 1 , f 2  respectively. In the figures, numeral 7 designates output signal of the amplifier 3, numeral 8 designates output signal of the reference voltage generator 5, and numeral 9 designates output signal of the comparator 4. 
     When the frequency of the input signal of the amplifier 3 is f 1 , since the gain of the amplifier 3 is as high as A v1 , pulses to the fourth pulse exceed the reference voltage V TH . However, when the frequency increases to f 2 , the gain of the amplifier 3 decreases to A v2  and therefore the number of pulses exceeding the reference voltage decreases to two pulses. Consequently, although the binary signal of (001111) is outputted from the comparator 4 at the frequency f 1 , the output of (000011) is obtained at the frequency f 2 . This corresponds to the case that the reference voltage is made V TH2  as shown by broken line in FIG. 5A. 
     Assuming that the level 1 in the output of the comparator 4 represents &#34;black&#34; and the level 0 represents &#34;white&#34;, when the frequency is f 1 , a level being nearer to &#34;white&#34; in the original signal is outputted as a &#34;black&#34; signal in comparison to the case of the frequency f 2 . On the contrary, when the frequency is f 2 , a level being nearer to &#34;black&#34; is outputted as &#34;white&#34;. Accordingly, in order to read the original picture with little density difference, such as the original document written in a pale color, the frequency control signal applied to the control terminal 11 is controlled and the frequency of the read clock of the image sensor 1 may be lowered. 
     FIG. 4 shows a circuit of the reference voltage generator 5 and the comparator 4. Since the reference voltage V TH  may be fixed in the invention, the dividing voltage of the power source V cc  by resistors R 1 , R 2  is made the reference voltage V TH . The comparator 4 comprises a comparator 41, and the reference voltage divided by the resistors R 1 , R 2  is supplied to the reference voltage input end of the comparator 41. 
     According to the embodiment as above described, even if the reference voltage 8 (V TH ) is made constant, the generated clock frequency f of the drive clock generator 11 to be inputted to the image sensor 1 is varied, thereby the relative level of the reference voltage V TH  at the binary coding of the image signal 7 of the original document of intermediate color can be varied. 
     The frequency range (f a  -f b ) used in the embodiment can be freely set by varying the cut-off frequency f c  by design of the amplifier 3. Accordingly, the frequency range can be set corresponding to the reaction speed of the image sensor 1 and the processing speed of appliances connected to the output terminal 9. 
     A second embodiment of the invention will be described in detail referring to the accompanying drawings. Although the clock signals having a frequency higher than the cut-off frequency f c  of the amplifier 3 are generated in the first embodiment, the frequency band lower than the cut-off frequency f c  is used in the second embodiment. Consequently, the voltage level of the image signal inputted to the comparator 4 is constant irrespective of the frequency of the drive clock. In the second embodiment, the reference voltage supplied to the comparator 4 is varied corresponding to frequency of the drive clock, thereby the binary level in the comparator 4 is varied. 
     FIG. 7 is a block diagram illustrating the second embodiment. FIG. 7 is different from FIG. 2 in that a reference voltage generator designated by numeral 12 generates reference signal 18 based on the output voltage of the amplifier 3. The image sensor 1, the amplifier 3, the comparator 4, and the frequency variable type drive clock generator 10 are similar to those in the first embodiment. However, the cut-off frequency f c  of the amplifier 3 is set higher than the upper limit of the frequency variation range of the drive clock generated by the frequency variable type drive clock generator 10 as hereinafter described. 
     The reference voltage generator 12 of the embodiment is constituted by a peak hold circuit comprising a comparator 13, a diode 14, a capacitor 15, and a voltage divider comprising resistors 16, 17. The peak hold circuit holds the peak value of the output voltage of the amplifier 3 in the capacitor 15. The voltage V TH3  held in the capacitor 15 is divided by the resistors 16, 17, and the divided voltage is supplied as the reference voltage V TH4  to the comparator 4. The holding period of the peak value, i.e., response characteristics of the peak hold circuit can be determined corresponding to the time constant determined by impedance of the capacitor 15 and circuits (such as the resistors 16, 17) connected thereto. In the embodiment, the time constant is set to a sufficiently large value. 
     FIG. 8 shows frequency characteristics of the output voltage 7 of the amplifier 3 and the output voltage 18 of the reference voltage generator 12 in the embodiment. Graph a illustrates the frequency characteristics of the output signal of the amplifier 3, graph b illustrates the frequency characteristics of the output signal of the peak hold circuit, and graph c illustrates the frequency characteristics of the reference signal inputted to the comparator 4. As shown in graph b, the cut-off frequency f c1  of the peak hold circuit is set lower than the cut-off frequency f c2  of the amplifier 3. The cut-off frequency f c1  of the peak hold circuit can be set by varying the output impedance of the comparator 13, the internal resistance of the diode 14, the capacitance value of the capacitor 15, and the resistance values of the dividing resistors 16, 17. 
     In the second embodiment, the frequency of the clock pulse is varied in the range from f d  to f e , thereby the reference voltage V TH4  is varied in the range from V TH5  to V TH6  so as to vary the binary level in the comparator 4. 
     That is, even if signals having the same black peak level are inputted to the peak hold circuit from the amplifier 3, and since the black peak level is varied in the range from V TH5  to V TH6  by varying the frequency of the drive clocks in the range from f d  to f e , the binary level in the comparator 4 is varied corresponding to the frequency of the drive clocks even at the image signals having the same black peak level. 
     FIGS. 9A, 9B, 9C show input/output signals of the comparator 4 when the reference voltage V TH4  is varied from V TH5  to V TH6 . When the image signal having voltage decreasing stepwise is inputted as shown in FIG. 9A, outputs of the comparator 4 in the case of the reference voltage being V TH5  and V TH6  become as shown in FIGS. 9B, 9C respectively. When the clock frequency is made f e , the reference voltage 18 drops to V TH6  even at the same black peak level and therefore more signals are outputted as black. Accordingly, when a original document with little density is read, the frequency of the drive clocks may be increased. 
     According to the invention as above described, the binary level of the comparator can be varied by varying the frequency of the drive clocks. 
     In the second embodiment, since the image signal (black peak value) at a portion being the nearest to black among the optical information read by the image sensor 1 is held by the peak hold circuit and the reference voltage is determined based on the held voltage, the optimum reference voltage can be automatically determined by the read image. 
     If the time constant determined by the capacitor 15 and the resistors 16, 17 is set relatively short in the embodiment, since the reference voltage is automatically varied at front and rear sides with respect to the black peak existing at the midway when a sheet of the image is read, the binary level in the comparator 4 is varied and the binary state of the image signals can be obtained at a uniform sensitivity even if portions being different in the density exist on one original document. 
     Also in the second embodiment, since the power source of the reference voltage generator is made to be an output voltage of the amplifier 3, the resistor 16 may be set small or the resistance value may be made zero, thereby the maximum value of the dynamic range of the output of the amplifier 3 coincides with the maximum value of the reference voltage thereby the excessively high voltage is not used as the reference voltage source. When the voltage is divided by the resistor 16, the image signal 7 also may be divided by the resistor. 
     Further in the second embodiment, although the plus terminal of the comparator 13 of the reference voltage generator 12 is connected to the output end of the amplifier 3, it may be connected to the output end of the frequency variable type drive clock generator 10 and the reference voltage may be generated directly from the drive clock signal. In this case, however, the voltage of the output clock signal of the drive clock generator 10 must be set larger than the maximum value of the output of the amplifier 3 or otherwise the output of the amplifier 3 must be level-downed by a resistance dividing network or the like and then supplied to the comparator 4. 
     Next, a constitution of the frequency variable type drive pulse generator 10 used in the first and second embodiments will be shown in FIG. 10. The frequency variable type drive pulse generator 10 comprises an oscillator 21, a start pulse generator 22, a frequency divider 23, an AND circuit 24, an OR circuit 25, and a decoder 26. The frequency divider 23 divides the frequency of the original clock pulses generated by the oscillator 21 and outputs the divided frequency. The frequency control signal is applied to the decoder 26 through a bus 27 (connected to the control terminal 11 in FIG. 2), and the decoder 26 decodes the frequency control signal into binary codes of 2 n  and outputs the binary codes per each bit to the AND circuit 24. The output of the frequency divider 23 is supplied per each bit to another input end of the AND circuit 24. The output of the AND circuit 24 is inputted to the OR circuit 25, which outputs logic 1 if any one of the AND circuits 24 is logic 1. In this constitution, for example, when the decoder 26 outputs 2 in the binary notation, the output of the frequency divider 23 is frequency-divided in two. When the decoder 26 outputs 4 in the binary notation, the output is frequency-divided in four. The start pulse generator 22 generates signals indicating the read start of the image sensor 1. 
     In addition, the control signal which is supplied through the bus 27 and applied to the control signal 11 may be automatically calculated and transmitted when the operator inputs it by an input means (not shown) or when the output of the comparator 4 is processed by a processing unit (not shown). 
     FIGS. 11A, 11B, 11C show the relation of the start pulse (S) to the clock pulse from the OR circuit 25. FIG. 11A shows the start pulse (S), FIG. 11B shows the clock signal (φ 1 ) of the frequency f 2 , and FIG. 11C shows the clock pulse (φ 2 ) of the frequency f 1 . Of course, the start pulse (S) and the clock pulse (φ) are not inputted to the image sensor 1. 
     The first and second embodiments do not particularly touch on a light being incident to the image sensor 1. However, in general, the color component signals of the three colors, i.e., red (R), green (G) and blue (B), are obtained from the color original document using the image sensor, and a color image input device is frequently used so as to obtain the image data per one color. In this case, in order to obtain the color component signals of plural colors, one method uses individual circuits for respective color component images so that the image signals from the image sensor corresponding to the plural colors are made the binary state and converted into the image data. Or, another method uses one image sensor and one image exclusive circuit so that the circuit constant is adjusted or varied in interlocking with a change of color component filters installed in front of the image sensor. Also in this case, problems similar to the prior art exist even at the binary circuit portion of the image exclusive circuit and therefore the invention becomes effective. 
     A third embodiment of the invention applied to a color image input unit will now be described in detail referring to the accompanying drawings. 
     In FIG. 12, numerals 1-11 designates similar parts to the circuit elements in the embodiment of FIG. 2, and numeral 30 designates a color component discriminator. In the embodiment of FIG. 12, the amplifier 3, the comparator 4 and the reference voltage generator 5 are assembled together and called an analog/digital converter (ADC) 100. The image sensor 1 has the spectral sensitivity characteristics as shown in FIG. 13, and the relative output voltage of the output signal of the image sensor 1 becomes different depending on the wave length of the optical signals being incident to the image sensor 1. In order to obtain the color component images of the three colors, R, G, B, when the color component filters of the colors R, G, B are arranged alternately at the light receiving surface side of the image sensor 1, since the color component signals being incident to the image sensor 1 are different from each other in wave length as shown in a graph example of the transmittivity of each color component filter and wave length as shown in FIG. 14, the output signal voltage of the picture signals from the image sensor does not become equal but is different corresponding to the wave length of each of the color component signals R, G, B. 
     In the image sensor 1, the optical information being incident to the n image sensors is converted into the image signal voltage, and in synchronization with the start pulse (S) from the above-mentioned frequency variable type drive clock generator 10 as shown in FIG. 15A and the clock pulse (φ) as shown in FIG. 15B the image signal V out  in analog pulse form is outputted in sequence as shown in FIG. 15C. Even if the frequency of the drive clock φ is varied, the amount of the output voltage of the image signal V out   is not affected in the CCD type image sensor. Also in the MOS type image sensor, the frequency of the start pulse (S) to control the charge storage time (T int ) shown in FIG. 15A is held constant, thereby the output voltage of the image signal V out  is not affected by the frequency variation of the drive clock (φ) similar to the CCD type image sensor. The frequency variable type drive clock generator 10 varies the frequency of the output drive clock signal corresponding to the frequency control signal applied from the color component discriminator 30 to the control terminal 11. The frequency-gain characteristics of the amplifier 3 are as shown in FIG. 3, and the circuit operation of the rear stage of the amplifier 3 is similar to that described in detail in the foregoing embodiments. 
     FIG. 16 is a diagram illustrating a constitution of the color component discriminator in the embodiment of FIG. 12. Numeral 40 designates a color original document, numeral 43 designates a light source, and numeral 42 designates a lens. A filter change circuit 31 changes color component filters 32R, 32G, 32B, and outputs the color component discrimination signal to the control terminal 11. The ADC 100 has similar constitution to the circuit shown in FIG. 4. The filter change circuit 31 discriminates the color component filters 32R, 32G, 32B arranged in front of the light receiving surface of the image sensor 1, and outputs control signals corresponding to the respective color components to the terminal 11. As seen in the graph of FIG. 13, since color R is low in the spectral sensitivity of the image sensor 1 in comparison to other colors G, B, in the case of the color component filter 32R, a control signal to lower the frequency of the drive clock in comparison to other filters 32G, 32B is outputted to the control terminal 11. 
     According to the thrid embodiment as above described, even if the reference voltage 8 (V TH ) is made constant, the generated clock frequency f of the frequency variable type drive clock generator 10 to be inputted to the image sensor 1 is varied, thereby deviation of the image signal voltage of each color component due to the spectral sensitivity characteristics of the image sensor 1 can be made uniform and the relative level of the reference voltage 8 for binary coding the image signal 7 of each color component can be also made uniform. 
     In order to apply the invention to a color image input device, the constitution of the foregoing second embodiment may be used. FIG. 17 shows an embodiment in this case. The ADC 100 has similar constitution to that shown in FIG. 7. Numerals 34R, 34G, 34B designate lamps to emit respective color components, and the lamp change circuit 33 selects and changes one of the lamps 34R, 34G, 34B and applies the discrimination signal of the emitting lamp to the control terminal 11. The cut-off frequency f c  of the amplifier 3 is set higher than the upper limit of the frequency variation range of the drive clocks as already described in detail. Operation of the circuit at rear stage of the amplifier 3 is similar to that in the foregoing embodiment. 
     According to the embodiment, the frequency of the drive clock is varied corresponding to the color component image being incident to the image sensor 1, thereby deviation of the output signal of each color component image due to the spectral characteristics of the image sensor 1 can be absorbed by varying the binary level of the comparator and deviation of the binary data of each color component image signal can be eliminated. 
     FIG. 18 shows a circuit example of the drive clock generator 10 in the embodiments shown in FIG. 12, FIG. 16 and FIG. 17. The basic circuit constitution is similar to that shown in FIG. 10. In a decoder 26&#39;, a bus 27 and signal lines 29 are connected to the control terminal 11. Numeral 28 designates a switch group which is ON/OFF controlled in response to the discrimination signal from a color component discriminator 30, and the switch 28 corresponding to the color element inputted to the image sensor 1 is turned on and +V cc  appears at the signal line 29 connected to the selected switch 28. The decoder 26&#39; outputs the binary code group of 2 n  to the output terminal in response to the control signal from the bus 27 and the signal from the signal line 29. Since the circuit constitution of the decoder 26&#39; is obvious to those skilled in the art, its description shall be omitted together with a detailed circuit constitution of the decoder 26. 
     According to the invention as above described in detail, in place of the clock with the frequency f constant supplied to the image sensor in the prior art, the drive clock generator with the frequency f variable by hardware or software is installed, thereby the variable resistor for adjusting the output reference voltage V TH  of the reference voltage generator may be omitted and the circuit with non-adjustment and a compact and simple structure can be realized. 
     The clock frequency f is varied and set by hardware or software, thereby the relative level difference between the image signal inputted to the comparator and the reference voltage (V TH ) can be easily adjusted and the binary output data also can be easily adjusted. The drive clock generator is installed so that the frequency of the drive clock supplied to the image sensor is interlocking with the color component signal being incident to the image sensor is made variable, thereby duplicate binary circuits of exclusive use for respective color components may be omitted and one binary circuit can process respective color components. Moreover, a binary circuit witn not needing adjustment and having a compact and simple structure can be realized. 
     In the simultaneous image read apparatus of plural color components, a single binary circuit with the same circuit constant can be used by a number of plural color components without the need for adjustment and the binary circuits with dedicated circuit constant of exclusive use for respective color components are not required. 
     In the apparatus where the image is read by one circuit at times of the plural color components, the binary circuit of the same circuit constant can be used for the plural color components, and a binary circuit with nonadjustment and having a compact and simple structure can be realized.