Method and arrangement for testing mega-bit memory modules with arbitrary test patterns in a multi-bit test mode
BACKGROUND OF THE INVENTION 
     The invention is directed to a method for testing memory modules of the mega-bit generation with arbitrary test patterns in a multi-bit test mode, and to an arrangement for the implementation of this method. 
     In order to keep testing times short, memory modules of the mega-bit generation comprise a multi-bit test mode in which test information signasl are read-in at the data input of the memory module and simultaneously imaged on a plurality of cells of the cell field. For example, 1M (words)×1 (bit) -organized memory modules are tested as though they were organized with m cells, such as 256K×4, 128K×8, 64K×16, etc. so that 4, 8, 16 cells, etc. are simultaneously tested with a 1-bit datum per applied memory address. 
     The data actually written into the respectively m cells depend on the module design of the individual manufacturers. The cell data written-in are the m-dimensional result of the allocation of the one-bit test datum to the individual cells of a cell group described by the m-dimensional function 
     
         f (DE)={DE}.sub.1, . . . , m with DEε{0, 1} 
    
     in which DE represents a data information signal that is read into the mega-bit memory module. 
     The inverse allocation 
     
         f.sup.-1 ({DA}.sub.1, . . . , m)=DA with DAε{0, 1}, 
    
     is produced upon read-out of the cell contents of a cell group, so that the original test datum again appears at the data output of the memory module having error-free memory cells. DA represents a data information signal that is read out of the mega-bit memory module. 
     When the negated test datum is written in, the cell data are written into the cells of a cell group negated, so that the negated bit pattern resides in the cell group overall, in comparison to the bit pattern previously written in. The mapping function is: ##EQU1## wherein f 0  and f 1  =f 0  represent the functions prescribed by the module design. 
     Depending on the module design and, thus manufacturer-dependent, every memory module comprises exactly one mapping function f (DE), proceeding from the test datum, this mapping function generating a defined bit pattern within a cell group. The bit pattern can merely be negated for testing the memory module. However, the memory module is not adequately tested for bit pattern sensitivity with the respectively two bit patterns available. Many errors occur at malfunction cells only when their support field comprises a specific bit pattern. A number of topological tests exist for the recognition of such errors that are based on the interaction of at least two cells, these topological tests working with various test patterns. Topological tests, however, cannot be executed in unlimited fashion in the previous multi-bit test mode because the test patterns needed therefor cannot be generated in the cell fields. They can only be executed in the individual bit mode in mega-bit modules. This, however, is not expedient because the test cycle times are dependent on the type of test and on the storage capacity of the memory module are thus disproportionately high. Test cycle times of up to several hundred hours can occur. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to specify a method and an arrangement for the implementation of this method by which an arbitrary test pattern can be generated and, thus, topological tests having shortened test times can be enabled with memory modules of the mega-bit generation in a multi-bit test mode within a cell group. 
     The present invention achieves this object for the method. What is essential is that a fixed, design-dependent, m-dimensional imaging of a 1-bit datum onto the cells of a cell group of the cell field no longer takes place; rather, a test word provided with arbitrary individual data and having individual bits permanently allocated to the individual cells of a cell group is first formed, this being subsequently mapped onto the cells of a cell group of the cell field. 
     For the implementation of the method, the arrangement of the memory modules at the input of the cell field comprises at least one additional test word register having a bit width corresponding to the plurality of a cell group to be tested. A comparison logic in which the data information read out from the cell field are compared to the data information of the test word originally read-in is situated at the output of the cell field. 
     For controlling the read-in or write-in of a test word into the test word register or, respectively, of a test word into the cell field, an advantageous improvement of the invention utilizes an address line which becomes free as a result of the address space to be addressed having been reduced because of the multi-bit test mode, utilizing this in order to eliminate a relatively involved counter arrangement which counts the m data information of a test word during read-in. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     Reference will now be made to the accompanying drawing in which: 
     FIG. 1 illustrates the fundamental structure of a memory module of the mega-bit generation according to the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In additon to the switches S1 and S4 already present and in addition to the cell field ZF, the mega-bit memory module MBS shown in the figure comprises two additional test word registers for the test words TW0 and TW1 preceding the cell field ZF, and also comprises a comparison logic VGL following the cell field ZF. For example, the test word registers can be constructed of shift registers or of parallel registers. 
     The switch S3 is arranged between ZF and the test word registers, this switch S3 selecting the content of one of the test words TW0 or TW1 during the test in the multi-bit mode via the data information DE and forwarding it into the cell field ZF. 
     The mapping function is: ##EQU2## whereby f 0  =f 1  now need not necessarily apply. f 0  and f 1  are now no longer rigidly prescribed but are freely selectable from the outside by programming. 
     The switch S2 is connected from writing the test word registers to produce the selection signal DE for selecting one of the test words TW0 or TW1. The time of switching of S2 is controlled with the signal TW which is derived either from a counter Z having a counter cycle 2×m count units (case a) or from an address line A j  (case b). The address line A j  is an address line that is not used in the multi-bit test mode. It is assumed for the exemplary embodiment that the counter Z is integrated into the memory module. 
     When the multi-bit test mode is switched off with the signal TM=OFF, the data information DE arriving at the data input at the memory module are forwarded directly to the cell field ZF via the switch S1 and are written into the cell field ZF at a location specified by an address. When the content of a cell of the cell field ZF is read out, the cell information DA proceeds via the switch S4 directly to the data output of the memory module MBS. 
     For testing the memory module MBS, the signal TM=ON switches the memory module MBS into the multi-bit test mode. Further the turn-on of the test mode informs the counter Z of the memory module MBS that the incoming data information of the following 2×m write cycles (identified by low level pulses of the signal WRITE) are to be written into the test word register. To that end, the counter Z generates the control signal TW=ON whcih causes the swtich S2 to switch on the write-in into the test word register. The first m data information DE at the data input of the memory module MBS which are counted by the counter Z proceed via the switches S1 and S2 into the first test word register and form the test word TWO there. The second m data information DE, under control of the switch S2, are written into the second test word register and form the test word TW1. The relationship 
     
         TWO=TW1 
    
     need not necessarily apply to the test words TW0 and TW1. Simultaneously with the generating of two test words TW0 and TW1, the comparison logic VGL is supplied with the test words TW0 and TW1. 
     After 2×m data information DE have been read in, the counter Z sets the control line TW=OFF. In response thereto, the switch S2 causesone of the test words TW0 or TW1 to be mapped onto an m-dimensional cell group of the cell field ZF at the next write cycle. The test word can thereby be mapped onto one cell group or, preferably, can be successively mapped onto a plurality of cell groups. On the basis of the datum DE externally applied to the module, a switch can be randomly undertaken between the test word TW0 and TW1 during the mapping event. In the mapping of a test word TW0 or TW1 onto the individual cells of an m-dimensional cell group, the content of exactly one bit place of the test word is respectively mapped onto one cell of the cell group. The greatest variety of bit patterns are generated in this way in the cell field ZF at a prescribed location, with the appertaining support field being generated by the selection of specific test words TW0 and TW1. 
     Upon read-out, the cell contents of an m-dimensional cell group of the cell field ZF are subjected to inverse mapping in that the comparison logic VGL compares them to the test words TW0 and TW1. Given a positive course of the comparison, the result of the inverse function is output at the data output corresponding to 0 or 1, i.e. dependent on whether the bit pattern coincides with TW0 or TW1, whereas the data output is switched into the Hi condition or tri-state condition instead when a negaative comparision is realized. 
     A malfunctioning cell, however, could also be indicated in that the output level of the data output of the memory module MBS is 0 or 1 upon read-out of cell contents of error-free cells, whereas the level when reading out a cell group comprising at least one but at most m-1 malfunctioning cells correspondingly assumes the inverse value. The function of the comparison logic VGL is: ##EQU3## 
     A simplified embodiment of the circuit arrangement comprises only one additional test word register for a test word TW0, whose contents are mapped onto the cells of a cell group not negated (TW0) or negated (TW0), dependent on the data information DE given a fixed individual allocation of the bit places of the test word to the m cells of a cell group. For the rest, the operation of this circuit arrangement is analogous to that of the circuit arrangement comprising two additional test word registers. 
     It will be apparent that various modifications and/or additions may be made in the apparatus of the invention without departing from the essential features of novelty involved, which are intended to be defined and secured by the appended claims.