Programmable radio frequency communications device capable of programming a similar device
FIELD OF THE INVENTION 
     This invention is generally directed to computer-controlled devices having functional characteristics (i.e. a &#34;personality&#34; ) determined, at least in part, by characteristic-defining stored digital data. In particular, the invention is directed to an improvement whereby each device is given the ability to automatically transmit/ receive such characteristic/defining stored digital data to/from a similar computer-controlled device so as to provide yet another device having similar functional characteristics. By analogy to biological processes, the invention may be considered as providing a &#34;cloning&#34; ability to devices having a computer controlled personality. 
     BACKGROUND OF THE INVENTION 
     It is now commonplace (and becoming more so all the time) to provide computer-controlled devices having functional characteristics determined at least in part by characteristic-defining stored digital data within the device. For example, computer controlled radio communication devices may be provided wherein particular channel frequencies, encoder/decoder audio modulation tones (used for addressing purposes and the like), minimum volume settings, channel scanning patterns, etc. are defined by a particular pattern of stored digital data within a digital memory. In this way, radio equipment capable of performing a wide range of functions may have its unique &#34;personality&#34; defined for a particular functional installation by simply storing an appropriate pattern of characteristic-defining digital data in the appropriate digital memory of the radio. 
     The memory component used for storing such characteristic-defining digital data is typically of a substantially nonvolatile type (e.g. low power consuming CMOS memory circuits with automatic battery backup). The appropriate characteristic-defining digital data may be placed in the memory during the manufacturing process or in the field by users and/or distributors or the like. 
     Although by no means exhaustive, the following listing of prior issued U.S. Patents will provide an example of computer-controlled devices having functional characteristics determined, at least in part, by characteristic-defining stored digital data: 
     U.S. Pat. No. 3,835,384--Liff (1974); 
     U.S. Pat. No. 3,898,567--George (1975); 
     U.S. Pat. No. 3,924,192--George (1975); 
     U.S. Pat. No. 3,947,773--Christensen (1976); 
     U.S. Pat. No. 3,953,801--Podowski (1976); 
     U.S. Pat. No. 3,965,336--Grohmann (1976); 
     U.S. Pat. No. 3,968,444--Tenny (1976); 
     U.S. Pat. No. 4,017,800--Champagne (1977); 
     U.S. Pat. No. 4,031,491--Sakamoto (1977); 
     U.S. Pat. No. 4,114,100--Klank (1978); 
     U.S. Pat. No. 4,117,407--Kusakabe (1978); 
     U.S. Pat. No. 4,123,724--Das et al. (1978); 
     U.S. Pat. No. 4,131,853--Dreiske (1978); 
     U.S. Pat. No. 4,152,654--Tanaka (1979); 
     U.S. Pat. No. 4,155,043--Sakamoto (1979); 
     U.S. Pat. No. 4,223,352--Belisomi (1980); 
     U.S. Pat. No. 4,271,532--Wine (1981); 
     U.S. Pat. No. 4,287,601--Borg et al. (1981); 
     U.S. Pat. No. 4,320,386--Harris (1982). 
     So far as I am aware, all such prior art devices have required the use of a special programming unit to generate and store the characteristic-defining digital data in their appropriate digital memories. As will be appreciated, this represents the need for an additional special piece of equipment for many users of these devices which may only be utilized occasionally (e.g. when new devices are purchased or when it is desired to change the &#34;personality&#34; of an existing device to more closely resemble that of another existing device). 
     SUMMARY OF THE INVENTION 
     I have now discovered an economical way to provide each such device with the ability to automatically transmit/receive such characteristic stored digital data to/from a similar computer-controlled device so as to &#34;clone&#34; another device having a similar &#34;personality&#34; insofar as the functional characteristics controlled by such data are concerned. With this ability, users of such devices will hereinafter not have to invest in any further special purpose programming devices to merely transfer characteristic-defining data from one device to another. Accordingly, as soon as one device is available with the desired characteristic-defining data, all remaining devices within a user&#39;s system or subsystem may be quickly and easily reconfigured in the same way by briefly interconnecting them (preferably via a unidirectional data transfer wiring harness) with the first device. 
     In the presently preferred exemplary embodiment, this ability to &#34;clone&#34; additional devices having the same functional characteristics is realized by providing special purpose input/output/control bus connections between an externally accessible plug connector and the internal digital data processor which is conditioned by a special program subroutine. In the preferred exemplary embodiment, a unique unidirectional data transfer wiring harness is then plug-connected between two of these devices using the externally accessible plug connector just described. The specially conditioned data processor in each device then detects such an interconnection between devices and automatically assumes the appropriate data loading mode or data dumping mode (depending upon the orientation of the wiring harness). The device in the data dumping mode then proceeds under control of the other device to read and transfer duplicate characteristic-defining data thereto. At the same time, the device in the data loading mode automatically proceeds to request, accept and store such characteristic-defining digital data. 
     When applied to radio communication devices, the provision of this special purpose load/dump bus plug connector on each device will permit the &#34;personality&#34; features of one radio device to be copied directly into another through an appropriate wiring harness. This will add a new degree of flexibility to field programming abilities and will permit many field programming problems to be solved without requiring the use of a separate special purpose personality programming unit in the field. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These as well as other objects and advantages of this invention will be more completely understood and appreciated by careful reading of the following detailed description of the presently preferred exemplary embodiment and the accompanying drawing, of which: 
     FIG. 1 is a schematic diagram of a radio device having personality features determined by stored digital data and, in accordance with this invention, also having the ability to automatically transmit/receive such characteristic-defining stored digital data to/from a similar radio device; 
     FIG. 2 is a schematic illustration of two radio devices of the type shown in FIG. 1 interconnected by a unique unidirectional data transfer wiring harness used to effect automatic transfer of characteristic-defining stored digital data from radio device number 1 to a similar radio device 2; 
     FIG. 3 is a flow chart of the maskable interrupt code included in the program of the digital data processor utilized in the radio devices of FIGS. 1 and 2; and 
     FIG. 4 is a timing diagram useful in explaining the data transfer process effected by the subroutine of FIG. 3 between the radio devices of FIGS. 1 and 2. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The radio device 10 shown in FIG. 1 includes a conventional digital data processor 12 (e.g. a Motorola MC 146805G2) and a conventional digital data memory 14 (e.g. two Harris type 6514 integrated circuits) 16. The exemplary data processor 12 is a microprocessor of the type which includes internal random access memory (RAM), read only memory (ROM), timer circuits and input/output portions as depicted in FIG. 1. As should be recognized, other types of microprocessor circuits (e.g. a collection of separate conventionally interconnected integrated circuit chips for the processor, program memory, I/O ports, etc.) could also be used. The data processor 12 is conventionally supplied with operating electrical potential as depicted in FIG. 1 and is conventionally programmed so as to interact with other radio circuits via I/O ports 18. For example, via ports 18, the microprocessor 12 may sense the output of various tone decoders, may control tone encoders and tone decoders, may control audio volume, transmitter circuits, channel scanning circuitry, etc. In short, the overall &#34;personality&#34; of the radio device is substantially controlled by the microprocessor 12. (Of course, there may be some fixed personality features of the radio device which are not alterable by the data processor 12.) 
     To appropriately control the personality functions of the radio device, the data processor 12 is conventionally programmed to access characteristic-defining digital data stored in the RAM 14 (typically low current drain CMOS circuitry with automatic battery backup). For example, if a particular digital word in RAM 14 has a particular predetermined configuration, then the microprocessor 12 may cause a certain sequence of audio tones to be encoded and/or decoded by the radio circuits when the operator actuates a given switch or when a new carrier signal is first received, etc. Similarly, other digital words in RAM 14 can cause the microprocessor 12 to tune the radio filter circuits so as to permit reception and/or transmission of carrier frequency signals on a particular channel frequency, etc. Since this manner of effecting control over the &#34;personality&#34; of radio and/or of other computer controlled devices is conventional and well known in the art, no further detailed description of such features is needed for the understanding and practice of this invention. 
     In addition to the conventional components and functions just described, the radio device of FIG. 1 includes a special externally accessible plug connector 20. In the exemplary embodiment, plug connector 20 includes a ground connection (GND), a special control connection (HWARE) to an input port of the data processor 12 (e.g. PB7), a data output connection (DATAO) to an ouput port of the data processor 12 (e.g. PD.0.), and a data input connection (DATAI) to the interrupt terminal of the microprocessor 12 (e.g. IRQ). Alternatively, the data input connection could be to a separate data input port of the data processor 12 although this would not provide the preferred interrupt capability for the data transfer function. 
     In the exemplary embodiment depicted in FIG. 1, the HWARE and DATAI terminals are normally held at a high voltage level (binary data value &#34;1&#34;) by resistances 22 and 24 respectively which are connected to the voltage supply as shown. The data output port PD.0. in the exemplary embodiment is normally maintained at a low voltage level (e.g. a binary data value of &#34;.0.&#34;) and is also used to drive, among other things, the &#34;idle&#34; mode display (e.g. LCD 26) as also depicted in FIG. 1 
     The output of OR gate 28 is connected to the WRITE input of RAM 14 and is used to provide memory protection. In particular, if any of the inputs or OR gate 28 is high, then the WRITE input to RAM 14 is conditioned so as to prevent the writing of any digital data into its memory circuits. As depicted in FIG. 1, one input of OR gate 28 is connected to the normally high voltage HWARE control line. Accordingly, whenever, the HWARE control line is grounded, it will be possible to WRITE into the RAM 14. 
     To effect the transfer of characteristic-defining digital data from RAM 14 in one device 10 to another similar device, their respective external plug connectors 20 are interconnected by a unidirectional data transfer wiring harness 30 as shown in FIG. 2. Here, the wiring harness 30 is connected with its data receiving end 32 connected to radio device 2 and its data transmitting end 34 connected to a similar radio device 1. Both radio devices in this exemplary embodiment have identical hardware architectures of the type shown in FIG. 1. However, the characteristic-determining stored data in RAM 14 of radio 1 is initially different from that stored in the memory device of radio 2 and it is desired to change this situation so as to cause radio 2 to have the same &#34;personality&#34; or characteristic functional attributes as radio 1. 
     As may be seen in the FIG. 2 showing of wiring harness 30, the GND leads of both radios are interconnected by conductor 36. The control HWARE connection at radio 1 is left open circuited (i.e. at the transmitting end 34) but this same lead is shorted to ground via conductor 38 at the data receiving end 32 of harness 30. The remaining conductors 40 and 42 of the harness 30 effect transposed electrical connections between the DATAO terminal of radio 1 and the DATAI terminal of radio 2 on the one hand and between the DATAI terminal of radio 1 and the DATAO terminal of radio 2 on the other hand. 
     In the exemplary embodiment, microprocessor 12 has a maskable interrupt capability. In particular, anytime the IRQ terminal of microprocessor 12 is forced to a low voltage level, then the normal execution sequence of programmed instructions is altered by transfer to the maskable interrupt program depicted in the flow chart of FIG. 3. Alternatively, the executive program used by microprocessor 12 could be devised so as to periodically monitor a special control input to one of its input/output ports so as to detect an operator request (e.g. via switch, jumper wire connection, etc.) to enter a special &#34;cloning&#34; code of the type shown in FIG. 3. However, in the presently preferred exemplary embodiment depicted in FIGS. 1 and 2, since the I/O port PD.0. is normally maintained at a low voltage level, the mere interconnection of the special wiring harness 30 will immediately cause the DATAI terminal of the connector 20 on each of the radios to go a low voltage level and thus cause the microprocessor of each of the interconnected devices to immediately transfer to the &#34;cloning&#34; subroutine of FIG. 3. 
     Once the subroutine of FIG. 3 is entered at 50, the existing data value of the control HWARE line is immediately read at 52. Alternatively, the subroutine of FIG. 3 could initially enter a wait loop for a fixed time (or until an operator switch is actuated) to insure that connectors are firmly in place before the main body of the subroutine is executed. 
     As should be appreciated from FIGS. 1 and 2, the HWARE line of radio 1 will remain in its high &#34;1&#34; bit value status while the HWARE line of radio 2 is forced to a low .0. bit value status by the short to ground via conductor 38 of the wiring harness 30. Thus, the internal electrical control connections associated with the ends 32 and 34 of the unidirectional transfer wiring harness 30 make the two ends electrically distinguishable from one another by each of the interconnected radio devices. 
     A bit counter B is reset to zero at 54 in the flow chart of FIG. 3 and any other necessary initializing conditions for the particular subroutine to be employed may also be effected at this point in the flow chart. 
     A test of the previously read HWARE data value is made at 56 in the flow chart of FIG. 3. If the bit value is &#34;1&#34; (as it will be for the data transmitting device in the exemplary embodiment), a branch is made to a data dump mode shown at the righthand side of FIG. 3. Otherwise, control is transferred to a data load mode segment of the subroutine as also depicted in FIG. 3. 
     As should now be appreciated, in the exemplary embodiment, the data receiving device will branch to the data load mode. Accordingly, in the exemplary embodiment, immediately upon interconnection of radio devices 1 and 2 by the wiring harness 30, each of their respective data processors will be substantially immediately interrupted and, depending upon the directional orientation of the wiring harness 30, the data processor in one of the devices will be placed in a data dump mode while the data processor of the other device will be placed in the data load mode. 
     The exemplary embodiment is arranged so that the data receiving device sends successive bit clocking signals from its DATAO terminal to the DATAI terminal of the other device. In response, the data transmitting device reads successive bits of its characteristic-determining stored digital data and generates corresponding bit valued signals at its DATAO terminal which are then presented via the wiring harness 30 to the DATAI terminal of the data receiving device. This interactive exchange of bit clocking and data bit value signals between the two devices continues in rapid succession until all of the stored data bit values from the transmitting device have been nondestructively read and transferred to corresponding locations in a similar digital memory of the data receiving device. It should be noted that because of the memory protect feature associated with OR gate 28 and because of the non-grounded condition of the control HWARE line at the data transmitting device, the memory circuits of the transmitting device are protected from any inadvertant writing thereinto. 
     A more detailed understanding of this interactive data transfer process may be had by now considering the data load and data dump mode sections of the subroutine depicted in FIG. 3. 
     In the data load mode, a bit clocking signal is initiated at 58 e.g. by lowering the voltage level on the DATAO terminal (if not already lowered). Thereafter, the data value appearing on the DATAI terminal is read at 60. Then a request for an additional data bit is effected (e.g. by raising the voltage level of the bit clocking signal on the DATAO terminal at 62). The just previously read data value is stored at a properly indexed memory position (e.g. indexed by the bit counter B) at 64. The bit counter is then incremented at 66 and special tests are made at 68 and 70 to detect a possible request for transfer to a test routine (these steps may be omitted if no test routine is employed or if some other technique for entering the test routine is provided.) 
     In the exemplary embodiment, the characteristic-defining data stored in RAM 14 normally includes at least one nonzero bit value within the first eight bits of the memory. Accordingly, as soon as the first eight bits have been read from the DATAI input terminal (as detected at 68), they are checked for a constant zero value (at 70). If all zero values are detected, then this is an indication that a special purpose test apparatus has been connected to the plug connector 20 and that a special test code is to be entered. For purposes of understanding the present invention, the details of such a test code are not necessary. 
     In the absence of a special request for the test code, a check will be made at 72 to see if the requisite number of data bits have yet been received and stored. If not, transfer is made back to block 58 for another cycle of operation in the data load mode. On the other hand, if all of the characteristic-defining data bits have now been transferred, then control is passed to box 74 where the radio is reset such that its subsequent operation with new personality data will begin from a desired starting condition (e.g. previously set tone encoder/decoder, frequency filters and the like may be reset to an inactive or other common starting condition). 
     In the exemplary embodiment, resetting the radio also causes an audible beep to the operator which can be used as a positive indication that the desired data transfer process has been completed and that the wiring harness 30 may be disconnected. In addition, it should be noted that the LCD display 26 will provide a continuously changing visual indication of the ongoing data transfer process since the DATAO terminals on both radios will normally be changing between low and high voltage levels during the data transfer process. 
     In the exemplary embodiment, the interrupt terminal IRQ of the microprocessor 12 is also used as the data input terminal for this special type of data transfer. This dual function for the interrupt line is made possible because microprocessor 12 used in the exemplary embodiment has a maskable interrupt feature which permits it to ignore subsequent interrupt requests until the interrupt code has been completely exited and the masking bit reset. In the meantime, however, the exemplary microprocessor has an instruction set which includes conditional branch instructions depending upon the high or low condition of the interrupt line. Accordingly, data values can be effectively &#34;read&#34; from the high or low voltage level of the interrupt line during execution of the maskable interrupt subroutine of FIG. 3 by performing these branch instructions. If a branch is effected indicating a high voltage level on the interrupt line, then this can be interrupted as a &#34;1&#34; bit value. On the other hand, if that branch is not made (or if another branch is executed because the interrupt line is low), then this may be taken to represent a &#34;.0.&#34; bit value. This technique of monitoring the value of the interrupt line during execution of a maskable interrupt subroutine is believed to be conventional per se in the digital processing arts and thus needs no further description here. 
     If the microprocessor branches to the data dump mode shown in FIG. 3, then a properly indexed data bit value is read from the RAM 14 (e.g. as indexed by the bit counter B) and presented as an appropriate output data level on its DATAO terminal at 76. Thereafter, a wait loop is entered at 78 until the next positive-going edge of the bit clocking signal is detected at the DATAI terminal. Once that positive going edge of the bit clocking signal is detected, the bit counter is incremented at 80 and a test is made at 82 for the end of the data transfer process. Until the end of the data control process is reached, transfer is looped back to box 76 of the data dump mode portion of the subroutine shown in FIG. 3. Upon completion of the data transfer process, control is passed to box 74 where the radio is reset, etc. as previously described. 
     To briefly recap, once the radio devices are interconnected as shown in FIG. 2, the data recipient device enters a data load mode of operation while the data transmitting device enters a data dump mode of operation. Thereafter, the data recipient generates bit clocking pulses at its DATAO terminal which are received and used for control purposes at the DATAI terminal data transmitting device. Successive bit values are then fetched from the memory of data transmitting device and transmitted via its DATAO terminal to the DATAI terminal of the recipient device. In general, once the data transfer process has begun, new data values are output from the transmitting device on each positive-going clock pulse edge while data values are inputed to the recipient device at each negative-going clock transition. 
     This process is graphically depicted at the timing diagram of FIG. 4. Initially, the DATAO terminals of both devices are in their normal low level (&#34;.0.&#34;) status (due to conventional programming of the data processors 12) while the DATAI terminals are in a normally high level (&#34;1&#34;) as are the HWARE lines of both devices. Then, at time t1 the plug connection of wiring harness 30 is completed between both radios. This immediately causes the DATA I terminals of both devices to go low and, after some time interval delta t, radio 1 will enter its dump mode while radio 2 will enter its load mode. Thus, radio 2 generates successive positive and negative going bit clocking level transitions at its DATAO terminal which are connected to the DATAI terminal of radio 1. At the same time, successive data bit level values are transmitted from the DATAO terminal of radio 1 to the DATAI terminal of radio 2. For the exemplary process depicted in FIG. 4, bit values &#34;100 . . .&#34; would be transferred. 
     As will be noted in the exemplary embodiment, the harness 30 should not be connected between devices unless both devices are in their &#34;idle&#34; mode with DATAI terminals at a low voltage level --as can be visually checked by LCD 26. Interconnection of harness 30 substantially simultaneously will cause an interrupt in both devices and a transfer to the &#34;cloning&#34; code of FIG. 3. Alternatively, another wait loop can be incorporated in the data load mode program or in the common initial portion of the &#34;cloning&#34; code so as to insure that both devices are plug connected and fully ready to execute the data transfer process before actually entering the data load/dump mode operation. If desired, some initial signal &#34;handshake&#34; sequence or the like could also be incorporated in the FIG. 3 code for this purpose before branching to the load or dump mode portions of the program. Switched connections could also be incorporated in harness 30 to insure simultaneous interruption of both connected devices as should by now be apparent. 
     Although only one presently preferred exemplary mode of this invention has been described in detail above, those skilled in the art will recognize that there may be many modifications and variations of this exemplary embodiment which nevertheless retain many of the novel advantages and features of this invention. For example, there are many different interrupt and/or signal monitoring techniques that may be employed by the data processors to detect the request for this type of data transfer. Furthermore, the data transfer can be effected in many different specific ways via dedicated input/output ports, I/O ports having shared usage, special purpose control terminals (possibly also having shared usages), etc. Many different types of data transmitting protocols and/or clocking protocols may also be utilized. The detailed sequences of operations in the data load/dump mode may also take many different forms. Accordingly, all such variations and modifications are intended to be within the scope of the following appended claims.