Pulse width modulated control method and means
CROSS REFERENCE TO RELATED APPLICATIONS 
     Portions of the disclosure herein are related to a copending patent application entitled TOTEM POLE SNUBBER METHOD AND MEANS, filed in the name of the same inventor and on the same date as this application, the entire content of which is incorporated by reference herein. 
     BACKGROUND OF THE INVENTION 
     This invention relates to improved electronic pulse width modulated control method and means for supplying power to an inductive load with special applications to D.C. motors. 
     Methods are known for controlling current in an inductive load using a relatively high frequency chopper circuit in the order of 10 KHz for applying power to the load using pulse width modulation (P.W.M.). 
     P.W.M. controls typically operate in relation to reoccuring P.W.M. periods. A clock or other sequencer typically times the beginning of each P.W.M. period. A power switch (or switches) is typically switched &#34;on&#34; (if not already &#34;on&#34;), applying a pulse of current to the load at the beginning of each P.W.M. period. In the &#34;off&#34; state the power switch removes the power applied to the load. A P.W.M. controller, which may include the power switches, controls the &#34;on&#34; and &#34;off&#34; times of the power switches. 
     On a pulse-by-pulse basis, each pulse of applied power can be limited in duration by duty cycle control or by current limit control when a predetermined maximum current is flowing either in the load and/or in the power switch which couples the power to the load. 
     FIG. 10 is a flow chart depicting the &#34;on&#34; and &#34;off&#34; time of the power switch for a known P.W.M. method for driving an inductive load and could be implemented on either a software or firmware controlled computer or in hardware or a combination of the two. The &#34;on&#34; and &#34;off&#34; states of the power switch connect and disconnect a source of power across the inductive load. 
     One of the significant inductive loads controlled by P.W.M. techniques is that of a motor winding for a D.C. motor. 
     The flow chart of FIG. 10 contains eight blocks numbered 1-8. The operation within blocks 2, 3, 6 and 8 depicts action items whereas the items in blocks 4, 5 and 7 depict test conditions and branches to be taken depending on the results of the tests. The symbolic notation used within the blocks will become better understood with reference to the description of FIGS. 3-5. 
     However, the operation can briefly be described as follows. As depicted by FIG. 11, the P.W.M. control is controlled by regular reoccurring clock periods or P.W.M. periods. P.W.M. periods 1, 2, 3 and 4 are shown by way of example. At the beginning of each P.W.M. period, the P.W.M. control forms an &#34;on&#34; or high signal which turns &#34;on&#34; the power switch coupling the source of power across the inductive load. A duty cycle is selected for the &#34;on&#34; period depicted as &#34;ton&#34;. When the duty period has elapsed, the P.W.M. control turns the power switch &#34;off&#34;, allowing the power to remain &#34;off&#34; for the rest of the P.W.M. period. 
     The P.W.M. control also monitors the current flowing, either in the inductive load or through the power switch, and when the current reaches a predetermined limit value, the P.W.M. control switches the power switch &#34;off&#34;. This occurs during P.W.M. period 3 at 3a. 
     When the inductive load is a winding or windings of a D.C. motor, there are many constraints that have to be taken into account when selecting a P.W.M. switching frequency. Some of the pertinent constraints are now described. 
     Switching Losses: 
     Any power switch used in a chopper circuit has internal switching losses and there may be switching losses in associated circuitry such as a snubber or diode protection device for the power switch. These losses are undesirable from thermal considerations, and are directly proportional to the switching frequency. Therefore, to keep switching losses low it is desirable to keep the switching frequency low. 
     Avoidance of Current Ramping: 
     The following two equations govern the rate of rise of current in the motor windings for the &#34;on&#34; and &#34;off&#34; states of the power switch: ##EQU1## where: Vs=D.C. supply voltage 
     E=Motor back E.M.F. 
     I=Current flowing in the motor windings 
     R=Resistance of motor windings 
     L=Inductance of motor windings 
     di/dt=Rate of rise of current 
     In typical power switching applications, current limiting is used to protect the power switches against current rising above the maximum limit allowable for the power switch. Sensing circuitry is used to monitor current in the motor windings and/or the power switch. By sensing the current the power switches can be turned &#34;off&#34; before the current reaches this maximum limit. In practice, a predetermined current limit is set that is known to be inside the switching capabilities of the power switch. 
     Typically, in D.C. motor applications, a power switch has one side coupled through the motor windings to one rail of a D.C. supply voltage and the other side of the power switch is coupled serially through a sensing resistor to the return of the supply voltage. Also, a free wheel diode may be connected in parallel with the motor windings to allow current decay in the winding when the power switch is &#34;off&#34;. 
     When the power switch is &#34;on,&#34; current flows from the supply voltage through the motor windings, the power switch, the current sensing resistor and back through the return. When the power switch is switched &#34;off,&#34; however, the current decays through the motor windings and around through the free wheel diode. During the power switch &#34;off&#34; state, current cannot be sensed in the sense resistor. Therefore, even when the maximum allowable level of current is flowing in the motor windings, if the power switch is &#34;off&#34;, the current is not sensed. At the start of the next P.W.M. period the power switch is turned &#34;on&#34; if the duty cycle is not zero. Also, depending on the type of power switch, there are constraints which cause a minimum &#34;on&#34; time of the device once it has been switched &#34;on&#34;. Such a constraint may be the inherent storage time of a bipolar power transistor. 
     The implication of this minimum &#34;on&#34; time is that even if a current limit is reached as soon as the power switch is turned &#34;on&#34;, the power switch cannot turn &#34;off&#34; until this minimum time has elapsed. Once it has turned &#34;off&#34;, current is removed from the sense resistor, and at the start of the next P.W.M. period, this minimum &#34;on&#34; time cycle can be repeated. 
     For a D.C. motor, when the back E.M.F. (E) is small and the expression E+IR is small with respect to the supply voltage Vs, then, from equations (1) and (2) the rate of rise of current is high relative to its rate of fall. 
     To ensure current stays at or below the maximum level when current limit control is occurring, it is important that the current falls during the power switch &#34;off&#34; time by at least as much as it rises during the &#34;on&#34; time. If this condition is not met, it can result in failure of the power switch by excessive current build-up occurring over several P.W.M. periods. This mechanism is known as current ramping and is illustrated in the current waveform of FIG. 12. 
     To control current ramping, it is necessary to have an &#34;off&#34; time of sufficient duration to allow the current to fall by at least as much as it can rise during minimum &#34;on&#34; time. In practice, this requirement then limits the maximum switching frequency or puts constraints on the type of switching device which is suitable. 
     Another method of controlling current ramping is to continuously sense the current flowing in the motor windings. Thus the current limit sensing can remain active even during the &#34;off&#34; time and be used to prevent the new P.W.M. period from turning &#34;on&#34; the power switch if a current limit is still present. In practice, however, the difficulty and/or cost of continuous current sensing, particularly for multi-phase motor systems, can make this approach restrictive in its application. 
     CURRENT RIPPLE 
     It is a property of a D.C. motor that the torque produced from the motor is directly proportional to the current flowing in the motor windings. When maximum torque is required from the motor, the P.W.M. control system allows maximum current to flow and operates in a current limited mode. A current limited mode is one in which 100% duty cycle is provided and, as a result, the power switch stays &#34;on&#34; continuously through a P.W.M. period and even into the next P.W.M. period and only turns &#34;off&#34; when a current limit is sensed. 
     When the motor speed is low and the back E.M.F. is low, then the rate of fall of current during the &#34;off&#34; time is low with respect to the rate of rise of current during the &#34;on&#34; time as outlined above when discussing current ramping. Since the rate of fall of current is low within a single P.W.M. period, then, provided current ramping can be avoided, low current ripple, particularly in current limit operation, is obtainable in the motor windings. FIG. 13 depicts the low ripple current waveform for low back E.M.F. 
     When the motor speed is high, motor back E.M.F. is high, and the situation is reversed. With the back E.M.F. high, then from equations (1) and (2) it can be seen that the rate of fall of current during the &#34;off&#34; time is high with respect to the rate of rise of current during the &#34;on&#34; time. Therefore, if a current limit occurs at the start of a P.W.M. period, terminating the &#34;on&#34; time of the power switch, current will fall in the motor winding until the next P.W.M. period is commenced. If the P.W.M. period is long compared to the rate of fall of current, then during the &#34;off&#34; time the current could fall to a low or even zero value. If the current has fallen to zero in the motor windings, then it will stay at zero until the start of the next P.W.M. period occurs, and it may take several P.W.M. periods for current to build back up to the required level. This implies that 100% current ripple is possible. If the system is operating in the current limited mode, then this current ripple lowers the average current in the motor which in turn lowers the average torque developed by the motor. FIG. 14 shows the current waveform in the motor with high back E.M.F. and high current ripple compared with the previous FIG. 13. 
     The net effect of increasing current ripple with increasing motor speed is that the average driving current decreases and therefore the maximum available motor torque decreases with increasing motor speed. FIG. 15 illustrates this effect. Thus when the available motor torque has dropped and intersected the load torque line, the motor is incapable of any further increase in speed. 
     The problem of loss of average motor current at high speed is further aggravated in applications where a D.C. motor is driven from an A.C. rectified unfiltered supply, sometimes called a rippling rail supply. FIG. 16 depicts a voltage supply with full voltage ripple at twice the A.C. supply frequency. A motor running from this supply can draw current only when the magnitude of the supply voltage is greater than the motor back E.M.F. voltage. Thus the value of motor back E.M.F. determines the conduction angle and hence conduction time of current from the supply. With a high back E.M.F., the conduction angle is very low and the average torque in the motor over several main cycles is reduced accordingly. 
     One method to reduce current ripple and increase average driving current, with high speed and high load requirements, is to increase the switching frequency. This has the effect of reducing the maximum possible &#34;off&#34; time after a current limit before a new P.W.M. period begins, resulting in the effect shown in FIG. 17. 
     To summarize, a low switching frequency is required to minimize switching losses and to avoid current ramping, while a high switching frequency is required to minimize high speed and high load current ripple. The conflict is obvious. 
     For systems where this conflict must be accepted, the solution for increased motor torque at high speed is often to increase the switching frequency to the limit of current ramping and/or increase the peak allowable current in the power switch before current limiting occurs. Both of these methods increase the power handling requirements of the system and increase the cost. 
     Attempts have been made at minimizing the conflict. An example is disclosed in U.S. Pat. No. 4,037,145 entitled Multiple Frequency Chopper Control. In this patent, the switching frequency of the P.W.M. system is increased as the current in the motor increases. While this may decrease the effect of high speed current ripple, it does not take into account applications where there can be current ramping at low speed and the system must be rated to dissipate the switching losses when operating at the highest switching frequency. 
     BRIEF SUMMARY OF THE INVENTION 
     It is therefore desirable to have a P.W.M. control method and means that eliminate the switching frequency conflict without the need of increased power handling. 
     The present invention improves the operation of a P.W.M. control system. This is effected in an embodiment of the invention by using a single frequency P.W.M. period with a frequency of operation that maintains acceptable switching losses and effects of current ramping. Also, current ripple is reduced in loads where the current ripple can reach an undesirable level. 
     Briefly, a method which embodies the present invention uses at least one power switch having &#34;on&#34; and &#34;off&#34; states for providing, respectively, low and high impedance paths between an inductive load and a source of power, and thereby controls current flow through the inductive load during a sequence of regular reoccurring time periods. The at least one power switch is switched, if in the &#34;off&#34; state, to the &#34;on&#34; state substantially at the beginning of at least some of the time periods. The method comprises a combination of steps, operative during any one of a plurality of the &#34;on&#34; duty periods. The method switches the at least one power switch from the &#34;on&#34; state to the &#34;off&#34; state when a predetermined level of current flow has been reached in one of, the inductive load and the at least one power switch, and switches the at least one power switch back to the &#34;on&#34; state independent of the occurrence of the beginning of a time period. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic and block diagram of a P.W.M. control for controlling a power switch which provides low and high impedance paths between an inductive load and a source of voltage and embodying the present invention; 
     FIG. 2 is a schematic and block diagram of a P.W.M. control and timing sequencer for controlling a plurality of power switches which in turn apply and remove power across the multiple windings of a D.C. motor, the system forming an electronic commutated motor drive system and embodying the present invention; 
     FIG. 2A is a schematic and block diagram of a laundry machine having an electronically commutated motor and motor control similar to that depicted in FIG. 2; 
     FIG. 3 is a flow diagram illustrating the method of operation of the P.W.M. control for the power switches of FIGS. 1 and 2; 
     FIG. 4 is a waveshape diagram illustrating the current waveform in the motor windings of FIGS. 1 and 2 with the method of operation depicted in FIG. 3 at 100% duty cycle; 
     FIG. 5 is a flow diagram illustrating the method of operation of an alternate P.W.M. control for FIGS. 1 and 2 which is speed sensitive and embodying the present invention; 
     FIGS. 6A and 6B are block diagrams of a P.W.M. control for use in the P.W.M. controls of FIGS. 1 and 2 and embodying the method depicted in FIG. 5; 
     FIG. 7 is a block diagram of an alternate P.W.M. control for use in the block diagram of FIGS. 1 and 2 and embodying the method depicted in FIG. 5; 
     FIG. 8 depicts an alternate embodiment similar to that depicted in FIG. 1 with current sensing in the motor winding and embodying the present invention; 
     FIG. 9 is a flow diagram illustrating the sequence of operation of the system depicted in FIG. 8 and embodying the present invention; 
     FIG. 10 is a flow diagram illustrating the method of operation of a prior art P.W.M. control for D.C. motors; 
     FIG. 11 is a waveshape diagram illustrating the output of a prior art P.W.M. control; 
     FIG. 12 is a waveshape diagram illustrating the current waveform under current ramping conditions for conventional P.W.M. controls known in the prior art; 
     FIG. 13 is a waveshape diagram illustrating the current waveform in the winding of a D.C. motor for conventional P.W.M. controls known in the art under low speed conditions; 
     FIG. 14 is a waveshape diagram illustrating the current waveform in the winding of a D.C. motor employing a conventional P.W.M. control known in the prior art; 
     FIG. 15 depicts a waveshape diagram illustrating the torque curve of a motor employing a conventional P.W.M. control known in the prior art; 
     FIG. 16 depicts a waveshape diagram for rippling rail power supply and the corresponding conduction time of the power switch in a system of the type depicted in FIGS. 1 and 2; and 
     FIG. 17 depicts the current waveform in the motor windings of a D.C. motor control using a conventional P.W.M. control of the prior art. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENT 
     An embodiment of the invention involves method and means which operate such that within the &#34;on&#34; duty period of each P.W.M. period, the power switch is reenabled or turned back &#34;on&#34;, independent of the beginning of a P.W.M. period, after having been switched &#34;off&#34; due to a current limit having been reached. Preferably the reenabling or turning back &#34;on&#34; of the power switch is delayed for a predetermined delay period after the power switch has been switched &#34;off&#34;. Another embodiment of the invention switches the power switch back &#34;on&#34; after an &#34;off&#34; state after current in the inductive load has decayed to a predetermined current level. 
     FIG. 1 is a schematic and block diagram depicting an embodiment of the present invention. FIG. 1 includes a P.W.M. control 10 whose output 10a is connected to a power switch in the form of a transistor 12. The transistor 12 has its collector electrode serially coupled through a motor winding 14 of a motor 16 to the positive side or rail 18 of a voltage supply called V supply. The emitter electrode of transistor 12 is serially connected through a current sensing resistor 20 to a return rail 22 where the return rail is connected to the negative, or 0 volt, side of V supply. The motor winding 14 is schematically depicted by an inductive element 24 and a resistive element 26 and a rotating armature 28. The motor 16 can be any one of a number of different types of D.C. motors, such as a D.C. brushless motor or an electronically commutated A.D. synchronous motor, which rotate the rotor responsive to current pulses in the winding. The P.W.M. control 10 has conductors 32 and 34 connected across the current sense resistor 20, and includes a circuit (not shown) which senses when a predetermined level or limit of current flow exists through resistor 20 and hence through transistor 12 and motor winding 14 during a &#34;on&#34; state of transistor 12. 
     P.W.M. control 10 applies a control signal to the base electrode of the transistor 12 to switch it to &#34;on&#34; and &#34;off&#34; states. When transistor 12 is &#34;on&#34;, it is in a low impedance condition and couples the V supply across the motor winding 14, causing current flow through the motor winding 14, power switch 12 and the sense resistor 20 between the rails 18 and 22. When transistor 12 is &#34;off&#34; it forms a high impedance condition and in effect disconnects the source of power from the motor winding. When the P.W.M. control 10 switches the transistor 12 &#34;off&#34;, the motor winding maintains its current flow in the same direction. However with the transistor 12 &#34;off&#34;, current now circulates around the path including the motor winding and the free wheel diode 36. A clock 30 provides a source of regular reoccurring clock signals which synchonize the operation of the P.W.M. control 10. 
     The P.W.M. control 10 includes a microprocessor indicated generally at 10b. The microprocessor controls the sequence of operation of the transistor 12 thereby implementing the method and means according to the present invention. 
     FIG. 4 depicts the current waveform and operation of transistor 12 when the motor rotor is at high speed, and under high load similar to that depicted for the prior art in FIG. 14. It will be seen that the current ripple is substantially less than that of FIG. 14 and hence the average current driving the motor is substantially higher. This represents substantially higher available torque and higher efficiency and an improvement in performance. 
     Consider now the method depicted in FIG. 3. The method involves the use of at least one power switch, such as the transistor 12, which provides low and high impedance paths between an inductive load, such as motor winding 14, and a source of power, such as the V supply. The transistor thereby controls the current flow through the inductive load during a sequence of regular reoccurring time periods such as those depicted along the lower axis of FIG. 4. The transistor is switched, if in an &#34;off&#34; state, to an &#34;on&#34; state substantially at the beginning of at least some of the time periods to thereby provide the low impedance path. The method includes the combination of steps, operative during any one of a plurality of the time periods, for sensing a predetermined level of current flow through one of the motor winding and the transistor during its &#34;on&#34; state. In this regard, the P.W.M. control 10 determines when the current flowing through the sense resistor 20 exceeds the predetermined level (i.e., current limit, ILIM). 
     The transistor is then switched from the &#34;on&#34; state to the &#34;off&#34; state when the predetermined level of current flow has been sensed, causing the current flowing through the motor winding 14 to decay around the loop including the free wheel diode 36. 
     The power switch is then switched back to the &#34;on&#34; state after the &#34;off&#34; state, independent of the occurrence of the beginning of a time period. Preferably, as disclosed, the method depicted in FIG. 3 causes the transistor 12 to be switched back &#34;on&#34; after a delay period has elapsed following the &#34;off&#34; state. 
     Consider now the details of the method depicted in FIG. 3 in more detail. The method is preferably implemented in a P.W.M. control in a combination of a program controlled microprocessor and hardware as will be discussed in more detail. The entry is made to the flow through blocks 1 and 2 and, at block 2, symbol P.W.M. (OUT)=OFF indicates that the switch 12 is turned to &#34;off&#34;. The P.W.M. control 10 includes TIMER (PERIOD) which determines the P.W.M. period and a TIMER (DUTY) which determines the duty cycle, i.e., the &#34;on&#34; and &#34;off&#34; duty periods during each P.W.M. period. During block 3, the value PERIOD TIME is loaded into the TIMER (PERIOD) and the value DUTY TIME is loaded into the register DUTY CYCLE TIME. Subsequently, the value DUTY TIME is loaded into the TIMER (DUTY) and both timers start a count-down. Count-down of all counters is at the same rate and in synchronism with the clock pulses from clock 30 (FIG. 1). 
     Operation passes down through to blocks 4 and 5 to block 11, assuming that the TIMER (DUTY) is not initially zero, and that the current limit has not been sensed (i.e., current limit ILIM is not true). Accordingly, block 11 will be entered where P.W.M. (OUT)=ON indicates that the P.W.M. control switches transistor 12 &#34;on&#34;, providing a low impedance condition. This then switches transistor 12 &#34;on&#34; at the beginning of a P.W.M. period. 
     Control continues to pass through blocks 4, 5 and 11, maintaining the transistor 12 &#34;on&#34; until a current limit ILIM is sensed in the sense resistor 20, at which time operation passes from block 5 to block 6 where a reenable time value T1 is loaded into TIMER (RE ENABLE) and block 7, where the TIMER (RE ENABLE) is starting its count-down. Operation then passes through blocks 8 and 9, since neither of the timers indicated there have reached zero, and at block 10, the P.W.M. control again switches the transistor 12 to an &#34;off&#34; state. Operation continues around blocks 8, 9 and 10 until one of the timers reaches zero. Assume that the TIMER (RE ENABLE) reaches zero. This occurs when the delay time value loaded in TIMER (RE ENABLE) has been counted to zero, and causes a branch out of block 9 back to blocks 4 and 5 and back to block 11 where the P.W.M. control again switches transistor 12 to an &#34;on&#34; state. Since the TIMER (PERIOD) has not reached zero, setting of the switch 12 to an &#34;on&#34; state occurred within one P.W.M. period. Also since the TIMER (DUTY) has not reached zero, this also occurred within the &#34;on&#34; duty period of the P.W.M. period. 
     Assume that transistor 12 is &#34;on&#34;, as a result of a time-out of TIMER (RE ENABLE). Also assume another current limit ILIM is sensed. The operation again goes through blocks 6-10, setting the transistor 12 &#34;off&#34;. 
     If, on the other hand, the TIMER (DUTY) had reached zero, then during block 4, blocks 12 and 13 would have been entered where, assuming the TIMER (PERIOD) has not reached zero, the P.W.M. control would have set the transistor 12 &#34;off&#34; even though the current limit ILIM had not yet been reached. 
     Note that the method depicted in FIG. 3 contemplates the situation where the DUTY TIME stored in TIMER (DUTY) can range from zero up to the value of the PERIOD TIME. In a situation where the value DUTY TIME is equal to the value PERIOD TIME, the &#34;on&#34; period of the duty cycle is equal to the P.W.M. period. Under these circumstances the operation will initially pass from block 4 to block 5 and then on to block 11 where the transistor 12 is set &#34;on&#34;, providing full output current. Assuming that the current limit ILIM does not become true, the transistor will be maintained &#34;on&#34; throughout the entire P.W.M. period. The timers TIMER (DUTY) and TIMER (PERIOD) will then reach zero at the same time, the operation will branch from block 4 to block 12, then back to block 3 where the timers are reloaded and restarted, and then blocks 4, 5 and 11 will be reentered. As a result, transistor 12 will be maintained &#34;on&#34; from one P.W.M. period to the next without turn &#34;off&#34;. This is the condition depicted in FIG. 4, where in effect there is a 100% DUTY TIME for the transistor switch. A 100% duty cycle is used where desired to provide full power and full current to the winding of the D.C. motor to bring it up to speed. 
     Another condition may exist. Specifically, it may be desirable not to apply any power to the motor. This is accomplished by loading a DUTY TIME of zero into the TIMER (DUTY). When this occurs, the operation will initially pass directly from block 4 to blocks 12 and 13 where the transistor 12 will be maintained &#34;off&#34; and thus no power is applied to the motor winding. 
     FIG. 5 depicts a preferred method and embodiment of the invention where the step of switching the transistor back to the &#34;on&#34; state within the same time period is inhibited until the motor speed exceeds a predetermined value. Additionally, the delay period between the &#34;off&#34; state and the reenable condition where the transistor is switched back &#34;on&#34; within the same P.W.M. period is delayed, and the delay period is a function of motor speed. 
     The need for such an arrangement will be understood from the following discussion. At low motor speeds, current ramp-up is fast and current decay is slow, and therefore current ripple in the motor winding is low. As a result, it is not necessary to reenable or re-turn &#34;on&#34; the transistor within the same P.W.M. period and this may even be unacceptable in that it may contribute to current ramping. At medium motor speeds, it is desirable to reenable where the transistor is switched back &#34;on&#34; after an &#34;off&#34; state within the same P.W.M. period so as to increase the average current to the motor winding without current ramping. At high motor speed, the time for the reenable time can be decreased to further reduce current ripple. 
     Combining these features provides reenable control that is a function of motor speed or velocity, has the advantage that current ramping does not occur, and minimize the amount of switching of the transistor. In summary, the transistor is switched &#34;on&#34; and then switched &#34;off&#34; when a current limit through either the transistor or the motor winding is reached and the transistor is reenabled &#34;on&#34; after a time delay which varies as a function of motor speed. The turn &#34;off&#34; at current limit and the reenable can be repeated several times and may all occur within a single P.W.M. Additionally, the reenable function is inhibited until motor speed reaches a minimum level. 
     FIG. 5 illustrates the method implemented in the P.W.M. control 10 of FIG. 1 for providing the reenable inhibit at low motor speeds and for providing the variable time delay for reenable as a function of motor speed. FIG. 5 has blocks numbered the same as FIG. 3. Blocks bearing the same numbers in FIG. 5 perform essentially the same function as the corresponding blocks of FIG. 3. 
     In addition, FIG. 5 has additional blocks numbered 14, 15, 16 and 17 connected to the output of block 3 and blocks 18 and 19 sequentially connect between the output of blocks 6 and 7. 
     Inhibiting of the reenable operation at low motor speeds is performed by making a test at block 14 to determine if motor speed is below a low motor speed value A. If it is, then the reenable function is inhibited by passing through to blocks 15, 16 and 17. During block 15, the TIMER (DUTY) is checked to see if it is zero, i.e., whether the end of the duty period has been reached. During block 16, a test is made to see whether the current limit ILIM has been reached. If either test is met, a branch is taken out of the corresponding block back to block 12 where, as discussed above, if the TIMER (PERIOD) is not at zero, block 13 is entered where the transistor is set &#34;off&#34;. Assuming neither test is true in blocks 15 and 16, block 17 is entered where the transistor is switched &#34;on&#34; and the operation recycles back to the beginning of block 15. This operation will repeat, causing the transistor switch to remain &#34;on&#34; until the TIMER (DUTY) is zero, causing a branch from block 15, or if current limit ILIM is true, causing a branch from block 16 to blocks 12 and 13 where operation is as described above. 
     Assuming that the motor speed is above the low value A, operation branches from block 14 to blocks 4, 5 and 6 which are, in operation, the same blocks described with reference to FIG. 3. Following block 6, block 18 is entered where another motor speed check determines if motor speed is below the higher motor speed value of B. If the actual motor speed is less than B, the delay time stored in TIMER (RE ENABLE) is the delay period to be used, and accordingly a branch is taken around block 19 to block 7 where, as discussed with respect to FIG. 3, the TIMER (RE ENABLE) count-down starts. 
     If during block 18 it is found that the actual motor speed is larger than the higher speed value B, then block 19 is entered where the lower delay time T2 is loaded into the TIMER (RE ENABLE) and then in block 7 where TIMER (RE ENABLE) has started its count-down. Thus it will be seen that the delay period for reenable is larger when motor speed is low and lower when motor speed is higher. Theoretically, the delay time for reenable can be changed many additional times in accordance with changing motor speed. However, for most systems, only two or three reenable time changes are required to maintain an acceptable value of current ripple over the motor speed range. 
     FIG. 9 is a flow diagram illustrating an alternate method for the P.W.M. control 10, where instead of using a delay to determine the time for reenabling the &#34;on&#34; state of the transistor, the means for reenabling is based on continuous monitoring of the current flowing in the motor winding. In operation, when a current limit ILIM occurs and the transistor is switched &#34;off&#34; after an &#34;on&#34; state in the same P.W.M. period, the current in the motor winding begins to fall. By monitoring the level of the current in the motor winding, the transistor can be reenabled &#34;on&#34; after current passes through some lower selected value of current. When the selected value of current is sensed in the motor winding, the transistor is reenabled &#34;on&#34;. As a result, the operational conditions that require maximum motor current to be confined between an upper and a lower threshold, and that current ripple is to be confined, may be achieved. One advantage of this method is that more consistent current ripple control may be achieved. However, the disadvantage is that it is difficult and costly to continuously monitor current in the motor winding because of the signal conditions across the winding. 
     Referring to FIG. 9, the sensing of a selected value of motor winding current is achieved by replacing blocks 6, 7, 9, and 19 of FIG. 5 with, respectively, blocks 6&#39;, 7&#39;, 9&#39;, and 19&#39;. The remaining blocks of FIG. 9 are essentially the same in operation as those depicted in FIG. 5. 
     During block 6&#39; which follows block 5 (as described above), a LOWER LIMITS register is set or loaded with a selected current value L1. L1 represents a low current limit value. If the actual motor speed is below the higher value B, then block 7&#39; is entered where the actual current level in the motor winding is read. Subsequently, during block 9&#39;, the selected current value in LOWER LIMITS register is compared with the actual motor winding current read during block 7&#39;. If the actual current is higher, then block 10 is entered where the transistor is maintained &#34;off&#34;. Blocks 7&#39;, 8, 9&#39; and 10 are reentered, maintaining the transistor &#34;off&#34; until either the TIMER (PERIOD) reaches zero (i.e., the duty cycle times out) or the actual current read during block 7&#39; is less than the value in LOWER LIMITS register. When either of these conditions occurs, the operation branches back from blocks 8 or 9&#39; to block 4. 
     Assuming that the duty cycle is not over, operation passes through block 4 to block 5 and if a current limit has not been reached, operation passes on to block 11 where the transistor is turned &#34;on&#34;. If during block 18 the actual motor speed is found to be higher than the higher value B, then block 19&#39; is entered, before blocks 7&#39;, 8, 9&#39; and 10, where the high current limit value L2 is loaded in the CURRENT LOWER LIMIT register for comparison during block 9&#39;. 
     FIG. 6B is a schematic and block diagram of the portion of the P.W.M. control for use with microprocessor 10B for implementing the variable speed control method depicted in FIG. 5. FIG. 6B has inputs 40, 42, 43, 44 and 46 which, preferably, are inputs from the microprocessor 10B and other parts of the P.W.M. control 10. The basic P.W.M. operation is provided by TIMER (DUTY) 48, preferably a programmable monostable multivibrator. Its time-out period is controlled by the value DUTY TIME applied on line 46 by the microprocessor. To initiate the operation, the microprocessor provides a CYCLE START pulse on line 44. The leading edge of the CYCLE START pulse, as indicated in FIG. 6B, triggers the time-out operation of the TIMER (DUTY). It will now be seen that the overall frequency of the P.W.M. periods is determined by the repetition rate of the CYCLE START pulses on line 44, which in turn are synchronized with the regular occurring clock pulses. The &#34;on&#34; period of the duty cycle is determined by the time-out period of TIMER (DUTY) 48. 
     A &#34;D&#34; type output latch 50 allows the current limit and reenable controls to be implemented. The output 51 of the output latch 50 corresponds to the P.W.M. (OUT) in the flow diagram of FIG. 5. Thus when the signal at output 51 is true, transistor 12 is switched &#34;on&#34;, whereas when the signal at line 51 is false, transistor 12 is &#34;off&#34;. The output latch 50 is connected to the input line 44 on which the CYCLE START pulses are applied. The trailing edge of the CYCLE START pulse causes any clear signals to the output latch 50 from TIMER (DUTY) 48 to be removed. A zero delay comparator 52 compares the DUTY TIME on line 46, and when the DUTY TIME is zero, applies a signal at the input of output latch 50, causing the output latch 50 to maintain a false signal at the output 51. This is required where the duty period is zero and therefore the transistor is not to be turned &#34;on&#34; throughout the P.W.M. period. OR gate 53 is connected to the clear input of the output latch 50. OR gate 53 has an input connected to the line 40 on which the microprocessor applies an ILIM control signal when the current limit is reached. OR gate 53 also has an input connected to the output of TIMER (DUTY). As a result, the OR gate 53 clears the output latch to a condition providing a false output at the end of the time delay of TIMER (DUTY) 48, or when a signal ILIM appears on line 40. 
     The TIMER (RE ENABLE) 54 together with AND gate 56 controls the reenable operation. More specifically, if the reenable operation is to take place, a true signal is formed on the on/off line 43 by the microprocessor for AND gate 56. As long as the P.W.M. period has not ended by time-out of the TIMER (DUTY), it too provides a true signal to the input of AND gate 56. 
     Assume now that a current limit has been sensed in the current flowing through transistor 12 of FIG. 1. The microprocessor will apply a true signal ILIM on line 40 and will apply a reenable time value on line 42 to select the time-out period for TIMER (RE ENABLE) 54. The ILIM signal also is applied through OR gate 53 to clear or reset the output latch 50 to a state causing a false output at the P.W.M. (OUT) 51. As a result the transistor 12 is reset &#34;off&#34;. When the TIMER (RE ENABLE) 54 times out, a true signal is applied to the remaining input of AND gate 56 causing a true signal to the set input of the OUTPUT LATCH 50 which in turn causes the output P.W.M. (OUT) 51 to become true and thereby switch the transistor 12 &#34;on&#34;. Note that the duty cycle is determined by TIMER (DUTY). The true output from TIMER (DUTY) or the ILIM signal will cause OR gate 53 to clear or reset the OUTPUT LATCH 50 so as to provide a false output at 51 and thereby switch the transistor back &#34;off&#34;. 
     The control signals as indicated above may be applied directly by a microprocessor such as microprocessor 10B in the P.W.M. control 10, or a special purpose timing control unit may be employed. FIG. 6A depicts a special purpose timing control unit for applying the control signals to the input lines 40, 42, 43, 44 and 46 of FIG. 6B. A controller and sequencer 60 sequenced by a clock signal provides a basic timing and control. Control and sequencer 60 applies a control signal on the CYCLE START line 44 to initiate the operation of the P.W.M. control circuit shown in FIG. 6B. If a reenable after current limit is to be performed, then a true signal is applied on the on/off line 43. Additionally, a value, indicative of the duty cycle &#34;on&#34; time, is loaded into a DUTY TIME register 62, and is provided on line 46 to the circuits of FIG. 6B. 
     Motor winding current sensor 64 senses the magnitude of the current through the current sense resistor 20 of FIG. 1 and applies a signal representing the magnitude comparator 66. A current limit value is stored in limit register 68 and corresponds to the desired limit of current flowing through sense resistor 20 before turn &#34;off&#34; is required. The comparator 66 compares the actual motor current value from sensor 64 with the value in register 68 and provides a control signal ILIM at line 40 when the actual motor current is equal to the limit value in register 68. 
     A motor speed sensor 70 senses actual motor speed or velocity and provides a value to a comparator 72 corresponding to the actual speed. The motor speed sensor may be constructed in any one of a number of ways well known in the art. For example, it may be a tachometer and, since motor speed is proportional to motor winding voltage, preferably the motor speed sensor is a combination of a microprocessor and voltage sensing circuitry which uses winding voltage to determine motor speed. The comparator 72 has inputs connected to the outputs of registers 74 and 76 which store motor speed values. The motor speed values A and B, discussed in connection with FIG. 5, are stored in registers 74 and 76, respectfully. Comparator 72 compares the actual motor speed from sensor 70 with the values in registers 74 and 76 and forms a true signal at the output 78 whenever the actual motor speed is less than the value in register 74, and a false signal when it is greater. Comparator 72 also compares the actual motor speed from sensor 70 with the value in the B register 76, forming a control signal at output 80 when the actual motor speed is lesser and a false signal when it is larger. Gate 82 is connected to T1 register 84 and T2 register 86. Reenable time values are stored in registers 84 and 86 corresponding to T1 and T2 values described in connection with FIG. 3. When actual motor speed is not less than the value in A register 74, but is less than the value in register B, a false signal is formed at output 78 and a true signal is formed at output 80, causing gate 82 to couple the value in T1 register 84 through to the reenable line 42. If the actual motor speed value is less than the value in both the A and B registers 74 and 76, then false signals are formed at both outputs 78 and 80, and will cause gate 82 to couple the value in T2 register 86 through to the reenable line 42. 
     The control in sequencer 60 has an input from line 78, and when the signal on line 78 is true, indicating that motor speed is less than the value in A register, it forms a false signal at the output 43, disabling the reenable operation in the P.W.M. control circuitry of FIG. 6B. 
     FIG. 7 depicts an alternate P.W.M. control unit which may be implemented as a special purpose microprocessor or a general purpose processor program in accordance with the flow diagram of FIG. 5. A timing control unit 80 synchronized by clock signals forms control signals at the outputs 1-19 indicated within circles. All counters count down at the same rate in synchronism with the clock signals. The outputs of the timing control unit 80 are used as controls for various other portions of FIG. 7 and, as indicated by the corresponding numbers within circles, the numbers within circles also correspond to the flow blocks of FIG. 5. A time value is stored in the PERIOD TIME register 81 and is transferred at time 3 to the TIMER (PERIOD) counter 84. Time 3 initiates the count-down of counter 84 and when it is at zero a true signal is formed at its output which in turn is connected back to the timing and control unit 80 for sequencing its operation. A value is stored in the DUTY TIME register 86 corresponding to the load duty cycle time. Also during time 8, gate 88 gates the content of register 86 into TIMER (DUTY) counter 90 whose count-down is initiated. The output of counter 90 which receives a true signal when in a zero state is connected back to the timing and control 80. A motor speed sensing circuit 92 senses motor speed and provides a representative value to the MOTOR SPEED register 94 corresponding to motor speed. Comparator 96 compares the actual motor speed from register 94 with the A and B values in registers 98 and 100 and provides control signals at the indicated outputs indicating whether the motor speed value is above or below the value in the two registers. 
     Motor winding current sensor 102 provides an output signal indicating the value of the current in resistor 20. Comparator 104 compares the actual motor current with the current limit value ILIM in register 106 and forms a control signal at the output ILIM when the actual motor current is the larger. TIMER (RE ENABLE) counter 122 is loaded from both of registers 114 and 118 through gates 116 and 120, respectively. The control signal at time 16 causes the T1 value from register 114 to be loaded into the TIMER (RE ENABLE) 122, whereas at time 19, gate 120 loads the motor speed value T2 from register 118 into TIMER (RE ENABLE) counter 122. Counter 122, at time 7, starts its count-down operation. When the counter 122 is at zero, a true signal is formed at its output to control the timing and control unit 80. 
     Flip flop 112 has its output 113 connected to the base or input of transistor 12. When flip flop 112 is in a true state, the transistor is &#34;on&#34;. When flip flop 112 is in a false state, the transistor is &#34;off&#34;. Flip flop 112 is set to a true state by OR gate 108 during times 11 or 7. Flip flop 112 is reset to a zero state by OR gate 110 during times 10 or 12. The sequence of operation of FIG. 7 is thus depicted by the flow diagram of FIG. 5. 
     FIG. 2 depicts an alternate embodiment of the invention in which a P.W.M. control and timing sequencer 136 is controlling an electronically commutated motor (E.C.M.) system. The motor is depicted at 100 and is a brushless type motor with windings 102, 104 and 106 and a rotor 107. Each winding is schematically depicted by an inductor and a resistor such as 102a and 102b for winding 102. One side of the windings is connected together to a common junction 105. 
     The opposite end of each of the windings from the common junction 105 is connected to a totem pole type switching circuit indicated generally at 129. The totem pole switching circuit 129 includes a pair of transistors serially connected together at a junction emitter with the junction connected to the opposite ends of the windings of the motor 100 from common connection 105 of the windings. Thus, transistor pairs 110,113, 111,114, and 112,115 are connected, respectively, to the motor windings 102, 104 and 106, with the emitter junction of transistors 110, 111 and 112 connected to the collector electrodes, respectively, of transistors 113, 114 and 115. 
     Free wheel diodes are connected across the collector and emitter electrodes of each of the transistors so as to protect the transistors in a conventional manner known in the art. The anode and cathode electrodes of the diodes 120, 122, 123, 124 and 125 are connected, respectively, to the collector and emitter electrodes of transistors 110, 111, 112, 113, 114 and 115. Each of the transistor pairs 110,113, 111,114, and 112,115, is serially connected between a positive rail 130 of the V supply and a conductor 132. The conductor 132 is serially connected through a current sense resistor 134 to a rail 136, which is the zero volt or negative side of the V supply. The bases of the electrodes of each of the transistors are connected to the P.W.M. control and timing sequencer 138 which provides the sequencing, timing and control for properly sequencing the &#34;on&#34; and &#34;off&#34; states of the transistors. 
     Current is provided through each of the windings 102, 104 and 106 in sequence and in directions which rotate the rotor 107. Transistors 110, 111 and 112 couple windings to the positive rail 130, and transistors 113, 114 and 115 connect windings to the negative rail 136 through resistor 134. Two transistors, one from the group 110, 111 and 112, and one from the group 113, 114 and 115, are &#34;on&#34; at any one time so as to pass current through the motor windings in a sequence well known in the art. One of the &#34;on&#34; transistors stays on continuously and the other is controlled in accordance with the P.W.M. methods disclosed herein. 
     The preferred power supply for each of FIGS. 1, 2 and 8 is an A.C. line driven unfiltered full wave rectifier such as depicted at 139 in FIG. 2. The sine wave from the A.C. line is thus converted to an A.C. full wave rectified signal between rails 130 and 136. As a result, the multiple harmonic feedback into the A.C. lines, which is attendant with filtered power supplies, is avoided. Significantly, an embodiment of the invention using the described method avoids the need for a filtered source of power to achieve the desired motor power. 
     FIG. 2A is a schematic and block diagram of a preferred embodiment of the invention employing the E.C.M. of FIG. 2 in a laundry machine. Microprocessor 150 applies a sequence of P.W.M. control signals, using methods similar to that disclosed above, to driving circuits 152 which in turn control transistors in a totem pole bridge of the type disclosed in FIG. 2. 
     Motor windings 157 of a 3-phase D.C. brushless motor 156 cause motor armature 158 to rotate. Armature 158 is directly connected to and reciprocally rotates agitator 160 of a washing machine 162. The agitator in turn rotates spin tub 160. The washing machine is of the type where an E.C.M. motor can be directly connected to the agitator and reciprocally rotates the agitator but when the agitator rotates in one direction it picks up and drives the spin tub at the same speed. Such a washing machine is disclosed in U.S. Pat. No. 3,914,463 filed in the name of Brimer, the subject of which is incorporated herein by reference. Current limit register 164 provides the limit value for motor and/or transistor switch current and actual motor speed is provided by sensor 166 to microprocessor 150 for carrying out the method discussed above. 
     FIG. 8 depicts an alternate embodiment of the invention which senses current through the motor winding. In the embodiment of FIG. 8, motor winding current is sensed to determine when it has decayed in order to determine the reenable time for switching the transistor back to &#34;on&#34;. Additionally, the motor winding current is sensed to determine when the current limit ILIM has been reached. The system of FIG. 8 includes a transistor 130, a motor winding 132 and a current sense resistor 134 serially connected between the positive rail 136 and the negative rail 138 of V supply. A current sense circuit 140 is connected across the sense resistor 134 for determining the level of current flow and has an output connected to the input of P.W.M. control 142. The P.W.M. control 142 has another input connected to a clock 144 and an output connected to the base of transistor 130. A free wheel diode 146 is connected in parallel with the series connected resistor 134 and winding 132. 
     In operation, the P.W.M. control 142 switches the transistor 130 to an &#34;on&#34; state causing current to flow between rails 136 and 138 from the V supply, flowing through resistor 134, winding 132 and transistor 130. When the output from current sense circuit 140 indicates the current limit ILIM, P.W.M. control 142 switches the transistor 130 &#34;off&#34;. The current sense circuit 140 also monitors the decay in current through the sense resistor 134 and, when current has decayed to a selected value, P.W.M. control 142 switches the transistor 130 back &#34;on&#34;. Again, the initial turn &#34;on&#34; of transistor 130 is commenced at the beginning of a P.W.M. cycle, and the turn &#34;off&#34; and reenable to turn back &#34;on&#34;, are all performed within a single P.W.M. cycle using a method according to the present invention illustrated in FIG. 9. 
     Although this invention has been described with an inductive load in the form of a motor winding, it is to be understood that in the broader concepts of the invention, the inductive load may be a power supply or other inductive load where a P.W.M. control is desired. 
     It will also be appreciated that the V supply may be a rippling rail type of power supply without deleterious effects because of the characteristics of the method and means according to this invention. 
     Examples of values in a practical embodiment of this invention are: 
     PERIOD TIME = 100 microseconds 
     DUTY TIME = 0-100 microseconds 
     RE ENABLE time T1=30 microseconds 
     RE ENABLE time T2=21 microseconds 
     Speed A = 4,480 RPM 
     Speed B = 6,560 RPM 
     It will be understood that other types of switches may be used in place of the transistor such as a gate turn-on thyristor, it being a prime desire to minimize costs of the switches because of the large number involved in a bridge of the type shown in FIG. 2. 
     Although an exemplary embodiment of the invention has been disclosed for purposes of illustration, it will be understood that various changes, modifications and substitutions may be incorporated into such embodiment without departing from the spirit of the invention as defined by the claims appearing hereinafter.