Differential amplifier with input bias current cancellation
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to electronic amplifier circuits. In particular, the present invention relates to an improved input bias current cancellation circuit which cancels out first and second order errors while achieving a wide input voltage range. 
     2. Description of the Prior Art 
     Bias current cancellation circuits have been used in the past in amplifier circuits, particularly operational amplifiers. These circuits usually involve monitoring the input current to the differential amplifier NPN transistors, inverting the input current with PNP current mirrors, and injecting the inverted current back into the inputs of the differential amplifier. 
     The prior art bias current cancellation circuits have, in general, been successful in cancelling first order bias current errors. The biggest contributor to cancellation errors in these circuits is the second order error caused by base current difference in the current mirror PNP transistors. The base current difference is due to the low beta of the PNP transistors. 
     Another shortcoming of prior art bias current cancellation circuit has been the relatively large amount of head room consumed in order to provide input bias current cancellation. Prior art input bias current cancellation circuits typically limit the input voltage swing to within three to four volts of the power supply rails. Operational amplifiers using input bias current cancellation circuits have typically used ±15 volt supply voltages. In order to provide an operational amplifier which operates at much lower supply voltages (such as ±5 volts), there is a need for input bias cancellation which does not consume such a large amount of head room while still providing the cancellation. 
     THE SUMMARY OF THE INVENTION 
     The input bias cancellation circuit of the present invention monitors current flowing through the current source connected to a differential amplifier, replicates base currents of the differential amplifier transistors in a matched transistor, inverts the base current with a current mirror circuit, and injects that current back into the inputs of the differential amplifier. 
     The bias current cancellation circuit also includes a second order cancellation circuit which compensates for base currents of the current mirror transistors which inject current to the inputs, so that only the base current of the matched transistor affects the injected current to the inputs of the differential amplifier. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The FIGURE shows an electrical schematic diagram of an input stage of an operational amplifier having a differential amplifier and the bias current cancellation circuit of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Amplifier circuit 10, which is a part of a bipolar transistor operational amplifier, includes inputs 12 and 14 for receiving an input voltage V IN  and outputs 16 and 18 for providing an output voltage V OUT . NPN transistors Q1 and Q2 form a differential amplifier. The base of transistor Q1 is connected to input 12, while the base of transistor Q2 is connected to input 14. The emitters of transistors Q1 and Q2 are connected together to a current source formed by NPN transistors Q3 and Q4 and resistors R1 and R2. Current source resistors R1 and R2 are connected between the emitters of transistors Q3 and Q4, respectively, and negative supply voltage -V. The bases of transistors Q3 and Q4 are connected together to bias voltage V BIAS . 
     The collectors of transistors Q1 and Q2 are connected to a cascode stage formed by NPN transistors Q5 and Q6. PNP transistors Q7 and Q8 are connected to the collectors of Q5 and Q6, respectively, to provide the load for the cascode stage. Output 16 is connected to the collectors of transistors Q5 and Q7, and output 18 is connected to the collectors of transistors Q6 and Q8. The emitters of Q7 and Q8 are connected to positive power supply +V. 
     PNP transistors Q9 and Q10 and resistors R3 and R4 form a current mirror circuit which provides current to the bases of cascode stage transistors Q5 and Q6. The current being mirrored by the current mirror of transistors Q9 and Q10 is set up by transistor Q11 and resistor R5. The base of transistor Q11 is connected to the bases of current source transistors Q5 and Q6 to receive the bias voltage V BIAS . The emitter of transistors Q11 is connected through resistor R5 to negative supply voltage -V. The collector of transistor Q11 is connected through protection diodes D1 and D2 to the collector and base of transistor Q9. The current supplied to the bases of Q5 and Q6, therefore, is related to the current flowing through the current source formed by transistors Q3 and Q4, and resistors R1 and R2. 
     Input bias cancellation circuit 20 of the present invention is formed by transistors Q12-Q22, resistors R6, R7, and R8, and diode D3. 
     NPN transistor Q12 and resistor R6 are connected in a current mirror relationship with transistors Q3 and Q4. The size of transistors Q12 and resistor R6 is selected so that the collector current of transistor Q12 is equal to one half of the combined collector current of transistors Q3 and Q4. 
     NPN transistor Q13 is matched to differential amplifier NPN transistors Q1 and Q2 and is connected to Q12 so that the base current of Q13 (I BQ13 ) is equal to the base currents I BQ1  and I BQ2  of Q1 and Q2, respectively. The collector current of transistor Q13 is provided by NPN transistor Q14, which has its base connected to node 22, and therefore to the bases of cascode stage transistors Q5 and Q6. The base of transistor Q13 is connected to node 24. 
     PNP transistors Q15 and Q16 have their collectors connected to the bases of transistors Q1 and Q2, respectively. The emitters of transistors Q15 and Q16 are connected together through resistor R7 to node 22. The bases of transistors Q15 and Q16 are connected together to node 24. 
     PNP transistors Q17 and Q18 have their bases connected to node 24. The emitters of Q17 and Q18 are connected through resistor R8 to node 22. The collector of Q17 is also connected to node 24. 
     Transistors Q15 and Q16 are, therefore, connected in a current mirror relationship to transistor Q17. The collector currents of transistors Q15 and Q16 (which are supplied to the bases of transistors Q1 and Q2 to provide input bias current cancellation) mirror the collector current I CQ17  of the transistor Q17. In cancellation circuit 20 of the present invention, I CQ17  is maintained equal to the base current I BQ13  of transistor Q13. 
     Transistors Q18-Q21 provide a second order bias cancellation by ensuring that I CQ17  =I BQ13 . This is achieved by making the collector current I CQ21  of NPN transistor Q21 equal to the sum of the base currents of transistors Q15, Q16, Q17, and Q18. The collector current of transistor Q18, which is equal to the collector current I CQ17  of transistor Q17, is provided to the emitter of PNP transistor Q19. The base current of transistor Q19 is mirrored by the current mirror formed by NPN transistors Q20 and Q21 so that the collector current I CQ21  of transistor Q21 is a function of the base current of PNP transistor Q19. The transistors, particularly Q19, are scaled so that I CQ21  =I BQ15  +I BQ16  +I BQ17  +I BQ18 . Since the only other current flowing into node 24 is I CQ17  and the only other current flowing out of node 24 is I BQ13 , then I CQ17  =I BQ13  and the effects of the base currents of transistors Q15, Q16 and Q17 on the current supplied to transistors Q1 and Q2 are negated. 
     PNP transistor 22 and diode D3 ensure that the input bias current cancellation will occur despite variations in the common node voltage at inputs 12 and 14. The base of transistor Q22 is connected to the emitters of transistors Q1 and Q2. Thus, the base of transistors Q22 is one V BE  below inputs 12 and 14. In turn, the emitter of transistor Q22 is one V BE  above the base of transistor Q22. Diode De makes the voltage at node 22 two V BE  above the emitters of transistors Q1 and Q2 or one V BE  above inputs 12 and 14. The amount of current dropped across resistors R7 and R8 is relatively small, and therefore the voltages at the emitters of transistors Q15 and Q16 and at the emitters of transistors Q17 and Q18 are nearly equal to the voltage at node 22. The voltage at node 24 is one V BE  below the voltage at node 22, and therefore is approximately equal to the common mode voltage at inputs 12 and 14. As the common mode voltage at inputs 12 and 14 shifts, the voltages at nodes 22 and 24 also shift so that changes in the common node voltage will not affect operation of input bias cancellation circuit 20. 
     In a preferred embodiment of the present invention, resistors R7 and R8 are trimmable to provide further precision in cancellation of input bias current. 
     With the present invention, both first order and second order bias current cancellation is achieved. In addition, the input bias current cancellation circuit 20 of the present invention allows voltage swings of about 1.5 volts of the power supply rails. As a result, input bias current cancellation is achieved without significant sacrifices in head room, as has been the case with prior art input bias current cancellation circuits. 
     Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.