D/A converter
This application is a continuation of application Ser. No. 07/038,951 filed Apr. 16, 1987, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a D/A (Digital-to-Analog) converter and, more particularly, to a D/A converter using a two-stage binary weighted capacitor ladder network. 
     A D/A converter using a binary weighted capacitor ladder network is suitable for an integrated D/A converter. Such a D/A converter using a two-stage weighted capacitor network has advantages in a smaller number of unit capacitors, a smaller occupying area on a D/A converter IC, and low fabrication cost as compared with a one-stage weighted capacitor network. U.S. Pat. No. 4,077,035 (Feb. 28, 1978) describes a two-stage binary weighted capacitor network comprising an integrator and two similar groups of capacitors connected in parallel. However, this network requires an operational amplifier since the network includes the integrator, resulting in a complicated circuit arrangement and large current consumption. 
     Another conventional D/A converter using a two-stage binary weighted capacitor network as shown in FIG. 1 is described in &#34;Integrated PCM Codec&#34;, IEEE Journal Solid State Circuits, SC-14, PP. 38-46, Feb. 1979. This D/A converter does not include an operational amplifier. 
     Referring to FIG. 1, capacitors C 0  to C l  constitute a first stage capacitor ladder 1. These capacitors C 0  to C l  have binary weighted capacitances as follows: C 0  =1.C, C 1  =2 0 .C, C 2  =2 1 .C, C 3  =2 2 .C, . . . C l  ═2 l-1 .C where C is the capacitance of the unit capacitor. Capacitors C l+1  to C l+m  constitute a second stage capacitor ladder 2. These capacitors C l+1  to C l+m  have binary weighted capacitances as follows: C l+1  =2 0 .C, C l+2  =2 1 .C, C l+3  =2 2 .C, . . . C l+  =2 m-1 .C. The first and second capacitor ladders are coupled by a coupling capacitor C c  of a capacitance C c .C to constitute a two-stage binary weighted capacitor network. One of the electrodes of the capacitances C 1  to C l  and C l+1  to C l+m  is grounded or connected to a reference voltage V R  through a corresponding one of switches S 1  to S l  and S l+1  to S l+m . The switches S 1  to S l  are controlled by less significant l bits of a digital input signal. The switches S l+1  to S l+m  are controlled by more significant m bits of the digital input signal. The D/A converter serves as an (l+m)-bit D/A converter. 
     An output voltage V 0  of the D/A converter shown in FIG. 1 is calculated on the basis of charge conservation as follows: ##EQU1## where b k  is the coefficient of 0 or 1 determined in response to an (ll+m)-bit digital input signal, and V R  is the reference voltage. In order to arrange the circuit as the (l+m)-bit D/A converter, the coupling capacitance C c  must be given as follows: 
     
         C.sub.c ={2.sup.l /(2.sup.l -1)}C                          (2) 
    
     If equation (2) is satisfied, a substitution of equation (2) into equation (1) yields the output voltage V 0  as follows: ##EQU2## Equation (3) can be rewritten as follows: ##EQU3## therefore, the analog output voltage V 0  corresponding to the (l+m)-bit binary digital signal is obtained. The circuit in FIG. 1 serves as the (l+m)-bit D/A converter if the following condition is satisfied: 
     
         C.sub.c {2.sup.l /(2.sup.l -1)}C 
    
     However, it is difficult to obtain the coupling capacitance C c  which constantly and perfectly satisfies equation (2). 
     For example, if l=6, then 
     
         C.sub.c /C=2.sup.6 /(2.sup.6 -1)=64/63=1.01587 
    
     It is difficult to accurately obtain the C c  value, and thus precise digital-to-analog conversion precision cannot be obtained. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to eliminate the conventional drawback described above and to provide a highly precise D/A converter using a two-stage binary weighted capacitor network. 
     Accordingly, the present invention provides a D/A converter for converting a (l+m)-bit digital input signal to an analog signal, whereboth l and m are natural numbers, the D/A converter comprising a first stage capacitor ladder which converts the less significant l bits of the (l+m)-bit digital input signal and includes l capacitors having one side electrodes thereof commonly connected a first point and capacitances binary-increased from 2 0 .C 2  to 1-1 -1  C where C is a unit capacitance; a second stage capacitor ladder which converts the more significant m bits of the (l+m)-bit digital input signal and includes m capacitors having one side electrodes thereof commonly connected to a second point and capacitances binary-increased from 2 0 .C to 2 m-1 .C; a coupling capacitor having a capacitance of 1.C and connected between the first and second points; (l+m) switches connected with another side electrode of the (l+m) capacitors in one-to-one correspondence for selectively connecting the another side electrodes of the (l+m) capacitors to a first or second reference voltage in response to the C(l+m)-bit digital input signal; and a short-circuiting switch connected between the first reference voltage and the first point of the first stage capacitor ladder. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing an arrangement of a conventional D/A converter; 
     FIG. 2 is a circuit diagram showing an arrangement of a D/A converter according to an embodiment of the present invention; and 
     FIG. 3 is a block diagram showing an application of the D/A converter shown in FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A preferred embodiment of the present invention will be described with reference to the accompanying drawings. 
     FIG. 2 is a circuit diagram showing an arrangement of a D/A converter according to an embodiment of the present invention. The same reference numerals as in FIG. 1 denote the same parts in FIG. 2. Referring to FIG. 2, capacitors C 1  to C l  constitute a first capacitor ladder 3 and have binary weighted capacitances as follows: 
     
         C.sub.1 =2.sup.0.C, C.sub.2 =2.sup.1.C, C.sub.3 =2.sup.2.C, . . . C.sub.l =2.sup.l-1.C. 
    
     Capacitors C l+1  to C l+m  constitute a second capacitor ladder 2 and have binary weighted capacitors as follows: 
     C l+1  =2 0 .C, C l+2  =2 1 .C, C l+3  =2 2 .C, . . . C l+m  32 2 m-1 .C. 
     One electrode of each of the capacitors C 1  to C l  is connected to a common connecting point 5. The common connecting point 5 is connected to one terminal of a short-circuiting switch S s , the other terminal of which is grounded. The common connecting point 5 is also connected to one electrode of a coupling capacitor 6 having a capacitance 1·C. The other electrode of the coupling capacitor 6 is connected to an output terminal 8 to which one electrode of each of the capacitors C l+1  to C l+m  of the second capacitor ladder 2 is connected. The other electrode of each of the capacitors C 1  to C l+m  is grounded or connected to a reference voltage terminal 9 through a corresponding one of switches S 1  to S l+m  in response to a digital input signal. The switches S 1  to S l  are controlled by less significant l bits of the digital input signals and select a reference voltage V R  or a ground potential. The switches S l+1  to S l+m   are controlled by more significant m bits of the digital input signal and select the reference voltage V R  or the ground potential. The short-circuiting switch S s  is driven and closed while the second capacitor ladder 2 is operated. 
     The characteristic feature of the present invention lies in the facts that the capacitance of the coupling capacitor 6 is set to be 1C and the first capacitor ladder 3 includes the capacitors C 1  to C l  and the short-circuiting switch S s . 
     The operation of the D/A converter according to this embodiment will be described below. In this embodiment, D/A conversion is performed in two steps. When more significant m bits of the digital input signal are input to the second capacitor ladder 2, the switches S l+1  to S l+m  are operated. In this case, the short-circuiting switch S s  is closed and the common connecting point 5 of the first capacitor ladder 3 is grounded. At the same time, the switches S 1  to S l  select the ground potential. When the operation of the second capacitor ladder 2 is completed, the short-circuiting switch S s  is opened. The switches S 1  to S l  select the reference voltage V R  or the ground potential in response to the less significant l bits of the digital input signal. In this case, the switches S l+1  to S l+m  hold the previous operation stage. 
     The output voltage generated by the D/A converter according to this embodiment of the present invention will be described. If the output voltage is defined as V 0  &#39; when it is generated in response to the more significant m bits of the digital input signal supplied to the second capacitor ladder 2, the output voltage V 0  &#39; is calculated for the second capacitor ladder 2 as follows since the switch S s  is closed and the common connecting point 5 is grounded: ##EQU4## 
     A voltage V s  is calculated as follows when the lower bits of the digital input signal are input to the first capacitor ladder 3: ##EQU5## therefore, a final output voltage V 0a  is defined by: ##EQU6## In equation (7), since the following condition is given: 
     
         1&gt;&gt;1/2.sup.l+m 
    
     then 
     
         1/(1-1/2.sup.l+m)≈1                                (8) 
    
     Equation (7) is given in the same manner as for equation (3) and can be rewritten into equation (9) as for equation (4): ##EQU7## 
     The D/A converter according to this embodiment serves as the (l+m)-bit D/A converter. 
     An error V e  generated by approximation using equation (8) will be calculated below: ##EQU8## 
     A maximum value V em  of the error V e  is obtained for b k  =1 wherein k=1 to l: 
     
         V.sub.em =(V.sub.R /2.sup.l+m).2.sup.l.{1/2.sup.l+m -1)}   (11) 
    
     A minimum step voltage V LSB  of the D/A converter is V R  /2 l+m  and the maximum value V em  is thus given by equation (12): 
     
         V.sub.em =V.sub.LSB ·2.sup.l ·{1/(2.sup.l+m -1)} 
    
     
         ={1/(2.sup.m -1/2.sup.l)}V.sub.LSB &lt;V.sub.LSB              (12) 
    
     For example, if l=6 and m=6, 
     then 
     
         V.sub.3m ={1/(2.sup.6 -1/2.sup.6)}V.sub.LSB 
    
     
         ≈V.sub.LSB /64&lt;&lt;V.sub.LSB 
    
     Therefore, the error by approximation using equation (8) is negligible in practice. 
     FIG. 3 is a successive approximation A/D converter system as an application of the D/A converter shown in FIG. 2. Reference numeral 10 in FIG. 3 denotes an (l+m)-bit D/A converter shown in FIG. 2. The D/A converter 10 generates an output V 0 . A comparator 11 compares an analog input V IN  from an input terminal 15 with the output V 0  from the D/A converter 10. A logic control circuit 12 outputs control signal bits D 1  to D m+l  through a bus 13 so as to cause the D/A converter 10 to generate the predetermined analog output V 0 . 
     In operation of the circuit in FIG. 3, the control signal bits D 1  to D l+m  (1000 . . . 000) are supplied from the logic control circuit 12 to the D/A converter 10, and the D/A converter 10 generates an analog signal corresponding to V 0  =V R  /2. The comparator 11 compares the analog signal V 0  with the analog input V IN . If V IN&gt;V   0 , then the most significant bit (MSB) is set to be logic &#34;1&#34;. However, if V IN  &lt;V 0 , then the MSB is set to be logic &#34;0&#34;. In the next step, the bits D 1  to D l+m  are set to be a binary code &#34;1100 . . . 00&#34; or &#34;0100 . . . 00&#34;. In this case, the D/A converter 10 generates V 0  =3V R  /4 or V R  /4. The output V 0  is compared with the analog input V IN  to determine the second bit. The above voltage comparison cycle is repeated (l+m) times to determine the logic levels of the bits from the MSB to the LSB (Least Significant Bit). Therefore, the analog input V IN  is converted into the corresponding signal bits D 1  to D m+l . 
     The above operation is called successive approximation. By using this scheme, the first capacitor ladder is operated in response to the less significant bits of the input signal after the second capacitor ladder is operated in response to the upper bits, which is the characteristic feature of the D/A converter of the present invention. In this operation, no problem is presented because the less significant bits can be fixed while sequential comparison is started from the more significant bits bit by bit. In other words, a successive approximation A/D converter may be constituted by using the D/A converter according to the present invention. 
     According to the present invention as described above, in a D/A converter using a two-stage capacitor ladder network, the two capacitor ladders are capacitively coupled by a unit capacitor having the same capacitance C as that constituting the capacitor ladders. As a result, there is provided a highly precise D/A converter wherein precision of the coupling capacitance can be improved and conversion errors can be reduced.