Wattmeter comprising a hall sensor and an A/D converter
TECHNICAL FIELD 
     The invention relates to a wattmeter comprising a Hall sensor and an A/D converter, in which wattmeter said Hall sensor is used as a current transformer as well as a multiplier, and a circuit for the compensation of a temperature drift and of disturbing voltages generated in the sensor itself as well as of disturbing signals, especially of the offset voltage of the circuit, are comprised. 
     The invention belongs to the field of electric power measurements with devices using a galvanomagnetic effect, more precisely a Hall effect. The pertinent IPC designation is G 01 R 21/08. The invention also relates to the Hall sensor itself (H 01 L 43/06). The proposed solution of the object of the invention is feasible in integrated circuit technology (H 01 L 27/22). 
     BACKGROUND OF THE INVENTION 
     In recent years semiconductor Hall elements have been used for electronic measurements of electric power. The feeding current is proportional to the mains voltage and the magnetic induction is proportional to the mains current, hence the Hall voltage is proportional to the power. The Hall voltage expression is: 
     
         U.sub.H =K(T)·I.sub.N ·B=K(T)·k.sub.1 U·k.sub.2 I 
    
     with the following meanings of the designations: Hall voltage U H , feeding current I N , magnetic induction B, temperature dependent Hall coefficient K(T), mains voltage U, mains current I, and conversion coefficients k 1 , k 2 . 
     Because of the temperature dependent coefficient K(T) the Hall sensor as such is not appropriate for application in wattmeters for which high-accuracy performance in a broad temperature interval is required. 
     There are known various methods of temperature compensation, mostly using thermistors. A thermistor series-connection to the Hall element is described in the Japanese patent JP 57 121288. A deficiency of this compensation method is that the thermistor temperature dependence is different from the one of the Hall element, for which reason an exact compensation can hardly be accomplished. 
     Further, the temperature dependence of the Hall voltage is compensated with a separate measuring circuit, in which the temperature is sensed by a thermistor and a correction voltage is generated, which is added to the Hall voltage (U.S. Pat. No. 4,327,416). This is a demanding and expensive system since two separate measuring circuits and a large capacity storage unit are required. 
     The actual Hall element output voltage is very low, often below the level of disturbing voltages such as the Hall voltage originating from feeding current induction or from the quadratic term in K(T). With known voltage-frequency converters and A/D converters no signals with a level below the level of disturbing voltages can be measured. 
     It has not been possible to make high-accuracy wattmeters comprising Hall elements because of an asymmetric geometry and of a piezoresistive effect of Hall elements. By these two disturbing influences an alternating component is generated following the feeding current behaviour. In known wattmeters (e.g. JP No. 58 154263 and DE No. 30 01 772) this disturbing voltage is reduced by a special geometric disposition of differently oriented Hall elements within the Hall sensor. Voltage terminals of Hall elements are either series- or parallel-interconnected. The disturbing voltage is reduced, yet the interconnected sensor elements influence each other. On the other hand, there is known a circuit, in which to separately tapped voltages of particular elements (patent DE No. 30 26 226) offset voltages of differential transistor circuits are superposed. 
     SUMMARY OF THE INVENTION 
     In accordance with the foregoing background discussion, the object of this invention is to compensate disturbing influences as e.g. the temperature Hall voltage variation, linear or quadratic, the voltage originating from feeding current induction, the piezoresistive effect and the asymmetric geometry of particular Hall elements, whereat the complete wattmeter circuit should be capable of being produced as a single integrated circuit and should comply with the technical requirements made on such meters. 
     With the foregoing objects in view, the wattmeter according to the invention is characterized by features of the characterizing portion of the first claim. Further embodiments of the invention are evident from the dependent claims. 
     Specific embodiments of the invention will be presented in the following detailed description in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings, 
     FIG. 1 is a block diagram of the meter according to the invention, 
     FIG. 2 is the time behaviour of appearing signals, 
     FIGS. 3a-3e show a circuit of the meter according to the invention, 
     FIG. 4 is a variant solution of an impulse shaper, 
     FIG. 5 is a variant solution of a sensor circuit, 
     FIG. 6 is a block diagram of a delta modulator, which is a variant solution of an impulse-width modulator. 
    
    
     DETAILED DESCRIPTION 
     The compensation of disturbing voltages is based on dividing a measuring period into two equal time intervals. By measuring the input voltage directly in the first time interval (t 0 , t 1 ) and with a reversed sign in the second time interval (t 1 , t 2 ), the useful and the disturbing signal are added and subtracted, respectively, giving a value made free of any disturbing signal at the end of the period. The sign of the Hall voltage is reversed by a sensor circuit 1, 1&#39; by interchanging the feeding terminals of the sensor Hall elements. 
     By the block diagram in FIG. 1 and the meter circuit in FIGS. 3a, b, c, d, e, a basic wattmeter embodiment of the invention is represented. The A/D converter of FIG. 1 is shown to comprise all of the elements except sensor circuit. 
     The Hall sensor voltage U S  is generated in an adding circuit 2 by adding up voltages U S1 , . . . U SN  of the Hall elements SZ 1 , . . . SZ N , a reference voltage U R , and a compensation voltage U K  by which a disturbing voltage U M  is compensated. The voltage U S  is applied to an impulse-width modulator 3, where it is integrated by an integrator I. When the output voltage U I  of the integrator I reaches the switching level U H .sup.± of a comparator circuit ST, the sign of the output voltage U T  of this circuit is changed. Therefore the integrator voltage U I  is limited by the switching levels U H .sup.±. In the switching moment the polarity of the reference voltage U R  is changed so that the output voltage U I  of the integrator I moves around zero potential. The frequency of the voltage U T  at the output of the modulator 3 is divided by a digital frequency divider 6 with a division ratio N. By divider 6 the output voltage, which is synchronous with a signal U o , the sign of the feeding current in the Hall elements SZ 1 , . . . SZ N  is changed. 
     When the voltage U S  is different from zero, the fall and rise slope of the voltage U I  differ; for this reason the durations of the differently signed impulses in the impulse train U T  are different. The train U T  in the time interval t 1 , t 2  is inverted with respect to the train U T  in the interval t o , t 1  (FIG. 2), which is a consequence of a change of the polarity of the voltage U S  in the moment t 1 . 
     An impulse train U F  is generated at the output of an exclusive OR gate 8a in an impulse shaper 8. The ratio of the durations of differently signed impulses within the train U F  is constant. By the train U F  the counting direction (adding, subtracting) of a counter 8b counting impulses CL of a clock generator is determined. The content of this counter increases with an increasing modulation factor, i.e. the ratio of the durations of differently signed impulses within the train U F . A digital trigger 8a forms a frequency signal from the numerical counter content. This signal is conducted through a latch 8d to the output U OUT  when its frequency is higher than the frequency of the signal from a digital frequency divider 7 with a division ratio M. 
     The appearance of a DC disturbing voltage U M  is the reason why the durations of the differently signed impulses are different also when the input voltage U S  is zero. This fact is used for the compensation of this disturbing voltage. A counter 4a, whose counting direction is determined by the voltage U T , will have a content in the moment t 1  different from the content in the moment t 2 , if the disturbing voltage U M  is present; this represents a measure of the level of the disturbing voltage U M . At each transition of the signal U o  from the state 1 to the state 0 the content of the counter 4a is stored in a latch register 4b, whose output is connected to the digital input of a D/A converter 4c. The converter 4c generates the compensation voltage U K  in dependence on the state of the latch 4b. The content c 4a  of the counter 4a will increase until the disturbing voltage U M   is compensated by the voltage U K . 
     In FIG. 2 there are also shown: 
     a signal TR which triggers the transfer of the binary content 
     c 4a  in the latch register 4b at each change of the signal U o  from the state 1 to the state 0; 
     the compensation voltage U K  at the output of the D/A converter 4c, this voltage U K  being proportional to the content c 4a  of the counter 4a; 
     the content c 8b  of the counter 8b, being reset when a maximal value is reached; 
     the output signal U OUT  of the digital trigger 8c; the trigger 8c is set into the state 1 when the content c 8b  for the first time reaches a half value C S , and is returned into the state 0 when the content c 8b  reaches its maximum C R  ; 
     the content c 4a  which at the moment of the transfer represents a measure of the level of the disturbing voltage U M . 
     The temperature compensation is accomplished by an approximation of the temperature dependence of the Hall voltage U S  (T) by the temperature dependence of the voltage U R  (T) of a CMOS bandgap. In this way it is tried to reach the temperature independence of the ratio U S  (T)/U R  (T). The precision curvature compensation CMOS bandgap reference is used (B.-S. Song, P. R. Gray, IEEE Journal of Solid-State Circuits, 634-648, 18 (1983)), approximating the voltage U S  (T) linearly and quadratically. 
     A sensor circuit 1 is provided with controlled CMOS switches SO 1 , . . . SO 4  (FIG. 3) interconnected into a bridge. The sign of the feeding current I N  is controlled by the signals C, D, opposite in phase and obtained from the frequency divider 6. The frequency input terminal of the current I N  enters the bridge from the mains phase terminal S (through a resistor R) and flows through the second input terminal of the bridge back to the mass-connected mains zero terminal 0. The Hall elements SZ 1 , . . . SZ N  are connected in parallel to the output diagonal of the bridge. Diodes D 1 , D 2  protect against an over-voltage. 
     A reference voltage source 4 applies a base-emitter voltage U BE  of a transistor Q3 and a voltage ΔU BE , i.e. the difference of base-emitter voltages of transistors Q1, Q2. The emitter area of the transistor Q1 is A-times the emitter area of the transistor Q2. The emitter current of the transistor Q1 is the difference of the currents from a temperature independent current source TI 1  and a current source PTAT 1 , whose current is proportional to temperature. The emitter current of the transistor Q2 is a sum of currents from sources TI 2  and PTAT 2 . By the ratio of the currents from TI 2  and PTAT 2  a quadratic term in the temperature dependence is determined. Therefore by changing the currents from PTAT 1 , PTAT 2  the temperature dependence of the reference voltage U R  (T) can be set at will. The transistor Q3 is fed from a temperature independent current source TI 3 . The reference voltage U R  (T) is set by capacitors C a , C b  and is given by the following expression: ##EQU1## The adding circuit 2, made as a switching capacitor circuit, tapes the Hall element voltages by the capacitors C 1 , . . . C N , the reference voltages U R  by the capacitors C a , C b , and the compensation voltage U K  by the capacity of the D/A converter 4c. The electronic switches are controlled by non-overlapping reversing signals E, F (FIG. 4e). The total charge fed into the modulator 3 by the capacitors C 1 , . . . C N , C a , C b  and 4c at a single switching of the switches S 11 , . . . S N2  is ##EQU2## A linear temperature dependence is set by the capacity ratio of the capacitors C a , C b . 
     A rhythmic reversing of the reference voltage polarity is performed by changing the polarity of the voltages U BE , ΔU BE  with a switching commutator, which is provided with switches S K1 , . . . S K8 . Said switches are controlled by the output signals A, B of the modulator 3. 
     The impulse-width modulator 3 is provided at its input side with an integrator I comprising an operational amplifier A 1  with a backcoupling capacitor C1. The integrator output voltage U I  is brought to the input of the comparator circuit ST, which reverses its output voltage at the threshold voltages U H .sup.±. A synchronization with clock impulses CL is performed by a flip-flop D1, which at the transitions of the impulse CL from 0 to 1 transfers the state of the comparator circuit ST to the output Q of the flip-flop D1, representing the modulator 3 output. The inverted signal is generated at at the output Q of the flip-flop D1. 
     The impulse shaper 8 transforms the impulse-width modulated signal into the output signal U OUT , the frequency of which is proportional to the measured electric power. The influence of the reversing of the signal U I  polarity is removed by an exclusive OR gate 8a. The first input of the gate 8a is connected to the Q output of the modulator 3, the second one, however, is connected to the output of the digital frequency divider 6. By the obtained signal U F  the counting direction of the up/down counter 8a, by which the impulses CL are counted, is determined. The counter content is increased depending on the modulation factor of the signal U F . Said content can be transferred to a computer and is a measure of the measured energy. When the output signal of the counter is needed in the form of impulses, a digital trigger 8c, provided with gates AND1, AND2 and an RS cell, is connected to the outputs Q n , Q n-1  of the counter 8b. When the counter content reaches the half value for the first time, the output of the cell RS1 is changed to the state 1; this is kept to the moment when the maximum counter content is reached, whereafter the cell output is returned to the state 0. The signal at the output Q of the cell RS1 is compared to the signal at the output of the divider 7, whose frequency is the frequency of the modulator 3 divided by M. By a flip-flop D3 it is transformed into impulses with a width equal to that of the impulse CL and with a frequency equal to that of the signal at the divider 6 output. 
     The latch 8d consists of two binary frequency dividers K, L with division ratios K and L, respectively. To the counting input C of the divider K the output signal of the counter 8b is conducted, to the reset input R, however, the reference signal from the flip-flop D3 is conducted. At the divider L both said signals are interchanged. The outputs of the dividers K, L are connected to the input R and S, respectively, of the cell RS2. The output signal U OUT  is transmitted by a logic gate AND3 only when its frequency is higher than the frequencies set by the frequency dividers M, K, L. 
     By the compensation circuit 4 with the counter 4a, whose direction of counting the impulses CL is determined by the modulator 3 output voltage U T , the presence of a DC disturbing voltage in the measuring signal is detected. As long as the disturbing voltage is not compensated by the voltage U K  from the D/A converter 4c, the content c 4a  of the counter 4a at the moment t 2  differs from the one at the moment t o . This difference is therefore a sign of a non-compensated disturbing voltage presence. For this reason at each end period of the polarity reversal of the input signal a new content of the counter 4a is transferred to the latch register 4b through exclusive OR gates E1, . . . En. An order signal TR for the transfer of the content c 4a  into the latch register 4b is generated by a D flip-flop 4e D2 by forming the impulse CL on its output Q whenever the signal D changes from 1 to 0. At the negative polarity of the disturbing voltage the content of the counter 4a is lowered. Therefore the output Qm+1 takes the state 1 and, as a consequence thereof, the outputs Q o , . . . Qm are inverted by gates E1, . . . Em, respectively. The binary signal D value in the digital latch register 4b is determined by the capacity C K  of the circuit 4c representing together with switches S 8 , S 9  a feedback for the compensation of the disturbing voltage. The circuit 4c is represented in FIG. 3d. The level of the compensation voltage U K  of the reference voltage source 4d is determined by a resistor R K  and by current sources I + , I - , and the polarity of the voltage U K  is determined by switches S 10 , S 11 , controlled by the output of the counter 4a. 
     A clock generator 10 is provided with a crystal oscillator Q. Its clock impulses CL provide a time base synchronizing the digital logic. Non-overlapping signals E, F controlling the CMOS switches are formed by the impulses CL. The time behaviour of the signals E, F is represented in FIG. 3e. An equivalent circuit for the controlled CMOS switch with a control terminal O and with connecting terminals G, H is shown in FIG. 3c. 
     A further embodiment of an impulse shaper 9 is represented in FIG. 4, which is adapted to reading off the content of the counter 9a by a computer through a shift register 9b. When the signal TR is in the state 1, the content of the counter 9a is transferred into the shift register 9b. Synchronously to the signal CL the content of the shift register 9b is transferred to the output OUT, whenever a signal TR from the computer is delivered to the register 9b. 
     When a higher consumption can be provided for the electronic circuit of the meter according to the invention, in the sensor circuit 1&#39; an operational amplifier A3 is used (FIG. 5). Because of the amplifier A3, the Hall voltage terminal of the last sensor SZ N  is at zero potential. Thus a voltage drop across the feeding part of the sensor is twice as high as in the basic embodiment, at the same time, however, the common voltage of both Hall terminals (&#34;common mode&#34; component) with respect to the ground of Hall voltages U S1 , . . . U SN  is strongly reduced. The reversing of the Hall voltage polarity is performed like in the basic embodiment by switching controlled switches SO1, . . . SO4, which are interconnected to a bridge whose second input terminal is connected to the output of the amplifier A3. 
     As an alternative to the impulse-width modulator 3 a delta modulator 3&#39;, shown in FIG. 6, can be applied. The modulator 3&#39; is provided with a comparator K instead of the comparator circuit ST, switching at the zero level. The frequency of reversing the reference voltage polarity is increased by applying the modulator 3&#39;; thereby the conversion accuracy is slightly reduced, the capacity, however, of the capacitor C 1  in the modulator 3&#39; is far smaller than in the modulator 3. At the integrated meter circuit according to the invention this is an advantage since the capacitor C 1  takes up considerable space. In this embodiment the divider 6 is connected to the clock generator 10. 
     An advantage of the wattmeter according to the invention exists above all in that it makes possible the use of the Hall sensor for measurements of as high accuracy as it is required at electric wattmeters. A further advantage exists in that voltages of individual Hall elements are tapped separately, thus reducing the piezoresistive effect and the effect of the Hall element asymmetry as well as preventing the mutual disturbances present at parallel or series voltage tapping in known circuits. The wattmeter according to the invention is also advantageous in that the meter circuit occupies little space, its power consumption is low and the essential circuit parts are capable to be produced in CMOS technology on a single wafer.