Method and apparatus for extracting an auxiliary data clock from the clock and/or the clock-phase of a synchronous or plesiochronic digital signal
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method and to an arrangement for extracting an auxiliary data clock from the clock and/or the clock phase of a synchronous or plesiochronic digital signal. 
     2. Description of the Prior Art 
     From the incoming digital signals at the inputs of devices for transmitting or processing digital signals, their clock must be recovered. A corresponding clock recovery facility TR is disclosed, for example, as a block in FIG. 4 of the periodical &#34;telecom report&#34;, Vol. 9, No. 3, 1986, pp. 190-197. 
     The clock frequency of the plesiochronic digital signals correspond to a nominal value, with a slight relative deviation, the permissible maximum value of which is typically of the order of magnitude of a few times 10 -5 . As far as can be technically implemented, the clock frequency of synchronous signals in the mean corresponds accurately to a nominal value. Interfering influences in electric circuits and on the transmission path have the effect that the instantaneous frequency of synchronous signals also slightly deviates from the nominal value. Therefore, there is no significant difference between the two types of signals with regard to the problem of clock recovery. Therefore, the illustrative embodiments of the present invention are restricted to plesiochronic signals. 
     SUMMARY OF THE INVENTION 
     The present invention has the object of providing a method and an apparatus for carrying out the method which can be exclusively implemented by way of logic circuits, for example in gate arrays or cell arrays. Test from calibration work should not be required. It should be possible to utilize inexpensive semiconductor technology such as complementary-metal-oxide-semiconductor (CMOS) technology even with digital signals of a high bit rate, such as 34 Mbit/s. 
     Starting with a method of the type initially set forth, the above object is achieved, according to the present invention, by the fact that an auxiliary clock is generated, the frequency of the clock being selected as a single or multiple factor of the nominal value of the frequency of the digital signal with the addition of either a positive or negative frequency deviation which is greater than a permissible frequency deviation, multiplied by the value of the single or multiple factor, of the digital signal but at a maximum 10% of the frequency, multiplied by the single or multiple factor, of the digital signal. The invention is also characterized in that the auxiliary clock has a frequency within the range of a single factor of the nominal value of the frequency of the digital signal and is used directly as an auxiliary data clock and the auxiliary clock having a frequency within the range of a multiple factor of this nominal value is used as an auxiliary data clock after a frequency division by a dividing factor equal to the multiple factor the nominal value. A check is made as to whether the active edges of the digital signal and of the auxiliary data clock have approached each other to less than a defined time interval. In such a case, a single correction signal is generated and the generation of further correction signals is inhibited. After the occurrence of a correction signal, the phase of the auxiliary data signal is shifted by polarity reversal in such a manner that the time interval between the active edges of the digital signal and of the auxiliary data clock is greater than the defined time interval. After conclusion of the phase correction process and any frequency division, the inhibition of the generation of correction signals is canceled and a new check is made as to whether the active edges of the digital signal and of the auxiliary data clock have again approached each other to less than the defined time interval and that, in such a case, the generation of a signal correction signal, the inhibition of further correction signals, the shifting and the check are repeated. 
     The auxiliary data clock is used for clocking the digital signal containing the data in a known manner, for example with the aid of a D-type flip-flop, in a circuit following the phase recovery circuit. Depending on the technology used, this is done by way of the positive or negative edge of the auxiliary data clock which is then called the active edge. It is of no importance to the invention which of the edges is used. 
     An advantageous variation of the method of the present invention lies in the fact that auxiliary clocks are extracted from the auxiliary clock which have the same frequency with respect to one another, but different phase relationships, that the auxiliary clock or one of the extracted auxiliary clocks having a frequency within the range of the single factor of the nominal value of the frequency of the digital signal is used directly as an auxiliary data clock and the auxiliary clock or one of the extracted auxiliary clocks having a frequency within the range of a multiple factor of the nominal value is used as an auxiliary clock after a frequency division by a dividing factor equal to the multiple factor of the nominal value and that the phase shifting of the auxiliary data clock is effected by switching between the extracted auxiliary clocks and/or by polarity reversal of the auxiliary clock or of the extracted auxiliary clocks. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects, features and advantages of the invention, its organization, construction and operation will be best understood from following detailed description, taken in conjunction with the accompanying drawings, on which: 
     FIG. 1 is a basic circuit diagram of a clock recovery circuit constructed in accordance with the present invention; 
     FIG. 2 is a circuit diagram of a clock recovery circuit constructed in accordance with the present invention; 
     FIG. 3 is a pulse diagram for the phase sensor of FIG. 2; 
     FIG. 4 is a pulse diagram for the phase correction facility according, to FIG. 2; 
     FIG. 5 is a basic circuit diagram of a second illustrative embodiment of a clock recovery circuit constructed in accordance with the invention; 
     FIG. 6 is a pulse diagram for the clock recovery facility according to FIG. 5; 
     FIG. 7 is a basic circuit diagram of a third illustrative embodiment of a clock recovery circuit constructed in accordance with the present invention; 
     FIG. 8 is a pulse diagram for the clock recovery circuit according to FIG. 7; and 
     FIG. 9 is a basic circuit diagram showing four clock recovery facilities according to the present invention in a digital signal multiplex device. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, a basic circuit diagram illustrates a clock recovery facility constructed in accordance with the present invention. The clock recovery circuit comprises an auxiliary clock generator 6, a phase correction device 7, a phase sensor 1 and, possibly, a frequency divider 12, and a resetting device 16. 
     The auxiliary clock generator 6 generates an auxiliary clock HT and, possibly, further auxiliary clocks HT1, HT2, . . . HTn, which are extracted from the auxiliary clock HT and have the same frequency, but differing phase relationships with respect to one another. 
     The phase correction device 7 receives, at its input or its inputs 8, the auxiliary clock HT and/or the extracted auxiliary clocks HT1, HT2, . . . HTn and selects, under the control of the correction signal K at a correction signal input 9, one of the auxiliary clocks or reverses the polarity of one of the auxiliary clocks. The result is a corrected auxiliary clock kHT at an output 10. Depending on the dimensioning, this is either supplied directly to an output 18 and is there called an auxiliary data clock DHT or is supplied to an input 13 of a frequency divider 12 and is emitted as an auxiliary data clock BHT only at the output 15 of the latter. 
     The phase sensor 1 consists of a circuit, the output of which changes from a state of rest to a correction state when the active edge of the auxiliary data clock DHT approaches one edge of the digital signal DS to less than a fixed predetermined time interval Δt. Since the instantaneous frequencies differ slightly from the clock of the digital signal DS and from the auxiliary data clock DHT, this state will invariably occur after a certain time. 
     The change from the rest state to the correction state results in a single phase correction of the corrected auxiliary clock kHT in such a manner that the clock edges which are active for the subsequent frequency divider 12 are advanced in time if the auxiliary clock frequency f, which is possibly divided by V, is slower than a frequency F of the digital signal DS, and in such a manner that the clock edges active for the subsequent frequency divider 12 are retarded in time if the auxiliary clock frequency f, divided by V, is faster than the frequency F of the digital signal DS. 
     Therefore, a phase correction has the effect that one period of the auxiliary data clock DHT generated by the frequency divider 12 is shortened or extended, depending on whether the auxiliary clock frequency f is too slow or too fast. As a result, the time interval between the active edges of the auxiliary data clock DHT and the edges of the digital signal DS increases to a value which is greater than the value Δt. 
     Due to the frequency difference between the clock of the digital signal DS and the auxiliary data clock DHT, the edges approach each other again and the process is repeated as described above after the interval drops below the time interval Δt. 
     If resetting does not occur automatically at the phase sensor 1, a resetting device 16 is also provided which receives from the reset signal outputs 11 and 14 of the phase correction device 7, after phase correction and frequency division, reset signals R1 and R2 which it then supplies at the output 17 as a reset signal R to the reset input 4 of the phase sensor 1. Apparatus constructed in accordance with the present invention provides the possibility of digital clock recovery even with digital signals DS, the frequency of which approaches the processing speed of any semiconductor technology used. The phase sensor 1, the phase correction device 7, the frequency divider 12 and the resetting device 16 can be implemented as an integrated circuit 19. 
     FIG. 2 illustrates a clock recovery circuit according to FIG. 1 for a single factor of the nominal value of the frequency F of the digital signal DS at the input 2 and a phase correction PK=180° by means of polarity reversal. 
     The phase sensor 1 comprises a delay device 20, an EXCLUSIVE OR gate 21, an AND gate 22 and a D-type flip-flop 23. 
     FIG. 3 illustrates the operation of the phase sensor 1 according to FIG. 2. The top pulse diagram is the digital signal DS at the input 2. The second pulse is designated A and represents the signal DS delayed by the delay device 20. The third pulse B is the output signal of the EXCLUSIVE OR gate 21, to the inputs of which the digital signal DS and the pulse A were applied. The fourth pulse C is the result of ANDing the digital signal DS with the pulse B in the AND gate 22. The fifth pulse is the auxiliary data clock DHT at the input 3 of the phase sensor 1. The active edges of the auxiliary data clock DHT are marked by an arrow. The D-type flip-flop 23 emits the correction signal K at an output Q which is the output 5 of the flip-flop 23 when a pulse C coincides in time with an active edge of the auxiliary data clock DHT, which is indicated by the sixth pulse diagram. 
     The phase correction device 7a in FIG. 2 comprises a D-type flip-flop 24, an EXCLUSIVE OR gate 25, an RS flip flop 26 and an OR gate 27. 
     FIG. 4 shows the operation of the phase correction device 7a according to FIG. 2. The top pulse is the auxiliary clock HT emitted by a crystal oscillator 28a in the auxiliary clock generator 6, at an input 8 of the phase correction device 7a. The second pulse is the correction signal K at an input 9 of the phase correction device 7a. The third pulse X is the signal at an output Q of the D-type flip-flop 24 which operates as a toggling stage. The fourth pulse Y is the output signal of the EXCLUSIVE OR gate 25, while the fifth pulse Z is the signal at the Q output of the RS flip-flop 26 and the sixth pulse is the auxiliary data clock DHT at the output 10 of the phase correction device 7a. 
     FIG. 5 illustrates another variation of the clock recovery circuit according to the present invention and in accordance with FIG. 1 of a multiple factor V=2 of the nominal value of the frequency F of the digital signal DS and a phase correction PK=90°. The arrangement differs from that according to FIG. 2 by a crystal oscillator 28b which outputs an auxiliary clock HT of twice the frequency f compared with the frequency of the auxiliary clock HT in FIG. 2. Additionally, a frequency divider 12a for a dividing ratio 2:1 is also connected to follow the output 10 of the phase correction device 7a. A resetting device 16a contains a delay section 29, an EXCLUSIVE OR gate 30 and an RS flip-flop 31. 
     A reset device 16a becomes necessary when the transit times of the flip-flops and of the gates are no longer negligibly small with reference to the clock of the digital signal DS. The RS flip-flop 31 is set and, in further consequence, the D-type flip-flop 23 is reset when the D-type flip-flop 23 emits a correction signal K at its output Q to the output 5. The D-type flip-flop 23 is held in this state as long as the logic state at the output Q of the RS flip-flop 31 is &#34;H&#34;. The RS flip-flop 31 remains in this state until the output Q of the D-type flip-flop 24, that is to say the pulse X, changes its state as a consequence of the correct signal K. This change results in a polarity reversal of the pulse at the output of the EXCLUSIVE OR gate 25 and therefore the desired phase correction. After the change of state of the pulse phase X, the phase correction is therefore completed. The change of state of the pulse X results in a pulse at the input R of the RS flip-flop 31 by way of the delay device 29 and the EXCLUSIVE OR gate 30. This causes the flip-flop 31 to be reset again and in further consequence the D-type flip-flop 23 to be enabled. 
     FIG. 6 illustrates the operation of the phase correction device 7a. The first six pulses correspond to those in FIG. 4, the seventh pulse is the auxiliary data pulse DHT which results from the corrected auxiliary clock kHT by division in the frequency divider 12a. 
     FIG. 7 illustrates another variation of the clock recovery facility according to the present invention in accordance with FIG. 1 for a single factor V=1 of the nominal value of the frequency F of the digital signal DS and a phase correction PK=4×90°. The arrangement differs from that of FIG. 2 by having another auxiliary clock generator 6 and another phase correction device 7b. 
     The auxiliary clock generator 6 comprises a crystal oscillator 28c and a subsequent frequency divider 29 for a dividing ratio 2:1 which emits two auxiliary clocks HT1 and HT2 shifted by 90°. 
     The phase correction device 7b comprises a plurality of EXCLUSIVE or gates 33-36 AND gates 37-40, and OR gate 41, a plurality of D-type flip-flips 42-45 and a NOR gate 46. 
     FIG. 8 illustrates the operation of the EXCLUSIVE OR gates 33-36 which, with the 1 shown, generates four auxiliary clocks φ1-φ4, which are shifted by 90° with respect to one another, at the other input in each case from the auxiliary clocks HT1 and HT 2. One of these auxiliary clocks φ1-φ4 in each case can be passed through a first input of one of the AND gates 37-40 and the OR gate 41 as an auxiliary data clock DHT to an output 18. The D-type flip-flops 42-45 and the NOR gate 46 act as a control facility which applies a logic state &#34;H&#34; to one of the second inputs of the AND gates 37-40 in each case. 
     If a correction signal K appears at an input 9, all of the D-type flip-flops 42-45 pass the logic state at the D input to the Q output. If a logic state &#34;L&#34; is present at the Q output of the D-type flip-flops 42-45, the NOR gate 46 passes a logic state &#34;H&#34; to the D input of the D-type flip-flop 42. This logic state is shifted through the NOR gate 46. This logic state is shifted through the D-type flip-flops 42-45 with the corrections signals K until the NOR gate 46 again outputs a logic state &#34;H&#34; with new logic state &#34;L&#34;. 
     FIG. 9 illustrates the multiplexer section of a digital signal multiplex device. The arrangement comprises a plurality of amplifiers 47-50 and 60, a clock recovery device 51-54, buffers 55-58, a multiplexer 59 and an auxiliary clock generator 6 including a crystal oscillator 28c, and a pair of frequency dividers 61 and 62. 
     The clock recovery devices 51-54, without auxiliary clock generators, buffers, 55-58 and the multiplexer 59 can be combined as an integrated circuit 63. The clock recovery circuits 51-54 can, in each case, correspond to that of FIG. 7, but only a single auxiliary clock generator 6 is required. 
     The reference characters Dl-D4 designate data, that is to say digital signals DS1-DS4 of the clock of which has been corrected by the clock recovery devices 51-54. The reference characters LT1-LT4 designate read clocks and the reference character DS5 designates a digital signal of the next higher hierarchy level which contains the digital signals DS1-DS4. 
     Although I have described my invention by reference to particular illustrative embodiments thereof, many changes and modifications of the invention may become apparent to those skilled in the art without departing from the spirit and scope of the invention. I therefore intend to include within the patent warranted hereon all such changes and modifications as may reasonably and properly be included within the scope of my contribution to the art.