Vertical tracking circuit
The invention relates to a control circuit of a deflection circuit in which an amplitude of a deflection current varies in accordance with a control voltage. 
     In a typical television receiver, for example, a B+voltage is applied to a primary winding of a horizontal flyback transformer for energizing a horizontal deflection circuit that generates a deflection current in a horizontal deflection winding. An ultor voltage is provided from a high voltage retrace pulse voltage developed in a tertiary winding of the flyback transformer. 
     An AC mains supply voltage provides an input power to a power supply regulator that produces the B+voltage at a regulated nominal value. When regulation operation is normal, a change in the mains supply voltage may have only a negligible effect on the B+ voltage. However, when the mains supply voltage is lower than a lower limit of a nominal range, the regulator may not be capable of stabilizing the B+ voltage at the same nominal value as when the mains supply voltage is within its normal range. The result is a decrease in the horizontal deflection current amplitude. Consequently, the raster width will decrease relative to when the AC mains supply voltage is within its normal range. 
     To prevent an undesired change in the horizontal-to-vertical proportional dimension of an image that is displayed on the CRT, it may be desired to decrease a vertical deflection current in a vertical deflection winding, when, for example, the aforementioned decrease in the B+ voltage occurs. In this way, the same proportion of such image that is displayed on the CRT is maintained after the decrease in the B+ voltage occurs. 
     In a deflection circuit, embodying an aspect of the invention, a control voltage, produced from a trace voltage during a horizontal trace interval that is developed in a secondary winding of the flyback transformer, is applied to a control terminal of a vertical deflection circuit. The control voltage controls the amplitude of the vertical deflection current. A decrease, for example, in the B+voltage causes a corresponding decrease in the control voltage that, in turn, causes a decrease in the amplitude of the vertical deflection current that is proportional to the decrease in the amplitude of the vertical deflection current. The decrease in the control voltage tends to reduce the aforementioned raster distortion in the proportional dimensions. 
     In a deflection circuit, embodying an aspect of the invention, that includes a Miller feedback arrangement, a given decrease in the control voltage results, proportionately, in a larger decrease in the vertical deflection current. It may be desirable to provide a better compensation so as to prevent the aforementioned raster distortion in the dimensional proportions of the displayed image that occurs when the B+voltage decrease. To that end, it may be desirable to decrease the aforementioned control voltage proportionally less than the decrease in the B+voltage. Thus, better compensation of the vertical deflection is provided than had the proportional decrease of both been, for example, the same. 
     A television deflection apparatus, embodying an aspect of the invention, includes a source of a first supply voltage and a horizontal deflection circuit coupled to the first supply voltage. The deflection circuit generates a horizontal deflection current in a horizontal deflection winding at an amplitude that changes when a change in the first supply voltage occurs. A first control voltage that is indicative of an amplitude of the horizontal deflection current is generated. The first control voltage changes when the change in the horizontal deflection current occurs. A vertical deflection circuit responsive to a second control voltage that varies with the change in the horizontal deflection current produces a vertical deflection current in a vertical deflection winding. The vertical deflection current is at an amplitude that is determined in accordance with the change in the amplitude of the horizontal deflection current. A change in the second control voltage causes the vertical deflection current to proportionally change by an amount that is different from the proportional changes in the second control voltage. When the change in the horizontal deflection current occurs, the proportional change in the second control voltage is different from the proportional change in the horizontal deflection current. 
    
    
     The sole FIGURE illustrates vertical and horizontal deflection circuits and a control voltage generating circuit, embodying an aspect of the invention. 
     The sole FIGURE illustrates a horizontal deflection circuit 100 that generates an output supply voltage V that is applied, via a control voltage generating circuit 102, embodying an aspect of the invention, to a vertical deflection circuit 101. 
    
    
     In circuit 100, an AC mains supply voltage V AC  is coupled to a bridge rectifier BR. Rectifier BR generates an unregulated supply voltage V UR  that is coupled to a regulator 12. Regulator 12 generates a regulated B+voltage at a terminal 11. Horizontal deflection circuit 100 includes a flyback transformer T having a primary winding W1 that is coupled between output terminal 11 of regulator 12 and between a collector electrode of a horizontal transistor switch Q1, operating at a horizontal deflection rate. The collector of transistor 01 is also coupled in a conventional manner to a horizontal deflection winding L H , to a retrace capacitor C R  and to a damper diode D1. 
     A baseband television signal 150 obtained from a video detector, not shown in the FIGURE, is coupled to a stage 13 that includes a sync separator. The sync separator generates a signal H s  containing the horizontal synchronizing information of signal 150. Signal H s  is applied to a horizontal oscillator and driver stage 14 that produces a horizontal rate control signal 15 for controlling the switching operation of transistor Q1 that is synchronized to signals H s  and 150. 
     As a result of the switching operation of transistor Q1, an ultor voltage U is generated from a corresponding retrace voltage developed in a tertiary winding W3 of flyback transformer T and a supply voltage V of, for example, +25 volts is developed from a corresponding trace voltage developed at a secondary winding W2. Each of voltage V, voltage U and a deflection current i y  in winding L H  is directly proportional to the B+voltage. 
     As long as voltage V AC  is within a predetermined normal range, the B+voltage that is regulated is substantially the same. Outside the normal range, and in particular, below a lower limit of the normal range of voltage V AC  that is required by regulator 12, the B+voltage, and hence voltage V, and currente i y , are at corresponding levels that are smaller than when voltage V AC  is within the normal range. The proportional change in each of voltages V and U and of current i y  is approximately the same. 
     In vertical deflection circuit 101, that operates as a Miller feedback arrangement, supply voltage V is applied to a supply voltage receiving terminal 18a of an integrated circuit (IC) ICI, such as the IC LA7831, manufactured by Sanyo Corporation. Integrated Circuit ICI includes a vertical amplifier 18 having a push-pull driver stage. Amplifier 18 is responsive to an input signal 19 produced in a negative feedback loop at an inverting input terminal 16. An output terminal 17 of amplifier 18 is coupled to one end terminal of a vertical deflection winding L V  that conducts a deflection current i v . A second end terminal, a terminal 20, of winding L V  is coupled through a DC blocking capacitor C V  to a deflection current sampling resistor R s  that is coupled to a common potential, referred to herein as ground. During each vertical trace interval trace, a voltage 22 developed at a terminal 21 across resistor R 2  is a downramping voltage that changes in a sawtooth manner and that is indicative of the waveform current i v . 
     Resistors R10 and R11 that provide a DC feedback in deflection circuit 101 are coupled in series between terminal 20 and between a terminal 23 of a Miller integrating capacitor C10. A capacitor C11 that provides S-correction is coupled between ground and a junction terminal of resistors R10 and R11. A resistor R12 and a capacitor C12 are coupled in series between a second terminal 24 of capacitor C10 and terminal 21 of resistor R s  to provide linearity correction. A resistor R13 is coupled between ground and a junction terminal of resistor R12 and capacitor C12. A diode D3 that provides a fast discharge path for discharging capacitor C10 during vertical retrace is coupled between terminal 24 and ground. A resistor R14 is coupled between terminal 24 and a wiper terminal of a resistor R15 to provide vertical size control. Resistor R15 forms with a resistor R16 a series arrangement that is coupled across resistor R s . 
     A pulse generator that is included in stage 13 generates vertical rate signal V RES , in accordance with the corresponding vertical synchronization pulses of signal 150. A transistor switch Q2 operates at a vertical rate in accordance with vertical rate signal V RES . A collector electrode of transistor Q2 is coupled via a resistor R17 to terminal 23 of capacitor C10. The emitter electrode of transistor Q2 if grounded. Resistor R17 controls a discharge rate of capacitor C10 during vertical retrace that is partially discharged when transistor switch Q2 is conductive. A terminal of resistor R17 that is remote from terminal 23 of capacitor C10 is coupled to a noninverting input terminal of a pre-amplifier 26. Pre-amplifier 26 has an output terminal that is coupled to input terminal 16 of amplifier 18 to complete the negative feedback loop. 
     Supply voltage V that is generated in circuit 100 is also applied to a control terminal 102a of control voltage generating circuit 102, embodying an aspect of the invention, that generates a control voltage 10 at an output terminal 102b. Voltage 10 is couple via a resistive voltage divider formed by resistors R30 and R31 to an inverting input terminal 25 of pre-amplifier 26 for developing a control voltage V 25  that controls the amplitude of vertical deflection current i v . Voltage 10 is coupled to a supply voltage receiving terminal of pre-amplifier 26 for energizing pre-amplifier 26. Pre-amplifier 26, resistors R30 and R31 and transistor Q2 are included in an IC TA7777P made by Toshiba Corp. 
     When transistor switch Q2 becomes conductive and vertical retrace is initiated, capacitor C10 is discharged through transistor switch Q2©resistor R17 and forward biased diode D3. The forward voltage of diode D3 develops a voltage V c10  in capacitor C10 having an initial nonzero voltage at the end of retrace. Transistor Q2 becoming nonconductive, in accordance with signal V RES , causes vertical trace to begin. During vertical trace, capacitor C10 is charged via resistor R11. 
     Assume, for the sake of explanation, that a voltage V c11  in capacitor C11 remains the same during the entire vertical deflection interval. Although such assumption ignores a variation of voltage V c11  that provides S-correction, such variation is relatively small. Voltage V c11  is applied to capacitor C10 during a given vertical trace, to generate a current i c10  that charges capacitor C10 during the vertical trace. Due to the negative feedback arrangement, a voltage V 23  at terminal 23 of capacitor C10 that is coupled to a noninverting input terminal of pre-amplifier 26 is maintained substantially equal to voltage V 25  developed at inverting input terminal 25 of pre-amplifier 26. Voltages V 23  and V 25  are equal because of the low offset voltage of pre-amplifier 26. Since voltages V 25  and V c11  are constant in a given vertical trace, voltage V c10  across capacitor C10 increases in a generally upramping, linear manner. To maintain the voltages at the input terminals of pre-amplifier 26 substantially the same, the feedback arrangement causes vertical amplifier 18 to generate a downramping portion 28 of a vertical sawtooth voltage V v . Voltage V v  produces deflection current i v  that flows in winding L v . Vertical current i v  develops corresponding voltage 22 across resistor R s  that is a downramping voltage. The sum of downramping voltage 22 applied to the bottom of capacitor C10 and unramping voltage V c10  in capacitor C10 is maintained constant by the negative feedback loop, as described before. Consequently current i v  also changes in a linear manner, in accordance with the rate of change of voltage V c10 . The rate of change of voltage V c10  is determined by the level of current i c10 . Current i c10  is determined by the voltage at terminal 24 of capacitor C10. 
     The initial nonzero value of voltage V c10  in capacitor C10, after transistor Q2 becomes nonconductive, is determined by the forward voltage drop of diode D3, as explained before. That initial nonzero value of voltage V c10  causes current i c10  been zero. 
     As a result of the negative feedback, a smaller value of voltage V 25  at terminal 25 of pre-amplifier 26 caused by a decrease of the B+voltage will cause the voltage at terminal 24 of capacitor C10, at a given instant of vertical trace such as immediately after transistor Q2 turns off, to be smaller than prior to such decrease in voltage V 25 . However the reduction in the voltage at terminal 24 is proportionally, larger in magnitude than in voltage V 25 . The proportional reduction in the voltage at terminal 25 is larger because the voltage at terminal 24 is less positive than voltage V 25  as a result of the level shifting caused by the initial nonzero value of voltage V c10 . Consequently, current i c10  and deflection current i v  will decrease by a larger proportional decrease than voltage V 25 . If follows that a decrease in voltage V 25 , resulting from, for example, a decrease in the B+voltage, causes proportionally a larger decrese in the amplitude of vertical deflection current i v . 
     Since voltage V decreases proportionally the same as the B+voltage induced decrease in horizontal deflection current i y , it may be desirable to decrease control voltage 10, proportionally, less than the proportional decrease in voltage V. In this way, the decrease in vertical deflection current i v  becomes porportionally equal to that of horizontal deflection current i y  for maintaining the width-to-height ratio of an image on the raster constant. 
     To obtain the aforementioned ratio constant, supply voltage V is coupled to a series arrangement of resistors R18 and R19 and a zener diode D4. A junction terminal between resistors R18 and R19, operating as a voltage divider of voltage V, is coupled to a base electrode of a transistor Q3. Transistor Q3 operates as an emitter follower. Control voltage 10 is developed at the emitter of transistor Q3, in accordance with a base voltage V bQ3 . Voltage bQ3 is approximately equal to the sum of the voltage across zener diode D4 and of the voltage across resistor R19. In this way control voltage 10 includes a first portion that remains constant when voltage V changes and a second portion that changes when voltage V changes. Thus supply voltage V operates as a control voltage of circuit 102. 
     Assume, hypothetically, that mains supply voltage V AC  decreases below a lower required for proper regulation in regulator 12. Consequently, the B+voltage will have a value that is lower than the nominal value obtained during normal operation. Therefore, the value of each of deflection current i y  and supply voltage V will decrease in a corresponding proportion that is approximately the same for each and that is referred to hereinafter as the first proportion. The decrease in current i y  will cause the length of an electron beam sweep in the horizontal direction on the CRT, not shown in the FIGURE, during a corresponding portion of each of the scan lines in which an image is displayed to decrease as well. If the length of the electron beam sweep in the vertical direction in which the image is displayed during a corresponding portion of vertical trace does not decrease in the same proportion as current i y , a proportionality distortion will occur. In order to prevent such distortion in a horizontal-to-vertical length ratio of the image that is displayed on the CRT at such low mains supply voltage V AC  , it may be desirable to decrease the amplitude of vertical current i v , proportionally, the same as the aforementioned first proportion. In this way, the horizontal-to-vertical length ratio of the displayed image will remain the same despite the decrease in the B+voltage. 
     In accordance with an aspect of the invention, circuit 102 generates control voltage 10 that decreases proportionally less than the aforementioned first proportion. In this way, the aforementioned effect on the image proportion caused by diode D3 is compensated. 
     The ratio between the values of resistors R18 and R19 and the value of the voltage across zener diode D4 provide two circuit parameters that may be, for example, empirically selected for maintaining unchanged the required horizontal-to-vertical length ratio of the displayed image at two corresponding levels of voltage V. One level of voltage V may be selected to be the nominal or normal operation value. The second one may be selected to be the value that corresponds with a predetermined low amplitude of voltage V AC  . When voltage V assumes a value that is between the aforementioned two levels of voltage V, compensation is also obtained. Advantageously, the compensation provided by circuit 102 is better than were control voltage 10 to change proportionally the same as the change in the B+voltage.