Maximum duty cycle limiting of pulse width modulators
FIELD OF THE INVENTION 
     The present invention relates to electronic power converters and more particularly to an apparatus for controlling the maximum pulse width duty cycle generated by pulse width modulators controlling such power converters. 
     BACKGROUND OF THE INVENTION 
     In some power converters, particularly those including isolation transformers, it is mandatory to limit the maximum duty cycle generated by the converter&#39;s pulse width modulator. 
     The duty cycle of the pulse width modulator output signal (which controls power converter &#34;on-time&#34;) must be limited to a certain maximum which, to avoid damage or failure, may not be exceeded under any condition; transient or steady state. This possibility for damage is due to the transformer&#39;s inability to demagnetize at large duty cycle ratios and it emphasizes the importance of accurately setting the maximum duty cycle value. 
     FIG. 1(a) illustrates a prior art pulse width modulator as implemented for example by the Unitrode UC3825 high speed PWM controller. 
     As shown, the Unitrode PWM function is performed by comparator 1 which receives as one input a voltage V 1  derived from an error amplifier (not shown), and as a second input, a sawtooth signal V 2  (illustrated in FIG. 1(b)) which is generated by an oscillator (not shown). 
     The two inputs cause the output of the PWM comparator to be high as long as the sawtooth voltage V 2  is lower in amplitude than the error voltage V l , and to be low when the sawtooth voltage V 2  exceeds the voltage V 1 . 
     The duty cycle δ is mathematically defined as: ##EQU1## where t on  is the time interval when the output of the PWM comparator is high, and T is the entire period of the signal. 
     Viewing FIGS. 1(b) and 1(c), the duty cycle δ at the output of the Unitrode PWM modulator is varied from zero to unity as the value of the error voltage V 1  varies from less than the lowest value of sawtooth voltage V 2  (i.e. V valley ) to more than the highest value of sawtooth voltage V 2  (i.e., V peak ). 
     To limit the maximum duty cycle to a value lower than unity, the prior art method limits V 2  by applying a voltage clamp 2 to the PWM comparator input. A circuit implementation of this method is shown in FIG. 1(a) where a diode 3 and adjustable source 2 are used to set a clamp level, V clamp . A waveform illustrating the method is shown in FIG. 1(c). 
     Assuming for illustration that the value of V clamp  is made equal to V peak  /2, and that the forward drop of diode 3 is negligible, then under these conditions the Unitrode maximum duty cycle will be limited to 50%. 
     This method of duty cycle limiting, although simple, is extremely inaccurate. The duty cycle calibration is affected by several factors that vary from circuit to circuit, and also vary for a given circuit as the ambient temperature and the supply voltage of the circuit changes. 
     These factors include: 
     Initial accuracy and temperature stability of V clamp  ; 
     Initial accuracy and supply/temperature stability of V peak  ; 
     Initial accuracy and supply/temperature stability of V valley  ; 
     Initial value and supply/temperature stability of the response time of comparator 1. 
     The cumulative effect of the above variations may be very significant. They may amount to a sizeable tolerance in the maximum duty cycle setting. Accommodation of this tolerance requires trade offs in the design of the converters that adversely affect performance parameters such as power density, efficiency and cost. 
     It is therefore one object of this invention to provide an improved technique in power conversion circuits for limiting the maximum duty cycle of a pulse width modulator to an accurate value. 
     It is still a further object of the present invention to provide accurate PWM duty cycle limiting circuits which vary within close tolerances from circuit to circuit. 
     It is yet a further object of the present invention to provide an accurate PWM duty cycle limiter which is virtually unaffected by temperature and circuit voltage changes. 
     SUMMARY OF THE INVENTION 
     The invention may generally be described as a technique for use in power conversion systems employing a pulse width modulated (PWM) system control signal, for accurately and stably setting the maximum duty cycle of the PWM signal. The technique employs: 
     (a) means for generating a reference PWM signal having a preset duty cycle representing a maximum value; 
     (b) means for comparing said reference PWM signal with said system PWM signal such that the maximum duty cycle of the latter is determined by that of the former. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1(a) is a schematic diagram which depicts a prior art PWM circuit. 
     FIG. 1(b) is an illustration of a sawtooth timing signal V 2 . 
     FIG. 1(c) is an illustration of how the PWM signal output by the circuit shown in FIG. 1(a) compares to the sawtooth timing signal shown in FIG. 1(b). 
     FIG. 2 is a schematic diagram which shows a preferred embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 2 illustrates a preferred embodiment wherein a sawtooth timing signal V 2  is fed to the inverting inputs of comparators 1 and 2. Supplying the non-inverting input of comparator 1 is output voltage V 1  of an error amplifier (not shown). 
     The outputs of comparators 1 and 2 are fed to the inputs of AND logic gate 3. In addition, the output of comparator 2 is connected to its non-inverting input via an integrator 4 implemented with an operational amplifier A having an input resistor Ri and a feedback capacitor C i . The non-inverting input of integrator 4 receives a DC voltage V ref , derived from resistive divider 5 (R 1 , R 2 ) connected across the circuit&#39;s supply voltage V cc . 
     In operation, comparator 1 generates a pulse width modulated signal PWMout by comparing the sawtooth timing signal V 2  to the output voltage of the error amplifier. 
     The second comparator 2 also generates a PWM signal, in this case as a result of the sawtooth timing signal v 2  at one input and the output of integrator 4 at the other. 
     AND gate 3, which receives the outputs of the two PWM comparators, provides an output PWMout dominated by that comparator (1 or 2) which produces the lower duty cycle signal. 
     The comparator circuit parameters in the preferred embodiment are chosen to provide a voltage swing from close to V cc  when in the &#34;high&#34; state to near zero in the &#34;low&#34; state. Consequently, the average, V av , of the voltage V 3  at the output of the second comparator 2 is the product of the voltage V cc  and the duty cycle of comparator 2. Thus: 
     
         V.sub.av =V.sub.cc ×δ.sub.2                    (2) 
    
     The duly cycle, δ 2  of comparator 2 is a function of the voltage at its non-inverting input. This input is the output of the integrator 4. 
     The output of integrator 4 is such as to null its input, that is, to provide at its inverting input, a voltage whose average value is substantially equal to its non-inverting input, V ref  : 
     The latter is given by: 
     
         V.sub.ref =V.sub.cc ×R.sub.1 /(R.sub.1 +R.sub.2).    (3) 
    
     Thus, at steady state, the output of, integrator 4 will cause PWM comparator 2 to generate a signal V 3  whose average value, V av , equals V ref . That is ##EQU2## 
     Eliminating the V cc  term on both sides of (4) yields: ##EQU3## 
     As a result, and since V av  is applied to gate 3, the maximum duty cycle δ max  selected at the output of the gate is equal to δ 2  which is limited to a constant and accurate value. This constant and accurate value is independent of variations in the supply voltage, sawtooth parameters or response delays in the comparators. In effect, the actual value of the maximum duty cycle will be determined solely by the ratio of two resistances which can be preset or rendered adjustable. 
     If for any reason the minimum and maximum voltage values of comparator 2 do not have the previously described relation to V cc , then appropriate compensation can be made in the selection of R 1  and R 2 . 
     In practice, very accurate and stable ratios of resistors are easily attainable with discrete, printed or integrated resistors. 
     After considering the embodiment disclosed here, it will be apparent to those versed in the art that the illustrated maximum duty cycle limiting technique shown can be employed by various modifications of the disclosed embodiment without departing from the spirit of the invention. These may include, for example, changing the logic from positive to negative, using alternate timing waveforms, employing duality, etc.