Buried zener diode
BACKGROUND AND FIELD OF THE INVENTION 
     This invention relates to an improved buried zener diode, in particular one providing minimal adverse consequences caused by series resistances. 
     Parasitic series resistances in the terminals have plagued buried zener diodes which limit the performance of the device. The fact that the zener diode is buried beneath the surface of the wafer increases these series resistances. Furthermore, these resistance values and temperature coefficients can vary from device to device according to process variations. These values and temperature coefficients are also affected by variations in power supply voltages, causing further unpredictable changes in the series resistances. 
     One prior art way to overcome the series resistance problem is by reducing the current through the diode. The less the current, the less the undesirable voltage changes which result from these series resistances. However, low current results in higher zener noise, an undesirable side effect. 
     A buried zener diode of the prior art is shown in FIGS. 1 and 2. The undesirable series resistances R 1  and R 2  lie between the N+ region 10 and the P+ region 11. When current is passed through the device, voltage drops through the series resistance and results in the voltage between the terminals 10 and 11 being different from the actual intrinsic breakdown voltage of the zener diode. 
     One way used in the prior art to reduce the effects of these voltage drops is called a &#34;force-sense buried zener&#34;. This type of zener, shown in FIGS. 3 and 4, employs three terminals, an N+ terminal 13, a P+ sense terminal 14 and a force terminal 15. The primary current flow is between force terminal 15 and terminal 13, while the high resistance path flows to sense terminal 14 to minimize the adverse effects of the series resistance. However, even in this solution, there is still some resistive coupling between force terminal 15 and sense terminal 14, so the effects of the series resistances are not completely eliminated. 
     In applications where very low noise, low temperature drift and high power supply rejection is required, but where there are likely to be changes in the series resistances caused by process variations or temperature changes, these prior art solutions are insufficient. This invention provides a buried zener diode where the disadvantage created by these series resistances is almost completely eliminated. 
     Briefly, the improved zener diode of this invention comprises a semiconductor wafer having a primary surface and a zener diode having a PN junction buried beneath that surface. A pair of spaced P+/N+ contacts for the diode are located on the surface of the wafer, the first located on a first region of the surface and the second located on a second region of the surface laterally spaced from the first, the contacts establishing a current path through the diode across the PN junction. 
     The device of the invention also employs what is termed a &#34;replica device&#34;, formed in the same semiconductor wafer, which generally replicates the physical dimensions of the zener diode. The replica device has a pair of spaced surface contacts with a replica current path between them having substantially the same on-resistance as the current path of the zener, the replica current path replicating the current path through the zener except that it has no PN junction in the current path. 
     Finally, the diode of the invention has a means coupling the replica device with the diode in a manner such that the voltage across the replica device is subtracted from the voltage across the diode to generate a difference voltage whereby, when current is simultaneously passed through the diode and the replica device, this difference voltage will be substantially independent of changes in the series resistance of the anode/cathode current path of the diode caused by variations in the wafer manufacturing process and by changes in the ambient temperature or applied voltage at which the diode is being used. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a cross-sectional view of a buried zener diode of the prior art; 
     FIG. 2 is a top, plan view of the prior art zener diode shown in cross-section in FIG. 1; 
     FIG. 3 is a cross-sectional view of another buried zener diode of the prior art; 
     FIG. 4 is a top, plan view of the prior art zener diode shown in cross-section in FIG. 3; 
     FIG. 5 is a cross-sectional view of the buried zener diode and replica device of the invention; 
     FIG. 6 is a top, plan view of the circuit of the invention shown in FIG. 5. 
     FIG. 7 is a schematic circuit diagram showing the connections between the buried zener diode and the replica device of the invention; and 
     FIG. 8 is a schematic circuit diagram showing the connections between the buried zener diode and the replica device of another embodiment of the invention which uses an operational amplifier. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIGS. 5 and 6, the construction of the buried zener diode and replica device of the invention will be explained. Using conventional CMOS technology, the high resistivity P- wells 20 and 21 are formed in silicon semiconductor substrate 22. In the preferred embodiment, substrate 22 is N-type, high resistivity material, as indicated by the &#34;N-&#34; designation. P-type wells 20 an 21 also are high resistivity material as indicated by the &#34;P-&#34; designation. P+ region 23 for the buried zener diode 35 and P+ region 24 for the replica device 25 are formed at the same time by the diffusion or implantation of P-type impurities into the wafer. N+ region 26 of the buried zener diode, forming the buried zener PN junction 27 with P+ region 23, is formed by diffusion or implantation of impurities, preferably simultaneously with the formation of N+ region 28 which surrounds P+ region 24 of replica device 25. 
     At the time it is originally formed, N+ region 28 of the replica device, which may be a single doughnut shaped region which surrounds region 24, has the same lateral dimensions and looks very much like N+ region 26 of zener diode 35. During the formation of N+ regions 26 and 28, a mask is employed covering the surface of the wafer over the replica device at region 24, thereby preventing the diffusion of the N-type impurities into region 24. In the next step, P+ contact regions 29 (for the zener diode), and 30 (for the replica device) are formed by diffusion or implantation. The heavy concentration of P-type impurities creating low resistivity regions 29 and 30 which allow the attachment of metal contacts 32 and 33, such as aluminum, as is well known in the art. Region 24 of the replica device already is heavily doped, permitting the attachment of a good ohmic contact 34 without additional P-type diffusion or implantation. Ohmic contact 36 is attached to N-type region 26 of the zener. 
     To operate the buried zener diode 35 and the replica device 25, a current is applied to the zener diode 35 between contacts 32 and 36. To reverse bias the PN junction 27 between regions 23 and 26, as is well known in the art, a positive current is forced into contact 36 so that a negative voltage develops between contacts 32 and 36. The same polarity current is also passed through the replica device between contacts 33 and 34, resulting in a positive voltage being developed between contacts 33 and 34. In the case of zener diode 35, the PN junction 27 becomes reversed biased, operating in the conventional manner. However, since there is no PN junction between contacts 33 and 34 of the replica device, there is no such reverse biasing. Instead, the replica device merely provides a resistive path (shown as resistor 42) between contacts 33 and 34 which, since the geometry of the replica device 25 is a substantial copy of the geometry of the zener diode 35, provides the same resistive path as provided by the zener diode in the forward biased direction between contacts 32 and 36 (shown as resistor 41). 
     This operation will be better explained referring to the circuit shown in FIG. 7. In FIG. 7, current source 40 supplies current both to zener diode 35 and to replica device 25. The current I 1  from current source 40 is divided between current I 3  through resistor 41 and zener diode 35, and the current I 2  through replica device 25. Resistor 41 represents the series on-resistance between contacts 32 and 36 of the zener diode 35 shown in FIGS. 5, 6 and 7. Resistor 42 of the replica device 25 represents the corresponding resistance between contacts 33 and 34 shown in FIGS. 5, 6 and 7. 
     Using the circuit of the invention, the replica device 25, having substantially the same physical dimensions as the zener diode 35, provides the same resistance, which tracks the zener series-resistance with process and temperature variations. In the operation of the circuit shown in FIG. 7, the currents to be generated by current sources 40 and 43 are selected so that when the voltage generated across replica device 25 is subtracted from the voltage generated across the on-resistance 41 in the zener path, the difference will be zero. The voltage generated by these two corresponding series-resistances are subtracted from one another so that the output voltage V out  shown in FIG. 7 is substantially independent of these resistances. Any drop across them is cancelled out since the two voltages are subtracted from one another, and V out  remains equal to the intrinsic zener breakdown voltage from device to device, irrespective of process variations which might otherwise affect these resistors and thus the output voltage V out . Moreover, the temperature and power supply variation effects of the current sources on series resistances 41 and 42 also cancel themselves out because they affect both these resistors in exactly the same way. 
     The use of the circuit of this invention eliminates variations caused by series resistances in zener diode 35. Furthermore, the current through the replica device and the zener diode is independently controlled using current sources 40 and 43 to trim out any slight mismatches between resistors 41 and 42 in the event that these resistances, as formed, are not identically equal. By thus adjusting the current I 1 , it is possible to achieve precisely zero equivalent resistance. 
     In the operation of the circuit of FIG. 7, a constant current is applied to the N+ contact of the zener diode through terminal 36. The same current is applied to the replica device through terminal 34. In a preferred embodiment of the invention, the current I 1  from current source 40 is 2.3 times the current I 3  flowing through zener diode 35. The remainder of the current I 1  from source 40 is passed through the replica device 25, and is equal to 1.3 times I 3 , the current through zener 35. The use of a current ratio different from 1-to-1 may be required because the actual zener diode breakdown occurs at a single point in the central area of PN junction 27 shown in FIGS. 5 and 6, which has a higher resistance than that of the corresponding area of the replica device which, due to photolithography limitations, cannot be confined to a single point. This difference in current restriction causes the series resistance 42 to be slightly lower in the replica device 25 than in the diode 35. To compensate for this limitation, a lower current I 3  is used across the diode 35 than the current I 2  across the replica device 25. 
     An alternative embodiment of the circuit of the invention is shown in FIG. 8. In that embodiment, instead of connecting the replica device 25 between the cathode of the zener diode and V out , it is connected across operational amplifier 50. In the circuit of FIG. 8, the replica device 25 is connected in the feedback loop of operational amplifier 50. Mathematically, this connection is equivalent to the connection shown in FIG. 7. Since an ideal operational amplifier has infinite gain, the potentials at the two input terminals 51 and 52 are forced to be equal by the feedback of the amplifier. In the circuit of FIG. 8, the voltage on the non-inverting input terminal 51 is established at the zener voltage on the N+ terminal of the zener diode, and is thus the breakdown voltage of the zener diode plus the voltage drop across resistor 41. Because of the feedback in operational amplifier 50, the inverting input 52 of operational amplifier 50 is also at the zener voltage at terminal 51. The output of the amplifier, V out , is therefore equal to the voltage at terminal 51 less the voltage drop across replica device 25. Since the resistor 42 of the replica device 25 and resistor 41 of the zener 35 are calculated to achieve the same voltage drop, the output voltage V out  will be unaffected by relative changes in the zener on-resistance 41 and the resistance 42 of replica device 25 because these will cancel each other out in the manner discussed above. 
     The manufacture of the integrated zener diode and replica device of the invention uses conventional MOS techniques, preferably CMOS. These techniques are described in European Patent No. 0,082,331, which is incorporated herein by reference. The only special considerations in the design of the zener and replica devices of this invention not explained in this reference is the need to mask region 24 shown in FIGS. 5 and 6 during the diffusion of N-type impurities to form regions 26 and 28, so that there will be no PN junction within P-type region 24. 
     As will be apparent to one skilled in the art, the N-type and P-type regions may be reversed to obtain opposite polarity type structures. Moreover, many other variations in the arrangement of the regions of the buried zener diode and replica device and in the process for its manufacture, well within the skill of the art, may be made and still remain within the intended scope of the invention, which should be limited only as set forth in the claims which follow.