PWM inverter apparatus for controlling rotating magnetic flux in a.c. motors
BACKGROUND OF THE INVENTION 
     This invention relates to a PWM inverter apparatus, and more particularly to a gate signal generating method and device suitable for controlling a rotating magnetic flux in an a.c. motor driven by a PWM inverter. 
     A manner of control is called PWM control when a three-phase inverter driving an a.c. motor is controlled by a pulse-width modulated (PWM) gate signal. In the case of the so-called PWM control, it is known that such a PWM gate signal is generated on the basis of a detected rotating magnetic flux in the a.c. motor which is the load of the three-phase inverter or on the basis of an externally-applied rotating magnetic flux command. 
     JP-A-No. 59-25592 describes a method of controlling an output voltage vector of an inverter driving a load such as an induction motor by detecting a rotating magnetic flux in the induction motor, comparing this detected rotating magnetic flux with a predetermined reference rotating magnetic flux and, when the former deviates from the latter, correcting the error to zero. 
     JP-A-Nos. 61-227696 and 62-16092 describe a method of controlling an output voltage vector of an inverter by setting a vector of a virtual rotating magnetic flux related to that of a reference rotating magnetic flux, comparing these vectors and, when the former deviates from the latter, correcting the error to zero. 
     The control of the inverter output voltage vector is also described in JP-A-58-39278 corresponding to U.S. Pat. No. 4,488,215 in addition to JP-A-61-22769 and JP-A-62-16092 cited above. According to the disclosures of these publications, six voltage unit vectors v and two zero vectors v 0  determined by combination of on-off states of the inverter&#39;s switching elements of three-phase bridge arrangement are suitably combined to control the output voltage vector of the inverter. 
     However, in the case of the prior art method and apparatus for controlling the inverter output voltage vector on the basis of the deviation of the detected rotating magnetic flux from the reference rotating magnetic flux, a magnetic flux detector for detecting the rotating magnetic flux is necessarily required, resulting in a complicated structure of the apparatus. 
     Also, in the case of the prior art method and apparatus for controlling the inverter output voltage vector on the basis of the deviation of the detected rotating magnetic flux from the reference rotating magnetic flux, as well as the prior art method and apparatus for controlling the inverter output voltage vector on the basis of the deviation of the virtual rotating magnetic flux vector from the reference rotating magnetic flux vector, the sequence of processing from the step of data sampling for detecting the deviation to the step of controlling the voltage vector must be carried out at the same time, that is, the sequence of processing must be substantially instantaneously executed so as to prevent degradation of the accuracy of control. Therefore, high-speed processing means is necessarily required in order to follow up the rotating magnetic flux command to attain the desired control with high accuracy. In other words, there arises the problem that the accuracy of control is inevitably restricted by the speed of processing. Another problem is that the PWM switching frequency is limited by the processing period described above and cannot be increased. 
     Further, because the voltage vectors are selected so as to confine all the instantaneous errors within an allowable range, and the switching elements of the inverter are turned on-off on the basis of the selected voltage vectors, the order of turning on-off the switching elements of the individual phases, that is, the switching mode is irregularly changed. Therefore, there arises the problem that the switching frequency of the inverter&#39;s switching elements per unit time cannot be predicted for the control purpose. This problem exerts a great influence on the selection of the switching tolerance determined in relation to the heat tolerance of the switching elements of the inverter. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a PWM inverter apparatus and a gate signal generating method and device, in which a PWM inverter gate signal can be generated while following up a rotating magnetic flux command with high accuracy and without being restricted by the prior art requirement for provision of high-speed processing means for generating the PWM gate signal. 
     Another object of the present invention is to provide a gate signal generating method and device for a PWM inverter apparatus, in which the switching frequency can be predicted to attain the desired control. 
     Still another object of the present invention is to provide a PWM inverter apparatus and a gate signal generating method and device for the PWM inverter apparatus, in which the frequency of the gate signal is increased so as to minimize appearance of ripples in the inverter output voltage and to decrease noise generated in a load of the PWM inverter. 
     In accordance with one aspect of the present invention which attains the above objects, there is provided a PWM inverter apparatus used for driving an a.c. motor, comprising: inverter means including an output part connected to the a.c. motor and switching elements on-off controlled by a PWM signal; means for receiving, at an interval of a given sampling period, status command information specifying a desired status of a vector of a rotating magnetic flux in the a.c. motor; means for predicting, on the basis of at least the status command information received and sampled at each sampling time, the status of the vector of the rotating magnetic flux which will be produced in the a.c. motor at next sampling time; means for calculating the difference between the status of the vector of the rotating magnetic flux specified, by the status command information sampled at the present or current sampling time and the predicted status of the vector of the rotating magnetic flux which will be produced at next sampling time; means for synthesizing the difference vector using ones selected from among a plurality of predetermined reference voltage vectors; and means for generating a PWM signal for controlling the switching elements of the inverter means so as to produce the selected reference voltage vectors. 
     There are two methods for predicting the magnetic flux vector which will be obtained by sampling at the next sampling time. The sampling period is very short. Therefore, in the first predicting method, the difference between the magnetic flux vector which will be obtained by sampling at the next sampling time and the magnetic flux vector obtained by sampling at the current sampling time is regarded to be substantially equal to the difference between the magnetic flux vector obtained by sampling at the preceding sampling time and the magnetic flux vector obtained by sampling at the current sampling time. On the other hand, in the second predicting method, the magnitude of the magnetic flux vector which will be obtained by sampling at the next sampling time is regarded to be substantially equal to the magnitude of the magnetic flux vector obtained by sampling at the present sampling time, and the magnetic flux vector which will be obtained by sampling at the next sampling time is regarded to be equal to the magnetic flux vector obtained by rotating the magnetic flux vector, obtained by sampling at the present sampling time, by an angle corresponding to the rotation angle of the magnetic flux vector. In the case of the latter predicting method, the means used in the former predicting method for calculating the difference between the magnetic flux vector obtained by sampling at the preceding sampling time and the magnetic flux vector obtained by sampling at the present sampling time can be directly used for calculating the difference between the magnetic flux vector predicted to be obtained by sampling at the next sampling time and the magnetic flux vector obtained by sampling at the present sampling time, by merely changing the input data. Thus, the former predicting method will be principally described hereinafter. 
     The plural reference voltage vectors described above include six voltage unit vectors v and two zero vectors v 0 . The six voltage unit vectors are such that their directions determined by the combinations of the on-off states of the inverter&#39;s switching elements of three-phase bridge arrangement are shifted by an angle of 60° relative to each other, and the magnitude of each of these six vectors is a unit voltage. The magnitude of each of the two zero vectors is zero. 
     In an embodiment of the present invention, the difference vector e between a magnetic flux vector obtained by sampling the preceding sampling time and that obtained by sampling at the present sampling time is calculated each time the sampling is effected, and two voltage unit vectors v i  and v j  nearest in direction to the difference vector e are selected to synthesize the difference vector e according to the following equation: 
     
         e=αv.sub.i +βv.sub.j 
    
     where α and β are hold times of the voltage unit vectors v 1  and v j  respectively. 
     On the basis of the two voltage unit vectors and their hold times described above, the switching mode of the switching elements of the inverter is determined. 
     The result of synthesis of the difference vector and the magnetic flux vector obtained at the present sampling time provides the predicted magnetic flux vector which will be obtained at the next sampling time, and this latter magnetic flux vector is delayed from the magnetic flux vector obtained at the present sampling time, by a period of time T S  given by the following equation: 
     
         T.sub.S =α+β 
    
     Therefore, in order that the synthesized vector coincides with a magnetic flux vector corresponding to a magnetic flux command which will be sampled at the next sampling time, the next sampling must be effected at time later by T S  from the present sampling time. Thus, it may be necessary to change the sampling period at each sampling time. 
     In a second embodiment of the present invention, the sampling period T S  is maintained at a predetermined value. First, as in the case of the first embodiment, two voltage unit vectors v i , v j  and their hold times α, β are selected so as to synthesize the difference vector between a magnetic flux vector obtained at preceding sampling time and a magnetic flux vector obtained at the present sampling time. When the relation T S  =α+β does not hold, a value T 0  which satisfies the relation 
     
         T.sub.S =α+β+T.sub.0 
    
     is calculated. Then, the difference vector e is synthesized by multiplying the two voltage unit vectors v i , v j  and zero vector v 0  by their hold times α, β and T 0   respectively and adding the results of multiplication. Therefore, the difference vector e is given by the following equation: 
     
         e=αv.sub.i +βv.sub.j +T.sub.o v.sub.0 
    
     Further, the hold times α, β and T o  may be divided into m sections (m: a natural number) α m , β m  and T om  (m=1, 2, 3, ---, m), so that the values of α m , β m  and T om  satisfy the following equations: ##EQU1## 
     Further, it is desirable that the zero vector v 0  is located at the start point or end point of one of the two voltage unit vectors v i  and v j , so that the state of the switching element belonging to one phase only changes when the zero vector v 0  shifts to v i  or v j . 
     The PWM inverter apparatus of the present invention is based on the principle which will be described now. That is, a given magnetic flux command φ R  (a scalar value) and a given velocity command ω R  (a scalar value) are sampled at an interval of a sampling period T S , and the rotation angle of a magnetic flux vector obtained at each sampling time is calculated on the basis of the velocity command value and the sampling period T S . Also, the difference vector e between a magnetic flux vector φ(n-1) obtained at (n-1)-th sampling time and a magnetic flux vector φ(n) obtained at n-th sampling time is calculated, and the result of addition of the difference vector e to the magnetic flux vector φ(n) obtained at the n-th sampling time is predicted to be a magnetic flux vector φ(n+1) which will be obtained at (n+1)-th sampling time. This difference vector e is synthesized by the use of at least two reference voltage vectors selected from among a plurality of reference voltage vectors on the basis of the calculated rotation angle described above. Thus, when the PWM inverter apparatus is driven to produce the selected reference voltage vectors, the magnetic flux vector obtained at the (n+1)-th sampling time coincides with the predicted magnetic flux vector φ(n+1), so that the rotating magnetic flux in a load connected to the PWM inverter can follow up the magnetic flux command. The principle of the PWM inverter apparatus according to the present invention will be understood from the above description. 
     It will be seen that the difference vector e(n) obtained at the n-th sampling time corresponds to a change of the commanded magnetic flux vector from the (n-1)-th sampling time to the n-th sampling time. This difference vector e(n) is equal to the product of the inverter output voltage vector v(n) and the sampling period T S . Therefore, when the PWM inverter is driven for the period of time T S  by the voltage vector v(n) corresponding to the difference vector e(n), the rotating magnetic flux in the load is subjected to the change corresponding to the difference vector e(n), thereby producing the rotating magnetic flux vector meeting the command. 
     In the case of the PWM inverter formed of the switching elements of three-phase bridge arrangement, the inverter output voltage vector is determined by the combinations of the on-off states of the switching elements disposed on the positive and negative arms of the bridge. Thus, there are eight combinations. That is, there are six voltage unit vectors v(v 1 , v 2 , v 3 , v 4 , v 5 , v 6 ) shifted by an angle of π/3 one another and two zero vectors v 0  (v 7 , v 8 ) The zero vectors designate those voltage unit vectors where the line output voltage of the inverter is zero. 
     Therefore, in order to obtain a desired output voltage vector corresponding to a difference vector, suitable ones of the voltage unit vectors must be combined to synthesize the difference vector. For this purpose, two voltage vectors having respectively the same directions as those of two adjacent voltage unit vectors v i  and v j  nearest in direction (angle) to the difference vector e(n) are used to produce a voltage vector which coincides with the difference vector e(n). The magnitudes of these voltage vectors having the same directions as those of v i  and v j  are determined by suitably selecting the holding times α and β during which the associated switching elements are held to produce output voltages of the respective voltage vectors. When the sum (α+β) of the hold times is not equal to the sampling period T S , the sampling period T S  is suitably adjusted or the hold time T o  of the zero vector v 0  is added to the sum (α+β) so that the relation T S  =α+β+T o  can be obtained. 
     The voltage unit vectors v i , v j  and v 0  constituting the desired output voltage vector are represented by the combinations of the on-off states of the switching elements of the inverter as described already. Thus, a &#34;1&#34; and a &#34;0&#34; are used to represent the on and off states respectively of the switching elements so as to provide the pattern of the gate signal applied to the switching elements of the inverter. 
     Therefore, when the vector components of the voltage unit vectors v i , v j , v 0  and their hold times α, β, T o  are combined to form the gate signal so as to selectively turn on-off the switching elements of the inverter according to the gate signal pattern, the output voltage vector of the PWM inverter can be controlled in a relation in which the rotating magnetic flux changes while following up the magnetic flux command. 
     The logical and arithmetic processing between the step of reading the commands and the step of producing the gate signal can be completed within the sampling period T S . Therefore, the sampling period T S  can be set to match the processing speed of the logical and arithmetic processing means, and any especial high-speed processing means is unnecessary. 
     Further, the PWM switching frequency can be predicted for the purpose of control, because the sampling period T S  is known, and the number of times of changing over the voltage unit vectors within the sampling period T S  is known and fixed. 
     On the other hand, when the hold times α, β and T o  are divided into m sections to calculate the synthesized difference vector, the PWM switching frequency can be increased even when the sampling period T S  may be maintained constant. Therefore, appearance of ripples in the output voltage of the PWM inverter can be minimized when a high PWM switching frequency is employed. Also, the noise level of the a.c. motor connected as the load can be made higher than the audible frequency range, so that the audible noise can be decreased. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the general structure of a PWM inverter apparatus provided with an embodiment of the gate signal generating device according to the present invention. 
     FIG. 2 is a block diagram showing the detailed structure of the embodiment of the gate signal generating device shown in FIG. 1. 
     FIG. 3 illustrates how a vector of a magnetic flux command changes. 
     FIG. 4 illustrates an arrangement of voltage unit vectors. 
     FIG. 5 illustrates how to calculate a difference vector and hold times. 
     FIGS. 6A, 6B and 6C illustrate how to synthesize the difference vector. 
     FIG. 7 illustrates difference vectors lying outside an angular range defined between two selected voltage unit vectors. 
     FIG. 8 is a flow chart showing the steps of logical and arithmetic processing executed for synthesizing the difference vector from the voltage unit vectors. 
     FIG. 9 is a general timing chart of the processing sequence shown in FIG. 8. 
     FIG. 10 is a block diagram showing the detailed structure of the gate signal producing means shown in FIG. 2. 
     FIG. 11 is a timing chart of the operation of the gate signal producing means shown in FIG. 10. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Preferred embodiments of the present invention will now be described in detail with reference to the drawings. 
     FIG. 1 shows the general structure of a PWM inverter apparatus provided with an embodiment of the gate signal generating device according to the present invention. 
     Referring to FIG. 1, a PWM inverter 1 inverts d.c. power supplied from a d.c. power source 2 into a.c. power so as to generate a rotating magnetic flux for driving a three-phase a.c. motor 3 which is illustrated herein as an induction motor. A rotating magnetic flux command for determining the phase of rotation of the a.c. motor 3 is supplied from speed control means or torque control means (not shown). That is, a magnetic flux command φ R  and a velocity command ω R  commanding the magnitude and velocity respectively of a rotating magnetic flux vector are supplied through respective potentiometers 4 and 5 to the gate signal generating device generally designated by numeral 6. 
     The gate signal generating device 6 receives the magnetic flux command φ R  and the velocity command ω R  at an interval of a predetermined sampling period T S . On the basis of these commands, a difference vector between a magnetic flux vector obtained by sampling at preceding sampling time generally called (n-1)-th sampling time and a magnetic flux vector obtained by sampling at the present sampling time generally called n-th sampling time is calculated in the gate signal generating device 6. Then, this difference vector is synthesized from at least two selected from among a plurality of reference voltage vectors, and gate signals components U P , V P , W P , U N , V N  and W N  providing such a synthesized vector are produced and applied to the gates of respective switching elements S UP , S VP , S WP , S UN , S VN  and S WN  of the PWM inverter 1. Herein, the suffixes U, V and W represent the three phases respectively, and the suffixes P and N represent the positive and negative arms of the bridge respectively. The gate signal generating device 6 includes pre-processing means 10, voltage vector synthesizing means 20 and gate signal producing means 30 and can be formed by a one-chip microcomputer. 
     The detailed structure and operation of the pre-processing means 10, voltage vector synthesizing means 20 and gate signal producing means 30 constituting the gate signal generating device 6 will now be described in detail with reference to FIG. 2. 
     Pre-processing means 10 
     The magnetic flux command φ R  is supplied at the interval of the predetermined sampling period T S  to an A/D converter 11 to be converted from an analog quantity into a digital magnetic flux command φ S . The output of the A/D converter 11 is successively supplied to a register 12 acting as magnetic flux command storing means. The register 12 temporarily stores both the magnetic flux command φ S  (n-1) sampled at preceding (n-1)-th sampling time and the magnetic flux command φ S  (n) sampled at the present n-th sampling time. 
     On the other hand, the velocity command ω R  is supplied at the interval of the predetermined sampling period T S  to an A/D converter 13 to be converted from an analog quantity into a digital velocity command ω 1 . This velocity command ω 1  is supplied to a multiplier 14 acting as angle-of-lead calculating means. In the multiplier 14, the velocity command ω 1  is multiplied by the period T S  supplied from sampling signal generating means 15, and an amount of lead Δθ(n) of the rotation angle of the magnetic flux vector from each sampling time to the next sampling time is generally calculated as expressed by the following equation (1): 
     
         Δθ(n)=ω.sub.1 (n)·T.sub.S       (1) 
    
     Therefore, the rotation angle θ S  (n) of the magnetic flux vector obtained at the present sampling time relative to the rotation angle θ S  (n-1) of the magnetic flux vector obtained at preceding sampling time is given by the following equation (2): 
     
         θ.sub.S (n)=θ.sub.S (n-1)+Δθ(n-1)  (2) 
    
     The equation (2) is calculated by the combination of an adder 16 and a register 17. That is, the desired rotation angle θ S  (n-1) of the magnetic flux vector obtained at the preceding (n-1)-th sampling time is stored in the register 17, and the angle-of-lead Δθ(n) obtained at the present n-th sampling time is added to the rotation angle θ S  (n-1) in the adder 16. As soon as the calculation according to the equation (2) is executed, the result of addition is supplied to the register 17 to update the content of the register 17. 
     Voltage vector synthesizing means 20 
     First, the basic idea of synthesizing a voltage vector will be described. The relation between an output voltage vector v(t) of the PWM inverter 1 and a magnetic flux vector φ(t) induced in the a.c. motor 3 is expressed by the following equation (3): 
     
         V(t)=dφ(t)/dt                                          (3) 
    
     Considering processing by software, the continuous equation (3) is now transformed into the following discrete equation (4): 
     
         V(n)={φ(n)-φ(n-1)}/T.sub.S                         (4) 
    
     Further transformation of the equation (4) provides the following equation (5): 
     
         φ(n)-φ(n-1)=T.sub.S ·V(n)                 (5) 
    
     It is supposed that, in the equation (5), the sampling period T S  is very short, and the magnitude of φ(n) does not change in that period. Thus, when φ S  (n) represents the magnitude of φ(n), and θ S  (n) represents the direction, that is, the rotation angle of φ(n), the following equation (6) is obtained: 
     
         φ(n)=φ.sub.S (n)e.sup.jθs(n)                 (6) 
    
     The motion of the magnetic flux vector given by the equation (6) is schematically illustrated in FIG. 3. Suppose now that a change as shown in FIG. 3 occurs between the vector φ(n-1) of the magnetic flux command sampled at the (n-1)-th sampling time and the vector φ(n) of the magnetic flux command sampled at the n-th sampling time. In this case, the difference {φ(n)-φ(n-1)} between theose two vectors is equal to a difference vector e(n) directed from the point A to the point B in FIG. 3. 
     Suppose further that the difference between a predicted magnetic flux vector φ(n+1) which will be obtained at the next (n+1)-th sampling time and the magnetic flux vector φ(n) is equal to the difference between the magnetic flux vectors φ(n-1) and φ(n). Then, it will be apparent from the equation (5) that, when a voltage vector v(n) corresponding to the difference vector e(n) is produced, the magnetic flux vector φ(n) can be changed to the predicted magnetic flux vector φ(n+1) which will be obtained at the next (n+1)-th sampling time. 
     It is known that the direction of the output voltage vector of the PWM inverter 1 is determined by the combinations of the on-off states of the switching elements of three-phase bridge arrangement constituting the inverter 1. In terms of unit vectors, the output voltage vector of the PWM inverter 1 can be expressed by six discrete voltage unit vectors v 1  to v 6  shifted in direction by a pitch of π/3 one another and two zero vectors v 0  (v 7  and v 8  ), as shown in FIG. 4. When a &#34;1&#34; and a &#34;0&#34; are used to represent the on and off states respectively of each of the switching elements S UP , S VP  and S WP  on the positive arm of the bridge, each of the voltage unit vectors and zero vectors can be expressed by the combination of the &#34;1&#34; and &#34;0&#34;. For example, the voltage unit vector v 1  can be expressed as (1, 0, 0). It is apparent that, in the case of the switching elements S UN , S.sub. VN and S WN  on the negative arm of the bridge, the binary expression is contrary to that described above. 
     Therefore, in order to produce a voltage vector v(n) corresponding to the difference vector e(n), this voltage vector v(n) must be synthesized by the combination of suitable ones of the plural voltage unit vectors v 1  to v 6  and zero vector v 7 , v 8 . 
     According to a most preferable method, two adjacent voltage unit vectors v i  and v j  nearest in direction to the difference vector e(n) are selected, and the hold times α and β of the respective voltage unit vectors v i  and v j  are suitably adjusted until the following equation (7) is satisfied, so that the voltage vector v(n) corresponding to the difference vector e(n) can be produced: 
     
         e(n)=αv.sub.i +βv.sub.j                         (7) 
    
     This means that, after the voltage vector v i  is produced for a period of α from the point A in FIG. 3, and the voltage unit vector v j  is then produced for a period of β, the leading end of the magnetic flux vector reaches the target point B in FIG. 3. 
     However, the equation (5) shows that the voltage vector v(n) has the magnitude of T S  which is a scalar quantity. Therefore, when the period of time (α+β) required until the difference vector e(n) given by the equation (7) moves from the point A to the point B in FIG. 3 coincides with the sampling period T S , the voltage vector v(n) is expressed by the right-hand members of the equation (7). That is, the equation (7) is based on the condition that the following equation (8) is satisfied: 
     
         T.sub.S =α+β                                    (8) 
    
     The value of (α+β) changes depending on the angle-of-lead Δθ(n) and rotation angle θ S  (n) of the magnetic flux vector. Therefore, in the case of synthesizing the difference vector e(n) on the basis of the equations (7) and (8), the value of the sampling period T S  is changed in relation to the change in the value of (α+β). However, a complex control is required for changing the sampling period T S . In order to avoid such a complexity of control, the zero vector v 0  having no magnitude and no direction is preferably employed, and the difference vector e(n) is synthesized so that the following equations (9) and (10) are satisfied: 
     
         e(n)=αv.sub.i +βv.sub.j +T.sub.o v.sub.0        (9) 
    
     
         T.sub.o =T.sub.S -(α+β)                         (10) 
    
     That is, when the hold time T o  to the zero vector v 0  is selected to satisfy the equation (10), the sampling period T S  can be maintained constant regardless of whatever change in the value of (α+β). 
     The difference vector e(n) can be similarly synthesized when, in the equation (9), the hold times α, β and T o  may be suitably divided into two values α 1 , α 2  ; β 1 , β 2  ; and T o1 , T o2  which satisfy the relations α 1  +α 2  =α, β 1  +β 2  =β and T o1  +T o2  =T o  respectively, and the right-hand members may be changed over in the order of α 1  v i  →T o1  v 0  →β 1  v j  →α 2  v i  →T o2  v 0  →β 2  v j . Synthesis may be similarly achieved by dividing each of the hold times α, β and T o  into m values (m: a natural number). Division of the hold times in the manner described above is advantageous in that the inverter output frequency can be increased so that appearance of ripples in the invention output voltage can be minimized, and audible noise generated from the a.c. motor 3 can be greatly suppressed. 
     As described above, the difference vector e(n) coincides with the voltage vector T S .v(n), and the hold times α, β and T o  have a dimension of time, while the voltage unit vectors v i , v j  v 0  have a unit of voltage. 
     The detailed structure of the voltage vector synthesizing means 20 shown in FIG. 2 will now be described. 
     Voltage unit vector selecting means 21 
     As described already, two adjacent voltage unit vectors v i  and v j  nearest in direction to the difference vector e(n) are selected for the synthesis of e(n). However, it takes a long period of time for the logical and arithmetic processing when the directions of all of the six voltage unit vectors are compared with that of the difference vector e(n). Usually, the magnitude of the magnetic flux vector φ(n) does not make any appreciable change, and its leading end moves along the circumference of a circle. Thus, the direction of the difference vector e(n) is oriented along the circle. Therefore, the direction of the difference vector e(n) is generally determined by the rotation angle θs(n) of the vector φ(n) of the magnetic flux command φ S  sampled at the n-th sampling time or by the rotation angle θ S  (n-1) of the vector φ(n-1) of the magnetic flux command φ S  sampled at the (n-1)-th sampling time. Therefore, the voltage unit vector selecting means 21 shown in FIG. 2 includes a ROM storing the following Table 1. More precisely, six angular ranges I to VI partitioned by the six voltage unit vectors v 1  to v 6  are set as shown in FIG. 4, and the combinations of voltage unit vectors v i  and v j  to be selected are listed in Table 1 to define the individual angular ranges I to VI respectively. 
     
                       TABLE 1                                                     
______________________________________                                    
             Voltage unit vectors                                         
             to be selected                                               
θs(n - 1)                                                           
             (v.sub.i, v.sub.j)                                           
______________________________________                                    
I            (v.sub.3, v.sub.4)                                           
II           (v.sub.4, v.sub.5)                                           
III          (v.sub.5, v.sub.6)                                           
IV           (v.sub.6, v.sub.7)                                           
V            (v.sub.1, v.sub.2)                                           
VI           (v.sub.2, v.sub.3)                                           
______________________________________                                    
 
    
     Thus, when the rotation angle θs(n-1) of the vector φ n  (n-1) of the magnetic flux command φ S  (n-1) sampled at the (n-1)-th sampling time is supplied from the register 17 of the pre-processing myans 10, the voltage unit vector selecting means 21 selects and generates the corresponding combination of the voltage unit vectors v i  and v j  as its output. The voltage unit vector selecting means 21 further includes means for storing vector component data of the voltage unit vectors including the zero vectors v 0 , and the selected vector component data of the voltage unit vectors v i , v j  and zero vectors v 7 , v 8  are supplied from the voltage unit vector selecting means 21 to vector arrangement determining means 24. 
     Difference vector calculating means 22 
     This difference vector calculating means 22 receives the magnetic flux commands φ S  (n-1) and φ S  (n) from the magnetic flux command storing means 12 in the pre-processing means 10 and receives also the detected angle-of-lead Δθ(n) from the multiplier 14 in the pre-processing means 10, so as to calculate the vector components, that is, the magnitude and direction of the difference vector e(n). This calculation will be described with reference to FIG. 5. 
     Suppose that the magnetic flux commands φ S  (n-1) and φ S  (n) have the relation shown in FIG. 5. In such a case, the magnitude d of the difference vector e(n) and the angle δ between the difference vector e(n) and the vector φ(n-1) of the magnetic flux command φ S  (n-1) can be geometrically calculated according to the following equations (11) and (12) respectively: 
     
         d={φ.sub.S (n-1).sup.2 +φ.sub.s (n).sup.2 -2φ.sub.S (n-1).φ.sub.S (n) cos Δθ(n)}.sup.1/2      (11) 
    
     
         δ=cos.sup.-1 {(φ.sub.S (n-1)-φ.sub.S (n).cos Δθ(n))/d}                                     (12) 
    
     When the sampling period T S  is short, the command φ S  (n) can be approximated to be substantially equal to the command φ S  (n-1), and the angle-of-load Δθ(n) is also small. Therefore, the equations (11) and (12) can be transformed into the following equations (11&#39;) and (12&#39;) respectively: 
     
         d=Δθ(n).φ.sub.s (n)                        (11&#39;) 
    
     
         δ=1/2{π-Δθ(n)}                        (12&#39;) 
    
     Hold time calculating means 23 
     The hold times α and β of the selected voltage unit vectors v i  and v j  respectively are calculated by hold time calculating means 23 according to the geometric diagram shown in FIG. 5. 
     In the case of the calculation of the individual hold times α and β, whether or not the difference vector e(n) lies within the angular range defined between the voltage unit vectors v i  and v j  selected from Table 1 must be checked. This is because, when the magnitude of the commanded magnetic flux vector φ(n) changes greatly relative to the commanded magnetic flux vector φ(n-1) until φ(n) changes to φ&#39;(n) or φ&#34;(n) as shown in FIG. 7, its leading end will be located outside the angular range defined between the selected voltage unit vectors v i  and v j , although this is an exceptional example. In such a case, these two voltage unit vectors v i  and v j  cannot be used to synthesize the difference vector e(n). 
     Therefore, the hold time calculating means 23 decides, on the basis of the angle data δ of the difference vector e(n), as to whether or not the vector e(n) lies within the angular range defined between the vectors v i  and v j . When the result of decision is &#34;Yes&#34;, the hold times α and β are calculated according to the diagram shown in FIG. 5. On the other hand, when the result of decision is &#34;No&#34;, one of the voltage unit vectors v i  and v j  nearer in direction to the difference vector e(n) is selected, and the hold time α or β corresponding to the selected vector v i  or v j  is calculated to be used for the synthesis of the difference vector e(n). The procedure for the latter mode of voltage vector synthesis will be described later in connection with the vector arrangement determining means 24 for conveniences of description. Herein, the former case, that is, the general case where the difference vector e(n) lies within the angular range defined between the voltage unit vectors v i  and v j  will now be described. 
     Let α=AC and β=CB in FIG. 5. Then, the hold times α and β can be calculated according to the following equations (13) and (14) respectively: ##EQU2## where kt is a coefficient used for conversion into time, and γ is an angle determined by both the selected one of the voltage unit vectors and the rotation angle θ S  (n-1). Table 2 shows the relation between the voltage unit vectors v 1  to v 6  and the corresponding values of the angle γ. 
     
                       TABLE 2                                                     
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Selected voltage                                                          
unit vector                                                               
           γ                                                        
______________________________________                                    
v.sub.1 (1, 0, 0)                                                         
            θ.sub.S (n - 1) - π                                  
v.sub.2 (1, 1, 0)                                                         
           θ.sub.S (n - 1) + 2π/3 (0° ≦ θ.sub
           .S (n - 1) &lt; π/6                                            
           θ.sub.S (n - 1) - 4π/3 (3π/2 ≦ θ.sub.S
            (n - 1) &lt; 2π)                                              
v.sub.3 (0, 1, 0)                                                         
           θ.sub.S (n - 1) + π/3 (0° ≦ θ.sub.
           S (n - 1) &lt; π/2)                                            
           θ.sub.S (n - 1) - 5π/3 (11π/6 ≦ θ.sub.
           S (n - 1) &lt; 2π)                                             
v.sub.4 (0, 1, 1)                                                         
           θ.sub.S (n - 1) -v.sub.5 (0, 0, 1) θ.sub.S (n - 1) 
           - π/3                                                       
v.sub.6 (1, 0, 1)                                                         
           θ.sub.S (n - 1) - 2π/3                                
______________________________________                                    
 
    
     When the sampling period T S  is maintained constant, the values of α and β calculated according to the respective equations (13) and (14) are substituted into the equation (10) to calculate the hold time T o  of the zero vector v 0 . 
     Vector arrangement determining means 24 
     By the use of the hold times α, β, T o  and the voltage unit vectors v i , v j , v 0  selected in the manner described above, the voltage vector v(n) corresponding to the difference vector e(n) can be synthesized. Therefore, when the switching elements of the PWM inverter 1 are driven according to this synthesized voltage vector v(n), the rotating magnetic flux can be controlled to follow up the change in the vector of the magnetic flux command from φ(n-1) to φ(n). 
     In the course of the synthesis of the voltage vector v(n), the vector arrangement determining means 24 determines the arrangement of the individual voltage unit vectors v i , v j  and v 0 . Although there are various ways of arranging these voltage unit vectors, it is desirable that the vector components of only one phase are changed among the vector components of all the phases in each of the voltage unit vectors. This is because changing the vector components of two phases results in an increased switching loss and an increased voltage variation. 
     Referring to FIG. 4 again, it will be seen that the vector components of only one phase change in the two adjacent voltage unit vectors, and the vector components of two phases do not simultaneously change in the adjacent voltage unit vectors. Thus, the aforementioned problem is obviated. In the case of the zero vector v 0 , the selection of either v 7  or v 8  and the location of the selected zero vector v 0  are determined in relation to the selected voltage unit vectors v i  and v j . In this case, the zero vector v 0  showing the vector component change of one phase only between it and the associated voltage unit vectors is selected and located. 
     The manner of vector arrangement will be described in more detail with reference to FIGS. 6A, 6B and 6C representing switching modes I, II and III respectively. 
     Referring to FIG. 6A, the switching mode I designates a mode in which the voltage unit vectors v i , v j  and v 0  are divided into m sections to synthesize the voltage vector v(n) corresponding to the difference vector e(n). In FIG. 6A, the hold times α, β and T o  are divided into α=α 1  +α 2 , β=β 1  +β 2  and T o  =T o1  +T o2  respectively by way of example. The zero vector v 8  is located at the position indicated by the mark O in FIG. 6A, that is, at the start point or end point of the divided voltage vectors (α 1  v i  +β 1  v j ) or (β 2  v i  +β 2  v j ). For example, when the voltage unit vectors v 3  (0, 1, 0) and v 4  (0, 1, 1) are selected as v i  and v j   respectively, the following vector arrangement is provided according to the switching mode I: 
     
         ______________________________________                                    
v.sub.7 (0, 0, 0) → v.sub.3 (0, 1, 0) → v.sub.4 (0, 1, 1)   
→                                                                  
v.sub.8 (1, 1, 1) → v.sub.4 (0, 1, 1,) → v.sub.3 (0, 1,     
______________________________________                                    
0)                                                                        
 
    
     Referring to FIG. 6B, the switching mode II designates a mode where the voltage unit vectors v i , v j  and v 0  are not divided. In this case too, the zero vector v 0  is selected and located according to the rule described above. Thus, when, for example, the voltage unit vectors v 3  (0, 1, 0) and v 4  (0, 1, 1) are selected as v i  and v j  respectively, the following vector arrangement is provided: 
     
         v.sub.7 (0, 0, 0)→v.sub.3 (0, 1, 0)→v.sub.4 (0, 1, 1) 
    
     Referring to FIG. 6C, the switching mode III is an exceptional switching mode. As described already, the two adjacent voltage unit vectors v i  and v j  nearest in direction to the difference vector e(n) are selected according to the principle of the present invention, and, in the illustrated embodiment, the combinations of the voltage unit vectors v i  and v j  corresponding to the various angular ranges of the commanded magnetic flux vector φ(n-1) are previously set as shown in Table 1 so as to simplify the logical and arithmetic processing. Therefore, when the magnitude of the commanded magnetic flux vector φ(n) greatly changes as indicated by φ&#39;(n) or φ&#34;(n) in FIG. 7, the difference vector e(n) deviates from within the predetermined angular range defined between the adjacent voltage unit vectors v i  and v j . In such a situation, these two voltage unit vectors cannot be used to synthesize the difference vector e(n). In such a case, therefore, one of the two voltage unit vectors v i  and v j  which is nearest in direction to the difference vector e(n) is selected alone and used to approximate the difference vector e(n), as shown in FIG. 6C representing the switching mode III. In this case too, the zero vector v 0  is suitably selected and located at the start point or end point of the vector v i  or v j , as shown in the following equation (15) or (16): 
     
         e&#39;(n)≈αv.sub.i +T.sub.o v.sub.0              (15) 
    
     
         e&#34;(n)≈βv.sub.j +T.sub.o v.sub.0               (16) 
    
     Therefore, in the present embodiment, the switching mode I or II is selected when the difference vector e(n) lies inside the angular range defined between the voltage unit vectors v i  and v j , but the switching mode III is selected when e(n) lies outside the above angular range. 
     The switching mode I or II is selected under the condition specified above. However, the switching mode II is exclusively selected when the zero vector hold times T o1  and T o2  are shorter than the minimum on-duty time (T o ) min  determined by the inherent characteristics of the switching elements of the PWM inverter 1. This is because the turn-off time is required for each of the switching elements of the PWM inverter 1. Thus, when one of the switching elements forming pair with the other switching element on the positive and negative arms respectively of the bridge is turned off, it is necessary to turn on the other switching element with a delay time of (T o ) min , thereby preventing objectionable short-circuit trouble. (Such a delay time in the switching state of the switching elements of the inverter is called dead time.) Therefore, this time (T o ) min  is absorbed in the hold time T o  or hold times T o1  and T o2  of the zero vector v 0 . 
     Also, when the relation T o  &lt;(T o ) min  occurs in the switching mode II, the switching mode II is changed over to the switching mode III. 
     The above conditions for selection of the switching modes I, II and III will be summarized as follows: 
     ○ 1  When the result of decision as to whether or not the difference vector e(n) lies inside the angular range defined between the voltage unit vectors v i  and v j  is: 
     (a) &#34;Yes&#34;, the switching mode I or II is selected; but 
     (b) &#34;No&#34;, the switching mode III is selected. 
     ○ 2  When the comparison between the hold times T o , T o1 , T o2  and the time (T o ) min  proves that: 
     (a) T o1 , T o2  &gt;(T o ) min , the switching mode I is selected; 
     (b) T o  &gt;(T o ) min  &gt;T o1 , T o2 , the switching mode II is selected, and 
     (c) T o , T o1 , T o2  &lt;(T o ) min , the switching mode III is selected. 
     In the manner described above, the switching mode I, II or III is selected, and the arrangement of the voltage unit vectors v i , v j  and v 0  is determined. Then, according to the determined order of arrangement, data for producing the gate signal including the voltage unit vector components and hold times are supplied from the vector arrangement determining means 24 to gate signal producing means 30. In this case, the vector hold times α, β, T o , etc. are converted into corresponding values on a time axis t whose origin is 0 (zero), and such values are supplied to the gate signal producing means 30. Also, in this case, a dead time gate signal component having a length of time T d  corresponding to the value of (T o ) min  is also supplied to the gate signal producing means 30. 
     FIG. 8 is a flow chart showing the sequence of logical and arithmetic processing in the pre-processing means 10 and voltage vector synthesizing means 20 described already when the processing is executed by a one-chip microcomputer. 
     In a step 101 in FIG. 8, an interrupt signal INT is analyzed. When the result of analysis proves that an interrupt signal INT1 is applied, an interrupt in the processing by the aforementioned pre-processing means 10 and voltage vector synthesizing means 20 is requested. On the other hand, when the result of analysis proves that an interrupt signal INT2 is applied, setting of voltage vector data synthesized by the voltage vector synthesizing means 20 in the gate signal producing means 30 is requested. 
     When the result of analysis in the step 101 proves that the interrupt signal INT1 is applied, the magnetic flux command φ R  and velocity command ω R  and read and A/D converted in a step 102. Then, in a step 103, the angle-of-lead Δθ(n) is calculated according to the equation (1), and the rotation angle θ S  (n) is calculated according to the equation (2). In a step 104, Table 1 is searched to retrieve pre-set two voltage unit vectors v i  and v j  on the basis of the rotation angle θ S  (n-1) calculated in the preceding sampling. Then, in a step 105, the vector components of the difference vector e(n) are calculated according to the equations (11) and (12), and decision is made as to whether or not the difference vector e(n) lies inside the angular range defined between the voltage unit vectors v i  and v j . 
     When the result of decision in the step 105 is &#34;Yes&#34;, the step 105 is followed by a step 106 in which the hold times α, β and T o  of the voltage unit vectors v i , v j  and zero vector v 0  are calculated according to the equations (13), (14) and (10) respectively. Then, in steps 107 and 108, one of the switching modes I, II and III is selected according to the conditions set forth in 2. 
     When the switching mode I is selected, the step 107 is followed by a step 110 in which gate signal data based on the manner of divided voltage vector synthesis shown in FIG. 6A are prepared. On the other hand, when the switching mode II is selected, the step 108 is followed by a step 111 in which gate signal data based on the manner of voltage vector synthesis shown in FIG. 6B are prepared. 
     Further, when the switching mode III is selected, the step 108 is followed by a step 120. This step 120 is the same as the step which is followed by the step 105 when the result of decision is &#34;No&#34;. In the step 120, one of the voltage unit vectors v i  and v j  which is nearer in direction to the difference vector e(n) is selected. Then, in a step 121, the hold time α or β of the selected one of the voltage unit vectors v i  and v j  and that T o  of the zero vector v 0  are calculated. The step 121 is followed by a step 122 in which gate signal data based on the manner of voltage vector synthesis shown in FIG. 6C are prepared. 
     On the other hand, when the result of analysis in the step 101 proves that the interrupt signal INT2 is applied, prepared gate signal data are set in the gate signal producing means 30. 
     FIG. 9 is a time chart showing the timing of interrupt processing by application of the interrupt signals INT1 and INT2 described above. FIG. 9 illustrates the interrupt processing in the case of the switching mode I. It will be seen that the interrupt signal INT1 is activated once in each sampling period T S , and the interrupt signal INT2 is activated twice in each sampling period T S . Gate signal data processed as a result of (n-1)-th sampling are set in the gate signal producing means 30 in an n-th sampling period. 
     Gate signal producing means 30 
     According to the gate signal data supplied to the gate signal producing means 30, the gate signal producing means 30 applies the corresponding gate signal components to the respective switching elements S UP , S VP , S WP , S UN , S VN  and S WN  of the PWM inverter 1. 
     FIG. 10 shows the detailed structure of the gate signal producing means 30. Gate signal data prepared by the vector arrangement determining means 24 are set in registers 31 and 45 via an internal bus 25 of the gate signal generating device 6. Data of the hold times α, β, T o , T d  are set in the register 31 together with data of voltage unit vector change-over times t 1 , t 2 , t 3 , - - - determined according to the vector arrangement. These times t 1 , t 2 , t 3 , - - - are counted from an arbitrarily selected reference point 0 (zero) on a time axis and are selected to provide the individual hold times α, β, T o  and T d . Gate signal data (vector components) corresponding to the individual voltage unit vectors are set in the register 45. Therefore, the register 45 includes six elements BU P , BV P , BW P , BU P , BV N  and BW N  corresponding to the respective switching elements S UP , S VP , S WP , S UN , S VN  and S WN  of the PWM inverter 1. Further, this register 45 has, for example, an FIFO (first-in-first-out) register structure so that switching-element on-off signal components corresponding to voltage unit vectors to be generated in each sampling period T S  or half sampling period 1/2T S  are sequentially stored therein. 
     The register 31 is connected at its output to input terminals of registers 32 to 37, and these registers 32 to 37 are connected at their output terminals to an input terminal of a register 38. This register 38 is connected at its output terminal to one of two input terminals of a comparator 39. A register 40 is connected at its output terminal to the other input terminal of the comparator 39. The register 40 is connected at its input terminal to an output terminal of a timer 41. The timer 41 includes a counter which starts its counting operation from the reference time 0 (zero) of the aforementioned vector change-over times t 1 , t 2 , t 3 , - - - on the time axis, so that its count indicates the vector change-over time. The timer 41 is connected at its clock input terminal to a control circuit 42. The control circuit 42 is connected also to control terminals of the registers 32 to 37 and 38. 
     The comparator 39 is connected at its output terminal to input terminals of six elements BU P  &#39;, BV P  &#39;, BW P  &#39;, BU N  &#39;, BV N  &#39; and BW N  &#39; of a register 46. The six elements BU P , BV P , BW P , BU N , BV N  and BW N  of the register 45 are connected at their output terminals to the input terminals of the six elements BU P  &#39;, BV P  &#39;, BW P  &#39;, BU N  &#39;, BV N  &#39; and BW N  &#39; of the register 46 respectively. 
     The operation of the gate signal producing means 30 having such a structure will now be described. 
     When any one of the registers 32 to 37 becomes empty, the time data stored in the register 31 is transferred from the register 31 to the empty register. The time data stored in each of the registers 32 to 37 is sequentially transferred to the register 38 in response to a control signal applied from the control circuit 42. On the other hand, the time data of the timer 41 is transferred from the timer 41 to the register 40 to update the content of the register 40 with lapse of time. The comparator 39 generates a reset pulse when the time data stored in the register 40 coincides with the content of the register 38. In response to the appearance of this reset pulse, the content of the register 45 is transferred to the register 46, and, at the same time, one of the registers 32 to 37 having transferred its content to the register 38 is cleared. As a result, gate signals components U P , V P , W P , U N , V N   and W N  are applied from the register 46 to the gate circuits of the corresponding switching elements respectively of the PWM inverter 1. 
     FIG. 11 is an operation timing chart of the gate signal producing means 30. As described already, the gate signal is the combination of the gate signal components U P , V P , W P , U N , V N , W N  as shown in FIG. 11. Among these gate signal components, the components U P , V P  and W P  have the same expressions as those of the vector components of the voltage unit vectors, while the components U N , V N , W N  have inverted expressions, except that the dead time gate signal components are not inverted. 
     Before time t 1  in FIG. 11, a gate signal (0, 0, 0, 1, 1, 1) is stored already in the register 46. Suppose now that time data t 2  =t 1  +(T o1  -T d ) is stored in the register 35, and a dead-time gate signal (0, 0, 0, 1, 0, 1) is stored in the register 45. Then, when the count of the timer 41 indicates t 2  =t 1  +(T o1  -T d ), a reset pulse is generated from the comparator 39. As a result, the register 35 is cleared, and, at the same time, the gate signal stored in the register 45 is transferred to the register 46. Consequently, the on-off states of the switching elements of the PWM inverter 1 at time t 2  change from (0, 0, 0, 1, 1, 1) to (0, 0, 0, 1, 0, 1). 
     Then, in response to the output signal of the control circuit 42, the content of the register 34 is transferred to the register 38 to be compared with the count of the timer 41 by the comparator 39. When the result of comparison proves that the content of the register 34 coincides with the count of the timer 41, the next gate signal which is, for example, (0, 1, 0, 1, 0, 1) is generated at time t 3  according to the processing sequence described already. On the other hand, when the content of the register 34 does not coincide with the count of the timer 41, the content of one of the remaining registers 32 to 37, which has not been compared yet, is transferred to the register 38 in response to the output signal of the control circuit 42 to be compared with the count of the timer 41. In this case, the count of the timer 41 is held under control of the control circuit 42 until the comparison between the contents of all the registers 32 to 37 and the count of the timer 41 is completed. The count of the timer 41 is incremented because a &#34;1&#34; is added to the count each time a pulse of the clock signal is applied from the control circuit 42 with lapse of time. It will be noted that, during the period of time of addition of a &#34;1&#34; to the count of the timer 41, the comparator 39 can compare the count of the timer 41 with the contents of all the registers 32 to 37. 
     Thus, as shown in FIG. 11, the gate signal conforming to the gate signal data supplied from the vector arrangement determining means 24 is sequentially applied to the gates of the switching elements of the PWM inverter, so the PWM inverter 1 is driven to produce the rotating magnetic flux commanded by the magnetic flux command φ R  and velocity command ω R . 
     It will be seen from the foregoing description that the illustrated embodiment of the present invention provides various advantages which will now be described. 
     On the basis of a magnetic flux command φ R  and a velocity command ω R  received at an interval of a sampling period T S , a change in the magnitude of and an angle-of-lead of the commanded magnetic flux vector obtained by sampling at the present sampling time relative to those of the commanded magnetic flux vector obtained by sampling at preceding sampling time, that is, a difference vector e(n) is calculated, and this difference vector e(n) is synthesized using a plurality of voltage unit vectors v. Then, the gate signal applied to the switching elements of the PWM inverter is produced according to the synthesized voltage vector v(n). This logical and arithmetic processing for producing the gate signal after reception of the commands can be executed within each sampling period T S . Therefore, as compared to the prior art apparatus in which the gate signal is produced on the basis of an error vector between a detected value and a target value of a magnetic flux vector, the present invention is advantageous in that the logical and arithmetic processing for producing the gate signal need not be executed at a high speed, and the gate signal that can follow up rotating magnetic flux commands with high accuracy can be generated. 
     Further, for the synthesis of the difference vector e(n), two voltage unit vectors v i  and v j  nearest in direction to the difference vector e(n) are used. Because of the selection of such voltage unit vectors for the synthesis of the difference vector e(n), the number of times (the frequency) of switching the switching elements of the PWM inverter within the sampling period T S  can be previously grasped. Therefore, the switching frequency can be suitably controlled so as to decrease thermal losses of the switching elements of the PWM inverter and to rationally determine the heat tolerance of the switching elements. 
     Further, the zero vector v 0  is used to adjust the magnitude of the synthesized voltage vector v(n) so that the sum of hold times coincides with the sampling period T S . Therefore, the sampling period T S  can be maintained constant, and the circuit structure for controlling the sampling period T S  can be simplified. 
     According to the switching mode I, the hold times α, β and T o  of the respective voltage unit vectors v i , v j  and v 0  are each divided into two values for the purpose of synthesis of the synthesized voltage vector v(n). Thus, even when the sampling period T S  is constant the switching frequency can be increased according to the number of division of the hold times. Therefore, appearance of ripples in the output voltage of the PWM inverter can be minimized, and generation of audible noise from the a.c. motor can also be minimized. 
     In the present invention, the combinations of two voltage unit vectors v i  and v j  used for the synthesis of the difference vector e(n) at each or n-th sampling time are previously stored in the form of a table in the ROM together with the values of the corresponding rotation angle θ S  (n-1) of the magnetic flux vector obtained by sampling at preceding or (n-1)-th sampling time, and this table is retrieved to select the suitable combination of the voltage unit vectors v i  and v j . Therefore, the processing period of time required for selecting such voltage unit vectors can be shortened. In the illustrated embodiment, the table listing the combinations of the voltage unit vectors v i  and v j  corresponding to the values of the rotation angle θ S  (n-1) is shown by way of example. However, it is apparent that, because the angle-of-lead Δθ(n) is actually considerably small, the result is substantially the same as that described above even when the table lists the values of Δθ(n) corresponding to those of θ  S  (n). 
     It will be understood from the foregoing detailed description of the present invention that, on the basis of a magnetic flux command and a velocity command received at an interval of a sampling period, a change in the magnitude of and an angle-of-lead of the commanded magnetic flux vector obtained by sampling at current the present sampling time relative to those of the commanded magnetic flux vector obtained by sampling at preceding sampling time, that is, the difference vector is calculated, and this difference vector is synthesized using a plurality of voltage unit vectors. Then, the gate signal applied to the gates of the switching elements of the PWM inverter is produced according to the synthesized voltage vector. This logical and arithmetic processing for producing the gate signal after reception of the commands can be executed within each sampling period. Therefore, as compared to the prior art apparatus in which the gate signal is produced on the basis of an error vector between a detected value and a target value of a magnetic flux vector, the present invention is advantageous in that the logical and arithmetic processing for producing the gate signal need not be executed at a high speed, and the gate signal that can follow up rotating magnetic flux commands with high accuracy can be generated. 
     In the present invention, two voltage unit vectors v i  and v j  nearest in direction to the difference vector are used for the synthesis of the difference vector. Because of the selection of such voltage unit vectors for the synthesis of the difference vector, the number of times (the frequency) of switching the switching elements of the PWM inverter within the sampling period can be previously grasped. Therefore, the switching frequency can be suitably controlled so as to decrease thermal losses of the switching elements of the PWM inverter and to rationally determine the withstand heat capability of the switching elements. 
     In the present invention, the zero vector v 0  is used to adjust the magnitude of the synthesized voltage vector so that the sum of hold times coincides with the sampling period. Therefore, the sampling period can be maintained constant, and the circuit structure for controlling the sampling period can be simplified. 
     Also, in the present invention, the hold times α, β and T o  of the respective voltage unit vectors v i , v j  and v 0  may be divided into m sections (m: natural number) for the synthesis of the synthesized voltage vector. Thus, even when the sampling period is constant, the switching frequency can be increased according to the number m of division of the hold times. Therefore, appearance of ripples in the output voltage of the PWM inverter can be minimized, and generation of audible noise from the a.c. motor can also be minimized. 
     In the illustrated embodiment, it is assumed that a difference vector e(n) between a magnetic flux vector φ(n-1) obtained by sampling at preceding, that is, (n-1)-th sampling time and a magnetic flux vector φ(n) obtained by sampling at the present, that is, n-th sampling time is regarded to be equal to a difference vector e(n+1) between a magnetic flux vector φ(n+1) obtained by sampling at next, that is, (n+1)-th sampling time and the magnetic flux vector φ(n) obtained by sampling at the present n-th sampling time, and, on the basis of the above assumption, the value of a magnetic flux vector φ(n+1) which will be obtained by sampling at the next (n+1)-th sampling time is predicted. Therefore, the value of the magnetic flux vector φ(n+1) which will be obtained by sampling at the next sampling time is calculated by adding the difference vector e(n) to the magnetic flux vector φ(n) obtained by sampling at the present sampling time. 
     However, in the present invention, the magnitude of the magnetic flux vector φ(n+1) obtained by sampling at the next sampling time is assumed to be substantially equal to the magnitude of the magnetic flux vector φ(n) obtained by sampling at the present sampling time, as described already. On the basis of the above assumption, the magnetic flux vector obtained by rotating the magnetic flux vector φ(n) by the rotation angle Δθ(n) may be predicted as the magnetic flux vector φ(n+1) which will be obtained by sampling at the next sampling time. In this case, φ S  (n) and Δθ(n) may be applied, in lieu of φ S  (n-1) and Δθ(n-1) respectively, as inputs to the difference vector calculating means 22 shown in FIG. 2. Further, as described already with reference to FIG. 2, φ S  (n-1) and φ S  (n) can be regarded to be equal to each other in the calculation of the difference vector according to the equations (11) and (12). Therefore, it will be readily understood that the circuitry of FIG. 2 need not be greatly altered even in such a case.