Intelligent disk drive having configurable controller subsystem providing drive-status information via host-computer expansion bus
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of application Ser. No. 07/220,536, filed 7-18-89, now abandoned. 
    
    
     This invention relates generally to the communications and control of disk drives by a host computer. More particularly, the invention provides a method and circuit for control of intelligent or integrated disk drives whereby a single computer address may be used for control of two intelligent disk drives. 
     BACKGROUND OF THE INVENTION 
     Microcomputers normally provide a single expansion slot or other connection point for external disk drives. Controller cards designed for attachment to the interface had previously provided control capability for two &#34;dumb&#34; disk drives. The host computer accesses either of the drives through the controller by the use of a common address selecting the controller and a disk drive selection bit provided to a command register within the controller. The controller provides the status of both disk drives to the computer and interprets computer selection commands to activate one or the other drive as the selected drive. 
     More recently, intelligent or integrated disk drives have become available. The intelligent disk drive incorporates the controller within the disk drive unit, requiring only an address and data cable hook-up to the host microcomputer. In this configuration, however, one intelligent disk drive consumes the single expander port or connection point with the address and host data cables. Techniques have been developed for driving two intelligent disk drives from a common cable set; however, external jumper connections for designation of single or multiple disk operation, master or slave designation, and drive number designation have been required. 
     Operation of the intelligent disk drive, therefore, required selection of its configuration and installation of the appropriate jumper connections. As an example, if a disk drive were to be the master drive, or drive 0, in a two-drive hook-up, the jumper designating master drive would be installed. The jumper designating no second drive would not be installed, and the third jumper indicating a second drive present would be installed. Conversely, on the second drive, the first two jumpers would not be installed, and the third jumper designating a slave drive present would be installed. It should be noted that the master drive would not function properly if the slave drive were not present. For a master drive operating singly, the first and second jumpers would be installed, while the third jumper would not. The prior art technique described, therefore, required three jumpers uniquely installed for any configuration operation, singly or multiply. The present invention eliminates the requirements for multiple jumpers. A single jumper designating device address is sufficient. 
     SUMMARY OF THE INVENTION 
     The present invention provides a disk drive controlled by an internal microprocessor interface wherein the microprocessor has one firmware bit programmable to designate intelligent drive operation. A single external jumper connection is provided for connection to a pull-up resister. Connection of the jumper designates a disk drive controller as drive 1. Absence of the jumper designates a disk drive controller as drive 0. A sensing means interconnects the jumper connection with the microprocessor for sensing of the jumper connection. A disabling circuit under the control of the microprocessor is connected to the tristate drivers on all outputs from the disk drive controller unit to the host computer. Commands issued by the host computer are read by the disk drive controller. The microprocessor in the controller compares the drive selected by the computer with the drive number of the controller selected by connection of the jumper. The comparison result is provided to the disable circuit whereby a comparison &#34;not true&#34; will disable the tristate write drivers. A compare &#34;true&#34; will enable the tristate write drivers, allowing transfer of command acknowledgement signals and data by the intelligent disk drive to the host computer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 provides a schematic diagram for two intelligent-drive disk controllers, employing the invention attached in parallel to a host computer interface; 
     FIG. 2 provides a schematic logic diagram of the tristate driver disable circuit. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, a first disk drive controller 10 is connected to the host computer interface through a first address bus 12, a second address bus 14, and a bidirectional data bus 16. The peripheral controller 18 receives the host register address signals HA0, HA1, HA2 and HA9 for selection of data registers internal to the peripheral controller. The host chip select signal HCS- the host write enable signal HWE-, and the host read enable HRE- are received by the peripheral controller on address bus 14. Tristate read drivers 20 and tristate write drivers 22 connect the host data bus 16 to the peripheral controller. The peripheral controller provides direct memory access request signals, DMAREQ, to the host computer through tristate write driver 24. Similarly, the peripheral controller provides interrupt request signals, INTREQ, to the host computer through tristate write driver 26. 
     A microprocessor 28 communicates with the peripheral controller through an address data bus 30. A microprocessor write enable signal MWE is provided to the peripheral controller on line 32, and the peripheral controller provides a microprocessor interrupt MINT signal to the microprocessor on line 34. A pull-up resister 36 is provided for connection through jumper points 38 to the microprocessor. The peripheral controller provides a disable signal for write drivers 22, 24, and 26 on line 40. Assertion of the disable signal by the peripheral controller precludes data transfer from the peripheral controller to the host data bus and precludes transmission of DMAREQ and INTREQ to the host computer. 
     A second intelligent disk drive controller 210 is connected to the host computer in parallel with the first intelligent disk drive controller. The second disk drive controller is identical in configuration to the first disk drive controller. Components of the second disk drive controller include the peripheral controller 218, host data bus read drivers 220, and host data bus light write drivers 222, direct memory access request write driver 224, interrupt request write driver 226, microprocessor 228, address data bus 230, microprocessor write enable signal line 232, microprocessor interrupt signal line 234, pull-up resister 236, jumper connection points 238, and write driver disable signal line 240. The second intelligent disk drive controller has a jumper 242 connecting the jumper connect points 238. 
     A drive interconnection line 246 connects the first and second intelligent drives. This line is commonly called &#34;slave present&#34;, and is a standard connection in multiple disk drive interface cables. Interconnect line 246 is sensed by the microprocessor 28 of the first drive and the microprocessor 228 of the second drive. Firmware in the second drive microprocessor decodes the presence of jumper 242 in the second drive designating the second drive as drive 1. The second microprocessor 228 will output a &#34;slave present&#34; signal on the interconnect line 246, which is, in turn, read by microprocessor 28 in the first intelligent disk drive. 
     Operation of the second intelligent disk drive controller is identical to that described for the first intelligent disk drive controller. However, host computer commands addressed to the disk drives which result in a drive selected compare &#34;false&#34; in intelligent disk drive controller 0 will result in a disk drive selected compare &#34;true&#34; in intelligent disk drive number 1, due to the installation of the jumper 242. 
     INTREQ or DMAREQ signals acknowledging the host command will be transmitted to the host computer from the peripheral controller of only the selected drive. The drive not selected -will have the Write drivers disabled. Consequently, while both drives receive and interpret the commands from the host computer, only one drive will respond. 
     The details of the disable circuit for the write drivers is shown in FIG. 2. The configuration shown in FIG. 2 is a preferred embodiment providing for support of multiple types of host computers. For a first computer type (computers equivalent to the IBM-XT), commands to the intelligent disk drive controller will include accessing of a drive select register 250 through the first host address bus 12 and second host address bus 14 of FIG. 1. Data is written to the drive select register from the internal host data bus 252. The internal host data bus is the continuation of the host data bus 16 of FIG. 1. 
     The peripheral controller will issue an interrupt signal MINT to the microprocessor when the host computer writes to the drive select register. Data is written to the microprocessor by the host as a command block. The command block transferred through the buffer memory 253 is read by the microprocessor on the microprocessor data bus 254. The data bit of the command block representing the drive number is compared by the microprocessor with the intelligent disk drive controller drive number determined by the presence of the jumper connection. Sensing of the jumper connection may be accomplished by a direct connection of the jumper connection point to an input of the microprocessor or through a multiplexed bus architecture for configuration sensing as described in copending Patent Application for a Multiplexed Bus Architecture for Configuration Sensing by Jen and Goldstone, U.S. application Ser. No. 07/220,533, filed 7/18/88, now U.S. Pat. No. 4,866,309, and having a common assignee with the present application, the disclosure of which is herein incorporated by reference. 
     The microprocessor will write a disk selection bit to a first flip/flop 256 from the microprocessor address data bus by assertion of the microprocessor write enable signal MWE. A mode signal MODEl designating the host computer type is also provided by the microprocessor. 
     Additionally, a second control bit is provided by the microprocessor designating the configuration of the peripheral controller as an intelligent disk drive unit. This bit is written to a second flip/flop 258 from the microprocessor address data bus simultaneously with writing of the disk select bit to the first flip/flop upon assertion of MWE. The drive select bit provided by the microprocessor to the first flip/flop for the first computer type will be a &#34;1&#34; for drive selected or a &#34;0&#34; for drive not selected. A &#34;0&#34; for drive not selected will result in a high signal from the inverting output of the first flip/flop. The presence of the intelligent disk drive bit as a &#34;1&#34; in the second flip/flop and the MODE1 signal high for designation of the first computer type will, therefore, result in a &#34;true&#34; condition on NAND gate 260. This will, in turn, result in a false condition of NAND gate 262 producing a high intelligent disk drive disable signal, IDDDIS, to be transmitted to the write drivers, placing them in a tristate condition. 
     A drive selected signal from the host computer resulting in a drive select bit &#34;1&#34; in flip/flop 256 will result in a low signal from the inverting output of the flip/flop, thereby creating a false condition in NAND gate 260, and forcing the output of NAND gate 262 low, thereby enabling the tristate drivers for normal communication between the intelligent disk drive controller and the host computer. 
     If the second host computer type (computers equivalent to the IBM-AT) is interfaced to the intelligent disk drive controller, the host computer will access a plurality of registers, including a select disk and head or SDH register 264. The peripheral controller will interrupt the microprocessor by assertion of the MINT signal as discussed previously. The microprocessor will assess the host computer command and provide on the microprocessor address data bus a &#34;1&#34; in the disk select bit if the jumper is installed, and a &#34;0&#34; if the jumper is not installed. The IDD bit and the disk select bit will be written to flip/flops 256 and 258 as previously described. 
     The SDH register bit designating the selected drive, bit 4, will then be compared with the drive select bit present in flip/flop 256 through NAND gates 266 and 268. The second host computer type is interfaced; therefore, the MODE1 signal will be low, resulting in a high signal through inverter 261. NAND gate 266 receives SDH bit 4 and the inverted output from flip/flop 256 while NAND gate 268 receives the normal output of flip/flop 256 and an inversion of the SDH bit 4 through inverter 270. Based on this configuration, a &#34;11&#34; comparison or a &#34;00&#34; comparison of the two bits will result in a &#34;false&#34; indication from both NAND gates 266 and 268. The consequent high signals from NAND gates 266 and 268 will render NAND gate 262 &#34;true&#34;, resulting in a low IDDDIS signal, thereby allowing the write drivers to remain enabled. A &#34;10&#34; or &#34;01&#34; comparison of the two bits will result in a &#34;true&#34; indication from the NAND gates 266 and 268. The consequent low outputs from the NAND gates 266 and 268 will result in a &#34;false&#34; condition on NAND gate 262, providing a high IDDDIS signal, thereby disabling the write drivers. 
     A third computer communication type (computers equivalent to the IBM-PS2) is supported similarly to the second mode with alterations of the registers for drive select bit. Those skilled in the art will recognize that multiple registers may be used for interfacing multiple computer types and multiplexers provided to select appropriate bits from the registers for drive selection. Such an interface method is described in the patent application to Carl Bonke et al. for a Data Recording System Buffer Management and Multiple Host Interface Control U.S. patent application Ser. No. 07/220,531, filed 7/18/88, and having a common assignee with the present application, the disclosure of which is incorporated herein by reference. 
     The embodiment of the invention shown in FIG. 2 further includes a drive 0 status register 272 and a drive 1 status register 274, which are enabled when the invention is interfaced to the second computer type. The drive 0 status register is enabled to provide status to the host computer from the intelligent disk drive when drive 0 is addressed and no jumper is installed, thereby designating the drive as drive 0. The drive 1 status register provides status to the host computer when the drive 1 is selected, and the jumper is installed designating the intelligent disk drive controller as drive 1. 
     The embodiment shown in FIG. 2 provides for operation of the disk drive controller when interfaced to the second computer type, regardless of the presence of one or the other intelligent disk drive units. If the second drive (drive 1) is not present, the first intelligent drive will continue to be operable without modification. The interconnect line 246, previously described, will no longer be connected to the second drive. The microprocessor of the first intelligent drive, sensing a slave not present, will not provide a &#34;1&#34; in the IDD bit for the second flip/flop 258 of FIG. 2. The IDDDIS signal will, therefore, not be asserted. The drive 0 status for the first intelligent disk drive will be provided to the computer upon request through the drive 0 status register 272. If the host computer attempts to access the second intelligent disk drive, or drive 1, the first intelligent disk drive will provide a &#34;drive not ready&#34; condition in the drive 1 status register 274. 
     Similarly, the second intelligent disk drive, if present without the first intelligent disk drive, may provide similar capability, giving a drive 0 &#34;not ready&#34; signal in response to attempted access of the first disk drive by the host computer while providing a &#34;normal&#34; status for the second disk drive on the drive 1 status register. 
     Similar operation may be achieved for the first host computer type through control of the drive status register 276 by the microprocessor. Attempted access by the host computer of the missing disk drive will result in a &#34;drive busy&#34; status, while attempted access of the host computer of the disk drive which is present will result in a &#34;normal&#34; drive status provided to the drive status register. 
     The invention as shown in the embodiment will be operable, regardless of the presence of a second drive, without reconfiguring the jumper. This provides a distinct advantage over the prior art where absence of the second disk drive in either the master or slave condition designated by the three jumpers, as previously described, requires alteration of the jumper connections to provide proper operation. 
     Having now described the invention in detail in accordance with the requirements of the Patent statutes, those skilled in this art will have no difficulty in making changes and modifications in the individual circuit elements, or their relative connections, in order to meet specific requirements or conditions. Such changes and modifications may be made without departing from the scope and spirit of the invention as set forth in the following claims.