Two level multiplexer circuit shifter apparatus
BACKGROUND OF THE INVENTION 
     1. Field of Use 
     The present invention relates to apparatus for shifting information and more particularly to shifting apparatus which can be efficiently implemented in gate array form. 
     2. Prior Art 
     To satisfy the demand for large scale digital integrated circuits, the semiconductor industry has developed three basic approaches. These include standard off-the-shelf circuits, custom circuits and gate arrays. The gate array involves the use of a standard array of a large number of gate circuits diffused into a chip. The metalization pattern converting these gate circuits into functional custom circuits is processed according to the customer&#39;s requirements. 
     A macrocell array is an extension of the gate array concept. A macrocell is an array subsection performing a higher level logic function than a basic gate. A macrocell array is an array circuit in which macro functions used to define logic simulations are directly implemented within the basic cell structure rather than formed by interconnecting gates. Each cell in a macrocell array contains a number of unconnected transistors and resistors. A metalization process transforms the interconnected transistors and resistors within each cell into Small Scale Integrated (SSI) logic functions called macros. The macros take the form of standard logic elements such as dual type &#34;D&#34; flip-flops, multiplexers and many other functions. 
     The high density packing of a macrocell array chip offers substantial reductions in system component count and power dissipation. Thus, it becomes desirable to utilize such chips in computer designs. 
     With recent advances, it is possible for a processor to execute millions of instructions per second (MIPS). Many different types of such instructions simply involve the transfer or manipulation of operands through high speed adder circuits. 
     This can be easily accomplished within a system or machine cycle of operation. However, it is much more difficult and time-consuming to perform shifting types of operations within the same time period particularly where large operands are involved. This has been found to be particularly true where shifting networks have utilized shift registers and multiplexers. In shift register implementations, the time required to execute a multibit shift is normally dependent upon the number of shifts required. Multiplexer implementations using single bit or several bits at a time shifts require several passes or cycles in order to provide larger operand shifts, in addition to requiring a considerable number of interconnections. 
     The interconnection problem is compounded when a large number of bits are required to be shifted at a time. For example, it was found that when it was attempted to simply expand a prior art multiplexer arrangement capable of shifting right or left by eight bits for a total shift of 16 to accommodate a larger number of shifts, it was found to be too slow and require a considerable amount of chip area when implemented in macrocell array form. 
     Accordingly, it is a primary object of the present invention to provide a shifter in which multibit shifts can be achieved within a single cycle of operation. 
     It is a further object of the present invention to provide a shifter which has a minimum number of interconnections and multiplexer circuits so as to be readily implementable in macrocell array form. 
     SUMMARY OF THE INVENTION 
     The above and other objects are achieved in a preferred embodiment of the shifter apparatus of the present invention. The apparatus receives from a plurality of input switching circuits the input operand signals to be shifted. These signals are selectively applied to the inputs of the multiplexer circuits of a first level or stage. The outputs are applied to a smaller number of multiplexer circuits of a second level or stage. 
     Additionally, the input switching circuits apply to the shift control circuits of the shifter apparatus, a set of shift control signals coded to specify the direction and amount of shifts to be applied to said input operand signals. The shift control circuits generate first and second sets of signals which are separately applied to the first and second levels of multiplexer circuits. These sets of control signals are coded to condition the first and second stage multiplexer circuits to select as outputs, the appropriate sets of input operand signals and shifted operand input signals required to provide as outputs of the second stage multiplexer circuits, operand signals shifted by the specified number of bit positions. 
     In more particular terms, the first and second stages of multiplexer circuits, each include means for shifting signals applied as inputs by a selectable number of different shifts in selected directions. For example, in the preferred embodiment, an operation specifying a left shift of 20 bit positions produces within the first and second stages left shifts of 14 bit positions and 6 bit positions, respectively. By contrast, an operation specifying a right shift of 20 bit positions produces within the first and second stages right shifts of 13 and 7 bit positions, respectively. However, operations specifying left and right shifts of 10 bit positions produce within the first and second stages left and right shifts of 18 and 8 bit positions and right and left shifts of 17 and 7 bit positions. 
     It is seen that the result is that the resulting algebraic addition of sum of the shifts by both stages provides as an output, the input operand shifted by the specified number of positions within a minimum of time. The arrangement of the present invention requires only a small number of selectable shifts to be provided within each stage which minimizes the number of interconnections between stages. 
     The above arrangement has the advantage of minimizing the number of interconnections and multiplexer circuits. This enables the arrangement to be implemented in macrocell array form within a small area using standard macrocells. 
    
    
     The above and other objects and advantages of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a system which includes the shifter apparatus of the present invention. 
     FIGS. 2a through 2e show in greater detail, different portions of the system and shifter of FIG. 1. 
     FIG. 3 is a diagram used to explain the operation of the shifter apparatus of the present invention. 
     FIGS. 4a through 4d are diagrams which are used to describe how different types of shift operations are performed by the present invention. 
     FIG. 5 is a flow diagram illustrating the overall operation of the shifter apparatus of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows in block diagram form, a portion of a pipelined processing unit (CPU) 10 which includes the shifter apparatus of the present invention. As shown, the CPU 10 includes the shifter apparatus of the present invention. As shown, the CPU 10 includes an instruction (I) unit 10-2 and an A unit 10-4. The instruction unit 10-2 performs the function of prefetching instructions from an instruction cache unit, not shown, and &#34;cracking&#34; each instruction fetched to determine how the other units, such as the A unit 10-4, will process that instruction. 
     The A unit 10-4 generates the addresses from instructions it receives from I unit 10-2 which are loaded into an instruction register 10-46. Additionally, it completes the execution of certain types of instructions (e.g. register to register instructions) thereby removing them from the pipeline in a production line fashion. Accordingly, it is important for the A unit 10-4 to be able to complete instructions as fast as possible in order to maintain a high level of performance. 
     The A unit 10-4 includes a register file memory 10-44 which contains 64 32-bit register locations used to store the contents of registers which are programmer accessible; that is, so-called software visible registers. Also, register file memory 10-44 also includes a number of private registers which are only accessible by the A unit 10-4. 
     Register file memory 10-44 has dual port read outputs RFA and RFB through which data signals are transferred to shifter 10-42. The ports are addressed by addresses applied to A and B port address inputs AAD and BAD. Writing or updating the contents of file register locations takes place via a write port RFC through a multiposition selector switch 10-45 which has as an input the output of shifter 10-42. 
     Additionally, A unit 10-4 includes a microprogrammed control store unit represented by block 10-40. In the preferred embodiment, the unit is located off the A unit chip. Control Store unit 10-40 stores sequences of 64-bit microinstruction words which are read out and loaded into an RDR output register 10-48 for use in executing instructions received from I unit 10-2. 
     As shown, A unit 10-4 further includes a Q register input source and a shifter represented by block 10-42 for performing a variety of operations in response to instructions received from I unit 10-2. The shifter 10-42, constructed according to the teachings of the present invention, is capable of performing shifting operations within a single CPU or machine cycle of operation. As shown, shifter 10-42 has an input section 10-400, a shifter control circuit 10-420 and a two-level shift network 10-440. Input section 10-400 includes a plurality of operand input multiposition selector switches 10-402a through 10-402c designated as SIN1, SIN2 and SIN3 which connect to ports RFA and RFB of register file memory 10-44, as shown. A further multiposition switch 10-402d, included in input section 10-400, is connected to receive shift control signals from instruction register 10-46, RDR register 10-48, register file memory 10-44 and Q register 10-49, as shown. 
     Each of the switches 10-402a through 10-402d receive a number of control signals from RDR register 10-48. These signals select which input source is connected to apply signals to the output terminals of switches SIN1, SIN2 and SIN3. The control signals are derived from different control fields included within the microinstruction word stored in RDR register 10-48. The codings of the bits included in each of these fields are shown in detail in FIG. 2a. 
     The shift control 10-420 receives a 5-bit function code corresponding to signals SHIFT1 through SHIFT5 from any one of the sources which connect to control switch 10-402d. A sixth signal corresponding to signal SHIFT0 is provided by RDR register bit position 16, as shown. Shift control 10-420 includes a number of logic gates which decode the 6-bit code into two sets of signals used to control the operation of the shifter network 10-440. These gates are shown in detail in FIG. 2b. 
     Referring to FIG. 2b, it is seen that shift control 10-420 includes a pair of exclusive NOR gates 10-421a and 10-421b which combine signals SHIFT2 and SHIFT3 to produce output signals AL1 and BL1. These signals, along with signal SHIFT0 relabeled as CL1, are applied to the control input terminals A, B and C of each multiplexer circuit which make up a first stage (level 1) of shifter network 10-440. 
     A group of exclusive OR gates 10-422a through 10-422c combine signals SHIFT0, SHIFT1, SHIFT4 and SHIFT5 to produce output signals AL2, BL2 and CL2. These signals are applied to the control input terminals A, B and C of each multiplexer circuit which make up a second stage (level 2) of shifter network 10-440. 
     It is seen in FIG. 1 that the level 1 stage includes 53 multiplexer circuits which are connected to receive different combinations of input signals from switches SIN1, SIN2 and SIN3. The outputs of the level 1 multiplexer circuits are applied as inputs to the 34 multiplexer circuits of the level 2 stage. FIG. 2e shows the manner of connecting inputs to the multiplexer circuits of each stage. Referring to the FIGURE, it is seen that the level 1 or first stage multiplexer circuits (M1) have inputs I (43+j) through I (0+j) where j has the values 0 to 52 for each of the eight inputs. The level 2 or second stage multiplexer circuits (M2) receive first stage multiplexer outputs (0+k) through (19+k) where k has the values 0 to 33 for each of the eight inputs. The first multiplexer circuit M2(0) provides the carry left or end around input while the last multiplexer circuit M2 (33) provides the carry right input. 
     The network shifter stages are so arranged to require a minimum number of interconnections and multiplexer circuits. FIG. 2c diagrammatically illustrates the organization of shifter network 10-440 in greater detail. The FIGURE shows different portions or sections of the design and interconnects. It is seen that layout has been simplified with a small number of interconnects required between the first and second stages. 
     In the preferred embodiment, a standard CMOS multiplexer macrocell is used to implement shifter network 10-440. A block diagram of this macrocell is shown in FIG. 2d. From FIG. 2d, it is seen that the macrocell is an 8-bit non-inverting multiplexer circuit which has a set of eight data input pins D0 through D7, a set of three control pins A, B and C and an output pin Z. The selection of data inputs is defined by the table in FIG. 2d. The multiplexer circuit takes the form of the macrocell designated as MUX81P, manufactured by LSI Logic Corporation. For further information regarding this part, reference may be made to The HCM05 Compacted Array Products Databook, published by LSI Logic Corporation, Copyright 1987. 
     The interconnections provide the means of selecting a small number of shifts or shift distances within each stage which collectively provide the desired amount of shift. These shift values are shown by the matrix in an Appendix. Referring to the Appendix, it is seen that for the first stage, each of the selectable right and left shift distances differ by a constant whose value equals 4. Therefore, the four right shift distance values can be expressed as n, n+k, n+2k and n+3k where n=9 and k=4. The left shift distance values are m, m+k, m=2k and m+3k wherein m=n+1 or 10. 
     In the case of the second stage, the four left and right shift distance values can be similarly expressed. The right shift distance values are n, n+k, n+2k and n+3k where n=7 and k=1. The left shift distance values are m, m+k, m+2k and m+3k wherein m=n-1 or 6. The logical sum of shifts n+m performed by both stages corresponds to the number of shifts specified by the shift instruction. For example, if a 9-bit left shift operation is specified, Appendix A indicates that the shift distance values are left 18 and right 9. The resulting or &#34;logical &#34; sum of these values is the algebraic addition of +18-9=9=L9 wherein L is positive or + and R is negative or -. 
     DESCRIPTION OF OPERATION 
     With reference to the diagram of FIG. 4, the operation of shifter 10-42 will now be described. As previously discussed, shifter 10-42 is used to perform operations specified by a number of different program instructions. These include both single and double bit operand instructions such as single or double shift arithmetic left, right closed left or closed right and open left or open right. For each of these instructions, shifter 10-42 performs the shifting of a single operand from 0 up to 31 positions within a time period to enable the instruction to be completed within a single CPU cycle. An additional cycle of time is required only for those double operand instructions designating two register locations to receive the shifted operand result for purposes of program compatibility. 
     The shifter 10-42 of the present invention performs the shift operations specified by these instructions under the control of the specific fields of microinstruction words shown in FIG. 2a which are read out into RDR register 10-48 during a machine cycle of operation in response to such instructions. Each A unit or machine cycle is 140 nanoseconds. During the first part of each cycle, the contents of an A unit register file memory location are read out. During the remaining part of the cycle, the A unit performs the operation specified by the instruction stored in instruction register 10-46. Near the end of the cycle, the resulting shifted operand produced by shifter 10-42 is applied to register file memory and written into the designated location. 
     The A register file memory 10-44 locations include seven 16-bit general word operand registers designated as R1 through R7, seven 32-bit address registers designated as B1 through B7 and seven 32-bit double word registers designated as K1 through K7. For further information concerning the organization of register file memory 10-44, reference may be made to the copending patent application of David E. Cushing, Richard P. Kelly, Robert V. Ledoux and Jian-Kuo Shen entitled, &#34;A Mechanism for Automatically Updating Multiple Unit Register File Memories,&#34; bearing Ser. No. 07/286,551, filed on Dec. 19, 1988, which is assigned to the same assignee as named herein. 
     FIG. 3 illustrates the manner in which shifter 10-42 executes shifting operations performed on a 32-bit operand received from register file memory 10-44. As shown in FIGS. 4a through 4d, the operand signals applied to the SIN1, SIN2, and SIN3 switches of the input section of shifter 10-42 differ as a function of the type of shift instruction being executed. 
     Referring to FIG. 4a, it is seen that for a 32-bit operand shift right open instruction, the 32-bit operand received from the register file memory 10-44 is selected as the output of the SIN2 switch while an ALL ZERO input is selected as the output of the SIN1 switch. In the case of a 32-bit operand shift left open instruction, the outputs from the SIN1 and SIN3 switches are reversed as shown in FIG. 4b. 
     FIGS. 4c and 4d show that two of the switches, SIN1 and SIN2 or SIN2 and SIN3 are used to provide operand outputs for 32-bit operand shift right closed and left closed instructions respectively. Similar combinations of switch outputs are selected for the execution of the other types of shift instructions. 
     With reference to FIG. 3, it will be assumed by way of example that the A unit 10-4 is required to execute shift instructions which cause shifter 10-42 to perform the different bit shift operations indicated in FIG. 3. In the first example, it is assumed that shifter 10-42 is required to shift an operand left 7 bit positions. This type of operation could result from executing either a shift left open or shift left closed instruction. 
     In either case, the shift instruction causes a microinstruction word to be read out into RDR register 10-48. Referring to FIGS. 2a, 4a and 4b, it is seen that the bits of positions 25-26, 28-29, and 30-31 of the microinstruction word are so coded to cause the selection of positions 2 and 0 of the SIN1 and SIN2 switches respectively for the shift right open instruction or positions 0 and 3 of the SIN2 and SIN3 switches respectively for a shift left open instruction. 
     Since the operand bits will overlay the bits to the right in the case of the shift right open instruction, the output from switch SIN3 is represented as &#34;don&#39;t care.&#34; However, in the case of the shift left open instruction, the output of the SIN3 switch must be all ZEROS since it will form part of the resulting shifted operand. However, the output from switch SIN1 is labeled &#34;don&#39;t care&#34; since these bits will be overlaid as in the case of the SIN3 switch output. 
     As seen in FIG. 2a, the bits of positions 17-19 of the microinstruction word are coded to select the appropriate position of the SHFTCTL switch 10-402d of the shifter input section 10-402. In the case of both of the above instructions, the output of position 3 of the SHFTCTL switch is selected. The bits corresponding to 1-5 are coded to specify up to a 31-bit position shift. 
     According to the present invention, these bits are interpreted or decoded by the shift control circuits 10-420 of FIG. 2b. As mentioned, the shift control circuits 10-420 generate the two sets of three-bit control codes. A different set is applied to the control inputs of the multiplexer circuits of both stages. The generation of each set of codes is carried out according to the matrix of the Appendix. 
     More specifically, the most significant bit is coded to indicate the direction of the shift. For first stage operations, a binary &#34;0&#34; significant bit designates a shift left while for second stage operations, it designates a shift right operation. This is due to the reversal of the left and right inputs in the second stage multiplexer circuits to facilitate layout shown in FIG. 2e. The next two bits are coded to specify the number of shifts or shift distance. That is, referring to FIG. 2b, it is seen that signals CL1 and CL2 designating the direction, select the appropriate first or second half multiplexer inputs. The other two signals (AL1, BL1 and AL2, BL2) select one of the former inputs which provides the required number of shifts. 
     In the first example, in order to effect the shift left 7 operation in FIG. 3, the first stage of multiplexer circuits are conditioned to perform a left shift of 14 bit positions and the second stage of multiplexer circuits are conditioned to perform a right shift of 7 bit positions. As seen in FIG. 2e, input I44 corresponds to input D2. The code applied to the control inputs of the first stage multiplexer circuits causes the selection of the D2 input. That is, the shift control circuits 10-420 apply a code of &#34;010&#34; which is applied to the first stage multiplexer circuits. This causes the D2 input of each circuit of FIG. 2d to be selected as the Z output. The result is that the operand output from the SIN2 switch applied to the first stage is shifted left by 14 bit positions. 
     The binary &#34;0&#34; in the most significant bit of the &#34;010&#34; code indicates the left shift direction and causes the selection of the first half of the multiplexer inputs of the first stage multiplexer circuits which have been assigned to left shift operations as shown in FIG. 2e. The next two bits &#34;10&#34; select the left fourteen (L14) input D2 of each first stage multiplexer circuit. 
     The shift left by 7-bit operation is diagrammatically illustrated in FIG. 3 relative to the shifting of bit 12 from switch SIN2. As shown, bit 12 corresponds to input bit 44. The result is that bit 44 which is applied as an input to first stage multiplexer circuit M1 (9) is selected as an output which is to be applied to the second stage. 
     At the same time, the shift control circuits 10-420 apply a code of &#34;011&#34; to the control inputs of the second stage multiplexer circuits. This causes the D3 input of each circuit of FIG. 2d to be selected as the Z output. This results in the operand outputs applied to the second stage by the first stage being shifted by 7 bit positions. The different bits of the binary code applied to the second stage control inputs function in the same way as described above. That is, the most significant bit is used to select the first half of multiplexer inputs and the remaining bits are used to select the amount of shift or shift distance. However, the binary &#34;0&#34; the most significant bit designates a right shift direction instead of a left shift direction as in the case of the first stage multiplexer circuits. 
     As shown in FIG. 3, bit 12 corresponding to the output of first stage multiplexer circuit 9 is selected as the output of multiplexer circuit 5 of the second stage in response to code &#34;011.&#34; The D3 outputs of the remaining second stage multiplexer circuits are similarly selected. The sum of the shift distances provided by both shifter stages produces left 7 bit shifted operand (i.e., L14+R7). 
     The shift right 7 operation illustrated in FIG. 3 is carried out in a similar manner. As seen from Appendix A, a shift right of 7 bit positions, requires that the first stage shift the input operand right by 13 bit positions and that the second stage shift left its inputs by 6 bit positions. The shift control circuits 10-420 generate sets of codes (i.e., &#34;110&#34; and &#34;100&#34;) which are applied to the control inputs of the first and second multiplexer circuits required to perform the required shifts. 
     In FIG. 3, the code &#34;101&#34; causes bit 12 of switch SIN2, which corresponds to input R13, to be selected as the output of multiplexer circuit 36. The bits applied to the D5 inputs of the remaining first stage multiplexer circuits as similarly selected. The code &#34;100&#34; causes the shifted bit 12 output from multiplexer circuit 36 which corresponds to input L6 to be selected as the output of second stage multiplexer circuit 19. The bits applied to the D4 inputs of the remaining second stage multiplexer circuits are similarly selected. The sum of the shift distances provided by both shifter stages produces the right 7 bit shifted operand. 
     FIG. 3 further illustrates the flow of bit 12 from switch SIN2 as a result of being shifted left and right by 21 bit positions. These operations would be specified by 32 bit operand shift left and shift right closed instructions. They cause the combinations of SIN1, SIN2 and SIN3 switches to select the outputs shown in FIGS. 4c and 4d. In greater detail, for the shift right closed instruction, bits 27-29 and 30-31 of the microinstruction word are coded to select position 0 of switches SIN2 and switch SIN3 which apply the operand inputs to the first stage multiplexer circuits. 
     Bit positions 17-19 of the microinstruction are coded to select position 3 of the SHFTCTL switch. The shift control circuits 10-420 generate the appropriate sets of control code signals. The codes for the 21-bit right shift are &#34;101&#34; and &#34;010.&#34; As seen from FIG. 3, the code &#34;101&#34; causes bit 12 of switch SIN1 applied as input R13 to be selected as the output of first stage multiplexer circuit 4. The bits applied to the D5 inputs of the remaining first stage multiplexer circuits as similarly selected. The code &#34;010&#34; causes shifted bit 12 output of switch SIN2 corresponding to input R8 to be selected as the output of second stage multiplexer circuit. The bits applied to the D2 inputs of the remaining second stage multiplexer circuits are similarly selected. The sum of the shift distances provided by both shifter stages (i.e., R13+R8) produces the specified 21-bit right shifted operand. 
     In a similar fashion, the left shift closed instructions causes shifter 10-40 to perform a 21-bit left shift operation. This causes operand inputs to be applied from position 0 of switches SIN2 and SIN3. In this example, the bit 12 output of switch SIN3, corresponding to input 76, is shifted left by 14 bit positions by first stage multiplexer circuit 41 and is then shifted left by 7 bit positions by second stage multiplexer circuit 23 as shown in FIG. 3. The remaining operand bits are similarly shifted. The sum of the shift distances (i.e., L14+L7) produces the specified 21-bit left shifted operand. 
     From the above examples, it is seen how the shifter of the present invention is able to execute a variety of shifting operations within one cycle. The overall operation of the shifter is summarized in the flow chart of FIG. 5. It is assumed that the register file memory location into which the shifted operand is being written is assumed to have the same number of bit locations. The shifter of the present invention can also be used with register file memory register locations having half or double the number of bit locations. In such cases, another cycle of operation would be required to complete the operation. 
     It will be appreciated that many changes may be made to the preferred embodiment of the present invention without departing from its teachings. For example, the invention is not limited to the use of a particular macrocell or technology. 
     While in accordance with the provisions and statutes there has been illustrated and described the best form of the invention, certain changes may be made without departing from the spirit of the invention as set forth in the appended claims and that in some cases, certain features of the invention may be used to advantage without a corresponding use of other features. 
     
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APPENDIX                                                                  
First stage          Second stage                                         
Right        Left    Right   Left                                         
Shift                                                                     
     21                                                                   
       17                                                                 
         13                                                               
           9 22                                                           
               18                                                         
                 14                                                       
                   10                                                     
                     10                                                   
                       9 8 7 9 8 7 6                                      
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Left 1             X   X                                                  
Left 2             X     X                                                
Left 3             X       X                                              
Left 4           X   X                                                    
Left 5           X     X                                                  
Left 6           X       X                                                
Left 7           X         X                                              
Left 8         X     X                                                    
Left 9         X       X                                                  
Left 10        X         X                                                
Left 11        X           X                                              
Left 12      X       X                                                    
Left 13      X         X                                                  
Left 14      X           X                                                
Left 15      X             X                                              
Left 16            X               X                                      
Left 17            X             X                                        
Left 18            X           X                                          
Left 19            X         X                                            
Left 20          X                 X                                      
Left 21          X               X                                        
Left 22          X             X                                          
Left 23          X           X                                            
Left 24        X                   X                                      
Left 25        X                 X                                        
Left 26        X               X                                          
Left 27        X             X                                            
Left 28      X                     X                                      
Left 29      X                   X                                        
Left 30      X                 X                                          
Left 31      X               X                                            
By 0       X                 X                                            
Right 1    X                   X                                          
Right 2    X                     X                                        
Right 3    X                       X                                      
Right 4  X                   X                                            
Right 5  X                     X                                          
Right 6  X                       X                                        
Right 7  X                         X                                      
Right 8                                                                   
       X                     X                                            
Right 9                                                                   
       X                       X                                          
Right 10                                                                  
       X                         X                                        
Right 11                                                                  
       X                           X                                      
Right 12                                                                  
     X                       X                                            
Right 13                                                                  
     X                         X                                          
Right 14                                                                  
     X                           X                                        
Right 15                                                                  
     X                             X                                      
Right 16   X               X                                              
Right 17   X             X                                                
Right 18   X           X                                                  
Right 19   X         X                                                    
Right 20 X                 X                                              
Right 21 X               X                                                
Right 22 X             X                                                  
Right 23 X           X                                                    
Right 24                                                                  
       X                   X                                              
Right 25                                                                  
       X                 X                                                
Right 26                                                                  
       X               X                                                  
Right 27                                                                  
       X             X                                                    
Right 28                                                                  
     X                     X                                              
Right 29                                                                  
     X                   X                                                
Right 30                                                                  
     X                 X                                                  
Right 31                                                                  
     X               X                                                    
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