Digital deemphasis circuit
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is in the field of digital deemphasis circuits for volume-compressed, amplitude-normalized audio signals which are digitized in the two&#39;s complement binary system, and, in particular, in the field of digital deemphasis circuits which can be implemented in the audio sections of television receivers designed to receive the Electronics Industries Association (EIA) Broadcast Television Systems Committee (BTSC) multichannel television standard 
     2. Description of the Related Art 
     The EIA BTSC is a relatively new standard for transmission of stereo information with the simultaneous opportunity for broadcasting a separate second audio program. The system of this standard is described in detail, for example, in Leslie B. Tyler, et al., &#34;A COMPANDING SYSTEM FOR MULTICHANNEL TV SOUND,&#34; IEEE Transactions on Consumer Electronics, November 1984, pp. 633-640. In that article, the individual subcircuits in the described system are presented as analog-signal-processing circuits. Of particular interest in connection with the present invention are FIGS. 5 and 15 and the text of the description on pages 636.639. 
     It is desirable to use digital circuits in place of analog circuits in modern television receivers. The prior-art analog circuits described in the Tyler, et al., article, like many other analog circuits, cannot be readily converted to corresponding digital circuits for processing signals digitized by an analog-to-digital converter because, in the present case for example, such a direct replacement of analog circuits by corresponding digital circuits would lead to a feedback control loop without delay, which cannot be implemented digitally. 
     SUMMARY OF THE INVENTION 
     The present invention is a digital deemphasis circuit for use in processing digitized audio signals in a television receiver. The circuit is used in the television receiver to offset the preemphasis applied in accordance with the BTSC standard at the transmitting end. The deemphasis circuit according to the present invention can be readily implemented in the form of semiconductor integrated circuits and can be used to advantage in so-called digital television receivers. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will now be explained in greater detail with reference to the accompanying drawings, in which: 
     FIG. 1 illustrates a highly schematic block diagram of a first embodiment of the invention; 
     FIGS. 2a and 2b illustrate two curves used to explain the operation of a subcircuit of FIG. 1; and 
     FIG. 3 illustrates a highly schematic block diagram of a second embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIGS. 1-3 of the drawings, it is assumed that a digital audio signal ss has been separated from a received television-transmitter signal and has been digitized by means of a conventional analog-to-digital converter to obtain signals in the two&#39;s complement binary system, and that the digital signals have been normalized in amplitude so that the amplitudes lie only in the digital number range between greater than or equal to -1 and less than +1 (i.e., -1≦amplitude&lt;+1). (The range limit &#34;equal to +1&#34; has been deliberately omitted, since in the two&#39;s complement binary system, as is well known, there is no positive 1 in left-justified representation, which is used in the present case.) 
     In FIG. 1, the audio signal ss is applied to the minuend input of a first subtracter s1, whose output controls the input of a digital filter df. The digital filter df has a transfer function: 
     
         F(z)=(b-ac)/(z+a), 
    
     where z, as is usual in the mathematical treatment of digital filters, is the complex frequency variable, and a, b and c are constants which determine the frequency response of the digital filter so that the deemphasis function conforming to the BTSC standard is obtained. Preferred decimal numerical values for the three constants are: 
     
         a=-118/128, 
    
     
         b=2/128, 
    
     
         c=8/128 
    
     The output of the digital filter df is connected to the first input of a first multiplier ml and to the first input of a second multiplier m2. The output of the first multiplier ml is coupled to the first input of a first adder al, and the output of the second multiplier m2 is coupled to the subtrahend input of the first subtracter s1. The output of the first subtracter s1 is coupled to the first input of a third multiplier m3, whose output is connected to the second input of the first adder al. The output of the first adder a1 provides the output signal of the deemphasis circuit. 
     The audio signal ss is also fed to the input of a band-pass filter bp. The band-pass filter bp is easy to implement as it is the counterpart of, and has virtually the same transfer function as, the corresponding analog band-pass filter of the above-mentioned Tyler, et al., reference. In particular, see FIGS. 9 and 10 and the description thereof in the left-hand column of page 637 of the Tyler, et al., reference. The output of the bandpass filter bp feeds a first squarer q1, which has an output that is applied through a low-pass filter tp to the minuend input of a second subtracter s2. The low-pass filter tp has a cutoff frequency which is of the order of 10 Hz. 
     The output of the second subtracter s2 is coupled to the input of a first accumulator k1, which is a limiting accumulator. The first accumulator k1 includes an internal adder (not shown) and an intermediate store (not shown) which operate in a conventional manner. The limiting first accumulator k1 is designed so that if either of the two above-mentioned limits of the number range is reached or if the results of additions by the adder exceed those limits, the internal adder of the first accumulator k1 will only deliver a signal representative of the respective limit. Expressing this in an example using decimal numbers, if the result of an addition is -2, the adder will limit its output to -1. Similarly, if the result is +1.5, the output will be limited to that next lower number than +1 which is possible with the number of bits of the audio signal 
     The intermediate store in the first accumulator k1 is a register, or the like, via which the output of the adder in the first accumulator k1 is fed back to one input of the adder after being delayed by one period of the clock system controlling the digital signal processing. In the present invention, the first accumulator k1 has a first output 1 and a second output 2. The first output 1 of the first accumulator k1 is the output of the adder and is shown as a signal v. The second output 2 of the first accumulator k1 is the output of the intermediate store The second output 2 is coupled to the inputs of a second squarer q2. The second squarer q2 has an output that is connected to the subtrahend input of the second subtracter s2. 
     The subcircuit comprising the second subtracter s2, the first accumulator and the second squarer q2, represents a surprisingly simple square-root extractor. In the second squarer q2, deliberate use is made of the fact that in the two&#39;s complement system, the square of the most negative number, -1, is not +1, but -1 again. (In left-justified two&#39;s complement numbers, the first zero is comparable to the zero before the point of a decimal fraction and is also the sign bit, while a one in this position gives the negative sign but is not comparable to the one before the point of a decimal fraction.) 
     The square-root extractor subcircuit (i.e., s2, k1, q2) compares the squared output value from the first accumulator k1 with the value of the audio signal ss fed to the subtracter s2, so that after a few sampling steps, the value corresponding to the square root of the output signal from the low-pass filter tp will appear at the output of the accumulator k1. This operation of the square-root extractor subcircuit is shown for two different initial conditions in FIGS. 2a and 2b. For ease of illustration, the y-axes of the two figures are marked with decimal values between +1 and -1, and the x-axes are marked with a few sampling instants of the above-mentioned clock system. The sampling instants are numbered from 1 to 7. 
     FIG. 2a illustrates the case where the output of the low-pass filter tp has the value 0.25=2 -2  over the seven sampling instants, and where the intermediate store of the first accumulator k1 has an initial value of 0 (zero). As shown in FIG. 2a, the signal v provided at the first output 1 of the first accumulator K1 (i.e., at the output of the adder of the first accumulator k1 converges with sufficient accuracy toward the square root of 0.25, namely 0.5 already at the third sampling instant (3). 
     In FIG. 2b, the value of the low-pass filter output, 0.25, is again assumed to be constant over the seven sampling instants, but the initial value assumed for the signal at the output of the intermediate store has an inch initial value of -0.55. FIG. 2b shows that in this case, also, the signal v converges toward the target value 0.5. It is interesting that first, at the first, second and third sampling instant numbers (1, 2 and 3) the square-root extractor subcircuit (s2, k1, q2) tends toward increasingly negative numbers, and that only after reaching -1 does it &#34;jump&#34; to the positive number range, from where it converges monotonically toward the target value 0.5. 
     The frequency of the clock system is much higher than the frequency required by the sampling theorem. Thus, a &#34;transient time&#34; of several sampling periods is readily permissible. 
     The signal v appearing at the first output of the first accumulator k1, which, as mentioned above, represents the root-mean-square value, is applied to the input of a first constant multiplier km1, which multiplies by the constant -c. The output of the first constant multiplier km1 is coupled to the first input of a second adder a2. The output of the second adder a2 is connected to the first input of a fourth multiplier m4. The output of the fourth multiplier m4 is coupled to the first input of a third adder a3. The second inputs of the second and third adders a2, a3 are fed with a signal for the constant number -1. 
     The output of the third adder a3 is connected to the input of a second accumulator k2, which is preferably a limiting accumulator similar to the first accumulator k1, and which has a first output 1 and a second output 2. The first output 1 of the second accumulator k2 is coupled to the input of a second constant multiplier km2, which multiplies the input by -1. The output of the second constant multiplier km2 is a signal w1 which is applied to the second input of the first multiplier m1, to the first input of a fifth multiplier m5, and to the input of a third constant multiplier km3. The third constant multiplier km3 multiplies the value at its input by the constant c. The first input of a fourth adder a4 is connected to the output of the fifth multiplier m5, and the second input of the fourth adder a4 is connected to the output of the third constant multiplier km3. The output of the fourth adder a4 is a signal w3 which is coupled to the second input of the third multiplier m3. The output of the fifth multiplier m5 is a signal w2 which is coupled to the second input of the second multiplier m2. 
     In the second embodiment of the invention, illustrated in FIG. 3, the lower portion of the figure is identical with the lower portion of FIG. 1 and the elements are identified the same. Only the upper portion of FIG. 3, having elements identified with reference characters provided with a prime, differs from the corresponding portion of FIG. 1. The difference between the two embodiments comprises the different arrangement and interconnection of the first, second and third multipliers m1&#39;, m2&#39;, m3&#39;, the first subtracter s1&#39;, the first adder a1&#39;, and the digital filter df&#39;, while the control (i.e., the inputs to the first, second and third multipliers m1&#39;, m2&#39;, m3&#39;) from the lower portion of FIG. 3 is the same as in FIG. 1. 
     In FIG. 3, the audio signal ss is applied to the first input of the first multiplier m1&#39; and to the first input of the third multiplier m3&#39;. The output of the first multiplier m1&#39;, is coupled to the minuend input of the first subtracter sl&#39;, whose output is connected to the input of the digital filter df&#39;. The digital filter df&#39; has the same transfer function as the digital filter df of FIG. 1. The output of the digital filter df&#39; is connected to one input of the first adder a1&#39;. The second input of the first adder a1&#39; is connected to the output of the third multiplier m3&#39;. The output of the first adder a1&#39; is again the output of the deemphasis circuit. 
     The subtrahend input of the subtracter sl&#39; is connected to the output of the second multiplier m2&#39;. The first input of the second multiplier m2&#39; is connected to the output of the first adder a1&#39;. The second input of the second multiplier m2&#39; is connected to the output of the fifth multiplier m5 and receives the signal w2 therefrom. The second input of the first multiplier m1&#39; is connected to the output of the second constant multiplier km2 and receives the signal w1 therefrom. The second input of the third multiplier m3&#39; is connected to the output of the fourth adder a4 and receives the signal w3 therefrom. 
     In both embodiments of the invention, the above-mentioned conversion of the analog circuit to the desired digital circuit is accomplished essentially by transforming the signal v, which corresponds to the analog root-mean-square control signal, by means of the subcircuit following the first accumulator k1 into three signals w1, w2, w3, which are fed to the three multipliers ml, m1&#39;; m2 m2&#39;; m3, m3&#39;. To a very good approximation 
     
         w1=1/(1+cv); 
    
     
         w2=v/(1+cv)=vw1; 
    
     
         w3=(c+v)/(1+cv)=cw1+w2. 
    
     To form the signal w1, use is made of a feedback control loop comprising the fourth multiplier m4, the third adder a3, and the second accumulator k2. The control loop is comparable to the above-described square-root extractor (i.e., the second subtracter s2, the first accumulator k1 and the second squarer q2), and by which the signal w1 is increased if too small, and increased if too large. The signals w1, w2, w3 are thus dependent only on the constant c and the signal v.