Driver for a high efficiency, high frequency Class-D power amplifier
RELATED APPLICATIONS 
     This application is related to Korman et al. application entitled &#34;Half Bridge Device Package, Packaged Devices and Circuits&#34;, Ser. No. 454,550, and to El-Hamamsy et al. application entitled &#34;Lamp Ballast Configuration&#34;, Ser. No. 454,549, both filed concurrently herewith. 
     FIELD OF THE INVENTION 
     The present invention relates generally to high efficiency power amplifiers. More particularly, the present invention relates to a driver for a high efficiency, high frequency Class-D voltage-switching power amplifier. 
     BACKGROUND OF THE INVENTION 
     A Class-D power amplifier employs two active switching devices as a single-pole double-throw switch for generating a square wave signal. An output load network includes a resonant circuit which is tuned to the switching frequency of the devices, thus removing the harmonics of the square wave signal and resulting in a sinusoidal output signal. There are two types of Class-D power amplifiers, a voltage-switching type and a current-switching type. In the voltage-switching type, the switching devices are connected in series with a power supply, and the supply voltage is switched alternately between the respective inputs thereof. The current-switching type, which is the dual of the voltage-switching type, employs the devices in a parallel or push-pull configuration, and the supply current is alternately switched therebetween. For either type, since the switching devices of Class-D power amplifiers are driven alternately between cutoff and saturation such that one is conducting while the other one is turned off and vice versa, Class-D power amplifiers are conveniently driven by square wave signals. An input isolation transformer is conventionally used to provide the two out-of-phase driving signals. 
     Switching power losses at low frequencies are generally negligible for Class-D power amplifiers. However, at higher operating frequencies, switching losses are significant, thus decreasing efficiency. In particular, for a voltage-switching amplifier, the power dissipated by each switching device in discharging the output capacitance of the other switching device increases with increasing operating frequency. Moreover, as frequency increases, isolation transformers which are capable of passing the higher harmonics of the square wave drive signals must be more complex. It is generally accepted that the aforesaid shortcomings impose an upper limit on attainable efficiency for Class-D power amplifiers, e.g. 80% for high frequency, low power applications and less than 70% for high frequency, high power applications. 
     OBJECTS OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a new and improved driver for a voltage switching Class-D power amplifier which reduces device switching losses, thereby increasing efficiency. 
     Another object of the present invention is to provide a driver for a Class-D power amplifier which provides a sinewave input signal and optimizes the transition time between turn-off of one switching device and turn-on of the other device in order to increase efficiency. 
     Still another object of the present invention is to provide a driver for a Class-D power amplifier which increases efficiency at any operating frequency by controlling the switching transition time. 
     SUMMARY OF THE INVENTION 
     The foregoing and other objects of the present invention are achieved in a new driver for a voltage-switching Class-D power amplifier which provides an input sinewave power signal and controls the transition time between switching the two active devices of the half-bridge so as to improve efficiency over conventional drivers, even at high operating frequencies. In particular, the driver of the present invention is useful for driving a voltage-switching Class-D power amplifier which employs two switching devices that have capacitive gates and are connected in a half-bridge configuration. In accordance with the present invention, the transition time is optimized depending on the output capacitance of the switching devices, the threshold voltage of the switching devices, the power output requirement, and the impedance of the load network. Specifically, by controlling the amplitude of the voltage signals at the inputs of the switching devices, i.e. the gate-source voltage signals, depending on the aforesaid variables, the transition time can be optimized for a particular application to reduce switching losses substantially to zero. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention will become apparent from the following detailed description of the invention when read with the accompanying drawings in which: 
     FIG. 1 is a schematic diagram of a conventional voltage-switching Class-D power amplifier; 
     FIG. 2 is a schematic diagram of a Class-D power amplifier and a driver circuit therefor in accordance with a first preferred embodiment of the present invention; 
     FIGS. 3A-3C are graphical illustrations of voltage and current waveforms useful in describing the operation of the Class-D system of FIG. 2; 
     FIG. 4 is a graphical illustration of peak output current versus dc power supply voltage for a type IRF 140 MOSFET employed in a Class-D power amplifier such as that of FIG. 2; 
     FIG. 5 is a graphical illustration of dc power supply voltage versus optimum transition time for a type IRF 140 MOSFET employed in a Class-D power amplifier such as that of FIG. 2; 
     FIG. 6 is a graphical illustration of peak output current versus optimum transition time for a type IRF 140 MOSFET employed in a Class-D power amplifier such as that of FIG. 2; and 
     FIG. 7 is a schematic diagram of a Class-D power amplifier and a driver circuit therefor in accordance with a second preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 illustrates a conventional voltage-switching Class-D power amplifier 10. Two power switching devices Q 1  and Q 2  are connected in series with a dc power supply V DD1  in a half-bridge configuration. Switching devices Q 1  and Q 2  are illustrated as MOSFET&#39;s, but other types of switching devices having capacitive gates may be used, such as insulated gate bipolar transistors (IGBT&#39;s) or MOS-controlled thyristors (MCT&#39;s). Each switching device Q 1  and Q 2  includes an output parasitic capacitance C oss1  and C oss2  (shown in dashed lines), respectively, and an input parasitic capacitance C iss1  and C iss2  (also shown in dashed lines), respectively. A load network comprising a series resonant circuit, including an inductor Lo and a capacitor Co, and a load resistance R L , is connected to the half-bridge at the junction between devices Q 1  and Q 2 . A typical driver circuit 12 generates a square wave input signal and is coupled to the gates of MOSFET&#39;s Q 1  and Q 2  by an isolation transformer 14. The isolation transformer causes devices Q 1  and Q 2  to be driven by square wave voltage signals which are 180° out-of-phase. Ideally, a square wave voltage signal is thus applied to the series resonant circuit. In actuality, due to a finite switching transition time, this voltage signal is generally trapezoidal. For a properly tuned resonant circuit, there is zero reactance at the switching frequency, and the output signal across the load resistance R L  is sinusoidal. 
     During turn-on of a respective switching device Q 1  or Q 2 , energy is stored in the output capacitance C oss2  or C ossl  of the other switching device, respectively. When the switching device Q 1  or Q 2  is turned off, the energy stored in the output capacitance of the other switching device is dissipated. The transition time, or &#34;dead time&#34;, t d  is the time between turning off one device and turning on the other device. At low frequencies, the energy lost during the dead time t d  due to discharging the output capacitance is negligible. However, as frequency increases, this energy loss becomes significant. 
     In accordance with the present invention, a Class-D power amplifier is driven by a sinusoidal driver, and the dead time t d  is optimized to provide zero-voltage switching, thereby improving efficiency, even at high frequencies. As used herein, the term zero-voltage switching is defined as turning on/off at zero voltage across the device and zero current therethrough, i.e., the conditions for lossless switching. 
     A preferred embodiment of a high efficiency driver 16 of the present invention comprises a high efficiency Class-E power amplifier, as illustrated in FIG. 2. As shown, the Class-E power amplifier 16 employs a single driver switching device Q 3  connected in series with a dc power supply V DD2 . Like switching devices Q 1  and Q 2 , switching device Q 3  may comprise a MOSFET. A series resonant circuit, which is coupled to the drain of device Q 3 , comprises an inductance L 1  and a capacitance connected to a load, i.e., the Class-D power amplifier 10. Preferably, the inductance L 1  comprises the leakage inductance of an isolation transformer T 1  which couples driver 16 to the Class-D power amplifier 10 By so using the parasitic inductance, driver size can be decreased, while efficiency is increased. The capacitance of the series resonant circuit comprises the series combination of a blocking capacitance C b1  and the capacitance due to the combination of input parasitic capacitances C iss1  and C iss2  reflected to the primary of transformer T 1 . Blocking capacitance C b1  is provided to prevent saturation of transformer T 1  by blocking application of dc voltage thereto. Since blocking capacitance C b1  is typically large compared with the reflected capacitance due to the combination of capacitances C iss1  and C iss2 , the capacitance of the series resonant circuit is effectively equal to the reflected capacitance of the combination of parasitic capacitances C iss1  and C iss2 . The Class-E driver circuit further comprises an RF choke L RFC  to ensure that the drain current of device Q 3  remains substantially constant. A capacitance C s , which preferably comprises at least a portion of the output parasitic capacitance of device Q 3 , is employed to shunt the switching device Q 3 . The driver switching device Q 3  is driven by an oscillator 18 that generates a sinewave power signal at a high frequency, e.g. 13.56 MHz, a suitable frequency for driving a Class-D ballast for an electrodeless high intensity discharge lamp. With a sufficiently high quality factor Q, the output voltage from the Class-E driver circuit is sinusoidal. 
     FIG. 3A illustrates the 180° out-of-phase sinusoidal gate-source voltage waveforms v Gs1  and v Gs2 , each having an amplitude V p , which result from driving the Class-D amplifier with the illustrated Class-E driver circuit via transformer T 1 , as shown in FIG. 2. The switching devices Q 1  and Q 2  are not ideal and thus have a threshold voltage V T  which must be reached before these devices can turn on. The transition time t d  occurring between turn-off of device Q 1  and turn-on of device Q 2  is illustrated in FIG. 3A. In accordance with the present invention, this transition time is optimized to obtain zero-voltage switching, as will be described hereinafter. 
     FIG. 3B graphically illustrates the drain voltage waveform v(t) for device Q 2  of the Class-D amplifier of FIG. 2, i.e., the voltage at the junction between the two switching devices Ql and Q2. This voltage waveform is generally trapezoidal. The transition time t d  is the time required for the trapezoidal voltage to transition from its maximum value to its minimum value and vice versa, as shown. FIG. 3B also shows the corresponding fundamental component waveform v f  (t) of the voltage waveform v(t). The amplitude V f  of the fundamental component waveform v f  (t) may be expressed ##EQU1## where the load impedance angle φ, in radians, may be expressed in terms of the transition time t d  as follows: ##EQU2## where T represents the period of the gate-source voltage waveform of the respective switching device. 
     FIG. 3C graphically illustrates the output load current waveform i(t) along with the voltage waveform v(t) under conditions for which zero-voltage switching of the Class-D amplifier of FIG. 2 is attained. In particular, in accordance with the present invention, the transition time t d  is optimized so that switching occurs when the voltage waveform v(t) and the current waveform i(t) intersect at zero. In this way, the output capacitance of each respective switching device is completely discharged at the switching instant, thereby resulting in lossless switching. The following equation describes the discharge of the output capacitance C oss  of a switching device of a voltage-switching Class-D power amplifier in terms of transition time t d , operating frequency ω load impedance angle φ, and peak output current I 1  : ##EQU3## 
     In accordance with the present invention, the transition time t d  is optimized by controlling the amplitude V p  of the sinusoidal gate-source voltage signals v GS1  and v GS2  depending on: the output capacitances C oss1  and C oss2  ; the threshold voltage V T  of the switching devices; the power output requirement; and the impedance of the resonant load network. In particular, the output power P o  may be expressed as follows: ##EQU4## Furthermore, by integrating equation (3) and rearranging terms, the dc power supply voltage Vool may be expressed as follows: ##EQU5## 
     Equations (1), (4), and (5) may be solved to yield an expression for the peak output current I 1  of the Class-D power amplifier as follows: ##EQU6## 
     FIG. 4 is a graph of peak output current I 1  versus dc power supply voltage V DD1  for a type IRF 140 MOSFET manufactured by International ReCtifier Corporation which may used to implement switching devices Q 1  and Q 2  of the Class-D power amplifier 10 of FIG. 2. Using the graph of FIG. 4, an operating point comprising values for supply voltage V DD1  and peak output current I 1  may be selected. In particular, safe operating points for a type IRF 140 MOSFET are found within the bounded region 19. FIGS. 5 and 6, respectively, are graphs of the peak output current I 1  and the dc supply voltage V DD1  versus the optimum transition time t d  for type IRF 140 MOSFET&#39;s. The graphs of FIGS. 4-6 were generated using equations (1)-(6). By interpolating between the two transition time curves, i.e., FIGS. 5 and 6, the optimum transition time t d  may be approximated for a selected operating point, i.e., specific values of peak output current I 1  and dc supply voltage V DD1 . Knowing the value of the optimum transition time t d , the amplitude V p  of the gate-source voltage signals v GS1  and v GS2  needed to provide this optimum transition time t d  can be determined acCording to the following equation: ##EQU7## 
     Finally, design of oscillator 18 for generating an input signal to produce gate-source voltage signals v GS1  and v GS2  having amplitude Vp at the required operating frequency is a matter well-known in the art. 
     A second preferred embodiment of a driver circuit for a high frequency Class-D power amplifier comprises another Class-D amplifier stage 20, as illustrated in FIG. 7, for which the amplitude of the sinusoidal gate-source voltage signals is controlled such that the transition time t d  is optimized in accordance with the principles of the present invention. Such a Class-D driver circuit comprises two switching devices Q 4  and Q 5  connected in series with a dc power supply VDD3 in a half-bridge configuration. A series resonant circuit is connected to the half-bridge at the junction between switching devices Q 4  and Q 5 . The series resonant circuit comprises an inductance L 1  and the series combination of a blocking capacitance C b2  and the reflected capacitance due to the input parasitic capacitances C iaal  and C iss2  of switching devices Q 1  and Q 2 . Since blocking capacitance C b2  is typically large, compared with the reflected capacitance due to the combination of capacitances C iss1  and C iss2 , the capacitance of the series resonant circuit is effectively equal to the reflected capacitance of the combination of parasitic capacitances C iss1  and C iss2 . The inductance L 1  preferably comprises the leakage inductance of the isolation transformer T 1 . The Class-D driver circuit is driven via a transformer 22 by an oscillator 24. 
     While the preferred embodiments of the present invention have been shown and described herein, it will be obvious that such embodiments are provided by way of example only. Numerous variations, changes and substitutions will occur to those of skill in the art without departing from the invention herein. Accordingly, it is intended that the invention be limited only by the spirit and scope of the appended claims.