TTL to ECL voltage level translator
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a voltage level translator, which especially enhanced the speed of level translating by constituting the circuit not to make the transistor saturated in translating the TTL(Transistor-Transistor Logic) level ECL (Emitter-Coupled Logic) level. 
     2. Description of the Prior Art 
     In the Integrated Circuit of high-speed performance over LSI( Large Scale Integrated Circuit),the ECL circuit, of which the speed is high, is frequently used. 
     But the general outer circuit of the system is composed of TTL in many cases. 
     Like this, When the outer logic of the system is composed of TTL and the inner logic of the Integrated Circuit is composed of ECL, a translator which translates the TTL level to the ECL level (hereinafter referred to as TTL to ECL level translator) is indispensible and has been introduced many times up to now, but the time in translating the level has always been the problem. 
     Generally, the traditional TTL to ECL level translator uses the TTL input circuit as shown in FIG. 2 or DTL(Diode-Transistor-Logic) input circuit as shown in FIG. 3. 
     But the DTL input circuit is generally slower than TTL, and in the TTL input circuit as shown in FIG. 2, there has been the problem that the speed of data processing is lowered because of the phenomenon of the transistor Q 1  being saturated. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to provide the TTL to ECL translator with high speed which can improve the abovementioned problem. 
     To accomplish the said object, The translating speed of level translator is made to become higher by designing the input circuit part of the TTL to ECL level translator to be composed of emitter coupled pair 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present, and wherein: 
     FIG. 1 is a circuit diagram of the present invention; and 
     FIG. 2 and 3 are the traditional circuit diagram. 
    
    
     THE DETAILED DESCRIPTION OF THE INVENTION 
     The input circuit part of the TTL to ECL level translator of the present invention is composed of transistors Q 1 , Q 2  and resistances R 1 , R 2  as the emitter coupled pair. 
     The base of the transistor Q 1 , to which the input signal of the TTL data is applied, is grounded through the resistance R 3 , and emitter of the transistor Q 3  is connected to the base of the transistor Q 1  through the resistance R 4 . 
     The resistances R 5 , R 6  and the transistor Q 4  are activating for the bias of the transistors Q 2 , Q 3 . 
     And for the bias of the transistor Q 4 , the biasing voltage from the divided voltage by the resistances R 7  and R 8  is applied to the base of the transistor Q 4 . 
     Each collector signal of the transistors Q 1  and Q 2  is transferred to the bases of transistors Q 9  and Q 10  which are composed of emitter coupled pair and are operated in the output circuit of the voltage level shifter, by way of voltage-level-transfer circuit which is composed of the transistors Q 5  -Q 8 , the resistances R 9  and R 10  and the current sources I 2  and I 3 , and so the signals of the ECL level are supplied at the collectors of the transistors Q 9  and Q 10  respectively. 
     In operation, the input data of the TTL level is inputed to the base of the transistor Q 1 , and the middle level of the high and low level of the TTL level is applied to the base of the transistor Q 2 . 
     When the TTL level inputed from the outer driving TTL circuit is high, the current flows from the Pull-up element of the outer TTL circuit through the resistance R 3 , and when the TTL level inputed is low, the current flows into the active pull-down transistor of outer TTL circuit through the transistor Q 3  and resistance R 4 . 
     And the TTL level inputed to the transistor Q 1  is compared with the middle level applied to the base of the transistor Q 2 , and then changed to the level of inner voltage which is divided by the current source I 1  and each resistance R 1  and R 2 . 
     And so it is applied to the bases of transistors Q 9  and Q 10  by way of voltage-level-shifter circuit composed of the transistors Q 5  -Q 8 , the resistances R 9  and R 10  and the current source I 2  and I 3 . 
     And then the signal of the ECL level, which is determined by the resistances R 11  and R 12  and the current source I 4 , is outputted to each collector of the transistor Q 9  and Q 10 , and inputed to the ECL circuit of the LSI. 
     As mentioned above, according to the circuit of the present invention the translation speed is enhanced because any transistor in the circuit is not saturated by designing the input circuit part, which receives the data of the TTL level, to be emitter coupled pair. 
     And also there is the advantage that it can increase the speed of the outer driving TTL circuit by making the path which makes the current flow from the pull-up element of the TTL circuit which is driving through the resistance R 3  when the data of the level inputed is high level, and which makes the current flow through the transistor Q 3  and the resistance R 4  to the pull-down transistor of the outer TTL circuit which is driving, when low level.