Isolated semiconductor macro circuit
BACKGROUND OF THE INVENTION 
     The invention relates generally to semiconductor devices, and deals more particularly with a semiconductor macro circuit which is electrically isolated from other adjacent semiconductor macro circuits integral therewith and other sources of external electrical noise. 
     There are many semiconductor technologies presently known. One common technology provides semiconductor devices produced in an epitaxially grown layer on a substrate of opposite conductivity or polarity. Another common technology provides semiconductor devices produced in a diffused layer. 
     External noise and internal feedback problems have arisen, particularly when the semiconductor devices form sensitive, high gain amplifiers. In such a case, a small amount of external noise or internal feedback can obscure the input signal or even drive the amplifier into oscillations. One route of the noise is laterally through the semiconductor epitaxially layer or diffused layer which contains the semiconductor devices or laterally through the lower substrate layer, to the input of a transistor or other sensitive device. 
     Heretofore, it was known to provide a single, low impedance isolation ring around a sensitive transistor i.e., a high gain (high beta) transistor used as an amplifier stage. For example, if the transistor is formed in an epitaxial layer, an isolation ring of opposite polarity to the epitaxial layer is diffused from the surface of the epitaxial layer to the substrate, and either floated or tied to a voltage. The voltage is ground voltage if the isolation ring is P type and positive power supply voltage if the isolation ring is N type. For a P type isolation ring, noise in the form of hole carriers traveling laterally through the epitaxial layer is shunted through the isolation ring to ground. For an N-type isolation ring, noise in the form of electron carriers travelling through the epitaxial layer is shunted through the isolation ring to the power supply voltage. Thus, the single isolation ring has proven effective in isolating the transistor from moderate levels of noise. If many sensitive transistors are provided in the same epitaxial or diffused layer, then each can be protected by its own single isolation ring. 
     Nevertheless, some noise hole carriers or electron carriers travel underneath the isolation ring through the substrate, and then interfere with the adjacent semiconductor devices. The noise problem does not dissipate until the noise hole carriers and electron carriers recombine, and this can slow the operation of the main device. Therefore, in high gain amplifiers, additional prior art precautions have been taken. The semiconductor chip containing an input stage/pre-amplifier can be physically separated by a spacing from the semiconductor chip containing the output/driver stage so that noise from the output/driver stage cannot feed back through the semiconductor layers to the input stage. While such a technique is effective in reducing the feedback, this technique is undesirable because it requires fabrication and interconnection of two separate chips. 
     Accordingly, a general object of the present invention is to provide a highly effective technique for isolating a stage of amplification or other macro device from external noise or internal feedback. 
     Another general object of the present invention is to provide a technique of the foregoing type which can be used to isolate different stages of a single amplifier yet permit the entire amplifier to be made from a single semiconductor chip. 
     A more specific object of the present invention is to provide an isolation technique which need not wait for recombination of hole and electron carriers. 
     SUMMARY OF THE INVENTION 
     The invention resides in a semiconductor device comprising a macro semiconductor circuit formed in a first semiconductor layer. The semiconductor layer can be an epitaxially layer grown on a substrate or a diffused layer. A first semiconductor isolation region is formed in the semiconductor layer around the macro device, and a contact is provided for connecting the first isolation region to a voltage source or ground. A second semiconductor isolation region is also formed in the semiconductor layer around the first isolation region, and has a contact for connecting the second isolation region to a voltage source or ground. The two isolation regions have opposite conductivity type. A second semiconductor layer adjoins the first semiconductor layer and has an opposite conductivity type as the first semiconductor layer. The isolation region which has the same conductivity type as the second semiconductor layer extends entirely through the first semiconductor layer to the second semiconductor layer, and the other isolation region preferably extends only partially through the first isolation region. The P-type isolation region shunts noise holes to ground and the N-type isolation region shunts noise electrons to a positive voltage source. 
     Within each macro device, another isolation ring having the opposite conductivity type as the first semiconductor layer can be provided around sensitive transistors or other electronic components to increase the isolation. 
    
    
     BRIEF DESCRIPTION OF THE FIGURES 
     FIG. 1 is a schematic top view of the stages and a few of the many semiconductor components of a multi-stage amplifier, and the isolation regions of the present invention surrounding each stage. 
     FIG. 2 is an enlarged fragmentary, cross-sectional view of FIG. 1 taken along the plane 2--2 of FIG. 1. 
     FIG. 3 is an enlarged, fragmentary cross-sectional view, taken along the plane 3--3 of FIG. 1 and illustrates the manner of making an electrical connection between stages, over the isolation rings of FIG. 1. 
     FIG. 4 is an enlarged fragmentary, cross-sectional view of a semiconductor circuit in accordance with another embodiment of the present invention, taken along the line 4--4 of FIG. 5. 
     FIG. 5 is a three dimensional view of the embodiment of FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to the drawings in detail wherein like reference numerals indicate like elements throughout the several views, FIG. 1 illustrates portions of a multi-stage amplifier generally designated 10 which amplifier includes the present invention. Amplifier 10 is comprised of a pre-amplifier or input stage 12, a buffer stage 14, a first gain stage 16, a second gain stage 18, a third gain stage 20, a fourth gain stage 22, an output/driver stage 24, and a feedback stage 26. All of these stages 12-26 are formed in one integral semiconductor chip. Each of these stages comprises a multiplicity of semiconductor devices such as transistors, diodes, resistors, capacitors, etc. However, only some of the semiconductor devices within stages 12 and 14 are shown because the invention does not depend on the particular semiconductor devices which make up each of these stages. 
     The invention relates to macro isolation rings or regions 49, 50 which, in the illustrated embodiment, substantially surround each of the stages of amplifier 10. The regions 49, 50 prevent feedback between stages, particularly internal noise created by driver stage 24 from feeding back through the semiconductor layers to pre-amplifier 12 or any other stage. Also, the isolation regions 49, 50 prevent external noise from travelling through the semiconductor layers to pre-amplifier 12 or any other stage of the amplifier 10. It should be noted that isolation regions 49, 50 according to the present invention can also be used to isolate other types of macro devices. 
     FIG. 2 illustrates in cross-section a portion of pre-amplifier 12 which contains a transistor 36, a local isolation ring 38 surrounding transistor 36, transistor 37, local isolation ring around 39 around transistor 37, and isolation region 49, 50 around pre-amplifier 12 according to the present invention. The transistors 36 and 37 are formed in an N type epitaxial layer 44 which was grown on a P type substrate 46. However, it should be understood that the present invention is also useful in diffused layer technology. Transistor 36 is a standard NPN transistor having a diffused N+ region 41 forming the emitter of the transistor, a diffused P+ region 40 forming the base of the transistor, and N- region 42 which forms the collector of the transistor and is part of the N type epitaxial layer 44. Transistor 36 also includes an N+ type subcollector 48. Suitable contacts 63, 65 and 67 are provided on the surface of layer 44 for regions 41, 40 and 48, respectively. Isolation ring 38 has a P+ conductivity, extends from the surface of epitaxial layer 44 through the entire thickness of epitaxial layer 44 to substrate 46 and surrounds transistor 36. Isolation ring 38 is connected to ground via a contact 60 to shunt noise holes to ground and away from transistor 36. Transistor 37 and local isolation ring 39 are identically constructed as transistor 36 and local isolation ring 38. 
     Each region 49, has the same polarity or conductivity type as substrate 46 and in the illustrated embodiment is P+ type. Region 49 is diffused from the surface of epitaxial region 44 through the entire thickness of epitaxial layer 44 to substrate 46. Region 50 has the opposite polarity as substrate 46 and in the illustrated embodiment is N+ type. Region 50 is diffused from the surface of epitaxial layer 44 into epitaxial layer 44. In the illustrated embodiment, N+ region 50 extends only part way through epitaxial layer 44 to minimize the width of region 50, but if desired could extend entirely through layer 44. P+ region 49 is grounded via metallic contact strip 51 to collect and shunt noise holes (from leakage hole currents and injection hole currents) to ground. This is effective for D.C. and transient hole injection. N+ region 50 is connected via metal contact strip 53 to a positive power supply voltage to collect and shunt noise electrons to the power supply voltage. Because P+ region 49 and N+ region 50 are adjacent to each other, the noise carriers are removed without waiting for them to recombine. This allows operation of the macro device at high speed. 
     The following Table I lists preferred ranges of and one specific example of the concentrations and dimensions of the foregoing elements illustrated in FIG. 1: 
     
                                           TABLE I                                 
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           PREFERRED                                                      
           CONCENTRATION                                                  
           OR CONDUCTIVITY                                                
                       DIMENSIONS                                         
                                 DIMENSIONS                               
ELEMENT    RANGE       RANGE     EXAMPLE                                  
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N EPITAXIAL                                                               
           10.sup.15 -10.sup.16                                           
                       1.5-10.0 MICRONS                                   
                                 2.0 MICRONS                              
LAYER 44   ATOMS/cm.sup.3                                                 
                       (THICKNESS)                                        
                                 (THICKNESS)                              
P SUBSTRATE                                                               
           10-20       N.A.      N.A.                                     
LAYER 46   OHM/cm                                                         
P+         10.sup.17 -10.sup.18                                           
                       3-30 MICRONS                                       
                                 5.0 MICRONS                              
REGION 38  ATOMS/cm.sup.3                                                 
                       (WIDTH)   (WIDTH)                                  
P+         10.sup.17 -10.sup.18                                           
                       4-28 MICRONS                                       
                                 6 MICRONS                                
REGION 49  ATOMS/cm.sup.3                                                 
                       (WIDTH)   (WIDTH)                                  
N+         10.sup.17 -10.sup.18                                           
                       4-28 MICRONS                                       
                                 6 MICRONS                                
REGION 50  ATOMS/cm.sup.3                                                 
                       (WIDTH)   (WIDTH)                                  
SEPARATION             2-14 MICRONS                                       
                                 3 MICRONS                                
N+ REGION 50                                                              
TO P+ REGION 49                                                           
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     The example given in Table 1 for the width dimensions is applicable for a 2.0 micron bipolar technology. For a smaller dimension technologies, rings 49, 50 can be located closer to isolation ring 38 to conserve &#34;real estate&#34;. 
     As listed in table 1, the lateral resistivity of substrate 46 is substantial, 10-20 ohm centimeters. The resistance vertically through P+ region 49 is very low in view of the small thickness of epitaxial layer 44 and the high concentration of P+ region 49, and the vertical resistance through N+ region 50 is very low in view of the small thickness of epitaxial layer 44 and the high concentration of N+ region 50. Consequently, noise electrons which travel laterally through P substrate 46 toward N+ region 50 underneath P+ region 49 or from the other direction are shunted to the power supply via N+ region 50, and noise holes which travel underneath N+ region 50 or P+ region 38 in P substrate 56 are shunted to ground via P+ region 49. Regions 49 and 50 also shunt holes and electrons, respectively which travel through epitaxial layer 44 adjacent to these two regions. 
     There are two ways according to the present invention to electrically interconnect two stages or macro devices which are substantially surrounded by regions 49, 50, or electrically connect such a stage to an external device. As illustrated in FIG. 1, small gaps 70, 71, 73 can be provided in regions 49, 50 and a metallic lead 68 integrated in the semiconductor layers can be passed through one or more of the gaps. Alternately, as illustrated in FIGS. 1 and 3, an insulating oxide layer 72 (for example one micron thick) can be grown or otherwise provided on top of stages 12 and 14 and over contacts 51, 53, 60, 63, 65, 67 and all other intrastage metal conductors which are schematically illustrated collectively as 92 and 94 respectively. To interconnect macro 12 with macro 14, holes are etched in insulating layer 72 in registration with the appropriate metal contacts, and metal 96 and 98 is deposited in the holes. Next, a metal lead 86 is deposited on top of insulating layer 72 to connect metal deposit 96 to metal deposit 98 and thereby form a bridge over rings 49, 50. Preferably another oxide layer 90 is grown over oxide layer 72 and metal lead 86 to insulate lead 86. 
     FIGS. 4 and 5 illustrate another embodiment of the present invention. A macro device 112 including a transistor 116 is isolated by rings or regions 149 and 150 from a macro device 114 including a transistor 136. Regions 149 and 150 substantially surround macro device 116. The macro devices and regions 149 and 150 are integrated into one semiconductor chip. 
     The chip comprises a P- substrate 146 and is formed as follows. A N+ blanket subcollector 161 is grown on the substrate. Next, the bottom portion of P+ region 149 is formed by diffusion into the N+ layer 161, until reaching the substrate. Then, a N- layer 163 is grown over the N+ layer 161 and P+ region 149. Next, the remainder of P+ region 149 is formed by diffusion into the N- layer in registration with the previous P+ diffusion so that region 149 extends from the surface of the upper epitaxial layer to the substrate. Then, an N+ region 150 is diffused into the N- layer 163 so that N+ region 150 extends from the surface of the upper epitaxial layer to the substrate. Next, insulator regions 165 are formed between and around regions 149 and 150, by etching trenches between and around regions 149 and 150 and filling the trenches with an insulator such as glass or polymide. Insulated rings or regions 165 help prevent noise from traveling laterally through the epitaxial layers by providing a barrier and increasing the shunting effectiveness of regions 149 and 150. Insulated rings or regions 167 are also formed around transistors 136 and 137, by etching trenches and then filling the trenches with an insulator such glass or polymide. A conductive strip 171 on the surface of region 150 is used to connect region 150 to a positive power supply, and a conductive strip 173 on the surface of region 149 is used to connect region 149 to ground. Other contacts such as 140, 141, 148 and conductive strips (not shown) in the same layer are used to interconnect electronic components within the same micro device. 
     Connections between different macro devices, and inputs and outputs of a micro device are provided in the following manner. An insulating layer of glass 175 (shown in FIG. 4 only) is formed over the epitaxial layer 163 and exposed contacts and conductor strips. Next, windows are etched in glass layer 175 in registration with contacts in other conductive strips to permit electrical connection, and the windowed holes are then filled with metal. FIGS. 4 and 5 illustrate two such metal fillings 180 and 182. Next, metal conductor strips such as 184 are deposited over the glass layer 175 and the metal fillings to make the desired connections. As illustrated in FIGS. 4 and 5 also, the metal strip 184 bridges over isolation regions 149 and 150 to interconnect transistors 116 and 136 within macro devices 112 and 114, respectively. Next, the metal strip 184 is covered with another layer of insulation 188. 
     The following TABLE II lists preferred ranges of and are specific example of the concentrations and dimensions of the foregoing elements illustrated in FIGS. 4 and 5: 
     
                                           TABLE II                                
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           PREFERRED                                                      
           CONCENTRATION                                                  
           OR CONDUCTIVITY                                                
                       DIMENSIONS                                         
                                DIMENSIONS                                
ELEMENT    RANGE       RANGE    EXAMPLE                                   
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N- EPITAXIAL                                                              
           10.sup.15 -10.sup.16                                           
                       1.5-10 MICRONS                                     
                                2.0 MICRONS                               
LAYER 163  ATOMS/cm.sup.3                                                 
                       (THICKNESS)                                        
                                (THICKNESS)                               
N+ BLANKET 10.sup.18 -10.sup.19                                           
                       .5-5 MICRONS                                       
                                1.0 MICRONS                               
SUBCOLLECTOR                                                              
           ATOM/cm.sup.3                                                  
                       (THICKNESS)                                        
                                (THICKNESS)                               
LAYER 161                                                                 
P SUBSTRATE                                                               
           10-20       N.A.     N.A.                                      
LAYER 146  OHM/cm                                                         
P+         10.sup.16 -10.sup.17                                           
                       4-28 MICRONS                                       
                                5 MICRONS                                 
REGION 149 ATOMS/cm.sup.3                                                 
                       (WIDTH)  (WIDTH)                                   
N+         10.sup.16 -10.sup.17                                           
                       4-28 MICRONS                                       
                                6 MICRONS                                 
REGION 150 ATOMS/cm.sup.3                                                 
                       (WIDTH)  (WIDTH)                                   
SEPARATION             1-5 MICRONS                                        
                                3 MICRONS                                 
N+ REGION 150                                                             
TO P+ REGION 149                                                          
INSULATION             1-5 MICRONS                                        
                                2.5 MICRONS                               
REGION 165             (WIDTH)  (WIDTH)                                   
INSULATION             1-5 MICRONS                                        
                                2.5 MICRONS                               
REGION 167             (WIDTH)  (WIDTH)                                   
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     Based on the foregoing, isolated semiconductor circuits embodying the present invention have been disclosed. However, numerous modification and substitutions can be made without deviating from the scope of the invention. For example, if desired, regions 49 and 50 or 149 and 150 can be formed around a single semiconductor transistor or other device instead of around a macro device as illustrated in FIG. 1. Therefore, the invention has been disclosed by way of illustration and not limitation, and reference should be made to the following claims to determine the scope of the invention.