Electronic tuner for a musical instrument
FIELD OF THE INVENTION 
     The present invention relates generally to an electronic tuner for a musical instrument and more specifically to such an apparatus particularly adapted for use with electric stringed instruments. 
     BACKGROUND OF THE INVENTION 
     Tuning of a musical instrument traditionally involves a first player listening to a reference note, which may be the note sounded by one or more other players of an ensemble, and adjusting the first player&#39;s instrument until the corresponding note is consonant with the reference note. Detection of correct intonation involves a subconscious comparison of the two notes until the combination of the two notes are in tune with each other. 
     The determination of correct intonation is a skill which is acquired as part of the player&#39;s basic musicianship training and which is acquired only after long hours of practice. As with many acquired skills, the accuracy of the intonation which results is a combination of the inherent talent of the performer and the diligence with which the task is pursued. 
     There have been numerous prior art attempts to provide electromechanical, mechanical or electronic apparatus for use as tuning aids which can detect the presence or absence of the desired intonation characteristics. Musicians are greatly assisted by the use of such tuning aids. For example, professional players can benefit from comparison of their intonation with the theoretically perfect standard. 
     For example, one class of prior art tuning aids are frequency meters which employ period measuring circuits to detect a zero crossing of the output of a suitable transducer. The inverse of the period may then be computed and the frequency of the tone thus determined and displays. Such instruments can give quite accurate results, but suffer from a disadvantage and limitation that the displayed value has little meaning to a musician who thinks not in terms of physical units but rather in terms of subjective cycle acoustic phenomenon such as pitch. A further disadvantage and limitation of such devices is that the detected waveform contains not only the fundamental frequency but also harmonic frequencies of the fundamental frequency. Therefore, the period measuring circuit may develop an error when encountering zero crossings of the transducer output which are caused by the summation of the harmonic frequencies in the fundamental frequency. 
     For example, Moravec, et al., U.S. Pat. No. 4,354,418, disclose an automatic note analyzer which computes the fundamental frequency from the time period of the output signal from a transducer. A data count is obtained by counting the number of CPU clock pulses counted within a measurement period extending over P consecutive cycles of the input signal, or data count equals P times C 1 , where C 1  equals the period of the input signal. The measurement period should extend for at least two cycles of the input signal. A number of sequential data counts similar to the first data count are then taken. These data counts are then analyzed to determine whether a consistent pattern can be found. In particular, N separate data counts which are equal to one another, within a tolerance of about 3%, are attempted to be found. Once N consistent data counts are found, then a variable K is set equal to the sum of these N data counts. Thus, K is a variable which corresponds to the sum of a selected number of N consistent data counts. Since the time period C 1  is not actually a constant value, the variable K is a function of three variables: (1) the time delay between adjacent zero crossings, (2) the duration of the measurement period of a single data count in terms of the number of zero crossings which occur between the starting and stopping of the counter, and (3) the number of data counts which are summed to determine K. 
     Once an initial value for the variable K has been determined, K is then normalized to place it within a desired range. The normalization is accomplished by multiplying or dividing as necessary by factors of 2 until it falls within the desired range. For example, if the value of K is lower than the minimum accepted value, K is doubled. If K is still below the minimum acceptable value then it is doubled again. Conversely, if K is greater than the maximum allowed value then the value of K is divided by 2 and so forth. In this way, the variable K is normalized to fall within the desired range. Of course this desired range is the expected value. 
     The normalized value of K is then averaged with previous calculated values of K to smooth out fluctuations. For example, the current value of K may be summed with 15 immediately preceding values of K and the summed divided by 16 to recursively generate an average. The variable T is then equal to the recursively averaged K divided by N. T is a measure of the expected data count for measurement periods lasting over P cycles of the input signal. The variable T is used as a target signal to define a window which is used to screen incoming data to ascertain whether that incoming data is consistent with previously measured values of the data count and thereby to screen out erroneous measurements. 
     In addition, the recursive average of K is used to determine the musical note corresponding to the input signal. In particular, the recursively averaged K is compared with the look-up table which lists values for the recursively averaged K at the halfway points between adjacent semi-tone. In this way, the semitone closest to the recursively averaged K is determined. In addition, the difference between recursively averaged K and the table entry for the nearest semitone is determined as the fractional deviation of the recursively averaged K from the nearest semitone in cents. 
     A disadvantage and limitation of the apparatus disclosed in Moravec, et al., is that the computations to compute K or frequency appear to be sensitive to large amplitude harmonics of the fundamental frequency. In calculating K, it is assumed that interrupts will occur at the fundamental frequency of the output signal from the transducer. However, relatively large amplitude harmonics which occur will cause substantial measurement errors in this fundamental frequency. Since this error will not always be in a factor of two, the calculated fundamental frequency may be in gross error. 
     Other types of electronic apparatus use a comparison of a known frequency standard, such as the output frequency of a crystal controlled oscillator, with the frequency of the unknown signal being measured. Both signals are electronically conditioned to provide a substantially pure sine waveform before they are applied to the vertical and horizontal deflection plates of a cathode ray tube oscilloscope. When the notes are identical in frequency, a circular &#34;Lissajous&#34; pattern is formed on the screen. When sharp or flat the Lissajous pattern will appear to rotate at a rate which is determined by the magnitude of the departure of the frequency of the unknown signal from the frequency of the reference signal. 
     A similar oscilloscope based device employs an oscilloscope having a known horizontal sweep rate. The horizontal sweep rate is then compared with an unknown signal input. When the signal is properly synchronized, a stationary waveform will appear on the oscilloscope screen. When the note represented by the unknown signal is slightly too sharp, the pattern appears to move to the left. Conversely, when the note is slightly too flat, the pattern appears to move to the right. 
     The indications available from these oscilloscope based instruments are ambiguous to the user in that the degree of the inaccuracy of the incoming pitch cannot be readily be determined. In the case of the first type of oscilloscope display described, it is difficult to determine both polarity (sharp or flat) and the degree of departure from the theoretical perfect intonation. Since the user is unable to determine the needed information by merely viewing the oscilloscope screen, he can never be absolutely sure of his intonation. Moreover, as a training aid, these devices are disadvantageously limited in that they do not readily indicate in which direction the pitch of the unknown signal must be varied in order to bring it close to the theoretically correct pitch. 
     To make the displays more readable, LED diodes in a linear array may be used. For example, in Roses. U.S. Pat. No. 4,434,697, there is disclosed a tuning device wherein an acoustic signal is used to develop an electrical input signal. The input signal is applied to a plurality of low pass filters. The signal from the lowest cut-off frequency low pass filter which passes the signal is utilized. After filtering, a high frequency clock count is obtained to determine the time period of the signal chosen. An entry and a look-up table in computer memory is selected as being the closest to determine time period. An LED display is used to determine visually if the time period of chosen signal is above or below the selected entry in the look-up table. 
     SUMMARY OF THE INVENTION 
     According to the present invention, an electronic tuner generates a pulse train signal from an analog signal transduced from vibrations on a selected one of several strings of a musical instrument. The pulse train signal has a plurality of successive pulses, each of the pulses having a pulse width which may vary between successive pulses. Two of the pulses have a longest pulse width of all pulses in the pulse string are identified. The tuner then computes a current fundamental frequency on the selected string as a function of a ratio between a numerical count of the pulses occurring between these two pulses, the count including one of these pulses, and a sum of the pulse width of each of the pulses included in the count. The two of the pulses have a longest pulse width of all pulses in the pulse string. A difference signal is developed as a function of a difference between the current fundamental frequency and a known in-tune frequency associated with the selected string being tuned. The difference signal may then be used to visually display the difference whereby the selected one of the strings can be tuned to minimize the difference. 
     These an other objects, advantages and features of the present invention will become more apparent to those skilled in the art from a study of the following description of an exemplary preferred embodiment when read in conjunction with the attached drawings and appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram of an electronic tuner constructed according to the principles of the present invention; 
     FIG. 2 is a schematic block diagram of the CPU shown in FIG. 1; 
     FIG. 3 is a circuit diagram of the pulse generator of FIG. 1; 
     FIG. 4 is a circuit diagram of the select and display function of FIG. 1; 
     FIG. 5 is a circuit diagram of the mute function of FIG. 1; 
     FIG. 6 is a more detailed circuit diagram of the power supply shown in FIG. 1; 
     FIG. 7 illustrates one use of the electronic tuner of the present invention; 
     FIG. 8 is an enlarged detail of a portion of FIG. 7; 
     FIG. 9 is a cross-sectional view, broken away, taken along line 9--9 of FIG. 8; and 
     FIGS. 10-15 are flow charts illustrating the sequence of operations executed by the CPU of FIG. 1. 
    
    
     DESCRIPTION OF AN EXEMPLARY PREFERRED EMBODIMENT 
     Referring now to FIG. 1, there is shown an electronic tuner 10 constructed according to the principles of the present invention. The electronic tuner 10 is particularly useful in conjunction with a musical instrument 12 (as best seen in FIG. 7) having plurality of strings 14. Each of the strings 14 is vibratable at a different fundamental frequency and at an integer multiple harmonic frequencies of the fundamental frequency. The instrument 12 includes means 16 for transducing vibrations on each of the strings 12 into an electrical analog signal. As is known, the instrument 12 also includes means 18 for tensioning each of the strings to tune the fundamental frequency to an in tune frequency associated with each of the strings 14. The electrical analog signal developed by the transducer 16 is generally represented in the Drawing by the audio input signal applied to the electronic tuner 10, as best seen in FIG. 1. 
     The electronic tuner 10 includes means 20 for generating a pulse train signal from the analog signal developed by the transducer 16, means 22 for computing the current fundamental frequency on one of the strings 14 and further for determining the difference between the current fundamental frequency and the in-tune frequency associated with the selected string 14, and means 24 for visually displaying the difference whereby the selected one of the strings 14 can be tuned to minimize the difference. 
     The pulse train signal developed by generating means 20 has a plurality of successive pulses. Each of the pulses has a pulse width which may vary between successive pulses. The pulse train signal is developed from an analog signal which is transduced from vibrations on a selected one of the strings 14. 
     Computing means 22, hereinafter also referred to as CPU 22, computes the current fundamental frequency on the selected one of the strings 14 as a function of a ratio between a numerical count of the pulses occurring between at least two of the pulses and including one of those two pulses and a sum of the pulse width of each of the pulses included in the count. The pulses are selected to have the longest pulse width of the pulses in the pulse string. Computing means 22 further develops a difference signal as a function of the difference between the current fundamental frequency and the in tune frequency associated with the selected one of the strings. The display means 24 is responsive to this difference signal to generate its display. 
     With further reference to FIG. 2, the CPU 22 includes a microprocessor 26. The microprocessor 26 has a plurality of I/O ports represented by a P0, P1, P2, and P3. At least two of the ports, P1 and P3, have a plurality of parallel pins, P1.0-P1.7 and P3.0-P3.7. The pulse train is applied to one of the pins, and in particular P3.2. The difference signal is developed at other ones of the pins, and in particular, as herein described below, at all pins in port 1, P1, and further at pins P3.0 and P3.1 at port P3. 
     The instruction set, attached hereto as Appendix A, is stored in a ROM 28 which forms part of the CPU 22. The ROM 28 is connected to the microprocessor 26 in a known manner. Microprocessor 26 may be a 8051 processor wherein one I/O port, P0, transmits both data and addresses. Accordingly, an address latch 30 is also provided. 
     Referring further to FIG. 3, pulse generator means 20 is a waveshaping circuit 31 which develops each of the pulses to have a leading edge corresponding to a positive slope zero crossing of the analog signal and a trailing edge corresponding to a negative slope zero crossing of the analog signal. The pulse width of each one of the pulses extends between the leading edge of one pulse and the leading edge of the next successive one of the pulses. The waveshaping circuit 31 includes a unity gain noninverting first amplifier circuit 32 an inverting second amplifier circuit 34 and an inverting high voltage gain third amplifier circuit 36. The first amplifier circuit 32 has an input to which the audio input analog signal is applied and an output. The second amplifier circuit has an input electrically coupled to the output of the first amplifier circuit 32 and an output. The third amplifier circuit 36 has an input electrically coupled to the output of the second amplifier circuit 34 and an output at which the pulse out pulse train signal is developed. 
     More particularly, the first amplifier circuit 32 includes an operational amplifier 38, a DC blocking capacitor 40, a first bias resistor 42, a second bias resistor 44 and a high frequency shunt capacitor 46. The operational amplifier 38 has an inverting input, a noninverting input and an output. The amplifier 38 has its inverting input electrically coupled to its output. The output of the amplifier 38 forms the output of the first amplifier circuit 32. The DC blocking capacitor 46 has a first plate electrically coupled to the noninverting input of the amplifier 38 and a second plate which the audio input analog signal is applied. The first bias resistor is also coupled to the noninverting input of the amplifier 38. The second bias resistor is coupled in series to the first bias resistor and is adapted to have a first bias potential applied thereto. The high frequency shunt capacitor 46 has a first plate electrically coupled to each of the first resistor 42 and the second resistor 44 at a common node and a second plate coupled to ground potential. 
     The second amplifier circuit 34 includes an operational amplifier 48, a first bias resistor 50, an input resistor 52, a feedback resistor 54 and a high frequency shunt capacitor 56. The output of amplifier 48 forms the output of the second amplifier circuit 34. The input resistor 52 is coupled between the output of the first amplifier circuit 32 and the inverting input of the amplifier 48. The feedback resistor is electrically coupled between the inverting input and output of the amplifier 48. The first bias resistor is coupled to the noninverting input of amplifier 48 and adapted to have the first bias potential applied thereto. The high frequency shunt capacitor 56 has a first plate electrically coupled to the node where the bias potential is applied to the bias resistor 50 and a second plate coupled to ground potential. 
     Third amplifier circuit 36 includes an operational amplifier 58, a first input resistor 60, a second input resistor 62, a first voltage divider 64 and a second voltage divider 66. The first input resistor 60 is electrically coupled between the output of the second amplifier circuit 34 and the inverting input of the amplifier 58. The second input resistor is electrically coupled to the noninverting input of the amplifier 58 and is adapted to have the first bias potential applied thereto. The first bias potential is developed by the first voltage divider 64. Accordingly, the first voltage divider 64 has a resistor 68 to which a second bias voltage, V bb , is applied and a resistor 70 serially coupled between the resistor 68 and ground potential. The first bias potential is developed at a node 64 between the resistor 68 and the resistor 70. The second input resistor 62 is further electrically coupled to the node between the resistors 68 and 70. The second voltage divider 66 has a resistor 72 coupled to the output of the amplifier 58 and a resistor 74 serially coupled between the resistor 72 and ground potential. The output of the third amplifier circuit 36 is that there is a node between the resistor 72 and 74. Furthermore, the second bias potential V bb , is applied to an upper bias voltage input of the amplifier 58. The lower bias voltage input of the amplifier 58 is coupled to ground potential. Thus, the signal applied to the inputs of the amplifier 58 cause the output of the amplifier 58 to switch between ground potential and potential V bb . The voltage divider 66, in a preferred embodiment of the present invention reduces maximum voltage to one half if each of resistors 72 and 74 are equal. For example, each of resistors 72 and 74 may be 2.2k ohms. In the preferred embodiment of the present invention, capacitor 40, capacitor 46 and capacitor 56 are each 0.1 microfarad capacitors. Resistors 42 and 44 are 100k ohms resistors. Resistors 50 and 52 are 10k ohms resistors and resistor 54 is a 470k ohms. Resistors 68 and 70 of first voltage divider 64 are each 4.7k. Input resistors 60 and 62 of the third amplifier 58 are also 10k resistors. 
     Referring now to FIG. 4, there is shown a circuit diagram of the displaying means 24 of FIG. 1. Displaying means 24 includes a first LED 76, a pair of second LEDs 78 and a plurality of third LEDs 80. The anode of the first LED 76 is coupled to the logic level bias potential, V cc , and its cathode is coupled to pin P3.0 and P3.3 of the I/O port, P3, of the microprocessor 26 through a resistor 82 and a resistor 84, respectively. In a preferred embodiment of the present invention, resistors 82 and 82 have a substantially equivalent resistance. For example, of each of resistors 82 and 84 may be 680 ohms. 
     The anode of each of the pair of second LED 78, and the anode of each of the plurality of third diodes 80 are commonly connected to the logic levels bias potential, V cc , through a resistor 86. In a preferred embodiment of the present invention, the resistance of resistor 86 is substantially equivalent to the resistance of each of the resistors 82 and 84. Again, the resistance of resistor 86 may be 680 ohms. The cathode of a first one of LED 78 and a cathode of a second one of LED 78 are coupled to the I/O port P1 through pin P1.0 and pin P1.7, respectively. Similarly, the cathode of each of the third LEDs 80 are coupled to the first port P1 of the microprocessor 26 at pins P1.1-P1.6, as best seen in FIG. 4. 
     As hereinabove described, the difference signal is developed at the pins of the microprocessor 26 through each cathode of LED 76, second LED 78 and third LED 80, the hereinabove described pins being those pins at which the difference signal is developed. The first LED 76 is illuminated when the difference is substantially illuminated. Accordingly, the difference signal is a plurality of parallel bits corresponding to the above-described pins. One of the first LED 76, second LED 78 and third LED 80 are illuminated in response to a state change in a corresponding one of those bits. For example, when the difference is substantially minimized, pins P3.0 and P3.1 go low developing a current through the first LED 76 and each of the resistor 82 and the resistor 84. When a magnitude of the difference exceeds a pre-selected magnitude, one of pins P1.0 and P1.7 go low. The difference signal thereby illuminates one of the second LED 78. One of the second LED 78 indicates a negative (-) polarity and a second one of the second LED 78 indicates a positive (+) polarity of the difference, as generally indicated in FIG. 4. When the magnitude of the difference is above a pre-selected increment but less than the pre-selected magnitude, the difference signal illuminates one of the third LED 80. Accordingly, one of pins P1.1-P1.6 goes low to develop a current through the corresponding one of the third LED 80. Also, first ones of said third LEDs indicate a negative (-) polarity and second ones of the third LEDs indicate a positive (+) of the difference, again as indicated in FIG. 4. 
     With further reference to FIG. 8, the first LED 76, the second LED 78 and third LED 80 are disposed in a linear array 88. The first LED 76 is disposed at the center of the array 88. A first one of the second LED 78 is disposed at a first end of the array 88 and corresponding to a negative polarity and the second one of the second LEDs is disposed at a second end of the array corresponding to a positive polarity. An equal number of the third LEDs are disposed intermediate each one of the second LED 78 and the first LED 76. Each of the third LEDs 80 adjacent the first LED 76 indicates a first increment of the magnitude of the difference. In a preferred embodiment of the present invention, this increment may be five cents. This increment of the magnitude doubles for each successive one of the third LEDs and second LEDs encounter toward said first end and said second end of the array 88. 
     It is particularly useful in the tuner 10 such that the first LED 76 is adapted to display green light. The second LEDs may be adapted to display red light and the third LED is adapted to display yellow light. Also, since the first LED 76 is coupled through resistors 82 and 84, when pins P3.0 and P3.1 go low, the current through first LED 76 is twice that for the current through any of the second LED 78 and third LED 80. It should be noted that the difference signal only illuminates one of the above-described LEDs, 76, 78 and 80. When the difference is minimized, the difference signal causes the first LED 76 to emit twice the optical energy of the second LED 78 and third LED 80. 
     The displaying means 24 also includes a plurality of normally open switches 90. Each of the switches 90 are coupled in series between a corresponding one of third LED 80 and ground potential, as best seen in FIG. 4. Switches 90 are of the type which momentarily close when pressed, such as the membrane type switch as best seen in FIG. 8. Each of the switches 90 represents a corresponding one of the strings 14, which may be indicated by appropriate indicia on an exterior surface 92 of the display means 24. Momentarily closing of one of the switches 90 develops a voltage transition across the closed switch. The voltage transmission is sensed that the corresponding one of pins P1.1-P1.6. The microprocessor in response to the voltage transition determines a proper value of the in tune frequency to be used. The proper value of the frequency is associated with the selected one of the strings. Also, the momentary closing of the switch causes a current through the third LED 80 attached thereto to provide visual confirmation. The microprocessor 26, the control of system software as described hereinbelow, repeatedly scans switches 90 to determine when a voltage transition does exits to indicate that one of the strings will be tuned and select a proper frequency. 
     In a further embodiment of the present invention, displaying means 24 also includes a plurality of further LEDs 94 and a plurality of normally open switches 96. Each of the switches 96 are coupled in series between a cathode of a corresponding one of the LEDs 94 and ground potential. The anode of each of the LED 94 is commonly connected to resistor 86. The face 92 of displaying means 24 may contain certain indicia such that each of the switches 96 represents a selected tonal increment from an audible tone heard at the in tune frequency. Closing of one of the switches 96 will make the corresponding one of the LED 94 and develops a voltage transition across the switch 96. The microprocessor 26 in response to this voltage transition occurring at one of pins P3.3-P3.5 changes the in tune frequency in accordance with the selected tonal increment. Also the closing of the switch 96 develops a current through to the corresponding LED 94 for a visual confirmation. The tonal increment in a preferred embodiment of the present invention may represent half tone steps. A half tone step may be either sharp or flat in tonal polarity. Again, the microprocessor 26 scans these switches to determine if one has been closed momentarily. 
     With reference to each of FIG. 1 and FIG. 5, the electronic tuner 10 of the present invention further comprises means 98 for muting the instrument 12 during tuning of the selected one of the strings 14. Muting means 98 may include a normally conductive transistor switch 100 having a source, S, a drain, D, and a gate, G. The audio analog signal is applied to the source, S, and is coupled through the switch 100 to the drain, D. Muting means further includes means 102 for selectively biasing the gate, G, to turn the transistor switch 100 off when muting is desired. In a preferred embodiment of the present invention, transistor switch 100 may be a P-channel JFET 104. 
     The biasing means 120 include a flip-flop 106 and a normally open switch 108. Flip-flop 106 has a set input, S, a reset input, R, a logical output, Q. The logical output, Q (not) is electrically coupled to the gate of the FET 104. In normal operation, the logical output Q of the flip-flop 106 develops a bias voltage to maintain the transistor switch 100 on. As best seen in FIG. 5, the signals applied to the set input, S, and reset input, R, are logically inverted. 
     The normally open first switch 108 is coupled to the reset input, R, and ground potential. Closing of the switch 108 develops a voltage transition at the reset input, R, to change a logical state of the bias voltage to turn the transistor switch 100 off thereby muting the instrument 12. Voltage transition is caused by current through a resistor 110 coupled between the bias voltage, V bb , and the reset input, R. In a preferred embodiment of the present invention, resistor 110 may be a 4.7k resistor. 
     Biasing means 98 further includes a normally open switch 112 coupled intermediate the set input S of the flip-flop 106 and ground potential. The set input S of the flip-flop 106 is also coupled to the bias potential V bb  through a resistor 114. In a preferred embodiment of the present invention, resistor 114 may also be a 4.7k ohm resistor. A voltage transition at the set input changes the logical state of the bias voltage to turn the transistor switch 100 on thereby allowing induction between the audio and an audio out as best seen in FIG. 5. 
     When muting the instrument 12, an audio sound is developed through a high powered amplifier, the switching of the transistor switch 100 may cause thump in the speakers. Accordingly, a capacitor 116 is electrically coupled between the gate of the transistor switch 100 and ground potential filter switching transients which may cause an audible thump to be heard. The flip-flop 106 may also be a 74C74 flip-flop which is commercially available. 
     The biasing means 98 further includes a pair of filter circuits 118. Each of the filter circuits 118 includes a resistor 120 coupled between a corresponding one of the source, S, and drain, D, and ground potential to reduce residual DC voltage in the audio signal. The filter circuits 118 also include a pair of diodes 122, 124 electrically coupled between the corresponding one of the source and the drain of the transistor switch 100. The first diode 122 is coupled in reverse polarity to the second diode 124. The diodes prevent DC splice at the corresponding one of the source S and drain D of the transistor switch 100. Since the normal forward conduction voltage drop in each first diode 122 and second diode 124 is 0.6 volts, the audio signal which is in millivolts does not cause forward biasing of either diodes 122 or 124. Biasing means 98 also includes a capacitor 126 coupled between the set input S and ground potential. In power up of the tuner 10, as the voltage, V bb , increases, the voltage at the set input, S, is maintained low to force a set of the flip-flop 106 so that transistor switch 100 is conductive on power up. 
     With reference now to FIG. 1 and FIG. 6, the electronic tuner 10 also includes a power supply 128 to develop each of the bias potentials, V bb  and V cc . The power supply 128 includes a PNP power supply transistor 130, a normally open first switch 132, an NPN control transistor 134, a first zener diode 136 and a normally open second switch 138. 
     The power supply transistor 130 has an emitter adapted for electrical coupling to a positive terminal of a battery 140, a collector and a base. In the preferred embodiment of the present invention, battery 140 may be a 9 volt battery which is removable as indicated in FIG. 6. The first switch 132 is resistively coupled to the base of transistor 130 through resistor 142 and diode 144. Momentary closing of switch 132 turns transistor 130 on into saturation whereby voltage of battery 140 is developed at the collector of switch 130, this voltage being V bb . The control transistor 134 has an emitter adapted to be coupled to ground potential, collector electrically coupled to the first switch 132 and a base adapted for coupling to a negative terminal of the battery 140. 
     The zener diode 136 has an anode resistively coupled through a resistor 146 to the base of the control transistor 134 and a cathode coupled to the collector of the power supply transistor 130. The control transistor saturates in response to the power supply transistor being turned on thereby maintaining the base of the power supply transistor 130 at a low voltage to keep the power supply transistor on. The second switch 138 is coupled between the base of the control transistor 134 and ground potential. Momentary closing of the second switch turns the control transistor off to remove the base bias voltage from the base of the power supply transistor 130. The transistor 130 is then turned off. The emitter of the control transistor 134 is coupled to ground potential through the inverse logic output, Q of a flip-flop 148. The logical inverse set input of the flip-flop 148 is coupled to the capacitor 126 of muting means 98 such that flip-flop 148 is set on power up. The inverse logic output Q is therefore at zero volts or ground potential. When the tuning apparatus is turned on and not used for a given length of time, a strobe pulse is developed at pin P3.6 which is applied to the clock input C of the flip-flop 148. The strobe pulse changes the output state causing the voltage at the inverse logic output Q to go high thereby turning off the control transistor 134. As described hereinabove when transistor 134 turns off, the base bias is removed from transistor 130, turning off the power supply. In a preferred embodiment of the present invention, flip-flop 148 may also be 74C74 commercially available flip-flop. 
     Power supply 128 further includes a voltage regulator 150 for developing a well regulated logic level second bias voltage, V cc  in response to the first bias voltage, V bb . As battery 140 discharges, the bias voltage V bb  may be insufficient. Therefore, the power supply also includes a low power indicator circuit 152. 
     Indicator circuit 152 has a second NPN transistor 154 and a second zener diode 156. The transistor 154 has a collector resistively coupled to the bias voltage V cc  through a resistor 158, an emitter coupled to ground potential and a base resistively coupled to the anode of zener diode 156 through a resistor 160. Zener diode 156 has its cathode coupled to the first bias potential V bb . The NPN transistor 154 is saturated when the battery 140 has sufficient voltage. The second NPN transistor 154 turns off when the battery voltage falls below a reverse breakdown voltage of the second zener diode 156. The collector of the second NPN transistor 154 develops a collector voltage substantially equal to the second bias voltage V cc  when the second transistor turns off. This collector voltage is coupled to the microprocessor 26 at pin P3.7. When this collector voltage is sensed, the microprocessor may develop a further signal, the displaying means in response may visually indicate the low voltage of the battery. This may be done through the first LED 78. 
     A complete listing of the 8051 assembler language program stored in ROM 28 of the CPU 22 is attached hereto as Appendix A. FIGS. 10-15 are self-explanatory flowcharts summarizing the operation of the program in Appendix A. 
     There has been described hereinabove a novel electronic tuner constructed according to the principles of the present invention. Those skilled in the art may now make numerous uses of and modifications to the exemplary preferred embodiment without departing from the inventive concepts disclosed herein. Accordingly, the present invention is to be defined solely by the scope of the following claims. ##SPC1##