Polycrystalline silicon ohmic contacts to group III-arsenide compound semiconductors
This is a continuation of application Ser. No. 07/497,187, filed March 22, 1990 now abandoned. 
    
    
     BACKGROUND AND SUMMARY OF THE INVENTION 
     The present invention relates generally to group III-arsenide binary or ternary compound semiconductor substrates and devices and more specifically to contact for these devices. 
     Semiconductor devices made with group III-arsenide alloys, for example gallium arsenide, have increased in their use. Presently ohmic contacts to gallium arsenide substrates or devices use a gold-germanium alloyed contact. These contacts start to degrade in an unpredictable manner when processing temperatures exceed 400° centigrade. Alloying also produces pitted metal/GaAs interfaces which can give rise to high field regions, current crowding with associated local joule heating, enhanced electromigration, and eventual device failure. This places a substantial restriction on the final processing steps, including packaging and die attachment. 
     Thus it is an object of the present invention to provide an ohmic contact structure to group III-arsenide substrates which does not restrict the final processing and packaging temperatures. 
     These and other objects are obtained by using polycrystalline silicon as the contact to regions of a group III-arsenide substrate. The substrate may be gallium arsenide or other group III-arsenide compound semiconductor. A heavily doped N type contact region is formed in the N type substrate region by heating the device sufficiently to out-diffuse silicon impurities from the polycrystalline silicon contact into the N type region. The N type region may be sources or drains of field effect transistors. The process of formation includes forming an opening in an insulative material, which may be silicon nitride, silicon dioxide or tantalum oxide and applying the polycrystalline silicon contact material into the opening. The heating of the substrate will diffuse silicon from the contact material into the substrate to form the heavily doped N type contact region. 
     Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The FIGURE is a cross-sectional view of an ohmic incorporating the principles of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE DRAWING 
     A group III-arsenide substrate 10 for example gallium arsenide, having an N conductivity type region therein, includes an ohmic contact 12 of polycrystalline silicon. The contact 12 extends through an opening 14 in an insulative layer 16, which may be silicon nitride. Depending upon the processing steps, a highly doped N++ contact region 18 is formed in the substrate 10 by out-diffusion of silicon impurities from the polycrystalline silicon contact layer 12 in the substrate 10. This forms an ohmic contact with the gallium arsenide substrate. 
     The group III-arsenide substrate may be selected from the group of gallium arsenide, aluminum gallium arsenide, gallium indium arsenide, and aluminum indium arsenide. The region 10 of the substrate may be a source or drain of field effect transistors or any other active or passive device. The polycrystalline silicon layer 12 is stable up to temperatures in the range of 1000° C. which is well above the anticipated processing temperatures for the final processing, packaging and die attachment which generally do not exceed 350° C. 
     The process for forming the ohmic contact includes forming an opening 14 in the insulative layer 16 and applying a layer of polycrystalline silicon. This may be applied by photo-enhanced chemical vapor deposition, laser-induced chemical vapor deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition. The layer is then patterned to form the ohmic contact 12. A special heating step may be performed to diffuse silicon from the polycrystalline silicon layer 12 into the substrate 10. In a typical example, the substrate 10 may have a background impurity concentration range 5×10 15  cm -3  to 5×10 17  cm -3 . The high impurity region contact 18 may be formed by heating the substrate at a temperature in the range of 750° C. to 900° C. for a period of 5 seconds to 60 seconds to produce an impurity concentration in the range of 1×10 18  cm -3  to 1×10 19  cm -3 . 
     The process for forming N++ regions in the gallium arsenide substrate 10 may also be used wherein the substrate region 10 is a P conductivity type and therefore forms a PN junction between regions 18 and 10. 
     Although the process has been described as forming N++ regions in a gallium arsenide substrate, if the final processing and packaging temperatures are below 700° C., very little if any, out-diffusion from the polycrystalline silicon layer contact 12 will result and therefore the polycrystalline silicon 12 may be used as a contact to any region of the gallium arsenide substrate 10. 
     Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only, and is not to be taken by way of limitation. The spirit and scope of the present invention are to be limited only by the terms of the appended claims.