Method and circuit for decoding a Manchester code signal
BACKGROUND OF THE INVENTION 
     The present invention relates to a circuit for extracting separate data and clock signals from a Manchester encoded digital communication signal. 
     Manchester encoding is commonly used in bit-serial digital communications, and numerous types of Manchester decoder circuits exist in the prior art. Many of these circuits are incapable of accurately decoding a Manchester signal at high speed, typically because signal propagation delays in the components of the circuits are either too long (i.e., the circuit is slow) or not sufficiently controllable. Such circuits include those having one-shot logic circuits and those implemented using TTL logic. Further, of the prior art Manchester decoder circuits that are capable of reliable operation at high speed, many are complicated and expensive. Such circuits include phase-locked loop circuits and fast-sampling state machines. 
     SUMMARY OF THE INVENTION 
     The present invention is a reliable method and circuit for decoding a Manchester encoded signal. The circuit includes a pair of latch circuits which are used to detect transitions or edges in the encoded signal for providing respectively set and reset pulses to a third latch circuit, an output of which comprises the decoded data of the Manchester signal. The circuit also includes two delay elements, input and delay matching buffers, and one or more logic gates. Logical combination of the decoded data with a delayed encoded signal provides a decoded clock. The circuit can be implemented using fast ECL devices in a single integrated circuit. In a preferred embodiment, the latch circuit pair comprise flip-flop logic circuits matched on an integrated circuit to equalize signal propagation delays through the flip-flops. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other advantages of the present invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a signal diagram illustrating the method of the present invention.; 
     FIG. 2 is a schematic of an embodiment of the Manchester decoder circuit of the present invention; and 
     FIG. 3 is a timing diagram of the circuit of FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Manchester encoding is a method of combining a serial data stream and a synchronized clock signal into a single signal. It can be accomplished, for example, by combining a serial data stream of NRZ data with a synchronized 50% duty cycle clock signal in an exclusive-NOR logical operation. As a result of this operation, the data becomes encoded as a series of two-bit codes. A logical &#34;1&#34; is represented as a data bit cell in which the signal is at a high level for the first half of the data bit cell and at a low level for the second half. Thus a logical &#34;1&#34; is encoded as a two-bit code 1,0, each code bit cell being one-half the data bit cell. A logical &#34;0&#34; is represented as a data bit cell in which the signal is at a low level for the first half of the data bit cell and at a high level for the second half. Thus a logical &#34;0&#34; is encoded as a two-bit code 0.1. 
     By examining examples of typical Manchester encoded data streams, it can be seen that a transition in the original data from a logical &#34;0&#34; to a logical &#34;1&#34; causes the Manchester encoded data stream to contain a sequence of two code bits equal to 1. Likewise when the original data transitions from a logical &#34;1&#34; to a logical &#34;0&#34;, the Manchester encoded data stream contains a sequence of two code bits equal to 0. At all other times, i.e., when the original data is a stream of consecutive logical &#34;1&#34;s or &#34;0&#34;s, the Manchester encoded data stream consists of alternating 1 and 0 code bits. 
     Referring to FIG. 1, an exemplary Manchester encoded waveform 100 having clock periods 102 is shown. Each clock period 102 defines a data bit cell including two code bit cells (e.g., high state code bit cell 104 and low state code bit cell 106). Waveform 100 has falling edge transitions A,C,E,G,I,K,M and 0 and rising edge transitions B,D,F,H,J,L and N. Transitions A,B,C,E,F,H,J,L,M and 0 each occurs in the center of a clock period, and thus each conveys information: the falling edge transitions represent logical &#34;1&#39;s&#34;, and the rising edge transitions represent logical &#34;0&#39;s&#34;. Transitions D,G,I,K and N each occur at an edge of a clock period, and thus do not convey data. The preferred method of the present invention for extracting a data signal from a Manchester encoded waveform is described below with reference to the exemplary waveform of FIG. 1. 
     As a first step in the preferred method, each transition in the waveform is detected, although, as will be apparent, it is only necessary to detect the transitions occurring in the middles of clock periods 102. For each detected transition, the state (high or low) of the waveform 100 between one-half and one clock period preceding the detected transition is determined. Thus, for example, assuming transition B to have been detected, the state (low) of waveform 100 at point 101 is determined. 
     An output signal 103 is then generated having a first and a second state, preferably comprising respectively a low state to represent a logical &#34;0&#34; in the encoded data and a high state to represent a logical &#34;1&#34;, although an inverse relationship may also be used if desired to represent the original data. The output signal, the clock periods of which may be delayed with respect to the clock periods of waveform 100, is characterized by the following rules based on the direction of the detected transitions and the correspondingly determined state of waveform 100: 
     a. if a detected transition is a rising transition and the determined state of the waveform is a low state (e.g., the conditions shown by arrow 108), the output signal (which in the example is assumed to begin as a logical &#34;1&#34;) changes from a high state to a low state; 
     b. if a detected transition is a rising transition and the determined state of the waveform is a high state (e.g., the conditions shown by arrow 110), the output signal remains in its previous state; 
     c. if a detected transition is a falling transition and the determined state of the waveform is a low state (e.g., the conditions shown by arrow 112), the output signal again remains in its previous state; and 
     d. if a detected transition is a falling transition and the determined state of the waveform is a high state (e.g., the conditions shown by arrow 114), the output signal changes from a low state to a high state. 
     As can be seen, transitions which occur at an edge of the clock period (e.g., 116 and 118) are governed by rules (b) and (c) above, and thus produce no change in output signal 103. 
     An embodiment 200 of the Manchester decoder circuit of the present invention is shown in FIG. 2. For purposes of illustration, a timing diagram of the circuit 200 of FIG. 2 is shown in FIG. 3, with corresponding signal points indicated in each figure. Referring to FIGS. 2 and 3, a Manchester encoded signal 300 is coupled through buffer circuit 202 to the clocking input of flip-flop FF2 and to the input of delay element circuit 204. Buffer circuit 202 also inverts the encoded signal 300 and provides inverted signal 302 to the clocking input of flip-flop FF1. 
     Delay element circuit 204 generates delayed by encoded signals 304 and 306. Signal 304 is delayed by 1/2 of a clock period of the original clock encoded in signal 300, and signal 306 is delayed by 3/4 of a clock period. The length of the delay depends on the speed at which data is transferred to circuit 200. For example, at a data transfer rate of 100 Megabits per second, delay element circuit 204 would be implemented to delay signal 304 by 5.0 nanoseconds(ns), and signal 306 by 7.5 ns. Delay element circuit 204 may be implemented using a fixed or programmable delay line circuit. Alternately, if it is desired that circuit 200 be implemented in a fully integrated circuit, delay element circuit 204 may be implemented as a high-speed clock circuit and a multiple-output shift register circuit to generate the delayed signals 304 and 306. 
     Delayed encoded signal 306 is provided to the data input D of each flip-flop FF1, FF2. Flip-flops FF1 and FF2 are rising edge triggered flip-flop circuits. FF1 samples delayed encoded signal 306 when the inverted encoded signal 302 at its clocking input transitions from a low level to a high level (i.e., on a rising edge of inverted signal 302). Thus in effect FF1 is clocked once for each falling edge of encoded signal 300. FF2 samples delayed encoded signal 306 when the original encoded signal 300 at its clocking input transitions from a low level to a high level (i.e., on a rising edge of encoded signal 300). As described above, it is a property of a Manchester encoded signal that a transition occurs in the midpoint of every data cell due to the encoded clock signal. The encoded data is represented by the direction of that transistion. Thus, depending on the data represented in each data cell of the encoded signal, either FF1 or FF2 will be clocked by an edge or transition at the midpoint of each data cell. Although edges are also present at the boundaries of the data cells, these transitions do not cause the latched data output of either flip-flop FF1 or FF2 to change because the data at the input of the flip-flop will be the same as the data previously latched. 
     The data signal at the D input of FF1 (delayed signal 306) represents the original encoded signal 300 delayed by 3/4 of a data cell, which is equivalent to 11/2 code bit cells. If, when a rising edge transition in inverted signal 302 causes FF1 to sample the data at its D input, the sampled data is a 1, then it is known that original encoded signal 300 has been a 1 for two consecutive code bit cells and that the decoded data should change from a logical &#34;0&#34; to a logical &#34;1&#34;. Flip-flop FF1 accordingly outputs a 1 on its Q output which is coupled to the set control input of an SR flip-flop FF3. This transition, shown for example by point 308 on signal 310, causes the Q output of FF3 to be set to a &#34;1&#34;. The signal 312 at the Q output of flip-flop FF3 is coupled back to the reset control input of FF1 to cause signal 310 at the Q output of FF1 to return to 0 after FF3 has been successfully set. This prevents flip-flop FF1 from trying to set flip-flop FF3 at the same time flip-flop FF2, the operation of which is described below, may try to reset flip-flop FF3. 
     If, on the other hand, the data at the D input of flip-flop FF1 is a 0 when sampled, it is known that original encoded signal 300 has not been a 1 for two consecutive code bit cells, indicating that the encoded data has not changed from a logical &#34;0&#34; to a logical &#34;1&#34;. Therefore flip-flop FF1 remains in the 0 state (i.e., the signal at Q output of FF1 remains 0) and FF3 is not set. This is the result, for example, whenever flip-flop FF1 is clocked by an edge at the boundary of a data cell. 
     Flip-flop FF2 operates in a similar manner to reset FF3 whenever the data at its D input (delayed signal 306) is a 0 when flip-flop FF2 is clocked by a rising edge in signal 300. As in the case of FF1, the data signal at the D input of FF2 (delayed signal 306) represents the original encoded signal 300 delayed by 3/4 of a data cell, which is equivalent to 11/2 code bit cells. If, when a rising edge transition in non-inverted signal 300 causes FF2 to sample the data at its D input, the sampled data is a 0, then it is known that original encoded signal 300 has been a 0 for two consecutive code bit cells and that the decoded data should change from a logical &#34;1&#34; to a logical &#34;0&#34;. Flip-flop FF2 accordingly outputs a 1 on its inverted Q output which is coupled to the reset control input of SR flip-flop FF3. This transition, shown for example by point 314 on signal 316, causes the Q output of FF3 to be set to a &#34;0&#34;. The signal at the inverted Q output of flip-flop FF3 is coupled back to the set control input of FF2 to cause signal 316 at the inverted Q output of FF2 to return to 0 after FF3 has been successfully reset. This coupling back prevents flip-flop FF2 from trying to reset flip-flop FF3 at the same time flip-flop FF1 may be trying to set flip-flop FF3. 
     If, on the other hand, the data at the D input of flip-flop FF2 is a 1 when sampled, it is known that original encoded signal 300 has not been a 0 for two consecutive code bit cells, indicating that the encoded data has not changed from a logical &#34;1&#34; to a logical &#34;0&#34;. Therefore flip-flop FF2 remains in the 1 state (i.e., the signal at inverted Q output of FF2 remains 0) and FF3 is not reset. This is always the result when flip-flop FF2 is clocked by an edge at a boundary of a data cell. 
     The Q output of flip-flop FF3 is coupled to an input of each of exclusive-OR logic gates 206 and 208. A second input of logic gate 206 is coupled to to the 1/2 clock period delay line of delay element circuit 204 by a plurality of delay matching buffer circuits 210. The Manchester encoded data signal delayed by 1/2 clock period (signal 304) is combined with the decoded data at the Q output of FF3 (signal 312) to recover the clock from the encoded signal. 
     There is a delay in the decoded data of signal 312 relative to the original data encoded in signal 300. This delay includes a 1/2 data cell delay which, in recovering the clock signal, is compensated for by the delay of 1/2 clock period in signal 304. There is additional delay in the decoded data due to signal propagation delays through flip-flops FF1/FF2 and FF3. Delay matching buffer circuits 210 compensate for this delay (see signal 317). Preferably, flip-flops FF1, FF2 and FF3, and delay matching buffers 210 are implemented in a single integrated circuit to minimize variations in the signal propagation delays of the different component circuits that might be caused by variations in the semiconductor processes used to manufacture the circuits. ECL devices are preferred because of their speed, although other technologies also may be used. Delay matching buffers 210 can be implemented as desired to emulate the signal propagation delays of the flip-flops during operation. If the circuit is implemented using discrete components, delay matching buffers can be implemented using conventional fixed or programmable delay elements. 
     The clock signal at the output of exclusive-0R gate 206 (signal 318) is inverted with respect to original clock signal 320. This arrangement is useful for subsequent circuitry because the rising edge of the inverted clock occurs in the center of each data cell of the decoded data (signal 312), thus giving equal set up and hold times for clocking the decoded data into additional circuits. Because the decoded data signal 312 is coupled through exclusive-OR gate 206 to generate the recovered clock 318, the recovered clock will be delayed from the center of the data cells of the decoded data by the propagation delay of exclusive-OR gate 206. If it is desired that the propagation delay of exclusive-OR gate 206 be cancelled, the decoded data signal 312 can be coupled through an optional delay element, such as exclusive-OR gate 208 shown in FIG. 2, preferably in the same integrated circuit, to provide a data signal output having a matching delay. 
     Thus a novel circuit for decoding a Manchester encoded digital communication signal has been described. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments. For example, flip-flops FF1 and FF2 can be replaced by falling edge triggered flip-flops if the clocking inputs provided to the two flip-flops are reversed. Further, each flip-flop can be replaced by other latch circuits having cross-coupled logic gates, and alternate circuitry may be used to condition the control signals provided to set and reset flip-flop FF3 to avoid conflict. The described embodiments are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.