IC D-type master/slave flip-flop
BACKGROUND OF THE INVENTION 
     This invention relates to an integrated circuit, comprising a D-type master/slave flipflop comprising: 
     a bistable master element connected between two supply voltage terminals and having a first data input for receiving data, 
     control means having a control signal input for erasing or enabling writing into the master element under control of a control signal; 
     a bistable slave element connected between two supply terminals and having a second data input connected to a data output of said master element. 
     The invention is used, for example, a comparator which is part of an analog-to-digital converter which is referred to as a parallel converter in which an analog input signal is applied to the inputs of several parallel comparator circuits in order to obtain a digital output signal. The input voltage is compared in said circuits with a reference voltage which differs for each comparator circuit. The output signals of the comparator circuits are converted into a digital output signal by means of a decoding device. Analog converters often comprise a flip-flop as described above. 
     A circuit of this kind is known, inter alia from European Patent Application No. 85 20 1742.5, which corresponds to U.S. Pat. No. 4,649,293 (3/10/87). 
     The cited U.S. Pat. No. describes a clocked voltage comparator which comprises a Delay-type master/slave flip-flop. The clocked comparator comprises: 
     an acquisition or comparison stage which serves to compare an analog input voltage (V IN ) with an analog reference voltage (V REF ) and to supply the result of said comparison as an intermediate signal (V M ) and its complement (V M ). An amplifier stage amplifies the logic states of the intermediate signal. A first and a second latching stage are coupled to the comparison stage and the amplifier stage, respectively, for generating and storing the logic states determined by the signals from the comparison stage and the amplifier stage. Each latching stage comprises a differential transistor pair having a common terminal connected to ground. A further differential transistor pair is arranged in parallel with the last-mentioned transistor pair and is controlled by a clock signal C for the first latching stage and by its complement C for the second latching stage. The comparison stage and the amplifier stage are also controlled by the clock signal C and the latching stages are each coupled to the comparison stage and the amplifier stage, respectively, by means of load resistors. 
     The known comparator operates in two periods. In a first period acquisition of the information by the first differential pair takes place. This acquisition is effected at the drain of the transistors of the first differential pair of the first latching stage when the clock or control signal is high. 
     At that instant the output signals of the memory stage, being available at the gate electrodes of the transistors of the bistable circuit and forming the output signals of the comparator, appear as signals whose states are both nearly zero. Former information available at the gate electrodes is erased. 
     During a second period, when the clock or control signal becomes low or zero again, the decision and storage function is performed, i.e. the signals which are available at the gate electrodes of the bistable circuit and which were previously both nearly zero then become complementary. 
     Thus, each time when the clock signal is high, the output signals of the comparator are erased and both become approximately zero and at that time these output signals do not furnish information. This is a problem in applications where this information is needed at any moment. 
     It is known from the state of the art, i.e. from the cited U.S. patent, that this problem can be solved by utilizing a master-slave structure, i.e. by associating two comparators in the way that has been set forth hereinabove. This structure enables the storage of the information during the acquisition phases. 
     However, this known structure necessitates the use of a large number of components, which is a drawback when large scale integration is desired. On the other hand, this solution also necessitates the use of a complementary clock signal which is always difficult to realize when a strictly complementary signal is to be obtained. 
     SUMMARY OF THE INVENTION 
     The present invention proposes a circuit which enables the storage of the information while avoiding the drawbacks of the known master/slave system. 
     In accordance with the invention, this object is achieved by means of a circuit as defined in the introductory paragraph above by providing means for controlling the slave element by means of an input signal at said second data input alone and for simultaneously writing into the slave element when the input signal at said second data input has reached a predetermined voltage level. 
     An embodiment in accordance with the invention includes an integrated circuit in which the master element comprises two cross-coupled inverters, each of which is connected between the two supply voltage terminals and comprises a respective first load and a respective first driver transistor. The slave element comprises two cross-coupled inverters, each of which is connected between the two supply voltage terminals and comprises a respective second load and a respective second driver transistor. The control means comprise two control transistors, each of which has a channel disposed in parallel to a channel of the respective first driver transistor and a control electrode for receiving the control signal. The circuit is characterized in that the means for controlling the slave element comprises two coupling transistors, each of which has a channel disposed parallel to a channel of the respective second driver transistor and a control electrode, which is a data input terminal, coupled to a respective data output terminal of the master element. 
     The circuit in accordance with the invention thus offers, inter alia, the following advantages: 
     it comprises relatively few components, 
     it operates by means of a single clock signal of high frequency, 
     it has a low power consumption, 
     it enables output signals to be obtained which save, upon each change-over of the state of a control signal, the information acquired during the preceding state. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be described in detail hereinafter, by way of example, with reference to the accompanying drawings; in which: 
     FIG. 1 diagrammatically shows an example of the circuit in accordance with the invention; 
     FIG. 2 provides waveforms which illustrate the sequencing of the signals occurring in the circuit shown in FIG. 1; and 
     FIG. 3 shows an analog-to-digital converter circuit realized by means of comparators in accordance with the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     As appears from FIG. 1, the example of the circuit in accordance with the invention comprises three parts P 1 , P 2 , P 3  which cooperate in order to obtain the desired result, enabling signals to be obtained at the output which save, upon each change-over of the state of a control signal, the information acquired during the preceding state. 
     In the embodiment of the invention which is shown in FIG. 1, the synchronized comparator is preferably realized by way of enhancement-type field effect transistors which are made, for example, in gallium arsenide; because their pinch-off voltage V T  &gt;0, they are normally pinched off in the absence of a gate-source signal. 
     The first part P 1  of the circuit shown in FIG. 1 is a comparator circuit which is formed by an acquisition stage followed by a memory stage. The memory stage is a D-type flip-flop which forms the master element of the circuit. 
     The acquisition stage is formed in known manner by two field effect transistors T 1  and T 2  which are coupled by way of their sources in order to form a first differential pair. The sources coupled to the node 3 are connected to the drain of a transistor T 3  which is connected as a current source. This transistor T 3 , whose source electrode is connected to ground, is controlled either by a clock signal C or by a d.c. supply voltage V B . 
     The gate electrode of one of the transistors of the acquisition stage, for example, the transistor T 1 , receives the analog signal V IN  which is to be compared with the reference signal V REF  which is applied to the gate electrode of the second transistor T 2  of the first differential pair. 
     The drains of the transistors T 1  and T 2  of the acquisition stage are connected to a d.c. supply voltage V DD  via loads R 1  and R 2 , respectively, which may be, for example, resistive loads. 
     In order to form a bistable circuit, the memory stage is formed, first of all by a second differential pair of driver transistors T 5  and T 6  which are coupled by way of their sources and which are connected directly to ground at the node 9. 
     The gate electrodes of the transistors T 5  and T 6  of this second differential pair, i.e. nodes 5 and 6, respectively, receive, via resistive loads R&#39; 1  and R&#39; 2 , respectively, the drain signals of the transistors T 1  and T 2 , respectively, of the first differential pair. 
     The gate electrode of each of the transistors T 5  and T 6  is cross-wise coupled to the drain of the other transistor T6 and T5 of the second differential pair. This second differential pair, with their respective loads, forms the D-type flip-flop (master element). The master element thus includes two cross-coupled inverters T 5 , T 6 . 
     The memory stage is controlled by means of two transistors T 7  and T 8  which are connected parallel to the transistors T 5  and T 6 , respectively, of the second differential pair, thus forming a third differential pair. The transistors T 7  and T 8  of the third differential pair are controlled by the clock signal C. The common sources are connected to ground at the node 9. 
     When the clock signal C becomes high, with field effect transistors of the enhancement type, the acquisition stage is activated because the current source transistor T 3  becomes conductive (in this case this transistor is controlled by the clock signal C). 
     Because the memory stage is controlled by the clock signal C, as soon as the clock signal becomes high the two output signals of the memory stage, S 1  and S&#39; 1 , which are available at the nodes 5 and 6, respectively, simultaneously become zero, more exactly, they assume a state in the vicinity of zero because of the difference existing between the signals V IN  and V REF . Consequently, the output of the memory stage no longer bears a relationship to the relative values of V IN  and V REF  and the memory stage is erased. 
     This de-activation of the memory stage at the instant at which the acquisition stage is activated prevents the occurrence of instabilities which would occur if the acquisition stage and the memory stage were controlled by different clock signals, for example by complementary clock signals, as is the case in U.S. Pat. No. 4,649,293. 
     This result is obtained because of the fact that the control of the memory stage is imposed by means of the third differential pair T 7 , T 8 . The same result is obtained if the acquisition stage is continuously active, i.e. when the current source transistor is fed by a d.c. voltage V B  and hence is continuously conductive. 
     The second part of the circuit P 2  of FIG. 1 consists of two stages for modifying the output signals S 1  and S&#39; 1  of the memory stage, each of said stages treating a respective one of the signals S 1  or S&#39; 1 . 
     As has already been stated, when the clock signal is high and the comparator operates in the acquisition period, the output signals S 1  and S&#39; 1  of the memory stage have a state which is only approximately zero and not exactly zero. 
     Each stage for modifying the signals comprises: 
     a transistor which is connected as an inverter, T 11  and T 12  respectively, whose drain is connected to the d.c. supply V DD  via a load, for example, a resistive load R 11  and R 12 , respectively, and whose source is connected to ground, 
     followed by a second transistor which is connected as an inverter, T 13  and T 14 , respectively, whose drain is connected to the d.c. supply voltage V DD  via a load, for example, a resistive load R 13  and R 14 , respectively, and whose source is connected to ground. 
     The output signals S 1  and S&#39; 1  of the memory stage are applied to the gate electrodes of the first inverter transistors T 11 , T 12 . The output signals of the first inverter transistors are applied to the gate electrodes of the second inverter transistors T 13 , T 14 , and the output signals S 2  and S&#39; 2  form the modified output signals of the memory stage. Actually, the proportioning and the conductivity type of the transistors of this part P 2  are such that when the output signals S 1  and S&#39; 1  of the memory stage have a state near zero, the output signals S 2  and S&#39; 2  have a state which is exactly zero. 
     As has already been stated, in order to avoid the loss of information due to the fact that the two output signals of the memory stage simultaneously become zero during the acquisition phase, the signals S 2  and S&#39; 2  supplied by the part P 2  are applied to the inputs of the part P 3 , which makes up the slave element of the circuit. 
     This part P 3  constitutes a flipflop of the R-S type. It is formed by a first pair of parallel-connected transistor T 21  and T 23  whose coupled drains are connected to the d.c. power supply voltage V DD  via a load, for example, a resistive load R 21 , and whose sources are connected to ground, and by a second pair of parallel-connected transistors T 22 , T 24  whose coupled drains are connected to the d.c. power supply voltage V DD  via another load, for example a resistive load R 22 , and whose sources are connected to ground. The gate electrodes of one of the transistors of each pair, i.e. T 21  and T 22 , respectively, receive the signals supplied by the part P 2 , i.e. S 2  and S&#39; 2 . The gate electrodes of the second transistor of each pair are cross-wise coupled to the common drain of the other pair. The cross coupled transistors T 23  and T 24  together with the resistive loads R 21  and R 22  form a pair of coupled inverters and act as the slave element in the master/slave circuit. 
     As appears from FIG. 2, it is thus ensured that the state assumed by the signals S 2  and S&#39; 2  during the decision period corresponding to the low state of the clock signal C is saved and hence memorized by the output signals S and S of the R-S flipflop. 
     FIG. 2 illustrates the sequencing of the signals in the circuit and shows first of all the input signals V IN  and V REF . It also shows the clock signal C whose high states correspond to the acquisition phase A and whose low states correspond to the decision phase D. It shows that the signal S 1  becomes low at the instant t 1  at the start of an acquisition phase, the signal S&#39; 1  also being low, after which the signal S&#39; 1  becomes high at the instant t 2  at the start of the decision phase D, the difference between the input signals V IN  and V REF  being positive. At the instant t 3  at the start of the next acquisition phase the information in the master element is erased and both signals S 1  and S&#39; 1  again becomes low. At the start of the next decision phase at t 4  the signal S 1  becomes high, the difference between the signals V IN  and V REF  being negative, etc. 
     The signals S 2  and S&#39; 2  follow the same diagram at the same instants, but in the low state they are both exactly zero. 
     At the instant t 5  the situation at the instant t 1  occurs again and at the instant t 6  the situation at the instant t 2  occurs. At the start of the first decision phase at t 2 , the states of the signals S and S are reversed and these signals then keep their states until the instant t 4  where they are reversed again. Thus, they always remain complementary and are reversed only at the start of a decision phase when the sign of the difference between V IN  and V REF  changes. The information of the preceding state is thus memorized. 
     The output signals S and S of the R-S flipflop of the part P 3  constitute the digital output signals of the comparator in accordance with the invention. 
     The phase of the output signal S follows the sign of the difference between the input signal V IN  and the reference signal V REF . 
     The analog-to-digital converter shown in FIG. 3 comprises several comparators (COMP 1, . . . COMPN) which are connected in parallel and each of which is provided with two inputs. The analog input voltage V IN  to be converted is applied to an input of each comparator. The other input of each comparator receives a reference voltage which is obtained by application of a reference voltage to the terminals of the series connection of several resistances. When all resistances are equal, an arithmetical progression of reference voltages is obtained, the difference of the reference voltages being equal to V REF  /2 n , where n is the number of resolution bits for which the converter is designed. The various reference voltages have a rank number 1, 2, . . . , i, 2 n-1 , 2 n  and thus constitute a series according to V REF  /2 n , 2 V REF  /2 n , 3 V REF  /2 n  . . . V REF , the latter voltages being used only for indicating an overshoot bit. The outputs of the comparators are connected to the inputs of a logic encoding device (COD) which supplies an n-bit digital signal to the next output in an arbitrary code which may be, for example a Gray code. The structure of the encoding device depends on the required code, but is not described herein because the encoding device actually does not form a part of the present invention. A memory (MEMO) may be coupled to the output of the encoding device in order to save the information of the encoding device for at least a part of the clock period, thus enabling synchronization of the comparators. The clock signal required for the comparator and the memories is supplied by an external circuit. These circuits may be integrated on the same semiconductor substrate. 
     When the described comparator is realized by means of gallium arsenide Schottky transistors, the voltages V IN , V REF  are valued between ground and half the level of the positive supply voltage V DD , that is to say in the order of 1 V. 
     The threshold voltages of the transistors are V T  =0.1 V. 
     The d.c. supply voltages are: 
     for the first: V DD  =2 V 
     for the second: ground 
     for the third V B  =0.5 V, if any. 
     The lengths of the gate electrodes 1, the widths of the gate electrodes L g  and the values of the resistances R are stated in the following table. 
     
                       TABLE I                                                     
______________________________________                                    
Transistors                                                               
           1 in μm                                                     
                     Lg     Resistances                                   
                                      Value                               
______________________________________                                    
T.sub.1, T.sub.2                                                          
           50        1      R.sub.1,R.sub.2,R&#39;.sub.1,R&#39;.sub.2             
                                      2.7 kQ                              
T.sub.3,T.sub.13,T.sub.14                                                 
T.sub.21,T.sub.22,T.sub.23,T.sub.24                                       
           30        0.7    R.sub.11, R.sub.12                            
                                      10 kQ                               
T.sub.5,T.sub.6,T.sub.7,T.sub.8                                           
           20        0.7    R.sub.13, R.sub.14                            
                                      2.5 kQ                              
T.sub.11, T.sub.12                                                        
           10        0.7    R.sub.21, R.sub.22                            
                                      2 kQ                                
______________________________________