Digital GMSK modulator with non-integer bit interval handling
This is a continuation of application Ser. No. 07/278,080, filed Nov. 30, 1988 and now abandoned. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to radio frequency (RF) circuits, and, more particularly, to RF modulation circuits. 
     DESCRIPTION OF THE PRIOR ART 
     Gaussian Minimum Shift Keying (GMSK) modulation can be generated digitally by employing ROM (read only memory) look-up tables, or a combination of random logic and ROM look-up tables, using digital FIR (Finite Impulse Response) techniques. This is typically accomplished in an RF system by programming two ROMs with data to accommodate FIR filtering functions, one ROM programmed to produce the I channel component and the second ROM programmed to produce the Q channel component of the baseband GMSK signal. FIG. 1 illustrates this known approach. For more details on this modulation technique, reference may be made to H. Suzuki et al., &#34;Single-Chip Baseband Waveform Generator CMOS-LSI for Quadrature-Type GMSK Modulator,&#34; Electronic Letters, 11 Oct. 1984, Vol. 20, No. 21, pp. 875-876, which discloses a diagram representative of that shown herein in FIG. 1. Additional background information of frequency shift keying, e.g., MSK or GMSK, modulation/demodulation systems may be obtained by referencing U.S. Pat. Nos. 4,606,051--Crabtree; 4,414,675--Comroe; and 4,581,749--Carney et al., all of which are assigned to Motorola, Inc. Reference may also be made to M. Simon and C. Wang, &#34;Bit Synchronization of Differentially Detected MSK and GMSK,&#34; IEEE International Conference on Communications, June 1985, pp. 583-590; and K. Murota and K. Hirade, &#34;GMSK Modulation for Digital Mobile Radio Telephony,&#34; IEEE Transactions on Communications, Vol. COM-29, No. 7, Jul., 1981, pp. 1044-1050. For information on digital phase modulation techniques using ROMs, reference may be made to John B. Anderson, Tor Aulin and Carl-Erik Sundberg, &#34;Digital Phase Modulation,&#34; Plenum Press, New York, N.Y., 1986, pp. 211-235. 
     Such a technique works well with data being clocked out regularly on one bit intervals. However, there are times when the data has to be clocked for an interval greater than one bit (e.g., 1.25 bit). This may occur, for example, in TDMA (time division multiple access) systems which has time slots which contain a non-integer number of bits. 
     Theoretically, such a requirement would not cause a splatter in the transmission frequency spectrum since the data rate is lowered at such irregular times. However, the fractional bit interval causes a phase discontinuity in the ROM look-up table output. For this reason, known systems using the approach of FIG. 1 cannot be employed to accommodate such a requirement. 
     OBJECTS OF THE INVENTION 
     It is therefore a general object of the present invention to provide a digital modulation technique which overcomes the above mentioned shortcomings. 
     It is a more specific object of the present invention to provide a digital modulation technique which provides digital GMSK or any digital frequency modulation with non-integer interval capability. 
     The present invention may briefly be described in terms of a preferred embodiment. Essentially, a modulation circuit is used in a modulation system substantially synchronized to a system clock. The system includes one or more ROMs, each ROM being preprogrammed as a look-up table for generating a representative digital waveform based on an input data stream and a clock signal. Each digital waveform is converted to an analog signal for subsequent radio frequency (RF) modulation. Each ROM is addressed by an interpolation counter controlled by the clock signal, by a data shift register receiving input data at a rate corresponding to the clock signal, and by a quadrant register, also receiving the input data, for specifying the phase of the data signal with respect to the clock signal. Additionally, an external signal indicates a time at which a non-integer phase modulation synchronization to the system clock is required, and in response to that signal, the address of the ROMs is adjusted in order to modify the phase of the data signal so that it is consistent with the system clock requirement. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS AND APPENDICES 
     FIG. 1 is a block diagram of a modulation arrangement known in the prior art; 
     FIG. 2 is a block diagram of a modulation arrangement, according to the present invention; 
     App. A is a C language program useful for generating the contents of the ROMs 210 and 212 of FIG. 2; 
     App. B is a state diagram representing the operation of the quadrant register 230 of FIG. 2; and 
     App. C is a state diagram representing the operation of the quarter bit register 240 of FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The arrangement disclosed in this specification is directed to GMSK signalling in an RF cellular radiotelephone communication system. More specifically, the instant invention is best used in a digitally generated GMSK signalling technique which allows data to be clocked into the signalling protocol at irregular non-integer intervals, e.g., at one quarter bit intervals. 
     FIG. 2 illustrates a general block diagram of an arrangement which embodies the instant invention. The arrangement of FIG. 2 is similar to the known arrangement of FIG. 1, but it includes an improvement to accommodate the signalling protocol at irregular non-integer intervals, as previously discussed. Common to both arrangements of FIGS. 1 and 2 are conventional 2048-byte ROMs 110/112 and 8192-byte ROMs 210/212, digital to analog (D/A) converters 114/116 and 214/216 such as a TDC1016 available from TWA, Inc., reconstruction filters 118/120 and 218/220 (preferably conventional Bessel low pass filters), interpolation counters 124 and 224 such as a conventional divide-by-N ripple counter, M-bit shift registers 126 and 226 having parallel data output, and quadrant registers 130 and 230 such as a conventional 2-bit up/down counter. Unique to the arrangement of FIG. 2 is a quarter-bit register 240, its associated 1/4 bit indicator 242 and data 243, its quadrant register output 244 and its ROM address outputs 246. 
     Preferably, a 2-bit up/down counter is used to implement the quarter-bit register 240. 
     The operation of the arrangement of FIG. 2 will now be discussed in block diagram form using references to conventional counters and shift registers to facilitate discussion. This discussion will be followed with a state operational discussion of the quadrant register 230 and the quarter bit register 240 for more specific explanation. 
     The I- and Q- channel ROMs 210 and 212 are preprogrammed with data using a C language program, attached as appendix A. This program provides the data for the ROMs to serve four functions: (1) a digital FIR (Finite Impulse Response) filter, (2) an integration process, (3) phase correlation for sine and cosine processing of the I- and Q- channel components of the input data, and (4) NRZ (nonreturn-to-zero) to impulse conversion. Because GMSK modulation can be generated digitally by a digital FIR (Finite Impulse Response) filter, the FIR function is incorporated into the preprogrammed ROM data to approximate the required Gaussian data filter with NRZ data input and the phase angle output. The phase angle output is then used in conjunction with a SIN (sine) and a COS (cosine) portion of the respective ROM look-up tables to generate the I- and Q- channel baseband components in digital form. 
     The D/A converters 214 and 216 are used to convert the data output from the ROMs 210 and 212 to the I- and Q- channel baseband components in analog form. Conventional reconstruction filters 218 and 220 are then employed before the quadrature modulation step. 
     The interpolation counter 224 provides the interpolation filtering (oversampling) control for the ROMs 210 and 212 by addressing the ROMs 210 and 212 using its counter outputs. The interpolation counter 224 is used to ease the reconstruction filter design for anti-aliasing and sinx/x correction. The interpolation counter 224 is driven by a clock signal 252 operating at a rate of N times C, where C is the clock rate at which data is to be transmitted through the system and N is determined so that there is an adequate number of samples to represent a bit. Functioning as a divide-by-N counter, the output of the interpolation counter 251 is a clock signal operating at rate C. This output is connected to the data shift register 226 to clock data 250 therein, and connected to data source circuitry (not shown) so as to provide the rate at which data is to be received by the data shift register 226. 
     The data shift register 226 receives the data 250 in serial form and provides address signals to the ROMs 210 and 212 according to the program attached in appendix A in order for the ROMs to provide its representation in I- and Q-channel component form. The length of the data shift register 226 is determined to be greater than or equal to the duration of the FIR impulse response. In the illustrated embodiment, the length of the data shift register 226 is 5 bits. 
     The quadrant register 230 receives the data shifted out of the data shift register 226, and is used to inform the ROMs 210 and 212 of the phase angle of the data 250 for the phase angle calculation in the integration process of the program of appendix A. Because the program integrates in conjunction with the phase angle calculation, the calculation result may go beyond 0 to 360 degrees. Since the GMSK may be viewed as a Gaussian data filter followed by an FSK (frequency shift key) modulator with a modulation index of 0.5, i.e., the phase change due to FSK is always plus or minus 90 degrees at the end of a bit interval, a 2 bit quadrant register is sufficient to represent 1 of the 4 possible quadrants as a result of the integration process. When the energy of a modulating bit ripples through the FIR, the quadrant register 230 is incremented or decremented accordingly and the ROM look-up table can be restarted with a new bit shifted in. 
     A non-integer bit (fractional-bit) register 240, a quarter bit register in the illustrated embodiment, is introduced to handle irregular (unpredicted or aperiodic with respect to the clock rate C) data synchronization. This may occur in systems which require resynchronization for access transmission, e.g., resynchronization to a system clock in a TDMA (time division multiple access) system. 
     The quarter bit register 240 handles such irregularity by adjusting the addresses of the ROMs which specify the phase of the data signal. More specifically, this is accomplished by coupling the data lead 243 to the up/down port of the counter used to implement the quarter bit register 240, by clocking and enabling the quarter bit register 240 only upon reception of an external quarter bit indicator 242, and by coupling the overflow bit 244 of the register 240 to the up/down port of the quadrant register 230. The 1/4 bit indicator 242 is coupled to the interpolation counter 224 in order to restart its counting process. The restarting of the counting process is necessary in systems which require resynchronization with the such irregular non-integer bit times. The output 246 of the quarter bit register 240 addresses the ROMs 210 and 212 according to the specification of the program of appendix A. 
     Using 1/4 bit incrementation as an example, a two bit register or counter may be used in the implemention of the quarter-bit register 240. 
     It should be noted that the data shift register 226 should contain all &#34;1&#34;s or all &#34;0&#34;s before the 1/4 bit indicator activates so that the FIR portion of the circuit is in a steady state mode. 
     Appendix B illustrates a state diagram of the quadrant register 230. There are four states which represent this operation and 3 conditions to which the states react. Each state represents a steady state condition of the quadrant register 230. Condition &#34;A&#34; occurs when the output of the data shift register is high and the interpolation counter 224 has reached 15 (counting from 0 to 15); or the output of the data shift register is high and the outputs of the quarter bit register 240 represent &#34;3&#34; (highest count from 0 to 3 of a 2 bit counter) and the 1/4 bit indicator 242 is high. Condition &#34;B&#34; occurs when the output of the data shift register is low and the interpolation counter 224 has reached 15 (counting from 0 to 15); or the output of the data shift register is low and the outputs of the quarter bit register 240 represent &#34;0&#34; (lowest count from 0 to 3 of a 2 bit counter) and the 1/4 bit indicator 242 is high. The &#34;else&#34; condition represents all other conditions. 
     Appendix C illustrates a state diagram of the quarter bit register 240. There are four states which represent this operation and 3 conditions to which the states react. Each state represents a steady state condition of the quarter bit register 240. Condition &#34;A&#34; occurs when the output of the data shift register is high and the 1/4 bit indicator 242 is high. Condition &#34;B&#34; occurs when the output of the data shift register is low and the 1/4 bit indicator 242 is high. The &#34;else&#34; condition represents all other conditions. ##SPC1##