Data bus arrangement with improved speed and timing
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a microcomputer and more specifically to a data bus arrangement which improves the speed with which data can be moved within the system. 
     2. Description of the Prior Art 
     Currently-used microcomputers inevitably include on a single silicon chip, a central processing unit CPU, a read only memory ROM, a random access memory RAM, an input output interface I/O, and a timer or clock circuit. 
     The CPU of such devices includes a register, an arithmetical unit (ALU), and an internal data bus which is used to transfer data between the two. These devices further include an external data bus which is used in conjunction with the internal bus to move data to peripheral circuits. 
     FIG. 1 shows an example of how the currently-used prior art devices have managed the movement of data. 
     Data from the internal register of the CPU is inputted to the ALU and subsequently processed. The result is latched in a temporary register. This data is then transferred to the internal data bus, latched in an output data latch and outputted therefrom to the external data bus. The data appearing on the output terminal of the chip is transferred into a memory located eternally of the chip on which the CPU and ALU are formed. 
     FIG. 2 depicts the number of bus cycles required to achieve the above mentioned data transfer. In the first half of the first bus cycle (nth bus cycle) data from the internal register is inputted to the ALU. In the latter half of the same cycle, data is processed and, at the same time, the internal bus is precharged. During the first half of the next cycle (viz., the n+1 cycle) the temporary charge is stored by temporarily latching the same. During the second half of this cycle, data is outputted to the external bus, and in the first half of the n+2 cycle, the data is written into an external memory. 
     Thus, as will be clear, there is a full bus cycle between the one in which data is inputted to the ALU and the one in which data from the CPU is actually written into memory. In this case, the result from the ALU is determined during the first half of the n+1 cycle but even though the processing is complete a total of three full bus cycles are required to transfer the data. 
     In addition to the above, the currently used devices have included circuit arrangements such as shown in FIG. 3. In this figure, numeral 1a denotes a ROM, and numerals 2a, 2b, 2c and 2d denote internal function registers which act as a program counter, a common use register, a stack pointer, an accumulator, and a program status word, respectively. These internal function registers 2a-2d are connected by way of an internal data bus 3, a data buffer 4, and an external bus 5 to a peripheral function register 6. 
     The data contained in these internal function registers 2a-2d is transferred to the peripheral function register 6 through the above mentioned internal bus 3, the data buffer 4 and the external bus 5, while in the reverse instance the data in the peripheral function register is supplied via the same path. 
     However, with this type of arrangement, the rate at which the bus can actually move data is insufficiently high to meet high speed processing requirements and hampers the attainment of currently required data speed handling and management targets. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a system which enables increased data transfer speed using simple hardware arrangements. 
     In brief, to speed up data transfer, one embodiment of the invention features a transmission gate arrangement which pre-charges and transfers data in internal and external buses with the same timing and which further initializes the internal bus and a device such as an ALU, every bus cycle. A second embodiment speeds the data transfer in the buses per se by providing two data transfer paths through the interconnected buses and reducing the combined resistances of the internal and external buses on the order of 50%. 
     More specifically, a first aspect of the present invention is in the form of a microcomputer which comprises a CPU. The CPU includes a calculation unit and an internal bus. An external bus is operatively connected with the internal bus and a transmission gate means for pre-charging and transferring data into the internal bus and the external bus with the same timing, and for initializing the calculation unit and the internal bus on every bus cycle. 
     A second aspect of the invention is in the form of a microcomputer which features: a CPU, the CPU inluding a first register and an internal bus, the internal bus having first and second ends; an external bus having first and second ends, the first end being connected with the first end of the internal bus and the second end being connected with the second end of the internal bus; a second register operatively connected with the external bus; and transmission gate means for transferring data between the first and second registers via the internal and external buses. 
     A further aspect of the invention is in the form of a microcomputer which features: a CPU, the CPU including a ALU and an internal bus, the internal bus having first and second ends; an external bus, the external bus having first and second ends, the first end of the external bus being connected to the first end of the internal bus, and the second end of the internal bus being connected to the second end of the external bus; and transmission gate means for pre-charging and transferring data into the internal bus and the external bus with the same timing, and for initializing the ALU and the internal bus on every bus cycle. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The various features merits and advantages of the instant invention will become more clearly appreciated from a description of the preferred embodiments of the same, taken in conjunction with the appended drawings in which: 
     FIG. 1 is a block diagram depicting the operations performed by a prior art arrangement discussed in the opening paragraphs of the instant disclosure; 
     FIG. 2 is a timing chart showing the stages involved in moving data from a CPU to an external memory; 
     FIG. 3 is a circuit diagram showing a prior art circuit arrangement which has also been discussed in the opening paragraphs of the instant disclosure; 
     FIG. 4 is circuit diagram showing the arrangement which characterizes a first embodiment of the instant invention; 
     FIG. 5 is a timing chart showing the various signals which are produced and/or utilized during the operation of the circuit shown in FIG. 4; and 
     FIG. 6 is a circuit diagram of a second embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 4 shows a circuit arrangement which characterizes a first embodiment of the present invention. In this figure, the CPU internal bus 1 and the external data bus 2 are connected by a transmission gate formed of n-channel MOS-FET 3. This transmission gate 3 is connected to the output of an AND circuit 3a. One of the input terminals 3b of this AND circuit 3a is supplied with a control signal C1 which is produced by control circuit of the microcomputer which will be described hereinlater with reference to FIG. 2c, while the other input terminal is supplied with a bus cycle pulse signal Q0 of the nature shown in curve A in FIG. 5 and which is applied to the pulse cycle input terminal 8. 
     The external bus 2 is connected to a buffer circuit 5a which is connected to an output terminal 5. The internal and external buses 1 and 2 are respectively connected with precharge circuits 6 and 7 in a manner to be supplied with a precharge voltage VD. The precharge circuits 6 and 7 have input terminals 6a and 7a respectively which are supplied with control signals in form of a second bus cycle clock pulse signal Q2 of the nature shown in the curve B in FIG. 5. When this signal assumes a high level &#34;1&#34;, the internal and external data buses 1 and 2 precharge and assume a high level by way of example. 
     In the instant arrangement, the bus cycle pulses Q0 and Q2 are arranged to have the same period (viz, the same bus cycle time) and are arranged so that, as shown by curves A and B in FIG. 5, when one assumes a high level &#34;1&#34; the other assumes a low level &#34;0&#34; and vice versa. 
     The control signal C1, shown at curve C in FIG. 5, is arranged so that during the n-1th cycle, it assumes a high level at timing coincident with the leading edge of the Q0 signal and remains at a high level until the next leading edge of the Q0 signal appears in the nth cycle. Accordingly, signal C1 is such as to rise to a high level in every other bus cycle. 
     The internal bus 1 is connected to the ALU unit 4a by way of an n-channel MOS-FET 9. In this instance, the internal bus 1 is connected to the drain of the MOS-FET 9 while the source thereof is connected with the input terminal of the ALU. The gate of the MOS-FET 9 is connected to the output of an AND circuit 9a. One of the input terminals (viz., terminal 9b) of the AND circuit 9a is arranged to receive a control signal C2 of the nature shown at curve D in FIG. 5. The signal C2 is produced by the control circuit of the microcomputer. On the other hand, the other input terminal of the AND circuit 9a is arranged to receive the bus cycle clock pulse signal Q0 from the pulse cycle input terminal 8. 
     As shown by curve D in FIG. 5 the second control signal C2 is arranged to assume a low level when the signal C1 assumes a high level and vice versa. 
     Accordingly, the MOS-FET 9 is arranged to assume an ON state when the bus cycle clock pulse signal Q0 assumes a high level. 
     The ALU unit 4a is arranged so that an output terminal thereof is connected with one of the inputs of a NOR gate circuit 4b. The other input terminal of the NOR gate 4b is connected with a terminal 4c which is supplied with the second bus cycle clock pulse signal Q2. The output of the NOR gate 4b is connected with a drain of n-channel MOS-FET 4d. The source of this MOS-FET 4d is connected with the gate of a MOS-FET 10. Further, in the instant arrangement, the source of a MOS-FET 4d is connected with a drain of a MOS-FET 4e which forms part of the initialization circuit. The source of the MOS-FET 4e is grounded at 4g while the gate thereof is connected with the terminal 4c. 
     The node 4f which is defined between the MOS-FET 4d, MOS-FET 4e and MOS-FET 10 is such as to develop a low level &#34;0&#34; when the second bus cycle clock pulse signal Q2 assumes a high level &#34;1&#34;. 
     A terminal 4h associated with an inverter 4i is supplied with a fourth control signal C4. This signal is identical to signal C2 as shown in curve D in FIG. 5. This signal is supplied by way of inverter 4i to the drain of a n-channel MOS-FET 4j. The source of this MOS-FET 4j is connected by way of an inverter 41 to the gate of MOS-FET 4d. 
     The first bus cycle clock signal input terminal 8 is connected by way of an inverter 4k to the gate of the MOS-FET 4j. Accordingly, with this arrangement, the signal shown in curve E of FIG. 5 is produced. As shown, this signal is such as to assume a high level in the n-1th cycle until the occurrence of the trailing edge of signal Q0. The signal remains at a low level &#34;0&#34; until such time as the next trailing edge of the signal Q0 occurs just prior the end of the nth cycle. Following this, the signal remains at a high level &#34;1&#34; until such time as the next trailing edge of the signal Q0 occurs in the n+1 cycle. 
     The source of the MOS-FET 10 is grounded while the drain is connected to the source of n-channel MOS-FET 10a. The drain of the MOS-FET 10a is connected to the internal bus 1 while the gate thereof is connected with the output of an AND circuit 10b. One input of the AND circuit 10b is connected with an input terminal 10c which is adapted to receive a control signal C3 of the nature shown at curve C in FIG. 5. The other input of the AND gate 10b is connected to the terminal 8 so as to receive the first bus cycle clock signal Q0. With this arrangement, when signal Q0 assumes a high level &#34;1&#34;, the MOS-FET 10a is induced to assume an ON state. 
     As the remaining construction and arrangement of the circuit shown in FIG. 4 is essentially the same as found in conventional arrangements, a detailed explanation of the same will be omitted for brevity. 
     With the above described arrangement, during the first half of the nth bus cycle when signal Q2 assumes a high level &#34;1&#34;, the MOS- FET 4e is rendered ON and the signal appearing on node 4f assumes a low level. This causes the ALU to be initialized. Following this, in the last half of the nth cycle, while signal Q0 remains at high level &#34;1&#34;, the MOS-FET input gate 9 is maintained ON and during this period, the data in the internal register of the CPU (not shown) is inputted to the ALU. In addition to this, the MOS- FET 4d is conditioned to assume an ON state and the signal shown in curve E of FIG. 5 rises to a high level &#34;1&#34; until the leading edge of signal Q2 is produced in the n+1th cycle. This maintains the signal in question at a high level for a time To. In response to the signal Q2 assuming a low level &#34;0&#34; in the n+1th cycle, the result produced by the ALU is subject to a timing latching at node 4f. 
     Next, during the period To in the n+1th cycle the MOS-FET 4d is ON, and while the signal Q0 is at a high level &#34;1&#34; the MOS-FET 10a is rendered ON, so that the data indicative of the result of the ALU processing is transferred through the MOS-FET 10a, the internal bus 1, the transmission gate 3, the external bus 2 and the buffer circuit 5a to the output terminal 5. 
     While the bus cycle clock pulse signal Q2 is at a high level &#34;1&#34;, the node 4f is initialized via discharge. Viz., when the MOS-FET 4d transmission gate is ON, the signal appearing on the node 4f becomes &#34;0&#34; with the result that the adjacent MOS-FET 4d goes ON. This induces the signal appearing at the node 4f to either remain at a low level &#34;0&#34; or change from &#34;1&#34; to &#34;0&#34;. As a result, the MOS-FET 10a is ON and data is transferred to the data bus 1 before the outcome of the ALU processing, so that it is not required to pre-charge the internal data bus 1. 
     Accordingly, during the above mentioned n+1th bus cycle the data latched on the node 4f is directly transferred to the internal and external data buses 1 and 2 and driven to the output terminal 5, thus rendering it possible to achieve the required data management in two data bus cycles. This of course reduces the number of bus cycles required and enables the desired tasks to be achieved in a shorter time. Further, with the instant arrangement, as the internal and external data buses are subject to the same timing, and as data is being transferred it is not necessary to perform individual data input and output latches between the input and output buses, and it is possible to omit the pre-charging operations. This permits an advantageous simiplication in hardware. 
     FIG. 6 shows a second embodiment of the present invention. In this figure, for the sake of clarity, only a single register 2&#39; is illustrated. However, it is to be understood that this single unit is representative of devices such as a program counter, stack pointer, accumulator, and program password type registers. 
     As shown, the internal register is connected with an internal data bus 3&#39; and with the gate of a MOS-FET 9&#39;. The source of the MOS-FET 9&#39; is connected to the source of another MOS-FET 9a&#39;. The drain of the latter mentioned MOS-FET is connected to the internal data bus 3&#39; while the gate of the same is connected with a ROM in a manner to be supplied with a predetermined control signal. Viz., when the MOS-FET 9a is ON, the data in the internal register 2&#39; is supplied to the internal data bus 3&#39;. In this figure, the terminal 2i&#39; is arranged to function to receive a signal which indicates that data is to be written into the internal register 2&#39;. In this arrangement, the input terminal 2i&#39; is operatively connected with the ROM 1a&#39; in a manner to receive said predetermined signal. 
     In the instant arrangement, the internal data bus 3&#39; is provided with two transmission gates 7&#39; and 8&#39;. Both are formed of n-channel MOS-FET&#39;s. The drain of the gate 7&#39; and the source of the gate 8 is connected to the &#34;outboard portions&#34; of the internal bus 3&#39; while the source of gate 7&#39; is connected to the drain of gate 8&#39; through the portion of the bus extending therebetween. A peripheral function register 6&#39; is connected in parallel with an external bus 5&#39; in a manner to be operatively connected with the gates 7&#39; and 8&#39; in the illustrated manner. 
     The peripheral function register 6&#39; is provided with a terminal 6a&#39; which is adapted to receive a read control signal from the ROM. This device is also provided with a terminal 6b&#39; is adapted to receive a read out control signal. 
     It will be noted that in this drawing the internal and external data buses are illustrated by a single line, however, this is only for the sake of illustration. In an 8 bit type one chip microprocessor, these buses would in fact include 8 lines (16 lines in the case of a 16 bit machine and so forth. 
     In the instant arrangement in the case data is transferred from the internal register 2&#39; to the peripheral function register 6&#39; (the internal and external buses being previously precharged), the control ROM 1a&#39; outputs a control signal to the gate of the MOS-FET 9a&#39; which renders the same ON. Data from the internal function register 2&#39; is transferred to the internal bus 3&#39; via the gates 7&#39; and 8&#39; which are also rendered ON. From the internal bus 3&#39; the data enters the external bus 5&#39; and is transferred into the peripheral function register 6&#39; in the presence of a control signal from the control ROM 1a&#39; appearing on the terminal 6a&#39;. In this case, data from the internal register 2&#39; is supplied to the internal and external buses via two separate directions. 
     Given that the resistances of the two paths are R1 and R2 respectively, the resistance developed between the internal and peripheral registers 2&#39; and 6&#39; can be represented as follows: 
     
         R=R1×R2/R1+R2 . . .                                  (1) 
    
     Assuming that R1=R2 for the sake of explanation, it can be seen that the resistance of the arrangement shown in FIG. 6 is half that of an arrangement wherein data is transferred in one direction only. The same effect exists in the case data is transferred from the peripheral register 6&#39; to the internal one 2&#39;. 
     As will be appreciated this marked reduction in resistance enables data to be physically transferred with less resistance and therefore faster. The arrangement of the second embodiment of the present invention therefore enables data to be moved faster which in combination with the first embodiment which reduces the number of bus cycles necessary for any given data transfer. The combined effect is highly advantageous in promoting high speed processing by speeding up the rate with which data can be moved within the system.