Serial-parallel type analogue/digital converter
FIELD OF THE INVENTION 
     This invention relates to an analogue/digital (A/D) converter, and more particularly to, a serial-parallel type A/D converter for converting an analogue signal to a digital signal by serially combining plural bit groups obtained in a predetermined bit significant order. 
     BACKGROUND OF THE INVENTION 
     A first conventional serial-parallel type A/D converter comprises a recursive circuit consisting of a first sample holding circuit for sampling and holding an analogue signal, a 4-bit parallel A/D converter which converts the analogue signal to a 4-bit digital code number, a digital/analogue (D/A) converter which converts the 4-bit digital code number to an analogue signal, a subtracter which subtracts the converted analogue signal from the sampled analogue signal and amplifies the result of subtraction by four times, a second sample holding circuit for sampling and holding an output signal of the subtracter and amplifies the sampled signal by twice, and a switch which selectively connects inputs of the 4-bit parallel A/D converter and the first sample holding circuit with either an input terminal of the serial-parallel type A/D converter to which an original input analogue signal is supplied or an output of the second sample holding circuit. 
     In operation, in the first cycle, the switch connects terminals so that the input analogue signal is supplied to both the first sample holding circuit and the 4-bit parallel A/D converter. The sample holding circuit samples the input analogue signal to hold the sampled input signal for a predetermined period. The 4-bit parallel A/D converter converts the input analogue signal to a first 4-bit digital code number corresponding to first highest significant bits of the sampled input analogue signal. Then, the D/A converter converts the first 4-bit digital code number to an analogue signal which corresponds to the first highest significant bits of the sampled input analogue signal. Then, the subtracter subtracts the converted analogue signal form the the sampled input analogue signal and amplifies the result of subtraction by four times. The second sample holding circuit samples an output signal of the subtracter and amplifies the sampled output signal by twice and holds the amplified result for a predetermined period. As a result, the second sample holding circuit generates an output signal which is an amplified value by eight times of the result of subtraction of the analogue signal supplied by the D/A converter from the sampled input analogue signal. 
     Next, in the second to fourth cycles, the switch connects terminals so that an output of the second sample holding circuit is supplied to inputs of the first sample holding circuit and the 4-bit parallel A/D converter. Then, the same converting operation of the first cycle described above is carried out in the second to fourth cycles to obtain second to fourth 4-bit digital code numbers corresponding to second to fourth highest significant bits of the sampled input analogue signal, respectively. 
     By carrying out the converting operations of the first to fourth cycles described above, the first to fourth 4-bit digital code numbers respectively corresponding to the first to fourth highest significant bits of the input analogue signal can be obtained, provided that the four 4-bit digital code numbers overlap at the most and least significant bits of the adjacent code numbers by one bit, so that the resultant digital code number which corresponds to the original input analogue signal is a 13-bit digital code number in accordance with the bit combination of (4×4-3 bits). 
     A second conventional serial-parallel type A/D converter comprises first to third circuit blocks serially connected and a 4-bit parallel A/D converter serially connected to an output of the third circuit block. Each of the first to third circuit blocks comprises a first sample holding circuit which samples and holds an input analogue single, a 4-bit parallel A/D converter which converts the input analogue signal to a 4-bit digital code number, a D/A converter which converts the 4-bit digital code number to an analogue signal, a subtracter which subtracts the converted analogue signal from the sampled input analogue signal and amplifies the result of subtraction by four times, and a second sample holding circuit which samples an output of the subtracter and amplifies the sampled signal by twice and holds the amplified value. 
     Outputs of the first and second circuit blocks are respectively supplied to inputs of the second and third circuit blocks, and the output of the third circuit block is supplied to an input of the 4-bit parallel A/D converter. 
     In operation, the same converting operation as that in each cycle of the first conventional serial-parallel type A/D converter is carried out in each of the first to third circuit blocks sequentially, and first to fourth 4-bit digital code numbers respectively corresponding to first to fourth highest significant bits of the input analogue signal can be obtained in the first to third circuit blocks and the 4-bit A/D converter connected to the third circuit block, respectively, in pipe lining operation. Thus, a 13-bit digital signal is generated by the bit combination as described in the first conventional serial-parallel type A/D converter. 
     According to the first and second conventional serial-parallel type A/D converters, however, there are disadvantages as described after. 
     In the first conventional serial-parallel type A/D converter, the operation time for obtaining the 13-bit digital code number corresponding to the input analogue signal is relatively long, because the four cycles must be carried out to convert the input analogue signal to the digital code number. The operation time of one cycle depends on the precision of A/D conversion, so that it is difficult to shorten the converting operation time without reducing the precision of A/D conversion which is of 13 bits in the first conventional serial-parallel type A/D converter. 
     In the second conventional serial-parallel type A/D converter, the converting operation time is approximately one fourth of that in the first conventional serial-parallel type A/D converter, however, a chip area and a power consumption of the converter are four times of those of the first conventional serial-parallel type A/D converter. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the invention to provide a serial-parallel type A/D converter in which both converting operation time and power consumption thereof are reduced with the suppression of the chip area increase. 
     According to the invention, a serial-parallel type A/D converter comprises: 
     a first circuit block for converting an input analogue signal to a first digital code number consisting of first highest significant bits; 
     a second circuit block for converting an analogue signal, which is obtained by subtracting an analogue signal equal in value to the first digital code number from the input analogue signal, to second and later digital code numbers consisting of second and later highest significant bits, respectively, the second circuit block being a recursive circuit in which the converting is carried out for plural times at a timing faster than that of the first circuit block to obtain the second and later digital code numbers; 
     wherein the first and second circuit block operates in pipe lining to convert the input analogue signal to a digital signal obtained by combining the first, second and later highest significant bits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be explained in more detail in conjunction with appended drawings wherein: 
     FIG. 1 is a block diagram of a first conventional serial-parallel type A/D converter; 
     FIG. 2 is a block diagram of a second conventional serial-parallel type A/D converter; 
     FIG. 3 is a block diagram of a serial-parallel type A/D converter in a first preferred embodiment according to the invention; 
     FIG. 4 is a timing chart of operation in the serial-parallel type A/D converter in the first preferred embodiment according to the invention; and 
     FIG. 5 is a block diagram of a serial-parallel type A/D converter in a second preferred embodiment according to the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before describing a serial-parallel type A/D converters in preferred embodiments according to the invention, the conventional serial-parallel type A/D converters described before will be explained in conjunction with FIGS. 1 and 2. 
     FIG. 1 is a block diagram of a first conventional serial-parallel type A/D converter which is described in &#34;12-bit low consumption power CMOS recursive type serial-parallel type A/D converter IC&#34; of Electro Information Communication Society Technical Researching Report, ICD-116. 
     In the serial-parallel type A/D converter shown in FIG. 1, a reference numeral 11 denotes a first sample holding circuit 11, 12 a 4-bit parallel A/D converter, 13 a D/A converter, 14 a subtracter, 15 a second sample holding circuit, and 16 a switch. 
     The operation of the first conventional serial-parallel type A/D converter has been described before, so that the explanation thereof will not be carried out. 
     In this serial-parallel type A/D converter, it takes four cycles to convert an analogue signal to a 13-bit digital code number. If one period of one cycle is defined to be T s0 , the converting time becomes 4T s0 . The number of electric elements composing the converter is relatively small, so that the chip area for the converter is as narrow as approximately 3.9 mm 2 . The power consumption thereof is approximately 25 mW, and the converting speed thereof is 200 Ksample/sec (200 Ksps). Therefore, T s0  is calculated as follows. ##EQU1## 
     FIG. 2 is a block diagram of a second conventional serial-parallel type A/D converter which converts an analogue signal to a digital signal in pipe lining operation. 
     The second conventional serial-parallel A/D converter comprises first to third circuit blocks serially connected and a 4-bit parallel A/D converter 17 serially connected to an output of the third circuit block. Each of the first to third circuit blocks comprises a first sample holding circuit 11, a 4-bit parallel A/D converter 12, a D/A converter 13, a subtracter 14, and a second sample holding circuit 15. 
     In this serial-parallel type A/D converter, the converting speed thereof is as fast as approximately 800 Ksps, however, the chip area for the converter is as large as approximately 15 mm 2  and the power consumption thereof is approximately 100 mW, which are four times as those of the first conventional serial-parallel type A/D converter. 
     The precision which is needed for conversion is 13 bits in the first circuit block, 10 bits in the second circuit block, 7 bits in the third circuit block, and 4 bits in the 4-bit parallel A/D converter 17 corresponding to the fourth block. However, the converting time depends on the largest precision among the circuit blocks, that is 13 bits in the first circuit block, so that the second and later circuit blocks have precision characteristics more than needed. 
     FIG. 3 is a block diagram of a serial-parallel A/D converter in a first preferred embodiment. The serial-parallel type A/D converter comprises first and second circuit blocks which are connected each other in serial. 
     The first circuit block comprises a first sample holding circuit 21 which samples an input analogue signal and holds the sampled analogue signal, a 4-bit parallel A/D converter 22 which converts the input analogue signal to a 4-bit digital code number, a D/A converter 23 which converts the 4-bit digital code number to an analogue signal, a subtracter 24 which subtracts the converted analogue signal from the sampled input analogue signal and amplifies the result of subtraction by four times, and a second sample holding circuit 25 which samples an output of the subtracter 24 and amplifies the sampled signal by twice and holds the result of the amplified value. 
     The second circuit block comprises a first sample holding circuit 31 which samples an input analogue signal and holds the sampled analogue signal, a 4-bit parallel A/D converter 32 which converts the input analogue signal to a 4-bit digital code number, a D/A converter 33 which converts the 4-bit digital code number to an analogue signal, a subtracter 34 which subtracts the converted analogue signal from the sampled input analogue signal and amplifies the result of subtraction by four times, a second sample holding circuit 35 which samples an output of the subtracter 34 and increases the sampled output by twice and holds the result of the amplified value, and a switch 36 which selectively connects a terminal A which is connected to both inputs of the first sample holding circuit 21 and the 4-bit parallel A/D converter 32 with either a terminal B which is connected to an output of the second sample holding circuit 25 of the first circuit block or a terminal C which is connected to an output of the second sample holding circuit 35 of the second circuit block. 
     In this serial-parallel type A/D converter, the relation between one cycle periods T 1  and T 2  in the first and second circuit blocks is as follows. 
     
         T.sub.1 =mT.sub.2 (m is an integer over 1) 
    
     FIG. 4 is a timing chart of operation in the serial-parallel A/D converter in the first preferred embodiment. Here, it is supposed that m=3. 
     In operation, in the first circuit block, the first sample holding circuit 21 becomes a sampling state at the time t 00  for sampling the input analogue signal until the time t 10  at which it samples the input analogue signal to obtain a sampled input analogue signal D 0 . After sampling, the first sample holding circuit 21 holds the sampled input analogue signal D 0  during the period t 10  to t 20 . Then, the first sample holding circuit 21 becomes a sampling state again at the time t 20  for sampling the input analogue signal D 1  as a next sample until the time t 30 . In such a manner, the first sample holing circuit 21 becomes sampling and holding states alternately at the times t 00 , t 10 , t 20 , . . . . 
     The 4-bit parallel A/D converter 22 converts the input analogue signal D 0  to a first 4-bit digital code number corresponding to a first highest significant bits of the input analogue signal D 0 . Then, the D/A converter 23 converts the first 4-bit digital code number supplied from the 4-bit parallel A/D converter 22 to a first analogue signal which corresponds to the first highest significant bits of the input analogue signal D 0 . Then, the subtracter 24 subtracts the first analogue signal from the the sampled input analogue signal D 0  and amplifies the result of subtraction by four times. These operations of the 4-bit parallel A/D converter 22, the D/A converter 23 and the subtracter 24 finish by the time t 20 . 
     The second sample holding circuit 25 becomes a sampling state at the time t 10  for sampling an output signal of the subtracter 24 until it samples the output signal at the time t 20 , and amplifies the sampled signal by twice and holds the result of the amplified signal until the time t 30 . Then, the second sample holding circuit 25 becomes a sampling state at the time t 30  for sampling an output signal of the subtracter 24 as a next sample. In such a manner, the sample holing circuit 25 becomes sampling and holding states alternately at the times t 00 , t 10 , t 20 , . . . . 
     As a result, the second sample holding circuit 25 supplies the terminal B with an output signal which is a value amplified by eight times of the result of subtraction of the first analogue signal supplied by the D/A converter 23. 
     In the second circuit block, the switch 36 connects the terminal A with the terminal B to receive the output signal from the terminal B. The sample holding circuit 31 becomes a sampling state at the time t 21  for sampling the output signal of the second sample holding circuit 25 until at the time t 30  at which it samples the output signal. After sampling, the first sample holding circuit 31 holds the sampled output signal during the period t 30  to t 31 . Then, the first sample holding circuit 21 becomes a sampling state again at the time t 20  for sampling the input analogue signal as a next sample until the time t 30 . 
     The 4-bit parallel A/D converter 32 converts the sampled output signal of the second sample holding circuit 25 to a second 4-bit digital code number corresponding to a second highest significant bits of the input analogue signal. Then, the D/A converter 33 converts the second 4-bit digital code number N 2  (D 0 ) supplied from the 4-bit parallel A/D converter 32 to a second analogue signal which corresponds to the second highest significant bits of the input analogue signal D 0 . Then, the subtracter 34 subtracts the second analogue signal from the the sampled output signal of the sample holding circuit 25 and amplifies the result of subtraction by four times. These operations of the 4-bit parallel A/D converter 32, the D/A converter 33 and the subtracter 34 finish by the time t 31 . 
     The second sample holding circuit 35 becomes a sampling state at the time t 30  for sampling an output signal of the subtracter 34, and amplifies the sampled signal by twice and holds the amplified value until at the time t 32 , and supplies the terminal A with an output signal which is a signal amplified by eight times of the result of subtraction of the second analogue signal supplied by the D/A converter 33 from the sampled output signal of the sample holding circuit 25, after the switch 36 connects the terminal A with the terminal C. And, the second and third cycles of converting operation for obtaining third and fourth 4-bit digital code numbers corresponding to third and fourth highest significant bits of the input analogue signal are carried out. In short, the input analogue signal D 0  is held by the first sample holding circuit 21, and is simultaneously converted to provide the first 4-bit code number by the 4-bit parallel A/D converter 22. The first 4-bit code number is converted to provide the first analogue signal by the D/A converter 23, and the subtraction is carried out between the held analogue signal D 0  and the first analogue signal. This subtraction is indicated by N(D 0 ), and the subtracted result is indicated by N 00 . The subtracted result N 00  is held by the first sample holding circuit 31 in the second circuit block, and is simultaneously converted to provide the second 4-bit code number by the 4-bit parallel A/D converter 32. The second 4-bit code number is converted to provide the second analogue signal by the D/A converter 33, and the subtraction is carried out between the held analogue signal N 00  and the second analogue signal. This subtraction is indicated by N(N 00 ), and the subtracted result is indicated by N 01 . The subtracted result N 01  is held in the second circuit block by the second sample holding circuit 35, and is simultaneously converted to provide the third 4-bit code number by the 4-bit parallel A/D converter 32. The third 4-bit code number is converted to provide the third analogue signal by the D/A converter 33, and subtraction is carried out between the held analogue signal N 01  and the third analogue signal. This subtraction is indicated by N(N 01 ), and the subtracted result is indicated by N 02 . The subtracted result N 02  is held by the second sample holding circuit 35, and is simultaneously converted to provide the fourth 4-bit code number by the 4-bit parallel A/D converter 32. Although the fourth 4-bit code number is converted to provide the fourth analogue signal by the D/A converter 33, and the subtraction N(N 02 ) is carried out to provide the result N 03 , these operations are no longer necessary. The first to fourth 4-bit code numbers are combined to provide a 13-bit digital signal, as described before. 
     In the serial-parallel type A/D converter, the operation is carried out in pipe lining way through the first and second circuit blocks, so that the A/D conversion operation time of the input analogue signal to a 13-bit digital code number depends on the converting operation times in either the first or second circuit block. 
     In practical operation, the relation between the converting periods T s1  and T s2  in the first and second circuit blocks is as follows, as clearly shown in FIG. 4. 
     
         T.sub.s1 =3T.sub.s2 
    
     The first circuit block needs the precision of A/D conversion equal to 13 bits. The 13-bit precision corresponds to: 
     
         (1/2)·(1/2.sup.13)=0.0061% 
    
     If the first circuit block consists of a circuit realized by the same technical level, T s1  becomes as follows. 
     
         T.sub.s1 =T.sub.s0 =1.25 μs 
    
     However, the second circuit block needs the precision of A/D conversion equal to 10 bits. The 10-bit precision corresponds to: 
     
         (1/2)·(1/2.sup.10)=0.049% 
    
     Therefore, the precision needed in the second circuit block is one eighth of that needed in the first circuit block, so that the converting period can be set to T s2  in the second circuit block to be equal to or below (1/3)·T s1 . In this embodiment, T s2  is set as follows. 
     
         T.sub.s2 ≦(1/3)·(1.25) μs=0.417 μs 
    
     It will be confirmed by &#34;P5-271 of Spring Term National Conference Report in Electro Information Communication Society, 1989&#34;. 
     Consequently, the converting time in the serial-parallel type A/D converter in the first preferred embodiment becomes one fourth of that in the first conventional serial-parallel type A/D converter, although the consumption power and the chip area thereof becomes up to twice. 
     FIG. 5 is a block diagram of a serial-parallel A/D converter in a second preferred embodiment. The basic structure of the serial-parallel A/D converter in the second preferred embodiment is the same as that in the first preferred embodiment, except that the sample holding circuits 25 and 35 in the first preferred embodiment is replaced by a sample holding circuit 37 in the second preferred embodiment. The number of electric elements composing the serial-parallel type A/D converter in the second preferred embodiment is reduced as compared with that in the first preferred embodiment, so that the operation time becomes shorter as compared with that in the first preferred embodiment. 
     In other preferred embodiment, the sample holding circuit 21 in FIG. 3 or FIG. 5 may be located just after the input terminal 10. 
     Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to thus limited and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.