Switching circuit having constant impedance regardless switching operation thereof
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a switching circuit, more particularly, to a switching circuit used for a measurement apparatus, a phase shifter, or a phased array system. Furthermore, the present invention also relates to a single pole double throw switch having two switching circuits used for a transceiver, and the like. 
     2. Description of the Related Art 
     Recently, a switching circuit is used in various apparatuses or systems, and a loss of signal transfer must be decreased regardless of the insertion of a switching circuit thereto. Note, when applying the switching circuit to an objective circuit, an impedance of the switching circuit must be matched with that of the objective circuit in order to decrease the loss of signal transfer. Namely, a characteristic impedance of the switching circuit must be matched with internal impedances of circuits connected to an input terminal and an output terminal of the switching circuit regardless of the ON or OFF state of the switching circuit. 
     For example, the prior art switching circuit comprises a first switching portion and a second switching portion. The first switching portion includes two FETs (Field Effect Transistors) connected in series between an input terminal and the second switching portion, and the second switching portion includes an FET and a resistor connected in series between a transmission line and the ground GND. Note, a first control signal is supplied to gate electrodes of the two FETs of the first switching portion, a second control signal is supplied to a gate electrode of the FET of the second switching portion, and the first control signal and the second control signal are complementary signals. 
     In this prior art switching circuit, a switching operation is carried out by the FETs of the first switching portion, and an impedance matching operation is carried out by the FET of the second switching portion. However, in the first switching portion of the switching circuit, two FETs are connected in series, and thus a loss of signal transfer becomes large by resistance components (resistive components) of the FETs. 
     Note, in the prior art, another switching circuit has been provided. For example, Japanese Unexamined Patent Publication (Kokai) NO. 1-264014 discloses a diode switching circuit. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a switching circuit for enabling to impedance-match with an objective circuit (for example, a measurement apparatus, a transceiver, a phased array system, and the like) regardless of the ON or OFF state of the switching circuit. It is another object of the present invention to provide a switching circuit having a small loss of signal transfer. It is still another object of the present invention to provide a single pole double throw switch having a small loss of signal transfer. 
     According to the present invention, there is provided a switching circuit, for controlling the transmission of signals by switching operation thereof, comprising: an input terminal, for receiving the signals; an output terminal, for outputting or not outputting the signals; a transmission line having a specific impedance value, connected to the input terminal, for transferring the signals; a first switching portion including a plurality of first transistors connected in parallel between the transmission line and the ground, for controlling the impedance between the transmission line and the ground in accordance with a first control signal supplied to a control electrode Of each of the first transistors; and a second switching portion including a second transistor and a resistor connected in parallel between the transmission line and the output terminal, for controlling the impedance between the transmission line and the output terminal in accordance with a second control signal supplied to a control electrode of the second transistor, wherein the first transistors and the second transistor are complementarily switched by the first and second control signals. 
     The first transistors and the second transistor may be the same conduction type field effect transistors, and the first and second control signals may be complementary signals. The signals inputting into the switching circuit may be microwave signals. The first switching portion may include a plurality of transistors and a plurality of impedance components of the transmission line, a length of the transmission line corresponding to a first impedance component connected to an input terminal may be the same length of the transmission line corresponding to a last impedance component connected to the second switching portion, and lengths of the transmission line corresponding to intermediate impedance components placed between the first and last impedance components may be specified to the same. 
     The length of the transmission line corresponding to each of the first and last impedance components may be shorter than the length of the transmission line corresponding to each of the intermediate impedance components placed between the first and last impedance components. The length of the transmission line corresponding to each of the first and last impedance components may be specified as a half length of the transmission line corresponding to each of the intermediate impedance components placed between the first and last impedance components. A gate width of each of the first transistors may be shorter than a gate width of the second transistor, further, gate width of each of the first transistors may be specified as a half length of the second transistor. The transmission line may be a microstrip line. 
     According to the present invention, there is also provided a single pole double throw switch, including two switching circuits, for selecting one of the two switching circuits for transferring signals through the selected one switching circuit, wherein each of the two switching circuits comprises: an input terminal, for receiving the signals; an output terminal, for outputting or not outputting the signals; a transmission line having a specific impedance value, connected to the input terminal, for transferring the signals; a first switching portion including a plurality of first transistors connected in parallel between the transmission line and the ground, for controlling the impedance between the transmission line and the ground in accordance with a first control signal supplied to a control electrode of each of the first transistors; and a second switching portion including a second transistor and a resistor connected in parallel between the transmission line and the output terminal, for controlling the impedance between the transmission line and the output terminal in accordance with a second control signal supplied to a control electrode of the second transistor, wherein the first transistors and the second transistor are complementarily switched by the first and second control signals. 
     The input terminal of each of the two switching circuits may be the same, and a third transistor may be inserted in series between the input terminal and the transmission line in each of the two switching circuit. The first transistors, the second transistor, and the third transistor may be the same conduction type field effect transistors, and the first and second control signals may be complementary signals. The signals inputting into the single pole double throw switch may be microwave signals. A gate width of each of the first transistors may be shorter than a gate width of the second transistor, and further, the gate width of each of the first transistors may be specified as a half length of the second transistor. The transmission line may be a microstrip line. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description of the preferred embodiments as set forth below with reference to the accompanying drawings, wherein: 
     FIG. 1 is a circuit diagram indicating an example of a switching circuit according to the prior art; 
     FIG. 2 is a circuit diagram indicating an example of a switching circuit according to the related art; 
     FIG. 3A is a circuit diagram indicating a modified example of the switching circuit shown in FIG. 2; 
     FIGS. 3B and 3C are equivalent circuit diagrams indicating switching ON and OFF states of the switching circuit shown in FIG. 3A; 
     FIG. 4 is a circuit diagram indicating an embodiment of a switching circuit according to the present invention; 
     FIG. 5A is a circuit diagram indicating a modified embodiment of the switching circuit shown in FIG. 4; 
     FIGS. 5B and 5C are equivalent circuit diagrams indicating switching ON and OFF states of the switching circuit shown in FIG. 5A; 
     FIG. 6 is a diagram indicating relationships between an insertion loss and a frequency in the switching circuits according to the related art and the present invention; 
     FIG. 7 is a diagram indicating relationships between an isolation and a frequency in the switching circuits according to the related art and the present invention; 
     FIG. 8 is a diagram indicating relationships between a return loss and a frequency in the switching circuits according to the related art and the present invention; 
     FIG. 9 is a circuit diagram indicating an embodiment of a single pole double throw switch according to the present invention; and 
     FIG. 10 is a diagram indicating a pattern of the single pole double throw switch shown in FIG. 9. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First, switching circuits according to the prior art and the related art will be explained with reference to FIGS. 1, 2, and 3A to 3C. 
     FIG. 1 is a circuit diagram indicating an example of a switching circuit according to the prior art. In FIG. 1, reference numeral 101 denotes a first switching portion, 102 denotes a transmission line, and 103 denotes a second switching portion. Further, reference IN denotes an input terminal of the switching circuit, OUT denotes an output terminal of the switching circuit, Q 01 , Q 02 , and Q 03  denote FETs (Field Effect Transistors), and R 03  denotes a resistor. 
     As shown in FIG. 1, the first switching portion 101 includes two FETs Q 01  and Q 02  connected in series between the input terminal IN and the second switching portion 103, and the second switching portion 103 includes the FET Q 03  and the resistor R 03  connected in series between the transmission line 102 (or the output terminal OUT) and the ground GND. Note, as shown in FIG. 1, the transmission line 102, which may be a microstrip line, is provided between a source electrode of the FET Q 01  and a drain electrode of the FET Q 02  and provided between a source electrode of the FET Q 02  and the output terminal OUT. Further, a first control signal CS 01  is supplied to gate electrodes of the FETs Q 01  and Q 02 , a second control signal CS 02  is supplied to a gate electrode of the FET Q 03 , and the first control signal CS 01  and the second control signal CS 02  are complementary signals. 
     In this prior art switching circuit, a switching operation is carried out by the FETs Q 01  and Q 02  of the first switching portion 101, and an impedance matching operation is carried out by the FET Q 03  of the second switching portion. Concretely, in the case that the FETs Q 01 , Q 02  and Q 03  are N-channel type transistors, and when the first control signal CS 01  is specified to a high level and the second control signal CS 02  is specified to a low level, the FETs Q 01  and Q 02  are switched ON and the FET Q 03  is switched OFF, so that the input terminal IN is connected to the output terminal OUT through the FETs Q 01  and Q 02  and the transmission line 102 (which is a switching ON state of the switching circuit). Conversely, when the first control signal CS 01  is specified to a low level and the second control signal CS 02  is specified to a high level, the FETs Q 01  and Q 02  are switched OFF and the FET Q 03  is switched ON, so that the input terminal IN is disconnected from the output terminal OUT (which is a switching OFF state of the switching circuit). 
     Note, in the prior art switching circuit, a plurality of FETs (for example, two FETs Q 01  and Q 02 ) provided in the first switching portion 101 are used to decrease a leak current flowing through the drain electrode and the source electrode of each of the FETs when the FETs are switched OFF. 
     Generally, internal impedances of a measurement apparatus, a transceiver, a phased array system, and the like are specified to 50 Ω, and thus a switching circuit must be constituted such that a characteristic impedance of the switching circuit is specified to 50 Ω regardless of the ON or OFF state thereof. 
     First, when the switching circuit is at a switching ON state, the FETs Q 01  and Q 02  are switched ON, and the FET Q 03  is switched OFF, so that the second switching portion 103 is disconnected, or the resistor R 03  is not connected between the transmission line 102 and the ground GND. Therefore, an impedance of the switching circuit is determined by the first switching portion 101, and the impedance of the switching circuit is specified to 50 Ω. 
     Next, when the switching circuit is at a switching OFF state, the FETs Q 01  and Q 02  are switched OFF, and the FET Q 03  is switched ON, so that the first switching portion 101 is disconnected and the second switching portion 103 is connected. Namely, the resistor R 03  is connected between the transmission line 102 and the ground GND through the FET Q 03 , and an impedance of the switching circuit is determined by the second switching portion 101, or the resistor R 03 , so that the impedance of the switching circuit is specified to 50 Ω. 
     Consequently, the prior art switching circuit shown in FIG. 1 can be matched with the circuits (objective circuits) connected to the input terminal IN and the output terminal OUT, and a reflection of signal transfer can be prevented. 
     However, in the first switching portion 101 of the switching circuit shown in FIG. 1, a plurality of FETs (two FETs Q 01  and Q 02 ) are connected in series between the input terminal IN and the second switching portion 103 (or the output terminal OUT), and thus a loss of signal transfer becomes large by the resistance components of the FETs. This problem becomes greater in accordance with the number of the FETs provided in the first switching portion 101 for decreasing the leak current. 
     FIG. 2 is a circuit diagram indicating an example of a switching circuit according to the related art. In FIG. 2, reference numeral 101 &#39; denotes a first switching portion, 102 &#39; denotes a transmission line, and 103 &#39; denotes a second switching portion. Further, reference IN denotes an input terminal of the switching circuit, OUT denotes an output terminal of the switching circuit, Q 010 , Q 020 , and Q 03  denote FETs, and R 03  denotes a resistor. 
     As shown in FIG. 2, the first switching portion 101 &#39; includes two FETs Q 010  and Q 020  connected in parallel between the transmission line 102 &#39; and the ground GND, and the second switching portion 103 &#39; includes the FET Q 03  and the resistor R 03  connected in series between the transmission line 102 &#39; and the ground GMD. Mote, as shown in FIG. 2, references Z 01  and Z 02  denote impedance components of the transmission line 102&#39;, and the transmission line 102 &#39; (which may be a microstrip line) is provided between the input terminal IN and the output terminal OUT. Further, a control signal CS 03  is supplied to gate electrodes of all of the FETs Q 010 , Q 020 , and Q 03 . 
     In this related art switching circuit shown in FIG. 2, when the switching circuit is at a switching ON state, all of the FETs Q 010 , Q 020 , and Q 03  are switched OFF, or the FETs Q 010 , Q 020 , and Q 03  are disconnected, so that the input terminal IN and the output terminal OUT is directly connected by the transmission line 102&#39;, and the transmission line 102 &#39; is not connected to the ground through any FETs. Conversely, when the switching circuit is at a switching OFF state, all of the FETs Q 010 , Q 020 , and Q 03  are switched ON, and input signals supplied to the input terminal IN are reflected by the ON state FETs Q 010  and Q 020 . Note, impedances of the FETs Q 010  and Q 020  are sufficiently smaller than the impedance components Z 01  and Z 02  of the transmission line 102&#39;, so that the input signals are not transferred from the input terminal IN to the output terminal OUT. Further, an impedance of the output terminal OUT of the switching circuit is determined by the second switching portion. Namely, the impedance of the output terminal OUT of the switching circuit is determined by the resistor R 03  connected between the transmission line 102 &#39; and the ground GND through the FET Q 03 . 
     Note, in the related art switching circuit shown in FIG. 2, when the switching circuit is at a switching ON state, no FET is inserted in the transmission line 102&#39;, or no FET is inserted in series between the input terminal IN and the output terminal OUT, and thus a loss of signal transfer caused by the transmission line 102 &#39; becomes exceedingly small. Further, in the switching ON state, a characteristic impedance of the switching circuit can be determined by the impedance components Z 01  and Z 02  of the transmission line 102 &#39; and capacitance components (capacitive components) of the FETs Q 010 , Q 020 , and Q 03 . Nevertheless, in the switching OFF state, the first switching portion 101 &#39; is connected, or the FETs Q 010  and Q 020  are connected in parallel between the transmission line 102 &#39; and the ground GND. Namely, when FETs Q 010  and Q 020  are switched ON, a composite impedance (internal impedance) of the first switching portion 101 &#39; is exceedingly low, and a composite impedance (characteristic impedance of the switching circuit) of the second switching portion 103 &#39; cannot be specified to 50 Ω, so that an impedance matching between the switching circuit and an objective circuit (a measurement apparatus, a transceiver, a phased array system, and the like) cannot be realized. 
     FIG. 3A is a circuit diagram indicating a modified example of the switching circuit shown in FIG. 2, and FIGS. 3B and 3C are equivalent circuit diagrams indicating switching ON and OFF states of the switching circuit shown in FIG. 3A. 
     By comparing the switching circuit shown in FIG. 3A with that shown in FIG. 2, in the first switching portion 101 &#39; of the modified example shown in FIG. 3A, two impedance components (which are connected in series between the input terminal IN and the second switching portion 103&#39;) and one FET (which is connected between the transmission line 102 &#39; and the ground GND) are added to the configuration of the first switching portion shown in FIG. 2, and in the second switching portion 103 &#39; of the modified example, one FET (which is connected in series between the first switching portion 101 &#39; and the output terminal OUT) is added to the configuration of the second switching portion shown in FIG. 2. 
     As shown in FIG. 3A, the first switching portion 101 &#39; includes three FETs Q 011 , Q 012 , and Q 013  connected in parallel between the transmission line 102 &#39; and the ground GND, and the second switching portion 103 &#39; includes two FETs Q 031  and Q 032  and a resistor R 030 . Note, in the second switching portion 103&#39;, one FET Q 031  is connected between the first switching portion 101 &#39; and the output terminal OUT, and the other FET Q 032  and the resistor R 030  are connected in series between the transmission line 102 &#39; (or the output terminal OUT) and the ground GND. Further, as shown in FIG. 3A, references Z 010 , Z 011 , Z 012 , and Z 013  denote impedance components of the transmission line 102&#39;, and the transmission line 102 &#39; is provided between the input terminal IN and the output terminal OUT. In addition, a first control signal CS 04  is supplied to gate electrodes of the FETs Q 011 , Q 012 , Q 013 , and Q 032 , a second control signal CS 05  is supplied to a gate electrode of the FET Q 031  and the first control signal CS 04  and the second control signal CS 05  are complementary signals. 
     In this related art switching circuit, as shown in FIG. 3A, a resistance value of each of the impedance components Z 010 ,Z 011 ,Z 012 , Z 013  is, for example, specified to 80 Ω, a length of each of the transmission lines corresponding to the impedance components Z 010  and Z 013  is, for example, specified to 350 μm, and a length of each of the transmission lines corresponding to the impedance components Z 011  and Z 012  is, for example, specified to 700 μm. Note, a resistance value of the resistor R 030  is, for example, specified to 41 Ω. Further, each length of the transmission lines are determined above (350 μm or 700 μm), when the transmission lines (microstrip lines) are formed on a GaAs (Gallium Arsenic) substrate whose dielectric constant ε=13. 
     As shown in FIG. 3B, in this related art switching circuit, when the switching circuit is at a switching ON state, the FETs Q 011 , Q 012 , Q 013 , and Q 032  are switched OFF, and the FET Q 031  is switched ON. Note, each of the OFF state FETs Q 011 , Q 012 , Q 013 , Q 032  is regarded as a capacitor (C 011 , C 012 , C 013 , C 032 ), and the ON state FET Q 031  is regarded as a resistor (R 031 ). Note, a capacitance component C 011 , C 012 , C 013 , C 032  of each of the OFF state FETs Q 011 , Q 012 , Q 013 , Q 032  is, for example, specified to 0.12 of, and an inductive component L 011 , L 012 , L013 between the transmission line 102&#39; and the ground GND through each of the FETs Q 011 , Q 012 ,Q 013  p is, for example, specified to 50 pH. Similarly, an inductive component L 032  between the transmission line 102 &#39; (or output terminal OUT) and the ground GND through the FET Q 032  and the resistor R 030  is, for example, specified to 50 pH. Further, a resistance component R 031  of the ON state FET Q 031  is, for example, specified to 3.0 Ω. 
     Note, the relationship between an insertion loss and a frequency in this related art switching circuit is indicated by a broken line LL 62  in FIG. 6. 
     As shown in FIG. 3C, in this related art switching circuit, when the switching circuit is at a switching OFF state, the FETs Q 011 , Q 012 , Q 013 , and Q 032  are switched ON, and the FET Q 031  is switched OFF. Note, each of the ON state FETs Q 011 , Q 012 , Q 013 , Q 032  is regarded as a resistor (R 011 ,R 012 ,R 013 ,R 032 ), and the OFF state FET Q 031  is regarded as a capacitor (C 031 ) Further, a resistance component R 011 ,R 012 ,R 013 ,R 032  of each of the ON state FETs Q 011 , Q 012 , Q 013 , Q 032  is, for example, specified to 6 Ω, and a capacitance component C 031  of the OFF state FET Q 031  is, for example, specified to 0.12 of. In FIG. 3C, a resistance R 00  (47 Ω) is a combined resistance of the resistors R 030  (41 Ω) and R 032  (6 Ω ). 
     Note, the relationship between an isolation and a frequency in this related art switching circuit is indicated by a broken line LL 72  in FIG. 7, and the relationship between a return loss and a frequency in this related art switching circuit is indicated by a broken line LL 82  in FIG. 8. 
     Next, the preferred embodiments of a switching circuit and a single pole double throw switch according to the present invention will be explained below. 
     FIG. 4 is a circuit diagram indicating an embodiment of a switching circuit according to the present invention. In FIG. 4, reference numeral 1 denotes a first switching portion, 2 denotes a transmission line, and 3 denotes a second switching portion. Further, reference IN denotes an input terminal of the switching circuit, OUT denotes an output terminal of the switching circuit, Q 1 , Q 2 , and Q 3  denote FETs (Field Effect Transistors), and R denotes a resistor. Note, each of the FETs Q 1 , Q 2 , and Q 3  are, for example, formed by a junction type FET, a MOS (Metal Oxide Silicon) type FET, and the like. 
     As shown in FIG. 4, the first switching portion 1 includes two FETs Q 1  and Q 2  connected in parallel between the transmission line 2 and the ground GND, and the second switching portion 3 includes the FET Q 3  and the resistor R connected in parallel between the first switching portion 1 and the output terminal OUT. Note, as shown in FIG. 4, references Z 1  and Z 2  denote impedance components of the transmission line 2, and the transmission line 2 (which may be a microstrip line) is provided between the input terminal IN and the second switching portion 3. Further, a first control signal CS 1  is supplied to gate electrodes of the FETs Q 1  and Q 2 , and a second control signal CS 2  is supplied to a gate electrode of the FET Q 3 . Note, the first control signal CS 1  and the second control signal CS 2  are complementary signals, and thus the FETs Q 1 ,Q 2  of the first switching portion 1 and the FET Q 3  of the second switching portion 3 are complementarily switched. 
     In this switching circuit, in the case that the FETs Q 1 , Q 2  and Q 3  are N-channel type transistors, and when the first control signal CS 1  is specified to a low level and the second control signal CS 2  is specified to a high level, the FETs Q 1  and Q 2  are switched OFF and the FET Q 3  is switched ON, so that the input terminal IN is connected to the output terminal OUT through the transmission line 2 and the ON state FET Q 3  (which is a switching ON state of the switching circuit). Note, in this switching ON state of the switching circuit, an impedance of the switching circuit is mainly determined by the impedance components Z 1  and Z 2 , and thus a characteristic impedance of the switching circuit at the switching ON state can be defined by adjusting values of the impedance components Z 1  and Z 2 . 
     Conversely, when the first control signal CS 1  is specified to a high level and the second control signal CS 2  is specified to a low level, the FETs Q 1  and Q 2  are switched ON and the FET Q 3  is switched OFF, so that the input terminal IN is connected to the output terminal OUT through the resistor R (which is a switching OFF state of the switching circuit). Note, in this switching OFF state of the switching circuit, an impedance of the switching circuit is mainly determined by the resistor R, and thus a characteristic impedance of the switching circuit at the switching OFF state can be defined by adjusting a resistance value of the resistor R. 
     As described above, in this switching circuit shown in FIG. 4, the characteristic impedance of the switching circuit can be defined to an optional value (for example, 50 Ω) by adjusting the values of the impedance components Z 1 ,Z 2  and the resistor R, regardless of the ON or OFF state of the switching circuit. Consequently, when connecting the switching circuit of the present embodiment to an objective circuit (for example, a measurement apparatus, a transceiver, a phased array system, and the like), an impedance matching between the switching circuit and the objective circuit can be realized by both switching ON and OFF states of the switching circuit, so that the signals input from the input terminal IN are not reflected thereby. Furthermore, according to the present embodiment, no FET of the first switching portion 1 is inserted and only one transistor (FET Q 3 ) of the second switching portion 3 is inserted in the transmission line 2 (or between the input terminal IN and the output terminal OUT), and thus insertion loss of the switching circuit can be small. Note, in the above embodiment, the number of the FETs of the first switching portion 1 is not limited to two, but it can be formed as a plural. 
     FIG. 5A is a circuit diagram indicating a modified embodiment of the switching circuit shown in FIG. 4, and FIGS. 5B and 5C are equivalent circuit diagrams indicating switching ON and OFF states of the switching circuit shown in FIG. 5A. 
     By comparing the switching circuit shown in FIG. 5A with that shown in FIG. 4, in the first switching portion 1 of the modified example shown in FIG. 5A, two impedance components (which are connected in series between the input terminal IN and the second switching portion 3) and one FET (which is connected between the transmission line 2 and the ground GND) are added to the configuration of the first switching portion shown in FIG. 4, and the second switching portion 2 has the same configuration as shown in FIG. 4. 
     As shown in FIG. 5A, the first switching portion 1 includes three FETs Q 11 , Q 12 , and Q 13  connected in parallel between the transmission line 2 and the ground GND, and the second switching portion 3 includes an FET Q 3  and a resistor R. Note, in the second switching portion 3, the FET Q 3  and the resistor R are connected in parallel between the first switching portion 1 and the output terminal OUT. Further, as shown in FIG. 5A, references Z 10 , Z 11 , Z 12 , and Z 13  denote impedance components of the transmission line 2, and the transmission line 2 is provided between the input terminal IN and the second switching portion 3. Furthermore, the impedance components Z 10 , Z 11 , Z 12 , and Z 13  correspond to transmission line 2, or divided transmission lines. In addition, a first control signal CS 3  is supplied to gate electrodes of the FETs Q 11 , Q 12 , and Q 13 , second control signal CS 4  is supplied to a gate electrode of the FET Q 3  and the first control signal CS 3  and the second control signal CS 4  are complementary signals. Note, each of the FETs Q 11 , Q 12 , Q 13 , and Q 3  are, for example, formed by a junction type FET, a MOS (Metal Oxide Silicon) type FET, and the like. 
     In this switching circuit, as shown in FIG. 5A, a resistance value of each of the impedance components Z 10 , Z 11 , Z 12 , Z 13  is, for example, specified to 80 Ω, a length of each of the transmission lines corresponding to the impedance components Z 10  and Z 13  is, for example, specified to 350 μm, and a length of each of the transmission lines corresponding to the impedance components Z 11  and Z 12  is, for example, specified to 700 μm. Note, a resistance value of the resistor R is, for example, specified to 48 Ω. Further, each length of the transmission lines are determined above (350 μm or 700 μm), when the transmission lines (microstrip lines) are formed on a GaAs (Gallium Arsenic) substrate whose dielectric constant ε=13. 
     As shown in FIG. 5B, in this switching circuit, when the switching circuit is at a switching ON state, the FETs Q 11 , Q 12 , and Q 13  are switched OFF, and the FET Q 3  is switched ON. Note, each of the OFF state FETs Q 11 ,Q 12 ,Q 13  is regarded as a capacitor (C 11 ,C 12 ,C 13 ), and the ON state FET Q 3  is regarded as a resistor (R 0 ). Note, a capacitance component C 11 ,C 12 ,C 13  of each of the OFF state FETs Q 11 ,Q 12 ,Q 13  is, for example, specified to 0.12 pF, and an inductive component L 11 ,L 12 ,L 13  between the transmission line 2 and the ground GND through each of the FETs Q 11 ,Q 12 ,Q 13  is, for example, specified to 50 pH. Further, a resistance component R 3  of the ON state FET Q 3  is, for example, specified to 3.0 Ω, and thus a resistance value R 0 , which is combined by the resistor R (48 Ω) and the resistance component R 3  (3.0 Ω), is specified to 2.8 Ω. In the above description, the resistance component R 3  (which is a resistance value of the switched ON state FET Q 3 ) is smaller than that of each switched ON state FETs Q 11 ,Q 12 ,Q 13  in order to decrease an insertion loss of the switching circuit. Concretely, for example, a gate width of the FET Q 3  is formed longer than that of the FETs Q 11 ,Q 12 ,Q 13 . 
     Note, the relationship between an insertion loss and a frequency in this switching circuit is indicated by a solid line LL 61  in FIG. 6. 
     In the switching ON state of the above switching circuit, an impedance of the switching circuit is determined by the impedance components Z 10 , Z 11 , Z 12 , and Z 13 . Concretely, the resistance value of each of the impedance components Z 10 ,Z 11 ,Z 12 ,Z 13  is specified to 80 Ω, and the impedance characteristics of the switching circuit at the switching ON state can be matched with internal impedances of objective circuits connected to an input terminal IN and an output terminal OUT of the switching circuit. Further, in order to decrease reflections, or decrease standing waves, a length of each of the transmission lines (350 μm) corresponding to the impedance components Z 10  and Z 13  is formed as a half length of that of the transmission lines (700 μm) corresponding to the impedance components Z 11  and Z 12 . 
     As shown in FIG. 5C, in this switching circuit, when the switching circuit is at a switching OFF state, the FETs Q 11 ,Q 12 , and Q 13  are switched ON, and the FET Q 3  is switched OFF. Note, each of the ON state FETs Q 11 , Q 12 ,Q 13  is regarded as a resistor (R 11 ,R 12 ,R 13 ), and the OFF state FET Q 3  is regarded as a capacitor (C 3 ). Further, a resistance component R 11 ,R 12 ,R 13  of each of the ON state FETs Q 11 ,Q 12 ,Q 13  is, for example, specified to 6 Ω, and a capacitance component C 3  of the OFF state FET Q 3  is, for example, specified to 0.12 pF. 
     Note, the relationship between an isolation and a frequency in this switching circuit is indicated by a solid line LL 71  in FIG. 7, and the relationship between a return loss and a frequency in this switching circuit is indicated by a solid line LL 81  in FIG. 8. 
     In the switching OFF state of the above switching circuit, an impedance of the switching circuit is determined by the resistor R, the impedance components Z 10 ,Z 11 ,Z 12 ,Z 13 , and the resistor values of the switching ON state FETs Q 11 ,Q 12 ,Q 13  especially determined by a resistor value of the resistor R. Concretely, the resistor value of the resistor R is specified to 48 Ω, each of the resistor values of the switching ON state FETs Q 11 ,Q 12 ,Q 13  is specified to 6 Ω. and the resistance value of each of the impedance components Z 10 ,Z 11 ,Z 12 ,Z 13  is specified to 80 Ω, and the impedance characteristics of the switching circuit at the switching OFF state can be matched with internal impedances of objective circuits connected to an input terminal IN and an output terminal OUT of the switching circuit. Note, a characteristic impedance of the switching circuit at the switching OFF state can be defined by adjusting a resistance value of the resistor R. 
     As described above, in this switching circuit shown in FIG. 5A, the characteristic impedance of the switching circuit can be defined to a optional value (for example, 50 Ω) by adjusting the impedance components Z 10 ,Z 11 ,Z 12 ,Z 13  and the resistor R, regardless of the ON or OFF state of the switching circuit. 
     FIG. 6 is a diagram indicating relationships between an insertion loss and a frequency in the switching circuits according to the related art and the present invention, FIG. 7 is a diagram indicating relationships between an isolation and a frequency in the switching circuits according to the related art and the present invention, and FIG. 8 is a diagram indicating relationships between a return loss and a frequency in the switching circuits according to the related art and the present invention. In FIGS. 6 to 8 each solid line LL 61 ,LL 71 ,LL 81  indicates characteristic of the switching circuit according to the present invention, or the switching circuit shown in FIGS. 5A to 5C, and each broken line LL 62 ,LL 72 ,LL 82  indicates characteristic of the switching circuit according to the related art, or the switching circuit shown in FIGS. 3A to 3C, in the frequency range from 1 GHz to 10 GHz. 
     First, as shown in FIG. 6, in switching ON state of the switching circuit, insertion loss characteristics of the present invention are smaller (by absolute value) than that of the related art, and thus according to the present invention (embodiment shown in FIG. 5A), signals (microwave signals from 1 GHz to 10 GHz) can be transferred by small degree of insertion loss. Namely, an insertion loss of the present invention (with reference to the solid line LL 61 ) is determined at about -1 dB during 1 GHz to 10 GHz, and an insertion loss of the related art (with reference to the broken line LL 62 ) is determined from about -1.3 dB to -2.5 dB during 1 GHz to 10 GHz, and thus the insertion loss of the present invention is smaller than that of the related art in all frequency band. For example, when the frequency (signals) is specified to 6 GHz, an insertion loss of the present invention is determined at -1.0 dB and an insertion loss of the related art is determined at -2.4 dB, so that the insertion loss of the present invention is smaller by -1.4 dB than that of the related art. 
     Further, as shown in FIG. 7, in switching OFF state of the switching circuit, both isolation characteristics of the present invention and the related art are preferable. An isolation of the present invention (with reference to the solid line LL 71 ) is determined from about -50 dB to -27 dB during 1 GHz to 10 GHz, and an isolation of the related art (with reference to the broken line LL 72 ) is determined from about -50 dB to -37 dB during 1 GHz to 10 GHz. Namely, the isolation of the present invention is smaller (by absolute value) than that of the related art, but the isolation of the present invention is lower than -25 dB at 10 GHz, and thus the isolation characteristics of the present invention are sufficiently small and have no problem in the present invention. 
     Next, as shown in FIG. 8, in switching OFF state of the switching circuit, return loss characteristics of the present invention is larger (by absolute value) than that of the related art, and thus according to the present invention, reflections of the signals input into the switching circuit can be determined to small. Namely, a return loss of the present invention (with reference to the solid line LL 81 ) is determined from about -22 dB to -25 dB during 1 GHz to 10 GHz, and a return loss of the related art (with reference to the broken line LL 82 ) is determined from about -9.0 dB to -20 dB during 1 GHz to 10 GHz, and thus the return loss of the present invention is larger (by absolute value) than that of the related art in all frequency band. For example, when the frequency is specified to 6 GHz, a return loss of the present invention is determined at -25 dB and a return loss of the related art is determined at -11 dB, so that the reflected signals from the switching circuit can be smaller by -14 dB than that of the related art. Consequently, according to the present invention, reflections of the signals can be decreased. 
     FIG. 9 is a circuit diagram indicating an embodiment of a single pole double throw switch according to the present invention, and FIG. 10 is a diagram indicating a pattern of the single pole double throw switch shown in FIG. 9. 
     As shown in FIGS. 9 and 10, the single pole double throw switch (SPDT) includes two switching circuits 91, 92, and one of the two switching circuits 91, 92 is switched ON and the other of the two switching circuits 91, 92 is switched OFF. One switching circuit 91 comprises four FETs Q 101 , Q 111 , Q 121 , and Q 31 , a transmission line 21 (impedance components Z 101 , Z 111 , and Z 121 ), a resistor R 1 , and an output terminal OUT 1 . Similarly, the other switching circuit 92 comprises four FETs Q 102 , Q 112 , Q 122 , and Q 32 , a transmission line 22 (impedance components Z 102 , Z 112 , and Z 122 ), a resistor R 2 , and an output terminal OUT 2 . Note, a first control signal V G  is applied to gate electrodes of the FETs Q 101 , Q 31 , Q 112 , and Q 122 , and a second control signal V GB  is applied to gate electrodes of the FETs Q 102 , Q 32 , Q 111 , and Q.sub. 121. Further, the first control signal V G  and the second control signal V GB  are complementary signals. In addition, drain electrodes of the FETs Q 101  and Q 102  are connected to an input terminal IN through an impedance components Z 100  (transmission line, or a microstrip line). 
     By comparing the above SPDT with the switching circuit shown in FIG. 4, the FETs Q 111  and Q 112  correspond to the FET Q 1  of the first switching portion 1, the FETs Q 121  and Q 122  correspond to the FET Q 2  of the first switching portion 1 shown in FIG. 4, the FETs Q 31  and Q 32  correspond to the FET Q 3  of the second switching portion 3 shown in FIG. 4, and the resistor R 1  and R 2  correspond to the resistor R of the second switching portion 3 shown in FIG. 4, respectively. As shown in FIGS. 9 and 10, in the switching circuits 91 of the single pole double throw switch, a drain electrode of the FET Q 111  is connected to the input terminal IN through a transmission line corresponding to an impedance component Z 100 , an FET Q 101 , and a transmission line corresponding to an impedance component Z 101 . Similarly, in the switching circuits 92 of the single pole double throw switch, a drain electrode of the FET Q 112  is connected to the input terminal IN through the transmission line corresponding to the impedance component Z 100 , an FET Q 102 , and a transmission line corresponding to an impedance component Z 102 . 
     In the above described SPDT, all of the FETs Q 101 , Q 111 ,Q 121 ,Q 31 ,Q 102 ,Q 112 ,Q 122 ,Q 32 , are the same conduction type, and the first control signal V G  and the second control signal V GB  are complementary signals. Further, the single pole double throw switch shown in FIGS. 9 and 10 is used for switching microwave signals. 
     Note, a gate width of the FET Q 101  is formed as a half length of that of the FETs Q 111  and Q 121 , and a gate width of the FET Q 102  is formed as a half length of that of the FETs Q 112  and Q 122 . Further, a gate width of the FET Q 31  is formed as a double length of that of the FETs Q 111  and Q 121 , and a gate width of the FET Q 32  is formed as a double length of that of the FETs Q 112  and Q 122 , in order to decrease an insertion loss of the SPDT. In addition, the SPDT can be applied to a transceiver, a phased array system, and the like. 
     Many widely differing embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention, and it should be understood that the present invention is not limited to the specific embodiments described in this specification, except as defined in the appended claims.