Magnetic disk apparatus having a read/write control circuit
BACKGROUND OF THE INVENTION 
     The present invention relates to a magnetic disk apparatus having a read/write control circuit for reading and writing data from and to only valid data areas of a selected target data track by skipping void data areas, such as embedded servo areas and magnetically defective areas. 
     A magnetic disk apparatus is connected to an apparatus, such as a computer, via an interface control circuit. The magnetic disk apparatus includes a read/write control circuit having timing clock generating means to produce a read/write synchronization signal which is supplied to the interface control circuit and used for transmitting read and write data to and from the computer. More specifically, the interface control circuit sends the write data from the computer to the magnetic disk apparatus in synchronization with the read/write synchronization signal in a write mode. Further, the interface control circuit sends the read data from the magnetic disk apparatus to the computer in synchronization with the read/write synchronization signal in a read mode. 
     The magnetic disk apparatus has one or more magnetic disks. If the magnetic apparatus has a servo surface assigned on one surface of a plurality of magnetic disk surfaces, servo information read from the servo surface is used for generating the read/write synchronization signal. The other surfaces of the magnetic disks are data surfaces having a plurality of concentric data tracks divided into a plurality of sectors. 
     The data surfaces of the magnetic disks often have one or more magnetically defective areas in which data cannot be recorded. Further, if embedded servo areas are provided at leading portions of the sectors on the data surfaces, the embedded servo areas cannot be used to record data, either (the magnetically defective area and the embedded servo area are referred to as a void data area or void area). Therefore, it is necessary to prevent the data from being recorded in the void area, and not to treat the signal read from the void area as the read data. 
     A conventional read/write control circuit of a conventional magnetic apparatus always supplies the read/write synchronization signal to the interface control circuit even when the read or write operation is carried out to the void area. This means that the conventional magnetic apparatus has no means to discriminate the void area from the normal or valid data area. Therefore, the interface control circuit is required to discriminate the void area. 
     To this end, a control circuit for detecting faulty sectors including a void area is disclosed in U.S. Pat. No. 4,405,952. The control circuit stores the address of the faulty sectors in order to discriminate the faulty sectors from normal or valid sectors. If the read or write operation is to be carried out to the faulty sectors, i.e., if the address of one of the faulty sectors is designated, the control circuit changes the faulty sector address into an address of a replacement sector so that the data to be written into or read from the faulty sector is written to or read from the replacement sector. 
     The conventional manner described above has, however, a disadvantage in that an excessive time period is required to position a magnetic head to the replacement sector. Further, the length of a data unit (logical record) transferred between the computer and the disk apparatus is limited by the memory capacity of one sector. That is, the capacity of the logical record cannot be larger than the memory capacity of one sector. 
     SUMMARY OF THE INVENTION 
     Therefore, an object of the present invention is to provide a magnetic disk apparatus capable of skipping void areas during a read or write operation without the control of an interface control circuit. 
     Another object of the present invention is to provide a magnetic disk apparatus capable of skipping void areas without using replacement sectors. 
     Still another object of the present invention is to provide a magnetic disk apparatus capable of setting a length of logical record, which is a data unit transferred between the magnetic disk apparatus and an apparatus, such as a computer, to be an arbitrary length. 
     A magnetic disk apparatus according to the present invention comprises at least one magnetic disk including a data surface on which a plurality of concentric data tracks are provided, a data surface having a void area in which recording of user&#39;s data is inhibited; a magnetic head for reading and writing the user&#39;s data from and to the plurality of data tracks; positioning means for positioning the magnetic head at a target track selected from the plurality of concentric data tracks: detecting means for detecting a circumferential position of the magnetic head on the target track: means for storing a position and a length of the void area on the data surface; read/write control means for supplying a read signal read from the target track by the magnetic head to an interface circuit as the user&#39;s data, and for supplying the user&#39;s data from the interface circuit to the magnetic head as a write signal to write to the target track timing clock generating means for generating a read/write synchronization signal supplied to the interface circuit, the interface circuit receiving the user&#39;s data from the read/write control means in synchronization with the read/write synchronization signal and supplying the user&#39;s data to the read/write control means in synchronization with the read/write synchronization signal: and control means for preventing the transmission of the read/write synchronization signal during a time period corresponding to the length of the void area when the circumferential position of the magnetic head is equal to the position of the void area. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1(a)-1(d) and FIGS. 2(a)-2(c) are timing charts showing a principal function of the present invention. 
     FIG. 3 is a block diagram showing an embodiment of the present invention. 
     FIG. 4 is a block diagram showing a void area skipping control circuit used in the embodiment of the present invention shown in FIG. 3. 
     FIGS. 5(a)-5(p) are a timing chart showing an operation of the void area skipping control circuit shown in FIG. 4. 
     FIG. 6 is a block diagram showing a void pointer used in the void area skipping control circuit shown in FIG. 4. 
     FIGS. 7(a)-7(p) and 8(a)-8(q) are timing charts showing operations of the void area skipping control circuit shown in FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     At first, a principal function of a magnetic disk explained. 
     With reference to FIG. 1(a), data units (logical records) R1, R2 and R3 transferred between an apparatus, such as a computer, and magnetic disk apparatus can be selected to have an arbitrary length (D 0  to D 1 ) determined by the requirements of the computer or other apparatus of which the magnetic disk apparatus is a part, irrespective of existence of void areas on a target track. The following description assumes the magnetic disk apparatus is used in a computer. However, the invention disclosed herein is not limited to any specific apparatus with which a magnetic disk apparatus of the invention may be used. The magnetic disk apparatus controls the following physical recording procedure for the logical records R1, R2 and R3 depending on existence of void areas on the target track. 
     (1) The case where there is no void area on the target track. 
     As is shown in FIG. 1(b), physical records R1-1, R2-1 and R3-1 are recorded on the target track corresponding to the data units R1, R2 and R3. 
     (2) The case where there are regular void areas, such as data-surface-embedded servo areas on the target track. 
     As is shown in FIG. 1(c), physical records R1-2, R2-2 and R3-2 are recorded in the order of the logical records R1, R2 and R3 by skipping void areas. In this example, since there are the data-surface-embedded servo areas E on the target track at portions corresponding to the logical records R2 and R3, the physical record R2-2 corresponding to the logical record R2 is divided and recorded as two physical segments composed of the first length (D 0  to D i ) and the second length (D i+1  to D 1 ) in order to avoid the recording to the void area. Also, the physical record R3-2 corresponding to the logical record R3 is divided and recorded as two physical segments composed of the first length (D 0  to D j ) and the second length (D j+1  to D 1 ). 
     (3) The case where there are irregular void areas due to magnetic defects on the target track. 
     As is shown in FIG. 1(d), if there are magnetic defects D on the track corresponding to the logical record R1, the physical record R1-3 is divided and recorded as three physical segments composed of a first segment of length (D 0  to D i ), a second segment of length (D i+1  to D j ) and a third segment of length (D j+1  to D 1 ) in order to avoid the void areas. 
     Obviously, the case where cases shown in FIGS. 1(c) and 1(d) are coexistent, can be treated similarly. 
     Next, converting a logical record to a physical record composed of divided segments, by skipping the void area on the target track will briefly be explained with reference to FIGS. 2(a)-2(c). A logical record (FIG. 2(a)) is applied to magnetic disk apparatus and written to a target track on a disk in for data transfer. The magnetic disk apparatus of the present invention functions to detect in advance the arrival of the void area on the target track, and to suspend the normal data write process upon encounter of the void area. The magnetic disk apparatus writes a particular pattern &#34;EG&#34; (&#34;End Gap&#34;) for interruption before the void area. After the central portion of the void area has been passed, the re-synchronization pattern &#34;RSYNC&#34; is written in advance before the normal data write process is resumed as shown in FIG. 2(c). Thereafter, the write process is restarted after the portion of the &#34;RSYNC&#34; pattern. The transmission of the synchronization clock R/W REFCLK for data transfer to the computer is suspended during void area processing period T1 in FIG. 2(b). During this time interval T1, the upper apparatus is in pause condition, so that it does not require any logical control. 
     In the operation for reading the physical record including the void area, the read-out signal is regarded as normal data and is transmitted to the upper apparatus by means of the synchronization clock R/W REFCLK for data transmission until the detection of the &#34;EG&#34; pattern. The &#34;EG&#34; pattern is detected from the read-out signal and then the interrupted data position D i  is determined. At this instant, the transmission of the synchronization clock R/W REFCLK for data transfer is suspended and the void area processing starts. After the detection of the &#34;EG&#34; pattern, the void area is skipped, and the search of PLO (phase-locked oscillator) pull-in gap and the resynchronization pattern &#34;RSYNC&#34; is initiated. After the &#34;RSYNC&#34; pattern is detected, the following readout signal is regarded as a continuation (D i+1  to D 1 ) of the interrupted data block and the normal data transfer to the upper apparatus is re-started by restarting the transmission of synchronization clock R/W REFCLK for data transfer. 
     Even if there are plural void areas in the same physical record, the processing can be realized by repeating a similar operation. 
     Now, an embodiment of a magnetic disk apparatus according to the present invention will be explained with reference to FIG. 3. 
     The magnetic disk apparatus includes a head disk assembly (HDA) 10 which has a plurality of magnetic disks 11 attached to a spindle motor 12, and a plurality of data heads 14 and a servo head 15 driven by a head positioning motor 13. 
     A head positioning servo circuit 21 has, as its first input, a cylinder address information &#34;CA&#34; from the interface control circuit 80 and, as a feedback input, a position signal from a servo signal demodulator 22. The third input of the circuit 21 is a read signal r supplied from one of the selected data heads 14 through read amplifier 51 for supplying an embedded servo information. 
     The servo signal demodulator 22 has, as its input, a servo signal from servo head 15, and outputs an index signal IDX and a clock signal applied to a write clock circuit 23 to generate an original servo clock signal SCLK in addition to the position signal for the head positioning servo circuit 21. 
     A head selection circuit 30 connects one of the data heads 14 to a write amplifier 42 at write mode and to the read amplifier 51 at read mode, according to the head address information &#34;HA&#34; from the interface control circuit 80. 
     A clock multiplexer 60 receives, as clock inputs, the original servo clock signal SCLK and the read clock signal RCLK from a data separator 52, and, as control input, a gated read control signal G·R·GATE. It outputs, as read/write clock multiplexer signal MPX·CLK. the read clock signal RCLK at read mode and the servo clock signal SCLK at other operation modes. 
     A write data encoder 41 receives, as control input, a gated write control signal G·W·GATE and, as input data sequence, a gated write data signal G·WDT. and outputs an input pulse train to the write amplifier 42 after converting to the predetermined modulation pattern. Under the control of the gated write control signal G·W·GATE. the write amplifier 42 sends the write pattern to the selected head 14 through the head selection circuit 30. 
     In the read mode indicated by the gated read control signal G·R·GATE. the read amplifier 51 amplifies and re-shapes the read signal from the selected data head 14 through the head selection circuit 30, and thereafter outputs a read pulse signal to the data separator 52. The data separator 52 receives the read pulse signal from read amplifier circuit 51, generates the read clock signal RCLK, and simultaneously outputs the read pulse signal to read data decoder 53. The read data decoder 53 converts the read pulse signal into a predetermined data code, and then outputs as original read data RDT. 
     The interface control circuit 80 performs a control operation for connecting the magnetic disk apparatus to an upper apparatus 90 and performs a format control operation for read/write data. The interface control circuit 80 includes a cylinder address register (CAR) 81 for outputting the cylinder address information &#34;CA&#34;, a head address register (HAR) 82 for outputting the head address information &#34;HA&#34; and a normal format controller (SFC) 83 for transferring the read and write data to and from the computer apparatus 90. 
     A void-area-skipping control circuit 100 is installed between the above-mentioned interface control circuit 80 and the circuits in the magnetic disk apparatus for executing the skipping operation without any help by the normal format controller 83 when the head 14 passes over the void area (the embedded servo information area or the defect area) on the target data track. For this purpose, the control circuit 100 performs the following conversion functions: from the original servo clock signal SCLK to the gated servo clock signal GSCLK; from the read/write clock multiplexer signal MPX·CLK to the read/write synchronization signal R/W REFCLK; from the original write gate signal W·GATE to the gated write control signal G·W·GATE; from the original read gate signal R·GATE to the gated read control signal G·R·GATE; from the original write date signal WDT to the gate write data signal GWDT; and from the original read data signal RDT to the gated read data signal GRDT. 
     Referring to FIG. 4 and FIGS. 5(a)-5(p), the void-area skipping control circuit 100 includes a servo-byte counter 101 initialized by the index signal IDX. The counter 101 receives as count input a servo clock signal SCLK (FIG. 5(b)) and outputs a head position on a target track as servo-byte address information SBA to a void pointer circuit 110. The void pointer circuit 110 receives as its inputs a cylinder address CA and a head address HA in addition to servo-byte address information SBA, and then compares them with predetermined void-area address information. If they coincide with each other, it outputs a void-control initiation signal VOID-ON and simultaneously applies a void-area-length information VOID-L corresponding to the associated void area to the sequence counter 130. 
     A sequencer (SQC) 120 executes a series of control sequences for void-area skipping in response to the void control initiation signal VOID-ON (FIG. 5(a)). More specifically, when the original read gate signal R·GATE, which is one of the input signals to the sequencer 120, is on (FIG. 5(j)) at a timing when the signal VOID-ON is output, the sequencer 120 executes a void-area skipping sequence (the details of this sequence are shown in FIG. 8) for the data read mode (READ mode). When the original read gate signal R·GATE is off (FIG. 5(d)), the sequencer 120 executes another void-area skipping sequence (details of this sequence are shown in FIG. 7) for the data write mode (WRITE mode) or neither read-out nor write mode (NOP). In response to the void-control initiation signal VOID-ON and the original read gate signal R·GATE the sequencer 120 outputs sequentially the control tag signals SQ-1, SQ-2, SQ-3 and SQ-4 (FIG. 5(e) or 5(k)). The transition conditions between these tag signals are determined by another input condition, that is a sequence-count termination signal SCN=0 from a sequence counter (SCN) 130 and a pattern coincidence detection signal COMP=0 from a pattern coincidence detector (COMP) 180. 
     A servo clock inhibitor 140 receives, as its inputs, the original read gate signal R·GATE, the sequence control tag signals SQ-1, SQ-2, SQ-3 and SQ-4, and the servo clock signal SCLK. It outputs a servo clock inhibit signal SCLKY (FIG. 5(f) or 5(l)) which starts at either leading edges of sequence control tag signals SQ-1 or SQ-2 depending on the onand off-status of the original read gate signal R·GATE and lasts for a certain time interval determined by the void-area-length information VOID-L. An AND gate 102 receives original servo clock signal SCLK and the servo clock inhibit signal SCLKY, outputs a gated servo clock signal GSCLK (FIG. 5(h) or 5(n)), and controls the supply of the gated servo clock signal GSCLK to an output terminal depending on the operation modes determined by the original read gate signal R·GATE. 
     An AND gate 103 has as an original clock input, the clock multiplexer signal MPX·CLK and, as a control input, an interface valid signal I/F-VALID (FIG. 5(g) or 5(m)) which is the output of a read/write synchronization inhibitor composed of an AND gate 109 and an OR gate 108. The AND gate 103 outputs read/write synchronization signal R/W REFCLK, which is inhibited during the void area processing time interval as is shown in FIG. 5(i) or 5(p). The AND gate 109 receives the original read gate signal R·GATE and the sequence control tag signal SQ-1, and outputs a gated sequence control tag signal SQ-1&#39;. The logical OR gate 108 receives the sequence control tag signals SQ-2, SQ-3 and SQ-4 in addition to the gated sequence control tag signal SQ-1&#39;. and outputs the interface valid signal I/F-VALID. as is shown in FIGS. 5(g) and 5(m). 
     An AND gate 106 receives the original read gate signal R·GATE and the sequence control tag signal SQ-2, and outputs a gated read control signal G·R·GATE. The details of the timing of these signals are shown in FIG. 8. 
     An AND-OR gate 105 constituting a write data multiplexer circuit has, as a discrimination input, the interface valid signal I/F-VALID, and outputs, as gated write data signal G·WDT, either an original write data signal WDT or a bit-serial output signal SFRSG from a shift register 160. The details of the timing of these signals are shown in FIG. 7. 
     An AND gate 107 receives the bit-serial output signal SFRSG from the shift register 160 and outputs a gated read data signal G·RDT which is gated by the interface valid signal I/F-VALID. When the original read gate signal R·GATE is on, that is, under the data read mode, the original read data signal RDT is applied to input terminal IN of the shift register 160 through one of the inputs of an AND-OR gate 170 which works as a signal multiplexer. The data sequence applied to input terminal IN of shift register 160 is delayed by the number of shift stages of shift register 160 and is outputted as a shift register serial output signal SFRSG&#39; to one of the inputs of the AND gate 107 and also, as a parallel output signal SFRSG of the shift register 160, to one of the inputs of a coincidence detector 180. The coincidence detector 180 compares SFRSG&#39; with its other input GPSG, which is the input of a gap pattern generator 150. If they are equal, a pattern coincidence detection signal &#34;COMP=&#34; is outputted, which is applied to the sequencer 120 and sequence counter 130. 
     A gap pattern generator 150 receives the original write gate signal W·GATE, the original read gate signal R·GATE, and the sequence control tag signals SQ-1, SQ-3 and SQ-4, and controls the generation of the end gap pattern &#34;EG&#34; indicating the interrupted position of original write data WDT necessary for a series of void area skipping, and also the generation of the phase-locked oscillator (PLO) pull-in and the re-synchronization pattern &#34;RSYNC&#34; indicating the resumption of original write date WDT after skipping the void-area. The details of the timing of a series of gap patterns in the write mode are shown in FIG. 7. 
     In the read mode, the gap pattern generator 150 generates the end gap pattern &#34;EG&#34; to detect the same pattern &#34;EG&#34; from the original read data RDT and to prevent the transmission of the particular gap pattern to the gated read data signal G·RDT, and moreover generates the &#34;RSYNC&#34; pattern to re-synchronization. The details of the timing of a series of gap patterns in the read mode are shown in FIG. 8. 
     Next, an example of the void pointer circuit (VOID POINTER) 110 in FIG. 4 will be explained with reference to FIG. 6. In FIG. 6, a buffer circuit 111 receives the cylinder address information &#34;CA&#34;, head address information &#34;HA&#34;, and servo-byte address information SBA, and holds the present address value of the selected head. A address coincidence detector (COMP) 112 receives the output of the buffer circuit 111 (the present address), and also receives, from a void area registering memory cell 115, the cylinder address, head address, and servo-byte address segment which show a void area previously stored in the void area registering memory cell 115. An address counter register 113 either increments or decrements the address stored in itself in the direction increasing the possibility of address coincidence. When the address coincidence detector 112 indicates that two addresses are different. A decoder 114 decodes the output address from the address counter register 113 to read all the corresponding segments in the void-area registering memory cell 115. When the coincidence is detected by the detector 112, the &#34;VOID-ON&#34; signal is generated on a signal line 210. At the time, a signal bus 211 outputs the length information VOID-L of the void area stored in the selected void-area registering memory cell 115. 
     Furthermore, if the position of the void-areas are common to all cylinder addresses and all head addresses (for example, the embedded servo information regularly disposed on the data tracks), a circuit for detecting only for servo-byte segment can easily be attached. 
     Now the detailed operation in the embodiment shown in FIG. 4 at the write mode will be explained with reference to FIG. 7. 
     When the void pointer circuit 110 asserts the void-area control initiation signal VOID-ON (FIG. 7(a)), the void-area-skipping control circuit 100 senses the on/off status of the original read gate signal R·GATE (FIG. 7(b)). If it is off, the circuit 100 recognizes the system to the write mode (WRITE) or non-operation mode (NOP), and initiates a series of void-area-skipping control sequences to write mode type. In this case, the difference between the write mode and non-operation mode is in that, in the non-operation mode (neither the write mode nor the read mode) the gate write control signal G·W·GATE (FIG. 7(m)) is always off. FIGS. 7(a)-7(p) shows the situation where the original write gate signal W·GATE (FIG. 7(c)) is on (i.e., the write mode). 
     When the void-control initiation signal VOID-ON comes on, the sequencer circuit 120 is triggered to generate the first sequence control tag signal SQ-1 (FIG. 7(d)) so that the interface valid signal I/F-VALID (FIG. 7(l)) becomes off. The length L e  of the &#34;EG&#34; pattern is set to the sequence counter 130 and the &#34;EG&#34; pattern is outputted (FIG. 7(j)) from the pattern generator 150. The &#34;EG&#34; pattern is then set to the shift register 160. When the interface valid signal I/F-VALID becomes off, the content of gated write data signal GWDT (FIG. 7(p)) changes from the original write data signal WDT (FIG. 7(n)) to the serial input signal SFRSG from the shift register circuit 160, that is, &#34;EG&#34; pattern (FIG. 7(k)). 
     The first sequence control tag signal SQ-1 holds until the serial output signal SFRSG from the shift register circuit 160 completes the transmission of &#34;EG&#34; pattern (E s  to E 1 ) This holding time interval ends at a timing when the sequence count termination signal SCN=0 (FIGS. 7(h) and 7(i)) is outputted from the sequence counter 130. 
     The second sequence control tag signal SQ-2 is generated (FIG. 7(e)) by the sequence circuit 120 triggered by the sequence count termination signal SCN=0. The tag signal SQ-2 makes the gated write control signal G·W·GATE &#34;off&#34; (FIG. 7(m)) by means of the AND gate 104 during the period determined by a void area skipping length (L v ) set in the sequence counter circuit 130 when the tag signal SQ-2 is generated. The tag signal SQ-2 is terminated by the sequence count termination signal SCN=0. 
     Then, the third sequence control tag signal SQ3 is generated (FIG. 7(f)) so that the write operation the PLO pull-in pattern (G s  -G 1 , FIG. 7(k)) is carried out. The PLO pull-in pattern is required for the data separator circuit 52 to detect the resynchronization pattern &#34;PSYNC&#34; after skipping the void area in the read mode. As the &#34;PSYNC&#34; pattern, &#34;0&#34; pattern generated by a &#34;0&#34; constant circuit 179 is utilized. 
     The length of the PLO pull-in pattern (G s  -G 1 ) is determined by a PLO pull-in length (L g ) set in the and 7(i)). Then the writing of the PLO pull-in pattern during the sequence control tag signal SQ-3 terminates by the sequence termination signal SCN=0. 
     Next, the sequence control tag signal SQ-4 is generated to control the write operation of the resynchronization pattern &#34;RSYNC&#34; (S s  -S 1 ), which is outputted from the pattern generator 150 to the shift register 160 (FIG. 7(k)). The &#34;RSYNC&#34; pattern has a length L s , and is supplied in serial to the circuit 105 and then outputted as the gated write data signal G·WDT. 
     When the write operation of the &#34;RSYNC&#34; pattern terminates at output timing of count termination signal SCN=0 from the sequence counter 130, the void sequences in the write mode are completed and the interface valid signal I/F-VALID again becomes on, so that the suspended normal data (user&#39;s data) write operation is resumed at the next bit D i+1  and the normal write operation continues until the original write gate signal W·GATE becomes off (FIGS. 7(n) and 7(p)). 
     Next, the operation of the void-area-skipping control circuit 100 at the read mode will be explained with reference to FIG. 8. 
     During the time the original read gate signal R·GATE (FIG. 8(b)) is on, a sequence constituting a void-area-skipping operation in the read mode is executed when the void-control initiation signal VOID-ON is outputted (FIG. 8(a)). Since the fundamental flow of the control sequence is similar to that of the aforementioned write mode, only the different points will be explained. 
     An &#34;EG&#34; search is executed by the sequence control tag signal SQ-1 (FIG. 8(c)); the &#34;EG&#34; search means the detection of &#34;EG&#34; pattern (E s  to E 1 ) indicating the suspension of the normal data pattern (D 0  to D i ) from the original read data signal RDT (FIG. 8(j)), and the inhibition of the transfer of &#34;EG&#34; pattern as the gated read data signal G·RDT (FIG. 8(p)). Upon the detection of the &#34;EG&#34; pattern, the interface valid signal I/F-VALID (FIG. 8(n)) is immediately set to off, and then the transfer of the original read data signal RDT as the gated read data signal G·RDT is inhibited until a sequence of the read void processing ends i.e., until the fourth sequence control tag signal SQ-4 (FIG. 8(f)) ends. 
     The sequence control tag signal SQ-2 (FIG. 8(d)) is for skipping the void area of predetermined length L v  (FIG. 8(h)), as is similar to the write mode. 
     A search of the re-synchronization pattern (RSYNC) is executed by the sequence control tag signal SQ-3 (FIG. 8(e)) This sequence is for waiting the detection of the &#34;RSYNC&#34; pattern for re-starting data read after void area passes over. 
     A dummy skip is executed by the sequence control tag signal SQ-4 to shift the content of the shift register 160 by a bit length of &#34;RSYNC&#34; pattern so that the resume bit D i+1  appears at bit-serial output terminal of the shift register 160, so that &#34;RSYNC&#34; pattern is completely excluded from the content of the shift register 160. 
     The lengths of the second and fourth sequence (sequences designated by the signals SQ-2 and SQ-4) are determined by the skip lengths (L v  and L s ) (FIGS. 8(g) and 8(h)) set in the sequence counter 130, as is similar to the write mode. Also, the &#34;EG&#34; search sequence (sequence designated by SQ-1) and the &#34;RSYNC&#34; search sequence (sequence designated by SQ-3) last until the pattern coincidence detector 180 outputs the coincidence signal COMP=&#34; (FIG. 8(m)). If the pattern coincidences in the &#34;EG&#34; and &#34;RSYNC&#34; search sequences are unsuccessful, the output of the sequence count termination signal SCN=0 (FIG. 8(h)) is determined by the &#34;EG&#34; timeout period of length T e  and the &#34;RSYNC&#34; timeout period of length T s , respectively, set in the sequence counter 130. FIG. 8(l) shows the output signal of the pattern generator 150, while FIGS. 8(m) and 8(g) denote the pattern coincidence detection signal &#34;COMP=&#34; and the read/write synchronization clock signal R/W REFCLK, respectively.