Jagged-edge killer circuit for three-dimensional display
BACKGROUND OF THE INVENTION 
     The present invention relates to a jagged-edge killer circuit used for a three-dimensional display. 
     Hidden surfaces are removed when displaying three-dimensional image. Here, &#34;hidden-surface&#34; means a picture existing in a portion behind an object which has a short distance from a viewpoint in the depth direction within the three-dimensional image. In many case, the boundary generated between a hidden surface and a displayed surface as a result form the hidden surface removal, accompanies so-called jugged-edge or jaggy-edge. 
     The jagged-edge is wearsome for a viewer, therefore, it is desirable to adopt the jagged-edge killer with the hidden surface removal. 
     There is conventionally known a Z-buffer method as one of various jagged-edge killing methods, which has the merit of being capable of eliminating the jagged-edge in spite of the shape and output order of the surface to be displayed. 
     FIG. 1 shows a block diagram of the schematic structure of a conventional jagged-edge killer circuit used in the application of the jagged-edge killing by the Z buffer method. 
     In the figure, a Z-buffer 1 stores distance data in the depth direction corresponding to each pixel of a display frame buffer 3. The distance data of the depth direction, which is stored in the Z-buffer 1, is supplied to a renewal circuit 2 as data Z old . 
     The renewal circuit 2 receives data of the X and Y addresses of the pixels on the frame buffer 3, distance data Z new  of the pixels in the depth direction, and a luminance I of the pixels, and compares the new distance data Z new  of the pixels in the depth direction with the old distance data Z old  of the pixels in the depth direction stored in the Z-buffer 1 when luminance or color data of the pixels is written in the frame buffer 3. Only when the new pixels have a distance shorter than the old pixels from the viewpoint in the depth direction, a writing signal S W  renews the storage contents of the frame buffer 3 by the luminance I or color data corresponding to the new pixels, and the distance data Z new  of the new pixels renews the storage contents of the Z-buffer 1. 
     A picture is reproduced from image data read out of the frame buffer 3 when the conventional circuit shown in FIG. 1 performs the jagged-edge killing. As the reproduced picture is quantized pixel by pixel at the killing, the luminance or color becomes discontinuous so as to generate jagged portions in a step-shape at an outline which has an ordinally continuous area. 
     Even though the jagged portions can be eliminated by means that the luminance or color can be displayed after adding a post-filtering, it is possible to obtain the reproduced picture only having a low resolution because of the reduction of the pixel numbers constructing one scene. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a jagged-edge killer circuit capable of eliminating jagged portions from continuous outlines dividing different areas on a display screen without reducing the pixel numbers constructing one scene, namely, without deteriorating the resolution of a reproduced picture. 
     In order to achieve the above object, the jagged-edge killer circuit according to the present invention comprises a frame buffer for storing data of each pixel of the display screen by a pixel unit, a Z-buffer for storing distance data in the depth direction of the picture of a sub-pixel unit into which the pixel unit as a stored unit of the frame buffer is subdivided in a predetermined number, a picture data buffer for storing picture data of a luminance color by the sub-pixel unit, renewal means for renewing the contents stored in the picture data buffer by picture data of new pixels only with respect to sub-pixels nearer in the depth direction to a viewpoint within sub-pixels into which new pixels are subdivided in the predetermined numbers by comparing the distance data in the depth direction of each sub-pixel subdivided in the predetermined number of the new pixels with distance data in the depth direction of each sub-pixel stored in the Z-buffer when the picture data of the new pixel is written in the picture data buffer, and for renewing the contents stored in the Z-buffer by the distance data of a plurality of sub-pixels corresponding to the new pixels, and means for generating picture data of the pixel unit in the frame buffer by the arithmetical mean of the picture data of a plurality of sub-pixel units in the picture data buffer. 
     For storing the display data, the frame buffer stores luminance or color (picture) data of each pixel of the display screen by the pixel unit. 
     The Z-buffer stores distance data in the depth direction of the picture by the sub-pixel unit into which the pixel as the storage unit of the frame buffer is subdivided in the predetermined numbers. 
     As the picture data buffer is provided for storing the picture data by the sub-pixel unit, the distance data in the depth direction of each sub-pixel subdivided from the new pixel into the predetermined numbers, is compared with distance data in the depth direction of each sub-pixel stored in the Z-buffer, thereby renewing the storage contents of the picture data buffer by the picture data of the new pixels with respect to the sub-pixels nearer in the depth direction to the viewpoint within sub-pixels subdivided from the new pixels into the predetermined numbers, and at the same time renewing the storage contents of the Z-buffer by the distance data of the plurality of sub-pixels corresponding to the new pixels. 
     The picture data of the pixel unit in the frame buffer, is generated by the arithmetical mean for the pixel data of a plurality of the sub-pixel units in the picture data buffer. 
     Therefore, the reproduced picture which is displayed on the basis of the picture data read out of the frame buffer, has a high resolution and non-jagged edge. 
     As is apparent from the above, the jagged-edge killer circuit of the present invention is characterized in that one pixel of the displayed picture is subdivided into a predetermined number such as &#34;M×N&#34; of sub-pixels, new distance data in the depth direction of each sub-pixel are compared with old data, picture data such as luminance or color data of the sub-pixels and distance data in the depth direction of the sub-pixels are both rewritten corresponding to the comparison result, and the picture data of one sub-pixel is operated by the arithmetical mean, thereby using the arithmetical mean value as the picture data of one pixel. Accordingly, it is possible to obtain a high-resolution reproduced picture and to prevent the reproduced picture form the jagged edge on the basis of picture data read out of the frame buffer. Furthermore, it is easy to perform the non-jagged matching by using an α value. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings: 
     FIG. 1 is a block diagram showing a schematic structure of a conventional jagged-edge killer circuit used when a jagged-edge killing by a Z buffer method is performed; 
     FIG. 2 is a block diagram showing a schematic structure of a jagged-edge killer circuit according to the present invention; 
     FIG. 3 is a block diagram showing an example of a main portion in a renewal circuit of a Z-comparison and Z-buffer/picture data buffer; 
     FIG. 4 is a block diagram showing an example of a main portion of the Z-buffer; 
     FIG. 5 is a block diagram showing an example of a main portion of the picture data buffer; and 
     FIGS. 6 and 7 are block diagrams respectively showing several parts of an arithmetical mean circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     There will be described in detail a concrete content of a jagged-edge killer circuit according to the present invention with reference to the accompanying drawings. 
     The killer circuit comprises, as shown in FIG. 2, a Z-comparison and renewal circuit 4 for comparing new data with old data and renewing a Z-buffer and picture data buffer, as shown in FIG. 3, a Z-buffer 5 for storing data in a depth direction, a picture data buffer 6 for storing picture data, an arithmetical mean circuit 7 for operating an arithmetical mean, a frame buffer 8 for storing data by a pixel unit, and an input data bus 9. 
     Furthermore, a concrete example of a main portion of the Z-comparison and renewal circuit 4 is shown in FIG. 3. 
     The jagged-edge killer circuit according to the present invention is characterized in that one pixel of the displayed picture is divided into sub-pixels in predetermined numbers such as sixteen of 4 by 4both new and old distance data in the depth direction of each sub-pixel is compared each other, the picture data and the distance data in the depth direction of each sub-pixel are respectively rewritten corresponding to the comparison result, and an arithmetical mean value is derived from the rewritten picture data of the sub-pixels corresponding to one pixel and used as the picture data of one pixel. Accordingly, when data of X and Y addresses on the frame buffer of the pixel and the distance data Z new1  to Z new16  in the depth direction of the sub-pixels are supplied through the input bus 9 to the Z-comparison and renewal circuit 4 for the Z-buffer and picture data buffer, new picture data of the pixel unit is written in the picture data buffer 6. Namely, the new distance data Z new1  to Z new16  in the depth direction of the sub-pixels are compared with old distance data Z old1  to Z old16 , sub-pixels having a shorter distance from the viewpoint within the subdivided sub-pixels are renewed with respect to their storage content in the buffer 6, and the storage content of the Z-buffer 5 is renewed by the distance data of sub-pixels corresponding to the new pixels. 
     In FIG. 3, when the picture data about the luminance and color is outputted to the picture data buffer 6, a latch circuit 42 latches data of X address on the frame buffer of the pixel, which are supplied through the input data bus 9 to the renewal circuit 4, and a latch circuit 43 latches data of Y address. The new distance data Z new1  to Z new16  in the depth direction of the sixteen sub-pixels corresponding to one pixel are respectively latched by the concerned circuit of latch circuits 10a to 10p of Z-comparison circuit 41a to 41p individually mounted to each sub-pixel. 
     A Z-comparison circuit 41a in the sixteen circuits 41a to 41p is provided for comparing distance data in the depth direction of the first sub-pixel, a circuit 41b handles the second sub-pixel, and a circuit 41p handles the sixteenth sub-pixel according to the same manner. 
     A pixel address signal S PA-A  is calculated on the basis of both values of the X and Y addresses which are latched by the latch circuit 42 and 43, respectively, so as to output it to the Z-buffer 5 and picture data buffer 6. A timing control circuit 45 makes the signal S PAS-A  active, and controls each timing of respective latch circuit. In this condition, a write enable signal S W  for the Z-buffer and picture data, is turned to be inactive. 
     Referring FIGS. 2 to 4, when the signal S PAS-A  becomes active, the Z-buffer 5 reads out the distance data Z old1  to Z old16  of the sub-pixel 1 to 16 in the depth direction which are stored in the memories 15a to 15p of the Z-buffer 5. These data Z old1  to Z old16  are latched by the latch circuit 11a to 11p provided in the Z-comparison circuits 41a to 41p. 
     The new distance data Z new1  to Z new16  latched by the latch circuit 10a to 10p, are respectively supplied to the corresponding memories 15a to 15p, at the same time, to the corresponding comparison circuits 13a to 13p. The circuits 13a to 13p are received the old data Z old1  to Z old16  from the latch circuits 11a to 11p. 
     The comparison circuits 13a to 13p each compare the new data Z new1  to Z new16  with the old data Z old1  to Z old16  in the manner that the corresponding pair is compared each other. In this comparison, when &#34;Z newi  &lt;Z oldi  &#34; (where a character i is any of 1 to 16), the concerned circuits 13a to 13p output active signals to AND circuits 14a to 14p corresponding thereto. 
     If the circuits 13a to 13p ascertain the active signals, the timing control circuit 45 causes the write enable signal S W  to be active. 
     Here, for example, when the AND circuit 14a receives an active signal from the comparison circuit 13a as the comparison result, the AND circuit 14a outputs a buffer write enable signal S W1  for the Z-buffer and picture data buffer if the write enable signal S W  is active, so that the distance data corresponding to the address signal S PA-A  is renewed in the concerned memory 15a, as shown in FIG. 4, by the distance data Z new1  of the sub-pixel 1 latched by the latch circuit 10a. 
     The picture data of the sub-pixel 1 corresponding to the signal S PA-A , is also renewed by the picture data latched by latch circuit 44. 
     When the AND circuit 14b receives an active signal from the comparison circuit 13b as the comparison result, the AND circuit 14b outputs a buffer write enable signal S W2  for the Z-buffer and picture data buffer if the write enable signal S W  is active, so that the distance data corresponding to the address signal S PAS-A  is renewed in the concerned memory 15b, as shown in FIG. 4, by the distance data Z new2  of the sub-pixel 2 latched by the latch circuit 10b. The picture data of the sub-pixel 2 corresponding to the signal S PA-A , is also renewed by the picture data latched by latch circuit 44. 
     Regarding the sub-pixels 3 to 16, the distance data Z new3  to Z new16  and picture data of sub-pixels 3 to 16 are renewed by the same manner as the sub-pixels 1 and 2. 
     When the Z-buffer 5 and picture data buffer 6 complete the renewal operation, the timing control circuit 45 causes both the signal S PAS-A  and write enable signal S W  to be non-active. Distance data of entire sub-pixels of the Z-buffer are initially set to the maximum value at starting the scene, namely, the most distant position value from the viewpoint. 
     Accordingly, both the picture data and the distance data of the sub-pixel i are renewed on the basis of a memory 15 i  having the output Z oldi  and input signals Z newi , S Wi , S PA-A  and a pixel address strobe signal S PAS-A . The renewal are performed when the pixel address strobe signal S PAS-A  is active. 
     In FIG. 5 showing the main portion of the picture data buffer 6, the picture data buffer 6 comprises the first buffer memory 16 and the second buffer memory 17 each surrounded by a dotted line so as to construct a double buffer. 
     Memories 16a to 16p of the first buffer memory 16 and memories 17a to 17p of the second buffer memory 17 respectively correspond to the first to sixteenth sub-pixels 1 to 16 for storing picture data such as luminance data I 1  to I 16  thereof. 
     For example, while the renewal circuit 4 has an access to the first buffer memory 16, the arithmetical mean circuit 7 has an access to the second buffer memory 17. In contrast, while the circuit 4 has an access to the second buffer memory 17, the circuit 7 has an access to the first buffer memory 16. 
     Numerals 18a to 18p, 19a to 19p and 20 to 23 denotes selectors. The selectors 18a to 18p are used for selecting the buffer memory which supplies the picture data I 1  to I 16  such as the luminance (or color) data to the arithmetical mean circuit 7, and the selectors 19a to 19p are used for selecting the buffer memory which supplies to the arithmetical mean circuit 7 with flags F W1  to F W16  for representing that the picture data have been written. 
     The selector 20 is used for selecting an address strobe signal used by the first buffer 16 from the pixel address strobe signal S PAS-A  of the renewal circuit 4 and the pixel address strobe signal S PAS-B  of the arithmetical circuit 7. 
     The selector 21 is used for selecting an address strobe signal used by the second buffer memory 17 from the pixel address strobe signal S PAS-A  of the renewal circuit 4 and the pixel address strobe signal S PAS-B  of the arithmetical mean circuit 7. 
     The selector 22 is used for selecting an address used by the first buffer memory 16 form the pixel address signal S PA-A  of the renewal circuit 4 and the pixel address signal S PA-B  of the arithmetical mean circuit 7. 
     The selector 23 is used for selecting an address used by the second buffer memory 17 from the pixel address signal S PA-A  of the renewal circuit 4 and the pixel address signal S PA-B  of the arithmetical means circuit 7. 
     If both the pixel address strobe signal S PAS-A  and the buffer write enable signal S W1  becomes active when the renewal circuit 4 selects the first memory 16 of the buffer 6 and the arithmetical mean circuit 7 selects the second memory 17 of the buffer 6, the picture data I is stored in the memory 16a as the luminance or color signal of the sub-pixel 1 according to the pixel address signal S PA-A  of the circuit 4. At this time, the flag for representing that the picture data of the sub-pixel 1 corresponding to the signal S PA-A  have been written, becomes true so as to be stored in the memory 16a. 
     As is in the same manner, if both the pixel address strobe signal S PAS-A  and the buffer write enable signal S W2  (or any of S W3  to S W16 ) becomes active when the renewal circuit 4 selects the first memory 16 of the buffer 6 and the arithmetical mean circuit 7 selects the second memory 17 of the buffer 6, the picture data I is stored in the memory 16b (any of 16c to 16p) as the luminance or color signal of the sub-pixel 2 (or any of 3 to 16) according to the pixel address signal S PAS-A  of the circuit 4. At this time, the flag for representing that the picture data of the sub-pixel 1 corresponding to the signal S PA-A  have been written, becomes true so as to be stored in the memory 16b (or any of 16c to 16p). 
     When the renewal circuit 4 selects the first buffer memory 16, the second memory 17 is selected by the arithmetical mean circuit 7. In this condition, hen the signal S PAS-B  is active, the picture data of the sub-pixel 1 (or any of 2 to 16) corresponding to the address signal S PA-B , is read out of the second memory 17a (or any of 17b to 17p) to be supply to the arithmetical mean circuit 7, and the flag F W1  (or any of F W2  to F W16 ) for representing that the picture data of subpixel 1 to 16 of the signal S PA-B  is read out of the second memory 17a (or any of 17b to 17p) so as to supply it to the arithmetical mean circuit 7. 
     There is performed a changeover of the first and second memories 16 and 17 at the start of the scene. At changing over the first and second memories 16 and 17, any memory selected from the memories 16 and 17 by the renewal circuit 4, is set to zero of the picture data and to be false of the flag that the picture data have been written. 
     FIGS. 6 and 7 are block diagrams respectively showing one and another parts of the arithmetical mean circuit 7. In FIG. 6, a circuitry comprises a plurality of full-adders 24 for obtaining the arithmetical mean of the picture data I 1  (or any of I 2  to I 16 ) of the sub-pixel 1 (or any of 2 to 16), and right shifting circuit 25 having four bits. In FIG. 7, a circuitry comprises a control circuit 26 for generating a pixel address strobe signal S PAS-B , a pixel address signal S PA-B , a pixel data strobe signal S PDS  and so on, and an α value calculating circuit 27. 
     Namely, the control circuit 26 sequentially generates the addresses of the entire pixels of one scene so as to output as the pixel address signal S PA-B . If one pixel address is fixed, the control circuit 26 causes the pixel address strobe signal to be active. 
     When the signal S PAS-B  becomes active, the picture data I 1  (or any of I 2  to I 16 ) of the pixel 1 (or any of 2 to 16) is read out of sixteen memories provided in any buffer memory which is selected from the first and second buffer memories 16 and 17 in the buffer 6 by the mean circuit 7 corresponding to the signal S PA-B . Any one selected from the picture data I 1  to I 16  is supplied to the circuitry having the full-adders 24 and the four-bit right shifted circuit 25. In this circuitry, an arithmetical mean value I out  of the picture data I 1  to I 16  is calculated to output it to the frame buffer 8. 
     any one of the flags F W1  to F W16  for representing that the picture data have been written, is read out of sixteen memories of the buffer memory which is selected by the mean circuit 7 from the first and second memories 16 and 17 of the buffer 6 corresponding to the signal S PA-B , thereby outputting it to the α value calculating circuit 27 of the mean circuit 7. 
     The α value calculating circuit 27 counts a number flags which are true in the flag F W1  to F W16  for representing that the picture data have been written, thereby setting an α value. The α value is used when another two-dimensional pictures are matched behind the picture generated by the jagged-edge killer circuit. A luminance I of the picture after matching is obtained by the following equation. 
     
         I=I.sub.out +{(16-α)/16}×I.sub.back 
    
     where I out  designates a pixel luminance of the picture generated by the jagged-edge killer circuit, and I back  designates a pixel luminance of the two-dimensional picture matched behind the picture which is generated by the jagged-edge circuit. 
     When the mean value I out  and the α value outputted from the circuit 7 become stable, the signal S PDS  outputted from the control circuit 26 is caused to be active, thereby allowing the values I out  and the α value to be supplied to an external circuit such as frame buffer 8. 
     When the frame buffer 8 receives both the values I out  and α, the buffer 8 causes a pixel data strobe acknowledge signal S PDSACK  to be active. If the signal S PDSACK  is caused to be active, the control circuit 26 of the mean circuit 7 causes the signals S PAS-B , S PA-B , and S PDS  to be inactive, thereby advancing an operation into the next process.