GOLD code generating device in a spread spectrum communication device
FIELD OF THE INVENTION 
     The present invention relates to a spread spectrum communication (hereinbelow abbreviated to SSC) device and in particular to an improvement of a GOLD code generating device used therein. 
     BACKGROUND OF THE INVENTION 
     In a spread spectrum communication device, as indicated in FIG. 5(a), a pseudo noise (PN) code, which is one of binary codes, is modulated with data and then a carrier is modulated with the modulated PN code to be transmitted. In the figure, reference numeral 31 is data; 32 is a modulator; 33 is a PN code generator (PNG); 34 is a carrier generator (OSC); 35 is a modulator; and 36 is an antenna. On the receiver side, as indicated in FIG. 5(b), the signal thus transmitted is received and correlation thereof with a PN code serving as a reference is formed in a matching filter. The data are reproduced by processing a self correlation waveform having a relatively large amplitude (hereinbelow, in the present specification, called correlation spike waveform) appearing when the two codes are in accordance with each other and in the neighborhood thereof. In the figure, reference numeral 37 is an antenna; 38 is a matching filter serving as a correlator; 39 is a reference PN code generator (PNG); 40 is a data demodulator; and 41 is data. 
     As one of matching filters 38 there is known a convolver. A convolver is a functional element executing convolution integration and acts as a matching filter effecting correlation operation, when a binary code serving as a reference (hereinbelow, in the present specification, called reference code) is in a time-inverted relationship with respect to the received code. 
     As an example of the convolver there is known a surface acoustic wave (hereinbelow abbreviated to SAW) convolver. In the SAW convolver, from the point of view of the structure, there are (1) those, in which an air gap is disposed between a piezo-electric body and a silicon substrate; (2) those, in which a piezo-electric body and a silicon substrate are formed in one body through an oxide film; (3) those composed only of a piezo-electric body; etc., either one of which effects multiplication operation by interaction of the two signals, utilizing non-linear characteristics, and integrates a result thus obtained in an electrode called gate disposed on an interaction region therefor. 
     FIG. 6 shows an example indicating the structure of the SAW convolver, in which 42 and 43 are transducers; 44 is a pezo-electric body; 45 is an oxide film; 46 is a silicon substrate; and 47 is a gate electrode. A signal s(t) inputted through the transducer 42 propagates towards the right in the figure and a signal r(t) inputted through the transducer 43 propagates towards the left. Interaction takes place between the two input signals s(t) and r(t) described above by non-linear characteristics, which a multilayered structure of piezo-electric body-oxide film-silicon substrate has, effecting multiplication operation, and a result thus obtained is integrated by the gate electrode 47. 
     A signal c(t) outputted by the gate electrode is represented by a following equation; ##EQU1## where A is a constant; T is a time required for sonic wave to pass through the region under the gate electrode (hereinbelow, in the present specification, called in-gate delay time); x is a distance measured in the propagation direction of the signal s(t); and v is a sound velocity. In a direct spreading SSC using e.g. a correlator such as an SAW convolver, as means for dividing communication channels in the case where a maximum length linearly recurring sequence code (hereinbelow called simply m sequence code) is used as a spreading code, it is conceivable to use not only the kind of the m sequence code but also the initial phase of the m sequence code used on both the transmitter and the receiver side. Algorithms for determining the data reproduction timing and initial phase information of the m sequence code, etc. are described in JP-A-Sho 63-95744 (corresponds to U.S. Pat. No. 4,847,861). 
     In the case where the SSC system is executed by the CSK system, by which transmitted codes are switched over (e.g. code 1 is used when the transmitted data are &#34;1&#34; and code 2 is used when the transmitted data are &#34;0&#34;), depending on the polarity of the transmitted binary data, when GOLD codes are used for the code 1 and the code 2 described above, in order to generate two kinds of GOLD codes, i.e. GOLD code 1 and GOLD code 2, by using m sequence code generators as indicated in JP-A-Sho 63-18835 and JP-A-Sho 63-132519 which both correspond to U.S. Pat. No. 4,864,525, two m sequence code generators are necessary for each of them, because the GOLD code is obtained by adding two kinds of m sequence codes mod. 2 (exclusive logic sum). 
     Consequently this system has a problem that the circuit scale for the m sequence generating circuit increases with increasing length of the period of the used GOLD codes. 
     OBJECT OF THE INVENTION 
     The object of the present invention is to provide an SSC system capable of generating GOLD codes by using an m sequence code generating circuit of small scale, in the case where the SSC using correlators such as SAW convolvers is effected by the CSK using GOLD codes. 
     SUMMARY OF THE INVENTION 
     In order to achieve the above object, a GOLD code generating device on the transmitter side in a spread spectrum communication device by the CSK system, by which a first GOLD code and a second GOLD code are transmitted while switching over them selectively, depending on information signals, according to a first invention of the present application is characterized in that it comprises a first m sequence code generator generating a first m sequence code; a second m sequence code generator generating a second m sequence code; phase delaying means for obtaining a first phase-delayed m sequence code by delaying the phase of either one code of the two m sequence codes by a predetermined number of chips; first exclusive logic sum means for forming an exclusive logic sum of the first m sequence code and the second m sequence code; and second exclusive logic sum means for forming an exclusive logic sum of the other code of the two m sequence codes and the first phase-delayed m sequence code. 
     A GOLD code generating device on the receiver side in a spread spectrum communication device by the CSK system, by which a first GOLD code and a second GOLD code are transmitted while switching over them selectively, depending on information signals, according to a second invention of the present application is characterized in that it comprises a third m sequence code generator generating a third m sequence code, which is a mirror image inverted in time with respect to the second m sequence code; a fourth m sequence code generator generating a fourth m sequence code, which is a mirror image inverted in time with respect to the first m sequence code; third exclusive logic sum means for forming an exclusive logic sum of the third m sequence code and the fourth m sequence code; phase delaying means for obtaining a second phase-delayed m sequence code by delaying the phase of either one code of the two m sequence codes by a predetermined number of chips; and fourth exclusive logic sum means for forming an exclusive logic sum of the other code of the third and the fourth m sequence code and the second phase-delayed m sequence code. 
     A GOLD code generating device in a spread spectrum communication device by the CSK system, by which a first GOLD code and a second GOLD code are transmitted while switching over them selectively, depending on information signals, according to a third invention of the present application is characterized in that a GOLD code generating device on the transmitter side comprises a first m sequence code generator generating a first m sequence code; a second m sequence code generator generating a second m sequence code; phase delaying means for obtaining a first phase-delayed m sequence code by delaying the phase of either one code of the two m sequence codes by a predetermined number of chips; first exclusive logic sum means for forming an exclusive logic sum of the first m sequence code and the second m sequence code; and second exclusive logic sum means for forming an exclusive logic sum of the other code of the two m sequence codes and the first phase-delayed m sequence code, while a GOLD code generating device on the receiver side comprises a third m sequence code generator generating a third m sequence code, which is a mirror image inverted in time with respect to the second m sequence code; a fourth m sequence code generator generating a fourth m sequence code, which is a mirror image inverted in time with respect to the first m sequence code; third exclusive logic sum means for forming an exclusive logic sum of the third m sequence code and the fourth m sequence code; phase delaying means for obtaining a second phase-delayed m sequence code by delaying the phase of either one code of the two m sequence codes by a predetermined number of chips; and fourth exclusive logic sum means for forming an exclusive logic sum of the other code of the third and the fourth m sequence code and the second phase-delayed m sequence code. 
     Owing to the construction described above, in the case where the SSC system using correlators is executed by the CSK system, it is possible to generate GOLD codes corresponding to codes 1 and 2 when data to be transmitted are &#34;1&#34; and &#34;2&#34; by means of 2 m sequence code generators on each of the transmitter side and the receiver side. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1(a) and 1(b) are schemes of a construction for generating two kinds of GOLD codes on the transmitter side and on the receiver side, respectively, according to the present invention; 
     FIG. 2 shows a construction conceivable for generating two kinds of GOLD codes; 
     FIGS. 3 and 4 are block diagrams of m sequence code generators, which are object of the present invention; 
     FIGS. 5(a) and 5(b) are block diagrams showing an example of a prior art spread spectrum communication system; and 
     FIG. 6 is a cross-sectional view showing a construction of an SAW convolver as an example. 
    
    
     DETAILED DESCRIPTION 
     In FIGS. 1 and 2, u, v, u, v, w and y are m sequence codes, PNG1˜PNG4 are m sequence code generators; G1, G2, G1, G2, G3 and G4 are GOLD codes; EX 1  ˜EX 4  are exclusive logic sum gates executing addition mod. 2; and FF is a flipflop. 
     In FIG. 3, SR 1  ˜SR n  are flipflops; G 1  ˜G n  are steering gate circuits; EX 1  ˜EX n  are exclusive logic sum gates; AND 0  ˜AND n  are AND gates; MPX is a multiplexer; DE-MPX is a demultiplexer; INV 1  and INV 2  are inverters; L 1  ˜L 6  are latch circuits; CLK is a supplied clock; STB is a code switching strobe signal; CS is a chip select signal; LE is a latch enable signal; DAT1˜n are initial information necessary for generating code by the code generating devices, which set following states (i) to (iii); 
     (i) initial state of the shift register, 
     (ii) feedback state, and 
     (iii) last stage selection state for the shift register. 
     SEL0˜1 are data select signals, which select the data as indicated in TABLE 1. FB0˜1 and CAS are input and output terminals for the cascade connection; FB2 is a three state output; and PN is an output of an m sequence code. 
     
                       TABLE 1                                                     
______________________________________                                    
SEL 1         SEL 0   DATA                                                
______________________________________                                    
L             L       (i)                                                 
L             H       (ii)                                                
H             L       (iii)                                               
H             H       Meaningless                                         
______________________________________                                    
 
    
     In FIG. 4, the symbols, which are used in FIG. 3 in common, represent parts, which are identical or similar to those described in FIG. 3, and data DAT 1  ˜DAT n  set following states (i) and (ii). 
     (i) initial state of the flipflops, and 
     (ii) feedback state and last stage selection state for the flipflops. 
     The data select signals SEL are signals for selecting data as indicated in TABLE 2. 
     
                       TABLE 2                                                     
______________________________________                                    
        SEL  DATA                                                         
______________________________________                                    
        L    (i)                                                          
        H    (ii)                                                         
______________________________________                                    
 
    
     FIG. 2 shows a construction conceived for generating the two kinds of GOLD codes and in this case 4 kinds of m sequence codes u, v, w and y are generated by using 4 m sequence code generators PNG1˜PNG4 so as to obtain the GOLD code G1 generated from (u, v) and the GOLD code G2 generated from (w, y). 
     However the circuit scale for the m sequence code generating circuit increases with increasing length of the period of the used GOLD codes. Further it is necessary to set the initial information indicated in (i)˜(iii) for PNG1˜PNG4. FIG. 1(a) shows the m sequence codes u, v and T 1  v as well as the GOLD codes G1 (u ⊕ v) and G2 (u ⊕ T 1  v), where ##EQU2## Consequently T 1  v means a code, whose phase is retarded by 1 chip with respect to v, and it is obtained by taking out v through the flipflop FF. 
     Denoting &#34;mirror images&#34; of u and v by u and v, respectively, the GOLD codes, which are to be generated on the receiver side, can be given by; 
     
         G1=u⊕v→u⊕v=G1                               (1 
    
     
         G2=u⊕T.sup.1 v→u⊕T.sup.-1 v=G2              2 
    
     However by the construction indicated in FIGS. 1(a) and 1(b) it is not possible to generate an m sequence code expressed by T 1  v. Therefore, multiplying the right member of Eq. 2 by T 1 , following Eq. 3 is obtained; 
     
         T.sup.1 u⊕T.sup.1 ·T.sup.-1 v=T.sup.1 u⊕v=T.sup.1 G23. 
    
     Although the phase of the GOLD code given by Eq. 3 is retarded by 1 chip with respect to the GOLD code given by Eq. 2, the code pattern thereof is completely identical to that of the latter. 
     Consequently, by setting on the receiver side v for PNG3 corresponding to u of PNG 1 on the transmitter side in FIG. 1(a) and u for PNG4 corresponding to v of PNG 2, as indicated in FIG. 1(b), it is possible to generate two kinds of GOLD codes, which are in the &#34;mirror image&#34; relation to each other, with a same construction on the transmitter side and on the receiver side. 
     Further, although a system, by which the phase is retarded by one chip, is used in the construction indicated in FIGS. 1(a) and 1(b), the present invention can be applied also to other cases where another system, by which the phase is retarded by any number of chips, is used. 
     Concerning the SS communication by the CSK system, refer to Japanese patent application No. Hei 1-29538. 
     As explained above, according to the present invention, an advantage can be obtained that it is possible to generate GOLD codes by using m sequence code generators having a small circuit scale. 
     While particular embodiments of the invention have been shown and described, it will be obvious to those skilled in the art that various changes and modifications may be made without departing from the present invention in its broader aspect.