Compound semiconductor integrated circuit
BACKGROUND OF THE INVENTION 
     The present invention generally relates to semiconductor integrated circuits, and more particularly to a compound semiconductor integrated circuit for producing a relatively large output voltage. 
     Generally, a thin active layer is used to reduce the pinch-off voltage of the field effect transistor (FET). However, when a compound semiconductor material such as GaAs is used and a surface depletion layer is introduced due to the surface levels, the surface depletion layer occupies an increasing amount, or proportion, of increases the channel increases and the channel becomes correspondingly narrower. As a result, the stray resistance, particularly the source resistance R s  increases, thereby reducing the mutual conductance. Accordingly, various measures are taken to reduce the effects of the surface depletion layer in order to minimize the stray resistance. 
     One such measure involves the so-called self-aligned type FET. The self-aligned type FET has an impurity layer of high impurity concentration formed in self-alignment with the gate electrode. The stray resistance R s  can be made extremely small because the impurity layer reaches the vicinity of the gate. 
     FIG. 1 shows an example of a conventional semiconductor integrated circuit. In FIG. 1, a logic part 10 forms an internal circuit, and a driver part 11 drives a load. The logic part 10 converts an internal signal S 1  into a logic signal S 2  and an inverted signal S 2X  of the logic signal S 2 . The driver part 11 amplifies the logic signals S 2  and S 2X  into driving signals S 3  and S 3X  which are sufficiently large to drive the load. The logic part 10 includes a self-aligned type FET T 1 . On the other hand, the driver part 11 includes self-aligned type FETs T 2  through T 4  and resistors R 1  and R 2  which are connected as shown. 
     The amplitudes of the driving signals S 3  and S 3X  are determined by terminal voltages E R1  and E R2  developed across the respective resistors R 1  and R 2  in relation to the switching operation of the respectively associated FETs T 2  and T 3 . For example, the amplitude of the driving signal S 3  is obtained by subtracting the drain voltage V D2ON  (=V DD  -E R1 ) of the FET T 2  when it is ON from the drain voltage V D2OFF  (=V DD ) of the FET T 2  when it is OFF, that is, the amplitude of the driving signal S 3  is given by E R1 . 
     However, since the FETs T 2  through T 4  used in the driver part 11 of the conventional semiconductor integrated circuit are of the self-aligned type, the amplitude of the driving signals S 3  and S 3X  is only 5 V at the maximum, and only 3 V if safety factor is taken into consideration. For this reason, there is a problem in that the conventional semiconductor integrated circuit cannot be used to drive a load which requires a driving signal which is greater than 5 V. 
     In other words, in order to make the amplitude of the driving signals S 3  and S 3X  greater than 5 V in FIG. 1, it is necessary to set the potential difference of the two power source voltages V DD  and V SS  to at least 10 V or greater. But if the potential difference of the two power source voltages V DD  and V SS  is set to 10 V or greater, this potential difference of 10 V or greater is applied across the drain and source of the FET T 2  (or T 3 ) which is OFF. Since the drain withstand voltage of the self-aligned type FET is in the range of 4 V to 6 V at the most, the FET T 2  (or T 3 ) breaks down permanently in this case. 
     It is conceivable to use non-self-aligned FETs in the driver part 11 in order to obtain a drain withstand voltage higher than that obtainable by the self-aligned type FETs T 2  through T 4 . However, in the case of the self-aligned type FET and the non-self-aligned type FET having the same gate electrode length, the gap between the two impurity regions is much smaller for the self-aligned type FET. For this reason, if the driver part 11 uses the non-self-aligned type FETs having the same gap between the two impurity regions as the self-aligned type FETs T 2  through T 4  in order to obtain the same performance, the gate electrode length of each non-self-aligned type FET must be made extremely small. However, the gate electrode length of each of the self-aligned type FETs T 2  through T 4  is relatively small to start with, when the driver part 11 is formed as an integrated circuit having a satisfactorily high integration density; thus, and it is extremely difficult to further reduce the electrode length of the non-self-aligned type FET compared to the corresponding gate electrode length of the self-aligned type FET. On the other hand, the gate electrode length of the non-self-aligned type FET must be increased to increase the gap between the two impurity regions in order to improve the drain withstand voltage, but this contradicts to the need to decrease the gap in order to obtain the same performance as the self-aligned type FET. Therefore, the above described problem cannot be eliminated by merely using non-self-aligned type FETs in the driver part 11. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor integrated circuit in which the problems described above are eliminated. 
     Another and more specific object of the present invention is to provide a semiconductor integrated circuit for outputting a driving signal for driving a load, comprising a compound semiconductor substrate, a logic part including at least a first field effect transistor formed on the compound semiconductor substrate for outputting a first signal, and a driver part, coupled to the logic part and including at least a second field effect transistor formed on the compound semiconductor substrate and outputting the first signal through the second field effect transistor as a driving signal, where the first field effect transistor is a self-aligned type field effect transistor having a first gate electrode and first and second impurity regions formed in self-alignment to the first gate electrode and the second field effect transistor is a non-self-aligned type field effect transistor having a second gate electrode and third and fourth impurity regions formed in non-self-alignment to the second gate electrode. According to the semiconductor integrated circuit of the present invention, it is possible to obtain a relatively high drain-source withstand voltage for the second field effect transistor, thereby making it possible to obtain a driving signal having an amplitude of 5 V or greater. 
     Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing an example of a conventional semiconductor integrated circuit; 
     FIG. 2 is a diagram for explaining an operating principle of the present invention; 
     FIG. 3 is a circuit diagram showing an embodiment of a semiconductor integrated circuit according to the present invention; 
     FIGS. 4A and 4B cross sectional views respectively showing a non-self-aligned type FET and a self-aligned type FET of the embodiment; 
     FIGS. 5A and 5B are cross sectional views for respectively explaining gate electrode lengths of non-self-aligned and self-aligned type FETs; and 
     FIG. 6 is a diagram for explaining an application of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First, a description will be given of the operating principle of the present invention, by referring to FIG. 2. FIG. 2 shows a first FET 1 and a second FET 2 which are formed on a common compound semiconductor substrate SUB. The first FET 1 has an impurity layer of high impurity concentration formed in self-alignment with the gate electrode. On the other hand, the second FET 2 has an impurity layer of high impurity concentration formed in an isolated manner from the gate electrode. An input voltage IN 1  is applied to the first FET 1, and an output voltage IN 2  of the first FET 1 is supplied to the second FET 2 which produces an output voltage OUT. This output voltage OUT is used as a driving signal for driving a load (not shown). 
     In FIG. 2, V DD1  and V SS1  respectively denote the high and low potential side power source voltages applied to the first FET 1, and V DD2  and V SS2  respectively denote the high and low potential side power source voltages applied to the second FET 2. 
     According to the present invention, the load is driven by the output voltage OUT of the second FET 2 which is of the non-self-aligned type. A FET having a lightly doped drain (LDD) structure is one example of the non-self-aligned type FET. In a FET having the LDD structure, the distance between the drain and source is long and the drain-source withstand voltage is large, e.g., approximately 10 V to 15 V. Hence, the potential difference between the power source voltages V DD2  and V SS2  can be made 10 V or greater provided that it is within the limit of the drain-source withstand voltage, and the amplitude of the output (driving) voltage OUT can be made 5 V or greater. 
     Next, a description will be given of an embodiment of the semiconductor integrated circuit according to the present invention, by referring to FIGS. 3, 4A and 4B. FIG. 3 shows a circuit diagram of the embodiment, FIG. 4A shows a cross section of a non-self-aligned type FET of the embodiment, and FIG. 4B shows a cross section of a self-aligned type FET of the embodiment. 
     In FIG. 3, the semiconductor integrated circuit includes a logic part 20 and a driver part 30. The logic part 20 includes three self-aligned type FETs 21, 22 and 23. The sources of the FETs 21 and 22 are connected in common to the drain of the FET 23, and the gate and the source of the FET 23 are respectively connected to the low potential side power source V SS20  which supplies a power source voltage V SS20  of -5.2 V, for example. In addition, the drain of the FET 21 is connected to the high potential side power source V DD20  which supplies a power source voltage V DD20  of 0 V, for example, and an output voltage V 20  is obtained from the drain of the FET 22. 
     On the other hand, the driver part 30 includes one non-self-aligned type FET 31 and resistors R 31 , R 32  and R 33 . The source of the FET 31 is connected to the drain of the FET 22, and the drain of the FET 31 is coupled to a high potential side power source V DD30  via the resistor R 31 . The gate of the FET 31 is connected to a node P 30  which connects the resistors R 32  and R 33 . In addition, the resistor R 32  is connected to a high potential side power source V DD31 , and the resistor R 33  is connected to a low potential side power source V SS30 . A driving voltage V 30  for driving a load (not shown) is output from the drain of the FET 31. 
     FIG. 4A shows the cross section of the non-self-aligned type FET 31 of the driver part 30. On the other hand, FIG. 4B shows the cross section of the self-aligned type FET of the logic part 20. For example, it is assumed for the sake of convenience that this self-aligned type FET is the FET 22. The FETs 31 and 22 are formed on a common compound semiconductor substrate 40 which is made of GaAs, for example. In other words, the FETs of the logic part 20 and the driver part 30 are formed on the same chip. In FIGS. 4A and 4B, &#34;A&#34; and &#34;B&#34; denote connections. 
     The self-aligned type FET 22 includes a drain electrode D 22 , a gate electrode G 22  and a source electrode S 22 . Two impurity regions 41 and 42 each have a high impurity concentration and are formed in self-alignment to the gate electrode G 22 . In addition, a channel region 43 is formed immediately below the gate electrode G 22  in a gap L 22  between the impurity regions 41 and 42. 
     The non-self-aligned type FET 31 includes a drain electrode D 31 , a gate electrode G 31  and a source electrode S 31 . Two impurity regions 44 and 45 having a high impurity concentration are formed in an isolated manner from the gate electrode G 31 . In addition, a channel region 46 is formed immediately below the gate electrode G 31  in a gap L 31  between the impurity regions 44 and 45. 
     The biggest structural difference between the self-aligned type FET 22 and the non-self-aligned type FET 31 is the different gaps L 22  and L 31  between the two impurity regions. For example, if it is assumed that the length of the gate electrode is approximately the same for the two FETs 22 and 31, the gap L 22  is always narrower than the gap L 31 . 
     The gap between the two impurity regions is one of the major factors which determine the drain-source withstand voltage of the FET, and the withstand voltage can be improved by increasing this gap. 
     The drain-source withstand voltage of the non-self-aligned type FET 31 is more than two times the drain-source withstand voltage of the self-aligned type FET 22. Generally, the drain-source withstand voltage of the self-aligned type FET is 4 V to 6 V, while the drain-source withstand voltage of the non-self-aligned type FET is 10 V to 15 V. 
     Hence, according to this embodiment, the source-drain voltage when the FET 31 is OFF can be increased to 10 V or greater because the FET 31 which has the large withstand voltage is used in the driver part 30, compared to approximately 5 V in the conventional case. As a result, the amplitude of the driving voltage V 30  which is obtained from the drain of the FET 31 can be made 5 V or greater. 
     When the non-self-aligned type FET 31 is used, the source resistance R 2  in particular becomes large because of the wide gap L 31 , and this large source resistance R s  may cause undesirable effects on the operating speed of the circuit. Hence, it is desirable to make the gate electrode length L a  of the self-aligned type FET as small as possible as shown in FIG. 5B, and to also make the gate electrode length L b  of the non-self-aligned type FET as small as possible as shown in FIG. 5A. Generally, the limit of the minimum gate electrode length L a  is approximately 0.8 μm, while the limit of the minimum gate electrode length L b  is approximately 0.25 μm. Hence, the substantial channel length of the non-self-aligned type FET can be reduced by the extremely small gate electrode length L b , thereby making it possible to improve the operating speed. 
     Next, a description will be given of an application of the present invention, by referring to FIG. 6. In FIG. 6, those parts which are the same as those corresponding parts in FIG. 3 are designated by the same reference numerals, and a description thereof will be omitted. 
     In FIG. 6, an optical modulator 100 modulates a 5 laser beam emitted from a laser diode 102 and produces an optical output. For example, the optical output of the optical modulator 100 is used to transmit information in an optical communication system. The optical modulator 100 needs to be driven by a relatively large driving voltage. For this reason, the semiconductor integrated circuit of the present invention is used to supply the output driving voltage V 30  of the driver part 30 to the optical modulator 100. In this particular case, the output signal of the optical modulator is fed back to the logic part 20 via a feedback circuit 104 in order to control the optical output of the optical modulator 100. 
     Of course, the load which may be driven by the output driving voltage of the driver part is not limited to the optical modulator, and the output driving voltage may be used to drive other kinds of loads. 
     Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.