Error detection and correction circuit
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to error detection and correction codes. More specifically, the present invention relates to multiple error detection and correction matrix codes. 
     While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility. 
     2. Description of the Related Art 
     A typical memory chip is a square array of data-storage cells. The 64K chip, for example, consists of an array of 256 by 256 data-storage cells. Each cell stores one bit, a 0 or a 1. The 0&#39;s and 1&#39;s stored in a memory chip are represented by the presence or absence of negative electric charge at sites in the silicon crystal. When a 0 is to be stored in a given cell, the potential well at the site is filled with electrons. When a 1 is to be stored, the well is emptied of electrons. When the cell is read, its negative charge is measured. If the charge exceeds a certain value, the stored bit is declared to be a 0, otherwise it is declared to be a 1. 
     Errors can occur when a cell loses its charge, or if an uncharged potential well acquires a charge. Hard errors occur when a given cell is stuck at 0 or stuck at 1 or toggling between 0 and 1. 
     Error correcting codes help correct most errors that occur when data is stored or read from computer memories. Error correcting codes, such as the Hamming Code, group data bits together with parity bits into a code word using an encoding algorithm. The parity bits act as checks for the data bits. Errors occurring in storing or reading of data bits from the computer memory are detected and corrected with a decoding algorithm. 
     Presently available high speed error detection and correction (EDC) chips for memory to CPU application perform single error correction/double error detection (SEC/DED). Many three and four bit errors are either ignored or miscorrected by these SEC/DED devices resulting in erroneous data. Chips which use polynomial or cyclic codes can detect these errors but are too slow for real time operation. For this reason there is a need in the art for an improved error correcting code. 
     SUMMARY OF THE INVENTION 
     The present invention substantially overcomes many of the problems associated with prior art error detection codes by providing a novel approach to detecting and correcting multiple bit errors. The invention is a system which organizes the data word into a matrix of n by m bits, where n is the number of m bit groups. Parity bits are generated for each column and each row. Single bit errors are detected and corrected. Double and triple bit errors are detected. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a matrix structure generated from a 128 bit data word. 
     FIG. 2 shows a block diagram of an illustrative implementation of a 128 bit data word parity bit encoder constructed in accordance with the teachings of the present invention. 
     FIG. 3 shows a block diagram of an illustrative implementation of a 128 bit data word decoder constructed in accordance with the teachings of the present invention. 
     FIG. 4 shows a block diagram of an illustrative implementation of a syndrome decoder constructed in accordance with the teachings of the present invention. 
    
    
     DESCRIPTION OF THE INVENTION 
     Illustrative embodiments and exemplary applications will now be described with reference to the accompanying drawings to disclose the advantageous teachings of the present invention. 
     The present invention is a system which organizes k bit data words into a matrix structure consisting of n+1 rows and m+1 columns, where k is the product of n and m. An illustrative matrix 8 is shown in FIG. 1 for a 128 bit data word. The matrix 8 consists of the 128 data bits D 1  -D 128  in 32 rows of 4 data bits each, parity bits N 1  -N 32 , and column parity bits C 1  -C 4  and CPP. Nibble parities N 1  through N 32  are generated by adding the 4 data bits in each row. An even number may be represented by a 0 for the nibble parity, whereas an odd number is represented by a 1 for the nibble parity. The column parity bits C 1  through C 4  are generated by adding the 32 data bits in each column. Again, an even number may be represented by a 0 and an odd number may be represented by a 1. The column parity parity CPP is generated in the same manner by adding the column parities C 1  through C 4 . 
     FIG. 2 shows a block diagram of an illustrative implementation of a 128 bit data word parity bit encoder constructed in accordance with the teachings of the present invention. In the preferred embodiment, the encoder 10 consists of a nibble parity generator 12 which outputs 32 nibble parity bits N 1  -N 32 , and a column parity generator 14 which outputs the 4 column parity bits C 1  -C 4 , in response to an input of 128 data bits. The nibble parity generator 12 adds data bits in each row and outputs a &#34;1&#34; for a nibble parity bit if the sum is odd or a &#34;0&#34; if the sum is even. The column parity generator 14 adds data bits in each column and outputs a &#34;1&#34; for a column parity bit if the sum is odd and a &#34;0&#34; if the sum is even. In the preferred embodiment, the nibble parity generator 12 may be implemented by 32 4-bit exclusive-OR (XOR) gates (not shown) generating nibble parities and the column parity generator 14 may be implemented by 4 32-bit XOR gates (not shown) generating column parities. By definition, the XOR gate is enabled only when an odd number of 1&#39;s appear at the inputs. The 4 column parities are input into a column parity parity bit generator 16 which may be implemented by a 4-bit XOR gate to generate a 33rd nibble parity which is input to a nibble check bit generator 18 along with the first 32 nibble parities. The nibble check bit generator 18 outputs 7 nibble check bits which are stored in a memory chip 20 along with the 128 bits of data and the 4 column parity bits. In the preferred embodiment, the nibble check bit generator may be implemented by a 33 bit modified hamming code. 
     FIG. 3 shows a block diagram of an illustrative implementation of a 128 bit data word decoder constructed in accordance with the teachings of the present invention. In the preferred embodiment, the 128 bit data word decoder 22 consists of a memory chip 24 which receives and stores the encoded data, i.e., the 128 bit data word, 4 column parity bits, and 7 nibble check bits from the data encoder 10. The 128 bit data word is output to a second nibble parity generator 26 and a second column parity generator 28 which generate 32 new nibble parities and 4 new column parities. The nibble parity generator 12 and the column parity generator 14 of the data encoder 10 may be used with appropriate switching circuitry to provide the 32 new nibble parities and the 4 new column parities. Nibble parities and column parities are generated in the same manner as in the data encoder 10. 
     The 4 column parity bits from the memory chip 24 are input to a second column parity parity generator 30 and the output is input to a nibble syndrome generator 32 along with the 32 new nibble parities and the 7 nibble check bits stored in the memory chip 24. 
     The nibble syndrome decoder 32 generates 7 new nibble check bits from the 32 new nibble parities and the new column parity parity bit, and compares the 7 newly generated nibble check bits to the 7 nibble check bits from the memory chip 24. Seven nibble syndrome bits are generated by the nibble syndrome decoder 32 by XORing the 7 new nibble check bits to the nibble check bits from the memory chip 24. In a similar manner, the 4 new column parity bits are XORed with the 4 column parity bits from the memory chip 24 in a column syndrome generator 34 which outputs 4 column syndrome bits. In the preferred embodiment of the 128 bit data word decoder 22, the nibble syndrome decoder 32 consists of a nibble check bit generator (not shown) and 7 2-bit XOR gates (not shown). The column syndrome generator 34 may be implemented by 4 2-bit XOR gates (not shown). The XOR gate outputs a &#34;1&#34; indicating an error when the inputs are different and outputs a &#34;0&#34; indicating no error when the inputs are the same. The 7 nibble syndrome bits and the 4 column syndrome bits are then input to a syndrome decoder 36. In the event the syndrome decoder 36 detects an error, an error corrector 38 shifts over a number of nibbles to the erroneous bit and corrects the error. 
     FIG. 4 shows a block diagram of an illustrative implementation of the syndrome decoder 36 constructed in accordance with the teachings of the present invention. The syndrome decoder 36 may be implemented by a 7-bit syndrome decoder 40, a 4-bit adder 42, an 11-bit OR gate 44, and an error decoder 46. The 7-bit syndrome decoder 36 uses a decode matrix to locate which nibble is in error or if a multiple error has occurred. The 4-bit adder 42 detects the number of 1&#39;s in the column syndrome bits and outputs either none, one, or multiple error. The error decoder 46 is a state machine which uses the outputs from the 7-bit syndrome decoder 40 and the number of column errors to decide what type of error occurred. The 11 bit OR gate 44 detects any 1&#39;s present in the 7 nibble syndrome bits and the 4 column parity bits. Inputs to the 11-bit OR gate 44 come directly from the column syndrome generator 34 and the nibble syndrome generator 32. A &#34;0&#34; output indicates all 0&#39;s and no detectable data errors in the data word and the 128 bit data word is outputted. 
     The error decoder 46 operates as follows: 
     If a single error is indicated in the 33rd bit then this means an error in nibble 32 which is a 4 column parity bit error or a syndrome check bit error. This causes Error Decoder to send CBE high but the error is not corrected. 
     If a multiple error is indicated by the 7 bit syndrome decoder or if the 4 bit adder indicates a multiple error then ME on the error decoder is sent high. The multiple error can not be corrected. 
     If a single bit error is indicated by the 7 bit syndrome decoder and 0 errors are indicated by the 4 bit adder then a multiple bit error has occurred and ME is sent high. The multiple error cannot be corrected. 
     If the 7 bit syndrome decoder indicates no error and the 4 bit adder indicates 1 error then a multiple bit error has occurred and ME is sent high. The multiple error can not be corrected. 
     If a single nibble error is indicated by the 7 bit syndrome decoder (part 40) and the 4 bit adder indicates (part 42) one column error then the error decoder changes nothing and only error from (part 44) is high. The error corrector corrects only if error is high and multiple error (ME) is low and check bit error (CBE) is low. The error corrector 38 uses the CSB (column syndrome bit) to shift over to an erroneous bit and correct the error. 
     Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications applications and embodiments within the scope thereof. For example, the invention is not limited to a specific number of data bits that can be encoded and decoded. The matrix can be expanded or compressed to handle a different number of data bits. 
     Further, the invention is not limited to the technique by which the desired logic is generated. Functionally equivalent logic may be used wherever applicable. In some cases, reverse logic may be implemented. 
     It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention.