Semiconductor memory device having an improved refresh operation
This is a continuation of application Ser. No. 07/468,438 filed Jan. 22, 1990 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which the period of time required for refreshing can be reduced. 
     2. Description of the Prior Art 
     Currently, a dynamic RAM (hereinafter, abbreviated as &#34;DRAM&#34;) is used as a semiconductor memory device with the greatest memory capacity, but its integration remains to be increased. In a DRAM, data are stored in memory cells using their capacitance. Because of this principle of holding data in memory cells, memory cells must be refreshed. Failure to refresh the memory cells results in the destruction of data stored in these cells. Further, the period of time for performing the refresh is prolonged with the advancement of the integration of a DRAM. Therefore, it has been demanded to shorten the period of time required for the refresh. Hereinafter, this period of time is referred to as &#34;refresh overhead time&#34;. 
     The refresh operation in a memory cell will be described with reference to FIGS. 13 and 14. In FIG. 14, shown are a memory cell MA, a sense amplifier SA, a word line W, a pair of bit lines b and /b, and a sense amplifier control circuit PLC. When the word line W is activated, data stored in the memory cell MA is read out to the pair of bit lines b and /b, and the sense amplifier SA is activated so that the read out data is amplified. Then, the amplified data is written back into the memory cell MA, thereby completing the refresh. In this way, the refresh is performed for each memory cell MA connected to the word line W, and therefore the length of the refresh overhead time depends on the number of word lines. 
     Referring to FIGS. 15-18, the refresh operation in a conventional semiconductor memory device will be described in more detail. The memory device shown in FIG. 15 comprises an input/output unit I/O, a pair of data lines D and /D, a memory block MB, a row decoder control circuit ROC, a column decoder control circuit COC, a row decoder control line RA, a column decoder control line CA, and a control line for a sense amplifier power source control circuit PLCL. The internal structure of the DRAM is illustrated in more detail in FIG. 16. In FIG. 16, CO is a column decoder, ROW is a row decoder, PLC is a sense amplifier power source control circuit, SA 1  -SA n  are sense amplifiers, SW 1  -SW n  are switching elements, SWC 1  -SWC n  are switching element control lines, b 1  -b n  and /b 1  -/b n  are bit line pairs, PL 1  is a first sense amplifier power source line, PL 2  is a second sense amplifier power source line, and W 1  -W n  are word lines. 
     In the DRAM shown in FIGS. 15 and 16, the refresh is performed sequentially from the memory cell MA connected to the word line W 1  to the one connected to the word line W n , in a predetermined unit of time, so that data are continuously rewritten in the memory cells. When the level of integration of a DRAM becomes higher, however, the refresh overhead time becomes longer, resulting in a shortening of the period of time for reading and writing data. More specifically, when comparing two memory devices one of which is greater in storage capacity by four times than the other, the refresh overhead time in the greater memory device ((b) of FIG. 17) is four times as long than the refresh overhead time ((a) of FIG. 17) in the smaller memory device. In a special type of DRAM such as a video memory, particularly, data in all memory cells must be sequentially read out and written, and, therefore, it is not possible to access all memory cells during the time when memory cells can retain their data, resulting in that the refresh times must be provided as shown in (b) of FIG. 18. If a DRAM has a small storage capacity, it is not necessary to provide such a refresh overhead time ((a) of FIG. 18). 
     As the level of integration of a DRAM becomes higher, the number of memory cells increases so that the refresh overhead time which is useless for the reading or writing operation is prolonged. To alleviate this problem, the number of refresh times is reduced in a highly integrated DRAM. This can be realized by improving the performance of memory cells, i.e., by lengthening the data hold time of the memory cells. In view of the recent strides in integration, however, further improvement of the performance of memory cells is nearly impossible. Hence, it is necessary to shorten the refresh overhead time. 
     In a DRAM, usually, memory cells are divided into several blocks as shown in FIG. 19. The DRAM of FIG. 19 comprises a row address decoder 201 for decording an external address signal, a refresh address counter 202 for generating a refresh address, an address change circuit 209; and memory blocks MB A  and MB B . The memory block MB A  includes a memory cell unit 203 and sense amplifiers 205. The other memory block MB B  includes a memory cell unit 204 and sense amplifiers 206. The address change circuit 209 changes an external address signal and an internal refresh address in accordance with a refresh request signal which is supplied when the refresh is to be performed. 
     The row address decoder 201 decodes an external address signal, and a write/read address is input to the address change circuit 209. The refresh address counter 202 generates an internal refresh address signal which is then supplied to the address change circuit 209. According to a refresh request signal, the address change circuit 209 changes the write/read address and the internal refresh address. In a write/read cycle, the address change circuit 209 outputs only a write/read address. This causes the corresponding word line in one memory block to be activated, and the potential change is amplified by a sense amplifier to write or read a memory cell. When the word line of the memory block MB A  is activated and the write or read is done in the memory block MB A , the word line of the address of the other memory block MB B  is not activated and the refresh of the address is not performed. When the refresh is to be performed, the refresh address counter 202 outputs the internal refresh address through the address change circuit 209. Then, the word lines of both the memory blocks MB A  and MB B   are simultaneously activated, and the potential changes on the word lines are amplified to refresh the memory cells of the address. After the refresh of the memory cells connected to one word line in both the memory blocks MB A  and MB B  is completed, the refresh address of the refresh address counter 202 is changed, and the refresh of the memory cells of the new refresh address is performed. In this way, all memory cells in the memory blocks MB A  and MB B  are sequentially refreshed. 
     When a memory block of a conventional DRAM is written or read, the refresh of a row address of other memory blocks in the DRAM cannot be performed. Therefore, the refresh overhead time is required for all word lines to refresh memory cells connected thereto, resulting in that the period of time for writing and reading is reduced. 
     SUMMARY OF THE INVENTION 
     The semiconductor memory device of this invention, which overcomes the above-discussed and numerous other disadvantages and deficiencies of the prior art, comprises a plurality of memory blocks, said memory blocks comprising: memory cells arranged in a matrix form; pairs of bit lines for selecting column addresses of said memory cells; word lines for selecting row addresses of said memory cells; sense amplifiers; and a sense amplifier control circuit for controlling said sense amplifiers, and further comprises: a control means for commonly controlling said word lines of all of said memory blocks; a selection means for selecting one or more blocks of said memory blocks to be subjected to the write and/or read operation; a first process means for performing the write and/or read operation in said selected memory blocks; and a second process means for performing the refresh operation in the unselected memory blocks. 
     In a preferred embodiment, the sense amplifier control circuit comprises a first portion for writing or reading, and a second portion for refreshing, said first portion being used in the write and/or read operation, and said second portion being used in the refresh operation. 
     The semiconductor memory device of this invention comprises, a plurality of memory blocks, said memory blocks comprising: memory cells arranged in a matrix form; pairs of bit lines for selecting column addresses of said memory cells; word lines for selecting row addresses of said memory cells; sense amplifiers; and a sense amplifier control circuit for controlling said sense amplifiers, and further comprises: a control means for commonly controlling said word lines of all of said memory blocks; and a process means for simultaneously performing the refresh operation in all of said memory blocks. 
     In a preferred embodiment, the sense amplifier control circuit comprises a first portion for writing or reading, and a second portion for refreshing, said first portion being used in the write and/or read operation, and said second portion being used in the refresh operation. 
     The semiconductor memory device of this invention comprises a plurality of memory blocks, said memory blocks comprising memory cells arranged in a matrix form, and further comprises: a selection means for selecting one or more blocks of said memory blocks to be subjected to the write and/or read operation; a process means for performing the write and/or read operation in said selected memory blocks; a refresh means for performing the refresh operation in the unselected memory blocks within the period of time of said write and/or read operation; a memory means for storing addresses of memory cells in said memory blocks, said memory cells being refreshed in said period of time of said write and/or read operation; another selection means for selecting memory cells which are not refreshed in said period of time of said write and/or read operation, on the basis of said stored addresses; and another refresh means for refreshing said selected memory cells within a period of time designated for refreshing. 
     In a preferred embodiment, the memory device further comprises a signal means for generating a signal which indicates that all of said selected memory cells have been refreshed up to the end of said period of time. 
     Thus, the invention described herein makes possible the objectives of (1) providing a semiconductor memory device in which the refresh overhead time is reduced; (2) providing a semiconductor memory device in which the refresh overhead time is not required; (3) providing a semiconductor memory device in which the period of time for writing or reading can be prolonged; and (4) providing a semiconductor memory device in which the increase of a current level can be suppressed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     This invention may be better understood and its numerous objects and advantages will become apparent to those skilled in the art by reference to the accompanying drawings as follows: 
     FIG. 1 is a block diagram showing a first embodiment of the semiconductor memory device according to the invention. 
     FIG. 2 is a block diagram showing a memory block of the memory device of FIG. 1. 
     FIG. 3 is a circuit diagram of a sense amplifier power source control circuit used in the memory device of FIG. 1. 
     FIG. 4 is a circuit diagram of a sense amplifier used in the memory device of FIG. 1. 
     FIGS. 5(a-c) are diagrams showing the timing in a conventional memory device and the memory device of FIG. 1. 
     FIGS. 6(a-c) are diagrams showing the write/read time and refresh overhead time in a second embodiment and a conventional memory device. 
     FIG. 7 is a block diagram showing a third embodiment of the semiconductor memory device according to the invention. 
     FIG. 8 is a block diagram showing a memory block of the memory device of FIG. 7. 
     FIG. 9 is a circuit diagram of a sense amplifier power source control circuit used in the memory device of FIG. 7. 
     FIG. 10 is a graph illustrating the amount of current flowing through a conventional memory device, and the first and third embodiments. 
     FIG. 11 is a block diagram showing a fourth embodiment of the semiconductor memory device according to the invention. 
     FIG. 12 is a diagram illustrating the timing in a conventional memory device and in the fourth embodiment. 
     FIG. 13 is a timing chart of the refresh operation. 
     FIG. 14 is a circuit diagram showing a memory cell in a DRAM. 
     FIG. 15 is a block diagram of a conventional DRAM. 
     FIG. 16 is a block diagram showing a memory block of the conventional DRAM of FIG. 15. 
     FIGS. 17(a-b) are diagrams illustrating a refresh overhead time in conventional DRAMs. 
     FIGS. 18(a-b) are diagrams illustrating the timing of the refresh in a conventional video memory. 
     FIG. 19 is a block diagram showing a conventional DRAM. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Example 1 
     With reference to FIGS. 1-5, the first embodiment of the invention will be described. This embodiment is a semiconductor memory device which is useful as a video memory. The outline of the memory device is shown in FIG. 1. The memory device of FIG. 1 comprises an input/output unit I/O, a pair of data lines D and /D, four memory blocks MB A  -MB D , a row decoder control circuit ROC, a column decoder control circuit COC, a row address bus RA, column address bus CA, and a control line for a sense amplifier power source control circuit PLCL. To each of the memory blocks MB A  -MB D  connected are one control line of the column address bus CA, m number of the control lines of the row address bus RA common to each block, and the control line PLCL. The column address bus CA includes 41 control lines in total. The column address bus CA conveys the output of the column decoder control circuit COC, and the row address bus RA conveys the output of the row decoder control circuit ROC. The memory blocks MB A  -MB D  are also connected to the input/output unit I/O through the pair of data lines D and /D. 
     The memory blocks MB A  -MB D  have a structure as shown in FIG. 2, and comprise a column decoder CO, a row decoder ROW, a sense amplifier power source control circuit PLC, sense amplifiers SA 1  -SA n , switching elements SW 1  -SW n , switching element control lines SWC 1  -SWC n , bit line pairs b 1  -b n  and b 1  -/b n , word lines W 1  -W n , a first power source line PL 1 , and a second power source line PL 2 . The bit line pairs b 1  -b n  and /b 1  -/b n  are arranged so as to perpendicularly intersect with the word lines W 1  -W n . At the intersections, memory cells MA are disposed. The row decoder ROW controls the word lines W 1  -W n , and selects one of the word lines W 1  -W n . The bit line pairs b 1  -b n  and /b 1  -/b n  are coupled to the inputs of the sense amplifiers SA 1  -SA n . The outputs of the sense amplifiers SA 1  -SA n  are connected to the pair of data lines D and /D via the switching elements SW 1  -SW n  which are controlled by outputs SWC 1  -SWC n  of the column decoder CO. The control circuit PLC controls the sense amplifiers SA 1  -SA n  through the first and second power source lines PL 1  and PL 2 . 
     FIG. 3 shows the sense amplifier power source control circuit PLC. When the state of a signal line PLCL for the control circuit PLC becomes HIGH, MOS transistors MP 3  and MN 3  are turned ON, and power is supplied to the power source lines PL 1  and PL 2 . In FIG. 3, IV 1  is an inverter. The sense amplifiers SA 1  -SA n  have the structure shown in FIG. 4, and comprise four MOS transistors MP 1 , MP 2 , MN 1  and MN 2 . When the power source lines PL 1  and PL 2  are energized, the sense amplifiers SA 1  -SA n  are activated to sense data which are read out to the bit line pairs b 1  -b n  and /b 1  -/b n . 
     The operation of the memory device of FIG. 1 will be described. As mentioned above, the memory device of FIG. 1 is a vidoe memory in which data stored in all memory cells are sequentially accessed to be written or read out. For example, the memory block MB A  is selected to be written or read out, and the remaining memory blocks MB B  -MB D  to be refreshed. Since the signal on the row address bus RA and the control signal line PLCL are common to all the memory blocks MB A  -MB D , the row decoders ROW and the power source control circuits PLC of the memory blocks MB A  -MB D  are commonly controlled, and, in all the memory blocks MB A  -MB D  a word line W m  having an address common to the memory blocks is selected. When the sense amplifiers SA 1  -SA n  are activated, data stored in the memory cells connected to the word line W m  in the memory blocks MB A  -MB D  are read out to the the bit line pairs b 1  -b n  and /b 1  -/b n , and sensed and amplified. Among the amplified data, the data of the memory block MB A  only is transferred to the pair of data lines D and /D through the switching elements SW 1  -SW n , and the data of the remaining memory blocks MB B  -MB D  are rewritten respectively in the original memory cells (i.e., the refresh of the memory blocks MB B  -MB D  is performed). In this way, the refresh of the memory blocks MB B  -MB D  is automatically performed while writing and reading the memory block MB A . This is schematically illustrated in (c) of FIG. 5. In FIG. 5, (a) shows the timing in a conventional memory device having a small storage capacity, and (b) the timing in another conventional memory device having a large storage capacity (four times that of the small DRAM of (a)). As shown in FIG. 5, in a conventional large memory device of (b), refresh overhead time is required. In contrast, according to this embodiment, data can be rewritten without providing the refresh overhead time. According to the invention, it is not necessary to provide refresh overhead time even if the storage capacity or number of memory blocks is increased. 
     Example 2 
     This embodiment is a DRAM having a configuration which is similar to that of the embodiment of FIG. 1, but is designed so that all the memory blocks MB A  -MB D  are refreshed simultaneously. In this configuration, therefore, the refresh is performed against four word lines in a bundle. This means that the apparent number of the word lines is reduced to one-fourth. Even if the DRAM of the embodiment has a fourfold storage capacity as compared with a conventional small DRAM ((a) of FIG. 6), therefore, the refresh overhead time in this embodiment ((c) of FIG. 6) is not increased as it is in a conventional large DRAM ((b) of FIG. 6), resulting in that it is not necessary to decrease the write/read time in a unit of time nor to reduce the number of the refresh operations. Consequently, conditions such as the retention time which must be considered in the design of a DRAM can be made less severe. In other words, according to this embodiment, the refresh overhead time can be shortened with the increase of the number of memory blocks, and the following expression can be held: ##EQU1## 
     Example 3 
     FIG. 7 illustrates the third embodiment of this invention. In the above-mentioned construction of the first embodiment, all of the four memory blocks are activated simultaneously, that is, one word line and sense amplifiers in each memory block are driven, so that, as shown in FIG. 10, the current is increased fourfold as compared with a conventional memory device. The increased current is a problem in itself, and may cause a malfunction due to the voltage drop of the power source line, and the reduction of the performance margin, and further adversely affects the design of a power source circuit such as a down converter. The embodiment of FIG. 7 can eliminate these problems. 
     In the memory device of FIG. 7, control lines PLCL A  -PLCL D  are respectively connected to the sense amplifier power source control circuits PLC of the memory blocks MB A  -MB D , and refresh control lines RPLCL A  -RPLCL D  for sense amplifier power source control circuits PLC are further provided. As shown in FIG. 9, each of the sense amplifier power source control circuits PLC is divided into a write/read portion PLCA connected to one of the control lines PLCL A  -PLCL D  and a refresh portion PLCB connected to one of the refresh control lines RPLCL A  -RPLCL D . The write/read portion PLCA comprises a P-channel MOS transistor MP 4 , an N-channel MOS transistor MN 4 , and an inverter IV 2 . The refresh portion PLCB comprises a P-channel MOS transistor MP 5 , an N-channel MOS transistor MN 5 , and an inverter IV 3 . 
     The operation of the memory device of FIG. 7 will be described by illustrating a case when the memory device is used as a video memory in which memory cells are sequentially accessed. For example, the memory block MB A  is selected to be written or read out, and the remaining memory blocks MB B  -MB D  to be refreshed. In the memory block MB A , the write/read portion PLCA is used, and, in the memory blocks MB B  -MB D , the refresh portions PLCB are used. As shown in FIG. 8, one word line W n  is connected to many memory cells MA. In the memory block MB A , memory cells MA connected to one word line W n  are sequentially accessed, and therefore a sufficient time is required to access all memory cells MA connected to one word line W n . By contrast, the refresh is simultaneously performed on memory cells MA connected to one word line W n . In the memory blocks MB B  -MB D , hence, it is possible to slowly perform the refresh while memory cells MA of the memory block MB A  are sequentially accessed, enabling the sense amplifier power source control circuits PLC to be designed in a small size. Consequently, the current or power consumed in this embodiment can be reduced as compared with the memory device of FIG. 1, as shown in FIG. 10. 
     In the sense amplifier power source control circuits PLC, the transistors MP 5  and MN 5  of the refresh portion PLCB are designed so as to occupy a relatively small size as compared with the transistors MP 4  and MN 4  of the write/read portion PLCA, thereby suppressing the current flowing in the refresh. Since the load capacitance caused by the pair of data lines D and /D, etc. connected to the sense amplifiers SA 1  -SA n  must be charged by the sense amplifiers within a unit of time, it is required to construct the transistors MP 4  and MN 4  of the write/read portion PLCA in a somewhat large size. 
     As described above, according to the embodiment, the power consumption can be suppressed even if a plurality of memory blocks are simultaneously refreshed. 
     Example 4 
     FIG. 11 shows a DRAM according to the invention. The DRAM of FIG. 11 comprises two memory blocks MB A  and MB B , and further comprises: a row address decoder 101 for decording an external address signal, a first refresh address counter 111 for generating an internal refresh address for the memory block MB A  ; a second refresh address counter 112 for generating an internal refresh address for the memory block MB B  ; and an address change circuit 109. The memory block MB A  includes a memory cell unit 103 and sense amplifiers 105. The other memory block MB B  includes a memory cell unit 104 and sense amplifiers 106. The address change circuit 109 changes an external address signal and an internal refresh address in accordance with a refresh request signal which is supplied when the refresh is to be performed. 113 is a refresh end signal generating circuit which outputs a refresh end signal indicating the completion of refresh of all blocks, in accordance with a signal from the refresh address counters 111 and 112. 
     The refresh operation in the DRAM of FIG. 11 will be described. When data is to be written or read out from the memory block MB A , the row decoder 101 decodes an external address signal, and the decoded external address signal is supplied to the address change circuit 109. The address change circuit 109 outputs a write or read address to activate the corresponding word line in the memory block MB A , and the writing or reading is performed in the memory block MB A . At the same time, the refresh address counter 112 outputs internal refresh addresses in a predetermined sequence to the memory block MB B , through the address change circuit 109. The refresh is conducted sequentially in the memory block MB B , while the writing or reading is performed in the memory block MB A . On the other hand, when data is to be written or read out from the memory block MB B , the row decoder 101 decodes an external address signal, and the decoded external address signal is supplied to the address change circuit 109. The address change circuit 109 outputs a write or read address to activate the corresponding word line in the memory block MB B , and the writing or reading is performed in the memory block MB B . At the same time, the refresh address counter 112 outputs internal refresh addresses in a predetermined sequence to the memory block MB A , through the address change circuit 109. The refresh is conducted sequentially in the memory block MB A , while the writing or reading is performed in the memory block MB A . 
     According to this embodiment, one memory block is refreshed while conducting the writing or reading of another memory block, and each of the refresh address counters 111 and 112 stores addresses of the corresponding memory block which have been subjected to the refresh. In accordance with the addresses stored in each refresh address counter, memory cells which have not been refreshed in the writing or reading operation are refreshed in the refresh overhead time. Since it is not necessary to refresh all memory cells during the refresh overhead time, the length of the refresh overhead time can be reduced. 
     In FIG. 12, (a) shows the refresh overhead time in a conventional DRAM, and (b) the refresh over head time in this embodiment. Numerals 114 and 116 indicate the period of time for writing or reading, and numerals 115 and 117 the refresh overhead time, in the conventional DRAM and this embodiment, respectively. As shown in (a) of FIG. 12, the refresh in the conventional DRAM is conducted for all memory cells during the refresh overhead time 115, and therefore the length of the refresh overhead time 115 is constant and relatively long. In contrast, according to this embodiment, it is not necessary to refresh all memory cells during the refresh overhead time 117. Hence, the length of the refresh overhead time 117 is not constant, and is shorter than the refresh overhead time 115 of the conventional DRAM. According to this embodiment, consequently, the length of the period of time for writing and reading can be increased. 
     When the refresh for all memory cells in a memory block has been completed within a refresh overhead time period, the refresh address counter 111 or 112 corresponding to the memory block outputs a memory block refresh end signal indicative of the completion of the refresh of all memory cells of the memory block, to the refresh end signal generating circuit 113. After receiving the memory block refresh end signals from all of the refresh address counters (i.e., 111 and 112), the refresh end signal generating circuit 113 generates a refresh end signal which indicates that all memory cells have been refreshed. This refresh end signal is supplied to the outside of the chip through a pin, so that an external device such as a CPU can detect the completion of the refresh, thereby enabling the process to transfer smoothly and without loss of time to the write/read operation. 
     The embodiment of FIG. 11 is provided with two memory blocks, but in the invention the number of memory blocks can be freely selected. 
     According to the embodiment, memory cells of one or more memory blocks which are not selected to be written or read are refreshed in synchronism with the writing or reading of memory cells of other memory blocks which are selected to be written or read, thereby shortening the refresh overhead time. When the refresh overhead time is not zero, the addresses of the memory cells which have been refreshed in a write/read time are stored. Then, memory cells of other memory blocks which have not been refreshed in said write/read time are refreshed, using the stored address of memory cells, thereby reducing the refresh overhead time. In other words, the period of time when the write/read operation is disabled can be shortened so that the usage efficiency of a DRAM is effectively improved. 
     It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be construed as encompassing all the features of patentable novelty that reside in the present invention, including all features that would be treated as equivalents thereof by those skilled in the art to which this invention pertains.