Burst phase detection circuit
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a burst phase detection circuit, in particular, relates to a burst phase detection circuit suitable for burst lock loop of a color video signal. 
     2. Description of the Prior Art 
     Color video signals contain a color signal where a carrier is modulated with first and second color difference signals. To digitally demodulate this color signal, the phase of a sampling clock for demodulating a particular color should be in synchronization with that of a color burst signal being input. If the phase of the sampling clock is not in synchronization with that of the color burst signal, the sampling value, that is, the demodulation output contains an error. Thus, the color cannot be correctly reproduced. With a conventional technique for controlling the phase of a sampling clock, data of the color burst signal being digitized is converted into an analog DC value by means of a D/A converter. Thereafter, the burst lock loop is controlled in accordance with the DC value. 
     The above mentioned prior art disadvantageously requires a D/A converter and the various associated circuit blocks for controlling the phase synchronization in accordance with the color burst signal of the sampling clock. Since it is difficult to include the D/A converter and the associated circuit blocks along with the circuit blocks for the phase control function of the sampling clock in an IC chip, the D/A converter and the associated circuit blocks should be externally provided. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     Therefore, an object of the present invention is to provide a burst phase detection circuit which allows the phase of a sampling clock to be in synchronization with a color burst signal in a simpler construction than the prior art, namely, without the necessity of a D/A converter and the various associated circuit blocks. 
     According to an aspect of the present invention, there is provided a burst phase detection circuit for receiving input signals including a color signal, which is produced by modulating a carrier with a first color difference signal and a second color difference signal, and a burst signal with a particular phase relation with the carrier and for generating a sampling pulse which is in synchronization with the burst signal comprising, a first sampling circuit for sampling a value during a period of the burst signal, said valve being a digital signal which is obtained by demodulating the modulated color signal with one of demodulation axes of the first color difference signal and the second color difference signal a second sampling circuit for sampling a value during a period of the burst signal in a horizontal period which has not been sampled by the first sampling circuit, the demodulated digital signal is supplied to the second sampling circuit, a digital addition circuit for adding an output signal from the first sampling circuit and an output signal from the second sampling circuit, and a detection circuit for digitally detecting the direction and amount of a phase difference between generated sampling pulse and the burst signal of the input signals in accordance with an output of the digital addition circuit. 
     The above, and other, objects, features and advantages of the present invention will become readily apparent from the following detailed description thereof which is to be read in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a burst phase detection circuit according to the present invention; 
     FIG. 2 is a block diagram of a circuit block for generating a sampling clock; 
     FIGS. 3A and 3B together comprise a schematic diagram showing sampling states of two adjacent lines; 
     FIG. 4 is a schematic diagram describing phase rotation in accordance with a color burst signal; 
     FIG. 5 is a schematic diagram describing an output of the burst phase detection circuit of FIG. 1 under the condition that the phase of the sampling clock is faster than that of the color burst signal in the clockwise direction; and 
     FIG. 6 is a schematic diagram describing an output of the burst p detection circuit of FIG. 1 under the condition that the phase of the sampling clock is faster than that of the color burst signal in the counterclockwise direction. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Now, an embodiment according to the present invention will be described with reference to FIGS. 1 to 5. FIG. 1 is a block diagram showing the construction of a burst phase detection circuit. 
     Before describing the details of the embodiment, the fundamental concept of the present invention is discussed. According to the present invention, by digitally adding levels of signal portions according to chroma signals such as color burst signals BTc of color difference signals (R-Y) which are demodulated on two adjacent lines, the direction and the amount of the phase difference between the sampling clock SCK and the color burst signal BTc at that time are detected. In other words, when the phase of the sampling clock SCK is in synchronization with that of the color burst signal BTc, the component of the color difference signal (R-Y) is not output when the color difference signal (R-Y) is in accordance with the color burst signal BTc, namely during a period TBU. However, when the sampling clock SCK is not in synchronization with the color burst signal BTc, namely, when there is a phase difference, the component of the color difference signal (R-Y) is output during the period TBU (while the color difference signal (R-Y) is in accordance with the color burst signal BTc). Therefore, when the polarity of the phase of the color difference signal (R-Y) and the amount of phase difference are obtained, the direction and amount of the phase difference between the color burst signal BTc and the sampling clock SCK can be obtained. The information concerning the direction and amount of the phase difference are output as a PWM signal. The phase of the sampling clock SCK is controlled in accordance with the output of the PWM signal. 
     In the construction as shown in FIG. 1, data DRY of a color difference signal (R-Y) which has been demodulated and digitized is supplied to a first sampling circuit 2 and a second sampling circuit 3 through a terminal 1. The data DRY is represented in for example two&#39;s complement notation. 
     With reference also to FIGS. 3A and 3B first sampling circuit 2 samples the data DRY during a period TBU in accordance with a color burst signal BTc by means of a sampling pulse PSb which is supplied through a terminal 4. The resultant signal is supplied to an addition circuit 5. The first sampling circuit 2 samples data DRYn of an n-th line which is the current line as shown in FIGS. 3A and 3B. In other words, when the video signal for use is in the NTSC system, a sampling value VbN of an n-th line, which is the current line, is obtained as shown in FIG. 3A. On the other hand, when the video signal for use is in the PAL system or in the PAL-M system, a sampling value VbP of the data DRYn of the n-th line, which is the current line, is obtained as shown in FIG. 3B. 
     The second sampling circuit 3 comprises a 1 H delay circuit 6 and a sampling circuit 7. The 1 H delay circuit 6 delays the supplied data DRY for one horizontal scanning period and supplies the resultant signal to the sampling circuit 7. The sampling circuit 7 samples the data DRY during the period TBU in accordance with the color burst signal BTc by means of the sampling pulse PSa which is supplied through a terminal 8 and supplies the resultant signal to the addition circuit 5. 
     The second sampling circuit 3 samples data DRY(n-1) of an (n-1)th line which is a 1 H earlier line as shown in FIG. 3. In other words, when the video signal for use is in the NTSC system, a sampling value VaN of the data DRY(n-1) of the (n-1)th line, which a 1 H earlier line, is obtained as shown in FIG. 3A. On the other hand, when the video signal for use is in the PAL system or in the PAL-M system, a sampling value VaP of the data DRY(n-1) of the (n-1)th line, which a 1 H earlier line, is obtained as shown in FIG. 3B. 
     The addition circuit 5 adds the data DRYn supplied from the first sampling circuit 2 and the data DRY(n-1) supplied from the second sampling circuit 3. In other words, the addition circuit 5 adds the sampling value vbN (or VbP) and the sampling value VaN (or VaP). The obtained addition output SUM is supplied to a polarity detection Circuit 9 and an absolute value circuit 10. 
     The sampling value VaP or VbP shown in FIG. 3B is used when the video system for use is in the PAL system or the PAL-M system. In this case, unlike the NTSC system, since the polarity of the color difference signal (R-Y) is inverted line by line, the polarity of the data DRYn or DRY(n-1) supplied from the second sampling circuit 3, which is the polarity of the sampling value vaP or VbP, is inverted line by line as shown in FIG. 3B. 
     The polarity detection circuit 9 detects the polarity of the data in accordance with the MSB (sign bit) of the addition output SUM represented in the two&#39;s complement notation and latches the resultant value. The polarity detection circuit 9 outputs a signal SIN which represents the polarity to a tri-state inverter 11. The polarity represents the advance and delay of the phase of the sampling clock against that of the color burst signal BTc. For example, the polarity &#34;+&#34; represents that the demodulation axes formed with the color difference signals (R-Y) and (B-Y) are rotated in the clockwise direction CW. On the other hand, for example, the polarity &#34;-&#34;  represents that the demodulation axes are rotated in the counterclockwise direction CCW. 
     The absolute value circuit 10 calculates the absolute value of the addition output SUM and supplies the resultant value to a gate control circuit 13. When the gate control circuit 13 receives the absolute value of the addition output SUM supplied from the absolute value circuit 10, it holds the absolute value and counts clock pulses supplied through a terminal 14 in accordance with the absolute value. While the gate control circuit 13 is counting the clock pulses, the output signal level of the circuit 13 goes low thereby controlling the inverter 11. Therefore, while the clock pulses in accordance with the absolute value of the addition output SUM are being counted, the inverter 11 outputs a polarity inverted signal SIN*, which is held by the polarity detection circuit 9 (in this specification, the negative logic symbol is represented with *), as a PWM signal from a terminal 15. The pulse width WT of the signal SIN* is defined by the absolute value of the addition output SUM as shown in FIG. 5 and FIG. 6 and as was described above. The inverter 11 inverts the output of the polarity detection circuit 9 so as to offset the advance and delay of the phase of the sampling clock SCK against that of the color burst signal BTc. 
     As shown in FIG. 4, when the phase of the sampling clock SCK differs from that of the color burst signal BTc in the clockwise direction CW, the signal SIN* which is in the low level is output as shown in FIG. 5. On the other hand, when the former phase differs from the later phase in the counterclockwise direction CCW as shown in FIG. 4, the signal SIN* which is in the high level is output. When the former phase matches the latter phase without phase difference, high impedance Hi-Z takes place. Therefore, the more the addition output SUM approaches &#34;zero&#34;, the more the phase of the sampling clock SCK becomes synchronous with that of the color burst signal BTc. Thereby, synchronous lock takes place. 
     The above mentioned signal SIN* is supplied to an integration circuit 22 comprising a resister R and a condenser C through a terminal 21 as shown in FIG. 2 thereby producing a DC voltage. The DC voltage is supplied to a variable delay circuit 23 as a control signal VDC. On the other hand, the color burst signal BTc0 which is successively generated in accordance with the color burst signal BTc is supplied to the variable delay circuit 23 through a terminal 24. The variable delay circuit 23 controls the phase of the color burst signal BTc0 in accordance with the level of the control signal VDC. In other words, the variable delay circuit 23 generates a color burst signal BTc1 for offsetting the difference of the phase of the sampling clock SCK against that of the color burst signal BTc and supplies the color burst signal BTc1 to a phase comparator 27 of the PLL circuit 26. 
     The PLL circuit 26 is used as a frequency synthesizer. The phase comparator 27 compares the phase of the color burst signal BTc1 with a signal S28 having a color subcarrier frequency fsc, the signal S28 being supplied from a frequency division circuit 28 thereby generating a phase error ER. The phase error ER is converted into a DC voltage with a low pass filter 29 and then supplied to a VCO 30. 
     The VCO 30 generates a signal S30 (4 fsc) with four phase as the color burst signal BTc1 in accordance with the output of the low pass filter 29 and outputs the signal S30 from a terminal 31. In addition, the signal S30 is supplied to the frequency division circuit 28. Thereby, the sampling clock SCK is generated in accordance with the signal S30 with frequency (4 fsc). The frequency division circuit 28 divides the frequency of the signal S30 by 4 thereby generating a signal S28. The signal S28 is supplied to the phase comparator 27 where the above mentioned phase comparison is performed. 
     In the above mentioned embodiment, the data DRYn and DRY(n-1) are digitally added during the period TBU, namely, when the color difference signals (R-Y) being demodulated and sampled on the adjacent n-th line and the (n-1)th line are in accordance with the color burst signals BTc. Thereby, the direction and amount of the phase difference between the sampling clock SCK and the color burst signal BTc at that time can be detected. The information is output as the PWM signal. With the PWM signal, the phase of the sampling clock SCK can be synchronized with the color burst signal BTc. Thus, the D/A converter and the associated circuit blocks which are required in the prior art can be omitted. Moreover, the phase of the sampling clock SCK can be synchronized with the color burst signal BTc in a very simple construction. Consequently, without the necessity D/A converter and the associated circuit blocks which are externally provided in the prior art, a circuit block with for synchronizing the sampling clock SCK with the color burst signal BTc can be constructed with an IC chip. 
     Furthermore, according to the above mentioned embodiment, the present invention can be applied to each of the NTSC system, PAL system, and the PAL-M system in the same construction. 
     The burst phase detection circuit according to the present invention calculates color difference signals of two adjacent lines, detects the direction and amount of phase difference between the sampling clock and the color burst, outputs the resultant signal as a PWM signal, and controls the sampling clock with the PWM signal so that the phase of the sampling clock is in synchronization with that of the color burst signal. Thus, the burst phase detection circuit can synchronize the sampling clock with the color burst signal in a very simple construction without the necessity of a D/A converter and the associated circuit blocks which are required in the prior art. Therefore, without the necessity for a D/A converter and the associated circuit blocks which are externally provided, a circuit block for synchronizing the sampling clock with the color burst signal can be constructed as an IC chip. 
     Having described a specific preferred embodiment of the present invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to that precise embodiment, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope or the spirit of the invention as defined in the appended claims.