Color signal contour compensator for matching the rise times of color and luminance signals of a video signal to produce sharper images
FIELD OF THE INVENTION 
     The present invention relates to a color signal contour compensator in video apparatuses and, more particularly, to a color signal contour compensator for matching the transient time (rise time) of a color signal to the transient time (rise time) of a luminance signal so as to digitally process the contour compensation of the color signal in video apparatuses such as video cassette recorders and televisions. 
     BACKGROUND OF THE INVENTION 
     Generally, as shown in FIG. 1, a video signal processor for next generation digital video apparatuses, such as high-resolution digital televisions and high-resolution digital video cassette recorders, converts an analog composite video signal input from an input source (not shown in FIG. 1) into a digital signal in an A/D converter 10. The digital video signal is digitally processed by first and second signal processors 20 and 30 and the digital video signal is output as luminance and color difference signals Y, R-Y and B-Y to a D/A converter 40. D/A converter 40 then converts the luminance and color difference signals into R, G and B analog color signals. 
     As shown in FIG. 2A, the normal transient rise time (hereinafter referred to as rise time) of luminance signal Y output from first signal processor 20 is about 150 nanoseconds (nsec) while, as shown in FIG. 2B, the rise time of color difference signals R-Y and B-Y output from the second signal processor 30 is about 800 to 1200 nsec. 
     The frequency bandwidth of a color difference signal is much smaller than that of a luminance signal. In a standard television system, the bandwidth of the color signal is smaller than that of the luminance signal by about a factor of five. 
     In other words, since the transmission frequency bandwidth of a color subcarrier is relatively narrow and the transient time of the color signal is about 5 times longer, as compared with that of the luminance signal, if the color is abruptly changed, the color edge becomes unclear. 
     According to the above apparatus, since the rise times of the color difference and luminance signals do not match and the rise time of the color difference signal is far longer than that of the luminance signal, when the digital luminance and color difference signals are converted into analog video signals to be displayed on a display, the sharpness of a picture&#39;s edge is reduced, resulting in reduced picture quality. 
     A circuit for steepening the transient slope of the color signal is disclosed in Japanese Laid-Open Patent Publication SHO 61-244186, which consists of a slope detector, a memory, a switch and a timing controller. Time threshold value and amplitude threshold value signals are supplied to the slope detector so as to steepen the slope of the color signal for operating conditions which are above the amplitude threshold value and below the time threshold value. However, the transient time of the color signal does not always match that of the luminance signal in the above mentioned apparatus. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the present invention to provide a color signal contour compensator for digitally processing signals so as to match the rise times of the color and luminance signals using a time delay device. 
     This and other objects, features and advantages of the present invention are provided by a color signal contour compensator including an input path, through which a composite video signal is provided, signal processors for processing the composite video signal into digital color and luminance signals, a color signal rise time compensator for detecting the rise time of the color signal output from the signal processors and generating a delay control signal of a predetermined level when the rise time of the color signal equals the rise time of the luminance signal at a time point having a predetermined amplitude, a converter for converting the color signal of the color and luminance signals output from the color signal rise time compensator into an analog signal during a period corresponding to an excited level of the delay control signal so as to output the color and luminance signals as analog red, green and blue signals, a controller for supplying a predetermined amplitude absolute value of the color signal, a rise time value of the luminance signal detected by the second signal processor, and delay data for delaying transmission of the luminance and color signals to the color signal rise time compensator for a predetermined period. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above object and other advantages of the present invention will become more apparent by describing in detail a preferred embodiment of the present invention with reference to the attached drawings, in which: 
     FIG. 1 is a block diagram of a conventional digital video signal processor; 
     FIGS. 2A and 2B illustrate the operational waveforms of the digital video signal processor of FIG. 1; 
     FIG. 3 is a block diagram of one embodiment of the color signal contour compensator of the present invention; 
     FIG. 4 is a detailed block diagram of the color signal rise time compensator of FIG. 3; 
     FIG. 5 is a block diagram of the D/A converter of FIG. 3; 
     FIGS. 6A through 6G illustrate the operational waveforms of the color signal rise time compensator of FIG. 4. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring to FIG. 3, an A/D converter 100 converts a composite video signal input from a not-shown signal input source into a digital signal according to an A/D clock signal output from a microcomputer 600 via a control bus line. 
     Signal processors 200 and 300 convert the digital composite vide signal into luminance and color signals Y and C. 
     A color signal rise time compensator 400, as illustrated in FIG. 4, comprises a color signal delay circuit 401 and a first luminance signal delay circuit 402 for delaying the color signal and luminance signal, respectively, output from signal processors 200 and 300 for corresponding periods according to delay data transmitted from microcomputer 600 via a control bus line, using a time delay device such as a shift register. Compensator 400 also includes a second luminance signal delay circuit 403 for re-delaying the once delayed luminance signal output from first luminance signal delay circuit 402 for a predetermined period, a color signal nibble demultiplexer 404 for converting the four-bit color signal output from color signal delay circuit 401 into an eight-bit signal, a color signal nibble multiplexer 405 receiving the four-bit color signal output from color signal delay circuit 401 and the eight-bit color signal output from color signal nibble demultiplexer 404 for converting them into a four-bit color signal, a first color difference signal separator 406 consisting of a demultiplexer which separates the eight-bit color signal C output from color signal nibble demultiplexer 404 into color difference signals R-Y and B-Y, R-Y and B-Y. Preferably, compensator 400 further includes interpolation filters 407 and 408 for converting the eight-bit color difference signals R-Y and B-Y into ten-bit color difference signals, a control bus interface 409 for providing an amplitude absolute value transmitted from microcomputer 600 via the three-bit control bus line to first and second rise time detectors 410 and 411 as a seven-bit signal, first and second rise time detectors 410 and 411, each consisting of a digital comparator for comparing the amplitude absolute value output from control bus interface 409 with the amplitudes of color difference signals R-Y and B-Y output from R-Y and B-Y interpolation filters 407 and 408, and a hold pulse generator 412 for generating a HOLD PULSE signal according to the output from first and second rise time detectors 410 and 411. 
     D/A converter unit 500, as illustrated in FIG. 5, comprises a second color difference signal separator 501 coupled to an output 1 of color signal nibble multiplexer 405 of color signal rise time compensator 400 for separating the color signal output from color signal nibble multiplexer 405 into color difference signals R-Y and B-Y, a first D/A converter 502 for converting the color signals R-Y and B-Y output from second color difference signal separator 501 into analog color difference signals R-Y and B-Y in response to the hold pulse signal output from hold pulse generator 412, a second D/A converter 503, coupled to an output 2 of second luminance signal delay circuit 403 of color signal rise time compensator 400, for converting the digital luminance signal Y into an analog luminance signal, a color matrix 504 for separating the luminance and color difference signals output from first and second D/A converters 502 and 503 into analog R, G, and B color signals according to a control signal CON output from microcomputer 600, and first, second and third amplifiers 505, 506 and 507 for amplifying the R, G and B color signals output from color matrix 504 and providing them to a not-shown display. 
     Microcomputer 600 controls the entire system, stores delay data for controlling the delay of the color and luminance signals as well as the rise time of the luminance signal in a built-in ROM 601, and supplies them to color signal rise time compensator 400. It will be appreciated that ROM 601 advantageously can be located outside of, but controlled from, microcomputer 600 so that the delay data and the rise time of the luminance signal are supplied to color signal rise time compensator 400. 
     Operation of the color signal contour compensator of the present invention will now be described while referring to the waveforms shown in FIGS. 6A through 6G. As shown in FIG. 3, a digital composite signal output from A/D converter 100 is processed in processors 200 and 300, and output as a color signal C and a luminance signal Y. 
     As shown in FIGS. 6A and 6B, the normal rise time of luminance signal Y is much shorter, about 150 nsec, than the normal rise time of color signal C, which is about 800 to 1200 nsec. As shown in FIG. 4, color signal C is input to color signal delay circuit 401, and luminance signal Y is input to first luminance signal delay circuit 402. 
     Color signal delay circuit 401 and first luminance signal delay circuit 402 delay luminance signal Y and color signal C by &#34;D1&#34; and &#34;D2&#34;, respectively, to output signals having the waveforms shown in FIGS. 6D and 6E. Here, the delay data corresponding to &#34;D1&#34; and &#34;D2&#34; are determined by data stored in ROM 601 of microcomputer 600 and transmitted via the control bus line. 
     The color signal delayed by color signal delay circuit 401 is output to color signal nibble demultiplexer 404 and color signal nibble multiplexer 405. The four-bit output signal from color signal nibble multiplexer 405 is input to second color difference separator 501 of D/A converter unit 500, and the eight-bit output signal from color signal nibble demultiplexer 404 is input to color signal nibble multiplexer 405 and first color difference signal separator 406. 
     The eight-bit color difference signal R-Y separated by first color difference signal separator 406 is converted into a ten-bit signal by first interpolation filter 407 and output to first rise time detector 410 while the eight-bit color difference signal B-Y is converted into a ten-bit signal by second interpolation filter 408 and output to second rise time detector 411. 
     First and second rise time detectors 410 and 411 compare the amplitude absolute value Ao of FIG. 6C stored in ROM 601 and input through control bus interface 409 with the amplitude gains of the color difference signals R-Y and B-Y output from first and second interpolation filters 407 and 408. When the amplitude gains of the color difference signals are above amplitude absolute value Ao, a &#34;HIGH&#34; logic signal is output, and when the gains are below the absolute value, a &#34;LOW&#34; logic signal is output. When the amplitude gains of the signals output from first and second rise time detectors 410 and 411 are above amplitude absolute value Ao, hold pulse generator 412 generates a &#34;HIGH&#34; logic start pulse for delaying color difference signals R-Y and B-Y by &#34;D3&#34; in FIG. 6F according to the delay data output from microcomputer 600 and transmitted via the control bus line. When the amplitude gains of color difference signals R-Y and B-Y are below amplitude absolute value Ao, hold pulse generator 412 generates a &#34;LOW&#34; logic stop pulse. The delay period corresponding to &#34;D3&#34; is the rise time of the luminance signal. The start and stop pulses output from hold pulse generator 412 are input to the control port of first D/A converter 502 of D/A converter unit 500 so that color difference signals R-Y and B-Y are D/A-converted only during the start pulse period (the rise time of the luminance signal). During the stop pulse period, the color difference signals are not D/A-converted. 
     In other words, the waveform shown in FIG. 6F is a waveform of the color difference signal output from first D/A converter 502 after the D/A converting operation of color difference signals R-Y and B-Y is controlled by the start and stop pulses output from hold pulse generator 412. It will be apparent that the output signal (FIG. 6E) of color signal delay circuit 401 is D/A-converted above amplitude absolute value Ao. Meanwhile, the delayed luminance signal (FIG. 6D) output from first luminance signal delay circuit 402 is further delayed for a period &#34;D4&#34;, as shown in FIG. 6G, by second luminance signal delay circuit 403 and fed to second D/A converter 503. In other words, the waveform shown in FIG. 6G is the signal output from second luminance signal delay circuit 403 and delayed, with respect to the luminance signal (FIG. 6D), for a period &#34;D4&#34;, which period corresponds to the stop pulse period of the hold pulse to match its rise time to that of the color difference signal shown in FIG. 6F. here, start period &#34;D3&#34; and stop period &#34;D4&#34; may be selected according to the Tables 1 and 2, which illustrate ranges of clock periods stored in ROM 601 of microcomputer 600. 
     
                       TABLE 1                                                     
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BITS                  CLOCK                                               
3         2     1           0   PERIOD                                    
______________________________________                                    
0         0     0           0   0                                         
0         0     0           1   1                                         
0         0     1           0   2                                         
0         0     1           1   3                                         
0         1     0           0   4                                         
0         1     0           1   5                                         
0         1     1           0   6                                         
0         1     1           1   7                                         
1         0     0           0   8                                         
1         0     0           1   9                                         
1         0     1           0   10                                        
1         0     1           1   11                                        
1         1     0           0   12                                        
1         1     0           1   13                                        
1         1     1           0   14                                        
1         1     1           1   15                                        
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                       TABLE 2                                                     
______________________________________                                    
BITS                  CLOCK                                               
7         6     5           4   PERIOD                                    
______________________________________                                    
0         0     0           0   0                                         
0         0     0           1   1                                         
0         0     1           0   2                                         
0         0     1           1   3                                         
0         1     0           0   4                                         
0         1     0           1   5                                         
0         1     1           0   6                                         
0         1     1           1   7                                         
1         0     0           0   8                                         
1         0     0           1   9                                         
1         0     1           0   10                                        
1         0     1           1   11                                        
1         1     0           0   12                                        
1         1     0           1   13                                        
1         1     1           0   14                                        
1         1     1           1   15                                        
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     The start periods of the hold pulse shown in Table 1 are stored in four lower-order bits of ROM 601, and the stop periods of the hold pulse shown in TABLE 2 are stored in four upper-order bits of ROM 601. 
     As described in detail above, the color signal contour compensator matches the rise time of a color signal to the relatively short rise time of a luminance signal using a time delay device, thereby sharpening the contour of a picture during playback and preventing the deterioration of picture quality. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.