Method of forming a light emitting diode
BACKGROUND OF THE INVENTION 
     The present invention relates, in general, to semiconductor devices, and more particularly, to optical semiconductor devices. 
     In the past, the semiconductor industry has utilized a variety of methods to implement optical semiconductor devices such as light emitting diodes. One previous method included forming multiple layers of semiconductor material on a gallium arsenide substrate and then creating a &#34;T&#34; shaped contact by etching the structure&#39;s top most layers. One such light emitting diode is described in U.S. Pat. No. 4,989,050 issued to Gaw et al on Jan. 29, 1991 which is hereby incorporated herein by reference. 
     One disadvantage with the previous method was inadvertent etching of the sides or edges of the &#34;T&#34; shaped contact&#39;s cross member. Generally, electrodes were formed by utilizing the cross member as a mask while depositing conductor material. The etching that affected the cross member&#39;s edges, altered the mask size thereby permitting the conductor material to create shorts across the diode&#39;s P-N junction and destroying the device. 
     Another disadvantage of previous methods was the number of processing steps required to form the &#34;T&#34; shaped contact. Generally the &#34;T&#34; shape was obtained by first etching layers off of the cross member. Then three successive etches were used to form the pedestal that supported the cross member thereby completing the &#34;T&#34; shape. These multiple etching operations resulted in a high manufacturing cost for the diode. 
     Accordingly, it is desirable to have a light emitting diode with a &#34;T&#34; shaped contact having a cross member whose sides or edges are not etched, with a P-N junction that is not shorted, and with a &#34;T&#34; shaped contact that is formed with a minimal number of processing steps. 
     SUMMARY OF THE INVENTION 
     Briefly stated, the present invention includes forming an optical semiconductor device by using controlled etch rates to form a &#34;T&#34; shaped contact structure. The etch rate is controlled by judicious selection of materials to provide a cladding layer that has a predetermined etch rate in hydrofluoric acid, a contact layer that is not affected by hydrofluoric acid, and a sacrificial layer that is removed by the hydrofluoric acid. The material selection prevents the sides of the contact layer from being affected by the etch, thus, the resulting &#34;T&#34; shaped contact can be used as a mask to accurately position the diode&#39;s electrodes. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an enlarged cross sectional view of a portion of an LED embodiment in a stage of manufacturing in accordance with the present invention; 
     FIG. 2 is the light emitting diode of FIG. 1 at a subsequent manufacturing stage in accordance with the present invention; 
     FIG. 3 is the light emitting diode of FIG. 2 further along in the manufacturing process in accordance with the present invention; and 
     FIG. 4 is an alternate LED embodiment in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates an early stage in the process of forming a light emitting diode 20 from an optical semiconductor wafer. The materials utilized in the optical semiconductor wafer are selected to optimize the structural elements that are created by each processing operation thereby reducing the total number of processing steps required to form diode 20. The optical semiconductor wafer includes a III-V compound semiconductor substrate 11 and a number of III-V compound semiconductor layers which are grown on substrate 11 by well known epitaxial techniques such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other similar methods. An N-type GaAs buffer layer 12 is epitaxially grown on an N-type GaAs substrate 11 to isolate or buffer any impurities that may exist in substrate 11 thereby preventing them from affecting other layers of diode 20. In the preferred embodiment, substrate 11 is approximately 100-250 microns of N-type gallium arsenide (GaAs), and buffer layer 12 is between approximately 0.5 to 2.0 microns of N-type GaAs. P-type aluminum gallium arsenide (AlGaAs) is employed for a cladding layer 13 which covers buffer layer 12. A very thin layer, typically less than 200 angstroms (Å), of P-type indium gallium arsenide (InGaAs) is used for an active layer 14. Indium gallium arsenide&#39;s small band gap, combined with the thinness of active layer 14, forms a quantum well that assists in confining carriers within active layer 14 and improves the efficiency of diode 20 by producing light having a wavelength that is long enough to pass through layers 13, 12, and 11. 
     The remaining layers of diode 20 are chosen not only for the device characteristics the materials can provide, but also for the material&#39;s chemical properties. As will be seen hereinafter, aluminum arsenide dissolves very rapidly in certain etchants. Because of this characteristic, the aluminum arsenide molar fraction of each remaining layer of diode 20 is chosen to provide a controlled etch rate that facilitates forming a &#34;T&#34; shaped contact yet doesn&#39;t etch the sides of the cross-member. An injection layer 16 covers active layer 14 and provides a source of electrons which are injected into the quantum well of active layer 14. The N-type aluminum gallium arsenide utilized to form injection layer 16 has an aluminum arsenide molar fraction of about eight to eighteen per cent (Al 0 .08-0.18 Ga 0 .92-0.82 As) in order to minimize the etch rate of injection layer 16. Injection layer 16 is covered by a cladding layer 17 that is between approximately one and two microns of N-type aluminum gallium arsenide with an aluminum arsenide molar fraction of approximately thirty-two to fifty percent (Al 0 .32-0.50 Ga 0 .68-0.50 As) with the preferred content being forty-two percent. Due to the higher aluminum arsenide molar fraction, cladding layer 17 has a higher etch rate than injection layer 16. A GaAs support layer 10 that is between approximately 0.2 and 0.3 microns thick covers cladding layer 17, and supports a contact layer 18. Contact layer 18 is approximately 100 Å of highly doped N-type indium gallium arsenide (InGaAs). Support layer 10 and contact layer 18 function as a single contact layer which has a very slow etch rate since it is devoid of AlAs. An aluminum arsenide (AlAs) lift-off layer 19 has a high aluminum content, thus, a very high etch rate. A GaAs barrier layer 21 covers lift off layer 19 and is used to prevent doping of layer 18 during implanting or diffusion operations. The rapid etching of lift-off layer 19 will subsequently be used as a means of detaching barrier layer 21 from diode 20. In the preferred embodiment, lift-off layer 19 is as thin as approximately 20 Å and as thick as about 1000 Å, but is typically about 500 Å. Lift-off layer 19 and barrier layer 21 function as a sacrificial layer that is sacrificed as a means of forming the desired structure. The aluminum content of layers 16-21 provide controlled etch rates that facilitate forming a &#34;T&#34; shaped contact on diode 20. 
     At the stage of manufacturing that is illustrated in FIG. 1, a mesa 15 that is approximately 50 to 125 microns wide is formed by applying a mask to the optical semiconductor wafer and removing unprotected portions of the wafer by using a reactive ion etch (RIE), ion mill, or other equivalent etching procedure to provide mesa 15 with vertical sidewalls. The etch removes exposed portions of layer 21, underlying portions of lift off layer 19, contact layer 18, and support layer 10; and etches a predetermined depth into cladding layer 17 thereby creating a sidewall portion of cladding layer 17. In the preferred embodiment, the exposed portions of layer 17 have a thickness that does not impede subsequent implanting of dopants into layers 14 and 16. The exposed sidewalls of cladding layer 17 will subsequently be etched to form a pedestal that supports contact layer 18 and support layer 10. 
     FIG. 2 illustrates an embodiment of a subsequent manufacturing stage of diode 20 of FIG. 1. Elements of FIG. 2 that are the same as FIG. 1 have the same reference numerals. Layers 19 and 21 are shown as being removed but are represented by dashed lines 19&#39; and 21&#39; to provide continuity for the explanation of FIG. 2. A P-type dopant, such as beryllium, is implanted into diode 20 to form continuity regions 22, illustrated by dashed lines, that extend into and preferably through active layer 14. The continuity regions facilitate forming a low resistance electrical contact between active layer 14 and metal electrodes that are subsequently formed on the surface of injection layer 16. During the implant operation, barrier layer 21 prevents the P-type dopant from being implanted into contact layer 18. Consequently, the thickness of barrier layer 21 must be greater than the implant depth of the P-type dopant into barrier layer 21. In the preferred embodiment the dopant is implanted to a depth of approximately 0.8 microns. Since an implant is employed to form the continuity regions, the P-type dopant is not deposited into the exposed edges of contact layer 18 and support layer 10 thereby permitting subsequent etch operations to accurately control the shape of the sides of layers 10 and 18 
     After forming continuity regions 22, barrier layer 21 is no longer needed and can be removed. A hydrofluoric acid (HF) etch is used to simultaneously remove barrier layer 21 and form a &#34;T&#34; shaped structure that supports layer 10. The HF etch dissolves AlAs lift-off layer 19 thereby detaching barrier layer 21, represented by dashed lines 19&#39; and 21&#39;, and exposing contact layer 18. HF generally etches P-type AlGaAs rather slowly, however; the implanted dopant does not convert the material to P-type until after the dopant is activated. Prior to the activation, HF provides etching of AlGaAs containing an implanted P-type dopant, the etch rate determined by the AlAs content. Consequently, during the HF etch of lift-off layer 19, cladding layer 17 is also etched but at a slower rate due to the lower aluminum content (about 32 to 50 percent). The aluminum content of cladding layer 17 permits the exposed side walls of cladding layer 17 to be etched thereby undercutting support layer 10 and contact layer 18, and forming a pedestal that supports layers 10 and 18. Support layer 10 and contact layer 18 are devoid of aluminum and not affected by the HF etch. Therefore, the exposed sides of layers 10 and 18 are not altered during the etch operation and the shape of layers 10 and 18 is accurately controlled. Because layers 10 and 18 will subsequently be used as a mask to form self aligned ohmic contact electrodes on the surface of injection layer 16, maintaining the shape is important. Also during the etch procedure, material is removed from the horizontal surface of cladding layer 17, at a rate equivalent to the sidewall removal, until injection layer 16 is exposed. Since injection layer 16 has a low aluminum arsenide molar fraction (approximately 8-18 percent), injection layer 16 is etched at a much slower rate thereby permitting the pedestal to be formed before etching through injection layer 16. It is important that the etch does not go through injection layer 16 in order to prevent surface recombination which could reduce the efficiency of diode 20. Subsequently, the implanted dopants are activated in an arsine over pressure to form P-type continuity regions 22, dashed lines. Such activation methods are well known in the semiconductor art. The single etch operation used to form the &#34;T&#34;  shaped contact structure and to simultaneously remove barrier layer 21 is a significant improvement over prior methods that employ multiple etch operations. 
     Referring to FIG. 3, layers 10 and 18 are utilized as a mask while depositing ohmic contact material to form an electrode 23 on contact layer 18, and a self-aligned electrode 24 on injection layer 16. Electrode 24 surrounds the mesa although it appears as two electrodes due to the cross-sectional illustration. 
     FIG. 4 illustrates an alternate embodiment of a method of forming diode 20 from the manufacturing stage of FIG. 1. Elements of FIG. 4 that are the same as FIG. 1 have the same reference numerals. A P-type region is formed by diffusing zinc, or other similar mobile dopant such as cadmium, magnesium, etc., into the exposed portions of diode 20 as shown by a dashed line 23. This P-type region will subsequently be used to create electrical connection to P-type InGaAs active layer 14. Since zinc has a higher diffusion rate in AlGaAs than in GaAs and InGaAs, the zinc diffusion front is not uniform as illustrated by the irregular shape of dashed line 23. GaAs barrier layer 21 is used to prevent the zinc dopant from diffusing into N-type InGaAs contact layer 18. Therefore, the thickness of barrier layer 21 must be greater than the distance the zinc dopant diffuses into barrier layer 21. In the preferred embodiment of FIG. 4, barrier layer 21 is approximately one micron thick and the zinc dopant diffuses approximately 0.8 microns into layer 21. After the diffusion is complete, layer 21 is no longer needed and can be removed. 
     A &#34;T&#34; shaped structure, such as the structure shown in FIG. 3, is formed by employing a two step etch procedure. First, a composition selective P-type etchant that dissolves P-type AlAs, such as a cerium sulfate and cerium nitrate solution, is used to rapidly dissolve the P-type portion of high AlAs content layers 17 and 19. This etch stops on N-type material and etches low Al content material very slowly, thus, the P-type portion of layer 19 is undercut from layer 21 and the P-type region of layer 17 is removed. Then, an HF etch is used to remove the remaining N-type portion of AlAs layer 19 along with a portion of N-type layer 17 thereby detaching barrier layer 21 and undercutting support layer 10. Layer 18 and support layer 10 are not affected by the HF etch, thus, the exposed sides on contact layer 18 and support layer 10 are not altered during the etch operation. It should be noted that a small P-type region remains at each end of layers 10 and 18, after performing the undercut etch. These areas subsequently will be shorted to the N-type areas of each respective layer by electrode 23 (FIG. 3). Consequently, the P-type area of layers 10 and 18 are electrically disabled. After the second etch is complete, P-type continuity regions extend from P-type cladding layer 13 through layer 16 to facilitate forming ohmic connection between electrode 24 (FIG. 3) and active layer 14. Contrary to continuity regions 22 of FIG. 2, these continuity regions extend beneath the cross-member of the &#34;T&#34; structure due to the dopant&#39;s diffusion front. 
     It will be apparent to those skilled in the art that the two step etch procedure explained in FIG. 4 could be applied to the etch procedure described in FIG. 2 if the implanted P-type dopant is activated prior to etching. 
     In another alternate embodiment, barrier layer 21 is aluminum gallium arsenide with a high aluminum molar fraction, typically greater than fifty percent, that facilitates completely dissolving barrier layer 21 during the HF etch. In this embodiment, lift-off layer 19 is not present. The thickness of barrier layer 21 still must prevent any P-type dopant, from contaminating contact layer 18. Since zinc diffuses two to four times faster into aluminum gallium arsenide than InGaAs or GaAs, barrier layer 21 is typically greater than three microns thick and the zinc diffuses less than three microns into barrier layer 21. 
     By now it should be appreciated that there has been provided a novel way to fabricate a light emitting diode. In one embodiment, a single HF etch removes barrier layer 21 thereby exposing contact layer 18, the etch also undercuts layers 10 and 18 to form a &#34;T&#34; shaped N-type contact. In an alternate embodiment, the HF etch is preceded by a composition selective P-type etch. The HF etch does not affect the size of support layer 10 or contact layer 18. Therefore, the mask formed by layers 10 and 18 provides accurate placement of the diode&#39;s electrodes, and prevents the electrodes from shorting the diode&#39;s P-N junction. The material combinations that are utilized for diode 20 minimize the number of etch operations required to form the structure thereby reducing manufacturing costs.