Time-varying modulo N trellis codes for input restricted partial response channels
CROSS REFERENCE TO RELATED APPLICATION 
     U.S. application Ser. No. 7/869,570, (Docket SA9-91-100) filed concurrently herewith, entitled, &#34;Time-Varying Viterbi Detector for Control of Error Event Length&#34;. 
     FIELD OF THE INVENTION 
     This invention relates to techniques for transmitting binary digital data over partial response channels. More particularly, it relates to a method and apparatus, using high rate modulation run length limited codes and associated detectors, for improving the reliability of data storage devices by increasing the minimum distance between output sequences of partial response channels. 
     BACKGROUND OF THE INVENTION 
     The following prior art references are considered by applicant to be the most pertinent to the present invention: 
     [A] H. K. Thapar and A. M. Patel, &#34;A Class of Partial Response Systems for Increasing Storage Density in Magnetic Recording,&#34; IEEE Transactions on Magnetics, vol. MAG-23, No. 5, September 1987. 
     [B] U.S. Pat. No. 4,786,890, granted Nov. 22, 1988, entitled &#34;Method and Apparatus for Implementing a PRML Code.&#34; 
     [C] U.S. Pat. No. 4,888,779, granted Dec. 19, 1989, entitled &#34;Matched Spectral Null Trellis Codes for Partial Response Channels.&#34; 
     [D] R. Adler, D. Coppersmith, and M. Hassner, &#34;Algorithms for Sliding Block Codes,&#34; IEEE Transactions on Information Theory, vol IT-29, No. 1, January, 1983. 
     [E] L. J. Fredrickson and J. K. Wolf, &#34;Error Detecting Multiple Block (d,k) Codes,&#34; IEEE Transactions on, Magnetics, vol. MAG-25, No. 5, September, 1989. 
     High rate run length limited (RLL) trellis codes and associated Viterbi detectors have heretofore been proposed for various partial response channels. Partial response channels of interest for data storage devices include those with channel polynomials of the form P(D)=(1-D)(1+D) n , where n is a nonnegative integer. Reference [A] notes that a (1-D) dicode channel, a PR4 (1-D 2 ) channel, and an EPR4 (1+D-D 2  -D 3 ) channel are useful for magnetic recording channels. Partial response channels PR1 (1+D), and (1+D 2 ), are preferred for optical recording channels. 
     Partial response channels (1+D n ) or (1-D n ) have a practical implementation advantage in that they can be deinterleaved into n (1+D) or (1-D) channels, respectively. In Reference [B], PR4 detection is accomplished by interleaving two (1-D) dicode detectors. In Reference [C], coding and detection for these channels is accomplished by interleaving appropriate dicode or PR1 channel codes. 
     Coding constraints are generally imposed which improve the reliability of data recovery. These constraints may require regular updates of timing and gain control loops and/or limitation of the length of divergent error events, as discussed in References [B] and [C]. Reference [D] discusses the incorporation of the usual (d,k) runlength constraints in codes for magnetic channels. 
     Reference [C] discloses a method for increasing the reliability of partial response storage channels, by increasing the minimum distance between coded output sequences using codes designed to match the spectral nulls in a channel partial response polynomial. The Viterbi detectors in Reference [C] have reduced complexity, achieved by tracking the spectral content of detected sequences. 
     Reference [C] also describes a method for eliminating &#34;quasi-catastropic sequences&#34; which are defined as sequences that are represented by more than one distinct path through the detector trellis. The &#34;minimum distance&#34; of a particular detector trellis (sometimes referred to in the art as d 2   free ) is defined as the minimum sum of the squared differences between noiseless sample values resulting from two distinct sequences that diverge from a common state on the trellis and remerge to a common state. For partial response, maximum likelihood (PRML) detection, d 2   free  is 2, but the first order matched spectral null codes of Reference [C] increase d 2   free  to 4. 
     Reference E discusses the design of error detection codes for minimum run length d=1 input restricted channels which rely on tracking the sum of the positions of NRZI ones modulo 2. Because a minimum distance error is made by shifting an NRZI one to an adjacent bit position, an NRZI one, originally in an odd (even) numbered position, is misdetected in an even (odd) numbered position, changing the modulo 2 sum of positions of NRZI ones. In Reference [E], error detection codes use prior knowledge of the modulo 2 sum of the positions of NRZI ones over a span of m bits in an encoded sequence to determine whether a minimum distance event has occurred. However, it should be noted that the channel in Reference [E] is a peak detected Lorentzian channel, and no reference is made to partial response channels or the detection thereof. 
     The referenced related application describes Viterbi detectors for matched spectral null codes with a trellis structure in which a predetermined number of states and edges are deleted in a preselected time-dependent pattern to create a time-varying trellis which significantly limits the maximum lengths of minimum distance error events. 
     However, these references and the related application do not teach or suggest a Viterbi detector which provides a time-varying trellis for a run-length-limited (RLL) code, wherein only certain values of a preselected attribute tracked modulo N are allowed every m bits, to increase the minimum distance between output sequences of a partial response channel and to eliminate quasi-catastrophic sequences for increasing the reliability of data storage devices. 
     SUMMARY OF THE INVENTION 
     According to the invention, a method and apparatus are described for generating high rate run-length-limited trellis (RLL) codes and designing the associated detectors which increases the minimum distance between output sequences of partial response channels with constrained channel inputs. 
     More particularly, trellis codes and Viterbi detectors are designed for partial response channels having characteristic polynomials of the form P(D)=(1±D n ), where n is a positive integer, and P(D)=(1+D-D 2  -D 3 ). The Viterbi detector replicates a conventional trellis pattern for the desired channel N times. The N copies of the channel response trellis are interconnected in such a way that a preselected function associates each state in the trellis with a particular integer value modulo N. The number N is selected according to the channel detection and coding constraints so that diverging erroneous sequences of minimum distance lead to detector states which are distinct from the correct detector state. 
     The detector trellis is time-varying in such a way that only certain values of the preselected function are allowed every m bits. The time-variation is provided such that there are no minimum distance extensions of erroneous sequences beyond a predetermined length. In this manner, the reliability of storage channels is desirably increased, because more noise is required to overcome the additional distance and cause an error in distinguishing the correct encoded sequence. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 depicts a block diagram of a data storage system comprising an encoder, a partial response channel corrupted by noise, a detector, and a decoder, as known in the prior art. 
     FIG. 2 depicts a combined Viterbi detector trellis for a (d,k) run-length-limited code wherein d=1, and the channel is an EPR4 (1+D-D 2  -D 3 ) input restricted channel, as known in the prior art. 
     FIG. 3 depicts the minimum distance sequences for the prior art trellis illustrated in FIG. 2. 
     FIG. 4 depicts the minimum distance sequences for maximum likelihood detection of a dicode (1-D) channel, as known in the prior art, for magnetic recording. 
     FIG. 5 depicts the minimum distance sequences for maximum likelihood detection of a PR1 (1+D) channel, as known in the art, for optical recording. 
     FIG. 6 depicts how, according to the invention, the six states of the trellis of FIG. 1 are modified to obtain twelve states. 
     FIG. 7 is a time-varying modulo 2 trellis, according to the invention, for tracking the parity of the even positions of NRZI ones. 
     FIG. 8 depicts how, according to the invention, the twelve states of the trellis of FIG. 6 are made time-varying in the first four bits of each sixteen bit block. 
     FIG. 9 depicts how, according to the invention, the twelve states of the trellis of FIG. 6 are made time-varying in the last four bits of each sixteen bit block. 
     FIG. 10 depicts, according to the invention, a symbolic representation of a three state rate 10/16 encoder for a modulo 2 EPR4 code. 
     FIG. 11 depicts how, according to the invention, the two states of the dicode trellis (1-D) are modified to obtain eight states. 
     FIG. 12 depicts how, according to the invention, the two states of the (1+D) PR1 trellis are modified to obtain eight states. 
     FIG. 13 is a simplified representation of a trellis of the types shown in FIG. 11 and FIG. 12; 
     FIG. 14 depicts minimum distance error events for the (1-D) trellis of FIG. 11. 
     FIG. 15 depicts minimum distance error events for the (1+D) trellis of FIG. 12. 
     FIG. 16 depicts, according to the invention, a circuit diagram for prebiasing minimum distance decisions for the (1-D) trellis of FIG. 11. 
     FIG. 17 depicts, according to the invention, a circuit diagram prebiasing minimum distance decisions for the (1+D) trellis of FIG. 12. 
     FIG. 18 depicts, according to the invention, a circuit diagram for prebiasing a specific minimum distance decision for the (1-D) trellis of FIG. 11. 
     FIG. 19 depicts, according to the invention, a time-varying modulo 4 trellis for the (1-D) or (1+D) channel. 
     FIG. 20 depicts, according to the invention, a circuit diagram showing incorporation of the circuits depicted in FIGS. 16-18 in the add-compare-select (ACS) unit of a time-varying Viterbi detector. 
    
    
     PRELIMINARY DESCRIPTION--PRIOR ART 
     As depicted in FIG. 1, input data, such as in the form of binary symbol strings, is transmitted from a bus 10 to an encoder 11. Encoder 11 produces a binary code symbol sequence which serves as input to a partial response channel 12. A channel output sequence is generated by partial response channel 12, corrupted by noise and detected at the channel output by a Viterbi detector 13. Detector 13 calculates and estimates, from the channel output sequence, the most probable coded sequence. A decoder 14 uses this estimate, as calculated by detector 13, to recover the original input data and output it to a bus 15. 
     For each partial response channel polynomial P(D) considered, the channel state consists of the most recent j NRZ channel input bits, where j is the degree of the polynomial. In certain examples, it is convenient to use NRZI notation to describe events. To distinguish the notation herein, NRZI input bits are labelled a i , and are related to NRZ input bits b i  by a i  =b i  XOR b i-1 , where XOR refers to the logical exclusive-or function. Some of the channels considered incorporate (d,k) runlength constraints in the detector. A (d,k) constrained sequence requires at least d and at most k NRZI zeroes between NRZI ones. 
     Let b={b 0 , b 1 , . . . , b m  } be a sequence of NRZ channel input bits. It is convenient to use the delay operator D, the channel input polynomial b(D) where ##EQU1## and the partial response channel polynomial P(D), to find the noiseless channel output polynomial c(D), where c(D)=P(D) b(D), as shown in FIG. 1. 
     FIG. 2 depicts a trellis structure characterizing a six state Viterbi detector for a minimum run length d=1 input-restricted EPR4 channel. Since the EPR4 channel state is characterized by the previous three NRZ channel input bits, each channel state at time i is labelled with a three-tuple, b i-3  b i-2  b i-1  and the noiseless channel response is given by c i  =b i  +b i-1  -b i-2  -b i-3 . 
     Note that channel states 101 and 010 are not included in FIG. 2, since they do not occur in a d=1 input-restricted EPR4 channel. Each branch in FIG. 2 has a two-component label (such as 0/0), where the first component is the NRZ channel input bit b i   and the second component is the noiseless channel response associated with the corresponding succession of channel states. 
     FIG. 3 depicts the minimum distance error event for a d=1 EPR4 trellis, with a minimum distance d 2   free  =4 in which a correct sequence and a minimum distance erroneous sequence (herein called &#34;minimum distance neighbors&#34;) diverge from a common state. This common state must have a label of the form xpp, where x is arbitrary, and p is the common value of previous channel inputs required to satisfy the d constraint such as states 000,011,100 and 111 in FIG. 2. In FIG. 3, the bit label q is used to indicate the complement of p. The squared difference between the noiseless sample values on the diverging branches is 1. The sequences eventually remerge to a common state labelled qqy, where y is arbitrary, and accumulate a total minimum distance of 4, equal to the sum of the squared differences of noiseless sample values. 
     This error event is conveniently characterized in NRZI notation. Each branch in FIG. 3 has three-component label, such as p/0/p-x where the first component is the NRZ channel input bit b i , the second is the NRZI channel input bit a i , and the third is the noiseless channel response associated with the corresponding succession of channel states. The minimum distance error event for the d=1 EPR4 channel involves minimum distance neighbors of the NRZI form w0010v and w0100v, where w and v are arbitrary. 
     FIG. 4 depicts the minimum distance event for detection of a dicode channel having a conventional trellis structure such as disclosed in Reference [B]. In FIG. 4, each branch has a two-component label, where the first component is the NRZ channel input bit b i  and the second is the noiseless channel response associated with the corresponding succession of channel states. The sequences diverge from a state labelled x, where x is arbitrary, and eventually remerge to a state labelled y, where y is arbitrary, and accumulate a total distance of 2. 
     FIG. 5 depicts the minimum distance event for a PR1 channel having a conventional trellis structure, such as disclosed in reference [C]. In FIG. 5, the branches have two component labels similar to those in FIG. 4. 
     PRELIMINARY DESCRIPTION--PRESENT INVENTION 
     According to the invention, alternative methods are described for achieving increases in coded minimum distance similar to those obtained in Reference [C] with first order spectral nulls, without requiring spectral nulls. In some cases, the resulting codes provide higher code rates for a given number of states than are possible using the methods of Reference [C]. 
     The method used by applicant to increase minimum distance includes the steps of: 
     (i) preselecting a weighting function Φ which maps each encoded sequence of channel input bits, in NRZ or NRZI notation, to an integer value modulo N, 
     (ii) interconnecting n Viterbi detectors, each having m channel states, each such state representing the most recent input to the partial response channel, for creating a modified trellis structure for a modified Viterbi detector having n times m states each representing a combination of a channel state and a particular value of the weighting function; 
     (iii) determining the value of N and channel input and detector constraints which ensure that sequences of minimum distance emanating from a common state in the modified detector lead to different detector states, 
     (iv) deleting, from the modified detector trellis, states and/or edges emanating from the trellis states in order to eliminate multiple paths with identical noiseless sample values, and 
     (v) selecting a code which is a subset of nonquasi-catastrophic sequences that correspond to permissible paths through the modified detector trellis. 
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     I. For Minimum Run Length d=1 Input Restricted EPR4 Channels 
     For EPR4 channels, the detector trellis is constricted using weighting function, generically expressed as Φ:{a 0 , a 1 , a 2 , . . . , ai}--&gt;Z n  as referred to in method step (i) above. Function Φ assigns a unique value modulo N to each sequence of i channel input bits in NRZI notation, where ##EQU2## 
     This expression is a weighted sum modulo N of the NRZI bits using preselected weights {w 0 , w 1 , . . . , w i  }. 
     Minimum distance events of distance d 2   free  =4 were described above in the Background section. A code described in Appendix A hereof contains no events of distance 4. An attribute which distinguishes a coded input sequence from minimum distance neighbors is the sum of even (or odd) positions of NRZI ones modulo 2. Appropriate weights for evaluating the sum of even positioned NRZI ones are given by w 2j  =1 and w 2j+1  =0. In this example, ##EQU3## which is the sum of even numbered positions of NRZI ones up to time i. 
     According to method step (ii) above, the Viterbi detector trellis is constructed in which the various trellis states are associated with distinct values of S=T modulo N. FIG. 6 discloses a detector trellis for N=2. In FIG. 6 each detector state has a two-component label in which the first component indicates the channel state (e.g. 110), and the second component (e.g., 1 mod 2) indicates the value of S modulo 2. Since an event with a minimum distance (d 2   free ) of 4 results in a change of one in S, a detector with N=2 satisfies method step (iii) for distance 4 events without additional detector constraints. Branches corresponding to NRZI ones are highlighted by thickened lines in FIG. 6 to show the change in S caused by NRZI ones in even numbered positions. 
     In the EPR4 detector disclosed in FIG. 6, minimum distance sequences which diverge from a common state in the trellis lead to detector states with distinct values of S. Quasi-catastrophic behavior resulting from pairs of paths with identical noiseless sample values must be eliminated from the code and/or detector to guarantee that increased reliability is achieved with a path memory of finite length. A pair of paths with identical noiseless sample values have identical channel inputs, and provide equal contributions to the value of S. As a result, minimum distance divergent paths retain different values of S. In the referenced related application, methods are disclosed for incorporating a time varying detector trellis to minimize the lengths of quasi-catastrophic paths. 
     FIG. 7 depicts a time-varying modulo 2 trellis, which indicates time-varying allowed values of S that eliminate all quasi-catastrophic sequences. Each state is labelled with the value of S, and branches are labelled with the allowed value of NRZI input bits a i  which result in the depicted state transitions. As shown in FIG. 7, only one value of S is allowed every 16 bits and the bit indices are specified along the bottom of the figure and correspond to those specified in FIGS. 6, 8 and 9, which in combination depict the entire time-varying trellis for modulo 2 minimum run length d=1 input restricted EPR4. 
     More specifically, FIG. 8 depicts the interconnection of the twelve-state trellis for the first four bits of each sixteen-bit block, as specified along the bottom of the figure. All sequences start with S=0 in the first bit of each block. After the third bit in each block, all states are fully connected as shown in FIG. 6 for bit indices 4, 5, 6, 7, 8, 9, 10, and 11. FIG. 9 shows the interconnection of the twelve-state trellis for the last four bits of each sixteen-bit block, as specified along the bottom of the figure. All sequences end with S=0 in the last bit of each block. 
     The available sequences (i.e. those corresponding to paths through the time-varying trellis) are used to derive the code described in step (v) above by applying sliding block methods, such as described in Reference [D]. FIG. 10 discloses a symbolic representation of a three-state encoder for the rate 10/16 code specified in Appendix A for the minimum run length d=1 input restricted d=1 EPR4 channel. 
     II. For Dicode and PR1 channels 
     For (1-D) dicode and (1+D) PR1 channels, a method for generating high rate trellis codes is disclosed which uses a weighting function Φ:{b 0 , b 1 , b 2 , . . . ,b i  }--&gt;Z n  of the form ##EQU4## This expression constitutes a weighted sum modulo N of the NRZ bits using preselected weights {w 0 , w 1 , . . . , w i  }. 
     For dicode channels, the weighting coefficient is w j  =1 for all j. For PR1 channels, the weighting coefficients are, w 2j  =1 and w 2j+1  =-1 for each j. 
     FIG. 11 depicts the trellis structure for dicode channels with N=4, while FIG. 12 depicts the trellis structure for PR1 channels with N=4. In each of these figures, each state has a two-component label, in which the first component is the previous NRZ channel input, b i-1 , and the second is the appropriate modulo 4 sum, S. Each branch has a two-component label (e.g. as 0/-1) in which the first component is the NRZ channel input, b i , and the second is the noiseless channel response. FIGS. 11 and 12 depict two-bit intervals, and have identical structures despite different labelling. FIG. 13 is a simplified drawing representing the structure of either FIG. 11 or FIG. 12 and depicts four-bit intervals. Branches emanating from the upper and lower states of FIG. 13 are used to represent the long, irregular, diagonal branches which are highlighted by the thickened lines in the second bit intervals of FIGS. 11 and 12. 
     Minimum distance (d 2   free ) 2 events for dicode and PR1 channels are depicted in FIGS. 4 and 5, respectively. However, if two sequences on the trellises of FIG. 13 diverge from a common initial state, after r noiseless extensions which do not accumulate distance, (i.e., after r consecutive same bit extensions for the (1-D) channel or r alternating bit extensions for the (1+D) channel), the value of S for the two sequences differs by (r+1) modulo N. Because of the structure of FIG. 13, the sequences can only remerge on the succeeding bit to a common state and complete a minimum distance event if they have a common value of S; i.e., if (r+1) modulo N=0. With N=4 as shown in FIG. 13, minimum distance 2 events have r ε {3, 7, 11, . . . }. FIG. 14 depicts minimum distance 2 events on the trellis of FIG. 11 with r=3. FIG. 15 depicts minimum distance 2 events on the trellis of FIG. 12 with r=3. 
     According to step (iii) above, a combination of coding and detector constraints must be imposed to ensure that minimum distance 2 events end on distinct detector states. Unlike the d=1 input restricted EPR4 channel earlier described in Section I, some of the minimum distance events described in the preceding paragraph must be eliminated from the code and/or detector. Asymptotically, the detector is most likely to make an error in a minimum distance decision between a coded sequence and some other trellis sequence. These decisions can be eliminated by use of the following strategies: 
     (A) selecting from available trellis sequences code sequences that do not require to eliminate minimum distance 2 decisions between a coded sequence and another trellis sequence, 
     (B) prebiasing the decision of the detectors so that it favors one of the subsequences in each minimum distance event pair of subsequences, and using only the favored subsequences in the code, or 
     (C) combining strategies (A) and (B). 
     For example, in FIG. 14, a minimum distance 2 event can occur if the detector has to distinguish between the NRZ sequences, 
     
         {b.sub.i-5, b.sub.i-4, b.sub.i-2, b.sub.i-1, b.sub.i }={0, 0, 0, 0, 0, 0}, and                                                       10(A) 
    
     
         {b.sub.i-5, b.sub.i-4, b.sub.i-2, b.sub.i-1, b.sub.i }={0, 1, 1, 1, 1, 0}, 10(B) 
    
     that connect state 0,S at time (i-5) to state 0,S at time i. 
     Similarly, a minimum distance 2 event can occur if the detector has to distinguish between the NRZ sequences, 
     
         {b.sub.i-5, b.sub.i-4, b.sub.i-2, b.sub.i-1, b.sub.i }={1, 0, 0, 0, 0, 0}, and                                                       11(A) 
    
     
         {b&#39;.sub.i-5, b&#39;.sub.1-4, b&#39;.sub.i-2, b&#39;.sub.i-1, b&#39;.sub.i }={1, 1, 1, 1, 1, 1},                                                       11(B) 
    
     that connect state 1,S at time (i-5) to state 0,S at time i. 
     All of the minimum distance 2 events with r≧3 involve a decision with at least one of each decision pair containing a subsequence with four or more consecutive same NRZ symbols. Therefore, all of the minimum distance 2 events can be eliminated by selecting a set of coded sequences which does not contain any subsequences with four or more consecutive same NRZ symbols. Therefore a minimum distance 4 code can be constructed using strategy (A). 
     Alternatively, according to the present invention and using strategy (B), all of the minimum distance 2 events in FIG. 14 can be eliminated by selecting a set of coded sequences and using, for each state, a prebiasing circuit and a preferred subsequence in each minimum distance 2 event pair of sequences. The prebiasing circuit 30 for the (1-D) dicode trellis of FIG. 11 is disclosed in FIG. 16. Circuit 30 receives inputs from path memories 32, 34 containing previous decisions for detector states with labels 0,S and 1,S respectively, respectively generate as outputs b -1  . . . b i-5  for one subsequence and b&#39; i-1  . . . b&#39; i-5 , for the other subsequence of a pair. Inverters 36a, b, c, d are interposed between outputs b i-1  to b -4  and an AND gate 38. Outputs b i-5  and b&#39; i-5  are connected via an exclusive OR invert (XNOR) gate 40 to AND gate 38; and the remaining outputs b&#39; i-1   to b&#39; i-4  are connected directly to AND gate 38. 
     The outputs of inverters 36a-d are logical ones if b i-1  to b i-4  are NRZ zeros. The output of XNOR gate 40 is a logical one when the two subsequences b and b&#39;1 being compared emanate from a common trellis state. If the output of AND gate 38 is a logical one, minimum distance decisions must be made for the states with labels 0,S and 1 ,S+1, as depicted in FIG. 14. 
     Normally, when the output of AND gate 38 is a logical one, AND gates 42, 44 will be enabled by external control lines 46, 48 respectively, to cause circuit 30 to prebias the Viterbi detector to select the lower path (FIG. 14) for state 0,S and select the upper path (FIG. 14) for state 1, S+1. However, if the signal is down in either line 46 or 48, the prebiasing circuit 30 will be rendered inoperative for the state with label 0,S or 1,S+1, respectively. 
     Thus, the circuit 30 of FIG. 16 calls for a prebiased decision when the output of AND gate 38 is a logical one because all of the following conditions exist: 
     
         b.sub.i-5 =b.sub.i-5 
    
     
         b.sub.i-4 =b.sub.i-3 =b.sub.i-2 =b.sub.i-1 =0, and 
    
     
         b&#39;.sub.i-4 =b&#39;.sub.i-3 =b&#39;.sub.i-2 =b&#39;.sub.i-1 =1. 
    
     Whether the detector selects subsequence (10A) and (10B) and (11A) or (11 B) in state 0,S of FIG. 14 is somewhat arbitrary and the subsequences selected can be chosen so as to optimize code parameters. As between subsequences (10A) and (10B), (10B) is generally preferred since it results in shorter run lengths and more frequent updates of timing and gain control loops. The choice (11 A) and (11 B) is not as clear cut because both result in the same run lengths. Accordingly, if AND gate 42 is enabled, the signal in control line 49 (select lower path for state 0,S) signifies that subsequence (11B) has been arbitrarily selected to be in the code; that subsequence (11A) is rejected by the detector when confronted with the choice between (11A) and (11 B); and that (10B) is preferred over (10A). 
     A prebiasing circuit 50 for the (1+D) PR1 trellis of FIG. 12 is disclosed in FIG. 17. It comprises path memories 52,54 inverters 56a, b, c, d AND gate 58, XNOR gate 60, and AND gates 62, 64. Operation of this circuit 50 and the conditions under which AND gate 58 will be enabled should be readily apparent in view of the detailed description of circuit 30. 
     As a third alternative, according to the invention and using strategy (C), all of the d 2  =2 events in FIG. 14 can be eliminated by selecting a set of coded sequences, where each state has a limited prebiasing circuit and a preferred subsequence in each d 2  =2 event prebiased pair, but neither subsequence in each unbiased d 2  =2 event pair is used in the code. A limited prebiasing circuit 70 for the trellis of FIG. 11 is disclosed in FIG. 18 for state 0,S. 
     The output of circuit 70 indicates whether a d 2  =2 minimum distance decision is required. Circuit 70 differs from that described in connection with FIG. 16 in that the input of AND gate 78 is connected to inverters 76e and 76f. Path memories 72, 74 are connected to circuit 70 by appropriate busses. Inverters 76 are are interposed between AND gate 78 and the path memory outputs b i-1  through b i-1  through b i-5  of one subsequence; and inverter 76f is interposed between the output b i-5  and AND gate 78. Whenever AND gate 82 is enabled by a signal in line 83 and a logical one output of AND gate 78, the need for a d 2  =2 decision between subsequences (10A) and (10B) is identified, and subsequence (10B) is selected. To eliminate the need for a d 2  =2 minimum distance decision between subsequences (11A) and (11B), a set of code sequences is selected in which each coded sequence does not contain a subsequence with five or more consecutive identical NRZ symbols. 
     FIG. 19 discloses the incorporation of the d 2  =2 decision identifier into the time-varying trellis Viterbi detector, disclosed in the above cited related application. 
     FIG. 19 discloses a time-varying trellis for a modulo 4 code for the (1-D) or (1+D) channel using combination strategy (C). The code maps eight user bits to ten channel bits in NRZ notation in each encoding operation. The codewords used in this module 4 code, and coding details are specified in Appendix B. 
     APPARATUS FOR GENERATING THE TIME-VARYING TRELLIS 
     Applicant&#39;s invention is implemented by modified Viterbi detector 13 (FIG. 1) in combination with the encoder 11 and channel 12. The encoder 11, channel 12 and decoder 14 may be as described in the above-cited references, such as Reference [C]. 
     According to the invention, Viterbi detector 13 comprises a plurality of add-compare-select (ACS) units 100 of the type illustrated in FIG. 20. Each unit 100 comprises latches 101, 102, and an adder 103, a comparator 104, a selector 105, and a multiplexer 107 (MUX) interposed between the comparator 104 and selector 105, as disclosed in the above cited related application. 
     The ACS units 100 implement the time variation in a trellis structure (such as that shown in FIG. 19) having at most two incoming edges per trellis state. Of these two edges, at most one incoming edge has a nonzero label. Let 1,S denote a state from which an incoming edge with nonzero sample label emanates (if such an edge exists); and let 0,S denote a state from which an edge with sample label 0 emanates (again, if such an edge exists). 
     In operation, at any time t, the survivor metric for state 0,S is stored in latch 101, and the survivor metric for state 1,S is stored in latch 102. Using a look-up table or simple arithmetic processor (not shown), separate from the trellis structure, a branch metric B(y) is computed for an edge with nonzero label when a sample y is received at time t+1. Adder 103 adds branch metric B(y) and the survivor metric for state 1,S generating a new state metric. Comparator 104 outputs a value of 0 or 1 according to whether the new state metric is smaller or larger than the metric for state 0,S. 
     In a conventional ACS unit, this quantity would trigger selector 105 to output the smaller metric to line 106 for storage (not shown). However, in the ACS unit 100 MUX 107 has inputs including not only the single bit output of comparator 104 but also a single bit override signal from line OR. Operation of MUX 37 is controlled by a single bit control signal in line C. Signals in these control and override lines C and OR are generated by a finite state machine (FSM) (not shown) as a function of the time step of the time-varying trellis structure. If the control signal in C has the value 0, ACS unit 100 will operate as a conventional ACS unit. However, if the control signal in C is set to 1, MUX 107 will be activated and allow the FSM to override the comparator 104 and generate a specified output S. Each ACS unit 100, as thus far described, is identical with that in the modified Viterbi detector described in the cited related application. 
     According to the present invention, Viterbi detector 13 is further modified by including in each ACS unit 100 the minimum distance decision identifier circuit 70 (FIG. 18), path memories 72, 74 and a MUX 108. When the control signal in line C is a logical zero, time variation provided by MUX 107 will be disabled, but an inverter 85 interposed between control line of C and line 83 will cause circuit 70 to be enabled. If the conditions described in connection with FIG. 18 are met to enable AND gate 78, AND gate 82 (FIG. 18) will be enabled by the select signal in lines 83. This will provide an output signal in line 84, thereby activating MUX 108 to provide the required minimum distance for state 0,S and concurrently activate MUX 105 to generate the same metric that would be produced if one of the edges state 0,S or for 1,S were deleted. In this manner, the minimum distance identifier circuit 70 can be incorporated into the time-varying trellis structure of the Viterbi detector described in the cited related application. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit, scope and teaching of the invention. Accordingly, the invention herein disclosed is to be considered merely as illustrative and limited in scope only as specified in the claims: ##SPC1##