MSK phase acquisition and tracking method
The Government has rights in this invention pursuant to contract F19628-91-C-0028 with the Department of the Air Force. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to an arrangement for reducing the lock-up time and improving the noise performance in a receiver for burst minimum-shift-keyed communications. 
     BACKGROUND OF THE INVENTION 
     Minimum-shift keying (MSK) is a form of frequency-shift keying with frequency separation equal to one-half the bit rate. MSK provides spectrally efficient modulation in terms of bits-per-second per hertz (Hz) of bandwidth. Prior-art MSK processors are described in U.S. Pat. No. 4,583,048, issued Apr. 15, 1986 in the name of Gumacos et al., and in U.S. Pat. No. 4,635,279, issued Jan. 6, 1987 in the name of Nossen, both of which are hereby incorporated by reference. 
     MSK signals are demodulated by concurrent use of in-phase (I) and quadrature (Q) demodulators, each of which includes the multiplier. Sinusoidal and co-sinusoidal reference or demodulating signals are applied to the Q and I multipliers, respectively, at a frequency which is ideally equal to that of the carrier frequency of the MSK signal. Asynchronous demodulation can be accomplished with reference signals which are at the same frequency as the MSK carrier, but which are not necessarily in the same phase. This type of asynchronous demodulation results in an increase in noise by comparison with synchronous demodulation, in which the sinusoidal reference signal is in both frequency and phase synchronism with a carrier component of the modulated MSK signal. Increased noise results in increased error rate, and is therefore undesirable. 
     The MSK signal to be received may be downconverted to baseband in preparation for demodulation. The downconversion is performed by mixing or multiplying a local oscillator signal with the MSK-modulated carrier. If the local oscillator signal is not phase coherent with the MSK carrier, the baseband signal carrier will include a phase drift or phase error. This phase error results in increased noise in the demodulated signal and increases the bit error rate (BER). 
     SUMMARY OF THE INVENTION 
     An MSK receiver includes a downconverter for downconverting the received MSK signals. The phase drift or phase error per bit of the message preamble is determined. The reference carriers are generated, and the phase of the reference signals is adjusted during message demodulation under the control of the rate of phase change per bit across the preamble portion. In accordance with another aspect of the invention, the downconverted MSK signal burst is digitized and the digitized burst signal is stored in memory, following which it is read repeatedly so that bit timing, start-of-message timing, carrier phase, and carrier drift processing may be performed in a desired sequence, using all the available information for more accurate demodulation. According to a yet further aspect of the invention, a second order tracking loop produces the demodulation reference signals. In one embodiment, this is accomplished determining the difference between the estimated signal phases of the two bits preceding the current bit, and subtracting from the difference the estimated phase change per bit. 
    
    
     DESCRIPTION OF THE DRAWING 
     FIG. 1 is a simplified block diagram illustrating an MSK modulator for transmitting MSK-modulated signals including a burst of information together with a preamble; 
     FIG. 2 illustrates details of the arrangement of the preamble in accordance with an aspect of the invention; 
     FIG. 3 is a simplified block diagram of a receiver according to the invention; 
     FIG. 4 is a simplified block diagram illustrating the scheme of a second-order tracking-loop included in the receiver of FIG. 3. 
    
    
     DESCRIPTION OF THE INVENTION 
     FIG. 1 illustrates a transmitter designated generally as 10 including a source of digital information 12, which applies the information over a data path 14 to a control apparatus illustrated as a block 16, and to the common element of a single-pole, double-throw switch 18 illustrated by mechanical switch symbol. Those skilled in the art know that such a symbol is conventional, but that solid-state switches are used instead of mechanical switches. Switch 18 alternates positions, under the control of controller 16, to connect source 12 by way of a data path 20a to a memory 22a in the illustrated position of the switch, and in the other position (not illustrated) by way of data path 20b to a memory 22b. In operation, source 12 produces a stream of digital information which is controlled, in conjunction with controller 16, so that sequential bursts of information are applied alternately to memories 22a and 22b for storage. A further single-pole, double-throw switch 24 is also controlled by controller 16, and couples the outputs of memories of 22a and 22b by way of a data path 26 to an error coding block illustrated as 28. Switch 24 is controlled in conjunction with switch 18 so that the memories 22a and 22b are written into and read alternately, in a fashion known as &#34;ping-pong&#34;. 
     In the illustrated position of switch 24, memory 22b is being read under control of controller 16, and the burst of data information stored therein is applied to error coding block 28, which encodes the data and applies it to a time-division multiplex (MPX) block 30. Controller 16 also controls a preamble generator 32 which generates a predetermined preamble in association with each burst of information data. Multiplex block 30 combines the preamble and coded information data, and applies the multiplexed signals over a data path 34 to an MSK modulator 36. MSK modulator 36 modulates the signals onto a carrier. The modulated MSK signals, including MSK symbols representative of the preamble and information data, are applied over a path 38 to an upconverter 40, which upconverts the frequency of the modulated signal to a frequency established by the frequency of local oscillator 42. The upconverted signal is applied from upconverter 40 to an antenna 44, which transmits the signal, as suggested by an arrow 46. 
     FIG. 2 illustrates the relationship of the preamble to the information data at the output of MSK modulator 36 of FIG. 1 in a particular embodiment of the invention. In FIG. 2, a first portion of the preamble is a continuous-wave (CW) portion 210 having a duration equal to 108 bits. Following CW portion 210, a start-of-message (SOM) portion 212 has a duration of 216 bits. Following SOM 212, the information data portion 214 has a length which may be fixed or variable as the information burst length may require. As also illustrated in FIG. 2, start-of-message portion 212 includes a bit/word sync portion 216 having a duration of 20 words, followed by a message sync portion 218 having a duration of 9 words. As illustrated in FIG. 2, the start-of-message portion also includes an order wire (OW) portion 220, which is not particularly related to the invention, and which may be considered to be a portion of the information signal. Each word of bit/word sync portion 216 and message sync portion 218 of the preamble has seven bits, so that the bit/word sync portion and message sync portion together represent 29 words, each of which is a sequence of 7 bits, for a total of 203 bits. Each of the 20 words of bit/word sync portion 216 of the preamble of FIG. 2 is the same word, designated A o . Preferably, the bits of each of the words of bit/word sync portion 216 are selected for low autocorrelation as, for example, by use of a Barker sequence. In the case of 7 bits per word, a 7-bit Barker sequence A.sub. o =111-1-11-1 may be used. The words of the message sync portion 218 are selected from among cyclic shifts of the 7-bit Barker sequence A 4 , A 2 , A 5 , A 3 , A 5 , A 2 , A 4 , A 0 , A 0 , where A i  is A 0  cyclically shifted to the left by i bits. For example, A 2  equals 1-1-11-111. 
     FIG. 3 is a simplified block diagram, designated as 310, of a receiver in accordance with the invention. In FIG. 3, transmitted signals 46 are received by an antenna 344. The received signals can be represented as ##EQU1## where T is the channel bit duration, f c  is the carrier frequency, θ is the unknown signal phase, A I  (t) and A Q  (t) are the even and odd transmitted bit sequences, respectively. The parameter S is the signal power given by S=RE b  /T, where R is the FEC code rate and E b  is the energy per data bit. The quantity n(t) is the received noise process, which is usually modelled as an additive white Gaussian noise (AWGN) with single-sided spectral density N O . 
     The received signals are applied to a downconverter 340, which receives in-phase (I) and quadrature (Q) components of local oscillator signals from a local oscillator 342. Since local oscillator 342 is different from local oscillator 42 of FIG. 1, is in a different environment, and is supplied with energizing voltage from a different source, its frequency will, in general, be different from the frequency of local oscillator 42. The downconverted signal produced on signal path 312 by downconverter 340, therefore, causes the MSK carrier to include a phase drift or phase error component. 
     More specifically, the downconverter generates the in-phase baseband analog signals, represented as ##EQU2## and the quadrature baseband analog signals, represented as ##EQU3## where Δf is the error in estimating the carrier frequency, and LPF denotes low-pass filtering, which removes high-frequency terms or components. 
     In FIG. 3, the downconverted x(t) and y(t) burst signals are applied from data path 312 to an analog-to-digital converter (ADC) 314, which samples the incoming signal, and produces digital signal samples at a rate of at least two, and preferably four or more, digital samples per bit of the incoming signal. Four samples per bit corresponds to eight samples per MSK symbol. 
     The sampled, digitized signal is applied from ADC 314 over a data path 316 to a memory (RAM) 318 in which the entire burst signal, including the start-of-message portion of the preamble and the information data, are stored. The CW portion of the preamble is applied directly to a frequency acquisition apparatus illustrated as 320, which adjusts the frequency of local oscillator 342 toward the frequency of the received carrier. RAM 318 and frequency acquisition block 320 are part of a preamble processing arrangement 328. 
     In general, the frequency of local oscillator 342 cannot be adjusted to be identical to the frequency of the received signal. As a result, the effective phase of the MSK carrier will include a phase progression component. The information stored in memory 318 of FIG. 3 includes the effect of this time-varying phase error. 
     A timing acquisition block 322 is coupled to RAM 318 and to a ROM memory 326 in FIG. 3. ROM 326 is preloaded with information equivalent to a replica of start-of-message portion 212 of the preamble of FIG. 2, including all twenty-nine sequences of seven bits each of the bit/word sync portion 216 and message sync portion 218. Bit/word timing block 322 compares the bit/word sync portion of the received message from RAM memory 318, as described below, with the stored information from ROM memory 326. The resulting bit and word timing information is then made available to a phase change estimation block illustrated as 324, in which stored copies of the received information from RAM 318 are further compared with stored replicas of the preamble from ROM 326, to determine or form an estimate of (a) the phase of the MSK carrier at the beginning of the start-of-message portion of the received signal, and (b) the phase change per bit across the preamble of the message, or more particularly across the bit/word sync and the message sync portions of the preamble. The resulting phase information is applied over a data path 329 to a phase tracking block 330, which combines the beginning-of-SOM phase with the phase-change-per-bit information to produce a demodulation carrier. The demodulation carrier is applied to a coherent MSK demodulator 332 together with stored data. Bit decisions are made in demodulator 332, which are applied back to phase tracking block 330 to allow data direction of the MSK carrier phase. The results of demodulation are also applied to a decoder block 334 for further processing. 
     While FIG. 3 illustrates discrete processor blocks such as 322, 324 and 330, these blocks and others may be incorporated into a single software-controlled processor in known manner. 
     Block 322 of FIG. 3 evaluates bit and word timing by repeatedly correlating the stored I and Q samples of the received signal with a replica of one of the 20 identical words of the bit/word synchronization portion of the SOM provided by ROM memory 326. The correlation window is advanced in a positive or negative direction by a time period corresponding to one sample interval. At four samples per bit, and with 7 bits in each of the 20 words of the bit/word sync portion of the preamble, a total of 28 correlations are performed for each word. Each of the 28 correlations of one word is added to the corresponding correlation of the next word. This process of computing 28 correlations and adding to the accumulated correlations continues until a correlation peak can clearly be identified. The largest correlation peak indicates the correct bit and word timing to within one sample interval. While bit and word timing are established by the above-described correlation, the starting time of the SOM is not yet established. 
     Once the correct bit/word timing relationship between the preamble information in ROM 326 and the received preamble stored in RAM 318 is known, the starting time of the message synchronization portion 218 of FIG. 2 can be established. This is accomplished by correlating the stored received message synchronization signal with the stored replica of the message synchronization signal in ROM 326. Since bit/word timing has already been established, the correlations for message sync detection are performed at each word boundary, and the correlation window is advanced by one word at a time. The message sync portion of the SOM has nine words, each of seven bits. A message sync correlation is the sum of nine correlations, each seven bits long. The largest value of the message synch correlation peaks identifies the timing of the message synchronization portion. 
     The duration of the word/sync portion of the start-of-message is known, so the time of the beginning of the bit/word synchronization portion is determined, to within one sample interval, by subtracting the known duration of the bit/word synchronization portion from the previously determined starting time of the message sync portion of the start-of-message portion of the preamble. 
     When the bit, word and message timing has been determined, as described above, in block 322 of FIG. 3, the MSK symbol phase acquisition process may begin. According to an aspect of the invention, phase acquisition and tracking are initiated in block 324 of FIG. 3 by, in general, estimating the phase change per bit Δ b , the signal phase θ, and applying Δ b  to aid in tracking the signal phase during the SOM portion 212 and the information data portion 214 of the burst communication. 
     As mentioned above, when the error in estimating the MSK carrier frequency is non-zero, the signal phase drifts. One frequency synchronization technique gives a frequency error of 0.01/T, where T is the duration of one received bit, at 4 dB signal-to-noise, corresponding to 3.6°/bit. 
     The correlations are performed in symbol correlation block 319. An in-phase symbol correlation XCORR evaluated at sampling time j is defined as ##EQU4## where x; is the value of x(t) at the i th  sampling time instant, the factor &#34;4&#34; causes the summation to take place at a corresponding sampling time in each bit, and S i  is the amplitude of the MSK pulse: 
     
         S.sub.i =sin(i π/8+π/16)                             (5) 
    
     Similarly, the quadrature symbol correlation YCORR(i) is defined as ##EQU5## These correlations are performed by correlating the stored I and Q samples with a template S i  of an MSK symbol stored in ROM 326. As in the correlations described above, the correlation window is advanced at each repetition, but by one bit of the preamble, rather than by one sample interval. This produces N pairs of XCORR and YCORR values, where N is the number of bits in the start-of-message portion 212 and the data portion 214 of FIG. 2. These values are stored in symbol correlation block 319 for use by the phase change estimation block 324, the phase tracking block 330 and the coherent MSK demodulation block 332. 
     The symbol correlations for the SOM portion of the preamble are combined coherently over the duration of the 7-bit sequences to form word correlations. The word correlation portion is performed by the phase change estimation block 324. Consider the bit sequence 111-1-11-1 of word A0 of FIG. 2. The in-phase and quadrature channel bit sequences are A I  =11-1-1 and A Q  =1-11. The sequence of seven transmitted MSK symbols has the polarities: ++-+-++, and is represented as P(0)=11-11-111. The polarity representations P(M) for sequences AM, M=2, 3, 4 and 5 can be determined similarly. Note that A 1  and A 6  are not used in the SOM. Suppose the word correlation begins at sample k and is for sequence M. Block 324 of FIG. 3 determines Z C  and Z S , the unadjusted in-phase and quadrature word correlations, respectively, for each word of the start-of-message portion of the preamble: ##EQU6## where P (M, j) is the jth component of P(M), the factor 8 is the number of samples per MSK symbol. 
     Equation (7) represents the sum of products of XCORR multiplied by the MSK symbol pulse polarity for the four even-numbered bits within each word, from which is subtracted the product of YCORR multiplied by the MSK symbol polarity for the three odd-numbered bits in the word. The first bit of each word is numbered zero. 
     The in-phase and quadrature word correlations R c  and R s , respectively, which are proportional to the cos θ and sin θ terms, respectively, where θ is the signal phase to be estimated, are related to Z c  and Z s . For the bit sequence corresponding to the first word of bit word sync portion 216 (i.e. for sequence 0), R c  =Z s  and R s  =Z s . For the sequence of bits corresponding to the second word of bit/word sync portion 210 (i.e. for sequence 1), the roles of A I  and A Q  are reversed, and R c  =Z s  and R s  =-Z c , where the minus sign accounts for the phase shift of π radians at the end of sequence 0 as a result of the MSK carrier having gone through a phase shift equal to an odd integer multiple of π radians. Similarly, for each of the bit sequences of the 29 words in the start-of-message portion 212 of the preamble, the values of R c  and R s  are listed in TABLE 1, where M4 is the number of bits counted modulo 4 from the beginning of the preamble to the beginning of the word, not counting the bits in the current word. 
     
                       TABLE 1                                                     
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SEQUENCE        M4        R.sub.c   R.sub.s                               
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0,4,8, . . . 24,28                                                        
                0         Z.sub.c   Z.sub.s                               
1,5,9, . . . 25 3         Z.sub.s   -Z.sub.c                              
2,6,10, . . . 26                                                          
                2         -Z.sub.c  -Z.sub.s                              
3,7,11, . . . 27                                                          
                1         -Z.sub.s  Z.sub.c                               
______________________________________                                    
 
    
     The phase drift per bit Δ b  is estimated by determining the phase of each 7-bit Barker sequence of a word, taking the difference of the phase estimates of the bit sequences of adjacent words, and averaging all the estimated phase differences. The estimate of the phase of a 7-bit Barker sequence is defined as the estimate of the phase 8 of the middle bit (the fourth bit) of the sequence, 
     
         θ=tan.sup.-1 (R.sub.S /R.sub.C)                      (9) 
    
     where can range from -π to π by taking into account the signs of R c  and R s . 
     The rate of change of phase per seven-bit word is ##EQU7## where is the estimated phase of word i, where i=0 for the first word of the SOM. As explained below, word 28 is not used in estimating the phase change. 
     Estimated rate of change of phase As is unbiased, i.e., not subject to a bias due to the effects of the polarities of adjacent bits. Other choices of start-of-message sequences may result in a bias requiring correction. The word 28 is not used since it would introduce a bias in the phase change estimate. 
     Since there are seven bits per sequence, the rate of phase change per bit is 
     
         Δ.sub.b =Δ.sub.S /7                            (11) 
    
     Computer simulations have shown that Δ b  can be estimated with an accuracy of about 0.1° for Δf=0.02/T and E b  /N 0  =4 dB. Estimating the rate of change of phase is equivalent to obtaining a better estimate of frequency. The computer simulation results in reduction of Δf to 0.0003/T. 
     The estimated value of Δ b  is applied to phase tracking block 330 of FIG. 3 to aid in tracking signal phase. The initial MSK carrier phase estimate is θ 0 , which is the phase estimate of word 0 computed above in conjunction with the estimation of phase change. This phase estimate is refined as described below in conjunction with FIG. 4 using the start-of-message and a second-order phase tracking loop. During tracking, the estimate of signal phase is incremented (positive or negative) by Δ b  per bit. Since Δ b  has an accuracy which may be 0.1° per bit, the MSK carrier signal phase being acquired and tracked changes by at most 0.1° per bit. Such a small uncompensated rate of phase change will allow the loop bandwidth to be reduced to achieve a good phase estimation performance at low SNRs typical of FEC-coded systems. 
     The estimated phase change per bit (Δ b ) and the estimated phase of word 0 θ are passed from the phase change estimation block 324 over data path 329 to the phase tracking block 330 of FIG. 3. 
     FIG. 4 is a simplified block diagram of a phase tracking loop in accordance with the invention, which is the phase tracking block 330 of FIG. 3. In FIG. 4, the XCORR and YCORR values calculated by and stored in the symbol correlation block 319 are applied to an error signal generator 410 together with the estimated signal phase φ k  of the current bit. Initially, only the start-of-message data is used to acquire carrier phase. Block 410 uses previously determined values of XCORR and YCORR to compute signals r c  and r s , which are related to the sine and cosine, respectively, of the phase error Δθ. When the bit count is even 
     
         r.sub.c =XCORR cosφ.sub.k +YCORR sinφ.sub.k r.sub.s =YCORR cosφ.sub.k -XCORR sinφ.sub.k                      (12) 
    
     and when the bit count is odd, 
     
         r.sub.c =-YCORR COSφ.sub.k +XCORR Sinφ.sub.k r.sub.s ==XCORR COSφ.sub.k -YCORR Sinφ.sub.k                      (13) 
    
     where φ k  iS the current estimated carrier phase. The bit count starts with 0 for the first bit of the SOM. 
     The effects of preamble modulation are removed by multiplying r c  and r s  by m k , the polarity of the k th  MSK pulse, which is either +1 or -1. 
     
         r&#39;.sub.c =m.sub.k r.sub.c r&#39;.sub.s =m.sub.k r.sub.s        (14) 
    
     so that r&#39; c  are r&#39; s  are proportional to the cosine and sine, respectively, of the phase error of the unmodulated MSK carrier. 
     A new estimate e of the phase error is made 
     
         e=tan.sup.-1 (r&#39;.sub.s /r&#39;.sub.c)-γ                  (15) 
    
     where γ is a bias attributable to unequal polarities of the bits, b k-1  and b k+1 , which are next adjacent to the current bit b k . The value of γ=0 if b k-1  =b k+1 , and γ˜0.57 b k-1  b k  otherwise, because tan -1  (2/π)=0.57 radians. The value of the bias term γ can be derived by noting that when r&#39; c  is normalized to unity (one), and if the phase error is zero, r&#39; s  equals 2/π if the current bit b k  equals the previous bit b k-1 , and r s  &#39; equals -2/π otherwise. 
     The error signal e produced by block 410 of FIG. 4 is limited in magnitude to form ek, the loop error signal ##EQU8## where limiting value X is expressed in radians. 
     Generator 410 of FIG. 4 generates a loop error signal e k  for the k th  bit as described above. The error signals e k  are applied from generator 410 to a block 412, together with f k , the residual phase change over one bit. Block 412 determines the values of g k , the residual phase shift over two bits, 
     
         g.sub.k =2f.sub.k-1 +β.sub.1 e.sub.k-1 +β.sub.2 e.sub.k-2(17) 
    
     where f k-1  iS a stored value of f k  from a previous loop traversal, and where β 1  and β 2  are loop parameters related to a parameter β by 
     
         β.sub.1 =2(1-e.sup.-β cosβ) β.sub.2 =e.sup.-2β -1(18) 
    
     The residual phase change over two bits ( g  k), which is produced by block 412 of FIG. 4, is applied to a block 416. Block 416 determines the current bit phase estimate φ k  as the sum of the phase estimate φ k-2  previously determined for the 2 nd  prior bit, plus twice the previously determined phase drift or phase change Δb over one bit, plus the residual phase shift over two bits (g k ) 
     
         φ.sub.k =φ.sub.k-2 +2Δ.sub.b +g.sub.k        (19) 
    
     The value of φ k  is applied back to error signal generator 410 for processing as described above in conjunction with block 410, and is also applied to a block 414. Block 414 determines f k , the residual phase shift over one bit, according to 
     
         f.sub.k =φ.sub.k -φ.sub.k-1 -Δ.sub.b         (20) 
    
     which is the difference between the phase of the current bit and the prior bit, from which is subtracted the previously determined phase change or phase drift per bit Δ b . 
     The loop of FIG. 4 generates estimated phase signals φ k  from the bits of the start-of-message portion of the preamble. Phase acquisition begins at bit count 3 of the start-of-message portion of the preamble, because the processing requires knowledge of the phase of the 2 nd  preceding, preceding, and following bits, relative to the current bit. Phase acquisition ends at bit count 202 of the SOM, which is the last bit for which the value is known a priori. 
     The second-order digital loop of FIG. 4 has an impulse response similar to that of an analog loop with a damping factor 1/2. the noise bandwidth B L  of the loop is, for B&lt;&lt;1, B L  ˜3β/2. 
     The loop of FIG. 4 is initially set with the values φ 3= φ 0  ; φ 2  =φ 0  -Δ b  ; e 3  =0; e 2  =0, where φ 0  is the estimate of the phase of word 0, described in conjunction with equations 9 and 10. Simulations have indicated that the value of parameter β for use in the loop of FIG. 4 should be near β=0.02, but that the bit error rate (BER) changes by only small amounts when B is /2 larger or smaller than 0.02. A value of β=0.01 resulted in a 2 dB degradation in BER at E b  /N 0  =6 dB. 
     The loop of FIG. 4 used to acquire the signal phase from the preamble is also used for phase tracking during the information data portion of the message. The advantage of using the same tracking loop is that the loop has already reached steady-state operation before data demodulation begins. Starting from bit count 203 after the start-of-message portion of the preamble, the transmitted bits are not known a priori. 
     Consequently, decision-directed tracking is employed in blocks 330 and 332 of FIG. 3, in conjunction with the loop of FIG. 4. The decision-directed tracking is identical to the tracking described above with the exception that b k-1 , b k  and b k+1  are demodulated bit values instead of known bit values. A decision must be made whether an information data bit is 1 or -1. The bit decisions are performed by coherent MSK demodulation block 332. When the bit count k, starting from the beginning of the start-of-message portion of the preamble, is even, the value r k , representing the matched filter output with the signal phase removed, is determined 
     
         r.sub.k =XCORR cosψ.sub.k +YCORR sinψ.sub.k        (21) 
    
     when bit count k is odd 
     
         r.sub.k =YCORR cosψ.sub.k +XCORR sinψ.sub.k        (22) 
    
     where ψ k  is the phase estimate provided by phase estimation block 330. The coherent MSK demodulation block 330 sets 
     
         Z.sub.k =r.sub.k for (k mod 4)=0, or 1 Z.sub.k =-r.sub.k for (k mod 4)=2, or 3. 
    
     The decision rule for bit modulation or polarity b k  is ##EQU9## An initial bit decision for the next following bit, b k+1 , is made by using φ k  +Δ b  in place of φ k  in equations 21 and 22, and the initial bit decision is redetermined when the new phase estimate is available. 
     During reception of a burst, the storage of the preamble, and multiple readouts for processing, might appear to cause a considerable delay, which might prevent acquisition of an immediately following burst. However, bit/word sync processing can begin almost immediately after the beginning of reception, and need not wait for reception and storage of the data portion of the MSK burst, nor even for completion of the reception and storage of the preamble. The carrier phase can be acquired before reception of the message portion of the burst is completed. Demodulation can therefore begin on the earlier-received portions of the message data before reception of the message portion is completed. The demodulation rate is not limited by the rate of data reception, but by the processor speed, which is likely to be much greater. The demodulation can therefore &#34;catch up&#34; with the data, and demodulation may be completed essentially concurrently with the end of the message data. 
     Other embodiments of the invention will be apparent to those skilled in the art. For example, other sequences can be used in place of the Barker sequences described. Factors affecting the choice may include the sidelobe levels of the sequence selected; the coherent integration time, with longer sequences having a longer integration time and therefore requiring a better frequency estimate; the processing capability of the receiver hardware, and the like. Also, while the preamble has been illustrated and described as preceding the information data, it may be within or follow the information data, since the entire sequence of information and preamble is stored and may be processed in any order when retrieved from memory. For similar reasons, the bit/word sync portion of the preamble may follow the message sync portion. An alternative technique for processing the continuous-wave portion of the preamble for frequency acquisition is to couple data path 312 to frequency acquisition block 320 to couple the analog signal thereto.