Down-bonded lead-on-chip type semiconductor device
BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor device, and more particularly to a semiconductor device which enables a down bonding and a mounting of a multi-pin in :semiconductor package. 
     The lead-on-chip (LOC) technique is introduced so as to make a large chip to be easily loaded in the standard package, for the semiconductor element, especially for a RAM-structured memory chip. And the strengthening of the chip characteristic was possible owing to the LOC technique. 
     Additionally, in a semiconductor memory device, method of down bonding the Vss or Vcc terminal is used for suppressing a latch-up so as to keep the characteristics of an element against the change of the external voltage for dynamic random access memory (DRAM). This method is also used for noise dispersion and speed enhancement for static random access memory (SRAM). The down bonding method means that the semiconductor element is connected with the pattern terminal for use in bonding formed on a top surface of the element, having the active surface of the element as a bottom surface thereof. 
     A bus-bar or conductive film is bonded in order to perform the down bonding in the LOC or chip-on-lead (COL) type semiconductor package wherein the chip attach pad is not provided. However, the mounting of multi-pin for this case is difficult. 
     The down bonding method of the conventional semiconductor package by referring to FIG. 1 to FIG. 6 is explained as follows: 
     First, FIGS. 1 and 2 acre the embodiments of the conventional bonding method, and illustrate the down bonding method for plastic package when the lead frame wherein the die attach pad is provided is used. FIG. 1 shows the case when the tie bar connected to die pad is down-bonded, while FIG. 2 shows the case when the wing-tip of die pad is down-bonded. 
     Referring to FIG. 1 and FIG. 2, when the sawing process wherein a multiple of chips formed on semiconductor wafer are sawed into separate chips and the quality chips are selected among the above separated chips is finished, the above quality chips 1 are detached from wafer. Then, the detached chips are attached on a die pad 8, and the wire bonding wherein bonding pads 2 and 3 of chip 1 are connected as shown in 5 and 5&#39; to leads 4 and 4&#39; is performed. At this time, the down bonding which supports a specific pad among the bonding pads of chip 1 is performed, and a tie bar 6 which supports die pad 8 is down-bonded 7 in FIG. 1, while a wing-tip 9, i.e., a protrusion of die pad 8 is down-bonded in FIG. 2. 
     FIG. 3 and FIG. 4 are the sectional views of FIG. 1 and FIG. 2, respectively. 
     As shown in FIG. 3 and FIG. 4, chip 1 separated from the semiconductor wafer is attached on die pad 8 whereon a conductive adhesive 10 is deposited. Then, a down bonding 7 is performed to tie bar 6 which supports die pad 8 or to wing-tip 9. 
     FIG. 5 and FIG. 6 show the embodiments of the bonding method of the conventional LOC type-package, and explain the down bonding method for the case of using the lead frame wherein the chip attach pad is not provided. FIG. 5 shows the case when the conductive film is used, while FIG. 6 shows the case when the bus-bar is used. 
     Referring to FIG. 5 and FIG. 6, the wire bonding which connects (15 and 15&#39;) a bonding pad 17 of the chip and leads 19 and 19&#39; on each individual chip 11 separated from the semiconductor wafer is performed after the sawing process is completed. At this time, down bonding which supports the specific pad among the bonding pads of the chip is performed, and down bondings 12, 12&#39;, 13 and 14 are performed for a conductive film 16 on chip 11 in FIG. 5, while down bondings 12, 14, 15 and 15&#39; are performed for Vcc or Vss bus-bars 20 and 21 in FIG. 6. The reference numerals 16&#39;, 17&#39; and 18 which are not explained in FIGS. 5 and 6 indicate an insulating tape, a bus-bar bonding pad and a Vcc or Vss lead, respectively. 
     Size of the conductive film and bus-bar region cannot be sufficiently expanded, when the down bonding is performed for the above conventional LOC-type package, and accordingly, the mounting of multi-pin is difficult. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a semiconductor device wherein the characteristics of an element is strengthened and the mounting of a multi-pin is made easy due to the conductive film attached to entire bottom surface of a chip. 
     To accomplish the above object, there is provided a semiconductor device comprising a semiconductor element; a lead-on-chip-type lead group For use as an electrical connection between the semiconductor element and an external circuit; a member which connects electrically between each lead of the lead group and each corresponding bonding pad placed on the top surface of the semiconductor element, and consists of encapsulating the semiconductor element, connecting member and the part of each lead using a resin, wherein the semiconductor device comprises a conductive member attached to the bottom surface of the semiconductor element to be electrically transmitted, and extended outside one side of the semiconductor element in which the leads are not placed, and wherein the extended part of the conductive member and the corresponding bonding pad on the top surface of the semiconductor element are down-bonded using the same member as that of the connecting member. 
     In addition to this, there is provided a semiconductor device comprising a semiconductor element wherein a plurality of bonding pads disposed on the center of the top surface in the lengthwise direction are provided; a pair of insulating tape attached to the left and right of the bonding pads on the top surface of the semiconductor element and extended in the lengthwise direction; a pair of lead group wherein a plurality of leads whose one end is electrically connected to the external circuit and the other end is extended to the top surface of the insulating tape in the direction of crossing the insulating tape and is electrically connected to the semiconductor element, are arranged in parallel by a predetermined spacing; a pair of power bus-bar which ranges partially on the insulating rope between the pair of lead group and the bonding pads at least, and extends lengthwise, having an both end parts horizontal to the leads; a conductive member attached to the bottom surface of the semiconductor element and extends from one side of the semiconductor element wherein the lead group is not provided to outside, and at least one part of the extended portion has a conductive layer for down bonding; and a connecting member which electrically connects the pair of lead group, the pair of power bus-bar, and the conductive member with each corresponding bonding pads. 
     Further, there is provided a semiconductor device comprising a semiconductor element wherein a central bonding pad line arranged in the lengthwise direction by a first predetermined spacing is provided on the center of the top surface, and a pair of edge bonding pad line arranged in the lengthwise direction by a second predetermined spacing is provided in the right and left edges of the top surface; a pair of insulating tape attached between the central bonding pad line and each edge bonding pad line on the top surface of the semiconductor element, and extended lengthwise; a pair of first lead group wherein a plurality of leads whose one end is electrically connected to an external circuit and the other end comes close to the edge bonding pad from the outside of one side of the semiconductor element and is electrically connected to each edge bonding pad of the semiconductor element, are arranged parallel in a third predetermined spacing; a pair of second lead group wherein a plurality of leads whose one end is electrically connected to the external circuit and the other end is extended to the insulating tape and is electrically connected to the each center bonding pads, are placed between each lead of the first lead group; a conductive member attached to the bottom surface of the semiconductor element and extended from one side of the semiconductor element wherein the first and second lead group is not placed to outside, and at least one part of the extended portion has a conductive layer for down bonding; and a connecting member which electrically connects the pair of first and second lead group, and the conductive member with each corresponding bonding pad. 
     According to a preferred embodiment of the present invention, the conductive member comprises an adhesive tape whose width is larger than that of the bottom surface of the semiconductor element and a conductive layer extended lengthwise along the center of the top surface of the adhesive tape, and a conductive polyimide adhesive tape is used as the adhesive tape. 
     Additionally, the conductive member can comprise a conductive adhesive tape whose width is larger than that of the bottom surface of the semiconductor element and a conductive layer which is formed on the part of the top surface of the conductive adhesive tape extended outside one side of the semiconductor element, whereto the connecting member is attached. 
     The present invention enables a down bonding in LOC-type package since the present invention uses the structure wherein a conductive member adhered to the bottom surface of a chip, which then is connected to the specific pad of a semiconductor element by a connecting member. 
     Further, the mounting density of the semiconductor package is increased since the present invention uses the structure wherein the multi-pin are arranged having minimized the lead spacing on the chip. 
     Accordingly, the present invention enables better suppression of a latch-up, noise dispersion and speed improvement as compared with the conventional LOC-type package. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objects and other advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which: 
     FIGS. 1 and 2 show the embodiment of the bonding method of the conventional semiconductor device; 
     FIGS. 3 and 4 are the sectional views of FIGS. 1 and 2 respectively; 
     FIGS. 5 and 6 show the embodiment of the bonding method of the conventional LOC-type package; 
     FIG. 7 shows the semiconductor device according to the bonding method of the present invention; 
     FIG. 8 shows the semiconductor device according to an embodiment of the present invention; 
     FIGS. 9 and 10 are the section views taken along A--A&#39; and B-B&#39; of FIG. 8, respectively; and 
     FIGS. 11A-11C and 12A-12C show the conductive member used for the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention will be described below in more detail with reference to the attached drawings. 
     FIG. 7 shows the semiconductor device according to the bonding method of the present invention, and specifically shows the LOC-type semiconductor package. 
     Referring to FIG. 7, a plurality of bonding pads 35 are arranged in the lengthwise direction of a chip 37 on the center of the top surface of chip 37 separated from the semiconductor wafer after the sawing process is finished. A conductive member attached to the bottom surface of chip 37 and comprises an adhesive tape 32, for example, a conductive polyimide tape whose width is larger than that of the bottom surface of the chip, and an adhesive pad 31, i.e, a conductive layer extended lengthwise of the chip on the center of top surface of adhesive tape 32. An insulating tape 34 is extended in the lengthwise direction of chip 37 and attached to the right and left of bonding pads 35 on the chip&#39;s top surface. Leads 39, which is provided as an electrical connection with the chip, adheres chip 37 by insulating tape 34. 
     The extended region of the adhesive pad 31, i.e., a conductive layer adhered to the bottom surface of chip 37, and a specific pad 35&#39; of chip 37 are connected to a first wire 33, i.e., a connecting member, and then are down-bonded. 
     Bonding pads 35 on the top surface of chip 37 are connected to leads 39 by a second wire 42, and connected to a power bus bar 38 by third wires 36 and 43. 
     As described above, the problem that the size of the conductive film and the region of bus-bar are not able to be extended when the conventional LOC-type package is down-bonded can be solved since the entire bottom surface of the chip can be used for down bonding. 
     FIG.8 shows the semiconductor device wherein the mounting of a multi-pin is made possible according to an embodiment of the present invention, having a view of the inside of the semiconductor package from above. 
     As shown in FIG. 8, central bonding pads 35 are disposed lengthwise of chip 37 by a first predetermined spacing, on the center of the top surface of chip 37 wherein the adhesive pad (reference numeral 31 of FIG. 7), i.e., a conductive member, adhered to the bottom surface. Also, edge bonding pads 40 are disposed lengthwise of chip 37 by a second predetermined spacing, at the right and left edges of the top surface of chip 37. 
     A pair of insulating tape 34 is attached to the top surface of chip 37 between central bonding pad 35 line and edge bonding pad 40 line, in the lengthwise direction of chip 37. 
     The leads electrically connected to chip 37 are divided into two lead groups and disposed. A first lead group 39&#39; is disposed by a third predetermined spacing, wherein one end is electrically connected to the external circuit and the other end comes close from the outside of the side of chip 37 to each edge bonding pad 40 and electrically connected to each edge bonding pad 40. A second lead group 39 is disposed between each lead of first lead group 39&#39;, wherein one end is electrically connected to the external circuit and the other end is extended to insulating tape 34 attached to the top surface of chip 37 and electrically connected to each central bonding pad 35. First and second lead groups 39&#39; and 39 adhered to chip 37 by insulating tape 34. 
     Second lead group 39, i.e, a LOC-type lead, which is connected to the inside of the semiconductor package and disposed on the top surface of chip 37, is connected to, central bonding pads 35 by second wire 42, i.e., a connecting member. First lead group 39&#39; which is disposed outside chip 37 is connected to edge bonding pads 40 by a fourth wire 41. 
     Also, specific pad 35&#39; of chip 37 and the conductive adhesive pad 31, i.e., a conductive member adhered to the bottom surface of chip 37 are down-bonded by first wire 33. Conductive adhesive pad 31 is attached to the bottom surface of chip 37, and extends to the outside from one side of the chip wherein first and second lead group 39 and 39&#39; are not disposed, and has a conductive layer on the part of the extended portion for down bonding. 
     According to an embodiment of the present invention, the multi-pin can be disposed smoothly by dividing the leads electrically connected to the chip into the center and right and left edges of the top surface of the chip. Further, the down bonding is possible using the conductive member adhered to the bottom surface of the chip. 
     FIG. 9 and FIG. 10 are the section views taken along A-A&#39; and B-B&#39; of FIG. 8, respectively. 
     Referring to FIG. 9 and FIG. 10, central and edge bonding pads 35 and 40 are disposed on the center and the right and left edges of the top surface of chip 37 separated from the semiconductor wafer. Central bonding pad 35 is connected to second lead group 39, i.e., a LOC-type lead, by second wire 42, and the edge bonding pad 40 is connected to first lead group 39&#39; disposed outside chip 37, by fourth wire 41. First and second lead group 39 and 39&#39; adhered to chip 37 by insulating tape 34. 
     Conductive adhesive pad 31, i.e., a conductive member, adhered to the bottom surface of chip 37 by an adhesive 45, and specific pad 35&#39; of chip 37 is down-bonded to conductive adhesive pad 31 by first wire 33. 
     Chip 37 and lead groups 39 and 39&#39; wherein the wire bonding connection is completed, are encapsulated by a package mold 50. At this time, package mold 50 encapsulates as much as the area of lead groups 39 and 39&#39;, wherein one end electrically connected to the external circuit is excluded. 
     FIGS. 11A-11C and FIG. 12A-12C show the structure of the conductive member of the bottom surface of the chip used for the present invention. 
     Referring to FIGS. 11A-C, a conductive metal is extended in a bar-shape on the center of an adhesive tape 54, for example, a conductive polyimide tape, as a conductive layer 51 so as to perform down bonding which supports the specific pad of a chip. A region 52 wherein the down bonding is performed is located at the end of conductive layer 51, i.e., a conductive metal, and a region 53 marked in dotted line indicates the region wherein the chip adhered to adhesive tape 54. The size of adhesive tape 54 is larger than that of the width of the bottom surface of chip 37, and conductive layer 51 extends in the lengthwise direction of chip 37. The conductive member of the present invention can comprise adhesive tape 54 of which size is larger than the width of the bottom surface of chip and the bar-shaped conductive layer which is extended lengthwise along the center of adhesive tape 54. 
     Referring to FIGS. 12A-12C, the bottom surface of chip adhered to the top surface of conductive adhesive tape 54, for example a conductive polyimide tape larger than the width of the bottom surface of chip. Also, conductive layer 51 for down bonding, for example a conductive metal, is formed on the part of the top surface of conductive adhesive tape 54 outside one side of chip 37. Region 52 to be down-bonded is located in the center of the conductive layer 51. The conductive member of the present invention can comprise the conductive adhesive tape larger than the width of the bottom surface of the chip and the conductive layer which is formed on the part of the top surface of the conductive adhesive tape extended outside one side of the chip. 
     Therefore, since the entire bottom surface of the chip wherein the conductive member adhered can be used for the down bonding according to the present invention, the down bonding is possible for the LOC-type package. Also, a mounting density can be increased since the multi-pin is made possible. Additionally, the balance of the thickness between the top and bottom mold of semiconductor package can be maintained to thereby improve an yield and ensure a highly reliable product. 
     The present invention enables more effective latch-up suppression, noise dispersion and speed improvement than the conventional LOC-type package structure. 
     It should be understood although preferred embodiments of the invention have been described in detail above, many modifications and variations could be effected therein by one with ordinary skill in the art without departing from the spirit and scope of the invention as defined by the appended claims.