Bipolar ECL to inverted CMOS level translator
FIELD OF THE INVENTION 
     The present invention relates generally to the field of electronic digital integrated circuits. In particular, the present invention pertains to a level translator circuit, which can be implemented in bipolar ECL technology, and which provides output levels suitable for driving low voltage CMOS integrated circuits. 
     BACKGROUND OF THE INVENTION 
     In the field of electronic integrated circuits, a number of different technologies and processes have been developed, resulting in the availability of a number of different families of integrated circuit types. Two examples which are discussed herein are bipolar and CMOS. Each of these families has its own advantages and disadvantages, in terms of operating speed, density, power consumption, cost, noise immunity, and other factors. The choice of integrated circuit type for a given application is often a balancing of these various factors. Because different IC types are best suited for different applications, there will be situations in which different IC types are brought together in a single system. However, this presents a problem in terms of interconnections, because the different technologies use different voltages, polarity and other electrical parameters. This leads to the need for various types of external level shifting and signal translation circuits, but this adds to the cost, space and power requirements for a system. 
     The present invention provides a level shifter circuitry on board a chip of one IC technology, to thereby provide the necessary level shifting and interface for direct connection to an IC of another technology. The preferred embodiment is directed to providing signals from a bipolar IC to a CMOS IC. One application for the invention would be in a system which uses a CMOS microprocessor, with bipolar supporting circuitry, where it is necessary for the bipolar IC to send logic signals to the CMOS IC. 
     SUMMARY OF THE INVENTION 
     The present invention provides an improved level shifter-driver that can be implemented on an IC of one chip technology, and which provides an output suitable for driving an input of an IC of a different chip technology. The preferred embodiment provides a level shifting circuity implemented in a bipolar IC, for providing signals suitable for driving LVCMOS (low voltage CMOS). In this manner logic signals developed on the bipolar IC can be output to an LVCMOS IC. 
     The improved driver includes a level shifter for receiving a logic signal in bipolar levels from circuitry on the bipolar IC, and applying a shifted signal to a high gain bootstrap circuit. The high gain bootstrap circuit responds to, and reinforces the logic level applied thereto by the level shifter, so as to switch cleanly on or off, according to the input state even for worst case conditions of input signal. An output of the high gain bootstrap circuit connects indirectly to the common ground voltage, and through a clamping circuit to a negative voltage, corresponding to the inverted rail CMOS levels. The output thus provided is suitable for driving inverted rail LVCMOS levels. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawing, FIG. 1 shows a bipolar implementation of the driver circuit of the present invention, suitable for developing output voltages for use in inverted rail LVCMOS chips. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The circuit is implemented in bipolar transistor technology, and the supply levels therefor are indicated throughout the FIGURE by reference voltages V CC , V EE1  and V EE2 . Specifically, V CC  equals 0 volts; V EE1  equals -4.5 volts; and V EE2  equals -3.3 volts. 
     Input 30 receives a signal developed or transmitted elsewhere on the bipolar IC chip. This is a normal level ECL (emitter coupled logic) level. It is applied to a level shifting network which is made up of transistors Q7,Q8, and associated components. Specifically, input 30 connects to the base of transistor Q7, and the emitter of transistor Q7 connects to the base of transistor Q8. The collectors of both transistors are connected to V CC . A resistor R8 connects from the Q7 emitter/Q8 base, to V EE1 . The emitter of transistor Q8 connects through resistor R1 to a node 31. The ratio of the resistors determines the shifted level. 
     Node 31 can be thought of as the input to a high gain bootstrap circuit which is composed of transistors Q1-Q6, and associated components. The differential pair Q1,Q2 are switched by the operation of the high gain bootstrap circuit, as is described below, such that one of the pair will be on and the other off, and vice versa, in the two switched states of the circuit. 
     The base of transistor Q1 connects to node 31, and its collector connects V CC . The base of transistor Q2 connects to node 32, and its collector connects to node 40, which becomes the output of the driver circuit. The emitters of the pair Q1,Q2 are connected in common through resistor R5 to V EE1 . Transistor Q5 is connected with its base and collector to node 31, and its emitter connects through resistor R4 to V EE1 . In similar fashion, transistor Q6 has its collector and base connected to node 32, and its emitter connected through R6 to V EE1 . 
     Transistor Q3 has its collector connected to node 31 and its emitter connected through resistor R3 to V EE1 . The base of transistor Q3 is connected to node 32. Similarly, transistor Q4 has its collector connected to node 32, its emitter connected through R7 to V EE1 , and its base connected to node 31. Transistor Q9 has its collector connected to V CC , its base to a reference voltage V BB2 , which in effect provides the switching threshold reference for the circuit. The emitter of Q9 is connected through R2 to node 32. 
     Output 40 connects through resistor R 0  to V CC . Node 40 is also connected to a clamping circuit, formed from transistors Q10,Q11 and associated circuitry. Specifically, the emitter of transistor Q10 connects to node 40, and its collector connects to V CC . Transistor Q11 has its emitter connected to V EE2  =-3.3 volts. The bases of transistor Q10,Q11 are connected together, and to the collector of Q11, all of which connect through resistor R11 to V CC . 
     The operation of the circuit is as follows. If the input signal to input 30 is high, transistors Q7 and Q8 will be turned on, and the signal at node 31 will also be high, although shifted to a level to help keep the differential pair Q1,Q2 properly biased. 
     With node 31 high, transistor Q4 is turned on, and the current developed through transistor Q4 will pull down the voltage at node 32. Since the node 32 is coupled to the base of transistor Q3, this reduces the current in Q3, which reinforces the high level at node 31. In this situation, Q1 is turned on, and Q2 is turned off. The bootstrapped gain from the positive feedback action provided by transistor Q3 and Q4 guarantees that the pair Q1,Q2 will be fully switched even for the worst case of input conditions. 
     With Q2 fully switched off, the output 40 is pulled up V CC  or 0 volts, through resistor  R0 . This level corresponds to one of the inverted rail CMOS levels needed by a CMOS IC that would be connected to receive the output 40. 
     When the input 30 goes low, transistors Q7 and Q8 will be turned off and node 31 will go low. This tends to reduce the current through transistor Q4, allowing the voltage at node 32 to go high. This in turn causes transistor Q3 to conduct, which further reinforces the lowering of the voltage at node 32. Once again the high gain bootstrapped positive feedback action ensures a complete switching. Q1 is then off and Q2 is on. 
     With Q2 on, the voltage at output 40 is driven low. There is sufficient gain in the clamping circuit and sufficient drive is applied thereto to activate transistors Q10 and Q11 to clamp the output at V EE2  (-3.3 volts). This level corresponds to the other state for the inverted rail CMOS input level. 
     In this manner the switching of the normal ECL level applied to input 30 causes a corresponding switching of output 40, between 0 and -3.3 volt levels, which can then be used to drive CMOS compatible levels. 
     It will be understood by those skilled in the art that the present invention is not limited to the circuit embodiment discussed above, but may be changed or modified without departing from the spirit or scope of the invention.