Circuit for generating very small currents
This is a continuation of PCT application PCT/EP 92/00774, filed Apr. 6, 1992, and titled CIRCUIT FOR GENERATING VERY LOW CURRENTS. The invention relates to circuitry for generating very small currents. 
     BACKGROUND OF THE INVENTION 
     Very small currents, for example, in the nA range, may be generated by current balancing (reflection) with the aid of multiple emitter circuits, but the currents generated in such manner are dependent upon parameter tolerances and temperature. In addition, such circuits require relatively large chip area if they are implemented in integrated circuits. Examples of the foregoing current balancing circuits may be found in U.S. Pat. Nos. 3,867,685; 3,952,257; 4,030,042; 4,045,694; 4,055,774; 4,225,816. It is the object or the present invention to specify a circuit with which very small currents can be generated. 
     SUMMARY OF THE INVENTION 
     In principle, the invention consists of current balancing circuitry which is coupled with further circuitry for modifying the size of the balanced current, whereby the relationship of a reference current (I ref ) applied to the current balancing circuitry to a current (I out , I out  &#39;) made available by the size modification circuitry can be adjusted using one or more components (R, R&#39;) contained in the size modification circuitry. The current balancing circuitry and the circuitry for modifying the size of the current each may contain one or more transistors, and the adjustment component contained within the size modification circuitry can consist of one resistor (R) or several resistors (R, R&#39;). 
     The relationship of the reference current of the current balancing circuit to the first output current at the collector of the output transistor can be adjusted by reducing the value of a first resistance in the emitter of the output transistor of a current balancing circuit. By adding a second current balancing stage with a second resistor R&#39; contained therein and with a second output current, there results, for R=R&#39;, the relationship of the first output current to the second output current corresponding to the relationship of the reference current to the first output current whereby only a relatively small chip area is necessary when using an integrated circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a current balancing stage. 
     FIGS. 2 and 3 are schematic diagrams of alternative current balancing circuits embodying the present invention. 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1, a current balancing stage includes an unbalanced current mirror amplifier circuit including a master transistor 13 and a slave transistor 14. The master transistor 13 has base and collector electrodes interconnected and coupled to a source of reference current (I ref ) 11. An emitter electrode of the master transistor 13 is connected to ground potential. The base electrode of the slave transistor 14 is connected to the base electrode of master transistor 13. The emitter electrode of the slave transistor 14 is coupled to ground potential through an impedance component such as a resistor R, and output current Iout is available from a collector electrode of transistor 14. The ratio of I ref  to I out  can be adjusted via the dimensioning of the impedance component, e.g. the resistance of resistor R 
     
         I.sub.out * R=U.sub.τ * ln(I.sub.ref /I.sub.out), 
    
     where U.sub.τ is the thermal voltage of the respective transistors, which are presumed to be in close proximity such that both transistors exhibit the same temperature. I out  can be further reduced by forming the master transistor 13 as a multiple transistor. Then the following relationship is valid: 
     
         I.sub.out * R=U.sub.τ * ln(I.sub.ref *k/I.sub.out), 
    
     where k is the number of transistors connected in parallel forming the master transistor, each of which is identical in geometry or conductance as the slave transistor 14. Alternatively, the transistor 13 may be constructed in any known manner which permits of forming different transistors with relative conductances which are highly predictable, such as transistors with different pluralities of similar base-emitter junctions or transistors with different relative geometry&#39;s where relative conductance of respective transistors may be accurately predicted by their relative geometric features. 
     FIG. 2 illustrates a graded current balancing circuit having a composite current mirror including a source of reference current (Iref) 21, first current master transistor 23, a first slave transistor 24 and a resistor R, connected similarly to the corresponding elements in FIG. 1. The collector of the first slave transistor 24 supplies the output current I out . A further impedance component, e.g., resistor R&#39; is coupled between the base electrode of the master transistor 23, and the base electrode of a transistor 28. Transistor 28 has a collector electrode connected to its base electrode and an emitter electrode connected to ground potential. 
     The base-collector interconnection of transistor 28 is connected to the base electrode of a transistor 27. Transistor 27 has an emitter electrode coupled to the emitter electrode of slave transistor 24 and a collector electrode from which a further output current, Iout&#39;, is available. The current Iout&#39; has an amplitude which is less than the amplitude of the output current Iout. Transistors 28 and 27 operate as a further current mirror with transistors 28 and 27 operating as master and slave respectively, and resistor R&#39; acting as an input current source. If resistors R and R&#39; are equal the following relationship is valid: 
     
         I.sub.out * R=U.sub.τ * ln(I.sub.ref /I.sub.out). 
    
     Advantageously, I out  &#39; can be further reduced by arranging transistor 28 as a multiple transistor. Then, for R=R&#39;: 
     
         I.sub.out * R=U.sub.τ * ln(I.sub.ref /(I.sub.out &#39;*n)). 
    
     where n is the number of transistors connected in parallel to form the transistor 28. 
     If both of the first transistors 24 and 28 are replaced by k, or respectively, n multiple transistors, then for R=R&#39;; 
     
         I.sub.out * R=U.sub.τ * ln(I.sub.ref *k/I.sub.out), 
    
     
         I.sub.out * R=U.sub.τ * ln(I.sub.ref /(I.sub.out &#39;*n). 
    
     Advantageously with R=R&#39; and k=n=l, there results for I out  /I out  &#39; the same current ratio as for I ref  /I out . 
     In this manner, current sources, for example, for the range 1 . . . 500 nA, may be realized with relatively small silicon area in integrated circuit form. Such current sources are useful in realizing integrated integrator circuits with long integration times, for example, in the range 0.015 . . . 0.06 s, and very small integration capacitances, for example, in the range 5 . . . 20 pF. 
     FIG. 3 shows a further embodiment, which is substantially similar to that of FIG. 2, and operates in similar fashion. However the FIG. 3 embodiment includes a switchable current source I off  connected to the interconnection of the emitter electrodes of the slave transistors and the resistor R. The current source I off , when conditioned to conduct will cause the currents Iout and I out  &#39; to be substantially zero. 
     The magnitude of current I off  is equal to or greater than an the amount which will cause the product of I off  times R to be greater than or equal to about 0.5 volts. A voltage of this magnitude, at the emitters of transistors 34 and 37, is sufficient to reverse bias the emitter-base junctions of transistors 34 and 37, and thereby cease conduction in the collector electrodes of the transistors 34 and 37. 
     In the claims the term current source is used in the conventional sense to mean apparatus which provides an output current at an output terminal substantially independent of the voltage potential appearing at the output terminal. The current source may be either a time varying or a constant current source.