Apparatus and method for performing small scale subtraction
FIELD OF THE INVENTION 
     The present invention relates to a subtracting circuit. 
     BACKGROUND OF THE INVENTION 
     Conventionally, a digital type subtracting circuit operate on a large scale and an analog type subtracting circuit operates with low accuracy in its calculation. 
     SUMMARY OF THE INVENTION 
     The present invention is invented so as to solve the conventional problems. It has a purpose to provide a subtracting circuit capable of performing a subtracting calculation on a small scale with high accuracy. Calculation through this subtracting circuit is therefore easily available for various kinds of calculation manners. 
     According to the present invention, an inverter is serially connected to an output terminal of two inputs which are coupled capacitively at an input terminal. Another inverter is connected to an output terminal of the above inverter as well as to an output terminal or another dual input capacitive coupling circuit. Accordingly the latter inverter outputs a subtraction result. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing an embodiment of the present invention. 
    
    
     PREFERRED EMBODIMENT OF THE INVENTION 
     Hereinafter, an embodiment of a subtracting circuit according to the present invention is described with referring to the attached drawings. 
     In FIG. 1, a subtracting circuit is composed of the first dual input capacitive coupling circuit CP 1 , the second dual input capacitive coupling circuit CP 2 , the first inverter INV 1  and the second inverter INV 2 . 
     In the first dual input capacitive coupling circuit C P1 , a voltage V 1  and a voltage V 01  are respectively input to capacitors C 1  and C 01 . Voltage V 2  is input through a capacitance C 2 . 
     C P1  is composed of capacitances C 1  and C 01  which are parallelly connected with the first inverter INV 1 . A capacitance C 2  is also connected with INV 1 . A feedback circuit FC is provided for feeding an output of inverter INV 1  back to its input through a capacitance C 01  in order to get an effect of a summing amplifier. 
     When voltages for impressing C 1 , C 01  and C 2  are V 1 , V 01  and V 2 , respectively, an input voltage V 00  for INV 1  is defined as following formula (1). ##EQU1## 
     INV 1  is composed of 3 inverters serially connected. An output of the first inverter changes to low level when V 00  exceeds a threshold voltage. An output of the next inverter changes to high level. Then, an output of the last inverter changes to low level. When the output voltage is defined as V 01 , V 01  can be obtained by formula (2). 
     
         V.sub.01 =-A.sub.1 V.sub.00                                (2) 
    
     where A1 is an open loop gain. 
     When formula (2) is input to formula (1) after transforming the formula, formulas (3) and (4) can be obtained. ##EQU2## Here, the first term in parentheses of formula (4) can be omitted as it is negligible compared with the second term of it. So formula (4) is substantially defined as formula (5). ##EQU3## 
     In the second dual input capacitive coupling circuit C p2 , voltage V 01  and a voltage V out  from an output terminal of INV 2  are input, voltage V 3  is also input through a capacitance C 3 . Capacitances C 02  and C 03  are parallelly connected within C P2  for input to the second inverter INV 2 . Capacitance C 3  is connected to INV 2  in parallel with C 02  and C 03 . 
     A feedback circuit FC feeds an output from inverter INV 2  back to its input through a capacitance C 03  in order to get an effect of summing amplifier. 
     Voltage which are applied to C 02 , C 03  and C 3  are V 01 , V OUT  so that V 3 , respectively, and an input voltage V 02  for INV 2  is defined as following formula (6). ##EQU4## 
     An inverter INV 2  is composed of 3 inverters by serial connecting, similar to INV 1 . An output of the first inverter changes to low level when V 02  exceeds a threshold voltage. An output of the next inverter changes to high level. Then an output of the last inverter changes to low level. When the output voltage is defined V out , then formula (7) is obtained, according to the same reason of above formulas from (2) to (5). ##EQU5## Here, inputting formula (5) to formula (7) and transforming it, formulas (8) and (9) are obtained. ##EQU6## Here if C 01  is equal to C 02 , then formula (10) is obtained. ##EQU7## 
     As a result, subtraction result is substantially obtained. 
     As mentioned above, an inverter is serially connected to an output terminal of the dual input capacitive coupling circuit provided at an input terminal, another inverter is connected to an output terminal of the above inverters as well as to an output terminal of another capacitive coupling circuit connected with another two inputs of voltage. The latter inverter outputs a subtraction result, so that the present invention has a purpose to provide a subtracting circuit capable of subtracting calculation with small scale and high accuracy and easily realize a various kinds of manners of calculations.