Circuit and method of providing thermal compensation for a transistor to minimize offset voltage due to self-heating of associated devices
BACKGROUND OF THE INVENTION 
     The invention relates to a circuit and method which provide thermal compensation for associated devices in a signal path in order to minimize shifts in offset voltages due to self-heating. 
     Conventional bipolar transistors operate approximately in accordance with the following equation: ##EQU1## where i c , i b , and i e  are the collector, base, and emitter currents, respectively, i s  is the saturation current for the transistor with predetermined geometry and doping, V BE  is the base-emitter voltage, and q/kT is the reciprocal of the thermal voltage. Accordingly, solving for V BE  results as follows: ##EQU2## where i s  =i d  e.sup.(-qEgo/kT), i d  being a predetermined constant and E go  being a constant approximately equal to 1.2V. 
     Substituting i s  into equation (1) and simplifying results in the following: ##EQU3## 
     With respect to the above equations, it will be appreciated that for a given transistor, variances in temperature result in opposing changes in the base-emitter voltage. For example, for an increase in temperature in the transistor, the base-emitter voltage required to activate the transistor decreases. This relationship becomes critical when utilizing such transistors in matched pair configurations. 
     Matched pairs of transistors are commonly utilized as differential pairs in gain block circuits such as operational amplifiers and comparators, where a differential voltage is used as an input. The predetermined input offset voltage V os  (the negative of the input voltage which must be applied across the input terminals of the pair in order to obtain zero output voltage) for such devices is ideally 0V, and in practice is a few millivolts. When the differential pair is used primarily for large signal operation, the small offset voltage is acceptable. When used in applications where a small input voltage represents some measured quantity as in a converter, meter, or measuring device, any nonzero input offset voltage can result in substantial error. 
     Offset voltage errors typically occur due to initial matching differences and to temperature drift in component parameters. Temperature drift refers to the change in input offset voltage resulting from change in temperature. The drift components may be compensated by introducing complementary temperature coefficients within the circuit. A common source of drift is local heating of diode junctions and resistive components having non-zero temperature coefficients. 
     Devices which are fabricated in dielectrically isolated processes exhibit much higher thermal resistances of individual devices than junction isolated processes, thus there is an even greater need for thermal compensation to prevent shifts in offset voltages due to self-heating. Full dielectric isolation is achieved by using silicon-on-silicon insulator wafers and trenching the silicon layer. 
     A cross-section of an exemplary NPN transistor 10 fabricated using an exemplary dielectrically isolated process is shown in FIG. 1. Initially, a silicon substrate 11 is subjected to an anisotropic etch which removes all the silicon in a specified area, and selectively stops at a buried silicon oxide layer 14 to form a trench 16. The trench is preferably 2 um wide and approximately 6 um deep. The trench 16 is then filled with polysilicon and oxide which eventually form a polysilicon barrier 18 and silicon dioxide barrier 20 to form a dielectrically isolated region 13 after doping. 
     The silicon substrate 11 consists of a p-type epitaxial layer which is counterdoped with a heavily doped n +  -type buried layer 22 and a lightly doped n-type diffusion 24 from the epitaxial layer surface (PNP devices are fabricated using p-type epitaxial layer with a heavily doped p +  -type buried layer). The upward diffusion of the buried layer 22 merges with the downward diffusion of the surface implant 24 and reverses the conductivity type of the epitaxial layer. The bases of the NPN and PNP (not shown) are formed by boron and phosphorus implants, respectively, or any desired p-type base diffusion 26. An extrinsic p-type base diffusion 28 is used to make an ohmic contact to the metallic base contact 27. A n-type diffusion 30, preferably arsenic, is implanted (boron for P-emitters) in the emitter material, preferably polysilicon. Deep contact diffusions 32 (plugs) are used for collector contacts in both NPN and PNP transistors. The collector plugs 32 help reduce collector (Rc) series resistance. An emitter diffusion 33 is also provided inside the plug and the extrinsic part of the bases to form ohmic contacts to these areas. Metallic contacts for the base 27, emitter 31, and collector 34 are formed using a conventional process. 
     Devices fabricated with such processes exhibit enhanced thermal isolation, and therefore are more susceptible to shifts in offset voltage due to self-heating during operation. Conventional methods for compensating for these self-heating effects include utilizing excessively large devices, degenerating and cascoding current mirrors, and running the transistors at lower currents. The use of excessively large devices have associated area and speed drawbacks. Degenerating and cascoding has a headroom disadvantage and can only be used with current mirrors, and not with differential pairs, to decrease self-heating effects. Operating transistors at lower currents has an associated device speed liability. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide thermal compensation for self-heating effects of associated devices. 
     It is a further object of the invention to vary the temperature of a transistor in order to modify the operational electrical charactersistics of the transistor. 
     Accordingly, the present invention is a circuit and method for varying the temperature of a transistor configured within an isolated electrical region in order to thermally compensate for self-heating effects of an associated device in a common signal path with the transistor. The circuit includes heat generating means, provided separately from the transistor within said isolated electrical region and adapted to be thermally coupled to the transistor, for generating heat which modifies the temperature and in turn the operational electrical characteristics of the transistor so as to minimize shifts in offset voltage. 
     In one embodiment of the invention, the transistor is a first bipolar transistor configured within an isolated collector region, and the heating means is a second bipolar transistor provided within the isolated collector region and thermally coupled to the first transistor. The second transistor is operable for providing heat to said first transistor so as to alter the temperature to a predetermined level, thus changing said operational voltage characteristics of the first transistor so as to minimize shifts in offset voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a cross-section view of an NPN transistor fabricated in a dielectrically isolated process; 
     FIG. 2 shows one embodiment of the present invention utilized in connection with an NPN transistor fabricated in a dielectrically process; 
     FIG. 3 shows a circuit schematic diagram of an embodiment of the present invention; 
     FIG. 4 shows a circuit diagram of a differential input circuit utilizing the present invention; 
     FIG. 5 shows a block diagram of an exemplary differential circuit; 
     FIGS. 6 and 7 show graphic results of voltage offset measurements in a circuit not utilizing the present invention; and 
     FIGS. 8 and 9 show graphic results of voltage offset measurements in a circuit utilizing the present invention. 
    
    
     DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS 
     With reference now to FIG. 2, a cross-section view of the present invention is shown as including a second base-emitter region 35 implemented with a NPN transistor 10 fabricated in a dielectrically isolated process. The second base-emitter region 35 is primarily configured with a p-type base diffusion 36 and a n-type emitter diffusion 40 with associated metallic contact 41. An extrinsic p-type base diffusion 38 coupled to metallic contact 37 is also used to make an ohmic contact to the base. The base-emitter region 35 utilizes the collector region 32 as a common collector to effectively form a second transistor within the dielectrically isolated region 13. The second transistor will preferably serve as a heating transistor as will be described hereinafter. 
     FIG. 3 shows a circuit schematic diagram of the present invention which includes a bipolar transistor 50, having base 51 coupled to input signal source 54, collector 52, and emitter 53; and a second bipolar transistor 56 having base 57 coupled to signal source 59, emitter 58, and utilizing collector 52 as a common collector. In one preferred embodiment of the present invention, the transistor 50, and more particularly the emitter 53 is used as a signal buffer for the signal provided from signal source 54. The second transistor 56 is utilized to heat the transistor 50 when activated by a signal applied from signal source 59. Accordingly, the transistor 56 heats the transistor 50 in order to vary the operational voltage characteristics of transistor 50. This operation serves to compensate for self-heating effects of associated devices in the signal path. 
     For illustrative purposes, the present invention will be described in accordance with an application as an input differential gain stage 60 of a comparator device as shown in FIG. 4. A differential input signal to the comparator is applied across inputs PIN and NIN. The input signal is buffered by transistors 61, 62 (Q1 and Q2) and applied to a differential pair, consisting of transistors 63, 64 (Q3 and Q4). The resultant differential current then flows through a folded cascode, consisting of transistors 65, 66 (Q5 and Q6), and induces a differential voltage at the top of resistors 67, 68 (R3 and R4). In the illustration provided, the gain of the first stage is about 13 V/V (differential out/differential in). 
     A problem occurs if the differential input is fixed at a large value for a significant length of time. For instance, if PIN is raised above NIN by 100 mV, substantially all of the current from current source I3 flows through transistor 63 (Q3), thus causing the transistor 63 (Q3) to warm and the transistor 64 (Q4) to cool. Accordingly, the operational characteristics of transistor 64 (Q4) will be different from transistor 63 (Q3) due to their difference in temperature. When the differential input voltage changes to zero, it will take several thermal time constants (τ≈3 to 5 uS) for the transistors 63, 64 (Q3 and Q4) to reach the same temperature, hence, zero offset voltage V os . 
     As described above, the present invention involves creating an extra base-emitter region in the respective collector pockets of transistor 61 (Q1) and transistor 62 (Q2), so as to form heating transistors 70, 72 (Q1H and Q2H). Therefore, if the connections are made as indicated in the schematic of FIG. 4, with the addition of an extra current source I4, the heating transistor 70 (Q1H) will act as a heater so as to alter the emitter temperature of transistor 61 (Q1) in such a manner as to cancel the effects of self-heating of transistor 64 (Q4). The heating transistor 72 (Q2H) will, in the same way, act as a heater for altering the emitter temperature of transistor 62 (Q2) so as to cancel the effects of self-heating of the transistor 63 (Q3). 
     Several advantages are derived from such a configuration of the present invention. For example, the circuit of the present invention does not change the operating condition of the signal transistors, eg. no modulation of current. In addition the circuit minimizes collector base capacitance of the input devices, since the base region of the input transistors does not change. Furthermore, the configuration minimizes the amount of components required, in this instance the circuit only needed an extra current source and heating transistors. 
     Resulting input offset voltage V os  of an exemplary differential circuit shown in FIG. 5 was estimated in simulation tests with and without the heating transistors Q1H and Q2H of the present invention. The exemplary circuit was configured to produce a differential output (Pout-Nout) equal to V os  *100. The simulation results show that when the differential input is a large fixed voltage, a 4.4 mV V os  will result due to device self-heating effects. With the use of present invention, the V os  shift, due to self-heating, is reduced to under 1 mV. 
     FIGS. 6 and 7 show graphic results, of self-heating, of V os  *100 when the heating transistors are not utilized. FIG. 6 shows V os  *100 when the exemplary differential circuit has a 5V supply and the input is 100 mV (at the input) from 10 uS to 50 uS. Pout-Nout is equal to about 270 mV immediately following the return of the input signal to 0V. Hence, a 2.7 mV offset is induced at the input due to device self-heating. FIG. 7 shows the result when the exemplary differential circuit is running on a 10V supply. The result shows a 4.4 mV offset induced at the input. 
     FIGS. 8 and 9 show graphic results of V os  *100 when the heating transistors Q1H and Q2H are used. FIG. 8 shows the results of the thermal compensation from the heating transistors when the conditions are the same as in FIG. 6. With the heating transistors, only 0.8 mV of offset is induced at the input, compared to 2.7 mV without the compensation. FIG. 9 shows the results of V os  *100 when the heating transistors are utilized and the conditions are the same as in FIG. 7. Only 0.3 mV of offset is induced at the input, compared to 4.4 mV without the compensation. 
     The foregoing description has been set forth to illustrate the invention and is not intended to be limiting. Since modifications of the described embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the scope of the invention should be limited soley with reference to the appended claims and equivalents thereof.