Image pickup signal processing apparatus for performing nonlinear processing
This application is a continuation of U.S. application Ser. No. 07/618,989 filed Nov. 28, 1990, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an image pickup signal processing apparatus for performing nonlinear processing such as λ-correction and white compression processing. 
     2. Related Background Art 
     A conventional apparatus of this type is known and used in a variety of applications. Of these conventional applications, an apparatus having good frequency characteristics in nonlinear processing is shown in FIG. 4. 
     This processing apparatus comprises a VCA (Voltage-Controlled Amplifier) 31, amplifiers 32 and 35, a clamp circuit 33, a nonlinear processor 34, and an A/D (analog/digital) converter 36. The nonlinear processor 34 includes pnp transistors Q 1  to Q 7  and resistors R 1  to R 12 . 
     An operation of this processing apparatus will be described below. 
     A video input signal is amplified to an optimal signal level by the VCA 31 controlled by a gain control signal. The VCA 31 is arranged to correct the white balance. The level-controlled gain control signal is input to and amplified by the amplifier 32. The amplified signal is input to the clamp circuit 33, and the black level of the video signal is fixed to a predetermined potential. The clamped video signal is input to a buffer amplifier and a differential switch in the nonlinear processor 34. The buffer amplifier is constituted by the transistor Q 1  and the resistor R 1 . The differential switch is constituted by a set of the transistors Q 2  and Q 3  and the resistor R 2 , a set of the transistors Q 4  and Q 5  and the resistor R 3 , and a set of the transistors Q 6  and Q 7  and the resistor R 4 . The bases of the transistors Q 3 , Q 5 , and Q 7  receive reference voltages V A , V B , and V C  obtained by dividing a power source voltage V CC  through the resistors R 5  to R 8 . A clamp voltage V CP  and the above voltages V A , V B , V C , and V CC  satisfy the condition V CP  &lt;V A  &lt;V B  &lt;V C  &lt;V CC . 
     When the voltage of the video signal falls within the range between the voltages V A  and V B , the transistors Q 2 , Q 4 , and Q 7  are turned on, and the transistors Q 3 , Q 5 , and Q 6  turned off. The level of the video signal input is attenuated to R 12  /(R 9  //R 10  //R 11  +R 12 ) (where // represents a resistance of parallel-connected resistors) by the resistors R 9  to R 11 . 
     When the voltage of the video signal falls within the range between the voltages V CP  and V A , the level of the input video signal is attenuated to 1. When the voltage of the video signal falls within the range of the voltages V B  and V C , the level of the input video signal is attenuated to (R 11  //R 12 )/(R 9  //R 10  +R 11  //R 12 ). When the voltage of the video signal is V C  or more, its level is attenuated to (R 10  //R1 1  //R 12 )/(R 9  R 10  //R 11  //R 12 ). When the resistances of the resistors R 9  to R 12  are appropriately set, nonlinear processing such as λ-correction shown in FIG. 5 and white compression processing is performed in accordance with the nonlinear regression approximation. 
     The level of the nonlinearly processed video signal is amplified by the amplifier 35 into an optimal input level of the A/D converter 36. For example, the amplified signal is subjected to digital signal processing (not shown). 
     In this conventional processing apparatus, however, (a) when the voltages V CP , V A , V B , and V C  in FIG. 5 are close to each other, the response characteristics of the differential switch or variations in the reference voltages V A , V B , and V C  which are caused by variations in resistances of the resistors R 5  to R 8  become nonnegligible, and good nonlinear characteristics cannot be obtained at points of changes in regression approximation characteristics. 
     (b) In order to prevent the above drawback, the video signal is sufficiently amplified by the amplifier 32 to increase differences between the reference voltages. In this case, since the video signal in image pickup signal processing has a magnitude which is several times that of a normal television signal, the dynamic range of the amplifier 32 becomes insufficient. 
     (c) In the conventional apparatus, since nonlinear processing has attenuation characteristics, the video signal must match the input level of the A/D converter 36, which requires a relatively large amplitude. The circuit size is undesirably increased as a result. 
     In the conventional apparatus, gain control processing such as white balancing of the video input signal is performed by the VCA 31. In order to improve the frequency characteristics of the VCA 31 and to simplify its circuit arrangement, reference potentials across a ladder resistor circuit in the A/D converter 36 are changed to variably control the gain of the A/D converter 36, thereby performing gain control processing. 
     (d) In this case, nonlinear processing must be performed prior to gain control processing such as white balancing. In the conventional processing apparatus, however, since the nonlinear characteristics are fixed, the above arrangement cannot be realized, resulting in inconvenience. 
     SUMMARY OF THE INVENTION 
     The present invention has been made to solve these problems and to provide an image pickup signal processing apparatus having good nonlinear characteristics. 
     In order to achieve the above object of the present invention, the image pickup signal processing apparatus according to embodiments of the present invention is arranged as follows: 
     (1) An image pickup signal processing apparatus comprising an A/D converter, and a nonlinear signal processing means for comparing an image pickup signal input to the A/D converter with a potential obtained by voltage-dividing a reference voltage of the A/D converter and nonlinearly processing the image pickup signal; 
     (2) An image pickup signal processing apparatus as in (1) above, wherein the nonlinear signal processing means comprises a negative feedback amplifier, and a negative feedback amount of the negative feedback amplifier is changed to generate nonlinear characteristics; 
     (3) An image pickup signal processing apparatus as in (1) above, wherein the reference voltage of the A/D converter is changed to use the A/D converter also as a voltage-controlled amplifier; and 
     (4) An image pickup signal processing apparatus as in (1) above, wherein the nonlinear signal processing means fixes the black level of the image pickup signal to a predetermined potential. 
     According to the arrangements (1) to (4) described above, the video signal having a large amplitude and serving as an input to the A/D converter is compared with the potential obtained by dividing the reference voltage of the A/D converter, and nonlinear processing of the video signal is performed based on the result of comparison. 
     In the arrangement (2), the nonlinear characteristics are generated by the negative feedback amount of the negative feedback amplifier. In the arrangement (3), the A/D converter also serves as the voltage-controlled amplifier. In the arrangement (4), the black level of the image pickup signal is fixed by the nonlinear signal processing means. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of the first embodiment according to the present invention; 
     FIG. 2 is a block diagram showing the main part of the second embodiment according to the present invention; 
     FIG. 3 is a circuit diagram showing the main part of the third embodiment according to the present invention; 
     FIG. 4 is a circuit diagram showing a conventional apparatus; and 
     FIG. 5 is a graph showing nonlinear characteristics of λ correction and white compression processing. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will be described in detail with reference to the preferred embodiments. 
     FIG. 1 is a circuit diagram of an image pickup signal processing apparatus according to an embodiment of the present invention. The processing apparatus comprises a negative feedback amplifier 1, a clamp circuit 2, a buffer amplifier/differential switch unit 3, and a parallel comparison-type 8-bit A/D converter 4. The buffer amplifier/differential switch unit 3 is constituted by resistors R&#39; 1  to R&#39; 18  and transistors Q 1  to Q 11 . The A/D converter 4 comprises ladder resistors R 1  to R 256 , comparators C 1  to C 255 , and an encoder circuit 4&#39;. 
     An operation of the image pickup signal processing apparatus will be described below. A video input inversion signal is inverted and amplified by the negative feedback amplifier 1. The resistors R&#39; 1  and R&#39; 2  serve as input and feedback resistors for the amplifier 1, respectively. The resistors R&#39; 3  and R&#39; 4  serve as resistors for setting a DC level of the amplifier 1. The amplified video signal is input to the clamp circuit 2. A lower reference voltage V RB  for the A/D converter 4 is also input to the clamp circuit 2 to fix the black level of the video signal to V RB . 
     The clamped video signal is input to the buffer amplifier consisting of the transistors Q 1  and Q 2  and the resistors R&#39; 11  and R&#39; 12 , and the differential switch constituted by a set of the transistors Q 3  and Q 4  and the resistor R&#39; 13 , a set of the transistors Q 6  and Q 7  and the resistor R&#39; 15 , and a set of the transistors Q 9  and Q 10  and the resistor R&#39; 17 . The bases of the transistors Q 4 , Q 7 , and Q 10  in the differential switch receive voltages at predetermined taps of the ladder resistors. These voltages are obtained by dividing a voltage (V RT  -V RB ) between the upper and lower reference voltages by the ladder resistors R 1  to R 256  of the A/D converter 4 (V RB  &lt;V A  &lt;V B  &lt;V C  &lt;V RT ). 
     Assume that an output signal level of the clamp circuit 2 falls within the range between the voltages V A  and V B . 
     In this case, since the transistors Q 4 , Q 7 , and Q 9  are turned on, and the transistors Q 3 , Q 6 , and Q 10  are turned off, the output video signal from the amplifier 1 is negatively fed back to the input terminal of the amplifier 1 through the clamp circuit 2, the transistor Q 9 , and the resistor R&#39; 9 , thereby decreasing the gain of the amplifier 1. Similarly, when the output signal level of the clamp circuit 2 falls within the range between the voltages V RB  and V A , negative feedback is not performed. When the output signal level falls within the range between the voltages V B  and V C , a negative feedback loop is formed through the resistors R&#39; 7  and R&#39; 9 . When the output signal level falls within the range between the voltages V C  and V RT , a negative feedback loop is formed through the resistors R&#39; 5 , R&#39; 7 , and R&#39; 9 . Therefore, the gain varies depending on the amplitude levels of the video signal. Therefore, by appropriately setting the resistances of the resistors R&#39; 2 , R&#39; 5 , R&#39; 7 , and R&#39; 9 , nonlinear processing such as correction and white compression processing shown in FIG. 5 can be performed by the regression approximation. Note that the buffer amplifiers constituted by a pair of the transistor Q5 and the resistor R&#39; 14 , a pair of the transistor Q 8  and the resistor R&#39; 16 , and a pair of the transistor Q 11  and the resistor R&#39; 18  receive the voltages V C , V B , and V A  to bias the negative feedback amplifier 1 through the resistors R&#39; 6 , R&#39; 8 , and R&#39;10. This arrangement is adopted to compensate for DC bias conditions of the negative feedback amplifier 1 upon ON/OFF operation of the differential switch. Therefore, the resistances of the resistors R&#39; 5 , R&#39; 7 , and R&#39; 9  are set to be equal to those of R&#39; 6 , R&#39; 8 , and R&#39; 10 , respectively. 
     The nonlinearly processed video signal is supplied to the A/D converter 4 and is converted from the analog signal to a digital signal by the ladder resistors R 1  to R 256 , the comparators C 1  to C 255 , and the encoder circuit 4&#39;. The video signal is then output as a video signal. 
     The upper reference voltage for the A/D converter 4 is the above-mentioned gain control signal to perform, e.g., white balance processing. The gain control signal is used to variably control the reference voltages, thereby controlling the conversion gain of the A/D converter 4. Since the points of changes in nonlinear processing characteristics are set in accordance with tap potentials of the ladder resistors of the A/D converter 4, the points are changed in synchronism with the gain control signal. Therefore, the video signal prior to gain control can be optimally nonlinearly processed. In this case, the tap potentials of the ladder resistors are utilized. However, another voltage divider may be arranged to generate potentials of the points of changes by using the upper and lower reference voltages, thereby obtaining the same effect as described above. In this embodiment, three points of changes in nonlinear characteristics are used. However, various nonlinear characteristics may be realized, as a matter of course. 
     The A/D converter 4 comprises an 8-bit converter in this embodiment. However, the number of bits of the converter may be an arbitrary number. 
     As described above, the video signal having a large amplitude equal to the input level of the A/D converter 4 is compared with the high-precision potentials at the taps of the ladder resistors in the A/D converter 4 to operate the differential switch, thereby obtaining high-precision nonlinear characteristics. 
     FIG. 2 is a block diagram showing the main part of the second embodiment according to the present invention. This embodiment includes a typical serial/parallel A/D converter 11. 
     In place of the parallel comparison type A/D converter in FIG. 1, the serial/parallel A/D converter is used in the second embodiment. More specifically, tap potentials of ladder resistors serving as constituting elements of an a bit parallel comparison-type high order AD converter 5 or a b bit parallel comparison-type low order AD converter 6 are used as reference voltages for the differential switch. Other arrangements of the second embodiment are the same as those of the first embodiment. FIG. 3 is a circuit diagram showing the main part of the third embodiment according to the present invention. Tap potentials of ladder resistors of a serial/parallel A/D converter different from that of the second embodiment are utilized in the third embodiment. As described above, when the parallel comparison-type A/D converter is replaced with the serial/parallel A/D converter, the size of the A/D converter can be greatly reduced, and hence the circuit size of the image pickup signal processing apparatus can be reduced. 
     According to the present invention, as has been described above, the following effects (a) to (e) are obtained. 
     (a) The points of changes in nonlinear characteristics are determined on the basis of the video signal having a relatively large amplitude equal to the input level of the A/D converter and the tap potentials of the ladder resistors of the A/D converter which have small relative variations. High-precision nonlinear characteristics can be obtained. 
     (b) Since the nonlinear characteristics are obtained by changing the negative feedback amount of the amplifier, a sufficiently wide dynamic range of the amplifier can be assured. 
     (c) When a wide-band, high-gain amplifier is used as the negative feedback amplifier 1, only one amplifier need be used, and the circuit arrangement can be simplified. 
     (d) When the reference voltage of the A/D converter is variably controlled and the A/D converter is utilized as a voltage-controlled amplifier, the nonlinear characteristics can be changed in synchronism with the reference voltages. Processing such as white balance processing can be performed in this arrangement. 
     (e) Since the apparatus is arranged on the basis of the upper and lower reference voltages of the A/D converter, matching in each signal processing can be improved.