Memory cartridge including a key detector for inhibiting memory access and preventing undesirable write operations
This is a continuation of application Ser. No. 07/623,645, filed Dec. 18, 1990, now abandoned. 
    
    
     FIELD OF THE ART 
     The present invention relates to a memory cartridge. More specifically, the present invention relates to a memory cartridge which is loaded in an attachable/detachable manner into a data processing apparatus. 
     PRIOR ART 
     For example, in Japanese Patent Publication (Kokai) No. 63-245535 laid open on Oct. 12, 1988, a memory cartridge which is attachable to or detachable from a data processing apparatus such as a home video game machine is disclosed. In this prior art, a memory cartridge is provided with a random access memory (RAM), and the RAM is backed-up by a battery. 
     In an external memory cartridge having a RAM, if data is written in the RAM during an unstable voltage period T1 or T2 as shown in FIG. 7, the data is occasionally destroyed. Since a power-on (or power-off) reset is normally effected in the data processing apparatus during the period T1 or T2, it is impossible to access the RAM in the external memory cartridge (hereinafter referred to as simply the external RAM). If reset occurs during a time period when the power-on and the unstable voltage period T1 (or T2) shown in FIG. 7 deviate from each other, the external RAM may be accessed in the unstable voltage period T1 or T2. When the power supplied to the data processing apparatus exceeds a given level, a reset state is released so that it becomes possible to access the external RAM. However, that power source voltage is not always sufficient for a normal operation when the reset state is released. If a write operation occurs at this time to the external RAM, the data to be written is destroyed. 
     As a method for solving such a problem, there is a method in which a power source voltage of the data processing apparatus is strictly watched and a power-on (power-off) reset is released only when the power source voltage becomes a voltage level sufficient for normal, stable operation. However, such a power source voltage watching circuit requires additional components increases the cost of the whole system. 
     SUMMARY OF THE INVENTION 
     Therefore, a principal object of the present invention is to provide a memory cartridge in which it is possible to prevent data from being undesirably written to or read from an external RAM with a simple scheme. 
     The present invention is directed to a memory cartridge which can be loaded into a data processing apparatus in an attachable/detachable manner and which includes an external RAM; a program read only memory (ROM) programmed in advance so as to generate first key data representing that the external RAM is accessible; holding means for holding the first key data read from the program ROM; and control means for enabling the external RAM in response to a selection signal from the data processing apparatus when the first key data is held by the holding means. 
     The data read from the program ROM is held in the holding means. When the data is other than the first key data, the control means does not permit access to the external RAM by the data processing apparatus. Then, when the data held in the holding means is the first key data, in response to the selection signal from the data processing apparatus, the selection signal is applied to the external RAM by the controlling means, whereby the external RAM becomes accessible. 
     In accordance with the present invention, since the external RAM can be accessed by the data processing apparatus only when the first key data is read from the program ROM, it is possible to prevent the data from being undesirably written to or read from the external RAM. More specifically, the probability is very small that a step for reading the key data from the program ROM is executed in a state where a power source voltage is astable, and as a result, the external RAM is selected and becomes accessible only at times when the power source voltage is stable. 
     These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the embodiments of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a bank changing circuit of one embodiment in accordance with the present invention. 
     FIG. 2 is a perspective view showing one example of a gaming apparatus to which the present invention is applicable. 
     FIG. 3 is a block diagram showing a detailed structure of the FIG. 2 embodiment. 
     FIG. 4 is a memory map showing an address space of a CPU core shown in FIG. 3. 
     FIG. 5 is an illustrative view showing a portion of a program ROM. 
     FIG. 6 is a flowchart showing an operation of the present invention in one embodiment. 
     FIG. 7 is an illustrative view showing a state of a power source voltage of a main unit of a data processing apparatus. 
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     FIG. 2 is a perspective view showing one example of a hand-held liquid crystal gaming apparatus to which the present invention is applicable. However, it is pointed out in advance that the present invention is applicable to such a hand-held liquid crystal gaming apparatus as well as any other memory cartridge which is loaded into a main unit in an attachable/detachable manner and incorporates a RAM backed-up by a back-up battery. 
     This hand-held liquid crystal gaming apparatus (hereinafter, simply called as &#34;gaming apparatus&#34;) 10 includes a body 12 which includes on an upper surface thereof a liquid crystal display (LCD) panel 14 in which display segments are arranged in accordance with a dot-matrix system. 
     On a rear surface of the body 12, an insertion port (not shown) is formed at an upper portion, and a memory cartridge 16 is inserted thereto in an attachable/detachable manner as shown by a dotted line in FIG. 2. Then, a program ROM is incorporated in the memory cartridge 16, and game program data is stored in the program ROM in advance. Therefore, when the memory cartridge 16 is loaded to the body 12 of the gaming apparatus 10, the game program is executed and an image for a game can be displayed on the LCD panel 14. 
     A cross-key switch 18 for moving a game character on the LCD panel 14 is provided on the upper surface of the body 12. The cross-key switch has four direction designating portions, and by depressing any one of them, it is possible to move the game character up, down, left, or right. 
     With reference to FIG. 3, the above described memory cartridge 16 is connected to a CPU 22 housed in the body 12 by a 32-pin connector 20. The CPU 22 includes a CPU core 24 (including conventional hardware such as an arithmetic logic unit, associated registers, etc.) which is connected to the 32-pin connector 20 via a control bus 26a, an address bus 26b, and a data bus 26c. Therefore, when the memory cartridge 16 is loaded, the CPU core 24 and the memory cartridge 16 are connected to each other. 
     The cross-key switch 18 and other switches shown in FIG. 2 are connected to the CPU core 24 through a port 27. In association with the CPU core 24, an internal RAM (working RAM) 28 and an internal ROM 30 are provided. The internal ROM 30 is accessed by the CPU core 24 only when the ROM 30 is selected by a memory changing circuit 32. 
     The CPU core 24 outputs display data to an LCD controller 38 through a line buffer 36 under the control of a direct memory access (DMA) controller 34. Then, the LCD controller 38 is connected to a display RAM 42 via an LCD display RAM interface 40. Although not shown, the display RAM 42 includes a character RAM and a video RAM (VRAM). Therefore, the LCD controller 38 converts the display data outputted from the CPU core 24 into an LCD drive signal which is output from the display RAM 42. More specifically, the display data from the CPU core 24 designates addresses of the character RAM and the VRAM so that a character (or object) signal and a background signal can be output therefrom, and respective signals are mixed with each other by the LCD controller 39 so as to generate the LCD drive signal. 
     Then, the LCD drive signal is applied to an LCD common driver 46 and an LCD segment driver 48 through an LCD drive signal buffer 44. Accordingly, an image in accordance with the display data from the CPU core 24 can be displayed on the LCD panel 14 by the LCD common driver 46 and the LCD segment driver 48. In addition, an LCD intensity adjuster 50 is connected to an LCD buffer amplifier 52. By operating the LCD intensity adjuster 50, it is possible to adjust the light intensity on the LCD panel 14. 
     As described above, the memory cartridge 16 in accordance with the present invention is loaded into the data processing apparatus, i.e. CPU 22, in an attachable/detachable manner. The memory cartridge 16 includes a program ROM 54 which stores program data for operating the CPU core 24 of the CPU 22. The program ROM 54 has a memory area of two mega bits, for example. The memory cartridge 16 further includes a bank changing circuit 56 for switching between banks of the program ROM 54 (shown in FIG. 4), and an external RAM 58 is included in the bank changing circuit 56. However, the external RAM 58 may be provided separately from the bank changing circuit 56. 
     A back-up power source is applied to the bank changing circuit 56, i.e. the external RAM 58 from a battery 60 such as a lithium battery. A voltage from the battery 60 is applied to the external RAM 58 through a forward direction switch, i.e., diode 62a. However, the external RAM 58 is further supplied with a voltage Vcc from the body through a forward direction switch, i.e., diode 62b. Therefore, the voltage of the battery 60 is applied to the external RAM 58 only when the power source voltage Vcc from the body is less than a reverse bias voltage of the diode 62a. 
     The control bus 26a, address bus 26b and data bus 26c, being connected to the CPU core 24, are connected to the program ROM 54 and the bank changing circuit 56 of the memory cartridge 16 through the connector 20. 
     In addition, in association with the CPU 22, as shown in FIGS. 2 and 3, the body 12 is provided with a power source switch 64 through which the power source voltage Vcc is applied. A reset circuit 66 is connected to the voltage source Vcc and, when the power source voltage Vcc through the reset circuit 66 is less than a predetermined level, the CPU core 24 outputs a reset signal so as to disable all the circuits. When the voltage from the reset circuit 66, i.e. the power source voltage Vcc, reaches the predetermined level, the CPU core 24 releases such a reset state so as to enable all the circuits. 
     An address space of the CPU core 24 is from the address &#34;0000H&#34; to the address &#34;DFFFH&#34; as shown in FIG. 4. It is noted that &#34;H&#34; is representative of a hexadecimal number. The addresses &#34;0000H-7FFFH&#34; are assigned for the program ROM 54 of the memory cartridge 16. The, addresses &#34;8000H-9FFFH&#34; are assigned for the display RAM 42, addresses &#34;A000H-BFFFH&#34; are assigned for the external RAM 58, and addresses &#34;C000H-DFFFH&#34; are assigned for the internal RAM 30. In this embodiment shown, since the external RAM 58 is 2048 bits (=512×4 bits), practically, the address space &#34;A000H-A1FFH&#34; of the CPU core 24 is used for the external RAM 58. 
     In addition, since the program ROM 54 is 2M bits (=16 k bytes×16) as described above, 16 banks in total from the bank 0 to the bank 15 are suitably selected by the bank changing circuit 56 to be used. In addition, the addresses &#34;0000H-3FFFH&#34; for the program ROM 54 are a so-called home bank which is used as a resident area. 
     With reference to FIG. 1, the bank changing circuit 56 includes the external RAM 56, as described above. Address bits A0-A8 of the address bus 26b of the CPU core 24 are connected to address inputs A0-A8 of the external RAM 58 through the connector 20. However, the address data is applied to the external RAM 58 through an AND gate only when a reset signal /RES (&#34;/&#34; is a symbol representative of an inverted or complementary signal, and so forth on) is &#34;1&#34;. As described above, the reset signal /RES is &#34;0&#34; until the voltage from the reset circuit 6, that is, the power source voltage Vcc, reaches a predetermined level and becomes &#34;1&#34; during a voltage stable period (T3 in FIG. 7). 
     The above described reset signal IRES is further applied as a clear input of a first register (Reg0) 68, a clear input of a second register (Reg1) 70 and respective first inputs of AND gates 72-82. The lower 4 bits D0-D3 of the data bus 26c of the above described CPU core 24 is given to respective data inputs D0-D3 of the first register 68, second register 70 and the external RAM 58 through the connector 20. The first register 68 is a register for storing or holding multi-bit &#34;key data&#34; from the program ROM 54 and the second register 70 is a register for storing the bank selection data for the program ROM 54. 
     Outputs Q0-Q3 of the first register 68 are applied to a 4-input AND gate 84 as respective inputs thereof. The AND gate 84 serves as a key detecting circuit for detecting the presence or absence of key data received from first register 68 and outputting key detection signals accordingly. The outputs Q0 and Q2 are inverted before being applied to the AND gate 84 AND gates 86 and 72 function as a control circuit for enabling the RAM 58 in response to various signals. An output of the AND gate 84 and the inverted outputs of the AND gates 74 and 76 are applied to a 3-input AND gate 86. An output of the AND gate 86 is applied to the other input of the AND gate 72 which outputs a RAM selection signal RAMCS. To the other input of the AND gate 74, a chip select signal /CS from the CPU core 24 is applied via the connector 20. The chip select signal /CS is output from the CPU core 24 when the CPU core 24 accesses the external RAM 58. 
     The upper 2 bits A14 and A15 of the address bus 26b of the CPU core 24 are respectively applied to respective other inputs of the above described AND gates 76 and 78 through the connector 20. Respective outputs of these AND gates 76 and 78 are inverted and applied to NAND gates 88 and 90, each having 4 inputs, as respective inputs thereof. The output of the AND gate 76 is further applied to respective inputs of AND gates 92-100. The output of the AND gate 78 is inverted to be further applied to one input of a NAND gate 102. 
     A write signal /WR from the CPU core 24 is applied to the other input of the AND gate 80 via the connector 20, and a read signal /RD from the CPU core 24 is applied to the AND gate 82 via the connector 20. An output of the AND gate 80 is inverted and applied to the NAND gates 88 and 90 as respective inputs thereof, and to the external RAM 58 as a write signal /WR. Furthermore, an output of the AND gate 82 is inverted and applied to the other input of the above described NAND gate 102, an output of which becomes a selection signal ROM/CS for selecting the program ROM 54. An output of NAND gate 88 is applied to the first register 68 as a clock or latch input thereof, and an output of the NAND gate 90 is applied to the second register 70 as a clock input thereof. 
     Inverted outputs /Q0-/Q3 of the second register 70 are applied to respective inputs of a 4-input AND gate 104. An output of the AND gate 104 is applied to the other input of AND gate 94. The output Q0 from the second register 70 is applied to the other input of the AND gate 92. Outputs of these AND gates 92 and 94 are input to an OR gate 106 which produces an address bit ROMA14 for the program ROM 54. The outputs Q1, Q2 and Q3 of the second register 70 are applied to other inputs of the AND gates 96, 98 and 100. Respective outputs of the AND gates 94, 98 and 100 provide address bits ROMA15, ROMA16 and ROMA17 for the program ROM 54. Therefore, these AND gates 96-100 generate addresses greater than address &#34;4000H&#34; of the resident area of the program ROM 54, that is, designation data of the bank 0-bank 15. 
     As shown in FIG. 5, the program ROM 54 includes a program step PS1 for storing a program for opening the &#34;lock&#34; (RAM access is permitted) to the external RAM 58, and a program step PS2 for storing a program for closing the lock (preventing RAM access). The program step PS1 includes instructions, for example, LDA0101 (load data &#34;0101&#34;  to an accumulator) and LDReg0A (load data of the accumulator to Reg0, i.e. the first register 68). The program step PS2 includes programs, for example, LDA0000 (load data &#34;0000&#34; to the accumulator) and LDReg0A (load data of the accumulator to Reg0, i.e. the first register 68). 
     Therefore, when the program step PS1 of the program ROM 54 is executed, first key data &#34;0101&#34; is loaded to the data inputs D0-D3. Therefore, when the first register 68 receives a clock or latch signal from the NAND gate 88, the data &#34;0101&#34; is loaded into the first register 68 and the output of the AND gate 84 becomes &#34;1&#34;. Since the CPU core 24 outputs the chip select signal /CS for the external RAM 58 at this time, when the address bit A14 becomes &#34;0&#34;, that is, when the change from the internal RAM 28 to the external RAM 58 is effected, a &#34;1&#34; is output from AND gate 86 and applied to the AND gate 72. The reset signal /RES is applied to the other input of the AND gate 72. The reset signal is &#34;0&#34; when the power source voltage Vcc is unstable and &#34;1&#34; when the power source voltage Vcc is stable. The AND gate 72 applies a chip select signal RAMCS to the external RAM when the power source voltage becomes stable. Thus, the first key data for &#34;opening&#34; the lock, i.e. generating the RAM chip select signal RAMCS, is loaded into the first register 68 from the program ROM 54, and the external RAM 58 is selected only when the power source voltage becomes stable. Of course, any predetermined data other than &#34;0101&#34; can be utilized as first key data. 
     When the program step PS2 of the program stored in ROM 54 is executed, data &#34;0000&#34;, which may be considered &#34;second key data&#34;, is stored in the first register 68. Therefore, the output of the AND gate 84 is &#34;0&#34; and, in response thereto, the output of the AND gate 86 also becomes &#34;0&#34;, and the output of the AND gate 72, i.e. the external RAM selection signal RAMCS is held as &#34;0&#34;. Accordingly, after the program step PS2 of the program ROM 54 is executed, it becomes impossible to access the external RAM 58. Thus, the program step PS2 &#34;closes the lock&#34; of the external RAM 58. In addition, predetermined data other than &#34;0000&#34; may be utilized as the second key data for closing the lock. 
     With reference to FIG. 6, when the power source switch 64 (FIG. 2 and FIG. 3) is turned-on, the CPU core 24 causes a power-on reset state in step S1 until an output voltage from the reset circuit 66 reaches a predetermined level. Then, in step S2, the program stored in program ROM 54 is executed to perform suitable data processing based upon the program. 
     In step S3, the program step PS1 described previously is executed to open the lock of the external RAM 58. In step S4, the CPU core 24 writes data to the external RAM 58 and, when the completion of writing is detected in step S5, the CPU core 24 executes the program step PS2 described previously, whereby the lock of the external RAM 58 is closed in step 6. Thereafter, in step S7, another program is executed, and the process is terminated by turning the power source switch 64 off. Thus, the CPU core 24 opens and closes the lock of the external RAM 58 by executing the program step PS1, i.e. step S3, and program step SP2, i.e. step S6, of the program ROM 54, and during only that period, it is possible to access to the external RAM 58 to write or read data. 
     The present invention is applicable not only to a gaming apparatus as set forth in the above described embodiment but also to other data processing apparatus using external memories having an external RAM which is backed-up by a battery. 
     Although the present invention as been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.