Input circuit of semiconductor integrated circuit device
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an input circuit of a semiconductor integrated circuit device, and more particularly, to a technique for improving the reliability of an input circuit which receives an input voltage which is higher than a power source voltage which is applied to the input circuit. 
     2. Description of the Prior Art 
     Due to recent development in the semiconductor technology, a MOS semiconductor integrated circuit device has increasingly high-component-density. As a result, in a MOS semiconductor integrated circuit device of fine structure, the thickness of agate insulation film is extremely thin, 10 nm to 14 nm. Hence, in order to prevent dielectric breakdown of the gate insulation film and to prevent a variation in a threshold voltage of a MOS transistor due to fixed charges in the gate insulation film which are created by hot electrons which are created during the operative state of the MOS transistor and implanted into the gate insulation film, a power source voltage to be applied to the fine MOS semiconductor integrated circuit device is set lower than a power source voltage which is applied to a conventional MOS semiconductor integrated circuit device. In general, an output voltage of a MOS semiconductor integrated circuit device is equal to a potential difference between a power source potential V DD1  and a ground potential V SS . Although in most cases the voltage of an input signal which is given to an input circuit is equal to a power source voltage for operating the input circuit, in data transmission between semiconductor integrated circuit devices 50 and 51 which operate at different power source voltages (e.g., 3.3 V and 5 V) as shown in FIG. 5, a binary signal which is outputted from the semiconductor integrated circuit device 51 to the semiconductor integrated circuit device 50, for example, is around 0 V (L level) and 5 V (H level) in general. Hence, in applying an output signal of the semiconductor integrated circuit device 51 which operates at a voltage which is higher than a power source voltage for the MOS semiconductor integrated circuit device 50 having fine features, for instance, to the MOS semiconductor integrated circuit device 50 of fine geometry, a voltage V GP  which can be applied to a gate electrode of a P channel MOS transistor must be in the range V SS  ≦V GP  ≦2×V DD1  while a voltage V GN  which can be applied to agate electrode of an N channel MOS transistor must be in the range V SS  ≦V GN  ≦V DD1 . 
     This is an important consideration fir an input circuit of a semiconductor integrated circuit device. In other words, to obtain an input circuit which is sufficiently reliable, in the case where as an input circuit, an invertor is used which is formed by a P channel MOS transistor having a backgate potential which is fixed to the power source potential V DD1  and an N channel MOS transistor having a backgate potential which is fixed to the ground potential V SS , for example, the voltage V GP  which can be applied to the gate electrode of the P channel MOS transistor and the voltage V GN  which can be applied to the gate electrode of the N channel MOS transistor must be in the respective ranges above. 
     FIG. 6 is a circuitry diagram of a conventional input circuit of a semiconductor integrated circuit device. In FIG. 6, Tr5 is a P channel MOS transistor and Tr6 is an N channel MOS transistor. Indicated at reference numeral 1 is a power source which serves as a first potential point to which the power source potential V DD1  is applied, indicated at reference numeral 2 is a ground which serves as a second potential point to which the ground potential V SS  is applied, indicated at reference numeral 3 is an input terminal of the input circuit, and indicated at reference numeral 4 is an output terminal of the input circuit. 
     Next, operations of the conventional input circuit will be described. A substrate of the P channel MOS transistor Tr5 is connected to the power source 1 so that the backgate potential of the P channel MOS transistor Tr5 is fixed at the power source potential V DD1 . A substrate of the N channel MOS transistor Tr6 is grounded so that the backgate potential of the N channel MOS transistor Tr6 is fixed at the ground potential V SS . The P channel MOS transistor Tr5 and the N channel MOS transistor Tr6 form a CMOS invertor circuit, and therefore, if the voltage V IN  of a signal which is applied to the input signal terminal 3 satisfies V T  ≦V IN  where a logical threshold voltage of the CMOS invertor circuit is V T , the power source potential V DD1  which is available from the power source 1 is outputted at the output terminal 4 of the input circuit. On the other hand, if V IN  ≦V T , the ground potential V SS  which is supplied from the ground 2 is outputted at the output terminal 4 of the input circuit. 
     Now, description will be given with reference to FIG. 7 on voltages which will be applied to the gate insulation films of the P channel MOS transistor Tr5 and the N channel MOS transistor Tr6 when the output V IN  of the semiconductor into, grated circuit device 51 is received by the input circuit shown in FIG. 6 which is mounted in the semiconductor integrated circuit device 50. 
     In the P channel MOS transistor Tr5, since the backgate potential is V DD1  when the input signal V DD1  is at L level, the voltage V G  which is applied to the gate insulation film of the P channel MOS transistor Tr5 is -V DD1  with respect to a potential at the source electrode. As the input voltage V IN  changes from L level to H level, the gate voltage at the P channel MOS transistor Tr5 increases accordingly. When the input voltage V IN  has risen to H level, a voltage applied to the gate insulation film of the P channel MOS transistor Tr5 amounts to 1.7 V. 
     In the N channel MOS transistor Tr6, when the input signal V IN  is at L level, the backgate potential of the N channel MOS transistor Tr6 is V SS . Hence, a voltage which is applied to the gate insulation film of the N channel MOS transistor Tr6 is 0 V with respect to a potential at the source electrode. As the input voltage V IN  changes from L level to H level, the gate voltage at the N channel MOS transistor Tr6 increases accordingly. When the input voltage V IN  has risen to H level, a voltage which is applied to the gate insulation film of the N channel MOS transistor Tr6 amounts to the power source voltage V DD2  for the semiconductor integrated circuit device 51 shown in FIG. 5 (i.e., 5 V). Thus, a voltage exceeding V DD1  is applied to the gate electrode of the N channel MOS transistor Tr6, degrading the reliability of the input circuit. 
     A relation between a gate electrode and a semiconductor substrate will be explained with reference to FIG. 8 which shows a cross section of an invertor which is formed on a semiconductor substrate. In FIG. 8, indicated at reference numeral 60 is the semiconductor substrate, indicated at reference numeral 61 is a p-well which is formed on the semiconductor substrate 60, indicated at reference numeral 62 is an n-well which is formed on the semiconductor substrate 60, indicated at reference numeral 63 is a p +  buried region which is formed on the p-well 61, indicated at reference numeral 64 is a source electrode of an N channel MOS transistor which is formed on the p-well 61, indicated at reference numeral 65 is a drain electrode of the N channel MOS transistor which is formed on the p-well 61, indicated at reference numeral 69 is a gate electrode of the N channel MOS transistor, indicated at reference numeral 69a is a gate insulation film of the gate electrode 69, indicated at reference numeral 66 is a drain electrode of a P channel MOS transistor which is formed on the n-well 62, indicated at reference numeral 67 is a source electrode of the P channel MOS transistor which is formed on the n-well 62, indicated at reference numeral 68 is an n +  buried region which is formed on the n-well 62, indicated at reference numeral 70 is a gate electrode of the P channel MOS transistor, and indicated at reference numeral 70a is a gate insulation film of the gate electrode 70. The source electrode 64 of the N channel MOS transistor and the p +  buried region 63 are grounded to stay at the ground potential V SS  so that the backgate potential of the N channel MOS transistor is fixed at V SS . On the other hand, the source electrode 67 of the P channel MOS transistor and the buried region 68 are connected to the power source 1 to remain at the power source potential V DD1  so that the backgate potential of the P channel MOS transistor is fixed at V DD1 . The gate electrodes of the N channel MOS transistor and the P channel MOS transistor are connected to the input terminal 3 while the drain electrode 65 of the N channel MOS transistor and the drain electrode 66 of the P channel MOS transistor are connected to the output terminal 4. Hence, a voltage which is applied to the gate insulation films 69a and 70a is equal to a difference between the associated backgate potential and a potential at the input terminal 3. 
     Since the conventional input circuit of a semiconductor integrated circuit device has such a structure, when the voltage of the input signal V IN  is larger than the power source voltage V DD1  tier the semiconductor integrated circuit device 50 as shown in FIG. 5, an excessively large voltage is applied to the gate insulation film of the N channel MOS transistor Tr6. This causes various reliability related problems such as destruction of the insulation film and shortened operating life of the MOSFET. 
     SUMMARY OF THE INVENTION 
     In a first aspect of the present invention, an input circuit of a semiconductor integrated circuit device for receiving at an input terminal an input signal and outputting at an output terminal an output signal which is in response to the input signal comprises: input voltage shift means including a field-effect transistor in which a potential at a control electrode of the field-effect transistor is fixed, the input voltage shift means receiving the input signal at the input terminal and shifting the voltage of the input signal in the field-effect transistor and outputting the same; and buffer means including an insulated gate field-effect transistor, the buffer means receiving an output of the input voltage shift means at a gate electrode of the insulated gate field-effect transistor, the buffer means outputting a signal which is in response to the input signal at the output terminal. 
     The input voltage shift means according to the first aspect of the present invention is capable of shifting the voltage of the input signal by use of the field-effect transistor in which a potential at a control electrode is fixed and outputting the shifted voltage. The input voltage shift means is also capable of providing the gate electrode of the insulated gate field-effect transistor of the buffer means with an input signal which has an appropriate potential range. 
     Hence, according to the first aspect of the present invention, since the input voltage shift means of the input circuit includes a field-effect transistor in which a potential at a control electrode is fixed and is capable of receiving the input signal at the input terminal, shifting the voltage of the input signal in the field-effect transistor and outputting the same, the voltage which is applied to the gate insulation film of the insulated gate field-effect transistor can be changed, making it possible to prevent destruction of the gate insulation film, shortened life of the insulated gate field-effect transistor and etc. Hence, the operating reliability of the input circuit of the semiconductor integrated circuit device is enhanced. 
     According to a second aspect of the present invention, in the input circuit of the first aspect, the input voltage shift means further includes resistor means having one end connected to a first power source potential which is in the potential range of the input signal, and the field-effect transistor of the input voltage shift means includes a field-effect transistor which has one current electrode connected to another end of the resistor means, other current electrode connected to the input terminal and a control electrode connected to a predetermined source potential which is in the potential range of the input signal. 
     Preferably, the field-effect transistor includes an insulated gate field-effect transistor. 
     The resistor means may include other field-effect transistor which has one current electrode connected to the first power source potential and other current electrode and a control electrode connected to the one current electrode of the field-effect transistor. 
     Further, the other field-effect transistor may include a P channel MOS transistor which has a source electrode connected to the first power source potential and a drain and agate electrodes connected to the one current electrode of the field-effect transistor. 
     The resistor means may include a resistor which has one end connected to the first power source potential and other end connected to the one current electrode of the field-effect transistor. 
     As hereinabove described, since the field-effect transistor of the second aspect of the present invention has its control electrode fixed at the second power source potential, it is possible to shift the input signal using the threshold voltage of the field-effect transistor and to output the shifted voltage at the other current electrode of the field-effect transistor. 
     According to the second aspect of the present invention, as the field-effect transistor of the input voltage shift means, such a field-effect transistor is used which has one current electrode connected to the first power source potential, another current electrode connected to the one current electrode of the field-effect transistor, and a control electrode connected to the second power source potential which is in the potential range of the input signal. The input signal is shifted using the threshold voltage of the field-effect transistor. The second aspect of the present invention is effective in preventing destruction of the gate insulation film, shortened life of the insulated gate field-effect transistor and etc., thereby enhancing the operating reliability of the input circuit of the semiconductor integrated circuit device. 
     According to a third aspect of the present invention, in the input circuit of the second aspect, the insulated gate field-effect transistor of the buffer means includes a first insulated gate field-effect transistor of a first conductivity type, the first insulated gate field-effect transistor having one current electrode connected to a second power source potential which is different from the first potential, another current electrode connected to the output terminal and a control electrode for receiving the output of the input voltage shift means. The buffer means further includes a second insulated gate field-effect transistor of a second conductivity type, the second insulated gate field-effect transistor having one current electrode connected to the first power source potential, another current electrode connected to the output terminal and a control electrode connected to the input terminal. 
     In the third aspect of the present invention, the first and the power source potentials may be used as a backgate potential respectively in the first and the second insulated gate field-effect transistors. 
     Preferably, the first power source potential includes a power source potential which is higher than the second power source potential, the first insulated gate field-effect transistor includes an N channel MOS transistor, and the second insulated gate field-effect transistor includes a P channel MOS transistor. 
     Alternatively, the first power source potential may include a power source potential which is lower than the second power source potential, the first insulated gate field-effect transistor may include a P channel MOS transistor, the second insulated gate field-effect transistor may include an N channel MOS transistor. 
     The buffer means according to the third aspect of the present invention receives, at the control electrode of the first insulated gate field-effect transistor of the first conductivity type, the voltage of the binary signal which is received as the input signal and shifted by the input voltage shift means. Since the received binary signal is directly received and processed at the control electrode of the second insulated gate field-effect transistor of the second conductivity type, the binary signal is outputted as a signal which has two potentials, i.e., the first power source potential and the second power source potential. 
     Thus, according to the third aspect of the present invention, the insulated gate field-effect transistor of the buffer means includes the first insulated gate field-effect transistor of the first conductivity type, which has one current electrode connected to the second power source potential, another current electrode connected to the output terminal and a control electrode for receiving the output of the input voltage shift means, and the second insulated gate field-effect transistor of the second conductivity type, which has one current electrode connected to the first power source potential, another current electrode connected to the output terminal and a control electrode connected to the input terminal. Hence, the binary signal which is received as the input signal is processed at the first and the second insulated gate field-effect transistors and outputted. Thus, by changing the voltage which is applied to the gate insulation films of the insulated gate field-effect transistors, destruction of the gate insulation film, shortened life of the insulated gate field-effect transistor and etc. are prevented and the operating reliability of the input circuit of the semiconductor integrated circuit device is improved. 
     According to a fourth aspect of the present invention, in the input circuit of the first aspect, the field-effect transistor of the input voltage shift means includes a first field-effect transistor of a first conductivity type which is formed on a semiconductor substrate, the first field-effect transistor having the other current electrode connected to the input terminal and a control electrode connected to the first power source potential, the second power source potential being used as a backgate potential of the first field-effect transistor. The input voltage shift means further includes a second field-effect transistor of a second conductivity type which is formed on the semiconductor substrate, the second field-effect transistor having one current electrode connected to the first power source potential and the other current electrode and a control electrode connected to the one current electrode of the first field-effect transistor, the first power source potential being used as a backgate potential of the second field-effect transistor. The insulated gate field-effect transistor of the buffer means includes a first insulated gate field-effect transistor of the first conductivity type which is formed on the semiconductor substrate, the first insulated gate field-effect transistor having one current electrode connected to the second power source potential, another current electrode connected to the output terminal and a control electrode receiving the output of the input voltage shift means. The buffer means further includes a second insulated gate field-effect transistor of the second conductivity type which is formed on the semiconductor substrate, the second insulated gate field-effect transistor having one current electrode connected to the first power source potential, the other current electrode connected to the output terminal and a control electrode connected to the input terminal. A channel region of the second field-effect transistor and a channel region of the second insulated gate field-effect transistor are not formed in the same semiconductor layer. 
     Alternatively, in the input circuit of the first aspect, the field-effect transistor of the input voltage shift means includes a first field-effect transistor of a first conductivity type which is formed on a semiconductor substrate, the first field-effect transistor having the other current electrode connected to the input terminal and a control electrode connected to the first power source potential, the second power source potential being used as a backgate potential of the first field-effect transistor. The input voltage shift means further includes a second field-effect transistor of a second conductivity type which is firmed on the semiconductor substrate, the second field-effect transistor having one current electrode connected to the first power source potential and the other current electrode and a control electrode connected to the one current electrode of the first field-effect transistor, the first power source potential being used as a backgate potential of the second field-effect transistor. The insulated gate field-effect transistor of the buffer means includes a first insulated gate field-effect transistor of the first conductivity type which is formed on the semiconductor substrate, the first insulated gate field-effect transistor having one current electrode connected to the second power source potential the, other current electrode connected to the output terminal and a control electrode receiving the output of the input voltage shift means. The buffer means further includes a second insulated gate field-effect transistor of the second conductivity type which is formed on the semiconductor substrate, the second insulated gate field-effect transistor having one current electrode connected to the first power source potential, the other current electrode connected to the output terminal and a control electrode connected to the input terminal. On the semiconductor substrate, wherein a region is firmed which surrounds the second field-effect transistor or the first insulated gate field-effect transistor, the region having a conductivity which is different from that of a semiconductor layer in which the second field-effect transistor and the first insulated gate field-effect transistor are formed. 
     In the fourth aspect of the present invention, the channel region of the second field-effect transistor and the channel region of the second insulated gate field-effect transistor are not formed in the same semiconductor layer. Hence, even if the potential at the input terminal becomes larger than a sum of the first power source potential and the threshold voltage of the second field-effect transistor and consequently a current is initiated from the one current electrode of the second field-effect transistor, the second insulated gate field-effect transistor will not be affected by the initiated current. Thus, latch-up would not be caused easily. 
     As described above, in the input circuit according the fourth aspect of the present invention, the input voltage shift means further includes the second field-effect transistor of the first conductivity type which is formed on the semiconductor substrate and the second field-effect transistor has one current electrode connected to the first power source potential and the other current electrode and a control electrode connected to the one current electrode of the first field-effect transistor. The power source potential is used as a backgate potential of the second field-effect transistor. The buffer means further includes a second insulated gate field-effect transistor of the first conductivity type which is formed on the semiconductor substrate and the second insulated gate field-effect transistor has one current electrode connected to the first power source potential, the other current electrode connected to the output terminal and a control electrode connected to the input terminal. In addition, the channel region of the second field-effect transistor and the channel region of the second insulated gate field-effect transistor are not formed in the same semiconductor layer. Hence, without causing latch-up, the binary signal which is received as the input signal is processed at the first and the second insulated gate field-effect transistors and outputted. Thus, by changing the voltage which is applied to the gate insulation films of the insulated gate field-effect transistors, destruction of the gate insulation film, shortened life of the insulated gate field-effect transistor and etc. are prevented and the operating reliability of the input circuit of the semiconductor integrated circuit device is improved. 
     These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuitry diagram showing the structure of an input circuit of a semiconductor integrated circuit device according to a preferred embodiment of the present invention; 
     FIG. 2 is a view showing a relation an input voltage and a voltage which is applied to agate insulation film to thereby explain operations of the input circuit of FIG. 1; 
     FIGS. 3 and 4 are cross sectional views showing the structure of the input circuit of FIG. 2 firmed on a semiconductor substrate; 
     FIG. 5 is a block diagram showing a relation between semiconductor integrated circuit devices; 
     FIG. 6 is a circuitry diagram showing the structure of a conventional input circuit of a semiconductor integrated circuit device; 
     FIG. 7 is a view showing a relation between an input voltage and a voltage which is applied to agate insulation film to thereby explain operations of the input circuit of FIG. 6; 
     FIG. 8 is a cross sectional view shoving the structure of the input circuit of FIG. 2 formed on a semiconductor substrate; and 
     FIG. 9 is a circuitry diagram showing the structure of the input circuit of the semiconductor integrated circuit device according to a modification of the preferred embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuitry diagram showing the structure of an input circuit of a semiconductor integrated circuit device according to a preferred embodiment of the present invention. In FIG. 1, a power source is indicated at 1, a ground is indicated at 2, an input terminal of the input circuit is indicated at 3, an output terminal of the input circuit is indicated at 4, P channel MOS transistors are indicated at Tr1 and Tr3, and N channel MOS transistors are indicated at Tr2 and Tr4. 
     Substrates of the P channel MOS transistors Tr1 and Tr3 are connected to a power source potential V DD1  while substrates of the N channel MOS transistors Tr2 and Tr4 are connected to the ground potential V SS . A resistor 90 may be used instead if transistor Tr3, as shown in FIG. 9. A gate electrode of the N channel MOS transistor Tr4 is connected to the power source potential V DD1 , a source electrode of the N channel MOS transistor Tr4 is connected to the input terminal 3 of the input circuit, and a drain electrode of the N channel MOS transistor Tr4 is connected to a gate electrode and a drain electrode of the P channel MOS transistor Tr3. A source electrode of the P channel MOS transistor Tr3 is connected to the power source potential V DD1  while the gate electrode and the drain electrode of the P channel MOS transistor Tr3 are connected to a gate electrode of the N channel MOS transistor Tr2. A gate electrode of the P channel MOS transistor Tr1 is connected to the input terminal 3 of the input circuit, a source electrode of the P channel MOS transistor Tr1 is connected to the power source potential V DD1 , and a drain electrode of the P channel MOS transistor Tr1 is connected to the output terminal 4. The gate electrode of the N channel MOS transistor Tr2 is connected to the gate electrode and the drain electrode of the P channel MOS transistor Tr3, a source electrode of the N channel MOS transistor Tr2 is connected to the ground potential V SS , while a drain electrode of the N channel MOS transistor Tr2 is connected to the output terminal 4. 
     Next, operations of the input circuit will be described. Assume that the voltage between the power source potential V DD1  and the ground potential V SS  is V DD1 . A case where an input signal shown as V IN  is applied to the input terminal 3 of the input circuit will be explained with reference to FIG. 2. 
     Description will be given on what voltage V G  is applied to the gate insulation films of the P channel MOS transistor Tr1 and the N channel MOS transistor Tr2 in a region 1 of FIG. 2, i.e., when the input voltage V IN  satisfies Eq. 1 below: 
     
         V.sub.DD1 -V.sub.TN (V.sub.BS =-V.sub.IN)≧V.sub.IN  (1) 
    
     where V TN  (V BS  =-V IN ) is a threshold voltage of when a potential at the substrate of the N channel MOS transistor Tr4 is V BS  =-V IN . 
     Under such a state, the N channel MOS transistor Tr4 is conductive. Hence, the gate voltage at the N channel MOS transistor Tr2 is 0 V or extremely close to 0 V, keeping the N channel MOS transistor Tr2 cut off. Since the gate electrode of the P channel MOS transistor Tr1 is connected to the input terminal 3 of the input circuit, a voltage applied between the gate and the source electrodes of the P channel MOS transistor Tr1 is V IN  -V DD1 . This allows the P channel MOS transistor Tr1 to stay strongly conductive, and therefore, a voltage which appears at the output terminal 4 of the input circuit is equal to V DD1  or very close to V DD1 . 
     Next, what voltage V G  is applied to the gate insulation films in a region 2 of FIG. 2, i.e., when the input voltage V IN  satisfies Eq. 2 below: 
     
         V.sub.DD1 ≧V.sub.IN &gt;V.sub.DD1 -V.sub.TN (V.sub.BS =-V.sub.IN)(2) 
    
     where V TN  (V BS  =-V IN ) is a threshold voltage of when a potential at the substrate of the N channel MOS transistor Tr4 is V BS  =-V IN . 
     When such a state is evoked, since the N channel MOS transistor Tr4 is cut off, the gate voltage at the N channel MOS transistor Tr2 is V DD1  +V TP  (V BS  =0) (V TP  (V BS  =0) is a threshold voltage of where a potential at the substrate of the P channel MOS transistor Tr3 V BS  is V BS  =0). Hence, the N channel MOS transistor Tr2 is in a strong conductive state. Since the gate electrode of the P channel MOS transistor Tr1 is connected to the input terminal 3 of the input circuit, a voltage which is applied between the gate and the source electrodes of the P channel MOS transistor Tr1 is V IN  -V DD1 . This causes the P channel MOS transistor Tr1 to be cut off or weakly conductive. Hence, a voltage which is available at the output terminal 4 of the input circuit is equal to 0 V or very close to 0 V. 
     Next, what voltage V G  is applied to the gate insulation films in a region 3 of FIG. 2, i.e., when the input voltage V IN  satisfies Eq. 3 below: 
     
         V.sub.DD1 &lt;V.sub.IN ≦V.sub.DD1 +V.sub.TN (V.sub.BS =-V.sub.IN)(3) 
    
     When Eq. 3 is satisfied, the N channel MOS transistor Tr4 is cut off, and therefore, the gate voltage at the N channel MOS transistor Tr4 is V DD1  +V TP . It is to be noted that between the drain and the source electrodes of the N channel MOS transistor Tr4, a voltage opposite to that in the precedent cases is applied. 
     Next, what voltage V G  is applied to the gate insulation films in a region 4 of FIG. 2, i.e., when the input voltage V IN  satisfies Eq. 4 below: 
     
         V.sub.IN &gt;V.sub.DD1 +V.sub.TN (V.sub.BS =-V.sub.IN)        (4) 
    
     Since the N channel MOS transistor Tr4 is conductive when such a relation is satisfied, the gate voltage the N channel MOS transistor Tr2 is equal to a difference between the input voltage V IN  and the threshold voltage V TN  of the N channel MOS transistor Tr4. This allows the N channel MOS transistor Tr2 conductive so that the gate voltage at the P channel MOS transistor Tr1 is equal to a difference between the input voltage V IN  and the threshold voltage V TN  of the N channel MOS transistor Tr4. 
     Since the substrates of the P channel MOS transistors Tr1 and Tr3 are connected to the power source potential V DD1  (i.e., voltage V DD1 ), a voltage which can be applied to the gate electrodes of the P channel MOS transistors Tr1 and Tr3 is in the range V SS  ≦V GP  ≦2×V DD1 . The substrates of the N channel MOS transistors Tr2 and Tr4 are connected to the ground potential V SS  (i.e., voltage V SS ), and therefore, a voltage which can be applied to the gate electrodes of the N channel MOS transistors Tr2 and Tr4 is in the range V SS  ≦V GN  ≦V DD1 . Hence, since V IN  is directly applied to the gate electrode of the gate electrode of the P channel MOS transistor Tr1, the reliability of the gate insulation film of the P channel MOS transistor Tr1 will not be deteriorated as far as V SS  ≦V IN  ≦2×V DD1  holds. As to the gate insulation film of the N channel MOS transistor Tr4, since it is when the N channel MOS transistor Tr4 turns conductive that a voltage V DD1  -V IN  is applied between the gate insulation films and since the input signal under such a circumstance satisfies V IN  ≦V DD1  -V TN  (V BS  =-V IN ) thereby causing as small voltage as V DD1  at most to be applied between the gate insulation films, it can be understood that the reliability of the gate insulation film of the gate insulation film of the N channel MOS transistor Tr4 will not be deteriorated. 
     Although the foregoing has described that the power source voltage V DD1  is larger than the ground potential V SS  in the preferred embodiment, the present invention is applicable to where the power source voltage V DD1  is smaller than the ground potential V SS . If the power source voltage VDn t  is to be smaller than the ground potential V SS  an input circuit has to be structured so that the P channel MOS transistors replace N channel MOS transistors and the N channel MOS transistors replace P channel MOS transistors in FIG. 1. 
     Now, the structure of an input circuit which is formed on a semiconductor substrate will be explained with reference to FIGS. 3 and 4. FIG. 3 is a cross sectional view showing an invertor which is formed on a semiconductor substrate. In FIG. 3, indicated at reference numeral 10 is the semiconductor substrate, indicated at reference numerals 11 and 13 are n-wells which are formed on the semiconductor substrate 10, indicated at reference numeral 12 is a p-well which is formed on the semiconductor substrate 10 between the n-wells 11 and 13, indicated at reference numeral 14 is an n +  buried region which is formed on the n-well 11, indicated at reference numeral 15 15 is a source electrode of a P channel MOS transistor (p +  region) which is formed on the n-well 11, indicated at reference numeral 16 is a drain electrode of the P channel MOS transistor (p +  region) which is formed on the n-well 11, indicated at reference numerals 17 and 21 are drain electrodes of N channel MOS transistors (n +  region) which are formed on the p-well 12, indicated at reference numerals 18 and 20 are source electrodes of the N channel MOS transistors (n +region ) which are formed on the p-well 12, indicated at reference numeral 19 is a p +  buried region which is formed on the p-well 12, indicated at reference numerals 22 and 25 are n +  buried regions which are formed on the n-well 13, indicated at reference numeral 23 is a source electrode of a P channel MOS transistor which is formed on the n-well 13, indicated at reference numeral 24 is a drain electrode of the P channel MOS transistor which is formed on the n-well 13, indicated at reference numerals 27 and 28 are gate electrodes of the N channel MOS transistors, indicated at reference numerals 27a and 28a are gate insulation films of the gate electrodes 27 and 28, indicated at reference numerals 26 and 29 are gate electrodes of the P channel MOS transistors, and indicated at reference numerals 26a and 29a are gate insulation films of the gate electrodes 26 and 29. 
     The P channel MOS transistor which is formed on the n-well 11 corresponds to the P channel MOS transistor Tr1 of FIG. 1, the P channel MOS transistor which is formed on the n-well 13 corresponds to the P channel MOS transistor Tr3 of FIG. I, the N channel MOS transistor which has the gate electrode 27 corresponds to the N channel MOS transistor Tr2 of FIG. 1, while the N channel MOS transistor which has the gate electrode 28 corresponds to the N channel MOS transistor Tr4 of FIG. 1. The source electrode 18 and the p +  buried region 19 are grounded so as to have the ground potential V SS  while the backgate potentials of the N channel MOS transistors are fixed at V SS . The source electrodes 15 and 23 of the P channel MOS transistors and the buried regions 14 and 25 which are formed on the n-wells 11 and 13 are connected to the power source potential V DD1  so that the backgate potentials of the P channel MOS transistors are fixed at V DD1 . 
     In addition, the gate electrode 27 of the N channel MOS transistor, the gate electrode 29 of the P channel MOS transistor, and the drain electrode 23 of the N channel MOS transistor and the drain electrode 21 of the P channel MOS transistor are connected to each other. The drain electrodes 16 and 17 of the P channel MOS transistors on the n-well 11 are connected to the output terminal 4. The transistors having the gate electrodes 26 and 27 form an invertor. The gate electrode 28 is fixed at the power source potential V DD1  and the source electrode 20 is connected to the input terminal 3 and the gate electrode 26. 
     If the input signal potential V IN  becomes higher than the power source potential V DD1  beyond a sum of the threshold voltage V TN  of the transistor which has the gate electrode 28 and the power source potential V DD1 , a current is poured from the drain electrode 23 to the n-well 13. Hence, by separating the n-wells 11 and 13 from each other, it is possible to prevent latch-up due to a change in a potential at the n-well 11. 
     The preferred embodiment above is related to where the power source potential V DD1  is higher than the ground potential V SS . However, an input circuit according to the present invention can be also applied to where the power source potential V DD1  is lower than the ground potential V SS . In such a case, an input circuit has to be structured so that the P channel MOS transistors replace N channel MOS transistors and the N channel MOS transistors replace P channel MOS transistors in FIG. 2. 
     While the invention has been described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is understood that numerous other modifications and variations can be devised without departing from the scope of the invention.