Semiconductor memory device having a prolonged data holding time
TECHNICAL FIELD OF THE INVENTION 
     The present invention pertains to semiconductor memories of a charge storage type such as dynamic random-access memories (DRAMs). 
     BACKGROUND OF THE INVENTION 
     In a DRAM, memory cells store data in terms of electric charge. The stored charge, however, fades with time due to a leakage of current. Therefore, periodic &#34;refresh&#34; operations must be carried out to maintain the stored data. 
     If data of a high logic level is written in a DRAM cell using a low voltage, this means that the amount of the stored electric charge in a capacitor is small. Therefore, the data-holding time is limited. If the data-holding time gets too short, refreshing cannot prevent the stored data from vanishing. 
     5 V DRAMs of a single power source type are known from Japanese Patent Applications, published under No. 58-23386and No. 58-23387. In these prior art techniques, 6 V or 7 V, which is greater than an external power supply voltage V CC  (=5 V), is used to write data into a memory cell. This prevents loss of data even if some drop in V CC  occurs, thereby improving operational margins. 
     Another type of DRAM is disclosed by M. Aoki et al (&#34;A 1.5 V DRAM for Battery-Based Applications&#34;, ISSCC DIGEST OF TECHNICAL PAPERS, pp.238-239, February, 1989) as well as by Japanese Patent Application, published under No. 5-21742. These prior art techniques use a cell plate voltage variation method. More specifically, the voltage of cell plates is made to vary so as to effectively boost a write voltage used to write data in a memory cell. 
     The above-described techniques, however, present drawbacks. In the former techniques, a high write voltage, such as 6 V or 7 V, is used. This causes the memory cell to suffer from a problem of how to resist such a high voltage, resulting in reducing DRAM life. In the latter techniques, the cell plate approach is adopted which, however, is not practical. The reason is that the capacitance of cell plates is so great that their voltage cannot be changed at high speeds. 
     SUMMARY OF THE INVENTION 
     It is a main object of the present invention to provide an improved semiconductor memory capable of prolonging the data-holding time with no sacrifice in memory cell voltage resistance. 
     The present invention achieves the object in the following way. An internal power supply voltage that varies with an external power supply voltage is compared with a predetermined voltage for the choice of which voltage to use as a voltage for data of a high logic level being written in a memory cell. This comparison operation is explained more specifically. If the internal power supply voltage is greater than the predetermined voltage, then the former is selected as a HIGH data write voltage (hereinafter called the &#34;HIGH data write voltage&#34;). If the internal power supply voltage is lower than the predetermined voltage, then a voltage (&gt;the internal power supply voltage) is selected. 
     The present invention discloses an improved semiconductor memory comprising a power supply circuit, a memory cell circuit, a sense amplifier, and a row decoder. A first internal power supply voltage V PERI  that varies with an external power supply voltage V CC  is applied to the power supply circuit. The power supply circuit outputs two different voltages; a second internal power supply voltage V W  that is set at the same value as V PERI  if V PERI  &gt;the predetermined voltage or above V PERI  if V PERI  &lt;the predetermined; and a third internal power supply voltage V WORD  that is set above V W . V PERI  may take the same voltage value as V CC  or be a voltage V RD  as a result of decreasing V CC . The memory cell circuit comprises a capacitor for holding electric charges and a MOS transistor whose source, drain, and gate are respectively connected with a bit line, with the aforesaid capacitor, and with a word line. The sense amplifier has a MOS transistor whose source and drain are respectively connected with a sense enable signal line and with the bit line and whose gate is fed a signal for making the MOS transistor of the aforesaid sense amplifier conduct. The row decoder places V W  and V WORD , output from the power supply circuit, onto the sense enable signal line and onto the word line, respectively. 
     For high-speed read and write operations to be realized, V W  is applied from the power supply circuit to a gate of a MOS transistor forming a column switch circuit. 
     For the case of semiconductor memories including a shared switch circuit as a part of its organization, V WORD  is applied to a gate of a MOS transistor forming the shared switch circuit from the power supply circuit, like the MOS transistor of the aforesaid memory cell. 
     The present invention has several advantages. If V CC  (or V RD ) is adequately high, then that V CC  (or V RD ) acts as a voltage for data of a high logic level being written in a memory cell. Therefore, there is no need to take into account the aforesaid problem of how to resist a high voltage being applied to a memory cell. If V CC  or V RD  is low, it is possible to prolong the data-holding time by raising the write voltage used to write data of a high logic level. 
     The sense amplifier determines the write voltage. In other words, V W , applied to a source of a MOS transistor of the sense amplifier, is applied to a capacitor of a memory cell through a bit line and a MOS transistor of the memory cell. The capacitor stores electric charge by a proportional amount to V W  applied. At this point, V WORD  is applied to a gate of the MOS transistor of the memory cell circuit through a word line, assuring complete conduction of the MOS transistor of the memory cell circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing a semiconductor memory according to a preferred embodiment of the present invention. 
     FIG. 2 is a circuit diagram showing a power supply voltage control circuit of FIG. 1. 
     FIG. 3 is a block diagram showing a power supply circuit of FIG. 1. 
     FIG. 4 shows an external power supply voltage-internal power supply voltage relationship, at the time when the power supply circuit of FIG. 3 is used in the semiconductor memory of FIG. 1. 
     FIG. 5 is a circuit diagram showing in detail a memory cell section of FIG. 1. 
     FIG. 6 is a block diagram showing a semiconductor memory of another preferred embodiment of the present invention. 
     FIG. 7 is a circuit diagram showing in detail a memory cell section of FIG. 6. 
     FIG. 8 is a circuit diagram showing a modification of the power supply voltage control circuit of FIG. 1 or FIG. 6. 
     FIG. 9 is a circuit diagram showing still another modification of the power supply voltage control circuit of FIG. 1 or FIG. 6. 
     FIG. 10 is a block diagram showing a modification of the power supply circuit of FIG. 1 or FIG. 6. 
     FIG. 11 shows an external power supply voltage-internal power supply voltage relationship, when the power supply circuit of FIG. 10 is used in the semiconductor memory of FIG. 1 or FIG. 6. 
     FIG. 12 is a block diagram showing a semiconductor memory of still another preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Preferred embodiments are described below with the help of the accompanying drawings. 
     Embodiment 1 
     FIG. 1 shows the organization of a DRAM according to a first preferred embodiment of the present invention. This DRAM comprises a memory cell section 10, a peripheral circuit 20, a power supply voltage (PSV) control circuit 30, and a power supply circuit 40. The memory cell section 10 includes a memory cell array 11, a row decoder 12, a column decoder 13, and a row of sense/switch circuits 14. The row 14 has a row of sense amplifiers 15 and a row of column switch circuits 16. 
     V CC  is directly applied to the peripheral circuit 20 as V PERI . The circuit 20 not only applies an address and a control signal to the memory cell section 10 but also controls data transfer between the memory cell section 10 and the outside of the DRAM. The selection of which memory cell to access is done by the row decoder 12 as well as by the column decoder 13 on the basis of the address received from the peripheral circuit 20. Like the peripheral circuit 20, the PSV control circuit 30 and the power supply circuit 40 are fed V CC . 
     The PSV circuit 30 contains a comparator 31 (see FIG. 2). The comparator 31 makes a comparison between V CC  and a reference voltage V REF . If V CC  &lt;V REF , then the comparator 31 sends out a signal of a high logic level as a voltage control signal V SIG . If V CC  &gt;V REF , the comparator 31 this time sends out a signal of a low logic level as V SIG . 
     As shown in FIG. 3, the power supply circuit 40 has a first voltage step-up circuit 41 and a second voltage step-up circuit 42. If V SIG  from the PSV control circuit 30 is LOW, the first voltage step-up circuit 41 outputs a voltage equal to V CC  as V W , whereas if V SIG  is HIGH, the circuit 41 outputs a voltage as a result of boosting V CC  as V W . The second voltage step-up circuit 42 outputs a voltage as a result of further boosting V W  output from the circuit 41, as V WORD . These V W  and V WORD  are applied to the memory cell section 10. 
     FIG. 4 shows a relationship between the internal power supply voltage (V CC ) and the external power supply voltage (V PERI , V W , V WORD ) for the power supply circuit 40 of FIG. 3. 
     In usual DRAMs, V CC  recommended operating conditions are set, the contents of which are a standard voltage V 0 , a high limit voltage V 0H , and a low limit voltage V 0L . For example, for 5 V DRAMs of a single power source type, V 0  =5.0 V, V 0H  =5.5 V, and V 0L  =4.5 V. On the other hand, for 3.3 V DRAMs of a single power source type, V 0  =3.3 V, V 0H  =3.6 V, and V 0L  =3.0 V. 
     FIG. 4 shows characteristics in a case where V REF  is set at V 0L  that is a low limit voltage in the voltage range specified by the V CC  recommended operating conditions (for example, 4.5 V or 3.0 V). As shown in the figure, V PERI  monotonically varies with V CC  over the full range of V CC . V W  agrees with V PERI  if V CC  is greater than V 0L . V W  has a constant voltage value (i.e., V 0L ) if V CC  is lower than V 0L . V WORD  is greater than V W  over the full range of V CC . The difference between V W  and V WORD  is set above a threshold voltage V T  of one MOS transistor. 
     FIG. 4 shows V CC  regions I and II. In the region I, the difference between V PERI  and V W  is not greater than V T  so that the memory cell section 10 can be connected directly to the peripheral circuit 20 as shown in FIG. 1. On the other hand, in the region II, the difference between V PERI  and V W  is greater than V T  so that a level shift circuit is sandwiched between the memory cell section 10 and the peripheral circuit 20 to make it (the level shift circuit) act as a voltage interface. 
     Referring now to FIG. 5, the organization of the memory cell section 10 is explained in detail. FIG. 5 shows a memory cell circuit 11a, a CMOS sense amplifier 15a, and a column switch circuit 16a. 
     The memory cell circuit 11a has a memory cell that forms one column of the memory cell array 11 of FIG. 1. FIG. 5 further shows cell plates 50, NMOS transistors 51 and 54, and capacitors 52 and 55. The NMOS transistor 51 has a source, a drain, and a gate, and they are respectively connected to one of two bit lines in a pair, to a cell plate 50 through the capacitor 52, and to a word line through which V WORD  is applied. The NMOS transistor. 54 has a source, a drain, and a gate, and they are respectively connected to the other bit line, to a cell plate 50 through the capacitor 55, and to another word line through which V WORD  is applied. The capacitors 52 and 55 form memory cells capable of storing 1-bit data in the form of the presence or absence of electric charge. If the row decoder 12 applies V WORD  to the gate of the NMOS transistor 51, this causes a memory cell formed by the capacitor 52 to be selected. On the other hand, if the row decoder 12 applies V WORD  to the gate of the NMOS transistor 54, this causes a memory cell formed by the capacitor 55 to be selected. 
     The CMOS sense amplifier 15a forms a part of the sense amplifier row 15 and is connected to the two bit lines of the memory cell circuit 11a. The CMOS sense amplifier 15a has two cross-coupled PMOS transistors 61 and 62 forming a PMOS sense amplifier and two cross-coupled NMOS transistors (not shown) forming an NMOS sense amplifier. The PMOS transistor 61 has a source, a drain, and a gate and they are respectively connected to a sense enable signal line SAP, to one of the bit lines on the NMOS transistor&#39;s 51 side, and to the other bit line on the NMOS transistor&#39;s 54 side. The PMOS transistor 62 has a source, a drain, and a gate and they are respectively connected to SAP, to the bit line on the NMOS transistor&#39;s 54 side, and to the bit line on the NMOS transistor&#39;s 51 side. The two cross-coupled PMOS transistors 61 and 62 together form a PMOS sense amplifier, and another two cross-coupled NMOS transistors (not shown) together form an NMOS sense amplifier. 
     The two bit lines of the memory cell circuit 11a are used as complementary signal lines. In other words, when a voltage of a high logic level is set to one of the two bit lines, a voltage of a low logic level is set to the other of the two bit lines. The CMOS sense amplifier 15a amplifies the voltages of the bit lines of the circuit 11a. As shown in FIG. 5, V W  is applied from the row decoder 12 to SAP of the PMOS sense amplifier formed by the PMOS transistors 61 an 62, in order to determine a high-logic-level voltage held by one of the two bit lines at V W  as soon as possible. On the other hand, in order to determine a low-logic-level voltage held by the other of the two bit lines at a V SS  (=0 V), V SS  is mutually applied to drains of the not-shown NMOS transistors. 
     The column switch circuit 16a is a part of the column switch circuit row 16 of FIG. 1, being connected to both of the two bit lines of the memory cell circuit 11a. The column switch circuit 16a has two NMOS transistors 71 and 72. The NMOS transistor 71 has a source, a drain, and a gate, and they are respectively connected to one of two data lines in a pair, and to the bit line on the NMOS transistor&#39;s 51 side, and to a column line COL. The NMOS transistor 72 has a source, a drain, and a gate, and they are respectively connected to the other data line, and to the bit line as the NMOS transistor&#39;s 54 side, and to COL. V W  is applied by the column decoder 13 to COL. 
     In a data write operation, whereas one of the two data lines of FIG. 5 receives V PERI  (=V CC ) from the peripheral circuit 20 as a voltage for data of a high logic level being written in a memory cell, the other data line receives 0V from the circuit 20 as a voltage used to write data of a low logic level in a memory cell. V WORD  is applied to one word line from the row decoder 12. V W  is applied to COL from the column decoder 13. V W  is applied to SAP from the row decoder 12. At this point, both of the NMOS transistors 71 and 72 are conducting. As a result, the voltages on the data lines are transferred onto the bit lines. Such voltage changes taking place in the bit lines are amplified by the CMOS sense amplifier 15a so that the voltages of the two bit lines are determined in a short time. At this point in time, V W  has been applied to SAP, as a result of which the voltage of one of the two bit lines is determined at V W . The voltage of the other of the two bit line becomes LOW (=0 V). These bit line voltages are applied to the NMOS transistors&#39; 51 and 54 sources. For example, suppose a memory cell formed by the capacitor 52 is selected, and the voltage setting of the data lines is carried out so that data of a high logic level is written in the memory cell in question. In this case, V W  is applied to the source of the NMOS transistor 51 and V WORD  that is greater than V W  is applied to the gate of the NMOS transistor 51. As a result, the NMOS transistor 51 comes to a complete conduction and the capacitor 52 holds V W  as a voltage for data of a high logic level. 
     In a data readout operation, one word line of FIG. 5 receives V WORD , and COL and SAP each receive V W . After the voltages of the bit lines are equalized by an equalizing circuit (not shown), a voltage held by, for example, the capacitor 52 within the memory cell circuit 11a is read out onto one bit line through the NMOS transistor 51 that is in a complete conducting state. According to the bit line voltage change, the CMOS sense amplifier 15a determines the voltages of the two bit lines. At this point, since V W  has been applied to SAP, the voltage of one of the bit lines is determined by the CMOS sense amplifier 15a at V W . Additionally, the voltage of the other of the bit lines becomes LOW (=0 V). These bit line voltages are read out onto the data lines through the NMOS transistors 71 and 72 within the column switch circuit 16a. 
     According to the present embodiment, V W  acts as a HIGH data write voltage. In other words, if V CC  is greater than V 0L , then V CC  becomes a write voltage. As a result, unlike conventional techniques, the present invention does not suffer from the previously described problem of how to resist a high voltage when such is applied to a memory cell. If V CC  is not greater than V 0L , V W  is boosted and becomes a write voltage. Therefore, the data-holding time can be extended as necessity requires. 
     Conventionally, 5 V DRAMs of a single power source type and 3.3 V DRAMs of a single power source type have not been manufactured under the same product series. If V REF  of the PSV control circuit 30 is set at 4.5 V, or V 0L , this makes it possible to cover these two different DRAMs under the same product series adopting the organization of FIG. 1. 
     Additionally, V REF  to be compared by the control circuit 30 with V CC  may be set above V 0L . Furthermore, even if the supply voltage to COL is set at V PERI  (=V CC ), as in the peripheral circuit 20, V W  still can act as a HIGH data write voltage, but the speed of read/write somewhat decreases as the ON impedance of the NMOS transistors 71 and 72 increases. 
     Embodiment 2 
     FIG. 6 is a block diagram showing the organization of a DRAM according to a second preferred embodiment of the invention. The second embodiment is characterized in that the memory cell section 10 contains shared switch circuits. FIG. 6 shows a first memory cell array 11.1 and a second memory cell array 11.2. The sense/switch circuit row 14 has a first row of shared switch circuits 17.1 and a second row of shared switch circuits 17.2, in addition to the sense amplifier row 15 and the column switch circuit row 16. 
     The first shared switch circuit row 17.1 is used to establish connection between the first memory cell array 11.1 and a circuit block formed by the sense amplifier 15 and the column switch circuit row 16, whereas the second shared switch circuit row 17.2 is used to establish connection between the second memory cell array 11.2 and the aforesaid circuit block. The PSV control circuit 30 of the present embodiment is identical in configuration with the one shown in FIG. 2, and the power supply circuit 40 of the present invention is identical in configuration with the one shown in FIG. 3. 
     The memory cell section 10 of FIG. 6 is partly detailed in FIG. 7. FIG. 7 shows a first memory cell circuit 11.1a, a second memory cell circuit 11.2a, a column switch circuit 16a, a first shared switch circuit 17.1a, and a second shared switch circuit 17.2a, in addition to the CMOS sense amplifier 15a, 
     The first memory cell circuit 11.1a has a memory cell forming one column of the first memory cell array 11.1 of FIG. 6. In addition to the cell plates 50, FIG. 7 shows NMOS transistors 51.1 and 54.1 and capacitors 52.1 and 55.1, and these elements are interconnected in the same manner as in the first embodiment. V WORD  is applied to a gate of the NMOS transistor 51.1 from the row decoder 12 through one word line. V WORD  is also applied to a gate of the NMOS transistors 54.1 from the row decoder 12 through another word line. 
     The second memory cell circuit 11.2a has a memory cell forming one column of the second memory cell array 11.2 of FIG. 6. Respectively indicated by reference numerals 51.2, 54.2 and 52.2, 55.2 are NMOS transistors each used to store 1-bit data and capacitors. V WORD  is applied to a gate of the NMOS transistor 51.2 from the row decoder 12 through one word line. V WORD  is also applied to a gate of the NMOS transistor 54.2 from the row decoder 12 through another word line. 
     A CMOS sense amplifier and a column switch circuit used here are identical in organization with their counterparts of the first embodiment, and thus they are indicated by the same reference numerals (i.e., 15a and 16a). SAP receives V W  from the row decoder 12, and COL receives V W  from the column decoder 13. 
     The first shared switch circuit 17.1a is a part of the first shared switch circuit row 17.1 of FIG. 6. This circuit 17.1a has two NMOS transistors 81.1 and 82.1. The NMOS transistor 81.1 has a source connected to one of two bit lines (i.e. a pair of common bit lines) of the CMOS sense amplifier 15a and the column switch circuit 16a, a drain connected to one of two bit lines of the first memory cell circuit 11.1a, and a gate connected to a first shared switch signal line SH1. The NMOS transistor 82.1 has a source connected to the other of the common bit lines, a drain connected to the other bit line of the first memory cell circuit 11.1a, and a gate connected to SH1. 
     The second shared switch circuit 17.2a is a part of the second shared switch circuit row 17.2 of FIG. 6. This circuit 17.2a has two NMOS transistors 81.2 and 82.2. The NMOS transistor 81.2 is sandwiched between one of the common bit lines and one of two bit lines of the second memory cell circuit 11.2a. The NMOS transistor 82.2 is sandwiched between the other common bit line and the other bit line of the second memory cell circuit 11.2a. These two NMOS transistors 81.2 and 82.2 are connected, through their respective gates, to a second shared switch signal line SH2. 
     The row decoder 12 of the second embodiment supplies the word lines of FIG. 7 with V WORD  and also supplies SAP with V W . Further, the row decoder 12 supplies SH1 or SH2 with V WORD  in a selective manner. In other words, the row decoder 12 applies V WORD  to SH1 when access to the first memory cell circuit 11.1a is required, while V WORD  is applied to SH2 when access to the second memory cell circuit 11.2a is required. 
     At the time when data is written in the first memory cell circuit 11.1a, V WORD  is applied to SH1 and a voltage at low logic level (=0 V) is applied to SH2. The source voltage of one of the two NMOS transistors 81.1 and 82.1 is raised by the CMOS sense amplifier 15a up to V W . V WORD  (&gt;V W ) is applied to the gates of these transistors 81.1 and 82.1 in order that they (transistors 81.1 and 82.1) come to a complete conduction. As a result, if data of a high logic level is written in the capacitor 52.1 that has been selected, then V W  supplied from the CMOS sense amplifier 15a is stored as a voltage for data of a high logic level. 
     At the time when data is written into the second memory cell circuit 11.2a, V WORD  is applied to SH2 and a voltage at low logic level (=0 V) is applied to SH1. The process of data write here is carried out in the same manner as in the data write operation to the first memory cell circuit 11.1a. 
     In a data readout operation to read data from the first memory cell circuit 11.1a, V WORD  is applied to SH1 and a voltage at low logic level (=0 V) is applied to SH2. At this point, the bit lines of the first memory cell circuit 11.1a are connected to the common bit lines through the first shared switch circuit 17.1a, while the bit lines of the second memory cell circuit 11.2a are electrically disconnected by the second shared switch circuit 17.2a from the common bit lines. Therefore, if it is assumed that the total storage capacity of the first and second memory cell circuits 11.1a and 11.2a is equal to the storage capacity of the memory cell circuit 11a of the first embodiment, the second embodiment will cut the bit line capacitance in half compared with the first embodiment. Usually, the readout voltage of from memory cell to bit line varies with CS/CB where CS is the capacitor&#39;s capacitance and CB is the bit line capacitance. Therefore, the readout voltage to a bit line doubles if the bit line capacitance falls fifty percent. This improves the amplification accuracy and the amplification speed of the CMOS sense amplifier 15a, and reliable, high-speed read operation can be achieved. 
     In a readout operation to read data from the second memory cell circuit 11.2a, V WORD  is applied to SH2 and a voltage at low logic level (=0 V) is applied to SH1. This electrically isolates the bit lines of the first memory cell circuit 11.1a from the common bit lines. The process of data readout here is carried out in the same manner as in the data readout operation from the first memory cell circuit 11.1a. 
     The second embodiment not only covers the advantages of the first embodiment but also provides the above described effects. 
     Other Preferred Embodiments 
     FIG. 8 shows another organization of the PSV control circuit 30 of FIG. 1 or FIG. 6. FIG. 8 shows a comparator 31, a PMOS transistor 32, a dummy capacitor 33, and a cell plate 34. This comparator 31 compare a voltage of V DC  held at the dummy capacitor 33 with V REF . The comparator 31 outputs a signal of a high logic level if V DC  &lt;V REF  or a signal of a low logic level if V DC  &gt;V REF , as V SIG . The dummy capacitor 33 corresponds to the capacitors 52 and 54 of FIG. 5 as well as to the capacitors 52.1, 52.2, 54.1, and 54.2 of FIG. 7. The dummy capacitor 33 is connected, at one of its terminals, to the cell plate 34. The same voltage as applied to the cell plate 50 is applied to the cell plate 34. 
     In the PSV control circuit 30 of FIG. 8, the application of a control signal V CONT  to the PMOS transistor&#39;s 32 gate at the time of POWER-ON-RESET makes the PMOS transistor 32 conduct for a certain period of time. This allows the dummy capacitor 33 to store electric charge by a proportional amount to V CC . Then, after an elapse of a predetermined period of time, V DC  and V REF  are compared by the comparator 31. The logic level of V SIG  is determined according to the result of the comparison operation. After having determined the V SIG  logic level at the time of POWER-ON-RESET in the above described sequence, the comparator 31 from then on holds the determined logic level. The power supply circuit 40 of FIG. 1 or FIG. 6 switches output voltage characteristics according to V SIG  held at and delivered by the comparator 31. 
     The PSV control circuit 30of FIG. 8 offers the advantage that advance evaluation of whether leakage of current is large or small (i.e., whether the data-holding time is long or short) can be made at the time of POWER-ON-RESET. This allows the output voltage characteristic of the power supply circuit 40 to be preset according to the evaluation result. The magnitude of V CC  and the data hold characteristic can be evaluated totally. 
     In the present example, the PSV control circuit 30 of FIG. 8 is made to operate for once at the time of POWER-ON-RESET. This, however, is not to be considered restrictive. The circuit 30 may operate periodically. For example, the PMOS transistor 32 is made to conduct every time a row address strobe signal RAS is input, whereby the dummy capacitor 33 is charged, and each time the dummy capacitor 33 is charged, V DC  is checked by the comparator 31. 
     FIG. 9 shows still another organization of the PSV control circuit 30 of FIG. 1 or FIG. 6. As seen from FIG. 9, the PMOS transistor 32 of FIG. 8 is replaced by an NMOS transistor 35 and the comparator 31 of FIG. 8 is replaced by a PMOS transistor 36 and a buffer 37. 
     The PSV control circuit 30 of FIG. 9 is described. V CONT  is applied to a gate of the NMOS transistor 35 at the time of POWER-ON-RESET, as a result of which the NMOS transistor 35 conducts just for a predetermined period of time. This allows the dummy capacitor 33 to store electric charge by a proportional amount to V CC . V DC , which is the gate voltage of the PMOS transistor 36, dissipates over a period of time because the dummy capacitor 33 leaks. When the gate-source voltage of the PMOS transistor 36 is held below its threshold voltage after an elapse of a predetermined period of time since the leakage current is small, the PMOS transistor 36 still remains in the OFF state. Therefore, the, buffer 37 sends out a signal of a low logic level as V SIG . When the gate voltage of the PMOS transistor 36 considerably drops since the leakage current is great, this causes the PMOS transistor 36 to conduct, and the buffer 37 sends out a signal of a high logic level as V SIG . After having determined the logic level of V SIG  at the time of POWER-ON-RESET in the above described sequence, the buffer 37 from then on holds the determined logic level. The power supply circuit 40 of FIG. 1 or FIG. 6 switches output voltage characteristics according to V SIG  held at and delivered by the buffer 37. 
     The PSV control circuit 30 of FIG. 9 offers the same effects as the one of FIG. 8, even with a smaller circuitry size. 
     In the present example, the PSV control circuit 30 of FIG. 8 is made to operate for once at the time of POWER-ON-RESET. This, however, is not to be considered restrictive. The PSV control circuit 30 may operate periodically. For example, the NMOS transistor 35 is made to conduct every time RAS is input, whereby the dummy capacitor 33 is charged, and each time the dummy capacitor 33 is charged, V DC  is checked by the PMOS transistor 36 and by the buffer 37. 
     FIG. 10 is a block diagram showing another organization of the power supply circuit 40 of the FIG. 1 or FIG. 6, which is similar to the one shown in FIG. 3 except for the provision of a comparator 43. 
     The voltage step-up circuit 41, used here, outputs a voltage that is equal to V CC  as V W  when the PSV control circuit 30 outputs V SIG  of a low logic level, while a voltage as a result of boosting V CC  is output from the circuit 41 as V W  when the PSV 5 control circuit 30 outputs V SIG  of a high logic level. The comparator 43 compares V CC  with V W  to deliver the comparison result to the first voltage step-up circuit 41 in order to hold the difference between V CC  and V W  below V T . The second voltage step-up circuit 42 outputs a voltage as a result of further boosting V W  from the circuit 41, as V WORD . 
     FIG. 11 shows a relationship between the internal power supply voltage (V CC ) and the external power supply voltage (V PERI , V W , V WORD ) for the power supply circuit 40 of FIG. 10. This graph shows characteristics when V REF  (i.e., the reference voltage of the PSV control circuit 30) is set at V 0L . 
     As seen from FIG. 11, V PERI  monotonically varies with V CC  over the full range of V CC . V W  agrees with V PERI  when V CC  is greater than V 0L , whereas V W  becomes a voltage (&lt;V 0L ) when V CC  is not greater than V 0L . In addition, the difference between V W  and V PERI  (=V CC ) is always set below V T . V WORD  is greater than V W  over the full range of V CC , and the difference between V W  and V WORD  is set above V T . 
     With the power supply circuit 40 of FIG. 10, even if V CC  is lower than V 0L , the difference between V PERI  (=V CC ) and V W  is held below V T . Therefore, as indicated in FIGS. 1 and 6, the memory cell section 10 and the peripheral circuit 20 can be interconnected directly without providing a level shift circuit between them. 
     FIG. 12 is a block diagram showing one DRAM organization to be adopted when, in order to increase the reliability of internal components, a voltage obtained by reducing V CC  is used as an internal power supply voltage. This organization is similar to the one of FIG. 1 or FIG. 6 except for the provision of a voltage step-down circuit 90. 
     The voltage step-down circuit 90 applies V RD  (i.e. the voltage as a result of lowering V CC ) to the peripheral circuit 20 as V PERI . Likewise, V RD  is applied to the PSV control circuit 30 as well as to the power supply circuit 40. V PERI , also in this case, monotonically varies with V CC . 
     For example, in a 5 V DRAM of a single power source type (V CC  recommended operating conditions: V 0  =5.0 V; V 0H  =5.5 V; and V 0L  =4.5 V), V CC  (=5 V) is reduced by the voltage step-down circuit 90 down to V RD  (=3.3 V). In such a case, V 0L  of FIG. 4 or FIG. 11 is changed to 3.0 V. 
     When using the power supply voltage characteristic form of FIG.4, V W  agrees with V PERI  if V RD  is greater than 3.0 V, and if V RD  is lower than 3.0 V, V W  is held at a constant value of 3.0 V. When using the power supply voltage characteristic form of FIG. 11, V W  agrees with V PERI  if V RD  is greater than 3.0 V. If V RD  is not greater than 3.0 V, V W  ≦3.0 V, and the difference between V PERI  (=V RD ) and V W  is restricted below V T . In each form, V PERI  monotonically varies with V RD  over the full range of V RD . Additionally, V WORD  is greater than V W  over the full range of V RD  and the difference between V W  and V WORD  is set below V T . 
     In a DRAM according to the organization of FIG. 12 capable of internally lowering V CC , the data-holding time can be extended as necessity requires, as in the first and second embodiments. 
     In each of the above-described preferred embodiments, the PSV control circuit 30 mounded on a DRAM generates V SIG  to the power supply circuit 40 according to V CC . The logical level of V SIG  may be fixed by, for example, a fuse ROM means when shipped from the factory, in which case the provision of the PSV control circuit 30 on DRAMs becomes unnecessary.