Analog/digital converter
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an analog/digital converter, and, more particularly, to a monolithic analog to digital converter (hereinafter called &#34;A/D converter&#34;) which is fabricated by the MOS technology. 
     2. Description of the Related Art 
     Conventionally, a successive approximation type A/D converter is known as an A/D converter fabricated by the MOS technology. 
     FIG. 1 is a circuit exemplifying this conventional successive approximation type A/D converter. As shown in FIG. 1, the conventional successive approximation type A/D converter includes a resistor-string type digital to analog converter (D/A converter) 1. This D/A converter 1 has a plurality of resistors 5 (resistance R) connected in series, and a plurality of switches 6 each of which selectively acquires the voltage across the associated resistor 5. The A/D converter equipped with this D/A converter 1 further has a comparator 2, a successive approximation register 3 and a switch controller 4. The comparator 2 sequentially compares an analog signal input to an analog input terminal 7 and supplied to the comparator 2 via a switch 8, with the output of the D/A converter 1, input via a switch 9. The successive approximation register 3 holds the output of the comparator 2. The switch controller 4 controls the individual switches of the D/A converter 1 based on the output of the successive approximation register 3. 
     While this conventional A/D converter can advantageously permit an easy simple increase in the number of bits, the increase in the number of bits inevitably increases the chip area. More specifically, this conventional A/D converter requires 2 N  resistors 5 and (2 N+1  -2) switches 6 in the case of N bits, and an increase in the number of bits significantly increase the chip area. 
     In this respect, therefore, there is a demand for an A/D converter, which has the advantage and feature of the resistor-string system and has a circuit structure to suppress an increase in the chip area. 
     FIG. 2 is a circuit diagram showing another conventional A/D converter designed to suppress an increase in the chip area. As shown in FIG. 2, this A/D converter includes an M-bit D/A converter 11 having a string of unit resistors 25 of a resistance R and a plurality of switches (not shown in FIG. 2) each of which selectively acquires the voltage across the associated resistor, and an N-bit D/A converter 15 having series-connected resistors 26 of a resistance R/2 N . A comparator 12 has a differential amplifier 22, a capacitor 20 connected between one input terminal of the comparator 12 and one input terminal of the differential amplifier 22, and a switch 21 connected between a pair of input terminals of the differential amplifier 22. The output of this comparator 12 is input to a successive approximation register 13. The output of the successive approximation register 13 is input to a first switch controller 14 and a second switch controller 16. The first switch controller 14 controls the switches of the D/A converter 11 and leads the output of the D/A converter 11 via an output line 23 to the aforementioned one input terminal of the comparator 12. A switch 19 is provided to this output line 23. The second switch controller 16 controls the switches of the D/A converter 15 and leads the output of the D/A converter 15 via an output line 24 to the other input terminal of the comparator 12. An analog input terminal 17 is connected via a switch 18 to the aforementioned one input terminal of the comparator 12. 
     This A/D converter of n (=M+N) bits comprises the resistors and switches, the number of which is about 1/2 N  compared to that of the simple resistor-string type n-bit A/D converter shown in FIG. 1. 
     FIG. 3 is a detailed configuration of the second D/A converter 15 shown in FIG. 2. As shown in FIG. 3, each resistor 26 of the second D/A converter 15 is constituted of 2 N  unit resistors 25 of a resistance R connected in parallel. 
     To improve the precision of the above conventional A/D converter, the resolution of the N-bit second D/A converter 15 should be increased. Since the second D/A converter 15 has 2 N  unit resistors 25 of a resistance R connected in parallel, the chip area inevitably increases as N increases. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide an analog/digital (A/D) converter which will suppress an increase in the circuit area even when the number of conversion bits increases. 
     The A/D converter according to the present invention comprises a first digital/analog converter including a first resistor string having unit resistors connected in series, and first switch means for selecting individual taps of said first resistor string and generating a first output signal of M bits (M being a natural number) as a reference to be compared with an analog input signal; reference-voltage supplying means for supplying voltages at both ends of an arbitrary one of said unit resistors in said first resistor string as reference voltages; a second digital/analog converter including N bits binary-weighted capacitive elements (N being a natural number) and second switch means for selectively connecting said binary-weighted capacitive elements to said reference-voltage supplying means to generate a second output signal; a comparator for comparing said analog input signal with said first and second output signals of said first and second digital/analog converters; a first controller for controlling said first digital/analog converter in accordance with an output of said comparator; and a second controller for controlling said second digital/analog converter in accordance with said output of said comparator, whereby upper M bits of (M+N) bits are subjected to analog/digital conversion by said first output signal of said first digital/analog converter and lower N bits are subjected to analog/digital conversion by said second output signal of said second digital/analog converter. 
     The A/D converter of this invention can ensure a greater number of bits and high precision without increasing the circuit area of the second D/A converter. In the case where an N-bit second D/A converter is constituted by the prior art, for instance, 2 2N  unit resistors and 2 N  switches are needed. According to this invention, however, such an N-bit second D/A converter simply requires 2 N  switches and capacitors of a capacitance 2 N  C. Even assuming that a unit resistor and a unit capacitor has the same area, the area of the D/A converter is reduced to 1/2 N  by this invention. 
     It is apparent that this invention can provide a low-cost A/D converter which is suitable for monolithic fabrication and will achieve large bits and high precision without enlarging the pellet area. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram showing the structure of a first conventional A/D converter; 
     FIG. 2 is a diagram showing the structure of a second conventional A/D converter; 
     FIG. 3 is a detailed resistors configuration diagram of the second D/A converter shown in FIG. 2; 
     FIG. 4 is a diagram showing the structure of an A/D converter according to a first embodiment of the present invention; 
     FIG. 5 is a detailed circuit diagram showing first and second D/A converters shown in FIG. 4; and 
     FIG. 6 is a circuit diagram mainly showing first and second D/A converters of a second embodiment of this invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Preferred embodiments of the present invention will now be described referring to the accompanying drawings. FIG. 4 illustrates the structure of an A/D converter according to a first embodiment of this invention. As shown in FIG. 4, the A/D converter of this embodiment comprises first and second D/A converters 31 and 35, first and second switch controllers 34 and 36, a comparator 32, and a successive approximation register 33. The first and second switch controllers 34 and 36 respectively control the first and second D/A converters 31 and 35. The comparator 32 compares an analog input from an analog input terminal 37 with the output of the second D/A converter 35 by means of a differential amplifier 42 and other components. The successive approximation register 33 holds the output of the comparator 32 and controls the first and second switch controllers 34 and 36. 
     The first D/A converter 31 includes a plurality of unit resistors 60 of a resistance R connected in series between a reference voltage source of V REF  and the ground, and a plurality of switches (not shown in FIG. 4; see switching transistors 61 in FIG. 5) which selectively extract voltages divided by the unit resistors (R) 60. 
     The first switch controller 34 controls the switches of the first D/A converter 31 and supplies the output voltage of the first D/A converter 31 to one input terminal of the comparator 32 via an output line 43. A switch 39 is provided to this output line 43. 
     The second D/A converter 35 receives voltages at both nodes a and b of one unit resistor (R) 60 among the resistor string of the first D/A converter 31 as first and second reference voltages. The second D/A converter 35 comprises capacitors 66 having binary-weighted capacitances of C to 2 N  C, and switches 67, which selectively couple those capacitors 66 to the first and second reference voltages. 
     The second switch controller 36 controls the switches 67 of the second D/A converter 35 in response to a control signal from the successive approximation register 33. 
     The comparator 32 has the aforementioned differential amplifier 42, a capacitor 40 connected between one input terminal of the comparator 32 and one input 48 of the differential amplifier 42, and a switch 41 connected between that one input 48 of the differential amplifier 42 and the other input 49 thereof. 
     The successive approximation register 33 controls the first and second switch controllers 34 and 36 in accordance with the comparison result of the comparator 32. 
     An analog signal input to the analog input terminal 37 is supplied via a switch 38 to the capacitor 40, while the output of the first D/A converter 31 is supplied to the capacitor 40 via the output line 43 provided with the switch 39. The output of the second D/A converter 35 is supplied via an output line 44 to the other input 49 of the differential amplifier 42. 
     FIG. 5 presents a detailed circuit diagram showing the first and second D/A converters 31 and 35 shown in FIG. 4. The circuit in FIG. 5 is for the case where the first D/A converter 31 has four bits (M=4) and the second D/A converter 35 has two bits (N=2). This first D/A converter 31 has sixteen unit resistors 60 of a resistance R and switching transistors 61 connected to nodes between those unit resistors 60. The individual switching transistors 61 are responsive to a signal from the first switch controller 34 and outputs divided voltages from the resistor string to the output line 43. Signal lines 45 and 46, led from a node &#34;a&#34; which is a mid point in the resistor string of the first D/A converter 31 and an adjoining node &#34;b&#34;, are connected to the second D/A converter 35, and reference voltages Va and Vb are supplied to the second D/A converter 35 via those signal lines 45 and 46. 
     The second D/A converter 35 has switches 50 to 54, and binary-weighted capacitors 55 to 57 each having one end connected to the output line 44. The capacitor 55 has the other end connected to the switches 50 and 51, the capacitor 56 has the other end connected to the switches 52 and 53, and the capacitor 57 has the other end connected to the switches 50 and 52 via the signal line 46. Those switches 50 to 54 are switched in accordance with a signal from the second switch controller 36. The binary-weighted capacitor 55 has a capacitance of 2C, and the binary-weighted capacitors 56 and 57 has a capacitance of C. 
     The action of the A/D converter according to this embodiment will be described referring to FIGS. 4 and 5. First, an analog signal V X , input to the analog input terminal 37, is sampled by the switches. At this time, the switches 41 and 54 are switched on, and the other end of the capacitor 40 is connected to the mid point (node a in FIGS. 4 and 5) of the resistor string of the first D/A converter 31. In other words, the capacitor 40 is biased by a voltage of V REF  /2. 
     When the switches 38 and 41 are switched on and the switch 39 is also switched on, charges of C O  (V X  -V REF  /2) are held in the capacitor 40 where C O  indicates the capacitance of the capacitor 40. In this manner, the analog input signal is held in the capacitor 40 during the successive approximation. 
     Then, to compare the voltage of V REF  /2 with the input signal voltage V X  first in the successive approximation, the successive approximation register 33 sends a control signal to the first and second switch controllers 34 and 36. In response to this control signal, the voltage V REF  /2 at the mid point (node a) is output to the output line 43. When the input analog signal V X  is larger than V REF  /2, &#34;1&#34;  is set to the MSB (Most Significant Bit) of the successive approximation register 33 in accordance with the output of the comparator 32, and, at the same time, the successive approximation register 33 sends a control signal to the first switch controller 34 in such a way that the first D/A converter 31 outputs a voltage of (3/4)V REF . When the input analog signal V X  is smaller than V REF  /2, on the other hand, &#34;0&#34; is set to the MSB of the successive approximation register 33 in accordance with the output of the comparator 32, and, at the same time, the successive approximation register 33 sends a control signal to the first switch controller 34 in such a way that the first D/A converter 31 outputs a voltage of (1/4)V REF . 
     By repeating the above successive approximation, digital values of the upper four bits are determined and are held in the successive approximation register 33. 
     A description will now be given of a voltage change V(48) at the first input terminal 48 of the differential amplifier 42 in the comparison of the upper four bits. This voltage change can be expressed by the following equation (1). 
     
         V(48)={(V.sub.REF /2.sup.6)(D.sub.1 2.sup.5 +D.sub.2 2.sup.4 +D.sub.3 2.sup.3 +D.sub.4 2.sup.2)-V.sub.X }+(V.sub.REF /2)        (1) 
    
     where D 1 , D 2 , D 3  and D 4  represent digital values of the MSB, the second bit, the third bit and the fourth bit, and will take a value of either &#34;0&#34; or &#34;1&#34;. The digital values are kept held in the successive approximation register 33 until comparison of the remaining, lower two bits is complete. 
     A voltage V(49) at the second input terminal 49 of the differential amplifier 42 in the comparator 32 is biased to V REF  /2 by keeping the switch 54 in FIG. 5 on until the comparison of the upper four bits ends. 
     Next, the successive approximation of the lower two bits is performed. This successive approximation is carried out by supplying the output of the second D/A converter 35 to the second input terminal 49 of the differential amplifier 42. During the aforementioned comparison of the upper four bits, the switches 50, 52 and 54 are switched on while the switches 51 and 53 are switched off. Under this condition, the combined capacitor (capacitance of 4C) of the capacitors 55 to 57 is charged to 4C(Va-Vb) where Va is the voltage at the node a of the first D/A converter 31 and Vb is the voltage at the node b. 
     If V(48)&gt;V(49) in the comparison of the fourth bit, &#34;0&#34; is set as the digital value D 2  of the fourth bit, switching the switches 51 and 52 on and switching the switches 50, 53 and 54 off. Accordingly, the charges accumulated in the combined capacitor are re-distributed. As a result, a voltage given by the following equation (2) appears on the output line 44. 
     
         Va-(1/2)(Vb-Va)=(V.sub.REF /2)-(1/2)(V.sub.REF /2.sup.4)=(V.sub.REF /2)-(V.sub.REF /2.sup.5)                                  (2) 
    
     Thus, the comparison of the fifth bit can be expressed by the following equation (3). ##EQU1## where D 5  represents the result of the comparison of the fifth bit. If V(48)&gt;V(49), D 5  will be set to &#34;0&#34;. If V(48)&lt;V(49), on the other hand, D 5  will be set to &#34;1&#34;. 
     Then, comparison of the LSB (Least Significant Bit) is executed. If D 5  is &#34;0&#34;, the switches 50 and 53 are switched on, and the switches 51, 52 and 54 switched off. At this time, a voltage of Va-{(Vb-Va)/4)=(V REF  /2)-(V REF  /2 6 ) appears on the output line 44. Thus, the comparison of the LSB is expressed by the following equation (4). ##EQU2## 
     If D 5  is &#34;1&#34; on the other hand, the switches 51 and 53 are switched on, and the switches 50, 52 and 54 switched off. At this time, a voltage of Va-{3(Vb-Va)/4}=(V REF  /2)-(3V REF  /2 6 ) appears on the output line 44. Thus, the comparison of the LSB is expressed by the following equation (5). ##EQU3## where D 6  represents the result of the successive approximation of the LSB. If V(48)&gt;V(49), D 6  will be set to &#34;0&#34;. If V(48)&lt;V(49), on the other hand, D 6  will be set to &#34;1&#34;. 
     The digital values D 1 , D 2 , . . . , and D 6  of the analog input signal V X  are determined in the above manner. 
     A second embodiment of this invention will briefly be described below referring to FIG. 6, which is a circuit diagram showing the first and second D/A converters 31 and 35. As shown in FIG. 6, the reference-voltage supplying lines 45 and 46 of the second D/A converter 35 are connected via buffer amplifiers 72 and 73 to the nodes a and b of the string of the resistors 60 of the first D/A converter 31, respectively. As the output resistance of the reference voltage source decreases by those buffer amplifiers 72 and 73, the time required for the re-distribution of the charges by the binary-weighted capacitors 66 is shortened. This ensure faster conversion. If the precision of the buffer amplifiers 72 and 73 is poor, an offset voltage may be produced. This offset voltage will not substantially affect the comparison since the offset voltage can be canceled by laying out the buffer amplifiers 72 and 73 in such a way that they have a better matching property.