Method and apparatus for multiplying a plurality of N numbers
This is a Continuation-in-Part of U.S. application Ser. No. 08/204,004 filed Mar. 1, 1994; which is a Continuation-in-Part of U.S. application Ser. No. 08/042,825 filed Apr. 5, 1993, which will issue as U.S. Pat. No. 5,291,430 on Mar. 1, 1994; which was a Continuation-in-Part of U.S. application Ser. No. 07/924,346, filed Aug. 03, 1992, which issued as U.S. Pat. No. 5,200,912 on Apr. 6, 1993; which was a Continuation-in-Part of U.S. application Ser. No. 07/794,995, filed Nov. 19, 1991, which issued as U.S. Pat. No. 5,136,537 on Aug. 4, 1992. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention is directed to a method for determining the product of a plurality of N numbers and an apparatus for carrying out that method. 
     In a computing system employing solid state components, preferably constructed from silicon components arrayed on a substrate, certain basic design criteria generally apply. For example, it is desired that the least space possible upon the substrate be occupied by each component. Further, it is desired that energy consumed by the apparatus be minimized as much as possible, especially in battery-supplied systems. Also, it is desired that the computing system operate as speedily as possible. 
     A multiplier for such computing systems is generally fashioned of a matrix of switching transistors, which matrix is of sufficient size to accommodate the maximum expected size of numbers to be handled by the computing apparatus. Thus, for example, in order to have a multiplication of a 4-digit number by a 4-digit number, a multiplier would necessarily comprise a 16×16 bit matrix (i.e., 16 columns of transistors, each column having 16 rows of transistors) with additional rows, or columns, or both to accommodate carries and other overhead operations involved in multiplication. 
     For smaller numbers, higher significance bits within the multiplier matrix are zero-filled as appropriate to correctly store the multiplicand and the multiplier involved in the multiplication operation. However, those zero-filled bits must still be powered-up in order to effect such zero-filling. Such zero-filled bits are necessarily involved in the calculations effected by the multiplier, so speed of operation, power requirements, and &#34;real estate&#34; (i.e., space) occupancy on the substrate are all sacrificed in accommodating larger numbers for multiplication operations. 
     It is well-known by those skilled in the art that a memory fetch operation is generally faster than a multiplication operation and generally consumes less power than a multiplication operation. Both of these features--increased speed and lesser power consumption--are desirable traits, especially in today&#39;s battery-powered laptop and notebook computers and in even smaller devices. 
     The product of a particular set of numbers will be the same resulting number every time those particular numbers of that set are multiplied. It is not necessary to recalculate the product every time the product is desired. It suffices to determine the product in advance and store the product for retrieval when needed. 
     It would be advantageous to have a method and apparatus for multiplying a plurality of numbers which does not require a multiplier to determine the product of the plurality of numbers. 
     SUMMARY OF THE INVENTION 
     The present invention includes a method for determining the product of a plurality of N numbers expressed in base Z; each number of the N numbers having a plurality of digits hierarchically arranged from a least-significant digit to a most-significant digit. The method comprises, in its preferred embodiment, the steps of: 
     (1) providing a plurality of N-1 storage units; each respective storage unit having a number S of arrays, each array comprising a (Z-1)-square array of storage loci. The number S is determined by the relationship ##EQU1## where x=an ordered succession in which the respective storage unit is employed. The plurality of storage units is arranged in a first storage unit and a plurality of succeeding storage units. The first storage unit includes a first plurality of storage loci, each respective first storage locus contains indicia of the partial product of a respective first digit of a first number of the N numbers and a respective second digit of a second number of the N numbers. The plurality of first storage loci are addressable by a plurality of pointers including a first elemental pointer and a second elemental pointer. The location of the first elemental pointer with respect to the first array is determined by the respective first digit and the location of the second elemental pointer with respect to the first array is determined by the respective second digit. The first elemental pointer and the second elemental pointer cooperate to identify a first solution locus among the first plurality of storage loci. The first solution locus contains indicia of the partial product of the respective first digit and the respective second digit. The plurality of succeeding storage units is each associated with a next succeeding number of the N numbers. One pointer of the first elemental pointer and the second elemental pointer identifies a designated succeeding array in the succeeding storage unit and the other pointer of the first elemental pointer and the second elemental pointer identifies a designated subset of storage loci in the designated succeeding array. A third elemental pointer associated with a particular respective digit of the next succeeding number identifies a second solution locus among the designated subsets. Each succeeding array&#39;s pointers cooperate to designate a next succeeding array and a designated subset of storage loci, and each of the succeeding arrays has an elemental pointer associated with digits of the next succeeding number of the N numbers to designate a succeeding solution locus until all N numbers are involved in the partial product. Each storage locus in each respective succeeding array contains indicia of the partial product of the particular digit of the particular number associated with the succeeding array and the partial product identified by the preceding array; 
     (2) determining a plurality of partial products comprising a respective partial product for each combination of the plurality of digits of each of the N numbers, each of the partial products having a combinational significance which is established by the significance of each digit of each of the N numbers of the combination involved in the respective partial product; 
     (3) effecting the accumulating in specified registered cells of a plurality of hierarchically arranged registered cells according to the following relationships: 
     P[m,n,o,p, . . . ]--accumulates in]--r[x]; 
     where: x=(m+n+o+p+. . . )-(N-1); 
     P[m,n,o,p, . . . ] represents the selected partial product; 
     m=significance of the digit from a first number of the N numbers involved in the selected partial product, m=1,2,3, . . . ; 
     n=significance of the digit from a second number of the N numbers involved in the selected partial product, n=1, 2, 3, . . . ; 
     o=significance of the digit from a third number of the N numbers involved in the selected partial product, o=1,2,3, . . . ; 
     p, . . .=significance of the digits from subsequent numbers involved in the selected partial product, p (and each subsequent significance)=1,2,3, . . . ; 
     r[x]=a specified register cell having a significance &#34;x&#34;; and 
     (4) effecting a shifting accumulation operation comprising shifting specific digits of the accumulated value stored in a lesser-significant register cell to the next-higher-significant register cell containing an accumulated value, and adding the specific digits to the accumulated value stored in the next-higher-significant register cell as least-significant digits; the specific digits being those digits of the accumulated value stored in the lesser-significant register cell having higher significance than the least-significant digit of the accumulated value; the shifting accumulation operation being effected sequentially between significance-adjacent register cells from the least-significant register cell to the most-significant register cell within the register. 
     A further aspect of the present invention includes an apparatus for practicing the above-described method, which apparatus, in its preferred embodiment, comprises a plurality of storage units for storing indicia of products of predetermined numbers, a logic circuit for employing a plurality of pointers to locate and fetch partial products from the plurality of storage units, a register having a plurality of register cells for storing accumulated values, which registered cells have a hierarchical significance; and an accumulating circuit for accumulating selected of the partial products to produce accumulated values, the accumulating circuit storing the accumulated values in specified register cells according to the relationships expressed above. 
     It is, therefore, an object of the present invention to provide a method and apparatus for determining the product of a plurality of N numbers which does not require a multiplier to determine the product. 
     Further objects and features of the present invention will be apparent from the following specification and claims when considered in connection with the accompanying drawings illustrating the preferred embodiment of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a representation of a generalized matrix for determining register set-ups according to the first embodiment of the method of the present invention. 
     FIG. 2 is a table illustrating the assignment of accumulated values to respective register cells according to the method of the present invention. 
     FIG. 3 is a representation of a generalized matrix for determining register set-ups according to the preferred embodiment of the method of the present invention. 
     FIG. 4 is a schematic block diagram of a prior art apparatus for determining the product of two numbers. 
     FIG. 5 is a schematic diagram of an apparatus for practicing the first embodiment of the method of the present invention in which the first number is segmented into a single first segment-pair and the second number is segmented into a single second segment-pair. 
     FIG. 6 is a schematic block diagram of an apparatus for practicing the first embodiment of the method of the present invention in which the multiplicand is segregated into first segment-pairs (a 1 ,b 1 ) and (a 2 ,b 2 ), and the multiplier is segregated into second segment-pairs (c 1 ,d 1 ) and (c 2 ,d 2 ). 
     FIG. 7 is a schematic block diagram of an apparatus for carrying out the preferred embodiment of the method of the present invention. 
     FIG. 8 is a schematic block diagram of an apparatus for providing power to selected portions of a multiplying device for carrying out the preferred embodiment of the method of the present invention. 
     FIG. 9 is a schematic block diagram of one embodiment of the apparatus of the present invention. 
     FIG. 10 is a schematic block diagram of the preferred embodiment of the apparatus of the present invention. 
     FIG. 11a is the top portion and FIG. 11b is the bottom portion of a skewed matrix representation of a multiplication of four numbers illustrating the register set-ups of the preferred embodiment of the present invention. 
     FIG. 12 is a schematic representation of a storage unit arrangement for effecting multiplication of three numbers according to the preferred embodiment of the present invention. 
     FIG. 13 is a schematic representation of a storage unit for effecting multiplication of five numbers according to the preferred embodiment of the present invention. 
     FIG. 14 is a schematic representation of employment of pointers in connection with the storage unit of the present invention for effecting multiplication of numbers. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Traditional high speed data signal processing apparatuses employ high speed multipliers to execute algorithms for purposes of such functions as speech compression, operation of high speed modems, operation of digital filters, and the like. Typically, the multipliers employed for such functions are large (on the order of a 16×16 bit array) and involve high power consumption, large die area (&#34;real estate&#34; occupancy on the substrate), and high precision. Other uses of multipliers, such as arithmetic logic units, generally suffer from the same disadvantages--high power consumption and large die area--in order to maintain high speed operation, and the disadvantages are exacerbated with requirements for higher speed, higher precision, and larger numbers. 
     The present invention includes a method for determining the product of two numbers (i.e., a method for multiplication) which comprises a distribution of multiplying operations among a plurality of smaller multipliers than the size of multiplier which would be required for multiplying with a single multiplier. Such distributive processing maintains speed of operation and precision of results while providing for a lesser die area requirement and affording the opportunity to only power-up the particular multiplying units in the distributive processing arrangement required for the particular multiplicand and multiplier involved in a specific multiplication operation. 
     Generally, the method involves the generation of partial products of portions of the multiplicand and multiplier, which partial products each individually require a smaller multiplier unit, and effecting a shifting accumulation operation in a register in which the partial products have been accumulated according to particular respective significance of the digits of the multiplicand and the digits of the multiplier. 
     In order to facilitate understanding of the terms used in describing the method of the present invention, the following terms are illustrated. 
     
         __________________________________________________________________________
 ##STR1##                                                                 
FIRST     FIRST     SECOND    SECOND                                      
ADDITIVE  SUBTRACTIVE                                                     
                    ADDITIVE  SUBTRACTIVE                                 
COMPRESSIONS                                                              
          COMPRESSIONS                                                    
                    COMPRESSIONS                                          
                              COMPRESSIONS                                
__________________________________________________________________________
(a.sub.1 + b.sub.1)                                                       
          (a.sub.1 - b.sub.1)                                             
                    (c.sub.1 + d.sub. 1)                                  
                              (c.sub.1 - d.sub.1)                         
(a.sub.2 + b.sub.2)                                                       
          (a.sub.2 - b.sub.2)                                             
                    (c.sub.2 + d.sub.2)                                   
                              (c.sub.2 - d.sub.2)                         
(a.sub.3 + b.sub.3)                                                       
          (a.sub.3 - b.sub.3)                                             
                    (c.sub.3 + d.sub.3)                                   
                              (c.sub.3 - d.sub.3)                         
.         .         .         .                                           
.         .         .         .                                           
.         .         .         .                                           
(a.sub.m + b.sub.m)                                                       
          (a.sub.m - b.sub.m)                                             
                    (c.sub.n + d.sub.n)                                   
                              (c.sub.n - d.sub.n)                         
__________________________________________________________________________
Primary Partial Products: P1.sub.m,n                                      
b.sub.1 d.sub.1                                                           
   b.sub.2 d.sub.1                                                        
      . . .                                                               
         b.sub.m d.sub.1                                                  
b.sub.1 d.sub.2                                                           
   b.sub.2 d.sub.2                                                        
      . . .                                                               
         b.sub.m d.sub.2                                                  
b.sub.1 d.sub.3                                                           
   b.sub.2 d.sub.3                                                        
      . . .                                                               
         b.sub.m d.sub.3                                                  
.  .     .                                                                
.  .     .                                                                
.  .     .                                                                
b.sub.1 d.sub.n                                                           
   b.sub.2 d.sub.n                                                        
      . . .                                                               
         b.sub.m d.sub. n                                                 
Secondary Partial Products: P2.sub.m,n                                    
(a.sub.1 + b.sub.1) (c.sub.1 + d.sub.1)                                   
          (a.sub.2 + b.sub.2) (c.sub.1 + d.sub.1)                         
                    . . .                                                 
                       (a.sub.m + b.sub.m) (c.sub.1 + d.sub.1)            
(a.sub.1 + b.sub.1) (c.sub.2 + d.sub.2)                                   
          (a.sub.2 + b.sub.2) (c.sub.2 + d.sub.2)                         
                    . . .                                                 
                       (a.sub.m + b.sub.m) (c.sub.2 + d.sub.2)            
(a.sub.1 + b.sub.1) (c.sub.3 + d.sub.3)                                   
          (a.sub.2 + b.sub.2) (c.sub.3 + d.sub.3)                         
                    . . .                                                 
                       (a.sub.m + b.sub.m) (c.sub.3 + d.sub.3)            
.         .            .                                                  
.         .            .                                                  
.         .            .                                                  
(a.sub.1 + b.sub.1) (c.sub.n + d.sub.n)                                   
          (a.sub.2 + b.sub.2) (c.sub.n + d.sub.n)                         
                    . . .                                                 
                       (a.sub.m + b.sub.m) (c.sub.n + d.sub.n)            
Tertiary Partial Products: P3.sub.m,n                                     
(a.sub.1 - b.sub.1) (c.sub.1 - d.sub.1)                                   
          (a.sub.2 - b.sub.2) (c.sub.1 - d.sub.1)                         
                    . . .                                                 
                       (a.sub.m - b.sub.m) (c.sub.1 - d.sub.1)            
(a.sub.1 - b.sub.1) (c.sub.2 - d.sub.2)                                   
          (a.sub.2 - b.sub.2) (c.sub.2 - d.sub.2)                         
                    . . .                                                 
                       (a.sub.m - b.sub.m) (c.sub.2 - d.sub.2)            
(a.sub.1 - b.sub.1) (c.sub.3 - d.sub.3)                                   
          (a.sub.2 - b.sub.2) (c.sub.3 - d.sub.3)                         
                    . . .                                                 
                       (a.sub.m - b.sub.m) (c.sub.3 - d.sub.3)            
.         .            .                                                  
.         .            .                                                  
.         .            .                                                  
(a.sub.1 - b.sub.1) (c.sub.n - d.sub.n)                                   
          (a.sub.2 - b.sub.2) (c.sub.n - d.sub.n)                         
                    . . .                                                 
                       (a.sub.m - b.sub.m) (c.sub.n - d.sub.n)            
 ##STR2##                                                                 
 ##STR3##                                                                 
 ##STR4##                                                                 
 ##STR5##                                                                 
__________________________________________________________________________
 
    
     According to a first embodiment of the method of the present invention, a first number and a second number are multiplied. The first number has a plurality of first digits hierarchically arranged from a least-significant place to a most-significant place, and the second number has a plurality of second digits hierarchically arranged from a least-significant place to a most-significant place. The most-significant places of the shorter of the two numbers are zero-filled appropriately that the first and second numbers occupy a like number of places. The first number is segmented into at least one first segment-pair, each of which first segment-pairs being representable by an expression &#34;a m , b m  &#34;, where &#34;a&#34; represents a higher-significance first segment of a respective first segment-pair and &#34;b&#34; represents a lower-significance first segment of the respective first segment-pair (&#34;m&#34;=1, 2, 3, . . . ). &#34;m&#34; represents the significance of the respective first segment-pair within the first number. The second number is similarly segmented into at least one second segment-pair, each of which second segment-pairs being representable by an expression &#34;c n , d n  &#34;, where &#34;c&#34; represents a higher-significance second segment of a respective second segment-pair and &#34;d&#34; represents a lower-significance second segment of a respective second segment-pair (&#34;n&#34;=1, 2, 3, . . . ). &#34;n&#34; represents the significance of the respective second segment-pair within the second number. Thus, the two numbers are segmented into an equal number of segment-pairs, and each of the first segments and second segments, for a given span of significance, comprise an equal number of digits. 
     An additive compression is calculated for each of the first segment-pairs and each of the second segment-pairs. That is, a first additive compression for each of the first segment-pairs, representable by an expression &#34;(a m  +b m )&#34; and a second additive compression for each of the second segment-pairs, representable by an expression &#34;(c n  +d n ) &#34;, are calculated. Similarly, a first subtractive compression for each of the first segment-pairs, representable by an expression &#34;(a m  -b m )&#34; and a second subtractive compression for each of the second segment-pairs, representable by an expression &#34;(c n  -d n )&#34; are also calculated. 
     A set of primary partial products, comprising the products of each lesser-significance segment of each of the first segment-pairs with each lesser-significance segment of each of the second segment-pairs, is calculated. Each primary partial product is representable by an expression &#34;P1 m ,n &#34; where P1 m ,n =b m  d n , and &#34;m n&#34; establishes a combinational significance for each of the primary partial products. 
     A set of secondary partial products, comprising the products of each of the first additive compressions with each of the second additive compressions, is calculated. Each of the secondary partial products is representable by an expression &#34;P2 m ,n &#34;, where P2 m ,n =(a m  +b m )(c n  +d n ), and &#34;m,n&#34; establishes a combinational significance for each of the secondary partial products. 
     A set of tertiary partial products, comprising the products of each of the first subtractive compressions with each of the second subtractive compressions, is calculated. Each of the tertiary partial products is representable by an expression &#34;P3 m ,n &#34;, where P3 m ,n =(a m  -b m )(c n  -d n ), and &#34;m,n&#34; establishes a combinational significance for each of the tertiary partial products. 
     The sum of a specific secondary partial product with a specific tertiary partial product having the same combinational significance, is calculated. The sum thus calculated is divided by two to provide an interim result. The primary partial product having the same combinational significance as the combinational significance of the secondary and tertiary partial products used in calculating the interim result is subtracted from that interim result to produce an additive factor. Each addition factor is representable by an expression &#34;F +   m ,n &#34;, were F +   m ,n =[(P2 m ,n +P3 m ,n)÷2]-P1 mn . 
     The difference of a secondary partial product less a tertiary partial product having the same combinational significance, is calculated to yield an interim difference. The interim difference is divided by two to produce a subtractive factor. Each subtractive factor is representable by an expression &#34;F -   m ,n &#34;, where F -   m ,n =(P2 m ,n -P3 m ,n)÷2. 
     The primary partial products, the subtractive factors, and the additive factors are accumulated in a register having an array of register cells to yield an accumulated value in appropriate of the register cells. The register cells are arrayed hierarchically from a first register cell to a (4j-1) register cell, where &#34;j&#34; represents the number of first segment-pairs. The first register cell has the lowest significance in the hierarchical arrangement, and each of the plurality of register cells is representable by r x , where &#34;x&#34; indicates the significance of a respective register cell. The accumulation of the plurality of primary partial products in a respective register cell is effected according to the relationship: 
     
         P1=b.sub.m d.sub.n --[accumulates in]→r.sub.2(m+n)-3. 
    
     The accumulation of subtractive factors in a respective register cell is effected according to the relationship: 
     
         F.sup.-.sub.m,n --[accumulates in]=r.sub.2(m+n)-2. 
    
     The accumulation of the additive factors in a respective register cell is effected according to the relationship: 
     
         F.sup.+.sub.m,n --[accumulates in]→r.sub.2(m+n)-1. 
    
     There is then effected a shifting accumulation operation from a lesser-significant register cell within the array of register cells to a next-higher-significance cell within the array of register cells. The shifting accumulation operation begins with the least-significant register cell and comprises shifting specific digits in the accumulated value in the lesser-significance register cell to the next-higher-significance register cell and summing the shifted digits of the higher significance as least-significant digits with the accumulated value in the next-higher-significance register cell. The specific digits to be shifted comprise all digits having higher significance than the number of least-significant digits in the accumulated value in the lesser-significance register cell equal to the number of digits in each of the first segments into which the first number is divided. The shifting accumulation operation continues from the least-significant cell and is effected sequentially between significance-adjacent register cells until the next-higher-significance register cell is the (4j-1) cell, that is, the highest-significance cell having an accumulated value stored therein. The number which is stored within the array of register cells after completion of the shifting accumulation operation described above comprises the product of the first number and second number, and may be shifted out of the array of register cells for use in further processing as appropriate in the apparatus employing the method of the present invention. 
     The method of the present invention may be illustrated by example: 
     EXAMPLE I 
     To multiply 256×256: 
     (1) Segregate the multiplicand and the multiplier into segment-pairs as follows: ##STR6## 
     (2) Determine additive compressions and subtractive compressions as follows: ##EQU2## 
     (3) Determine a primary partial product (P1) as follows: 
     
         bd=36 
    
     (4) Determine an additive factor (F + ) and a subtractive factor (F - ) as follows: ##EQU3## 
     (5) Accumulation of the determined terms in a plurality of register cells, hierarchically arranged according to significance, is determined as follows: 
     (a) Generally, according to generally accepted methods of manual multiplication: ##STR7## (b) Thus, the array of register cells is set up for accumulating values as follows: ##STR8## 
     (6) The next step is to effect a shifting accumulating operation, shifting specific digits from a lesser-significant register cell&#39;s accumulated value to the next-higher significance register cell, and adding those shifted specific digits to the accumulated value in the next-higher-significance register cell as least-significant digits. The shifted specific digits are all those digits having higher significance than the number of digits in &#34;b&#34;, &#34;b&#34; and &#34;d&#34; are required to have an equal number of digits. ##STR9## 
     (7) The contents of the register contain the correct answer (65,536), and are available for further processing by shifting the contents from the array of register cells, either serially or in parallel, as appropriate. 
     The method gives correct results regardless of how the multiplicand and multiplier are segregated, so long as &#34;a&#34; and &#34;c&#34; have an equal number of digits (blanks are treated as zeroes), and so long as &#34;b&#34; and &#34;d&#34; have an equal number of digits: 
     EXAMPLE II 
     (1) Segregate the multiplicand and the multiplier as follows: ##STR10## 
     (2) Determine additive compressions and subtractive compressions as follows: ##EQU4## 
     (3) Determine a primary partial product (P1) as follows: 
     
         bd=0 
    
     (4) Determine an additive factor (F + ) and a subtractive factor (F - ) as follows: ##EQU5## 
     (5) Accumulation of the determined terms in a plurality of register cells, hierarchically arranged according to significance, is determined as follows: 
     (a) Generally, according to generally accepted methods of manual multiplication: ##STR11## (b) Thus, the array of register cells is set up for accumulating values as follows: ##STR12## 
     (6) The next step is to effect a shifting accumulating operation, shifting specific digits from a lesser-significant register cell&#39;s accumulated value to the next-higher significance register cell, and adding those shifted specific digits to the accumulated value in the next-higher-significance register cell as least-significant digits. The shifted specific digits are all those digits having higher significance than the number of digits in &#34;b&#34;, &#34;b&#34; and &#34;d&#34; are required to have an equal number of digits. ##STR13## 
     (7) The contents of the register contain the correct answer (250,000), and are available for further processing by shifting the contents from the array of register cells, either serially or in parallel, as appropriate. 
     The method accommodates larger numbers as well: 
     EXAMPLE III 
     To multiply 1,234×5,678: 
     (1) Segregate the multiplicand and the multiplier as follows: ##STR14## 
     (2) Determine additive compressions and subtractive compressions as follows: ##EQU6## 
     (3) Determine a primary partial product (P1) as follows: 
     
         bd=2652 
    
     (4) Determine an additive factor (F + ) and a subtractive factor (F - ) as follows: ##EQU7## 
     (5) Accumulation of the determined terms in a plurality of register cells, hierarchically arranged according to significance, is determined as follows: 
     (a) Generally, according to generally accepted methods of manual multiplication: ##STR15## (b) Thus, the array of register cells is set up for accumulating values as follows: ##STR16## 
     (6) The next step is to effect a shifting accumulating operation, shifting specific digits from a lesser-significant register cell&#39;s accumulated value to the next-higher significance register cell, and adding those shifted specific digits to the accumulated value in the next-higher-significance register cell as least-significant digits. The shifted specific digits are all those digits having higher significance than the number of digits in &#34;b&#34;, &#34;b&#34; and &#34;d&#34; are required to have an equal number of digits. ##STR17## 
     (7) The contents of the register contain the correct answer (7,006,652), and are available for further processing by shifting the contents from the array of register cells, either serially or in parallel, as appropriate. 
     The method operates for numbers other than base 10 numbers. For example, to multiply 135×214 (Base 7 Numbers): 
     EXAMPLE IV 
     (Base 7 Numbers) 
     (1) Segregate the multiplicand and the multiplier as follows: ##STR18## 
     (2) Determine additive compressions and subtractive compressions as follows: ##EQU8## 
     (3) Determine a primary partial product (P1) as follows: 
     
         bd=26 
    
     (4) Determine an additive factor (F + ) and a subtractive factor (F - ) as follows: ##EQU9## 
     (5) Accumulation of the determined terms in a plurality of register cells, hierarchically arranged according to significance, is determined as follows: 
     (a) Generally, according to generally accepted methods of manual multiplication: ##STR19## (b) Thus, the array of register cells is set up for accumulating values as follows: ##STR20## 
     (6) The next step is to effect a shifting accumulating operation, shifting specific digits from a lesser-significant register cell&#39;s accumulated value to the next-higher significance register cell, and adding those shifted specific digits to the accumulated value in the next-higher-significance register cell as least-significant digits. The shifted specific digits are all those digits having higher significance than the number of digits in &#34;b&#34;, &#34;b&#34; and &#34;d&#34; are required to have an equal number of digits. ##STR21## 
     (7) The contents of the register contain the correct answer (32,556), and are available for further processing by shifting the contents from the array of register cells, either serially or in parallel, as appropriate. 
     The method can be extended to more fully segregate the multiplicand and the multiplier to further distribute the multiplication operation and thereby employ even smaller multipliers in distributive processing: 
     EXAMPLE V 
     (1) Segregate the multiplicand and the multiplier as follows: ##STR22## 
     (2) Determine additive compressions and subtractive compressions as follows: ##EQU10## 
     (3) Determine primary partial products (P1 m ,n) as follows: ##EQU11## 
     (4) Determine additive factors (F +   m ,n) and subtractive factors (F -   m ,n) as follows: ##EQU12## 
     (5) Accumulation of the determined terms in a plurality of register cells, hierarchically arranged according to significance, is determined as follows: 
     (a) Generally, according to generally accepted methods of manual multiplication: ##STR23## (b) Thus, the array of register cells is set up for accumulating values as follows: ##STR24## 
     (6) The next step is to effect a shifting accumulating operation, shifting specific digits from a lesser-significant register cell&#39;s accumulated value to the next-higher significance register cell, and adding those shifted specific digits to the accumulated value in the next-higher-significance register cell as least-significant digits. The shifted specific digits are all those digits having higher significance than the number of digits in &#34;b m  &#34;, &#34;b m  &#34; and &#34;d n  &#34; are required to have an equal number of digits. ##STR25## 
     (7) The contents of the register contain the correct answer (7,006,652), and are available for further processing by shifting the contents from the array of register cells, either serially or in parallel, as appropriate. 
     Inspection of the generally accepted manual method of multiplication reveals a simplified approach to the above-described method of the present invention and gives rise to an alternate embodiment of that method. 
     Specifically, for example, for a 4-digit number, the register set-up is determined as: ##STR26## The &#34;skewed matrix&#34; resulting from such an application of a manual multiplication technique may be written as a square matrix: (4-digit number, n=2) 
     
         ______________________________________                                    
a.sub.2 d.sub.1                                                           
        b.sub.2 d.sub.1                                                   
                       a.sub.1 d.sub.1                                    
                              b.sub.1 d.sub.1                             
a.sub.2 c.sub.1                                                           
        b.sub.2 c.sub.1                                                   
                       a.sub.1 c.sub.1                                    
                              b.sub.1 c.sub.1                             
a.sub.2 d.sub.2                                                           
        b.sub.2 d.sub.2                                                   
                       a.sub.1 d.sub.2                                    
                              b.sub.1 d.sub.2                             
a.sub.2 c.sub.2                                                           
        b.sub.2 c.sub.2                                                   
                       a.sub.1 c.sub.2                                    
                              b.sub.1 c.sub.2                             
______________________________________                                    
 
    
     The register set-up previously described in connection with the first embodiment of the method of the present invention is found on the diagonals. Note that the Primary Partial Products (P1 m ,n), the Additive Factors (F +   m ,n), and the Subtractive Factors (F -   m ,n) are found on diagonals also. 
     
         ______________________________________                                    
← columns                                                            
4-                                                                        
3-                                                                        
2-                                                                        
1-                                rows ↓                           
______________________________________                                    
a.sub.2 d.sub.1                                                           
          b.sub.2 d.sub.1                                                 
                 a.sub.1 d.sub.1                                          
                             b.sub.1 d.sub.1                              
1-                                                                        
a.sub.2 c.sub.1                                                           
          b.sub.2 c.sub.1                                                 
                 a.sub.1 c.sub.1                                          
                             b.sub.1 c.sub.1                              
2-                                                                        
a.sub.2 d.sub.2                                                           
          b.sub.2 d.sub.2                                                 
                 a.sub.1 d.sub.2                                          
                             b.sub.1 d.sub.2                              
3-                                                                        
a.sub.2 c.sub.2                                                           
          b.sub.2 c.sub.2                                                 
                 a.sub.1 c.sub.2                                          
                             b.sub.1 c.sub.2                              
4-                                                                        
______________________________________                                    
 
    
     That is, a diagonal extending through (Col. 1, Row 1) contains P1 1 ,1 (b 1  d 1 ); values on this diagonal accumulate in register cell r 1 . 
     The diagonal extending from (Col. 2, Row 1) to (Col. 1, Row 2) contains F -   1 ,1 (a 1  d 1  +b 1  c 1 ); values on this diagonal accumulate in register cell r 2 . 
     The diagonal extending from (Col. 3, Row 1) to (Col. 1, Row 3) contains P1 2 ,1 (b 2  d 1 ); F +   1 ,1 (a 1  c 1 ), and P1 1 ,2 (b 1  d 2 ); values on this diagonal accumulate in register cell r 3 . 
     The diagonal extending from (Col. 4, Row 1) to (Col. 1, Row 4) contains F -   2 ,1 (a 2  d 1  +b 2  c 1 ) and F -   1 ,2 (a 1  d 2  +b 1  c 2 ); values on this diagonal accumulate in register cell r 4 . 
     The diagonal extending from (Col. 4, Row 2) to (Col. 2, Row 4) contains F +   2 ,1 (a 2  c 1 ), P1 2 ,2 (b 2  d 2 ), and F +   1 ,2 (a 1  c 2 ); values on this diagonal accumulate in register cell r 5 . 
     The diagonal extending from (Col. 4, Row 3) to (Col. 3, Row 4) contains F -   2 ,2 (a 2  d 2  +b 2  c 2 ); values on this diagonal accumulate in register cell r 6 . 
     A diagonal through (Col. 4, Row 4) contains F +   2 ,2 (a 2  c 2 ); values on this diagonal accumulate in register cell r 7 . 
     Thus, for example, for a 6-digit number, where n=3, a square matrix may be set-up as follows: 
     
         ______________________________________                                    
← columns                                                            
6-                                                                        
5-                                                                        
4-                                                                        
3-                                                                        
2-                                                                        
1-                                      rows ↓                     
______________________________________                                    
a.sub.3 d.sub.1                                                           
      b.sub.3 d.sub.1                                                     
              a.sub.2 d.sub.1                                             
                      b.sub.2 d.sub.1                                     
                            a.sub.1 d.sub.1                               
                                  b.sub.1 d.sub.1                         
1-                                                                        
a.sub.3 c.sub.1                                                           
      b.sub.3 c.sub.1                                                     
              a.sub.2 c.sub.1                                             
                      b.sub.2 c.sub.1                                     
                            a.sub.1 c.sub.1                               
                                  b.sub.1 c.sub.1                         
2-                                                                        
a.sub.3 d.sub.2                                                           
      b.sub.3 d.sub.2                                                     
              a.sub.2 d.sub.2                                             
                      b.sub.2 d.sub.2                                     
                            a.sub.1 d.sub.2                               
                                  b.sub.1 d.sub.2                         
3-                                                                        
a.sub.3 c.sub.2                                                           
      b.sub.3 c.sub.2                                                     
              a.sub.2 c.sub.2                                             
                      b.sub.2 c.sub.2                                     
                            a.sub.1 c.sub.2                               
                                  b.sub.1 c.sub.2                         
4-                                                                        
a.sub.3 d.sub.3                                                           
      b.sub.3 d.sub.3                                                     
              a.sub.2 d.sub.3                                             
                      b.sub.2 d.sub.3                                     
                            a.sub.1 d.sub.3                               
                                  b.sub.1 d.sub.3                         
5-                                                                        
a.sub.3 c.sub.3                                                           
      b.sub.3 c.sub.3                                                     
              a.sub.2 c.sub.3                                             
                      b.sub.2 c.sub.3                                     
                            a.sub.1 c.sub.3                               
                                  b.sub.1 c.sub.3                         
6-                                                                        
______________________________________                                    
 
    
     Also, for example, for an 8-digit number, where n=4, a square matrix may be set-up as follows: 
     
         ______________________________________                                    
← columns                rows                                        
8-                                                                        
7-                                                                        
6-                                                                        
5-                                                                        
4-                                                                        
3-                                                                        
2-                                                                        
1-                                              ↓                  
______________________________________                                    
a.sub.4 d.sub.1                                                           
      b.sub.4 d.sub.1                                                     
             a.sub.3 d.sub.1                                              
                     b.sub.3 d.sub.1                                      
                          a.sub.2 d.sub.1                                 
                                b.sub.2 d.sub.1                           
                                     a.sub.1 d.sub.1                      
                                           b.sub.1 d.sub.1                
1-                                                                        
a.sub.4 c.sub.1                                                           
      b.sub.4 c.sub.1                                                     
             a.sub.3 c.sub.1                                              
                     b.sub.3 c.sub.1                                      
                          a.sub.2 c.sub.1                                 
                                b.sub.2 c.sub.1                           
                                     a.sub.1 c.sub.1                      
                                           b.sub.1 c.sub.1                
2-                                                                        
a.sub.4 d.sub.2                                                           
      b.sub.4 d.sub.2                                                     
             a.sub.3 d.sub.2                                              
                     b.sub.3 d.sub.2                                      
                          a.sub.2 d.sub.2                                 
                                b.sub.2 d.sub.2                           
                                     a.sub.1 d.sub.2                      
                                           b.sub.1 d.sub.2                
3-                                                                        
a.sub.4 c.sub.2                                                           
      b.sub.4 c.sub.2                                                     
             a.sub.3 c.sub.2                                              
                     b.sub.3 c.sub.2                                      
                          a.sub.2 c.sub.2                                 
                                b.sub.2 c.sub.2                           
                                     a.sub.1 c.sub.2                      
                                           b.sub.1 c.sub.2                
4-                                                                        
a.sub.4 d.sub.3                                                           
      b.sub.4 d.sub.3                                                     
             a.sub.3 d.sub.3                                              
                     b.sub.3 d.sub.3                                      
                          a.sub.2 d.sub.3                                 
                                b.sub.2 d.sub.3                           
                                     a.sub.1 d.sub.3                      
                                           b.sub.1 d.sub.3                
5-                                                                        
a.sub.4 c.sub.3                                                           
      b.sub.4 c.sub.3                                                     
             a.sub.3 c.sub.3                                              
                     b.sub.3 c.sub.3                                      
                          a.sub.2 c.sub.3                                 
                                b.sub.2 c.sub.3                           
                                     a.sub.1 c.sub.3                      
                                           b.sub.1 c.sub.3                
6-                                                                        
a.sub.4 d.sub.4                                                           
      b.sub.4 d.sub.4                                                     
             a.sub.3 d.sub.4                                              
                     b.sub.3 d.sub.4                                      
                          a.sub.2 d.sub.4                                 
                                b.sub.2 d.sub.4                           
                                     a.sub.1 d.sub.4                      
                                           b.sub.1 d.sub.4                
7-                                                                        
a.sub.4 c.sub.4                                                           
      b.sub.4 c.sub.4                                                     
             a.sub.3 c.sub.4                                              
                     b.sub.3 c.sub.4                                      
                          a.sub.2 c.sub.4                                 
                                b.sub.2 c.sub.4                           
                                     a.sub.1 c.sub.4                      
                                           b.sub.1 c.sub.4                
8-                                                                        
______________________________________                                    
 
    
     The register set-ups may be seen to lie along diagonals, and may be expressed in the following format (cases for n=2, n=3, and n=4 are tabulated for ease of comparison): 
     
         __________________________________________________________________________
r.sub.15                                                                  
        r.sub.14                                                          
            r.sub.13                                                      
                r.sub.12                                                  
                    r.sub.11                                              
                        r.sub.10                                          
                            r.sub.9                                       
                                r.sub.8                                   
                                    r.sub.7                               
                                        r.sub.6                           
                                            r.sub.5                       
                                                r.sub.4                   
                                                    r.sub.3               
                                                        r.sub.2           
                                                            r.sub.1       
__________________________________________________________________________
n = 2                               F.sub.2,2.sup.+                       
                                        F.sub.2,2.sup.-                   
                                            P1.sub.2,2                    
                                                F.sub.1,2.sup.-           
                                                    P1.sub.1,2            
                                                        F.sub.1,1.sup.-   
                                                            P1.sub.1,1    
                                            F.sub.1,2.sup.+               
                                                F.sub.2,1.sup.-           
                                                    P1.sub.2,1            
                                            F.sub.2,1.sup.+               
                                                    F.sub.1,1.sup.+       
n = 3               F.sub.3,3.sup.+                                       
                        F.sub.3,3.sup.-                                   
                            P1.sub.3,3                                    
                                F.sub.2,3.sup.-                           
                                    P1.sub.2,3                            
                                        F.sub.1,3.sup.-                   
                                            P1.sub.1,3                    
                                                F.sub.1,2.sup.-           
                                                    P1.sub.1,2            
                                                        F.sub.1,1.sup.-   
                                                            P1.sub.1,1    
                            F.sub.2,3.sup.+                               
                                F.sub.3,2.sup.-                           
                                    P1.sub.3,2                            
                                        F.sub.3,1.sup. -                  
                                            P1.sub.2,2                    
                                                F.sub.2,1.sup.-           
                                                    P1.sub.2,1            
                            F.sub.3,2.sup.+                               
                                    F.sub.1,3.sup.+                       
                                        F.sub.2,2.sup.-                   
                                            P1.sub.3,1                    
                                                    F.sub.1,1.sup.+       
                                    F.sub.3,1.sup.+                       
                                            F.sub.1,2.sup.+               
                                    F.sub.2,2.sup.+                       
                                            F.sub.2,1.sup.+               
n = 4                                                                     
    F.sub.4,4.sup.+                                                       
        F.sub.4,4.sup.-                                                   
            P1.sub.4,4                                                    
                F.sub.3,4.sup.-                                           
                    P1.sub.3,4                                            
                        F.sub.2,4.sup.-                                   
                            P1.sub.2,4                                    
                                F.sub.1,4.sup.-                           
                                    P1.sub.1,4                            
                                        F.sub.1,3.sup.-                   
                                            P1.sub.1,3                    
                                                F.sub.1,2.sup.-           
                                                    P1.sub.1,2            
                                                        F.sub.1,1.sup.-   
                                                            P1.sub.1,1    
            F.sub.3,4.sup.+                                               
                F.sub.4,3.sup.-                                           
                    P1.sub.4,3                                            
                        F.sub.3,3.sup.-                                   
                            P1.sub.3,3                                    
                                F.sub.2,3.sup.-                           
                                    P1.sub.2,3                            
                                        F.sub.3,1.sup.-                   
                                            P1.sub.2,2                    
                                                F.sub.2,1.sup.-           
                                                    P1.sub.2,1            
            F.sub.4,3.sup.+                                               
                    F.sub.2,4.sup.+                                       
                        F.sub.4,2.sup.-                                   
                            P1.sub.4,2                                    
                                F.sub.3,2.sup.-                           
                                    P1.sub.3,2                            
                                        F.sub.2,2.sup.-                   
                                            P1.sub.3,1                    
                                                    F.sub.1,1.sup.+       
                    F.sub.3,3.sup.+                                       
                            F.sub.1,4.sup.+                               
                                F.sub.4,1.sup.-                           
                                    P1.sub.4,1                            
                                            F.sub.1,2.sup.+               
                    F.sub.4,2.sup.+                                       
                            F.sub.2,3.sup.+                               
                                    F.sub.1,3.sup.+                       
                                            F.sub.2,1.sup.+               
                            F.sub.3,2.sup.+                               
                                    F.sub.3,1.sup.+                       
                            F.sub.4,1.sup.+                               
                                    F.sub.2,2.sup.+                       
__________________________________________________________________________
 
    
     By inspection, the register set-up may be recognized as being effected according to the following relationships: ##STR27## 
     A generalized case of a square matrix for determining register set-ups for multiplication of a first number and a second number according to the first embodiment of the method of the present invention is illustrated in FIG. 1. In FIG. 1, Columns numbered 1 through m are shown, indicating increasing significance from right to left, across the top of the square matrix; Rows numbered 1 through n are also shown, indicating increasing significance, from the top to the bottom of the square matrix. 
     The terms to be accumulated in respective registers r x  are indicated as being found on parallel diagonals. For example, for the case of a number divided into four first segment-pairs and four second segment-pairs (i.e., where m=4 and n=4), a square matrix of eight columns and eight rows will provide the elements to be accumulated in respective registers along its diagonals running from (Col. m, Row 1) to (Col. 1, Row n), where m=n. Only those terms falling within the square 8×8 matrix (delineated by bold line 10 in FIG. 1) along the various diagonals will be accumulated in the appropriate registers. Once accumulation is effected, the shifting accumulation operation previously described in connection with the first embodiment of the method of the present invention is carried out. 
     Comparing the (column, row) numbers, instead of the subscripts (m,n) indicating combinational significance for the segment-pairs of the multiplicand and multiplier with register numbers, one can, by inspection, observe that the accumulation of terms, or partial products, in register cells is effected according to the diagram illustrated in FIG. 2. Referring to FIG. 2, registers r x  are listed with the (column, row) location of the partial products to be accumulated in the respective registers tabulated colinearly with the respective register to the right of the register r x  into which they are accumulated. The sum of the column number and row number of each of the partial products accumulated within a respective register is tabulated colinearly to the left of the respective register number, r x . Inspection reveals that the (column, row) number sum (Σm+n) always equals the register designation, x, increased by one. That is, m+n=x+1. Therefore, the register r x  into which a given partial product is to be accumulated may be entirely determined by ascertaining its (column, row) location within an appropriate square matrix. 
     Accordingly, a simpler, preferred method for determining the product of two numbers according to the present invention does not require segmenting the multiplicand and multiplier into segment-pairs. According to the preferred method of the present invention, a first number (e.g., the multiplicand) has a plurality of first digits hierarchically arranged from a first least-significant place to a first most-significant place, and a second number (e.g., the multiplier) has a plurality of second digits hierarchically arranged from a second least-significant place to a second most-significant place. The preferred method comprises the steps of determining a plurality of partial products (treating blank places of the shorter of the two numbers as zeroes while determining the plurality of partial products), which plurality of partial products comprises a respective partial product for each pair-combination of the first digits and second digits. Each respective partial product thus has a combinational significance which is established by the significance of the first digit of the pair-combination involved in the respective partial product and by the significance of the second digit of the pair-combination involved in the respective partial product. A register is provided for storing information, which register has a plurality of register cells for storing accumulated values, each register cell having a hierarchical significance. Selected partial products are accumulated to produce accumulated values in specified register cells according to the following relationship: 
     
         P.sub.m,n --[accumulates in]→r.sub.x ; x=(m+n)-1 
    
     where &#34;P= m ,n &#34; represents a respective partial product, &#34;m&#34; represents the significance of the first digit of the pair-combination involved in the respective partial product (m=1, 2, 3, . . . ), &#34;n&#34; represents the significance of the second digit of the pair-combination involved in the respective partial product (n=1, 2, 3, . . . ), and &#34;r x  &#34; represents a specified register cell having a significance &#34;x&#34;. 
     Then a shifting accumulation operation is effected in the register. The shifting accumulation operation comprises shifting specific digits of the accumulated value stored in a lesser-significant register cell to the next-higher-significant register cell of the register cells containing an accumulated value, and adding the specific digits to the accumulated value stored in the next-higher-significant register cell as least-significant digits. The specific digits shifted are those digits of the accumulated value stored in the lesser-significant register cell having higher significance than the least-significant digit of the accumulated value. The shifting accumulation operation is effected sequentially between significance-adjacent register cells from the least-significant register cell to the most-significant register cell containing an accumulated value. The result contained within the array of register cells after completion of the shifting accumulation operation is the product of the multiplicand and multiplier and is available for shifting, serially or in parallel, as required for further processing. The significance of the respective digits of the multiplicand and multiplier directly determine the location of each partial product in a square matrix, and the location in the square matrix determines into which register cell each partial product is accumulated for the shifting accumulation operation. 
     In fact, with the proper apparatus for practicing this preferred method, no matrix is required. The significance of the first digit and the second digit involved in a respective partial product determine into which register cell the partial product is to be accumulated according to the relationship, x=(m+n)-1. 
     FIG. 3 is a representation of a generalized square matrix for determining register set-ups according to the preferred method of the present invention. In FIG. 3, digits of a first number (e.g., the multiplicand) are indicated as a m  (&#34;m&#34; indicates the significance of the first digit; m=1, 2, 3, . . . ) and digits of a second number (e.g., the multiplier) are indicated as b n  (&#34;n&#34; indicates the significance of the second digit; n=1, 2, 3, . . . ). By such arrangement, the significance of the respective first digits are directly correlative with the column number of the square matrix of FIG. 3, and the significance of the respective second digits are directly correlative with the row number of the square matrix of FIG. 3. Accordingly, a four-digit number may be represented by the 4×4 square matrix included within bold line 101, and diagonals running from (Col. m, Row 1) to (Col. 1, Row n), where m=n, in the generalized square matrix of FIG. 3 identify partial products within the 4×4 matrix defined by bold line 101 to be accumulated in specified register cells, r x . The matrix illustrated in FIG. 3 is not essential to the practice of the preferred method, but is helpful in illustrating and explaining the practice of the method. That is, placement of partial products within the square matrix of FIG. 3 is entirely dependent upon the combinational significance of the first digit and second digit of the pair-combination involved in a respective partial product; the (column, row) designation (m,n) entirely identifies the respective register cell into which a respective partial product is to be accumulated. Therefore, the combinational significance of a respective partial product entirely identifies the register cell into which the respective partial product is to be accumulated, and no matrix need be employed as an interim step or device for determining the register cell in which a respective partial product is to be accumulated. 
     In similar fashion, the product of a 6-digit multiplicand and a 6-digit multiplier can be determined by a square matrix defined by bold line 104 in FIG. 3 defining a 6×6 square matrix. The product of an 8-digit multiplicand and an 8-digit multiplier can be determined according to the preferred method of the present invention by a square 8×8 matrix defined by bold line 106 in FIG. 3; the product of a 10-digit multiplicand and a 10-digit multiplier may be determined by the square 10×10 matrix defined by bold line 108 in FIG. 3. 
     Thus, certain design parameters of a system for multiplying two numbers can be easily ascertained merely by knowing the expected size of multiplicand-multiplier operations to be accommodated by the system. For example, referring again to FIG. 3, the diagonal indicating accumulation of terms in register r 7  passes through (column, row) position (4,4); a designer need only know that either the multiplicand or the multiplier will comprise 4 digits. Knowing that, and calculating Σm+n=x+1 yields x=7. Thus, merely knowing that four digits will be involved in multiplication enables a designer to determine that he will be required to provide an array of 7 register cells to accommodate the preferred method of the present invention for a 4-digit multiplicand and 4-digit multiplier operation. Also, by determining the size of numbers required for a given multiplicand-multiplier operation, one can determine the number of multipliers required for determining the respective partial products involved in practicing the preferred method of the present invention. That is, for a 4-digit operation (requiring a 4×4 matrix), 16 partial products are calculated. A system designer may choose to provide 16 multipliers, thereby allowing single-clock cycle determination of the 16 partial products required, or a lesser number of multipliers may be provided to enable multi-clock cycle determination of the required 16 partial products. Moreover, since single-digit multiplications only are involved in determining partial products, only 4×4 multipliers are required. Thus, instead of a 256-bit (i.e., 16×16) multiplier for 4-digit multiplication operations, as would be required for a prior art multiplier apparatus, a designer may opt to employ only eight 4×4 multipliers (i.e., only 8×4×4=128 bits of area occupied) and save &#34;real estate&#34;. 
     Still further, control software or hardware may be programmed to power-up only the multipliers and register cells needed for a particular multiplication operation. Thus, for example, a 4×4 system may accommodate a 2-digit multiplication operation and only power-up the necessary multipliers (i.e., only m×n=2×2=4 multipliers are required), and only the necessary register cells need be powered-up (i.e., only (m+n-1=2+2-1=3 register cells are required). 
     Proper selection of the number of multipliers employed in distributive determination of partial products may actually speed the multiplication operation since numerous lower order multiplication operations to determine partial products occur simultaneously. Thus, if a designer elects to accommodate 4×4 multiplication operation (i.e., to multiply 4-digit numbers) using sixteen 4×4 multipliers (real estate occupancy=16×4×4=256 bits), while no real estate occupancy advantage is realized over the prior art, the multiplication operation will be completed in fewer clock cycles. 
     Another aspect of the present invention is an apparatus for carrying out the method of the present invention. 
     FIG. 4 is a schematic block diagram of a prior art apparatus for determining the product of two numbers. In FIG. 4, a multiplier apparatus 11 is illustrated comprising a multiplicand input 12 providing a multiplicand to a multiplier unit 14 and a multiplier input 16 providing a multiplier to multiplier unit 14. Multiplier unit 14 produces a result representing the product of the multiplicand and the multiplier via bus 18 to a result register 20. Multiplier unit 14 is large enough to accommodate a predetermined size of multiplicand and multiplier. For example, to accommodate a 4-digit multiplicand and a 4-digit multiplier, multiplier unit 14 must be a 16×16 bit multiplier. That is, in a prior art multiplier apparatus, such as multiplier apparatus 11 of FIG. 4, the multiplier unit 14 comprises 16 columns of transistors, each column having 16 rows of transistors, with additional rows, or columns, or both to accommodate carries and other overhead operations involved in multiplication. 
     FIG. 5 is a schematic diagram of an apparatus for practicing the first embodiment of the method of the present invention in which the first number is segmented into a single first segment-pair and the second number is segmented into a single second segment-pair. Such segmentation was illustrated and discussed in connection with Examples I through IV. In FIG. 5, a multiplier apparatus 30 is illustrated comprising an arithmetic logic unit (ALU) 32 receiving higher significance segment &#34;a&#34; of the first segment-pair (a,b) at an input 34 and receiving lower significance segment &#34;b&#34; of the first segment-pair (a,b) at an input 36. 
     An ALU 38 receives the higher significance segment &#34;c&#34; of second segment-pair (c,d) at an input 40 and receives lower significance segment &#34;d&#34; of second segment-pair (c,d) at an input 42. ALU 32 has a summing output 44 at which is produced the sum (a+b), and a difference output 46 at which is produced the difference (a-b). ALU 38 has a summing output 48 at which is produced the sum (c+d), and a difference output 50 at which is produced the difference (c-d). 
     A multiplier 52 is connected to receive summing output 44 of ALU 32 at an input 57, and is connected to receive summing output 48 of ALU 38 at an input 59. Multiplier 52 produces a secondary partial product (P2=[a+b][c+d]) at an output 54. A multiplier 56 is connected to receive difference output 46 of ALU 32 at an input 58 is connected to receive difference output 50 of ALU 38 at an input 60. Multiplier 56 produces a tertiary partial product (P3=[a-b][c-d]) at an output 62. Multiplier 56 also receives the quantity &#34;b&#34; from input 36 of ALU 32 at an input 64, and receives the quantity &#34;d&#34; from input 42 of ALU 38 at an input 66. Multiplier produces a primary partial product P1 (P1=bd) at an output 68. 
     An ALU 70 receives secondary partial product P2 from output 54 of multiplier 52 at an input 72, and receives tertiary partial product P3 from output 62 of multiplier 56 at an input 74. ALU 70 has a summing output 76 and a difference output 78. The sum of secondary partial product P2 and tertiary partial product P3 is produced at summing output 76, is divided by two by a divider 80, and is passed to an ALU 82 at an input 84. ALU 84 also receives primary partial product P1 from output 68 of multiplier 56 at an input 86 and produces at a difference output 88 additive factor F +  (F +  =[(P2+P3)+2]-P1). 
     The output produced at difference output 78 of ALU 70 is divided by two by a divider 90 to produce subtractive factor F -  (F -  =[(P2-P3]+2). Additive factor F.sup.÷, subtractive factor F - , and primary partial product P1 are appropriately provided to a register 92 according to the relationships described in connection with the first embodiment of the method of the present invention. Register 92 performs the shifting accumulation operation described in connection with the description of the first embodiment of the method of the present invention to generate the product of the numbers represented by first segment-pair (a,b) and second segment-pair (c,d) at an output 94. 
     FIG. 6 is a schematic block diagram of an apparatus for practicing the first embodiment of the method of the present invention in which the multiplicand is segregated into first segment-pairs (a 1 ,b 1 ) and (a 2 ,b 2 ), and the multiplier is segregated into second segment-pairs (c 1 ,d 1 ) and (c 2 ,d 2 ). In FIG. 6, a multiplier apparatus 100 is illustrated comprising a lower significance multiplier subsystem 102, a higher significance multiplier subsystem 104, and a cross-multiplying subsystem 106. Lower significance multiplier subsystem 102 and higher significance multiplier subsystem 104 are each substantially the same as multiplier apparatus 30, illustrated in FIG. 5. 
     Thus, lower significance multiplier subsystem 102 includes an ALU 108 receiving the higher-significance segment &#34;a 1  &#34; and the lower-significance segment &#34;b 1  &#34; of first segment-pair (a 1 ,b 1 ) as inputs; and an ALU 110 receiving the higher-significance segment &#34;c 1  &#34; and the lower-significance segment &#34;d 1  &#34; of second segment-pair (c 1 ,d 1 ) as inputs. 
     A multiplier 112 receives inputs from summing output 114 of ALU 108 and summing output 118 of ALU 110 to provide secondary partial product P2 1 ,1 (P2 1 ,1 =[a 1  +b 1  ][c 1  +d 1 ) at an output 122. A multiplier 124 receives inputs from difference output 116 of ALU 108 and difference output 120 of ALU 110 to provide tertiary partial product P3 1 ,1 (P3 1 ,1 =[a 1  -b 1  ][c 1  -d 1  ]) at an output 126. 
     An ALU 128 receives secondary partial product P2 1 ,1 from output 122 of multiplier 112 and tertiary partial product P3 1 ,1 from output 126 of multiplier 124 as inputs. The quantity (P2 1 ,1 +P3 1 ,1) is provided at summing output 130 of ALU 128, is divided by two by a divider 134, and is provided as an input to an ALU 138 Quantity &#34;b 1  &#34; and quantity &#34;d 1  &#34; are provided to multiplier 124 so that multiplier 124 provides primary partial product P1 1 ,1 (P1 1 ,1 =b 1  d 1 ) at an output 127. P1 1 ,1 is provided as an input to ALU 138 and is provided for accumulation in an accumulator 142. Difference output 140 of ALU 138 provides additive factor F +   1 ,1 (F +   1 ,1 =[(P2 1 ,1 +P3 1 ,1)÷2]-P 1 ,1) for accumulation in accumulator 142. The quantity (P2 1 ,1 -P3 1 ,1) is provided at difference output 132 of ALU 128 and is divided by two by a divider 136 to provide subtractive factor F -   1 ,1 (F -   1 ,1 =[P2 1 ,1 -P3 1 ,1 ]÷2) for accumulation in accumulator 142. 
     Higher significance multiplier subsystem 104 includes an ALU 144 receiving higher-significance segment &#34;a 2  &#34; and lower-significance segment &#34;b 2  &#34; of first segment-pair (a 2 ,b 2 ) as inputs. An ALU 146 receives higher-significance segment &#34;c 2  &#34; and lower-significance segment &#34;d 2  &#34; of second segment-pair (c 2 ,d 2 ) as inputs. A multiplier 156 receives inputs from summing output 148 of ALU 144 and summing output 152 of ALU 146. A multiplier 158 receives inputs from difference output 150 of ALU 144 and difference output 154 of ALU 146. Multiplier 156 produces secondary partial product P2 2 ,2 (P2 2 ,2 =[a 2  +b 2  ][c 2  +d 2  ]) at an output 160, and multiplier 158 produces tertiary partial product P3 2 ,2 (P3 2 .2 =[a 2  -b 2  ][c 2  -d 2  ]) at an output 162. 
     An ALU 164 receives secondary partial product P2 2 ,2 from output 160 of multiplier 156 and tertiary partial product P3 2 ,2 from output 162 of multiplier 158 as inputs. The quantity (P2 2 ,2 +P 2 ,2) is produced at summing output 166 of ALU 164, is divided by two by a divider 170, and is provided as an input to an ALU 172. The quantity (P2 2 ,2 -P3 2 ,2) is produced at difference output 168 of ALU 164 and is divided by two by a divider 174 to provide subtractive factor F -   2 ,2 (F -   2 ,2 =[P2 2 ,2 -P3 2 ,2 ]÷2) for accumulation in accumulator 142. Multiplier 156 receives quantity &#34;b 2  &#34; and quantity &#34;d 2  &#34; as inputs and produces primary partial product P1 2 .2 (P1 2 ,2 =b 2  d 2 ) at an output 176. Output 176 is operatively connected to provide primary partial product P1 2 ,2 as an input to ALU 172 and to provide P1 2 .2 for accumulation in accumulator 142. Difference output 178 of ALU 172 provides additive factor F +   2 ,2 (F +   2 ,2 =[P2 2 ,2 +P3 2 ,2 ]÷2-P1 2 ,2) for accumulation in accumulator 142. 
     Cross-multiplying subsystem 106 includes multipliers 180, 182, 184, and 186. Multiplier 180 receives as inputs the quantity (a 2  +b 2 ) produced at summing output 148 of ALU 144 and the quantity (c 1  +d 1 ) produced at summing output 118 of ALU 110, and produces secondary partial product P2 2 ,1 (P2 2 ,1 (P2 2 ,1 =[a 2  +b 2  ][c 1  +d 1  ]) at an output 188. Multiplier 182 receives as inputs the quantity (a 2  -b 2 ) produced at difference output 150 of ALU 144 and the quantity (c 1  -d 1 ) produced at difference output 120 of ALU 110, and produces tertiary partial product P3 2 ,1 (P3 2 ,1 =[a 2  -b 2  ][c 1  -d 1  ]) at an output 190. Multiplier 184 receives as inputs the quantity (c 2  +d 2 ) produced at summing output 152 of ALU 146 and the quantity (a 1  +b 1 ) produced at summing output 114 of ALU 108, and produces secondary partial product P2 1 ,2 (P2 1 ,2 =[ a 1  +b 1  ][c 2  +d 2  ]) at an output 192. Multiplier 186 receives as inputs the quantity (c 2  -d 1 ) produced at difference output 154 of ALU 146 and the quantity (a 1  -b 1 ) produced at difference output 116 of ALU 108, and produces tertiary partial product P3 1 ,2 (P3 1 ,2 =[a 1  -b 1  ][c 2  -d 2  ]) at an output 194. 
     An ALU 196 receives secondary partial product P2 2 ,1 from output 188 of multiplier 180 and tertiary partial product P3 2 ,1 from output 190 of multiplier 182. The quantity (P2 2 ,1 +P3 2 ,1) produced at summing output 198 of ALU 196 is divided by two by a divider 202 and provided as an input to an ALU 204. The quantity (P2 2 ,1 -P3 2 ,1) produced at difference output 200 of ALU 196 is divided by two by a divider 206 to produce subtractive factor F -   2 ,1 (F -   2 ,1 =[P2 2 ,1 -P3 2 ,1 ]÷2) for accumulation in accumulator 142. 
     Multiplier 158 receives as additional inputs the quantity &#34;b 2  &#34; and the quantity &#34;d 1  &#34; and produces primary partial product P1 2 ,1 (P1 2 ,1 =b 2  d 1 ) at an output 208. Output 208 is operatively connected to provide primary partial product P1 2 ,1 as an input to ALU 204 and to provide P1 2 ,1 for accumulation in accumulator 142. ALU 204 provides at its difference output 210 additive factor F +   2 ,1 (F +   2 ,1 =[P2 2 ,1 +P3 2 ,1 ]÷2-P1 1 ,1) for accumulation in accumulator 142. 
     An ALU 212 receives secondary partial product P2 1 ,2 (P2 2 ,1 =[a 1  +b 1  ][c 2  +d 2  ]) from output 192 of multiplier 184 and receives tertiary partial product P3 1 ,2 (P3 1 ,2 =[a 1  -b 1  ][c 2  -d 2  ]) from output 194 of multiplier 186 as inputs. ALU 212 provides at its summing output 214 a quantity (P2 1 ,2 +P3 1 ,2) which is divided by two by a divider 218 and provided as an input to an ALU 220. ALU 212 also provides at its difference output 216 a quantity (P2 1 ,2 -P3 1 ,2) which is divided by two by a divider 222 to produce subtractive factor F -   1 ,2 (F -   1 ,2 =[P 1 ,2 -P3 1 ,2 ]÷2) for accumulation in accumulator 142. 
     Multiplier 112 receives as inputs the quantities &#34;b 1  &#34; and &#34;d 2  &#34; and produces primary partial product P1 1 ,2 (P1 1 ,2 =b 1  d 2 ) at an output 224. Output 224 is operatively connected to provide primary partial product P1 1 ,2 as an input to ALU 220 and to provide P1 1 ,2 for accumulation in accumulator 142. ALU 220 produces at its difference output 226 additive factor F +   1 ,2 (F +   1 ,2 =[P2 1 ,2 +P3 1 ,2 ]÷2-P1 1 ,2) for accumulation in accumulator 142. 
     Accumulator 142 accumulates the various primary partial products P1 m ,n, additive factors F +   m ,n, and subtractive factors F -   m ,n for storage in an array of register cells 230 within a register 228. Register 228 performs a shifting accumulation operation as described in connection with the description of the first embodiment of the method of the present invention and the number residing within register 228 after completion of the shifting accumulation operation is the product of the first number comprising first segment-pairs (a 1 ,b 1 ) and (a 2 ,b 2 ) and the second number comprising second segment-pairs (c 1 ,d 1 ) and (c 2 ,d 2 ). That product is available for shifting, either serially or in parallel as appropriate, via an output 232. 
     FIG. 7 is a schematic block diagram of an apparatus for carrying out the preferred embodiment of the method of the present invention. In FIG. 7, a multiplying apparatus 240 receives a multiplicand from a multiplicand input 242 and receives a multiplier from a multiplier input 244. The multiplicand is received by a multiplexer 246 at an input 248 and the multiplier is received at an input 250 of multiplexer 246. 
     An array 252 of multipliers 254 is operatively connected by a bus 256 with multiplexer 246. Multiplexer 246 is programmed to recognize the significance of the respective digits of the multiplicand and the multiplier received at inputs 248, 250 so that, after routing respective pair-combinations of multiplicand digits and multiplier digits to available multipliers 254 for multiplication to produce a respective partial product for each such pair-combination, and after receiving the respective partial products from the array 252 of multipliers 254 via bus 256, multiplexer 246 directs accumulation of respective partial products in appropriate register cells 258 in result register 260 according to the significance of the multiplicand digit and the significance of the multiplier digit of the pair-combination involved in each respective partial product. 
     Result register 260 effects a shifting accumulation operation as described in connection with the preferred embodiment of the method of the present invention and, after completion of the shifting accumulation operation, the number residing in the array of register cells 258 is the product of the multiplicand and multiplier inputs received at inputs 248, 250 of multiplexer 246. That result is available for shifting through an output 262, either serially or in parallel as appropriate, for use or further processing by a system employing multiplying apparatus 240. 
     FIG. 8 is a schematic block diagram of the preferred embodiment of an apparatus for providing power to selected portions of a multiplying device for carrying out the preferred embodiment of the method of the present invention. 
     For clarity of understanding, elements appearing in FIG. 8 which are similar to elements appearing in FIG. 7 are designated by similar reference numerals, increased by 100. 
     In FIG. 8, a multiplying apparatus 340 receives a multiplicand from a multiplicand input 342 and receives a multiplier from a multiplier input 344. Multiplicands Md 1 , Md 2 , . . . , Md m  may be queued in multiplicand input 342; multipliers Mr 1 , Mr 2 , . . . , Mr n  may be queued in multiplier input 344. The current multiplicand Md 1  to be used in a multiplication operation by multiplying apparatus 340 is received by multiplexer 346 at an input 348 and the current multiplier Mr 1  to be used in the multiplication operation with current multiplicand Md 1  is received at an input 350 of multiplexer 346. 
     An array 352 of multipliers 354 is operatively connected by a bus 356 with multiplexer 346. Multiplexer 346 is programmed to recognize the significance of the respective digits of the multiplicands Md m  and the multipliers Mr n  received at inputs 348, 350 so that, after routing respective pair-combinations of multiplicand digits and multiplier digits (a m , b n , see FIG. 3) to appropriate multipliers 354 for multiplication to produce a respective partial product for each such pair-combination (a m , b n ). After receiving the respective partial products from array 352 of multipliers 354 via bus 356, multiplexer 346 directs accumulation of respective partial products in appropriate register cells 358 in result register 360 according to the significance of the multiplicand digit a m  and the significance of the multiplier digit b n  of the pair-combination involved in each respective partial product. 
     Result register 360 effects a shifting accumulation operation as described in connection with the preferred embodiment of the method of the present invention and, after completion of the shifting accumulation operation, the number residing in the array of register cells 358 is the product of the multiplicand Md m  and multiplier Mr n  received at inputs 348, 350 of multiplexer 346. That result is available for shifting through an output 362 either serially or in parallel as appropriate, for use or further processing by a system employing multiplying apparatus 340. 
     Multiplying apparatus 340 also includes a power control module 370 and power distribution buses 372, 374. Power control module 370 receives multiplicand inputs Md m  via an input 376 and receives multiplier inputs Mr n  via an input 378. Inputs 376, 378 may receive the current multiplicand Md 1  and the current multiplier Mr 1 , or may receive an earlier (i.e., yet to be processed) multiplicand Md m  and an earlier multiplier Mr n , as indicated in FIG. 8. 
     The &#34;powering up&#34; of selected components of multiplying apparatus 340 in the contemplated preferred embodiment illustrated in FIG. 8 consists mainly in precharging field effect transistor (FET) switching devices. Such precharging may easily be accomplished in less than a clock cycle. 
     Power distribution bus 372 is operatively connected with result register 360 and, in particular, is operatively connected to selectively provide power to respective register cells r 1 , . . . r x  via individual power lines 380. Power distribution bus 374 is operatively connected to selectively provide power to respective multipliers 354 via appropriate power lines 382. 
     Power control module 370 receives multiplicand inputs Md m  and multiplier inputs Mr n  and determines the sizes of a respective multiplicand input Md m  and multiplier Mr n  associated with a given multiplication operation. As discussed in connection with FIGS. 2 and 3, merely knowing the number of digits involved in a given multiplication operation enables determination of the number of register cells required to accommodate the preferred method of the present invention and, further, enables determination of the number of multipliers required for determining the respective partial products involved in practicing the preferred method of the present invention. 
     Power control module 370 may employ any appropriate means of a number of means for determining the sizes of multiplicands Md m  and multipliers Mr n . For example, the number of non-zero digits in a number may be counted, or the number of leading zeroes may be counted in a format comprising a predetermined number of digits. 
     Therefore, by way of example, power control module 370 may receive a multiplicand Md m  comprising the digits a 1 , a 2 , a 3 , 0 and may receive a multiplier Mr n  comprising digits b 1 , b 2 , b 3 , b 4 . According to the algorithmic relationship illustrated in FIG. 2, the number of registers r x  required to accommodate the preferred method of the present invention involving a 3-digit multiplicand and a 4-digit multiplier may be determined as r x  =m+n-1=(3+4-1)=6. Thus, power control module 370 may determine that six result registers, r x , must be powered up to accommodate the multiplication operation involving the particular multiplicand Md m  and Mr n  presently sampled. Similarly, power control module 370 may determine that a 3-digit multiplicand Mr n  (i.e., a 1 , a 2 , a 3 , 0) and a 4-digit multiplier Mr n  (i.e., b 1 , b 2 , b 3 , b 4 ) would require 12 (i.e., 3×4) partial products to be calculated. Accordingly, power control module 370 may determine that 12 multipliers 354 need power in order to accomplish the particular multiplication operation involved. Of course, as mentioned in connection with FIGS. 2 and 3, a designer may contemplate multi-cycle partial product calculations so that, if fewer than 12 multipliers 354 are available, another algorithmic relation must be applied by power control module 370 to determine the number of cycles required and the consequent number of multipliers 354 to be precharged to effect the particular multiplication desired. 
     Of course, either power distribution bus 372 or power distribution bus 374 may be omitted so that power to multipliers 354 only or power to result registers r x  only is controlled. 
     FIG. 9 is a schematic block diagram of one embodiment of the apparatus of the present invention. In FIG. 9, an apparatus 400 for multiplying a plurality of numbers is illustrated, including a first iteration multiplier 410, a second iteration multiplier 412, and an nth iteration multiplier 414. 
     First iteration multiplier 410 includes a multiplicand input 416, a multiplier input 418, an array of multipliers 420 (arranged similarly to the matter of arrangement of multiplier array 352 of FIG. 8). Of course, a power control module such as power control module 370 of FIG. 8 could likewise be employed with the apparatus illustrated in FIG. 9 or FIG. 10. First iteration multiplier 410 further includes a multiplexer 422, a result register 424, and an answer register 426. 
     Second iteration multiplier 412 includes a multiplicand input 428, an array of multipliers 430 (also similar to multiplier array 352 of FIG. 8). A power control module such as power control module 370 could be employed with second iteration multiplier 412, or a master power control module could be employed to serve each of the multipliers 410, 412, 414 of apparatus 400. Second iteration multiplier 412 further includes a multiplexer 432, a result register 434, and an answer register 436. 
     The nth iteration multiplier 414 is so designated to indicate that any number of multipliers may be employed in apparatus 400 to accomplish multiplication of any plurality of numbers. The nth iteration multiplier 414 includes a multiplicand input 438, an array of multipliers 440 (similar to multiplier array 352 of FIG. 8), a multiplexer 442, and a result register 444. 
     In operation, apparatus 400 determines a product involving n numbers. Thus, first iteration multiplier 410 receives a multiplicand via multiplicand input 416 and receives a multiplier via multiplier input 418. Multiplicand input 416 supplies a first multiplicand to multiplexer 422 at an input 417 to multiplexer 422 and multiplier input 418 provides a first multiplier to multiplexer 422 at an input 419 to multiplexer 422. Multiplier array 420 is operatively connected by a bus 421 with multiplexer 422. Multiplexer 422 is programmed to recognize the significance of the respective digits of the multiplicand and the multiplier received, respectively, at inputs 417, 419 so that, after routing respective pair-combinations of multiplicand digits and multiplier digits to available to multipliers in multiplier array 420 for multiplication to produce a respective partial product for each such pair-combination, and after receiving the respective partial products from multiplier array 420 via bus 421, multiplexer 422 directs accumulation of respective partial products in appropriate register cells in result register 424 according to the significance of the multiplicand digit and the significance of the multiplier digit of the pair-combination involved in each respective partial product. 
     Result register 424 effects a shifting accumulation operation as described in connection with the method of the present invention and, after completion of the shifting accumulation operation, the number residing in result register 424 is the result product of the first multiplicand and the first multiplier received at inputs 417, 419 of multiplexer 422. This result product can be conveyed to answer register 426 via a bus 425. 
     Second iteration multiplier 412 continues an iterative processing of the plurality of numbers involved in the product to be determined by apparatus 400. That is, a second multiplicand is received from multiplicand input 428 by second multiplexer 432 at an input 429, and multiplexer 432 receives at an input 431 the result product from first iteration multiplier 410 via a bus 427. In the alternative, bus 425 from result register 424 can be directly connected with input 431 of multiplexer 432, negating any need for answer register 426. Multiplicand input 428 preferably provides a next respective number of the plurality of numbers to be involved in the product to be determined by apparatus 400 as a second multiplicand at input 429 of multiplexer 432. 
     Multiplexer 432 is programmed to recognize the significance of the respective digits of the multiplicand and multiplier (i.e., the result product from first iteration multiplier 410) received at inputs 429, 431 so that, after routing respective pair-combinations of multiplicand digits and multiplier digits to available multipliers in multiplier array 430 for multiplication to produce a respective partial product for each such pair-combination, and after receiving the respective partial products from multiplier array 430 via a bus 433, multiplexer 432 directs accumulation of respective partial products in appropriate registers in result register 434 according to the significance of the multiplicand digit and the significance of the multiplier digit of the pair-combination involved in each respective partial product. 
     Result register 434 effects a shifting accumulation operation as described in connection with the method of the present invention and, after completion of the shifting accumulation operation, the number residing in result register 434 is a result product of the multiplicand received at input 429 of multiplexer 432 and the result product received from first iteration multiplier 410 at input 431 of multiplexer 432. That is, the result product in result register 434 is the product of the multiplicand provided by multiplicand input 416, the multiplier provided by multiplier input 418, and the multiplicand provided by multiplicand input 428. That result product is available for shifting via a bus 435 to answer register 436. 
     By such iterative multiplication of succeeding result products from successive iteration multipliers 410, 412, 414, by next succeeding respective numbers of the plurality of numbers the final product is determined. The final product of the plurality of n numbers may be shifted out of result register 444 at an output 446. 
     FIG. 10 is a schematic block diagram of the preferred embodiment of the apparatus of the present invention. In FIG. 10, an apparatus 500 for determining the product of a plurality of numbers is illustrated. Apparatus 500 is comprised of an input device 510 by which succeeding numbers of the plurality of numbers involved in the desired product may be introduced to a multiplexer 512 at an input 514. Multiplexer 512 is programmed to recognize the significance of the respective digits of a first number and a second number introduced at input 514 from input 510. Thus, after writing respective pair-combinations of first digits and second digits to available multipliers in an array of multipliers 516 (similar to multiplier array 352 of FIG. 8) for multiplication to produce a respective partial product for each such pair-combination, and after receiving the respective partial products from multiplier array 516 via a bus 518, multiplexer 512 directs accumulation of respective partial products in appropriate register cells of a result register 520 according to the significance of the first digit and the significance of the second digit received at input 514 of the pair-combination involved in each respective partial product. Result register 520 effects a shifting accumulation operation as described in connection with the method of the present invention and, after completion of this shifting accumulation operation, the number residing in register 520 is the result product of the first number and second number received at input 514 of multiplexer 512. 
     That result product is available for shifting through an output bus 522, either serially or in parallel as appropriate, for use for further processing. That is, the result product conveyed via bus 522 may be conveyed to an answer register 524. Answer register 524 produces the result product on a bus 525. Operative connection of bus 525 is controlled via a control unit 526 to be established with an input 528 of multiplexer 512 via a bus 530 or to be established with an output bus 532. 
     Thus, apparatus 500 may be employed for iterative multiplication of a plurality of numbers by providing the result product in answer register 524 as a second multiplication factor (i.e., a multiplicand or a multiplier) to multiplexer 512 via input 528. In such manner, a third number (successively provided from the plurality of numbers for which the final product is desired) may be provided to input 514 from input device 510 for iterative processing with the result product from answer register 524. That is, the third number provided to input 514 is treated in the manner of a multiplicand and the result product provided to input 528 via bus 530 is treated in the manner of a multiplier for a second iterative multiplication performed by apparatus 500. Each succeeding remaining respective number of the plurality of numbers for which the final product is desired may be subsequently provided at input 514 of multiplexer 512 for processing in the manner of a multiplicand for multiplications with the next preceding iteration result product (treated as a multiplier) received via bus 530 at input 528 of multiplexer 512. 
     When all remaining respective numbers of the plurality of numbers for which the final product is desired have been iteratively multiplied by the preceding iteration result product, result register 520 will contain the final product of all respective numbers of the plurality of numbers for which the final product is desired. Of course, bus 522 may be directly connected with control block 526, or may be directly connected with bus 530 to effect the required iterative multiplication operation. 
     Inspection of FIGS. 9 and 10 illustrates the method of the present invention for determining the product of a plurality of numbers. An iterative multiplication process is effected, whereby a first two numbers (a multiplicand and a multiplier) may be accumulated in register cells according to the following previously described relationships: ##STR28## 
     The shifting accumulation operation described in connection with the method in connection with the multiplication of two numbers is effected within the register in which the accumulation occurs and, after completion of the shifting accumulation operation, the register contains a result product of the first respective number of the plurality of numbers and the second respective number of the plurality of numbers. The method steps are repeated employing a next successive respective number of the plurality of numbers as one number of a multiplicand and a multiplier and employing the result product contained in the register as the result of the preceding iterative multiplication operation as the other number of the multiplicand and multiplier to generate a next iterative result product which in turn is employed with a next respective number of the plurality of numbers until all of the respective numbers of the plurality of numbers have been so iteratively multiplied with a next preceding iteration result product. The contents of the register after completion of the final shifting accumulation operation are the desired final product of the entire plurality of numbers involved. The same iterative method may be applied with whatever means is employed to accumulate partial products in the register cells among the various alternative methods described hereinabove. 
     FIG. 11a is the top portion and FIG. 11b is the bottom portion of a skewed matrix representation of a multiplication of four numbers illustrating the register set-ups of the preferred embodiment of the present invention. 
     In FIGS. 11a and 11b, a matrix 600 is comprised of a plurality of rows 610 and a plurality of columns 612. A first member comprising three digits of increasing significance (a 1 , a 2 , a 3 ) at row 620 is multiplied by a second number comprising three digits of increasing significance (b 1 , b 2 , b 3 ) at row 622. The partial products for effecting the multiplication of (a 1 , a 2 , a 3 ) (b 1 , b 2 , b 3 ) are arranged according to generally accepted methods of manual multiplication in rows 624, 626, 628. 
     Registers r 1 , r 2 , r 3 , . . . are assigned as indicated at row 630 (FIG. 11b). The sum of the significance of the digits involved in each partial product arrayed in each respective column of matrix 600 is indicated at line 632 for the multiplication of (a 1 , a 2 , a 3 ) (b 1 , b 2 , b 3 ). 
     For the above-described multiplication of (a 1 , a 2 , a 3 ) (b 1 , b 2 , b 3 ), inspection of matrix 600 reveals that the relationship between the sum of the significance (i.e., the combinational significance) of the respective partial products in each respective column are related to the assigned register as follows: 
     Σ m+n  --[accumulates in]--r[x]; 
     Where: 
     x=(m+n)-(N-1); 
     N=2; the number of numbers involved in the multiplication. 
     Continuing in FIGS. 11a, 11b, a third number comprising three digits of increasing significance (c 1 , c 2 , c 3 ) is indicated at line 634 (FIG. 11a), and the partial products for effecting the multiplication of (a 1 , a 2 , a 3 )) (b 1 , b 2 , b 3 ) (c 1 , c 2 , c 3 ) are arranged according to generally accepted methods of manual multiplication in rows 640, 642, 644, 646, 648, 650, 652, 654, 656. 
     The sum of the significance of the digits involved in each partial product arrayed in each respective column of matrix 600 which is involved in the multiplication of (a 1 , a 2 , a 3 ) (b 1 , b 2 , b 3 ) (c 1 , c 2 , c 3 ) is indicated at line 658 (FIG. 11a). The relationship between the sum of the combinational significance involved in the multiplication and the respective register designations for the respective columns is as follows: 
     Σ m+n+o  --[accumulates in]--r[x]; 
     Where 
     x=(m+n+o)-(N-1); N=3; the number of numbers involved in the multiplication. 
     A fourth number comprising three digits of increasing significance (d 1 , d 2 , d 3 ) is indicated at line 660 (FIG. 11a). The partial products for effecting the multiplication of (a 1 , a 2 , a 3 ) (b 1 , b 2 , b 3 ) (c 1 , c 2 , c 3 ) (d 1 , d 2 , d 3 ) are arranged according to generally accepted methods of manual multiplication in rows 662, 664, 666, 668, 670, 672, 674, 676, 678, 680, 682, 684, 686, 688, 690, 692, 694, 696, 698, 700, 702. 
     The sum of the partial product combinational significance relates to the register designations for each respective column of matrix 600 as follows: 
     Σ m+n+o+p  --[accumulates in]--r[x]. 
     Where 
     x=(m+n+o+p)-(N-1); 
     N=4; the number of numbers involved in the multiplication. 
     Thus, it may be seen that it is not necessary that iterative multiplication of a plurality of numbers be effected, as discussed in connection with FIG. 10 above, in order to accomplish the multiplication of a plurality of numbers. The relationship described above in connection with FIGS. 11a, 11b regarding the combinational significance and the designated registers for the various partial products of the N numbers involved in the multiplication holds true regardless of the number of numbers (N) involved in the multiplication, and regardless of the number of digits respectively contained in each of the N numbers. 
     Thus, the partial products accumulate in the respective register cells as follows: 
     P[m,n,o,p, . . . ]--[accumulates in]--r[x]; 
     where: x=(m+n+o+p+. . . )-(N-1); 
     P[m,n,o,p, . . .] represents a selected partial product; 
     m=significance of the digit from a first number of the N numbers involved in the selected partial product, m=1,2,3, . . . ; 
     n=significance of the digit from a second number of the N numbers involved in the selected partial product, n=1,2,3, . . . ; 
     o=significance of the digit from a third number of the N numbers involved in the selected partial product, o=1,2,3, . . . ; 
     p, . . .=significance of the digits from subsequent numbers involved in the selected partial product, p (and each subsequent significance)=1,2,3, . . . ; 
     r[x]=the specified register cell having a significance &#34;x&#34;. 
     The shifting accumulation operation described above in connection with the method regarding multiplication of two numbers is effected within the register to complete the multiplication of N numbers, once the accumulation of partial products within the register cells is complete. The contents of the register after completion of the shifting accumulation operation are the desired product of the entire plurality of N numbers. 
     Thus, no extra multiplying stages or iterative multiplications are required for multiplying a plurality of N numbers. All that is required is proper accumulation of partial products of digits of the N numbers in appropriate register cells according to the above-described relationship discussed in connection with FIGS. 11a, 11b, and completion of the shifting accumulation operation within the register. 
     Of course, whenever a first number and a second number are multiplied the same product will result. Similarly, whenever any given set of the same numbers is multiplied the same product will result. Accordingly, while many apparatus for effecting multiplication actually perform the multiplication. 
     FIG. 12 is a schematic representation of a storage unit arrangement for effecting the multiplication of three numbers according to the preferred embodiment of the present invention. In FIG. 12, a base 10 number system may have all of its non-zero products of two numbers stored in a 9-by-9 storage array 710. A logic unit (not shown in FIG. 12) executing a program may place a first elemental pointer P 1  according to a first digit of the two digits involved in the product. A second elemental pointer P 2  may be oriented according to the second digit involved in the product. Thus, for example, when multiplying (7×9), the logic unit program places first elemental pointer P 1  adjacent row 7 to identify the numbers stored in row 7 as a subset of the storage loci which comprise storage unit 710. Second elemental pointer P 2  may be oriented by the logic unit according to the second digit (9) of the numbers involved in the multiplication (7×9), as illustrated in FIG. 12. Accordingly, the subset of storage loci identified by first elemental pointer P 1  (i.e., row 7) now has identified within that subset of storage loci a first solution locus which contains indicia of the product of the multiplication (7×9), as illustrated in FIG. 12. 
     This approach is similar to the well-known multiplication table familiar to those even moderately skilled in the art. However, FIG. 12 also includes a succeeding storage unit 712. There is a respective succeeding storage array for each column of storage unit 710. For example, the succeeding storage array 714 is associated with column 9 of storage unit 710 and is illustrated in an enlarged scale to facilitate explanation of the storage unit arrangement illustrated in FIG. 12. 
     Thus, if one wishes to determine the product of multiplication of three numbers (e.g., 7×9×5), one may employ a logic unit to position a first elemental pointer P 1  adjacent row 7 of storage unit 710 to identify a subset of storage loci, as described previously. A second elemental pointer P 2  may be oriented with respect to storage unit 710 by the logic unit (not shown in FIG. 12) by the second digit (9) to identify a first solution locus at the intersection of row 7 and column 9 of storage unit 710. Thus, the product 63 is contained in the first solution locus identified by first elemental pointer P 1  and second elemental pointer P 2 . 
     Completing the multiplication of (7×9×5) requires identification of which succeeding storage array of succeeding storage unit 712 will be involved in that multiplication. In this case, the second digit involved in the multiplication being 9, succeeding storage array 714 is identified as a designated succeeding array to be involved in the particular multiplication undertaken in this example. It may be considered that a first derivative pointer D 1  is oriented (by the logic unit; not shown in FIG. 12) with respect to succeeding storage array 714 according to the intersection of first elemental pointer P 1  and second elemental pointer P 2  in storage unit 710. Thus, first derivative pointer D 1  identifies succeeding storage array 714 as a designated succeeding storage array and, further, identifies a designated subset of storage loci in the succeeding storage array 714 aligned along the row associated with the first solution locus identified in storage unit 710. 
     A third elemental pointer P 3  associated with the third digit (5) involved in the multiplication (7×9×5) identifies a second solution locus in succeeding storage array 714 at the intersection of the designated subset of storage loci identified in succeeding storage array 714 by first derivative pointer D 1  and the column identified in succeeding storage array 714 by third elemental pointer P 3 . As can be seen by inspecting FIG. 12, the stored value at the second solution locus identifying the product of (7×9×5) contains indicia of the product of that multiplication, the number 315. 
     Thus, the product of (7×9×5) need not be recalculated each time it is required. A search and fetch is executed using appropriate pointers to locate the prestored indicia of that product each time that product is required. It may be seen that the product of three numbers as illustrated in FIG. 12, is accomplished by three elemental pointers P 1 , P 2 , P 3 . Indeed, as will be illustrated, the product of N numbers may be found and fetched using N elemental pointers with (N-1) storage units of the sort illustrated in FIG. 12. 
     The storage unit arrangement illustrated in FIG. 12 may be employed to determine the partial products required for use by the apparatus or the method previously described herein for effecting multiplication of a plurality of numbers. 
     FIG. 13 is a schematic representation of a storage unit for effecting multiplication of five numbers according to the preferred embodiment of the present invention. In FIG. 13, a first storage unit 710 is illustrated comprising a 9-by-9 square matrix containing indicia of all products of two single-digit numbers expressed in base 10. Associated with storage unit 710 is a plurality of first succeeding storage arrays in a first succeeding storage unit 712, with each column of storage unit 710 having an associated 9-by-9 first succeeding storage array. Thus, there is a first succeeding storage array 714 associated with column 9, a first succeeding storage array 716 associated with column 8, a first succeeding storage array 718 associated with column 7, a first succeeding storage array 720 associated with column 6, a first succeeding storage array 722 associated with column 5, a first succeeding storage array 724 associated with column 4, a first succeeding storage array 726 associated with column 3, a first succeeding storage array 728 associated with column 2, and a first succeeding storage array 730 associated with column 1. 
     As described above in connection with FIG. 12, storage unit 710 and succeeding storage unit 712 suffice to provide all indicia of all partial products of three digits expressed in base 10. Of course, smaller arrays may suffice to effect multiplication of digits expressed in other bases less than 10. A (Z-1)-square array will store all indicia of products of two digits expressed in base Z. 
     To effect multiplication of four digits expressed in base 10, there is provided for each of the first succeeding storage arrays 714, 716, 718, 720, 722, 724, 726, 728, 730 in succeeding storage unit 712 a plurality of second succeeding storage arrays in a second succeeding storage unit 732. Thus, for example, as seen in FIG. 13, first succeeding storage array 714 will have a second succeeding storage array 734 associated with its column 9, a second succeeding storage array 736 associated with its column 8, a second succeeding storage array 738 associated with its column 7, a second succeeding storage array 740 associated with its column 6, a second succeeding storage array 742 associated with its column 5, a second succeeding storage array 744 associated with its column 4, a second succeeding storage array 746 associated with its column 3, a second succeeding storage array 748 associated with its column 2, and a second succeeding storage array 750 associated with its column 1. 
     For effecting multiplication of five digits expressed in base 10, each of the second succeeding storage arrays (e.g., second succeeding storage arrays 734, 736, 738, 740, 742, 744, 746, 748, 750) has a respective plurality of third succeeding storage arrays in a third succeeding storage unit 752. Thus, for example, second succeeding storage array 750 has a third succeeding storage array 754 associated with its column 9, a third succeeding storage array 756 with its column 8, a third succeeding storage array 758 with its column 7, a third succeeding storage array 760 with its column 6, a third succeeding storage array 762 with its column 5, a third succeeding storage array 764 with its column 4, a third succeeding storage array 766 with its column 3, a third succeeding storage array 768 with its column 2, and a third succeeding storage array 770 with its column 1. 
     Thus, by inspection of FIG. 13, it is clear that the total number S of (Z-1)-square arrays in each succeeding storage unit is determined by the relationship: ##EQU13## where X=an ordered succession in which the respective storage unit is employed in a multiplication operation. 
     By way of example, the product of the multiplication (9×9) may be located using a first elemental pointer P 1  and a second elemental pointer P 2  to identify a first solution locus as the storage locus identified by the letter &#34;A&#34; in FIG. 13. If one desires to ascertain the product of the multiplication (9×9×9), one employs a first derivative pointer D 1  associated with the first solution locus A and a third elemental pointer P 3  associated with first succeeding storage array 714 to identify a second solution locus at the storage locus indicated by letter &#34;B&#34; in FIG. 13. 
     One may see by inspecting FIG. 13 that the storage locus identified by letter &#34;C&#34; contains indicia of the product of the multiplication (9×9×2×9). Similarly, the storage locus indicated by letter &#34;D&#34; contains indicia of the product of the multiplication (9×9×1×9). 
     Thus, one may prestore indicia of products of numbers and fetch those products when needed as illustrated in FIG. 13. That is, in a number system expressed in base Z, an ordered succession of a plurality of (Z-1)-square arrays may be accessed for determining the product of N numbers using N pointers and (N-2) derivative pointers. 
     FIG. 14 is a schematic representation of the employment of pointers in connection with the storage unit of the present invention for effecting multiplication of numbers. In FIG. 14, a first storage unit 710 is illustrated as being addressed by a first elemental pointer P 1  and a second elemental pointer P 2  which cooperate to identify a first solution locus L 1 . First solution locus L 1  positions a first derivative pointer D 1  which identifies a designated succeeding storage array, such as first succeeding storage array 714, and identifies a designated subset of storage loci along a particular row 713 of first succeeding storage array 714. 
     A third elemental pointer P 3  is aligned with first succeeding storage array 714 according to the third number associated with the multiplication for which a product is sought. Third elemental pointer P 3  cooperates with first derivative pointer D 1  to identify a second solution locus L 2 . Second solution locus L 2  positions a second derivative pointer D 2  which identifies a designated next-succeeding storage array, such as second succeeding storage array 750. Second derivative pointer D 2  also identifies a designated subset of storage loci within second succeeding storage array 750 along a particular row 749. 
     A fourth elemental pointer P 4  associated with second succeeding storage array 750 is positioned with respect to second succeeding storage array 750 by the next-succeeding digit involved in the particular multiplication for which a product is sought. Fourth elemental pointer P 4  cooperates with second derivative pointer D 2  to identify a third solution locus L 3 . Third solution locus L 3  positions a third derivative pointer D 3 . Third derivative pointer D 3  identifies a designated next-succeeding array, such as third succeeding storage array 754, and identifies a designated subset of storage loci associated with a particular row 753 of third succeeding storage array 754. 
     A fifth elemental pointer P 5  associated with third succeeding storage array 754 is positioned with respect to third succeeding storage array 754 by the next-succeeding digit involved in the multiplication for which a product is sought. Fifth elemental pointer P 5  cooperates with third derivative pointer D 3  to identify a fourth solution locus L 4  which contains indicia of the product of those digits which positioned elemental pointers P 1 , P 2 , P 3 , P 4 , P 5 . 
     Thus, it may be seen that for a plurality of N numbers, a plurality of N elemental pointers cooperates with a plurality of (N-2) derivative pointers in addressing (N-1) 3 storage arrays to locate prestored indicia of the product of the particular N numbers involved in the multiplication. 
     Of course, throughout this description, the use of the terms &#34;row&#34; and &#34;column&#34; are arbitrary. That is, horizontally oriented block sets may as well be termed &#34;columns&#34; as &#34;rows&#34; without affecting the scope or operation of the present invention. Also, vertically oriented block sets may as well be termed &#34;rows&#34; as &#34;columns&#34; without affecting the scope or operation of the present invention. 
     It is to be understood that, while the detailed drawings and specific examples given describe preferred embodiments of the invention, they are for the purpose of illustration, that the apparatus of the invention is not limited to the precise details and conditions disclosed and that various changes may be made therein without departing from the spirit of the invention which is defined by the following claims: