Cross-checking for on-the-fly Reed Solomon error correction code
This is related to U.S. patent application Ser. No. 07/650,791, filed on Feb. 1, 1991, now U.S. Pat. No. 5,241,546. 
     FIELD OF THE INVENTION 
     The present invention relates to cross-checking the correction of byte errors detected within a data stream. More particularly, the present invention relates to improved methods and apparatus for reducing the probability of misdetection of error miscorrection within a serial data stream of data blocks, such as data blocks read out from a storage surface within a rotating disk data storage subsystem. 
     BACKGROUND OF THE PRESENT INVENTION 
     The present invention comprises an improvement over the cross-checking method and apparatus disclosed in the related parent application, namely U.S. patent application Ser. No. 07/650,791, entitled &#34;On-The-Fly Error Correction with Embedded Digital Controller&#34; now U.S. Pat. No. 5,241,546, the disclosure of which is incorporated herein by reference, (hereinafter referred to as &#34;the referenced patent&#34;). 
     As disk drive areal densities increase, the goal of maintaining low data error rates becomes more difficult. At the same time, increased data throughput rates have led to on-the-fly error correction processes. The use of a 112 bit single and double burst Reed-Solomon on-the-fly error correction code techniques, as described in the referenced patent application, remains a presently preferred manner for detecting and correcting such error bursts. 
     In an on-the-fly error correction processing environment, once an error condition is detected within a data block, the error correction code remainder bytes, and the cross-check remainder bytes, for that block as obtained by the ECC and cross-check hardware, are latched, and are transferred to an ECC-tasked on-board microcontroller. The block having the detected data error condition is transferred to a temporary block storage location within an on-board block buffer memory array. The ECC and cross-check hardware receives and processes the next block of data incoming from the disk surface. 
     Simultaneously with the on-going data transfer, the ECC firmware executed by the microcontroller locates and corrects the error or errors and tests the correction with cross-check syndrome bytes which are updated in light of the corrections made to the data bytes. Once the correction process is tentatively completed, a cross-checking process is carried out. If the computational results of the cross-checking process are found to be equal to a reference value, such as zero, the cross-checking process ostensibly determines that the correction is valid, and that a miscorrection has not occurred. Since the cross-check syndrome bytes are based upon a different Reed Solomon generator polynomial than the one employed to generate the ECC syndrome bytes, it is hoped that only proper data corrections will be detected by the cross checking process. Unfortunately, the cross-checking process is susceptible to determination of a correction, whereas a miscorrection has in fact occurred. 
     The possibility of miscorrection is statistically derived and is known as the &#34;miscorrection probability&#34;. A very low miscorrection probability is highly desirable, as miscorrection of erroneous data otherwise results in erroneous data being put out. While a cross-checking process is one known way to determine if a miscorrection has occurred in the ECC process, the cross-checking process may include weaknesses which increase the miscorrection probability. 
     In the prior approaches as disclosed, for example, in the Tenengolts U.S. Pat. No. 4,782,490, and in the referenced patent, the cross-checking algorithms provided two cross check bytes, each of which separately checked for miscorrection within a cross check interleave of each corrected data block. In that prior approach, there were three Reed-Solomon ECC interleaves within each data block and two cross check interleaves (odd data bytes, and even data bytes) within the same data block, with one cross check byte assigned to the odd bytes cross check interleave and the other cross check byte assigned to the even bytes cross check interleave. 
     With the prior eight-bit cross check byte approach, the misdetection probability of the cross-checking methodology was determined to be one out of 256 (or 3.9×10 -3 ). In other words, if the cross-check bytes erroneously became convoluted in such a way that the syndrome becomes zero as a result of a miscorrection, a misdetection occurred; and, that possibility of misdetection existed with a probability of one out of 256. 
     While a misdetection probability of one out of 256 has been deemed to be adequate to confirm proper correction of most error burst patterns, some error burst patterns have been found which require a greater misdetection capability. For example, if a series of error bursts occurred within the same ECC interleave and also within the same cross check interleave (which can happen if the errors occur at multiples of six apart), the possibility of misdetection arises, and a miscorrection may occur which goes undetected by the cross check procedure. The prior cross-checking methodology has been determined to be ineffectual in detecting miscorrection of such error burst patterns. Thus, a hitherto unsolved need has remained for an error detection method and system which extends the probability of detecting miscorrections occurring within an error correction process, such as Reed-Solomon ECC, or other process such as another cyclic error correction code. 
     SUMMARY OF THE INVENTION WITH OBJECTS 
     A general object of the present invention is to provide improved error correction cross-checking methods and apparatus for reducing the probability of misdetecting miscorrections of data error bursts resulting from an error correction process by a factor, which in the preferred example hereof is 256, and in a manner overcoming limitations and drawbacks of the prior art. 
     Another object of the present invention is to provide an error correction cross-checking method which is applied efficiently to the entirety of a data block, rather than to multiple cross-check interleaves of the data block. 
     A further object of the present invention is to provide methods and apparatus for implementing improved detection of error bursts miscorrected by an embedded digital controller executing an error correction firmware or software process wherein the error detection process is accomplished in a manner requiring an efficiently minimized amount of additional hardware logic. 
     A still further object of the present invention is to provide for improved detection of on-the-fly miscorrection of error bursts by an embedded digital controller with minimized additional firmware instructions for implementing the improved cross-checking method. 
     One more object of the present invention is to provide an improved cross checking generator polynomial based upon a 2B(Hex) primitive alpha 1  constant, as follows: ##EQU1## 
     In accordance with principles of the present invention, an improved cross-checking circuit is provided for use within a Reed-Solomon error correction and cross-checking apparatus. The apparatus performs error correction and cross checking upon a data block within an incoming stream of substantially contiguous data blocks flowing from a source to a destination. The apparatus is based upon a distinguished primitive element, alpha=x 5  +x 3  +x+1, of a Galois field (i.e. a finite field) whose elements are represented by residue classes of binary polynomials modulo p(x)=x 8  +x 4  +x 3  +x 2  +1. The distinguished element alpha can be more concisely represented by its coefficients: 101011 (binary) or 2B (hexadecimal). The apparatus includes a microcontroller for supervising the flow of the data blocks and for making calculations related to error corrections, and a Galois field syndrome generator and remainder recovery circuit connected to receive the incoming stream and recover therefrom plural error correction remainder bytes for each ECC interleave and selectively to hold the remainder bytes in a syndrome latch, the remainder bytes being related to syndrome bytes appended to the data block. The generator and remainder recovery circuit includes the Reed-Solomon cross-checking circuit for recovering cross-checking remainder information related to cross check syndrome information in accordance with the polynomial G XC  (x)=x 2  +alpha 134  x+alpha 1 . 
     In one aspect of the invention, the Reed-Solomon cross-checking circuit comprises a first summing junction connected to the incoming data stream, a second summing junction, an alpha 1  multiplier connected to the first and second summing junctions, a first cross-check byte register connected between the first and second summing junctions, a second cross check byte register connected between the alpha 1  multiplier and the second summing junction, the first and second cross check byte registers being connected to the syndrome latch. 
     In another aspect of the present invention, the Reed-Solomon cross-checking circuit further comprises a first multiplexer for switching between the incoming data stream and an output of the first cross check byte register for enabling cross check syndrome remainder bytes to be appended to each data block passing through the cross-checking circuit. 
     In a further aspect of the present invention, the Reed-Solomon cross-checking circuit alpha 1  multiplier circuit implements the following logical operations: 
     Y 0  =X 0  +X 3  +X 5   
     Y 1  =X 0  +X 1  +X 4  +X 6   
     Y 2  =X 1  +X 2  +X 3  +X 7   
     Y 3  =X 0  +X 2  +X 4  +X 5   
     Y 4  =X 1  +X 6   
     Y 5  =X 0  +X 2  +X 7   
     Y 6  =X 1  +X 3   
     Y 7  =X 2  +X 4 , 
     where Y 0  -Y 7  represent eight bit positions of an output of the multiplier circuit and wherein X 0  -X 7  are the eight bit positions of incoming data thereto, and wherein the &#34;+&#34; sign denotes an exclusive-OR logical operation. 
     In a still further aspect of the present invention, the cross check information supplied to the syndrome latch comprises cross check remainder byte values XC 0  and XC 1  and the microcontroller calculates updated cross-check syndrome bytes NXC 0  and NXC 1  in accordance with the relations: 
     NXC 0  -(RXC 1  +RXC 0 )+E1+E2 . . . +E6, and 
     NXC 1  =((RXC 1  ·alpha 1 )+RXC 0 )/alpha 2  +E1·alpha L1  +E2·alpha L2  . . . +E6·alpha L6 , where E1, L1; E2, L2; and, E6, L6 represent up to six separate decoded error (E) and location (L) values in the data block provided by the error correction apparatus and methodology as described in the referenced parent application. 
     In yet another aspect of the present invention the Reed-Solomon cross-checking circuit includes an encoder section and a decoder section for decoding cross-check remainder bytes into updated syndrome bytes in accordance with the relations: 
     NXC 0  =(RXC 1  +RXC 0 )+E1+E2 . . . +E6, and 
     NXC 1  =((RXC 1  ·alpha 1 )+RXC 0 )/alpha 2  +E1·alpha L1  +E2·alpha L2  . . . +E6·alpha L6 , where E1, L1; E2, L2; and, E6, L6 represent up to six separate decoded error (E) and location (L) values in the data block provided by the error correction apparatus and methodology (as described in the referenced parent application employing three ECC interleaves per block with the capability of locating and correcting two errors per interleave). 
     In still one more aspect of the present invention the Reed-Solomon cross-checking circuit encoder section comprises a first summing junction connected to receive the incoming data stream, a second summing junction, an alpha 1  multiplier connected to the first and second summing junctions through a second multiplexer, a first cross check byte register connected between the first and second summing junctions, a second cross check byte register connected between the alpha 1  multiplier and the second summing junction; and, the decoder section comprises a third summing junction connected to receive the incoming data stream and to an output of the alpha 1  multiplier, a first cross-check syndrome register for holding the value SXC 1  and connected to the third summing junction and to the first multiplexer and also connected to the syndrome latch, and a fourth summing junction connected to receive the incoming data stream and connected to a second cross-check syndrome register having an output feeding directly back to the fourth summing junction holding said value SXC 0  and also connected to the syndrome latch, and wherein the microcontroller is programmed to test the values SXC 0  and SXC 1  against zero, the second multiplexer being switched between the encoder section and the decoder section in accordance with encoding and decoding operations. 
     In another facet of the present invention, a method is provided for cross-checking the correctness of a correction made to a data block by an error correction process, wherein the error correction process divides data bytes of the data block into a plurality of interleave segments. The method comprises the steps of: 
     a. developing a plurality of cross-check bytes based upon all of the data bytes comprising the data block without respect to the interleave segments, in accordance with a predetermined cross check algorithm, and appending the developed plurality of cross-check bytes to the data block, 
     b. developing at least one error correction byte based upon the data bytes and any cross-check byte within each interleave segment, and appending the developed error correction bytes to the data block, 
     c. passing the data block including appended cross-check bytes and error correction bytes through a potentially degrading data transfer medium, such as magnetic data storage disk, 
     d. recovering the data block including recovering the cross-check bytes and error correction bytes from the data transfer medium, 
     e. converting the recovered cross-check bytes into cross-check syndrome bytes, 
     f. processing the recovered error correction bytes to determine if error is present in the recovered data block, 
     g. locating and correcting an error or errors determined to be present in the particular interleave segment of the recovered data block by reference to at least one of the recovered error correction bytes developed within the segment, 
     h. updating the cross-check syndrome bytes by reference to correction of the error determined to be present, and 
     i. testing the updated cross-check syndrome bytes to see if each of them is equal to a predetermined value such as zero, thereby to cross check the correctness of the correction step. 
     As one aspect of this facet of the invention, the error correction process comprises a Reed-Solomon error correction process for performing error correction upon the data block using digital logic apparatus based upon a distinguished element alpha (2B(Hex))=x 5  +x 3  +x+1 of a Galois field whose elements are represented by residue classes of binary polynomials modulo p(x)=x 8  +x 4  +x 3  +x 2  +1, and wherein the predetermined cross-checking algorithm comprises a Reed-Solomon cross-checking code in accordance with the polynomial GXC(x)=x 2  +alpha 134  x+alpha 1 . 
     As another aspect of this facet of the invention, the alpha 134  multiplier term is carried out by implementing the following alpha 1  multiplier: 
     Y 0  =X 0  +X 3  +X 5   
     Y 1  =X 0  +X 1  +X 4  +X 6   
     Y 2  =X 1  +X 2  +X 3  +X 7   
     Y 3  =X 0  +X 2  +X 4  +X 5   
     Y 4  =X 1  +X 6   
     Y 5  =X 0  +X 2  +X 7   
     Y 6  =X 1  +X 3   
     Y 7  =X 2  +X 4   
     and then XORing the resultant product with x, where Y 0  -Y 7  represent eight bit positions of an output of a multiplier for performing the alpha 1  multiplication term of the Reed-Solomon cross-checking code polynomial, and wherein X 0  -X 7  are the eight bit positions of incoming data thereto, and wherein the &#34;+&#34; sign denotes an exclusive-OR logical operation. With this simplified, logic-reduced approach, the alpha 134  multiplier performs these operations: 
     Y 0  =X 3  +X 5   
     Y 1  =X 0  +X 4  +X 6   
     Y 2  =X 1  +X 3  +X 7   
     Y 3  =X 0  +X 2  +X 3  +X 4  +X 5   
     Y 4  =X 1  +X 4  +X 6   
     Y 5  =X 0  +X 2  +X 5  +X 7   
     Y 6  =X 1  +X 3  +X 6   
     Y 7  =X 2  +X 4  +X 7   
     and, this approach saves as many as 18 additional exclusive-OR gates in the implementing logic circuitry which would otherwise be required to implement the alpha 134  multiplier directly. 
     As a further aspect of this facet of the invention, the data transfer medium comprises a data storage disk of a fixed disk drive. 
    
    
     These and other objects, aspects, advantages and features of the present invention will be more fully understood and appreciated by those skilled in the art upon consideration of the following detailed description of preferred embodiments, presented in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the Drawings: 
     FIG. 1 is a series of graphs of a data block including a field of 512 user data bytes, followed by two cross-check bytes, followed by 12 error correction bytes. In this example, the field is divided into three error correction interleaves IL1, IL2 and IL3, and in accordance with the present invention, a single cross-check interleave including the entire user data field. 
     FIG. 2 is one presently preferred embodiment of a block diagram of an encoder/decoder for appending and recovering cross check bytes from the FIG. 1 data block, in accordance with principles of the present invention. 
     FIG. 3 is a second presently preferred embodiment of a block diagram of an encoder and a separate decoder for appending, and recovering cross-check bytes and calculating cross-check syndrome remainders from the recovered bytes, in accordance with principles of the present invention. 
     FIG. 4 is a detailed block diagram of an error correction syndrome encoder and decoder circuit incorporating the FIG. 2 or FIG. 3 cross-check encoder/decoder of the present invention. 
     FIG. 5 is a more generalized block diagram of a data sequencer within a hard disk drive incorporating the FIG. 4 ECC circuit and a cross-check encoder/decoder in accordance with the present invention. 
     FIG. 6 is an architectural block diagram of a hard disk drive including the FIG. 4 ECC circuit and FIG. 5 sequencer. 
     FIG. 7 is a simplified block diagram of the error correction and cross-check apparatus within the FIG. 6 hard disk drive architecture. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The following description employs terms and reference numerals which are chosen to be consistent insofar as practical with the reference numerals for the same structural elements appearing in the referenced patent. Thus, the following explanation should be construed in light of the disclosure of the referenced patent. 
     With reference to FIG. 1, an exemplary data block of 526 bytes includes e.g. 512 user data bytes d[1]-d[512], two cross-check remainder bytes XC 0  [513] and XC 1  [514] and twelve ECC remainder bytes ec[515]-ec[526]. In the FIG. 1 example, the 526 bytes of the data block are arranged into three error correction interleaves: interleave ecclL1 which includes data bytes [1], [4], [7] . . . , cross check byte XC 1  [514], and ECC remainder bytes ec[517], [520], [523], and [526]; interleave ecclL2 which includes data bytes [2], [5], [8] . . . , ECC bytes [515]. [518], [521], and [524]; and interleave ecclL3 which includes data bytes [3], [6], [9] . . . , cross check byte XC 0  [513], and ECC bytes [516], [519], [522], and [525]. Each of the three interleaves is encoded with four ECC remainder bytes. 
     As illustrated in FIG. 1, in accordance with the present invention, the two cross check bytes XC 0  and XC 1  are derived from a single cross check &#34;interleave&#34; including all 512 data bytes. While the cross check bytes are based only upon the 512 byte user data field, the four ECC bytes for the first and third ECC interleaves ecclL1 and ecclL3 respectively take into account the cross check remainder bytes XC 1  and XC 0 , so that any burst errors including the cross check bytes may also be detected and corrected by the ECC process as described in the referenced patent. 
     Turning now to FIG. 2, an improved cross-check remainder byte encoder/decoder circuit 11 is shown. In this figure, reference numerals of elements described in the referenced patent are continued for the same structural elements, to aid in clarity of understanding and to avoid unnecessary repetition in the description. In the referenced parent application, the alpha 1  constant is equal to 2B(HEX). Also, in the referenced patent, the cross check algorithm is: 
     
         G.sub.xc (x)-x.sup.2 +alpha.sup.1.                         (24) 
    
     The new and improved cross check algorithm implemented by the configuration of the FIG. 2 encoder/decoder circuit 11 is: ##EQU2## This new algorithm is based upon the same 2B(Hex) primitive alpha 1  constant, and has been discovered to be significantly more powerful in checking the entire data field of each data block, thereby extending the miscorrection detection probability to one in 256 2  (or 1.5×10 -5 ). Advantageously, as explained above, the alpha 134  term may be reduced to (1+alpha 1 ). 
     Since the alpha 1  multiplier 86 is already present (see FIGS. 2 and 3), it is not necessary to implement separately an alpha 134  multiplier in order to realize circuitry implementing this improved cross check algorithm. By not having to implement separately the alpha 134  multiplier, as many as 18 additional exclusive-OR gates are thereby rendered unnecessary, leading to a streamlined cross-check circuit implementation. 
     In the FIG. 2 cross-checking encoder/decoder circuit 11, data from a buffer (during writing) enters a first byte-wide summing circuit 85 via an ECC data in bus 16. An output bus 17 from the summing circuit 85 enters an alpha 1  multiplier 86. The alpha 1  multiplier 86 provides an output to a first cross check register 90a and also directly to a second byte-wide summing circuit 89, which receives other inputs from the bus 17 and from the register 90a. An output 91 from the second summing circuit 89 feeds into a second cross check byte register 90b. The second cross check byte register 90b has an output bus 96 which feeds into the first summing circuit 85 and also into a multiplexer 97 which functions to append the two cross check bytes XC 0  and XC 1  onto the outgoing data block in byte positions [513] and [514] as shown in FIG. 1. These cross check bytes XC 0  and XC 1  are respectively contained in registers 90A and 90B after the occurrence of 512 successive data byte clock periods of a particular data block. 
     At other times, the multiplexer 97 passes the data bytes [1] through [512] which also pass through the error correction circuit 10 described in the referenced patent in order that the 12 ECC remainder bytes may also be generated and appended in byte positions [515] through [526] of the data block. 
     The alpha 1  multiplier 86 shown in FIG. 2 is implemented in accordance with the following series of relationships, implemented with e.g. 16 exclusive-OR gates, as follows: 
     Y 0  =X 0  +X 3  +X 5   
     Y 1  =X 0  +X 1  +X 4  +X 6   
     Y 2  =X 1  +X 2  +X 3  +X 7   
     Y 3  =X 0  +X 2  +X 4  +X 5   
     Y 4  =X 1  +X 6   
     Y 5  =X 0  +X 2  +X 7   
     Y 6  =X 1  +X 3   
     Y 7  =X 2  +X 4   
     where Y 0  -Y 7  represent the eight bit positions of the output of the multiplier 86 and wherein X 0  -X 7  are the eight bit positions of incoming data thereto. (In the foregoing table of equations, and throughout this specification, unless otherwise indicated, the &#34;+&#34; sign denotes an exclusive-OR operation.) 
     During decoding, the circuit 11 recovers cross-check remainder bytes RXC 0  and RXC 1  of an incoming data block on the bus 16, see FIG. 4. After 514 byte clock periods for the incoming block, the RXC 0  and RXC 1  remainder bytes are located respectively in the registers 90A and 90B. If an error in this particular block has been detected as explained in the referenced parent application, the cross-check remainder bytes RXC 0  and RXC 1  are latched into a syndrome latch 68 and are transferred to cross check buffer registers of a microcontroller 196 via the syndrome latch bus 82. In the meanwhile, the 512 user data bytes of this particular block, including the byte or bytes in error, are transferred to a block buffer 214 (FIG. 6) to which the microcontroller 196 has direct memory access. The microcontroller 196 then commences execution of an error correction and cross check process while the next data block is being processed by the error correction hardware circuitry, so that at this stage, the error correction process is carried out &#34;on-the-fly&#34;. 
     During execution of the error correction process, the particular data block having the error or errors (512 user bytes only) has been transferred to the block buffer memory 214 and temporarily stored at a known block address therein. The microcontroller 196 has direct memory access to each byte location to each byte being temporarily stored in this memory, so that corrected bytes may be substituted for erroneous bytes at error locations in the block. At the same time, the two cross check remainder bytes RXC0 and RXC1 and twelve ECC remainder bytes are transferred from the latch 68 to ECC buffer registers of the microcontroller 196, so that it may determine which interleave(s) contain one or more burst errors. 
     In executing the ECC process firmware routines, the microcontroller 196 calculates a first error value E1 and its corresponding location L1 within the particular data block, and thereupon updates the cross check syndrome bytes NXC 0  and NXC 1  in function of the error value E1 in accordance with equations (24c) and (24d) given hereinbelow. For a single burst error condition within each ECC interleave, once the cross check remainder bytes are processed into cross-check syndrome bytes they are checked to be equal to zero. If the cross-check syndrome bytes are zero, the block is deemed corrected, and is sent out from the temporary storage buffer to the host computing system. If either cross-check syndrome byte is not zero, an uncorrectable error condition is flagged. 
     In the case of detected multiple error bursts within at least one interleave of the particular block, a re-read of the data block is carried out on the next revolution of the disk. If the error condition persists, the computation of error values E and locations L, and update of the cross check bytes, is made iteratively on an error burst by error burst basis. After the last user data byte correction and cross check byte update is completed, the updated cross check bytes are tested to be equal to zero. If they are zero, the data is transferred from the buffer. If either cross check byte is not zero, an uncorrectable error condition is flagged. 
     If an error location is determined to be in a cross check byte location, or in an ECC byte location, and there is no corresponding error located within the user data field of 512 bytes, the error is ignored, and the data block is transferred from the buffer. 
     If an error occurs in the data, and a second error occurs in one or both cross check bytes, the iterative process of updating the cross check syndrome bytes automatically corrects them, and when the updating process based upon correction of user data bytes is completed, the updated cross-check syndrome bytes are tested to be zero. If they are zero, the data block is transferred from the buffer. If either updated cross check syndrome byte is not zero, an uncorrectable error is flagged. No correction is made to the ECC bytes. 
     As a generalized proposition, the calculation of the updated cross check bytes NXC i  is carried out in accordance with the generalized relation for the cross-check syndrome, as follows: 
     
         NXC.sub.i =(RXC1·alpha.sup.i +RXC.sub.0)/alpha.sup.2i + . . . E1·alpha.sup.iLi                                 (24b) 
    
     As a further explanation of the preferred method for obtaining updated syndrome cross check bytes NXC 0  and NXC 1 , a sequence of instructions included within firmware controlling the microcontroller is executed. A presently preferred process sequence is as follows: 
     1. Obtain cross check remainder bytes RXC 0  and RXC 1  from the syndrome latch array 68 via the syndrome data bus 82. 
     2. Perform the error correction by generating error correction values E1, E2, . . . E6, and associated location values L1, L2, . . . L6. 
     3. Compute the updated cross check syndrome byte NXC 0  in accordance with the following algorithm: 
     
         NXC.sub.0 =(RXC.sub.1 +RXC.sub.0)+E1+E2 . . . +E6.         (24c) 
    
     If the cross check syndrome byte NXC 0  is not equal to zero, then flag a miscorrection. Otherwise, proceed to step 4. 
     4. Compute cross check syndrome byte NXC 1  in accordance with the following algorithm: 
     
         NXC.sub.1 =(RXC1·alpha.sup.1 +RXC.sub.0)/alpha.sup.2 +E1·alpha.sup.L1 +E2·alpha.sup.L2 . . . +E6·alpha.sup.L6.                                (24d) 
    
     If the updated cross check byte NXC 1  is not equal to zero, then flag a miscorrection. Otherwise, the error correction process has functioned properly in locating and correcting the error burst(s) within a misdetection probability of one out of 256 2 , the data block is transferred from the temporary buffer block storage location, and the overall error correction firmware process is reset to await detection of an error condition in a subsequent data block. 
     A series of firmware routines and Galois field log and antilog lookup tables used to carry out the calculations and data manipulations associated with the FIG. 2 embodiment are set forth below. This firmware is developed for execution upon an NEC 78322 16 bit microcontroller core, or equivalent. 
     A potential drawback of the circuit 11 depicted in FIG. 2 is that the processing time required by the microcontroller 196 to calculate the updated cross check syndrome bytes NXC 0  and NXC 1  may prove to be excessive under some on-the-fly data handing conditions or in some hardware examples or implementations. If the calculational time proves to be excessive in a particular application, the circuit depicted in FIG. 3 may be used. 
     The FIG. 3 circuit includes a separate encoder 11a for encoding and appending the check bytes to the data stream during data writing operations, and a separate decoder 11b for decoding the syndrome bytes SXC 0  and SXC 1  from the data stream being played back during data readback operations. The encoder 11a is essentially identical to the encoder 11 depicted in FIG. 2, and the description thereof will not be repeated. The decoder 11b advantageously makes use of the alpha 1  multiplier 86 found within the encoder 11. A multiplexer 99 enables the multiplier 86 to be switched into the decoder circuit 11b during playback operations. 
     During playback, the ECC Data in is received into the decoder section 11b via a bus 16&#39; and immediately enters a byte-wide summing junction 98. An output from the summing junction 98 leads to a cross check syndrome register 101 which recovers directly the cross-check syndrome byte SXC 1 . An output path 105 from the register 101 leads into the syndrome latch 68. 
     The incoming data stream also enters another summing junction 107 which provides an output to a second cross check syndrome register 109 having an output path 111 feeding back to the summing junction 107. The syndrome register 109 recovers directly a cross-check syndrome byte SXC 0 . An output path 113 likewise leads from the register 109 into the syndrome latch 68. The latched cross-check syndrome bytes SXC 1  and SXC 0  are then iteratively updated by the microcontroller 196 and then tested to be equal to zero, or not, in accordance with the following relations: 
     
         NXC.sub.0 =SXC.sub.0 +E1+E2 . . . +E.sub.i =0              (24e) 
    
     
         and 
    
     
         NXC.sub.1 =SXC.sub.1 +E1·alpha.sup.L1 +E2·alpha.sup.L2 . . . +Ei·alpha.sup.Li =0.                         (24f) 
    
     where i is equal to a maximum of 6 error bursts in the implementation of the parent application, SXC 0  =(RXC 1  +RXC 0 )/alpha 0 , (or RXC 1  +RXC 0 ), and SXC 1  =(RXC 1  alpha 1  +RXC 0 )/alpha 2 . 
     Thus, it will be appreciated by those skilled in the art that the decoder circuitry 11b fully implements in hardware the cross-check syndrome equations (24c) and (24d) above, thereby freeing the microcontroller 196 and its firmware for performance of other, more important tasks. 
     In the second implementation of FIG. 3, the microcontroller 196 performs steps 1 and 2 as in the FIG. 2 implementation above, and then updates SXC 0  and SXC 1  in accordance with equations (24e) and (24f). After all update operations are completed, the updated cross-check syndrome bytes NXC 0  and NXC 1  are tested to be zero. If each updated cross check syndrome byte equals zero, a miscorrection is not present, as determined to be within a misdetection probability of one out of 256 2 . If one of the updated cross check bytes is not equal to zero, the firmware flags other processes controlled by the microcontroller 196 in order to flag detection of a miscorrection. 
     When an ECC error occurs, the ECC firmware process checks to see if the error is correctable on the fly, as in accordance with the teachings of the referenced parent application. With the state of present microcontroller technology, this process takes about 200 microseconds, or less. If the detected error burst is correctable on-the-fly, the error is corrected, and checked, and then the data is transferred to a target location, such as a host computing system with which a disk drive employing the ECC method is operatively associated. If the data proves not to be correctable on-the-fly, the data block is re-read, e.g. for up to eight times, in an attempt to read the data correctly without applying a double burst ECC correction process. Before invoking the more complex double burst ECC algorithm, the ECC firmware process will always try to recover from an error by attempting to re-read the data correctly. This strategy prevents invoking double burst correction processes resulting from &#34;soft&#34; or non-repeating data errors. Each time a block in error is re-read a set of ECC remainders is computed. If all of the remainders equal zero, the data was read with no errors, and the block is transferred to its target location. If any of the syndrome values do not equal zero, an error has occurred, the syndrome remainder bytes, and cross check bytes are captured in, and retrieved from the syndrome latch 68, and another re-read is invoked. 
     When the sets of syndromes from two consecutive re-reads are the same, a &#34;stable syndrome&#34; has been acquired. This event may automatically trigger execution of the double error burst correction algorithm, and may lead to other actions such as defect management within the overall disk drive internal operating system. 
     Turning now to FIG. 5, it is to be seen that the ECC syndrome generator circuit 10 is but one functional element within a data sequencer 100 of an overall disk drive architecture 160, shown in FIG. 6. The data sequencer 100 includes, in pertinent part, a run length limited encoder/decoder (ENDEC) 104 which encodes and decodes serial data into and from e.g. a 1, 7 run length limited (RLL) code, and a serializer/deserializer (SERDES) 106 which bundles and unbundles data bytes into and from serial-by-bit data format. A FIFO byte register 108 enables data bytes to be asynchronously transferred between the sequencer 100 and an external cache buffer memory array 214. A multiplexer 110 regulates bidirectional data flow through the SERDES 106 and ENDEC 104, so that ECC syndrome bytes generated by the ECC generator (including the two cross-check bytes generated by the cross-check generator 11) may be appended to data blocks flowing to a selected data storage surface of a rotating data storage disk 162, shown in FIG. 6. Operation of the remainder of the sequencer circuitry not directly related to the ECC process is described in the referenced patent. 
     Referring to FIG. 6, a fixed disk drive data storage subsystem 160 includes at least one rotating data storage disk 162 which is rotated at a constant rotational velocity by a spindle motor 164. The spindle motor is controlled by a motor driver circuit 166 operating under the control of a motor control circuit 168. The data storage disk includes a plurality of embedded servo sectors S, and these sectors provide information for spindle motor speed control, and for positioning data transducer heads 170A and 170B relative to concentric data storage tracks on storage surfaces of the disk 162. An arm assembly 171 supporting the data transducer heads 170A and 170B is actuated by a mass balanced rotary voice coil actuator 172, so that the heads 170 fly in close proximity to the rotating disk 162 upon an air bearing. A coil of the actuator 172 is driven by a servo driver circuit 174 which develops bidirectional driving currents in response from pulses received from a low pass filter 176. The filter 176 is connected to a servo pulse width modulator circuit 178 within a servo control circuit 180. Servo pulses which are shaped by a pulse detector 184 and peak detected by a peak detector 192 are converted into digital values in an analog to digital converter 194 and delivered directly to the microcontroller 196. Coarse head position information read by the head 170 from the embedded servo sectors S is directly decoded by the servo control circuit 180 independent of the PLL 188, ENDEC 104 and sequencer 100. 
     Each data transducer head 170A and 170B is selected by head select circuitry within a preamplifier/head select/write driver circuit 182. The recovered analog data is then passed through a pulse detector 184 which transforms the analog flux transitions into digital logic edges in conventional fashion. A write precompensation circuit 186 precompensates data to be written to the disk which has been received from the sequencer 100. The phase locked loop circuit 188 operates to separate the digital edges into data bit pairs (encoded data) and delivers those data bit pairs to the ENDEC 104. A frequency synthesizer 190 enables a variety of reference frequencies to be synthesized in order to provide for zoned bit recording. 
     A microcontroller address/data/control bus 198 extend to a microcontroller interface 202 which directly communicates with the sequencer 100, ENDEC 104, motor controller 168, servo control circuit 180 and a buffer memory controller 210, these circuits being preferably included in a very large scale integrated circuit. The buffer memory controller 210 generates buffer addresses and supplies them to address the buffer memory 214. Data blocks are transferred to and from the FIFO register 108 within the sequencer 100 and the buffer memory 214 via a buffer data bus 216. This bus 216 also extends to an interface control circuit 218 which receives data blocks and command values via an interface bus 220 connected to a host system, and stores the values and blocks in the memory 214, and which returns status values and data blocks from the memory via the interface bus 220 to the host. A direct memory access path exists between the microcontroller 196 and the buffer memory 214 via the micro interface 202 and the buffer controller 210. With this path, it is practical for the microcontroller 196 to access particular byte locations of the buffer memory to withdraw an erroneous byte from an error location, XOR the correction value with the erroneous byte, and write a resultant value to the error location thereby to replace the erroneous value, in order to implement an on-the-fly error correction method. 
     Thus, in FIG. 7, the error correction process is essentially seen to include the error correction circuit 10, the cross-check circuit 11, the latch 68, the programmed microcontroller 196 operating in accordance with resident ECC firmware 197, the buffer controller 210, and the buffer memory 214 which lies in a bidirectional data path extending between a host computer 230 and a data-degrading storage medium, such as the data storage disk 162. During flow of data blocks from the host computer 230 to the disk 162, the ECC circuit 10 and cross-check circuit 11 calculate error correction remainder bytes and cross check bytes upon each incoming data block. In accordance with the present invention, each of the two cross-check bytes covers the entire data field, and the error correction remainder bytes cover three interleaves of the data field, as well as the cross-check bytes. 
     During reverse flow, i.e. from the disk 162 to the host 230, the cross-check bytes, and error correction remainder bytes are recovered. The error correction remainder bytes are tested in the zero compare circuit 78 to detect if one or more errors are present. If so, the error correction remainder bytes and the recovered cross-check bytes are latched into the latch 68 and passed onto the microcontroller 196. The error location and a correction value are determined, and the effect of the correction value is tested upon the cross-check bytes to detect whether a miscorrection has occurred. If not, the correction value is XORed with the erroneous byte, and the result is substituted for the error within the block in the buffer memory 214. The corrected block is then ready to be passed to the host. If so, the error correction process is retried or halted, and the host is then signalled that the block includes an uncorrectable error condition. 
     Here follows a listing of program routines for carrying out the method steps described hereinabove in conjunction with the FIG. 2 embodiment, together with a Galois field log table, and Galois field antilog table. ##SPC1## 
     Having thus described embodiments of the invention, it will now be appreciated that the objects of this invention have been fully achieved, and it will be understood by those skilled in the art that many changes in construction and widely varying embodiments and applications of the invention will suggest themselves without departing from the spirit and scope of the invention. The disclosures and the description herein are purely illustrative and are not intended to be in any sense limiting.