Solenoid drive circuit
This is a continuation-in-part of application Ser. No. 07/994,937 filed on Dec. 22, 1994, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     A. Field of Invention 
     The present invention relates generally to driver circuits and more particularly to a new and improved circuit used to drive a solenoid coil. 
     B. Description of Related art 
     When operating a solenoid coil, for example as a valve actuator, power consumption can be a concern, particularly when high power consumption causes coil heating. When multiple solenoid actuated valves are grouped and required to have high speed operation capability, it is desirable to reduce power consumption while not reducing the voltage necessary for high speed coil excitation. Circuitry has been designed to cause the voltage directed to the coil to include an initial high voltage &#34;spike&#34; followed by a lower &#34;hold&#34; voltage. Such circuitry is designed to initiate rapid excitation of the solenoid with the voltage spike and maintain the excitation of the solenoid with the lower voltage, hold portion of the signal. In this way, the relatively high voltage necessary to quickly and efficiently operate a solenoid coil is not continued during the portion of the operation cycle when high voltage is not required to maintain the solenoid in operation. 
     FIG. 1 represents a prior art solenoid coil drive circuit that utilizes a spike and hold method of operating a solenoid. The spike and hold method activates the solenoid with a high voltage spike (usually two or three times the rated voltage of the coil) for only long enough to switch the position of the solenoid armature. The input voltage is reduced to a holding voltage (usually about one half the rated coil voltage) for the remainder of the on cycle. By using a lower voltage to hold the solenoid armature in the &#34;on&#34; position, less power is used when operating the solenoid. The wave forms in FIGS. 2a and 2b represent a common input signal and the resulting voltage across the solenoid coil generated by the conventional spike and hold circuit such as diagramed in FIG. 1. A square wave signal is applied to the control signal input terminals. When the control signal is high, a transistor (Q4 in FIG. 1) is turned on which allows current to flow through the solenoid coil. Another transistor (Q1 in FIG. 1) is coupled to the control signal input terminal through a capacitor (C2 in FIG. 1) and a resistor (R2 in FIG. 1) and is momentarily turned on at the rising edge of the control signal. This initiates a timer circuit to output a pulse of a duration that is determined by the combination of a resistor (R1 in FIG. 1) and a capacitor (C1 in FIG. 1). The output pulse from the timer circuit turns on two other transistors (Q2 and Q3 in FIG. 1) which allow voltage (V1) to be applied to the coil. Diode D1 isolates voltage V2 from V1 when V1 is applied to the coil. When the timer circuit output pulse terminates, transistors Q2 and Q3 turn off. This isolates voltage V1 from the solenoid coil and allows a second voltage (V2) to be applied to the coil. The voltage V2 represents the lower holding voltage and will continue to hold the solenoid armature in the &#34;on&#34; position until the control voltage is removed from the control signal terminals. This turns off transistor Q4 which prevents current from flowing though the coil. 
     The circuit in FIG. 1 requires at least two different voltage levels (V1, V2, and possible a third level for the timer) as well as a control signal input. Extensive circuitry is necessary to insure correct timing sequences between the timer and the transistor as well as to isolate the different voltage levels during activation of the solenoid coil. 
     SUMMARY OF THE INVENTION 
     The present invention is a drive-circuit specifically designed for the operation of a solenoid. The drive circuit consists of a timing circuit, a variable voltage regulator, and a voltage control circuit. Timing circuit comprises a first resistor and capacitor connected in parallel to each other with a second resistor serially connected to the resistor-capacitor circuit between said resistor-capacitor circuit and the input voltage source such that after charging the first capacitor, the first and second resistors split the voltage and a connection is made to the voltage control circuit between the resistor-capacitor circuit and the second resistor. The variable voltage regulator has an input-terminal, an output-terminal, and an adjustment terminal and may be one of several commercially available regulators. The input terminal of the voltage regulator and the second resistor are connected to a voltage source from which to receive a control signal as an essentially rectangular wave or a voltage level that is effective for the desired operation and rapid excitation of the device to be driven. The variable voltage regulator comprises means for adjusting the voltage at the output terminal in response to variations in the voltage at the adjustment terminal. The voltage control circuit is a means for changing the voltage at the voltage regulator adjustment terminal in response to activation by the timing circuit. Specifically, the voltage control circuit comprises a third resistor connected to the output terminal of the voltage regulator and serially connected to two additional resistors that are parallel to each other. The adjustment terminal is connected to the voltage control circuit between the third resistor and the parallel pair of fourth and fifth resistors. Between the fourth resistor and ground is interposed a field effect transistor the gate of which is connected to the timing circuit between the second resistor and the resistor-capacitor pair. The source of the field effect transistor is grounded and the drain of the field effect transistor is connected to the fourth resistor. In operation, while the capacitor is charging, the field effect transistor is open, taking out the fourth resistor, and accordingly the voltage at the adjustment terminal of the voltage regulator is controlled by the voltage derived from the third resistor and the fifth resistor. On charging of the first capacitor in the timing circuit, the voltage at the base of the field effect transistor reaches a level sufficient to close the transistor. As the transistor closes, the voltage at the adjustment terminal of the voltage regulator is changed to the voltage derived from the third resistor and the equivalent resistance of the now parallel fourth and fifth resistors. The effect of the change to the equivalent resistance is to reduce the voltage at the adjustment terminal thereby causing the voltage regulator to reduce the voltage at its output terminal to which the device to be driven is connected. A second capacitor may be also connected between the voltage source and ground and a diode is connected parallel to the solenoid coil. 
     Since the voltage of the control signal is in inverse proportion to the charging time of the first capacitor, the change in duration of the &#34;spike&#34; portion of the output voltage approximates the wave form needed for efficient operation of the solenoid coil (i.e. shorter duration for higher voltage). The impedance of the fourth and fifth resistors may be varied to control the amount of reduction of the output voltage after activation of the field effect transistor by the timing circuit thus adjusting the &#34;holding&#34; voltage level. 
     The circuit presented in FIG. 3 offers several advantages over the prior art as exemplified by the circuit in FIG. 1. First, the present circuit has the advantage of operating solely from a single input control signal and no other additional voltage inputs are necessary. Second, the resistor-capacitor timer circuit of the present invention also has the advantage of being input voltage dependant in that the duration of the spike voltage is inversely proportional to the input voltage. Thus if higher voltages are applied the duration of the spike voltage decreases. Since solenoid coils respond faster as higher voltages are applied to their coils, only a shorter spike pulse duration is required at higher input voltages. By shortening the spike duration for higher input voltages, power consumption is minimized. The holding voltage which is applied to maintain the solenoid in operation after the spike voltage initiates the movement of the solenoid armature is constant and unaffected by the input voltage level. These features offer the flexibility of using the circuit over a wide range of input voltages. The driver circuit of the present invention requires fewer components being thus more economical to manufacture and maintain. The driver circuit of the present invention consumes power only when the solenoid is being energized while, the prior art circuit in FIG. 1 has power continually applied to the timer circuit which consumes power whether the solenoid is energized or not. 
     The principal aim of the present invention is to provide a new and improved drive circuit for the efficient operation of a solenoid coil. 
     Another and further object and aim of the present invention is to provide a new and improved drive circuit for the operation of a solenoid coil with a rapid activation time and relatively low power consumption and coil heat generation. 
     Other objects and advantages of the invention will become apparent from the Description of the Preferred Embodiments and the Drawings and will be in part pointed out in more detail hereinafter. 
     The invention consists in the features of construction, combination of elements and arrangement of parts exemplified in the construction hereinafter described and the scope of the invention will be indicated in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a conventional spike and hold circuit according to the prior art. 
     FIG. 2(a) is a graph showing the wave form of the control signal used to activate the prior art circuit depicted in FIG. 1.; FIG. 2(b) is a graph depicting the wave form of voltage produced by the prior art circuit depicted in FIG. 1. 
     FIG. 3 is a schematic diagram of a drive-circuit in accordance with the present invention. 
     FIG. 4(a) is a graph depicting the wave form of the voltage signal into the circuit depicted in FIG. 3; FIG.4(b) is a graph depicting the wave form of voltage produced by the circuit depicted in FIG. 3 in response to the signal depicted in FIG. 4(a). 
     FIG. 5A is a graph showing three different signals and FIG. 5B is a graph showing the voltage wave forms produced by the circuit depicted in FIG. 3 in response to said signals superimposed upon each other. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT(S) 
     With reference to the drawings wherein like numerals represent like parts throughout the Figures, a solenoid driver circuit in accordance with the present invention is generally designated by numeral 10 in FIG. 3. A first end of the solenoid coil 12 is connected to a output voltage terminal 14 and the second end is connected to a ground terminal 16. A switching diode 18 is connected in parallel with the solenoid coil 12. A voltage regulator 20 has an output pin 22 connected to the output voltage terminal 14, an input pin 24 connected to the input voltage terminal 26, and an adjustment pin 28 connected to resistors 30, 32 and 34. Resistor 30 has its first end connected to the output pin 22 of the voltage regulator 20 and the second end of resistor 30 is connected to the adjustment pin 28 of said regulator 20. Resistor 32 has its first end connected to the adjustment pin of said voltage regulator 20 and its second end connected to the ground terminal 16. The first end of resistor 34 is connected to the adjustment pin 28 of said voltage regulator 20 and the second end of resistor 34 is connected to the drain terminal 36 of an N-channel field effect transistor 38. 
     The source terminal 40 of the N-channel field effect transistor 38 is connected to the ground terminal 16. The gate terminal 42 of the N-channel field effect transistor 38 is connected to a timing circuit comprising of two resistors 44 and 46 and a capacitor 48. The first end of resistor 44 is connected to the input voltage terminal 26 and the second end of resistor 44 is connected to the gate terminal 42 of the N-channel field effect transistor 38. The first end of resistor 46 is connected to the gate terminal 42 of the N-channel field effect transistor 38 and the second end of resistor 46 is connected to the ground terminal 16. Capacitor 48 is connected in parallel with resistor 46. The first end of a second capacitor 50 is connected to the input voltage terminal 26 and the second end of capacitor 50 is connected to the ground terminal 16. 
     The wave forms shown in FIG. 4 represent the input voltage to the drive circuit 10 and the resulting voltage at the output terminal of the circuit 10 which is the same as the voltage across the solenoid coil 12. Applying a voltage of a sufficient level to energize the solenoid 12 to the input voltage terminal 26 causes an initial output voltage to be generated at the output terminal 14 whose level is determined by the resistors 30 and 32. These resistors are of a predetermined value such that the generated output voltage is approximately equal to the input voltage and is sufficient to activate the solenoid. Resistor 34 is isolated from the voltage regulator 20 while the N-channel field effect transistor 38 is in the off state. Applying the voltage to input voltage terminal 26 starts charging the capacitor 48 at a rate determined by the values of Resistors 44 and 46 and timing circuit capacitor 48. When the voltage across timing circuit capacitor 48, which is also the voltage at the gate terminal 42 of the N-channel field effect transistor 38, reaches a predetermined level the N-channel field effect transistor 38 changes to the on state. This rate of charging timing circuit capacitor 48 determines the duration of the higher voltage supplied to the solenoid coil 12 such that the spike is of sufficient duration to activate the solenoid coil 12. When the N-channel field effect transistor 38 turns on, resistor 34 is now in parallel with resistor 32 changing the equivalent resistance connected between the adjustment pin 28 of the voltage regulator 20 and the ground terminal 16. This causes the output voltage to change to a new level determined by the equivalent resistor. The value of resistor 34 is chosen such that the equivalent resistance of resistor 34 in parallel with resistor 32 causes the voltage at the output terminal 24, and hence across the solenoid coil 12, to be much less than the input voltage but sufficient to keep the solenoid coil 12 energized. The output voltage will remain at this `holding` level until the voltage is removed from the input terminal 26. Removing the input voltage causes the output voltage to drop to zero de-energizing the solenoid coil 12 and allows the voltage at the N-channel field effect transistor gate 42 to discharge to zero volts which returns the N-channel field effect transistor 38 back to the off-state. After a predetermined time the capacitor 48 is fully discharged and the circuit is ready to be energized again. This discharge time is dependent on the component values of the timing circuit and the input voltage. 
     As may be expected, there are many variations of values possible for the individual components of drive circuit 10 with corresponding variations in performance. As an exemplar of the performance of the drive circuit 10, FIG. 4(a) and 4(b) depict a typical input voltage and the resulting output voltage produced by a particular configuration of the preferred embodiment of drive circuit 10. Specifically, the output voltage shown in FIG. 4(b) is produced by the drive circuit 10 wherein the voltage regulator 38 is a three terminal adjustable regulator supplied by National Semiconductor Corporation under part number LM317L, which according to the purveyor&#39;s specifications, will produce an output voltage according to the following formula: ##EQU1## wherein R 1  corresponds to Resistor 30 of the drive circuit 10 and R 2  corresponds to the resistance provided by Resistor 32 when field effect transistor 38 is turned off and by the equivalent resistance provided by Resistors 32 and 34 when the field effect transistor 38 is turned on, and I adj  corresponds to the current at the regulator adjustment pin 28, the V out  represents the output voltage at the output pin 22 of regulator 20 and V on the right side of the equation signifies that the units of measure are volts and does not constitute a variable. The specific output voltage depicted in FIG. 4(b) is produced by drive circuit 10 wherein the following components were of the performance characteristics and values as described below: 
     
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COMPONENT          VALUE                                                  
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Resistor 30        240 Ohms                                               
Resistor 32        5.1 Kilo Ohms                                          
Resistor 34        820 Ohms                                               
Resistor 44        1.3 Mega Ohms                                          
Resistor 46        150 Kilo Ohms                                          
Capacitor 48       0.1 micro Farads                                       
Capacitor 50       0.1 micro Farads                                       
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     The drive circuit 10 with the specific values set forth above, by way of further illustration of its performance, produces the variety of wave forms depicted in FIG. 5 in response to a variety of input voltages as shown therein. As such, FIG. 5 exemplifies and graphically shows the inverse relationship of the input voltage level to the duration of high voltage or &#34;spike&#34; portion of the output voltage. As such, the graphs shown in FIGS. 5A and 5B, are idealized representations of the relationship between input voltage and the duration of the spike portion of the output voltage, showing the changes in voltage V on the vertical axis, over time t on the horizontal axis, from the input source in FIG. 5A and at the output pin 22 of regulator 20 in FIG. 5B and are intended solely for the purpose of illustration and not as an expression or representation of particular test data. Typically, with the particular component values recited herein, the duration of the spike portion of the output, shown as &#34;T spike  in FIG. 5B would be expected to be on the order of 50 milliseconds, given an input voltage of 15 volts. The change in duration of the &#34;spike&#34; portion of the graph represents the change in the charging time for the capacitor 48, which delays the turning on of the transistor 38. Accordingly, the vertical edge of each graph in FIG. 5B, at the termination of the output voltages, V Hsp , V Msp , and V Lsp  as T spike, the end of the &#34;Spike&#34;, constitutes the time when capacitor 48 has become fully charged causing the input voltage as divided by resistors 44 and 46 to turn on transistor 38, thereby changing the equivalent resistance of resistors 34 and 32, causing the regulator 20 to drop the output voltage according to the equation discussed above. The specific duration of the &#34;spike&#34; portion of the output voltage can be modified by changing the values of resistors 44 and 46 and capacitor 48. The output voltage level during the &#34;hold&#34; portion of the output signal may be varied by changing the values of resistors 30, 32, and 34 and is not affected by the input voltage level. 
     Although the preferred embodiment for the present invention described above identifies transistor 38 as an N-channel field effect transistor, the circuit of the present invention will perform if other types of transistors or other electronic switching means, specifically including a bipolar junction transistor, are substituted for the field effect transistor as transistor 38. Such substitution would involve connecting the base electrode of the bipolar junction transistor in the same manner as the gate terminal 42 of transistor 38 is connected in the foregoing description. Further, appropriate connections of the other electrodes of a transistor, such as the emitter and collector electrodes of a n-p-n bipolar junction transistor would have to be made in the same manner as the source terminal 40 and drain terminal 36 of the described transistor 38. 
     While preferred embodiments of the foregoing invention have been set forth for purposes of illustration, the foregoing description should not be deemed a limitation of the invention herein. Accordingly, various modifications, adaptations and alternatives may occur to one skilled in the art without departing from the spirit and the scope of the present invention.