Fuse circuitry to control the propagation delay of an IC
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to integrated circuit devices, and more specifically to a fused delay circuit for use in such integrated circuit devices. 
     2. Description of the Prior Art 
     Integrated circuits, especially high speed devices such as EPROMs, microprocessors, gate arrays, and memory devices, are optimally designed to operate as fast as possible. Devices which are marketed as slower version,,; of these high speed devices may or may not be slower, and often retain the high speed characteristics of the fastest device. For this reason, customers often purchase &#34;slower&#34; versions of a high speed device at a discount, and simply characterize and speed-sort the devices to determine which devices are actually &#34;fast&#34;. Such an endeavor can be quite advantageous for the purchaser, due to the high premium price typically charged for the fastest speed grade part. 
     From an engineering perspective, devices branded as slow devices that are actually a fast speed grade can cause difficulties in the circuitry in which they are used. Often devices must meet the electrical parameters required by a slower application. For instance, timing problems can result when the proper hold time and set-up time for a device is not achieved. 
     To date, there have been few feasible methods available to effectively slow down integrated circuits. Mask changes may be used to slow down a fast device by adding additional logic gates or other circuitry to the mask set. Using this method, a new mask set is required for every speed grade of the device. Unfortunately, mask changes also require extensive design time and are therefore costly in terms of time and money expended. For these economical and engineering reasons, it would be desirable in the art to slow down the speed of an integrated circuit with a minimum amount of time, effort, and expense. 
     SUMMARY OF THE INVENTION 
     Therefore, according to the present invention, circuitry provides for the ability to selectively introduce delays into the timing of the integrated circuit, without the expense and time associated with methods used in the prior art. As a minimum, a fuse element having at least one fuse and a transistor element having at least one transistor are placed in parallel to each other between a voltage supply of a gate of the integrated circuit and a corresponding voltage supply of the integrated circuit. When the fuse element is intact, the fuse element provides a relatively low resistance path from the voltage supply of the gate to the corresponding voltage supply of the integrated circuit. However, upon blowing the fuse element, this low resistance path is no longer available. An increased resistance path through the transistor element must be used, and the integrated circuit is slowed down accordingly. The amount of delay introduced to the delay element is a function of the value chosen for the transistors in the transistor element. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
     FIG. 1a is a gate block diagram for slowing an integrated circuit according to the present invention; 
     FIG. 1b is a gate block diagram with multiple delay elements for slowing an integrated circuit according to the present invention; 
     FIG. 2 is inverter circuitry for slowing an integrated circuit according to a first preferred embodiment of the present invention; 
     FIG. 3 is inverter circuitry for slowing an integrated circuit according to a second preferred embodiment of the present invention; and 
     FIG. 4 is inverter circuitry having a pass gate for slowing an integrated circuit according to a third embodiment of the present invention. 
     FIG. 5 is an inverter circuit according to a fourth embodiment of the present invention. 
    
    
     DESCRIPTION OF THE INVENTION 
     High speed integrated circuits, including EPROMs, microprocessors, gate arrays, and memory devices, are optimally designed to function as fast as possible. Because of economical and engineering reasons described in the Description of the Prior Art, it can be quite important to be able to slow down integrated circuits with an inexpensive and reliable means. 
     Referring to FIG. 1a, a gate block diagram 10 for slowing an integrated circuit is shown. Gate 12 can be any logic gate, including a NAND gate, a NOR gate, or an inverter, and has input signal 14 and output signal 16. Fuses F 1  or F 2  may be blown to slow down gate 12. The path to a supply voltage, either V cc  or V ss , has two paths in parallel, through either a fuse or a transistor. For instance, V cc  of gate 12 has a path to the V cc  supply voltage through fuse F 1  or through p-channel transistor T 1 . Both fuse F 1  and transistor T 1  are chosen such that when fuse F 1  is intact, there is an effective short to the V cc  supply voltage. When fuse F 1  is blown, gate 12 experiences an increased resistance to voltage supply V cc  through p-channel transistor T 1 . This increased resistance has the effect of slowing down the device. In a similar fashion, V ss  of gate 12 has a path to the V ss  supply voltage through fuse F 2  or n-channel transistor T 2 . When fuse F 2  is blown, the resultant increased resistance through transistor T 2  slows the device. 
     FIG. 1b shows a gate block diagram 10 for introducing different delay times to an integrated circuit. For slowing down the device in the V cc  direction, two different delays may be introduced. First, when fuse F 1  &#39; is blown, transistor T 1  is in parallel with T 1  &#39; and a delay, which is dependent on the resistance value of transistor T 1  in parallel with transistor T 1  &#39;, is introduced to the device. Second, when both fuse F 1  and F 1  &#39; are blown, a longer delay is introduced because the effective resistance is the resistance of T 1  itself. Therefore, adding a resistive element, in this case T 1  &#39; in series with fuse F 1  and then placing a second fuse F 1  &#39; in parallel with F 1  and T 1  &#39; allows one of two delay times to be introduced to the device. More delay times may be realized by adding additional delay circuitry. In a similar fashion, for delay in the V ss  direction, transistor T 2  &#39; has been added in series with fuse F 2  and fuse F 2  &#39; is placed in parallel to both F 2  and T 2  &#39;. Blowing fuse F 2  &#39; introduces a delay which is a function of the resistance of T 2  in parallel with T 2  &#39;. A longer delay may be obtained by blowing both fuses F 2  and F 2  &#39;; the resultant delay is determined by the resistance of T 2 . Although the resistive portion of the delay circuitry has been shown as transistors T 1 , T 1  &#39;, T 2 , and T 2  &#39;, resistors may be utilized in their place. 
     Referring to FIG. 2, inverter circuitry 20 for slowing an integrated circuit according to a first preferred embodiment of the present invention is shown. The gate 12 of FIG. 1a has been replaced by the inverter defined by p-channel transistor T 2  and n-channel transistor T 3 . When fuses F 1  and F 2  are intact, transistors T 2  and T 3  behave as an inverter. Input signal 22 is inverted and passed through as output signal 24. Input signal 22 is analogous to input signal 14 of FIGS. 1a and 1b while output signal 24 is analogous to output signal 16 of FIGS. 1a and 1b. 
     Transistors T 1  and T 4  are small transistors; the ratio of width to length of these transistors is typically less than the width to length ratio of transistors T 2  and T 3 . The values of transistors T 1  and T 4  are chosen such that when corresponding fuses F 1  or F 2 , respectively, are blown, the resistance of the path of supply voltage V cc  or V ss , respectively, increases substantially, thereby slowing down the integrated circuit device. Typical values of the resistance of transistors T 1  and T 4  may be as much as ten times the value of the resistance of transistors T 2  and T 3 , Since transistors T 1  and T 4  act as resistive elements, they may be replaced with high impedance resistors which may be formed in poly or active regions. Additional transistors and fuses may be added as shown in FIG. 1b to introduce delay times of differing duration. 
     Referring to FIG. 3, inverter circuitry 30 for slowing an integrated circuit according to a second preferred embodiment of the present invention is shown; circuitry 30 reduces the circuitry resistance when the fuses are intact. Input signal 32 and output signal 34 are analogous to input signal 22 and output signal 24, respectively, of FIG. 2. 
     Placing fuses F 1 , F 2 , F 3 , and F 4  in parallel to each other and to transistor T 1  as shown in FIG. 3 reduces the resistance they provide when they are intact. This is also true for fuses F 5 , F 6 , F 7 , and F 8  which are parallel to each other and to transistor T 4 . If the required delay need only be in one voltage direction, either V cc  or V ss , then only one of series transistors T 1  or T 4  provides a path to a supply voltage. In this case, only one of the transistors, T 1  or T 4 , and its associated fuses would need to be layed out in the circuitry of the device. For instance, if a V ss  delay is required, then fuses F 5 , F 6 , F 7 , and F 8  are blown such that transistor T 4  provides a high resistance path to ground, thereby slowing down the device. The fuses of FIG. 3 may be placed in parallel with slew rate limiting resistors of the output driver (not shown) of circuitry 30 in order to adjust for noise levels. This may be accomplished by replacing transistors T 1  and T 4  with resistors R 1  and R 4 . 
     Referring to FIG. 4, inverter circuitry 40, having a pass gate, for slowing an integrated circuit according to a third embodiment of the present invention is shown. Input signal 42 is connected to an inverter comprised of transistors T 1  and T 2 . This circuitry uses less fuses than the circuitry of FIGS. 1, 2, and 3. Fuse F 1  is in series with pass gate 46 in the path of output signal 44. Although this configuration saves on the number of fuses used, the output signal 44 is loaded down when fuse F 1  is intact because of the diffusion capacitance of pass gate 46. The source and drain regions of pass gate 46 contribute extra capacitance when fuse F 1  is not blown. Poly resisters as well as active region resistors, however, could be used instead of pass gate 46 to fulfill the same resistance function. 
     Additionally, as shown and described in conjunction with FIG. 1b, a resistive element, such as a second pass gate, could be placed in series with fuse F 1 , and a second fuse placed in parallel to fuse F 1  and the second pass gate to allow for two different delays: a delay introduced by blowing the second fuse and a longer delay introduced by blowing both fuse F 1  and the second fuse. Referring to FIG. 5, such inverter circuitry 50 is shown. Input signal 52 is connected to an inverter comprised of transistors T1 and T2. Fuse F 1  is connected in series with pass gate 58 in the path of output signal 54. A second pass gate 58 is connected in series with fuse F 1 , and a second fuse F 2  is placed in parallel to fuse F 1  and pass gate 58 such that two different delays maybe obtained: a delay by blowing fuse F 2  and a delay by blowing both fuse F 1  and fuse F 2 . 
     While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the .art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.