System which achieves efficient utilization of buses for selectively interconnecting communication lines
BACKGROUND OF THE INVENTION 
     This invention relates to a system for selectively interconnecting a plurality of communication lines to provide communication therebetween and, in particular, to a system capable of dealing with both of a data signal and a speech signal. 
     Various systems have been proposed for selectively distributing digital signals among a plurality of communication lines. A typical system is disclosed in U.S. Pat. No. 4,601,029 issued to Franklin Hargrave et al. In this conventional system, each communication port, through which communication signals are transmitted and received, is assigned with transmitting time slots on a transmission bus and receiving time slots on a reception bus. Communication is carried out by the use of the transmitting and receiving time slots. 
     In order to carry out intercommunication or two-way communication through two communication ports, the above-mentioned conventional system requires two transmission time slots on the transmission bus and two receiving time slots on the reception bus in the manner known in the art. In this connection, these buses can not be fully efficiently used. For example, it is assumed that a single frame consists of twenty-four time slots in each of the transmission and the reception buses. In this event, only twelve pairs of the communication ports can simultaneously carry out intercommunication through each pair. 
     In addition, it is impossible for the conventional switching system to deal with a particular signal having a transmission speed which is lower than that of a speech signal. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of this invention to provide a system which achieves efficient utilization of buses. 
     Other objects of this invention will become clear as the description proceeds. 
     According to an aspect of this invention, there is provided a system for selectively interconnecting a plurality of communication lines each of which is adapted for transmitting a communication signal. The system comprises a plurality of port buses and a plurality of interface circuits connected to the communication lines and the port buses, respectively. Each of the interface circuits carries out a transmission of the communication signal between each of the communication lines and each of the port buses. The system further comprises a loop bus forming a loop shape, exchanging means connected to the port buses and the loop bus for exchanging the communication signal between the port buses through the loop bus, and means connected to the exchanging means for controlling operation of the exchanging means. 
     According to another aspect of this invention, there is provided a system for selectively interconnecting a plurality of communication lines. The system comprises a plurality of bidirectional buses for propagation of communication signals supplied through the communication lines, a plurality of interface circuits connected to the bidirectional buses for carrying out transmission and reception of the communication signals to and from the bidirectional buses, a plurality of switching units connected in one-to-one correspondence to the bidirectional buses for exchanging the communication signals on the bidirectional buses, a unidirectional bus connecting the switching units to form a loop shape, a delay unit connected to the unidirectional bus for making the communication signal have a particular delay on the unidirectional bus, and means connected to the interface circuits for assigning to the interface circuits time slots available in communication by the use of the communication signals. 
     According to still another aspect of this invention, there is provided an apparatus for exchanging an input signal and an output signal by the use of a repetitive sequence of time slots. The apparatus comprises a unidirectional bus forming a loop shape and a plurality of bidirectional buses connected to the unidirectional bus. Each of the bidirectional buses is adapted for selectively propagating the input and the output signals in a particular time slot of the first-mentioned time slot sequence and has an input and an output mode which use each of the time slots as a transmitting time slot and as a receiving time slot, respectively. The apparatus further comprises a plurality of switching units each of which is connected between the unidirectional bus and each of the bidirectional buses, a plurality of interface circuits connected to the bidirectional buses, a delay unit connected to the unidirectional bus, and a timing-generating unit connected to the unidirectional bus and generating a succession of frame pulses and a succession of clock pulses to supply the frame pulse succession and the clock pulse succession to the switching units, the interface circuits, and the delay unit. Each of the interface circuits comprises interface-producing means for producing a state indication signal and a use indication signal in response to the input signal, interface-supplying means connected to the interface-producing means and to one of the bidirectional buses for supplying the state indication, the use indication, and the communication signals to the transmitting time slot on the one of the bidirectional buses, and receiving means connected to the one of the bidirectional buses for receiving the communication signal from the receiving time slot on the one of the bidirectional buses. Each of the switching units comprises judging means connected to the one of the bidirectional buses for judging whether or not the state indication signal is present in the particular time slot on the one of the bidirectional buses and first transmitting means connected to the unidirectional bus and the judging means for transmitting the communication signal from one of the interface circuits to a specific time slot on the unidirectional bus when the state indication signal is present in the particular time slot. The specific time slot corresponds to the particular time slot. Each of the switching units further comprises second transmitting means connected to the one of the bidirectional buses and the judging means for transmitting the communication signal from the one of the interface circuits to the particular time slot on the one of the bidirectional buses when the state indication signal is absent in the particular time slot. 
     According to yet another aspect of this invention, there is provided a system for selectively interconnecting a plurality of communication lines each of which is adapted for transmitting a communication signal. The system comprises signal circulating means for circulating a loop bus signal along a loop shape, signal supplying means connected to a first one of the communication lines and to the signal circulating means for supplying the communication signal as the loop bus signal from the first one, signal sending means connected to a second one of the communication lines and to the signal circulating means for sending the loop bus signal as the communication signal to the second one from the signal circulating means, and distributing means connected to the signal circulating and the signal sending means for distributing the loop bus signal between the signal circulating and the signal sending means. 
     According to a further aspect of this invention, there is provided a method for selectively interconnecting a plurality of communication lines each of which is adapted for transmitting a communication signal. The method comprises steps of circulating a loop bus signal along a loop shape, supplying the communication signal as the loop bus signal from a first one of the communication lines, sending the loop bus signal as the communication signal to a second one of the communication lines from the signal circulating means, and distributing the loop bus signal between the signal circulating and the signal sending means. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a block diagram of a system according to an embodiment of this invention; 
     FIG. 2 is a block diagram of a first line interface circuit included in the system illustrated in FIG. 1; 
     FIG. 3 is a circuit diagram of a first switching unit included in the system illustrated in FIG. 1; 
     FIG. 4 is a block diagram of a delay unit included in the system illustrated in FIG. 1; 
     FIG. 5 is a time chart for describing an exchange operation between bidirectional buses included in the system illustrated in FIG. 1; and 
     FIG. 6 is a time chart for describing operation of the first switching unit included in the system illustrated in FIG. 1. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, description will be made of a system according to an embodiment of this invention. The system is for selectively interconnecting first, second, and third communication lines 11, 12, and 13 each of which is adapted for transmitting an input and an output signal by the use of a repetitive sequence of time slots in the manner known in the art. A combination of the input and the output signals may be called a communication signal. 
     The system comprises a loop bus 14, first, second, and third switching units 15, 16, and 17, a delay unit 18, and a timing-generating unit 19. The loop bus 14 comprises loop timing, loop data, and loop use indication buses 14a, 14b, and 14c each of which forms a loop shape. In the loop bus 14, a loop bus signal is transmitted along the loop shape in a predetermined direction which is indicated by an arrow. Therefore, the loop bus 14 may be called a unidirectional bus. 
     Each of the first, the second, and the third switching units 15, 16, and 17 is connected to the loop timing, the loop data, and the loop use indication buses 14a, 14b, and 14c of the unidirectional bus 14 and has operation which will later be described in detail. A combination of the first, the second, and the third switching units 15, 16, and 17 is referred to as an exchanging arrangement. 
     The delay unit 18 is connected to the loop timing, the loop data, and the loop use indication buses 14a, 14b, and 14c of the unidirectional bus 14 and is for making the loop bus signal have a particular delay on the unidirectional bus 14. The timing-generating unit 19 is connected to the loop timing bus 14a and is adapted for generating a timing signal to supply the timing signal to the loop timing bus 14a. The timing signal comprises a succession of clock pulses and a succession of frame pulses of 8 kHz. 
     The system further comprises first, second, and third port buses 21, 22, and 23, first interface, second main interface, second supplementary interface, third main interface, and third supplementary interface circuits 25, 26a, 26b, 27a, and 27b, and a central processing unit 28. The first port bus 21 comprises first state indication, first data, first timing, and first use indication buses 21a, 21b, 21c, and 21d which are connected to the first switching unit 15 and the first interface circuit 25. The second port bus 22 comprises second state indication, second data, second timing, and second use indication buses 22a, 22b, 22c, and 22d which are connected to the second switching unit 16 and the second main interface and the second supplementary interface circuits 26a and 26b. The third port bus 23 comprises third state indication, third data, third timing, and third use indication buses 23a, 23b, 23c, and 23d which are connected to the third switching unit 17 and the third main interface and the third supplementary interface circuits 27a and 27b. In each of the first, the second, the third port buses 21, 22, and 23, a port bus signal is transmitted in both of a first direction and a second direction opposite to the first direction. Therefore, the first, the second, the third port buses 21, 22, and 23 may be called a first, a second, and a third bidirectional buses, respectively. 
     The first interface circuit 25 is connected to the first communication line 11. The second interface circuit 26 is connected to the second communication line 12. The third interface circuit 27 is connected to the third communication line 13. Each of the first, the second, and the third interface circuits 25, 26, and 27 performs an operation which will later be described in detail. 
     The central processing unit 28 is connected to the delay unit 18 and the first interface, the second main interface, the second supplementary interface, the third main interface, and the third supplementary interface circuits 25, 26a, 26b, 27a, and 27b and is for producing a line control signal to control the system in the manner which will later become clear. 
     Turning to FIG. 2, the description will be made as regards the first interface circuit 25 alone. The other interface circuits 26a, 26b, 27a, and 27b will not be described. This is because each of the other interface circuits 26a, 26b, 27a, and 27b has a structure similar to that of the first interface circuit 25. 
     In the manner which will presently be described, the first interface circuit 25 comprises a use indication signal gate circuit 31, a line control signal detection circuit 32, a data signal gate circuit 33, a state indication signal gate circuit 34, a signal transmission/reception circuit 35, a signal assembling/disassembling circuit 36, and a line terminating circuit 37. 
     The line terminating circuit 37 terminates the communication signal sent through the first communication line 11 and carries out transmission and reception of the communication signal to and from the signal assembling/disassembling circuit 36. Received with the communication signal from the signal assembling/disassembling circuit 36, the line terminating circuit 37 transmits the communication signal to the first communication line 11. In this event, the line terminating circuit 37 will be referred to as an additional communication signal transmitting arrangement. 
     The signal assembling/disassembling circuit 36 disassembles or assembles the communication signal and the line control signal that is supplied through the line 38. The communication signal is transmitted and received between the signal assembling/disassembling and the signal transmission/reception circuits 36 and 35. The line control signal is transmitted and received between the signal assembling/disassembling circuit 36 and the line control data detection circuit 32. 
     In response to a transmission/reception request supplied from the signal transmission/reception circuit 35, the line control data detection circuit 32 carries out transmission and reception of the line control signal to and from the signal transmission/reception circuit 35. 
     During transmission, the signal transmission/reception circuit 35 produces a signal which will hereafter be called a control signal. In this event, the signal transmission/reception circuit 35 will be referred to as a control signal producing arrangement. The control signal is sent together with the communication signal to a predetermined time slot of a predetermined transmission frame in the manner known in the art. Specifically, the signal transmission/reception circuit 35 sends the control signal and the communication signal to the data signal gate circuit 33 collectively as a line data signal. The line data signal is supplied to the first data bus 21b from the data signal gate circuit 33. The data signal gate circuit 33 will be referred to as a communication signal transmitting arrangement. 
     At this time, the data transmission/reception circuit 35 produces a state indication signal indicating that the line data signal is transmitted. In this event, the data transmission/reception circuit 35 will be referred to as a state indication signal producing arrangement. 
     The state indication signal is supplied to the first state indication bus 21a through the state indication signal gate circuit 34. The state indication signal gate circuit 34 will be referred to as a state indication signal supplying arrangement. 
     Furthermore, the data transmission/reception circuit 35 produces a use indication signal indicating that the first data bus 21b is being used. The use indication signal is supplied to the first use indication bus 21d through the use indication signal gate circuit 31. Simultaneously, the transmission/reception circuit 35 supplies a gate control signal to each of the use indication signal gate circuit 31, the data signal gate circuit 33, and the state indication signal gate circuit 32 so as to selectively deliver the line data signal corresponding to a preassigned time slot on the first data bus 21b. 
     On the other hand, during reception, the transmission/reception circuit 35 receives the line data signal on a preselected time slot of a preselected reception frame. In this event, the signal transmission/reception circuit 35 will be referred to as a control signal receiving arrangement. 
     When the bus use indication signal at the time slot thus designated is active prior to transmission of the line data signal, the transmission/reception circuit 35 interrupts data transmission. During reception, the transmission/reception circuit 35 selectively receives the active data signal from the line data signal. 
     In the first interface circuit 25, the signal transmission/reception circuit 35 may be referred to as an interface-producing arrangement. A combination of the use indication signal gate, the data signal gate, and the state indication signal gate circuits 31, 33, and 34 may be referred to as an interface-supplying arrangement. The signal transmission/reception circuit 35 may be referred to as each of a use indication signal receiving arrangement and an interface-judging arrangement. 
     Turning to FIG. 3 together with FIG. 1, the description will be directed to the first switching unit 15 alone. Each of the second and the third switching units 16 and 17 will not be described. This is because each of the second and the third switching units 16 and 17 has a structure similar to that of the first switching unit 15. 
     In the manner which will presently be described, the first switching unit 15 comprises timing control, demultiplexing, counter data control, data control, and multiplexing circuits 41, 42, 43, 44, and 45. Responsive to the timing signal supplied as a loop timing signal from the loop timing bus 14a, the timing control circuit 41 generates a clock signal and a frame signal. The clock signal is delivered through the first timing bus 21c to the first interface circuit 25. The frame signal is delivered through the loop timing bus 14a to the second switching unit 16. The clock and the frame signals are also supplied to the demultiplexing, the data control, the counter data control, the data control, and the multiplexing circuits 42, 43, 44, and 45. 
     In the manner which will become clear, it is assumed that the demultiplexing circuit 42 is supplied with the data and the use indication signals through the loop data and the loop use indication buses 14b and 14c, respectively. Responsive to the clock, the frame, the data, and the use indication signals, the demultiplexing circuit 42 carries out demultiplexing operation between the data and the use indication signals to produce a demultiplexed signal and a multiplexing signal. The demultiplexed signal is supplied to the data control circuit 44. The multiplexing signal is supplied to the multiplexing circuit 45. The counter data control circuit 43 produces a counter active signal in response to the clock and the frame signals to supply the counter active signal to the data control circuit 44. In addition, the data control circuit 44 is received with the state indication, the line data, and the use indication signals through the first state indication, the first data, and the first use indication buses 21a, 21b, and 21d. In this event, the data control circuit 44 will be referred to as a receiving arrangement. 
     In response to the clock, the frame, the demultiplexed, the counter active, the state indication, the line data, and the use indication signals, the data control circuit 44 produces an interruption indication signal, an active line indication signal, the line data signal, and the use indication signal in the manner which will presently be described. 
     The timing control circuit 41 determines whether or not the state indication signal is present on the first indication bus 21a. In this event, the timing control circuit 41 will be referred to as an exchange-judging arrangement. 
     When the state indication signal is present on the first state indication bus 21a, the data control circuit 44 takes the line data signal on the first data bus 21b. In this event, the data control circuit 44 will be referred to as a first transmitting arrangement. In addition, the data control circuit 44 takes the use indication signal on the first use indication bus 21d and delivers the line data signal and the use indication signal to the multiplexing circuit 45 collectively as an active line data signal. 
     Simultaneously, the data control circuit 44 delivers the interruption indication signal to the demultiplexing circuit 42. Responsive to the interruption indication signal, the demultiplexing circuit 42 interrupts the demultiplexing operation thereof. 
     On the other hand, when the state indication signal is absent on the first state indication signal bus 21a, the data control circuit 44 receives the demultiplexed signal from the demultiplexing circuit 42 and delivers the line data signal and the use indication signal to the first data bus 21b and the first use indication bus 21d, respectively. Furthermore, the data control circuit 44 delivers the counter active signal to the first data bus 21b. 
     The multiplexing circuit 45 is for multiplexing the multiplexing signal and the active line indication signal to produce a multiplexed signal and the use indication signal. The multiplexed signal is supplied as the data signal to the second switching unit 16 through the loop data bus 14b. The use indication signal is supplied to the second switching unit 16 through the use indication bus 14c. A combination of the data control circuit 44 and the multiplexing circuit 45 will be referred to as a second transmitting arrangement. 
     Turning to FIG. 4, the description will be directed to the delay unit 14. In the manner which will be described in the following, the delay unit 14 comprises a count data producing circuit 51, a delay control circuit 52, a write circuit 53, a buffer circuit 54, and a read circuit 55. The count data producing circuit 51 is supplied with a delay control signal from the central processing unit 28 through the line 56. In this event, the count data producing circuit 51 will be referred to as a count data sending arrangement. 
     In operation, the count data control circuit 51 counts up count data one by one as from an initial value or zero to an upper limit value in response to the delay control signal. When the count data reaches the upper limit value, the count data control circuit 51 resets the count data. The count data are sent as a count data signal to the delay control circuit 52. The above-mentioned operation is cyclically repeated. 
     Responsive to the delay control signal and the count data, the delay control circuit 52 controls operation of the write circuit 53, supplies the count data to the buffer circuit 54, and controls the timing of operation of the read circuit 55. Received with a write request from the delay control circuit 52, the write circuit 53 writes the loop data signal and the use indication signal into the buffer circuit 54 with reference to the clock signal and the frame signal. Received with a write inhibition request supplied from the delay control circuit 52, the write circuit 53 interrupts its writing operation. During interruption, the buffer circuit 54 is written with the count data that are supplied from the count data control circuit 51 through the delay control circuit 52. 
     The buffer circuit 54 comprises a FIFO memory and holds the data signal supplied from the write circuit 54 to make the data signal be read under control of the read circuit 55. Typically, the buffer circuit 54 holds the line data signal in an amount corresponding to one of signal frames which are defined in accordance with the frame signal. It is noted that this amount is variable under control of the delay control circuit 55. The buffer circuit 54 also holds the count data that is supplied from the delay control circuit 52. In response to the timing signal, the reads circuit 55 read the data signal and the use indication signal from the buffer circuit 54 to send the data signal and the use indication signal to the loop data bus 14b and the loop use indication bus 14c, respectively. Thus, the data and the use indication signals are delayed by one of the signal frames and sent to the second switching unit 16. 
     Next referring to FIG. 5 together with FIG. 1, the description will be directed to an example of basic operation of the system. The frame signal on each of the first and the second timing buses 21c and 22c is depicted along each of a first or top line and a fifth line. The clock signal on each of the first and the second timing buses 21c and 22c is depicted along each of a second line and a sixth line. A repetitive sequence of time slots on each of the first and the second data buses 21b and 22b is illustrated along each of a third line and a seventh line as zeroth, first, second, and third time slots T0, T1, T2, and T3. The state indication signal on each of the first and the second state indication buses 21a and 22a is depicted along each of a fourth line and an eighth line. 
     The central processing unit 28 assigns the first and the second interface circuits 25 and 26 with the zeroth through the third time slots T0 to T3 as follows. On each of the first and the second data buses 21b and 22b, the zeroth time slot T0 is assigned for the count data signal. On the first data bus 21b, the first time slot T1 is assigned as a transmission time slot. The third time slot T3 is assigned as a reception time slot. 
     On the second data bus 22b, the first time slot T1 is assigned as the reception time slot. The third time slot T3 is assigned as a transmission time slot. 
     Upon transmission of the line data signal, the first interface circuit 25 sends a logic &#34;0&#34; level to each of the first state indication bus 21a and the first use indication bus 21d at the first time slot T1. The operation is repeated before termination of the line data signal. 
     The description will be made of a case where the communication signal is transmitted from the first interface circuit 25 to the second main interface circuit 26a. The first switching unit 15 monitors the first state indication bus 21a. When the first state indication bus 21a has the logic &#34;0&#34; level, the first switching unit 15 sends the multiplexed and the use indication signals towards the second switching unit 16 collectively as the loop bus signal. Supplied with the loop bus signal, the second switching unit 16 sends the line data signal to the second data bus 22b and the second use indication bus 22d only when the second state indication bus 22a has a logic &#34;1&#34; level. The second main interface circuit 26a confirms the first time slot T1 on the second data bus 22b and receives the line data signal that is addressed to the second main interface circuit 31. 
     The description will be directed to another case where the communication signal is transmitted from the second main interface circuit 26a to the first interface circuit 25. In this case, the line data signal is delivered to the third time slot T3 on the second data bus 22b. In the manner similar to that described in conjunction with the first switching unit 15, the second switching unit 16 delivers the line data signal to the loop data bus 14b and the loop use indication bus 14c. 
     The line data signal is sent through the third switching unit 17 to the delay unit 18. The delay unit 18 gives the particular delay having a length corresponding to one of the signal frames. Thus, the line data signal is carried on the third time slot T3 of a following signal frame immediately following a frame position of the transmission frame delivered from the second main interface circuit 26a. The line data signal is circulated on the loop data bus 14b. 
     Supplied with the line data signal, the first switching unit 15 delivers the line data signal to the first data bus 21b and to the first use indication bus 21d only when the state indication bus 21a has the logic &#34;1&#34; level in a time instant corresponding to the third time slot T3. The first interface circuit 25 confirms the third time slot T3 and receives the line data signal that is addressed to the first interface circuit 25. 
     Further referring to FIG. 6, the description will be directed to operation of the first switching unit 15. As described in the foregoing, the count data signal is sent from the delay unit 18 to a predetermined time slot. It is assumed here that the count data signal is present at a zeroth time slot T0. Each of the first interface circuit 25 and the second main interface circuit 26a is preliminarily allotted with transmission and reception frame positions and time slot positions which are indicated by the count data signal. Operation is carried out similar to the basic operation as described above. Thus, by deciding the frame position, it is possible to exchange a particular communication signal having a speed slower than 64 kbps in addition to the basic data signal on the order of, for example, 64 kbps. 
     In a case where the communication signal is of, for example, 32 kbps, the count data signal is assumed to have a repetition between a logic &#34;0&#34; level and a logic &#34;1&#34; level. The first interface circuit 25 is allotted with a zeroth frame and a first time slot T1 as a transmission frame and a transmission time slot and with a first frame and a third time slot T3 as a reception frame and a reception time slot. On the other hand, the second main interface circuit 26a is allotted with a zeroth frame and a third time slot T3 as a transmission frame and a transmission time slot and with a zeroth frame and a first time slot T1 as a reception frame and a reception time slot. 
     Thus, the transmission interval of each interface circuit is once per two frames so that the communication signal of 32 kbps is exchanged. 
     The use indication signal is controlled as follows. As described above, the use indication signal is sent to each interface circuit in the manner similar to the line data signal. 
     It is assumed here that a particular one of the interface circuits is about to transmit the line data signal. When the bus use indication signal has the logic &#34;0&#34; level at the assigned time slot, the interface circuit interrupts transmission of the line data signal until the use indication signal is turned to the logic &#34;1&#34; level. During reception, the interface circuit selectively receives an active component of the line data signal alone. 
     The description will be made as regards the control signal. As described above, each interface circuit is operable to deliver the line information signal and the control signal collectively as the line data signal. 
     For example, it is assumed that the control signal is a sound/silence information data signal indicating the state of the speech data. The speech data have a rate of 32 kbps. The delay has a length corresponding to two frames. The count data signal has the repetition between the logic &#34;0&#34; level and the logic &#34;1&#34; level. The first interface circuit 25 is assigned with the first time slot T1 of a zeroth frame for transmission of the control signal, the first time slot T1 of a first frame for transmission of the speech data signal, the third time slot T3 of a zeroth frame for reception of the control signal, and the third time slot T3 of a first frame for reception of the speech data signal. 
     The second main interface circuit 26a is assigned with the third time slot T3 of the zeroth frame for transmission of the control data signal, the third time slot T3 of the first frame for transmission of the speech data signal, the first time slot T1 of the zeroth frame for reception of the control data signal, and the first time slot T1 of the first frame for reception of the speech data signal. 
     Thus, the operation is carried out similar to the basic operation so that the control signal and the speech data signal are alternately transmitted and received. 
     With this structure, a single time slot is commonly used in transmission and reception. As a consequence, the efficiency in utilization of the bus is increased to twice as large as that of the conventional device using the transmission bus and the reception bus. In other words, the line data input/output control device of this invention has a reduced bus scale corresponding to one of the transmission and reception buses and still exhibits the capacity equivalent to that of the conventional device having the transmission and the reception buses. 
     In addition, it is possible to avoid data collision on the exchange bus by introducing control with the time slot use indication signal. 
     While the present invention has thus far been described in connection with only a single embodiment thereof, it will readily be possible for those skilled in the art to put this invention into practice in various other manners. For example, the system may comprise four or more port buses although three port buses are exemplified.