Code conversion circuit
The present invention relates to a code conversion circuit which, when a value i in a binary code form is applied, provides an output &#34;1&#34; on all of the first to the i-th ones of a plurality of output lines and an output &#34;0&#34; on all of the remaining (i+1)-th to the highest order output lines, or provides &#34;1&#34; on i most significant output lines and &#34;0&#34; on all of the remaining output lines. The value i is 0 or any positive integer. 
     BACKGROUND OF THE INVENTION 
     Typically, the code conversion of the type stated above is carried out by means of two decoders. When a binary code representing the value i is applied, a first decoder develops a signal &#34;1&#34; only on the (i+1)-th one of a plurality of output lines thereof, and develops a signal &#34;0&#34; on all of the remaining output lines. The second of the two decoders receives outputs of the first decoder and develops the signal &#34;1&#34; on all of the first to the i-th ones of a plurality of output lines thereof and the signal &#34;0&#34; on all of the remaining output lines. Alternatively, the second decoder receives output signals from the first decoder and develops the signal &#34;1&#34; on all of the i most significant output lines and the signal &#34;0&#34; on all of the remaining output lines. 
     An example of a circuit which may be used as the second decoder is disclosed in of Japanese Unexamined Patent Publication No. SHO 63-156427. The circuit of this publication is called an decoding circuit&#34; and includes a number of gates serially connected between a voltage supply and a point of reference potential. Respective outputs from a first decoder are coupled to corresponding gates of the second decoder. Output lines are derived from respective junctions between adjacent ones of the gates. 
     The second decoder of the above-described type requires a large number of transmission gates for handling a large value. For example, for a value i in a range of from 0 to 30, thirty (30) transmission gates must be connected in series, causing an increase in capacitance provided by diffusion layers of transistors constituting the gates as well as an increase in capacitance and resistance associated with wiring for the transistors. This could cause instability in circuit performance or reduce operating speed. 
     Another type of conventional circuit which may be used as the second decoder includes a number of OR gates connected in series, as shown in prior art FIG. 3. Respective first decoder outputs are coupled to the respective ones of the OR gates. The output of the second decoder is derived from the respective OR gates. In this type of decoder, when an input signal &#34;1&#34; is applied to a more significant OR gate, the signal must cause less significant OR gates successively to be enabled, which results in significant delay in operation. 
     Accordingly, a major object of the present invention is to provide a second decoder which can operate stably and at a high speed. 
     SUMMARY OF THE INVENTION 
     According to a first embodiment of the present invention, a code conversion circuit includes a first decoder which is responsive to an a-bit binary input representing a value i to develop a signal &#34;1&#34; only on the (i+1)-th one of b output lines thereof and develop a signal &#34;0&#34; on all of the remaining output lines, where i is an integer and b is equal to or smaller than 2 a . The code conversion circuit further includes a second decoder which is responsive to the output signals of the first decoder to develop the signal &#34;1&#34; on all of the first to i-th ones of j ordinally numbered output lines thereof and develop the signal &#34;0&#34; on all of the remaining (i+1)-th to the j-th output lines. The number j can be equal to or less than (b-1). 
     According to the first embodiment of the present invention, the second decoder is segmented into a plurality of blocks each having ordinally numbered ones of output lines. Each block also includes block control means. The block control means controls the state of the block to which the block control means belongs. The block may be placed in a first state in which a signal &#34;1&#34; is developed on all of the output lines of that block, a second state in which the signal &#34;1&#34; is developed on the i-th one of all of the output lines of the second decoder and also on lower order ones of the output lines which belong to that block, if that block includes the i-th output line and a signal &#34;0&#34; is developed on all of the remaining output lines of that block, or a third state in which the signal &#34;0&#34; is developed on all of the output lines of that block. 
     Segmentation control signal generating means is provided, which prepares block control signals in accordance with the binary input to the first decoder, for controlling the block control means of the respective blocks such that the n-th block which includes the i-th output line assumes the second state, the first to the (n-1)-th blocks assume the first state, and all of the remaining blocks above in the order the (n+1)-th block assume the third state. 
     A code conversion circuit according to a second embodiment of the invention includes a first decoder similar to the one described above. A second decoder includes j ordinally numbered output lines and is responsive to the output signals of the first decoder to develop the signal &#34;1&#34; on all of the i most significant ones of the j output lines thereof, and develop the signal &#34;0&#34; on all of the remaining output lines. The number j can be equal to or smaller than (b-1). 
     According to the second embodiment of the present invention, the second decoder is segmented into a plurality of blocks each having ordinally numbered ones of output lines. Each block also includes block control means. The block control means controls the block to which the block control means belongs. The block may be placed in a first state in which the signal &#34;1&#34; is developed on all of the output lines of that block, a second state in which the signal &#34;1&#34; is developed on the (j-i+1) output line of all the output lines of the second decoder and on higher order output lines of that block and a signal &#34;0&#34; is developed on all of the remaining output lines of that block when the (j-i+1)-th output line belongs to that block, or a third state in which the signal &#34;0&#34; is developed on all of the output lines of that block. 
     Segmentation control signal generating means is provided, which prepares block control signals in accordance with the binary input to the first decoder, for controlling the block control means of the respective blocks such that the n-th block which includes the (j-i+1)-th output line assumes the second state, the first to the (n-1)-th blocks assume the first state, and all of the remaining blocks above in the order the n+1)-th block assume the third state. 
     It is advantageous to divide the second decoder into a power of 2. Assuming that the number of blocks is 2 c , the block control signal generating means can prepare block control signals based on the c most significant bits of the a-bit input binary code signal. 
     For example, when a 4-bit binary code is applied as an input, the second decoder may be segmented into two blocks so that the most significant bit of the 4-bit binary input can be used to prepare the block control signals. If the second decoder is segmented into four blocks, the two most significant bits of the binary input may be used to prepare the block control signals. 
     When a binary code representing a value i is applied to the code conversion circuit of the present invention, the first decoder develops the signal &#34;1&#34; only on the (i+1)-th one of the output lines thereof, which is applied to the (i+1)-th input line to second decoder. The block control signal generating means prepares block control signals based on a most significant bit of the input binary code. The block control signals are applied to the block control means of the respective blocks of the second decoder. 
     In the code conversion circuit according to the above-described first embodiment, only the n-th block of the second decoder that includes the i-th one of the output lines of the second decoder operates, in response to the block control signals, to develop the signal &#34;1&#34; on the i-th one of the output lines of the second decoder and lower order output lines belonging to the n-th block and develop the signal &#34;0&#34; on the (i+1)-th one of the output lines of the second decoder and higher order output lines of the n-th block. All of the (n-1)-th and lower order blocks, having output lines lower in order than the i-th output line are forced to develop the signal &#34;1&#34; on all of their output lines, whereas all of the (n+1)-th and higher order blocks, having output lines higher in order than the i-th output line are forced to develop the signal &#34;0&#34; on all of their output lines. This operation is performed in response to the block control signals applied to the respective blocks. 
     In the code conversion circuit according to the above-described second embodiment, only the n-th block that includes the output line (i-1)-th from the most significant bit output lines (i.e. the (j-i+1)-th output line) of the second decoder operates, in response to the block control signal applied to to develop the signal &#34;1&#34; on the output line (i-1)-th from the most significant bit output line of the second decoder and higher order output lines belonging to the n-th block and develop the signal &#34;0&#34; on the output line i-th from the most significant bit output line of the second decoder and on lower order output lines belonging to the n-th block. All of the (n+1)-th and higher order blocks are forced to develop the signal &#34;1&#34; on all of their output lines, whereas all of the (n-1)-th and lower order blocks are forced to develop the signal &#34;0&#34; on all of their output lines. This operation is performed in response to the block control signals applied to the respective blocks. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a table illustrating the code conversion performed by a code conversion circuit according to a first embodiment of the present invention, which exemplifies 4-bit binary inputs representative of values of from 0 to 15, block control signals applied to a second decoder, outputs of a first decoder, and outputs of the second decoder, corresponding to the respective 4-bit binary inputs; 
     FIG. 2 shows a conventional code conversion circuit which performs code conversion similar to the code conversion provided by the circuit according to the first embodiment of the present invention, in which the second decoder comprises a number of gates connected in series; 
     FIG. 3 shows another conventional circuit having a the function similar to that of the second decoder used in the code conversion circuit of FIG. 2, and which comprises a number of OR gates; 
     FIG. 4 shows a first example of code conversion circuit according to an embodiment of the present invention, in which the second decoder is segmented into four blocks each employing serially connected transmission gates; 
     FIG. 5(a) shows one form of a transmission gate which may be used in the FIG. 4 decoder. FIG., 5(b) shows another form of a transmission gate which may be used in the FIG. 4 decoder. FIG. 5(c) shows another form of a transmission gate which may be used in the FIG. 4 decoder. 
     FIG. 6 shows a second decoder used in another example of code conversion circuit according to an embodiment of the present invention, in which the second decoder is segmented into blocks each comprising serially connected transmission gates and an OR gate; 
     FIG. 7 shows a second decoder used in a third example of code conversion circuit according to an embodiment of the present invention, in which the second decoder is segmented into blocks each employing serially connected OR gates; 
     FIG. 8 shows a second decoder used in a fourth example of code conversion circuit according to an embodiment of the present invention, in which the second decoder is segmented into blocks each employing multiple-input OR gates; 
     FIG. 9 shows a code conversion circuit according to an embodiment of the present invention, in which output lines of the second decoder are ordinally numbered in the reverse direction relative to the embodiments shown in FIGS. 4-8; 
     FIG. 10 is a table illustrating the code conversion performed by the code conversion circuit of FIG. 9; 
     FIG. 11 shows an example of block control signal generating circuit for segmenting the second decoder into two blocks; 
     FIG. 12 shows an example of block control signal generating circuit for segmenting the second decoder into eight blocks; and 
     FIG. 13 shows an example of block control signal generating circuit for segmenting the second decoder into sixteen blocks. 
     FIG. 14 shows a conventional decoder circuit shown in Japanese Unexamined Patent Publication No. SHO 63-156427. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring to FIG. 4, the code conversion circuit according to an embodiment of the present invention, receives a binary input signal comprising, for example, four bits L 1 , L 2 , L 3  and L 4 , representing a value from 0 to 15. A decoder 1 in this example has sixteen (16) output lines Z 1  through Z 16 . Output signals on output lines Z 1  through Z 16  are applied to a second decoder 2 having fifteen (15) output lines Y 1  through Y 15 . Decoder 2 in turn, develops output signals on its output lines Y 1  through Y 15 . For example, when the input value is 6, the binary input signal is &#34;0110&#34; Decoder 1 receives this binary input &#34;0110&#34; and develops a signal &#34;1&#34; only on output line Z 7 , and decoder 2 develops the signal &#34;1&#34; on output lines Y 1  through Y 6 . 
     Such code conversion has been conventionally performed by a circuit, for example as shown in FIG. 2. In FIG. 2, decoder 1 is supplied with a binary input signal through 4-bit lines L 1 , L 2 , L 3  and L 4  and develops an output signal &#34;1&#34; on an appropriate one of sixteen-bit output lines Z 1  through Z 16 . Decoder 2 is supplied with outputs on output lines Z 1  through Z 16  of decoder 1 and develops output signals on fifteen-bit output lines Y 1  through Y 6  when the input value i is 6. Output signals on output lines Y 1  through Y 6  of decoder 2 and binary input signals applied to decoder 1 are related as shown in TABLE 1 shown in FIG. 1. 
     In the conventional circuit shown in FIG. 2, decoder 2 comprises 16 transmission gates 201-216 connected in series between a voltage source and ground. Output signals of decoder 1 are applied to associated ones of the transmission gates of decoder 2. Outputs from decoder 2 are derived from junctions between respective adjacent gates. The operation and configuration of decoder 2 are similar to those of allotting section 2 of the circuit disclosed in the previously referred Japanese Unexamined Patent Publication No. SHO 63-156427. This circuit is shown in FIG. 14 of the present invention. Specifically, the allotting section of this Japanese patent publication has an equivalent function to decoder 2 of the present invention, and includes transmission gates each including a P-channel FET, an N-channel FET, and an inverter, as shown in FIG. 14. In FIG. 2 of the present application, a block represents this transmission gate. Furthermore, the circuit shown in FIG. 14 uses only four such transmission gates, in contrast with sixteen gates used in the arrangement of FIG. 2. 
     The operation of the circuit shown in FIG. 2 is specifically described. Let it be assumed that a value 6 is applied to the circuit. The input to decoder 1 is L 1  =&#34;0&#34;, L 2  =&#34;1&#34;, L 3  &#34;1&#34;, L 4  =&#34;0&#34;, and the output signals bn the output lines of decoder 1 are all &#34;0&#34; except output line Z 7 , as shown in FIG. 1. A signal &#34;1&#34; is developed only on output line Z 7 . Gates 201-216 are rendered conductive when they are supplied with an input &#34;0&#34;, and are rendered nonconductive when an input &#34;1&#34; is applied to them. Accordingly, in this particular example, only gate 207 becomes nonconductive due to the output signal &#34;1&#34; on output line Z 7  connected to gate 207. As a result, a signal &#34;1&#34; is developed on output line Y 8  and on all of output lines Y 5 , Y 4 , Y 3 , Y 2  and Y 1  closer to the voltage source than output line Y 6 . A signal &#34;0&#34; is developed on all of output lines Y 7  through Y 15  which are closer to ground. 
     FIG. 3 shows another conventional example of decoder 2, in which fourteen OR gates 272-285 are used. OR gates are connected in series, each receiving an output from an associated one of output lines of decoder 1 and a next higher ordered OR gate, as shown. For example, OR gate 272 receives an output from output line Z 2  and an output from OR gate 273, and OR gate 284 receives an output on output line Z 14  of decoder 1 and an output of OR gate 285. OR gate 285 receives outputs on output lines Z 15  and Z 16  of decoder 1. The output signal on output line Z 18  of decoder 1 is also developed as the most significant bit output Y 15  of decoder 2. 
     The circuit shown in FIG. 3 operates as follows. Assume, for example, that only the output signal on output line Z 7  of decoder 1 is &#34;1&#34; and the remaining outputs are all &#34;0&#34;. In this case, none of OR gates 278-285 receives a signal &#34;1&#34; and, therefore, an output &#34;0&#34; is developed on all of output lines Y 7  through Y 15 . OR gate 277 receives an signal &#34;1&#34; at its one input and, therefore, develops a output signal &#34;1&#34;, which is also applied as an input to OR gate 276. Thus, a signal &#34;1&#34; is applied to OR gates 275, 274, 273 and 272. Accordingly, a signal &#34;1&#34; is developed on each of output lines Y 1  through Y 6 . 
     As is understood from the above-described examples, many of conventional decoders 2 require a number of transmission gates or OR gates connected in series, which causes unstable operations or reduction in speed, as previously described. 
     FIG. 4 shows an embodiment of the present invention. A decoder 1 has the same configuration as decoder 1 shown in FIG. 2. Decoder 1 is responsive to a 4-bit binary code signal i applied through input lines L 1 , L 2 , L 3  and L 4 , and develops an output signal &#34;1&#34; only on the (i+1)-th bit one of sixteen output lines Z 1  through Z 16 . 
     For example, when an input value i is 6, a binary code &#34;0110&#34; is applied to decoder 1, with &#34;1&#34; on lines L 2  and L 3  and with &#34;0&#34; on lines L 1  L 4 , and a signal &#34;1&#34; is developed on the seventh ((6+1)-th) output line Z 7  and a signal &#34;0&#34; is developed on all of the remaining output lines of decoder 1. 
     Signals on the respective output lines of decoder I are applied to a decoder 2. Decoder 2 is segmented into four blocks 21, 22, 23 and 24. Signals on output lines Z 1  -Z 4  are applied to gates 201-204, respectively, in block 21, signals on output lines Z 5  -Z 8  are applied to gates 205-208, respectively, in block 22, signals on output lines Z 9  -Z 12  are applied to gates 209-212, respectively, in block 23, and signals on output lines Z 13  -Z 16  are applied to gates 213-216, respectively, in block 24. 
     In block 21, gates 201-204 and an auxiliary gate 221 are connected in series in the named order from a voltage supply to ground. Output lines Y 1 , Y 2 , Y 3  and Y 4  are derived from the junction between gates 201 and 202, from the junction between gates 202 and 203, from the junction between gates 203 and 204, and from the junction between gate 204 and auxiliary gate 221, respectively. 
     In block 22, an auxiliary gate 225, gates 205-208 and an auxiliary gate 222 are connected in series in the named order from the voltage supply to ground. Output lines Y 5 , Y 6 , Y 7  and Y 8  are derived from the junction between gates 205 and 206, from the junction between gates 206 and 207, from the junction between gates 207 and 208, and from the junction between gate 208 and auxiliary gate 222, respectively. 
     Similarly, in block 23, an auxiliary gate 226, gates 209-212 and an auxiliary gate 223 are connected in series in the named order from the voltage supply and ground. Output lines Y 9 , Y 10 , Y 11  and Y 12  are derived from the junction between gates 209 and 210, from the junction between gates 210 and 211, from the junction between gates 211 and 212, and from the junction between gate 212 and auxiliary gate 223, respectively. 
     Block 24 includes an auxiliary gate 227 and gates 213-216 connected in series in the named order from the voltage supply to ground, and output lines Y 13 , Y 14  and Y 15  are derived from the junction between gates 213 and 214, from the junction between gates 214 and 215, and from the junction between gates 215 and 216, respectively. 
     All of gates 201-216 and auxiliary gates 221, 222, 223, 225, 226 and 227 are enabled when a signal &#34;0&#34; is applied to inputs thereof, and are disabled when a signal &#34;1&#34; is applied to input thereof. Accordingly, in blocks 21-24, when one of the gates or auxiliary gates is disabled upon receiving an input signal &#34;1&#34;, a higher potential signal &#34;1&#34; is developed on all of the output lines lower in bit order (i.e. output lines shown in the upper side of that gate in the drawings) than the disabled gate, whereas a lower potential signal &#34;0&#34; is developed on all of the output lines higher in bit order (i.e. output lines shown in the lower side of the disabled gate in the drawings) than the disabled gate. 
     Auxiliary gates 221, 222, 223, 225, 226 and 227 are controlled by block control signals C 1 , C 2 , C 3 , C 1 , C 2  and C 3 , respectively, to determine the states of the blocks to which they belong. Block control signals are prepared by a block control signal generating circuit 3 from the most significant two bits of the binary input on input lines L 3  and L 4 . Signals on L 3  and L 4  are processed by a NOR gate 31 and a NAND gate 32 of block control signal generating circuit 3 to develop block control signals C 1  and C 3  respectively, which are further inverted by inverters 33 and 34 to develop block control signals C 1  and C 3 . 
     A signal on input line L 4  is used for it is as block control signal C 2  and further is inverted by an inverter 35 to produce block control signal C 2 . TABLE 1 in FIG. 1 shows the correspondence between the input value i and block control signals C 1 , C 2  and C 3 . 
     In FIG. 4, assuming that an input value i of 6 is applied, decoder 1 develops &#34;1&#34; on output line Z 7 . Since signals on L 3  and L 4  are &#34;1&#34; and &#34;0&#34; respectively, block control signals C 1 , C 2  and C 3  are &#34;1&#34;, &#34;0&#34; and &#34;0&#34;, respectively. 
     Due to C 1  =&#34;0&#34; and C 2  =&#34;0&#34;, auxiliary gates 225 and 222 at the ends of the series connection of gates in block 22 of decoder 2 are both enabled, and gate 207 is disabled by Z 7  =&#34;1&#34;. A higher potential signal &#34;1&#34; is developed on less significant bit output lines Y 5  and Y 6  than gate 207, where a lower potential signal &#34;0&#34; is developed on more significant bit output lines Y 7  and Y 8 . 
     In block 21 which is lower in order than block 22, since grounded gate 221 is disabled by C 1  =&#34;1&#34;, a signal &#34;1&#34; is developed on all of its output lines Y 1  -Y 4 . On the other hand, in blocks 23 and 24, which are higher in order than block 22, since voltage supply side auxiliary gates 226 and 227 are disabled by C 2  =&#34;1&#34; and C 3  =&#34;1&#34;, respectively, a lower potential signal &#34;0&#34; is developed on all of output lines Y 9  -Y 15 . 
     Thus, the block which receives a signal &#34;1&#34; from decoder 1 is activated by the block control signal applied thereto to operate to allot either a signal &#34;0&#34; or a signal &#34;1&#34; to output lines so that all the blocks lower in order than that block are forced by the block control signals applied thereto to produce a signal &#34;1&#34; on all of their output lines, whereas all the blocks higher in order than that block are forced by the block control signals applied thereto to produce a signal &#34;0&#34; on all of their output lines. 
     FIGS. 5(a), 5(b) and 5(c) show examples of circuits which may be used as gates 201-216 and auxiliary gates 221-223 and 225-227 shown in FIG. 4, which are transmission gates frequently used in CMOS ICs. Reference number 25 denotes an input terminal, and 26 and 27 denote output terminals. Reference number 28 denotes a P-channel MOS transistor, and 29 denotes an N-channel MOS transistor. Reference number 30 denotes an inverter. 
     FIG. 6 shows another embodiment of decoder 2 which can be used in the code conversion circuit shown In FIG. 4. 
     In block 21, gates 201, 202, 203 and 204 are connected in series in the named order from the voltage supply and ground. In a similar manner, in each of blocks 22, 23 and 24, a respective one of series connections of gates 205, 206, 207 and 208, gates 209, 210, 211 and 212, and gates 213, 214 and 215 is connected from the voltage supply and ground. Gates 204, 205, 208, 209, 212, 213 and 215 receive outputs of OR gates 231, 232, 233, 234, 235, 236 and 237, respectively. 
     Gates 201, 202 and 203 receive signals from output lines Z 1 , Z 2  and Z 3  of decoder 1, respectively. Gates 206 and 207 receive signals from output lines Z 6  and Z 7 , respectively. Output signals on lines Z 10  and Z 11  are respectively applied to gates 210 and 211. An output signal on line Z 14  is applied to gate 214. OR gate 231 receives an output from line Z 4  and block control signal C 1  ; OR gate 232 receives a block control signal C 1  and an output from line Z 5  ; OR gate 233 receives an output from line Z 8  and block control signal C 2  ; OR gate 234 receives an output from line Z 9  and block control signal C 2  ; OR gate 235 receives an output from line Z 12  and block control signal C 3  ; OR gate 236 receives an output from line Z 13  and block control signal C 3  ; and OR gate 237 receives an output from lines Z 15  and Z 16 . 
     Output lines Y 1 , Y 2 , Y 3 , Y 5 , Y 6 , Y 7 , Y 9 , Y 10 , Y 11 , Y 13  and Y 14  of decoder 2 are derived from between gates 201 and 202, from between gates 202 and 203, from between gates 203 and 204, from between gates 205 and 206, from between gates 206 and 207, from between gates 207 and 208, from between gates 209 and 210, from between gates 210 and 211, from between gates 211 and 212, from between gates 213 and 214, and from between gates 214 and 215 respectively. Block control signals C 1 , C 2  and C 3  are coupled respectively to output lines Y 4 , Y 8  and Y 12 , and output line Z 16  of decoder 1 is coupled to output line Y 15 . 
     Referring to FIG. 6, assume that an input value 6 is applied through lines L 1 , L 2 , L 3  and L 4  to decoder 1 (FIG. 4). This causes a signal &#34;1&#34; to be developed on line Z 7 . Block control signal generating circuit 3 (FIG. 4) provides block control signal C 1  =&#34;0&#34; which is applied to OR gate 232. Because an output on line Z 5  applied to OR gate 232 is also &#34;0&#34;, OR gate 232 produces &#34;0&#34; as an output. Gate 205 is enabled. Similarly because an output on Z 8  is &#34;0&#34; and C 2  =&#34;0&#34;, gate 208 is also enabled. However, because the output on line Z 7  is &#34;1&#34;, gate 207 is disabled. Consequently, in block 22, a signal &#34;1&#34; is developed on output lines Y 5  and Y 6 , and an output signal &#34;0&#34; is developed on line Y 7 . Since C 2  =&#34;0&#34;, the signal on output line Y 8  is also &#34;0&#34;. 
     In block 21, C 1  =&#34;1&#34; causes a signal &#34;1&#34; to be developed on line Y 4 . Gate 204 is disabled. Thus, a signal &#34;1&#34; is developed also on lines Y 1 , Y 2  and Y 3 . In block 23, because C 2  is &#34;1&#34;, gate 209 is disabled, a signal &#34;0&#34; is developed on each of output lines Y 9 , Y 10  and Y 11 . Furthermore, since C 3  is &#34;0&#34;, the signal on output line Y 12  is also &#34;0&#34;. In block 24, because of C 3  being &#34;1&#34;, gate 213 is disabled, and a signal &#34;0&#34; is developed on lines Y 13  and Y 14 . Since the signal on line Z 16  is &#34;0&#34;, a signal &#34;0&#34; is also developed on line Y 15 . 
     Thus, the same result as that obtained by decoder 2 of FIG. 4 is obtained from the code conversion circuit employing decoder 2 shown in FIG. 6. 
     FIG. 7 shows an alternative embodiment of decoder 2 which can be used in the code conversion circuit of FIG. 4. Decoder 2 of FIG. 7 includes OR gates rather than transmission gates. 
     In block 21, OR gates 240, 241 and 242 receive at one of their respective inputs output signals of decoder 1 (FIG. 4) through lines Z 2 , Z 3  and Z 4 , respectively. At the other input of respective OR gates 240, 241 and 242, an output of gate 241, an output of gate 242, and block control signal C 1  are applied. Outputs of OR gates 240, 241 and 242 are coupled to output lines Y 1 , Y 2  and Y 3 , respectively. Block control signal C 1  is coupled to output line Y 4 . 
     Blocks 22 and 23 are constructed similar to block 21, and include OR gates 243, 244 and 245, and OR gates 246, 247 and 248, respectively. Signals on lines Z 8 , Z 7  and Z 8  are coupled to a respective input of OR gates 243, 244 and 245 which receive at their respective other input, an output of OR gate 244, an output of OR gate 245, and block control signal C 2 . Outputs of OR gates 243, 244 and 245 are also coupled to output lines Y 5 , Y 8  and Y 7 , respectively. Block control signal C 2  is coupled to output line Y 8 . OR gates 246, 247 and 248 receive at their respective one inputs, signals on lines 210, Z 11  and Z 12 , and receive, at their respective other inputs, an output of OR gate 247, an output of OR gate 248 and block control signal C 3 . Outputs of OR gates 246, 247 and 248 are coupled to output lines Y 9 , Y 10  and Y 11 , respectively. Block control signal C 3  is coupled to output line Y 12 . 
     Block 24 includes OR gates 249 and 250. OR gate 249 receives a signal on line Z 14  and an output of OR gate 250. OR gate 250 receives signals on lines Z 15  and Z 16  at its respective inputs. Outputs of OR gates 249 and 250 are coupled to output lines Y 13  and Y 14 , respectively. The signal on line Z 16  is coupled to output line Y 15 . 
     In FIG. 7, assume that an input value i equal to 6 is applied to decoder 1 (shown in FIG. 4). This causes decoder 1 to develop a signal &#34;1&#34; only on line Z 7  and also causes block control signal generating circuit 3 (also shown in FIG. 4) to generate block control signals C 1  =&#34;1&#34;, C 2  =&#34;0&#34; and C 3  =&#34;0&#34;. Since the output signal &#34;1&#34; on line Z7 is applied to OR gate 244 in block 22, a signal &#34;1&#34; is developed on each of output lines Y 5  and Y 6 , but output lines Y 7  and Y 8  remain at &#34;0&#34;. 
     Because C 1  =&#34;1&#34; is applied to block 21, a signal &#34;1&#34; is developed on all of output lines Y 1 , Y 2 , Y 3  and Y 4 . In blocks 23 and 24, since all of input signals including block control signal C 3  are &#34;0&#34;, an output signal &#34;0&#34; is developed on all of output lines Y 9  through Y 15 . 
     FIG. 8 shows a decoder 2 which uses multiple-input OR gates. In block 21, block control signal C 1  is coupled to output line Y 4  and also to one input of each of OR gates 253, 252 and 251. Line Z 4  is coupled to OR gates 253, 252 and 251. Line Z 3  is coupled to OR gate 252 and 251, and line Z2 is coupled to OR gate 251. Outputs of OR gates 251, 252 and 253 are coupled to output lines Y 1 , Y 2  and Y 3  respectively. 
     Blocks 22 and 23 have a similar configuration to block 21. Block 22 includes OR gates 254, 255 and 256 to which lines Z 6 , Z 7  and Z 8  are respectively coupled. Block control signal C 2  is coupled to all of OR gates 254, 255 and 256 as well as to output line Y 8 . Line Z 7  is also coupled to OR gate 254, and line Z 8  is also coupled to OR gates 254 and 255. Outputs of OR gates 254, 255 and 256 are coupled to output lines Y 5 , Y 6  and Y 7  respectively. 
     Block 23 includes OR gates 257, 258 and 259 to which lines Z 10 , Z 11  and Z 12  are respectively coupled. Block control signal C 3  is coupled to all of OR gates 257, 258 and 259 as well as to output line Y 12 . Line Z 11  is also coupled to OR gate 257, and line Z 12  is also coupled to OR gates 257 and 258. Outputs of OR gates 257, 258 and 259 are coupled to output lines Y 9 , Y 10  and Y 11  respectively. 
     Block 24 includes two OR gates 260 and 261 to which lines Z 14  and Z 15  are respectively coupled. Line Z 15  is also coupled to an input of OR gate 260. Line Z 16  is coupled to OR gates 260 and 261 and also to output line Y 15 . Output lines Y 13  and Y 14  are derived from the outputs of OR gates 260 and 261, respectively. 
     The code conversion circuit employing decoder 2 shown in FIG. 8 operates in a similar manner to the circuit employing the decoder shown In FIG. 7. 
     FIG. 9 shows a code conversion circuit of a second type according to the present invention. The relationship between an input value i and the circuit outputs is as shown in TABLE 2 of FIG. 10. As is shown in FIG. 10, when an input value i is applied to a decoder 1 through input lines L 1  through L 4 , a signal &#34;1&#34; is developed on the decoder output line (i-1)-th from the most significant bit output line and on output lines higher in order than that. In other words, when an input value i is applied to decoder 1 in the binary form, a signal &#34;1&#34; is developed on the i most significant bit output lines of decoder 2. On the remaining output lines, a signal &#34;0&#34; is developed. 
     The configuration of the code conversion circuit shown in FIG. 9 is quite the same as that of the code conversion circuit shown in FIG. 4, except that output lines are derived from different locations than in FIG. 4. For example, the most significant bit output line Y 15  is derived from between gates 201 and 202, rather than from between gates 215 and 216, and the least significant bit output line Y 1  is derived from between gates 215 and 216 rather than from between gates 201 and 202. Specifically, output lines Y 15 , Y 14 , Y 13  and Y 12  are derived from between gates 201 and 202, from between gates 202 and 203, from between gates 203 and 204, and from between gate 204 and auxiliary gate 221 respectively; output lines Y 11 , Y 10 , Y 9  and Y 8  are derived from between gates 205 and 206, from between gates 206 and 207, from between gates 207 and 208, and from between gate 208 and auxiliary gate 222 respectively; output lines Y 7 , Y 6 , Y 5  and Y 4  are derived from between gates 209 and 210, from between gates 210 and 211, from between gates 211 and 212, and from gate 212 and auxiliary gate 223 respectively; and output lines Y 3 , Y 2  and Y 1  are derived from between gates 213 and 214, from between gates 214 and 215, and from between gates 215 and 216 respectively. 
     In operation, let it be assumed that an input value of 6 is applied to decoder 1. Decoder 1 develops a signal &#34;1&#34; only on its output line Z 7 , and block control signal generating circuit 3 generates block control signals C 1  =&#34;1&#34;, C 2  =&#34;0&#34; and C 3  =&#34;0&#34;. 
     Because of C 1  =&#34;0&#34; and C 2  =&#34;0&#34;, auxiliary gates 222 and 225 of block 22 are enabled, whereas gate 207 is disabled by the signal &#34;1&#34; on line Z 7 . Thus, a high level signal &#34;1&#34; is developed on output lines Y 10  and Y 11 , and a low level signal &#34;0&#34; is developed on output lines Y 8  and Y 9 . 
     In block 21, grounded gate 221 is disabled so that a high level signal &#34;1&#34; is developed on all of output lines Y 12  -Y 15 . In blocks 23 and 24, because to C 2  =&#34;1&#34; and C 3  =&#34;1, auxiliary gates 226 and 227 coupled to the voltage supply are disabled, whereby a low level signal &#34;0&#34; is developed on all of output lines Y 4  -Y 7  and all of output lines Y 1  -Y 3 . 
     Thus, as shown TABLE 2 in FIG. 10, an output signal &#34;1&#34; is developed on the output line Y 10  fifth (i.e. (6-1)-th) from the most significant bit output line Y 15  and also on all of the higher order output lines Y 11  -Y 15 . (In other words, a signal &#34;1&#34; is developed on each of the six most significant bit output lines Y 10  -Y 15 .) On all of the output lines Y 9  -Y 1  lower in bit order than output line Y 10 , a signal &#34;0&#34; is developed. 
     Reviewing the circuit shown in FIG. 9, it is seen that the circuit structure is the same as that of the circuit shown in FIG. 4, except that the numbering of the output lines from decoder 2 is opposite to each other. That is, in the circuit of FIG. 4, the less significant bit output side of decoder 2 is on the same side as the less significant bit output side of decoder 1, where the less significant bit output side of decoder 2 is on the more significant bit output side of decoder 1 in FIG. 9. Thus, there is no essential difference in operation between the circuits shown in FIGS. 4 and 9. 
     The present invention has been described in terms of circuits in which an input value i is applied in a four-bit binary code format, and decoder 2 is divided into four blocks. It should be noted, however, that the number of input bits and the number of blocks is optional. Block control signals, such as C 1 , C 2 , C 3  . . . , for controlling respective blocks of decoder 2 are prepared from the most significant bit of the input value i when the number of blocks is two, from the two most significant bits for four blocks as described above, from the three most significant bits for eight blocks, and from the four most significant bits for sixteen blocks. 
     FIG. 11 shows an embodiment of a circuit arrangement of block control signal generating circuit 3 for segmenting decoder 2 into two blocks. The most significant bit L 4  of the binary input is used as it is as a block control signal C 1 , and its inverted version C 1  prepared by an inverter 36 is used as another block control signal. 
     FIG. 12 shows an embodiment of block control signal generating circuit 3 for use with decoder 2 segmented into eight blocks. The most significant bit L a  is applied to a NOR gate 41, a NOR gate 42, the NOR section of an AND-NOR gate 43, an inverter 44, the NAND section of an OR-NAND gate 45, a NAND gate 46, and a NAND gate 47. The second significant bit L.sub..spsb.a-1 is applied to NOR gate 41, NOR gate 42, the AND section of AND-NOR gate 43, the OR section of OR-NAND gate 45, NAND gate 46 and NAND gate 47. The bit L.sub..spsb.a-2 is applied to NOR gate 41, the AND section of AND-NOR gate 43, the OR section of OR-NAND gate 45, and NAND gate 47. 
     Outputs from gates 41, 42, 43, 44, 45, 46 and 47 are block control signals C 1 , C 2 , C 3 , C 4 , C 5 , C 6  and C 7  respectively. These block control signals are inverted by inverters 51, 52, 53, 54, 55, 56 and 57 to produce block control signals C 1 , C 2 , C 3 , C 4 , C 5 , C 6  and C 7 . 
     FIG. 13 is block control signal generating circuit 3 for use with a decoder 2 segmented into sixteen blocks. The second significant bit signal L.sub..spsb.a-1 is applied to NOR gates 51, 61, NOR gates 52, 62, the NOR sections of AND-NOR gates 53, 63, inverters 54, 64, the NAND sections of OR-NAND gates 55, 65, NAND gates 56, 66, and NAND gates 57, 67. The third significant bit signal L.sub..spsb.-2 is applied to NOR gates 51, 61, NOR gates 52, 62, the AND sections of AND-NOR gates 53, 63, the OR sections of OR-NAND gates 55, 65, NAND gates 56, 66, and NAND gates 57, 67. The fourth significant bit signal L.sub..spsb.a-3 is applied to NOR gates 51, 61, the AND sections of AND-NOR gates 53, 63, the OR sections of OR-NAND gates 55, 65, and NAND gates 57, 67. 
     The arrangements of the group of gates 51-57 and the group of gates 61-67, and the connection of inputs L.sub..spsb.a-1, L.sub..spsb.a-2 and L.sub..spsb.a-3 to the gates groups are the same as the arrangements of gates 41-47 and the connections of inputs L a , L.sub..spsb.a-1, and L.sub..spsb.a-2 to gates 41-47 shown in FIG. 12. 
     Output from gates 51-57 are applied to NAND gates 71-77, respectively, and output from gates 61-67 are applied to NOR gates 81-87. NAND gates 71-77 and NOR gates 81-87 also receive the most significant bit signal L a  after it is inverted by an inverter 68. NAND gates 71-77 produce block control signals C 1  -C 7 , and NOR gates 81-87 produce block control signals C 9  -C 15 . As a block control signal C 8 , the most significant bit signal L a  may be used as it is, or a signal prepared by inverting the inverted version of L a  from inverter 68 may be used. 
     As described in detail above, according to the present invention, gates are divided into a plurality of blocks which are operated in parallel, so that the number of gates connected in series is reduced relative to conventional circuits. Accordingly, the circuit can operate with stability and at a higher operating speed.