Band-switchable, low-noise voltage controlled oscillator (VCO) for use with low-q resonator elements
BACKGROUND OF THE INVENTION 
     This invention relates generally to oscillators and more particularly to voltage controlled oscillators (VCO). 
     The generation of a sine wave of a given frequency is an important building block upon which many circuits are based. Examples of these circuits include radio receivers and transmitters employing mixers to translate the frequency of an information-bearing signal. There are two basic approaches to the design of sine wave generators. The first is to design a non-linear oscillator, which generates square or triangular waveforms, and apply the waveform to a sine wave-shaper, which usually consists of diodes and resistors. These non-linear oscillators are also referred to as function generators. The second approach employs a positive-feedback loop that contains a frequency-selective network. The loop is designed to have a gain of unity at a single frequency determinedly the frequency selective network. In this type of oscillator, called a &#34;linear oscillator,&#34; sine waves are generated essentially by a resonance phenomenon. This application deals with this latter approach. 
     An example of a linear oscillator is shown in FIG. 1A. The oscillator, shown generally at 10, includes a bipolar junction transistor (BJT) Q1 biased by a current source 12 and loaded by a load resistor R O . The oscillator includes a delay line 14 interposed between the load resistor and the collector of transistor Q1. The base of Q1 is then connected to an output terminal 16 thereby forming a loop with the delay line 14 and the collector to base junction of the Q1. The delay line 14 has a time delay or, alternatively, a wavelength, which is selected to correspond to one-half the period of oscillation of a sinusoidal voltage V O  produced on output terminal 16. The other one-half of the period is produced by inverter-connected transistor Q1, thus satisfying the oscillator criteria, i.e., unity gain and 360 degrees of phase shift. 
     Although discrete delay lines can be used as shown above, a more common approach is to use a L-C tank circuit such as shown in FIG. 2 to produce the delay. Oscillator 30 of FIG. 2 includes two inductors L 1  and L 2  and two varactors CR1 and CR2, though fixed capacitors can also be used in place of varactors if tuning is not required. The two L&#39;s and two C&#39;s form a single tank circuit having an equivalent inductance and equivalent capacitance. Varactors CR1 and CR2 are used in the tank circuit so that the frequency of oscillation can be modulated by a tuning voltage V TUNE  applied to control terminal 32. The variable capacitance of the varactors provides some fine-tuning of the oscillator frequency. The oscillator 30 is commonly referred to as a voltage controlled oscillator (VCO). 
     One limitation of the oscillator 30 is that the frequency of oscillation can only be tuned over a very small range because of the limitations of the varactors. The oscillator 40 shown in FIG. 3 overcomes the limitation of the tuning range of oscillator 30 by including multiple varactors CR1-CR3 that are switched into the oscillator circuit responsive to respective control currents I SW1  -I SW3 . Each varactor CR1-CR3 has a different nominal capacitance so as to provide a unique base frequency for the oscillator when that particular varactor is enabled by the corresponding control current. The varactors, therefore, each provide a unique frequency band of oscillation. The frequency of oscillation can then be tuned within that band by modulating the tuning voltage V TUNE  applied to a tuning input 42. With proper selection of the varactors, the oscillator 40 can provide a substantially continuous frequency range that greatly exceed that of oscillator 30 shown in FIG. 2. Conversely, a single varactor can be made to work in concert with a multiplicity of inductors to achieve the same result. 
     A characteristic of all of these oscillators is that their phase noise is only as good as the Q of the components that comprise the delay elements, i.e., the inductors and varactors. This presents a particular problem for integrated or monolithic circuits because it is difficult to achieve high Q inductors and varactors. For example, a typical on-chip inductor has a Q of approximately two to three, but a Q of approximately 50 is typically needed for adequate phase noise. Varactors have better Q&#39;s than inductors when formed on-chip, but are still inadequate for low phase noise. 
     An obvious solution is to provide these components in their discreet form and place them off-chip. There are several drawbacks to this approach. First is cost. The cost of providing additional external components adds to the expense of manufacturing the oscillator, not only in terms of direct materials costs, but also in terms of support and service, because of the added failures due to the manufacturing and placement of these additional parts. These additional components also consume precious real estate on a printed circuit board which may increase the form factor of the resultant product. 
     There are also mechanisms that compromise the Q of these off-chip solutions as well. The first is the interconnect bond wire resistance, which is a major contributor. Second is the external parasitics between the chip package and the external component. For the band switchable oscillator shown in FIG. 3, the resistance of switches (CR4, CR5, CR6) used to select the varactors appear in series with the varactors and therefore compromise the Q of those elements. For these reasons, a need remains for a fully integrated variable frequency oscillator with low phase noise. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the invention to overcome the limitations described above of prior art oscillators. 
     There are two aspects to the present invention. The first is a high-Q delay element that can be used in linear oscillators to improve their phase noise performance. The high-Q delay element according to the invention is made up of a plurality of individual delay sections. Although the Q of each section is not that high, when these sections are placed in series to form the delay element, the overall Q of the delay element increases proportional to the square root of the number of sections. In its most simple form, each section includes two parallel capacitors with an inductor connected therebetween. These capacitors can be made into varactors thereby allowing the delay of the element to be modulated in response to a control or tuning signal. These delay elements can then be used in any oscillator topology to provide the desired delay. 
     In the second aspect of the invention, several new oscillator topologies are discussed which provide for bandswitching, but that do not compromise the Q of the delay element as in the prior art. In particular, there is no additional resistance interjected into the signal path due to the switching element, because the transistor of the oscillator itself is used to perform the switching. In this new topology, a plurality of delay elements are connected in series. One of the delay elements has a delay that corresponds to the minimum frequency of oscillation. Each successive delay element has a delay, in the preferred embodiment, of only a fraction of this first delay. This fraction is chosen to correspond to the tunable range of the variable delay elements so that the oscillator has a substantially continuous frequency spectrum. 
     The topology is implemented in two basic forms. The first is a single-ended version. This version includes N delay elements connected in series and N transistors, each biased mutually exclusively by a current source. The collector of each transistor is connected to a node formed by the connection of two adjacent delay elements. The bases are connected together and to the output terminal of the oscillator to form N loops where each loop comprises a single collector-base junction and all of the delay elements between the collector of the respective transistor and the output terminal. Thus, each loop contains a unique combination of delay elements. A desired sine wave can then be generated by enabling the transistor of the corresponding delay combination. 
     A fully differential version of the invention is also described which includes a plurality (N in general) of cross-coupled transistor pairs such as that shown in FIGS. 1B and 2. Each cross-coupled pair has a pair of input terminals and an output terminal. A current source is coupled to the output terminals of the transistor pairs to provide a bias current to a desired one of the pairs in a mutually exclusive fashion based on the desired frequency of oscillation. A first one of the cross-coupled pairs (called the inner pair) has a first delay element connected by its respective input terminals. This delay element establishes the maximum frequency of oscillation when the first pair is enabled. A second pair of cross-coupled transistors is placed in parallel with the first pair and two additional delay elements are added. One of additional delay elements is connected between one of the output terminals of the second pair of transistors and a corresponding output terminal of the first pair. The other additional delay element is connected between the other output of the second pair of transistors and the corresponding output of the first pair. Each additional pair of cross-coupled transistors can be connected in a similar fashion to the adjacent pair until all N pairs of cross-coupled pairs are connected, which requires 2N-1 delay elements. The output terminals of the outermost pair forms the output terminals of the oscillator. 
     The differential version operates on the same basic principle as the single-ended version. Only one of the pairs is enabled at a time and the pair selected determines the frequency of oscillation of the circuit. In the preferred embodiment the first delay has a delay (t D ), which establishes the maximum frequency of oscillation (f MAX ). Each of the additional delays has only a fraction of the first delay (i.e., Δt D ). In this way fixed frequency bands can be selected by selecting the appropriate cross-coupled pair. Additional vernier tuning can be provided by using varactors to form the delay elements. The variability of the varactor capacitance can be chosen so as to span the frequency from one band to adjacent bands thereby providing a substantially continuous frequency spectrum of oscillation. 
    
    
     The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a schematic drawing of a prior art, single-ended oscillator. 
     FIG. 1B is a schematic drawing of a prior art, differential oscillator using only a single delay element. 
     FIG. 2 is a schematic drawing of a prior art differential oscillator using an L-C tank circuit. 
     FIG. 3 is a schematic drawing of a prior art, band-switchable oscillator. 
     FIG. 4 is a schematic drawing of a band-switchable single-ended oscillator according to the invention. 
     FIG. 5 is a schematic diagram of a band-switchable differential oscillator according to the invention. 
     FIG. 6 is a schematic drawing of the oscillator shown in FIG. 1B using a plurality of L-C sections according to the invention. 
     FIG. 7 is a schematic drawing of a second embodiment of a band-switchable differential oscillator according to the invention. 
     FIG. 8 is a schematic drawing of the band-switchable differential oscillator of FIG. 7 using a plurality of L-C sections according to the invention. 
     FIG. 9 is a schematic diagram of a tunable L-C delay section according to the invention. 
     FIG. 10 is a schematic diagram of a switchable current source that can be used in conjunction with the band-switchable oscillators according to the invention. 
     FIG. 11 is a block diagram of a switchable current source that can be used in conjunction with the band-switchable oscillators according to the invention. 
     FIG. 12 is a practical embodiment of a differential oscillator according to the invention. 
     FIG. 13 is a schematic drawing of a differential oscillator having quadrature outputs according to the invention. 
    
    
     DETAILED DESCRIPTION 
     Referring now to FIG. 4, a single-ended band-switchable oscillator according to the invention is shown generally at 50. The oscillator 50 includes three delay elements DL41, DL42 and DL43 connected in series. Although only three delay elements are shown, as will be apparent by the following description, the oscillator can be extended in general to include N delay elements. To simplify the drawing and the explanation, however, only three delay elements are shown. In the preferred embodiment, delay element DL41 has a delay t D  that corresponds to the maximum desired frequency of oscillation. The subsequent delay elements DL42 and DL43 each have a delay that is only a fraction (Δt D ) of the delay of the first delay element DL41. Each of these fractional delays forms a unique frequency band beneath the maximum frequency of oscillation established by the first delay element DL41. By selecting the delays in this manner, a plurality of fixed frequency bands can be formed. The first delay element DL41 also has an impedance Z 0  that is approximately equal to the impedance of a load resistor R L  connected between an output terminal 52 and a supply voltage rail V+. The impedances R L  and Z 0  are matched to minimize reflections from both ends of the line. 
     The oscillator 50 also includes three transistors Q41, Q42 and Q43. In the preferred embodiment, these transistors are bipolar junction transistors (BJT&#39;s), but the invention is not limited thereto. Each transistor is biased by a switchable current source that provides a bias current thereto responsive to a control signal received at the current source. Current source 58 is connected to the emitter of transistor Q41 and has a control input 60 to which a control signal V SW1  is applied. This control signal V SW1  turns the current source 58 either off or on depending upon the state of the signal. When the current source is on the current flows through the transistor Q41 thereby enabling the transistor. Similarly, a current source 62 is connected to the emitter of transistor Q42. The current source 62 also includes a control input 64 to which the control signal V SW2  is applied. The current source 62 operates in an identical manner to that to current source 58 except responsive to the control signal V SW2 . Likewise, transistor Q43 is selectively biased by current source 66 responsive to control signal V SW3  received on control input 68. 
     The collector of each transistor is connected to one or more of the delay elements. The collector of Q41 is connected to node 70 formed between delay elements DL41 and DL42; the collector of Q42 is connected to node 72 between delay elements DL42 and DL43; and the collector of Q43 is connected to node 74 formed by the connection of the collector and delay element DL43. The bases of the three transistors are connected together and further connected to output terminal 52 on which an output oscillator voltage signal V OUT  is produced. Capacitors C41, C42, and C43 provide AC return paths for Q41, Q42, and Q43, respectively. 
     The oscillator 50 operates as follows. Only one of the three transistors is turned on at any one time. The other transistors are turned off. The transistor that is turned on is determined by the desired frequency of oscillation. Once the transistor is turned on, a loop is formed with the transistor and one or more of the delay elements, depending on which transistor is turned on. For example, if transistor Q41 is turned on, and transistors Q42 and Q43 are turned off, a loop is formed with delay element DL41 and transistor Q41 acting as an inverting amplifier. The choice of emitter current, which sets the transconductance (gm) of Q41, and Z 0  (and hence R L ) combine to give a net gain around the loop of greater than unity. This satisfies one of the criteria for oscillator startup. The other condition, i.e., a net phase around the loop of 360 degrees, is met by the inverting characteristics of Q41 (180 degree phase shift) and the 180 degrees of phase shift due to the active delay line section. This selection causes the oscillator 50 to oscillate at its maximum frequency of oscillation, which is inversely proportional to twice the delay of the delay element DL41, i.e., f MAX  =1/2t D  (MIN). 
     If, on the other hand, transistor Q42 is turned on and transistors Q41 and Q43 are turned off, a loop is formed with delay elements DL41 and DL42 and transistor Q42 acting as an inverter. This produces a second frequency of oscillation corresponding to a delay equal to the sum of the delays of delay elements DL41 and DL42, i.e., t D  +Δt D . Thus, a new frequency is generated below the maximum frequency of oscillation which has a frequency of oscillation equal to 1/[2(t D  +Δt D )]. 
     Finally, if transistor Q43 is turned on or enabled and the other two transistors Q41 and Q42 are turned off, a new loop is formed with delay elements DL41, DL42 and DL43 and transistor Q43. Yet a third frequency of oscillation is produced thereby, which is inversely proportional to the sum of the delays of delay elements DL41, DL42 and DL43. It should be apparent that this topology can be extended in general to N delay elements to provide a plurality of frequency bands of oscillation. However, it is not necessary that the incremental delay of each additional stage be identical. As will be described further below, each of the delay elements can be tunable across its corresponding band to thereby provide a substantially continuous frequency spectrum for the oscillator. 
     Referring now to FIG. 5, another implementation of a band switchable oscillator according to the invention is shown generally at 80. The oscillator 80 uses the same basic topology in that a plurality of delay elements DL51-DLN are connected in series, each connected to a respective transistor Q51-QN, respectively. The ends of the line are terminated in a load R L  equal to Z 0 . A capacitor C31, however, closes the loop, allowing a DC potential to exist between VOUT and the base of Q55, while at the same time completing the loop in an AC sense. Capacitor C52, on the other hand, acts to establish an AC ground at the emitter of Q55. The operation of the transistors Q51-QN are mutually exclusive, i.e., only one is operational at a time. The transistors Q51-QN do not provide any phase shift as did the transistors Q41-Q43 of FIG. 4. Instead, transistors Q51-QN act solely to bypass the downstream delay elements. The necessary phase shift is provided by transistor Q55, which is biased by a current source 82 connected to the emitter thereof and a diode (or alternatively resistor) 86 connected between the supply rail voltage V+ and its base. A second current source 84 is also connected between the base of transistor Q55 and ground to ensure that diode 86 is maintained in its forward conduction operation. 
     The oscillator 80 includes a differential pair of outputs 88 and 90 across which a differential oscillator output signal (V OUT ) is produced. The frequency of oscillation of this signal is a function of which delay element or elements is currently in the loop. This is, in turn, determined by which of the plurality of transistors is enabled. The base of each transistor Q51-QN forms a control input to which a respective control signal (V SW1  -V SWN ) is applied. When the respective control signal is pulled to the positive supply rail, V+, and all others are held at a level at least 100 mv lower, the transistor forms an effective short thereby bypassing all of the downstream elements. For example, when control signal V SW1  is pulled high (i.e., asserted) and the other control signals V SW2  -V SWN  are pulled low (i.e., deasserted), transistor Q51 is turned on and transistors Q52-QN are turned off. By turning transistor Q51 on, node 92 is effectively shorted to output terminal 90. A loop is thus formed with the delay element DL51, the inverting amplifier transistor Q55 and capacitor C31. The delay of delay element DL51 determines the frequency of oscillation of the resulting oscillator signal, which is the maximum frequency signal of the oscillator 80 equal to f MAX  =1/2t D . 
     Similarly, if control signal V SW2  is asserted and control signals V SW1 , V SW3  -V SWN  are deasserted, transistor Q52 is turned on and transistors Q51, Q53-QN are turned off. This, in effect, takes transistors Q51, Q53-QN out of the circuit, because they are in a high impedance state. With transistor Q52 thus turned on, a loop is formed, in effect, with delay elements DL51 and DL52, transistor Q55 and the capacitor C31. Transistor Q52 is also included in the loop, however, its effect is minimal. Configured in this way, the oscillator 80 oscillates at a second frequency of oscillation, which is less than the first frequency of oscillation set by delay element DL51. In the preferred embodiment, the delay of each of the delay elements is equal so that the incremental changes in the frequency of oscillation are equal although this is not of fundamental importance to the operation of the device. The impedance of each is also approximately equal. As with oscillator 50 of FIG. 4, oscillator 80 can be extended in general to N delay elements (and corresponding bypass transistors) as indicated by the notation in FIG. 5 (i.e., DLN, QN, V SWN ). If only a single delay element (and corresponding bypass transistor) is used, the bypass transistor acts as a cascode transistor and the control signal (e.g., V SW1 ) simply acts to establish the correct bias. Each delay element can also be tunable to thereby provide a substantially continuous frequency spectrum. 
     Referring now to FIG. 6, another oscillator 100 according to the invention is shown. This oscillator includes a cross-coupled pair of transistors 104 such as that shown in FIG. 1B. The cross-coupled pair includes transistors Q61 and Q62 where the collector of each is connected to the base of the opposite transistor. The emitters are connected together to form a common emitter node 106 that is connected to a variable current source 102, which provides a tail current I TAIL  to the cross-coupled pair. 
     The oscillator 100 also includes an L-C circuit comprised of a plurality of L-C sections, together forming a lumped equivalent of delay line DLY in FIG. 1B. Each section includes two capacitors and an inductor connected therebetween. The L-C circuit shown in FIG. 6 includes four such L-C sections. The first section includes capacitor C61 and C62 with inductor L61 connected between the two capacitors. The ends of the capacitors opposite the inductors are connected to an AC ground node, i.e., the supply rail V+ in this case. The next section includes capacitors C62 and C63 with inductor L62 connected between the two capacitors. The other two sections are similarly configured. It should be apparent that each capacitor, with the exception of the outer-most capacitors (C61 and C65) are shared between two adjacent L-C sections. The effective impedance of the lumped-element line is given by the familiar relationship: ##EQU1## and the delay of each section is ##EQU2## The net delay is then Nt D , where N is equal to the number of sections (e.g., four). 
     At each end of the L-C circuit is a pair of termination resistors connected in series. A first pair R61 and R62 are connected in series between the supply rail V+ and a first output terminal 108. Each resistor, in the preferred embodiment, is approximately 25 ohms so as to provide a 50 ohm termination to the delay line, whose characteristic impedance is assumed to be 50 ohms. An additional capacitor C t1  is also connected in parallel with resistor R61. Similarly, a second pair of resistors R63 and R64 is connected in series between the supply rail V+ and a second output terminal 110. As with the other pair, the two resistors R63 and R64 form a 50 ohm output impedance. A capacitor C t2  is connected in parallel with resistor R63. The capacitors C t1  and C t2  form high-pass filters to roll off the network&#39;s response so oscillations will not occur at integer multiples of the fundamental frequency. 
     The advantage of using a delay line comprised of a plurality of L-C sections connected in series is that the effective Q of the L-C circuit increases with the square root of the number of L-C sections, which can be expressed as follows: ##EQU3## where n is equal to the number of L-C sections comprising the delay line; and Q SECTION  is equal to the Q of an individual L-C section. This is important since the Q of a typical integrated (on chip) inductor is only 3-6, or possibly 10 only with elaborate processing. 
     Thus, by using a plurality of sections, a low noise oscillator can be achieved on a monolithic circuit using existing process technology. The L-C sections can also be used in the band-switchable embodiments shown herein so as to increase the tuning range of the oscillator. 
     Referring now to FIG. 7, a band-switchable, low-noise oscillator is shown generally at 120. Oscillator 120 includes three cross-coupled pairs of transistors. The first pair includes transistors Q71 and Q72, the second includes transistors Q73 and Q74, and the third includes transistors Q75 and Q76. Although oscillator 120 is shown having three pairs of cross-coupled to transistors, as will become apparent below, the oscillator 120 can be extended in general to N pairs of cross-coupled transistors. 
     Each pair of cross-coupled transistors is connected to a respective switchable current source, which provides a current thereto responsive to a control signal supplied to the respective current source. These current sources 122, 124 and 126 operate in substantially the same manner as current sources 58, 62 and 68 described above with reference to FIG. 4. Accordingly, they are not discussed further. The first pair of cross-coupled transistors Q71 and Q72 includes a first collector node 128 connected to the collector of Q71 and the base of Q72. The pair also includes a second collector node 130 connected to the collector of Q72 and the base of Q71 thereby creating the cross-coupled relationship. The emitters of transistors Q71 and Q72 are connected to a common emitter node 132 that is connected to current source 122 to receive a switchable current therefrom responsive to the control signal V SW1 . A first delay element DL70 is connected between the two collector nodes 128 and 130. 
     Cross-coupled pair of transistors Q73 and Q74 similarly include a first collector node 134 connected to the collector of Q73 and the base of Q74 and a second collector node 136 connected to the collector of Q74 and to the base of Q73. The emitters of Q73 and Q74 are connected to a common emitter node 138, which is connected to a current source 124 to receive the switchable current therefrom responsive to the control signal V SW2 . A second delay element DL72 is connected between the first collector nodes 128 and 134 of the first and second pairs of cross-coupled transistors, respectively. Similarly, a third delay element DL71 is connected between the second collector nodes 130 and 136 of the first and second pairs of cross-coupled transistors, respectively. 
     The oscillator 120 further includes a third pair of cross-coupled transistors Q75 and Q76. The third pair includes a first collector node 140 connected to the collector of Q75 and the base of Q76 and a second collector node 142 connected to the collector of Q76 and to the base of Q75. The third pair also includes a common emitter node 144 connected to both emitters and to the third current source 126. A fourth delay element DL74 is connected between the first collector nodes 134 and 140 of the second and third pairs of cross-coupled transistors, respectively. Similarly, a fifth delay element DL73 is connected between the second collector nodes 136 and 142 of the second and third pairs of cross-coupled transistors, respectively. 
     Also connected to the first collector node 140 is a first load resistor R L1 , which is connected between the node 140 and the supply rail V+. On the opposite side of the oscillator, a second load resistor R L2  is connected between the supply rail V+ and the second collector node 142. Collector nodes 140 and 142 therefore form a differential output of the oscillator 120 across which a differential oscillator signal is generated. 
     The oscillator 120 switches between bands in much the same way as the oscillator in FIG. 4. If the first pair of cross-coupled transistors Q71 and Q72 are activated by enabling the corresponding current source 122, the other two pairs are disabled by deasserting the corresponding control signals. Once the first pair is activated, the gain of the cross-coupled pair (the transconductance) operates into the delay line impedance Z 0  and establishes a net gain around the loop in excess of unity. Likewise, the phase inversion through the cross-coupled pair and the time delay of DL70 combine to produce a net 360 degree phase change around the loop. Together the gain and phase satisfy the starting conditions for an oscillator. As the amplitude of oscillation increase, a point is reached at which the swing at the collectors limits and a steady-state condition is established wherein the average gain over the period of one cycle is unity in the presence of a net phase shift of 360 degrees around the loop. 
     At steady-state, an output signal is generated across nodes 140 and 142, which has a frequency of oscillation inversely proportional to twice the delay of the delay element DL70. Even though the oscillation signal is generated across collector nodes 128 and 130, the signal propagates out through the other (equal) delay elements to the nodes 140 and 142 in a symmetrical fashion. If the impedance of the delay element DL70 is chosen to be approximately equal to that of the load resistors R L1  and R L2 , there will be little-to-no reflection. Note that the signals at nodes 140 and 142 maintain a 180 degree phase relationship, even though separated in time from 128 and 130. 
     If the middle pair of cross-coupled transistors is turned on and the other two pairs are turned off, the frequency of the output signal of the oscillator is inversely proportional to twice the sum of the delays of delay elements DL70, DL71 and DL72 because it is these elements that are now inside the loop formed with the second pair of cross-coupled transistors. The final case, where the third pair of cross-coupled transistors Q75 and Q76 are turned on and the first and second pair are turned off, all of the delay elements DL70-DL74 are included in the loop. Therefore, the oscillator has a frequency of oscillation that is inversely proportional to the twice sum of the delays of all the delay elements (t DL70-DL74 ). In the preferred embodiment, the first delay element DL70 is chosen to correspond to the maximum frequency of oscillation. Each of the remaining delays (DL71-DL74) have only a fraction of the delay of the first delay element (Δt D ). In that case, the frequency of oscillation can be expressed in terms of these two delays as a function of the control signals as shown in the table below. 
     
                       TABLE 1                                                     
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Oscillator frequency as a function of                                     
switch setting.                                                           
V.sub.SW1 V.sub.SW2                                                       
                   V.sub.SW3                                              
                          FREQUENCY                                       
______________________________________                                    
ON        OFF      OFF    1/(2 × t.sub.D)                           
OFF       ON       OFF    1/[2 × (t.sub.D + 2Δt.sub.D)]       
OFF       OFF      ON     1/[2 × (t.sub.D + 4Δt.sub.D)]       
OFF       OFF      OFF    0                                               
______________________________________                                    
 
    
     Referring now to FIG. 8, a tunable version of the oscillator 120 is shown. The delay elements have been replaced with L-C circuits according to the topology of FIG. 6, with the additional use of varactors in place of fixed capacitors which allow the oscillator&#39;s frequency to be tuned responsive to a tuning signal V TUNE  applied to a tuning input 150. Delay element DL70, as described above, is comprised of a plurality (n) of L-C sections. This raises the Q of the overall L-C circuit over the individual L-C sections by a factor of the square root of n. Each of the other delay elements will generally only include a single L-C section comprised of two varactors in parallel with an inductor connected therebetween, though the use of more than one L-C section in the switched delay elements may be advantageous in some applications and is certainly allowed by the topology. All of the varactors are connected to the tuning input 150 to receive the tuning voltage. The varactors are chosen so that the oscillator can be tuned from one frequency band to the next by adjusting the tuning voltage through its entire tuning range. Thus, the oscillator shown in FIG. 8 provides both low-phase noise and a substantially continuous frequency spectrum. The tunable oscillator of FIG. 8 operates in substantially the same manner as does the oscillator of FIG. 7 and will therefore not be described further. 
     Another embodiment of an L-C section capable of being used in the oscillator of FIG. 7 is shown in FIG. 9. The L-C section shown generally at 160 includes two parallel branches, where each branch includes a fixed capacitor C F  in series with a varactor C V . An inductor L F  is connected between the two fixed capacitors at the opposite sides of the inductor to form the input nodes of the L-C section to which adjacent L-C sections are connected. A tuning node 162 is connected to the center points of the two branches via two identical resistors R. The tuning voltage V TUNE  is then applied to this tuning node to vary the capacitance of the varactors and thereby tune the frequency of the oscillator. For lower noise, resistors R may be replaced with inductors which offer low DC-resistance but a high impedance at the oscillator frequency. 
     Referring now to FIG. 10, a different embodiment of a switchable current source capable of being used in conjunction with the oscillators according to the invention is shown. The current sources that drive either the individual transistors in the single ended versions (FIG. 4) or the pairs of cross-coupled transistors in the differential versions (FIGS. 7-8) are shown above as individual current sources each having a unique control signal for actuating that current source. The current sources need not be implemented in that way. Because only a single current is required for any given frequency, a single current source can be used, which can be multiplexed between the various transistors or pairs of transistors, whichever the case may be. An example of this approach is shown in FIG. 10 where only two transistors or two pairs of transistors (for the differential case) are required. In this case, a resistor R14 is connected between a switch 172 and a negative supply voltage rail V EE . This forms a rudimentary current source. The switch 172 switches between two outputs 174 and 176 responsive to a control signal V SW  applied to a control input 178. The control input 178 is connected to a select input 180 of the switch 170. The state of the signal appearing on the select input 180 causes the switch to move between one of the two switch positions. Thus, switch 172 operates as a multiplexer. An oscillator using this switchable current source is shown in FIG. 12. This approach can be extended in general to N stages as shown in FIG. 11. The number of control signals required to select one of N is equal to log 2  N as is known in the art. 
     Another embodiment of an oscillator according to the invention is shown in FIG. 13. The oscillator 200 produces a differential sinusoidal output voltage (V O , V 180 ) on two output terminals 202 and 204. The oscillator includes a pair of transistors Q85 and Q86 whose emitters are connected to a current source 206, which provides a tail current thereto. Instead of a single delay line as in FIG. 1A, the oscillator 20 includes two delay lines 208 and 210. Delay line 208 is connected between output terminal 202 and the collector of transistor Q86 while the delay line 210 is connected between output terminal 204 and the collector of transistor Q85. A respective resistor is connected between the supply rail V+ and the base of each transistor. Assuming each delay line has an equal delay (t D ), the frequency of oscillation is equal to the reciprocal of two times the delay through each delay line, i.e., f OUT  =1/2t D . An advantage of this topology is the ability to generate a quadrature version (V 90 , V 270 ) of the sinusoidal output. If the delay lines have taps at the midpoint of the delay, the quadrature version of the sinusoidal output signal can be produced. The delay lines can be implemented using any of the delay designs described above. In addition, the oscillator can be made band-switchable using the topologies described above. 
     Having described and illustrated the principles of the invention in a preferred embodiment thereof, it should be apparent that the invention can be modified in arrangement and detail without departing from such principles. Although the delay elements are described above to include a plurality of L-C sections in the preferred embodiment, the delay elements can take a variety of forms in the topologies described herein. For example, the delay elements can take the form of microstrips or even discrete delay lines. Moreover, the invention is not limited to bipolar junction transistors. Rather, equivalent versions of the oscillators can be constructed using MOS and junction field effect transistors, gallium arsenide transistors and a variety of other transistors in place of the bipolar junction transistors described above. I claim all modifications and variation coming within the spirit and scope of the following claims.