Intermediate voltage sensor for CMOS circuits
FIELD OF THE INVENTION 
     The present invention relates generally to an intermediate voltage sensor for use in a CMOS circuit, and more particularly to a built-in intermediate voltage sensor for the CMOS circuit. 
     BACKGROUND OF THE INVENTION 
     The conventional testing method for detecting a fault of a digital circuit is based on logic testing, in which the output logic values of a circuit under test are observed. Such a conventional testing method as described above is incapable of detecting an intermediate fault of the CMOS circuit at such time when the output voltage value is intermediate between V DD  (logic 1) and GND (logic 0). 
     According to a technical proposal disclosed by C. F. Hawkins, et al in their research paper entitled &#34;Quiescent Power Supply Current Measurement for CMOS IC Defect Detection&#34; and published in the May, 1989 issue of IEEE Trans. on Industrial Electronics, such an intermediate fault as described above can be defected by the I DDQ  current testing method, which is used in conjunction with some automatic testing equipment (ATE) or built-in current sensors (BICS). However, the employment of automatic testing equipment can result in a substantial reduction in the testing speed and the sensing resolution of the measurable current. On the other hand, the employment of the built-in current sensors can undermine seriously the performance of the circuit under test unless the expensive BiCMOS or dual power supply technique is used. Moreover, the task of designing the CMOS circuits must be carried out in accordance with a specific set of designing rules so as to enable the CMOS circuits to be tested for an intermediate fault by the I DDQ  testing method. It must be noted here that the specific set of designing rules is implemented at the expense of the design feasibility of the CMOS circuits. 
     Another method for testing the intermediate voltage fault was disclosed by G. G. Freeman, et al in their research paper entitled &#34;Two CMOS Metastability Sensors&#34; and published in the 1986 Proceedings of the International Test Conference. This method is based on the theory that the metastability brings about intermediate voltages, which can be therefore detected by the metastability sensors. However, the implementation of the metastability method calls for the employment of a number of complementary input signals. As a result, the metastability method can undermine seriously the performance of the circuit under test. 
     SUMMARY OF THE INVENTION 
     It is therefore the primary objective of the present invention to provide an intermediate voltage sensor for CMOS circuits, which is capable of a high-speed testing. 
     It is another objective of the present invention to provide an intermediate voltage sensor for CMOS circuits, which can be made economically. 
     It is still another objective of the present invention to provide an intermediate voltage sensor for CMOS circuits, which does not interfere adversely and seriously with the performance of the circuit under test. 
     In keeping with the principles of the present invention, the foregoing objectives of the present invention are attained by three preferred embodiments, which are merely illustrative and not restrictive. 
     According to a first preferred embodiment of the present invention, the intermediate voltage sensor for CMOS circuits comprises a linear invertor, a first voltage control switch, a second voltage control switch, and a buffer. 
     The linear inverter has an input end which is connected with an input signal under test. The linear inverter further has an output end. 
     The first voltage control switch has a control end and an input end, which are connected respectively with the input end and the output end of the linear inverter. The first voltage control switch further has an output end. 
     The second voltage control switch has a control end and an input end which are connected respectively with the output end and the input end of the linear inverter. The second voltage control switch further has an output end. 
     Being opposite in characteristic to the linear inverter, the buffer has an input end which is connected with the output end of the first voltage control switch and the output end of the second voltage control switch. 
     When the voltage of the input signal under test is a logic value &#34;0&#34; or &#34;1&#34;, a first logic voltage is delivered by the buffer. However, when the voltage of the input signal under test is of an intermediate nature, a second logic voltage, which is different from the first logic voltage, is given forth by the buffer. 
     When the voltage of the input signal under test has a logic value &#34;0&#34; or &#34;1&#34;, either the first voltage control switch or the second voltage control switch is connected, depending on which input end has a voltage of logic &#34;0&#34;. As a result, the input voltage and the output voltage of the buffer will remain in the state of logic &#34;0&#34;. On the other hand, when the voltage of the input signal under test has a logic value which is intermediate between &#34;0&#34; and &#34;1&#34;, the inputs and outputs the first voltage control switch and the second voltage control switch will not remain in the state of logic values &#34;0&#34;. Thereafter, a voltage of logic &#34;1&#34; is given forth by the buffer which has a precipitous switching characteristic. 
     It is suggested that the first and the second voltage control switches of the intermediate voltage sensor of the first preferred embodiment of the present invention are preferably MOS transistors, 
     An intermediate voltage sensor of the second preferred embodiment of the present invention comprises a first linear inverter, a second linear inverter, a voltage control switch, and a buffer. 
     The first linear inverter has an input end which is intended to connect with an input signal under test. The first linear inverter further has an output end. 
     The second linear inverter has an input end which is connected with the output end of the first linear inverter. 
     The voltage control switch has a control end, an input end, and an output end. The control end and the input end are connected respectively with the input end of the first linear inverter and the output end of the second linear inverter. 
     Being opposite in characteristic to the first and the second linear inverters and having a precipitous switching characteristic, the buffer has an input end which is connected with the output end of the voltage control switch. 
     When the voltage of an input signal under test has a logic value &#34;0&#34; or &#34;1&#34;, a first logic voltage is given forth by the buffer: When the voltage of the input signal under test is a fault capable of bringing about an intermediate voltage value, a second logic voltage, which is different from the first logic voltage, is given forth by the buffer. 
     The voltage control switch of the intermediate voltage sensor of the second preferred embodiment of the present invention can be a negative logic voltage control switch, such as the MOS transistor or more preferably the PMOS transistor. 
     When the voltage of the input signal under test of the second preferred embodiment of the present invention has a logic value &#34;1&#34;, the voltage control switch remains in an &#34;open&#34; state so as to enable the buffer to have an input or output voltage having a logic value &#34;0&#34;. On the other hand, when the voltage of the input signal under test has a logic value &#34;0&#34;, the output voltages of the first inverter and the second inverter have respectively a logic value &#34;1&#34; and a logic value &#34;0&#34;. The voltage control switch remains in a &#34;short&#34; state so as to enable the buffer to have an input or output voltage having a logic value &#34;0&#34;. When the voltage of the input signal under test has a logic value which is intermediate between logic &#34;0&#34; and logic &#34;1&#34;, the output voltages of the first inverter and the second inverter do not remain respectively in a logic &#34;0&#34; state and a logic &#34;1&#34; state. Thereafter, a voltage having the logic &#34;1&#34; is given forth by the buffer which has a precipitous switching characteristic. 
     The voltage control switch of the intermediate voltage sensor of the second preferred embodiment of the present invention is preferably the MOS transistor. 
     An intermediate voltage sensor for CMOS circuits of the third preferred embodiment of the present invention comprises a first positive logic voltage control switch, an inverter, a first negative logic voltage control switch, and a buffer. 
     The first positive logic voltage control switch has a control end which is connected with an input signal under test. The first positive logic voltage control switch further has an output end. 
     The inverter has an input end which is connected with the output end of the first positive logic voltage control switch. 
     The first negative logic voltage control switch has an input end and a control end which are connected respectively with the output end of the inverter and the input signal under test. 
     The buffer is provided with a precipitous switching characteristic. The buffer has an input end which is connected with the output end of the first negative logic voltage control switch. 
     When the voltage of the input signal under test is in the logic &#34;0&#34; or &#34;1&#34; state, a first logic voltage is given forth by the buffer. However, when the voltage of the input signal under test is of an intermediate nature, a second logic voltage is given forth by the buffer. 
     The intermediate voltage sensor of the third preferred embodiment of the present invention further comprises a second negative logic voltage control switch and a second positive logic voltage control switch. 
     The second negative logic voltage control switch has a control end and an input end, which are connected respectively with a negative logic test signal (TEST) and a power supply signal (V DD ). The second negative logic voltage control switch further has an output end which is connected with the input end of the inverter for providing the input end of the inverter with a precharged potential. 
     The second positive logic voltage control switch has a control end and an input end, which are connected respectively with a positive logic test signal (TEST) and a ground end. The second positive logic voltage control switch further has an output end, which is connected with the input end of the buffer for providing the input end of the buffer with a predischarged potential. 
     The second negative logic voltage control switch and the second positive logic voltage control switch of the intermediate voltage sensor of the third preferred embodiment of the present invention are intended respectively for use in precharging a potential (V 01 ) of the input end of the inverter and predischarging a potential (V 03 ) of the input end of the buffer. The first positive logic voltage control switch and the first negative logic voltage control switch are used to sense the input signal under test. Before the input signal is to be sensed, the &#34;TEST&#34; signal must be set at logic &#34;1&#34;. In other words, the intermediate voltage sensor of the present invention is set at the setup phase, in which the potentials (V 01  and V 03 ) are preset respectively at logic &#34;1&#34; and logic &#34;0&#34;. The &#34;TEST&#34; signal is then set at logic &#34;0&#34; so as to set the intermediate voltage sensor of the present invention at the evaluation phase. If the voltage of the input signal is logic &#34;1&#34;, the potential V 03  will approach logic &#34;0&#34; in view of the fact that the first negative logic voltage control switch is turned off. As a result, the values of both input voltage and output voltage of the buffer are logic &#34;0&#34;. On the other hand, if the voltage value of the input signal to be sensed is logic &#34;0&#34;, the potential V 01  is kept at logic &#34;1&#34; in view of the fact that the first positive logic voltage control switch is turned off. The values of both input voltage and output voltage of the buffer can be set at logic &#34;0&#34; by setting the potential (V 02 ) of the output end of the inverter at logic &#34;0&#34;. When the voltage value of the input signal to be sensed is intermediate between logic &#34;0&#34; and logic &#34;1&#34;, the first positive logic voltage control switch and the first negative logic voltage control switch will not be in the logic &#34;0&#34; state and the logic &#34;1&#34; state simultaneously. As a result, the potential V 01  is pulled low while the potentials V 02  and V 03  are pulled high. A voltage having logic &#34;1&#34; is thus given forth by the buffer which has a precipitous switching characteristic. 
     Preferably, the buffers referred to above in three preferred embodiments of the present invention are composed of two CMOS circuits which are connected in series. In the meantime, the first logic and the second logic values are designated respectively as &#34;0&#34; and &#34;1&#34; 
     The intermediate voltage sensor for CMOS circuits of the present invention has inherent advantages, which are described explicitly hereinafter. 
     The sensor of the present invention is capable of a high-speed detection of intermediate faults and is further capable of delivering a sensed result within 4.21 ns. In addition, the sensor of the present invention is so simple in construction that the sensor takes up a relatively small space of an integrated circuit into which the sensor of the present invention is incorporated. Furthermore, the sensor of the present invention has the least performance impact on the circuit under test and further has special limitations in the design of the circuit which is not under test. 
     The foregoing objectives, features, functions and advantages of the present invention will be more readily understood upon a thoughtful deliberation of the following detailed description of the embodiments of the present invention in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a circuitry of the intermediate voltage sensor for CMOS circuits of the first preferred embodiment of the present invention. 
     FIG. 2 shows a circuitry of the intermediate voltage sensor for CMOS circuits of the second preferred embodiment of the present invention. 
     FIG. 3 shows a circuitry of the intermediate voltage sensor for CMOS circuits of the third preferred embodiment of the present invention. 
     FIG. 4 shows a functional scheme of the linear inverter which is suitable for use in the present invention. 
     FIG. 5 shows a functional scheme of the buffer which is suitable for use in the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     As shown in FIG. 1, a built-in intermediate voltage sensor (BIVS1) of the first preferred embodiment comprises the component parts which are described explicitly hereinafter. 
     A linear inverter has an input end for receiving an input signal under test and further has an output end. 
     A first positive logic voltage control switch, which is made of the MOS transistor or preferably the NMOS transistor, has an input end, an output end, and a control end. The input end is connected with the output end of the linear inverter while the control end is intended for receiving the input signal under test. 
     A second positive logic voltage control switch, which is made of the MOS transistor or preferably the NMOS transistor, has an input end, an output end, and a control end. The input end serves to receive the input signal under test while the control end is connected with the output end of the inverter. 
     A buffer has an input end which is connected with the output end of the first positive logic voltage control switch and the output end of the second positive logic voltage control switch. The buffer is capable of delivering an output. 
     As shown in FIG. 4, the linear inverter comprises a NMOS transistor and a load which is made up of a PMOS transistor. Both the gate and the drain of the PMOS transistor are connected directly with the drain output end of the NMOS transistor. The inverter has a linear switching characteristic, which is less precipitous. The relationship of the input and the output of the inverter can be expressed by the equation of V out  =V DD  -V IN , in which V IN  stands for the input voltage; V out , the output voltage; and V DD , the power supply voltage 
     When the voltage V G  has logic &#34;0&#34;, the positive logic voltage control switch is almost in the open state. On the other hand, when the voltage V G  has logic &#34;1&#34;, the positive logic voltage control switch is almost in the short state. V G  stands for the input voltage of the control end of the positive logic voltage control switch, namely, the gate voltage of the MOS transistor. 
     As shown in FIG. 5, the buffer is made up of two CMOS circuits, which are connected in series and with gates being reversed. The buffer has a precipitous linear switching characteristic. 
     The buffer is intended to accelerate the sensing speed and to promote the voltage swing. When V IN  is greater than V MiD , the voltage V out  has logic &#34;1&#34;. On the other hand, when V IN  is smaller than V MID , the voltage Vout has logic &#34;0&#34;. V IN  stands for the input voltage of the buffer; V out , the output voltage of the buffer; and V MID , the intermediate voltage located between logic &#34;0&#34; and logic &#34;1&#34;. 
     As shown in FIG. 1, when the voltage value of an input signal under test is logic &#34;0&#34; or logic &#34;1&#34;, the voltage control switch having the input end voltage value of logic &#34;0&#34; is turned on via the inverter so as to cause the input end and the output end of the buffer to have respectively the voltage value of logic &#34;0&#34;. When the voltage value of the sensing input end is intermediate between logic &#34;0&#34; and logic &#34;1&#34;, both voltage control switches will remain in a state intermediate between logic &#34;0&#34; and logic &#34;1&#34;. A voltage having the value of logic &#34;1&#34; is then given forth by the buffer which has a precipitous switching characteristic. 
     As illustrated in FIG. 2, a built-in intermediate voltage sensor (BIVS2) for CMOS circuits of the second preferred embodiment of the present invention comprises a first linear inverter, a second linear inverter, a negative logic voltage control switch, a load impedance, and a buffer. 
     The first linear inverter is made up of transistors AP and AN and is provided with an output end and an input end, The input end is used to connect with the input end of an input signal under test. 
     The second linear inverter is made up of transistors BP and BN and is provided with an output end and an input end. The input end is connected with the output end of the first linear inverter. 
     The negative logic voltage control switch is composed of PMOS transistor designated as CP. This control switch has an input end which is connected with the output end of the second linear inverter. The control switch further has a control end intended for use in receiving the input signal under test. 
     The load impedance is made up of a transistor CN and is connected at one end thereof with the output end of the negative logic voltage control switch. The load impedance is further connected at another end thereof with ground (GND). 
     The buffer has an input end which is connected with the output end of the negative logic voltage control switch and one end of the load impedance. The buffer is capable of giving forth an output. 
     The inverters of the BIVS2 are similar in function to the inverter of the BIVS1. 
     When the value of the input voltage V G  of the control end of the negative logic voltage control switch is logic &#34;0&#34;, the negative logic voltage control switch is almost in a short state. It must be noted here that the control end input voltage V G  is corresponding to the gate voltage of the MQS transistor. 
     The load impedance has an electrical characteristic similar to a resistance. 
     The buffer of the BIVS2 is similar in function to the buffer of the BIVS1. 
     As illustrated in FIG. 2, when the voltage value of an input signal under test is logic &#34;1&#34;, the negative logic voltage control switch CP remains in an open state so as to cause the input voltage and the output voltage of the buffer to have the value of logic &#34;0&#34;. When the voltage value of the input signal is logic &#34;0&#34;, the outputs of the first inverter and the second inverter are respectively in the logic &#34;1&#34; state and the logic &#34;0&#34; state. In the meantime, the negative logic voltage control switch CP is kept in a short state so as to cause the input voltage and the output voltage of the buffer to have the value of logic &#34;0&#34;. When the voltage value of the input signal is intermediate between logic &#34;0&#34; and logic &#34;1&#34;, the output voltage values of the first inverter and the second inverter are also in the intermediate state. The negative logic voltage control switch CP is almost in a short state. An output voltage having the value of logic &#34;1&#34; is thus delivered by the buffer which has a precipitous switching characteristic. 
     As shown in FIG. 3, a built-in intermediate voltage sensor (BIVS3) of the third preferred embodiment of the present invention comprises the component parts, which are described explicitly hereinafter. 
     A third positive logic voltage control switch is made up of a transistor AN and is provided with an input end which is connected with ground (GND). The third positive logic voltage control switch is further provided with an output end and a control end which is used to receive a negative logic TEST signal. 
     A first positive logic voltage control switch is made up of the NMOS transistor designated as BN. The first positive logic voltage control switch is provided with an output end, an input end which is connected with the output end of the third positive logic voltage control switch, and a control end which is used to receive an input signal under test. 
     A second negative logic voltage control switch is made up of the PMOS transistor designated as AP. The control switch AP is provided with an output end, and input end which is connected with the power source(V DD ), and a control end which is used to receive the negative logic TEST signal. 
     An inverter is provided with an output end and an input end which is connected with the output end of the first positive logic voltage control switch and the output end of the second negative logic voltage control switch. 
     A first negative logic voltage control switch is made up of the PMOS transistor, which is designated as BP. This control switch BP has an output end, an input end which is connected with the output end of the inverter, and a control end which is connected with the input signal. 
     A second positive logic voltage control switch is made up of the NMOS transistor designated as CN, The control switch CN has an output end, an input end which is connected with ground (GND), and a control end which is used to receive a positive logic TEST signal. 
     A buffer has an input end which is connected with the output end of the first negative logic voltage control switch and the output end of the second positive logic voltage control switch. The buffer is capable of giving forth an output. 
     Being opposite in characteristic to the linear inverter of the BIVS1 of the present invention, the inverter of the BIVS3 has a much more precipious switching characteristic that a common CMOS inverter has. The positive logic voltage control switch of the BIVS3 is similar in function to that of the BIVS1 of the present invention. The negative logic voltage control switch of the BIVS3 is similar in function to that of the BIVS2 of the present invention. The buffer of the BIVS3 is similar in function to that of the BIVS1 of the present invention. 
     As shown in FIG. 3, the transistors AP and CN are used to precharge and predischarge the potentials of V 01  and V 03  while the transistor AN is intended to isolate V 01  so as to prevent the grounding from taking place when the precharging is under way. The transmission transistors BN and BP are used to sense the input signal under test. Before the process of sensing the input signal under test is initiated, the TEST signal must be first set at logic &#34;1&#34; so as to enable the sensor of the present invention to phase into an initialization phase, in which V 01  and V 03  are initialized to logic &#34;1&#34; and logic &#34;0&#34;, respectively. Thereafter, the TEST signal is set at logic &#34;0&#34; so as to enable the sensor of the present invention to phase into an evaluation phase. If the voltage value of the input signal is logic &#34;1&#34;, the transistor BP is turned off so as to cause V 03  to remain at logic &#34;0&#34;. As a result, the values of the input voltage and the output voltage of the buffer are logic &#34;0&#34; respectively. If the voltage value of the input signal is logic &#34;0&#34;, the transistor BN is turned off so as to cause V 01  to remain at logic &#34;1&#34;. In the meantime, V 02  is set at logic &#34;0&#34; via the inverter so as to cause the input voltage and the output voltage of the buffer to have respectively the value of logic &#34;0&#34;. When the voltage value of the sensed input end is intermediate between logic &#34;0&#34; and logic &#34;1&#34;, the two voltage control switches (transistors BN and BP) are in an intermediate state between logic &#34;0&#34; and logic &#34;1&#34;. As a result, V 01  is pulled down while V 02  and V 03  are pulled high, In the meantime, an output signal having the voltage value of logic &#34;1&#34; is given forth by the buffer which has a precipitous switching characteristic. 
     The embodiments of the present invention described above are to be regarded in all respects as merely illustrative and not restrictive. Accordingly the present invention may be embodied in other specific forms without deviating from the spirit thereof. The present invention is therefore to be limited only by the scope of the following appended claims.