Display buffer using minimum number of VRAMs
NOTICE 
     (C) Copyright, *M* Texas Instruments Incorporated, 1990. A portion of the Disclosure of this patent document contains material which is subject to copyright protection. The copyright and mask work owner has no objection to facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the U.S. Patent and Trademark Office, patent file or records, but otherwise reserves all rights in its copyright and mask work whatsoever. 
     TECHNICAL FIELD OF THE INVENTION 
     The present invention relates in general to processing systems and in particular to circuits, systems and methods for minimizing unused memory in a processing system. 
     BACKGROUND OF THE INVENTION 
     When designing a graphics system there are substantial cost advantages to be gained by minimizing amount of video random access memory (VRAM) used in the system display buffer. Several constraining factors dictate the absolute minimum amount of VRAM required in a particular system. The most important of these factors is the resolution of the system display. For example, a 1280×1024×8 display (i.e. a display arranged as an array of 1280×1024 pixels with 8 bits from the graphics processor defining each pixel) requires an absolute minimum of 1 1/4M bytes of VRAM. 
     Current display buffers are typically constructed with 256K×4 VRAM chips, therefore, if the display buffer is operating in conjunction with a 32 bit wide data bus, 8 VRAM chips are required per bank of memory. In this architecture, each bank provides 1 Mbyte of memory such that two banks are required to contain a 1280×1024×8 display. This disadvantageously leaves 3/4 Mbyte of display buffer memory unused by the system. Given that VRAM costs are determined primarily by the number of storage bits per chip, such a large number of unused bits represents significant unnecessary costs. 
     Thus the need has arisen for circuitry, systems and methods which reduce the amount of unused RAM in processing systems. In particular, by reducing the amount of unused VRAM in a given graphics system, the significant advantage of cost reduction is achieved since VRAM bit per bit is relatively expensive. 
     SUMMARY OF THE INVENTION 
     Memory circuitry is provided which includes a plurality of memory banks, with each memory bank having a plurality of ordered rows of data storage locations including a first row and a last row, the storage locations of each row also ordered to include a first and a last storage location. Circuitry is also provided for controlling the storage of a plurality of sequences lines of data in the memory bank, each line of data comprising a plurality of sequenced data words. The circuitry for controlling storage of data in the memory banks is operable to store at least a portion of a first one of the sequences lines of data in the first row of the first one of the memory banks, the first word of the first line being stored in a location offset from the first location of the first row of the first memory bank such that the last word of the last line being stored in the first memory bank is stored in the last location of the last row of the first memory bank. The circuitry for controlling stores a first subsequent line in the sequence of lines in a second one of the memory banks, the first word of the first subsequent line being stored in a location in a row in a second bank other than the first row of the second bank. The circuitry for controlling then stores a second subsequent line of the lines being stored in the second bank such that a word of the second subsequent line is stored in the last location of the last row of the second bank and such that the next word of the sequenced words of the second subsequent line is stored in the first location in the first row of the second bank. 
     The present invention provides a means for reducing the amount of unused random access memory in a processing system. In particular, the present invention allows for a reduction of the amount of unused VRAM in a graphic system allowing for a significant overall system cost reduction. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a functional block diagram of a graphics processor system utilizing one embodiment of the present invention; 
     FIG. 2 is a schematic diagram depicting a typical video random access memory architecture for use in the graphics system of FIG. 1: 
     FIG. 3a-c depict possible methods of storing data in a graphics system display buffer; 
     FIG. 4 depicts a method of storing data in a graphics system display buffer according to one embodiment of the present invention; and 
     FIG. 5a-c depict example display buffer address decoding schemes for implementing the embodiment shown in FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The preferred embodiment of the present invention and its advantages are best understood by referring to FIGS. 1 through 5 of the drawings, like numerals being used for like and corresponding parts of the various drawings. 
     FIG. 1 is a functional block diagram of a graphics computer system 10. Graphics computer system 10 includes a host processing system 12 coupled to a graphics processor board 14 through a bidirectional bus 16. Located on graphics processor board 14 are a graphics processor 18, memory 20, a video palette 22 and a digital-to-video converter 24. Video display 26 is driven by graphics board 14. 
     Host processing system 12 provides the major computational capacity for graphics computer system 10 and determines the content of the visual display to be presented to the user on video display 26. The details of the construction of host processing system 12 are conventional in nature and known in the art and therefore will not be discussed in further detail herein. Graphics processor 18 provides the data manipulation capability required to generate the particular video display being presented to the user. Graphics processor 18 may be for example a Texas Instruments TMS34020 graphics systems processor more completely described in the &#34;TMS 34020 User&#39;s Guide&#34; and the &#34;TMS34020 Graphics System Processor Data Sheet&#34;, both published by and available from Texas Instruments Incorporated, Dallas, Tex., and incorporated herein by reference. Graphics processor 18 is bidirectionally coupled to processing system 12 via bus 16. While graphics processor 18 operates as a data processor independent of host processing system 12, graphics processor 18 is fully responsive to requests output from host processing 12. Graphics processor 18 further communicates with memory 20 via video memory bus 28. In the illustrated embodiment, bus 28 includes a 32-bit multiplexed local address/data bus and assorted row and column address lines. Graphics processor 12 controls the data stored within video RAM 30, VRAM 30 forming a portion of memory 20. In addition, graphics processor 18 may be controlled by programs stored in either video RAM 30 or in read-only memory 32. Read-only memory 32 may also include various types of graphic image data, such as alpha-numeric characters in one or more font styles, and frequently used icons. Further, graphics processor 12 controls data stored within video palette 22 via bidirectional bus 34. Finally, graphics processor 18 controls digital-to-video converter 24 via video control bus 36. 
     Video RAM 30 (the &#34;display buffer&#34;) contains bit-map graphics data which control the video image presented to the user as manipulated by graphics processor 18. In addition, video data corresponding to the current display screen are output from video RAM 30 on bus 38 to video palette 22. As discussed in detail below, video RAM 30 may consist of banks of several separate random access memory integrated circuits, the output of each circuit typically being only one, four or eight bits wide as coupled to bus 38. 
     Video palette 22 receives high speed video data from video random access memory 30 via bus 38 and data from graphics processor 18 via bus 34. In turn, video palette 22 converts the data received on bus 38 into a video level which is output on bus 40. This conversion is achieved by means of a look-up table maintained in video palette 22 which is specified by graphics processor 18 via video memory bus 34. The output of video palette 22 may comprise color, hue and saturation signals for each picture element or may comprise red, green and blue primary color levels for each pixel. Digital-to-video converter 24 converts the digital output of video palette 22 into the necessary analog levels for application to video display 26 via bus 40. Together, video palette 22 and digital to video converter 24 make up the &#34;backend&#34; or simply &#34;palette&#34; 42. 
     Video display 26 receives the video output from digital-to-video converter 24 and generates the specified video image as a sequence of lines of pixels for viewing by the user of graphics computer system 10. Significantly, video palette 22, digital-to-video converter 24 and video display 26 may operate in accordance with either of two major video techniques. In the first technique, video data are specified in terms of hue, saturation and lightness for each individual pixel. In the second technique, the individual primary color levels of red, blue and green are specified for each individual pixel. Upon selection of the desired design using either of these two techniques, video palette 22, digital-to-video converter 24 and video display 26 are customized to implement the selected technique. However, the principles of the present invention in regard to the operation of the graphics processor 18 are unchanged regardless of the particular design choice of the video technique. 
     Referring next to FIG. 2, a graphics memory system configuration for video RAM 20 using 256k×4 VRAMs is depicted. When operating in conjunction with a 32-bit local address/data portion of bus 28, an array of eight VRAM memories 44 is used per bank, two of which are depicted as 44a and 44b. Each 256k×4 VRAM memory 44 has four 512×512-bit planes, 0, 1, 2 and 3. The construction of each plane is such that a single data lead 46 is used to exchange information to that plane. In FIG. 2, leads 46 represent the &#34;random port&#34; allowing the reading and writing of pixel data into a given location across the planes of one or more VRAM memories 44 in a manner similar to that used with a conventional RAM. In FIG. 2, VRAM memories 44 are arranged such that the pixel information for the graphics display is stored serially across the planes in the same row. Assuming an 8-bit word per pixel (or simply 8-bit pixel) system, then the bits for each pixel are stored across the planes of two 256k×4 VRAM memories 44 (if only four bits per pixel are being used, then one pixel would be stored across the planes of a single VRAM 44). In the 8-bits per pixel example of FIG. 2, pixel 0 is stored in locations A0 of VRAMs 44a and 44b. Pixels 1, 2, and 3 are then disposed in locations AO across the planes of the remaining 6 VRAMS forming the array of the bank (not shown for clarity). Pixel 4 is then located in locations A1 of VRAMs 44a and 44b, and so on. 
     Each VRAM plane has a serial register 48 for shifting out information from a row of memory. In the preferred embodiment, the shifting out is performed in response to a shift clock signal SCLK (not shown) generated on palette 42 (FIG. 1). The outputs from these registers (representing the &#34;serial port&#34; are connected in parallel bus 38 (a 32-bit bus in present illustrative embodiment). Thus, data from a row memory, such as row A, would be moved into registers 48 and output serially from each register 48 the array in parallel on bus 38. 
     FIG. 3a depicts the use of two banks, bank0 and bank1, of 256K×4 VRAMS containing a 1280×1024×8 display with unpacked lines of pixels. Each of the banks is shown in equivalent view of the architecture shown in FIG. 2 with all bit planes of all parallel VRAM devices 44 merged into one for clarity and simplicity. Note that with this arrangement, approximately 3/4 Mbyte of memory (shown in the shaded area) remains unused. It is also important to note that in this unpacked arrangement the unused memory is not contiguous and is thus of limited use for holding data. FIG. 3b shows the same 1280×1024×8 display stored in 256k×4 VRAMs but with display (pixel) lines packed so the unused memory is contiguous. The disadvantage of the approach of FIG. 3b is that bank 0 ends in the middle of line 819. Without significant extra logic it is not possible to switch from one bank of memory to another in the middle of a display line making this packed display line scheme is impractical for a buffer design. FIG. 3c shows the same packed line arrangement of FIG. 3b, but this time the start of line 0 is offset so that the first bank of memory ends at the end of line 818. In this way a display buffer can be made which has all unused memory in a contiguous block, however, 3/4 Mbyte of memory remains unused. 
     FIG. 4 depicts the use of 128K×8 VRAMS as a frame buffer holding a 1280×1024×8 display as an illustration of one embodiment of the present invention. In the illustrative example of FIG. 4, the amount of unused memory is reduced from approximately 3/4 Mbyte to approximately 1/4 Mbyte. In the illustrated embodiment, three banks (bank 0 bank 1 and bank 2) of 128kx8 VRAMS, each having 8 bit-planes of 512×256 bits, are provided and line packing is used. An offset of the first bit of line 0 along the first row ensures that last available locations (the last locations in the last row) stores the last pixel of line 408. In the depicted example, the first pixel of line 0 is offset from the first available memory location at address 000000h to the memory location at address 1800h such that the pixel for line 408 is held in the location at the address 3fffff, the last available address for bank 0. In alternate embodiments, the offset may vary depending on the length of the display lines and the bit-width provided by the planes of the VRAMs. Further, in alternate embodiments the number of lines packed in a given VRAM may also vary depending on the depth of the VRAMs. 
     Storage of pixel data (data words) in Bank 1 begins with the first pixel processed of line 409 being held in the first available location in the bank (first row, no offset), in this case at address 400000h. Lines of pixels are then stored in a packed fashion until the last pixel of line 792 is sent to the last location of row 383, in this example at address 7bffffh. Special decode logic, examples of which are discussed below, then detects attempts to address locations at or beyond address 07c0000h, in which case bank 2 is selected. This has the effect of ending bank 1 at the exact end of line 792. 
     The next address 7cooooh is now used to place the start of line 793 in a row in the lower half of bank 2. Bank 2 now ends part way through line 817 at address 7fffffh. The next pixel of line 817 is then sent to the first location in bank 2 using the next address in sequence, address 800000h. Since the rest of line 817 is stored within the same bank at a logically contiguous location, the shift register re-load proceeds correctly. 
     In the example scheme shown in FIG. 4, the unused memory is minimized with only 32K unused bytes in bank 1 and approximately 224K unused bytes in bank 2. The primary advantage of the illustrative scheme is that the display buffer for a 1280×1024×8 display can be fit into 3 banks of 128K×8 VRAMS. This saves PCB space and cuts the system cost. An additional advantage is that the two blocks of unused memory are contiguous within themselves. 
     FIGS. 5a-5c are representative implementations of the address decode scheme for a 1280×1024×8 display contained in three banks of 128K×8 VRAM discussed above. In FIGS. 5a-5c, the addressing schemes are defined using the local address/data bus line designations for the Texas Instruments TMS34020 as an example only (in FIG. 1, the corresponding local address/data forms part of bus 28). Reference is again made to the &#34;TMS 34020 User&#39;s Guide&#34; (January 1990) and the &#34;TMS34020 Graphics System Processor Data Sheet&#34; (October 1990), available from Texas Instruments and incorporated herein by reference. Similar addressing schemes may be used with alternate graphics processors as understood by those skilled in the art; the inventive concepts described using this example remain the same. The decoding scheme shown in FIG. 5c uses mask/compare logic that already exist for use in four bank systems. Thus chips such as the Texas Instruments TMS34094 designed to work with a four bank system can easily be adapted to the more economical three bank scheme. The and/or logic used to process the output of the comparators can also be easily generalized to accommodate systems with more banks. 
     The idea of using an address decode scheme to enable a minimum VRAM system to be built has applications across a range of display resolutions, pixel sizes, buffer widths, VRAM designs and so on. The 1280×1024×8 in a 32 bit wide buffer of 128K×8 VRAMs is just one specific example. 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.