Semiconductor storage device requiring short time for program voltage to rise
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor storage device and particularly it relates to a semiconductor storage device adapted to execute a program using a program voltage. 
     2. Description of Related Arts 
     A conventional semiconductor storage device comprises a memory cell array and a peripheral circuit. Said peripheral circuit comprises an internal boosted power source generating circuit which, when receiving an external power source voltage Vcc, delivers an internal boosted power source voltage Vpp for transferring &#34;H&#34; data to memory cells, and an internal reset circuit which delivers an internal reset signal ZPOR for starting said internal boosted power source generating circuit. 
     A conventional semiconductor storage device will now be described with reference to the drawings. 
     FIG. 8 is a block diagram showing an example of the arrangement of said internal boosted power source generating circuit. 
     In FIG. 8, the internal boosted power source generating circuit comprises an internal boosted power source voltage Vpp generating circuit 201, an internal boosted power source voltage Vpp supplementing circuit 203, and a clamp 205. The Vpp generating circuit 201 comprises a ring oscillator 207 and a pump 209. The Vpp supplementing circuit 203 comprises a level detector 211, a ring oscillator 213 and a pump 215. 
     The Vpp generating circuit 201 is connected to an external power source and generates the internal boosted power source voltage Vpp on the basis of the external power source voltage Vcc. The ring oscillator 207 in the Vpp generating section 201 produces and delivers a pulse signal having an amplitude |GND-Vcc| from the external power source voltage Vcc. The pump 209 is connected to the ring oscillator 207 and is actuated by a pulse signal from the ring oscillator 207 to generate the internal boosted power source voltage Vpp. The Vpp supplementing circuit 203 is connected to the Vpp generating circuit 201 and generates a voltage which supplements the internal boosted power source voltage Vpp when the latter is at lower level. The level detector 211 in the Vpp supplementing circuit 203 is designed such that when the level of the internal boost source voltage Vpp is lower than a target value, it detects said level and delivers a signal (operating signal) to actuate the ring oscillator 213. The ring oscillator 213 is connected to the level detector 211, and upon receiving an operating signal from the level detector 211, it produces and delivers a pulse signal. The pump 215 is connected to the ring oscillator 213 and is adapted to be actuated by a pulse signal from the ring oscillator 213 to deliver a voltage for supplementing the internal boosted power source voltage Vpp. The clamp 205 is connected to the Vpp generating circuit 201 and to the Vpp supplementing circuit 203 such that if the level of the internal boosted power source voltage Vpp delivered from either the Vpp generating circuit 201 or the Vpp supplementing circuit 203 is higher than a target value, it detects said voltage and delivers the internal boosted power source voltage Vpp after it has controlled the latter to a suitable value. 
     FIG. 9 is a view showing the internal arrangement of the pumps 209 and 215 shown in FIG. 8. 
     In FIG. 9, each pump comprises NMOS transistors 301, 311, 313 and 319, a clamp 303, inverters 305 and 307, and capacitors 309, 315 and 317. 
     Terminal p, q, r and s are connected to an external power source to have an external power source voltage Vcc applied thereto. The NMOS transistor 301 of diode junction sets an initial value for the boosted power source voltage Vpp. The clamp 303 has a plurality (3, in FIG. 9) of NMOS transistors of diode junction and is designed such that when the level of the internal boosted power source voltage Vpp rises too high, it detects said level to control the latter to a suitable value. 
     The inverter 305 is connected at its terminal u to the ring oscillator 207 or 213 of FIG. 8 and adapted to deliver a pulse signal having an amplitude |GND-Vcc|. The inverter 307 is connected to the inverter 305 and adapted to deliver an inverted pulse signal having an amplitude |GND-Vcc|. 
     The capacitor 309 is connected to the NMOS transistor 301 and to the inverter 305 and is designed such that when a voltage is periodically applied to one electrode thereof associated with the inverter 305, a voltage is applied to the other electrode from the NMOS transistor 301, whereby the capacitor is charged. The NMOS transistors 311 and 313 have their drains connected to the external power source and their gates connected to the capacitor 309; thus, when the capacitor 309 is charged until the electrode voltage exceeds the threshold voltage of the NMOS transistors 311 and 313, whereupon they are turned on, feeding the voltage from the power source. 
     The capacitor 315 is connected to the inverter 307 and the drain of the NMOS transistor 311, while the capacitor 317 is connected to the inverter 307 and the NMOS transistor 313. When a voltage is applied, with a period inverted with respect to the capacitor 309, to the electrode associated with the inverter 307, a voltage is applied to the other electrode from the associated NMOS transistor 315 or 317, whereby the capacitor is charged. 
     The NMOS transistor 319 has its source connected to the drain of the NMOS transistor 311 and to the capacitor 315 and its gate connected to the drain of the NMOS transistor 313 and to the capacitor 317. When this NMOS transistor 319 is turned on, the voltages obtained by charging the capacitors 315 and 317 and the voltages obtained by turning on the NMOS transistors 311 and 313 are added. As a result, a voltage can be obtained which is higher than the power source voltage Vcc necessary for generating the target value Vpp of the internal boosted power source voltage. And the internal boosted power source voltage Vpp thus obtained is delivered from the terminal w connected to the drain of the NMOS transistor 319 and thus delivered from the Vpp generating circuit 201 of FIG. 8. 
     FIG. 10 is a timing chart showing how the internal boosted power source voltage Vpp is boosted when the power is turned on in a conventional semiconductor storage device. 
     In the conventional semiconductor storage device, when the external power source is off (time t; to&lt;t&lt;t 1 ), the external power source voltage Vcc, the internal boosted power source voltage Vpp and the internal reset signal ZPOR are all at the ground voltage GND. When the power is turned on (t 1  &lt;t&lt;t 7 ), the internal reset signal maintains the ground voltage GND level for a given time, resetting the circuits in the device. When the internal reset signal ZPOR turns to &#34;H&#34; level, the reset time is up and the internal boosted power source generating circuit is started (t 7 ) elevate the internal boosted power source voltage Vpp from the ground voltage GND to an intended boosted level (t 7  &lt;t&lt;t 11 ). 
     In the prior art, however, since the internal boosted power source voltage Vpp rises only after the external power source voltage Vcc has risen when the external power source is turned on, it takes time for the internal boosted power source voltage to reach the intended boosted level. In the semiconductor storage device comprising the internal boosted power source generating circuit and the internal reset circuit as described above, if a substantial time has to elapse before an intended boosted level can be reached after the rise of the internal boosted power source voltage Vpp, then the following problems arise. 
     (1) The specification telling that the internal boosted power source voltage Vpp will rise in a given time cannot be ensured; 
     (2) There are adverse effects including latch-up sometimes taking place in a semiconductor; 
     Latch-up mentioned in (2) will now be described with reference to the drawings. 
     FIG. 11 shows an example of the peripheral circuit of a semiconductor storage device, said circuit being liable to cause latch-up when the rise of the internal boosted power source voltage is slow. This circuit is used to elevate the potential at the node c from the ground voltage GND to the same voltage as the internal boosted power source voltage Vpp. 
     In FIG. 11, this circuit comprises PMOS transistors 401, 402 and 403 and NMOS transistors 404, 405 and 406. The terminals k and z connected to the respective sources of the PMOS transistors 401 and 402 and the terminal n connected to the gate of the PMOS transistor 403 are connected to the internal boosted power source, and the terminal m connected to the source of the PMOS transistor 403 is connected to the external power source. The internal boosted power source voltage Vpp is supplied from the node A and the external power source voltage Vcc is supplied from the node B. 
     One cycle of operation will now be described with reference to a timing chart shown in FIG. 12. However, suppose that the timing chart is an ideal one in which the external power source voltage Vcc and the internal boosted power source voltage Vpp have already risen to a final value and an intended boosted level, respectively. 
     The nodes A and B are supplied with the ground voltage END and the external power source voltage Vcc (A; t 100  &lt;F t&lt;F t 103 , B; t 100  &lt;F t&lt;F t 101 ). When the supply of the external power source voltage Vcc from the node B is stopped (t 101 ), the PMOS transistor 403 is turned on to supply the node C with a voltage (Vcc-Vpp). When the internal boosted power source voltage Vpp is supplied from the node A (t 103 ), the NMOS transistor 404 and the PMOS transistor 402 are turned on to supply the node C with the internal boosted power source voltage Vpp (t 104 ), and the voltage at the node C becomes equal to the internal boosted power source voltage Vpp (t 105 ). 
     Again, the node B is supplied with the external power source voltage Vcc (t 106 ), and when the node A starts to be supplied with the ground voltage GND (t 107 ), the voltage at the node C lowers to the ground voltage GND (t 108 ). 
     FIG. 13 is a view showing the construction of the PMOS transistor 403 in FIG. 11. Latch-up will now be described using this FIG. 13. 
     In FIG. 13, the PMOS transistor 403 comprises an n-well 503 formed in a p-type substrate 501, a source 505 in p+ layer form formed in said n-well 503, a drain 507 in p+ layer form, and a gate electrode 509. The terminals m and n correspond to the terminals m and n in FIG. 11. 
     The gate 509 is connected to the node B. The internal boosted power source voltage Vpp is applied to the n-well 503. The external power source voltage Vcc is fed in from the source 505 and delivered from the drain 507 to the node C. 
     Here, it is to be noted that while the external power source voltage Vcc rises at a stroke, if the internal boosted power source voltage Vpp takes time to rise, then a forward bias (p→n) is applied longitudinally from the source 505 to the n-well 503, causing latch-up to take place, damaging the device. 
     SUMMARY OF THE INVENTION 
     Accordingly, an object of this invention is to realize early stabilization of a program voltage when the power is turned on in a semiconductor storage device. 
     Another object of this invention is to effect boost of a program voltage in a short time when the power is turned on in a semiconductor storage device. 
     Yet another object of this invention is to save power consumption when the power is turned on in a semiconductor device. 
     A further object of this invention is to prevent occurrence of latch-up when the power is turned on in a semiconductor device. 
     Still a further object of this invention is to effect boost of a program voltage in a short time in a program voltage generating method for a semiconductor storage device. 
     These objects are achieved in that a semiconductor storage device comprises the following elements. That is, a semiconductor storage device for executing a program using a program voltage according to this invention comprises a terminal for receiving a power source voltage, a detector for detecting the varying level of rise of said power source voltage, and a booster for boosting said program voltage on the basis of the result of the rise of level. 
     According to the invention, a power source voltage is received, the changing level of rise is detected, and a program voltage is boosted on the basis of the result of the level of rise; therefore, immediately after the rise of the power source voltage and before the start of the boosted power source, the program voltage rises and is boosted. Since the program voltage is boosted immediately after the power source voltage has risen when the power is turned on, the time taken to reach an intended boosted level is shortened. 
     As a result, in a semiconductor storage device, early stabilization of a program voltage is realized. 
     Preferably, such program voltage comprises a first program voltage for executing the program and a second program voltage lower than said first program voltage. The semiconductor storage device is provided with a program voltage generator for generating the first program voltage, said generator boosting the second program voltage to the first program voltage. 
     In another aspect of this invention, the semiconductor storage device executes a program using the first program voltage. The semiconductor storage device comprises a power source voltage terminal for receiving a power source voltage to generate a first program voltage after the lapse of a predetermined time, a program voltage generator, and a rectifier connected to the power source voltage terminal and to the program voltage generator to pass a current only from the power source voltage terminal to the program voltage generator. The rectifier is adapted, after the lapse of said predetermined time, to boost the potential at the program voltage generator to a second program voltage which is lower than the first program voltage. 
     A rectifier is provided which passes a current only from the power source voltage terminal to the program voltage generator and which elevates the potential at the program voltage generator to the second program voltage lower than the first program voltage before the program voltage generator generates the predetermined first program voltage. Because of the current passing only from the power source voltage terminal to the program voltage generator, before the program voltage generator generates a first potential upon turning-on of the power, its output is boosted to a second potential which is lower than the first potential. As a result, the power consumption can be saved as compared with the case of boosting the output from the predetermined reference voltage to the first program voltage at a stroke. 
     In a further aspect of this invention, a program voltage generating method for a semiconductor storage device for executing a program using a predetermined first voltage comprises the steps of detecting a power source voltage, boosting the program voltage to a second voltage which is lower than a first voltage, and boosting the program voltage to the first voltage subsequent to the boosting to the second voltage. 
     Depending upon the detected power source voltage, the program voltage is boosted to the second voltage lower than the first predetermined voltage and then to the first predetermined voltage; therefore, in the program voltage generating method for a semiconductor storage device, the boosting of the program voltage can be effected in a short time. 
     The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the entire arrangement of a DRAM which is an example of a semiconductor storage device according to an embodiment of the present invention; 
     FIG. 2 is a circuit diagram of a first embodiment of a rectifying circuit 4 in an embodiment of a semiconductor according to the invention; 
     FIG. 3 is a timing chart showing how an internal boosted power source voltage Vpp is boosted in a first embodiment of the present invention; 
     FIG. 4 is a circuit diagram of a second embodiment of a rectifying circuit 4 in a semiconductor storage device according to an embodiment of the invention; 
     FIG. 5 is a timing chart showing how an internal boosted power source voltage Vpp is boosted in a second embodiment of the present invention; 
     FIG. 6 is a circuit diagram of a third embodiment of a rectifying circuit 4 in a semiconductor storage device according to an embodiment of the invention; 
     FIG. 7 is a timing chart showing how an internal boosted power source voltage Vpp is boosted in a third embodiment of the present invention; 
     FIG. 8 is a block diagram showing an example of the arrangement of an internal boosted power source voltage generating circuit; 
     FIG. 9 is a circuit diagram of an example of a pump in the internal boosted power source voltage generating circuit; 
     FIG. 10 is a timing chart showing how the internal boosted power source voltage Vpp in a conventional semiconductor storage device is boosted; 
     FIG. 11 is a circuit diagram of a circuit including a PMOS transistor 403 liable to cause latch-up; 
     FIG. 12 is a timing chart showing the operation of the circuit shown in FIG. 11; and 
     FIG. 13 is a view showing the internal construction of the PMOS transistor 403 shown in FIG. 11. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Semiconductor storage device according to an embodiment of the present invention will now be described. 
     Referring to FIG. 1, a semiconductor storage device comprises an internal boosted power source generating circuit 1, an internal reset circuit 3, a rectifying circuit 4, a clock generating circuit 5, a gate 7, a row/column address buffer 9, a row decoder 11, a column decoder 13, a sense refresh amplifier and input/output control circuit 15, a memory cell array 17, an input buffer 19, and an output buffer 21. In response to a column address strobe input /CAS (&#34;/&#34; denotes a reverse signal), a row address strobe input /RAS and a read/write designation input /WE, the semiconductor storage device performs predetermined operations to store data in predetermined memory cells in the memory cell array 17 corresponding to the address and row designated by the address input An (for example, n=0, 1, 2, . . . 11) or read stored data. Data to be stored is transferred to the memory cell array 17 through the input buffer 19 and the read data is delivered through the output buffer 21. These operations are the same as in an ordinary DRAM. In the figure, Vcc is an external power source voltage; Vss is the ground voltage; DQ is data to be inputted/outputted; and /OE is an output enable signal for controlling data input/output. 
     The internal reset circuit 3 is connected at the terminal a to the external power source and the internal boosted power source generating circuit 1. The rectifying circuit 4 is connected at the terminal a to the external power source and at the terminal b to the internal boosted power source generating circuit 1. The rectifying circuit 4 may be connected to the terminal c if need arises. 
     (1) First Embodiment 
     FIG. 2 is a first embodiment of the rectifying circuit in FIG. 1. 
     In FIG. 2, the rectifying circuit 4 comprises an NMOS transistor 101. The diode-connected NMOS transistor 101 has the terminal d from its source connected to the external power source at the terminal a in FIG. 1 and has the terminal e from its drain connected to the internal boosted power source generating circuit 1 at the terminal b in FIG. 1. 
     The operation will now be described using the timing chart in FIG. 3. 
     When the external power source is off (t 0  &lt;t&lt;t 1 ), the external power source voltage Vcc, the internal boosted power source voltage Vpp, and the internal reset signal ZPOR delivered from the internal reset circuit 3 in FIG. 1 are all at the ground voltage GND. Turning on the external power source causes the external power source voltage Vcc to rise (t 1 ). When the external power source voltage Vcc exceeds the threshold voltage Vth of the NMOS transistor 101 (t 3 ), the NMOS transistor 101 is turned on, whereupon the internal boosted power source starts to be supplied with a voltage (Vcc-Vth). The internal boosted power source voltage Vpp starts to rise in such a manner as to follow the course of rise of the external power source voltage Vcc. The external power source voltage Vcc reaches the final value (t 5 ), supplying the internal power source with the voltage (Vcc-Vth). When the internal boosted power source voltage Vpp becomes (Vcc-Vth) (t 9 ), this voltage is retained until the internal reset signal ZPOR expires (t 9  &lt;t&lt;t 7 ). When the internal reset signal ZPOR expires (t 7 ), the internal boosted power source generating circuit 1 starts to operate, whereby the internal boosted power source voltage Vpp is raised to the intended boosted level at a stroke (t 7  &lt;t&lt;t 17 ). 
     As described above, if the internal boosted power source voltage Vpp is boosted half way before the internal boosted power source generating circuit 1 is started to operate, then the period of time in which the internal boosted power source generating circuit 1 which requires a large power consumption is saved; thus, the power consumption is reduced. 
     Further, in the arrangement shown in FIG. 13, since Vpp is boosted while following Vcc, latch-up will not occur. 
     In FIG. 2, even if the above arrangement is replaced by another arrangement in which a diode or other elements in diode connection is used in place of the NMOS transistor 101, the same operation is performed. 
     (2) Second Embodiment 
     FIG. 4 shows a second embodiment of the rectifying circuit 4 shown in FIG. 1. 
     In FIG. 4, the rectifying circuit 4 comprises an inverter 102, an NMOS transistor 103, and a node 104. 
     The inverter 102 is connected to the external power source and the terminal f is connected to the internal reset circuit 3 at the terminal c in FIG. 1 to receive the internal reset signal ZPOR, and the node 104 is connected to the gate of the NMOS transistor 103. The NMOS transistor 103 is connected at the terminal d leading to its source to the external power source at the terminal a in FIG. 1 and connected at the terminal e leading to its drain to the internal boosted power source generating circuit 1 at the terminal b in FIG. 1. 
     The operation will now be described using the timing chart in FIG. 5. 
     When the external power source is off (t 0  &lt;t&lt;t 1 ), the external power source voltage Vcc, the internal boosted power source voltage Vpp, and the internal reset signal ZPOR are all at the ground voltage GND. Turning on the external power source causes the external power source voltage Vcc to rise (t 1 ). After the external power source has been turned on, a fixed period is the internal reset duration, so that the internal reset signal ZPOR remains at &#34;L&#34; level (t 1  &lt;t&lt;t 7 ). When the external power source voltage Vcc exceeds the threshold voltage Vth of the transistor in the inverter 102 (t 3 ), the potential at the node 104 starts to gradually rise. When the potential at the node 104 exceeds the threshold voltage Vth of the NMOS transistor 103 (t 13 ), the NMOS transistor 103 is turned on. When NMOS transistor 103 is turned on, the internal boosted power source is supplied with a voltage (Vcc-Vth). And the internal boosted power source voltage Vpp starts to rise. The power source voltage Vcc reaches the final value (t 5 ), and when the internal boosted power source voltage Vpp reaches the voltage (Vcc-Vth) (t 15 ), this voltage is retained until the internal reset signal ZPOR turns to &#34;H&#34; level (t 15  &lt;t&lt;t 7 ). When the internal reset signal ZPOR turns to &#34;H&#34; level (t 7 ), the inverter 104 switches the node 104 to &#34;L&#34; level, lowering the gate voltage of the NMOS transistor 103 to turn off the NMOS transistor 103. When the internal reset signal ZPOR turns to &#34;H&#34; level, the internal boosted power source generating circuit 1 starts to operate, whereby the internal boosted power source voltage Vpp is raised to the intended boosted level at a stroke (t 7  &lt;t&lt;t 17 ). When the NMOS transistor 103 is turned off and the external power source and the internal boosted power source voltage Vpp are separated from each other, it is possible to prevent a leak current which flows from the internal boosted power source to the external power source even if the internal boosted power source voltage Vpp stepped up by the internal boosted power source generating circuit 1 shown in FIG. 1 becomes higher than the external power source voltage Vcc. 
     Further, as in the case of the first embodiment, the power consumption can be reduced by boosting the internal boosted power source voltage Vpp in advance before the internal boosted power source generating circuit 1 starts to operate. 
     (3) Third Embodiment 
     FIG. 6 shows a third embodiment of the rectifying circuit 4 shown in FIG. 1. 
     In FIG. 6, the rectifying circuit 4 comprises NMOS transistors 105, 106 and 107, PMOS transistors 108 and 109, and a differential amplifier circuit 110. 
     The terminal d connected to the source of the NMOS transistor 105, the terminals g and h connected to the source and gate of the NMOS transistor 106, respectively, and the terminal i connected to the source of the NMOS transistor 107 are all connected to the external power source at the terminal a shown in FIG. 1. The terminal e connected to the drain of the NMOS transistor 105 and the terminal j connected to the gate of the NMOS transistor 107 are connected to the internal boosted power source generating circuit 1 at the terminal b shown in FIG. 1. The sources and gates of the PMOS transistors 108 and 109 are grounded. The drain of the NMOS transistor 106 and the drain of PMOS transistor 108 are connected at the node 111 to the non-inverting input terminal + of the differential amplifier circuit 110. The drain of the NMOS transistor 107 and the drain of PMOS transistor 109 are connected at the node 112 to the inverting input terminal - of the differential amplifier circuit 110. The output of the differential amplifier circuit 110 is connected at the node 113 to the gate of the NMOS transistor 105. The source-drain current I1 is the source-drain current of the NMOS transistor 106 and PMOS transistor 108, and the source-drain current I2 is the source-drain current of the NMOS transistor 107 and PMOS transistor 109. The NMOS transistors 106, 107 and the PMOS transistors 108, 109 are equal in size (W: gate width, L: gate length) to each other so that their characteristics are also the same. 
     The operation will now be described using the timing chart in FIG. 7. 
     When the external power source is off (t 0  &lt;t&lt;t 1 ), the external power source voltage Vcc, the internal boosted power source voltage Vpp, and the internal reset signal ZPOR are all at the ground voltage GND. Turning on the external power source causes the external power source voltage Vcc to rise (t 1 ). After the external power source has been turned on, a fixed period (t 1  &lt;t&lt;t 7 ) is the internal reset duration, so that the internal reset signal ZPOR remains at &#34;L&#34; level and the internal boosted power source generating circuit 1 does not operate, with the internal boosted power source voltage Vpp remaining at the ground voltage GND (t 1  &lt;t&lt;t 19 ). Therefore, the NMOS transistor 106 is turned on, but the NMOS transistor 107 remains in the off state. The source-drain current I1 and the on-resistance of the PMOS transistor 108 elevate the voltage at the node 111 from the ground voltage GND (t 3 ). On the other hand, since the source-drain current I2 does not flow, the voltage at the node 112 remains at the ground voltage GND. When a potential difference appears between the nodes 111 and 112, the differential amplifier circuit 110 operates, causing the voltage at the node 113 to exceed the threshold voltage Vth (t 19 ), whereupon the NMOS transistor 105 is turned on, supplying the internal boosted power source with a voltage (Vcc-Vth). When the internal boosted power source voltage Vpp exceeds the threshold voltage Vth (t 21 ) of the NMOS transistor 107, the NMOS transistor 107 is turned on and the source-drain current I2 flows. During the time the voltage at the node 111 is higher than the voltage at the node 112 (t 21  &lt;t&lt;t 23 ), the output (node 113) of the differential amplifier circuit 110 remains at &#34;H&#34; level. Therefore, when the external power source voltage Vcc reaches the final value (t 5 ), in the NMOS transistor 105 the voltage supplied to the internal boosted power source is (Vcc-Vth). During this time, the voltage at the node 112 gradually increases until it is equal to the voltage at the node 111, whereupon the output (at the node 111) of the differential amplifier circuit 110 turns to &#34;L&#34; level, turning off the NMOS transistor 105 so as to isolate the external power source and the internal boosted power source from each other. As a result of this isolation, the internal reset duration ends (t 7 ) and the internal boosted power source generating circuit 1 starts to operate, and even if the level of the internal boosted power source voltage Vpp becomes higher than the external power source voltage Vcc, it is possible to prevent a leak current from flowing from the internal boosted power source to the external power source; thus, the internal boosted power source voltage Vpp is elevated to the intended boosted level (t 7  &lt;t&lt;t 25 ). 
     This third embodiment also, as in the case of the first embodiment, is capable of saving the power consumption by boosting the internal boosted power source voltage Vpp in advance before the internal boosted power source generating circuit 1 starts to operate. 
     While the threshold voltages of all transistors have been designated by Vth; however, there is no need for the values of Vth for all transistors to be the same. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.