Thyristor load detector
BACKGROUND AND SUMMARY OF THE INVENTION 
     The present invention relates generally to a device for determining if a load is present in an electronic system, and more particularly, to a circuit arrangement which determines if load current is present in a Thyristor device. 
     A silicon controlled rectifier (SCR), one type of &#34;Thyristor&#34;, can be thought of as a switchable diode controlled by a positive gate signal. If connected in series with a supply voltage and load, and the supply voltage is less than the rated voltage of the device and no trigger current is applied to the gate, the Thyristor will remain off. If however, sufficient trigger signal is applied to the gate, the Thyristor&#39;s forward voltage will decrease to a value approximating the forward conduction drop of a diode, and the Thyristor will turn on, conducting as a diode. Once on, the Thyristor remains conducting (latches) regardless of the signal applied to the gate. For the Thyristor to be turned off, the anode-to-cathode current must be reduced below the holding current of the device. 
     Similarly, a triac operates in much the same way, but conducts in both directions when gated on (AC conduction), and accepts either polarity of gate signal. 
     Prior devices which are or can be used to detect the presence of a load in a system include resistors, current transformers, and Hall detectors; each of which has disadvantages: weight, size, cost, and/or added dissipation. 
     The present invention enables the detection of load current in a Triac or SCR (or similar Thyristor device) by monitoring the characteristic voltage found on the gate of the device. 
     Load status information can be used in various ways, for example, to turn off an output, to signal a load fault, etc. When incorporated into a control chip, the circuit of the present invention adds virtually no weight, requires no additional board space, and has negligible cost. 
     As an example of an application of the present invention, the circuit may be applied to a multi-channel chip that controls aircraft passenger reading lights. The chip removes power from burned-out lamps preferably within one second of their failure. This &#34;lamp-fail reset&#34; feature eliminates many relamping hazards with socket power still applied. Such hazards commonly include electrical shock, burned fingers, socket arcing, and multiple-surges during relamping. The present invention may be especially useful in connection with quartz halogen lamps due to the fact that such lamps operate at extremely high temperatures and pressures, and can even explode if haphazardly inserted into a live socket. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a graphical depiction of an AC supply line and the Triac gate signal seen with load current present in the Triac; 
     FIG. 1B is a graphical depiction of FIG. 1A when no load current is flowing through the Triac; 
     FIG. 2A shows an electrical schematic diagram of one embodiment of the present invention; and 
     FIG. 2B is a graphical depiction of typical signals occurring at each of seven locations as identified in FIG. 2A. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENT(S) 
     Referring now to the drawings, and particularly FIG. 1A, there is shown a typical Triac gate negative voltage pulse 12 as seen by the circuit which is applied at each line voltage zero-crossing. With load current flowing through the Triac, a voltage approximately equal to the Triac&#39;s on-state voltage (typically 0.9 Vpk) is present at the gate after pulsing provided the circuit&#39;s gate drive transistor is turned off immediately after pulsing to allow evaluation of the gate signal. Referring now to FIG. 1B, if no load current is flowing through the Triac, the gate signal 14 quickly recovers toward zero volts a few microseconds after pulsing. 
     As shown in FIG. 2A, one embodiment of the present invention is depicted in a circuit arrangement. The load sensing circuit 16 of the present invention is identified by the dashed box which surrounds it. The Triac 18 is turned on with a pulse typically 100 microseconds in duration applied to the gate as determined by the AC line voltage zero-crossing detector 20. Sampling of the gate voltage is delayed another 100 microseconds after gate pulse termination to give the gate capacitance enough time to discharge from the pulse. One method of deriving anti-coincidence timing for the gate pulse and sampling may be accomplished using an RC delay 22 and two comparators 24, 26 with different thresholds. The first comparator terminates the gate pulse, followed by the second that clocks the gate voltage sample result into a load sense latch. Of course other means could be used to achieve the gate/sample time split, e.g. separate time delays or system clock divide-down circuit. 
     In FIG. 2B typical signals are depicted at various locations in the circuit of FIG. 2A. For example, the signal identified in FIG. 2B number &#34;1&#34; is taken from location &#34;1&#34; as shown in FIG. 2A. 
     To avoid false load detection signals due to line glitches, a counter may be incorporated into the circuit, which requires several events before action is taken based on a load detection signal. In another embodiment of the present invention a low-voltage detector may also be incorporated that inhibits sensing when the line voltage is low. This might be required if Thyristor holding current would be inadequate to guarantee latching under light load conditions. 
     Referring again to FIGS. 2A and 2B, an AC voltage &#34;1&#34; is applied to the input of the zero-crossing detector 20, causing its output to change state with each reversal of the AC line voltage&#39;s zero-crossing &#34;2&#34;. FIG. 2B shows the timing between the AC line (&#34;waveform &#34;1&#34;) and the zero-crossing detector&#39;s output (waveform &#34;2&#34;). The phase relationship of these two signals is not critical. In fact the zero-crossing detector&#39;s output may be further delayed by any usual means to insure adequate current is developed for thyristor latching with light loads or cold temperatures. 
     The zero-crossing signal is then applied to an edge detector circuit comprised of XOR gate 28, resistor-capacitor delay network 22, and a voltage detector 24. With each zero-crossing transition, the XOR gate momentarily goes HI producing a gate pulse &#34;5&#34; until the voltage detector&#39;s delayed signal arrives &#34;4&#34;, approximately 100 us later. The duration of this pulse is controlled by the delay&#39;s 22 time constant and the voltage detector&#39;s 24 threshold. Ideally fie voltage detector&#39;s threshold is 50% of Vdd if the zero-crossing detector&#39;s output swings rail-to-rail so that gating pulses are identical in width for either LO-HI or HI-LO transition for each zero-crossing. 
     Assuming the load is on, control input D is held HI. With this enabling signal present, gating pulses appear at the AND gate 30 output, turning on the transistor 32 for the duration of the pulse. This causes triac gate current to flow from +Vdd, through the triac gate (G on FIG. 2A), resistor Rg and transistor 32 to ground. Once gated, the triac continues conducting until the load current drops below the triac&#39;s holding current, near the AC line&#39;s zero-crossing. 
     Conversely, if the load is off, the control input D is held LO. With a logic LO at the AND 30 input, the AND&#39;s output remains LO regardless of gate pulses from the XOR 28. As a result, transistor 32 remains off, and the triac 18 remains off. 
     The detection of current in the triac is determined by looking at the gate&#39;s responding voltage state, shortly after triac gating. In the case of AC, for convenience the gate signal is ignored during the positive half cycle, as it is difficult to sense above the logic supply rail. 
     As discussed, the sampling of the gate voltage must be delayed to give the gate capacitance enough time to discharge from the pulse. To accomplish this, the RC delay 22 signal is also connected to a load sensing circuit 16 whose voltage detector 26 is typically set for 25% of Vdd. This voltage is significantly lower than that of voltage detector 24. The difference of these two voltage thresholds provides two discrete timing events necessary for valid interpretation of the resulting gate voltage. As previously discussed, the gate pulse turns off when the RC voltage reaches 50%, and the gate voltage is sampled when the voltage reaches 25%. 
     Referring now to FIG. 1A, if current is present in the triac, the triac gate voltage 12 will be approximately 0.75 Vpk above or below the Vdd supply rail after the gating pulse depending on the AC line&#39;s phase 10. If however no current is present (FIG. 1B), the gate voltage 14 will quickly rise to the +Vdd level after the gating pulse. 
     The gate voltage is continuously monitored by the gate&#39;s voltage detector 34 whose threshold is typically 0.4 V below the +Vdd logic supply rail. Assuming now that the RC delay has now dropped 25% of Vdd, the voltage detector 26 goes HI (waveform &#34;6&#34; of FIG. 2B), and the D input of the latch 36 is clocked. If current is present in the triac, voltage detector 34 will be LO and a Logic LO will appear at the Q output of the latch 36. If however, current is absent in the triac, voltage detector 34 will be HI the moment voltage detector 26 goes HI and a Logic HI will clocked into the Q output of the latch, indicating that load current is not present. 
     The present invention is described by way of example only, and various modification and/or alterations will be apparent to those skilled in the art without departing from the scope of the invention as defined by the accompanying claims.