Dynamically switchable power supply
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present invention is a continuation-in-part of U.S. application Ser. No. 08/399,060, filed Mar. 8, 1995, which in turn is a continuation-in-part of U.S. application Ser. No. 08/335,209, filed Nov. 7, 1994, abandoned. 
    
    
     TECHNICAL FIELD 
     The present invention relates generally to power supplies for portable electronic devices having multiple operational voltage levels and specifically to a dynamically switchable power supply for portable electronic devices which operate at multiple logic voltage levels. 
     BACKGROUND OF THE INVENTION 
     The invention herein is a further improvement of related subject matter contained in the cross-referenced prior patent applications, which prior patent applications are relied upon for priority rights in previously described novel features. 
     Computer systems are becoming increasingly more portable while at the same time becoming increasingly more powerful. Low power consumption is an essential design criterion of portable battery powered computer systems and data terminals. For this reason much of the hardware in a portable computer system, such as the system microprocessor, operates at lower logical voltage supply levels, typically 3.3 volts or even 2.7 volts, because systems operating at lower voltages consume less power than systems operating at higher voltages. The most common computer hardware devices operate at 5.0 volts for logic voltage levels. Portable data terminals and other laptop type computer systems employ microprocessors and other hardware devices which operate at 3.3 volts or 2.7 volts for logic voltage levels in order to reduce system power consumption and thereby extend operational battery time. 
     As the logical switching speeds of computer systems increase, the amount of heat generated as a result also increases. It is for this reason that microprocessor chip manufacturers have needed to lower the logical operating voltages with increased processor speeds because even with heat sinks and fans to cool them, high operating speeds combined with high voltages will cause the chip to overheat. 
     If proper thermal management of the electronics of a portable electronic device are not carefully considered and engineered for, catastrophic thermal failure may occur resulting in a total loss of electronic function. In general, for a capacitive load, the relationship between the power generated by an electronic device and the operational voltage and frequency is given as: 
     
         P∝v.sup.2 ·f 
    
     where P is the power generated, v is the operational voltage and f is the operational frequency. Therefore, with increased operational frequencies, it is desirable to correspondingly decrease the operational voltage in order to minimize the power (and thereby the heat) generated by the electronic device. However, the dichotomy of decreasing the operational voltage of an electronic device operating at high frequencies is that the switching speeds of electronic devices operating at lower voltages are slowed as a result of the lower voltages. Thus, it is difficult to obtain high frequency operation of an electronic device with simultaneous low power operation. 
     Because maintaining low power consumption and preserving battery energy are important design criteria in portable data terminal systems, the dynamics of delivering power in multiple supply logic voltage computer systems must be taken into account. For example, the powering up of the system hardware devices requires more power than the average power consumed during normal operations, and therefore it is of great advantage to preserve battery energy by minimizing power consumption during system startup. A prudently designed power supply system for mixed logic voltage level computer hardware may consider the order in which the devices are powered up and the system hardware is reset. 
     Electronic devices are often rated according to their speed-power product, which is the average switching time multiplied with the average power dissipation. Energy may be conserved in multiple supply logic voltage computer systems by dynamically altering the clock speed of the system according to the processing needs of the system. By keeping the clock speed nominally low and increasing the speeds when applications demand higher speeds, the amount of energy generated and dissipated by the electronic systems may be minimized. Additionally, energy may be conserved by dynamically altering the operational logic voltage levels accordingly with required operational clock speed. Operational power levels above average rated power levels may be attained for momentary periods without damage to the electronic systems. 
     For the foregoing reasons, there is a need for a power supply system in multiple logic voltage computer systems that dynamically varies the logic voltage levels and operational frequency at which the particular circuitry operate according to the demands of a particular application in order to minimize power consumption in a hand held portable electronic system. 
     Thus, despite the intense efforts of those skilled in the art, there still exists a need for a power supply which is capable of dynamically switching the operational voltage and operational frequency in a multiple logic voltage level electronic system. 
     SUMMARY OF THE INVENTION 
     The present invention provides a dynamically switchable power supply which varies the operational frequency and operational voltage of an electronic system such that power consumption is minimized when high performance is not required and power utilization is maximized upon demand in an electronic system. 
     In a preferred embodiment an electronic system may dynamically switch operational voltages from a nominal 2.7 volts up to 3.3 volts or 5.0 volts when required. The electronic system may correspondingly vary the operational frequency from 40 MHz to 60 MHz or 80 MHz on demand. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The numerous objects and advantages of the present invention may be better understood by those skilled in the art by reference to the accompanying figures in which: 
     FIG. 1 is a block diagram of an exemplary embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF AN EXEMPLARY EMBODIMENT 
     FIG. 1 depicts a preferred embodiment of the present invention. FIG. 1 shows an arrangement for a dynamically adjustable multiple logic level, multiple frequency power supply which is capable of providing multiple logic voltage levels in a multiple logic voltage level system. Additionally, the embodiment of the present invention shown in FIG. I is capable of providing a variable clock frequency timing control signal for control of logic circuits requiring a clock signal. 
     A battery (BATT) 10 preferably provides a direct current voltage and is the primary source of energy for a portable electronic device in which the present invention may be utilized. The battery 10 preferably comprises some type of rechargeable cells such as nickel-cadmium, nickel-metal hydride, or lithium ion, for example. The battery 10 provides a direct current voltage to the multiple voltage convertors: a 5.0 volt convertor (CONV 5.0 V) 12, a 3.3 volt convertor (CONV 3.3 V) 14 and a 2.7 volt convertor (CONV 2.7 V) 16. The voltage convertors 12, 14 and 16 receive a direct current input voltage from the battery 10 whose voltage is generally poorly specified (i.e. fluctuates over a large percentage of its nominal voltage) and provide a constant, regulated output voltage which is well specified at a particular logic and supply voltage for other circuits (e.g. 5.0 V, 3.3 V, 2.7 V). The present invention also contemplates other combinations of operating logic voltages. 
     A central processing unit (CPU) 18 preferably functions as the main control unit of a portable electronic system. The CPU 18 may be one of various types of microprocessors, microcontrollers or digital signal processors. The CPU 18 receives operational voltages from the voltage convertors 12, 14 and 18. The CPU 18 is preferably a microprocessor which is capable of operating at multiple operational voltages, available from Advanced Micro Devices. The CPU 18 may receive a 5.0 volt operational voltage at input V1 from the 5.0 volt convertor 12, a 3.3 volt operational voltage at input V2 from the 3.3 volt convertor 14, and a 2.7 volt operational voltage at input V3 from the 2.7 volt convertor 16. The CPU preferably has a control output C1 to control the 5.0 volt convertor 12, a control output C2 to control the 3.3 volt convertor 14, and a control output C3 to control the 2.7 volt convertor 16. The voltage convertors 12, 14 and 16 may provide respective supply voltages VS1, VS2 and VS3 to the electronic system in which the present invention is utilized. 
     The CPU 18 may also have a clock signal input CK to receive a timing control signal which controls the frequency of operation of the CPU 18. The clock signal input CK to the CPU 18 is preferably provided by a frequency synthesizer (FREQ SYNTH) 20 which receives a fixed clock signal from a clock circuit (CLOCK) 22. The frequency synthesizer 20 receives the signal from the clock 22 and provides a timing control output signal by multiplying or dividing the frequency of the signal from the clock 22. 
     The clock 22 preferably provides a nominal frequency of 20 MHz which may be doubled to 40 MHz, tripled to 60 MHz or quadrupled to 80 MHz, for example, by the frequency synthesizer 20. The frequency of the timing control signal output from the frequency synthesizer 20 is preferably controlled by the CPU 18 with a frequency control signal CF. The frequency synthesizer 20 may provide a timing control signal F to the electronic system in which the present invention is utilized. 
     The power supply system so arranged is capable of conserving the energy consumed by the electronic system thereby extending the life of the battery 10 between recharge cycles. In an exemplary embodiment of the present invention, the system may nominally operate in a low power mode wherein the processor 18 runs at 2.7 volts and 40 MHz. The 2.7 volt operational voltage is sufficient to maintain the data in memory systems utilizing CMOS technology. When an application demands more processing speed and power, for example, the CPU may recognize the demand and raise the operational voltage to 3.3 volts and the operational frequency to 60 MHz for the duration of the application. If an application demands even greater speed and power, the CPU may recognize the greater demand and switch the operational voltage to 5.0 volts and the operational frequency to 80 MHz for the duration of the demand for higher power. Alternatively, the power levels may be user selectable, or may be monitored and controlled by a fuzzy logic routine which manages the power supply system in the background of operations of the processor 18. 
     The electronic system thus described may dynamically switch to momentarily operate at power and speed levels well above the rated average power levels for the processor and the electronic system while at the same time consuming less energy in the long run than if the voltage and frequency levels were fixed or semipermanently set. As a result, battery life is extended, a smaller sized heat sink or cooling fan for the CPU may be used, and higher processing power may be achieved for a given system. 
     In view of the above detailed description of a preferred embodiment and modifications thereof, various other modifications will now become apparent to those skilled in the art. The claims below encompass the disclosed embodiments and all reasonable modifications and variations without departing from the spirit and scope of the invention.