Emitter coupled logic circuit with MOS differential stage
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to logic circuits of the type comprising differential stages operating in linear mode, such as Emitter-Coupled Logic (ECL) circuits. 
     2. Discussion of the Related Art 
     ECL circuits are ones of the fastest logic circuits. To reach a high operation speed, ECL circuits are designed so that their bipolar transistors never go to saturation mode. Bipolar transistors saturate when their collector-emitter voltage Vce is lower than their base-emitter voltage Vbe. In such an instance, the base has a substantially higher capacity as compared to an instance in which the transistor operates in the linear mode, which causes conventional bipolar circuits to be slow. To prevent transistors from saturating, the transistors are connected in differential stages, hence the &#34;emitter-coupled&#34; terminology. Thus, differential signals are generally processed by ECL circuits, each component of a differential signal being applied to a respective input of a differential stage. 
     FIG. 1 represents an exemplary conventional ECL circuit, in this example a multiplexer. All the transistors of the ECL circuits are of the bipolar NPN-type. A first complementary signal A/A* is applied to the inputs of a first differential stage formed by a pair of transistors Q1 and Q2. The collectors of transistors Q1 and Q2 are connected to a high supply voltage Vcc through respective resistors Rc. The resistors Rc are mounted in the branches of the differential stage Q1, Q2. A second differential signal B/B* is applied to the inputs of a differential stage formed by a pair of transistors Q3 and Q4. The two branches of stage Q3, Q4 are connected to the branches of stage Q1, Q2, respectively. 
     Stages Q1, Q2, and Q3, Q4 are respectively connected in the branches of a differential stage formed by a pair of transistors Q5 and Q6, i.e., the collector of transistor Q5 is connected to the emitters of transistors Q1 and Q2, and the collector of transistor Q6 is connected to the emitters of transistors Q3 and Q4. Stage Q8, Q6 is biased through a supply source formed by a transistor Q7 whose emitter is connected to a low supply voltage GND (ground) through a resistor Re1, and whose collector is connected to the emitters of transistors Q5 and Q6. A reference voltage Vr applied to the base of transistor Q7 determines the biasing current of stage Q5, Q6. A differential selection signal S/S* is applied to the inputs of stage Q5, Q6 through follower-connected transistors Q8 and Q9. 
     The output of the logic circuit is a differential signal D/D* drawn from the branches of stage Q1, Q2 through follower transistors Q10 and Q11. 
     The follower transistors Q8-Q11 are respectively biased by transistors Q12-Q15 that are connected to emitter resistors (Re2 for transistors Q12, Q13 and Re3 for transistors Q14 and Q15) like transistor Q7. 
     The multiplexer operates as follows. If the differential signal S/S* is high (i.e., components S and S* are respectively high and low), transistor Q5 is conductive and transistor Q6 is blocked. Stage Q3, Q4 is then inactive; only stage Q1, Q2 imposes the value of signal A/A* to the output D/D* Conversely, if signal S/S* is low, signal B/B* ms present at output D/D*. 
     The follower transistors Q8 and Q9 are necessary to prevent transistors Q5 and Q6 from saturating. For example, if components A and S are at the same state, the collector and base voltages of transistor Q5 are equal, which ensures that the collector-emitter voltage of transistor Q5 is at least equal to the base-emitter voltage Vbe of transistor Q5. In the absence of the follower transistor Q8, the collector-emitter voltage of transistor Q5 would be substantially zero, causing transistor Q5 to saturate. 
     ECL signals have a small range, i.e., the voltage difference between the high state and the low state of a component of an ECL signal is small. This small range, approximately 0.5 volt, increases the rapidity of the logic circuit by decreasing the charge and discharge energy of any parasitic capacitances. 
     To determine the change over time of an ECL signal the emitter voltage (D*) of transistor Q10, for example, is considered. If transistors Q1 and Q4 are blocked, this voltage is substantially equal to Vcc-Vbe. If transistors Q1 and Q5 are conductive, the voltage drops by a value Vs, corresponding to the ECL range, equal to the product of the current in transistor Q7 by the resistance Rc. Accordingly, the voltage at the output D* varies from Vcc-Vbe to Vcc-Vbe-Vs. The circuit of FIG. 1 is designed to be connected through one of its input (A/A* B/B* S/S*) to the output (D/D*) of another similar circuit. The range Vs being fixed (approximately 0.5 volt), the voltage Vcc should be high enough so that the minimum value of the output of the other circuit does not cause transistors Q1, Q5, Q7 or Q8, Q5, Q7, for example, to saturate. Thus, the minimum voltage of output D* is equal to the sum of three voltages Vbe (of transistors Q1 or Q8, and Q5 and Q7, for example) and of a voltage Vr-Vbe occurring across the emitter resistor Re of transistor Q7. Therefore, the minimum voltage is 2Vbe+Vr. Therefore, the supply voltage Vcc should be such that: 
     
         Vcc-Vbe-Vs&gt;2Vbe+Vr. 
    
     For typical values Vs=0.5, Vbe=0.9, Vr=1.2, voltage Vcc should be at least equal to to 4.4 volts. An ECL circuit is typically supplied at 5 volts. 
     A drawback of ECL circuits is their high current consumption due to the fact that the currents supplied by the current sources are always consumed by the follower transistors or by either one of the other branches of a differential stage. If the supply voltage Vcc could be decreased, the current consumption would be decreased by the same extent. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to fabricate a differential stage logic circuit whose supply voltage is particularly low. 
     A further object of the present invention is to fabricate such a logic circuit consuming a particularly low current. 
     These objects are achieved according to an embodiment of the present invention by replacing specific bipolar transistors of the logic circuit with MOS transistors. 
     An illustrative embodiment of the present invention more particularly relates to a logic circuit comprising at least one first differential stage made of bipolar transistors operating in linear mode. The differential stage is mounted in a branch of a second differential stage biased by a current source, in which the second stage and the current source are made of MOS transistors. 
     According to an embodiment of the invention, the gates of the MOS transistors of the second stage directly form logic circuit inputs. 
     According to an embodiment of the invention, the current source comprises a MOS transistor whose source is directly connected to a supply voltage. 
     A multiplexer according to the invention comprises two first stages whose corresponding branches are interconnected, these two stages being respectively connected in the branches of the second stage. 
     A logic gate according to the invention includes a first stage connected to a first branch of the second stage, the second branch of the second stage being connected to a branch of the first stage. 
     According to an embodiment of the invention, the bipolar transistors are NPN transistors and the MOS transistors are N-channel transistors. 
     The foregoing and other objects, features, aspects and advantages of the invention will become apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1, above described, represents a conventional ECL circuit; 
     FIG. 2 represents an exemplary logic circuit with differential stages according to the present invention; and 
     FIG. 3 represents another exemplary logic circuit according to the present invention. 
    
    
     DETAILED DESCRIPTION 
     A differential stage logic circuit according to an illustrative embodiment of the invention generally comprises a first level of differential stages formed by NPN bipolar transistors. In contrast, a second level of differential stages, comprising in their branches differential stages of the first level, is formed by N-channel MOS transistors. Similarly, the biasing current sources of the stages of the second level and of the follower transistors are also formed by N-channel MOS transistors. 
     FIG. 2 illustrates an exemplary logic circuit fabricated according to an embodiment of the present invention. The circuit of FIG. 2 is a multiplexer of the same type as that of FIG. 1, and the same elements as in FIG. 1 are designated with the same references. In FIG. 2, the differential stage Q5, Q6 of FIG. 1 is replaced with a differential stage including MOS transistors M5 and M6. Similarly, the current sources constituted by transistors Q7, Q14, and Q15, as well as the associated emitter resistors Re of FIG. 1, are replaced with MOS transistors M7, M14, and M15, which are directly connected to ground GND. In addition, the stage M5, M6 can directly receive the differential signal S/S*, without it being necessary to provide follower transistors and corresponding biasing sources (Q8, Q9, Q12, and Q13 in FIG. 1). Accordingly, the current consumption of the circuit is decreased by suppressing as many pairs of biasing sources as MOS differential stages. 
     The gate-source threshold voltage Vt of a MOS transistor plays the same role as the base-emitter voltage Vbe of a bipolar transistor. Thus, it could be assumed, from calculations carried out for the circuit of FIG. 1, that the minimum voltage Vcc is 2Vt+2Vbe+Vs. This value would be higher than the minimum voltage Vcc calculated for the circuit of FIG. 1 (with the typical values Vs=0.5, Vbe=0.9, and Vt=1.2 V). However, an aspect of the present invention has been to note that the fact that the drain-source voltage of a MOS transistor is lower than the threshold voltage Vt is not an impairment. Indeed, the gate capacitance of the MOS transistor does not vary. The only, not impairing, difference is that the MOS transistor turns to a resistive operating mode, during which the drain-source resistance varies as a function of the gate-source voltage. Practically, this drain-source voltage in resistive mode, referred to as Von, does not exceed 0.3 volt. 
     Therefore, the minimum voltage Vcc is expressed by 2Vbe+2Von+Vs which is approximately 2.9 volts using the above-mentioned typical values. A logic circuit according to the invention is particularly well adapted for integration in a 0.7-micron technology which withstands a supply voltage of approximately 3.3 volts. 
     Also, the minimum voltage Vcc may be calculated with respect to the voltage to be applied to the gates of transistors M5 and M6. This minimum voltage is then Vbe+Vt+Von, where Vt is the threshold voltage of transistors M5 and M6, and Von is the drain-source voltage of transistor M7. The minimum voltage Vcc is substantially equal to the voltage previously calculated, because voltage Vt is substantially equal to Von+Vbe. 
     Follower transistors need not precede transistors M5 and M6 as in FIG. 1. For example, if the components A and S are at the same voltage, the drain-source voltage of transistor M5 is equal to Vt-Vbe, i.e., approximately Von. 
     In addition, transistors M7, M14, and M15 need not be provided with source resistors. In FIG. 1, emitter resistors were provided to compensate for differences between the transistor base-emitter voltages and voltage drops between the emitters caused by relatively high currents flowing through the conductors connecting the emitters. Bipolar transistors have a high transconductance. So, in the absence of emitter resistors, a low difference between the base-emitter voltages of two of the transistors of the current source could cause a significant difference between the collector currents of the bipolar transistors. In contrast, MOS transistors have a low transconductance, which allows the suppression of source resistors. 
     Since MOS transistors have a lower transconductance than bipolar transistors, the size of transistors M5 and M6 are typically relatively large so that the transconductance of the MOS transistors has the same order of magnitude as the transconductance of the bipolar transistors Q5 and Q6 of FIG. 1. This increase in size is not impairing because it is compensated for by the fact that the follower transistors Q8 and Q9, the corresponding biasing sources, and the emitter resistors of FIG. 1 are omitted. The increase in the size generally causes an increase in the gate capacitance of the MOS transistors. However, the possible resulting speed decrease is compensated for by increasing the biasing current of the MOS transistor stages. This current increase is not impairing since many biasing sources (Q12, Q13) have been omitted and, furthermore, this still increases the MOS transistor transconductance. 
     In the embodiments shown, MOS transistors have not been substituted for bipolar transistors Q1-Q4 because, if the voltage Vcc is selected at its minimum value, the maximum gate-source voltage of the MOS transistors would be approximately Vbe+Vs, which not substantially exceeds the threshold voltage Vt of a MOS transistor. A MOS transistor would be hardly conductive and could only partially transmit the current of the differential stage to its corresponding branch. In contrast, value Vbe+Vs is highly sufficient to render a bipolar transistor entirely conductive. 
     Of course, the invention is not limited to the multiplexer circuit of FIG. 2 which is given by way of example only. 
     FIG. 3 illustrates another exemplary logic circuit according to the invention, in this case an AND gate (or NAND gate depending on whether outputs D/D* are inverted). A first differential signal A/A* is applied to the inputs of a stage comprising transistors Q1 and Q2 that are connected like transistors Q1 and Q2 of FIG. 2 to collector resistors Rc and to output transistors Q10 and Q11. The stage Q1, Q2 is connected in one branch of a differential stage made of MOS transistors M5 and M6, whose other branch (drain of transistor M6) is connected to the collector of transistor Q2. The stage M5, M6 receives a differential signal B/B* and is biased through a MOS transistor M7 like stage M5, M6 of FIG. 2. 
     Having thus described at least one illustrative embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The invention is limited only as defined in the following claims and the equivalents thereto.