Aircraft Equipment Problem Less Severe; Deviation / Discrepancy - Procedural Published Material / Policy
General None Reported / Taken
Aircraft
I recently was informed about a trim runaway situation involving an ERJ170/175 after take-off from Atlanta. I worked briefly as a consultant to [Company] and manager doing reviews of the TTP [time-triggered protocol] Fly by Wire Flight Control FPGA [field-programmable gate array] and hardware. While there I observed that the Trim Control Unit used a Lattice FPGA which normally does not offer Single Event Upset Resistance unless specifically placed in the FPGA manually by the design engineer using one of the applicable techniques as outlined in the FPGA white papers on SEU [single-event upsets]. The TTP FPGA which [a co-worker] was in charge of used these and I and other consultants who had access to this FPGA code identified the SEU issues with the TTP FPGA; and people who followed me addressed some (or all) of the issues with the TTP ASIC [application-specific integrated circuit]. I did not have access to the Trim Control FPGA code. This trim circuit is common to the A220; ERJ170; ERJ175; ERJ195; C929; and possibly the MRJ-70 and MRJ-100 airliners. While a low probability; it is still possible that SEU toggling a bit in the Lattice Trim Control FPGA could result in a trim runaway situation on any of these airliners depending on if they all use identical trim control FPGA code.
Reporter with experience in flight control engineering and design reported a concern that trim runaway is possible in several aircraft types.