the preferred embodiment of the present invention and its advantages are best understood by referring to fig1 through 22 of the drawings , like numerals being used for like and corresponding parts of the various drawings . the present invention will be described in conjunction with the following table of contents : fig1 and 2 are isometric illustrations of the disclosed bone growth stimulator configured for generating an alternating current output . in particular , fig1 depicts the ac bone growth stimulator ready for implantation into a patient . fig2 depicts the disclosed bone growth stimulator prior to final assembly . fig1 depicts a bone growth stimulator configured for an alternating current (&# 34 ; ac &# 34 ;) output generally at 10 . ( hereinafter the &# 34 ; ac stimulator &# 34 ;). ac stimulator 10 comprises a thin elongate arm 12 made of a flexible elastomeric material connecting a first electrode 14 and a second electrode 16 . arm 12 maintains a predetermined distance between electrodes 14 and 16 while ac stimulator 10 is generally flat . arm 12 , however , flexes allowing ac stimulator 10 to more readily conform to the contours of the patient into which it is surgically implanted . in the preferred embodiment , arm 12 is fabricated from silicon manufactured by dow - corning designated mdx 4 - 4516 . other implantable grade materials such as urethane and silicon - urethane blends may be used in place of silicon . electrodes 14 and 16 are manufactured from titanium . additionally , electrode 14 is an exposed portion of a titanium housing imbedded in ac stimulator 10 . ( shown in fig2 .) the housing is coated with an electrically non - conductive material such as parylene such that no portion of titanium other than electrode 14 is exposed . ac stimulator 10 is approximately 6 inches long and 0 . 2 inches thick . approximately 5 . 5 inches of ac stimulator 10 consists of arm 12 . the remaining portion of ac stimulator 10 comprises a coated electronics housing ( shown in fig2 ). in operation , ac stimulator 10 generates an alternating current between electrodes 14 and 16 . the resulting electric field may be used to stimulate bone healing . fig2 depicts ac stimulator 10 before arm 12 has been formed and before a non - conducting layer of parylene has been applied to a housing 18 . housing 18 comprises a feed - through assembly 20 . feed - through assembly 20 passes an electrical lead 22 to electrode 16 . the dashed line on housing 18 indicates the location of electrode 14 after final assembly . additionally , housing 18 has two lips 24 which have an irregular surface . lips 24 thereby facilitate a secure union between arm 12 ( shown in fig1 ) and housing 18 . in one embodiment , housing 18 is manufactured from two clam - shell halves having a length equal to the final length of housing 18 . in this first embodiment , the electronics are inserted between the two clam shells and the clam shells are welded together to form a hermetic seal . in the second embodiment , housing 18 is formed from two clam - shell halves which are slightly longer than the final length . these clam shells are welded together initially without the electronic assembly . the end portion is then removed , the electronics are inserted therein and a cap is welded over the opening to form a hermetic seal . in the one embodiment , lead 22 is a helical coil comprised of a medical grade metal alloy such as mp35n . fig3 depicts an isometric illustration of the disclosed bone growth stimulator 26 configured for generating a direct current output ( hereinafter the &# 34 ; dc stimulator &# 34 ;). dc stimulator 26 comprises an anode 28 and two cathodes 30 . anode 28 is a quantity of platinum electroplated onto the housing of dc stimulator 26 ( shown substantially in fig2 ). dc stimulator 26 has a short elastomeric arm 32 to better smooth dc stimulator 26 for insertion into the human body and to insulate the feed - through assembly ( depicted in fig2 ). as described in connection with fig1 and 2 , dc stimulator 26 has a titanium housing . it is not coated with a non - conductive material . in addition , cathodes 30 are coupled to electronics within dc stimulator 26 by a coil manufactured from a suitable medical grade metal alloy such as mp35n . leads 34 are not completely incased in arm 32 so that cathodes 30 may be more easily placed on or within the bone mass to be treated . leads 34 are sheathed in a tube of elastomeric material . in operation , dc stimulator 26 generates a dc current between cathodes 30 and anode 28 . as will be described in connection with fig1 through 22 , each cathode 30 of dc stimulator 26 is an independent current path . fig4 is a graphical representation of the output of the bone growth stimulator depicted in fig1 and 2 . ac stimulator 10 ( depicted in fig1 and 2 ) generates an alternating current output . in the preferred embodiment , ac stimulator 10 generates an asymmetric output of 99 pulses ( a &# 34 ; burst &# 34 ;) followed by a rest period . after the rest period , the burst / rest cycle is repeated until ac stimulator 10 is turned off . the positive portion of the output pulse , indicated having the duration t 1 , is approximately 65 μs long and has an amplitude of 900 μa . this current generates approximately 3 mv / cm at the healing site in implantation configuration depicted in fig6 . the negative portion of the output , indicated having the duration t 2 , is approximately 195 μs long and has an amplitude of - 300 μa . thus generates - 1 mv / cm at the same healing site . the ac output signal is off after 99 pulses for approximately 640 milliseconds . the resulting burst / rest rate has a frequency of 1 . 49 hz . it should be understood that ac stimulator 10 may be made to output other wave forms , both symmetric and asymmetric . for instance , ac stimulator 10 could produce a wave form having a sinusoidal form . the amplitude of the negative portion of the output may be modified to provide a field strength of - 0 . 3 to - 3 mv / cm at the bone site with a corresponding field strength of 0 . 9 to 9 mv / cm for the positive portion of the waveform , to keep the ratio between the positive portion and negative portion of the output at approximately three to one . this range produces optimum healing results . fig5 is a graphical representation of the output of the bone growth stimulator depicted in fig3 . dc stimulator 26 ( shown in fig3 ) generates a constant negative current between its two cathodes and anode of approximately - 20 μa during its operation . fig6 is a simplified cross - sectional view of the human body depicting one embodiment of an implant configuration for ac bone growth stimulator 10 depicted in fig1 and 2 . ac stimulator 10 is bisected along its longitudinal axis in a plane generally perpendicular to the planes containing the electrodes 14 and 16 . ac stimulator 10 is implanted in the human body indicated generally by 36 near a vertebra 38 . ac stimulator 10 is placed near vertebra 38 so that the electric field generated between electrodes 14 and 16 is made to penetrate a portion of vertebra 38 in need of bone growth stimulation . the outer limit of the electric field generated by ac stimulator 10 is indicated generally by field lines 40 . vertebra 38 typically is in need of bone growth stimulation when two or more vertebrae are clinically fused together . because of the ac nature and the electrode spacing of ac stimulator 10 , vertebra 38 will receive the benefit of the electric field 40 even if ac stimulator 10 does not abut vertebra 38 . for instance , ac stimulator 10 may be placed further than 1 centimeter away from the injured section of vertebra 38 . this allows a surgeon to implant ac stimulator 10 subcutaneously . this simplifies implant and explant , reduces the chance of infection and improves imaging results . imaging results are improved because there are no foreign objects near vertebra 38 . in the preferred embodiment , ac stimulator 10 is implanted subcutaneously with its electrodes 14 and 16 facing away from vertebra 38 . empirical studies have determined that this placement results in a better electric field distribution and lower inadvertent muscle stimulation . fig7 is a simplified isometric view of the human body depicting one embodiment of an implant configuration for the dc stimulator 26 depicted in fig3 . here , dc stimulator 26 is used to fuse a bone growth mass 42 to two adjacent vertebrae 38 of spine 44 . dc stimulator 26 may be implanted subcutaneously . however , leads 34 must be inserted such that cathodes 30 ( not shown ) are directly in or adjacent to bone graft mass 42 . it is not required that both cathodes 30 be placed at the same bone site . it should be understood that both ac stimulator 10 and dc stimulator 26 may be implanted near any bone for the repair of several types of bone injuries . for instance , the stimulators may be used to promote bone healing in the long bones of the body . also , the stimulators may be used at a bone site to promote the healing of a bone fracture . fig8 a and 8b depict left and right halves of a block diagram of the application specific integrated circuit (&# 34 ; asic &# 34 ;) 46 used in the bone growth stimulator depicted in fig1 through 3 . integrated circuit 46 has 28 external connections , pads 1 through 28 . internally , ic 46 comprises a crystal oscillator circuit 48 , a power on reset circuit 50 , a main time base circuit 52 , an output driver circuit 54 , a transmitter circuit 56 , a ppm decoder circuit 58 , a communication modem circuit 60 , a lead status circuit 62 , a receiver circuit 64 , a battery status circuit 66 , and a voltage reference / regulator circuit 68 . crystal oscillator circuit 48 generates a 76 . 8 khz clock signal labeled c76 -- 8 . this circuit has three external connections , xtrm , xtal1 , and xtal2 , and one input gnd -- ref . this circuit is more fully described in connection with fig1 . power on reset circuit 50 generates three reset outputs , nreset , nrstprg , nrst , to put all other circuits in an initial condition after powering up . this circuit has four inputs , c76 -- 8 , c1 -- 49 , nstrt and ipor , and two test points , test and tp6 . power on reset circuit 50 is more fully described in connection with fig1 . main time base circuit 52 generates the pulse timing signals for control of the output driver circuit 54 . in addition , main time base circuit 52 acts as the 24 - hour timer for ic 46 . this circuit generates 8 outputs , biason , niplus , iminus , iminus2 , nout -- on , nen -- anl , anl -- clk , and c1 -- 49 . this circuit has six inputs , nreset , rec -- off , c76 -- 8 , dcon , stim0 , stim1 , and two test points , test and tp1 . main time base circuit 52 is more fully described in connection with fig1 . output driver circuit 54 controls the output signal , out1 and out2 delivered to the patient . this circuit has inputs gnd -- ref , nout -- on , iminus , iminus2 , niplus , and biason and external connections ilimit , itrm , and symtrm . output driver circuit 54 is more fully described in connection with fig1 . transmitter circuit 56 combines the pulse timing parameters from ppm decoder 58 with the data output from communication modem 60 to transmit a low frequency magnetic pulse to an external receiver through ntrans -- out . this circuit has inputs c76 -- 8 , startclk , oneclk , zeroclk , tcode and xmit . transmitter circuit 56 is more fully described in connection with fig1 . ppm decoder circuit 58 determines if received information from receiver circuit 64 is a valid down - link communication . also , ppm decoder circuit 58 generates the pulse position protocol used by transmitter circuit 56 . this circuit has outputs c38 -- 4 , nppmrst , dstb , data , startclk , rec -- off , zeroclk , oneclk . ppm decoder circuit 58 also has inputs c76 -- 8 , nrec -- out , ntrans , nrst , and 2 test points , test and tp4 . this circuit is more fully described in connection with fig1 a and 15b . communication modem circuit 60 controls the mode of operation of ic 46 through two of its output bits , stim0 and stim1 . these two bits define the four possible modes of operation : off , four hours on / 20 hours off , eight hours on / 16 hours off , or continuously on . also this circuit receives signals from battery status circuit 66 indicating the status of the battery ( eol and lowbatt ) and from lead status circuit 62 indicating the impedance of the output leads ( ldhigh and ldlow ). the circuit then generates an 11 - bit communication word and transmit enable ( tcode and xmit ) for transmission by transmitter circuit 56 . communication modem circuit 60 circuit has eleven other inputs , nrstprg , c38 -- 4 , nppmrst , dstb , data , startclk , rec -- off , dcon , and code , two other outputs , ntrans and nstrt , and two test points , test and tp5 . communication modem circuit 60 is more fully described in connection with fig1 . lead status circuit 62 compares the impedance of the output leads with a predetermined threshold or thresholds . it has two outputs , ldlow and ldhigh . the circuit has inputs , nrst , iminus , anl -- clk , dcon , nen -- anl , ilead , and connections to out1 , out2 , ldtrm1 and ldtrm2 , and two test points , test and tp2 . lead status circuit 62 is more fully described in connection with fig1 . receiver circuit 64 generates a digital output , nrec -- out from an analog input recv . this signal is received from a device external to ic 46 . receiver circuit 64 has an additional input irec . this circuit is more fully described in connection with fig1 . battery status circuit 66 monitors the voltage supplied by the associated battery and signals the communication modem circuit 60 when the battery reaches two trippoints with lowbatt and eol . this circuit has inputs , nrst , rec -- off , c1 -- 49 , nen -- anl , ibatt , and gnd -- ref , an external connection to eoltrm and two test points , test and tp3 . battery status circuit 66 is more fully described in connection with fig1 . voltage reference / regulator circuit 68 generates the bias currents used in ic 46 : ipor , irec , ibatt , ilead , idcon , icode , and itest . this circuit has inputs , vset1 , vset2 , and vref and output gnd -- ref . voltage reference regulator circuit 68 is more fully described in connection with fig2 . fig9 a is a graphical representation of the communication protocol used by the circuit depicted in fig8 a and 8b . integrated circuit 46 transmits and receives data at 1200 hz . this rate results in a 833 μs overall transmission window . after receiving a start pulse at the start window , integrated circuit 46 looks for the presence or absence of a data pulse in the &# 34 ; one window ,&# 34 ; &# 34 ; zero window &# 34 ; or &# 34 ; no pulse detected window &# 34 ; . as depicted , these three data windows occur approximately 208 μsec , 416 μsec , and 624 μsec after the start pulse . the communication protocol results in a data logic level one if a pulse is received in the one window and a data value zero if a pulse is received in the zero window . a communications error is indicated if a pulse is received in the no pulse detected window . the disclosed communications protocol permits additional error checking by requiring a pulse at both start windows and requiring one but not both of the one window and zero window to have a data value . each window is approximately 104 μs long . data detection is enabled only in the four windows described above during each communication . an external receiver / transmitter may be fabricated from a microprocessor with 1200 baud capability connected to a suitable coil . fig9 b and 9c depict tables containing an explanation of the down - link program data word and up - link handshake respectively of the circuit depicted in fig8 a and 8b . integrated circuit 46 uses an 11 bit program data word . the down - link , or received data word comprises three programmable data bits . the second , third , and fourth bits of the down link program data word contain data which is used by integrated circuit 46 to adjust its mode of operation . bit 2 is a read - not write ( rnw ) bit . when rnw equals zero , ic 46 acts upon the third and fourth bits as subsequently described . if rnw equals one , then ic 46 will simply up - link an 11 bit program data word to the external transmitter / receiver . the third and fourth bits , stim0 and stim1 indicate how long the bone growth stimulator runs . as depicted in fig9 a , the bone growth stimulator has four modes of operation . ( 1 ) it may be continuously off . ( 2 ) it may be on 4 hours , off 20 hours . ( 3 ) it may be on 8 hours , off 16 hours . ( 4 ) it may operate continuously . all other bits in the down link program data word do not vary . the first , sixth , and seventh bits must be a logic 1 while the fifth , eighth , and eleventh bits must be a 0 . the ninth and tenth bits must follow the hard - wired control bits dcon and code respectively . dcon is an externally hard - wired bit indicating whether the bone growth stimulator is configured for ac or dc output . a logical level of 0 indicates an ac output while a logic level of 1 indicates a dc output . code is an externally hardwired input bit . it may be used , for instance , to indicate a first and second version of manufactured stimulators . the down - link program data word is transmitted left to right . the up - link program data word transmitted from integrated circuit 46 to an external receiver has 8 bits of data , an odd parity check , and start and stop bits . the start and stop bits are logic high and low respectively . the second and third bits indicate the present mode of operation of ic 46 as described in connection with the down - link program data word . the fourth and fifth bits indicate whether the dcon or codes bits are high or low . the sixth and seventh bits indicate the status of the stimulator leads . in the ac mode , these bits indicate whether electrode 16 ( shown in fig1 and 2 ) is normal , has a low impedance or has a high impedance . in the dc mode , these bits indicate whether either of leads 34 ( shown in fig3 ) has an abnormally high impedance . the particular logic values for each condition in each mode is defined in this figure . the eighth and ninth bits indicate the status of the internal battery of the bone growth stimulator . the battery status circuitry 62 ( depicted in fig8 ) monitors the battery voltage for two trippoints , 2 . 1 v and 2 . 4 v . these voltages correspond to the end of life ( eol ) and low battery ( lowbatt ) depicted as indicated in the figure . the tenth data bit is an odd parity check bit . it is high when the number of ones preceding it is even and it is low when the number of ones preceding it is odd . the following signals are used by integrated circuit 46 internally and as external connections : anl -- clk is generated by main time base circuit 52 . it enables lead status circuit 62 during certain intervals of the dc output signal . biason is generated by the main time base circuit 52 . in the ac mode , it turns on the bias current for the positive portion of the output signal . it is disabled during the negative portion of the ac signal output . in the dc mode , it is continuously high . biason is used by the output driver . c1 -- 49 is generated by main time - base circuit 52 . it is a clock signal of 1 . 49 hz . it is used as a gating signal for the control logic of the output switches of output driver 54 . c76 -- 8 is generated by crystal oscillator circuit 48 . it is a clock signal of 76 . 8 khz . it is the main time signal used by integrated circuit 46 . code is an externally hardwired input bit ( pad 10 ). the communication protocol requires that communication words have a matching bit for a valid downlink . data is generated by ppm decoder block 58 . it is the output from the ppm decoder indicating a valid data 0 or data 1 received from receiver circuit 64 . dcon is an externally hardwired bit ( pad 13 ). it is used to indicate for which configuration , ac or dc , the circuit is set up . a logic level of 0 indicates the ac configuration while logic level 1 indicates dc configuration . dstb is generated by ppm decoder circuit 58 . it strobes valid data into communication modem circuit 60 . eol is generated by battery status circuit 66 . this bit will have a logic value of 1 when the battery voltage is less than or equal to 2 . 1 v . otherwise it will have a logic value of 0 . eoltrm is an input to battery status circuit 66 . it is coupled to v dd through an external capacitor and resistor ( pad 12 ). it is used to trim the low battery and end of life voltages to the desired trippoints ( here , 2 . 4 and 2 . 1 v respectively ). gnd -- ref is generated by voltage reference / regulator circuit 68 . it is a buffered voltage level , 1 . 5 v less than v dd . it is brought off - chip through pad 18 . ibatt is generated by voltage reference regulator circuit 68 . it produces a 20 na current sink used to establish the bias current in battery status circuit 68 . icode is generated by the voltage reference / regulator circuit 68 . it produces a 100 na current sink used to pull down the code pin if that pin is left open . idcon is generated by voltage reference / regulator circuit 68 . it produces a 100 na current sink used to pull down the dcon pin if that pin is left open . ilead is generated by voltage reference / regulator circuit 68 . it is a 20 na current source used to bias lead status circuit 62 . ilimit is an external connection to output driver circuit 54 ( pad 22 ). in the ac mode , ilimit is not used . in the dc mode , ilimit is connected to the stimulator housing and acts as the unit anode . iminus is generated by main time base circuit 52 . in the ac mode , it switches the negative output portion of the signal . in the dc mode , it switches the output current . it is used by output driver circuit 54 . iminus2 is generated by main time base circuit 52 . in the ac mode , it is not used . in the dc mode , it switches the output current for out2 . it is used by output driver circuit 54 . ipor is generated by voltage reference / regulator 68 . it is a 10 na current sink used to bias the power on reset circuit 50 . irec is generated by voltage reference / regulator 68 . it is a 20 na current source used by the receiver circuit 64 . itest is generated by the voltage reference / regulator 68 . it is a 100 na current sink used to pull down the test pin if that pin is not connected . itrm is an external connection to v dd through an external resistor ( pad 25 ). the resistor is used to trim the output current in both the ac and dc modes . it is an input to output driver circuit 54 . ldhigh is generated by the lead status unit . in the ac mode , a logic level 1 indicates a high lead impedance . in the dc mode , a logic level 1 indicates a high lead impedance for out2 . ldlow is generated by the lead status unit . in the ac mode , a logic level of 1 indicates a low lead impedance . in the dc mode , logic level of 1 indicates a high lead impedance for out1 . ldtrm1 is an input to lead status circuit 62 . it is coupled to gnd -- ref through an external resistor ( pad 20 ). it sets the trippoints for lead status circuit 62 . ldtrm2 is an input to lead status circuit 62 . it is coupled to gnd -- ref through two resistors in series ( pad 19 ). it is used to set the trippoints for lead status circuit 62 . lowbatt is generated in battery status circuit 66 . this signal is normally low . when the battery output drops below 2 . 4 v , this signal switches to logic level 1 . nen anl -- is generated by main time base unit 52 . in the ac mode , this signal enables the battery and lead status circuits during the negative portion of the output signal . otherwise , these circuits are disabled to conserve power . in the dc mode , this signal enables the battery and lead status circuits once every 1 . 49 hz . niplus is generated by main time base circuit 52 . in the ac mode , this signal controls the output switch for the positive portion of the output signal . it is not used in the dc mode . nout -- on is generated by main time base circuit 52 . in the ac mode , this signal enables the output driver during the burst period . it is otherwise off . in the dc mode , this signal is on for the duration of the stimulus , i . e ., 4 hours , 8 hours , or continuous . nppmrst is generated by ppm decoder circuit 58 . it is a primary reset for the communication modem circuit 60 . nrec -- out is generated by the receiver circuit 64 . it is a digital representation of the received external input . nreset is generated by power on reset circuit 50 . it is reset on power up and after a valid downlink / uplink communication . in either case , it returns high after two 76 . 8 khz clock cycles . nrst is generated by power on reset circuit 50 . it is reset on power up and after a valid downlink / uplink communication . in either case , it returns to its high state after one 1 . 49 hz clock cycle . nrstprg is generated by power on reset circuit 50 . it is reset on power up . it returns to its high state after nrst transitions high . nstrt is generated by communication modem circuit 60 . it initiates a reset after a valid downlink / uplink communication . ntrans is generated by communication modem circuit 60 . it indicates the completion of a valid downlink communication . ntrans -- out is generated by transmitter unit 58 . it is the output signal of the driver stage of the transmitter circuit 56 . it is connected to an external coil ( pad 8 ). oneclk is generated by ppm decoder circuit 58 . it is the decoded clock signal corresponding to the data position for logic level one in the communications protocol . out1 is an output from output driver circuit 54 ( pad 23 ). in the both the ac and dc modes , this is the output signal . out2 is an output from output driver circuit 54 ( pad 24 ). in the ac mode , out2 is connected to out1 . in the dc mode , out2 is the second independent current path . rec -- off is generated by ppm decoder circuit 58 . this signal disables the receiver , battery status and output driver circuits during an uplink operation . recv is input to receiver unit 56 . it is coupled to an external coil ( pad 9 ). startclk is generated by ppm decoder circuit 58 . it is a decoded clock signal corresponding to the start position in the communications protocol . stim0 is generated by communication modem circuit 60 . it is used with the stim1 bit to generate the four stimulation modes ( off , on 4 hours , on 8 hours , on continuously ). stim1 is generated by communication modem circuit 60 . it is used with the stim0 signal to generate the four stimulation modes ( off , on 4 hours , on 8 hours , on continuously ). symtrm is an input to output driver circuit 54 . it may be coupled to gnd -- ref or v dd through an external resistor ( pad 21 ). it is used to trim the positive portion of the output current . it is presently not used . tcode is generated by communication modem circuit 60 . it is the data output sent to transmitter circuit 56 for external transmission . test is a testing signal used in conjunction with tp1 through tp6 . it is brought off chip at pad 4 . tp1 through tp6 are external test points ( pads 26 , 27 , 28 , 1 , 2 , and 3 respectively ). they output data from the various cell blocks for testing purposes . v dd is an external connection to the positive terminal of the 2 . 8 v battery ( pad 14 ). v ss is an external connection to the negative terminal of the 2 . 8 v battery ( pad 11 ). vref is an input to voltage reference / regulator circuit 68 . it is coupled to a 1 . 5 v unbuffered reference voltage ( pad 17 ). vset1 is an input to voltage reference / regulator circuit 68 . it is coupled to v dd through two external resistors in series ( pad 15 ). it is used to trim vref . vset2 is an input to voltage reference / regulator circuit 68 . it is coupled to v dd through a resistor ( pad 16 ). it is also used to trim vref . xmit is generated by communication modem circuit 60 . it enables the transmitter output . xtal1 is an external connection to one terminal of a 76 . 8 khz oscillator / resistor circuit ( pad 6 ). it is an input to crystal oscillator circuit 48 . xtal2 is an external connection to one terminal of a 76 . 8 khz oscillator / resistor pair ( pad 7 ). it is an input to crystal oscillator circuit 48 . xtrm is an external connection to v dd through a resistor ( pad 5 ). it sets the bias current on the 76 . 8 khz crystal oscillator . zeroclk is generated by ppm decoder circuit 58 . it is the decoded clock signal corresponding to a logic level zero in the communications protocol . fig1 illustrates a block diagram of the crystal oscillator circuit 48 depicted in fig8 a . crystal oscillator circuit 48 comprises a crystal driver 70 , a hysteresis comparator 72 , and an output driver 74 . crystal driver 70 is connected to crystal x1 and resistor r2 through pads 6 and 7 . crystal x1 and resistor r2 are themselves connected in parallel . the inputs of hysteresis comparator 72 are also coupled to crystal x1 and resistor r2 through pads 6 and 7 . the output of hysteresis comparator 72 is connected to output driver 74 which outputs signal c76 -- 8 . an external resistor r1 is coupled between v dd and pad 5 . pad 5 is coupled to two current sources 76 and 78 in series . current source 76 is controlled by the signal gnd -- ref . current mirrors 80 , 82 , and 84 supply the bias current to crystal driver 70 , hysteresis comparator 72 , and output driver 74 , respectively . each of these current mirrors mirror current source 78 times some integer . this relationship is indicated by the dashed line . in particular , current mirror 80 sources a current five times that of current source 78 , current mirror 82 sources three times the amount of current sourced by current source 78 and current mirror 84 sources two times the current of current source 78 . current source 78 and current mirrors 80 , 82 and 84 are connected to v ss . in operation , crystal driver 70 applies a voltage across crystal x1 such that crystal x1 oscillates at the regular frequency of 76 . 8 khz . hysteresis comparator 72 toggles if the potential across crystal x1 swings approximately 100 mv . the digital high low output of hysteresis comparator 72 is amplified by output driver 74 . driver 74 ensures that the final signal swings rail to rail ( v ss to v dd ). resistor r1 in conjunction with gnd -- ref is used to adjust the bias current mirrors 80 , 82 , and 84 . fig1 illustrates a block diagram of the power on reset circuit 50 depicted in fig8 a . power on reset circuit 50 comprises a diode 86 connected between v dd and a node 88 . node 88 is coupled to v ss through a capacitor 90 . capacitor 90 may have a capacitance of 6 pf . node 88 is coupled to the input of a buffer 92 . buffer 92 is coupled to a node 94 through a 10 kohm resistor 96 . node 94 acts as one input to latches 98 , 100 , and 102 . latches 98 and 102 are dual reset latches , while latch 100 is a single reset latch . latch 98 gets set ( nreset goes high ) two 76 . 8 khz clock cycles after both reset conditions ( npor , node 94 , is low or nstrt is low ) return to logic one . similarly , latch 102 gets set one 1 . 49 hz cycle after both reset conditions go high . latch 100 gets set one 1 . 49 hz cycle after reset condition npor goes high . as depicted , the outputs of latches 98 , 100 , and 102 generate signals nreset , nrstprg , and nrst respectively . tp6 is connected through pad 3 to either node 94 or nrst . the particular connection is dependant upon the logic level of test applied at pad 4 . when test equals zero , tp6 is connected to nrst . when test equals one , tpc is connected to node 94 . in operation , a power drop will cause capacitor 90 to discharge . this will momentarily bring node 88 low . buffer 92 will reset latches 98 , 100 , and 102 . latch 98 will return high after two full clock cycles of the clock signal c76 -- 8 . latches 100 and 102 will return high after one cycle of the clock signal c1 -- 49 . in addition , latches 98 and 102 may be reset by nstrt . during testing , tp6 views the output of slow buffer 92 at node 94 or the output of latch 102 . resistor 96 prevents tp6 from pulling down the output of buffer 92 during testing . fig1 illustrates schematically the main time base circuit 52 depicted in fig8 b . main time base circuit 52 generates the clock signals necessary for output driver circuit 54 ( shown in fig1 ). main time base circuit 52 comprises a series of cascaded divide - by circuits 104 , 106 , 108 , 110 , 112 , 114 , and 116 and various logic gates driven by the divide - by circuits . each divide - by circuit lowers the frequency of the clock signal input to it by particular value . divide - by circuit 104 is a divide - by 5 circuit which has as an input signal c76 -- 8 . divide - by circuit 104 therefore outputs a 15 . 36 khz signal . the output of divide - by circuit 104 is connected to the input of divide - by circuit 106 . divide - by circuit 106 , a divide - by 4 circuit , generates a 3 . 84 khz output . the output of divide - by circuit 106 is connected to the input of divide - by circuit 108 . divide - by circuit 108 , a divide - by 99 circuit , generates a 38 . 8 hz clock signal . the output of divide - by circuit 108 is input to the divide - by circuit 110 . divide - by circuit 110 , a divide - by 26 circuit , generates a 1 . 49 hz signal , c1 -- 49 . the output of divide - by circuit 110 is input to divide - by circuit 112 . divide - by circuit 112 , a divide - by 5 circuit generates a clock signal having a period of 3 . 35 seconds . the output of divide - by circuit 112 is input to divide - by circuit 114 . divide - by circuit 114 , a divide - by 4 , 297 circuit , generates a clock signal having a period of 4 hours . the output of divide - by circuit 114 is input , to divide - by circuit 116 through t - gate 118 . divide - by circuit 116 , a divide - by 6 circuit , generates a clock signal having a period of 24 hours . divide - by circuit 116 may alternately have as its input the output from divide - by circuit 112 . the signal , clk5 may be fed through t - gate 120 as depicted . t - gates 118 and 120 are controlled by test . divide - by circuit 116 also has as its inputs signals stim0 and stim1 . as depicted , each divide - by circuit 104 through 116 is reset by the signal nreset . the control logic of main time base circuit 52 generates the signals anl -- clk , nen -- anl , nout -- on , iminus2 , iminus , niplus and biason as depicted . c1 -- 49 is the output of divide - by circuit 110 . the output of divide - by circuit 104 clocks d - type flipflops 122 , 132 and 134 . the output of divide - by circuit 104 is first inverted by an inverter 124 before clocking flipflop 122 . the input of flipflop 122 , pulse , is connected to an alternate output ( pw ) of divide - by circuit 106 . output pw , labeled clk2 , generates a pulse identical to the output of divide - by circuit 106 occurring on the falling edge of the output of divide - by circuit 106 . nreset and rec -- off are input to an and / nand gate 126 after rec -- off is inverted by an inverter 128 . the nanded output of gate 126 is combined with dcon by a nor gate 130 . the output of gate 130 is connected to the reset input of flipflop 122 . the anded output of gate 126 is connected to the reset input of a d - type flipflops 132 and 134 . flipflop 132 has as its input the output of an and gate 136 . gate 136 has two inputs , stim -- on ( the output of divide - by circuit 116 ) and the output from divide - by circuit 110 . the input to flipflop 134 is connected to the output of an and gate 138 . gate 138 has as its two inputs stim -- on and the output from an or gate 140 . or gate 140 has two inputs , dcon and the output from divide - by circuit 110 . anl -- clk is the output from a three input and gate 142 . gate 142 has inputs dcon , the output of gate 136 and the output of flipflop 132 . nen anl -- is generated from the output of an or gate 144 inverted by an inverter 146 . or gate 144 has inputs which are the outputs of gate 136 and flipflop 132 . nout -- on is generated by the output of an or gate 148 inverted by an inverter 150 . gate 148 has inputs which are the outputs of or gate 144 and of an and gate 152 . gate 152 has two inputs stim -- on and dcon . iminus2 is generated from the output of an or gate 154 inverted by an inverter 156 . gate 154 has inputs which are the outputs of flipflop 134 ( inverted ) and gate 130 . iminus is generated from the output of an or gate 158 inverted by an inverter 160 . gate 158 has inputs which are the outputs of flipflop 134 ( inverted ) and flipflop 122 . niplus is generated from the anded output of a dual and / nand gate 162 inverted by an inverter 164 . gate 162 has as its inputs the outputs from flipflops 122 and 134 . biason is generated by the output of an and gate 166 inverted by inverter 168 . gate 166 has as its input the nanded output of gate 162 and dcon inverted by an inverter 170 . in addition , t - gates 172 and 174 have their outputs coupled to tp1 . the input of t - gates 172 and 174 are coupled to the alternate output , pw , of divide - by circuit 106 and the output of flipflop 134 , respectively . t - gates 172 and 174 are controlled by test . when test equals 0 , tp1 is connected to output pw of divide - by circuit 106 . when test equals 1 , tp1 is connected to the output of flipflop 134 . in operation , the output of divide - by circuit 116 ( stim -- on ) generates a series of four - hour pulses depending upon the values of stim1 and stim0 according to the following values : if stim1 = 0 and stim0 = 0 , then stim -- on is low continuously , if stim1 = 0 and stim0 = 1 then stim -- on is periodically high for 4 hours and low for 20 , if stim1 = 1 and stim0 = 0 , then stim -- on is periodically high for 8 hours and low for 16 , if stim1 = 1 and stim0 = 1 , then stim -- on is continuously high . this internal signal controls the four modes of operation of the stimulator . the output of divide - by circuit 104 acts as the timing clock for main time base circuit 52 . the alternate output , pw , of divide - by circuit 106 generates the 25 % high / 75 % low duty cycle in the ac mode . divide - by circuit 108 generates 99 pulses for each burst of the ac signal . divide - by circuit 110 generates the burst to rest ratio of 1 : 25 . this is the 1 . 49 hz output in the ac mode . the final divide - by operations are split among three divide - by circuits 112 , 114 and 166 to facilitate testing . this allows main time base circuit 52 to be tested using an artificial 20 - second day . as described above , when test = 1 the divide - by circuit 114 is bypassed . also , as described above , the output of divide - by circuit 106 and flipflop 134 may be viewed directly through t - gates 172 and 174 through tp1 . fig1 illustrates a block diagram of the output driver circuit 54 depicted in fig8 b . output driver 54 comprises current mirrors 176 , 178 , 180 , 182 , 184 , 186 , and 188 . current mirror 176 is connected to v dd through pad 25 and an external resistor r11 . current mirror 176 has a control voltage input , gnd -- ref . current mirror 176 is connected to current mirror 178 through a switch 190 . switch 190 is controlled by nout -- on . current mirror 178 mirror is connected between switch 190 and v ss . current mirror 180 is connected between v dd and node 192 . node 192 is connected to v dd also through an optional external resistor r12 at pad 21 . node 192 is also connected to current mirror 182 through a switch 194 . switch 194 is controlled by biason . current mirror 182 is also connected to v ss . current mirror 184 is connected between v dd and a node 196 . node 196 is connected externally to ilimit , at pad 22 . node 196 is also coupled to a node 198 through a switch 200 . switch 200 is controlled by niplus . node 198 is connected externally to out1 , at pad 23 and to control mirror 186 through a switch 202 . switch 202 is controlled by iminus . control mirror 186 is also connected to v ss . a switch 204 is controlled by iminus2 and connects an external output , out2 , at pad 24 to current mirror 188 . current mirror 188 is also connected to v ss . resistor r11 trims the current through current mirror 176 and hence the current through current mirror 178 . current mirror 182 is designed such that it sinks three times the current of current mirror 178 . current mirrors 186 and 188 are designed such that they sink 33 times the current of current mirror 178 . current mirror 180 sources the same current as current mirror 182 when resistor r12 is omitted . resistor r12 may be included to trim the current through current mirror 180 . current mirror 184 is designed such that it sources 33 times the current through current mirror 180 or approximately 99 times the current of current mirror 178 . in the ac mode of operation , switch 204 is open allowing out2 to be externally connected to out1 . simultaneously , switches 200 and 202 are asymmetrically open and closed to periodically source and sink current to out1 from current sources 184 and 186 . biason disables current mirrors 180 and 184 during the negative portion of the output . nout -- on enables output drive circuit 54 only during the pulse portion of the output signal . ilimit is not used . in the dc mode of operation , ilimit is connected to the bone growth stimulator housing ( depicted in fig2 ) and acts as the anodes . switch 200 is open and switch 194 is closed . out1 and out2 are connected to the 2 cathodes ( depicted in fig3 ) and each is connected to current mirrors 186 and 188 , respectively , by switches 202 and 204 , respectively . the dc output is controlled by iminus and iminus2 . fig1 illustrates schematically the transmitter circuit 56 depicted in fig8 . transmitter circuit 56 comprises switching logic 206 which drives inverter drivers 208 and 210 . inverter drivers 208 and 210 control switches 212 and 214 , respectively . switch 212 connects v dd to a resistor 216 . resistor 216 is connected to a node 218 . switch 214 connects node 218 to v ss . node 218 is connected to a node 220 through an external connection , trans , at pad 8 through an external capacitor c2 . node 220 is connected to v dd through an external inductor l1 . also , node 220 is connected through an external resistor r3 back into integrated circuit 46 through recv , at pad 9 . in one embodiment of transmitter circuit 56 , resistors 216 and r3 are 10 kohm resistors , c2 is a 1000 pf capacitor , and inductor l1 is a 4 . 8 mh inductor . logic 206 outputs to inverter drivers 208 and 210 the output of a nand gate 224 twice inverted by inverters 226 and 228 . gate 224 is a three input nand gate which combines c76 -- 8 the output from an or gate 230 , and xmit . gate 230 is a three input or gate having inputs startclk , the output of an and gate 232 and the output from an and gate 234 . gate 232 has inputs oneclk and tcode . gate 234 has inputs tcode inverted by an inverter 236 and zeroclk . in operation , logic 206 synchronizes output data on tcode with the appropriate communications protocol window . in particular , a high data bit is synchronized with oneclk and c76 -- 8 . a data low is synchronized with zeroclk and c76 -- 8 . xmit acts as an enabling signal . the synchronized output signal from logic 206 will cause inverter 208 and 210 to close switches 212 and 214 . current will then flow through inductor 222 . logic 206 will peck inductor l1 twice per data bit due to the length of the pulses of the clocking signals and of tcode . fig1 a and 15b illustrate schematically the ppm decoder circuit 58 depicted in fig8 a . ppm decoder circuit 58 comprises ; a ppm clock decode block 238 and related data checking logic . block 238 as depicted in the figure generates ; c38 -- 4 , zeroclk , oneclk , startclk , dstb and nppmrst . block 238 also generates signal telclk , a timing signal , for use within ppm decoder circuit 58 . block 238 is more fully described in connection with fig1 b . fig1 a comprises five cascading d - type flipflops 240 , 242 , 244 , 246 and 248 . as depicted , the output of flipflops 240 , 242 , 244 and 246 are connected to the input of the next flipflop . flipflop 240 is clocked by nrec -- out inverted by an inverter 250 . flipflop 240 is reset by telclk after that signal is momentarily delayed by delay circuit 252 . ( delay circuit 252 might be an and gate with both of its inputs tied to telclk .) flipflops 242 , 244 , 246 and 248 are each clocked by telclk and reset by nrst . a nand gate 254 ensures that the data bit input on nrec -- out complies with the communication protocol described in fig9 a . gate 254 has three inputs , the inverted output of flipflop 242 , the output of an xor gate 256 and the output of flipflop 248 . the inputs to gate 256 are connected to the outputs of flipflops 244 and 246 . data is generated from the output of flipflop 246 . rec -- off is generated from the inverted output of a d - type flipflop 258 inverted by an inverter 260 . flipflop 258 has its input connected to v dd and is clocked by ntrans . the reset signal to flipflop 258 is connected to the output of a rs flipflop 262 . flipflop 262 has a first input from the output of a nand gate 264 and a second from the output of inverter 250 . nand gate 264 has inputs nrst and the output of a nand gate 266 . nand gate 266 is a three input nand gate having inputs of the inverted output of flipflop 258 , dstb and the output of a nand gate 254 . the set input to flipflop 242 is connected to the output of a nand gate 268 . the inputs to nand gate 268 are connected to the output of inverter 250 and to nppmrst through an inverter 270 . t - gates 272 and 274 alternately switch rec -- out and telclk to tp4 under control of test . when test equals zero , tp4 is connected to the 4800 hz signal telclk . when test equals one tp4 is connected to rec -- out . in operation , flipflops 240 , 242 , 244 , 246 and 248 capture data present on nrec -- out which is synchronized with the 4800 hz telclk signal . gate 254 ensures that the data bit follows the ppm protocol described in connection with fig9 a . gate 254 outputs a high signal if any of the three ppm conditions are not met : ( 1 ) the start bit is high , ( 2 ) either the second or third bit is high , but not both or neither and ( 3 ) the no pulse detected window is low . flipflop 258 and inverter 260 generate rec -- off . fig1 b illustrates a schematic diagram of ppm clock decode block 238 depicted in fig1 a . block 238 comprises six d - type flipflops 276 , 278 , 280 , 282 , 284 and 286 . these flipflops are cascaded together such that the output of flipflops 276 , 278 , 280 , 282 and 284 are connected to the clock input of flipflops 278 , 280 , 282 , 284 and 286 , respectively . the clock input to flipflop 276 is connected to the output of and gate 288 . gate 288 has two inputs , c76 -- 8 and the output of an and gate 290 . and gate 290 has inputs nstop and ntrans . the output gate 290 is also connected to the resets of flipflops 276 , 278 and to a d - type flipflop 292 . flipflop 292 is clocked by the output of flipflop 278 and its input is held high by v dd . the output of flipflop 292 generates the signal nppmrst . the inverted output of flipflop 292 inverted by an inverter 294 resets flipflops 280 , 282 , 284 and 286 . the input and inverted output of each of flipflops 276 , 278 , 280 , and 282 are tied together to form nodes 296 , 298 , 300 , and 302 . these nodes form the inputs to or gate 304 . zeroclk is generated by a nor gate 306 . gate 306 has three inputs , the output of gate 304 , a node 308 and the output of flipflop 286 . node 308 is connected to the input and inverted output of flipflop 284 . oneclk is generated by a nor gate 310 . gate 310 has three inputs , the output of gate 304 , the output of flipflop 284 and the output of latch 286 . startclk is generated by a nor gate 312 . nor gate 312 has three inputs , the output of gate 304 , node 308 and the inverted output of flipflop 286 . dstb is generated by a nor gate 314 . nor gate 314 has four inputs , node 300 , the output of flipflop 282 , node 308 and a node 315 . node 315 is connected to the input and the inverted output of flipflop 286 . telclk is generated from node 302 inverted by an inverter 316 . fig1 illustrates a block diagram of the communication modem circuit 60 depicted in fig8 b . communication modem circuit 60 comprises an 11 bit shift register 318 with outputs nstrt and an 11 bit bus 320 . shift register 318 is reset by nppmrst and is clocked by dstb . data and rec -- off are logically combined by an or gate 322 . the output of gate 322 is the data input to shift register 318 . bus 320 connects shift register 318 to protocol check circuit 324 , to 11 - to - 1 multiplexer 326 and to stimulation control bit latches 328 . protocol check circuit 324 has inputs dcon , code through pads 13 and 10 , respectively . protocol check circuit 324 has a single output access input to latches 328 and to a downlink / uplink control circuit 330 . latches 328 also have inputs nrstprg , dcon , and the output from circuit 330 . latches 328 output stim0 and stim1 . circuit 330 also has inputs nppmrst and c38 -- 4 . as depicted , multiplexer 326 has data inputs stim0 , stim1 , dcon , code , ldlow , ldhigh , lowbatt , and eol . multiplexer 326 also has two control inputs startclk and rec -- off . multiplexer 326 outputs tcode and xmit . a switch 332 alternately switches an external connection , tp5 , to either the tenth data line in bus 320 or to access depending upon the logic value of test . if test = 0 , then tp5 is connected to access . if test = 1 , tp5 is connected to a data line within bus 320 containing the final or stop bit of information . pad 2 is connected to tp5 while pad 4 is connected to test . in operation , 11 bits of data are strobed into shift register 318 through dstb and data . these bits are then made available on bus 320 . protocol check circuit 324 then compares the received data with the programmed data word requirements described in connection with fig9 b . if these requirements are met , then protocol check circuit 324 outputs a logic one on access . latches 328 check the second received data bit to determine if stim0 and stim1 should be written to ( rnw = 0 ) or simply read from ( rnw = 1 ). if a write command is indicated on bus 320 , latches 328 will be loaded with new data . if only a read operation is indicated , communication modem 60 will uplink a handshake communication to the external receiver . circuit 330 outputs a logic zero on ntrans after a valid communication is received as indicated by protocol check circuit 324 . after a valid downlink , communication modem 60 outputs 11 data bits according to the communication protocol described in connection with fig9 c on tcode . multiplexer enables transmitter circuit 56 through xmit . multiplexer 326 outputs each bit in the proper order by receiving sequentially a jammed bit on each of the 11 bus lines 320 from shift register 318 . a logic 1 is jammed into shift register 318 through rec -- off . multiplexer 326 sequentially enables each data line as the one ripples through bus 320 . this procedure causes the contents of stim0 , stim1 dcon code ldlow ldhigh , low , batt and eol data lines along with the start bit to be serially outputted through tcode in the proper order without requiring an address counter . an internal toggle generates an odd parity bit after the last data bit is output and immediately prior to the stop bit . it should be understood that a conventional multiplexer with address bits could be employed in place of multiplexer 326 . fig1 illustrates schematically the lead status circuit 62 depicted in fig8 b . lead status circuit 62 comprises a first and second comparator 334 and 336 . out1 is connected to the first input of comparator 334 through pad 23 . a node 338 is connected to the second input of comparator 334 . node 338 is also connected to node 340 through external pad 20 . node 340 is connected to gnd -- ref through resistor r9 . the first input to comparator 336 is connected to node 342 . node 342 is connected to a node 340 through external resistor r8 and pad 19 . node 342 is also coupled to a current mirror 344 . current mirror 344 is connected to v ss and mirrors current through a current mirror 346 . current mirror 346 is connected to ilead through switch 348 under the control of nen -- anl current mirror . current mirror 346 is also connected to v ss . node 338 is coupled to a second current mirror 350 through a switch 352 under the control of dcon . current mirror 350 also mirrors current mirror 346 and is connected to v ss . the outputs to comparators 334 and 336 are connected to nodes 354 and 356 . node 354 is one input to a xor gate 358 . gate 358 has dcon as its second input . the output to gate 358 is connected to the input of a flipflop 360 . node 356 is connected to the input of a flipflop 362 . flipflops 360 and 362 are reset by nrst and are clocked by the output from an or gate 364 . gate 364 has inputs anl -- clk and iminus . flipflops 360 and 362 generate ldlow and ldhigh , respectively . switch 366 alternately connects tp2 through pad 27 to each of the outputs of comparators 334 and 336 . switch 366 is under the control of test through pad 4 . when test equals 0 , tp2 is connected to node 356 . when test equals 1 , tp2 is connected to node 354 . in the ac mode of operation , the bone growth stimulator has a single electrode output . out1 and out2 are therefore shorted together off chip . comparator 334 compares the voltage on out1 to the voltage at node 340 . if voltage on out1 drops below the voltage at node 340 , comparator 334 will output a zero to latch 360 and onto ldlow . the voltage at node 340 is determined by the choice of resistor r9 . comparator 336 compares the voltage on out1 with a voltage at node 342 . when the voltage on out2 exceeds the voltage at node 342 , comparator 336 outputs a logic level zero which is latched by flipflop 362 and output on ldhigh . the voltage at node 342 is determined by the choice of resistors r8 and r9 . nen -- anl disables lead status circuit 62 during the positive portion and rest portion of the output signal to conserve power . current mirror 344 sinks na 100 of current from node 342 . in the dc mode of operation , out1 and out2 are each connected to a cathode through pads 23 and 24 . also , node 342 is connected to gnd -- ref through resistor r8 . ( resistor r8 is not connected to node 340 ). switch 352 is closed by dcon , allowing current mirror 350 to sink na 100 from node 338 . both comparators 334 and 336 compare the voltages on out1 and out2 to the voltages on nodes 338 and 342 , respectively . comparator 334 will output a logic level zero if out1 is lower than the voltage at node 340 ( high lead impedance on out1 ). comparator 336 will output a logic level one if out2 is lower than the voltage at made 342 ( high lead impedance on out2 ). these outputs will be latched by flipflops 360 and 362 . fig1 illustrates schematically the receiver circuit 64 depicted in fig8 a . receiver circuit 64 comprises a power transconductance comparator 368 which outputs nrec -- out . the first input to comparator 368 is connected to a node 370 . the second input is connected to an internal voltage supply which will range from 75 to 150 mv . current is sunk from node 370 by a current source 372 . current source 372 is coupled to v ss . node 370 is connected to an external node 220 by resistor r3 through external pad 9 . node 370 is also connected to v dd through inductor l1 . pad 8 is an external connection for a transmitter circuit 56 . it is connected to node 374 through capacitor c2 . as described inn connection with fig1 , inductor l1 has an inductance of 4 . 8 mh , resistor r3 has a resistance of 10 kohms and capacitor c2 has a capacitance of 1000 pf . in operation , comparator 368 pulses low when inductor l1 receives a pulse from an external transmitter . comparator 368 can detect a pulse of approximately 20 mv in amplitude , 7 . 5 μsec in width , and pulses spaced as close together as 75 μsec . fig1 illustrates schematically the battery status indicator circuit 66 depicted in fig8 b . battery status circuit 66 comprises a comparator 376 . the output from comparator 376 is logically combined with rec -- off by an and gate 378 . the output of gate 378 is connected to the input of a latch 380 . latch 380 is reset by nrst and its output generates lowbatt . the output of latch 380 is combined with the output from gate 378 by an and gate 382 . the output of and gate 382 is connected to the input of a latch 384 . latch 384 is reset by nrst and clocked by c1 -- 49 . latch 384 requires two clock cycles to latch . the output of latch 384 generates eol . the first input to comparator 376 is connected to a node 386 . node 386 is connected to an external node 388 through eoltrm and pad 12 . external capacitor c3 is connected between node 388 and v dd . an external resistor r4 is connected between the node 388 and v ss . two current mirrors 390 and 392 are connected in parallel between node 386 and a node 394 . a switch 396 selectively connects current source 392 to node 394 under control of the output of latch 380 . node 394 is coupled to v dd by a switch 398 under control of nen -- anl . the second input of comparator 376 is connected to gnd -- ref . a switch 400 alternately connects tp3 through pad 28 to either the output of gate 378 or the output of latch 384 . switch 400 is controlled by test through external pad 4 . when test equals zero , tp3 is connected to the output of gate 378 . when test equals one , tp3 is connected to the output of latch 384 . in operation , comparator 376 compares the voltage at node 386 with gnd -- ref . the first voltage , that of node 386 , is constant depending upon how much current is drawn through resistor r4 by current mirrors 390 and 392 . gnd -- ref however drops as v dd drops during the lifetime of the circuit . initially , the output of latch 380 is low and switch 396 is closed . current mirrors 390 and 392 sink 120 na through resistor r4 . initially , gnd -- ref is at a higher potential than node 386 . the output of comparator 376 is therefore low . as the battery ages , gnd -- ref will drop below the constant voltage at node 386 and trip the output of comparator 376 high . this will output a lowbatt bit from latch 380 and open switch 396 . node 386 will therefore only have 80 na current flowing through it . this will lower the voltage of node 388 . gnd -- ref will again be higher than the voltage at node 386 causing output of comparator 376 to go low again . eventually as the battery continues to age , gnd -- ref will drop below the second , even lower , voltage level at node 386 tripping the output of comparator 376 high . the second high output will be combined with the output from latch 380 by gate 382 and output as eol . fig2 illustrates a block diagram of the voltage reference / regulator circuit 68 depicted in fig8 b . voltage reference / regulator circuit 68 comprises a diode 403 connected to v dd and node 402 , biased as depicted . node 402 is connected to v ss through a current mirror 404 . a second diode 405 is connected between v dd and vset1 through pad 15 . vset1 is coupled to vset2 through external resistor r5 . vset2 exits the circuit through pad 16 . vset2 is coupled to a node 406 . node 406 is coupled to v ss through a current mirror 408 . an op - amp 410 has its first input to node 406 and its second input connected to node 402 . an external resistor r6 is connected between v dd and pad 16 . external resistor r7 is connected between v dd and a node 412 . node 412 is coupled to vref through pad . 17 . pad 17 is connected to v ss through a current mirror 414 . node 412 is the first input of comparator 416 . the second input to comparator 416 is tied to its output . the output of comparator 416 generates gnd -- ref ( internally and gnd -- externally ). gnd -- ref is coupled to one terminal of an external capacitor c5 through external pad 18 . the second terminal of capacitor c5 is coupled to v dd . first and second current mirrors 418 and 420 are connected in series between v dd and v ss . current mirrors 422 and 424 are coupled to v dd and generate the 20 na bias currents irec -- and ilead respectively . itest is connected to v ss through a current mirror 426 . idcon is connected to v ss through a current mirror 428 . icode is connected to v ss through a current mirror 430 . ibatt is connected to v ss through a current mirror 432 . ipor is connected to v ss through a current mirror 434 . current mirrors 426 , 428 , and 430 generate 100 na bias currents . current mirrors 432 and 434 generate a 20 and 10 na bias current respectively . nrstprg controls a switch 436 . switch 436 connects v dd to a current mirror 438 . the output of voltage mirror 438 is connected to output of comparator 410 . the currents flowing through current mirrors 438 , 404 , 408 , 414 , 420 , 426 , 428 , 430 , 432 and 434 governed by the output of comparator 410 and are compensated for variation in temperature as will be described below . current mirrors 4181 , 422 and 424 are controlled by the output of comparator 410 through current mirror 420 . current mirror 438 enables voltage reference / regulator circuit 68 . voltage reference / regulator circuit 68 is based on the band gap principal . comparator 410 sets the current mirrors such that the voltages at nodes 402 and 406 are equal . therefore , the current through r6 is directly proportional to the single diode 403 . the current through r5 is based on the difference in the two diodes 403 and 405 , which are selected to have an 8 : 1 difference in current density . when r5 is selected in the proper balance with r6 ( r6 / r5 = 16 . 2 ), the current sum will be temperature independent . vref is set by the mirrored current and external resistor r7 . in the illustrated embodiment , vref equals gnd ( gnd -- ref ) or v dd - 1 . 5 volts . fig2 illustrates schematically the circuit depicted in fig8 and 85 configured for the ac output signal . when packaged , pins 1 - 4 and 26 - 28 are left open on integrated circuit 46 . testing is done before final assembly . xtrm is connected to v dd 5 through resistor r1 . resistor r1 is a 10 mohm resistor . xtal1 is connected to crystal x1 in parallel with resistor r2 . xtal2 is connected to the other terminal of crystal x1 and resistor r2 . crystal x1 is a 76 . 8 khz crystal and resistor r2 has a resistance of 20 mohm . trans , is connected to one terminal of capacitor c2 . recv is connected to the first terminal of external resistor r3 . the remaining terminal of capacitor c2 and resistor r3 are tied together and to the first terminal of inductor l1 . the second terminal of inductor l1 is connected to v dd . capacitor c2 has a capacitance of 1 , 000 pf , resistor r3 has a resistance of 10 kohm , and inductor l1 has an inductance of 4 . 8 mh . code may or may not be connected to v dd through external pad 10 . v ss is connected to the negative terminal of battery bt1 . battery bt1 is a 2 . 8 volt lithium iodine battery rated for 200 mah . a slightly larger battery may be substituted increasing the rating of the battery bt1 to 0 . 5 ah . as depicted , v ss is also connected to one terminal of capacitor c1 and one terminal of resistor r4 . the second terminal of capacitor c1 is connected to v dd and the second terminal of resistor r4 is connected to eoltrim . eoltrim is also connected to v dd through capacitor c3 . capacitors c1 and c3 have a capacitance of 22 μf and 100 pf respectively . resistor r4 is actively trimmed with a range of 3 - 9 mohm to achieve a lowbatt trippoint of 2 . 4 prior to final assembly . dcon is left floating at external pad 13 . v dd is connected to the positive terminal of battery bt1 . vset1 is connected to v dd through resistor series combination of resistors r5 and r6 . vset2 is connected to the node formed by the inner connection of resistor r5 to resistor r6 . vref is connected to parallel resistor / capacitor combination . parallel resistor capacitor combination comprises resistor r7 and capacitor c4 . the second terminal of r7 and c4 are connected to v dd . resistors r6 and r7 have a resistance of 18 . 75 mohm . resistor r5 is actively trimmed prior to assembly to generate gnd = v dd - 1 . 5 volts . gnd -- is coupled to v dd through capacitor c5 and to the electrode window on the bone growth stimulator . ldtrm2 is connected to a node 440 through a resistor series comprising resistors r8 and r9 . node 440 is connected to gnd . ldtrm1 is connected to the node formed by the connection of resistors r8 and r9 . the low lead impedance trippoint is set by actively trimming resistor r9 . the high impedance trippoint is set by actively trimming resistor r8 after resistor r9 . symtrim is connected to a node 442 through optional resistor r12 . symtrim exits integrated circuit 46 at external pad 22 . out1 is connected to the output electrode through capacitor c7 . capacitor c7 ensures that the output has no net dc component . capacitor c7 has the capacitance of 10 μf . out1 is also connected to node 442 through resistor r10 . resistor r10 has a resistance of 2 mohm . nodes 442 and 440 are electrically connected . out2 is connected to out1 . itrim is connected to v dd through resistor r11 . resistor r11 is actively trimmed to set the output current . in addition , zener diode d1 is coupled between gnd -- and output and are biased as depicted . they provide high voltage protection to the circuit . capacitor c6 is also connected between output1 and gnd -- . capacitor c6 protects the circuit from emi . capacitor c6 has a capacitance of 1 , 000 pf . fig2 illustrates schematically the circuit depicted in fig8 a and 8b configured for the dc output signal . integrated circuit 46 has substantially the same configuration for the dc output as for the ac output . there are the following differences : dcon is connected to v dd to indicate the dc mode of operation . out2 is connected to the second cathode . each output has a parallel zener diode / capacitor combination between it and ldtrm1 . diode d1 and capacitor c6 are connected in parallel between out1 and ilimit . diode d2 and capacitor c7 are connected in parallel between out1 and ilimit . ilimit is connected to the anode , can . certain resistors and capacitors may have different values to reflect the dc configuration . this adjustment can be made by one skilled in art in connection with the foregoing description . although the present invention and its advantages have been described in detail , it should be understood that various changes , substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims .
a method for the therapeutic stimulation of bone growth of a bone site is disclosed comprising the steps of implanting first and second electrodes into the tissue near the base site . the electrodes are coupled to a bone growth stimulator which generates an alternating current .