plte[1] = 0xc3e00000 | (disp & 0x1fffff);
int hi, lo; hi = value - (Elf64_Addr)&plte[0]; lo = (short)hi; hi = (hi - lo) >> 16;   plte[0] = 0x277b0000 | (hi & 0xffff);   plte[1] = 0x237b0000 | (lo & 0xffff);   plte[2] = 0xc3e00000 | (edisp & 0x1fffff);
elf_alpha_fix_plt(struct link_map *l,		  const Elf64_Rela *reloc,		  Elf64_Addr value){  const Elf64_Rela *rela_plt;  Elf64_Word *plte;  long disp;  /* Recover the PLT entry address by calculating reloc's index into the     .rela.plt, and finding that entry in the .plt.  */  rela_plt = (void *)(l->l_addr + l->l_info[DT_JMPREL]->d_un.d_ptr);  plte = (void *)(l->l_addr + l->l_info[DT_PLTGOT]->d_un.d_ptr);  plte += 2*(reloc - rela_plt) + 8;  /* Find the displacement from the plt entry to the function.  */  disp = value - (Elf64_Addr)&plte[2];  /* Change "lda $27, ofs($31)" to "ldq $27, ofs($gp)" */  plte[0] = 0xa77d0000 | (plte[0] & 0xffff);  if (disp >= -0x100000 && disp < 0x100000)    {      /* If we are in range, use br to perfect branch prediction and	 elide the dependancy on the address load.  This case happens,	 e.g., when a shared library call is resolved to the same library.  */      /* Change "br $0, plt0" to "br $31,function" */      plte[1] = 0xc3e00000 | (disp & 0x1fffff);    }  else    {      /* Don't bother with the hint since we already know the hint is	 wrong.  Eliding it prevents the wrong page from getting pulled	 into the cache.  */      /* Change "br $0, plt0" to "jmp $31,($27)" */      plte[1] = 0x6bfb0000;    }  /* Flush the instruction cache now that we've diddled.   Tag it as     modifying memory to checkpoint memory writes during optimization.  */  asm volatile("call_pal 0x86" : : : "memory");}