else { pr_ticks_per_second = _PR_UNIX_TicksPerSecond(); }
static void _MD_IrixIntervalInit(){    /*     * As much as I would like, the service available through this     * interface on R3000's (aka, IP12) just isn't going to make it.     * The register is only 24 bits wide, and rolls over at a verocious     * rate.     */    PRUint32 one_tick = 0;    struct utsname utsinfo;    uname(&utsinfo);    if ((strncmp("IP12", utsinfo.machine, 4) != 0)        && ((mmem_fd = open("/dev/mmem", O_RDONLY)) != -1))    {        int poffmask = getpagesize() - 1;        __psunsigned_t phys_addr, raddr, cycleval;        phys_addr = syssgi(SGI_QUERY_CYCLECNTR, &cycleval);        raddr = phys_addr & ~poffmask;        iotimer_addr = mmap(            0, poffmask, PROT_READ, MAP_PRIVATE, mmem_fd, (__psint_t)raddr);        clock_width = syssgi(SGI_CYCLECNTR_SIZE);        if (clock_width < 0)        {            /*              * We must be executing on a 6.0 or earlier system, since the             * SGI_CYCLECNTR_SIZE call is not supported.             *              * The only pre-6.1 platforms with 64-bit counters are             * IP19 and IP21 (Challenge, PowerChallenge, Onyx).             */            if (!strncmp(utsinfo.machine, "IP19", 4) ||                !strncmp(utsinfo.machine, "IP21", 4))                clock_width = 64;            else                clock_width = 32;        }        /*         * 'cycleval' is picoseconds / increment of the counter.         * I'm pushing for a tick to be 100 microseconds, 10^(-4).         * That leaves 10^(-8) left over, or 10^8 / cycleval.         * Did I do that right?         */        one_tick =  100000000UL / cycleval ;  /* 100 microseconds */        while (0 != one_tick)        {            pr_clock_shift += 1;            one_tick = one_tick >> 1;            pr_clock_granularity = pr_clock_granularity << 1;        }        pr_clock_mask = pr_clock_granularity - 1;  /* to make a mask out of it */                    iotimer_addr = (void*)            ((__psunsigned_t)iotimer_addr + (phys_addr & poffmask));    }}  /* _MD_IrixIntervalInit */