return value;
elf_machine_fixup_plt(struct link_map *map, const Elf64_Rela *reloc,                      Elf64_Addr *reloc_addr, Elf64_Addr value){  unsigned int *insns = (unsigned int *) reloc_addr;  Elf64_Addr plt_vaddr = (Elf64_Addr) reloc_addr;  /* Now move plt_vaddr up to the call instruction.  */  plt_vaddr += (2 * 4);  /* PLT entries .PLT32768 and above look always the same.  */  if (__builtin_expect (reloc->r_addend, 0) != 0)    {      *reloc_addr = value - map->l_addr;    }  /* 32-bit Sparc style, the target is in the lower 32-bits of     address space.  */  else if ((value >> 32) == 0)    {      /* sethi	%hi(target), %g1	 jmpl	%g1 + %lo(target), %g0  */      insns[2] = 0x81c06000 | (value & 0x3ff);      __asm __volatile ("flush %0 + 8" : : "r" (insns));      insns[1] = 0x03000000 | ((unsigned int)(value >> 10));      __asm __volatile ("flush %0 + 4" : : "r" (insns));    }  /* We can also get somewhat simple sequences if the distance between     the target and the PLT entry is within +/- 2GB.  */  else if ((plt_vaddr > value	    && ((plt_vaddr - value) >> 32) == 0)	   || (value > plt_vaddr	       && ((value - plt_vaddr) >> 32) == 0))    {      unsigned int displacement;      if (plt_vaddr > value)	displacement = (0 - (plt_vaddr - value));      else	displacement = value - plt_vaddr;      /* mov	%o7, %g1	 call	displacement	  mov	%g1, %o7  */      insns[3] = 0x9e100001;      __asm __volatile ("flush %0 + 12" : : "r" (insns));      insns[2] = 0x40000000 | (displacement >> 2);      __asm __volatile ("flush %0 + 8" : : "r" (insns));      insns[1] = 0x8210000f;      __asm __volatile ("flush %0 + 4" : : "r" (insns));    }  /* Worst case, ho hum...  */  else    {      unsigned int high32 = (value >> 32);      unsigned int low32 = (unsigned int) value;      /* ??? Some tricks can be stolen from the sparc64 egcs backend	     constant formation code I wrote.  -DaveM  */      /* sethi	%hh(value), %g1	 sethi	%lm(value), %g5	 or	%g1, %hm(value), %g1	 or	%g5, %lo(value), %g5	 sllx	%g1, 32, %g1	 jmpl	%g1 + %g5, %g0	  nop  */      insns[6] = 0x81c04005;      __asm __volatile ("flush %0 + 24" : : "r" (insns));      insns[5] = 0x83287020;      __asm __volatile ("flush %0 + 20" : : "r" (insns));      insns[4] = 0x8a116000 | (low32 & 0x3ff);      __asm __volatile ("flush %0 + 16" : : "r" (insns));      insns[3] = 0x82106000 | (high32 & 0x3ff);      __asm __volatile ("flush %0 + 12" : : "r" (insns));      insns[2] = 0x0b000000 | (low32 >> 10);      __asm __volatile ("flush %0 + 8" : : "r" (insns));      insns[1] = 0x03000000 | (high32 >> 10);      __asm __volatile ("flush %0 + 4" : : "r" (insns));    }}