sys_config.cpu[0].tlbsize = 48;
mips_init(int argc, int32_t *argv){	char *cp;	int i;	unsigned firstaddr;	caddr_t sd;	extern char start[], edata[], end[];	extern char tlb_miss[], e_tlb_miss[];	extern char tlb_miss_tramp[], e_tlb_miss_tramp[];	extern char xtlb_miss_tramp[], e_xtlb_miss_tramp[];	extern char exception[], e_exception[];	/*	 *  Clean up any mess.	 */	Bios_FlushAllCaches();	/*	 * Clear the compiled BSS segment in OpenBSD code	 */	bzero(edata, end-edata);	/*	 *  Reserve symol table space. If invalid pointers no table.	 */	ssym = (char *)*(u_int64_t *)end;	esym = (char *)*((u_int64_t *)end + 1);	ekern = esym;	if (((long)ssym - (long)end) < 0 ||	    ((long)ssym - (long)end) > 0x1000 ||	    ssym[0] != ELFMAG0 || ssym[1] != ELFMAG1 ||	    ssym[2] != ELFMAG2 || ssym[3] != ELFMAG3 ) {		ssym = NULL;		esym = NULL;		ekern = end;	}	/*	 *  Initialize the system type and set up memory layout	 */	bios_ident();	/*	 * Determine system type and set up configuration record data.	 */	if (sys_config.system_type == SGI_O2) {		bios_putstring("Found SGI-IP32, setting up.\n");		strlcpy(cpu_model, "SGI O2", sizeof(cpu_model));		sys_config.cons_ioaddr[0] = 0x00390000;	/*XXX*/		sys_config.cons_ioaddr[1] = 0x00398000;	/*XXX*/		sys_config.cons_baudclk = 1843200;		/*XXX*/		sys_config.cons_iot = &macebus_tag;		sys_config.local.bus_base = 0x0;		/*XXX*/#if defined(_LP64)		sys_config.pci_io[0].bus_base = 0xffffffff00000000;/*XXX*/		sys_config.pci_mem[0].bus_base = 0xffffffff00000000;/*XXX*/#else		sys_config.pci_io[0].bus_base = 0x00000000;/*XXX*/		sys_config.pci_mem[0].bus_base = 0x00000000;/*XXX*/#endif		sys_config.pci_mem[0].bus_base_dma = 0x00000000;/*XXX*/		sys_config.pci_mem[0].bus_reverse = my_endian;		sys_config.cpu[0].tlbwired = 2;		sys_config.cpu[0].clock = 180000000;  /* Reasonable default */		/* R1xK O2's are one disk slot machines. Offset slotno */		switch ((cp0_get_prid() >> 8) & 0xff) {		case MIPS_R10000:		case MIPS_R12000:		case MIPS_R14000:	/* Anyone seen an O2 with R14K? */			bootdriveoffs = -1;			break;		}		/* R12K O2's must run with DSD on */		switch ((cp0_get_prid() >> 8) & 0xff) {		case MIPS_R12000:			setsr(SR_DSD);			break;		}	} else {		bios_putstring("Unsupported system!!!\n");		while(1);	}	/*	 *  Use cpufrequency from bios to start with.	 */	cp = Bios_GetEnvironmentVariable("cpufreq");	if (cp) {		i = atoi(cp, 10, NULL);		if (i > 100)			sys_config.cpu[0].clock = i * 1000000;	}	/*	 *  Set pagesize to enable use of page macros and functions.	 *  Commit available memory to UVM system	 */	uvmexp.pagesize = 4096;	uvm_setpagesize();	for(i = 0; i < MAXMEMSEGS && mem_layout[i].mem_first_page != 0; i++) {		u_int32_t fp, lp;		u_int32_t firstkernpage = atop(KSEG0_TO_PHYS(start));		u_int32_t lastkernpage = atop(KSEG0_TO_PHYS(ekern));		fp = mem_layout[i].mem_first_page;		lp = mem_layout[i].mem_last_page - 1;		/* Account for kernel and kernel symbol table */		if (fp >= firstkernpage && lp < lastkernpage)			continue;	/* In kernel */		if (lp < firstkernpage || fp > lastkernpage) {			uvm_page_physload(fp, lp, fp, lp, VM_FREELIST_DEFAULT);			continue;	/* Outside kernel */		}		if (fp > firstkernpage)			fp = lastkernpage + 1;		else if (lp < lastkernpage)			lp = firstkernpage - 1;		else { /* Need to split! */			u_int32_t xp = firstkernpage - 1;			uvm_page_physload(fp, xp, fp, xp, VM_FREELIST_DEFAULT);			fp = lastkernpage + 1;		}		if (lp >= fp)			uvm_page_physload(fp, lp, fp, lp, VM_FREELIST_DEFAULT);	}	/*	 *  Figure out where we was booted from.	 */	cp = Bios_GetEnvironmentVariable("OSLoadPartition");	if (cp == NULL)		cp = "unknown";	makebootdev(cp, bootdriveoffs);	/*	 * Look at arguments passed to us and compute boothowto.	 * Default to SINGLE and ASKNAME if no args or	 * SINGLE and DFLTROOT if this is a ramdisk kernel.	 */#ifdef RAMDISK_HOOKS	boothowto = RB_SINGLE | RB_DFLTROOT;#else	boothowto = RB_SINGLE | RB_ASKNAME;#endif /* RAMDISK_HOOKS */	dobootopts(argc, argv);	/* Check l3cache size and disable (hard) if non present. */	if (Bios_GetEnvironmentVariable("l3cache") != 0) {		i = atoi(Bios_GetEnvironmentVariable("l3cache"), 10, NULL);		CpuTertiaryCacheSize = 1024 * 1024 * i;	} else {		CpuTertiaryCacheSize = 0;	}	sys_config.cpu[0].type = (cp0_get_prid() >> 8) & 0xff;	sys_config.cpu[0].vers_maj = (cp0_get_prid() >> 4) & 0x0f;	sys_config.cpu[0].vers_min = cp0_get_prid() & 0x0f;	sys_config.cpu[0].fptype = (cp1_get_prid() >> 8) & 0xff;	sys_config.cpu[0].fpvers_maj = (cp1_get_prid() >> 4) & 0x0f;	sys_config.cpu[0].fpvers_min = cp1_get_prid() & 0x0f;	/*	 *  Configure TLB.	 */	switch(sys_config.cpu[0].type) {	case MIPS_RM7000:		/* Rev A (version >= 2) CPU's have 64 TLB entries. */		if (sys_config.cpu[0].vers_maj < 2) {			sys_config.cpu[0].tlbsize = 48;		} else {			sys_config.cpu[0].tlbsize = 64;		}		break;	case MIPS_R10000:	case MIPS_R12000:	case MIPS_R14000:		sys_config.cpu[0].tlbsize = 64;		break;	default:		sys_config.cpu[0].tlbsize = 48;		break;	}	/*	 *  Configure Cache.	 */	switch(sys_config.cpu[0].type) {	case MIPS_R10000:	case MIPS_R12000:	case MIPS_R14000:		sys_config.cpu[0].cfg_reg = Mips10k_ConfigCache();		sys_config._SyncCache = Mips10k_SyncCache;		sys_config._InvalidateICache = Mips10k_InvalidateICache;		sys_config._InvalidateICachePage = Mips10k_InvalidateICachePage;		sys_config._SyncDCachePage = Mips10k_SyncDCachePage;		sys_config._HitSyncDCache = Mips10k_HitSyncDCache;		sys_config._IOSyncDCache = Mips10k_IOSyncDCache;		sys_config._HitInvalidateDCache = Mips10k_HitInvalidateDCache;		break;	default:		sys_config.cpu[0].cfg_reg = Mips5k_ConfigCache();		sys_config._SyncCache = Mips5k_SyncCache;		sys_config._InvalidateICache = Mips5k_InvalidateICache;		sys_config._InvalidateICachePage = Mips5k_InvalidateICachePage;		sys_config._SyncDCachePage = Mips5k_SyncDCachePage;		sys_config._HitSyncDCache = Mips5k_HitSyncDCache;		sys_config._IOSyncDCache = Mips5k_IOSyncDCache;		sys_config._HitInvalidateDCache = Mips5k_HitInvalidateDCache;		break;	}	tlb_set_wired(0);	tlb_flush(sys_config.cpu[0].tlbsize);	tlb_set_wired(sys_config.cpu[0].tlbwired);#if 0	/* XXX Save the following as an example on how to optimize I/O mapping */	/*	 *  Set up some fixed mappings. These are so frequently	 *  used so faulting them in will waste to many cycles.	 */	if (sys_config.system_type == MOMENTUM_CP7000G ||	    sys_config.system_type == MOMENTUM_CP7000 ||	    sys_config.system_type == GALILEO_EV64240) {		struct tlb tlb;		tlb.tlb_mask = PG_SIZE_16M;#if defined(LP64)		tlb.tlb_hi = vad_to_vpn(0xfffffffffc000000) | 1;		tlb.tlb_lo0 = vad_to_pfn(0xfffffffff4000000) | PG_IOPAGE;#else		tlb.tlb_hi = vad_to_vpn(0xfc000000) | 1;		tlb.tlb_lo0 = vad_to_pfn(0xf4000000) | PG_IOPAGE;#endif		tlb.tlb_lo1 = vad_to_pfn(sys_config.cons_ioaddr[0]) | PG_IOPAGE;		tlb_write_indexed(2, &tlb);		if (sys_config.system_type == GALILEO_EV64240) {			tlb.tlb_mask = PG_SIZE_16M;			tlb.tlb_hi = vad_to_vpn(0xf8000000) | 1;			tlb.tlb_lo0 = vad_to_pfn(sys_config.pci_io[0].bus_base) | PG_IOPAGE;			tlb.tlb_lo1 = vad_to_pfn(sys_config.pci_mem[0].bus_base) | PG_IOPAGE;			tlb_write_indexed(3, &tlb);		}	}/* XXX */#endif	/*	 *  Get a console, very early but after initial mapping setup.	 */	bios_putstring("Initial setup done, switching console.\n\n");	consinit();	/*	 * Init message buffer.	 */	msgbufbase = (caddr_t)pmap_steal_memory(MSGBUFSIZE, NULL,NULL);	initmsgbuf(msgbufbase, MSGBUFSIZE);	/*	 * Allocate U page(s) for proc[0], pm_tlbpid 1.	 */	proc0.p_addr = proc0paddr = curprocpaddr =		(struct user *)pmap_steal_memory(USPACE, NULL,NULL);	proc0.p_md.md_regs = (struct trap_frame *)&proc0paddr->u_pcb.pcb_regs;	firstaddr = KSEG0_TO_PHYS(proc0.p_addr);	tlb_set_pid(1);	/*	 * Allocate system data structures.	 */	i = (vsize_t)allocsys(NULL);	sd = (caddr_t)pmap_steal_memory(i, NULL, NULL);	allocsys(sd);	/*	 * Bootstrap VM system.	 */	pmap_bootstrap();	/*	 * Copy down exception vector code. If code is to large	 * copy down trampolines instead of doing a panic.	 */	if (e_tlb_miss - tlb_miss > 0x80) {		bcopy(tlb_miss_tramp, (char *)TLB_MISS_EXC_VEC,		    e_tlb_miss_tramp - tlb_miss_tramp);		bcopy(xtlb_miss_tramp, (char *)XTLB_MISS_EXC_VEC,		    e_xtlb_miss_tramp - xtlb_miss_tramp);	} else {		bcopy(tlb_miss, (char *)TLB_MISS_EXC_VEC,		    e_tlb_miss - tlb_miss);	}	bcopy(exception, (char *)CACHE_ERR_EXC_VEC, e_exception - exception);	bcopy(exception, (char *)GEN_EXC_VEC, e_exception - exception);#ifdef DDB	db_machine_init();	if (boothowto & RB_KDB)		Debugger();#endif	/*	 * Clear out the I and D caches.	 */	Mips_SyncCache();	/*	 *  Return new stack pointer.	 */	return ((caddr_t)proc0paddr + USPACE - 64);}