if (!(sc->bge_rdata->bge_status_block.bge_status & BGE_STATFLAG_UPDATED))  return(0);
bge_intr(xsc)	void *xsc;{	struct bge_softc *sc;	struct ifnet *ifp;	u_int32_t status, mimode;	sc = xsc;	ifp = &sc->arpcom.ac_if;#ifdef notdef	/* Avoid this for now -- checking this register is expensive. */	/* Make sure this is really our interrupt. */	if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))		return (0);#endif	/* Ack interrupt and stop others from occurring. */	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);	/*	 * Process link state changes.	 * Grrr. The link status word in the status block does	 * not work correctly on the BCM5700 rev AX and BX chips,	 * according to all available information. Hence, we have	 * to enable MII interrupts in order to properly obtain	 * async link changes. Unfortunately, this also means that	 * we have to read the MAC status register to detect link	 * changes, thereby adding an additional register access to	 * the interrupt handler.	 */	if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) {		status = CSR_READ_4(sc, BGE_MAC_STS);		if (status & BGE_MACSTAT_MI_INTERRUPT) {			sc->bge_link = 0;			timeout_del(&sc->bge_timeout);			bge_tick(sc);			/* Clear the interrupt */			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,			    BGE_EVTENB_MI_INTERRUPT);			bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR);			bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR,			    BRGPHY_INTRS);		}	} else {		if ((sc->bge_rdata->bge_status_block.bge_status &		    BGE_STATFLAG_UPDATED) &&		    (sc->bge_rdata->bge_status_block.bge_status &		    BGE_STATFLAG_LINKSTATE_CHANGED)) {			sc->bge_rdata->bge_status_block.bge_status &=			    ~(BGE_STATFLAG_UPDATED | 				BGE_STATFLAG_LINKSTATE_CHANGED);			/*			 * Sometimes PCS encoding errors are detected in			 * TBI mode (on fiber NICs), and for some reason			 * the chip will signal them as link changes.			 * If we get a link change event, but the 'PCS 			 * encoding bit' in the MAC status register			 * is set, don't bother doing a link check.			 * This avoids spurious "gigabit link up" messages			 * that sometimes appear on fiber NICs during			 * periods of heavy traffic. (There should be no			 * effect on copper NICs).			 *			 * If we do have a copper NIC (bge_tbi == 0) then			 * check that the AUTOPOLL bit is set before			 * processing the event as a real link change.			 * Turning AUTOPOLL on and off in the MII read/write			 * functions will often trigger a link status			 * interrupt for no reason.			 */			status = CSR_READ_4(sc, BGE_MAC_STS);			mimode = CSR_READ_4(sc, BGE_MI_MODE);			if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR | 			    BGE_MACSTAT_MI_COMPLETE)) && (!sc->bge_tbi &&			    (mimode & BGE_MIMODE_AUTOPOLL))) {				sc->bge_link = 0;				timeout_del(&sc->bge_timeout);				bge_tick(sc);			}			/* Clear the interrupt */			CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|			    BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|			    BGE_MACSTAT_LINK_CHANGED);			/* Force flush the status block cached by PCI bridge */			CSR_READ_4(sc, BGE_MBX_IRQ0_LO);			}	}	if (ifp->if_flags & IFF_RUNNING) {		/* Check RX return ring producer/consumer */		bge_rxeof(sc);		/* Check TX ring producer/consumer */		bge_txeof(sc);	}	bge_handle_events(sc);	/* Re-enable interrupts. */	CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);	if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd))		bge_start(ifp);	return (1);}