default: panic("setipl: Can't determine cpu type!");
setipl(unsigned level){	unsigned curspl;	m88k_psr_type psr; /* proccessor status register */#ifdef MVME188	int cpu = 0;#endif 	if (level > 7) {		level = 0;	/* assume this for the time being */	}	psr = disable_interrupts_return_psr();	switch (cputyp) {#ifdef MVME188	case CPU_188:		cpu = cpu_number();		curspl = m188_curspl[cpu];		setlevel(level);		break;#endif /* MVME188 */#if defined(MVME187) || defined(MVME197)	case CPU_187:	case CPU_197:		curspl = *int_mask_level;		*int_mask_level = level;		break;#endif /* defined(MVME187) || defined(MVME197) */	default:		panic("setipl: Can't determine cpu type!");	}	flush_pipeline();	/* The flush pipeline is required to make sure the above write gets	 * through the data pipe and to the hardware; otherwise, the next	 * bunch of instructions could execute at the wrong spl protection	 */	set_psr(psr);	return curspl;}