(i < (sizeof(ar5k_2ghz_channels) / sizeof(ar5k_2ghz_channels[0]))) &&
(i < AR5K_ELEMENTS(ar5k_2ghz_channels)) &&
ath_hal_init_channels(hal, channels, max_channels, channels_size, country, mode,    outdoor, extended)	struct ath_hal *hal;	HAL_CHANNEL *channels;	u_int max_channels;	u_int *channels_size;	HAL_CTRY_CODE country;	u_int16_t mode;	HAL_BOOL outdoor;	HAL_BOOL extended;{	u_int i, c;	u_int32_t domain_current;	u_int domain_5ghz, domain_2ghz;	HAL_CHANNEL all_channels[max_channels];	i = c = 0;	domain_current = hal->ah_getRegDomain(hal);	/*	 * In debugging mode, enable all channels supported by the chipset	 */	if (domain_current == DMN_DEFAULT) {		int min, max, freq;		u_int flags;		min = ieee80211_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MIN,		    IEEE80211_CHAN_2GHZ);		max = ieee80211_mhz2ieee(IEEE80211_CHANNELS_2GHZ_MAX,		    IEEE80211_CHAN_2GHZ);		flags = CHANNEL_B | CHANNEL_TG |		    (hal->ah_version == AR5K_AR5211 ?		    CHANNEL_PUREG : CHANNEL_G); debugchan:		for (i = min; i <= max && c < max_channels; i++) {			freq = ieee80211_ieee2mhz(i, flags);			if (ar5k_check_channel(hal, freq, flags) == AH_FALSE)				continue;			all_channels[c].c_channel = freq;			all_channels[c++].c_channel_flags = flags;		}		if (flags & IEEE80211_CHAN_2GHZ) {			min = ieee80211_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MIN,			    IEEE80211_CHAN_5GHZ);			max = ieee80211_mhz2ieee(IEEE80211_CHANNELS_5GHZ_MAX,			    IEEE80211_CHAN_5GHZ);			flags = CHANNEL_A | CHANNEL_T | CHANNEL_XR;			goto debugchan;		}		goto done;	}	domain_5ghz = ieee80211_regdomain2flag(domain_current,	    IEEE80211_CHANNELS_5GHZ_MIN);	domain_2ghz = ieee80211_regdomain2flag(domain_current,	    IEEE80211_CHANNELS_2GHZ_MIN);	/*	 * Create channel list based on chipset capabilities, regulation domain	 * and mode. 5GHz...	 */	for (i = 0; (hal->ah_capabilities.cap_range.range_5ghz_max > 0) &&		 (i < (sizeof(ar5k_5ghz_channels) /		     sizeof(ar5k_5ghz_channels[0]))) &&		 (c < max_channels); i++) {		/* Check if channel is supported by the chipset */		if (ar5k_check_channel(hal,		    ar5k_5ghz_channels[i].rc_channel,		    IEEE80211_CHAN_5GHZ) == AH_FALSE)			continue;		/* Match regulation domain */		if ((IEEE80211_DMN(ar5k_5ghz_channels[i].rc_domain) &			IEEE80211_DMN(domain_5ghz)) == 0)			continue;		/* Match modes */		if (ar5k_5ghz_channels[i].rc_mode & IEEE80211_CHAN_TURBO) {			all_channels[c].c_channel_flags = CHANNEL_T;		} else if (ar5k_5ghz_channels[i].rc_mode &		    IEEE80211_CHAN_OFDM) {			all_channels[c].c_channel_flags = CHANNEL_A;		}		/* Write channel and increment counter */		all_channels[c++].channel = ar5k_5ghz_channels[i].rc_channel;	}	/*	 * ...and 2GHz.	 */	for (i = 0; (hal->ah_capabilities.cap_range.range_2ghz_max > 0) &&		 (i < (sizeof(ar5k_2ghz_channels) /		     sizeof(ar5k_2ghz_channels[0]))) &&		 (c < max_channels); i++) {		/* Check if channel is supported by the chipset */		if (ar5k_check_channel(hal,		    ar5k_2ghz_channels[i].rc_channel,		    IEEE80211_CHAN_2GHZ) == AH_FALSE)			continue;		/* Match regulation domain */		if ((IEEE80211_DMN(ar5k_2ghz_channels[i].rc_domain) &			IEEE80211_DMN(domain_2ghz)) == 0)			continue;		/* Match modes */		if (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_CCK)			all_channels[c].c_channel_flags = CHANNEL_B;		if (ar5k_2ghz_channels[i].rc_mode & IEEE80211_CHAN_OFDM) {			all_channels[c].c_channel_flags |=			    hal->ah_version == AR5K_AR5211 ?			    CHANNEL_PUREG : CHANNEL_G;			if (ar5k_2ghz_channels[i].rc_mode &			    IEEE80211_CHAN_TURBO)				all_channels[c].c_channel_flags |= CHANNEL_TG;		}		/* Write channel and increment counter */		all_channels[c++].channel = ar5k_2ghz_channels[i].rc_channel;	} done:	bcopy(all_channels, channels, sizeof(all_channels));	*channels_size = c;	return (AH_TRUE);}