ncr53c9x_dmaselect = 1;
ncr53c9x_dmaselect = use_dmaselect;
espattach(parent, self, aux)	struct device *parent, *self;	void *aux;{	register struct confargs *ca = aux;	struct esp_softc *esc = (void *)self;	struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;	struct bootpath *bp;	int dmachild = strncmp(parent->dv_xname, "dma", 3) == 0;	/*	 * Set up glue for MI code early; we use some of it here.	 */	sc->sc_glue = &esp_glue;	/*	 * Make sure things are sane. I don't know if this is ever	 * necessary, but it seem to be in all of Torek's code.	 */	if (ca->ca_ra.ra_nintr != 1) {		printf(": expected 1 interrupt, got %d\n", ca->ca_ra.ra_nintr);		return;	}	esc->sc_pri = ca->ca_ra.ra_intr[0].int_pri;	printf(" pri %d", esc->sc_pri);	/*	 * Map my registers in, if they aren't already in virtual	 * address space.	 */	if (ca->ca_ra.ra_vaddr)		esc->sc_reg = (volatile u_char *) ca->ca_ra.ra_vaddr;	else {		esc->sc_reg = (volatile u_char *)		    mapiodev(ca->ca_ra.ra_reg, 0, ca->ca_ra.ra_len);	}	/* Other settings */	esc->sc_node = ca->ca_ra.ra_node;	if (ca->ca_bustype == BUS_SBUS) {		sc->sc_id = getpropint(esc->sc_node, "initiator-id", 7);		sc->sc_freq = getpropint(esc->sc_node, "clock-frequency", -1);	} else {		sc->sc_id = 7;		sc->sc_freq = 24000000;	}	if (sc->sc_freq < 0)		sc->sc_freq = ((struct sbus_softc *)		    sc->sc_dev.dv_parent)->sc_clockfreq;	/* gimme Mhz */	sc->sc_freq /= 1000000;	if (dmachild) {		esc->sc_dma = (struct dma_softc *)parent;		esc->sc_dma->sc_esp = esc;	} else {		/*		 * find the DMA by poking around the dma device structures		 *		 * What happens here is that if the dma driver has not been		 * configured, then this returns a NULL pointer. Then when the		 * dma actually gets configured, it does the opposing test, and		 * if the sc->sc_esp field in it's softc is NULL, then tries to		 * find the matching esp driver.		 */		esc->sc_dma = (struct dma_softc *)			getdevunit("dma", sc->sc_dev.dv_unit);		/*		 * and a back pointer to us, for DMA		 */		if (esc->sc_dma)			esc->sc_dma->sc_esp = esc;		else {			printf("\n");			panic("espattach: no dma found");		}	}	/*	 * XXX More of this should be in ncr53c9x_attach(), but	 * XXX should we really poke around the chip that much in	 * XXX the MI code?  Think about this more...	 */	/*	 * It is necessary to try to load the 2nd config register here,	 * to find out what rev the esp chip is, else the ncr53c9x_reset	 * will not set up the defaults correctly.	 */	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;	sc->sc_cfg3 = NCRCFG3_CDB;	NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);	if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=	    (NCRCFG2_SCSI2 | NCRCFG2_RPE)) {		sc->sc_rev = NCR_VARIANT_ESP100;	} else {		sc->sc_cfg2 = NCRCFG2_SCSI2;		NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);		sc->sc_cfg3 = 0;		NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);		sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);		NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);		if (NCR_READ_REG(sc, NCR_CFG3) !=		    (NCRCFG3_CDB | NCRCFG3_FCLK)) {			sc->sc_rev = NCR_VARIANT_ESP100A;		} else {			/* NCRCFG2_FE enables > 64K transfers */			sc->sc_cfg2 |= NCRCFG2_FE;			sc->sc_cfg3 = 0;			NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);			sc->sc_rev = NCR_VARIANT_ESP200;		}	}	/*	 * XXX minsync and maxxfer _should_ be set up in MI code,	 * XXX but it appears to have some dependency on what sort	 * XXX of DMA we're hooked up to, etc.	 */	/*	 * This is the value used to start sync negotiations	 * Note that the NCR register "SYNCTP" is programmed	 * in "clocks per byte", and has a minimum value of 4.	 * The SCSI period used in negotiation is one-fourth	 * of the time (in nanoseconds) needed to transfer one byte.	 * Since the chip's clock is given in MHz, we have the following	 * formula: 4 * period = (1000 / freq) * 4	 */	sc->sc_minsync = 1000 / sc->sc_freq;	/*	 * Alas, we must now modify the value a bit, because it's	 * only valid when can switch on FASTCLK and FASTSCSI bits  	 * in config register 3... 	 */	switch (sc->sc_rev) {	case NCR_VARIANT_ESP100:		sc->sc_maxxfer = 64 * 1024;		sc->sc_minsync = 0;	/* No synch on old chip? */		break;	case NCR_VARIANT_ESP100A:		sc->sc_maxxfer = 64 * 1024;		/* Min clocks/byte is 5 */		sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);		break;	case NCR_VARIANT_ESP200:		sc->sc_maxxfer = 16 * 1024 * 1024;		/* XXX - do actually set FAST* bits */		break;	}	/* add me to the sbus structures */	esc->sc_sd.sd_reset = (void *) ncr53c9x_reset;#if defined(SUN4C) || defined(SUN4M)	if (ca->ca_bustype == BUS_SBUS) {		if (dmachild)			sbus_establish(&esc->sc_sd, sc->sc_dev.dv_parent);		else			sbus_establish(&esc->sc_sd, &sc->sc_dev);	}#endif /* SUN4C || SUN4M */	/* and the interuppts */	esc->sc_ih.ih_fun = (void *) ncr53c9x_intr;	esc->sc_ih.ih_arg = sc;	intr_establish(esc->sc_pri, &esc->sc_ih);	evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt);	/*	 * If the boot path is "esp" at the moment and it's me, then	 * walk our pointer to the sub-device, ready for the config	 * below.	 */	bp = ca->ca_ra.ra_bp;	switch (ca->ca_bustype) {	case BUS_SBUS:		if (bp != NULL && strcmp(bp->name, "esp") == 0 &&		    SAME_ESP(sc, bp, ca))			bootpath_store(1, bp + 1);		break;	default:		if (bp != NULL && strcmp(bp->name, "esp") == 0 &&			bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit)			bootpath_store(1, bp + 1);		break;	}	/* Do the common parts of attachment. */	ncr53c9x_attach(sc, &esp_switch, &esp_dev);	/* Turn on target selection using the `dma' method */	ncr53c9x_dmaselect = 1;	bootpath_store(1, NULL);}