bus_dmamem_free(sc->sc_dmat, &sc->sc_listseg, rseg); goto fail_1;
goto fail_3;
vr_attach(parent, self, aux)	struct device *parent, *self;	void *aux;{	int			s, i;	u_int32_t		command;	struct vr_softc		*sc = (struct vr_softc *)self;	struct pci_attach_args 	*pa = aux;	pci_chipset_tag_t	pc = pa->pa_pc;	pci_intr_handle_t	ih;	const char		*intrstr = NULL;	struct ifnet		*ifp = &sc->arpcom.ac_if;	bus_size_t		iosize;	int rseg;	caddr_t kva;	s = splimp();	/*	 * Handle power management nonsense.	 */	command = pci_conf_read(pa->pa_pc, pa->pa_tag,	    VR_PCI_CAPID) & 0x000000ff;	if (command == 0x01) {		command = pci_conf_read(pa->pa_pc, pa->pa_tag,		    VR_PCI_PWRMGMTCTRL);		if (command & VR_PSTATE_MASK) {			pcireg_t	iobase, membase, irq;			/* Save important PCI config data. */			iobase = pci_conf_read(pa->pa_pc, pa->pa_tag,						VR_PCI_LOIO);			membase = pci_conf_read(pa->pa_pc, pa->pa_tag,						VR_PCI_LOMEM);			irq = pci_conf_read(pa->pa_pc, pa->pa_tag,						VR_PCI_INTLINE);			/* Reset the power state. */			command &= 0xFFFFFFFC;			pci_conf_write(pa->pa_pc, pa->pa_tag,						VR_PCI_PWRMGMTCTRL, command);			/* Restore PCI config data. */			pci_conf_write(pa->pa_pc, pa->pa_tag,						VR_PCI_LOIO, iobase);			pci_conf_write(pa->pa_pc, pa->pa_tag,						VR_PCI_LOMEM, membase);			pci_conf_write(pa->pa_pc, pa->pa_tag,						VR_PCI_INTLINE, irq);		}	}	/*	 * Map control/status registers.	 */	command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);	sc->vr_revid = PCI_REVISION(pa->pa_class);#ifdef VR_USEIOSPACE	if (!(command & PCI_COMMAND_IO_ENABLE)) {		printf(": failed to enable I/O ports\n");		goto fail;	}	if (pci_mapreg_map(pa, VR_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,	    &sc->vr_btag, &sc->vr_bhandle, NULL, &iosize, 0)) {		printf(": failed to map i/o space\n");		goto fail;	}#else	if (!(command & PCI_COMMAND_MEM_ENABLE)) {		printf(": failed to enable memory mapping\n");		goto fail;	}	if (pci_mapreg_map(pa, VR_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,	    &sc->vr_btag, &sc->vr_bhandle, NULL, &iosize, 0)) {		printf(": failed to map memory space\n");		goto fail;	}#endif	/* Allocate interrupt */	if (pci_intr_map(pa, &ih)) {		printf(": couldn't map interrupt\n");		goto fail_1;	}	intrstr = pci_intr_string(pc, ih);	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, vr_intr, sc,				       self->dv_xname);	if (sc->sc_ih == NULL) {		printf(": could not establish interrupt");		if (intrstr != NULL)			printf(" at %s", intrstr);		printf("\n");		goto fail_1;	}	printf(": %s", intrstr);	/*	 * Windows may put the chip in suspend mode when it	 * shuts down. Be sure to kick it in the head to wake it	 * up again.	 */	VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));	/* Reset the adapter. */	vr_reset(sc);	/*	 * Turn on bit2 (MIION) in PCI configuration register 0x53 during	 * initialization and disable AUTOPOLL.	 */	pci_conf_write(pa->pa_pc, pa->pa_tag, VR_PCI_MODE,	    pci_conf_read(pa->pa_pc, pa->pa_tag, VR_PCI_MODE) |	    (VR_MODE3_MIION << 24));	VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);	/*	 * Get station address. The way the Rhine chips work,	 * you're not allowed to directly access the EEPROM once	 * they've been programmed a special way. Consequently,	 * we need to read the node address from the PAR0 and PAR1	 * registers.	 */	VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);	DELAY(1000);	for (i = 0; i < ETHER_ADDR_LEN; i++)		sc->arpcom.ac_enaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);	/*	 * A Rhine chip was detected. Inform the world.	 */	printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr));	sc->sc_dmat = pa->pa_dmat;	if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vr_list_data),	    PAGE_SIZE, 0, &sc->sc_listseg, 1, &rseg, BUS_DMA_NOWAIT)) {		printf("%s: can't alloc list\n", sc->sc_dev.dv_xname);		goto fail_1;	}	if (bus_dmamem_map(sc->sc_dmat, &sc->sc_listseg, rseg,	    sizeof(struct vr_list_data), &kva, BUS_DMA_NOWAIT)) {		printf("%s: can't map dma buffers (%d bytes)\n",		    sc->sc_dev.dv_xname, sizeof(struct vr_list_data));		bus_dmamem_free(sc->sc_dmat, &sc->sc_listseg, rseg);		goto fail_1;	}	if (bus_dmamap_create(sc->sc_dmat, sizeof(struct vr_list_data), 1,	    sizeof(struct vr_list_data), 0, BUS_DMA_NOWAIT, &sc->sc_listmap)) {		printf("%s: can't create dma map\n", sc->sc_dev.dv_xname);		bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct vr_list_data));		bus_dmamem_free(sc->sc_dmat, &sc->sc_listseg, rseg);		goto fail_1;	}	if (bus_dmamap_load(sc->sc_dmat, sc->sc_listmap, kva,	    sizeof(struct vr_list_data), NULL, BUS_DMA_NOWAIT)) {		printf("%s: can't load dma map\n", sc->sc_dev.dv_xname);		bus_dmamap_destroy(sc->sc_dmat, sc->sc_listmap);		bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct vr_list_data));		bus_dmamem_free(sc->sc_dmat, &sc->sc_listseg, rseg);		goto fail_1;	}	sc->vr_ldata = (struct vr_list_data *)kva;	bzero(sc->vr_ldata, sizeof(struct vr_list_data));	ifp = &sc->arpcom.ac_if;	ifp->if_softc = sc;	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;	ifp->if_ioctl = vr_ioctl;	ifp->if_start = vr_start;	ifp->if_watchdog = vr_watchdog;	ifp->if_baudrate = 10000000;	IFQ_SET_READY(&ifp->if_snd);	bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);	/*	 * Do MII setup.	 */	sc->sc_mii.mii_ifp = ifp;	sc->sc_mii.mii_readreg = vr_miibus_readreg;	sc->sc_mii.mii_writereg = vr_miibus_writereg;	sc->sc_mii.mii_statchg = vr_miibus_statchg;	ifmedia_init(&sc->sc_mii.mii_media, 0, vr_ifmedia_upd, vr_ifmedia_sts);	mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY,	    0);	if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);	} else		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);	timeout_set(&sc->sc_to, vr_tick, sc);	/*	 * Call MI attach routines.	 */	if_attach(ifp);	ether_ifattach(ifp);	shutdownhook_establish(vr_shutdown, sc);fail_1:	bus_space_unmap(sc->vr_btag, sc->vr_bhandle, iosize);fail:	splx(s);	return;}