volatile struct clreg *cl_reg;
struct clreg *cl_reg;
clcninit(cp)struct consdev *cp;{#ifdef MAP_DOES_WORK	int size = (0x1ff + PGOFSET) & ~PGOFSET;	int pcc2_size = (0x3C + PGOFSET) & ~PGOFSET;#endif	volatile struct clreg *cl_reg;		cl_cons.cl_paddr = (void *)0xfff45000;#ifdef MAP_DOES_WORK	cl_cons.cl_vaddr = mapiodev(cl_cons.cl_paddr,size);	cd_pcc2_base = mapiodev(0xfff42000,pcc2_size);#else	cl_cons.cl_vaddr   = (struct clreg *)IIOV(cl_cons.cl_paddr);	cl_cons.pcctwoaddr = (void *)IIOV(0xfff42000);#endif	cl_reg = cl_cons.cl_vaddr;	/* reset the chip? */#ifdef CLCD_DO_RESET#endif	/* set up globals */#ifdef NOT_ALREADY_SETUP	cl_reg->cl_tftc  = 0x10;	cl_reg->cl_tpr   = CL_TIMEOUT; /* is this correct?? */	cl_reg->cl_rpilr = 0x03;	cl_reg->cl_tpilr = 0x02;	cl_reg->cl_mpilr = 0x01;	/* set up the tty00 to be 9600 8N1 */	cl_reg->cl_car   = 0x00;	cl_reg->cl_cor1  = 0x17;	/* No parity, ignore parity, 8 bit char */	cl_reg->cl_cor2  = 0x00;	cl_reg->cl_cor3  = 0x02;	/* 1 stop bit */	cl_reg->cl_cor4  = 0x00;	cl_reg->cl_cor5  = 0x00;	cl_reg->cl_cor6  = 0x00;	cl_reg->cl_cor7  = 0x00;	cl_reg->cl_schr1 = 0x00;	cl_reg->cl_schr2 = 0x00;	cl_reg->cl_schr3 = 0x00;	cl_reg->cl_schr4 = 0x00;	cl_reg->cl_scrl  = 0x00;	cl_reg->cl_scrh  = 0x00;	cl_reg->cl_lnxt  = 0x00;	cl_reg->cl_cpsr  = 0x00;#endif	return 0;}