}
hpt_setup_channel(chp)	struct channel_softc *chp;{	struct ata_drive_datas *drvp;	int drive;	int cable;	u_int32_t before, after;	u_int32_t idedma_ctl;	struct pciide_channel *cp = (struct pciide_channel*)chp;	struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;	cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL);	/* setup DMA if needed */	pciide_channel_dma_setup(cp);	idedma_ctl = 0;	/* Per drive settings */	for (drive = 0; drive < 2; drive++) {		drvp = &chp->ch_drive[drive];		/* If no drive, skip */		if ((drvp->drive_flags & DRIVE) == 0)			continue;		before = pci_conf_read(sc->sc_pc, sc->sc_tag,				       HPT_IDETIM(chp->channel, drive));		/* add timing values, setup DMA if needed */		if (drvp->drive_flags & DRIVE_UDMA) {			/* use Ultra/DMA */			drvp->drive_flags &= ~DRIVE_DMA;			if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 &&			    drvp->UDMA_mode > 2)				drvp->UDMA_mode = 2;			after = (sc->sc_wdcdev.nchannels == 2) ?			    ((sc->sc_wdcdev.UDMA_cap == 6) ?			    hpt374_udma[drvp->UDMA_mode] :			    hpt370_udma[drvp->UDMA_mode]) :			    hpt366_udma[drvp->UDMA_mode];			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);		} else if (drvp->drive_flags & DRIVE_DMA) {			/*			 * use Multiword DMA.			 * Timings will be used for both PIO and DMA, so adjust			 * DMA mode if needed			 */			if (drvp->PIO_mode >= 3 &&			    (drvp->DMA_mode + 2) > drvp->PIO_mode) {				drvp->DMA_mode = drvp->PIO_mode - 2;			}			after = (sc->sc_wdcdev.nchannels == 2) ?			    ((sc->sc_wdcdev.UDMA_cap == 6) ?			    hpt374_dma[drvp->DMA_mode] :			    hpt370_dma[drvp->DMA_mode]) :			    hpt366_dma[drvp->DMA_mode];			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);		} else {			/* PIO only */			after = (sc->sc_wdcdev.nchannels == 2) ?			    ( (sc->sc_wdcdev.UDMA_cap == 6) ?			    hpt374_pio[drvp->PIO_mode] :			    hpt370_pio[drvp->PIO_mode]) :			    hpt366_pio[drvp->PIO_mode];		}		pci_conf_write(sc->sc_pc, sc->sc_tag,		    HPT_IDETIM(chp->channel, drive), after);		WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x "		    "(BIOS 0x%08x)\n", sc->sc_wdcdev.sc_dev.dv_xname,		    after, before), DEBUG_PROBE);	}	if (idedma_ctl != 0) {		/* Add software bits in status register */		bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,		    IDEDMA_CTL(chp->channel), idedma_ctl);	}	pciide_print_modes(cp);}