MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_SPEEDSEL);
static void mx_init(xsc)	void			*xsc;{	struct mx_softc		*sc = xsc;	struct ifnet		*ifp = &sc->arpcom.ac_if;	u_int16_t		phy_bmcr = 0;	int			s;	if (sc->mx_autoneg)		return;	s = splimp();	if (sc->mx_hasmii != 0)		phy_bmcr = mx_phy_readreg(sc, PHY_BMCR);	/*	 * Cancel pending I/O and free all RX/TX buffers.	 */	mx_stop(sc);	mx_reset(sc);	/*	 * Set cache alignment and burst length.	 */	CSR_WRITE_4(sc, MX_BUSCTL, MX_BUSCTL_CONFIG);	MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_NO_RXCRC);	MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_HEARTBEAT);	MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_STORENFWD);	MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_TX_BACKOFF);	/*	 * The app notes for the 98713 and 98715A say that	 * in order to have the chips operate properly, a magic	 * number must be written to CSR16. Macronix does not	 * document the meaning of these bits so there's no way	 * to know exactly what they mean. The 98713 has a magic	 * number all its own; the rest all use a different one.	 */	MX_CLRBIT(sc, MX_MAGICPACKET, 0xFFFF0000);	if (sc->mx_type == MX_TYPE_98713)		MX_SETBIT(sc, MX_MAGICPACKET, MX_MAGIC_98713);	else		MX_SETBIT(sc, MX_MAGICPACKET, MX_MAGIC_98715);	if (sc->mx_hasmii != 0) {		MX_SETBIT(sc, MX_WATCHDOG, MX_WDOG_JABBERDIS);		mx_setcfg(sc, mx_phy_readreg(sc, PHY_BMCR));	} else		mx_setmode(sc, sc->ifmedia.ifm_media, 0);	MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_TX_THRESH);	MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_SPEEDSEL);	if (IFM_SUBTYPE(sc->ifmedia.ifm_media) == IFM_10_T)		MX_SETBIT(sc, MX_NETCFG, MX_TXTHRESH_160BYTES);	else		MX_SETBIT(sc, MX_NETCFG, MX_TXTHRESH_72BYTES);	/* Init circular RX list. */	if (mx_list_rx_init(sc) == ENOBUFS) {		printf("mx%d: no memory for rx buffers\n", sc->mx_unit);		mx_stop(sc);		(void)splx(s);		return;	}	/*	 * Init tx descriptors.	 */	mx_list_tx_init(sc);	/*	 * Load the address of the RX list.	 */	CSR_WRITE_4(sc, MX_RXADDR, vtophys(sc->mx_cdata.mx_rx_head->mx_ptr));	/*	 * Load the RX/multicast filter.	 */	mx_setfilt(sc);	/*	 * Enable interrupts.	 */	CSR_WRITE_4(sc, MX_IMR, MX_INTRS);	CSR_WRITE_4(sc, MX_ISR, 0xFFFFFFFF);	/* Enable receiver and transmitter. */	MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_TX_ON|MX_NETCFG_RX_ON);	CSR_WRITE_4(sc, MX_RXSTART, 0xFFFFFFFF);	/* Restore state of BMCR */	if (sc->mx_hasmii != 0)		mx_phy_writereg(sc, PHY_BMCR, phy_bmcr);	ifp->if_flags |= IFF_RUNNING;	ifp->if_flags &= ~IFF_OACTIVE;	(void)splx(s);	return;}