if (hal->ah_op_mode & HAL_M_HOSTAP) { int_mask |= AR5K_AR5211_PIMR_MIB; } else { int_mask &= ~AR5K_AR5211_PIMR_MIB; }
ar5k_ar5211_set_intr(hal, new_mask)	struct ath_hal *hal;	HAL_INT new_mask;{	HAL_INT old_mask, int_mask;	/*	 * Disable card interrupts to prevent any race conditions	 * (they will be re-enabled afterwards).	 */	AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE);	old_mask = hal->ah_imr;	/*	 * Add additional, chipset-dependent interrupt mask flags	 * and write them to the IMR (interrupt mask register).	 */	int_mask = new_mask & HAL_INT_COMMON;	if (new_mask & HAL_INT_RX)		int_mask |=		    AR5K_AR5211_PIMR_RXOK |		    AR5K_AR5211_PIMR_RXERR |		    AR5K_AR5211_PIMR_RXORN |		    AR5K_AR5211_PIMR_RXDESC;	if (new_mask & HAL_INT_TX)		int_mask |=		    AR5K_AR5211_PIMR_TXOK |		    AR5K_AR5211_PIMR_TXERR |		    AR5K_AR5211_PIMR_TXDESC |		    AR5K_AR5211_PIMR_TXURN;	if (new_mask & HAL_INT_FATAL) {		int_mask |= AR5K_AR5211_PIMR_HIUERR;		AR5K_REG_ENABLE_BITS(AR5K_AR5211_SIMR2,		    AR5K_AR5211_SIMR2_MCABT |		    AR5K_AR5211_SIMR2_SSERR |		    AR5K_AR5211_SIMR2_DPERR);	}	if (hal->ah_op_mode & HAL_M_HOSTAP) {		int_mask |= AR5K_AR5211_PIMR_MIB;	} else {		int_mask &= ~AR5K_AR5211_PIMR_MIB;	}	AR5K_REG_WRITE(AR5K_AR5211_PIMR, int_mask);	/* Store new interrupt mask */	hal->ah_imr = new_mask;	/* ..re-enable interrupts */	AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE);	return (old_mask);}