s = splimp();
s = splnet();
vr_init(xsc)	void			*xsc;{	struct vr_softc		*sc = xsc;	struct ifnet		*ifp = &sc->arpcom.ac_if;	struct mii_data		*mii = &sc->sc_mii;	int			s, i;	s = splimp();	/*	 * Cancel pending I/O and free all RX/TX buffers.	 */	vr_stop(sc);	vr_reset(sc);	/*	 * Set our station address.	 */	for (i = 0; i < ETHER_ADDR_LEN; i++)		CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);	/* Set DMA size */	VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);	VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);	/*	 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,	 * so we must set both.	 */	VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);	VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);	VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);	VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);	VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);	VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);	VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);	VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);	/* Init circular RX list. */	if (vr_list_rx_init(sc) == ENOBUFS) {		printf("%s: initialization failed: no memory for rx buffers\n",		    sc->sc_dev.dv_xname);		vr_stop(sc);		splx(s);		return;	}	/*	 * Init tx descriptors.	 */	if (vr_list_tx_init(sc) == ENOBUFS) {		printf("%s: initialization failed: no memory for tx buffers\n",		    sc->sc_dev.dv_xname);		vr_stop(sc);		splx(s);		return;	}	/* If we want promiscuous mode, set the allframes bit. */	if (ifp->if_flags & IFF_PROMISC)		VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);	else		VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);	/* Set capture broadcast bit to capture broadcast frames. */	if (ifp->if_flags & IFF_BROADCAST)		VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);	else		VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);	/*	 * Program the multicast filter, if necessary.	 */	vr_setmulti(sc);	/*	 * Load the address of the RX list.	 */	CSR_WRITE_4(sc, VR_RXADDR, sc->vr_cdata.vr_rx_head->vr_paddr);	/* Enable receiver and transmitter. */	CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|				    VR_CMD_TX_ON|VR_CMD_RX_ON|				    VR_CMD_RX_GO);	CSR_WRITE_4(sc, VR_TXADDR, sc->sc_listmap->dm_segs[0].ds_addr +	    offsetof(struct vr_list_data, vr_tx_list[0]));	/*	 * Enable interrupts.	 */	CSR_WRITE_2(sc, VR_ISR, 0xFFFF);	CSR_WRITE_2(sc, VR_IMR, VR_INTRS);	/* Restore state of BMCR */	mii_mediachg(mii);	ifp->if_flags |= IFF_RUNNING;	ifp->if_flags &= ~IFF_OACTIVE;	if (!timeout_pending(&sc->sc_to))		timeout_add(&sc->sc_to, hz);	splx(s);}