ret = ar5k_register_timeout(hal, AR5K_AR5211_QCU_STS(queue),
ar5k_register_timeout(hal, AR5K_AR5211_QCU_STS(queue),
ar5k_ar5211_stop_tx_dma(hal, queue)	struct ath_hal *hal;	u_int queue;{	HAL_BOOL ret;	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);	/*	 * Schedule TX disable and wait until queue is empty	 */	AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXD, queue);	ret = ar5k_register_timeout(hal, AR5K_AR5211_QCU_STS(queue),	    AR5K_AR5211_QCU_STS_FRMPENDCNT, 0, AH_FALSE);	if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, queue))		return (AH_FALSE);	/* Clear register */	AR5K_REG_WRITE(AR5K_AR5211_QCU_TXD, 0);	return (AH_TRUE);}