if (mmutype == MMU_68040 && pmap != pmap_kernel() && (curproc->p_md.md_flags & MDP_UNCACHE_WX) && (prot & VM_PROT_EXECUTE) && (prot & VM_PROT_WRITE)) checkpv = cacheable = FALSE;
pmap_enter(pmap, va, pa, prot, wired)	register pmap_t pmap;	vm_offset_t va;	register vm_offset_t pa;	vm_prot_t prot;	boolean_t wired;{	register u_int *pte;	register int npte;	vm_offset_t opa;	boolean_t cacheable = TRUE;	boolean_t checkpv = TRUE;#ifdef DEBUG	if (pmapdebug & (PDB_FOLLOW|PDB_ENTER))		printf("pmap_enter(%x, %x, %x, %x, %x)\n",		       pmap, va, pa, prot, wired);#endif	if (pmap == NULL)		return;#ifdef DEBUG	if (pmap == pmap_kernel())		enter_stats.kernel++;	else		enter_stats.user++;#endif	/*	 * For user mapping, allocate kernel VM resources if necessary.	 */	if (pmap->pm_ptab == NULL)		pmap->pm_ptab = (u_int *)			kmem_alloc_wait(pt_map, AMIGA_UPTSIZE);	/*	 * Segment table entry not valid, we need a new PT page	 */	if (!pmap_ste_v(pmap, va))		pmap_enter_ptpage(pmap, va);	pte = pmap_pte(pmap, va);	opa = pmap_pte_pa(pte);#ifdef DEBUG	if (pmapdebug & PDB_ENTER)		printf("enter: pte %x, *pte %x\n", pte, *(int *)pte);#endif	/*	 * Mapping has not changed, must be protection or wiring change.	 */	if (opa == pa) {#ifdef DEBUG		enter_stats.pwchange++;#endif		/*		 * Wiring change, just update stats.		 * We don't worry about wiring PT pages as they remain		 * resident as long as there are valid mappings in them.		 * Hence, if a user page is wired, the PT page will be also.		 */		if (wired && !pmap_pte_w(pte) || !wired && pmap_pte_w(pte)) {#ifdef DEBUG			if (pmapdebug & PDB_ENTER)				printf("enter: wiring change -> %x\n", wired);#endif			if (wired)				pmap->pm_stats.wired_count++;			else				pmap->pm_stats.wired_count--;#ifdef DEBUG			enter_stats.wchange++;#endif		}		/*		 * Retain cache inhibition status		 */		checkpv = FALSE;		if (pmap_pte_ci(pte))			cacheable = FALSE;		goto validate;	}	/*	 * Mapping has changed, invalidate old range and fall through to	 * handle validating new mapping.	 */	if (opa) {#ifdef DEBUG		if (pmapdebug & PDB_ENTER)			printf("enter: removing old mapping %x\n", va);#endif		pmap_remove(pmap, va, va + PAGE_SIZE);#ifdef DEBUG		enter_stats.mchange++;#endif	}	/*	 * If this is a new user mapping, increment the wiring count	 * on this PT page.  PT pages are wired down as long as there	 * is a valid mapping in the page.	 */	if (pmap != pmap_kernel())		vm_map_pageable(pt_map, trunc_page(pte),				round_page(pte+1), FALSE);	/*	 * Enter on the PV list if part of our managed memory	 * Note that we raise IPL while manipulating pv_table	 * since pmap_enter can be called at interrupt time.	 */	if (pmap_valid_page(pa)) {		register pv_entry_t pv, npv;		int s;#ifdef DEBUG		enter_stats.managed++;#endif		pv = pa_to_pvh(pa);		s = splimp();#ifdef DEBUG		if (pmapdebug & PDB_ENTER)			printf("enter: pv at %x: %x/%x/%x\n",			       pv, pv->pv_va, pv->pv_pmap, pv->pv_next);#endif		/*		 * No entries yet, use header as the first entry		 */		if (pv->pv_pmap == NULL) {#ifdef DEBUG			enter_stats.firstpv++;#endif			pv->pv_va = va;			pv->pv_pmap = pmap;			pv->pv_next = NULL;			pv->pv_ptste = NULL;			pv->pv_ptpmap = NULL;			pv->pv_flags = 0;		}		/*		 * There is at least one other VA mapping this page.		 * Place this entry after the header.		 */		else {#ifdef DEBUG			for (npv = pv; npv; npv = npv->pv_next)				if (pmap == npv->pv_pmap && va == npv->pv_va)					panic("pmap_enter: already in pv_tab");#endif			npv = (pv_entry_t)				malloc(sizeof *npv, M_VMPVENT, M_NOWAIT);			if (npv == NULL)				panic("pmap_enter: PV allocation failure");			npv->pv_va = va;			npv->pv_pmap = pmap;			npv->pv_next = pv->pv_next;			npv->pv_ptste = NULL;			npv->pv_ptpmap = NULL;			pv->pv_next = npv;#ifdef DEBUG			if (!npv->pv_next)				enter_stats.secondpv++;#endif		}		splx(s);	}	/*	 * Assumption: if it is not part of our managed memory	 * then it must be device memory which may be volitile.	 */	else if (pmap_initialized) {		checkpv = cacheable = FALSE;#ifdef DEBUG		enter_stats.unmanaged++;#endif	}	/*	 * Increment counters	 */	pmap->pm_stats.resident_count++;	if (wired)		pmap->pm_stats.wired_count++;validate:	/*	 * Now validate mapping with desired protection/wiring.	 * Assume uniform modified and referenced status for all	 * AMIGA pages in a MACH page.	 */#ifdef M68040	if (mmutype == MMU_68040 && pmap == pmap_kernel() && va >= AMIGA_UPTBASE && 	    va < (AMIGA_UPTBASE + AMIGA_UPTMAXSIZE))		cacheable = FALSE;	/* don't cache user page tables */#endif	npte = (pa & PG_FRAME) | pte_prot(pmap, prot) | PG_V;	npte |= (*(int *)pte & (PG_M|PG_U));	if (wired)		npte |= PG_W;	if (!checkpv && !cacheable)		npte |= PG_CI;#ifdef M68040	else if (mmutype == MMU_68040 && (npte & PG_PROT) == PG_RW)		npte |= PG_CCB;		/* cache copyback */#endif	/*	 * Remember if this was a wiring-only change.	 * If so, we need not flush the TLB and caches.	 */	wired = ((*(int *)pte ^ npte) == PG_W);#ifdef M68040	if (mmutype == MMU_68040 && !wired) {		DCFP(pa);		ICPP(pa);	}#endif#ifdef DEBUG	if (pmapdebug & PDB_ENTER)		printf("enter: new pte value %x\n", npte);#endif	*(int *)pte++ = npte;	if (!wired && active_pmap(pmap))		TBIS(va);#ifdef DEBUG	if ((pmapdebug & PDB_WIRING) && pmap != pmap_kernel()) {		va -= PAGE_SIZE;		pmap_check_wiring("enter", trunc_page(pmap_pte(pmap, va)));	}#endif}