cl_reg->cl_car	= (char) channel;
cl_reg->cl_car	= (u_char) channel;
cl_initchannel(sc, channel)	struct clsoftc *sc;	int channel;{	int s;	volatile struct clreg *cl_reg = sc->cl_reg;	/* set up option registers */	sc->sc_cl[channel].tty = NULL;	s = splhigh();	cl_reg->cl_car	= (char) channel;	/* async, do we want to try DMA at some point? */	cl_reg->cl_livr	= PCC2_VECBASE + 0xc;/* set vector base at 5C */	cl_reg->cl_ier	= 0x88;  /* should change XXX */	cl_reg->cl_licr	= 0x00;  /* will change if DMA support XXX */	/* if the port is not the console */	if (sc->sc_cl[channel].cl_consio != 1) {		cl_reg->cl_cmr	= 0x02; 		cl_reg->cl_cor1	= 0x17;		cl_reg->cl_cor2	= 0x00;		cl_reg->cl_cor3	= 0x02;		cl_reg->cl_cor4	= 0xec;		cl_reg->cl_cor5	= 0xec;		cl_reg->cl_cor6	= 0x00;		cl_reg->cl_cor7	= 0x00;		cl_reg->cl_schr1	= 0x00;		cl_reg->cl_schr2	= 0x00;		cl_reg->cl_schr3	= 0x00;		cl_reg->cl_schr4	= 0x00;		cl_reg->cl_scrl	= 0x00;		cl_reg->cl_scrh	= 0x00;		cl_reg->cl_lnxt	= 0x00;		cl_reg->cl_rbpr	= 0x40; /* 9600 */		cl_reg->cl_rcor	= 0x01;		cl_reg->cl_tbpr	= 0x40; /* 9600 */		cl_reg->cl_tcor	= 0x01 << 5;		/* console port should be 0x88 already */		cl_reg->cl_msvr_rts	= 0x00;		cl_reg->cl_msvr_dtr	= 0x00;		cl_reg->cl_rtprl	= CL_RX_TIMEOUT;		cl_reg->cl_rtprh	= 0x00;	}	splx(s);}