ncr53c9x_dmaselect = 1;
sc->sc_features |= NCR_F_DMASELECT;
espattach(esc, gluep)	struct esp_softc *esc;	struct ncr53c9x_glue *gluep;{	struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;	void *icookie;	unsigned int uid = 0;	/*	 * Set up glue for MI code early; we use some of it here.	 */	sc->sc_glue = gluep;	/* gimme Mhz */	sc->sc_freq /= 1000000;	/*	 * XXX More of this should be in ncr53c9x_attach(), but	 * XXX should we really poke around the chip that much in	 * XXX the MI code?  Think about this more...	 */	/*	 * It is necessary to try to load the 2nd config register here,	 * to find out what rev the esp chip is, else the ncr53c9x_reset	 * will not set up the defaults correctly.	 */	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;	sc->sc_cfg3 = NCRCFG3_CDB;	NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);	if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=	    (NCRCFG2_SCSI2 | NCRCFG2_RPE)) {		sc->sc_rev = NCR_VARIANT_ESP100;	} else {		sc->sc_cfg2 = NCRCFG2_SCSI2;		NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);		sc->sc_cfg3 = 0;		NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);		sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);		NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);		if (NCR_READ_REG(sc, NCR_CFG3) !=		    (NCRCFG3_CDB | NCRCFG3_FCLK)) {			sc->sc_rev = NCR_VARIANT_ESP100A;		} else {			/* NCRCFG2_FE enables > 64K transfers */			sc->sc_cfg2 |= NCRCFG2_FE;			sc->sc_cfg3 = 0;			NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);			sc->sc_rev = NCR_VARIANT_ESP200;			/* XXX spec says it's valid after power up or chip reset */			uid = NCR_READ_REG(sc, NCR_UID);			if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */				sc->sc_rev = NCR_VARIANT_FAS366;		}	}#ifdef ESP_SBUS_DEBUG	printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid);#endif	/*	 * XXX minsync and maxxfer _should_ be set up in MI code,	 * XXX but it appears to have some dependency on what sort	 * XXX of DMA we're hooked up to, etc.	 */	/*	 * This is the value used to start sync negotiations	 * Note that the NCR register "SYNCTP" is programmed	 * in "clocks per byte", and has a minimum value of 4.	 * The SCSI period used in negotiation is one-fourth	 * of the time (in nanoseconds) needed to transfer one byte.	 * Since the chip's clock is given in MHz, we have the following	 * formula: 4 * period = (1000 / freq) * 4	 */	sc->sc_minsync = 1000 / sc->sc_freq;	/*	 * Alas, we must now modify the value a bit, because it's	 * only valid when can switch on FASTCLK and FASTSCSI bits  	 * in config register 3... 	 */	switch (sc->sc_rev) {	case NCR_VARIANT_ESP100:		sc->sc_maxxfer = 64 * 1024;		sc->sc_minsync = 0;	/* No synch on old chip? */		break;	case NCR_VARIANT_ESP100A:		sc->sc_maxxfer = 64 * 1024;		/* Min clocks/byte is 5 */		sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);		break;	case NCR_VARIANT_ESP200:	case NCR_VARIANT_FAS366:		sc->sc_maxxfer = 16 * 1024 * 1024;		/* XXX - do actually set FAST* bits */		break;	}	/* Establish interrupt channel */	icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 0,				     ncr53c9x_intr, sc);	/* register interrupt stats */	evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt);	/* Turn on target selection using the `dma' method */	if (sc->sc_rev != NCR_VARIANT_FAS366)		ncr53c9x_dmaselect = 1;	/* Do the common parts of attachment. */	ncr53c9x_attach(sc, &esp_switch, &esp_dev);}