sc->cl_reg->cl_cor1 = 0x40 | clen ;
cor1 = 0x10 | clen;
clccparam(sc, par, channel)	struct clsoftc *sc;	struct termios *par;	int channel;{	u_int divisor, clk, clen;	int s, imask, ints;	s = splcl();	sc->cl_reg->cl_car = channel;	if (par->c_ospeed == 0) { 		/* dont kill the console */		if(sc->sc_cl[channel].cl_consio == 0) {			/* disconnect, drop RTS DTR stop reciever */			sc->cl_reg->cl_msvr_rts = 0x00;			sc->cl_reg->cl_msvr_dtr = 0x00;			sc->cl_reg->cl_ccr = 0x05;		}		splx(s);		return (0xff);	}	sc->cl_reg->cl_msvr_rts = 0x03;	sc->cl_reg->cl_msvr_dtr = 0x03;	divisor = cl_clkdiv(par->c_ospeed);	clk	= cl_clknum(par->c_ospeed);	sc->cl_reg->cl_tbpr = divisor;	sc->cl_reg->cl_tcor = clk << 5;	divisor = cl_clkdiv(par->c_ispeed);	clk	= cl_clknum(par->c_ispeed);	sc->cl_reg->cl_rbpr = divisor;	sc->cl_reg->cl_rcor = clk;	sc->cl_reg->cl_rtprl = cl_clkrxtimeout(par->c_ispeed);	sc->cl_reg->cl_rtprh = 0x00;	switch (par->c_cflag & CSIZE) {	case CS5:		clen = 4; /* this is the mask for the chip. */		imask = 0x1F;		break;	case CS6:		clen = 5;		imask = 0x3F;		break;	case CS7:		clen = 6;		imask = 0x7F;		break;	default:		clen = 7;		imask = 0xFF;	}	sc->cl_reg->cl_cor3 = par->c_cflag & PARENB ? 4 : 2;	if (par->c_cflag & PARENB) {		if (par->c_cflag & PARODD) {			sc->cl_reg->cl_cor1 = 0xE0 | clen ; /* odd */		} else {			sc->cl_reg->cl_cor1 = 0x40 | clen ; /* even */		}	} else {		sc->cl_reg->cl_cor1 = 0x10 | clen; /* ignore parity */	}	if (sc->sc_cl[channel].cl_consio == 0		&& (par->c_cflag & CREAD) == 0 )	{		sc->cl_reg->cl_ccr = 0x08;	} else {		sc->cl_reg->cl_ccr = 0x0a;	}	ints = 0;#define SCC_DSR 0x80#define SCC_DCD 0x40#define SCC_CTS 0x20	if ((par->c_cflag & CLOCAL) == 0) {		ints |= SCC_DCD;	}	if ((par->c_cflag & CCTS_OFLOW) != 0) {		ints |= SCC_CTS;	}	if ((par->c_cflag & CRTSCTS) != 0) {		ints |= SCC_CTS;	}#ifdef DONT_LET_HARDWARE	if ((par->c_cflag & CCTS_IFLOW) != 0) {		ints |= SCC_DSR;	}#endif	sc->cl_reg->cl_cor4 = ints | CL_FIFO_CNT;	sc->cl_reg->cl_cor5 = ints | CL_FIFO_CNT;	return imask;}