if (te_cfg->active_ch & (1 << i)) {
if (te_cfg->active_ch & (1 << (i-1))) {
sdla_te_config(void* card_id){	sdla_t		*card = (sdla_t*)card_id;	sdla_te_cfg_t	*te_cfg = &card->fe_te.te_cfg;	u_int16_t	 adapter_type;	unsigned char	 value = 0x00, xlpg_scale = 0x00;	int		 channel_range = (IS_T1(&card->fe_te.te_cfg)) ?				NUM_OF_T1_CHANNELS : NUM_OF_E1_TIMESLOTS;	int i = 0;	WAN_ASSERT(card == NULL);	WAN_ASSERT(card->write_front_end_reg == NULL);	WAN_ASSERT(card->read_front_end_reg == NULL);	sdla_getcfg(card->hw, SDLA_ADAPTERTYPE, &adapter_type);#ifdef DEBUG_INIT	log(LOG_INFO, "%s: Setting %s configuration!\n",			card->devname,			IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1");	if (IS_T1(&card->fe_te.te_cfg)) {		log(LOG_DEBUG, "%s: Line decoding %s\n",			card->devname,			(te_cfg->lcode == WAN_LC_AMI) ? "AMI" : "B8ZS");		log(LOG_DEBUG, "%s: Frame type %s\n",			card->devname,			(te_cfg->frame == WAN_FR_ESF) ? "ESF" :			(te_cfg->frame == WAN_FR_D4) ? "D4" : "Unframed");		switch (te_cfg->lbo) {		case WAN_T1_LBO_0_DB:			log(LOG_DEBUG, "%s: LBO 0 dB\n", card->devname);			break;		case WAN_T1_LBO_75_DB:			log(LOG_DEBUG, "%s: LBO 7.5 dB\n", card->devname);			break;		case WAN_T1_LBO_15_DB:			log(LOG_DEBUG, "%s: LBO 15 dB\n", card->devname);			break;		case WAN_T1_LBO_225_DB:			log(LOG_DEBUG, "%s: LBO 22.5 dB\n", card->devname);			break;		case WAN_T1_0_110:			log(LOG_DEBUG, "%s: LBO 0-110 ft.\n", card->devname);			break;		case WAN_T1_110_220:			log(LOG_DEBUG, "%s: LBO 110-220 ft.\n", card->devname);			break;		case WAN_T1_220_330:			log(LOG_DEBUG, "%s: LBO 220-330 ft.\n", card->devname);			break;		case WAN_T1_330_440:			log(LOG_DEBUG, "%s: LBO 330-440 ft.\n", card->devname);			break;		case WAN_T1_440_550:			log(LOG_DEBUG, "%s: LBO 440-550 ft.\n", card->devname);			break;		case WAN_T1_550_660:			log(LOG_DEBUG, "%s: LBO 550-660 ft.\n",					card->devname);			break;		}	} else {		log(LOG_DEBUG, "%s: Line decoding %s\n", card->devname,		    (te_cfg->lcode == WAN_LC_AMI) ? "AMI" : "HDB3");		log(LOG_DEBUG, "%s: Frame type %s\n", card->devname,		    (te_cfg->frame == WAN_FR_CRC4) ? "CRC4" :		    (te_cfg->frame == WAN_FR_NCRC4) ? "non-CRC3" :		    "Unframed");	}	log(LOG_DEBUG, "%s: Clock mode %s\n", card->devname,	    (te_cfg->te_clock == WAN_NORMAL_CLK) ? "Normal" : "Master");#endif /* DEBUG_INIT */	/* 1. Initiate software reset of the COMET */	/* Set RESET=1 to place COMET into RESET */	WRITE_REG(REG_RESET, BIT_RESET);	/* Set RESET=0, disable software reset. COMET in default mode. */	WRITE_REG(REG_RESET, 0x0/*~BIT_RESET*/);	/* 2.Setup the XLPG(Transmit pulse template) to clear the pulse	** template */	ClearTemplate(card);	xlpg_scale = InitTemplate(card);	/* Program PMC for T1/E1 mode (Reg 0x00) */	if (IS_E1(&card->fe_te.te_cfg)) {		if (adapter_type & A101_ADPTR_T1E1_MASK) {			WRITE_REG(REG_GLOBAL_CFG,					BIT_GLOBAL_TRKEN | BIT_GLOBAL_PIO_OE |					BIT_GLOBAL_E1);		} else {			WRITE_REG(REG_GLOBAL_CFG,					BIT_GLOBAL_PIO_OE | BIT_GLOBAL_E1);		}	} else {		if (adapter_type & A101_ADPTR_T1E1_MASK) {			WRITE_REG(REG_GLOBAL_CFG,					BIT_GLOBAL_TRKEN | BIT_GLOBAL_PIO_OE);		}	}	/* Set SCALE[4-0] value in XLPG Line driver Configuration (Reg. 0xF0) */	WRITE_REG(REG_XLPG_LINE_CFG, xlpg_scale);	/* Set system clock and XCLK (Reg 0xD6) */	if (IS_T1(&card->fe_te.te_cfg)) {		WRITE_REG(REG_CSU_CFG, BIT_CSU_MODE0);		/*WRITE_REG(REG_CSU_CFG,		**	BIT_CSU_MODE2 | BIT_CSU_MODE1 | BIT_CSU_MODE0); */	} else {		WRITE_REG(REG_CSU_CFG, 0x00);	}	/* Set Line decoding (Reg. 0x10) */	if (te_cfg->lcode == WAN_LC_AMI) {		WRITE_REG(REG_CDRC_CFG, BIT_CDRC_CFG_AMI);	} else {		WRITE_REG(REG_CDRC_CFG, 0x00);	}	/* Program the RX-ELST/TX-ELST for the appropriate mode	** (Reg 0x1C, 0x20)*/	if (IS_E1(&card->fe_te.te_cfg)) {		WRITE_REG(REG_RX_ELST_CFG, BIT_RX_ELST_IR | BIT_RX_ELST_OR);		WRITE_REG(REG_TX_ELST_CFG, BIT_TX_ELST_IR | BIT_RX_ELST_OR);	} else {		WRITE_REG(REG_RX_ELST_CFG, 0x00);		WRITE_REG(REG_TX_ELST_CFG, 0x00);	}	value = 0x00;	if (IS_E1(&card->fe_te.te_cfg)) {		/* Program the trasmitter framing and line decoding		** (Reg. 0x80) */		if (te_cfg->lcode == WAN_LC_AMI) {			value |= BIT_E1_TRAN_AMI;		}		if (te_cfg->frame == WAN_FR_CRC4) {			value |= BIT_E1_TRAN_GENCRC;		} else if (te_cfg->frame == WAN_FR_UNFRAMED) {			value |= BIT_E1_TRAN_FDIS;		}		/* E1 TRAN Configuration (Reg 0x80) */		WRITE_REG(REG_E1_TRAN_CFG, value);		/* Configure the receive framer (Reg 0x90) */		value = 0x00;		if (te_cfg->frame == WAN_FR_CRC4) {			value |=				(BIT_E1_FRMR_CRCEN |				BIT_E1_FRMR_CASDIS |				BIT_E1_FRMR_REFCRCEN);		} else if (te_cfg->frame == WAN_FR_NCRC4) {			value |= BIT_E1_FRMR_CASDIS;		}		WRITE_REG(REG_E1_FRMR_CFG, value);	} else {		/* Set framing format & line decoding for transmitter		** (Reg 0x54) */		if (te_cfg->lcode == WAN_LC_B8ZS) {			value |= BIT_T1_XBAS_B8ZS;		} else {			value |= BIT_T1_XBAS_ZCS0;		}		if (te_cfg->frame == WAN_FR_ESF) {			value |= BIT_T1_XBAS_ESF;		}		WRITE_REG(REG_T1_XBAS_CFG, value);		/* Program framing format for receiving (Reg. 0x48) */		value = 0x00;		if (te_cfg->frame == WAN_FR_ESF) {			value = BIT_T1_FRMR_ESF | BIT_T1_FRMR_ESFFA;		}		WRITE_REG(REG_T1_FRMR_CFG, value);		/* Program the transmitter framing format and line deconding		** (Reg. 0x60) */		value = 0x00;		if (te_cfg->frame == WAN_FR_ESF) {			value = BIT_T1_ALMI_CFG_ESF;		}		WRITE_REG(REG_T1_ALMI_CFG, value);	}	/* Configure the SIGX configuration register */	if (IS_E1(&card->fe_te.te_cfg)) {		WRITE_REG(REG_SIGX_CFG, 0x00);	} else {		value = READ_REG(REG_SIGX_CFG);		if (te_cfg->frame == WAN_FR_ESF) {			value |= BIT_SIGX_ESF;		}		WRITE_REG(REG_SIGX_CFG, value);	}	/* Program the BTIF for the frame pulse mode */	value = 0x00;	if (IS_E1(&card->fe_te.te_cfg)) {		value |= BIT_BTIF_RATE0;	}	if (te_cfg->lcode == WAN_LC_AMI) {		value |= BIT_BTIF_NXDS0_0;	} else if (te_cfg->frame != WAN_FR_UNFRAMED) {		value |= BIT_BTIF_NXDS0_1;	}	if (adapter_type & A101_ADPTR_T1E1_MASK) {		value |= (BIT_BTIF_CMODE | BIT_BTIF_DE | BIT_BTIF_FE);	}	WRITE_REG(REG_BTIF_CFG, value);	/* Set the type of frame pulse on the backplane */	value = 0x00;	if (adapter_type & A101_ADPTR_T1E1_MASK) {		value = BIT_BTIF_FPMODE;	}	WRITE_REG(REG_BTIF_FR_PULSE_CFG, value);	/* Program the BRIF for the frame pulse mode */	value = 0x00;	if (IS_E1(&card->fe_te.te_cfg)) {		value |= BIT_BRIF_RATE0;	}	if (te_cfg->lcode == WAN_LC_AMI) {		value |= BIT_BRIF_NXDS0_0;	} else if (te_cfg->frame != WAN_FR_UNFRAMED) {		value |= BIT_BRIF_NXDS0_1;	}	if (adapter_type & A101_ADPTR_T1E1_MASK) {		value |= BIT_BRIF_CMODE;	}	WRITE_REG(REG_BRIF_CFG, value);	/* Set the type of frame pulse on the backplane */	value = 0x00;	if (adapter_type & A101_ADPTR_T1E1_MASK) {		value = BIT_BRIF_FPMODE;	}	WRITE_REG(REG_BRIF_FR_PULSE_CFG, value);	/* Program the data integraty checking on the BRIF */	WRITE_REG(REG_BRIF_DATA_CFG, BIT_BRIF_DATA_TRI_0);	/* Set TJAT FIFO output clock signal (Reg 0x06) */	if (te_cfg->te_clock == WAN_NORMAL_CLK) {		WRITE_REG(REG_TX_TIMING_OPT, BIT_TX_PLLREF1 | BIT_TX_TXELSTBYP);	} else {		WRITE_REG(REG_TX_TIMING_OPT,			BIT_TX_PLLREF1 | BIT_TX_PLLREF0 | BIT_TX_TXELSTBYP);	}	/* Set long or short and enable the equalizer (Reg 0xF8) */	WRITE_REG(REG_RLPS_CFG_STATUS, BIT_RLPS_CFG_STATUS_LONGE);	/* Select ALOS Detection and Clearance Thresholds (Reg 0xF9) */	/* NC: Aug 20 2003:	 *     Set the correct ALSO Detection/Clearance tresholds	 *     for T1/E1 lines, to get rid of false ALOS alarms.	 *	 *     Original incorrect value set was 0x00, for both T1/E1 */	if (IS_E1(&card->fe_te.te_cfg)) {		WRITE_REG(REG_RLPS_ALOS_DET_CLR_THR,				BIT_RLPS_ALOS_DET_THR_2|				BIT_RLPS_ALOS_DET_THR_1|				BIT_RLPS_ALOS_DET_THR_0);	} else {		WRITE_REG(REG_RLPS_ALOS_DET_CLR_THR,				BIT_RLPS_ALOS_CLR_THR_2|				BIT_RLPS_ALOS_CLR_THR_0|				BIT_RLPS_ALOS_DET_THR_2|				BIT_RLPS_ALOS_DET_THR_0);	}	/* Select ALOS Detection period to set the ALOS alarm (Reg 0xFA) */	WRITE_REG(REG_RLPS_ALOS_DET_PER, REG_RLPS_ALOS_DET_PER_0);	/* Select ALOS Clearance period to clear the ALOS alarm (Reg 0xFB) */	WRITE_REG(REG_RLPS_ALOS_CLR_PER, BIT_RLPS_ALOS_CLR_PER_0);	/* Program to 0x00 to initiate a microprocessor access to RAM	** (Reg 0xFC) *//* ERRATA	WRITE_REG(REG_RLPS_EQ_ADDR, 0x00); */	/* Write the value 0x80 to this register to select a write to the RAM	** (Reg 0xFD) *//* ERRATA	WRITE_REG(REG_RLPS_EQ_RWB, BIT_RLPS_EQ_RWB); */	/* Program this register to 0x00 to reset the pointer to the RAM	** (Reg 0xFE) */	WRITE_REG(REG_RLPS_EQ_STATUS, 0x00);	/* Configure the Recive line Equalizer (Reg 0xFF) */	WRITE_REG(REG_RLPS_EQ_CFG,		BIT_RLPS_EQ_RESERVED | BIT_RLPS_EQ_FREQ_1 | BIT_RLPS_EQ_FREQ_0);	/* Configure the TJAT FIFO (Reg 0x1B) */	WRITE_REG(REG_TJAT_CFG, BIT_TJAT_CENT);	/* Configure the RJAT FIFO (Reg 0x17) */	WRITE_REG(REG_RJAT_CFG, BIT_RJAT_CENT);	/* Program Receive Options (Reg 0x02) */	if (te_cfg->frame == WAN_FR_UNFRAMED) {		WRITE_REG(REG_RECEIVE_OPT, BIT_RECEIVE_OPT_UNF);	} else {		WRITE_REG(REG_RECEIVE_OPT, 0x00);	}	/* Configure XLPG Analog Test Positive control (Reg 0xF4) */	WRITE_REG(REG_XLPG_TPC, BIT_XLPG_TPC_0);	/* Configure XLPG Analog Test Negative control (Reg 0xF5) */	WRITE_REG(REG_XLPG_TNC, BIT_XLPG_TNC_0);	/* Program the RLPS Equalizer Voltage (Reg 0xDC) */	if (IS_E1(&card->fe_te.te_cfg)) {		WRITE_REG(REG_EQ_VREF, 0x34);	} else {		WRITE_REG(REG_EQ_VREF, 0x2C);	}	WRITE_REG(REG_RLPS_FUSE_CTRL_STAT, 0x00);/* ERRATA WRITE_REG(REG_RLPS_FUSE_CTRL_STAT, 0x00);*//* ERRAT VVV */	WRITE_REG(0xF4, 0x01);	WRITE_REG(0xF4, 0x01);	value = READ_REG(0xF4) & 0xFE;	WRITE_REG(0xF4, value);	WRITE_REG(0xF5, 0x01);	WRITE_REG(0xF5, 0x01);	value = READ_REG(0xF5) & 0xFE;	WRITE_REG(0xF5, value);	WRITE_REG(0xF6, 0x01);/* ERRATA ^^^ */	InitLineReceiver(card);	ClearRPSCReg(card);	ClearTPSCReg(card);	DisableAllChannels(card);	if (te_cfg->active_ch == ENABLE_ALL_CHANNELS) {#ifdef DEBUG_INIT		log(LOG_DEBUG, "%s: All channels enabled\n", card->devname);#endif /* DEBUG_INIT */		EnableAllChannels(card);	} else {		for (i = 1; i <= channel_range; i++) {			if (te_cfg->active_ch & (1 << i)) {#ifdef DEBUG_INIT				log(LOG_DEBUG, "%s: Enable channel %d\n",						card->devname, i);#endif /* DEBUG_INIT */				EnableTxChannel(card, i);				EnableRxChannel(card, i);			}		}	}	/* Initialize and start T1/E1 timer */	card->fe_te.te_timer_cmd = TE_SET_INTR;	bit_clear((u_int8_t*)&card->fe_te.te_critical,TE_TIMER_KILL);	timeout_set(&card->fe_te.te_timer, sdla_te_timer, (void*)card);	sdla_te_enable_timer(card, INTR_TE1_TIMER);	bit_set((u_int8_t*)&card->fe_te.te_critical, TE_CONFIGURED);	return 0;}