s = splimp();
s = splnet();
int ste_mii_readreg(sc, frame)	struct ste_softc		*sc;	struct ste_mii_frame	*frame;	{	int			i, ack, s;	s = splimp();	/*	 * Set up frame for RX.	 */	frame->mii_stdelim = STE_MII_STARTDELIM;	frame->mii_opcode = STE_MII_READOP;	frame->mii_turnaround = 0;	frame->mii_data = 0;		CSR_WRITE_2(sc, STE_PHYCTL, 0);	/* 	 * Turn on data xmit.	 */	MII_SET(STE_PHYCTL_MDIR);	ste_mii_sync(sc);	/*	 * Send command/address info.	 */	ste_mii_send(sc, frame->mii_stdelim, 2);	ste_mii_send(sc, frame->mii_opcode, 2);	ste_mii_send(sc, frame->mii_phyaddr, 5);	ste_mii_send(sc, frame->mii_regaddr, 5);	/* Turn off xmit. */	MII_CLR(STE_PHYCTL_MDIR);	/* Idle bit */	MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));	DELAY(1);	MII_SET(STE_PHYCTL_MCLK);	DELAY(1);	/* Check for ack */	MII_CLR(STE_PHYCTL_MCLK);	DELAY(1);	ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;	MII_SET(STE_PHYCTL_MCLK);	DELAY(1);	/*	 * Now try reading data bits. If the ack failed, we still	 * need to clock through 16 cycles to keep the PHY(s) in sync.	 */	if (ack) {		for(i = 0; i < 16; i++) {			MII_CLR(STE_PHYCTL_MCLK);			DELAY(1);			MII_SET(STE_PHYCTL_MCLK);			DELAY(1);		}		goto fail;	}	for (i = 0x8000; i; i >>= 1) {		MII_CLR(STE_PHYCTL_MCLK);		DELAY(1);		if (!ack) {			if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)				frame->mii_data |= i;			DELAY(1);		}		MII_SET(STE_PHYCTL_MCLK);		DELAY(1);	}fail:	MII_CLR(STE_PHYCTL_MCLK);	DELAY(1);	MII_SET(STE_PHYCTL_MCLK);	DELAY(1);	splx(s);	if (ack)		return(1);	return(0);}