s = splimp();
s = splnet();
vr_mii_readreg(sc, frame)	struct vr_softc		*sc;	struct vr_mii_frame	*frame;	#ifdef VR_USESWSHIFT{	int			i, ack, s;	s = splimp();	/*	 * Set up frame for RX.	 */	frame->mii_stdelim = VR_MII_STARTDELIM;	frame->mii_opcode = VR_MII_READOP;	frame->mii_turnaround = 0;	frame->mii_data = 0;		CSR_WRITE_1(sc, VR_MIICMD, 0);	VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);	/* 	 * Turn on data xmit.	 */	SIO_SET(VR_MIICMD_DIR);	vr_mii_sync(sc);	/*	 * Send command/address info.	 */	vr_mii_send(sc, frame->mii_stdelim, 2);	vr_mii_send(sc, frame->mii_opcode, 2);	vr_mii_send(sc, frame->mii_phyaddr, 5);	vr_mii_send(sc, frame->mii_regaddr, 5);	/* Idle bit */	SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));	DELAY(1);	SIO_SET(VR_MIICMD_CLK);	DELAY(1);	/* Turn off xmit. */	SIO_CLR(VR_MIICMD_DIR);	/* Check for ack */	SIO_CLR(VR_MIICMD_CLK);	DELAY(1);	ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;	SIO_SET(VR_MIICMD_CLK);	DELAY(1);	/*	 * Now try reading data bits. If the ack failed, we still	 * need to clock through 16 cycles to keep the PHY(s) in sync.	 */	if (ack) {		for(i = 0; i < 16; i++) {			SIO_CLR(VR_MIICMD_CLK);			DELAY(1);			SIO_SET(VR_MIICMD_CLK);			DELAY(1);		}		goto fail;	}	for (i = 0x8000; i; i >>= 1) {		SIO_CLR(VR_MIICMD_CLK);		DELAY(1);		if (!ack) {			if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)				frame->mii_data |= i;			DELAY(1);		}		SIO_SET(VR_MIICMD_CLK);		DELAY(1);	}fail:	SIO_CLR(VR_MIICMD_CLK);	DELAY(1);	SIO_SET(VR_MIICMD_CLK);	DELAY(1);	splx(s);	if (ack)		return(1);	return(0);}#else  {	int			s, i;	s = splimp();	/* Set the PHY-address */	CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|	    frame->mii_phyaddr);	/* Set the register-address */	CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);	VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);	for (i = 0; i < 10000; i++) {		if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)			break;		DELAY(1);	}	frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);	(void)splx(s);	return(0);}      