s = splimp();
s = splnet();
sk_init(void *xsc_if){	struct sk_if_softc	*sc_if = xsc_if;	struct sk_softc		*sc = sc_if->sk_softc;	struct ifnet		*ifp = &sc_if->arpcom.ac_if;	struct mii_data		*mii = &sc_if->sk_mii;	int			s;	DPRINTFN(2, ("sk_init\n"));	s = splimp();	if (ifp->if_flags & IFF_RUNNING) {		splx(s);		return;	}	/* Cancel pending I/O and free all RX/TX buffers. */	sk_stop(sc_if);	if (sc->sk_type == SK_GENESIS) {		/* Configure LINK_SYNC LED */		SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);		SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,			      SK_LINKLED_LINKSYNC_ON);		/* Configure RX LED */		SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,			      SK_RXLEDCTL_COUNTER_START);				/* Configure TX LED */		SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,			      SK_TXLEDCTL_COUNTER_START);	}	/* Configure I2C registers */	/* Configure XMAC(s) */	switch (sc->sk_type) {	case SK_GENESIS:		sk_init_xmac(sc_if);		break;	case SK_YUKON:	case SK_YUKON_LITE:	case SK_YUKON_LP:		sk_init_yukon(sc_if);		break;	}	mii_mediachg(mii);	if (sc->sk_type == SK_GENESIS) {		/* Configure MAC FIFOs */		SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);		SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);		SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);				SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);		SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);		SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);	}	/* Configure transmit arbiter(s) */	SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,	    SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);	/* Configure RAMbuffers */	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);	/* Configure BMUs */	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,	    SK_RX_RING_ADDR(sc_if, 0));	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);	SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);	SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,            SK_TX_RING_ADDR(sc_if, 0));	SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);	/* Init descriptors */	if (sk_init_rx_ring(sc_if) == ENOBUFS) {		printf("%s: initialization failed: no "		    "memory for rx buffers\n", sc_if->sk_dev.dv_xname);		sk_stop(sc_if);		splx(s);		return;	}	if (sk_init_tx_ring(sc_if) == ENOBUFS) {		printf("%s: initialization failed: no "		    "memory for tx buffers\n", sc_if->sk_dev.dv_xname);		sk_stop(sc_if);		splx(s);		return;	}	/* Configure interrupt handling */	CSR_READ_4(sc, SK_ISSR);	if (sc_if->sk_port == SK_PORT_A)		sc->sk_intrmask |= SK_INTRS1;	else		sc->sk_intrmask |= SK_INTRS2;	sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;	CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);	/* Start BMUs. */	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);	if (sc->sk_type == SK_GENESIS) {		/* Enable XMACs TX and RX state machines */		SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);		SK_XM_SETBIT_2(sc_if, XM_MMUCMD,			       XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);	}	if (SK_YUKON_FAMILY(sc->sk_type)) {		u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);		reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;		reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN);		SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);	}	ifp->if_flags |= IFF_RUNNING;	ifp->if_flags &= ~IFF_OACTIVE;	splx(s);}