CORE_ADDR func_addr,
struct value *function,
sh_push_dummy_call_fpu (struct gdbarch *gdbarch,			CORE_ADDR func_addr,			struct regcache *regcache,			CORE_ADDR bp_addr, int nargs,			struct value **args,			CORE_ADDR sp, int struct_return,			CORE_ADDR struct_addr){  int stack_offset = 0;  int argreg = ARG0_REGNUM;  int flt_argreg = 0;  int argnum;  struct type *type;  CORE_ADDR regval;  char *val;  int len, reg_size = 0;  int pass_on_stack = 0;  int treat_as_flt;  /* first force sp to a 4-byte alignment */  sp = sh_frame_align (gdbarch, sp);  if (struct_return)    regcache_cooked_write_unsigned (regcache,				    STRUCT_RETURN_REGNUM, struct_addr);  /* make room on stack for args */  sp -= sh_stack_allocsize (nargs, args);  /* Initialize float argument mechanism. */  sh_init_flt_argreg ();  /* Now load as many as possible of the first arguments into     registers, and push the rest onto the stack.  There are 16 bytes     in four registers available.  Loop thru args from first to last.  */  for (argnum = 0; argnum < nargs; argnum++)    {      type = VALUE_TYPE (args[argnum]);      len = TYPE_LENGTH (type);      val = sh_justify_value_in_reg (args[argnum], len);      /* Some decisions have to be made how various types are handled.         This also differs in different ABIs. */      pass_on_stack = 0;      /* Find out the next register to use for a floating point value. */      treat_as_flt = sh_treat_as_flt_p (type);      if (treat_as_flt)	flt_argreg = sh_next_flt_argreg (len);      /* In contrast to non-FPU CPUs, arguments are never split between	 registers and stack.  If an argument doesn't fit in the remaining	 registers it's always pushed entirely on the stack.  */      else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))	pass_on_stack = 1;      while (len > 0)	{	  if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)	      || (!treat_as_flt && (argreg > ARGLAST_REGNUM	                            || pass_on_stack)))	    {	      /* The data goes entirely on the stack, 4-byte aligned. */	      reg_size = (len + 3) & ~3;	      write_memory (sp + stack_offset, val, reg_size);	      stack_offset += reg_size;	    }	  else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)	    {	      /* Argument goes in a float argument register.  */	      reg_size = register_size (gdbarch, flt_argreg);	      regval = extract_unsigned_integer (val, reg_size);	      /* In little endian mode, float types taking two registers	         (doubles on sh4, long doubles on sh2e, sh3e and sh4) must		 be stored swapped in the argument registers.  The below		 code first writes the first 32 bits in the next but one		 register, increments the val and len values accordingly		 and then proceeds as normal by writing the second 32 bits		 into the next register. */	      if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE	          && TYPE_LENGTH (type) == 2 * reg_size)	        {		  regcache_cooked_write_unsigned (regcache, flt_argreg + 1,						  regval);		  val += reg_size;		  len -= reg_size;		  regval = extract_unsigned_integer (val, reg_size);		}	      regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);	    }	  else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)	    {	      /* there's room in a register */	      reg_size = register_size (gdbarch, argreg);	      regval = extract_unsigned_integer (val, reg_size);	      regcache_cooked_write_unsigned (regcache, argreg++, regval);	    }	  /* Store the value one register at a time or in one step on stack.  */	  len -= reg_size;	  val += reg_size;	}    }  /* Store return address. */  regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);  /* Update stack pointer.  */  regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);  return sp;}