bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 0x800 + PCIC_INTR, bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET);   pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
pccbb_chipinit(sc)	struct pccbb_softc *sc;{	pci_chipset_tag_t pc = sc->sc_pc;	pcitag_t tag = sc->sc_tag;	pcireg_t reg;	/* 	 * Set PCI command reg.	 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip.	 */	reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);	/* I believe it is harmless. */	reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |	    PCI_COMMAND_MASTER_ENABLE);	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);	/* 	 * Set CardBus latency timer.	 */	reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG);	if (PCI_CB_LATENCY(reg) < 0x20) {		reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT);		reg |= (0x20 << PCI_CB_LATENCY_SHIFT);		pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg);	}	DPRINTF(("CardBus latency timer 0x%x (%x)\n",	    PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG)));	/* 	 * Set PCI latency timer.	 */	reg = pci_conf_read(pc, tag, PCI_BHLC_REG);	if (PCI_LATTIMER(reg) < 0x10) {		reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);		reg |= (0x10 << PCI_LATTIMER_SHIFT);		pci_conf_write(pc, tag, PCI_BHLC_REG, reg);	}	DPRINTF(("PCI latency timer 0x%x (%x)\n",	    PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG)));	/* Route functional interrupts to PCI. */	reg = pci_conf_read(pc, tag, PCI_BCR_INTR);	reg &= ~CB_BCR_INTR_IREQ_ENABLE;	/* use PCI Intr */	reg |= CB_BCR_WRITE_POST_ENABLE;	/* enable write post */	pci_conf_write(pc, tag, PCI_BCR_INTR, reg);	switch (sc->sc_chipset) {	case CB_TI113X:		reg = pci_conf_read(pc, tag, PCI_CBCTRL);		/* This bit is shared, but may read as 0 on some chips, so set		   it explicitly on both functions. */		reg |= PCI113X_CBCTRL_PCI_IRQ_ENA;		/* CSC intr enable */		reg |= PCI113X_CBCTRL_PCI_CSC;		/* functional intr prohibit | prohibit ISA routing */		reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK);		pci_conf_write(pc, tag, PCI_CBCTRL, reg);		break;	case CB_TOPIC95B:		reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL);		reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;		pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg);		reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);		DPRINTF(("%s: topic slot ctrl reg 0x%x -> ",		    sc->sc_dev.dv_xname, reg));		reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |		    TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);		reg &= ~TOPIC_SLOT_CTRL_SWDETECT;		DPRINTF(("0x%x\n", reg));		pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg);		break;	}	/* Close all memory and I/O windows. */	pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff);	pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0);	pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff);	pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0);	pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff);	pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0);	pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff);	pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0);}