s = splimp();
s = splnet();
vr_mii_writereg(sc, frame)	struct vr_softc		*sc;	struct vr_mii_frame	*frame;	#ifdef VR_USESWSHIFT{	int			s;	s = splimp();	CSR_WRITE_1(sc, VR_MIICMD, 0);	VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);	/*	 * Set up frame for TX.	 */	frame->mii_stdelim = VR_MII_STARTDELIM;	frame->mii_opcode = VR_MII_WRITEOP;	frame->mii_turnaround = VR_MII_TURNAROUND;		/* 	 * Turn on data output.	 */	SIO_SET(VR_MIICMD_DIR);	vr_mii_sync(sc);	vr_mii_send(sc, frame->mii_stdelim, 2);	vr_mii_send(sc, frame->mii_opcode, 2);	vr_mii_send(sc, frame->mii_phyaddr, 5);	vr_mii_send(sc, frame->mii_regaddr, 5);	vr_mii_send(sc, frame->mii_turnaround, 2);	vr_mii_send(sc, frame->mii_data, 16);	/* Idle bit. */	SIO_SET(VR_MIICMD_CLK);	DELAY(1);	SIO_CLR(VR_MIICMD_CLK);	DELAY(1);	/*	 * Turn off xmit.	 */	SIO_CLR(VR_MIICMD_DIR);	splx(s);	return(0);}#else  {      	int			s, i;	s = splimp();	/* Set the PHY-address */	CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|	    frame->mii_phyaddr);	/* Set the register-address and data to write */	CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);	CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);	VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);	for (i = 0; i < 10000; i++) {		if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)			break;		DELAY(1); 	}	(void)splx(s);	return(0);}