hal->ah_cw_max = AR5K_TUNE_CWMAX_XR;
cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR;
ar5k_ar5212_resetTxQueue(hal, queue)	struct ath_hal *hal;	u_int queue;{	u_int32_t cw_min, cw_max, retry_lg, retry_sh;	struct ieee80211_channel *channel = (struct ieee80211_channel*)	    &hal->ah_current_channel;	HAL_TXQ_INFO *tq;	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);	tq = &hal->ah_txq[queue];	if (tq->tqi_type == HAL_TX_QUEUE_INACTIVE)		return (AH_TRUE);	/*	 * Set registers by channel mode	 */	if (IEEE80211_IS_CHAN_XR(channel)) {		hal->ah_cw_min = AR5K_TUNE_CWMIN_XR;		hal->ah_cw_max = AR5K_TUNE_CWMAX_XR;		hal->ah_aifs = AR5K_TUNE_AIFS_XR;	} else if (IEEE80211_IS_CHAN_B(channel)) {		hal->ah_cw_min = AR5K_TUNE_CWMIN_11B;		hal->ah_cw_max = AR5K_TUNE_CWMAX_11B;		hal->ah_aifs = AR5K_TUNE_AIFS_11B;	} else {		hal->ah_cw_min = AR5K_TUNE_CWMIN;		hal->ah_cw_max = AR5K_TUNE_CWMAX;		hal->ah_aifs = AR5K_TUNE_AIFS;	}	/*	 * Set retry limits	 */	if (hal->ah_software_retry == AH_TRUE) {		/* XXX Need to test this */		retry_lg = hal->ah_limit_tx_retries;		retry_sh = retry_lg =		    retry_lg > AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY ?		    AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY : retry_lg;	} else {		retry_lg = AR5K_INIT_LG_RETRY;		retry_sh = AR5K_INIT_SH_RETRY;	}	AR5K_REG_WRITE(AR5K_AR5212_DCU_RETRY_LMT(queue),	    AR5K_REG_SM(AR5K_INIT_SLG_RETRY,		AR5K_AR5212_DCU_RETRY_LMT_SLG_RETRY)	    | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,		AR5K_AR5212_DCU_RETRY_LMT_SSH_RETRY)	    | AR5K_REG_SM(retry_lg, AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY)	    | AR5K_REG_SM(retry_sh, AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY));	/*	 * Set initial content window (cw_min/cw_max)	 */	cw_min = 1;	while (cw_min < hal->ah_cw_min)		cw_min = (cw_min << 1) | 1;	cw_min = tq->tqi_cw_min < 0 ?	    (cw_min >> (-tq->tqi_cw_min)) :	    ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);	cw_max = tq->tqi_cw_max < 0 ?	    (cw_max >> (-tq->tqi_cw_max)) :	    ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);	AR5K_REG_WRITE(AR5K_AR5212_DCU_LCL_IFS(queue),	    AR5K_REG_SM(cw_min, AR5K_AR5212_DCU_LCL_IFS_CW_MIN) |	    AR5K_REG_SM(cw_max, AR5K_AR5212_DCU_LCL_IFS_CW_MAX) |	    AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs,	    AR5K_AR5212_DCU_LCL_IFS_AIFS));	/*	 * Set misc registers	 */	AR5K_REG_WRITE(AR5K_AR5212_QCU_MISC(queue),	    AR5K_AR5212_QCU_MISC_DCU_EARLY);	if (tq->tqi_cbr_period) {		AR5K_REG_WRITE(AR5K_AR5212_QCU_CBRCFG(queue),		    AR5K_REG_SM(tq->tqi_cbr_period,		    AR5K_AR5212_QCU_CBRCFG_INTVAL) |		    AR5K_REG_SM(tq->tqi_cbr_overflow_limit,		    AR5K_AR5212_QCU_CBRCFG_ORN_THRES));		AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue),		    AR5K_AR5212_QCU_MISC_FRSHED_CBR);		if (tq->tqi_cbr_overflow_limit)			AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue),			    AR5K_AR5212_QCU_MISC_CBR_THRES_ENABLE);	}	if (tq->tqi_ready_time) {		AR5K_REG_WRITE(AR5K_AR5212_QCU_RDYTIMECFG(queue),		    AR5K_REG_SM(tq->tqi_ready_time,		    AR5K_AR5212_QCU_RDYTIMECFG_INTVAL) |		    AR5K_AR5212_QCU_RDYTIMECFG_ENABLE);	}	if (tq->tqi_burst_time) {		AR5K_REG_WRITE(AR5K_AR5212_DCU_CHAN_TIME(queue),		    AR5K_REG_SM(tq->tqi_burst_time,		    AR5K_AR5212_DCU_CHAN_TIME_DUR) |		    AR5K_AR5212_DCU_CHAN_TIME_ENABLE);		if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) {			AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue),			    AR5K_AR5212_QCU_MISC_TXE);		}	}	if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) {		AR5K_REG_WRITE(AR5K_AR5212_DCU_MISC(queue),		    AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS);	}	if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {		AR5K_REG_WRITE(AR5K_AR5212_DCU_MISC(queue),		    AR5K_AR5212_DCU_MISC_BACKOFF_FRAG);	}	/*	 * Set registers by queue type	 */	switch (tq->tqi_type) {	case HAL_TX_QUEUE_BEACON:		AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue),		    AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT |		    AR5K_AR5212_QCU_MISC_CBREXP_BCN |		    AR5K_AR5212_QCU_MISC_BCN_ENABLE);		AR5K_REG_ENABLE_BITS(AR5K_AR5212_DCU_MISC(queue),		    (AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL <<		    AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL) |		    AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS |		    AR5K_AR5212_DCU_MISC_BCN_ENABLE);		AR5K_REG_WRITE(AR5K_AR5212_QCU_RDYTIMECFG(queue),		    ((AR5K_TUNE_BEACON_INTERVAL -		    (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) -		    AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |		    AR5K_AR5212_QCU_RDYTIMECFG_ENABLE);		break;	case HAL_TX_QUEUE_CAB:		AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue),		    AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT |		    AR5K_AR5212_QCU_MISC_CBREXP |		    AR5K_AR5212_QCU_MISC_CBREXP_BCN);		AR5K_REG_ENABLE_BITS(AR5K_AR5212_DCU_MISC(queue),		    (AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL <<		    AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL));		break;	case HAL_TX_QUEUE_PSPOLL:		AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue),		    AR5K_AR5212_QCU_MISC_CBREXP);		break;	case HAL_TX_QUEUE_DATA:	default:		break;	}	/*	 * Enable tx queue in the secondary interrupt mask registers	 */	AR5K_REG_WRITE(AR5K_AR5212_SIMR0,	    AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXOK) |	    AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXDESC));	AR5K_REG_WRITE(AR5K_AR5212_SIMR1,	    AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR1_QCU_TXERR));	AR5K_REG_WRITE(AR5K_AR5212_SIMR2,	    AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR2_QCU_TXURN));	return (AH_TRUE);}