prev_op = sh_insn_info (prev_insn);
if (dsp && (prev_insn & 0xfc00) == 0xf800) continue;   if (dsp && i - 2 > start) { unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);  if ((pprev_insn & 0xfc00) == 0xf800) prev_op = NULL; else prev_op = sh_insn_info (prev_insn); } else prev_op = sh_insn_info (prev_insn);
_bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,			 plabel, label_end, start, stop, pswapped)     bfd *abfd;     asection *sec;     bfd_byte *contents;     boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));     PTR relocs;     bfd_vma **plabel;     bfd_vma *label_end;     bfd_vma start;     bfd_vma stop;     boolean *pswapped;{  bfd_vma i;  /* Instructions should be aligned on 2 byte boundaries.  */  if ((start & 1) == 1)    ++start;  /* Now look through the unaligned addresses.  */  i = start;  if ((i & 2) == 0)    i += 2;  for (; i < stop; i += 4)    {      unsigned int insn;      const struct sh_opcode *op;      unsigned int prev_insn = 0;      const struct sh_opcode *prev_op = NULL;      insn = bfd_get_16 (abfd, contents + i);      op = sh_insn_info (insn);      if (op == NULL	  || (op->flags & (LOAD | STORE)) == 0)	continue;      /* This is a load or store which is not on a four byte boundary.  */      while (*plabel < label_end && **plabel < i)	++*plabel;      if (i > start)	{	  prev_insn = bfd_get_16 (abfd, contents + i - 2);	  prev_op = sh_insn_info (prev_insn);	  /* If the load/store instruction is in a delay slot, we	     can't swap.  */	  if (prev_op == NULL	      || (prev_op->flags & DELAY) != 0)	    continue;	}      if (i > start	  && (*plabel >= label_end || **plabel != i)	  && prev_op != NULL	  && (prev_op->flags & (LOAD | STORE)) == 0	  && ! sh_insns_conflict (prev_insn, prev_op, insn, op))	{	  boolean ok;	  /* The load/store instruction does not have a label, and	     there is a previous instruction; PREV_INSN is not	     itself a load/store instruction, and PREV_INSN and	     INSN do not conflict.  */	  ok = true;	  if (i >= start + 4)	    {	      unsigned int prev2_insn;	      const struct sh_opcode *prev2_op;	      prev2_insn = bfd_get_16 (abfd, contents + i - 4);	      prev2_op = sh_insn_info (prev2_insn);	      /* If the instruction before PREV_INSN has a delay		 slot--that is, PREV_INSN is in a delay slot--we		 can not swap.  */	      if (prev2_op == NULL		  || (prev2_op->flags & DELAY) != 0)		ok = false;	      /* If the instruction before PREV_INSN is a load,		 and it sets a register which INSN uses, then		 putting INSN immediately after PREV_INSN will		 cause a pipeline bubble, so there is no point to		 making the swap.  */	      if (ok		  && (prev2_op->flags & LOAD) != 0		  && sh_load_use (prev2_insn, prev2_op, insn, op))		ok = false;	    }	  if (ok)	    {	      if (! (*swap) (abfd, sec, relocs, contents, i - 2))		return false;	      *pswapped = true;	      continue;	    }	}      while (*plabel < label_end && **plabel < i + 2)	++*plabel;      if (i + 2 < stop	  && (*plabel >= label_end || **plabel != i + 2))	{	  unsigned int next_insn;	  const struct sh_opcode *next_op;	  /* There is an instruction after the load/store	     instruction, and it does not have a label.  */	  next_insn = bfd_get_16 (abfd, contents + i + 2);	  next_op = sh_insn_info (next_insn);	  if (next_op != NULL	      && (next_op->flags & (LOAD | STORE)) == 0	      && ! sh_insns_conflict (insn, op, next_insn, next_op))	    {	      boolean ok;	      /* NEXT_INSN is not itself a load/store instruction,		 and it does not conflict with INSN.  */	      ok = true;	      /* If PREV_INSN is a load, and it sets a register		 which NEXT_INSN uses, then putting NEXT_INSN		 immediately after PREV_INSN will cause a pipeline		 bubble, so there is no reason to make this swap.  */	      if (prev_op != NULL		  && (prev_op->flags & LOAD) != 0		  && sh_load_use (prev_insn, prev_op, next_insn, next_op))		ok = false;	      /* If INSN is a load, and it sets a register which		 the insn after NEXT_INSN uses, then doing the		 swap will cause a pipeline bubble, so there is no		 reason to make the swap.  However, if the insn		 after NEXT_INSN is itself a load or store		 instruction, then it is misaligned, so		 optimistically hope that it will be swapped		 itself, and just live with the pipeline bubble if		 it isn't.  */	      if (ok		  && i + 4 < stop		  && (op->flags & LOAD) != 0)		{		  unsigned int next2_insn;		  const struct sh_opcode *next2_op;		  next2_insn = bfd_get_16 (abfd, contents + i + 4);		  next2_op = sh_insn_info (next2_insn);		  if ((next2_op->flags & (LOAD | STORE)) == 0		      && sh_load_use (insn, op, next2_insn, next2_op))		    ok = false;		}	      if (ok)		{		  if (! (*swap) (abfd, sec, relocs, contents, i))		    return false;		  *pswapped = true;		  continue;		}	    }	}    }  return true;}