desc->ds_us.tx.ts_tstamp =
desc->ds_us.tx.ts_rate =
ar5k_ar5210_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc){	struct ar5k_ar5210_tx_status *tx_status;	struct ar5k_ar5210_tx_desc *tx_desc;	tx_desc = (struct ar5k_ar5210_tx_desc*)&desc->ds_ctl0;	tx_status = (struct ar5k_ar5210_tx_status*)&desc->ds_hw[0];	/* No frame has been send or error */	if ((tx_status->tx_status_1 & AR5K_AR5210_DESC_TX_STATUS1_DONE) == 0)		return (HAL_EINPROGRESS);	/*	 * Get descriptor status	 */	desc->ds_us.tx.ts_tstamp =	    AR5K_REG_MS(tx_status->tx_status_0,	    AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP);	desc->ds_us.tx.ts_shortretry =	    AR5K_REG_MS(tx_status->tx_status_0,	    AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT);	desc->ds_us.tx.ts_longretry =	    AR5K_REG_MS(tx_status->tx_status_0,	    AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT);	desc->ds_us.tx.ts_seqnum =	    AR5K_REG_MS(tx_status->tx_status_1,	    AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM);	desc->ds_us.tx.ts_rssi =	    AR5K_REG_MS(tx_status->tx_status_1,	    AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH);	desc->ds_us.tx.ts_antenna = 1;	desc->ds_us.tx.ts_status = 0;	desc->ds_us.tx.ts_tstamp =	    AR5K_REG_MS(tx_desc->tx_control_0,	    AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE);	if ((tx_status->tx_status_0 &	    AR5K_AR5210_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) {		if (tx_status->tx_status_0 &		    AR5K_AR5210_DESC_TX_STATUS0_EXCESSIVE_RETRIES)			desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY;		if (tx_status->tx_status_0 &		    AR5K_AR5210_DESC_TX_STATUS0_FIFO_UNDERRUN)			desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO;		if (tx_status->tx_status_0 &		    AR5K_AR5210_DESC_TX_STATUS0_FILTERED)			desc->ds_us.tx.ts_status |= HAL_TXERR_FILT;	}	return (HAL_OK);}