struct siop_softc *sc;
struct siop_common_softc *sc;
siop_pci_reset(sc)	struct siop_softc *sc;{	int dmode;	dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE);	if (sc->features & SF_PCI_RL)		dmode |= DMODE_ERL;	if (sc->features & SF_PCI_RM)		dmode |= DMODE_ERMP;	if (sc->features & SF_PCI_BOF)		dmode |= DMODE_BOF;	if (sc->features & SF_PCI_CLS)		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL,		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) |		    DCNTL_CLSE);	if (sc->features & SF_PCI_WRI)		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) |		    CTEST3_WRIE);	if (sc->maxburst) {		int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh,		    SIOP_CTEST5);		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) &		    ~CTEST4_BDIS);		dmode &= ~DMODE_BL_MASK;		dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK;		ctest5 &= ~CTEST5_BBCK;		ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK;		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5);	} else if ((sc->features & SF_CHIP_C10) == 0) {		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) |		    CTEST4_BDIS);	}	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode);}