pio:		sis_tim |= sis_pio_act[drvp->PIO_mode] << SIS_TIM_ACT_OFF(drive); sis_tim |= sis_pio_rec[drvp->PIO_mode] << SIS_TIM_REC_OFF(drive);
pio:		switch (sc->sis_type) { case SIS_TYPE_NOUDMA: case SIS_TYPE_66: case SIS_TYPE_100OLD: sis_tim |= sis_pio_act[drvp->PIO_mode] << SIS_TIM66_ACT_OFF(drive); sis_tim |= sis_pio_rec[drvp->PIO_mode] << SIS_TIM66_REC_OFF(drive); break; case SIS_TYPE_100NEW: case SIS_TYPE_133OLD: sis_tim |= sis_pio_act[drvp->PIO_mode] << SIS_TIM100_ACT_OFF(drive); sis_tim |= sis_pio_rec[drvp->PIO_mode] << SIS_TIM100_REC_OFF(drive); break; default: printf("unknown SiS IDE type %d\n", sc->sis_type); }
sis_setup_channel(chp)	struct channel_softc *chp;{	struct ata_drive_datas *drvp;	int drive;	u_int32_t sis_tim;	u_int32_t idedma_ctl;	struct pciide_channel *cp = (struct pciide_channel*)chp;	struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;	WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for "	    "channel %d 0x%x\n", chp->channel, 	    pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))),	    DEBUG_PROBE);	sis_tim = 0;	idedma_ctl = 0;	/* setup DMA if needed */	pciide_channel_dma_setup(cp);	for (drive = 0; drive < 2; drive++) {		drvp = &chp->ch_drive[drive];		/* If no drive, skip */		if ((drvp->drive_flags & DRIVE) == 0)			continue;		/* add timing values, setup DMA if needed */		if ((drvp->drive_flags & DRIVE_DMA) == 0 &&		    (drvp->drive_flags & DRIVE_UDMA) == 0)			goto pio;		if (drvp->drive_flags & DRIVE_UDMA) {			/* use Ultra/DMA */			drvp->drive_flags &= ~DRIVE_DMA;			sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 			    SIS_TIM_UDMA_TIME_OFF(drive);			sis_tim |= SIS_TIM_UDMA_EN(drive);		} else {			/*			 * use Multiword DMA			 * Timings will be used for both PIO and DMA,			 * so adjust DMA mode if needed			 */			if (drvp->PIO_mode > (drvp->DMA_mode + 2))				drvp->PIO_mode = drvp->DMA_mode + 2;			if (drvp->DMA_mode + 2 > (drvp->PIO_mode))				drvp->DMA_mode = (drvp->PIO_mode > 2) ?				    drvp->PIO_mode - 2 : 0;			if (drvp->DMA_mode == 0)				drvp->PIO_mode = 0;		}		idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);pio:		sis_tim |= sis_pio_act[drvp->PIO_mode] <<		    SIS_TIM_ACT_OFF(drive);		sis_tim |= sis_pio_rec[drvp->PIO_mode] <<		    SIS_TIM_REC_OFF(drive);	}	WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for "	    "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE);	pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim);	if (idedma_ctl != 0) {		/* Add software bits in status register */		bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,		    IDEDMA_CTL(chp->channel), idedma_ctl);	}	pciide_print_modes(cp);}