* If this is an Intel 21143 and we're not using the * MII port, program the LED control pins so we get * link and activity indications. */ if (sc->dc_flags & DC_TULIP_LEDS) { CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); CSR_WRITE_4(sc, DC_WATCHDOG, 0); }
void dc_init(xsc)	void			*xsc;{	struct dc_softc		*sc = xsc;	struct ifnet		*ifp = &sc->arpcom.ac_if;	struct mii_data		*mii;	int			s;	s = splimp();	mii = &sc->sc_mii;	/*	 * Cancel pending I/O and free all RX/TX buffers.	 */	dc_stop(sc);	dc_reset(sc);	/*	 * Set cache alignment and burst length.	 */	if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))		CSR_WRITE_4(sc, DC_BUSCTL, 0);	else		CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);	if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {		DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);	} else {		DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);	}	if (sc->dc_flags & DC_TX_POLL)		DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);	switch(sc->dc_cachesize) {	case 32:		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);		break;	case 16:		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);		break; 	case 8:		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);		break;  	case 0:	default:		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);		break;	}	if (sc->dc_flags & DC_TX_STORENFWD)		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);	else {		if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) {			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);		} else {			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);			DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);		}	}	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);	if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {		/*		 * The app notes for the 98713 and 98715A say that		 * in order to have the chips operate properly, a magic		 * number must be written to CSR16. Macronix does not		 * document the meaning of these bits so there's no way		 * to know exactly what they do. The 98713 has a magic		 * number all its own; the rest all use a different one.		 */		DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);		if (sc->dc_type == DC_TYPE_98713)			DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);		else			DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);	}	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);	DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES);	/* Init circular RX list. */	if (dc_list_rx_init(sc) == ENOBUFS) {		printf("dc%d: initialization failed: no "		    "memory for rx buffers\n", sc->dc_unit);		dc_stop(sc);		(void)splx(s);		return;	}	/*	 * Init tx descriptors.	 */	dc_list_tx_init(sc);	/*	 * Load the address of the RX list.	 */	CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));	CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));	/*	 * Enable interrupts.	 */	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);	CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);	/* Enable transmitter. */	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);	/*	 * Load the RX/multicast filter. We do this sort of late	 * because the filter programming scheme on the 21143 and	 * some clones requires DMAing a setup frame via the TX	 * engine, and we need the transmitter enabled for that.	 */	dc_setfilt(sc);	/* Enable receiver. */	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);	CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);	mii_mediachg(mii);	dc_setcfg(sc, sc->dc_if_media);	ifp->if_flags |= IFF_RUNNING;	ifp->if_flags &= ~IFF_OACTIVE;	(void)splx(s);	timeout_set(&sc->dc_tick_tmo, dc_tick, sc);	if (sc->dc_flags & DC_21143_NWAY)		timeout_add(&sc->dc_tick_tmo, hz / 10);	else		timeout_add(&sc->dc_tick_tmo, hz);	return;}