printf("WARNING: PDC_BTLB error %d", error);
printf("WARNING: PDC_BTLB error %d\n", error);
hppa_init(start)	paddr_t start;{	struct pdc_model pdc_model PDC_ALIGNMENT;	extern int kernel_text;	vaddr_t v, v1;	int error, cpu_features = 0;	pdc_init();	/* init PDC iface, so we can call em easy */	cpu_hzticks = (PAGE0->mem_10msec * 100) / hz;	delay_init();	/* calculate cpu clock ratio */	/* cache parameters */	if ((error = pdc_call((iodcio_t)pdc, 0, PDC_CACHE, PDC_CACHE_DFLT,	    &pdc_cache)) < 0) {#ifdef DEBUG		printf("WARNING: PDC_CACHE error %d\n", error);#endif	}	dcache_line_mask = pdc_cache.dc_conf.cc_line * 16 - 1;	dcache_stride = pdc_cache.dc_stride;	icache_line_mask = pdc_cache.ic_conf.cc_line * 16 - 1;	icache_stride = pdc_cache.ic_stride;	/* cache coherence params (pbably available for 8k only) */	error = pdc_call((iodcio_t)pdc, 0, PDC_CACHE, PDC_CACHE_SETCS,	    &pdc_coherence, 1, 1, 1, 1);#ifdef DEBUG	printf ("PDC_CACHE_SETCS: %d, %d, %d, %d (%d)\n",	    pdc_coherence.ia_cst, pdc_coherence.da_cst,	    pdc_coherence.ita_cst, pdc_coherence.dta_cst, error);#endif	error = pdc_call((iodcio_t)pdc, 0, PDC_CACHE, PDC_CACHE_GETSPIDB,	    &pdc_spidbits, 0, 0, 0, 0);	printf("SPID bits: 0x%x, error = %d\n", pdc_spidbits.spidbits, error);	/* setup hpmc handler */	{		extern u_int hpmc_v[];	/* from locore.s */		register u_int *p = hpmc_v;		if (pdc_call((iodcio_t)pdc, 0, PDC_INSTR, PDC_INSTR_DFLT, p))			*p = 0x08000240;		p[6] = (u_int)&hpmc_dump;		p[7] = 32;		p[5] = -(p[0] + p[1] + p[2] + p[3] + p[4] + p[6] + p[7]);	}	{		extern u_int hppa_toc[], hppa_toc_end[];		register u_int cksum, *p;		for (cksum = 0, p = hppa_toc; p < hppa_toc_end; p++)			cksum += *p;		*p = cksum;		PAGE0->ivec_toc = (int (*)(void))hppa_toc;		PAGE0->ivec_toclen = (hppa_toc_end - hppa_toc + 1) * 4;	}	{		extern u_int hppa_pfr[], hppa_pfr_end[];		register u_int cksum, *p;		for (cksum = 0, p = hppa_pfr; p < hppa_pfr_end; p++)			cksum += *p;		*p = cksum;		PAGE0->ivec_mempf = (int (*)(void))hppa_pfr;		PAGE0->ivec_mempflen = (hppa_pfr_end - hppa_pfr + 1) * 4;	}	/* may the scientific guessing begin */	cpu_features = 0;	/* identify system type */	if ((error = pdc_call((iodcio_t)pdc, 0, PDC_MODEL, PDC_MODEL_INFO,	    &pdc_model)) < 0) {#ifdef DEBUG		printf("WARNING: PDC_MODEL error %d\n", error);#endif		pdc_model.hvers = 0;	}	/* BTLB params */	if ((error = pdc_call((iodcio_t)pdc, 0, PDC_BLOCK_TLB,	    PDC_BTLB_DEFAULT, &pdc_btlb)) < 0) {#ifdef DEBUG		printf("WARNING: PDC_BTLB error %d", error);#endif	} else {#ifdef BTLBDEBUG		printf("btlb info: minsz=%d, maxsz=%d\n",		    pdc_btlb.min_size, pdc_btlb.max_size);		printf("btlb fixed: i=%d, d=%d, c=%d\n",		    pdc_btlb.finfo.num_i,		    pdc_btlb.finfo.num_d,		    pdc_btlb.finfo.num_c);		printf("btlb varbl: i=%d, d=%d, c=%d\n",		    pdc_btlb.vinfo.num_i,		    pdc_btlb.vinfo.num_d,		    pdc_btlb.vinfo.num_c);#endif /* BTLBDEBUG */		/* purge TLBs and caches */		if (pdc_call((iodcio_t)pdc, 0, PDC_BLOCK_TLB,		    PDC_BTLB_PURGE_ALL) < 0)			printf("WARNING: BTLB purge failed\n");		if (pdc_btlb.finfo.num_c)			cpu_features |= HPPA_FTRS_BTLBU;	}	ptlball();	fcacheall();	totalphysmem = btoc(PAGE0->imm_max_mem);	resvmem = btoc(((vaddr_t)&kernel_text));	avail_end = ctob(totalphysmem);#if defined(HP7100LC_CPU) || defined(HP7300LC_CPU)	if (!pdc_call((iodcio_t)pdc, 0, PDC_TLB, PDC_TLB_INFO, &pdc_hwtlb) &&	    pdc_hwtlb.min_size && pdc_hwtlb.max_size)		cpu_features |= HPPA_FTRS_HVT;	else {		printf("WARNING: no HPT support, fine!\n");		pmap_hptsize = 0;	}#endif	/*	 * Deal w/ CPU now	 */	{		const struct hppa_cpu_typed *p;		for (p = cpu_types;		    p->arch && p->features != cpu_features; p++);		if (!p->arch) {			printf("WARNING: UNKNOWN CPU TYPE; GOOD LUCK (%x)\n",			    cpu_features);			p = cpu_types;		}		{			/*			 * Ptrs to various tlb handlers, to be filled			 * based on cpu features.			 * from locore.S			 */			extern u_int trap_ep_T_TLB_DIRTY[];			extern u_int trap_ep_T_DTLBMISS[];			extern u_int trap_ep_T_DTLBMISSNA[];			extern u_int trap_ep_T_ITLBMISS[];			extern u_int trap_ep_T_ITLBMISSNA[];			cpu_type = p->type;			cpu_typename = p->name;			cpu_ibtlb_ins = p->ibtlbins;			cpu_dbtlb_ins = p->dbtlbins;			cpu_hpt_init = p->hptinit;			cpu_desidhash = p->desidhash;#define	LDILDO(t,f) ((t)[0] = (f)[0], (t)[1] = (f)[1])			LDILDO(trap_ep_T_TLB_DIRTY , p->tlbdh);			LDILDO(trap_ep_T_DTLBMISS  , p->dtlbh);			LDILDO(trap_ep_T_DTLBMISSNA, p->dtlbnah);			LDILDO(trap_ep_T_ITLBMISS  , p->itlbh);			LDILDO(trap_ep_T_ITLBMISSNA, p->itlbnah);#undef LDILDO		}	}	{		const char *p, *q;		char buf[32];		int lev;		lev = 0xa + (*cpu_desidhash)();		cpu_hvers = pdc_model.hvers >> 4;		if (!cpu_hvers) {			p = "(UNKNOWN)";			q = lev == 0xa? "1.0" : "1.1";		} else {			p = hppa_mod_info(HPPA_TYPE_BOARD, cpu_hvers);			if (!p) {				snprintf(buf, sizeof buf, "(UNKNOWN 0x%x)",				    cpu_hvers);				p = buf;			}			switch (pdc_model.arch_rev) {			default:			case 0:				q = "1.0";#ifdef COMPAT_HPUX				cpu_model_hpux = HPUX_SYSCONF_CPUPA10;#endif				break;			case 4:				q = "1.1";#ifdef COMPAT_HPUX				cpu_model_hpux = HPUX_SYSCONF_CPUPA11;#endif				/* this one is just a 100MHz pcxl */				if (lev == 0x10)					lev = 0xc;				/* this one is a pcxl2 */				if (lev == 0x16)					lev = 0xe;				break;			case 8:				q = "2.0";#ifdef COMPAT_HPUX				cpu_model_hpux = HPUX_SYSCONF_CPUPA20;#endif				break;			}		}		snprintf(cpu_model, sizeof cpu_model,		    "HP 9000/%s PA-RISC %s%x", p, q, lev);	}	/* we hope this won't fail */	hppa_ex = extent_create("mem", 0x0, 0xffffffff, M_DEVBUF,	    (caddr_t)mem_ex_storage, sizeof(mem_ex_storage),	    EX_NOCOALESCE|EX_NOWAIT);	if (extent_alloc_region(hppa_ex, 0, (vaddr_t)PAGE0->imm_max_mem,	    EX_NOWAIT))		panic("cannot reserve main memory");	/*	 * Now allocate kernel dynamic variables	 */	/* buffer cache parameters */	if (bufpages == 0)		bufpages = totalphysmem / 100 *		    (totalphysmem <= 0x1000? 5 : bufcachepercent);	if (nbuf == 0)		nbuf = bufpages < 16? 16 : bufpages;	/* Restrict to at most 70% filled kvm */	if (nbuf * MAXBSIZE >	    (VM_MAX_KERNEL_ADDRESS-VM_MIN_KERNEL_ADDRESS) * 7 / 10)		nbuf = (VM_MAX_KERNEL_ADDRESS-VM_MIN_KERNEL_ADDRESS) /		    MAXBSIZE * 7 / 10;	/* More buffer pages than fits into the buffers is senseless. */	if (bufpages > nbuf * MAXBSIZE / PAGE_SIZE)		bufpages = nbuf * MAXBSIZE / PAGE_SIZE;	v1 = v = hppa_round_page(start);#define valloc(name, type, num) (name) = (type *)v; v = (vaddr_t)((name)+(num))	valloc(buf, struct buf, nbuf);#ifdef SYSVMSG	valloc(msgpool, char, msginfo.msgmax);	valloc(msgmaps, struct msgmap, msginfo.msgseg);	valloc(msghdrs, struct msg, msginfo.msgtql);	valloc(msqids, struct msqid_ds, msginfo.msgmni);#endif#undef valloc	v = hppa_round_page(v);	bzero ((void *)v1, (v - v1));	msgbufp = (struct msgbuf *)v;	v += round_page(MSGBUFSIZE);	bzero(msgbufp, MSGBUFSIZE);	/* sets physmem */	pmap_bootstrap(v);	msgbufmapped = 1;	initmsgbuf((caddr_t)msgbufp, round_page(MSGBUFSIZE));	/* locate coprocessors and SFUs */	if ((error = pdc_call((iodcio_t)pdc, 0, PDC_COPROC, PDC_COPROC_DFLT,	    &pdc_coproc)) < 0)		printf("WARNING: PDC_COPROC error %d\n", error);	else {		extern u_int fpu_enable;#ifdef DEBUG		printf("pdc_coproc: %x, %x\n", pdc_coproc.ccr_enable,		    pdc_coproc.ccr_present);#endif		fpu_enable = pdc_coproc.ccr_enable & CCR_MASK;	}	/* they say PDC_COPROC might turn fault light on */	pdc_call((iodcio_t)pdc, 0, PDC_CHASSIS, PDC_CHASSIS_DISP,	    PDC_OSTAT(PDC_OSTAT_RUN) | 0xCEC0);#ifdef DDB	ddb_init();#endif	fcacheall();}