printf("%s: primary channel %s to ", sc->sc_wdcdev.sc_dev.dv_xname,
printf(", %s %s to ", PCIIDE_CHANNEL_NAME(0),
cy693_chip_map(sc, pa)	struct pciide_softc *sc;	struct pci_attach_args *pa;{       	struct pciide_channel *cp;	pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc,				    sc->sc_tag, PCI_CLASS_REG));	bus_size_t cmdsize, ctlsize;	if (pciide_chipen(sc, pa) == 0)		return;	/*	 * this chip has 2 PCI IDE functions, one for primary and one for	 * secondary. So we need to call pciide_mapregs_compat() with	 * the real channel	 */	if (pa->pa_function == 1) {		sc->sc_cy_compatchan = 0;	} else if (pa->pa_function == 2) {		sc->sc_cy_compatchan = 1;	} else {		printf(": unexpected PCI function %d\n", pa->pa_function);		return;	}	if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) {		printf(": DMA");		pciide_mapreg_dma(sc, pa);	} else {		printf(": no DMA");		sc->sc_dma_ok = 0;	}	sc->sc_cy_handle = cy82c693_init(pa->pa_iot);	if (sc->sc_cy_handle == NULL) {		printf(", (unable to map ctl registers)");		sc->sc_dma_ok = 0;	}	if (sc->sc_dma_ok)		sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA;	sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |	    WDC_CAPABILITY_MODE;	sc->sc_wdcdev.PIO_cap = 4;	sc->sc_wdcdev.DMA_cap = 2;	sc->sc_wdcdev.set_modes = cy693_setup_channel;	sc->sc_wdcdev.channels = sc->wdc_chanarray;	sc->sc_wdcdev.nchannels = 1;	/* Only one channel for this chip; if we are here it's enabled */	cp = &sc->pciide_channels[0];	sc->wdc_chanarray[0] = &cp->wdc_channel;	cp->name = PCIIDE_CHANNEL_NAME(0);	cp->wdc_channel.channel = 0;	cp->wdc_channel.wdc = &sc->sc_wdcdev;	cp->wdc_channel.ch_queue =	    malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT);	if (cp->wdc_channel.ch_queue == NULL) {		printf(": cannot allocate memory for command queue\n");		return;	}	printf("%s: primary channel %s to ",	    sc->sc_wdcdev.sc_dev.dv_xname,	    (interface & PCIIDE_INTERFACE_SETTABLE(0)) ?	    "configured" : "wired");	if (interface & PCIIDE_INTERFACE_PCI(0)) {		printf("native-PCI");		cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize,		    pciide_pci_intr);	} else {		printf("compatibility");		cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan,		    &cmdsize, &ctlsize);	}        printf(" mode\n");	cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot;	cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh;	wdcattach(&cp->wdc_channel);	if (pciide_chan_candisable(cp)) {		pci_conf_write(sc->sc_pc, sc->sc_tag,		    PCI_COMMAND_STATUS_REG, 0);	}	pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface);	if (cp->hw_ok == 0)		return;	WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n",	    pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE);	cy693_setup_channel(&cp->wdc_channel);	WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n",	    pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE);}