* Avoid violating PCI spec on certain chip revs.
* Disable memory write invalidate.  Apparently it is not supported * properly by these devices.
bge_chipinit(sc)	struct bge_softc *sc;{	u_int32_t		cachesize;	int			i;	struct pci_attach_args	*pa = &(sc->bge_pa);#ifdef BGE_CHECKSUM	sc->arpcom.ac_if.if_capabilities =	  IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;#endif	/* Set endianness before we access any non-PCI registers. */#if BYTE_ORDER == BIG_ENDIAN	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,	    BGE_BIGENDIAN_INIT);#else	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,	    BGE_LITTLEENDIAN_INIT);#endif	/*	 * Check the 'ROM failed' bit on the RX CPU to see if	 * self-tests passed.	 */	if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {		printf("%s: RX CPU self-diagnostics failed!\n",		    sc->bge_dev.dv_xname);		return(ENODEV);	}	/* Clear the MAC control register */	CSR_WRITE_4(sc, BGE_MAC_MODE, 0);	/*	 * Clear the MAC statistics block in the NIC's	 * internal memory.	 */	for (i = BGE_STATS_BLOCK;	    i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))		BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);	for (i = BGE_STATUS_BLOCK;	    i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))		BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);	/* Set up the PCI DMA control register. */	pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,	    BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F);	/*	 * Set up general mode register.	 */#ifndef BGE_CHECKSUM	CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|		    BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|		    BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|		    BGE_MODECTL_NO_RX_CRC);#else	CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|		    BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|		    BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|		    BGE_MODECTL_NO_RX_CRC/*		    |BGE_MODECTL_TX_NO_PHDR_CSUM| *//*		    BGE_MODECTL_RX_NO_PHDR_CSUM */);#endif	/* Get cache line size. */	cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ);	/*	 * Avoid violating PCI spec on certain chip revs.	 */	if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) &	    PCIM_CMD_MWIEN) {		switch(cachesize) {		case 1:			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,				   BGE_PCI_WRITE_BNDRY_16BYTES);			break;		case 2:			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,				   BGE_PCI_WRITE_BNDRY_32BYTES);			break;		case 4:			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,				   BGE_PCI_WRITE_BNDRY_64BYTES);			break;		case 8:			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,				   BGE_PCI_WRITE_BNDRY_128BYTES);			break;		case 16:			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,				   BGE_PCI_WRITE_BNDRY_256BYTES);			break;		case 32:			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,				   BGE_PCI_WRITE_BNDRY_512BYTES);			break;		case 64:			PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,				   BGE_PCI_WRITE_BNDRY_1024BYTES);			break;		default:		/* Disable PCI memory write and invalidate. */#if 0			if (bootverbose)				printf("%s: cache line size %d not "				    "supported; disabling PCI MWI\n",				    sc->bge_dev.dv_xname, cachesize);#endif			PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD,			    PCIM_CMD_MWIEN);			break;		}	}#ifdef __brokenalpha__	/*	 * Must insure that we do not cross an 8K (bytes) boundary	 * for DMA reads.  Our highest limit is 1K bytes.  This is a	 * restriction on some ALPHA platforms with early revision	 * 21174 PCI chipsets, such as the AlphaPC 164lx	 */	PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4);#endif	/* Set the timer prescaler (always 66Mhz) */	CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);	return(0);}