: "=r" (pa) : "0" (pa) : "memory");
: "+r" (pa) :: "memory");
pmap_zero_page(pa)	register paddr_t pa;{	extern int dcache_line_mask;	/* register int psw; */	register paddr_t pe = pa + PAGE_SIZE;#ifdef PMAPDEBUG	if (pmapdebug & PDB_FOLLOW)		printf("pmap_zero_page(%x)\n", pa);#endif	pmap_clear_pv(pa, NULL);	/* rsm(PSW_I,psw); */	while (pa < pe) {		__asm volatile("stwas,ma %%r0,4(%0)\n\t"			       : "=r" (pa) : "0" (pa) : "memory");		if (!(pa & dcache_line_mask))			__asm volatile("rsm %1, %%r0\n\t"				       "fdc %2(%0)\n\t"				       "ssm %1, %%r0"			    :: "r" (pa), "i" (PSW_D), "r" (-4) : "memory");	}	sync_caches();	/* mtsm(psw); */}