s = splimp();
s = splnet();
void ste_init(xsc)	void			*xsc;{	struct ste_softc	*sc = (struct ste_softc *)xsc;	struct ifnet		*ifp = &sc->arpcom.ac_if;	struct mii_data		*mii;	int			i, s;	s = splimp();	ste_stop(sc);	mii = &sc->sc_mii;	/* Init our MAC address */	for (i = 0; i < ETHER_ADDR_LEN; i++) {		CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);	}	/* Init RX list */	if (ste_init_rx_list(sc) == ENOBUFS) {		printf("%s: initialization failed: no "		    "memory for RX buffers\n", sc->sc_dev.dv_xname);		ste_stop(sc);		splx(s);		return;	}	/* Set RX polling interval */	CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);	/* Init TX descriptors */	ste_init_tx_list(sc);	/* Set the TX freethresh value */	CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, ETHER_MAX_DIX_LEN >> 8);	/* Set the TX start threshold for best performance. */	CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);	/* Set the TX reclaim threshold. */	CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (ETHER_MAX_DIX_LEN >> 4));	/* Set up the RX filter. */	CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);	/* If we want promiscuous mode, set the allframes bit. */	if (ifp->if_flags & IFF_PROMISC) {		STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);	} else {		STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);	}	/* Set capture broadcast bit to accept broadcast frames. */	if (ifp->if_flags & IFF_BROADCAST) {		STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);	} else {		STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);	}	ste_setmulti(sc);	/* Load the address of the RX list. */	STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);	ste_wait(sc);	CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,	    vtophys((vaddr_t)&sc->ste_ldata->ste_rx_list[0]));	STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);	STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);	/* Set TX polling interval (defer until we TX first packet) */	CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);	/* Load address of the TX list */	STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);	ste_wait(sc);	CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);	STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);	STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);	ste_wait(sc);	sc->ste_tx_prev=NULL;	/* Enable receiver and transmitter */	CSR_WRITE_2(sc, STE_MACCTL0, 0);	CSR_WRITE_2(sc, STE_MACCTL1, 0);	STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);	STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);	/* Enable stats counters. */	STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);	/* Enable interrupts. */	CSR_WRITE_2(sc, STE_ISR, 0xFFFF);	CSR_WRITE_2(sc, STE_IMR, STE_INTRS);	/* Accept VLAN length packets */	CSR_WRITE_2(sc, STE_MAX_FRAMELEN,	    ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);	ste_ifmedia_upd(ifp);	ifp->if_flags |= IFF_RUNNING;	ifp->if_flags &= ~IFF_OACTIVE;	splx(s);	timeout_set(&sc->sc_stats_tmo, ste_stats_update, sc);	timeout_add(&sc->sc_stats_tmo, hz);	return;}