s = splimp();
s = splnet();
int sis_mii_readreg(sc, frame)	struct sis_softc	*sc;	struct sis_mii_frame	*frame; 	{	int			i, ack, s; 	s = splimp(); 	/*	 * Set up frame for RX.	 */	frame->mii_stdelim = SIS_MII_STARTDELIM;	frame->mii_opcode = SIS_MII_READOP;	frame->mii_turnaround = 0;	frame->mii_data = 0; 		/* 	 * Turn on data xmit.	 */	SIO_SET(SIS_MII_DIR);	sis_mii_sync(sc); 	/*	 * Send command/address info.	 */	sis_mii_send(sc, frame->mii_stdelim, 2);	sis_mii_send(sc, frame->mii_opcode, 2);	sis_mii_send(sc, frame->mii_phyaddr, 5);	sis_mii_send(sc, frame->mii_regaddr, 5); 	/* Idle bit */	SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));	DELAY(1);	SIO_SET(SIS_MII_CLK);	DELAY(1); 	/* Turn off xmit. */	SIO_CLR(SIS_MII_DIR); 	/* Check for ack */	SIO_CLR(SIS_MII_CLK);	DELAY(1);	ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;	SIO_SET(SIS_MII_CLK);	DELAY(1); 	/*	 * Now try reading data bits. If the ack failed, we still	 * need to clock through 16 cycles to keep the PHY(s) in sync.	 */	if (ack) {		for(i = 0; i < 16; i++) {			SIO_CLR(SIS_MII_CLK);			DELAY(1);			SIO_SET(SIS_MII_CLK);			DELAY(1);		}		goto fail;	} 	for (i = 0x8000; i; i >>= 1) {		SIO_CLR(SIS_MII_CLK);		DELAY(1);		if (!ack) {			if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)				frame->mii_data |= i;			DELAY(1);		}		SIO_SET(SIS_MII_CLK);		DELAY(1);	}fail:	SIO_CLR(SIS_MII_CLK);	DELAY(1);	SIO_SET(SIS_MII_CLK);	DELAY(1);	splx(s);	if (ack)		return(1);	return(0);}