siop_resetbus(sc);
siop_resetbus(&sc->sc_c);
siop_attach(sc)	struct siop_softc *sc;{	int error, i;	bus_dma_segment_t seg;	int rseg;	/*	 * Allocate DMA-safe memory for the script and map it.	 */	if ((sc->features & SF_CHIP_RAM) == 0) {		error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 		    PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT);		if (error) {			printf("%s: unable to allocate script DMA memory, "			    "error = %d\n", sc->sc_dev.dv_xname, error);			return;		}		error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, PAGE_SIZE,		    (caddr_t *)&sc->sc_script, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);		if (error) {			printf("%s: unable to map script DMA memory, "			    "error = %d\n", sc->sc_dev.dv_xname, error);			return;		}		error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1,		    PAGE_SIZE, 0, BUS_DMA_NOWAIT, &sc->sc_scriptdma);		if (error) {			printf("%s: unable to create script DMA map, "			    "error = %d\n", sc->sc_dev.dv_xname, error);			return;		}		error = bus_dmamap_load(sc->sc_dmat, sc->sc_scriptdma,		    sc->sc_script, PAGE_SIZE, NULL, BUS_DMA_NOWAIT);		if (error) {			printf("%s: unable to load script DMA map, "			    "error = %d\n", sc->sc_dev.dv_xname, error);			return;		}		sc->sc_scriptaddr = sc->sc_scriptdma->dm_segs[0].ds_addr;		sc->ram_size = PAGE_SIZE;	}	TAILQ_INIT(&sc->free_list);	TAILQ_INIT(&sc->ready_list);	TAILQ_INIT(&sc->urgent_list);	TAILQ_INIT(&sc->cmds);	TAILQ_INIT(&sc->lunsw_list);	sc->sc_currschedslot = 0;#ifdef SIOP_DEBUG	printf("%s: script size = %d, PHY addr=0x%x, VIRT=%p\n",	    sc->sc_dev.dv_xname, (int)sizeof(siop_script),	    (u_int32_t)sc->sc_scriptaddr, sc->sc_script);#endif	/* Start with one page worth of commands */	siop_morecbd(sc);	/*	 * sc->sc_link is the template for all device sc_link's	 * for devices attached to this adapter. It is passed to	 * the upper layers in config_found().	 */	sc->sc_link.adapter_softc = sc;	sc->sc_link.openings = SIOP_OPENINGS;	sc->sc_link.adapter_buswidth =	    (sc->features & SF_BUS_WIDE) ? 16 : 8;	sc->sc_link.adapter_target = bus_space_read_1(sc->sc_rt,	    sc->sc_rh, SIOP_SCID);	if (sc->sc_link.adapter_target == 0 ||	    sc->sc_link.adapter_target >=	    sc->sc_link.adapter_buswidth)		sc->sc_link.adapter_target = SIOP_DEFAULT_TARGET;	sc->sc_link.adapter = &siop_adapter;	sc->sc_link.device = &siop_dev;	sc->sc_link.flags  = 0;	sc->sc_link.quirks = 0;	if ((sc->features & SF_BUS_WIDE) == 0)	  sc->sc_link.quirks |= SDEV_NOWIDE;	for (i = 0; i < 16; i++)		sc->targets[i] = NULL;	/* find min_dt_sync and min_st_sync for this chip */	sc->min_dt_sync = 0;	for (i = 0; i < sizeof(period_factor) / sizeof(period_factor[0]); i++)		if (period_factor[i].scf[sc->scf_index].dt_scf != 0) {			sc->min_dt_sync = period_factor[i].factor;			break;		}	sc->min_st_sync = 0;	for (i = 0; i < sizeof(period_factor) / sizeof(period_factor[0]); i++)		if (period_factor[i].scf[sc->scf_index].st_scf != 0) {			sc->min_st_sync = period_factor[i].factor;			break;		}	if (sc->min_st_sync == 0)		panic("%s: can't find minimum allowed sync period factor\n", sc->sc_dev.dv_xname);	/* Do a bus reset, so that devices fall back to narrow/async */	siop_resetbus(sc);	/*	 * siop_reset() will reset the chip, thus clearing pending interrupts	 */	siop_reset(sc);#ifdef DUMP_SCRIPT	siop_dump_script(sc);#endif	config_found((struct device*)sc, &sc->sc_link, scsiprint);}