if ((st & PDC262_STATE_80P(channel)) != 0 || (chp->ch_drive[0].drive_flags & DRIVE_UDMA &&
if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA &&
pdc202xx_setup_channel(chp)	struct channel_softc *chp;{	struct ata_drive_datas *drvp;	int drive;	pcireg_t mode, st;	u_int32_t idedma_ctl, scr, atapi;	struct pciide_channel *cp = (struct pciide_channel*)chp;	struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;	int channel = chp->channel;	/* setup DMA if needed */	pciide_channel_dma_setup(cp);	idedma_ctl = 0;	WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n",	    sc->sc_wdcdev.sc_dev.dv_xname,	    bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)),	    DEBUG_PROBE);	/* Per channel settings */	if (PDC_IS_262(sc)) {		scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,		    PDC262_U66);		st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE);		/* Trim UDMA mode */		if ((st & PDC262_STATE_80P(channel)) != 0 ||		    (chp->ch_drive[0].drive_flags & DRIVE_UDMA &&		    chp->ch_drive[0].UDMA_mode <= 2) ||		    (chp->ch_drive[1].drive_flags & DRIVE_UDMA &&		    chp->ch_drive[1].UDMA_mode <= 2)) {			if (chp->ch_drive[0].UDMA_mode > 2)				chp->ch_drive[0].UDMA_mode = 2;			if (chp->ch_drive[1].UDMA_mode > 2)				chp->ch_drive[1].UDMA_mode = 2;		}		/* Set U66 if needed */		if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA &&		    chp->ch_drive[0].UDMA_mode > 2) ||		    (chp->ch_drive[1].drive_flags & DRIVE_UDMA &&		    chp->ch_drive[1].UDMA_mode > 2))			scr |= PDC262_U66_EN(channel);		else			scr &= ~PDC262_U66_EN(channel);		bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,		    PDC262_U66, scr);		WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n",		    sc->sc_wdcdev.sc_dev.dv_xname, channel,		    bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh,		    PDC262_ATAPI(channel))), DEBUG_PROBE);		if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI ||		    chp->ch_drive[1].drive_flags & DRIVE_ATAPI) {			if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) &&			    !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) &&			    (chp->ch_drive[1].drive_flags & DRIVE_DMA)) ||			    ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) &&			    !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) &&			    (chp->ch_drive[0].drive_flags & DRIVE_DMA)))				atapi = 0;			else				atapi = PDC262_ATAPI_UDMA;			bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,			    PDC262_ATAPI(channel), atapi);		}	}	for (drive = 0; drive < 2; drive++) {		drvp = &chp->ch_drive[drive];		/* If no drive, skip */		if ((drvp->drive_flags & DRIVE) == 0)			continue;		mode = 0;		if (drvp->drive_flags & DRIVE_UDMA) {			/* use Ultra/DMA */			drvp->drive_flags &= ~DRIVE_DMA;			mode = PDC2xx_TIM_SET_MB(mode,			   pdc2xx_udma_mb[drvp->UDMA_mode]);			mode = PDC2xx_TIM_SET_MC(mode,			   pdc2xx_udma_mc[drvp->UDMA_mode]);			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);		} else if (drvp->drive_flags & DRIVE_DMA) {			mode = PDC2xx_TIM_SET_MB(mode,			    pdc2xx_dma_mb[drvp->DMA_mode]);			mode = PDC2xx_TIM_SET_MC(mode,			   pdc2xx_dma_mc[drvp->DMA_mode]);			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);		} else {			mode = PDC2xx_TIM_SET_MB(mode,			    pdc2xx_dma_mb[0]);			mode = PDC2xx_TIM_SET_MC(mode,			    pdc2xx_dma_mc[0]);		}		mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]);		mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]);		if (drvp->drive_flags & DRIVE_ATA)			mode |= PDC2xx_TIM_PRE;		mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY;		if (drvp->PIO_mode >= 3) {			mode |= PDC2xx_TIM_IORDY;			if (drive == 0)				mode |= PDC2xx_TIM_IORDYp;		}		WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d "		    "timings 0x%x\n",		    sc->sc_wdcdev.sc_dev.dv_xname, 		    chp->channel, drive, mode), DEBUG_PROBE);		    pci_conf_write(sc->sc_pc, sc->sc_tag,		    PDC2xx_TIM(chp->channel, drive), mode);	}	if (idedma_ctl != 0) {		/* Add software bits in status register */		bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,		    IDEDMA_CTL(channel), idedma_ctl);	}	pciide_print_modes(cp);}