s = splimp();
s = splnet();
void wb_init(xsc)	void			*xsc;{	struct wb_softc *sc = xsc;	struct ifnet *ifp = &sc->arpcom.ac_if;	int s, i;	s = splimp();	/*	 * Cancel pending I/O and free all RX/TX buffers.	 */	wb_stop(sc);	wb_reset(sc);	sc->wb_txthresh = WB_TXTHRESH_INIT;	/*	 * Set cache alignment and burst length.	 */#ifdef foo	CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);	WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));#endif	CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);	WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);	switch(sc->wb_cachesize) {	case 32:		WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);		break;	case 16:		WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);		break;	case 8:		WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);		break;	case 0:	default:		WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);		break;	}	/* This doesn't tend to work too well at 100Mbps. */	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);	/* Init our MAC address */	for (i = 0; i < ETHER_ADDR_LEN; i++) {		CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);	}	/* Init circular RX list. */	if (wb_list_rx_init(sc) == ENOBUFS) {		printf("%s: initialization failed: no "			"memory for rx buffers\n", sc->sc_dev.dv_xname);		wb_stop(sc);		splx(s);		return;	}	/* Init TX descriptors. */	wb_list_tx_init(sc);	/* If we want promiscuous mode, set the allframes bit. */	if (ifp->if_flags & IFF_PROMISC) {		WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);	} else {		WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);	}	/*	 * Set capture broadcast bit to capture broadcast frames.	 */	if (ifp->if_flags & IFF_BROADCAST) {		WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);	} else {		WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);	}	/*	 * Program the multicast filter, if necessary.	 */	wb_setmulti(sc);	/*	 * Load the address of the RX list.	 */	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);	CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));	/*	 * Enable interrupts.	 */	CSR_WRITE_4(sc, WB_IMR, WB_INTRS);	CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);	/* Enable receiver and transmitter. */	WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);	CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);	CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));	WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);	ifp->if_flags |= IFF_RUNNING;	ifp->if_flags &= ~IFF_OACTIVE;	splx(s);	timeout_set(&sc->wb_tick_tmo, wb_tick, sc);	timeout_add(&sc->wb_tick_tmo, hz);	return;}