}
cmd0643_9_setup_channel(chp)	struct channel_softc *chp;{	struct ata_drive_datas *drvp;	u_int8_t tim;	u_int32_t idedma_ctl, udma_reg;	int drive;	struct pciide_channel *cp = (struct pciide_channel*)chp;	struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;	idedma_ctl = 0;	/* setup DMA if needed */	pciide_channel_dma_setup(cp);	for (drive = 0; drive < 2; drive++) {		drvp = &chp->ch_drive[drive];		/* If no drive, skip */		if ((drvp->drive_flags & DRIVE) == 0)			continue;		/* add timing values, setup DMA if needed */		tim = cmd0643_9_data_tim_pio[drvp->PIO_mode];		if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {			if (drvp->drive_flags & DRIVE_UDMA) {				/* UltraDMA on a 646U2, 0648 or 0649 */				drvp->drive_flags &= ~DRIVE_DMA;				udma_reg = pciide_pci_read(sc->sc_pc,				    sc->sc_tag, CMD_UDMATIM(chp->channel));				if (drvp->UDMA_mode > 2 &&				    (pciide_pci_read(sc->sc_pc, sc->sc_tag,				    CMD_BICSR) &				    CMD_BICSR_80(chp->channel)) == 0)					drvp->UDMA_mode = 2;				if (drvp->UDMA_mode > 2)					udma_reg &= ~CMD_UDMATIM_UDMA33(drive);				else if (sc->sc_wdcdev.UDMA_cap > 2) 					udma_reg |= CMD_UDMATIM_UDMA33(drive);				udma_reg |= CMD_UDMATIM_UDMA(drive);				udma_reg &= ~(CMD_UDMATIM_TIM_MASK <<				    CMD_UDMATIM_TIM_OFF(drive));				udma_reg |=				    (cmd0646_9_tim_udma[drvp->UDMA_mode] <<				    CMD_UDMATIM_TIM_OFF(drive));				pciide_pci_write(sc->sc_pc, sc->sc_tag,				    CMD_UDMATIM(chp->channel), udma_reg);			} else {				/*				 * use Multiword DMA.				 * Timings will be used for both PIO and DMA,				 * so adjust DMA mode if needed				 * if we have a 0646U2/8/9, turn off UDMA				 */				if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {					udma_reg = pciide_pci_read(sc->sc_pc,					    sc->sc_tag,					    CMD_UDMATIM(chp->channel));					udma_reg &= ~CMD_UDMATIM_UDMA(drive);					pciide_pci_write(sc->sc_pc, sc->sc_tag,					    CMD_UDMATIM(chp->channel),					    udma_reg);				}				if (drvp->PIO_mode >= 3 &&				    (drvp->DMA_mode + 2) > drvp->PIO_mode) {					drvp->DMA_mode = drvp->PIO_mode - 2;				}				tim = cmd0643_9_data_tim_dma[drvp->DMA_mode];			}			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);		}		pciide_pci_write(sc->sc_pc, sc->sc_tag,		    CMD_DATA_TIM(chp->channel, drive), tim);	}	if (idedma_ctl != 0) {		/* Add software bits in status register */		bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,		    IDEDMA_CTL(chp->channel),		    idedma_ctl);	}	pciide_print_modes(cp);#ifdef __sparc64__	/*	 * The Ultra 5 has a tendency to hang during reboot.  This is due	 * to the PCI0646U asserting a PCI interrupt line when the chip	 * registers claim that it is not.  Performing a reset at this	 * point appears to eliminate the symptoms.  It is likely the	 * real cause is still lurking somewhere in the code.	 */	wdcreset(chp, SILENT);#endif /* __sparc64__ */}