if ((error = pdc_call((iodcio_t)pdc, 0, PDC_BLOCK_TLB, PDC_BTLB_DEFAULT, &pdc_btlb)) < 0) {
if (cpu_type < HPPA_FPU_PCXU && (error = pdc_call((iodcio_t)pdc, 0, PDC_BLOCK_TLB, PDC_BTLB_DEFAULT, &pdc_btlb)) < 0) {
cpuid(){	/*	 * Ptrs to various tlb handlers, to be filled	 * based on cpu features.	 * from locore.S	 */	extern u_int trap_ep_T_TLB_DIRTY[];	extern u_int trap_ep_T_DTLBMISS[];	extern u_int trap_ep_T_DTLBMISSNA[];	extern u_int trap_ep_T_ITLBMISS[];	extern u_int trap_ep_T_ITLBMISSNA[];	extern u_int fpu_enable;	extern int cpu_fpuena;	struct pdc_cpuid pdc_cpuid PDC_ALIGNMENT;	const struct hppa_cpu_typed *p = NULL;	u_int cpu_features;	int error;	/* may the scientific guessing begin */	cpu_features = 0;	cpu_type = 0;	/* identify system type */	if ((error = pdc_call((iodcio_t)pdc, 0, PDC_MODEL, PDC_MODEL_INFO,	    &pdc_model)) < 0) {#ifdef DEBUG		printf("WARNING: PDC_MODEL error %d\n", error);#endif		pdc_model.hvers = 0;	}	bzero(&pdc_cpuid, sizeof(pdc_cpuid));	if (pdc_call((iodcio_t)pdc, 0, PDC_MODEL, PDC_MODEL_CPUID,	    &pdc_cpuid, 0, 0, 0, 0) >= 0) {		/* patch for old 8200 */		if (pdc_cpuid.version == HPPA_CPU_PCXU &&		    pdc_cpuid.revision > 0x0d)			pdc_cpuid.version = HPPA_CPU_PCXUP;		cpu_type = pdc_cpuid.version;	}	/* locate coprocessors and SFUs */	bzero(&pdc_coproc, sizeof(pdc_coproc));	if ((error = pdc_call((iodcio_t)pdc, 0, PDC_COPROC, PDC_COPROC_DFLT,	    &pdc_coproc, 0, 0, 0, 0)) < 0) {		printf("WARNING: PDC_COPROC error %d\n", error);		cpu_fpuena = 0;	} else {		printf("pdc_coproc: 0x%x, 0x%x; model %x rev %x\n",		    pdc_coproc.ccr_enable, pdc_coproc.ccr_present,		    pdc_coproc.fpu_model, pdc_coproc.fpu_revision);		fpu_enable = pdc_coproc.ccr_enable & CCR_MASK;		cpu_fpuena = 1;		/* a kludge to detect PCXW */		if (pdc_coproc.fpu_model == HPPA_FPU_PCXW)			cpu_type = HPPA_CPU_PCXW;	}	/* BTLB params */	if ((error = pdc_call((iodcio_t)pdc, 0, PDC_BLOCK_TLB,	    PDC_BTLB_DEFAULT, &pdc_btlb)) < 0) {#ifdef DEBUG		printf("WARNING: PDC_BTLB error %d\n", error);#endif	} else {#ifdef BTLBDEBUG		printf("btlb info: minsz=%d, maxsz=%d\n",		    pdc_btlb.min_size, pdc_btlb.max_size);		printf("btlb fixed: i=%d, d=%d, c=%d\n",		    pdc_btlb.finfo.num_i,		    pdc_btlb.finfo.num_d,		    pdc_btlb.finfo.num_c);		printf("btlb varbl: i=%d, d=%d, c=%d\n",		    pdc_btlb.vinfo.num_i,		    pdc_btlb.vinfo.num_d,		    pdc_btlb.vinfo.num_c);#endif /* BTLBDEBUG */		/* purge TLBs and caches */		if (pdc_call((iodcio_t)pdc, 0, PDC_BLOCK_TLB,		    PDC_BTLB_PURGE_ALL) < 0)			printf("WARNING: BTLB purge failed\n");		if (pdc_btlb.finfo.num_c)			cpu_features |= HPPA_FTRS_BTLBU;	}	if (!pdc_call((iodcio_t)pdc, 0, PDC_TLB, PDC_TLB_INFO, &pdc_hwtlb) &&	    pdc_hwtlb.min_size && pdc_hwtlb.max_size) {		cpu_features |= HPPA_FTRS_HVT;		if (pmap_hptsize > pdc_hwtlb.max_size)			pmap_hptsize = pdc_hwtlb.max_size;		else if (pmap_hptsize && pmap_hptsize < pdc_hwtlb.min_size)			pmap_hptsize = pdc_hwtlb.min_size;	} else {		printf("WARNING: no HPT support, fine!\n");		pmap_hptsize = 0;	}	if (cpu_type)		for (p = cpu_types; p->name[0] && p->cpuid != cpu_type; p++);	else		for (p = cpu_types;		    p->name[0] && p->features != cpu_features; p++);	if (!p->name[0]) {		printf("WARNING: UNKNOWN CPU TYPE; GOOD LUCK "		    "(type 0x%x, features 0x%x)\n", cpu_type, cpu_features);		p = cpu_types;	} else if ((p->type == hpcxl || p->type == hpcxl2) && !fpu_enable) {		/* we know PCXL and PCXL2 do not exist w/o FPU */		fpu_enable = 0xc0;		cpu_fpuena = 1;	}	/*	 * TODO: HPT on 7200 is not currently supported	 */	if (pmap_hptsize && p->type != hpcxl && p->type != hpcxl2)		pmap_hptsize = 0;	cpu_type = p->type;	cpu_typename = p->name;	cpu_ibtlb_ins = p->ibtlbins;	cpu_dbtlb_ins = p->dbtlbins;	cpu_hpt_init = p->hptinit;	cpu_desidhash = p->desidhash;	/* patch tlb handler branches */	if (p->patch) {		trap_ep_T_TLB_DIRTY [0] = trap_ep_T_TLB_DIRTY [p->patch];		trap_ep_T_DTLBMISS  [0] = trap_ep_T_DTLBMISS  [p->patch];		trap_ep_T_DTLBMISSNA[0] = trap_ep_T_DTLBMISSNA[p->patch];		trap_ep_T_ITLBMISS  [0] = trap_ep_T_ITLBMISS  [p->patch];		trap_ep_T_ITLBMISSNA[0] = trap_ep_T_ITLBMISSNA[p->patch];	}	/* force strong ordering for now */	if (p->features & HPPA_FTRS_W32B) {		extern register_t kpsw;	/* intr.c */		kpsw |= PSL_O;	}	{		const char *p, *q;		char buf[32];		int lev;		lev = 0xa + (*cpu_desidhash)();		cpu_hvers = pdc_model.hvers >> 4;		if (!cpu_hvers) {			p = "(UNKNOWN)";			q = lev == 0xa? "1.0" : "1.1";		} else {			p = hppa_mod_info(HPPA_TYPE_BOARD, cpu_hvers);			if (!p) {				snprintf(buf, sizeof buf, "(UNKNOWN 0x%x)",				    cpu_hvers);				p = buf;			}			switch (pdc_model.arch_rev) {			default:			case 0:				q = "1.0";#ifdef COMPAT_HPUX				cpu_model_hpux = HPUX_SYSCONF_CPUPA10;#endif				break;			case 4:				q = "1.1";#ifdef COMPAT_HPUX				cpu_model_hpux = HPUX_SYSCONF_CPUPA11;#endif				/* this one is just a 100MHz pcxl */				if (lev == 0x10)					lev = 0xc;				/* this one is a pcxl2 */				if (lev == 0x16)					lev = 0xe;				break;			case 8:				q = "2.0";#ifdef COMPAT_HPUX				cpu_model_hpux = HPUX_SYSCONF_CPUPA20;#endif				break;			}		}		snprintf(cpu_model, sizeof cpu_model,		    "HP 9000/%s PA-RISC %s%x", p, q, lev);	}}