"nop ! nop ! nop\n\t"
pmap_zero_page(pa)	paddr_t pa;{	extern int dcache_line_mask;	register paddr_t pe = pa + PAGE_SIZE;	int s;	DPRINTF(PDB_FOLLOW|PDB_PHYS, ("pmap_zero_page(%x)\n", pa));	/*	 * do not allow any ints to happen, since cache is in	 * inconsistant state during the loop.	 *	 * do not rsm(PSW_I) since that will lose ints completely,	 * instead, keep 'em pending (or verify by the book).	 */	s = splhigh();	while (pa < pe) {		__asm volatile(			/* can use ,bc */		    "stwas,ma %%r0,4(%0)\n\t"		    "stwas,ma %%r0,4(%0)\n\t"		    "stwas,ma %%r0,4(%0)\n\t"		    "stwas,ma %%r0,4(%0)"		    : "+r" (pa) :: "memory");		if (!(pa & dcache_line_mask))			__asm volatile("rsm	%1, %%r0\n\t"				       "fdc	%2(%0)\n\t"				       "ssm	%1, %%r0"			    :: "r" (pa), "i" (PSW_D), "r" (-4) : "memory");	}	sync_caches();	splx(s);}