0, 0, BUS_DMA_NOWAIT, &q.map)) {
MAX_JUMBO_FRAME_SIZE, 0, BUS_DMA_NOWAIT, &q.map)) {
em_encap(struct em_softc *sc, struct mbuf *m_head){	u_int32_t	txd_upper;	u_int32_t	txd_lower, txd_used = 0, txd_saved = 0;	int		i, j, error;	u_int64_t       address;        /* For 82544 Workaround */        DESC_ARRAY              desc_array;        u_int32_t               array_elements;        u_int32_t               counter;#if NVLAN > 0	struct ifvlan *ifv = NULL;#endif	struct em_q	q;	struct em_buffer   *tx_buffer = NULL;	struct em_tx_desc *current_tx_desc = NULL;	/*struct ifnet	 *ifp = &sc->interface_data.ac_if;*/	/*	 * Force a cleanup if number of TX descriptors	 * available hits the threshold	 */	if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {		em_clean_transmit_interrupts(sc);		if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {			sc->no_tx_desc_avail1++;			return (ENOBUFS);		}	}	/*	 * Map the packet for DMA.	 */	if (bus_dmamap_create(sc->txtag, MAX_JUMBO_FRAME_SIZE, 32,	    0, 0, BUS_DMA_NOWAIT, &q.map)) {		sc->no_tx_map_avail++;		return (ENOMEM);	}	error = bus_dmamap_load_mbuf(sc->txtag, q.map,				     m_head, BUS_DMA_NOWAIT);	if (error != 0) {		sc->no_tx_dma_setup++;		bus_dmamap_destroy(sc->txtag, q.map);		return (error);	}	EM_KASSERT(q.map->dm_nsegs!= 0, ("em_encap: empty packet"));	if (q.map->dm_nsegs > sc->num_tx_desc_avail) {		sc->no_tx_desc_avail2++;		bus_dmamap_destroy(sc->txtag, q.map);		return (ENOBUFS);	}#ifdef __FreeBSD__	if (ifp->if_hwassist > 0) {		em_transmit_checksum_setup(sc,	m_head,					   &txd_upper, &txd_lower);	} else#endif /* __FreeBSD__ */		txd_upper = txd_lower = 0;	/* Find out if we are in vlan mode */#if NVLAN > 0	if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&	    m_head->m_pkthdr.rcvif != NULL &&	    m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)		ifv = m_head->m_pkthdr.rcvif->if_softc;#endif	i = sc->next_avail_tx_desc;        if (sc->pcix_82544) {                txd_saved = i;                txd_used = 0;        }	for (j = 0; j < q.map->dm_nsegs; j++) {                /* If sc is 82544 and on PCIX bus */                if(sc->pcix_82544) {                        array_elements = 0;                        address = htole64(q.map->dm_segs[j].ds_addr);                        /*                         * Check the Address and Length combination and                         * split the data accordingly                         */                        array_elements = em_fill_descriptors(address,                                                             htole32(q.map->dm_segs[j].ds_len),                                                             &desc_array);                        for (counter = 0; counter < array_elements; counter++) {                                if (txd_used == sc->num_tx_desc_avail) {                                          sc->next_avail_tx_desc = txd_saved;                                          sc->no_tx_desc_avail2++;                                          bus_dmamap_destroy(sc->txtag, q.map);                                          return (ENOBUFS);                                }                                tx_buffer = &sc->tx_buffer_area[i];                                current_tx_desc = &sc->tx_desc_base[i];                                current_tx_desc->buffer_addr = htole64(                                        desc_array.descriptor[counter].address);                                current_tx_desc->lower.data = htole32(                                        (sc->txd_cmd | txd_lower |                                         (u_int16_t)desc_array.descriptor[counter].length));                                current_tx_desc->upper.data = htole32((txd_upper));                                if (++i == sc->num_tx_desc)                                         i = 0;                                tx_buffer->m_head = NULL;                                txd_used++;                        }                } else {		        tx_buffer = &sc->tx_buffer_area[i];		        current_tx_desc = &sc->tx_desc_base[i];		        current_tx_desc->buffer_addr = htole64(q.map->dm_segs[j].ds_addr);		        current_tx_desc->lower.data = htole32(		            sc->txd_cmd | txd_lower | q.map->dm_segs[j].ds_len);		        current_tx_desc->upper.data = htole32(txd_upper);		        if (++i == sc->num_tx_desc)	        		i = 0;				        tx_buffer->m_head = NULL;                }	}	sc->next_avail_tx_desc = i;        if (sc->pcix_82544) {                sc->num_tx_desc_avail -= txd_used;        }        else {                sc->num_tx_desc_avail -= q.map->dm_nsegs;        }#if NVLAN > 0	if (ifv != NULL) {		/* Set the vlan id */		current_tx_desc->upper.fields.special = htole16(ifv->ifv_tag);		/* Tell hardware to add tag */		current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE);	}#endif	tx_buffer->m_head = m_head;	tx_buffer->map = q.map;	bus_dmamap_sync(sc->txtag, q.map, 0, q.map->dm_mapsize,	    BUS_DMASYNC_PREWRITE);	/* 	 * Last Descriptor of Packet needs End Of Packet (EOP) 	 */	current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP);	/* 	 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000	 * that this frame is available to transmit.	 */	if (sc->hw.mac_type == em_82547 &&	    sc->link_duplex == HALF_DUPLEX) {		em_82547_move_tail_locked(sc);	} else {		E1000_WRITE_REG(&sc->hw, TDT, i);		if (sc->hw.mac_type == em_82547) {			em_82547_update_fifo_head(sc, m_head->m_pkthdr.len);		}	}	return (0);}