offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
offset = (inst & 0xff) << 1;
sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,		     struct sh_frame_cache *cache){  ULONGEST inst;  CORE_ADDR opc;  int offset;  int sav_offset = 0;  int r3_val = 0;  int reg, sav_reg = -1;  if (pc >= current_pc)    return current_pc;  cache->uses_fp = 0;  for (opc = pc + (2 * 28); pc < opc; pc += 2)    {      inst = read_memory_unsigned_integer (pc, 2);      /* See where the registers will be saved to */      if (IS_PUSH (inst))	{	  cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;	  cache->sp_offset += 4;	}      else if (IS_STS (inst))	{	  cache->saved_regs[PR_REGNUM] = cache->sp_offset;	  cache->sp_offset += 4;	}      else if (IS_MOV_R3 (inst))	{	  r3_val = ((inst & 0xff) ^ 0x80) - 0x80;	}      else if (IS_SHLL_R3 (inst))	{	  r3_val <<= 1;	}      else if (IS_ADD_R3SP (inst))	{	  cache->sp_offset += -r3_val;	}      else if (IS_ADD_IMM_SP (inst))	{	  offset = ((inst & 0xff) ^ 0x80) - 0x80;	  cache->sp_offset -= offset;	}      else if (IS_MOVW_PCREL_TO_REG (inst))	{	  if (sav_reg < 0)	    {	      reg = GET_TARGET_REG (inst);	      if (reg < 14)		{		  sav_reg = reg;		  offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;		  sav_offset =		    read_memory_integer (((pc + 4) & ~3) + offset, 2);		}	    }	}      else if (IS_MOVL_PCREL_TO_REG (inst))	{	  if (sav_reg < 0)	    {	      reg = (inst & 0x0f00) >> 8;	      if (reg < 14)		{		  sav_reg = reg;		  offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;		  sav_offset =		    read_memory_integer (((pc + 4) & ~3) + offset, 4);		}	    }	}      else if (IS_SUB_REG_FROM_SP (inst))	{	  reg = GET_SOURCE_REG (inst);	  if (sav_reg > 0 && reg == sav_reg)	    {	      sav_reg = -1;	    }	  cache->sp_offset += sav_offset;	}      else if (IS_FPUSH (inst))	{	  if (read_register (FPSCR_REGNUM) & FPSCR_SZ)	    {	      cache->sp_offset += 8;	    }	  else	    {	      cache->sp_offset += 4;	    }	}      else if (IS_MOV_SP_FP (inst))	{	  cache->uses_fp = 1;	  /* At this point, only allow argument register moves to other	     registers or argument register moves to @(X,fp) which are	     moving the register arguments onto the stack area allocated	     by a former add somenumber to SP call.  Don't allow moving	     to an fp indirect address above fp + cache->sp_offset. */	  pc += 2;	  for (opc = pc + 12; pc < opc; pc += 2)	    {	      inst = read_memory_integer (pc, 2);	      if (IS_MOV_ARG_TO_IND_R14 (inst))		{		  reg = GET_SOURCE_REG (inst);		  if (cache->sp_offset > 0)		    cache->saved_regs[reg] = cache->sp_offset;		}	      else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))		{		  reg = GET_SOURCE_REG (inst);		  offset = (inst & 0xf) * 4;		  if (cache->sp_offset > offset)		    cache->saved_regs[reg] = cache->sp_offset - offset;		}	      else if (IS_MOV_ARG_TO_REG (inst))		continue;	      else		break;	    }	  break;	}      else if (IS_JSR (inst))	{	  /* We have found a jsr that has been scheduled into the prologue.	     If we continue the scan and return a pc someplace after this,	     then setting a breakpoint on this function will cause it to	     appear to be called after the function it is calling via the	     jsr, which will be very confusing.  Most likely the next	     instruction is going to be IS_MOV_SP_FP in the delay slot.  If	     so, note that before returning the current pc. */	  inst = read_memory_integer (pc + 2, 2);	  if (IS_MOV_SP_FP (inst))	    cache->uses_fp = 1;	  break;	}#if 0				/* This used to just stop when it found an instruction that				   was not considered part of the prologue.  Now, we just				   keep going looking for likely instructions. */      else	break;#endif    }  return pc;}