rem: device->wb_txthresh = WB_TXTHRESH_INIT;
context: wb_reset(wb_device *device){	int i = 0;	cpu_status status;		LOG((DEVICE_NAME": reset()\n"));		status = disable_interrupts();		device->wb_txthresh = WB_TXTHRESH_INIT;		write32(device->reg_base + WB_NETCFG, 0L);	write32(device->reg_base + WB_BUSCTL, 0L);	write32(device->reg_base + WB_TXADDR, 0L);	write32(device->reg_base + WB_RXADDR, 0L);		WB_SETBIT(device->reg_base + WB_BUSCTL, WB_BUSCTL_RESET);	WB_SETBIT(device->reg_base + WB_BUSCTL, WB_BUSCTL_RESET);		for (i = 0; i < WB_TIMEOUT; i++) {		if (!(read32(device->reg_base + WB_BUSCTL) & WB_BUSCTL_RESET))			break;	}		if (i == WB_TIMEOUT)		LOG(("reset hasn't completed!!!"));		write32(device->reg_base + WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);	WB_SETBIT(device->reg_base + WB_BUSCTL, WB_BURSTLEN_16LONG);		switch(device->wb_cachesize) {		case 32:			WB_SETBIT(device->reg_base + WB_BUSCTL, WB_CACHEALIGN_32LONG);			break;			case 16:			WB_SETBIT(device->reg_base + WB_BUSCTL, WB_CACHEALIGN_16LONG);			break;		case 8:			WB_SETBIT(device->reg_base + WB_BUSCTL, WB_CACHEALIGN_8LONG);			break;		case 0:		default:			WB_SETBIT(device->reg_base + WB_BUSCTL, WB_CACHEALIGN_NONE);			break;	}		write32(device->reg_base + WB_BUSCTL_SKIPLEN, WB_SKIPLEN_4LONG);		/* Early TX interrupt; doesn't tend to work too well at 100Mbps */	WB_SETBIT(device->reg_base + WB_NETCFG, (WB_NETCFG_TX_EARLY_ON|WB_NETCFG_RX_EARLY_ON));		// fullduplex	WB_SETBIT(device->reg_base + WB_NETCFG, WB_NETCFG_FULLDUPLEX);		//100 MBits	WB_SETBIT(device->reg_base + WB_NETCFG, WB_NETCFG_100MBPS);		/* Program the multicast filter, if necessary */	//wb_setmulti(device);		//Disable promiscuos mode	WB_CLRBIT(device->reg_base + WB_NETCFG, WB_NETCFG_RX_ALLPHYS);			//Disable capture broadcast	WB_CLRBIT(device->reg_base + WB_NETCFG, WB_NETCFG_RX_BROAD);					restore_interrupts(status);		/* Wait a bit while the chip reorders his toughts */	snooze(1000);		//XXX Initialize MII interface}