rem: * TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForceFX 5200 if * the CRTC1 (and CRTC2) BUFFER register b2 = 0 */ switch(target->space) { case B_CMAP8: max_crtc_width = 16376; break; case B_RGB15: max_crtc_width =  8188; break; case B_RGB16: max_crtc_width =  8188; break; case B_RGB24: max_crtc_width =  5456; break; case B_RGB32: max_crtc_width =  4094; break;
add: * TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForce4 Ti4200, * GeForceFX 5200: if the CRTC1 (and CRTC2) BUFFER register b2 = 0 */  switch(target->space) { case B_CMAP8: max_crtc_width = 16368; break;  case B_RGB15: max_crtc_width =  8184; break;  case B_RGB16: max_crtc_width =  8184; break;  case B_RGB24: max_crtc_width =  5456; break;  case B_RGB32: max_crtc_width =  4092; break;
context: status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_row, bool *acc_mode){	uint32 video_pitch;	uint32 acc_mask, crtc_mask;	uint32 max_crtc_width, max_acc_width;	uint8 depth = 8;	/* determine pixel multiple based on 2D/3D engine constraints */	switch (si->ps.card_arch)	{	default:		/* confirmed for:		 * TNT1, TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForceFX 5200 */		switch (target->space)		{			case B_CMAP8: acc_mask = 0x0f; depth =  8; break;			case B_RGB15: acc_mask = 0x07; depth = 16; break;			case B_RGB16: acc_mask = 0x07; depth = 16; break;			case B_RGB24: acc_mask = 0x0f; depth = 24; break;			case B_RGB32: acc_mask = 0x03; depth = 32; break;			default:				LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));				return B_ERROR;		}		/* NV31 (confirmed GeForceFX 5600) has NV20A granularity!		 * So let it fall through... */		if (si->ps.card_type != NV31) break;	case NV20A:		/* confirmed for:		 * GeForce4 Ti4200 */		switch (target->space)		{			case B_CMAP8: acc_mask = 0x3f; depth =  8; break;			case B_RGB15: acc_mask = 0x1f; depth = 16; break;			case B_RGB16: acc_mask = 0x1f; depth = 16; break;			case B_RGB24: acc_mask = 0x3f; depth = 24; break;			case B_RGB32: acc_mask = 0x0f; depth = 32; break;			default:				LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));				return B_ERROR;		}		break;	}	/* determine pixel multiple based on CRTC memory pitch constraints:	 * -> all NV cards have same granularity constraints on CRTC1 and CRTC2,	 *    provided that the CRTC1 and CRTC2 BUFFER register b2 = 0;	 *	 * (Note: Don't mix this up with CRTC timing contraints! Those are	 *        multiples of 8 for horizontal, 1 for vertical timing.) */	if (0)	{		/* confirmed for:		 * TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForceFX 5200 if		 * the CRTC1 (and CRTC2) BUFFER register b2 = 1 */		switch (target->space)		{			case B_CMAP8: crtc_mask = 0x1f; break;			case B_RGB15: crtc_mask = 0x0f; break;			case B_RGB16: crtc_mask = 0x0f; break;			case B_RGB24: crtc_mask = 0x1f; break;			case B_RGB32: crtc_mask = 0x07; break;			default:				LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));				return B_ERROR;		}	}	else	{		/* confirmed for:		 * TNT1 always;		 * TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForceFX 5200 if		 * the CRTC1 (and CRTC2) BUFFER register b2 = 0 */		switch (target->space)		{			case B_CMAP8: crtc_mask = 0x07; break;			case B_RGB15: crtc_mask = 0x03; break;			case B_RGB16: crtc_mask = 0x03; break;			case B_RGB24: crtc_mask = 0x07; break;			case B_RGB32: crtc_mask = 0x01; break;			default:				LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));				return B_ERROR;		}	}	/* set virtual_width limit for accelerated modes */	switch (si->ps.card_arch)	{	case NV04A:		/* confirmed for:		 * TNT1, TNT2, TNT2-M64 */		switch(target->space)		{			case B_CMAP8: max_acc_width = 8176; break;			case B_RGB15: max_acc_width = 4088; break;			case B_RGB16: max_acc_width = 4088; break;			case B_RGB24: max_acc_width = 2720; break;			case B_RGB32: max_acc_width = 2044; break;			default:				LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));				return B_ERROR;		}		break;	default:		/* confirmed for:		 * GeForce2 MX400, GeForce4 MX440, GeForceFX 5200 */		switch(target->space)		{			case B_CMAP8: max_acc_width = 16368; break;			case B_RGB15: max_acc_width =  8184; break;			case B_RGB16: max_acc_width =  8184; break;			case B_RGB24: max_acc_width =  5456; break;			case B_RGB32: max_acc_width =  4092; break;			default:				LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));				return B_ERROR;		}		/* NV31 (confirmed GeForceFX 5600) has NV20A granularity!		 * So let it fall through... */		if (si->ps.card_type != NV31) break;	case NV20A:		/* confirmed for:		 * GeForce4 Ti4200 */		switch(target->space)		{			case B_CMAP8: max_acc_width = 16320; break;			case B_RGB15: max_acc_width =  8160; break;			case B_RGB16: max_acc_width =  8160; break;			case B_RGB24: max_acc_width =  5440; break;			case B_RGB32: max_acc_width =  4080; break;			default:				LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));				return B_ERROR;		}		break;	}	/* set virtual_width limit for unaccelerated modes */	if (0)	{		/* confirmed for:		 * TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForceFX 5200 if		 * the CRTC1 (and CRTC2) BUFFER register b2 = 1 */		switch(target->space)		{			case B_CMAP8: max_crtc_width = 16352; break;			case B_RGB15: max_crtc_width =  8176; break;			case B_RGB16: max_crtc_width =  8176; break;			case B_RGB24: max_crtc_width =  5440; break;			case B_RGB32: max_crtc_width =  4088; break;			default:				LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));				return B_ERROR;		}	}	else	{		/* confirmed for:		 * TNT1 always;		 * TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForceFX 5200 if		 * the CRTC1 (and CRTC2) BUFFER register b2 = 0 */		switch(target->space)		{			case B_CMAP8: max_crtc_width = 16376; break;			case B_RGB15: max_crtc_width =  8188; break;			case B_RGB16: max_crtc_width =  8188; break;			case B_RGB24: max_crtc_width =  5456; break;			case B_RGB32: max_crtc_width =  4094; break;			default:				LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));				return B_ERROR;		}	}	/* check for acc capability, and adjust mode to adhere to hardware constraints */	if (max_acc_width <= max_crtc_width)	{		/* check if we can setup this mode with acceleration */		*acc_mode = true;		/* virtual_width */		if (target->virtual_width > max_acc_width) *acc_mode = false;		/* virtual_height */		/* (NV cards can even do more than this(?)...		 *  but 4096 is confirmed on all cards at max. accelerated width.) */		if (target->virtual_height > 4096) *acc_mode = false;		/* now check virtual_size based on CRTC constraints */		if (target->virtual_width > max_crtc_width) target->virtual_width = max_crtc_width;		/* virtual_height: The only constraint here is the cards memory size which is		 * checked later on in ProposeMode: virtual_height is adjusted then if needed.		 * 'Limiting here' to the variable size that's at least available (uint16). */		if (target->virtual_height > 65535) target->virtual_height = 65535;		/* OK, now we know that virtual_width is valid, and it's needing no slopspace if		 * it was confined above, so we can finally calculate safely if we need slopspace		 * for this mode... */		if (*acc_mode)		{			/* the mode needs to adhere to the largest granularity imposed... */			if (acc_mask < crtc_mask)				video_pitch = ((target->virtual_width + crtc_mask) & ~crtc_mask);			else				video_pitch = ((target->virtual_width + acc_mask) & ~acc_mask);		}		else /* unaccelerated mode */			video_pitch = ((target->virtual_width + crtc_mask) & ~crtc_mask);	}	else /* max_acc_width > max_crtc_width */	{		/* check if we can setup this mode with acceleration */		*acc_mode = true;		/* (we already know virtual_width will be no problem) */		/* virtual_height */		/* (NV cards can even do more than this(?)...		 *  but 4096 is confirmed on all cards at max. accelerated width.) */		if (target->virtual_height > 4096) *acc_mode = false;		/* now check virtual_size based on CRTC constraints */		if (*acc_mode)		{			/* note that max_crtc_width already adheres to crtc_mask */			if (target->virtual_width > (max_crtc_width & ~acc_mask))					target->virtual_width = (max_crtc_width & ~acc_mask);		}		else /* unaccelerated mode */		{			if (target->virtual_width > max_crtc_width)					target->virtual_width = max_crtc_width;		}		/* virtual_height: The only constraint here is the cards memory size which is		 * checked later on in ProposeMode: virtual_height is adjusted then if needed.		 * 'Limiting here' to the variable size that's at least available (uint16). */		if (target->virtual_height > 65535) target->virtual_height = 65535;		/* OK, now we know that virtual_width is valid, and it's needing no slopspace if		 * it was confined above, so we can finally calculate safely if we need slopspace		 * for this mode... */		if (*acc_mode)		{			/* the mode needs to adhere to the largest granularity imposed... */			if (acc_mask < crtc_mask)				video_pitch = ((target->virtual_width + crtc_mask) & ~crtc_mask);			else				video_pitch = ((target->virtual_width + acc_mask) & ~acc_mask);		}		else /* unaccelerated mode */			video_pitch = ((target->virtual_width + crtc_mask) & ~crtc_mask);	}	LOG(2,("INIT: memory pitch will be set to %d pixels for colorspace 0x%08x\n",														video_pitch, target->space)); 	if (target->virtual_width != video_pitch)		LOG(2,("INIT: effective mode slopspace is %d pixels\n", 											(video_pitch - target->virtual_width)));	/* now calculate bytes_per_row for this mode */	*bytes_per_row = video_pitch * (depth >> 3);	return B_OK;}