rem: set_pci(pd->di[count].agp_adress + 8, 4, *command);
add: set_pci(pd->di[count].agp_adress + 8, 4, (*command & ~AGP_rate_rev));
context: void enable_agp (uint32 *command){	long count;	pci_info *pcii;	TRACE("agp_man: enable_agp called\n");	/* validate the given command: */	/* if we should set PCI mode, reset all options */	if (!(*command & AGP_enable)) *command = 0x00000000;	/* make sure we accept all modes lower than requested one and we reset reserved bits */	if (!(*command & AGP_rate_rev))	{		/* AGP 2.0 scheme applies */		if (*command & AGP_2_4x) *command |= AGP_2_2x;		if (*command & AGP_2_2x) *command |= AGP_2_1x;	}	else	{		/* AGP 3.0 scheme applies */		if (*command & AGP_3_8x) *command |= AGP_3_4x;		*command &= ~0x00000004;	}	/* reset all other reserved and currently unused bits */	*command &= ~0x00fffce0;	/* block features if requested by user in agp.settings file */	check_settings(command);	/* iterate through our device list to find the common capabilities supported */	for (count = 0; count < pd->count; count++)	{		pcii = &(pd->di[count].pcii);		/* refresh from the contents of the AGP capability registers */		/* (note: some graphicsdriver may have been tweaking, like nvidia) */		pd->di[count].agpi.interface.agp_stat = get_pci(pd->di[count].agp_adress + 4, 4);		check_capabilities(pd->di[count].agpi.interface.agp_stat, command);	}	/* select only the highest remaining possible mode-bits */	if (!(*command & AGP_rate_rev))	{		/* AGP 2.0 scheme applies */		if (*command & AGP_2_4x) *command &= ~(AGP_2_2x | AGP_2_1x);		if (*command & AGP_2_2x) *command &= ~AGP_2_1x;	}	else	{		/* AGP 3.0 scheme applies */		if (*command & AGP_3_8x) *command &= ~AGP_3_4x;	}	/* note:	 * we are not setting the enable AGP bits ourselves, as the user should have specified that	 * in 'command' if we should be enabling AGP mode here (otherwise we set PCI mode). */	/* note also:	 * the AGP standard defines that this bit may be written to the AGPCMD	 * registers simultanously with the other bits if a single 32bit write	 * to each register is used. */	/* first program all bridges */	for (count = 0; count < pd->count; count++)	{		if (pd->di[count].agpi.class_base == PCI_bridge)		{			pcii = &(pd->di[count].pcii);			/* program bridge, making sure not-implemented bits are written as zeros */			set_pci(pd->di[count].agp_adress + 8, 4, (*command & ~(AGP_rate_rev | AGP_RQ)));			/* update our agp_cmd info with read back setting from register just programmed */			pd->di[count].agpi.interface.agp_cmd = get_pci(pd->di[count].agp_adress + 8, 4);		}	}	/* wait 10mS for the bridges to recover (failsafe!) */	/* note:	 * some SiS bridge chipsets apparantly require 5mS to recover or the	 * master (graphics card) cannot be initialized correctly! */	snooze(10000);	/* _now_ program all graphicscards */	for (count = 0; count < pd->count; count++)	{		if (pd->di[count].agpi.class_base == PCI_display)		{			pci_info *pcii = &(pd->di[count].pcii);			/* program graphicscard */			set_pci(pd->di[count].agp_adress + 8, 4, *command);			/* update our agp_cmd info with read back setting from register just programmed */			/* note:			 * this 'sequence' resets the non-writable register bit AGP_rate_rev in our info */			pd->di[count].agpi.interface.agp_cmd = get_pci(pd->di[count].agp_adress + 8, 4);		}	}}