rem: u32 level,val,ret = 1;
add: s64 time; u32 level,ret = 1; s32 val;
context: static u32 __exi_probe(u32 nChn){	u32 level,val,ret = 1;	exibus_priv *exi = &eximap[nChn];	_CPU_ISR_Disable(level);	val = _exiReg[nChn*5];	if(!(exi->flags&EXI_FLAG_ATTACH)) {		if(val&EXI_EXT_IRQ) {			_exiReg[nChn*5] = (val&~(EXI_EXI_IRQ|EXI_TC_IRQ|EXI_EXT_IRQ))|EXI_EXT_IRQ;			exi->exi_buscode = 0;			exi_buscode[nChn] = 0;		}		if(_exiReg[nChn*5]&EXI_EXT_BIT) {		} else {			exi->exi_buscode = 0;			exi_buscode[nChn] = 0;			_CPU_ISR_Restore(level);			return 0;		}	}	if(!(_exiReg[nChn*5]&EXI_EXT_BIT) || (_exiReg[nChn*5]&EXI_EXT_IRQ)) {		exi->exi_buscode = 0;		exi_buscode[nChn] = 0;		ret = 0;	}	_CPU_ISR_Restore(level);	return ret;}