rem: DEBUGOUT("Forcing 100mb ");
add: HW_DEBUGOUT("Forcing 100mb ");
context: em_phy_force_speed_duplex(struct em_hw *hw){    uint32_t ctrl;    int32_t ret_val;    uint16_t mii_ctrl_reg;    uint16_t mii_status_reg;    uint16_t phy_data;    uint16_t i;    DEBUGFUNC("em_phy_force_speed_duplex");    /* Turn off Flow control if we are forcing speed and duplex. */    hw->fc = em_fc_none;    DEBUGOUT1("hw->fc = %d\n", hw->fc);    /* Read the Device Control Register. */    ctrl = E1000_READ_REG(hw, CTRL);    /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);    ctrl &= ~(DEVICE_SPEED_MASK);    /* Clear the Auto Speed Detect Enable bit. */    ctrl &= ~E1000_CTRL_ASDE;    /* Read the MII Control Register. */    if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg)))        return ret_val;    /* We need to disable autoneg in order to force link and duplex. */    mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;    /* Are we forcing Full or Half Duplex? */    if(hw->forced_speed_duplex == em_100_full ||       hw->forced_speed_duplex == em_10_full) {        /* We want to force full duplex so we SET the full duplex bits in the         * Device and MII Control Registers.         */        ctrl |= E1000_CTRL_FD;        mii_ctrl_reg |= MII_CR_FULL_DUPLEX;        DEBUGOUT("Full Duplex\n");    } else {        /* We want to force half duplex so we CLEAR the full duplex bits in         * the Device and MII Control Registers.         */        ctrl &= ~E1000_CTRL_FD;        mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;        DEBUGOUT("Half Duplex\n");    }    /* Are we forcing 100Mbps??? */    if(hw->forced_speed_duplex == em_100_full ||       hw->forced_speed_duplex == em_100_half) {        /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */        ctrl |= E1000_CTRL_SPD_100;        mii_ctrl_reg |= MII_CR_SPEED_100;        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);        DEBUGOUT("Forcing 100mb ");    } else {        /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */        ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);        mii_ctrl_reg |= MII_CR_SPEED_10;        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);        DEBUGOUT("Forcing 10mb ");    }    em_config_collision_dist(hw);    /* Write the configured values back to the Device Control Reg. */    E1000_WRITE_REG(hw, CTRL, ctrl);    if (hw->phy_type == em_phy_m88) {        if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,                                         &phy_data)))            return ret_val;        /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI         * forced whenever speed are duplex are forced.         */        phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;        if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,                                          phy_data)))            return ret_val;        DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);        /* Need to reset the PHY or these changes will be ignored */        mii_ctrl_reg |= MII_CR_RESET;    } else {        /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI         * forced whenever speed or duplex are forced.         */        if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,                                         &phy_data)))            return ret_val;        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;        phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;        if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,                                          phy_data)))            return ret_val;    }    /* Write back the modified PHY MII control register. */    if((ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg)))        return ret_val;    usec_delay(1);    /* The wait_autoneg_complete flag may be a little misleading here.     * Since we are forcing speed and duplex, Auto-Neg is not enabled.     * But we do want to delay for a period while forcing only so we     * don't generate false No Link messages.  So we will wait here     * only if the user has set wait_autoneg_complete to 1, which is     * the default.     */    if(hw->wait_autoneg_complete) {        /* We will wait for autoneg to complete. */        DEBUGOUT("Waiting for forced speed/duplex link.\n");        mii_status_reg = 0;        /* We will wait for autoneg to complete or 4.5 seconds to expire. */        for(i = PHY_FORCE_TIME; i > 0; i--) {            /* Read the MII Status Register and wait for Auto-Neg Complete bit             * to be set.             */            if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))                return ret_val;            if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))                return ret_val;            if(mii_status_reg & MII_SR_LINK_STATUS) break;            msec_delay(100);        }        if((i == 0) && (hw->phy_type == em_phy_m88)) {            /* We didn't get link.  Reset the DSP and wait again for link. */            if((ret_val = em_phy_reset_dsp(hw))) {                DEBUGOUT("Error Resetting PHY DSP\n");                return ret_val;            }        }        /* This loop will early-out if the link condition has been met.  */        for(i = PHY_FORCE_TIME; i > 0; i--) {            if(mii_status_reg & MII_SR_LINK_STATUS) break;            msec_delay(100);            /* Read the MII Status Register and wait for Auto-Neg Complete bit             * to be set.             */            if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))                return ret_val;            if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))                return ret_val;        }    }    if (hw->phy_type == em_phy_m88) {        /* Because we reset the PHY above, we need to re-force TX_CLK in the         * Extended PHY Specific Control Register to 25MHz clock.  This value         * defaults back to a 2.5MHz clock when the PHY is reset.         */        if((ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,                                         &phy_data)))            return ret_val;        phy_data |= M88E1000_EPSCR_TX_CLK_25;        if((ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,                                          phy_data)))            return ret_val;        /* In addition, because of the s/w reset above, we need to enable CRS on         * TX.  This must be set for both full and half duplex operation.         */        if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,                                         &phy_data)))            return ret_val;        phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;        if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,                                          phy_data)))            return ret_val;        /* Polarity reversal workaround for forced 10F/10H links. */        if(hw->mac_type <= em_82544 &&           (hw->forced_speed_duplex == em_10_full ||            hw->forced_speed_duplex == em_10_half)) {            if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,                                              0x0019)))                return ret_val;            if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,                                              0x8F0F)))                return ret_val;            /* IEEE requirement is 150ms */            msec_delay(200);            if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,                                              0x0019)))                return ret_val;            if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,                                              0x8F00)))                return ret_val;        }    }    return E1000_SUCCESS;}