rem: void voodoo3_setup_monitor(display_mode *dm)
add: voodoo3_setup_monitor(display_mode *dm)
context: void voodoo3_setup_monitor(display_mode *dm){	MonitorRegs mod; MonitorRegs *mode;	int i;	uint32 horizontal_display_end, horizontal_sync_start,		horizontal_sync_end, horizontal_total, horizontal_blanking_start,		horizontal_blanking_end;		uint32 vertical_display_enable_end, vertical_sync_start,		vertical_sync_end, vertical_total, vertical_blanking_start,		vertical_blanking_end;			uint32 wd; // CRTC offset	memset(&mod, 0, sizeof(mode));		mode = &mod;	    wd = (dm->timing.h_display >> 3) - 1;	horizontal_display_end  = (dm->timing.h_display >> 3) - 1;	horizontal_sync_start  = (dm->timing.h_sync_start >> 3) - 1;	horizontal_sync_end  = (dm->timing.h_sync_end >> 3) - 1;	horizontal_total  = (dm->timing.h_total   >> 3) - 1;	horizontal_blanking_start = horizontal_display_end;	horizontal_blanking_end = horizontal_total;	vertical_display_enable_end  = dm->timing.v_display - 1;	vertical_sync_start  = dm->timing.v_sync_start;// - 1;	vertical_sync_end  = dm->timing.v_sync_end;// - 1;	vertical_total  = dm->timing.v_total   - 2;	vertical_blanking_start = vertical_display_enable_end;	vertical_blanking_end = vertical_total;		mode->misc =     0x0f |    (dm->timing.h_display < 400 ? 0xa0 :     dm->timing.h_display < 480 ? 0x60 :     dm->timing.h_display < 768 ? 0xe0 : 0x20);         mode->seq_regs[0] = 3;    mode->seq_regs[1] = 1;    mode->seq_regs[2] = 8;    mode->seq_regs[3] = 0;    mode->seq_regs[4] = 6;        // crtc regs start    mode->crtc_regs[0] = horizontal_total - 4;    mode->crtc_regs[1] = horizontal_display_end;    mode->crtc_regs[2] = horizontal_blanking_start;    mode->crtc_regs[3] = 0x80 | (horizontal_blanking_end & 0x1f);    mode->crtc_regs[4] = horizontal_sync_start;        mode->crtc_regs[5] = ((horizontal_blanking_end & 0x20) << 2) | (horizontal_sync_end & 0x1f);    mode->crtc_regs[6] = vertical_total;    mode->crtc_regs[7] = ((vertical_sync_start & 0x200) >> 2) |    ((vertical_display_enable_end & 0x200) >> 3) |    ((vertical_total & 0x200) >> 4) |    0x10 |    ((vertical_blanking_start & 0x100) >> 5) |    ((vertical_sync_start  & 0x100) >> 6) |    ((vertical_display_enable_end  & 0x100) >> 7) |    ((vertical_total  & 0x100) >> 8);        mode->crtc_regs[8] = 0;    mode->crtc_regs[9] = 0x40 |    ((vertical_blanking_start & 0x200) >> 4);        mode->crtc_regs[10] = 0;    mode->crtc_regs[11] = 0;    mode->crtc_regs[12] = 0;    mode->crtc_regs[13] = 0;    mode->crtc_regs[14] = 0;    mode->crtc_regs[15] = 0;        mode->crtc_regs[16] = vertical_sync_start;    mode->crtc_regs[17] = (vertical_sync_end & 0x0f) | 0x20;    mode->crtc_regs[18] = vertical_display_enable_end;    mode->crtc_regs[19] = wd; // CRTC offset    mode->crtc_regs[20] = 0;    mode->crtc_regs[21] = vertical_blanking_start;        mode->crtc_regs[22] = vertical_blanking_end + 1;    mode->crtc_regs[23] = 128;    mode->crtc_regs[24] = 255;        // attr regs start    mode->attr_regs[0] = 0;    mode->attr_regs[1] = 0;    mode->attr_regs[2] = 0;    mode->attr_regs[3] = 0;    mode->attr_regs[4] = 0;    mode->attr_regs[5] = 0;        mode->attr_regs[6] = 0;    mode->attr_regs[7] = 0;    mode->attr_regs[8] = 0;    mode->attr_regs[9] = 0;    mode->attr_regs[10] = 0;    mode->attr_regs[11] = 0;        mode->attr_regs[12] = 0;    mode->attr_regs[13] = 0;    mode->attr_regs[14] = 0;    mode->attr_regs[15] = 0;    mode->attr_regs[16] = 1;    mode->attr_regs[17] = 0;    mode->attr_regs[18] = 15;    mode->attr_regs[19] = 0;    // attr regs end        // graph regs start    mode->graph_regs[0] = 159;    mode->graph_regs[1] = 127;    mode->graph_regs[2] = 127;    mode->graph_regs[3] = 131;    mode->graph_regs[4] = 130;    mode->graph_regs[5] = 142;    mode->graph_regs[6] = 30;    mode->graph_regs[7] = 245;    mode->graph_regs[8] = 0;	vga_outb(MISC_W, mode->misc | 0x01);    	for(i = 0; i < 5; i++)		write_seq_registers(i, mode->seq_regs[i]);    for (i = 0; i < 0x19; i ++)        write_crt_registers(i, mode->crtc_regs[i]);    for (i = 0; i < 0x14; i ++)        write_attr_registers(i, mode->attr_regs[i]);    for (i = 0; i < 0x09; i ++)        write_graph_registers(i, mode->graph_regs[i]);}