add: CRTC2W(BUFFER, 0xff);
context: status_t nv_general_bios_to_powergraphics(){	LOG(2, ("INIT: Skipping card coldstart!\n"));	/* let acc engine make power off/power on cycle to start 'fresh' */	NV_REG32(NV32_PWRUPCTRL) = 0x13110011;	snooze(1000);	/* power-up all nvidia hardware function blocks */	/* bit 28: OVERLAY ENGINE (BES),	 * bit 25: CRTC2, (> NV04A)	 * bit 24: CRTC1,	 * bit 20: framebuffer,	 * bit 16: PPMI,	 * bit 12: PGRAPH,	 * bit  8: PFIFO,	 * bit  4: PMEDIA,	 * bit  0: TVOUT. (> NV04A) */	NV_REG32(NV32_PWRUPCTRL) = 0x13111111;	/* select colormode CRTC registers base adresses */	NV_REG8(NV8_MISCW) = 0xcb;	/* unlock card registers for R/W access */	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);	CRTCW(LOCK, 0x57);	CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));	if (si->ps.secondary_head)	{		CRTC2W(OWNER, 0x03);		CRTC2W(LOCK, 0x57);		CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));	}	/* turn off both displays and the hardcursors (also disables transfers) */	nv_crtc_dpms(false, false, false);	nv_crtc_cursor_hide();	if (si->ps.secondary_head)	{		nv_crtc2_dpms(false, false, false);		nv_crtc2_cursor_hide();	}	if (si->ps.secondary_head)	{		/* switch overlay engine to CRTC1 */		/* bit 12: overlay engine,		 * bit  8: TVout chip (fixme: or bit 4?),		 * bit  4: DDC channel (fixme: or bit 8?) */		NV_REG32(NV32_2FUNCSEL) &= ~0x00001000;		NV_REG32(NV32_FUNCSEL) |= 0x00001000;	}	si->overlay.crtc = 0;	/* enable 'enhanced' mode on primary head: */	/* enable access to primary head */	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);	/* don't doublebuffer CRTC access: set programmed values immediately;	 * keep fine pitched CRTC granularity on > NV4 cards (b2 = 0) */	CRTCW(BUFFER, 0xfb);	/* select VGA mode (old VGA register) */	CRTCW(MODECTL, 0xc3);	/* select graphics mode (old VGA register) */	SEQW(MEMMODE, 0x0e);	/* select 8 dots character clocks (old VGA register) */	SEQW(CLKMODE, 0x21);	/* select VGA mode (old VGA register) */	GRPHW(MODE, 0x00);	/* select graphics mode (old VGA register) */	GRPHW(MISC, 0x01);	/* select graphics mode (old VGA register) */	ATBW(MODECTL, 0x01);	/* enable 'enhanced mode', enable Vsync & Hsync,	 * set DAC palette to 8-bit width, disable large screen */	CRTCW(REPAINT1, 0x04);	/* enable 'enhanced' mode on secondary head: */	if (si->ps.secondary_head)	{		/* enable access to secondary head (is SEQ2, GRPH2, CRTC2, ATB2, etc!!) */		CRTC2W(OWNER, 0x03);		/* select colormode CRTC2 registers base adresses */		NV_REG8(NV8_MISCW) = 0xcb;		/* don't doublebuffer CRTC2 access: set programmed values immediately;		 * keep fine pitched CRTC2 granularity (b2 = 0) */		CRTC2W(BUFFER, 0xfb);		/* select VGA mode (old VGA register) */		CRTC2W(MODECTL, 0xc3);		/* select graphics mode (old VGA register) */		SEQW(MEMMODE, 0x0e);		/* select 8 dots character clocks (old VGA register) */		SEQW(CLKMODE, 0x21);		/* select VGA mode (old VGA register) */		GRPHW(MODE, 0x00);		/* select graphics mode (old VGA register) */		GRPHW(MISC, 0x01);		/* select graphics mode (old VGA register) */		ATB2W(MODECTL, 0x01);		/* enable 'enhanced mode', enable Vsync & Hsync,		 * set DAC palette to 8-bit width, disable large screen */		CRTC2W(REPAINT1, 0x04);	}	/* enable palettes */	DACW(GENCTRL, 0x00100100);	if (si->ps.secondary_head) DAC2W(GENCTRL, 0x00100100);	/* enable programmable PLLs */	DACW(PLLSEL, 0x10000700);	if (si->ps.secondary_head) DACW(PLLSEL, (DACR(PLLSEL) | 0x20000800));	/* turn on DAC and make sure detection testsignal routing is disabled	 * (b16 = disable DAC,	 *  b12 = enable testsignal output */	DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeefff));	/* turn on DAC2 if it exists	 * (NOTE: testsignal function block resides in DAC1 only (!)) */	if (si->ps.secondary_head) DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeefff));	/* turn screen one on */	nv_crtc_dpms(true, true, true);	return B_OK;}