add: pci_config_teardown(&config_handle);
context: pcie_initchild(dev_info_t *cdip){	ddi_acc_handle_t	config_handle;	uint8_t			header_type;	uint8_t			bcr;	uint16_t		command_reg;	uint16_t		cap_ptr;	if (pci_config_setup(cdip, &config_handle) != DDI_SUCCESS)		return (DDI_FAILURE);	/*	 * Determine the configuration header type.	 */	header_type = pci_config_get8(config_handle, PCI_CONF_HEADER);	PCIE_DBG("%s: header_type=%x\n", ddi_driver_name(cdip), header_type);	/*	 * Setup the device's command register	 */	command_reg = pci_config_get16(config_handle, PCI_CONF_COMM);	command_reg |= pcie_command_default;	pci_config_put16(config_handle, PCI_CONF_COMM, command_reg);	PCIE_DBG("%s: command=%x\n", ddi_driver_name(cdip),	    pci_config_get16(config_handle, PCI_CONF_COMM));	/*	 * If the device has a bus control register then program it	 * based on the settings in the command register.	 */	if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) {		bcr = pci_config_get8(config_handle, PCI_BCNF_BCNTRL);		if (pcie_command_default & PCI_COMM_PARITY_DETECT)			bcr |= PCI_BCNF_BCNTRL_PARITY_ENABLE;		if (pcie_command_default & PCI_COMM_SERR_ENABLE)			bcr |= PCI_BCNF_BCNTRL_SERR_ENABLE;		bcr |= PCI_BCNF_BCNTRL_MAST_AB_MODE;		pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr);	}	cap_ptr = pcie_find_cap_reg(config_handle, PCI_CAP_ID_PCI_E);	if (cap_ptr != PCI_CAP_NEXT_PTR_NULL)		pcie_enable_errors(cdip, config_handle);	return (DDI_SUCCESS);fail:	cmn_err(CE_WARN, "PCIE init child failed\n");	return (DDI_FAILURE);}