rem: (target.timing.h_display * ((1 << 12) / ((float)iscale_x))))
add: ((target.timing.h_display * (1 << 12)) / iscale_x))
context: status_t nv_crtc2_set_timing(display_mode target){	uint8 temp;	uint32 htotal;		/*total horizontal total VCLKs*/	uint32 hdisp_e;            /*end of horizontal display (begins at 0)*/	uint32 hsync_s;            /*begin of horizontal sync pulse*/	uint32 hsync_e;            /*end of horizontal sync pulse*/	uint32 hblnk_s;            /*begin horizontal blanking*/	uint32 hblnk_e;            /*end horizontal blanking*/	uint32 vtotal;		/*total vertical total scanlines*/	uint32 vdisp_e;            /*end of vertical display*/	uint32 vsync_s;            /*begin of vertical sync pulse*/	uint32 vsync_e;            /*end of vertical sync pulse*/	uint32 vblnk_s;            /*begin vertical blanking*/	uint32 vblnk_e;            /*end vertical blanking*/	uint32 linecomp;	/*split screen and vdisp_e interrupt*/	LOG(4,("CRTC2: setting timing\n"));	/* setup tuned internal modeline for flatpanel if connected and active */	/* notes:	 * - the CRTC modeline must end earlier than the panel modeline to keep correct	 *   sync going;	 * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel	 *   wide horizontal stripes. This can be observed earliest on fullscreen overlay,	 *   and if it gets worse, also normal desktop output will suffer. The stripes	 *   are mainly visible at the left of the screen, over the entire screen height. */	if (si->ps.tmds2_active)	{		LOG(2,("CRTC2: DFP active: tuning modeline\n"));		/* horizontal timing */		target.timing.h_sync_start =			((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) *			target.timing.h_display)) & 0xfff8;		target.timing.h_sync_end =			((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) *			target.timing.h_display)) & 0xfff8;		target.timing.h_total =			(((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) *			target.timing.h_display)) & 0xfff8) - 8;		/* in native mode the CRTC needs some extra time to keep synced correctly;		 * OTOH the overlay unit distorts if we reserve too much time! */		if (target.timing.h_display == si->ps.p2_timing.h_display)		{			/* NV11 timing has different constraints than later cards */			if (si->ps.card_type == NV11)				target.timing.h_total -= 56;			else				/* confirmed NV34 with 1680x1050 panel */				target.timing.h_total -= 32;		}		if (target.timing.h_sync_start == target.timing.h_display)			target.timing.h_sync_start += 8;		if (target.timing.h_sync_end == target.timing.h_total)			target.timing.h_sync_end -= 8;		/* vertical timing */		target.timing.v_sync_start =			((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) *			target.timing.v_display));		target.timing.v_sync_end =			((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) *			target.timing.v_display));		target.timing.v_total =			((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) *			target.timing.v_display)) - 1;		if (target.timing.v_sync_start == target.timing.v_display)			target.timing.v_sync_start += 1;		if (target.timing.v_sync_end == target.timing.v_total)			target.timing.v_sync_end -= 1;		/* disable GPU scaling testmode so automatic scaling will be done */		DAC2W(FP_DEBUG1, 0);	}	/* Modify parameters as required by standard VGA */	htotal = ((target.timing.h_total >> 3) - 5);	hdisp_e = ((target.timing.h_display >> 3) - 1);	hblnk_s = hdisp_e;	hblnk_e = (htotal + 4);//0;	hsync_s = (target.timing.h_sync_start >> 3);	hsync_e = (target.timing.h_sync_end >> 3);	vtotal = target.timing.v_total - 2;	vdisp_e = target.timing.v_display - 1;	vblnk_s = vdisp_e;	vblnk_e = (vtotal + 1);	vsync_s = target.timing.v_sync_start;//-1;	vsync_e = target.timing.v_sync_end;//-1;	/* prevent memory adress counter from being reset (linecomp may not occur) */	linecomp = target.timing.v_display;	/* enable access to secondary head */	set_crtc_owner(1);	/* Note for laptop and DVI flatpanels:	 * CRTC timing has a seperate set of registers from flatpanel timing.	 * The flatpanel timing registers have scaling registers that are used to match	 * these two modelines. */	{		LOG(4,("CRTC2: Setting full timing...\n"));		/* log the mode that will be set */		LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e));		LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e));		/* actually program the card! */		/* unlock CRTC registers at index 0-7 */		CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f));		/* horizontal standard VGA regs */		CRTC2W(HTOTAL, (htotal & 0xff));		CRTC2W(HDISPE, (hdisp_e & 0xff));		CRTC2W(HBLANKS, (hblnk_s & 0xff));		/* also unlock vertical retrace registers in advance */		CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80));		CRTC2W(HSYNCS, (hsync_s & 0xff));		CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2)));		/* vertical standard VGA regs */		CRTC2W(VTOTAL, (vtotal & 0xff));		CRTC2W(OVERFLOW,		(			((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) |			((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) |			((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) |			((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4))		));		CRTC2W(PRROWSCN, 0x00); /* not used */		CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6))));		CRTC2W(VSYNCS, (vsync_s & 0xff));		CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f)));		CRTC2W(VDISPE, (vdisp_e & 0xff));		CRTC2W(VBLANKS, (vblnk_s & 0xff));		CRTC2W(VBLANKE, (vblnk_e & 0xff));		CRTC2W(LINECOMP, (linecomp & 0xff));		/* horizontal extended regs */		//fixme: we reset bit4. is this correct??		CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) |			(		 	((htotal & 0x100) >> (8 - 0)) |			((hdisp_e & 0x100) >> (8 - 1)) |			((hblnk_s & 0x100) >> (8 - 2)) |			((hsync_s & 0x100) >> (8 - 3))			));		/* (mostly) vertical extended regs */		CRTC2W(LSR,			(		 	((vtotal & 0x400) >> (10 - 0)) |			((vdisp_e & 0x400) >> (10 - 1)) |			((vsync_s & 0x400) >> (10 - 2)) |			((vblnk_s & 0x400) >> (10 - 3)) |			((hblnk_e & 0x040) >> (6 - 4))			//fixme: we still miss one linecomp bit!?! is this it??			//| ((linecomp & 0x400) >> 3)				));		/* more vertical extended regs */		CRTC2W(EXTRA,			(		 	((vtotal & 0x800) >> (11 - 0)) |			((vdisp_e & 0x800) >> (11 - 2)) |			((vsync_s & 0x800) >> (11 - 4)) |			((vblnk_s & 0x800) >> (11 - 6))			//fixme: do we miss another linecomp bit!?!			));		/* setup 'large screen' mode */		if (target.timing.h_display >= 1280)			CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb));		else			CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04));		/* setup HSYNC & VSYNC polarity */		LOG(2,("CRTC2: sync polarity: "));		temp = NV_REG8(NV8_MISCR);		if (target.timing.flags & B_POSITIVE_HSYNC)		{			LOG(2,("H:pos "));			temp &= ~0x40;		}		else		{			LOG(2,("H:neg "));			temp |= 0x40;		}		if (target.timing.flags & B_POSITIVE_VSYNC)		{			LOG(2,("V:pos "));			temp &= ~0x80;		}		else		{			LOG(2,("V:neg "));			temp |= 0x80;		}		NV_REG8(NV8_MISCW) = temp;		LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR)));	}	/* always disable interlaced operation */	/* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */	CRTC2W(INTERLACE, 0xff);	/* disable CRTC slaved mode unless a panel is in use */	// fixme: this kills TVout when it was in use...	if (!si->ps.tmds2_active) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f));	/* setup flatpanel if connected and active */	if (si->ps.tmds2_active)	{		uint32 iscale_x, iscale_y;		/* calculate inverse scaling factors used by hardware in 20.12 format */		iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display);		iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display);		/* unblock flatpanel timing programming (or something like that..) */		CRTC2W(FP_HTIMING, 0);		CRTC2W(FP_VTIMING, 0);		LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING)));		LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING)));		/* enable full width visibility on flatpanel */		DAC2W(FP_HVALID_S, 0);		DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1));		/* enable full height visibility on flatpanel */		DAC2W(FP_VVALID_S, 0);		DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1));		/* nVidia cards support upscaling except on ??? */		/* NV11 cards can upscale after all! */		if (0)//si->ps.card_type == NV11)		{			/* disable last fetched line limiting */			DAC2W(FP_DEBUG2, 0x00000000);			/* inform panel to scale if needed */			if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12)))			{				LOG(2,("CRTC2: DFP needs to do scaling\n"));				DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100));			}			else			{				LOG(2,("CRTC2: no scaling for DFP needed\n"));				DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff));			}		}		else		{			float dm_aspect;			LOG(2,("CRTC2: GPU scales for DFP if needed\n"));			/* calculate display mode aspect */			dm_aspect = (target.timing.h_display / ((float)target.timing.v_display));			/* limit last fetched line if vertical scaling is done */			if (iscale_y != (1 << 12))				DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16)));			else				DAC2W(FP_DEBUG2, 0x00000000);			/* inform panel not to scale */			DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff));			/* GPU scaling is automatically setup by hardware, so only modify this			 * scalingfactor for non 4:3 (1.33) aspect panels;			 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */			/* correct for widescreen panels relative to mode...			 * (so if panel is more widescreen than mode being set) */			/* BTW: known widescreen panels:			 * 1280 x  800 (1.60),			 * 1440 x  900 (1.60),			 * 1680 x 1050 (1.60),			 * 1920 x 1200 (1.60). */			/* known 4:3 aspect non-standard resolution panels:			 * 1400 x 1050 (1.33). */			/* NOTE:			 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */			if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10)))			{				uint16 diff;				LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n"));				/* X-scaling should be the same as Y-scaling */				iscale_x = iscale_y;				/* enable testmode (b12) and program new X-scaling factor */				DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12)));				/* center/cut-off left and right side of screen */				diff = ((si->ps.p2_timing.h_display -						(target.timing.h_display * ((1 << 12) / ((float)iscale_x))))						/ 2);				DAC2W(FP_HVALID_S, diff);				DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1));			}			/* correct for portrait panels... */			/* NOTE:			 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */			if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10)))			{				LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n"));				/* fixme: implement if this kind of portrait panels exist on nVidia... */			}		}		/* do some logging.. */		LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S)));		LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E)));		LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S)));		LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E)));		LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0)));		LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1)));		LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2)));		LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3)));		LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL)));	}	return B_OK;}