rem: temp = (ATBR(HORPIXPAN) & 0xf9); ATBW(HORPIXPAN, (temp | ((startadd & 0x00000003) << 1)));
add: ATBW(HORPIXPAN, ((startadd & 0x00000003) << 1));
context: status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp) {	uint8 temp;	LOG(4,("CRTC: setting card RAM to be displayed bpp %d\n", bpp));	LOG(2,("CRTC: startadd: $%08x\n", startadd));	LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer));	LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer));	/* retrace sync not needed here: doublebuffering in hardware */	/* enable access to CRTC1 on dualhead cards */	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);	if (si->ps.card_arch == NV04A)	{		/* upto 32Mb RAM adressing: must be used this way on pre-NV10! */		/* set standard registers */		/* (NVidia: startadress in 32bit words (b2 - b17) */		CRTCW(FBSTADDL, ((startadd & 0x000003fc) >> 2));		CRTCW(FBSTADDH, ((startadd & 0x0003fc00) >> 10));		/* set extended registers */		/* NV4 extended bits: (b18-22) */		temp = (CRTCR(REPAINT0) & 0xe0);		CRTCW(REPAINT0, (temp | ((startadd & 0x007c0000) >> 18)));		/* NV4 extended bits: (b23-24) */		temp = (CRTCR(HEB) & 0x9f);		CRTCW(HEB, (temp | ((startadd & 0x01800000) >> 18)));	}	else	{		/* upto 4Gb RAM adressing: must be used on NV10 and later! */		/* NOTE:		 * While this register also exists on pre-NV10 cards, it will		 * wrap-around at 16Mb boundaries!! */		/* 30bit adress in 32bit words */		NV_REG32(NV32_NV10FBSTADD32) = (startadd & 0xfffffffc);	}	/* set NV4/NV10 byte adress: (b0 - 1) */	temp = (ATBR(HORPIXPAN) & 0xf9);	ATBW(HORPIXPAN, (temp | ((startadd & 0x00000003) << 1)));	return B_OK;}