rem: case PCI_PRODUCT_INTEL_82845_AGP: {  uint8 ctrl = read_pci_config(bus, dev, func, 0x3e, 1);  if ((ctrl & 0x04) != 0x04) { dprintf("Enabling VGA_EN1 for Intel 82845 AGP Bridge\n"); ctrl |= 0x04; write_pci_config(bus, dev, func, 0x3e, 1, ctrl); } }
context: fixup_bridge(uint8 bus, uint8 dev, uint8 func){	uint16 vendor, device;		vendor = read_pci_config(bus, dev, func, PCI_vendor_id, 2);	device = read_pci_config(bus, dev, func, PCI_device_id, 2);		switch (vendor) {		case PCI_VENDOR_INTEL:			switch (device) {				case PCI_PRODUCT_INTEL_82443BX_AGP:				case PCI_PRODUCT_INTEL_82443BX_NOAGP: {					/* BIOS bug workaround					 * While the datasheet indicates that the only valid setting					 * for "Idle/Pipeline DRAM Leadoff Timing (IPLDT)" is 01,					 * some BIOS's do not set these correctly, so we check and 					 * correct if required.					 */					uint16 bcreg = read_pci_config(bus, dev, func, 0x76, 2);					if ((bcreg & 0x0300) != 0x0100) {						dprintf("Intel 82443BX Host Bridge: Fixing IPDLT setting\n");						bcreg &= ~0x0300;						bcreg |= 0x100;						write_pci_config(bus, dev, func, 0x76, 2, bcreg);					}					break;				}				case PCI_PRODUCT_INTEL_82845_AGP: {					/* Foward accesses to VGA memory onto the AGP card					 *					 * This is very experimental! Added to see if this will					 * fix Marcus's problem with this device.					 */					uint8 ctrl = read_pci_config(bus, dev, func, 0x3e, 1);										if ((ctrl & 0x04) != 0x04) {						dprintf("Enabling VGA_EN1 for Intel 82845 AGP Bridge\n");						ctrl |= 0x04;						write_pci_config(bus, dev, func, 0x3e, 1, ctrl);					}				}			}	}}