rem: DEBUGOUT("Error getting link speed and duplex\n");
add: HW_DEBUGOUT("Error getting link speed and duplex");
context: em_config_dsp_after_link_change(struct em_hw *hw,                                   boolean_t link_up){    int32_t ret_val;    uint16_t phy_data, speed, duplex, i;    uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =                                        {IGP01E1000_PHY_AGC_PARAM_A,                                        IGP01E1000_PHY_AGC_PARAM_B,                                        IGP01E1000_PHY_AGC_PARAM_C,                                        IGP01E1000_PHY_AGC_PARAM_D};    uint16_t min_length, max_length;    DEBUGFUNC("em_config_dsp_after_link_change");    if(hw->phy_type != em_phy_igp)        return E1000_SUCCESS;    if(link_up) {        if((ret_val = em_get_speed_and_duplex(hw, &speed, &duplex))) {            DEBUGOUT("Error getting link speed and duplex\n");            return ret_val;        }        if(speed == SPEED_1000) {            em_get_cable_length(hw, &min_length, &max_length);            if((hw->dsp_config_state == em_dsp_config_enabled) &&                min_length >= em_igp_cable_length_50) {                for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {                    if((ret_val = em_read_phy_reg(hw, dsp_reg_array[i],                                                     &phy_data)))                        return ret_val;                    phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;                    if((ret_val = em_write_phy_reg(hw, dsp_reg_array[i],                                                      phy_data)))                        return ret_val;                }                hw->dsp_config_state = em_dsp_config_activated;            }            if((hw->ffe_config_state == em_ffe_config_enabled) &&               (min_length < em_igp_cable_length_50)) {                uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;                uint32_t idle_errs = 0;                /* clear previous idle error counts */                if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,                                                 &phy_data)))                    return ret_val;                for(i = 0; i < ffe_idle_err_timeout; i++) {                    usec_delay(1000);                    if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,                                                     &phy_data)))                        return ret_val;                    idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);                    if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {                        hw->ffe_config_state = em_ffe_config_active;                        if((ret_val = em_write_phy_reg(hw,                                    IGP01E1000_PHY_DSP_FFE,                                    IGP01E1000_PHY_DSP_FFE_CM_CP)))                            return ret_val;                        break;                    }                    if(idle_errs)                        ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;                }            }        }    } else {        if(hw->dsp_config_state == em_dsp_config_activated) {            if((ret_val = em_write_phy_reg(hw, 0x0000,                IGP01E1000_IEEE_FORCE_GIGA)))                return ret_val;            for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {                if((ret_val = em_read_phy_reg(hw, dsp_reg_array[i],                                                 &phy_data)))                    return ret_val;                phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;                phy_data |=  IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;                if((ret_val = em_write_phy_reg(hw,dsp_reg_array[i],                                                  phy_data)))                    return ret_val;            }            if((ret_val = em_write_phy_reg(hw, 0x0000,                                              IGP01E1000_IEEE_RESTART_AUTONEG)))                return ret_val;            hw->dsp_config_state = em_dsp_config_enabled;        }        if(hw->ffe_config_state == em_ffe_config_active) {            if((ret_val = em_write_phy_reg(hw, 0x0000,                                              IGP01E1000_IEEE_FORCE_GIGA)))                return ret_val;            if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,                                              IGP01E1000_PHY_DSP_FFE_DEFAULT)))                return ret_val;            if((ret_val = em_write_phy_reg(hw, 0x0000,                                              IGP01E1000_IEEE_RESTART_AUTONEG)))                return ret_val;        hw->ffe_config_state = em_ffe_config_enabled;        }    }    return E1000_SUCCESS;}