rem: CRTCW(BUFFER, 0xff);
add: CRTCW(BUFFER, 0xfb);
context: static status_t nv_general_bios_to_powergraphics(){	LOG(2, ("INIT: Skipping card coldstart!\n"));	/* let acc engine make power off/power on cycle to start 'fresh' */	NV_REG32(NV32_PWRUPCTRL) = 0x13110011;	snooze(1000);	/* power-up all nvidia hardware function blocks */	/* bit 28: OVERLAY ENGINE (BES),	 * bit 25: CRTC2, (> NV04A)	 * bit 24: CRTC1,	 * bit 20: framebuffer,	 * bit 16: PPMI,	 * bit 12: PGRAPH,	 * bit  8: PFIFO,	 * bit  4: PMEDIA,	 * bit  0: TVOUT. (> NV04A) */	NV_REG32(NV32_PWRUPCTRL) = 0x13111111;	/* select colormode CRTC registers base adresses */	NV_REG8(NV8_MISCW) = 0xcb;	/* enable access to primary head */	set_crtc_owner(0);	/* unlock head's registers for R/W access */	CRTCW(LOCK, 0x57);	CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));	if (si->ps.secondary_head)	{		/* enable access to secondary head */		set_crtc_owner(1);		/* unlock head's registers for R/W access */		CRTC2W(LOCK, 0x57);		CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));	}	/* turn off both displays and the hardcursors (also disables transfers) */	head1_dpms(false, false, false);	head1_cursor_hide();	if (si->ps.secondary_head)	{		head2_dpms(false, false, false);		head2_cursor_hide();	}	if (si->ps.secondary_head)	{		/* switch overlay engine to CRTC1 */		/* bit 17: GPU FP port #1	(confirmed NV25, NV28, confirmed not on NV34),		 * bit 16: GPU FP port #2	(confirmed NV25, NV28, NV34),		 * bit 12: overlay engine	(all cards),		 * bit  9: TVout chip #2	(confirmed on NV18, NV25, NV28),		 * bit  8: TVout chip #1	(all cards),		 * bit  4: both I2C busses	(all cards) */		NV_REG32(NV32_2FUNCSEL) &= ~0x00001000;		NV_REG32(NV32_FUNCSEL) |= 0x00001000;	}	si->overlay.crtc = false;	/* enable 'enhanced' mode on primary head: */	/* enable access to primary head */	set_crtc_owner(0);	/* note: 'BUFFER' is a non-standard register in behaviour(!) on most	 * NV11's like the GeForce2 MX200, while the MX400 and non-NV11 cards	 * behave normally.	 * Also readback is not nessesarily what was written before!	 *	 * Double-write action needed on those strange NV11 cards: */	/* RESET: don't doublebuffer CRTC access: set programmed values immediately... */	CRTCW(BUFFER, 0xff);	/* ... and don't use fine pitched CRTC granularity on > NV4 cards (b2 = 1) */	/* note:	 * the higher-pitched CRTC granularity optimizes use of bandwidth so	 * less cards with trouble remain. Confirmed NV15 (GeForce2 Ti500). */	CRTCW(BUFFER, 0xff);	/* select VGA mode (old VGA register) */	CRTCW(MODECTL, 0xc3);	/* select graphics mode (old VGA register) */	SEQW(MEMMODE, 0x0e);	/* select 8 dots character clocks (old VGA register) */	SEQW(CLKMODE, 0x21);	/* select VGA mode (old VGA register) */	GRPHW(MODE, 0x00);	/* select graphics mode (old VGA register) */	GRPHW(MISC, 0x01);	/* select graphics mode (old VGA register) */	ATBW(MODECTL, 0x01);	/* enable 'enhanced mode', enable Vsync & Hsync,	 * set DAC palette to 8-bit width, disable large screen */	CRTCW(REPAINT1, 0x04);	/* enable 'enhanced' mode on secondary head: */	if (si->ps.secondary_head)	{		/* enable access to secondary head */		set_crtc_owner(1);		/* select colormode CRTC2 registers base adresses */		NV_REG8(NV8_MISCW) = 0xcb;		/* note: 'BUFFER' is a non-standard register in behaviour(!) on most		 * NV11's like the GeForce2 MX200, while the MX400 and non-NV11 cards		 * behave normally.		 * Also readback is not nessesarily what was written before!		 *		 * Double-write action needed on those strange NV11 cards: */		/* RESET: don't doublebuffer CRTC2 access: set programmed values immediately... */		CRTC2W(BUFFER, 0xff);		/* ... and don't use fine pitched CRTC granularity on > NV4 cards (b2 = 1) */		/* note:		 * the higher-pitched CRTC granularity optimizes use of bandwidth so		 * less cards with trouble remain. Confirmed NV15 (GeForce2 Ti500). */		CRTC2W(BUFFER, 0xff);		/* select VGA mode (old VGA register) */		CRTC2W(MODECTL, 0xc3);		/* select graphics mode (old VGA register) */		SEQW(MEMMODE, 0x0e);		/* select 8 dots character clocks (old VGA register) */		SEQW(CLKMODE, 0x21);		/* select VGA mode (old VGA register) */		GRPHW(MODE, 0x00);		/* select graphics mode (old VGA register) */		GRPHW(MISC, 0x01);		/* select graphics mode (old VGA register) */		ATB2W(MODECTL, 0x01);		/* enable 'enhanced mode', enable Vsync & Hsync,		 * set DAC palette to 8-bit width, disable large screen */		CRTC2W(REPAINT1, 0x04);	}	/* enable palettes */	DACW(GENCTRL, 0x00100100);	if (si->ps.secondary_head) DAC2W(GENCTRL, 0x00100100);	/* enable programmable PLLs */	DACW(PLLSEL, 0x10000700);	if (si->ps.secondary_head) DACW(PLLSEL, (DACR(PLLSEL) | 0x20000800));	/* turn on DAC and make sure detection testsignal routing is disabled	 * (b16 = disable DAC,	 *  b12 = enable testsignal output */	DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeefff));	/* turn on DAC2 if it exists	 * (NOTE: testsignal function block resides in DAC1 only (!)) */	if (si->ps.secondary_head) DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeefff));	/* setup AGP */	nv_agp_setup();	/* turn screen one on */	head1_dpms(true, true, true);	return B_OK;}