rem: nv_acc_cmd_dma(NV_GENERAL_FIFO_CH1, NV_GENERAL_CMDHANDLE, 1);
add: si->engine.dma.cmdbuffer[si->engine.dma.current++] = (NV_GENERAL_FIFO_CH1 | (1 << 18));
context: void nv_acc_assert_fifo_dma(void){	/* does every engine cmd this accelerant needs have a FIFO channel? */	//fixme: can probably be optimized for both speed and channel selection...	if (!si->engine.fifo.ch_ptr[NV_ROP5_SOLID] ||		!si->engine.fifo.ch_ptr[NV_IMAGE_BLACK_RECTANGLE] ||		!si->engine.fifo.ch_ptr[NV_IMAGE_PATTERN] ||		!si->engine.fifo.ch_ptr[NV4_SURFACE] ||		!si->engine.fifo.ch_ptr[NV_IMAGE_BLIT] ||		!si->engine.fifo.ch_ptr[NV3_GDI_RECTANGLE_TEXT])	{		uint16 cnt;		/* no, wait until the engine is idle before re-assigning the FIFO */		nv_acc_wait_idle_dma();		/* free the FIFO channels we want from the currently assigned cmd's */		si->engine.fifo.ch_ptr[si->engine.fifo.handle[0]] = 0;		si->engine.fifo.ch_ptr[si->engine.fifo.handle[1]] = 0;		si->engine.fifo.ch_ptr[si->engine.fifo.handle[2]] = 0;		si->engine.fifo.ch_ptr[si->engine.fifo.handle[3]] = 0;		si->engine.fifo.ch_ptr[si->engine.fifo.handle[4]] = 0;		si->engine.fifo.ch_ptr[si->engine.fifo.handle[5]] = 0;		/* set new object handles */		si->engine.fifo.handle[0] = NV_ROP5_SOLID;		si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE;		si->engine.fifo.handle[2] = NV_IMAGE_PATTERN;		si->engine.fifo.handle[3] = NV4_SURFACE;		si->engine.fifo.handle[4] = NV_IMAGE_BLIT;		si->engine.fifo.handle[5] = NV3_GDI_RECTANGLE_TEXT;		/* set handle's pointers to their assigned FIFO channels */		/* note:		 * b0-1 aren't used as adressbits. Using b0 to indicate a valid pointer. */		for (cnt = 0; cnt < 0x08; cnt++)		{			si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] =				(0x00000001 + (cnt * 0x00002000));		}		/* program new FIFO assignments */		nv_acc_cmd_dma(NV_GENERAL_FIFO_CH0, NV_GENERAL_CMDHANDLE, 1);		si->engine.dma.cmdbuffer[si->engine.dma.current++] =			(0x80000000 | si->engine.fifo.handle[0]); /* Raster OPeration */		nv_acc_cmd_dma(NV_GENERAL_FIFO_CH1, NV_GENERAL_CMDHANDLE, 1);		si->engine.dma.cmdbuffer[si->engine.dma.current++] =			(0x80000000 | si->engine.fifo.handle[1]); /* Clip */		nv_acc_cmd_dma(NV_GENERAL_FIFO_CH2, NV_GENERAL_CMDHANDLE, 1);		si->engine.dma.cmdbuffer[si->engine.dma.current++] =			(0x80000000 | si->engine.fifo.handle[2]); /* Pattern */		nv_acc_cmd_dma(NV_GENERAL_FIFO_CH3, NV_GENERAL_CMDHANDLE, 1);		si->engine.dma.cmdbuffer[si->engine.dma.current++] =			(0x80000000 | si->engine.fifo.handle[3]); /* 2D Surface */		nv_acc_cmd_dma(NV_GENERAL_FIFO_CH4, NV_GENERAL_CMDHANDLE, 1);		si->engine.dma.cmdbuffer[si->engine.dma.current++] =			(0x80000000 | si->engine.fifo.handle[4]); /* Blit */		nv_acc_cmd_dma(NV_GENERAL_FIFO_CH5, NV_GENERAL_CMDHANDLE, 1);		si->engine.dma.cmdbuffer[si->engine.dma.current++] =			(0x80000000 | si->engine.fifo.handle[5]); /* Bitmap */		/* tell the engine to fetch and execute all (new) commands in the DMA buffer */		nv_start_dma();	}}