rem: || defined(__NeXT__)
add: || defined(__NeXT__)) \ && !(defined(__mc68020_60__) || defined(mc68020_60))
context: 	adcl %3,%0"							\	   : "=r" ((USItype) (sh)),					\	     "=&r" ((USItype) (sl))					\	   : "%0" ((USItype) (ah)),					\	     "g" ((USItype) (bh)),					\	     "%1" ((USItype) (al)),					\	     "g" ((USItype) (bl)))#define sub_ddmmss(sh, sl, ah, al, bh, bl) \  __asm__ ("subl %5,%1	sbbl %3,%0"							\	   : "=r" ((USItype) (sh)),					\	     "=&r" ((USItype) (sl))					\	   : "0" ((USItype) (ah)),					\	     "g" ((USItype) (bh)),					\	     "1" ((USItype) (al)),					\	     "g" ((USItype) (bl)))#if defined (__BIG_ENDIAN__)  /* Accept no memory operands for ix86/big endian target */#define umul_ppmm(w1, w0, u, v) \  __asm__ ("mull %3"							\	   : "=a" ((USItype) (w0)),					\	     "=d" ((USItype) (w1))					\	   : "%0" ((USItype) (u)),					\	     "r" ((USItype) (v)))#define udiv_qrnnd(q, r, n1, n0, d) \  __asm__ ("divl %4"							\	   : "=a" ((USItype) (q)),					\	     "=d" ((USItype) (r))					\	   : "0" ((USItype) (n0)),					\	     "1" ((USItype) (n1)),					\	     "r" ((USItype) (d)))#else#define umul_ppmm(w1, w0, u, v) \  __asm__ ("mull %3"							\	   : "=a" ((USItype) (w0)),					\	     "=d" ((USItype) (w1))					\	   : "%0" ((USItype) (u)),					\	     "rm" ((USItype) (v)))#define udiv_qrnnd(q, r, n1, n0, d) \  __asm__ ("divl %4"							\	   : "=a" ((USItype) (q)),					\	     "=d" ((USItype) (r))					\	   : "0" ((USItype) (n0)),					\	     "1" ((USItype) (n1)),					\	     "rm" ((USItype) (d)))#endif#define count_leading_zeros(count, x) \  do {									\    USItype __cbtmp;							\    __asm__ ("bsrl %1,%0"						\	     : "=r" (__cbtmp) : "rm" ((USItype) (x)));			\    (count) = __cbtmp ^ 31;						\  } while (0)#define UMUL_TIME 40#define UDIV_TIME 40#endif /* 80x86 */#if defined (__i860__)#if 0/* Make sure these patterns really improve the code before   switching them on.  */#define add_ssaaaa(sh, sl, ah, al, bh, bl) \  do {									\    union								\      {									\	DItype __ll;							\	struct {USItype __l, __h;} __i;					\      }  __a, __b, __s;							\    __a.__i.__l = (al);							\    __a.__i.__h = (ah);							\    __b.__i.__l = (bl);							\    __b.__i.__h = (bh);							\    __asm__ ("fiadd.dd %1,%2,%0"					\	     : "=f" (__s.__ll)						\	     : "%f" (__a.__ll), "f" (__b.__ll));			\    (sh) = __s.__i.__h;							\    (sl) = __s.__i.__l;							\    } while (0)#define sub_ddmmss(sh, sl, ah, al, bh, bl) \  do {									\    union								\      {									\	DItype __ll;							\	struct {USItype __l, __h;} __i;					\      }  __a, __b, __s;							\    __a.__i.__l = (al);							\    __a.__i.__h = (ah);							\    __b.__i.__l = (bl);							\    __b.__i.__h = (bh);							\    __asm__ ("fisub.dd %1,%2,%0"					\	     : "=f" (__s.__ll)						\	     : "%f" (__a.__ll), "f" (__b.__ll));			\    (sh) = __s.__i.__h;							\    (sl) = __s.__i.__l;							\    } while (0)#endif#endif /* __i860__ */#if defined (__i960__)#define umul_ppmm(w1, w0, u, v) \  ({union {UDItype __ll;						\	   struct {USItype __l, __h;} __i;				\	  } __xx;							\  __asm__ ("emul	%2,%1,%0"					\	   : "=d" (__xx.__ll)						\	   : "%dI" ((USItype) (u)),					\	     "dI" ((USItype) (v)));					\  (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})#define __umulsidi3(u, v) \  ({UDItype __w;							\    __asm__ ("emul	%2,%1,%0"					\	     : "=d" (__w)						\	     : "%dI" ((USItype) (u)),					\	       "dI" ((USItype) (v)));					\    __w; })  #endif /* __i960__ */#if defined (__M32R__)#define add_ssaaaa(sh, sl, ah, al, bh, bl) \  /* The cmp clears the condition bit.  */ \  __asm__ ("cmp %0,%0	addx %%5,%1	addx %%3,%0"							\	   : "=r" ((USItype) (sh)),					\	     "=&r" ((USItype) (sl))					\	   : "%0" ((USItype) (ah)),					\	     "r" ((USItype) (bh)),					\	     "%1" ((USItype) (al)),					\	     "r" ((USItype) (bl))					\	   : "cbit")#define sub_ddmmss(sh, sl, ah, al, bh, bl) \  /* The cmp clears the condition bit.  */ \  __asm__ ("cmp %0,%0	subx %5,%1	subx %3,%0"							\	   : "=r" ((USItype) (sh)),					\	     "=&r" ((USItype) (sl))					\	   : "0" ((USItype) (ah)),					\	     "r" ((USItype) (bh)),					\	     "1" ((USItype) (al)),					\	     "r" ((USItype) (bl))					\	   : "cbit")#endif /* __M32R__ */#if defined (__mc68000__)#define add_ssaaaa(sh, sl, ah, al, bh, bl) \  __asm__ ("add%.l %5,%1	addx%.l %3,%0"							\	   : "=d" ((USItype) (sh)),					\	     "=&d" ((USItype) (sl))					\	   : "%0" ((USItype) (ah)),					\	     "d" ((USItype) (bh)),					\	     "%1" ((USItype) (al)),					\	     "g" ((USItype) (bl)))#define sub_ddmmss(sh, sl, ah, al, bh, bl) \  __asm__ ("sub%.l %5,%1	subx%.l %3,%0"							\	   : "=d" ((USItype) (sh)),					\	     "=&d" ((USItype) (sl))					\	   : "0" ((USItype) (ah)),					\	     "d" ((USItype) (bh)),					\	     "1" ((USItype) (al)),					\	     "g" ((USItype) (bl)))/* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */#if defined (__mc68020__) || defined(mc68020) \	|| defined(__mc68030__) || defined(mc68030) \	|| defined(__mc68040__) || defined(mc68040) \	|| defined(__mcpu32__) || defined(mcpu32) \	|| defined(__NeXT__)#define umul_ppmm(w1, w0, u, v) \  __asm__ ("mulu%.l %3,%1:%0"						\	   : "=d" ((USItype) (w0)),					\	     "=d" ((USItype) (w1))					\	   : "%0" ((USItype) (u)),					\	     "dmi" ((USItype) (v)))#define UMUL_TIME 45#define udiv_qrnnd(q, r, n1, n0, d) \  __asm__ ("divu%.l %4,%1:%0"						\	   : "=d" ((USItype) (q)),					\	     "=d" ((USItype) (r))					\	   : "0" ((USItype) (n0)),					\	     "1" ((USItype) (n1)),					\	     "dmi" ((USItype) (d)))#define UDIV_TIME 90#define sdiv_qrnnd(q, r, n1, n0, d) \  __asm__ ("divs%.l %4,%1:%0"						\	   : "=d" ((USItype) (q)),					\	     "=d" ((USItype) (r))					\	   : "0" ((USItype) (n0)),					\	     "1" ((USItype) (n1)),					\	     "dmi" ((USItype) (d)))#else /* not mc68020 */#if !defined(__mcf5200__)/* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX.  */#define umul_ppmm(xh, xl, a, b) \  __asm__ ("| Inlined umul_ppmm	move%.l	%2,%/d0	move%.l	%3,%/d1	move%.l	%/d0,%/d2	swap	%/d0	move%.l	%/d1,%/d3	swap	%/d1	move%.w	%/d2,%/d4	mulu	%/d3,%/d4	mulu	%/d1,%/d2	mulu	%/d0,%/d3	mulu	%/d0,%/d1	move%.l	%/d4,%/d0	eor%.w	%/d0,%/d0	swap	%/d0	add%.l	%/d0,%/d2	add%.l	%/d3,%/d2	jcc	1f	add%.l	%#65536,%/d11:	swap	%/d2	moveq	%#0,%/d0	move%.w	%/d2,%/d0	move%.w	%/d4,%/d2	move%.l	%/d2,%1	add%.l	%/d1,%/d0	move%.l	%/d0,%0"						\	   : "=g" ((USItype) (xh)),					\	     "=g" ((USItype) (xl))					\	   : "g" ((USItype) (a)),					\	     "g" ((USItype) (b))					\	   : "d0", "d1", "d2", "d3", "d4")#define UMUL_TIME 100#define UDIV_TIME 400#endif /* not mcf5200 */#endif /* not mc68020 *//* The '020, '030, '040 and '060 have bitfield insns. */#if defined (__mc68020__) || defined(mc68020) \	|| defined(__mc68030__) || defined(mc68030) \	|| defined(__mc68040__) || defined(mc68040) \	|| defined(__mc68060__) || defined(mc68060) \	|| defined(__NeXT__)#define count_leading_zeros(count, x) \  __asm__ ("bfffo %1{%b2:%b2},%0"					\