rem: if (((read & bits) != 0) == set)
add: if (((read & bits) == bits) == set)
context: wait_for_status(int32 bits, bool set){	int8 read;	int32 tries = 100;	TRACE(("wait_write_ctrl(bits = %lx, %s)\n", bits, set ? "set" : "cleared"));	while (tries-- > 0) {		read = gIsa->read_io_8(PS2_PORT_CTRL);		if (((read & bits) != 0) == set)			return B_OK;		spin(100);	}	return B_ERROR;}