rem: ACCW(PR_CTX1_D, 0x00000902);
add: ACCW(PR_CTX1_A, 0x00000902);
context: status_t nv_acc_init_dma(){	uint16 cnt;	uint32 surf_depth, cmd_depth;	/* reset the engine DMA stalls counter */	err = 0;	/* a hanging engine only recovers from a complete power-down/power-up cycle */	NV_REG32(NV32_PWRUPCTRL) = 0x13110011;	snooze(1000);	NV_REG32(NV32_PWRUPCTRL) = 0x13111111;	/* setup PTIMER: */	//fixme? how about NV28 setup as just after coldstarting? (see nv_info.c)	/* set timer numerator to 8 (in b0-15) */	ACCW(PT_NUMERATOR, 0x00000008);	/* set timer denominator to 3 (in b0-15) */	ACCW(PT_DENOMINATR, 0x00000003);	/* disable timer-alarm INT requests (b0) */	ACCW(PT_INTEN, 0x00000000);	/* reset timer-alarm INT status bit (b0) */	ACCW(PT_INTSTAT, 0xffffffff);	/* enable PRAMIN write access on pre NV10 before programming it! */	if (si->ps.card_arch == NV04A)	{		/* set framebuffer config: type = notiling, PRAMIN write access enabled */		NV_REG32(NV32_PFB_CONFIG_0) = 0x00001114;	}	else	{		/* setup acc engine 'source' tile adressranges */		ACCW(NV10_FBTIL0AD, 0);		ACCW(NV10_FBTIL1AD, 0);		ACCW(NV10_FBTIL2AD, 0);		ACCW(NV10_FBTIL3AD, 0);		ACCW(NV10_FBTIL4AD, 0);		ACCW(NV10_FBTIL5AD, 0);		ACCW(NV10_FBTIL6AD, 0);		ACCW(NV10_FBTIL7AD, 0);		ACCW(NV10_FBTIL0ED, (si->ps.memory_size - 1));		ACCW(NV10_FBTIL1ED, (si->ps.memory_size - 1));		ACCW(NV10_FBTIL2ED, (si->ps.memory_size - 1));		ACCW(NV10_FBTIL3ED, (si->ps.memory_size - 1));		ACCW(NV10_FBTIL4ED, (si->ps.memory_size - 1));		ACCW(NV10_FBTIL5ED, (si->ps.memory_size - 1));		ACCW(NV10_FBTIL6ED, (si->ps.memory_size - 1));		ACCW(NV10_FBTIL7ED, (si->ps.memory_size - 1));	}	/*** PRAMIN ***/	/* first clear the entire RAMHT (hash-table) space to a defined state. It turns	 * out at least NV11 will keep the previously programmed handles over resets and	 * power-outages upto about 15 seconds!! Faulty entries might well hang the	 * engine (confirmed on NV11).	 * Note:	 * this behaviour is not very strange: even very old DRAM chips are known to be	 * able to do this, even though you should refresh them every few milliseconds or	 * so. (Large memory cell capacitors, though different cells vary a lot in their	 * capacity.)	 * Of course data validity is not certain by a long shot over this large	 * amount of time.. */	for(cnt = 0; cnt < 0x0400; cnt++)		NV_REG32(NVACC_HT_HANDL_00 + (cnt << 2)) = 0;	/* RAMHT (hash-table) space SETUP FIFO HANDLES */	/* note:	 * 'instance' tells you where the engine command is stored in 'PR_CTXx_x' sets	 * below: instance being b4-19 with baseadress NV_PRAMIN_CTX_0 (0x00700000).	 * That command is linked to the handle noted here. This handle is then used to	 * tell the FIFO to which engine command it is connected!	 * (CTX registers are actually a sort of RAM space.) */	if (si->ps.card_arch >= NV40A)	{		/* (first set) */		ACCW(HT_HANDL_00, (0x80000000 | NV10_CONTEXT_SURFACES_2D)); /* 32bit handle (not used) */		ACCW(HT_VALUE_00, 0x0010114c); /* instance $114c, engine = acc engine, CHID = $00 */		ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */		ACCW(HT_VALUE_01, 0x00101148); /* instance $1148, engine = acc engine, CHID = $00 */		ACCW(HT_HANDL_02, (0x80000000 | NV4_GDI_RECTANGLE_TEXT)); /* 32bit handle */		ACCW(HT_VALUE_02, 0x0010114a); /* instance $114a, engine = acc engine, CHID = $00 */		/* (second set) */		ACCW(HT_HANDL_10, (0x80000000 | NV_ROP5_SOLID)); /* 32bit handle */		ACCW(HT_VALUE_10, 0x00101142); /* instance $1142, engine = acc engine, CHID = $00 */		ACCW(HT_HANDL_11, (0x80000000 | NV_IMAGE_BLACK_RECTANGLE)); /* 32bit handle */		ACCW(HT_VALUE_11, 0x00101144); /* instance $1144, engine = acc engine, CHID = $00 */		ACCW(HT_HANDL_12, (0x80000000 | NV_IMAGE_PATTERN)); /* 32bit handle */		ACCW(HT_VALUE_12, 0x00101146); /* instance $1146, engine = acc engine, CHID = $00 */	}	else	{//dma 3D test:		/* (first set) *///		ACCW(HT_HANDL_00, (0x80000000 | NV1_IMAGE_FROM_CPU)); /* 32bit handle (not used) *///		ACCW(HT_VALUE_00, 0x80011145); /* instance $1145, engine = acc engine, CHID = $00 *///end dma test.		/* (first set) */		ACCW(HT_HANDL_00, (0x80000000 | NV4_SURFACE)); /* 32bit handle */		ACCW(HT_VALUE_00, 0x80011151); /* instance $1151, engine = acc engine, CHID = $00 */		ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */		ACCW(HT_VALUE_01, 0x80011146); /* instance $1146, engine = acc engine, CHID = $00 */		ACCW(HT_HANDL_02, (0x80000000 | NV4_GDI_RECTANGLE_TEXT)); /* 32bit handle */		ACCW(HT_VALUE_02, 0x80011147); /* instance $1147, engine = acc engine, CHID = $00 *///dma 3D tst://outdated (pre-NV04):		ACCW(HT_HANDL_03, (0x80000000 | NV_RENDER_D3D0_TRIANGLE_ZETA)); /* 32bit handle (nolonger used) */		ACCW(HT_VALUE_03, 0x80011148); /* instance $1148, engine = acc engine, CHID = $00 */		/* NV4_ and NV10_DX5_TEXTURE_TRIANGLE should be identical */		ACCW(HT_HANDL_04, (0x80000000 | NV4_DX5_TEXTURE_TRIANGLE)); /* 32bit handle (3D) */		ACCW(HT_VALUE_04, 0x80011149); /* instance $1149, engine = acc engine, CHID = $00 */		/* NV4_ and NV10_DX6_MULTI_TEXTURE_TRIANGLE should be identical */		ACCW(HT_HANDL_05, (0x80000000 | NV4_DX6_MULTI_TEXTURE_TRIANGLE)); /* 32bit handle (not used) */		ACCW(HT_VALUE_05, 0x8001114a); /* instance $114a, engine = acc engine, CHID = $00 */		ACCW(HT_HANDL_06, (0x80000000 | NV1_RENDER_SOLID_LIN)); /* 32bit handle (not used) */		ACCW(HT_VALUE_06, 0x80011150); /* instance $1150, engine = acc engine, CHID = $00 *///end dma tst.		/* (second set) */		ACCW(HT_HANDL_10, (0x80000000 | NV_ROP5_SOLID)); /* 32bit handle */		ACCW(HT_VALUE_10, 0x80011142); /* instance $1142, engine = acc engine, CHID = $00 */		ACCW(HT_HANDL_11, (0x80000000 | NV_IMAGE_BLACK_RECTANGLE)); /* 32bit handle */		ACCW(HT_VALUE_11, 0x80011143); /* instance $1143, engine = acc engine, CHID = $00 */		ACCW(HT_HANDL_12, (0x80000000 | NV_IMAGE_PATTERN)); /* 32bit handle */		ACCW(HT_VALUE_12, 0x80011144); /* instance $1144, engine = acc engine, CHID = $00 *///dma 3D test:		ACCW(HT_HANDL_13, (0x80000000 | NV4_CONTEXT_SURFACES_ARGB_ZS)); /* 32bit handle (3D) */		ACCW(HT_VALUE_13, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 *///end dma test.	}	/* program CTX registers: CTX1 is mostly done later (colorspace dependant) */	/* note:	 * CTX determines which HT handles point to what engine commands. */	/* note also:	 * CTX registers are in fact in the same GPU internal RAM space as the engine's	 * hashtable. This means that stuff programmed in here also survives resets and	 * power-outages! (confirmed NV11) */	if (si->ps.card_arch >= NV40A)	{		/* setup a DMA define for use by command defines below. */		ACCW(PR_CTX0_R, 0x00003000); /* DMA page table present and of linear type;									  * DMA target node is NVM (non-volatile memory?)									  * (instead of doing PCI or AGP transfers) */		ACCW(PR_CTX1_R, (si->ps.memory_size - 1)); /* DMA limit: size is all cardRAM */		ACCW(PR_CTX2_R, ((0x00000000 & 0xfffff000) | 0x00000002));									 /* DMA access type is READ_AND_WRITE;									  * memory starts at start of cardRAM (b12-31):									  * It's adress needs to be at a 4kb boundary! */		ACCW(PR_CTX3_R, 0x00000002); /* unknown (looks like this is rubbish/not needed?) */		/* setup set '0' for cmd NV_ROP5_SOLID */		ACCW(PR_CTX0_0, 0x02080043); /* NVclass $043, patchcfg ROP_AND, nv10+: little endian */		ACCW(PR_CTX1_0, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */		ACCW(PR_CTX2_0, 0x00000000); /* DMA0 and DMA1 instance invalid */		ACCW(PR_CTX3_0, 0x00000000); /* method traps disabled */		ACCW(PR_CTX0_1, 0x00000000); /* extra */		ACCW(PR_CTX1_1, 0x00000000); /* extra */		/* setup set '1' for cmd NV_IMAGE_BLACK_RECTANGLE */		ACCW(PR_CTX0_2, 0x02080019); /* NVclass $019, patchcfg ROP_AND, nv10+: little endian */		ACCW(PR_CTX1_2, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */		ACCW(PR_CTX2_2, 0x00000000); /* DMA0 and DMA1 instance invalid */		ACCW(PR_CTX3_2, 0x00000000); /* method traps disabled */		ACCW(PR_CTX0_3, 0x00000000); /* extra */		ACCW(PR_CTX1_3, 0x00000000); /* extra */		/* setup set '2' for cmd NV_IMAGE_PATTERN */		ACCW(PR_CTX0_4, 0x02080018); /* NVclass $018, patchcfg ROP_AND, nv10+: little endian */		ACCW(PR_CTX1_4, 0x02000000); /* colorspace not set, notify instance is $0200 (b16-31) */		ACCW(PR_CTX2_4, 0x00000000); /* DMA0 and DMA1 instance invalid */		ACCW(PR_CTX3_4, 0x00000000); /* method traps disabled */		ACCW(PR_CTX0_5, 0x00000000); /* extra */		ACCW(PR_CTX1_5, 0x00000000); /* extra */		/* setup set '4' for cmd NV_IMAGE_BLIT */		ACCW(PR_CTX0_6, 0x0208005f); /* NVclass $05f, patchcfg ROP_AND, nv10+: little endian */		ACCW(PR_CTX1_6, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */		ACCW(PR_CTX2_6, 0x00001140); /* DMA0 instance is $1140, DMA1 instance invalid */		ACCW(PR_CTX3_6, 0x00001140); /* method trap 0 is $1140, trap 1 disabled */		ACCW(PR_CTX0_7, 0x00000000); /* extra */		ACCW(PR_CTX1_7, 0x00000000); /* extra */		/* setup set '5' for cmd NV4_GDI_RECTANGLE_TEXT */		ACCW(PR_CTX0_8, 0x0208004a); /* NVclass $04a, patchcfg ROP_AND, nv10+: little endian */		ACCW(PR_CTX1_8, 0x02000000); /* colorspace not set, notify instance is $0200 (b16-31) */		ACCW(PR_CTX2_8, 0x00000000); /* DMA0 and DMA1 instance invalid */		ACCW(PR_CTX3_8, 0x00000000); /* method traps disabled */		ACCW(PR_CTX0_9, 0x00000000); /* extra */		ACCW(PR_CTX1_9, 0x00000000); /* extra */		/* setup set '6' for cmd NV10_CONTEXT_SURFACES_2D */		ACCW(PR_CTX0_A, 0x02080062); /* NVclass $062, nv10+: little endian */		ACCW(PR_CTX1_A, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */		ACCW(PR_CTX2_A, 0x00001140); /* DMA0 instance is $1140, DMA1 instance invalid */		ACCW(PR_CTX3_A, 0x00001140); /* method trap 0 is $1140, trap 1 disabled */		ACCW(PR_CTX0_B, 0x00000000); /* extra */		ACCW(PR_CTX1_B, 0x00000000); /* extra */		/* setup DMA set pointed at by PF_CACH1_DMAI */		ACCW(PR_CTX0_C, 0x00003002); /* DMA page table present and of linear type;									  * DMA class is $002 (b0-11);									  * DMA target node is NVM (non-volatile memory?)									  * (instead of doing PCI or AGP transfers) */		ACCW(PR_CTX1_C, 0x00007fff); /* DMA limit: tablesize is 32k bytes */		ACCW(PR_CTX2_C, (((si->ps.memory_size - 1) & 0xffff8000) | 0x00000002));									 /* DMA access type is READ_AND_WRITE;									  * table is located at end of cardRAM (b12-31):									  * It's adress needs to be at a 4kb boundary! */	}	else	{		/* setup a DMA define for use by command defines below. */		ACCW(PR_CTX0_R, 0x00003000); /* DMA page table present and of linear type;									  * DMA target node is NVM (non-volatile memory?)									  * (instead of doing PCI or AGP transfers) */		ACCW(PR_CTX1_R, (si->ps.memory_size - 1)); /* DMA limit: size is all cardRAM */		ACCW(PR_CTX2_R, ((0x00000000 & 0xfffff000) | 0x00000002));									 /* DMA access type is READ_AND_WRITE;									  * memory starts at start of cardRAM (b12-31):									  * It's adress needs to be at a 4kb boundary! */		ACCW(PR_CTX3_R, 0x00000002); /* unknown (looks like this is rubbish/not needed?) */		/* setup set '0' for cmd NV_ROP5_SOLID */		ACCW(PR_CTX0_0, 0x01008043); /* NVclass $043, patchcfg ROP_AND, nv10+: little endian */		ACCW(PR_CTX1_0, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */		ACCW(PR_CTX2_0, 0x00000000); /* DMA0 and DMA1 instance invalid */		ACCW(PR_CTX3_0, 0x00000000); /* method traps disabled */		/* setup set '1' for cmd NV_IMAGE_BLACK_RECTANGLE */		ACCW(PR_CTX0_1, 0x01008019); /* NVclass $019, patchcfg ROP_AND, nv10+: little endian */		ACCW(PR_CTX1_1, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */		ACCW(PR_CTX2_1, 0x00000000); /* DMA0 and DMA1 instance invalid */		ACCW(PR_CTX3_1, 0x00000000); /* method traps disabled */		/* setup set '2' for cmd NV_IMAGE_PATTERN */		ACCW(PR_CTX0_2, 0x01008018); /* NVclass $018, patchcfg ROP_AND, nv10+: little endian */		ACCW(PR_CTX1_2, 0x00000002); /* colorspace not set, notify instance is $0200 (b16-31) */		ACCW(PR_CTX2_2, 0x00000000); /* DMA0 and DMA1 instance invalid */		ACCW(PR_CTX3_2, 0x00000000); /* method traps disabled *///dma 3D test:		/* setup set '3' for cmd NV1_IMAGE_FROM_CPU (not used) *///		ACCW(PR_CTX0_3, 0x01008021); /* NVclass $021, patchcfg ROP_AND, nv10+: little endian *///		ACCW(PR_CTX1_3, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) *///		ACCW(PR_CTX2_3, 0x00000000); /* DMA0 and DMA1 instance invalid *///		ACCW(PR_CTX3_3, 0x00000000); /* method traps disabled *///end dma test.		/* setup set '4' for cmd NV_IMAGE_BLIT */		ACCW(PR_CTX0_4, 0x0100805f); /* NVclass $05f, patchcfg ROP_AND, nv10+: little endian */		ACCW(PR_CTX1_4, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */		ACCW(PR_CTX2_4, 0x11401140); /* DMA0 instance is $1140, DMA1 instance invalid */		ACCW(PR_CTX3_4, 0x00000000); /* method trap 0 is $1140, trap 1 disabled */		/* setup set '5' for cmd NV4_GDI_RECTANGLE_TEXT */		ACCW(PR_CTX0_5, 0x0100804a); /* NVclass $04a, patchcfg ROP_AND, nv10+: little endian */		ACCW(PR_CTX1_5, 0x00000002); /* colorspace not set, notify instance is $0200 (b16-31) */		ACCW(PR_CTX2_5, 0x00000000); /* DMA0 and DMA1 instance invalid */		ACCW(PR_CTX3_5, 0x00000000); /* method traps disabled *///dma 3D test:		/* setup set '6' for cmd NV_RENDER_D3D0_TRIANGLE_ZETA (nolonger used) */		ACCW(PR_CTX0_6, 0x0100a048); /* NVclass $048, patchcfg ROP_AND, userclip enable,									  * nv10+: little endian */		ACCW(PR_CTX1_6, 0x00000d01); /* format is A8RGB24, MSB mono */		ACCW(PR_CTX2_6, 0x11401140); /* DMA0, DMA1 instance = $1140 */		ACCW(PR_CTX3_6, 0x00000000); /* method traps disabled */		/* setup set '7' ... */		if (si->ps.card_arch != NV04A)		{			/* ... for cmd NV10_DX5_TEXTURE_TRIANGLE */			ACCW(PR_CTX0_7, 0x0300a094); /* NVclass $094, patchcfg ROP_AND, userclip enable,										  * context surface0 valid, nv10+: little endian */		}		else		{			/* ... for cmd NV4_DX5_TEXTURE_TRIANGLE */			ACCW(PR_CTX0_7, 0x0300a054); /* NVclass $054, patchcfg ROP_AND, userclip enable,										  * context surface0 valid */		}		ACCW(PR_CTX1_7, 0x00000d01); /* format is A8RGB24, MSB mono */		ACCW(PR_CTX2_7, 0x11401140); /* DMA0, DMA1 instance = $1140 */		ACCW(PR_CTX3_7, 0x00000000); /* method traps disabled */		/* setup set '8' ... */		if (si->ps.card_arch != NV04A)		{			/* ... for cmd NV10_DX6_MULTI_TEXTURE_TRIANGLE (not used) */			ACCW(PR_CTX0_8, 0x0300a095); /* NVclass $095, patchcfg ROP_AND, userclip enable,										  * context surface0 valid, nv10+: little endian */		}		else		{			/* ... for cmd NV4_DX6_MULTI_TEXTURE_TRIANGLE (not used) */			ACCW(PR_CTX0_8, 0x0300a055); /* NVclass $055, patchcfg ROP_AND, userclip enable,										  * context surface0 valid */		}		ACCW(PR_CTX1_8, 0x00000d01); /* format is A8RGB24, MSB mono */		ACCW(PR_CTX2_8, 0x11401140); /* DMA0, DMA1 instance = $1140 */		ACCW(PR_CTX3_8, 0x00000000); /* method traps disabled */		/* setup set 'D' ... */		if (si->ps.card_arch != NV04A)		{			/* ... for cmd NV10_CONTEXT_SURFACES_ARGB_ZS */			ACCW(PR_CTX0_D, 0x00000093); /* NVclass $093, nv10+: little endian */		}		else		{			/* ... for cmd NV04_CONTEXT_SURFACES_ARGB_ZS */			ACCW(PR_CTX0_D, 0x00000053); /* NVclass $053, nv10+: little endian */		}		ACCW(PR_CTX1_D, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */		ACCW(PR_CTX2_D, 0x11401140); /* DMA0, DMA1 instance = $1140 */		ACCW(PR_CTX3_D, 0x00000000); /* method traps disabled */		/* setup set 'E' for cmd NV1_RENDER_SOLID_LIN (not used) */		ACCW(PR_CTX0_E, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable,									  * context surface0 valid, nv10+: little endian */		ACCW(PR_CTX1_E, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */		ACCW(PR_CTX2_E, 0x11401140); /* DMA0, DMA1 instance = $1140 */		ACCW(PR_CTX3_E, 0x00000000); /* method traps disabled *///end dma tst.		/* setup set 'F' for ... */		if(si->ps.card_arch >= NV10A)		{			/* ... cmd NV10_CONTEXT_SURFACES_2D */			ACCW(PR_CTX0_F, 0x01008062); /* NVclass $062, nv10+: little endian */		}		else		{			/* ... cmd NV4_SURFACE */			ACCW(PR_CTX0_F, 0x01008042); /* NVclass $042, nv10+: little endian */		}		ACCW(PR_CTX1_F, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */		ACCW(PR_CTX2_F, 0x11401140); /* DMA0 instance is $1140, DMA1 instance invalid */		ACCW(PR_CTX3_F, 0x00000000); /* method trap 0 is $1140, trap 1 disabled */		/* setup DMA set pointed at by PF_CACH1_DMAI */		ACCW(PR_CTX0_10, 0x00003002); /* DMA page table present and of linear type;									  * DMA class is $002 (b0-11);									  * DMA target node is NVM (non-volatile memory?)									  * (instead of doing PCI or AGP transfers) */		ACCW(PR_CTX1_10, 0x00007fff); /* DMA limit: tablesize is 32k bytes */		ACCW(PR_CTX2_10, (((si->ps.memory_size - 1) & 0xffff8000) | 0x00000002));									 /* DMA access type is READ_AND_WRITE;									  * table is located at end of cardRAM (b12-31):									  * It's adress needs to be at a 4kb boundary! */		/* NVM DMA is broken on TNT1, so we use PCI-transfers back to the gfxRAM here */		if (si->ps.card_type == NV04)		{			/* DMA target node is PCI */			ACCW(PR_CTX0_10, 0x00023002);			/* point at the DMA buffer via main system memory */			ACCW(PR_CTX2_10, (ACCR(PR_CTX2_10) +				(((uint32)((uint8 *)(si->framebuffer_pci))) & 0xfffff000)));		}//dma 3D test:/*	rud's (temp.) notes:	(problem: 3D driver renders in 32bit whatever the frontbuffer space in DMA mode.)	- the colorspace dependant info under 'acc engine' also sets the outcome for the	  3D add-on. I don't know yet if the 3D render funcs render in the frontbuffer	  space and the back-to-front blit isn't set (stays in 32bit!) (likely),	  or if the 3D funcs render always in 32bit space and back-to-front blit color-	  space converts... I'll try to nail this down asap.	- the colorspace dependant info under 'pramin' is probably needed to get the	  3D related surface commands up and running (still down). Currently the 3D	  add-on has a PIO workaround for these commands only, to get DMA mode up for now.*/		switch(si->dm.space)		{		case B_CMAP8:			/* acc engine */			ACCW(FORMATS, 0x00001010);			if (si->ps.card_arch < NV30A)				/* set depth 0-5: $1 = Y8 */				ACCW(BPIXEL, 0x00111111);			else				/* set depth 0-1: $1 = Y8, $2 = X1R5G5B5_Z1R5G5B5 */				ACCW(BPIXEL, 0x00000021);			ACCW(STRD_FMT, 0x03020202);			/* PRAMIN */			if (si->ps.card_arch == NV04A)			{				ACCW(PR_CTX1_D, 0x00000302); /* format is X24Y8, LSB mono */			}			else			{				ACCW(PR_CTX1_D, 0x00000000); /* format is invalid */				ACCW(PR_CTX1_E, 0x00000302); /* format is X24Y8, LSB mono */			}			break;		case B_RGB15_LITTLE:			/* acc engine */			ACCW(FORMATS, 0x00002071);			if (si->ps.card_arch < NV30A)				/* set depth 0-5: $2 = X1R5G5B5_Z1R5G5B5, $6 = Y16 */				ACCW(BPIXEL, 0x00226222);			else				/* set depth 0-1: $2 = X1R5G5B5_Z1R5G5B5, $4 = A1R5G5B5 */				ACCW(BPIXEL, 0x00000042);			ACCW(STRD_FMT, 0x09080808);			/* PRAMIN */			ACCW(PR_CTX1_D, 0x00000902); /* format is X17RGB15, LSB mono */			if (si->ps.card_arch != NV04A)			{				ACCW(PR_CTX1_E, 0x00000902); /* format is X17RGB15, LSB mono */			}			break;		case B_RGB16_LITTLE:			/* acc engine */			ACCW(FORMATS, 0x000050C2);			if (si->ps.card_arch < NV30A)				/* set depth 0-5: $5 = R5G6B5, $6 = Y16 */				ACCW(BPIXEL, 0x00556555);			else				/* set depth 0-1: $5 = R5G6B5, $a = X1A7R8G8B8_O1A7R8G8B8 */				ACCW(BPIXEL, 0x000000a5);			if (si->ps.card_arch == NV04A)				ACCW(STRD_FMT, 0x0c0b0b0b);			else				ACCW(STRD_FMT, 0x000b0b0c);			/* PRAMIN */			ACCW(PR_CTX1_D, 0x00000c02); /* format is X16RGB16, LSB mono */			if (si->ps.card_arch != NV04A)			{				ACCW(PR_CTX1_E, 0x00000c02); /* format is X16RGB16, LSB mono */			}			break;		case B_RGB32_LITTLE:		case B_RGBA32_LITTLE:			/* acc engine */			ACCW(FORMATS, 0x000070e5);			if (si->ps.card_arch < NV30A)				/* set depth 0-5: $7 = X8R8G8B8_Z8R8G8B8, $d = Y32 */				ACCW(BPIXEL, 0x0077d777);			else				/* set depth 0-1: $7 = X8R8G8B8_Z8R8G8B8, $e = V8YB8U8YA8 */				ACCW(BPIXEL, 0x000000e7);			ACCW(STRD_FMT, 0x0e0d0d0d);			/* PRAMIN */			ACCW(PR_CTX1_D, 0x00000e02); /* format is X8RGB24, LSB mono */			if (si->ps.card_arch >= NV10A)				ACCW(PR_CTX1_E, 0x00000e02); /* format is X8RGB24, LSB mono */			break;		default:			LOG(8,("ACC: init, invalid bit depth\n"));			return B_ERROR;		}//end dma tst.	}	if (si->ps.card_arch == NV04A)	{		/* do a explicit engine reset */		ACCW(DEBUG0, 0x000001ff);		/* init some function blocks */		ACCW(DEBUG0, 0x1230c000);		ACCW(DEBUG1, 0x72111101);		ACCW(DEBUG2, 0x11d5f071);		ACCW(DEBUG3, 0x0004ff31);		/* init OP methods */		ACCW(DEBUG3, 0x4004ff31);		/* disable all acceleration engine INT reguests */		ACCW(ACC_INTE, 0x00000000);		/* reset all acceration engine INT status bits */		ACCW(ACC_INTS, 0xffffffff);		/* context control enabled */		ACCW(NV04_CTX_CTRL, 0x10010100);		/* all acceleration buffers, pitches and colors are valid */		ACCW(NV04_ACC_STAT, 0xffffffff);		/* enable acceleration engine command FIFO */		ACCW(FIFO_EN, 0x00000001);		/* setup location of active screen in framebuffer */		ACCW(OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));		ACCW(OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));		/* setup accesible card memory range */		ACCW(BLIMIT0, (si->ps.memory_size - 1));		ACCW(BLIMIT1, (si->ps.memory_size - 1));		/* pattern shape value = 8x8, 2 color */		//fixme: not needed, unless the engine has a hardware fault (setting via cmd)!		//ACCW(PAT_SHP, 0x00000000);		/* Pgraph Beta AND value (fraction) b23-30 */		ACCW(BETA_AND_VAL, 0xffffffff);	}	else	{		/* do a explicit engine reset */		ACCW(DEBUG0, 0xffffffff);		ACCW(DEBUG0, 0x00000000);		/* disable all acceleration engine INT reguests */		ACCW(ACC_INTE, 0x00000000);		/* reset all acceration engine INT status bits */		ACCW(ACC_INTS, 0xffffffff);		/* context control enabled */		ACCW(NV10_CTX_CTRL, 0x10010100);		/* all acceleration buffers, pitches and colors are valid */		ACCW(NV10_ACC_STAT, 0xffffffff);		/* enable acceleration engine command FIFO */		ACCW(FIFO_EN, 0x00000001);		/* setup surface type */		ACCW(NV10_SURF_TYP, ((ACCR(NV10_SURF_TYP)) & 0x0007ff00));		ACCW(NV10_SURF_TYP, ((ACCR(NV10_SURF_TYP)) | 0x00020100));	}	if (si->ps.card_arch == NV10A)	{		/* init some function blocks */		ACCW(DEBUG1, 0x00118700);		ACCW(DEBUG2, 0x24e00810);		ACCW(DEBUG3, 0x55de0030);		/* copy tile setup stuff from 'source' to acc engine */		for (cnt = 0; cnt < 32; cnt++)		{			NV_REG32(NVACC_NV10_TIL0AD + (cnt << 2)) =				NV_REG32(NVACC_NV10_FBTIL0AD + (cnt << 2));		}		/* setup location of active screen in framebuffer */		ACCW(OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));		ACCW(OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));		/* setup accesible card memory range */		ACCW(BLIMIT0, (si->ps.memory_size - 1));		ACCW(BLIMIT1, (si->ps.memory_size - 1));		/* pattern shape value = 8x8, 2 color */		//fixme: not needed, unless the engine has a hardware fault (setting via cmd)!		//ACCW(PAT_SHP, 0x00000000);		/* Pgraph Beta AND value (fraction) b23-30 */		ACCW(BETA_AND_VAL, 0xffffffff);	}	if (si->ps.card_arch >= NV20A)	{		switch (si->ps.card_arch)		{		case NV40A:			/* init some function blocks */			ACCW(DEBUG1, 0x401287c0);			ACCW(DEBUG3, 0x60de8051);			/* disable specific functions, but enable SETUP_SPARE2 register */			ACCW(NV10_DEBUG4, 0x00008000);			/* set limit_viol_pix_adress(?): more likely something unknown.. */			ACCW(NV25_WHAT0, 0x00be3c5f);			/* unknown.. */			switch (si->ps.card_type)			{			case NV40:			case NV45:				ACCW(NV40_WHAT0, 0x83280fff);				ACCW(NV40_WHAT1, 0x000000a0);				ACCW(NV40_WHAT2, 0x0078e366);				ACCW(NV40_WHAT3, 0x0000014c);				break;			case NV41:				ACCW(NV40P_WHAT0, 0x83280eff);				ACCW(NV40P_WHAT1, 0x000000a0);				ACCW(NV40P_WHAT2, 0x007596ff);				ACCW(NV40P_WHAT3, 0x00000108);				break;			case NV43:				ACCW(NV40P_WHAT0, 0x83280eff);				ACCW(NV40P_WHAT1, 0x000000a0);				ACCW(NV40P_WHAT2, 0x0072cb77);				ACCW(NV40P_WHAT3, 0x00000108);				break;			case NV44:				ACCW(NV40P_WHAT0, 0x83280eff);				ACCW(NV40P_WHAT1, 0x000000a0);				NV_REG32(NV32_NV44_WHAT10) = NV_REG32(NV32_NV10STRAPINFO);				NV_REG32(NV32_NV44_WHAT11) = 0x00000000;				NV_REG32(NV32_NV44_WHAT12) = 0x00000000;				NV_REG32(NV32_NV44_WHAT13) = NV_REG32(NV32_NV10STRAPINFO);				ACCW(NV44_WHAT2, 0x00000000);				ACCW(NV44_WHAT3, 0x00000000);				break;			default:				ACCW(NV40P_WHAT0, 0x83280eff);				ACCW(NV40P_WHAT1, 0x000000a0);				break;			}			ACCW(NV10_TIL3PT, 0x2ffff800);			ACCW(NV10_TIL3ST, 0x00006000);			ACCW(NV4X_WHAT1, 0x01000000);			/* engine data source DMA instance = $1140 */			ACCW(NV4X_DMA_SRC, 0x00001140);			break;		case NV30A:			/* init some function blocks, but most is unknown.. */			ACCW(DEBUG1, 0x40108700);			ACCW(NV25_WHAT1, 0x00140000);			ACCW(DEBUG3, 0xf00e0431);			ACCW(NV10_DEBUG4, 0x00008000);			ACCW(NV25_WHAT0, 0xf04b1f36);			ACCW(NV20_WHAT3, 0x1002d888);			ACCW(NV25_WHAT2, 0x62ff007f);			break;		case NV20A:			/* init some function blocks, but most is unknown.. */			ACCW(DEBUG1, 0x00118700);			ACCW(DEBUG3, 0xf20e0431);			ACCW(NV10_DEBUG4, 0x00000000);			ACCW(NV20_WHAT1, 0x00000040);			if (si->ps.card_type < NV25)			{				ACCW(NV20_WHAT2, 0x00080000);				ACCW(NV10_DEBUG5, 0x00000005);				ACCW(NV20_WHAT3, 0x45caa208);				ACCW(NV20_WHAT4, 0x24000000);				ACCW(NV20_WHAT5, 0x00000040);				/* copy some fixed RAM(?) configuration info(?) to some indexed registers: */				/* b16-24 is select; b2-13 is adress in 32-bit words */				ACCW(RDI_INDEX, 0x00e00038);				/* data is 32-bit */				ACCW(RDI_DATA, 0x00000030);				/* copy some fixed RAM(?) configuration info(?) to some indexed registers: */				/* b16-24 is select; b2-13 is adress in 32-bit words */				ACCW(RDI_INDEX, 0x00e10038);				/* data is 32-bit */				ACCW(RDI_DATA, 0x00000030);			}			else			{				ACCW(NV25_WHAT1, 0x00080000);				ACCW(NV25_WHAT0, 0x304b1fb6);				ACCW(NV20_WHAT3, 0x18b82880);				ACCW(NV20_WHAT4, 0x44000000);				ACCW(NV20_WHAT5, 0x40000080);				ACCW(NV25_WHAT2, 0x000000ff);			}			break;		}		/* NV20A, NV30A and NV40A: */		/* copy tile setup stuff from 'source' to acc engine (pattern colorRAM?) */		for (cnt = 0; cnt < 32; cnt++)		{			NV_REG32(NVACC_NV20_WHAT0 + (cnt << 2)) =				NV_REG32(NVACC_NV10_FBTIL0AD + (cnt << 2));		}		if (si->ps.card_arch >= NV40A)		{			if ((si->ps.card_type == NV40) || (si->ps.card_type == NV45))			{				/* copy some RAM configuration info(?) */ 				ACCW(NV20_WHAT_T0, NV_REG32(NV32_PFB_CONFIG_0));				ACCW(NV20_WHAT_T1, NV_REG32(NV32_PFB_CONFIG_1));				ACCW(NV40_WHAT_T2, NV_REG32(NV32_PFB_CONFIG_0));				ACCW(NV40_WHAT_T3, NV_REG32(NV32_PFB_CONFIG_1));				/* setup location of active screen in framebuffer */				ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));				ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));				/* setup accesible card memory range */				ACCW(NV20_BLIMIT6, (si->ps.memory_size - 1));				ACCW(NV20_BLIMIT7, (si->ps.memory_size - 1));			}			else			{				/* copy some RAM configuration info(?) */				ACCW(NV40P_WHAT_T0, NV_REG32(NV32_PFB_CONFIG_0));				ACCW(NV40P_WHAT_T1, NV_REG32(NV32_PFB_CONFIG_1));				ACCW(NV40P_WHAT_T2, NV_REG32(NV32_PFB_CONFIG_0));				ACCW(NV40P_WHAT_T3, NV_REG32(NV32_PFB_CONFIG_1));				/* setup location of active screen in framebuffer */				ACCW(NV40P_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));				ACCW(NV40P_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));				/* setup accesible card memory range */				ACCW(NV40P_BLIMIT6, (si->ps.memory_size - 1));				ACCW(NV40P_BLIMIT7, (si->ps.memory_size - 1));			}		}		else /* NV20A and NV30A: */		{			/* copy some RAM configuration info(?) */			ACCW(NV20_WHAT_T0, NV_REG32(NV32_PFB_CONFIG_0));			ACCW(NV20_WHAT_T1, NV_REG32(NV32_PFB_CONFIG_1));			/* copy some RAM configuration info(?) to some indexed registers: */			/* b16-24 is select; b2-13 is adress in 32-bit words */			ACCW(RDI_INDEX, 0x00ea0000);			/* data is 32-bit */			ACCW(RDI_DATA, NV_REG32(NV32_PFB_CONFIG_0));			/* b16-24 is select; b2-13 is adress in 32-bit words */			ACCW(RDI_INDEX, 0x00ea0004);			/* data is 32-bit */			ACCW(RDI_DATA, NV_REG32(NV32_PFB_CONFIG_1));			/* setup location of active screen in framebuffer */			ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));			ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));			/* setup accesible card memory range */			ACCW(NV20_BLIMIT6, (si->ps.memory_size - 1));			ACCW(NV20_BLIMIT7, (si->ps.memory_size - 1));		}		/* NV20A, NV30A and NV40A: */		/* setup some acc engine tile stuff */		ACCW(NV10_TIL2AD, 0x00000000);		ACCW(NV10_TIL0ED, 0xffffffff);	}	/* all cards: */	/* setup clipping: rect size is 32768 x 32768, probably max. setting */	/* note:	 * can also be done via the NV_IMAGE_BLACK_RECTANGLE engine command. */	ACCW(ABS_UCLP_XMIN, 0x00000000);	ACCW(ABS_UCLP_YMIN, 0x00000000);	ACCW(ABS_UCLP_XMAX, 0x00007fff);	ACCW(ABS_UCLP_YMAX, 0x00007fff);	/*** PFIFO ***/	/* (setup caches) */	/* disable caches reassign */	ACCW(PF_CACHES, 0x00000000);	/* PFIFO mode: channel 0 is in DMA mode, channels 1 - 32 are in PIO mode */	ACCW(PF_MODE, 0x00000001);	/* cache1 push0 access disabled */	ACCW(PF_CACH1_PSH0, 0x00000000);	/* cache1 pull0 access disabled */	ACCW(PF_CACH1_PUL0, 0x00000000);	/* cache1 push1 mode = DMA */	if (si->ps.card_arch >= NV40A)		ACCW(PF_CACH1_PSH1, 0x00010000);	else		ACCW(PF_CACH1_PSH1, 0x00000100);	/* cache1 DMA Put offset = 0 (b2-28) */	ACCW(PF_CACH1_DMAP, 0x00000000);	/* cache1 DMA Get offset = 0 (b2-28) */	ACCW(PF_CACH1_DMAG, 0x00000000);	/* cache1 DMA instance adress = $114e (b0-15);	 * instance being b4-19 with baseadress NV_PRAMIN_CTX_0 (0x00700000). */	/* note:	 * should point to a DMA definition in CTX register space (which is sort of RAM).	 * This define tells the engine where the DMA cmd buffer is and what it's size is.	 * Inside that cmd buffer you'll find the actual issued engine commands. *///dma 3D test:	if (si->ps.card_arch >= NV40A)		ACCW(PF_CACH1_DMAI, 0x0000114e);	else		ACCW(PF_CACH1_DMAI, 0x00001152);//end dma test.	/* cache0 push0 access disabled */	ACCW(PF_CACH0_PSH0, 0x00000000);	/* cache0 pull0 access disabled */	ACCW(PF_CACH0_PUL0, 0x00000000);	/* RAM HT (hash table) baseadress = $10000 (b4-8), size = 4k,	 * search = 128 (is byte offset between hash 'sets') */	/* note:	 * so HT base is $00710000, last is $00710fff.	 * In this space you define the engine command handles (HT_HANDL_XX), which	 * in turn points to the defines in CTX register space (which is sort of RAM) */	ACCW(PF_RAMHT, 0x03000100);	/* RAM FC baseadress = $11000 (b3-8) (size is fixed to 0.5k(?)) */	/* note:	 * so FC base is $00711000, last is $007111ff. (not used?) */	ACCW(PF_RAMFC, 0x00000110);	/* RAM RO baseadress = $11200 (b1-8), size = 0.5k */	/* note:	 * so RO base is $00711200, last is $007113ff. (not used?) */	/* note also:	 * This means(?) the PRAMIN CTX registers are accessible from base $00711400. */	ACCW(PF_RAMRO, 0x00000112);	/* PFIFO size: ch0-15 = 512 bytes, ch16-31 = 124 bytes */	ACCW(PF_SIZE, 0x0000ffff);	/* cache1 hash instance = $ffff (b0-15) */	ACCW(PF_CACH1_HASH, 0x0000ffff);	/* disable all PFIFO INTs */	ACCW(PF_INTEN, 0x00000000);	/* reset all PFIFO INT status bits */	ACCW(PF_INTSTAT, 0xffffffff);	/* cache0 pull0 engine = acceleration engine (graphics) */	ACCW(PF_CACH0_PUL1, 0x00000001);	/* cache1 DMA control: disable some stuff */	ACCW(PF_CACH1_DMAC, 0x00000000);	/* cache1 engine 0 upto/including 7 is software (could also be graphics or DVD) */	ACCW(PF_CACH1_ENG, 0x00000000);	/* cache1 DMA fetch: trigger at 128 bytes, size is 32 bytes, max requests is 15,	 * use little endian */	ACCW(PF_CACH1_DMAF, 0x000f0078);	/* cache1 DMA push: b0 = 1: access is enabled */	ACCW(PF_CACH1_DMAS, 0x00000001);	/* cache1 push0 access enabled */	ACCW(PF_CACH1_PSH0, 0x00000001);	/* cache1 pull0 access enabled */	ACCW(PF_CACH1_PUL0, 0x00000001);	/* cache1 pull1 engine = acceleration engine (graphics) */	ACCW(PF_CACH1_PUL1, 0x00000001);	/* enable PFIFO caches reassign */	ACCW(PF_CACHES, 0x00000001);	/* setup 3D specifics */	nv_init_for_3D_dma();	/*** init acceleration engine command info ***/	/* set object handles */	/* note:	 * probably depending on some other setup, there are 8 or 32 FIFO channels	 * available. Assuming the current setup only has 8 channels because the 'rest'	 * isn't setup here... */	si->engine.fifo.handle[0] = NV_ROP5_SOLID;	si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE;	si->engine.fifo.handle[2] = NV_IMAGE_PATTERN;	si->engine.fifo.handle[3] = NV4_SURFACE; /* NV10_CONTEXT_SURFACES_2D is identical */	si->engine.fifo.handle[4] = NV_IMAGE_BLIT;	si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT;	si->engine.fifo.handle[6] = NV1_RENDER_SOLID_LIN;	si->engine.fifo.handle[7] = NV4_DX5_TEXTURE_TRIANGLE;	/* preset no FIFO channels assigned to cmd's */	for (cnt = 0; cnt < 0x20; cnt++)	{		si->engine.fifo.ch_ptr[cnt] = 0;	}	/* set handle's pointers to their assigned FIFO channels */	/* note:	 * b0-1 aren't used as adressbits. Using b0 to indicate a valid pointer. */	for (cnt = 0; cnt < 0x08; cnt++)	{		si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] =												(0x00000001 + (cnt * 0x00002000));	}	/*** init DMA command buffer info ***/	si->engine.dma.cmdbuffer = (uint32 *)((char *)si->framebuffer +		((si->ps.memory_size - 1) & 0xffff8000));	LOG(4,("ACC_DMA: command buffer is at adress $%08x\n",		((uint32)(si->engine.dma.cmdbuffer))));	/* we have issued no DMA cmd's to the engine yet */	si->engine.dma.put = 0;	/* the current first free adress in the DMA buffer is at offset 0 */	si->engine.dma.current = 0;	/* the DMA buffer can hold 8k 32-bit words (it's 32kb in size) */	/* note:	 * one word is reserved at the end of the DMA buffer to be able to instruct the	 * engine to do a buffer wrap-around!	 * (DMA opcode 'noninc method': issue word $20000000.) */	si->engine.dma.max = 8192 - 1;	/* note the current free space we have left in the DMA buffer */	si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;	/*** init FIFO via DMA command buffer. ***/	/* wait for room in fifo for new FIFO assigment cmds if needed: *///dma 3D test:	if (si->ps.card_arch >= NV40A)	{		if (nv_acc_fifofree_dma(12) != B_OK) return B_ERROR;	}	else	{		if (nv_acc_fifofree_dma(16) != B_OK) return B_ERROR;	}//end dma test.	/* program new FIFO assignments */	/* Raster OPeration: */	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH0, si->engine.fifo.handle[0]);	/* Clip: */	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH1, si->engine.fifo.handle[1]);	/* Pattern: */	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH2, si->engine.fifo.handle[2]);	/* 2D Surface: */	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH3, si->engine.fifo.handle[3]);	/* Blit: */	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH4, si->engine.fifo.handle[4]);	/* Bitmap: */	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]);//dma 3D test:	if (si->ps.card_arch < NV40A)	{		/* Line: (not used or 3D only?) */		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH6, si->engine.fifo.handle[6]);		/* Textured Triangle: (3D only) */		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH7, si->engine.fifo.handle[7]);	}//end dma test.	/*** Set pixel width ***/	switch(si->dm.space)	{	case B_CMAP8:		surf_depth = 0x00000001;		cmd_depth = 0x00000003;		break;	case B_RGB15_LITTLE:	case B_RGB16_LITTLE:		surf_depth = 0x00000004;		cmd_depth = 0x00000001;		break;	case B_RGB32_LITTLE:	case B_RGBA32_LITTLE:		surf_depth = 0x00000006;		cmd_depth = 0x00000003;		break;	default:		LOG(8,("ACC_DMA: init, invalid bit depth\n"));		return B_ERROR;	}	/* wait for room in fifo for surface setup cmd if needed */	if (nv_acc_fifofree_dma(5) != B_OK) return B_ERROR;	/* now setup 2D surface (writing 5 32bit words) */	nv_acc_cmd_dma(NV4_SURFACE, NV4_SURFACE_FORMAT, 4);	si->engine.dma.cmdbuffer[si->engine.dma.current++] = surf_depth; /* Format */	/* setup screen pitch */	si->engine.dma.cmdbuffer[si->engine.dma.current++] =		((si->fbc.bytes_per_row & 0x0000ffff) | (si->fbc.bytes_per_row << 16)); /* Pitch */	/* setup screen location */	si->engine.dma.cmdbuffer[si->engine.dma.current++] =		((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer); /* OffsetSource */	si->engine.dma.cmdbuffer[si->engine.dma.current++] =		((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer); /* OffsetDest */	/* wait for room in fifo for pattern colordepth setup cmd if needed */	if (nv_acc_fifofree_dma(2) != B_OK) return B_ERROR;	/* set pattern colordepth (writing 2 32bit words) */	nv_acc_cmd_dma(NV_IMAGE_PATTERN, NV_IMAGE_PATTERN_SETCOLORFORMAT, 1);	si->engine.dma.cmdbuffer[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */	/* wait for room in fifo for bitmap colordepth setup cmd if needed */	if (nv_acc_fifofree_dma(2) != B_OK) return B_ERROR;	/* set bitmap colordepth (writing 2 32bit words) */	nv_acc_cmd_dma(NV4_GDI_RECTANGLE_TEXT, NV4_GDI_RECTANGLE_TEXT_SETCOLORFORMAT, 1);	si->engine.dma.cmdbuffer[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */	/* Load our pattern into the engine: */	/* wait for room in fifo for pattern cmd if needed. */	if (nv_acc_fifofree_dma(7) != B_OK) return B_ERROR;	/* now setup pattern (writing 7 32bit words) */	nv_acc_cmd_dma(NV_IMAGE_PATTERN, NV_IMAGE_PATTERN_SETSHAPE, 1);	si->engine.dma.cmdbuffer[si->engine.dma.current++] = 0x00000000; /* SetShape: 0 = 8x8, 1 = 64x1, 2 = 1x64 */	nv_acc_cmd_dma(NV_IMAGE_PATTERN, NV_IMAGE_PATTERN_SETCOLOR0, 4);	si->engine.dma.cmdbuffer[si->engine.dma.current++] = 0xffffffff; /* SetColor0 */	si->engine.dma.cmdbuffer[si->engine.dma.current++] = 0xffffffff; /* SetColor1 */	si->engine.dma.cmdbuffer[si->engine.dma.current++] = 0xffffffff; /* SetPattern[0] */	si->engine.dma.cmdbuffer[si->engine.dma.current++] = 0xffffffff; /* SetPattern[1] */	/* tell the engine to fetch and execute all (new) commands in the DMA buffer */	nv_start_dma();	return B_OK;}