rem: ram_cfg = *((uint16*)(&(rom[(0x01a8 + (ram_cfg * 2))])));
add: ram_cfg = *((uint16*)(&(rom[(ram_tab + (ram_cfg * 2))])));
context: static void	setup_ram_config(uint8* rom){	uint32 ram_cfg, data;	/* set MRS = 256 */	NV_REG32(NV32_PFB_DEBUG_0) &= 0xffffffef;	/* read RAM config hardware(?) strap */	ram_cfg = ((NV_REG32(NV32_NVSTRAPINFO2) >> 2) & 0x0000000f);	LOG(8,("INFO: ---RAM config strap is $%01x\n", ram_cfg));	/* use it as a pointer in a BIOS table for prerecorded RAM configurations */	//fixme?: is 0x01a8 indeed fixed or should this adress be gained via pins somehow?	ram_cfg = *((uint16*)(&(rom[(0x01a8 + (ram_cfg * 2))])));	/* log info */	switch (ram_cfg & 0x00000003)	{	case 0:		LOG(8,("INFO: ---32Mb RAM should be connected\n"));		break;	case 1:		LOG(8,("INFO: ---4Mb RAM should be connected\n"));		break;	case 2:		LOG(8,("INFO: ---8Mb RAM should be connected\n"));		break;	case 3:		LOG(8,("INFO: ---16Mb RAM should be connected\n"));		break;	}	if (ram_cfg & 0x00000004)		LOG(8,("INFO: ---RAM should be 128bits wide\n"));	else		LOG(8,("INFO: ---RAM should be 64bits wide\n"));	switch ((ram_cfg & 0x00000038) >> 3)	{	case 0:		LOG(8,("INFO: ---RAM type: 8Mbit SGRAM\n"));		break;	case 1:		LOG(8,("INFO: ---RAM type: 16Mbit SGRAM\n"));		break;	case 2:		LOG(8,("INFO: ---RAM type: 4 banks of 16Mbit SGRAM\n"));		break;	case 3:		LOG(8,("INFO: ---RAM type: 16Mbit SDRAM\n"));		break;	case 4:		LOG(8,("INFO: ---RAM type: 64Mbit SDRAM\n"));		break;	case 5:		LOG(8,("INFO: ---RAM type: 64Mbit x16 SDRAM\n"));		break;	}	/* set RAM amount, width and type */	data = (NV_REG32(NV32_NV4STRAPINFO) & 0xffffffc0);	NV_REG32(NV32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f));	/* setup write to read delay (?) */	data = (NV_REG32(NV32_PFB_CONFIG_1) & 0xff8ffffe);	data |= ((ram_cfg & 0x00000700) << 12);	/* force update via b0 = 0... */	NV_REG32(NV32_PFB_CONFIG_1) = data;	/* ... followed by b0 = 1(?) */	NV_REG32(NV32_PFB_CONFIG_1) = (data | 0x00000001);	//fixme?: do RAM width test	//fixme?: do RAM size test}