rem: print_bridge_info(pci_info *info, bool verbose)
add: print_bridge_info(const pci_info *info, bool verbose)
context: print_bridge_info(pci_info *info, bool verbose){	TRACE(("PCI:   primary_bus %02x, secondary_bus %02x, subordinate_bus %02x, secondary_latency %02x\n",			info->u.h1.primary_bus, info->u.h1.secondary_bus, info->u.h1.subordinate_bus, info->u.h1.secondary_latency));	TRACE(("PCI:   io_base %04x%02x, io_limit %04x%02x\n",			info->u.h1.io_base_upper16, info->u.h1.io_base, info->u.h1.io_limit_upper16, info->u.h1.io_limit));	TRACE(("PCI:   memory_base %04x, memory_limit %04x\n",			info->u.h1.memory_base, info->u.h1.memory_limit));	TRACE(("PCI:   prefetchable memory base %08lx%04x, limit %08lx%04x\n",		info->u.h1.prefetchable_memory_base_upper32, info->u.h1.prefetchable_memory_base,		info->u.h1.prefetchable_memory_limit_upper32, info->u.h1.prefetchable_memory_limit));	TRACE(("PCI:   bridge_control %04x, secondary_status %04x\n",			info->u.h1.bridge_control, info->u.h1.secondary_status));	TRACE(("PCI:   interrupt_line %02x, interrupt_pin %02x\n",			info->u.h1.interrupt_line, info->u.h1.interrupt_pin));	TRACE(("PCI:   ROM base host %08lx, pci %08lx, size ??\n",			info->u.h1.rom_base, info->u.h1.rom_base_pci));	for (int i = 0; i < 2; i++)		TRACE(("PCI:   base reg %d: host %08lx, pci %08lx, size %08lx, flags %02x\n",			i, info->u.h1.base_registers[i], info->u.h1.base_registers_pci[i],			info->u.h1.base_register_sizes[i], info->u.h1.base_register_flags[i]));}