rem: ddi_put64(msix_p->msix_tbl_hdl, (uint64_t *)off, addr);
add: ddi_put64(msix_p->msix_tbl_hdl, (uint64_t *)(off + PCI_MSIX_LOWER_ADDR_OFFSET), addr);  DDI_INTR_NEXDBG((CE_CONT, "pci_msi_configure: " "msix_addr 0x%" PRIx64 " msix_data 0x%x\n", ddi_get64(msix_p->msix_tbl_hdl, (uint64_t *)(off + PCI_MSIX_LOWER_ADDR_OFFSET)), ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)(off + PCI_MSIX_DATA_OFFSET))));
context: pci_msi_configure(dev_info_t *rdip, int type, int count, int inum,    uint64_t addr, uint64_t data){	ushort_t		caps_ptr, msi_ctrl;	ddi_acc_handle_t	cfg_hdle;	DDI_INTR_NEXDBG((CE_CONT, "pci_msi_configure: rdip = 0x%p\n",	    (void *)rdip));	if (pci_get_msi_ctrl(rdip, type, &msi_ctrl,	    &caps_ptr, &cfg_hdle) != DDI_SUCCESS)		return (DDI_FAILURE);	if (type == DDI_INTR_TYPE_MSI) {		/* Set the bits to inform how many MSIs are enabled */		msi_ctrl |= ((highbit(count) -1) << PCI_MSI_MME_SHIFT);		pci_config_put16(cfg_hdle,		    caps_ptr + PCI_MSI_CTRL, msi_ctrl);		/* Set the "data" and "addr" bits */		pci_config_put32(cfg_hdle,		    caps_ptr + PCI_MSI_ADDR_OFFSET, addr);		if (msi_ctrl &  PCI_MSI_64BIT_MASK) {			pci_config_put32(cfg_hdle,			    caps_ptr + PCI_MSI_ADDR_OFFSET + 4, 0);			pci_config_put16(cfg_hdle,			    caps_ptr + PCI_MSI_64BIT_DATA, data);		} else {			pci_config_put16(cfg_hdle,			    caps_ptr + PCI_MSI_32BIT_DATA, data);		}		DDI_INTR_NEXDBG((CE_CONT, "pci_msi_configure: msi_ctrl = %x\n",		    pci_config_get16(cfg_hdle, caps_ptr + PCI_MSI_CTRL)));	} else if (type == DDI_INTR_TYPE_MSIX) {		uintptr_t	off;		ddi_intr_msix_t	*msix_p = i_ddi_get_msix(rdip);		/* Offset into the "inum"th entry in the MSI-X table */		off = (uintptr_t)msix_p->msix_tbl_addr +		    ((inum - 1) * PCI_MSIX_VECTOR_SIZE);		/* Set the "data" and "addr" bits */		ddi_put32(msix_p->msix_tbl_hdl,		    (uint32_t *)((uchar_t *)off + PCI_MSIX_DATA_OFFSET), data);		ddi_put64(msix_p->msix_tbl_hdl, (uint64_t *)off, addr);	}	pci_config_teardown(&cfg_hdle);	return (DDI_SUCCESS);}