rem: LOG(4,("DAC: Fixing DFP refresh to 62Hz!\n"));
add: LOG(4,("DAC: Fixing DFP refresh to 61Hz!\n"));
context: status_t nv_dac_set_pix_pll(display_mode target){	uint8 m=0,n=0,p=0;//	uint time = 0;	float pix_setting, req_pclk;	status_t result;	/* fix a DVI or laptop flatpanel to 62Hz refresh!	 * (we can't risk getting below 60.0Hz as some panels shut-off then!) */	/* Note:	 * The pixelclock drives the flatpanel modeline, not the CRTC modeline. */	if (si->ps.tmds1_active)	{		LOG(4,("DAC: Fixing DFP refresh to 62Hz!\n"));		/* use the panel's modeline to determine the needed pixelclock */		target.timing.pixel_clock = si->ps.p1_timing.pixel_clock;	}	req_pclk = (target.timing.pixel_clock)/1000.0;	LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk));	/* signal that we actually want to set the mode */	result = nv_dac_pix_pll_find(target,&pix_setting,&m,&n,&p, 1);	if (result != B_OK)	{		return result;	}	/*reprogram (disable,select,wait for stability,enable)*///	DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04);  /*disable the PIXPLL*///	DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01);  /*select the PIXPLL*/	/* program new frequency */	DACW(PIXPLLC, ((p << 16) | (n << 8) | m));	/* program 2nd set N and M scalers if they exist (b31=1 enables them) */	if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36))		DACW(PIXPLLC2, 0x80000401);	/* Wait for the PIXPLL frequency to lock until timeout occurs *///fixme: do NV cards have a LOCK indication bit??/*	while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000))	{		time++;		snooze(1);	}		if (time > 2000)		LOG(2,("DAC: PIX PLL frequency not locked!\n"));	else		LOG(2,("DAC: PIX PLL frequency locked\n"));	DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B);         //enable the PIXPLL*///for now:	/* Give the PIXPLL frequency some time to lock... */	snooze(1000);	LOG(2,("DAC: PIX PLL frequency should be locked now...\n"));	return B_OK;}