rem: HW_DEBUGOUT2("Base = %lx, Length = %lx\n",
add: HW_DEBUGOUT2("Base = %lx, Length = %lx",
context: em_initialize_transmit_unit(struct adapter * adapter){	u_int32_t       reg_tctl;	u_int32_t       reg_tipg = 0;	u_int64_t       tdba = vtophys((vm_offset_t)adapter->tx_desc_base);	INIT_DEBUGOUT("em_initialize_transmit_unit: begin");	/* Setup the Base and Length of the Tx Descriptor Ring */	E1000_WRITE_REG(&adapter->hw, TDBAL,			(tdba & 0x00000000ffffffffULL));	E1000_WRITE_REG(&adapter->hw, TDBAH, (tdba >> 32));	E1000_WRITE_REG(&adapter->hw, TDLEN, 			adapter->num_tx_desc *			sizeof(struct em_tx_desc));	/* Setup the HW Tx Head and Tail descriptor pointers */	E1000_WRITE_REG(&adapter->hw, TDH, 0);	E1000_WRITE_REG(&adapter->hw, TDT, 0);	HW_DEBUGOUT2("Base = %lx, Length = %lx\n", 		     E1000_READ_REG(&adapter->hw, TDBAL),		     E1000_READ_REG(&adapter->hw, TDLEN));	/* Set the default values for the Tx Inter Packet Gap timer */	switch (adapter->hw.mac_type) {	case em_82542_rev2_0:	case em_82542_rev2_1:		reg_tipg = DEFAULT_82542_TIPG_IPGT;		reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;		reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;		break;	default:		if (adapter->hw.media_type == em_media_type_fiber)			reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER;		else			reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER;		reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;		reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;	}	E1000_WRITE_REG(&adapter->hw, TIPG, reg_tipg);	E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay.value);	if(adapter->hw.mac_type >= em_82540)		E1000_WRITE_REG(&adapter->hw, TADV, adapter->tx_abs_int_delay.value);	/* Program the Transmit Control Register */	reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN |		   (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);	if (adapter->link_duplex == 1) {		reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;	} else {		reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;	}	E1000_WRITE_REG(&adapter->hw, TCTL, reg_tctl);	/* Setup Transmit Descriptor Settings for this adapter */   	adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS;	if (adapter->tx_int_delay.value > 0)		adapter->txd_cmd |= E1000_TXD_CMD_IDE;	return;}