add: TRACE(("pci_bridge()\n"));
context: static void pci_bridge(uint8 bus, uint8 dev, uint8 func){	uint16 command;	uint8 mybus;	struct pci_device *pcid;	struct pci_bus *pcib;	pci_info *pcii;		command = read_pci_config(bus, dev, func, PCI_command, 2);	command &= ~ 0x03;	write_pci_config(bus, dev, func, PCI_command, 2, command);	/* Keep Marcus happy */	pci_max_bus += 1;	mybus = pci_max_bus;		write_pci_config(bus, dev, func, PCI_primary_bus, 1, bus);	write_pci_config(bus, dev, func, PCI_secondary_bus, 1, mybus);	write_pci_config(bus, dev, func, PCI_subordinate_bus, 1, 0xff);	dprintf("PCI-PCI bridge at %d:%d:%d configured as bus %d\n", bus, dev, func, mybus);	pci_scan_bus(mybus);	write_pci_config(bus, dev, func, PCI_subordinate_bus, 1, pci_max_bus);	pcii = (pci_info*)kmalloc(sizeof(pci_info));	if (!pcii)		goto pci_bridge_skip_infolist;	pcid = (struct pci_device*)kmalloc(sizeof(struct pci_device));	if (!pcid) {		kfree(pcii);		goto pci_bridge_skip_infolist;	}	pcib = (struct pci_bus *)kmalloc(sizeof(struct pci_bus));	if (!pcib) {		kfree(pcii);		kfree(pcid);		goto pci_bridge_skip_infolist;	}		pcid->info = pcii;	pcid->type = PCI_BRIDGE;	pcib->info = pcii;	pcii->bus = bus;	pcii->device = dev;	pcii->function = func;		fill_basic_pci_structure(pcii);		pcii->u.h1.rom_base_pci =        read_pci_config(bus, dev, func, PCI_bridge_rom_base, 4);	pcii->u.h1.primary_bus =         read_pci_config(bus, dev, func, PCI_primary_bus, 1);	pcii->u.h1.secondary_bus =       read_pci_config(bus, dev, func, PCI_secondary_bus, 1);	pcii->u.h1.secondary_latency =   read_pci_config(bus, dev, func, PCI_secondary_latency, 1);	pcii->u.h1.secondary_status =    read_pci_config(bus, dev, func, PCI_secondary_status, 2);	pcii->u.h1.subordinate_bus =     read_pci_config(bus, dev, func, PCI_subordinate_bus, 1);	pcii->u.h1.memory_base =         read_pci_config(bus, dev, func, PCI_memory_base, 2);	pcii->u.h1.memory_limit =        read_pci_config(bus, dev, func, PCI_memory_limit, 2);	pcii->u.h1.prefetchable_memory_base =  read_pci_config(bus, dev, func, PCI_prefetchable_memory_base, 2);	pcii->u.h1.prefetchable_memory_limit = read_pci_config(bus, dev, func, PCI_prefetchable_memory_limit, 2);	pcii->u.h1.bridge_control =      read_pci_config(bus, dev, func, PCI_bridge_control, 1);	pcii->u.h1.subsystem_vendor_id = read_pci_config(bus, dev, func, PCI_sub_vendor_id_1, 2);	pcii->u.h1.subsystem_id        = read_pci_config(bus, dev, func, PCI_sub_device_id_1, 2);			pcii->u.h1.interrupt_line =      read_pci_config(bus, dev, func, PCI_interrupt_line, 1);	pcii->u.h1.interrupt_pin =       read_pci_config(bus, dev, func, PCI_interrupt_pin, 1) & PCI_pin_mask;	{		struct pci_device *pd = pci_devices;		while (pd && pd->next)			pd = pd->next;		if (pd)			pd->next = pcid;		else			pci_devices = pcid;	}	{		struct pci_bus *pb = pci_busses;		while (pb && pb->next)			pb = pb->next;		if (pb)			pb->next = pcib;		else			pci_busses = pcib;	}	show_pci_details(pcii);pci_bridge_skip_infolist:	command |= 0x03;	write_pci_config(bus, dev, func, PCI_command, 2, command);	return;}