rem: uint8 revision;
context: sis900_initPHYs(struct sis_info *info){	uint16 phy;	uint8 revision;	// search for total of 32 possible MII PHY addresses	for (phy = 0; phy < 32; phy++) {		struct mii_phy *mii;		uint16 status;		int i;		status = mdio_statusFromPHY(info,phy);		if (status == 0xffff || status == 0x0000)			// this MII is not accessable			continue;		mii = (struct mii_phy *)malloc(sizeof(struct mii_phy));		if (mii == NULL)			return B_NO_MEMORY;		mii->address = phy;		mii->id0 = mdio_readFromPHY(info,phy,MII_PHY_ID0);		mii->id1 = mdio_readFromPHY(info,phy,MII_PHY_ID1);		mii->types = MII_HOME;		mii->next = info->firstPHY;		info->firstPHY = mii;		for (i = 0; gMIIChips[i].name; i++) {			if (gMIIChips[i].id0 != mii->id0 || gMIIChips[i].id1 != (mii->id1 & 0xfff0))				continue;			dprintf("Found MII PHY: %s\n", gMIIChips[i].name);			mii->types = gMIIChips[i].types;			break;		}		if (gMIIChips[i].name == NULL)			dprintf("Unknown MII PHY transceiver: id = (%x, %x).\n",mii->id0,mii->id1);	}	if (info->firstPHY == NULL) {		dprintf("No MII PHY transceiver found!\n");		return B_ENTRY_NOT_FOUND;	}		sis900_selectPHY(info);	// if the internal PHY is selected, reset it	if (info->currentPHY->id0 == PHY_ID0_SiS900_INTERNAL		&& (info->currentPHY->id1 & 0xfff0) == PHY_ID1_SiS900_INTERNAL) {		if (sis900_resetPHY(info) & MII_STATUS_LINK) {			uint16 poll = MII_STATUS_LINK;			while (poll) {				poll ^= mdio_read(info,MII_STATUS) & poll;			}		}	}	// workaround for ICS1893 PHY	if (info->currentPHY->id0 == PHY_ID0_ICS_1893		&& (info->currentPHY->id1 & 0xfff0) == PHY_ID1_ICS_1893)		mdio_write(info, 0x0018, 0xD200);	// SiS 630E has some bugs on default value of PHY registers	if (info->pciInfo->revision == SiS900_REVISION_SiS630E) {		mdio_write(info, MII_AUTONEG_ADV, 0x05e1);		mdio_write(info, MII_CONFIG1, 0x22);		mdio_write(info, MII_CONFIG2, 0xff00);		mdio_write(info, MII_MASK, 0xffc0);	}		info->link = mdio_status(info) & MII_STATUS_LINK;	return B_OK;}