rem: ERROR("invalid device name");
add: ERROR("invalid device name\n");
context: rtl8169_open(const char *name, uint32 flags, void** cookie){	rtl8169_device *device;	char *deviceName;	uint32 val;	int dev_id;	int mask;	int i;		TRACE("rtl8169_open()\n");	for (dev_id = 0; (deviceName = gDevNameList[dev_id]) != NULL; dev_id++) {		if (!strcmp(name, deviceName))			break;	}			if (deviceName == NULL) {		ERROR("invalid device name");		return B_ERROR;	}		// allow only one concurrent access	mask = 1 << dev_id;	if (atomic_or(&gOpenMask, mask) & mask)		return B_BUSY;			*cookie = device = (rtl8169_device *)malloc(sizeof(rtl8169_device));	if (!device) {		atomic_and(&gOpenMask, ~(1 << dev_id));		return B_NO_MEMORY;	}		memset(device, 0, sizeof(*device));	device->devId = dev_id;	device->pciInfo = gDevList[dev_id];	device->nonblocking = (flags & O_NONBLOCK) ? true : false;	device->closed = false;		// setup defaults	device->maxframesize  = 1514; // not FRAME_SIZE	device->txBufferCount = DEFAULT_TX_BUF_COUNT;	device->rxBufferCount = DEFAULT_RX_BUF_COUNT;	// get modifications from settings file	read_settings(device);	device->rxBuf = (void **)malloc(sizeof(void *) * device->rxBufferCount);	device->rxSpinlock = 0;	device->rxNextIndex = 0;	device->rxIntIndex = 0;	device->rxFree = device->rxBufferCount;	device->rxReadySem = create_sem(0, "rtl8169 rx ready");	set_sem_owner(device->rxReadySem, B_SYSTEM_TEAM);		device->txBuf = (void **)malloc(sizeof(void *) * device->txBufferCount);	device->txSpinlock = 0;	device->txNextIndex = 0;	device->txIntIndex = 0;	device->txUsed = 0;	device->txFreeSem = create_sem(device->txBufferCount, "rtl8169 tx free");	set_sem_owner(device->txFreeSem, B_SYSTEM_TEAM);		// enable busmaster and memory mapped access, disable io port access	val = gPci->read_pci_config(device->pciInfo->bus, device->pciInfo->device, device->pciInfo->function, PCI_command, 2);	val = PCI_PCICMD_BME | PCI_PCICMD_MSE | (val & ~PCI_PCICMD_IOS);	gPci->write_pci_config(device->pciInfo->bus, device->pciInfo->device, device->pciInfo->function, PCI_command, 2, val);	// adjust PCI latency timer	TRACE("changing PCI latency to 0x40\n");	gPci->write_pci_config(device->pciInfo->bus, device->pciInfo->device, device->pciInfo->function, PCI_latency, 1, 0x40);	// get IRQ	device->irq = gPci->read_pci_config(device->pciInfo->bus, device->pciInfo->device, device->pciInfo->function, PCI_interrupt_line, 1);	if (device->irq == 0 || device->irq == 0xff) {		ERROR("no IRQ assigned\n");		goto err;	}	TRACE("IRQ %d\n", device->irq);		// map registers into memory	val = gPci->read_pci_config(device->pciInfo->bus, device->pciInfo->device, device->pciInfo->function, 0x14, 4);	val &= PCI_address_memory_32_mask;	TRACE("hardware register address %p\n", (void *) val);	device->regArea = map_mem(&device->regAddr, (void *)val, 256, 0, "rtl8169 register");	if (device->regArea < B_OK) {		ERROR("can't map hardware registers\n");		goto err;	}			TRACE("mapped registers to %p\n", device->regAddr);	// disable receiver & transmitter XXX might be removed	write8(REG_CR, read8(REG_CR) & ~(CR_RE | CR_TE));	// do a soft reset	write8(REG_CR, read8(REG_CR) | CR_RST);	for (i = 0; (read8(REG_CR) & CR_RST) && i < 1000; i++)		snooze(10);	if (i == 1000) {		ERROR("hardware reset failed\n");		goto err;	}	TRACE("reset done\n");	// get MAC hardware version	device->mac_version = ((read32(REG_TX_CONFIG) & 0x7c000000) >> 25) | ((read32(REG_TX_CONFIG) & 0x00800000) >> 23);	TRACE("8169 Mac Version %d\n", device->mac_version);	if (device->mac_version > 0) { // this is a RTL8169s single chip		// get PHY hardware version		device->phy_version = read_phy_reg(device, 0x03) & 0x000f;		TRACE("8169 Phy Version %d\n", device->phy_version);	} else {		// we should probably detect what kind of phy is used		device->phy_version = 0;		TRACE("8169 Phy Version unknown\n");	}		if (device->mac_version == 1) {		// as it's done by the BSD driver...		TRACE("Setting MAC Reg C+CR 0x82h = 0x01h\n");		write8(0x82, 0x01); // don't know what this does		TRACE("Setting PHY Reg 0x0bh = 0x00h\n");		write_phy_reg(device, 0x0b, 0x0000); // 0xb is a reserved (vendor specific register), don't know what this does	}		// configure PHY	phy_config(device);		dump_phy_stat(device);	print_link_status(device);	// initialize MAC address		for (i = 0; i < 6; i++)		device->macaddr[i] = read8(i);			TRACE("MAC %02x:%02x:%02x:%02x:%02x:%02x\n",		device->macaddr[0], device->macaddr[1], device->macaddr[2],		device->macaddr[3], device->macaddr[4], device->macaddr[5]);		// setup interrupt handler	if (install_io_interrupt_handler(device->irq, rtl8169_int, device, 0) < B_OK) {		ERROR("can't install interrupt handler\n");		goto err;	}		#ifdef PROFILING		device->intTotalCount = 0;		device->intTotalCountOld = 0;		device->intRxTotalCount = 0;		device->intTxTotalCount = 0;		device->intTimerTotalCount = 0;		device->intCurrentCount = 0;		device->intRxCurrentCount = 0;		device->intTxCurrentCount = 0;		device->intTimerCurrentCount = 0;	  	device->timer = create_timer(print_debug_info, device, 1000000, B_PERIODIC_TIMER);	#endif // PROFILING		write16(0xe0, read16(0xe0)); // write CR+ command	write16(0xe0, read16(0xe0) | 0x0003); // don't know what this does, BSD says "enable C+ Tx/Rx"	if (device->mac_version == 1) {		TRACE("Setting Reg C+CR bit 3 and bit 14 to 1\n");		// bit 3 is PCI multiple read/write enable (max Tx/Rx DMA burst size setting is no longer valid then)		// bit 14 ??? (need more docs)		write16(0xe0, read16(0xe0) | 0x4008);	}	// setup buffer descriptors and buffers	if (init_buf_desc(device) != B_OK) {		ERROR("setting up buffer descriptors failed\n");		goto err;	}	// enable receiver & transmitter	write8(REG_CR, read8(REG_CR) | CR_RE | CR_TE);		write8(REG_9346CR, 0xc0);	// enable config access	write8(REG_CONFIG1, read8(REG_CONFIG1) & ~1);	// disable power management	write8(REG_9346CR, 0x00);	// disable config access		write8(0xec, 0x3f); 		// disable early transmit treshold	write16(0xda, FRAME_SIZE);	// receive packet maximum size	write16(0x5c, read16(0x5c) & 0xf000); // disable early receive interrupts		write32(0x4c, 0); // RxMissed ???	// setup receive config, can only be done when receiver is enabled!	// 1024 byte FIFO treshold, 1024 DMA burst	write32(REG_RX_CONFIG, (read32(REG_RX_CONFIG) & RX_CONFIG_MASK)		| (0x6 << RC_CONFIG_RXFTH_Shift) | (0x6 << RC_CONFIG_MAXDMA_Shift)		| RX_CONFIG_AcceptBroad | RX_CONFIG_AcceptMulti | RX_CONFIG_AcceptMyPhys);	write32(0x8, 0); // multicast filter	write32(0xc, 0); // multicast filter	// setup transmit config, can only be done when transmitter is enabled!		// append CRC, 1024 DMA burst	write32(REG_TX_CONFIG, (read32(REG_TX_CONFIG) & ~(0x10000 | (1 << 8))) | (0x6 << 8));	  	// clear pending interrupt status  	write16(REG_INT_STAT, 0xffff);  	  	// enable used interrupts 	write16(REG_INT_MASK, INT_FOVW | INT_PUN | INT_TER | INT_TOK | INT_RER | INT_ROK);	return B_OK;err:	delete_sem(device->rxReadySem);	delete_sem(device->txFreeSem);	delete_area(device->regArea);	delete_area(device->txBufArea);	delete_area(device->rxBufArea);	delete_area(device->txDescArea);	delete_area(device->rxDescArea);	free(device->txBuf);	free(device->rxBuf);	free(device);	atomic_and(&gOpenMask, ~(1 << dev_id));	return B_ERROR;}