rem: target.timing.h_total = target.timing.h_display + 56; target.timing.h_sync_start = target.timing.h_total - 40;
add: target.timing.h_total = target.timing.h_display + 128; target.timing.h_sync_start = target.timing.h_total - 112;
context: status_t nv_crtc_set_timing(display_mode target){	uint8 temp;	uint32 htotal;		/*total horizontal total VCLKs*/	uint32 hdisp_e;            /*end of horizontal display (begins at 0)*/	uint32 hsync_s;            /*begin of horizontal sync pulse*/	uint32 hsync_e;            /*end of horizontal sync pulse*/	uint32 hblnk_s;            /*begin horizontal blanking*/	uint32 hblnk_e;            /*end horizontal blanking*/	uint32 vtotal;		/*total vertical total scanlines*/	uint32 vdisp_e;            /*end of vertical display*/	uint32 vsync_s;            /*begin of vertical sync pulse*/	uint32 vsync_e;            /*end of vertical sync pulse*/	uint32 vblnk_s;            /*begin vertical blanking*/	uint32 vblnk_e;            /*end vertical blanking*/	uint32 linecomp;	/*split screen and vdisp_e interrupt*/	LOG(4,("CRTC: setting timing\n"));	/* setup fixed modeline for flatpanel if connected and active */	if (si->ps.tmds1_active)	{		LOG(2,("CRTC: DFP active: tuning modeline\n"));		/* horizontal timing */		target.timing.h_total = target.timing.h_display + 56;		target.timing.h_sync_start = target.timing.h_total - 40;		target.timing.h_sync_end = target.timing.h_total - 16;		/* vertical timing */		target.timing.v_total = target.timing.v_display + 6;		target.timing.v_sync_start = target.timing.v_total - 3;		target.timing.v_sync_end = target.timing.v_total - 2;	}	/* Modify parameters as required by standard VGA */	htotal = ((target.timing.h_total >> 3) - 5);	hdisp_e = ((target.timing.h_display >> 3) - 1);	hblnk_s = hdisp_e;	hblnk_e = (htotal + 4);//0;	hsync_s = (target.timing.h_sync_start >> 3);	hsync_e = (target.timing.h_sync_end >> 3);	vtotal = target.timing.v_total - 2;	vdisp_e = target.timing.v_display - 1;	vblnk_s = vdisp_e;	vblnk_e = (vtotal + 1);	vsync_s = target.timing.v_sync_start;//-1;	vsync_e = target.timing.v_sync_end;//-1;	/* prevent memory adress counter from being reset (linecomp may not occur) */	linecomp = target.timing.v_display;	/* enable access to CRTC1 on dualhead cards */	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);	/* Note for laptop and DVI flatpanels:	 * CRTC timing has a seperate set of registers from flatpanel timing.	 * The flatpanel timing registers have scaling registers that are used to match	 * these two modelines. */	{		LOG(4,("CRTC: Setting full timing...\n"));		/* log the mode that will be set */		LOG(2,("CRTC:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e));		LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e));		/* actually program the card! */		/* unlock CRTC registers at index 0-7 */		CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f));		/* horizontal standard VGA regs */		CRTCW(HTOTAL, (htotal & 0xff));		CRTCW(HDISPE, (hdisp_e & 0xff));		CRTCW(HBLANKS, (hblnk_s & 0xff));		/* also unlock vertical retrace registers in advance */		CRTCW(HBLANKE, ((hblnk_e & 0x1f) | 0x80));		CRTCW(HSYNCS, (hsync_s & 0xff));		CRTCW(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2)));		/* vertical standard VGA regs */		CRTCW(VTOTAL, (vtotal & 0xff));		CRTCW(OVERFLOW,		(			((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) |			((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) |			((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) |			((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4))		));		CRTCW(PRROWSCN, 0x00); /* not used */		CRTCW(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6))));		CRTCW(VSYNCS, (vsync_s & 0xff));		CRTCW(VSYNCE, ((CRTCR(VSYNCE) & 0xf0) | (vsync_e & 0x0f)));		CRTCW(VDISPE, (vdisp_e & 0xff));		CRTCW(VBLANKS, (vblnk_s & 0xff));		CRTCW(VBLANKE, (vblnk_e & 0xff));		CRTCW(LINECOMP, (linecomp & 0xff));		/* horizontal extended regs */		//fixme: we reset bit4. is this correct??		CRTCW(HEB, (CRTCR(HEB) & 0xe0) |			(		 	((htotal & 0x100) >> (8 - 0)) |			((hdisp_e & 0x100) >> (8 - 1)) |			((hblnk_s & 0x100) >> (8 - 2)) |			((hsync_s & 0x100) >> (8 - 3))			));		/* (mostly) vertical extended regs */		CRTCW(LSR,			(		 	((vtotal & 0x400) >> (10 - 0)) |			((vdisp_e & 0x400) >> (10 - 1)) |			((vsync_s & 0x400) >> (10 - 2)) |			((vblnk_s & 0x400) >> (10 - 3)) |			((hblnk_e & 0x040) >> (6 - 4))			//fixme: we still miss one linecomp bit!?! is this it??			//| ((linecomp & 0x400) >> 3)				));		/* more vertical extended regs (on GeForce cards only) */		if (si->ps.card_arch >= NV10A)		{ 			CRTCW(EXTRA,				(			 	((vtotal & 0x800) >> (11 - 0)) |				((vdisp_e & 0x800) >> (11 - 2)) |				((vsync_s & 0x800) >> (11 - 4)) |				((vblnk_s & 0x800) >> (11 - 6))				//fixme: do we miss another linecomp bit!?!				));		}		/* setup 'large screen' mode */		if (target.timing.h_display >= 1280)			CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb));		else			CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x04));		/* setup HSYNC & VSYNC polarity */		LOG(2,("CRTC: sync polarity: "));		temp = NV_REG8(NV8_MISCR);		if (target.timing.flags & B_POSITIVE_HSYNC)		{			LOG(2,("H:pos "));			temp &= ~0x40;		}		else		{			LOG(2,("H:neg "));			temp |= 0x40;		}		if (target.timing.flags & B_POSITIVE_VSYNC)		{			LOG(2,("V:pos "));			temp &= ~0x80;		}		else		{			LOG(2,("V:neg "));			temp |= 0x80;		}		NV_REG8(NV8_MISCW) = temp;		LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR)));	}	/* always disable interlaced operation */	/* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */	CRTCW(INTERLACE, 0xff);	/* setup flatpanel if connected and active */	if (si->ps.tmds1_active)	{		uint32 iscale_x, iscale_y;		//fixme: checkout upscaling and aspect!!!		/* calculate needed inverse scaling factors in 20.12 format */		iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.panel1_width);		iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.panel1_height);		/* unblock flatpanel timing programming (or something like that..) */		CRTCW(FP_HTIMING, 0);		CRTCW(FP_VTIMING, 0);		/* nVidia cards support upscaling except on NV11 */		if (si->ps.card_arch == NV11)		{			/* disable last fetched line limiting */			DACW(FP_DEBUG2, 0x00000000);			/* inform panel to scale if needed */			if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12)))			{				LOG(2,("CRTC: DFP needs to do scaling\n"));				DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) | 0x00000100));			}			else			{				LOG(2,("CRTC: no scaling for DFP needed\n"));				DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff));			}		}		else		{			LOG(2,("CRTC: GPU scales for DFP if needed\n"));			/* GPU scaling is automatically setup by hardware *///fixme: checkout non 4:3 aspect scaling.//			DACW(FP_DEBUG3, (iscale_x & 0x00001fff) | ((iscale_y & 0x00001fff) << 16));//			temp = (((iscale_x >> 1) & 0x00000fff) | (((iscale_y >> 1) & 0x00000fff) << 16));//			DACW(FP_DEBUG1, (temp | (1 << 12) | (1 << 28)));			/* limit last fetched line if vertical scaling is done */			if (iscale_y != (1 << 12))				DACW(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16)));//not needed apparantly://								((1 << 12) | ((target.timing.h_display - 1) <<  0)));			else				DACW(FP_DEBUG2, 0x00000000);			/* inform panel not to scale */			DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff));		}		/* do some logging.. */		LOG(2,("CRTC: FP_DEBUG0 reg readback: $%08x\n", DACR(FP_DEBUG0)));		LOG(2,("CRTC: FP_DEBUG1 reg readback: $%08x\n", DACR(FP_DEBUG1)));		LOG(2,("CRTC: FP_DEBUG2 reg readback: $%08x\n", DACR(FP_DEBUG2)));		LOG(2,("CRTC: FP_DEBUG3 reg readback: $%08x\n", DACR(FP_DEBUG3)));		LOG(2,("CRTC: FP_TG_CTRL reg readback: $%08x\n", DACR(FP_TG_CTRL)));	}	return B_OK;}