rem: si->engine.dma.current = 0;  nv_start_dma();
context: static status_t nv_acc_fifofree_dma(uint16 cmd_size){	//test:	uint32 dummy;	if (si->engine.dma.free < cmd_size)	{		//test:		LOG(4,("ACC_FIFOFREE: level 1; free $%08x, max $%08x, current $%08x\n",			si->engine.dma.free, si->engine.dma.max, si->engine.dma.current ));		/* update to actual current situation (free is 'cached') *///		si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;		/* check again if we have enough space *///		if (si->engine.dma.free < cmd_size)		{			//test:			LOG(4,("ACC_FIFOFREE: level 2\n"));			/* nope, so instruct DMA engine to reset the buffer when it's done */			si->engine.dma.cmdbuffer[si->engine.dma.current++] = 0x20000000;			/* reset our buffer pointer, so new commands will be placed at the			 * beginning of the buffer. */			si->engine.dma.current = 0;			/* tell the engine to fetch the remaining command(s) in the DMA buffer			 * that where not executed before. */			nv_start_dma();			/* fixme if needed:			 * we are assuming here that a large part in the beginning of the DMA			 * cmd buffer is already processed. If this is not true, we need to wait			 * here until the engine becomes idle or so... *///test://nv_acc_wait_idle_dma();//	{		/* snooze a bit so I do not hammer the bus *///		snooze (100);//	}for (dummy = 0; dummy < 2; dummy++){	LOG(4,("ACC_DMA_WRAP: get $%08x\n", NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET +		si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])])));	LOG(4,("ACC_DMA_WRAP: put $%08x\n", (si->engine.dma.put << 2)));}			/* update the current free space we have left in the DMA buffer */			si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;		}	}	return B_OK;}