rem: static int pci_get_capability(uint8 bus, uint8 dev, uint8 func, uint8 cap, uint8 *offs)
add: pci_get_capability(uint8 bus, uint8 dev, uint8 func, uint8 cap, uint8 *offs)
context: static int pci_get_capability(uint8 bus, uint8 dev, uint8 func, uint8 cap,                               uint8 *offs){	uint16 status;	uint8 cap_data;	uint8 hdr_type;	uint8 ofs;	int maxcount;		status = read_pci_config(bus, dev, func, PCI_status, 2);	if (!(status & PCI_status_capabilities))		return 0;			hdr_type = read_pci_config(bus, dev, func, PCI_header_type, 1);	switch (hdr_type & 0x7f) { /* mask off multi function device indicator bit */		case PCI_header_type_generic:			ofs = PCI_capabilities_ptr;			break;		case PCI_header_type_PCI_to_PCI_bridge:			dprintf("ERROR: pci_get_capability: PCItoPCI bridge header type has no capabilities pointer???\n");			return 0;		case PCI_header_type_cardbus:			ofs = PCI_capabilities_ptr_2;			break;		default:			dprintf("ERROR: pci_get_capability: unknown PCI header type\n");			return 0;	}	/* the 192 bytes vendor defined configuration space can 	 * hold as maximum 48 times a 32 bit aligned capability,	 * we use this as abort condition to avoid lock up by 	 * searching in a circular loop on bad hardware	 */	maxcount = 48; 	ofs = read_pci_config(bus, dev, func, ofs, 1);	while (maxcount-- != 0 && ofs != 0) {		/* mask off low two bits, demanded by PCI standard */		ofs &= ~3; 				/* PCI specification 2.2, section 6.8.1.1 and following		 * describe capability ID and next capability position as		 * two 8 bit values, the "capability ID" is at the 32 bit		 * aligned position, after it the "next pointer" follows.		 */		/* read the 8 bit capability id is at the 32bit aligned ofs position */		cap_data = read_pci_config(bus, dev, func, ofs, 1);		if (cap_data == cap) {			if (offs)				*offs = ofs;			return 1;		}		/* at ofs + 1, we can read the next capability position */		ofs = read_pci_config(bus, dev, func, ofs + 1, 1);	}	return 0;}