rem: case DDI_INTROP_SUPPORTED_TYPES: *(int *)result = DDI_INTR_TYPE_FIXED; break;
context: px_intx_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,    ddi_intr_handle_impl_t *hdlp, void *result){	px_t	*px_p = DIP_TO_STATE(dip);	int	ret = DDI_SUCCESS;	DBG(DBG_INTROPS, dip, "px_intx_ops: dip=%x rdip=%x intr_op=%x "	    "handle=%p\n", dip, rdip, intr_op, hdlp);	switch (intr_op) {	case DDI_INTROP_GETCAP:		ret = pci_intx_get_cap(rdip, (int *)result);		break;	case DDI_INTROP_SETCAP:		DBG(DBG_INTROPS, dip, "px_intx_ops: SetCap is not supported\n");		ret = DDI_ENOTSUP;		break;	case DDI_INTROP_ALLOC:		*(int *)result = hdlp->ih_scratch1;		break;	case DDI_INTROP_FREE:		break;	case DDI_INTROP_GETPRI:		*(int *)result = hdlp->ih_pri ?		    hdlp->ih_pri : px_class_to_pil(rdip);		break;	case DDI_INTROP_SETPRI:		break;	case DDI_INTROP_ADDISR:		ret = px_add_intx_intr(dip, rdip, hdlp);		break;	case DDI_INTROP_REMISR:		ret = px_rem_intx_intr(dip, rdip, hdlp);		break;	case DDI_INTROP_ENABLE:		ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum,		    hdlp->ih_vector, PX_INTR_STATE_ENABLE, 0, 0);		break;	case DDI_INTROP_DISABLE:		ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum,		    hdlp->ih_vector, PX_INTR_STATE_DISABLE, 0, 0);		break;	case DDI_INTROP_SETMASK:		ret = pci_intx_set_mask(rdip);		break;	case DDI_INTROP_CLRMASK:		ret = pci_intx_clr_mask(rdip);		break;	case DDI_INTROP_GETPENDING:		ret = pci_intx_get_pending(rdip, (int *)result);		break;	case DDI_INTROP_NINTRS:	case DDI_INTROP_NAVAIL:		*(int *)result = i_ddi_get_nintrs(rdip);		break;	case DDI_INTROP_SUPPORTED_TYPES:		*(int *)result = DDI_INTR_TYPE_FIXED;		break;	default:		ret = DDI_ENOTSUP;		break;	}	return (ret);}