rem: mask_bits &= ~0;  ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)((uchar_t *)off), mask_bits);
add: DDI_INTR_NEXDBG((CE_CONT, "pci_msi_enable: " "msix_vector_mask 0x%x\n", ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)off)));
context: pci_msi_enable_mode(dev_info_t *rdip, int type, int inum){	ushort_t		caps_ptr, msi_ctrl;	uint16_t		cmd_reg;	ddi_acc_handle_t	cfg_hdle;	DDI_INTR_NEXDBG((CE_CONT, "pci_msi_enable_mode: rdip = 0x%p, "	    "inum  = 0x%x\n", (void *)rdip, inum));	if (pci_get_msi_ctrl(rdip, type, &msi_ctrl,	    &caps_ptr, &cfg_hdle) != DDI_SUCCESS)		return (DDI_FAILURE);	/* Disable INTx simulation, if applicable */	cmd_reg = pci_config_get16(cfg_hdle, PCI_CONF_COMM);	/* This write succeeds only for devices > PCI2.3 */	pci_config_put16(cfg_hdle, PCI_CONF_COMM,	    cmd_reg | PCI_COMM_INTX_DISABLE);	DDI_INTR_NEXDBG((CE_CONT, "pci_msi_enable_mode: "	    "Before CmdReg = 0x%x, After CmdReg = 0x%x\n",	    cmd_reg, pci_config_get16(cfg_hdle, PCI_CONF_COMM)));	if (type == DDI_INTR_TYPE_MSI) {		if (msi_ctrl & PCI_MSI_ENABLE_BIT)			goto finished;		msi_ctrl |= PCI_MSI_ENABLE_BIT;		pci_config_put16(cfg_hdle,		    caps_ptr + PCI_MSI_CTRL, msi_ctrl);	} else if (type == DDI_INTR_TYPE_MSIX) {		uintptr_t	off;		uint32_t	mask_bits;		ddi_intr_msix_t	*msix_p;		if (msi_ctrl & PCI_MSIX_ENABLE_BIT)			goto finished;		msi_ctrl |= PCI_MSIX_ENABLE_BIT;		pci_config_put16(cfg_hdle,		    caps_ptr + PCI_MSIX_CTRL, msi_ctrl);		msix_p = i_ddi_get_msix(rdip);		/* Offset into the "inum"th entry in the MSI-X table */		off = (uintptr_t)msix_p->msix_tbl_addr + ((inum - 1) *		    PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET;		/* Clear the Mask bit */		mask_bits = ddi_get32(msix_p->msix_tbl_hdl,		    (uint32_t *)((uchar_t *)off));		mask_bits &= ~0;		ddi_put32(msix_p->msix_tbl_hdl,		    (uint32_t *)((uchar_t *)off), mask_bits);	}finished:	DDI_INTR_NEXDBG((CE_CONT, "pci_msi_enable_mode: msi_ctrl = %x\n",	    msi_ctrl));	pci_config_teardown(&cfg_hdle);	return (DDI_SUCCESS);}