rem: if (si->ps.card_arch >= NV10A) {
add: if (si->ps.secondary_head) {
context: status_t nv_general_bios_to_powergraphics(){	LOG(2, ("INIT: Skipping card coldstart!\n"));	/* unlock card registers for R/W access */	CRTCW(LOCK, 0x57);	CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));	/* turn off both displays and the hardcursor (also disables transfers) */	nv_crtc_dpms(false, false, false);	nv_crtc_cursor_hide();	/* let acc engine make power off/power on cycle to start 'fresh' */	NV_REG32(NV32_PWRUPCTRL) = 0x13110011;	snooze(1000);	/* power-up all nvidia hardware function blocks */	/* bit 28: OVERLAY ENGINE (BES),	 * bit 25: CRTC2, (> NV04A)	 * bit 24: CRTC1,	 * bit 20: framebuffer,	 * bit 16: PPMI,	 * bit 12: PGRAPH,	 * bit  8: PFIFO,	 * bit  4: PMEDIA,	 * bit  0: TVOUT. (> NV04A) */	NV_REG32(NV32_PWRUPCTRL) = 0x13111111;	if (si->ps.card_arch >= NV10A)	{ 		/* switch overlay engine to head 1 */		//fixme: add other function blocks...		NV_REG32(NV32_FUNCSEL) |= 0x00001000;		NV_REG32(NV32_2FUNCSEL) &= ~0x00001000;	}	//fixme: FX5600 cards have a second postdivider for the pixel PLL VCO.	//find it and program it, instead of relying on the cards BIOS...	//BIOS tested: FX5600 BIOS V4.31.20.38.00	/* non-NV31 cards have no second postdivider */	si->pixpll_vco_div2 = 1;	if (si->ps.card_type == NV31)	{		/* only reading b0-7, as the rest seems to be write-only */		uint16 v_display = CRTCR(VDISPE) + 1;		if ((!(CRTCR(REPAINT1) & 0x01)) &&			((v_display == (600 & 0xff)) || (v_display == (1200 & 0xff))))		{			/* if a VESA mode was already set, and the mode was 800x600 or 1600x1200			 * the BIOS programs the second VCO postdivider to 5 */			si->pixpll_vco_div2 = 5;			LOG(2, ("INIT: assuming NV31 pixPLL second VCO postdivider is set to 5!\n"));		}		else		{			/* else the BIOS programs the second VCO postdivider to 4 */			si->pixpll_vco_div2 = 4;			LOG(2, ("INIT: assuming NV31 pixPLL second VCO postdiviver is set to 4!\n"));		}	}	/* enable 'enhanced mode', enable Vsync & Hsync,	 * set DAC palette to 8-bit width, disable large screen */	CRTCW(REPAINT1, 0x04);	/* turn on display */	nv_crtc_dpms(true, true, true);	return B_OK;}