void   *pccbb_intr_establish __P((struct pccbb_softc *, int irq, int level, int (*ih) (void *), void *sc)); void	pccbb_intr_disestablish(struct pccbb_softc *, void *ih);  void   *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, int level, int (*ih) (void *), void *sc)); void	pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih);  cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int, int); void	pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t); cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int); void	pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int, cardbusreg_t); void	pccbb_chipinit(struct pccbb_softc *);  int	pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, struct pcmcia_mem_handle *); void	pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t, struct pcmcia_mem_handle *); int	pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *); void	pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int); int	pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, bus_size_t, struct pcmcia_io_handle *); void	pccbb_pcmcia_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); int	pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, struct pcmcia_io_handle *, int *); void	pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int); void   *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t, struct pcmcia_function *, int, int (*)(void *), void *, char *)); void	pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *); void	pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t); void	pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t); int	pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch);  void	pccbb_pcmcia_do_io_map(struct pcic_handle *, int); void	pccbb_pcmcia_wait_ready(struct pcic_handle *); void	pccbb_pcmcia_do_mem_map(struct pcic_handle *, int); void	pccbb_powerhook(int, void *);   #if rbus  int	pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t, bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align, int flags, bus_addr_t * addrp, bus_space_handle_t * bshp); int	pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t, bus_space_handle_t, bus_size_t);  #endif   #if rbus  int	pccbb_open_win(struct pccbb_softc *, bus_space_tag_t, bus_addr_t, bus_size_t, bus_space_handle_t, int flags); int	pccbb_close_win(struct pccbb_softc *, bus_space_tag_t, bus_space_handle_t, bus_size_t); int	pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t, bus_size_t, bus_space_handle_t, int); int	pccbb_winlist_delete(struct pccbb_win_chain_head *, bus_space_handle_t, bus_size_t); void	pccbb_winset(bus_addr_t align, struct pccbb_softc *, bus_space_tag_t); void	pccbb_winlist_show(struct pccbb_win_chain *);  #endif    void	pccbb_pci_callback(struct device *);  #if defined SHOW_REGS void	cb_show_regs(pci_chipset_tag_t, pcitag_t, bus_space_tag_t, bus_space_handle_t memh); #endif  struct cfattach cbb_pci_ca = { sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach };  static struct pcmcia_chip_functions pccbb_pcmcia_funcs = { pccbb_pcmcia_mem_alloc, pccbb_pcmcia_mem_free, pccbb_pcmcia_mem_map, pccbb_pcmcia_mem_unmap, pccbb_pcmcia_io_alloc, pccbb_pcmcia_io_free, pccbb_pcmcia_io_map, pccbb_pcmcia_io_unmap, pccbb_pcmcia_intr_establish, pccbb_pcmcia_intr_disestablish, pccbb_pcmcia_socket_enable, pccbb_pcmcia_socket_disable, pccbb_pcmcia_card_detect };  #if rbus static struct cardbus_functions pccbb_funcs = { pccbb_rbus_cb_space_alloc, pccbb_rbus_cb_space_free, pccbb_cb_intr_establish, pccbb_cb_intr_disestablish, pccbb_ctrl, pccbb_power, pccbb_make_tag, pccbb_free_tag, pccbb_conf_read, pccbb_conf_write, }; #else static struct cardbus_functions pccbb_funcs = { pccbb_ctrl, pccbb_power, pccbb_mem_open, pccbb_mem_close, pccbb_io_open, pccbb_io_close, pccbb_cb_intr_establish, pccbb_cb_intr_disestablish, pccbb_make_tag, pccbb_conf_read, pccbb_conf_write, }; #endif  int pcicbbmatch(parent, match, aux) struct device *parent; void *match; void *aux; { struct pci_attach_args *pa = (struct pci_attach_args *)aux;  if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS && PCI_INTERFACE(pa->pa_class) == 0) { return 1; }  return 0; }  #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \ | ((prod) << PCI_PRODUCT_SHIFT))  struct yenta_chipinfo { pcireg_t yc_id;		        int yc_chiptype; int yc_flags; } yc_chipsets[] = {  { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX, PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},   { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X, PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X, PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X, PCCBB_PCMCIA_MEM_32},   { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95), CB_TOPIC95, PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B), CB_TOPIC95B, PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97), CB_TOPIC97, PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100), CB_TOPIC97, PCCBB_PCMCIA_MEM_32},   { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832), CB_CIRRUS, PCCBB_PCMCIA_MEM_32}, { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833), CB_CIRRUS, PCCBB_PCMCIA_MEM_32},   { 0  , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32}, };  int cb_chipset(pci_id, flagp) u_int32_t pci_id; int *flagp; { struct yenta_chipinfo *yc;   for (yc = yc_chipsets; yc < yc_chipsets + sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++) if (pci_id == yc->yc_id) break;  if (flagp != NULL) *flagp = yc->yc_flags;  return (yc->yc_chiptype); }  void pccbb_shutdown(void *arg) { struct pccbb_softc *sc = arg; pcireg_t command;  DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname));   pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);  bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK, 0);  command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);  command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE); pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); }  void pccbbattach(parent, self, aux) struct device *parent; struct device *self; void *aux; { struct pccbb_softc *sc = (void *)self; struct pci_attach_args *pa = aux; pci_chipset_tag_t pc = pa->pa_pc; pcireg_t busreg, reg, sock_base; pci_intr_handle_t ih; const char *intrstr = NULL; bus_addr_t sockbase; int flags;  sc->sc_chipset = cb_chipset(pa->pa_id, &flags);  #ifdef CBB_DEBUG printf(" (chipflags %x)", flags); #endif  TAILQ_INIT(&sc->sc_memwindow); TAILQ_INIT(&sc->sc_iowindow);  #if rbus sc->sc_rbus_iot = rbus_pccbb_parent_io(pa); sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa); #endif   sc->sc_base_memh = 0;   sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE);  if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 && PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) {  if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL, 0)) { printf("%s: can't map socket base address 0x%x\n", sc->sc_dev.dv_xname, sock_base);  if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_IO, 0, &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL, 0)) { printf("%s: can't map socket base address" " 0x%lx: io mode\n", sc->sc_dev.dv_xname, sockbase);  sc->sc_base_memh = 0; pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0); } } else { DPRINTF(("%s: socket base address 0x%lx\n", sc->sc_dev.dv_xname, sockbase)); } }  sc->sc_mem_start = 0;	        sc->sc_mem_end = 0xffffffff;      busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM); #if notyet if (((busreg >> 8) & 0xff) == 0) { printf(": CardBus support disabled because of unconfigured bus number\n"); flags |= PCCBB_PCMCIA_16BITONLY; } #endif    #if defined CBB_DEBUG { static char *intrname[5] = { "NON", "A", "B", "C", "D" }; printf(": intrpin %s, intrtag %d\n", intrname[pa->pa_intrpin], pa->pa_intrline); } #endif   sc->sc_pc = pc; sc->sc_iot = pa->pa_iot; sc->sc_memt = pa->pa_memt; sc->sc_dmat = pa->pa_dmat; sc->sc_tag = pa->pa_tag; sc->sc_function = pa->pa_function; sc->sc_sockbase = sock_base; sc->sc_busnum = busreg; sc->sc_intrtag = pa->pa_intrtag; sc->sc_intrpin = pa->pa_intrpin;  sc->sc_pcmcia_flags = flags;      if (pci_intr_map(pa, &ih)) { printf(": couldn't map interrupt\n"); return; } intrstr = pci_intr_string(pc, ih);  sc->sc_intrline = pci_intr_line(ih);   sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc, sc->sc_dev.dv_xname);  if (sc->sc_ih == NULL) { printf(": couldn't establish interrupt"); if (intrstr != NULL) { printf(" at %s", intrstr); } printf("\n"); return; } printf(": %s\n", intrstr);  shutdownhook_establish(pccbb_shutdown, sc);   switch (sc->sc_chipset) { case CB_RX5C46X:	        #if 0  case CB_RX5C47X: #endif  reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR); reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA); pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg); break;  default:  pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0); break; }  timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc); config_defer(self, pccbb_pci_callback); }      void pccbb_pci_callback(self) struct device *self; { struct pccbb_softc *sc = (void *)self; pci_chipset_tag_t pc = sc->sc_pc; bus_space_tag_t base_memt; bus_space_handle_t base_memh; u_int32_t maskreg; bus_addr_t sockbase; struct cbslot_attach_args cba; struct pcmciabus_attach_args paa; struct cardslot_attach_args caa; struct cardslot_softc *csc;  if (0 == sc->sc_base_memh) {  #if rbus if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff, (sc->sc_chipset == CB_RX5C47X || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000, 0, &sockbase, &sc->sc_base_memh)) { return; } sc->sc_base_memt = sc->sc_memt; pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n", sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); #else sc->sc_base_memt = sc->sc_memt; #if !defined CBB_PCI_BASE #define CBB_PCI_BASE 0x20000000 #endif if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff, 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) {  return; } pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase); DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n", sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc, sc->sc_tag, PCI_SOCKBASE))); #endif }   pccbb_chipinit(sc);  base_memt = sc->sc_base_memt;   base_memh = sc->sc_base_memh;     sc->sc_pil = NULL; sc->sc_pil_intr_enable = 1;  powerhook_establish(pccbb_powerhook, sc);  { u_int32_t sockstat = bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); if (0 == (sockstat & CB_SOCKET_STAT_CD)) { sc->sc_flags |= CBB_CARDEXIST; } }   if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM); pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG);   cba.cba_busname = "cardbus"; cba.cba_iot = sc->sc_iot; cba.cba_memt = sc->sc_memt; cba.cba_dmat = sc->sc_dmat; cba.cba_bus = (busreg >> 8) & 0x0ff; cba.cba_cc = (void *)sc; cba.cba_cf = &pccbb_funcs; cba.cba_intrline = sc->sc_intrline;  #if rbus cba.cba_rbus_iot = sc->sc_rbus_iot; cba.cba_rbus_memt = sc->sc_rbus_memt; #endif  cba.cba_cacheline = PCI_CACHELINE(bhlc); cba.cba_lattimer = PCI_CB_LATENCY(busreg);  #if defined CBB_DEBUG printf("%s: cacheline 0x%x lattimer 0x%x\n", sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer); printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc, busreg); #endif #if defined SHOW_REGS cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt, sc->sc_base_memh); #endif }  pccbb_pcmcia_attach_setup(sc, &paa); caa.caa_cb_attach = NULL; if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) { caa.caa_cb_attach = &cba; } caa.caa_16_attach = &paa; caa.caa_ph = &sc->sc_pcmcia_h;  if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) { DPRINTF(("pccbbattach: found cardslot\n")); sc->sc_csc = csc; }  sc->sc_ints_on = 1;   maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK); maskreg |= CB_SOCKET_MASK_CD;   bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg);  bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT));  return; }       void pccbb_chipinit(sc) struct pccbb_softc *sc; { pci_chipset_tag_t pc = sc->sc_pc; pcitag_t tag = sc->sc_tag; pcireg_t reg;   reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);  reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE); pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);   reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG); if (PCI_CB_LATENCY(reg) < 0x20) { reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT); reg |= (0x20 << PCI_CB_LATENCY_SHIFT); pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg); } DPRINTF(("CardBus latency timer 0x%x (%x)\n", PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG)));   reg = pci_conf_read(pc, tag, PCI_BHLC_REG); if (PCI_LATTIMER(reg) < 0x10) { reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); reg |= (0x10 << PCI_LATTIMER_SHIFT); pci_conf_write(pc, tag, PCI_BHLC_REG, reg); } DPRINTF(("PCI latency timer 0x%x (%x)\n", PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG)));   reg = pci_conf_read(pc, tag, PCI_BCR_INTR); reg |= CB_BCR_INTR_IREQ_ENABLE;		 reg |= CB_BCR_WRITE_POST_ENABLE;	 reg |= CB_BCR_RESET_ENABLE;		 pci_conf_write(pc, tag, PCI_BCR_INTR, reg);  switch (sc->sc_chipset) { case CB_TI113X: reg = pci_conf_read(pc, tag, PCI_CBCTRL);  reg |= PCI113X_CBCTRL_PCI_IRQ_ENA;  reg |= PCI113X_CBCTRL_PCI_CSC;  reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK); pci_conf_write(pc, tag, PCI_CBCTRL, reg); break;  case CB_TOPIC95B: reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL); reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL; pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg);  reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL); DPRINTF(("%s: topic slot ctrl reg 0x%x -> ", sc->sc_dev.dv_xname, reg)); reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN | TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS); reg &= ~TOPIC_SLOT_CTRL_SWDETECT; DPRINTF(("0x%x\n", reg)); pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg); break; }   pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff); pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0); pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff); pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0); pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff); pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0); pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff); pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0);   bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh, 0x800 + PCIC_INTR, bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh, 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET);   pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V); }      void pccbb_pcmcia_attach_setup(sc, paa) struct pccbb_softc *sc; struct pcmciabus_attach_args *paa; { struct pcic_handle *ph = &sc->sc_pcmcia_h; #if rbus rbus_tag_t rb; #endif   ph->ph_parent = (struct device *)sc; ph->sock = sc->sc_function; ph->flags = 0; ph->shutdown = 0; ph->ih_irq = sc->sc_intrline; ph->ph_bus_t = sc->sc_base_memt; ph->ph_bus_h = sc->sc_base_memh; ph->ph_read = pccbb_pcmcia_read; ph->ph_write = pccbb_pcmcia_write; sc->sc_pct = &pccbb_pcmcia_funcs;   Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET); if (sc->sc_chipset == CB_TI113X) { Pcic_write(ph, PCIC_CSC_INTR, 0); } else { Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE); Pcic_read(ph, PCIC_CSC); }   paa->paa_busname = "pcmcia"; paa->pct = sc->sc_pct; paa->pch = ph; paa->iobase = 0;	        paa->iosize = 0; #if rbus rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot; paa->iobase = rb->rb_start + rb->rb_offset; paa->iosize = rb->rb_end - rb->rb_start; #endif  return; }  #if 0 void pccbb_pcmcia_attach_card(ph) struct pcic_handle *ph; { if (ph->flags & PCIC_FLAG_CARDP) { panic("pccbb_pcmcia_attach_card: already attached"); }   pcmcia_card_attach(ph->pcmcia);  ph->flags |= PCIC_FLAG_CARDP; }  void pccbb_pcmcia_detach_card(ph, flags) struct pcic_handle *ph; int flags; { if (!(ph->flags & PCIC_FLAG_CARDP)) { panic("pccbb_pcmcia_detach_card: already detached"); }  ph->flags &= ~PCIC_FLAG_CARDP;   pcmcia_card_detach(ph->pcmcia, flags); } #endif   int pccbbintr(arg) void *arg; { struct pccbb_softc *sc = (struct pccbb_softc *)arg; u_int32_t sockevent, sockstate; bus_space_tag_t memt = sc->sc_base_memt; bus_space_handle_t memh = sc->sc_base_memh; struct pcic_handle *ph = &sc->sc_pcmcia_h;  if (!sc->sc_ints_on) return 0;  sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT); bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent); Pcic_read(ph, PCIC_CSC);  if (sockevent == 0) {  if (sc->sc_pil_intr_enable) { return pccbbintr_function(sc); } else { return 0; } }  if (sockevent & CB_SOCKET_EVENT_CD) { sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT); if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) {  if (sc->sc_flags & CBB_CARDEXIST) { DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); DPRINTF((" card removed, 0x%08x\n", sockstate)); sc->sc_flags &= ~CBB_CARDEXIST; if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_16) { #if 0 struct pcic_handle *ph = &sc->sc_pcmcia_h;  pcmcia_card_deactivate(ph->pcmcia); pccbb_pcmcia_socket_disable(ph); pccbb_pcmcia_detach_card(ph, DETACH_FORCE); #endif cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_16); } else if (sc->sc_csc->sc_status & CARDSLOT_STATUS_CARD_CB) {  cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_REMOVAL_CB); } } } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) &&  (sc->sc_flags & CBB_CARDEXIST) == 0) { if (sc->sc_flags & CBB_INSERTING) { timeout_del(&sc->sc_ins_tmo); } timeout_add(&sc->sc_ins_tmo, hz / 10); sc->sc_flags |= CBB_INSERTING; } }  return (1); }   int pccbbintr_function(sc) struct pccbb_softc *sc; { int retval = 0, val; struct pccbb_intrhand_list *pil; int s, splchanged;  for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) {  splchanged = 1; #if 0 if (pil->pil_level == IPL_SERIAL) { s = splserial(); } else if (pil->pil_level == IPL_HIGH) { #endif if (pil->pil_level == IPL_HIGH) { s = splhigh(); } else if (pil->pil_level == IPL_CLOCK) { s = splclock(); } else if (pil->pil_level == IPL_AUDIO) { s = splaudio(); } else if (pil->pil_level == IPL_IMP) { s = splimp(); } else if (pil->pil_level == IPL_TTY) { s = spltty(); #if 0 } else if (pil->pil_level == IPL_SOFTSERIAL) { s = splsoftserial(); #endif } else if (pil->pil_level == IPL_NET) { s = splnet(); } else { splchanged = 0;  }  val = (*pil->pil_func)(pil->pil_arg);  if (splchanged != 0) { splx(s); }  retval = retval == 1 ? 1 : retval == 0 ? val : val != 0 ? val : retval; }  return retval; }  void pci113x_insert(arg) void *arg; { struct pccbb_softc *sc = (struct pccbb_softc *)arg; u_int32_t sockevent, sockstate;  sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_EVENT); sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT);  if (0 == (sockstate & CB_SOCKET_STAT_CD)) {	 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent)); DPRINTF((" card inserted, 0x%08x\n", sockstate)); sc->sc_flags |= CBB_CARDEXIST;  if (sockstate & CB_SOCKET_STAT_16BIT) {   cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_16); } else if (sockstate & CB_SOCKET_STAT_CB) {   cardslot_event_throw(sc->sc_csc, CARDSLOT_EVENT_INSERTION_CB); } else {  } } else { timeout_add(&sc->sc_ins_tmo, hz / 10); } }  #define PCCBB_PCMCIA_OFFSET 0x800 u_int8_t pccbb_pcmcia_read(ph, reg) struct pcic_handle *ph; int reg; { bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ);  return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg); }  void pccbb_pcmcia_write(ph, reg, val) struct pcic_handle *ph; int reg; u_int8_t val; { bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE);  bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg, val); }   int pccbb_ctrl(ct, command) cardbus_chipset_tag_t ct; int command; { struct pccbb_softc *sc = (struct pccbb_softc *)ct;  switch (command) { case CARDBUS_CD: if (2 == pccbb_detect_card(sc)) { int retval = 0; int status = cb_detect_voltage(sc); if (PCCARD_VCC_5V & status) { retval |= CARDBUS_5V_CARD; } if (PCCARD_VCC_3V & status) { retval |= CARDBUS_3V_CARD; } if (PCCARD_VCC_XV & status) { retval |= CARDBUS_XV_CARD; } if (PCCARD_VCC_YV & status) { retval |= CARDBUS_YV_CARD; } return retval; } else { return 0; } break; case CARDBUS_RESET: return cb_reset(sc); break; case CARDBUS_IO_ENABLE:        case CARDBUS_IO_DISABLE:       case CARDBUS_MEM_ENABLE:       case CARDBUS_MEM_DISABLE:      case CARDBUS_BM_ENABLE:        case CARDBUS_BM_DISABLE:       return pccbb_cardenable(sc, command); break; }  return 0; }   int pccbb_power(ct, command) cardbus_chipset_tag_t ct; int command; { struct pccbb_softc *sc = (struct pccbb_softc *)ct;  u_int32_t status, sock_ctrl; bus_space_tag_t memt = sc->sc_base_memt; bus_space_handle_t memh = sc->sc_base_memh;  DPRINTF(("pccbb_power: %s and %s [%x]\n", (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command));  status = bus_space_read_4(memt, memh, CB_SOCKET_STAT); sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL);  switch (command & CARDBUS_VCCMASK) { case CARDBUS_VCC_UC: break; case CARDBUS_VCC_5V: if (CB_SOCKET_STAT_5VCARD & status) {	 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; sock_ctrl |= CB_SOCKET_CTRL_VCC_5V; } else { printf("%s: BAD voltage request: no 5 V card\n", sc->sc_dev.dv_xname); } break; case CARDBUS_VCC_3V: if (CB_SOCKET_STAT_3VCARD & status) { sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; sock_ctrl |= CB_SOCKET_CTRL_VCC_3V; } else { printf("%s: BAD voltage request: no 3.3 V card\n", sc->sc_dev.dv_xname); } break; case CARDBUS_VCC_0V: sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK; break; default: return 0;	        break; }  switch (command & CARDBUS_VPPMASK) { case CARDBUS_VPP_UC: break; case CARDBUS_VPP_0V: sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; break; case CARDBUS_VPP_VCC: sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; sock_ctrl |= ((sock_ctrl >> 4) & 0x07); break; case CARDBUS_VPP_12V: sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK; sock_ctrl |= CB_SOCKET_CTRL_VPP_12V; break; }  #if 0 DPRINTF(("sock_ctrl: %x\n", sock_ctrl)); #endif bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl); status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);  if (status & CB_SOCKET_STAT_BADVCC) {	 printf ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n", sc->sc_dev.dv_xname, sock_ctrl, status); DPRINTF(("pccbb_power: %s and %s [%x]\n", (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN", (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command)); #if 0 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) { u_int32_t force = bus_space_read_4(memt, memh, CB_SOCKET_FORCE);  force &= ~CB_SOCKET_FORCE_BADVCC; bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force); printf("new status 0x%x\n", bus_space_read_4(memt, memh, CB_SOCKET_STAT)); return 1; } #endif return 0; }   delay(300 * 1000);  return 1;		        }  #if defined CB_PCMCIA_POLL struct cb_poll_str { void *arg; int (*func)(void *); int level; pccard_chipset_tag_t ct; int count; };  static struct cb_poll_str cb_poll[10]; static int cb_poll_n = 0; static struct timeout cb_poll_timeout;  void cb_pcmcia_poll(void *arg);  void cb_pcmcia_poll(arg) void *arg; { struct cb_poll_str *poll = arg; struct cbb_pcmcia_softc *psc = (void *)poll->ct->v; struct pccbb_softc *sc = psc->cpc_parent; int s; u_int32_t spsr;		         timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg); timeout_add(&cb_poll_timeout, hz / 10); switch (poll->level) { case IPL_NET: s = splnet(); break; case IPL_BIO: s = splbio(); break; case IPL_TTY:		        default: s = spltty(); break; }  spsr = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_STAT);  #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2 if (!(spsr & 0x40)) {	        #else if (1) { #endif if ((*poll->func) (poll->arg) == 1) { ++poll->count; printf("intr: reported from poller, 0x%x\n", spsr); #if defined LEVEL2 } else { printf("intr: miss! 0x%x\n", spsr); #endif } } splx(s); } #endif    int pccbb_detect_card(sc) struct pccbb_softc *sc; { bus_space_handle_t base_memh = sc->sc_base_memh; bus_space_tag_t base_memt = sc->sc_base_memt; u_int32_t sockstat = bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT); int retval = 0;   if (sockstat & CB_SOCKET_STAT_XVCARD) return 0;   if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) {  if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) {  if (CB_SOCKET_STAT_CB & sockstat) {  retval = 2; } else if (CB_SOCKET_STAT_16BIT & sockstat) {  retval = 1; } } } return retval; }   int cb_reset(sc) struct pccbb_softc *sc; {  int reset_duration = (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000); u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);   bcr |= CB_BCR_RESET_ENABLE; pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); delay(reset_duration);  if (CBB_CARDEXIST & sc->sc_flags) {	  bcr &= ~CB_BCR_RESET_ENABLE; pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr); delay(reset_duration); }  return 1; }   int cb_detect_voltage(sc) struct pccbb_softc *sc; { u_int32_t psr;		        bus_space_tag_t iot = sc->sc_base_memt; bus_space_handle_t ioh = sc->sc_base_memh; int vol = PCCARD_VCC_UKN;        psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT);  if (0x400u & psr) { vol |= PCCARD_VCC_5V; } if (0x800u & psr) { vol |= PCCARD_VCC_3V; }  return vol; }  int cbbprint(aux, pcic) void *aux; const char *pcic; {  return UNCONF; }   int pccbb_cardenable(sc, function) struct pccbb_softc *sc; int function; { u_int32_t command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);  DPRINTF(("pccbb_cardenable:")); switch (function) { case CARDBUS_IO_ENABLE: command |= PCI_COMMAND_IO_ENABLE; break; case CARDBUS_IO_DISABLE: command &= ~PCI_COMMAND_IO_ENABLE; break; case CARDBUS_MEM_ENABLE: command |= PCI_COMMAND_MEM_ENABLE; break; case CARDBUS_MEM_DISABLE: command &= ~PCI_COMMAND_MEM_ENABLE; break; case CARDBUS_BM_ENABLE: command |= PCI_COMMAND_MASTER_ENABLE; break; case CARDBUS_BM_DISABLE: command &= ~PCI_COMMAND_MASTER_ENABLE; break; default: return 0; }  pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command); DPRINTF((" command reg 0x%x\n", command)); return 1; }  #if !rbus  int pccbb_io_open(ct, win, start, end) cardbus_chipset_tag_t ct; int win; u_int32_t start, end; { struct pccbb_softc *sc = (struct pccbb_softc *)ct; int basereg; int limitreg;  if ((win < 0) || (win > 2)) { #if defined DIAGNOSTIC printf("cardbus_io_open: window out of range %d\n", win); #endif return 0; }  basereg = win * 8 + 0x2c; limitreg = win * 8 + 0x30;  DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n", start, basereg, end, limitreg));  pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); return 1; }   int pccbb_io_close(ct, win) cardbus_chipset_tag_t ct; int win; { struct pccbb_softc *sc = (struct pccbb_softc *)ct; int basereg; int limitreg;  if ((win < 0) || (win > 2)) { #if defined DIAGNOSTIC printf("cardbus_io_close: window out of range %d\n", win); #endif return 0; }  basereg = win * 8 + 0x2c; limitreg = win * 8 + 0x30;  pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); return 1; }   int pccbb_mem_open(ct, win, start, end) cardbus_chipset_tag_t ct; int win; u_int32_t start, end; { struct pccbb_softc *sc = (struct pccbb_softc *)ct; int basereg; int limitreg;  if ((win < 0) || (win > 2)) { #if defined DIAGNOSTIC printf("cardbus_mem_open: window out of range %d\n", win); #endif return 0; }  basereg = win * 8 + 0x1c; limitreg = win * 8 + 0x20;  pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start); pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end); return 1; }   int pccbb_mem_close(ct, win) cardbus_chipset_tag_t ct; int win; { struct pccbb_softc *sc = (struct pccbb_softc *)ct; int basereg; int limitreg;  if ((win < 0) || (win > 2)) { #if defined DIAGNOSTIC printf("cardbus_mem_close: window out of range %d\n", win); #endif return 0; }  basereg = win * 8 + 0x1c; limitreg = win * 8 + 0x20;  pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0); pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0); return 1; } #endif   void * pccbb_cb_intr_establish(ct, irq, level, func, arg) cardbus_chipset_tag_t ct; int irq, level; int (*func)(void *); void *arg; { struct pccbb_softc *sc = (struct pccbb_softc *)ct;  return pccbb_intr_establish(sc, irq, level, func, arg); }    void pccbb_cb_intr_disestablish(ct, ih) cardbus_chipset_tag_t ct; void *ih; { struct pccbb_softc *sc = (struct pccbb_softc *)ct;  pccbb_intr_disestablish(sc, ih); }    void *
void   *pccbb_intr_establish __P((struct pccbb_softc *, int irq, int level,    int (*ih) (void *), void *sc));void	pccbb_intr_disestablish(struct pccbb_softc *, void *ih);void   *pccbb_cb_intr_establish __P((cardbus_chipset_tag_t, int irq, int level,    int (*ih) (void *), void *sc));void	pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih);cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int, int);void	pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t);cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int);void	pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int,    cardbusreg_t);void	pccbb_chipinit(struct pccbb_softc *);int	pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,    struct pcmcia_mem_handle *);void	pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t,    struct pcmcia_mem_handle *);int	pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t,    bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *);void	pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int);int	pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t,    bus_size_t, bus_size_t, struct pcmcia_io_handle *);void	pccbb_pcmcia_io_free(pcmcia_chipset_handle_t,    struct pcmcia_io_handle *);int	pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t,    bus_size_t, struct pcmcia_io_handle *, int *);void	pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int);void   *pccbb_pcmcia_intr_establish __P((pcmcia_chipset_handle_t,    struct pcmcia_function *, int, int (*)(void *), void *, char *));void	pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t,    void *);void	pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t);void	pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t);int	pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch);void	pccbb_pcmcia_do_io_map(struct pcic_handle *, int);void	pccbb_pcmcia_wait_ready(struct pcic_handle *);void	pccbb_pcmcia_do_mem_map(struct pcic_handle *, int);void	pccbb_powerhook(int, void *);/* bus-space allocation and deallocation functions */#if rbusint	pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t,    bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align,    int flags, bus_addr_t * addrp, bus_space_handle_t * bshp);int	pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t,    bus_space_handle_t, bus_size_t);#endif /* rbus */#if rbusint	pccbb_open_win(struct pccbb_softc *, bus_space_tag_t,    bus_addr_t, bus_size_t, bus_space_handle_t, int flags);int	pccbb_close_win(struct pccbb_softc *, bus_space_tag_t,    bus_space_handle_t, bus_size_t);int	pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t,    bus_size_t, bus_space_handle_t, int);int	pccbb_winlist_delete(struct pccbb_win_chain_head *,    bus_space_handle_t, bus_size_t);void	pccbb_winset(bus_addr_t align, struct pccbb_softc *,    bus_space_tag_t);void	pccbb_winlist_show(struct pccbb_win_chain *);#endif /* rbus *//* for config_defer */void	pccbb_pci_callback(struct device *);#if defined SHOW_REGSvoid	cb_show_regs(pci_chipset_tag_t, pcitag_t, bus_space_tag_t,    bus_space_handle_t memh);#endifstruct cfattach cbb_pci_ca = {	sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach};static struct pcmcia_chip_functions pccbb_pcmcia_funcs = {	pccbb_pcmcia_mem_alloc,	pccbb_pcmcia_mem_free,	pccbb_pcmcia_mem_map,	pccbb_pcmcia_mem_unmap,	pccbb_pcmcia_io_alloc,	pccbb_pcmcia_io_free,	pccbb_pcmcia_io_map,	pccbb_pcmcia_io_unmap,	pccbb_pcmcia_intr_establish,	pccbb_pcmcia_intr_disestablish,	pccbb_pcmcia_socket_enable,	pccbb_pcmcia_socket_disable,	pccbb_pcmcia_card_detect};#if rbusstatic struct cardbus_functions pccbb_funcs = {	pccbb_rbus_cb_space_alloc,	pccbb_rbus_cb_space_free,	pccbb_cb_intr_establish,	pccbb_cb_intr_disestablish,	pccbb_ctrl,	pccbb_power,	pccbb_make_tag,	pccbb_free_tag,	pccbb_conf_read,	pccbb_conf_write,};#elsestatic struct cardbus_functions pccbb_funcs = {	pccbb_ctrl,	pccbb_power,	pccbb_mem_open,	pccbb_mem_close,	pccbb_io_open,	pccbb_io_close,	pccbb_cb_intr_establish,	pccbb_cb_intr_disestablish,	pccbb_make_tag,	pccbb_conf_read,	pccbb_conf_write,};#endifintpcicbbmatch(parent, match, aux)	struct device *parent;	void *match;	void *aux;{	struct pci_attach_args *pa = (struct pci_attach_args *)aux;	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS &&	    PCI_INTERFACE(pa->pa_class) == 0) {		return 1;	}	return 0;}#define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \				| ((prod) << PCI_PRODUCT_SHIFT))struct yenta_chipinfo {	pcireg_t yc_id;		       /* vendor tag | product tag */	int yc_chiptype;	int yc_flags;} yc_chipsets[] = {	/* Texas Instruments chips */	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI12XX,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI12XX,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI12XX,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI12XX,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX,	    PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},	/* Ricoh chips */	{ MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X,	    PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X,	    PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X,	    PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X,	    PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X,	    PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X,	    PCCBB_PCMCIA_MEM_32},	/* Toshiba products */	{ MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95),	    CB_TOPIC95, PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B),	    CB_TOPIC95B, PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97),	    CB_TOPIC97, PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100),	    CB_TOPIC97, PCCBB_PCMCIA_MEM_32},	/* Cirrus Logic products */	{ MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832),	    CB_CIRRUS, PCCBB_PCMCIA_MEM_32},	{ MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833),	    CB_CIRRUS, PCCBB_PCMCIA_MEM_32},	/* sentinel, or Generic chip */	{ 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32},};intcb_chipset(pci_id, flagp)	u_int32_t pci_id;	int *flagp;{	struct yenta_chipinfo *yc;	/* Loop over except the last default entry. */	for (yc = yc_chipsets; yc < yc_chipsets +	    sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++)		if (pci_id == yc->yc_id)			break;	if (flagp != NULL)		*flagp = yc->yc_flags;	return (yc->yc_chiptype);}voidpccbb_shutdown(void *arg){	struct pccbb_softc *sc = arg;	pcireg_t command;	DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname));	/* turn off power */	pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);	bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK,	    0);	command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);	command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |	    PCI_COMMAND_MASTER_ENABLE);	pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command);}voidpccbbattach(parent, self, aux)	struct device *parent;	struct device *self;	void *aux;{	struct pccbb_softc *sc = (void *)self;	struct pci_attach_args *pa = aux;	pci_chipset_tag_t pc = pa->pa_pc;	pcireg_t busreg, reg, sock_base;	pci_intr_handle_t ih;	const char *intrstr = NULL;	bus_addr_t sockbase;	int flags;	sc->sc_chipset = cb_chipset(pa->pa_id, &flags);#ifdef CBB_DEBUG	printf(" (chipflags %x)", flags);#endif	TAILQ_INIT(&sc->sc_memwindow);	TAILQ_INIT(&sc->sc_iowindow);#if rbus	sc->sc_rbus_iot = rbus_pccbb_parent_io(pa);	sc->sc_rbus_memt = rbus_pccbb_parent_mem(pa);#endif /* rbus */	sc->sc_base_memh = 0;	/*	 * MAP socket registers and ExCA registers on memory-space	 * When no valid address is set on socket base registers (on pci	 * config space), get it not polite way.	 */	sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE);	if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 &&	    PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) {		/* The address must be valid. */		if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0,		    &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL, 0))		    {			printf("%s: can't map socket base address 0x%x\n",			    sc->sc_dev.dv_xname, sock_base);			/*			 * I think it's funny: socket base registers must be			 * mapped on memory space, but ...			 */			if (pci_mapreg_map(pa, PCI_SOCKBASE,			    PCI_MAPREG_TYPE_IO, 0, &sc->sc_base_memt,			    &sc->sc_base_memh, &sockbase, NULL, 0)) {				printf("%s: can't map socket base address"				    " 0x%lx: io mode\n", sc->sc_dev.dv_xname,				    sockbase);				/* give up... allocate reg space via rbus. */				sc->sc_base_memh = 0;				pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0);			}		} else {			DPRINTF(("%s: socket base address 0x%lx\n",			    sc->sc_dev.dv_xname, sockbase));		}	}	sc->sc_mem_start = 0;	       /* XXX */	sc->sc_mem_end = 0xffffffff;   /* XXX */	/*	 * When bus number isn't set correctly, give up using 32-bit CardBus	 * mode.	 */	busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM);#if notyet	if (((busreg >> 8) & 0xff) == 0) {		printf(": CardBus support disabled because of unconfigured bus number\n");		flags |= PCCBB_PCMCIA_16BITONLY;	}#endif	/* pccbb_machdep.c end */#if defined CBB_DEBUG	{		static char *intrname[5] = { "NON", "A", "B", "C", "D" };		printf(": intrpin %s, intrtag %d\n",		    intrname[pa->pa_intrpin], pa->pa_intrline);	}#endif	/* setup softc */	sc->sc_pc = pc;	sc->sc_iot = pa->pa_iot;	sc->sc_memt = pa->pa_memt;	sc->sc_dmat = pa->pa_dmat;	sc->sc_tag = pa->pa_tag;	sc->sc_function = pa->pa_function;	sc->sc_sockbase = sock_base;	sc->sc_busnum = busreg;	sc->sc_intrtag = pa->pa_intrtag;	sc->sc_intrpin = pa->pa_intrpin;	sc->sc_pcmcia_flags = flags;   /* set PCMCIA facility */	/* Map and establish the interrupt. */	if (pci_intr_map(pa, &ih)) {		printf(": couldn't map interrupt\n");		return;	}	intrstr = pci_intr_string(pc, ih);	/* must do this after intr is mapped and established */	sc->sc_intrline = pci_intr_line(ih);	/*	 * XXX pccbbintr should be called under the priority lower	 * than any other hard interrputs.	 */	sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc,	    sc->sc_dev.dv_xname);	if (sc->sc_ih == NULL) {		printf(": couldn't establish interrupt");		if (intrstr != NULL) {			printf(" at %s", intrstr);		}		printf("\n");		return;	}	printf(": %s\n", intrstr);	shutdownhook_establish(pccbb_shutdown, sc);	/* Disable legacy register mapping. */	switch (sc->sc_chipset) {	case CB_RX5C46X:	       /* fallthrough */#if 0	/* The RX5C47X-series requires writes to the PCI_LEGACY register. */	case CB_RX5C47X:#endif		/*		 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges		 * cannot be disabled by substituting 0 into PCI_LEGACY		 * register.  Ricoh CardBus bridges have special bits on Bridge		 * control reg (addr 0x3e on PCI config space).		 */		reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR);		reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA);		pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg);		break;	default:		/* XXX I don't know proper way to kill legacy I/O. */		pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0);		break;	}	timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc);	config_defer(self, pccbb_pci_callback);}/* * void pccbb_pci_callback(struct device *self) * *   The actual attach routine: get memory space for YENTA register *   space, setup YENTA register and route interrupt. * *   This function should be deferred because this device may obtain *   memory space dynamically.  This function must avoid obtaining *   memory area which has already kept for another device.  Also, *   this function MUST be done before ISA attach process because this *   function kills pcic compatible port used by ISA pcic. */voidpccbb_pci_callback(self)	struct device *self;{	struct pccbb_softc *sc = (void *)self;	pci_chipset_tag_t pc = sc->sc_pc;	bus_space_tag_t base_memt;	bus_space_handle_t base_memh;	u_int32_t maskreg;	bus_addr_t sockbase;	struct cbslot_attach_args cba;	struct pcmciabus_attach_args paa;	struct cardslot_attach_args caa;	struct cardslot_softc *csc;	if (0 == sc->sc_base_memh) {		/* The socket registers aren't mapped correctly. */#if rbus		if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff,		    (sc->sc_chipset == CB_RX5C47X		    || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000,		    0, &sockbase, &sc->sc_base_memh)) {			return;		}		sc->sc_base_memt = sc->sc_memt;		pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase);		DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n",		    sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag,		    PCI_SOCKBASE)));#else		sc->sc_base_memt = sc->sc_memt;#if !defined CBB_PCI_BASE#define CBB_PCI_BASE 0x20000000#endif		if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff,		    0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) {			/* cannot allocate memory space */			return;		}		pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase);		DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n",		    sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc,		    sc->sc_tag, PCI_SOCKBASE)));#endif	}	/* bus bridge initialization */	pccbb_chipinit(sc);	base_memt = sc->sc_base_memt;  /* socket regs memory tag */	base_memh = sc->sc_base_memh;  /* socket regs memory handle */	/* clear data structure for child device interrupt handlers */	sc->sc_pil = NULL;	sc->sc_pil_intr_enable = 1;	powerhook_establish(pccbb_powerhook, sc);	{		u_int32_t sockstat =		    bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT);		if (0 == (sockstat & CB_SOCKET_STAT_CD)) {			sc->sc_flags |= CBB_CARDEXIST;		}	}	/*	 * attach cardbus	 */	if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) {		pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM);		pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG);		/* initialize cbslot_attach */		cba.cba_busname = "cardbus";		cba.cba_iot = sc->sc_iot;		cba.cba_memt = sc->sc_memt;		cba.cba_dmat = sc->sc_dmat;		cba.cba_bus = (busreg >> 8) & 0x0ff;		cba.cba_cc = (void *)sc;		cba.cba_cf = &pccbb_funcs;		cba.cba_intrline = sc->sc_intrline;#if rbus		cba.cba_rbus_iot = sc->sc_rbus_iot;		cba.cba_rbus_memt = sc->sc_rbus_memt;#endif		cba.cba_cacheline = PCI_CACHELINE(bhlc);		cba.cba_lattimer = PCI_CB_LATENCY(busreg);#if defined CBB_DEBUG		printf("%s: cacheline 0x%x lattimer 0x%x\n",		    sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer);		printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc,		    busreg);#endif#if defined SHOW_REGS		cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt,		    sc->sc_base_memh);#endif	}	pccbb_pcmcia_attach_setup(sc, &paa);	caa.caa_cb_attach = NULL;	if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) {		caa.caa_cb_attach = &cba;	}	caa.caa_16_attach = &paa;	caa.caa_ph = &sc->sc_pcmcia_h;	if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) {		DPRINTF(("pccbbattach: found cardslot\n"));		sc->sc_csc = csc;	}	sc->sc_ints_on = 1;	/* CSC Interrupt: Card detect interrupt on */	maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);	maskreg |= CB_SOCKET_MASK_CD;  /* Card detect intr is turned on. */	bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg);	/* reset interrupt */	bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT,	    bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT));	return;}/* * void pccbb_chipinit(struct pccbb_softc *sc) * *   This function initialize YENTA chip registers listed below: *     1) PCI command reg, *     2) PCI and CardBus latency timer, *     3) route PCI interrupt, *     4) close all memory and io windows. */voidpccbb_chipinit(sc)	struct pccbb_softc *sc;{	pci_chipset_tag_t pc = sc->sc_pc;	pcitag_t tag = sc->sc_tag;	pcireg_t reg;	/*	 * Set PCI command reg.	 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip.	 */	reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);	/* I believe it is harmless. */	reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |	    PCI_COMMAND_MASTER_ENABLE);	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);	/*	 * Set CardBus latency timer.	 */	reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG);	if (PCI_CB_LATENCY(reg) < 0x20) {		reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT);		reg |= (0x20 << PCI_CB_LATENCY_SHIFT);		pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg);	}	DPRINTF(("CardBus latency timer 0x%x (%x)\n",	    PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG)));	/*	 * Set PCI latency timer.	 */	reg = pci_conf_read(pc, tag, PCI_BHLC_REG);	if (PCI_LATTIMER(reg) < 0x10) {		reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);		reg |= (0x10 << PCI_LATTIMER_SHIFT);		pci_conf_write(pc, tag, PCI_BHLC_REG, reg);	}	DPRINTF(("PCI latency timer 0x%x (%x)\n",	    PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG)));	/* Route functional interrupts to PCI. */	reg = pci_conf_read(pc, tag, PCI_BCR_INTR);	reg |= CB_BCR_INTR_IREQ_ENABLE;		/* disable PCI Intr */	reg |= CB_BCR_WRITE_POST_ENABLE;	/* enable write post */	reg |= CB_BCR_RESET_ENABLE;		/* assert reset */	pci_conf_write(pc, tag, PCI_BCR_INTR, reg);	switch (sc->sc_chipset) {	case CB_TI113X:		reg = pci_conf_read(pc, tag, PCI_CBCTRL);		/* This bit is shared, but may read as 0 on some chips, so set		   it explicitly on both functions. */		reg |= PCI113X_CBCTRL_PCI_IRQ_ENA;		/* CSC intr enable */		reg |= PCI113X_CBCTRL_PCI_CSC;		/* functional intr prohibit | prohibit ISA routing */		reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK);		pci_conf_write(pc, tag, PCI_CBCTRL, reg);		break;	case CB_TOPIC95B:		reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL);		reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;		pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg);		reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);		DPRINTF(("%s: topic slot ctrl reg 0x%x -> ",		    sc->sc_dev.dv_xname, reg));		reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |		    TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);		reg &= ~TOPIC_SLOT_CTRL_SWDETECT;		DPRINTF(("0x%x\n", reg));		pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg);		break;	}	/* Close all memory and I/O windows. */	pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff);	pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0);	pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff);	pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0);	pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff);	pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0);	pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff);	pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0);	/* reset 16-bit pcmcia bus */	bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh,	    0x800 + PCIC_INTR,	    bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh,		0x800 + PCIC_INTR) & ~PCIC_INTR_RESET);	/* turn off power */	pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);}/* * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc, *					 struct pcmciabus_attach_args *paa) * *   This function attaches 16-bit PCcard bus. */voidpccbb_pcmcia_attach_setup(sc, paa)	struct pccbb_softc *sc;	struct pcmciabus_attach_args *paa;{	struct pcic_handle *ph = &sc->sc_pcmcia_h;#if rbus	rbus_tag_t rb;#endif	/* initialize pcmcia part in pccbb_softc */	ph->ph_parent = (struct device *)sc;	ph->sock = sc->sc_function;	ph->flags = 0;	ph->shutdown = 0;	ph->ih_irq = sc->sc_intrline;	ph->ph_bus_t = sc->sc_base_memt;	ph->ph_bus_h = sc->sc_base_memh;	ph->ph_read = pccbb_pcmcia_read;	ph->ph_write = pccbb_pcmcia_write;	sc->sc_pct = &pccbb_pcmcia_funcs;	/*	 * We need to do a few things here:	 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by	 *    setting the IRQ numbers to 0.	 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable	 *    routing of CSC interrupts (e.g. card removal) to PCI while in	 *    PCMCIA mode.  We just leave this set all the time.	 * 3) Enable card insertion/removal interrupts in case the chip also	 *    needs that while in PCMCIA mode.	 * 4) Clear any pending CSC interrupt.	 */	Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET);	if (sc->sc_chipset == CB_TI113X) {		Pcic_write(ph, PCIC_CSC_INTR, 0);	} else {		Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE);		Pcic_read(ph, PCIC_CSC);	}	/* initialize pcmcia bus attachment */	paa->paa_busname = "pcmcia";	paa->pct = sc->sc_pct;	paa->pch = ph;	paa->iobase = 0;	       /* I don't use them */	paa->iosize = 0;#if rbus	rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot;	paa->iobase = rb->rb_start + rb->rb_offset;	paa->iosize = rb->rb_end - rb->rb_start;#endif	return;}#if 0voidpccbb_pcmcia_attach_card(ph)	struct pcic_handle *ph;{	if (ph->flags & PCIC_FLAG_CARDP) {		panic("pccbb_pcmcia_attach_card: already attached");	}	/* call the MI attach function */	pcmcia_card_attach(ph->pcmcia);	ph->flags |= PCIC_FLAG_CARDP;}voidpccbb_pcmcia_detach_card(ph, flags)	struct pcic_handle *ph;	int flags;{	if (!(ph->flags & PCIC_FLAG_CARDP)) {		panic("pccbb_pcmcia_detach_card: already detached");	}	ph->flags &= ~PCIC_FLAG_CARDP;	/* call the MI detach function */	pcmcia_card_detach(ph->pcmcia, flags);}#endif/* * int pccbbintr(arg) *    void *arg; *   This routine handles the interrupt from Yenta PCI-CardBus bridge *   itself. */intpccbbintr(arg)	void *arg;{	struct pccbb_softc *sc = (struct pccbb_softc *)arg;	u_int32_t sockevent, sockstate;	bus_space_tag_t memt = sc->sc_base_memt;	bus_space_handle_t memh = sc->sc_base_memh;	struct pcic_handle *ph = &sc->sc_pcmcia_h;	if (!sc->sc_ints_on)		return 0;	sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT);	bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent);	Pcic_read(ph, PCIC_CSC);	if (sockevent == 0) {		/* This intr is not for me: it may be for my child devices. */		if (sc->sc_pil_intr_enable) {			return pccbbintr_function(sc);		} else {			return 0;		}	}	if (sockevent & CB_SOCKET_EVENT_CD) {		sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT);		if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) {			/* A card should be removed. */			if (sc->sc_flags & CBB_CARDEXIST) {				DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname,				    sockevent));				DPRINTF((" card removed, 0x%08x\n", sockstate));				sc->sc_flags &= ~CBB_CARDEXIST;				if (sc->sc_csc->sc_status &				    CARDSLOT_STATUS_CARD_16) {#if 0					struct pcic_handle *ph =					    &sc->sc_pcmcia_h;					pcmcia_card_deactivate(ph->pcmcia);					pccbb_pcmcia_socket_disable(ph);					pccbb_pcmcia_detach_card(ph,					    DETACH_FORCE);#endif					cardslot_event_throw(sc->sc_csc,					    CARDSLOT_EVENT_REMOVAL_16);				} else if (sc->sc_csc->sc_status &				    CARDSLOT_STATUS_CARD_CB) {					/* Cardbus intr removed */					cardslot_event_throw(sc->sc_csc,					    CARDSLOT_EVENT_REMOVAL_CB);				}			}		} else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) &&		    /*		     * The pccbbintr may called from powerdown hook when		     * the system resumed, to detect the card		     * insertion/removal during suspension.		     */		    (sc->sc_flags & CBB_CARDEXIST) == 0) {			if (sc->sc_flags & CBB_INSERTING) {				timeout_del(&sc->sc_ins_tmo);			}			timeout_add(&sc->sc_ins_tmo, hz / 10);			sc->sc_flags |= CBB_INSERTING;		}	}	return (1);}/* * int pccbbintr_function(struct pccbb_softc *sc) * *    This function calls each interrupt handler registered at the *    bridge.  The interrupt handlers are called in registered order. */intpccbbintr_function(sc)	struct pccbb_softc *sc;{	int retval = 0, val;	struct pccbb_intrhand_list *pil;	int s, splchanged;	for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) {		/*		 * XXX priority change.  gross.  I use if-else		 * sentense instead of switch-case sentense because of		 * avoiding duplicate case value error.  More than one		 * IPL_XXX use same value.  It depends on		 * implementation.		 */		splchanged = 1;#if 0		if (pil->pil_level == IPL_SERIAL) {			s = splserial();		} else if (pil->pil_level == IPL_HIGH) {#endif		if (pil->pil_level == IPL_HIGH) {			s = splhigh();		} else if (pil->pil_level == IPL_CLOCK) {			s = splclock();		} else if (pil->pil_level == IPL_AUDIO) {			s = splaudio();		} else if (pil->pil_level == IPL_IMP) {			s = splimp();		} else if (pil->pil_level == IPL_TTY) {			s = spltty();#if 0		} else if (pil->pil_level == IPL_SOFTSERIAL) {			s = splsoftserial();#endif		} else if (pil->pil_level == IPL_NET) {			s = splnet();		} else {			splchanged = 0;			/* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */		}		val = (*pil->pil_func)(pil->pil_arg);		if (splchanged != 0) {			splx(s);		}		retval = retval == 1 ? 1 :		    retval == 0 ? val : val != 0 ? val : retval;	}	return retval;}voidpci113x_insert(arg)	void *arg;{	struct pccbb_softc *sc = (struct pccbb_softc *)arg;	u_int32_t sockevent, sockstate;	sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,	    CB_SOCKET_EVENT);	sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,	    CB_SOCKET_STAT);	if (0 == (sockstate & CB_SOCKET_STAT_CD)) {	/* card exist */		DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent));		DPRINTF((" card inserted, 0x%08x\n", sockstate));		sc->sc_flags |= CBB_CARDEXIST;		/* call pccard interrupt handler here */		if (sockstate & CB_SOCKET_STAT_16BIT) {			/* 16-bit card found *//*      pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */			cardslot_event_throw(sc->sc_csc,			    CARDSLOT_EVENT_INSERTION_16);		} else if (sockstate & CB_SOCKET_STAT_CB) {			/* cardbus card found *//*      cardbus_attach_card(sc->sc_csc); */			cardslot_event_throw(sc->sc_csc,			    CARDSLOT_EVENT_INSERTION_CB);		} else {			/* who are you? */		}	} else {		timeout_add(&sc->sc_ins_tmo, hz / 10);	}}#define PCCBB_PCMCIA_OFFSET 0x800u_int8_tpccbb_pcmcia_read(ph, reg)	struct pcic_handle *ph;	int reg;{	bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h,	    PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ);	return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h,	    PCCBB_PCMCIA_OFFSET + reg);}voidpccbb_pcmcia_write(ph, reg, val)	struct pcic_handle *ph;	int reg;	u_int8_t val;{	bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h,	    PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE);	bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg,	    val);}/* * int pccbb_ctrl(cardbus_chipset_tag_t, int) */intpccbb_ctrl(ct, command)	cardbus_chipset_tag_t ct;	int command;{	struct pccbb_softc *sc = (struct pccbb_softc *)ct;	switch (command) {	case CARDBUS_CD:		if (2 == pccbb_detect_card(sc)) {			int retval = 0;			int status = cb_detect_voltage(sc);			if (PCCARD_VCC_5V & status) {				retval |= CARDBUS_5V_CARD;			}			if (PCCARD_VCC_3V & status) {				retval |= CARDBUS_3V_CARD;			}			if (PCCARD_VCC_XV & status) {				retval |= CARDBUS_XV_CARD;			}			if (PCCARD_VCC_YV & status) {				retval |= CARDBUS_YV_CARD;			}			return retval;		} else {			return 0;		}		break;	case CARDBUS_RESET:		return cb_reset(sc);		break;	case CARDBUS_IO_ENABLE:       /* fallthrough */	case CARDBUS_IO_DISABLE:      /* fallthrough */	case CARDBUS_MEM_ENABLE:      /* fallthrough */	case CARDBUS_MEM_DISABLE:     /* fallthrough */	case CARDBUS_BM_ENABLE:       /* fallthrough */	case CARDBUS_BM_DISABLE:      /* fallthrough */		return pccbb_cardenable(sc, command);		break;	}	return 0;}/* * int pccbb_power(cardbus_chipset_tag_t, int) *   This function returns true when it succeeds and returns false when *   it fails. */intpccbb_power(ct, command)	cardbus_chipset_tag_t ct;	int command;{	struct pccbb_softc *sc = (struct pccbb_softc *)ct;	u_int32_t status, sock_ctrl;	bus_space_tag_t memt = sc->sc_base_memt;	bus_space_handle_t memh = sc->sc_base_memh;	DPRINTF(("pccbb_power: %s and %s [%x]\n",	    (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" :	    (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" :	    (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" :	    (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" :	    (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" :	    (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" :	    "UNKNOWN",	    (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" :	    (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" :	    (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" :	    (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" :	    "UNKNOWN", command));	status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);	sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL);	switch (command & CARDBUS_VCCMASK) {	case CARDBUS_VCC_UC:		break;	case CARDBUS_VCC_5V:		if (CB_SOCKET_STAT_5VCARD & status) {	/* check 5 V card */			sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;			sock_ctrl |= CB_SOCKET_CTRL_VCC_5V;		} else {			printf("%s: BAD voltage request: no 5 V card\n",			    sc->sc_dev.dv_xname);		}		break;	case CARDBUS_VCC_3V:		if (CB_SOCKET_STAT_3VCARD & status) {			sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;			sock_ctrl |= CB_SOCKET_CTRL_VCC_3V;		} else {			printf("%s: BAD voltage request: no 3.3 V card\n",			    sc->sc_dev.dv_xname);		}		break;	case CARDBUS_VCC_0V:		sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;		break;	default:		return 0;	       /* power NEVER changed */		break;	}	switch (command & CARDBUS_VPPMASK) {	case CARDBUS_VPP_UC:		break;	case CARDBUS_VPP_0V:		sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;		break;	case CARDBUS_VPP_VCC:		sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;		sock_ctrl |= ((sock_ctrl >> 4) & 0x07);		break;	case CARDBUS_VPP_12V:		sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;		sock_ctrl |= CB_SOCKET_CTRL_VPP_12V;		break;	}#if 0	DPRINTF(("sock_ctrl: %x\n", sock_ctrl));#endif	bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl);	status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);	if (status & CB_SOCKET_STAT_BADVCC) {	/* bad Vcc request */		printf		    ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n",		    sc->sc_dev.dv_xname, sock_ctrl, status);		DPRINTF(("pccbb_power: %s and %s [%x]\n",		    (command & CARDBUS_VCCMASK) ==		    CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command &		    CARDBUS_VCCMASK) ==		    CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command &		    CARDBUS_VCCMASK) ==		    CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command &		    CARDBUS_VCCMASK) ==		    CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command &		    CARDBUS_VCCMASK) ==		    CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command &		    CARDBUS_VCCMASK) ==		    CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN",		    (command & CARDBUS_VPPMASK) ==		    CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command &		    CARDBUS_VPPMASK) ==		    CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command &		    CARDBUS_VPPMASK) ==		    CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command &		    CARDBUS_VPPMASK) ==		    CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command));#if 0		if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) {			u_int32_t force =			    bus_space_read_4(memt, memh, CB_SOCKET_FORCE);			/* Reset Bad Vcc request */			force &= ~CB_SOCKET_FORCE_BADVCC;			bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force);			printf("new status 0x%x\n", bus_space_read_4(memt, memh,			    CB_SOCKET_STAT));			return 1;		}#endif		return 0;	}	/*	 * XXX delay 300 ms: though the standard defines that the Vcc set-up	 * time is 20 ms, some PC-Card bridge requires longer duration.	 */	delay(300 * 1000);	return 1;		       /* power changed correctly */}#if defined CB_PCMCIA_POLLstruct cb_poll_str {	void *arg;	int (*func)(void *);	int level;	pccard_chipset_tag_t ct;	int count;};static struct cb_poll_str cb_poll[10];static int cb_poll_n = 0;static struct timeout cb_poll_timeout;void cb_pcmcia_poll(void *arg);voidcb_pcmcia_poll(arg)	void *arg;{	struct cb_poll_str *poll = arg;	struct cbb_pcmcia_softc *psc = (void *)poll->ct->v;	struct pccbb_softc *sc = psc->cpc_parent;	int s;	u_int32_t spsr;		       /* socket present-state reg */	timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg);	timeout_add(&cb_poll_timeout, hz / 10);	switch (poll->level) {	case IPL_NET:		s = splnet();		break;	case IPL_BIO:		s = splbio();		break;	case IPL_TTY:		       /* fallthrough */	default:		s = spltty();		break;	}	spsr =	    bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,	    CB_SOCKET_STAT);#if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2	if (!(spsr & 0x40)) {	       /* CINT low */#else	if (1) {#endif		if ((*poll->func) (poll->arg) == 1) {			++poll->count;			printf("intr: reported from poller, 0x%x\n", spsr);#if defined LEVEL2		} else {			printf("intr: miss! 0x%x\n", spsr);#endif		}	}	splx(s);}#endif /* defined CB_PCMCIA_POLL *//* * int pccbb_detect_card(struct pccbb_softc *sc) *   return value:  0 if no card exists. *                  1 if 16-bit card exists. *                  2 if cardbus card exists. */intpccbb_detect_card(sc)	struct pccbb_softc *sc;{	bus_space_handle_t base_memh = sc->sc_base_memh;	bus_space_tag_t base_memt = sc->sc_base_memt;	u_int32_t sockstat =	    bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT);	int retval = 0;	/*	 * The SCM Microsystems TI1225-based PCI-CardBus dock card that	 * ships with some Lucent WaveLAN cards has only one physical slot	 * but OpenBSD probes two. The phantom card in the second slot can	 * be ignored by punting on unsupported voltages.	 */	if (sockstat & CB_SOCKET_STAT_XVCARD)		return 0;	/* CD1 and CD2 asserted */	if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) {		/* card must be present */		if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) {			/* NOTACARD DEASSERTED */			if (CB_SOCKET_STAT_CB & sockstat) {				/* CardBus mode */				retval = 2;			} else if (CB_SOCKET_STAT_16BIT & sockstat) {				/* 16-bit mode */				retval = 1;			}		}	}	return retval;}/* * int cb_reset(struct pccbb_softc *sc) *   This function resets CardBus card. */intcb_reset(sc)	struct pccbb_softc *sc;{	/*	 * Reset Assert at least 20 ms	 * Some machines request longer duration.	 */	int reset_duration =	    (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000);	u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);	/* Reset bit Assert (bit 6 at 0x3E) */	bcr |= CB_BCR_RESET_ENABLE;	pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr);	delay(reset_duration);	if (CBB_CARDEXIST & sc->sc_flags) {	/* A card exists.  Reset it! */		/* Reset bit Deassert (bit 6 at 0x3E) */		bcr &= ~CB_BCR_RESET_ENABLE;		pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr);		delay(reset_duration);	}	/* No card found on the slot. Keep Reset. */	return 1;}/* * int cb_detect_voltage(struct pccbb_softc *sc) *  This function detect card Voltage. */intcb_detect_voltage(sc)	struct pccbb_softc *sc;{	u_int32_t psr;		       /* socket present-state reg */	bus_space_tag_t iot = sc->sc_base_memt;	bus_space_handle_t ioh = sc->sc_base_memh;	int vol = PCCARD_VCC_UKN;      /* set 0 */	psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT);	if (0x400u & psr) {		vol |= PCCARD_VCC_5V;	}	if (0x800u & psr) {		vol |= PCCARD_VCC_3V;	}	return vol;}intcbbprint(aux, pcic)	void *aux;	const char *pcic;{/*  struct cbslot_attach_args *cba = aux;  if (cba->cba_slot >= 0) {    printf(" slot %d", cba->cba_slot);  }*/	return UNCONF;}/* * int pccbb_cardenable(struct pccbb_softc *sc, int function) *   This function enables and disables the card */intpccbb_cardenable(sc, function)	struct pccbb_softc *sc;	int function;{	u_int32_t command =	    pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);	DPRINTF(("pccbb_cardenable:"));	switch (function) {	case CARDBUS_IO_ENABLE:		command |= PCI_COMMAND_IO_ENABLE;		break;	case CARDBUS_IO_DISABLE:		command &= ~PCI_COMMAND_IO_ENABLE;		break;	case CARDBUS_MEM_ENABLE:		command |= PCI_COMMAND_MEM_ENABLE;		break;	case CARDBUS_MEM_DISABLE:		command &= ~PCI_COMMAND_MEM_ENABLE;		break;	case CARDBUS_BM_ENABLE:		command |= PCI_COMMAND_MASTER_ENABLE;		break;	case CARDBUS_BM_DISABLE:		command &= ~PCI_COMMAND_MASTER_ENABLE;		break;	default:		return 0;	}	pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command);	DPRINTF((" command reg 0x%x\n", command));	return 1;}#if !rbus/* * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) */intpccbb_io_open(ct, win, start, end)	cardbus_chipset_tag_t ct;	int win;	u_int32_t start, end;{	struct pccbb_softc *sc = (struct pccbb_softc *)ct;	int basereg;	int limitreg;	if ((win < 0) || (win > 2)) {#if defined DIAGNOSTIC		printf("cardbus_io_open: window out of range %d\n", win);#endif		return 0;	}	basereg = win * 8 + 0x2c;	limitreg = win * 8 + 0x30;	DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n",	    start, basereg, end, limitreg));	pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start);	pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end);	return 1;}/* * int pccbb_io_close(cardbus_chipset_tag_t, int) */intpccbb_io_close(ct, win)	cardbus_chipset_tag_t ct;	int win;{	struct pccbb_softc *sc = (struct pccbb_softc *)ct;	int basereg;	int limitreg;	if ((win < 0) || (win > 2)) {#if defined DIAGNOSTIC		printf("cardbus_io_close: window out of range %d\n", win);#endif		return 0;	}	basereg = win * 8 + 0x2c;	limitreg = win * 8 + 0x30;	pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0);	pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0);	return 1;}/* * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t) */intpccbb_mem_open(ct, win, start, end)	cardbus_chipset_tag_t ct;	int win;	u_int32_t start, end;{	struct pccbb_softc *sc = (struct pccbb_softc *)ct;	int basereg;	int limitreg;	if ((win < 0) || (win > 2)) {#if defined DIAGNOSTIC		printf("cardbus_mem_open: window out of range %d\n", win);#endif		return 0;	}	basereg = win * 8 + 0x1c;	limitreg = win * 8 + 0x20;	pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start);	pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end);	return 1;}/* * int pccbb_mem_close(cardbus_chipset_tag_t, int) */intpccbb_mem_close(ct, win)	cardbus_chipset_tag_t ct;	int win;{	struct pccbb_softc *sc = (struct pccbb_softc *)ct;	int basereg;	int limitreg;	if ((win < 0) || (win > 2)) {#if defined DIAGNOSTIC		printf("cardbus_mem_close: window out of range %d\n", win);#endif		return 0;	}	basereg = win * 8 + 0x1c;	limitreg = win * 8 + 0x20;	pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0);	pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0);	return 1;}#endif/* * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct, *					int irq, *					int level, *					int (* func)(void *), *					void *arg) * *   This function registers an interrupt handler at the bridge, in *   order not to call the interrupt handlers of child devices when *   a card-deletion interrupt occurs. * *   The arguments irq is not used because pccbb selects intr vector. */void *pccbb_cb_intr_establish(ct, irq, level, func, arg)	cardbus_chipset_tag_t ct;	int irq, level;	int (*func)(void *);	void *arg;{	struct pccbb_softc *sc = (struct pccbb_softc *)ct;	return pccbb_intr_establish(sc, irq, level, func, arg);}/* * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, *					   void *ih) * *   This function removes an interrupt handler pointed by ih. */voidpccbb_cb_intr_disestablish(ct, ih)	cardbus_chipset_tag_t ct;	void *ih;{	struct pccbb_softc *sc = (struct pccbb_softc *)ct;	pccbb_intr_disestablish(sc, ih);}/* * void *pccbb_intr_establish(struct pccbb_softc *sc, *				     int irq, *				     int level, *				     int (* func)(void *), *				     void *arg) * *   This function registers an interrupt handler at the bridge, in *   order not to call the interrupt handlers of child devices when *   a card-deletion interrupt occurs. * *   The arguments irq and level are not used. */void *pccbb_intr_establish(sc, irq, level, func, arg)	struct pccbb_softc *sc;	int irq, level;	int (*func)(void *);	void *arg;{	struct pccbb_intrhand_list *pil, *newpil;	pcireg_t reg;	DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil));	if (sc->sc_pil == NULL) {		/* initialize bridge intr routing */		reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);		reg &= ~CB_BCR_INTR_IREQ_ENABLE;		pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);		switch (sc->sc_chipset) {		case CB_TI113X:			reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);			/* functional intr enabled */			reg |= PCI113X_CBCTRL_PCI_INTR;			pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);			break;		default:			break;		}	}	/*	 * Allocate a room for interrupt handler structure.	 */	newpil = (struct pccbb_intrhand_list *)		malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK);	newpil->pil_func = func;	newpil->pil_arg = arg;	newpil->pil_level = level;	newpil->pil_next = NULL;	if (sc->sc_pil == NULL) {		sc->sc_pil = newpil;	} else {		for (pil = sc->sc_pil; pil->pil_next != NULL;		    pil = pil->pil_next);		pil->pil_next = newpil;	}	DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil));	return newpil;}