if (sp->device_type == XFRAME_II_DEVICE) { int write_cnt = (cnt == 8) ? 0 : cnt; writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);  val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | SPI_CONTROL_BYTECNT(write_cnt) | SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off); SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); val64 |= SPI_CONTROL_REQ; SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); while (exit_cnt < 5) { val64 = readq(&bar0->spi_control); if (val64 & SPI_CONTROL_NACK) { ret = 1; break; } else if (val64 & SPI_CONTROL_DONE) { ret = 0; break; } msleep(50); exit_cnt++; } }
static int write_eeprom(nic_t * sp, int off, u32 data, int cnt){	int exit_cnt = 0, ret = -1;	u64 val64;	XENA_dev_config_t __iomem *bar0 = sp->bar0;	val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |	    I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA(data) |	    I2C_CONTROL_CNTL_START;	SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);	while (exit_cnt < 5) {		val64 = readq(&bar0->i2c_control);		if (I2C_CONTROL_CNTL_END(val64)) {			if (!(val64 & I2C_CONTROL_NACK))				ret = 0;			break;		}		msleep(50);		exit_cnt++;	}	return ret;}