if (clk->flags & RATE_CKCTL) { dsor_exp = calc_dsor_exp(clk, rate); if (dsor_exp > 3) dsor_exp = -EINVAL; if (dsor_exp < 0) return dsor_exp;  spin_lock_irqsave(&clockfw_lock, flags); regval = omap_readw(ARM_CKCTL); regval &= ~(3 << clk->rate_offset); regval |= dsor_exp << clk->rate_offset; regval = verify_ckctl_value(regval); omap_writew(regval, ARM_CKCTL); clk->rate = clk->parent->rate / (1 << dsor_exp); spin_unlock_irqrestore(&clockfw_lock, flags); ret = 0; } else if(clk->set_rate != 0) { spin_lock_irqsave(&clockfw_lock, flags); ret = clk->set_rate(clk, rate); spin_unlock_irqrestore(&clockfw_lock, flags); }  if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) propagate_rate(clk);
spin_lock_irqsave(&clockfw_lock, flags); if (arch_clock->clk_set_rate) ret = arch_clock->clk_set_rate(clk, rate); spin_unlock_irqrestore(&clockfw_lock, flags);
int clk_set_rate(struct clk *clk, unsigned long rate){	int  ret = -EINVAL;	int  dsor_exp;	__u16  regval;	unsigned long  flags;	if (clk->flags & RATE_CKCTL) {		dsor_exp = calc_dsor_exp(clk, rate);		if (dsor_exp > 3)			dsor_exp = -EINVAL;		if (dsor_exp < 0)			return dsor_exp;		spin_lock_irqsave(&clockfw_lock, flags);		regval = omap_readw(ARM_CKCTL);		regval &= ~(3 << clk->rate_offset);		regval |= dsor_exp << clk->rate_offset;		regval = verify_ckctl_value(regval);		omap_writew(regval, ARM_CKCTL);		clk->rate = clk->parent->rate / (1 << dsor_exp);		spin_unlock_irqrestore(&clockfw_lock, flags);		ret = 0;	} else if(clk->set_rate != 0) {		spin_lock_irqsave(&clockfw_lock, flags);		ret = clk->set_rate(clk, rate);		spin_unlock_irqrestore(&clockfw_lock, flags);	}	if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))		propagate_rate(clk);	return ret;}