outb(vgaCRIndex,resetidx);
S3VGEReset(int from_timeout, int line, char *file){    unsigned long gs1, gs2;   /* -- debug info for graphics state -- */    unsigned char tmp, sr1, resetidx;    int r;    int ge_was_on = 0;    int32  fifo_control, miu_control, streams_timeout, misc_timeout;    if (S3_TRIO_3D_SERIES(s3vPriv.chip)) {      outb(0x3c4,0x01);      sr1 = inb(0x3c5);      if (sr1 & 0x20) {        if (xf86Verbose > 1)          ErrorF("\tTrio3D -- Display is on...turning off\n");        outb(0x3c5,sr1 & ~0x20);        VerticalRetraceWait();      }         }    if (from_timeout) {      static int n=0;      if (n++ < 10 || xf86Verbose > 1)	ErrorF("\tS3VGEReset called from %s line %d\n",file,line);    }    else {      if (S3_TRIO_3D_SERIES(s3vPriv.chip))        S3VNopAllCmdSets();      WaitIdleEmpty();    }    if (from_timeout && (s3vPriv.chip == S3_ViRGE || s3vPriv.chip == S3_ViRGE_VX			 || s3vPriv.chip == S3_ViRGE_DXGX)) {      /* reset will trash these registers, so save them */      fifo_control    = ((mmtr)s3vMmioMem)->memport_regs.regs.fifo_control;      miu_control     = ((mmtr)s3vMmioMem)->memport_regs.regs.miu_control;      streams_timeout = ((mmtr)s3vMmioMem)->memport_regs.regs.streams_timeout;      misc_timeout    = ((mmtr)s3vMmioMem)->memport_regs.regs.misc_timeout;    }    if(s3vPriv.chip == S3_ViRGE_VX){        outb(vgaCRIndex, 0x63);        }    else {        outb(vgaCRIndex, 0x66);        }  if (!S3_TRIO_3D_SERIES(s3vPriv.chip)) {    tmp = inb(vgaCRReg);    usleep(10000);    for (r=1; r<10; r++) {  /* try multiple times to avoid lockup of ViRGE/MX */      outb(vgaCRReg, tmp | 0x02);      usleep(10000);      outb(vgaCRReg, tmp & ~0x02);      usleep(10000);      if (!from_timeout) 	WaitIdleEmpty();      SETB_DEST_SRC_STR(s3vPriv.Bpl, s3vPriv.Bpl);       usleep(10000);      if (((IN_SUBSYS_STAT() & 0x3f00) != 0x3000)) 	ErrorF("restarting S3 graphics engine reset %2d ...\n",r);      else	break;    } } else {    usleep(10000);    for (r=1; r<10; r++) {      VerticalRetraceWait();      outb(vgaCRIndex,resetidx);      tmp = inb(vgaCRReg);      outb(0x3c4,0x01);      sr1 = inb(0x3c5);      if(sr1 & 0x20) {        if(xf86Verbose > 1) {          ErrorF("\tTrio3D -- Upps Display is on again ...turning off\n");        }        outb(0x3c4,0x01);        VerticalRetraceWait();        outb(0x3c5,sr1 & ~0x20);      }      VerticalRetraceWait();      gs1   = (long) IN_SUBSYS_STAT();      /* turn off the GE */      if(tmp & 0x01) {        tmp &= ~0x01;        outb(vgaCRReg, tmp);        ge_was_on = 1;        usleep(10000);      }      gs2   = (long) IN_SUBSYS_STAT();      outb(vgaCRReg, (tmp | 0x02));      usleep(10000);      VerticalRetraceWait();      outb(vgaCRReg, (tmp & ~0x02));      usleep(10000);      if(ge_was_on) {        tmp |= 0x01;        outb(vgaCRReg, tmp);        usleep(10000);      }      if (xf86Verbose > 2) {          ErrorF("\tTrio3D -- GE was %s ST#1: 0x%08lx ST#2: 0x%08lx\n",             (ge_was_on) ? "on" : "off",             (long)(gs1 & 0x3f802000),             (long)(gs2 & 0x3f802000) );      }      VerticalRetraceWait();      if (!from_timeout) {        S3VNopAllCmdSets();        WaitIdleEmpty();      }      SETB_DEST_SRC_STR(s3vPriv.Bpl,s3vPriv.Bpl);      usleep(10000);      if((IN_SUBSYS_STAT() & 0x3f802000) != 0x20002000) {        if(xf86Verbose > 1)          ErrorF("restarting S3 graphics engine reset %2d ..."                 "%lx\n",r,IN_SUBSYS_STAT() & 0x3f802000);      }        else          break;    }    }    if (from_timeout && (s3vPriv.chip == S3_ViRGE || s3vPriv.chip == S3_ViRGE_VX			 || s3vPriv.chip == S3_ViRGE_DXGX)) {      /* restore trashed registers */      ((mmtr)s3vMmioMem)->memport_regs.regs.fifo_control    = fifo_control;      ((mmtr)s3vMmioMem)->memport_regs.regs.miu_control     = miu_control;      ((mmtr)s3vMmioMem)->memport_regs.regs.streams_timeout = streams_timeout;      ((mmtr)s3vMmioMem)->memport_regs.regs.misc_timeout    = misc_timeout;    }    SETB_SRC_BASE(0);    SETB_DEST_BASE(0);       /* Now write some default rgisters and reset cached values */    s3vCached_CLIP_LR = -1;    s3vCached_CLIP_TB = -1;    CACHE_SETB_CLIP_L_R(0, s3vPriv.Width);    CACHE_SETB_CLIP_T_B(0, s3vPriv.ScissB);    s3vCached_MONO_PATTERN0 = 0;    s3vCached_MONO_PATTERN1 = 0;    CACHE_SETB_MONO_PAT0(~0);    CACHE_SETB_MONO_PAT1(~0);       s3vCached_RWIDTH_HEIGHT = -1;    s3vCached_PAT_FGCLR = -1;    s3vCached_PAT_BGCLR = -1;    s3vCached_CMD_SET = -1;    if (xf86Verbose > 1)        ErrorF("ViRGE register cache hits: %d misses: %d\n",            s3vCacheHit, s3vCacheMiss);        s3vCacheHit = 0; s3vCacheMiss = 0;    if (!from_timeout && S3_TRIO_3D_SERIES(s3vPriv.chip))      S3VNopAllCmdSets();}