(val << EMAC_STACR_PHYD_SHIFT));
(val << EMAC_STACR_PHYD_SHIFT) | EMAC_STACR_START);
static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg,			      u16 val){	struct emac_regs *p = dev->emacp;	int n;	DBG2("%d: mdio_write(%02x,%02x,%04x)" NL, dev->def->index, id, reg,	     val);	/* Enable proper MDIO port */	zmii_enable_mdio(dev->zmii_dev, dev->zmii_input);	/* Wait for management interface to be idle */	n = 10;	while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) {		udelay(1);		if (!--n)			goto to;	}	/* Issue write command */	out_be32(&p->stacr,		 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_WRITE |		 (reg & EMAC_STACR_PRA_MASK) |		 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |		 (val << EMAC_STACR_PHYD_SHIFT));	/* Wait for write to complete */	n = 100;	while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) {		udelay(1);		if (!--n)			goto to;	}	return;      to:	DBG("%d: MII management interface timeout (write)" NL, dev->def->index);}