if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, pa->pa_intrline, &ih)) {
if (pci_intr_map(pa, &ih)) {
void *lge_jalloc	__P((struct lge_softc *));void lge_jfree		__P((caddr_t, u_int, void *));int lge_newbuf		__P((struct lge_softc *, struct lge_rx_desc *,			     struct mbuf *));int lge_encap		__P((struct lge_softc *, struct mbuf *, u_int32_t *));void lge_rxeof		__P((struct lge_softc *, int));void lge_rxeoc		__P((struct lge_softc *));void lge_txeof		__P((struct lge_softc *));int lge_intr		__P((void *));void lge_tick		__P((void *));void lge_start		__P((struct ifnet *));int lge_ioctl		__P((struct ifnet *, u_long, caddr_t));void lge_init		__P((void *));void lge_stop		__P((struct lge_softc *));void lge_watchdog	__P((struct ifnet *));void lge_shutdown	__P((void *));int lge_ifmedia_upd	__P((struct ifnet *));void lge_ifmedia_sts	__P((struct ifnet *, struct ifmediareq *));void lge_eeprom_getword	__P((struct lge_softc *, int, u_int16_t *));void lge_read_eeprom	__P((struct lge_softc *, caddr_t, int, int, int));int lge_miibus_readreg	__P((struct device *, int, int));void lge_miibus_writereg	__P((struct device *, int, int, int));void lge_miibus_statchg	__P((struct device *));void lge_setmulti	__P((struct lge_softc *));u_int32_t lge_crc	__P((struct lge_softc *, caddr_t));void lge_reset		__P((struct lge_softc *));int lge_list_rx_init	__P((struct lge_softc *));int lge_list_tx_init	__P((struct lge_softc *));#ifdef LGE_USEIOSPACE#define LGE_RES			SYS_RES_IOPORT#define LGE_RID			LGE_PCI_LOIO#else#define LGE_RES			SYS_RES_MEMORY#define LGE_RID			LGE_PCI_LOMEM#endif#ifdef LGE_DEBUG#define DPRINTF(x)	if (lgedebug) printf x#define DPRINTFN(n,x)	if (lgedebug >= (n)) printf xint	lgedebug = 0;#else#define DPRINTF(x)#define DPRINTFN(n,x)#endif#define LGE_SETBIT(sc, reg, x)				\	CSR_WRITE_4(sc, reg,				\		CSR_READ_4(sc, reg) | (x))#define LGE_CLRBIT(sc, reg, x)				\	CSR_WRITE_4(sc, reg,				\		CSR_READ_4(sc, reg) & ~(x))#define SIO_SET(x)					\	CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)#define SIO_CLR(x)					\	CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)/* * Read a word of data stored in the EEPROM at address 'addr.' */void lge_eeprom_getword(sc, addr, dest)	struct lge_softc	*sc;	int			addr;	u_int16_t		*dest;{	register int		i;	u_int32_t		val;	CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|	    LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));	for (i = 0; i < LGE_TIMEOUT; i++)		if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))			break;	if (i == LGE_TIMEOUT) {		printf("%s: EEPROM read timed out\n", sc->sc_dv.dv_xname);		return;	}	val = CSR_READ_4(sc, LGE_EEDATA);	if (addr & 1)		*dest = (val >> 16) & 0xFFFF;	else		*dest = val & 0xFFFF;	return;}/* * Read a sequence of words from the EEPROM. */void lge_read_eeprom(sc, dest, off, cnt, swap)	struct lge_softc	*sc;	caddr_t			dest;	int			off;	int			cnt;	int			swap;{	int			i;	u_int16_t		word = 0, *ptr;	for (i = 0; i < cnt; i++) {		lge_eeprom_getword(sc, off + i, &word);		ptr = (u_int16_t *)(dest + (i * 2));		if (swap)			*ptr = ntohs(word);		else			*ptr = word;	}	return;}int lge_miibus_readreg(dev, phy, reg)	struct device *		dev;	int			phy, reg;{	struct lge_softc	*sc = (struct lge_softc *)dev;	int			i;	/*	 * If we have a non-PCS PHY, pretend that the internal	 * autoneg stuff at PHY address 0 isn't there so that	 * the miibus code will find only the GMII PHY.	 */	if (sc->lge_pcs == 0 && phy == 0)		return(0);	CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);	for (i = 0; i < LGE_TIMEOUT; i++)		if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))			break;	if (i == LGE_TIMEOUT) {		printf("%s: PHY read timed out\n", sc->sc_dv.dv_xname);		return(0);	}	return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);}void lge_miibus_writereg(dev, phy, reg, data)	struct device *		dev;	int			phy, reg, data;{	struct lge_softc	*sc = (struct lge_softc *)dev;	int			i;	CSR_WRITE_4(sc, LGE_GMIICTL,	    (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);	for (i = 0; i < LGE_TIMEOUT; i++)		if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))			break;	if (i == LGE_TIMEOUT) {		printf("%s: PHY write timed out\n", sc->sc_dv.dv_xname);	}}void lge_miibus_statchg(dev)	struct device *		dev;{	struct lge_softc	*sc = (struct lge_softc *)dev;	struct mii_data		*mii = &sc->lge_mii;	LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);	switch (IFM_SUBTYPE(mii->mii_media_active)) {	case IFM_1000_TX:	case IFM_1000_SX:		LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);		break;	case IFM_100_TX:		LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);		break;	case IFM_10_T:		LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);		break;	default:		/*		 * Choose something, even if it's wrong. Clearing		 * all the bits will hose autoneg on the internal		 * PHY.		 */		LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);		break;	}	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {		LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);	} else {		LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);	}	return;}u_int32_t lge_crc(sc, addr)	struct lge_softc	*sc;	caddr_t			addr;{	u_int32_t		crc, carry;	int			i, j;	u_int8_t		c;	/* Compute CRC for the address value. */	crc = 0xFFFFFFFF; /* initial value */	for (i = 0; i < 6; i++) {		c = *(addr + i);		for (j = 0; j < 8; j++) {			carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);			crc <<= 1;			c >>= 1;			if (carry)				crc = (crc ^ 0x04c11db6) | carry;		}	}	/*	 * return the filter bit position	 */	return((crc >> 26) & 0x0000003F);}void lge_setmulti(sc)	struct lge_softc	*sc;{	struct arpcom		*ac = &sc->arpcom;	struct ifnet		*ifp = &ac->ac_if;	struct ether_multi      *enm;	struct ether_multistep  step;	u_int32_t		h = 0, hashes[2] = { 0, 0 };	/* Make sure multicast hash table is enabled. */	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {		CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);		CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);		return;	}	/* first, zot all the existing hash bits */	CSR_WRITE_4(sc, LGE_MAR0, 0);	CSR_WRITE_4(sc, LGE_MAR1, 0);	/* now program new ones */	ETHER_FIRST_MULTI(step, ac, enm);	while (enm != NULL) {		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0)			continue;		h = lge_crc(sc, LLADDR((struct sockaddr_dl *)enm->enm_addrlo));		if (h < 32)			hashes[0] |= (1 << h);		else			hashes[1] |= (1 << (h - 32));		ETHER_NEXT_MULTI(step, enm);	}	CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);	CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);	return;}void lge_reset(sc)	struct lge_softc	*sc;{	register int		i;	LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);	for (i = 0; i < LGE_TIMEOUT; i++) {		if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))			break;	}	if (i == LGE_TIMEOUT)		printf("%s: reset never completed\n", sc->sc_dv.dv_xname);	/* Wait a little while for the chip to get its brains in order. */	DELAY(1000);        return;}/* * Probe for a Level 1 chip. Check the PCI vendor and device * IDs against our list and return a device name if we find a match. */int lge_probe(parent, match, aux)	struct device *parent;	void *match;	void *aux;{	struct pci_attach_args *pa = (struct pci_attach_args *)aux;	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LEVEL1 &&	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LEVEL1_LXT1001)		return (1);	return (0);}/* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */void lge_attach(parent, self, aux)	struct device *parent, *self;	void *aux;{	struct lge_softc	*sc = (struct lge_softc *)self;	struct pci_attach_args	*pa = aux;	pci_chipset_tag_t	pc = pa->pa_pc;	pci_intr_handle_t	ih;	const char		*intrstr = NULL;	bus_addr_t		iobase;	bus_size_t		iosize;	bus_dma_segment_t	seg;	bus_dmamap_t		dmamap;	int			s, rseg;	u_char			eaddr[ETHER_ADDR_LEN];	u_int32_t		command;	struct ifnet		*ifp;	int			error = 0;	caddr_t			kva;	s = splimp();	bzero(sc, sizeof(struct lge_softc));	/*	 * Handle power management nonsense.	 */	DPRINTFN(5, ("Preparing for conf read\n"));	command = pci_conf_read(pc, pa->pa_tag, LGE_PCI_CAPID) & 0x000000FF;	if (command == 0x01) {		command = pci_conf_read(pc, pa->pa_tag, LGE_PCI_PWRMGMTCTRL);		if (command & LGE_PSTATE_MASK) {			u_int32_t		iobase, membase, irq;			/* Save important PCI config data. */			iobase = pci_conf_read(pc, pa->pa_tag, LGE_PCI_LOIO);			membase = pci_conf_read(pc, pa->pa_tag, LGE_PCI_LOMEM);			irq = pci_conf_read(pc, pa->pa_tag, LGE_PCI_INTLINE);			/* Reset the power state. */			printf("%s: chip is in D%d power mode "			       "-- setting to D0\n", sc->sc_dv.dv_xname,			       command & LGE_PSTATE_MASK);			command &= 0xFFFFFFFC;			pci_conf_write(pc, pa->pa_tag,				       LGE_PCI_PWRMGMTCTRL, command);						/* Restore PCI config data. */			pci_conf_write(pc, pa->pa_tag, LGE_PCI_LOIO, iobase);			pci_conf_write(pc, pa->pa_tag, LGE_PCI_LOMEM, membase);			pci_conf_write(pc, pa->pa_tag, LGE_PCI_INTLINE, irq);		}	}	/*	 * Map control/status registers.	 */	DPRINTFN(5, ("Map control/status regs\n"));	command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);	command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |	  PCI_COMMAND_MASTER_ENABLE;	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);	command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);#ifdef LGE_USEIOSPACE	if (!(command & PCI_COMMAND_IO_ENABLE)) {		printf("%s: failed to enable I/O ports!\n",		       sc->sc_dv.dv_xname);		error = ENXIO;;		goto fail;	}	/*	 * Map control/status registers.	 */	DPRINTFN(5, ("pci_io_find\n"));	if (pci_io_find(pc, pa->pa_tag, LGE_PCI_LOIO, &iobase, &iosize)) {		printf(": can't find i/o space\n");		goto fail;	}	DPRINTFN(5, ("bus_space_map\n"));	if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->lge_bhandle)) {		printf(": can't map i/o space\n");		goto fail;	}	sc->lge_btag = pa->pa_iot;#else	if (!(command & PCI_COMMAND_MEM_ENABLE)) {		printf("%s: failed to enable memory mapping!\n",		       sc->sc_dv.dv_xname);		error = ENXIO;		goto fail;	}	DPRINTFN(5, ("pci_mem_find\n"));	if (pci_mem_find(pc, pa->pa_tag, LGE_PCI_LOMEM, &iobase,			 &iosize, NULL)) {		printf(": can't find mem space\n");		goto fail;	}	DPRINTFN(5, ("bus_space_map\n"));	if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->lge_bhandle)) {		printf(": can't map mem space\n");		goto fail;	}		sc->lge_btag = pa->pa_memt;#endif	DPRINTFN(5, ("pci_intr_map\n"));	if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,			 pa->pa_intrline, &ih)) {		printf(": couldn't map interrupt\n");		goto fail;	}	DPRINTFN(5, ("pci_intr_string\n"));	intrstr = pci_intr_string(pc, ih);	DPRINTFN(5, ("pci_intr_establish\n"));	sc->lge_intrhand = pci_intr_establish(pc, ih, IPL_NET, lge_intr, sc,					      sc->sc_dv.dv_xname);	if (sc->lge_intrhand == NULL) {		printf(": couldn't establish interrupt");		if (intrstr != NULL)			printf(" at %s", intrstr);		printf("\n");		goto fail;	}	printf(": %s", intrstr);	/* Reset the adapter. */	DPRINTFN(5, ("lge_reset\n"));	lge_reset(sc);	/*	 * Get station address from the EEPROM.	 */	DPRINTFN(5, ("lge_read_eeprom\n"));	lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);	lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);	lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);	/*	 * A Level 1 chip was detected. Inform the world.	 */	printf(": Ethernet address: %s\n", ether_sprintf(eaddr));	bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);	sc->sc_dmatag = pa->pa_dmat;	DPRINTFN(5, ("bus_dmamem_alloc\n"));	if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct lge_list_data),			     PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {		printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname);		goto fail;	}	DPRINTFN(5, ("bus_dmamem_map\n"));	if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg,			   sizeof(struct lge_list_data), &kva,			   BUS_DMA_NOWAIT)) {		printf("%s: can't map dma buffers (%d bytes)\n",		       sc->sc_dv.dv_xname, sizeof(struct lge_list_data));		bus_dmamem_free(sc->sc_dmatag, &seg, rseg);		goto fail;	}	DPRINTFN(5, ("bus_dmamem_create\n"));	if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct lge_list_data), 1,			      sizeof(struct lge_list_data), 0,			      BUS_DMA_NOWAIT, &dmamap)) {		printf("%s: can't create dma map\n", sc->sc_dv.dv_xname);		bus_dmamem_unmap(sc->sc_dmatag, kva,				 sizeof(struct lge_list_data));		bus_dmamem_free(sc->sc_dmatag, &seg, rseg);		goto fail;	}	DPRINTFN(5, ("bus_dmamem_load\n"));	if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva,			    sizeof(struct lge_list_data), NULL,			    BUS_DMA_NOWAIT)) {		bus_dmamap_destroy(sc->sc_dmatag, dmamap);		bus_dmamem_unmap(sc->sc_dmatag, kva,				 sizeof(struct lge_list_data));		bus_dmamem_free(sc->sc_dmatag, &seg, rseg);		goto fail;	}	DPRINTFN(5, ("bzero\n"));	sc->lge_ldata = (struct lge_list_data *)kva;	bzero(sc->lge_ldata, sizeof(struct lge_list_data));	/* Try to allocate memory for jumbo buffers. */	DPRINTFN(5, ("lge_alloc_jumbo_mem\n"));	if (lge_alloc_jumbo_mem(sc)) {		printf("%s: jumbo buffer allocation failed\n",		       sc->sc_dv.dv_xname);		goto fail;	}	ifp = &sc->arpcom.ac_if;	ifp->if_softc = sc;	ifp->if_mtu = ETHERMTU;	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;	ifp->if_ioctl = lge_ioctl;	ifp->if_output = ether_output;	ifp->if_start = lge_start;	ifp->if_watchdog = lge_watchdog;	ifp->if_baudrate = 1000000000;	ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;	DPRINTFN(5, ("bcopy\n"));	bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ);	if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)		sc->lge_pcs = 1;	else		sc->lge_pcs = 0;	/*	 * Do MII setup.	 */	DPRINTFN(5, ("mii setup\n"));	sc->lge_mii.mii_ifp = ifp;	sc->lge_mii.mii_readreg = lge_miibus_readreg;	sc->lge_mii.mii_writereg = lge_miibus_writereg;	sc->lge_mii.mii_statchg = lge_miibus_statchg;	ifmedia_init(&sc->lge_mii.mii_media, 0, lge_ifmedia_upd,		     lge_ifmedia_sts);	mii_attach(&sc->sc_dv, &sc->lge_mii, 0xffffffff, MII_PHY_ANY,		   MII_OFFSET_ANY, 0);	if (LIST_FIRST(&sc->lge_mii.mii_phys) == NULL) {		printf("%s: no PHY found!\n", sc->sc_dv.dv_xname);		ifmedia_add(&sc->lge_mii.mii_media, IFM_ETHER|IFM_MANUAL,			    0, NULL);		ifmedia_set(&sc->lge_mii.mii_media, IFM_ETHER|IFM_MANUAL);	}	else		ifmedia_set(&sc->lge_mii.mii_media, IFM_ETHER|IFM_AUTO);	/*	 * Call MI attach routine.	 */	DPRINTFN(5, ("if_attach\n"));	if_attach(ifp);	DPRINTFN(5, ("ether_ifattach\n"));	ether_ifattach(ifp);	DPRINTFN(5, ("timeout_set\n"));	timeout_set(&sc->lge_timeout, lge_tick, sc);	timeout_add(&sc->lge_timeout, hz);fail:	splx(s);}/* * Initialize the transmit descriptors. */int lge_list_tx_init(sc)	struct lge_softc	*sc;{	struct lge_list_data	*ld;	struct lge_ring_data	*cd;	int			i;	cd = &sc->lge_cdata;	ld = sc->lge_ldata;	for (i = 0; i < LGE_TX_LIST_CNT; i++) {		ld->lge_tx_list[i].lge_mbuf = NULL;		ld->lge_tx_list[i].lge_ctl = 0;	}	cd->lge_tx_prod = cd->lge_tx_cons = 0;	return(0);}/* * Initialize the RX descriptors and allocate mbufs for them. Note that * we arralge the descriptors in a closed ring, so that the last descriptor * points back to the first. */int lge_list_rx_init(sc)	struct lge_softc	*sc;{	struct lge_list_data	*ld;	struct lge_ring_data	*cd;	int			i;	ld = sc->lge_ldata;	cd = &sc->lge_cdata;	cd->lge_rx_prod = cd->lge_rx_cons = 0;	CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);	for (i = 0; i < LGE_RX_LIST_CNT; i++) {		if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)			break;		if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)			return(ENOBUFS);	}	/* Clear possible 'rx command queue empty' interrupt. */	CSR_READ_4(sc, LGE_ISR);	return(0);}/* * Initialize an RX descriptor and attach an MBUF cluster. */int lge_newbuf(sc, c, m)	struct lge_softc	*sc;	struct lge_rx_desc	*c;	struct mbuf		*m;{	struct mbuf		*m_new = NULL;	caddr_t			*buf = NULL;	if (m == NULL) {		MGETHDR(m_new, M_DONTWAIT, MT_DATA);		if (m_new == NULL) {			printf("%s: no memory for rx list "			       "-- packet dropped!\n", sc->sc_dv.dv_xname);			return(ENOBUFS);		}		/* Allocate the jumbo buffer */		buf = lge_jalloc(sc);		if (buf == NULL) {#ifdef LGE_VERBOSE			printf("%s: jumbo allocation failed "			       "-- packet dropped!\n", sc->sc_dv.dv_xname);#endif			m_freem(m_new);			return(ENOBUFS);		}		/* Attach the buffer to the mbuf */		m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;		m_new->m_flags |= M_EXT;		m_new->m_ext.ext_size = m_new->m_pkthdr.len =			m_new->m_len = LGE_JLEN;		m_new->m_ext.ext_free = lge_jfree;		m_new->m_ext.ext_arg = sc;		MCLINITREFERENCE(m_new);	} else {		m_new = m;		m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;		m_new->m_data = m_new->m_ext.ext_buf;	}	/*	 * Adjust alignment so packet payload begins on a	 * longword boundary. Mandatory for Alpha, useful on	 * x86 too.	*/	m_adj(m_new, ETHER_ALIGN);	c->lge_mbuf = m_new;	c->lge_fragptr_hi = 0;	c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));	c->lge_fraglen = m_new->m_len;	c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);	c->lge_sts = 0;	/*	 * Put this buffer in the RX command FIFO. To do this,	 * we just write the physical address of the descriptor	 * into the RX descriptor address registers. Note that	 * there are two registers, one high DWORD and one low	 * DWORD, which lets us specify a 64-bit address if	 * desired. We only use a 32-bit address for now.	 * Writing to the low DWORD register is what actually	 * causes the command to be issued, so we do that	 * last.	 */	CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));	LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);	return(0);}int lge_alloc_jumbo_mem(sc)	struct lge_softc	*sc;{	caddr_t			ptr, kva;	bus_dma_segment_t	seg;	bus_dmamap_t		dmamap;	int			i, rseg;	struct lge_jpool_entry   *entry;	/* Grab a big chunk o' storage. */	if (bus_dmamem_alloc(sc->sc_dmatag, LGE_JMEM, PAGE_SIZE, 0,			     &seg, 1, &rseg, BUS_DMA_NOWAIT)) {		printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname);		return (ENOBUFS);	}	if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, LGE_JMEM, &kva,			   BUS_DMA_NOWAIT)) {		printf("%s: can't map dma buffers (%d bytes)\n",		       sc->sc_dv.dv_xname, LGE_JMEM);		bus_dmamem_free(sc->sc_dmatag, &seg, rseg);		return (ENOBUFS);	}	if (bus_dmamap_create(sc->sc_dmatag, LGE_JMEM, 1,			      LGE_JMEM, 0, BUS_DMA_NOWAIT, &dmamap)) {		printf("%s: can't create dma map\n", sc->sc_dv.dv_xname);		bus_dmamem_unmap(sc->sc_dmatag, kva, LGE_JMEM);		bus_dmamem_free(sc->sc_dmatag, &seg, rseg);		return (ENOBUFS);	}	if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, LGE_JMEM,			    NULL, BUS_DMA_NOWAIT)) {		printf("%s: can't load dma map\n", sc->sc_dv.dv_xname);		bus_dmamap_destroy(sc->sc_dmatag, dmamap);		bus_dmamem_unmap(sc->sc_dmatag, kva, LGE_JMEM);		bus_dmamem_free(sc->sc_dmatag, &seg, rseg);		return (ENOBUFS);        }	sc->lge_cdata.lge_jumbo_buf = (caddr_t)kva;	DPRINTFN(1,("lge_jumbo_buf = 0x%08X\n", sc->lge_cdata.lge_jumbo_buf));	DPRINTFN(1,("LGE_JLEN = 0x%08X\n", LGE_JLEN));	LIST_INIT(&sc->lge_jfree_listhead);	LIST_INIT(&sc->lge_jinuse_listhead);	/*	 * Now divide it up into 9K pieces and save the addresses	 * in an array.	 */	ptr = sc->lge_cdata.lge_jumbo_buf;	for (i = 0; i < LGE_JSLOTS; i++) {		sc->lge_cdata.lge_jslots[i] = ptr;		ptr += LGE_JLEN;		entry = malloc(sizeof(struct lge_jpool_entry), 		    M_DEVBUF, M_NOWAIT);		if (entry == NULL) {			bus_dmamap_unload(sc->sc_dmatag, dmamap);			bus_dmamap_destroy(sc->sc_dmatag, dmamap);			bus_dmamem_unmap(sc->sc_dmatag, kva, LGE_JMEM);			bus_dmamem_free(sc->sc_dmatag, &seg, rseg);			sc->lge_cdata.lge_jumbo_buf = NULL;			printf("%s: no memory for jumbo buffer queue!\n",			       sc->sc_dv.dv_xname);			return(ENOBUFS);		}		entry->slot = i;		LIST_INSERT_HEAD(&sc->lge_jfree_listhead,				 entry, jpool_entries);	}	return(0);}/* * Allocate a jumbo buffer. */void *lge_jalloc(sc)	struct lge_softc	*sc;{	struct lge_jpool_entry   *entry;		entry = LIST_FIRST(&sc->lge_jfree_listhead);		if (entry == NULL) {#ifdef LGE_VERBOSE		printf("%s: no free jumbo buffers\n", sc->sc_dv.dv_xname);#endif		return(NULL);	}	LIST_REMOVE(entry, jpool_entries);	LIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);	return(sc->lge_cdata.lge_jslots[entry->slot]);}