static void __init tomatillo_register_error_handlers(struct pci_controller_info *p)
static void tomatillo_register_error_handlers(struct pci_controller_info *p)
static void __init tomatillo_register_error_handlers(struct pci_controller_info *p){	struct pci_pbm_info *pbm;	unsigned int irq;	struct ino_bucket *bucket;	u64 tmp, err_mask, err_no_mask;	/* Build IRQs and register handlers. */	pbm = pbm_for_ino(p, SCHIZO_UE_INO);	irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO);	if (request_irq(irq, schizo_ue_intr,			SA_SHIRQ, "TOMATILLO UE", p) < 0) {		prom_printf("%s: Cannot register UE interrupt.\n",			    pbm->name);		prom_halt();	}	bucket = __bucket(irq);	tmp = upa_readl(bucket->imap);	upa_writel(tmp, (pbm->pbm_regs +			 schizo_imap_offset(SCHIZO_UE_INO) + 4));	pbm = pbm_for_ino(p, SCHIZO_CE_INO);	irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO);	if (request_irq(irq, schizo_ce_intr,			SA_SHIRQ, "TOMATILLO CE", p) < 0) {		prom_printf("%s: Cannot register CE interrupt.\n",			    pbm->name);		prom_halt();	}	bucket = __bucket(irq);	tmp = upa_readl(bucket->imap);	upa_writel(tmp, (pbm->pbm_regs +			 schizo_imap_offset(SCHIZO_CE_INO) + 4));	pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);	irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) |					   SCHIZO_PCIERR_A_INO));	if (request_irq(irq, schizo_pcierr_intr,			SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) {		prom_printf("%s: Cannot register PBM A PciERR interrupt.\n",			    pbm->name);		prom_halt();	}	bucket = __bucket(irq);	tmp = upa_readl(bucket->imap);	upa_writel(tmp, (pbm->pbm_regs +			 schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));	pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);	irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) |					    SCHIZO_PCIERR_B_INO));	if (request_irq(irq, schizo_pcierr_intr,			SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) {		prom_printf("%s: Cannot register PBM B PciERR interrupt.\n",			    pbm->name);		prom_halt();	}	bucket = __bucket(irq);	tmp = upa_readl(bucket->imap);	upa_writel(tmp, (pbm->pbm_regs +			 schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));	pbm = pbm_for_ino(p, SCHIZO_SERR_INO);	irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO);	if (request_irq(irq, schizo_safarierr_intr,			SA_SHIRQ, "TOMATILLO SERR", p) < 0) {		prom_printf("%s: Cannot register SafariERR interrupt.\n",			    pbm->name);		prom_halt();	}	bucket = __bucket(irq);	tmp = upa_readl(bucket->imap);	upa_writel(tmp, (pbm->pbm_regs +			 schizo_imap_offset(SCHIZO_SERR_INO) + 4));	/* Enable UE and CE interrupts for controller. */	schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL,		     (SCHIZO_ECCCTRL_EE |		      SCHIZO_ECCCTRL_UE |		      SCHIZO_ECCCTRL_CE));	schizo_write(p->pbm_B.controller_regs + SCHIZO_ECC_CTRL,		     (SCHIZO_ECCCTRL_EE |		      SCHIZO_ECCCTRL_UE |		      SCHIZO_ECCCTRL_CE));	/* Enable PCI Error interrupts and clear error	 * bits.	 */	err_mask = (SCHIZO_PCICTRL_BUS_UNUS |		    SCHIZO_PCICTRL_TTO_ERR |		    SCHIZO_PCICTRL_RTRY_ERR |		    SCHIZO_PCICTRL_SERR |		    SCHIZO_PCICTRL_EEN);	err_no_mask = SCHIZO_PCICTRL_DTO_ERR;	tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL);	tmp |= err_mask;	tmp &= ~err_no_mask;	schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp);	tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL);	tmp |= err_mask;	tmp &= ~err_no_mask;	schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp);	err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |		    SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |		    SCHIZO_PCIAFSR_PTTO |		    SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |		    SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |		    SCHIZO_PCIAFSR_STTO);	schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR, err_mask);	schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, err_mask);	err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |		    BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |		    BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |		    BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |		    BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |		    BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |		    BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |		    BUS_ERROR_APERR | BUS_ERROR_UNMAP |		    BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);	schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL,		     (SCHIZO_SAFERRCTRL_EN | err_mask));	schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRCTRL,		     (SCHIZO_SAFERRCTRL_EN | err_mask));	schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL,		     (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));	schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_IRQCTRL,		     (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));}