case PCI_CHIP_I815_DC100: case PCI_CHIP_I815:
I810Probe(){   pciConfigPtr pcr;   pciConfigPtr I810pcr = NULL;   pciConfigPtr I810BridgePcr = NULL;   int temp;   int i;   /*    * Set up I/O ports to be used by this card.  Only do the second    * xf86AddIOPorts() if there are non-standard ports for this    * chipset.    */   xf86ClearIOPortList(vga256InfoRec.scrnIndex);   xf86AddIOPorts(vga256InfoRec.scrnIndex, Num_VGA_IOPorts, VGA_IOPorts);   /*    * First we attempt to figure out if one of the supported chipsets    * is present.    */   if (vga256InfoRec.chipset) {      char *chipset;      for (i = 0; (chipset = I810Ident(i)); i++) {	 if (!StrCaseCmp(vga256InfoRec.chipset, chipset)) {	    break;	 }      }      if (!chipset)	 return(FALSE);   }   /*    * Start with PCI probing, this should get us quite far already.    */   i = 0;   I810Chipset = -1;   if (vgaPCIInfo && vgaPCIInfo->AllCards) {      while (pcr = vgaPCIInfo->AllCards[i++]) {	 if (pcr->_vendor == PCI_VENDOR_INTEL) {	    int id = pcr->_device;	    if (vga256InfoRec.chipID) {	       ErrorF("%s %s: i810 chipset override, using ChipID "		      "value (0x%04X) instead of PCI value (0x%04X)\n",		      XCONFIG_GIVEN,		      vga256InfoRec.name,		      vga256InfoRec.chipID,		      pcr->_device);	       id = vga256InfoRec.chipID;	    }	    switch (id) {	    case PCI_CHIP_I810:	       vga256InfoRec.chipset = I810Ident(0);	       I810Chipset = id;	       I810LinearAddr = pcr->_base0 & 0xfe000000; /* 32/64M */	       I810MMIOAddr = pcr->_base1 & 0xfff80000; /* 512K window */	       I810pcr = pcr; 	       break;	    case PCI_CHIP_I810_DC100:	       vga256InfoRec.chipset = I810Ident(1);	       I810Chipset = id;	       I810LinearAddr = pcr->_base0 & 0xfe000000; /* 32/64M */	       I810MMIOAddr = pcr->_base1 & 0xfff80000; /* 512K window */	       I810pcr = pcr; 	       break;	    case PCI_CHIP_I810_E:	       vga256InfoRec.chipset = I810Ident(2);	       I810Chipset = id;	       I810LinearAddr = pcr->_base0 & 0xfe000000; /* 32/64M */	       I810MMIOAddr = pcr->_base1 & 0xfff80000; /* 512K window */	       I810pcr = pcr; 	       break;	    case PCI_CHIP_I810_BRIDGE:	    case PCI_CHIP_I810_DC100_BRIDGE:	    case PCI_CHIP_I810_E_BRIDGE:	       I810BridgePcr = pcr;	       break;	    }	 }      }   } else       return(FALSE);      if (I810Chipset == -1) {      if (vga256InfoRec.chipset)	 ErrorF("%s %s: i810: Unknown chipset\n",		XCONFIG_PROBED, vga256InfoRec.name);      return(FALSE);   }   /*    * Okay, it's an i810.    */   I810PciTag = pcibusTag(I810pcr->_bus, I810pcr->_cardnum, I810pcr->_func);   /* Override the linear address, if user specified one. */   if (vga256InfoRec.MemBase) {      if (vga256InfoRec.MemBase != I810LinearAddr) {	 ErrorF("%s %s: i810 linear address override, using 0x%08X "		"instead of probed value (0x%08X)\n",		XCONFIG_GIVEN,		vga256InfoRec.name,		vga256InfoRec.MemBase,		I810LinearAddr);      }      I810LinearAddr = vga256InfoRec.MemBase;   }   /* Override the MMIO address, if user specified one. */   if (vga256InfoRec.IObase) {      if (vga256InfoRec.IObase != I810MMIOAddr) {	 ErrorF("%s %s: i810 linear address override, using 0x%08X "		"instead of probed value (0x%08X)\n",		XCONFIG_GIVEN,		vga256InfoRec.name,		vga256InfoRec.IObase,		I810MMIOAddr);      }      I810MMIOAddr = vga256InfoRec.IObase;   }   /* Enable I/O Ports, etc. */   I810EnterLeave(ENTER);   /* Look for kernel GTT support, else try to fall back.  Currently    * ignores any dedicated video ram on the 810-dc100, as this is    * much slower than using system ram.  The main use of the dcache    * is as a zbuffer in a (forthcoming) 3d capable server.    */   if (!I810CharacterizeSystemRam( I810BridgePcr )) {      I810EnterLeave(LEAVE);      return FALSE;   }   if (!vga256InfoRec.videoRam) {      FatalError("\nCouldn't allocate physical memory for frame buffer.\n");   }   /*    * Last we fill in the remaining data structures.  We specify the    * chipset name, using the Ident() function and an appropriate    * index.  We set a boolean for whether or not this driver    * supports banking for the Monochrome server.  And we set up a    * list of all the option flags that this driver can make use of.    */   vga256InfoRec.bankedMono = FALSE;#ifdef XFreeXDGA   vga256InfoRec.directMode = XF86DGADirectPresent;#endif   /* Allowed options: */   OFLG_SET(OPTION_LINEAR, &I810.ChipOptionFlags);   OFLG_SET(OPTION_NOACCEL, &I810.ChipOptionFlags);   OFLG_SET(OPTION_SW_CURSOR, &I810.ChipOptionFlags);   OFLG_SET(OPTION_HW_CURSOR, &I810.ChipOptionFlags);   OFLG_SET(OPTION_MMIO, &I810.ChipOptionFlags);   OFLG_SET(OPTION_DAC_6_BIT, &I810.ChipOptionFlags);   OFLG_SET(OPTION_DAC_8_BIT, &I810.ChipOptionFlags);   OFLG_SET(OPTION_SLOW_DRAM, &I810.ChipOptionFlags);   /* Make sure users don't set mutually exclusive options!! */   if (OFLG_ISSET(OPTION_SW_CURSOR, &vga256InfoRec.options) &&       OFLG_ISSET(OPTION_HW_CURSOR, &vga256InfoRec.options))      FatalError(	 "\nOptions \"sw_cursor\" and \"hw_cursor\" are incompatible.\n");   if (OFLG_ISSET(OPTION_DAC_6_BIT, &vga256InfoRec.options) &&       OFLG_ISSET(OPTION_DAC_8_BIT, &vga256InfoRec.options))      FatalError(	 "\nOptions \"dac_6_bit\" and \"dac_8_bit\" are incompatible.\n");   /* Turn on 8 bit DAC mode, if 6 bit mode is not set or if the screen    * depth is greater than 8bpp.    */   if (!OFLG_ISSET(OPTION_DAC_6_BIT, &vga256InfoRec.options) ||       vgaBitsPerPixel > 8)      OFLG_SET(OPTION_DAC_8_BIT, &vga256InfoRec.options);   /* Turn off DAC_6_BIT if screen depth is greater than 8bpp     */   if (OFLG_ISSET(OPTION_DAC_6_BIT, &vga256InfoRec.options) &&       vgaBitsPerPixel > 8) {      OFLG_CLR(OPTION_DAC_6_BIT, &vga256InfoRec.options);      if (xf86Verbose) {	 ErrorF("%s %s: %s: Cannot use \"dac_6_bit\" in %d bpp mode\n",		XCONFIG_GIVEN,		vga256InfoRec.name,		vga256InfoRec.chipset,		vgaBitsPerPixel);      }   }   /*     * If your driver uses a programmable clockchip, you have to set    * this option to avoid clock probing etc.    */   OFLG_SET(CLOCK_OPTION_PROGRAMABLE, &vga256InfoRec.clockOptions);#ifdef DPMSExtension   vga256InfoRec.DPMSSet = I810DisplayPowerManagementSet;#endif   /*    * For the i740, the max RAMDAC dot clock is 220MHz, but the max    * pixel pipeline frequency is 203MHz so we'll use the 203MHz    * value.      *    * The i810 datasheet on intel's site has a max ramdac listed as    * 230 mHz.  I'm sticking with the 203 figure until I get some more    * information.    */   if (vga256InfoRec.dacSpeeds[0]) {      vga256InfoRec.maxClock = vga256InfoRec.dacSpeeds[0];   } else {      switch (I810Chipset) {      case PCI_CHIP_I810:      case PCI_CHIP_I810_DC100:      case PCI_CHIP_I810_E:	 switch (vgaBitsPerPixel) {	 case 8:  vga256InfoRec.maxClock = 203000; break;	 case 16: vga256InfoRec.maxClock = 163000; break;	 case 24: vga256InfoRec.maxClock = 128000; break;	 case 32: vga256InfoRec.maxClock =  86000; break;	 }	 break;      }   }   /* Undocumented bug in blit engine which is seen when screen pitch    * is not a multiple of 64 bytes.      */   vgaSetPitchAdjustHook(I810PitchAdjust);   return(TRUE);}