REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
bnx2_reset_chip(struct bnx2 *bp, u32 reset_code){	u32 val;	int i, rc = 0;	/* Wait for the current PCI transaction to complete before	 * issuing a reset. */	REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,	       BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |	       BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |	       BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |	       BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);	val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);	udelay(5);	/* Deposit a driver reset signature so the firmware knows that	 * this is a soft reset. */	REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,		   BNX2_DRV_RESET_SIGNATURE_MAGIC);	bp->fw_timed_out = 0;	/* Wait for the firmware to tell us it is ok to issue a reset. */	bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);	/* Do a dummy read to force the chip to complete all current transaction	 * before we issue a reset. */	val = REG_RD(bp, BNX2_MISC_ID);	val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |	      BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |	      BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;	/* Chip reset. */	REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);	if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||	    (CHIP_ID(bp) == CHIP_ID_5706_A1))		msleep(15);	/* Reset takes approximate 30 usec */	for (i = 0; i < 10; i++) {		val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);		if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |			    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {			break;		}		udelay(10);	}	if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |		   BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {		printk(KERN_ERR PFX "Chip reset did not complete\n");		return -EBUSY;	}	/* Make sure byte swapping is properly configured. */	val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);	if (val != 0x01020304) {		printk(KERN_ERR PFX "Chip not in correct endian mode\n");		return -ENODEV;	}	bp->fw_timed_out = 0;	/* Wait for the firmware to finish its initialization. */	bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {		/* Adjust the voltage regular to two steps lower.  The default		 * of this register is 0x0000000e. */		REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);		/* Remove bad rbuf memory from the free pool. */		rc = bnx2_alloc_bad_rbuf(bp);	}	return rc;}