"	.set	mips0					\n"
static __inline__ int atomic_add_return(int i, atomic_t * v){	unsigned long result;	if (cpu_has_llsc && R10000_LLSC_WAR) {		unsigned long temp;		__asm__ __volatile__(		"1:	ll	%1, %2		# atomic_add_return	\n"		"	addu	%0, %1, %3				\n"		"	sc	%0, %2					\n"		"	beqzl	%0, 1b					\n"		"	addu	%0, %1, %3				\n"		"	sync						\n"		: "=&r" (result), "=&r" (temp), "=m" (v->counter)		: "Ir" (i), "m" (v->counter)		: "memory");	} else if (cpu_has_llsc) {		unsigned long temp;		__asm__ __volatile__(		"1:	ll	%1, %2		# atomic_add_return	\n"		"	addu	%0, %1, %3				\n"		"	sc	%0, %2					\n"		"	beqz	%0, 1b					\n"		"	addu	%0, %1, %3				\n"		"	sync						\n"		: "=&r" (result), "=&r" (temp), "=m" (v->counter)		: "Ir" (i), "m" (v->counter)		: "memory");	} else {		unsigned long flags;		spin_lock_irqsave(&atomic_lock, flags);		result = v->counter;		result += i;		v->counter = result;		spin_unlock_irqrestore(&atomic_lock, flags);	}	return result;}