REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
bnx2_timer(unsigned long data){	struct bnx2 *bp = (struct bnx2 *) data;	u32 msg;	if (!netif_running(bp->dev))		return;	if (atomic_read(&bp->intr_sem) != 0)		goto bnx2_restart_timer;	msg = (u32) ++bp->fw_drv_pulse_wr_seq;	REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);	if ((bp->phy_flags & PHY_SERDES_FLAG) &&	    (CHIP_NUM(bp) == CHIP_NUM_5706)) {		spin_lock(&bp->phy_lock);		if (bp->serdes_an_pending) {			bp->serdes_an_pending--;		}		else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {			u32 bmcr;			bp->current_interval = bp->timer_interval;			bnx2_read_phy(bp, MII_BMCR, &bmcr);			if (bmcr & BMCR_ANENABLE) {				u32 phy1, phy2;				bnx2_write_phy(bp, 0x1c, 0x7c00);				bnx2_read_phy(bp, 0x1c, &phy1);				bnx2_write_phy(bp, 0x17, 0x0f01);				bnx2_read_phy(bp, 0x15, &phy2);				bnx2_write_phy(bp, 0x17, 0x0f01);				bnx2_read_phy(bp, 0x15, &phy2);				if ((phy1 & 0x10) &&	/* SIGNAL DETECT */					!(phy2 & 0x20)) {	/* no CONFIG */					bmcr &= ~BMCR_ANENABLE;					bmcr |= BMCR_SPEED1000 |						BMCR_FULLDPLX;					bnx2_write_phy(bp, MII_BMCR, bmcr);					bp->phy_flags |=						PHY_PARALLEL_DETECT_FLAG;				}			}		}		else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&			(bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {			u32 phy2;			bnx2_write_phy(bp, 0x17, 0x0f01);			bnx2_read_phy(bp, 0x15, &phy2);			if (phy2 & 0x20) {				u32 bmcr;				bnx2_read_phy(bp, MII_BMCR, &bmcr);				bmcr |= BMCR_ANENABLE;				bnx2_write_phy(bp, MII_BMCR, bmcr);				bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;			}		}		else			bp->current_interval = bp->timer_interval;		spin_unlock(&bp->phy_lock);	}bnx2_restart_timer:	mod_timer(&bp->timer, jiffies + bp->current_interval);}