else pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
static char * fp_const_from_val PROTO ((REAL_VALUE_TYPE *));static int eliminate_lr2ip PROTO ((rtx *));static char * shift_op PROTO ((rtx, HOST_WIDE_INT *));static int pattern_really_clobbers_lr PROTO ((rtx));static int function_really_clobbers_lr PROTO ((rtx));static void emit_multi_reg_push PROTO ((int));static void emit_sfm PROTO ((int, int));static enum arm_cond_code get_arm_condition_code PROTO ((rtx));static int const_ok_for_op RTX_CODE_PROTO ((Hint, Rcode));/*  Define the information needed to generate branch insns.  This is   stored from the compare operation. */rtx arm_compare_op0, arm_compare_op1;/* What type of floating point are we tuning for? */enum floating_point_type arm_fpu;/* What type of floating point instructions are available? */enum floating_point_type arm_fpu_arch;/* What program mode is the cpu running in? 26-bit mode or 32-bit mode */enum prog_mode_type arm_prgmode;/* Set by the -mfp=... option */const char * target_fp_name = NULL;/* Used to parse -mstructure_size_boundary command line option.  */const char * structure_size_string = NULL;int    arm_structure_size_boundary = 32; /* Used to be 8 *//* Bit values used to identify processor capabilities.  */#define FL_CO_PROC    0x01            /* Has external co-processor bus */#define FL_FAST_MULT  0x02            /* Fast multiply */#define FL_MODE26     0x04            /* 26-bit mode support */#define FL_MODE32     0x08            /* 32-bit mode support */#define FL_ARCH4      0x10            /* Architecture rel 4 */#define FL_THUMB      0x20            /* Thumb aware */#define FL_LDSCHED    0x40	      /* Load scheduling necessary */#define FL_STRONG     0x80	      /* StrongARM *//* The bits in this mask specify which instructions we are allowed to generate.  */static int insn_flags = 0;/* The bits in this mask specify which instruction scheduling options should   be used.  Note - there is an overlap with the FL_FAST_MULT.  For some   hardware we want to be able to generate the multiply instructions, but to   tune as if they were not present in the architecture.  */static int tune_flags = 0;/* The following are used in the arm.md file as equivalents to bits   in the above two flag variables.  *//* Nonzero if this is an "M" variant of the processor.  */int arm_fast_multiply = 0;/* Nonzero if this chip supports the ARM Architecture 4 extensions */int arm_arch4 = 0;/* Nonzero if this chip can benefit from load scheduling.  */int arm_ld_sched = 0;/* Nonzero if this chip is a StrongARM.  */int arm_is_strong = 0;/* Nonzero if this chip is a an ARM6 or an ARM7.  */int arm_is_6_or_7 = 0;/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we   must report the mode of the memory reference from PRINT_OPERAND to   PRINT_OPERAND_ADDRESS.  */enum machine_mode output_memory_reference_mode;/* Nonzero if the prologue must setup `fp'.  */int current_function_anonymous_args;/* The register number to be used for the PIC offset register.  */int arm_pic_register = 9;/* Location counter of .text segment.  */int arm_text_location = 0;/* Set to one if we think that lr is only saved because of subroutine calls,   but all of these can be `put after' return insns */int lr_save_eliminated;/* Set to 1 when a return insn is output, this means that the epilogue   is not needed. */static int return_used_this_function;/* Set to 1 after arm_reorg has started.  Reset to start at the start of   the next function.  */static int after_arm_reorg = 0;/* The maximum number of insns to be used when loading a constant.  */static int arm_constant_limit = 3;/* For an explanation of these variables, see final_prescan_insn below.  */int arm_ccfsm_state;enum arm_cond_code arm_current_cc;rtx arm_target_insn;int arm_target_label;/* The condition codes of the ARM, and the inverse function.  */char * arm_condition_codes[] ={  "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",  "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"};static enum arm_cond_code get_arm_condition_code ();#define streq(string1, string2) (strcmp (string1, string2) == 0)/* Initialization code */struct processors{  char *       name;  unsigned int flags;};/* Not all of these give usefully different compilation alternatives,   but there is no simple way of generalizing them.  */static struct processors all_cores[] ={  /* ARM Cores */    {"arm2",	FL_CO_PROC | FL_MODE26 },  {"arm250",	FL_CO_PROC | FL_MODE26 },  {"arm3",	FL_CO_PROC | FL_MODE26 },  {"arm6",	FL_CO_PROC | FL_MODE26 | FL_MODE32 },  {"arm60",	FL_CO_PROC | FL_MODE26 | FL_MODE32 },  {"arm600",	FL_CO_PROC | FL_MODE26 | FL_MODE32 },  {"arm610",	             FL_MODE26 | FL_MODE32 },  {"arm620",	FL_CO_PROC | FL_MODE26 | FL_MODE32 },  {"arm7",	FL_CO_PROC | FL_MODE26 | FL_MODE32 },   {"arm7m",	FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, /* arm7m doesn't exist on its own, */  {"arm7d",	FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 		     /* but only with D, (and I),       */  {"arm7dm",	FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, /* but those don't alter the code, */  {"arm7di",	FL_CO_PROC | FL_MODE26 | FL_MODE32 },		     /* so arm7m is sometimes used.     */  {"arm7dmi",	FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },  {"arm70",	FL_CO_PROC | FL_MODE26 | FL_MODE32 },  {"arm700",	FL_CO_PROC | FL_MODE26 | FL_MODE32 },  {"arm700i",	FL_CO_PROC | FL_MODE26 | FL_MODE32 },  {"arm710",	             FL_MODE26 | FL_MODE32 },  {"arm710c",	             FL_MODE26 | FL_MODE32 },  {"arm7100",	             FL_MODE26 | FL_MODE32 },  {"arm7500",	             FL_MODE26 | FL_MODE32 },  {"arm7500fe",	FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* Doesn't really have an external co-proc, but does have embedded fpu.  */  {"arm7tdmi",	FL_CO_PROC |             FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },  {"arm8",	             FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 |            FL_LDSCHED },  {"arm810",	             FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 |            FL_LDSCHED },  {"arm9",	                         FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },  {"arm9tdmi",	                         FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },  {"strongarm",	             FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 |            FL_LDSCHED | FL_STRONG },  {"strongarm110",           FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 |            FL_LDSCHED | FL_STRONG },  {"strongarm1100",          FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 |            FL_LDSCHED | FL_STRONG },    {NULL, 0}};static struct processors all_architectures[] ={  /* ARM Architectures */    {"armv2",     FL_CO_PROC | FL_MODE26 },  {"armv2a",    FL_CO_PROC | FL_MODE26 },  {"armv3",     FL_CO_PROC | FL_MODE26 | FL_MODE32 },  {"armv3m",    FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },  {"armv4",     FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4  },  /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no     implementations that support it, so we will leave it out for now.  */  {"armv4t",    FL_CO_PROC |             FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },  {NULL, 0}};/* This is a magic stucture.  The 'string' field is magically filled in   with a pointer to the value specified by the user on the command line   assuming that the user has specified such a value.  */struct arm_cpu_select arm_select[] ={  /* string	  name            processors  */	  { NULL,	"-mcpu=",	all_cores  },  { NULL,	"-march=",	all_architectures },  { NULL,	"-mtune=",	all_cores }};/* Return the number of bits set in value' */static unsigned intbit_count (value)     signed int value;{  unsigned int count = 0;    while (value)    {      value &= ~(value & - value);      ++ count;    }  return count;}/* Fix up any incompatible options that the user has specified.   This has now turned into a maze.  */voidarm_override_options (){  unsigned i;    /* Set up the flags based on the cpu/architecture selected by the user.  */  for (i = sizeof (arm_select) / sizeof (arm_select[0]); i--;)    {      struct arm_cpu_select * ptr = arm_select + i;            if (ptr->string != NULL && ptr->string[0] != '\0')        {	  struct processors * sel;          for (sel = ptr->processors; sel->name != NULL; sel ++)            if (streq (ptr->string, sel->name))              {		if (i == 2)		  tune_flags = sel->flags;		else		  {		    /* If we have been given an architecture and a processor		       make sure that they are compatible.  We only generate		       a warning though, and we prefer the CPU over the		       architecture. */		    if (insn_flags != 0 && (insn_flags ^ sel->flags))		      warning ("switch -mcpu=%s conflicts with -mtune= switch",			       ptr->string);		    		    insn_flags = sel->flags;		  }		                break;              }          if (sel->name == NULL)            error ("bad value (%s) for %s switch", ptr->string, ptr->name);        }    }    /* If the user did not specify a processor, choose one for them.  */  if (insn_flags == 0)    {      struct processors * sel;      unsigned int        sought;      static struct cpu_default      {	int    cpu;	char * name;      }      cpu_defaults[] =      {	{ TARGET_CPU_arm2,      "arm2" },	{ TARGET_CPU_arm6,      "arm6" },	{ TARGET_CPU_arm610,    "arm610" },	{ TARGET_CPU_arm710,	"arm710" },	{ TARGET_CPU_arm7m,     "arm7m" },	{ TARGET_CPU_arm7500fe, "arm7500fe" },	{ TARGET_CPU_arm7tdmi,  "arm7tdmi" },	{ TARGET_CPU_arm8,      "arm8" },	{ TARGET_CPU_arm810,    "arm810" },	{ TARGET_CPU_arm9,      "arm9" },	{ TARGET_CPU_strongarm, "strongarm" },	{ TARGET_CPU_generic,   "arm" },	{ 0, 0 }      };      struct cpu_default * def;	        /* Find the default.  */      for (def = cpu_defaults; def->name; def ++)	if (def->cpu == TARGET_CPU_DEFAULT)	  break;      /* Make sure we found the default CPU.  */      if (def->name == NULL)	abort ();            /* Find the default CPU's flags.  */      for (sel = all_cores; sel->name != NULL; sel ++)	if (streq (def->name, sel->name))	  break;            if (sel->name == NULL)	abort ();      insn_flags = sel->flags;            /* Now check to see if the user has specified some command line	 switch that require certain abilities from the cpu.  */      sought = 0;            if (TARGET_THUMB_INTERWORK)	{	  sought |= (FL_THUMB | FL_MODE32);	  	  /* Force apcs-32 to be used for interworking.  */	  target_flags |= ARM_FLAG_APCS_32;	  /* There are no ARM processor that supports both APCS-26 and	     interworking.  Therefore we force FL_MODE26 to be removed	     from insn_flags here (if it was set), so that the search	     below will always be able to find a compatible processor.  */	  insn_flags &= ~ FL_MODE26;	}            if (! TARGET_APCS_32)	sought |= FL_MODE26;      if (sought != 0 && ((sought & insn_flags) != sought))	{	  /* Try to locate a CPU type that supports all of the abilities	     of the default CPU, plus the extra abilities requested by	     the user.  */	  for (sel = all_cores; sel->name != NULL; sel ++)	    if ((sel->flags & sought) == (sought | insn_flags))	      break;	  if (sel->name == NULL)	    {	      unsigned int        current_bit_count = 0;	      struct processors * best_fit = NULL;	      	      /* Ideally we would like to issue an error message here		 saying that it was not possible to find a CPU compatible		 with the default CPU, but which also supports the command		 line options specified by the programmer, and so they		 ought to use the -mcpu=<name> command line option to		 override the default CPU type.		 Unfortunately this does not work with multilibing.  We		 need to be able to support multilibs for -mapcs-26 and for		 -mthumb-interwork and there is no CPU that can support both		 options.  Instead if we cannot find a cpu that has both the		 characteristics of the default cpu and the given command line		 options we scan the array again looking for a best match.  */	      for (sel = all_cores; sel->name != NULL; sel ++)		if ((sel->flags & sought) == sought)		  {		    unsigned int count;		    count = bit_count (sel->flags & insn_flags);		    if (count >= current_bit_count)		      {			best_fit = sel;			current_bit_count = count;		      }		  }	      if (best_fit == NULL)		abort ();	      else		sel = best_fit;	    }	  insn_flags = sel->flags;	}    }    /* If tuning has not been specified, tune for whichever processor or     architecture has been selected.  */  if (tune_flags == 0)    tune_flags = insn_flags;    /* Make sure that the processor choice does not conflict with any of the     other command line choices.  */  if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))    {      /* If APCS-32 was not the default then it must have been set by the	 user, so issue a warning message.  If the user has specified	 "-mapcs-32 -mcpu=arm2" then we loose here.  */      if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)	warning ("target CPU does not support APCS-32" );      target_flags &= ~ ARM_FLAG_APCS_32;    }  else if (! TARGET_APCS_32 && !(insn_flags & FL_MODE26))    {      warning ("target CPU does not support APCS-26" );      target_flags |= ARM_FLAG_APCS_32;    }    if (TARGET_THUMB_INTERWORK && !(insn_flags & FL_THUMB))    {      warning ("target CPU does not support interworking" );      target_flags &= ~ARM_FLAG_THUMB;    }    /* If interworking is enabled then APCS-32 must be selected as well.  */  if (TARGET_THUMB_INTERWORK)    {      if (! TARGET_APCS_32)	warning ("interworking forces APCS-32 to be used" );      target_flags |= ARM_FLAG_APCS_32;    }    if (TARGET_APCS_STACK && ! TARGET_APCS)    {      warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");      target_flags |= ARM_FLAG_APCS_FRAME;    }    if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)    warning ("-g with -fomit-frame-pointer may not give sensible debugging");    if (TARGET_POKE_FUNCTION_NAME)    target_flags |= ARM_FLAG_APCS_FRAME;    if (TARGET_APCS_REENT && flag_pic)    fatal ("-fpic and -mapcs-reent are incompatible");    if (TARGET_APCS_REENT)    warning ("APCS reentrant code not supported.  Ignored");    /* If stack checking is disabled, we can use r10 as the PIC register,     which keeps r9 available.  */  if (flag_pic && ! TARGET_APCS_STACK)    arm_pic_register = 10;    /* Well, I'm about to have a go, but pic is NOT going to be compatible     with APCS reentrancy, since that requires too much support in the     assembler and linker, and the ARMASM assembler seems to lack some     required directives.  */  if (flag_pic)    warning ("Position independent code not supported");    if (TARGET_APCS_FLOAT)    warning ("Passing floating point arguments in fp regs not yet supported");    /* Initialise boolean versions of the flags, for use in the arm.md file.  */  arm_fast_multiply = insn_flags & FL_FAST_MULT;  arm_arch4         = insn_flags & FL_ARCH4;    arm_ld_sched      = tune_flags & FL_LDSCHED;  arm_is_strong     = tune_flags & FL_STRONG;  arm_is_6_or_7     = ((tune_flags & (FL_MODE26 | FL_MODE32))		       && !(tune_flags & FL_ARCH4));    /* Default value for floating point code... if no co-processor     bus, then schedule for emulated floating point.  Otherwise,     assume the user has an FPA.     Note: this does not prevent use of floating point instructions,     -msoft-float does that.  */  arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;    if (target_fp_name)    {      if (streq (target_fp_name, "2"))	arm_fpu_arch = FP_SOFT2;      else if (streq (target_fp_name, "3"))	arm_fpu_arch = FP_SOFT3;      else	fatal ("Invalid floating point emulation option: -mfpe-%s",	       target_fp_name);    }  else    arm_fpu_arch = FP_DEFAULT;    if (TARGET_FPE && arm_fpu != FP_HARD)    arm_fpu = FP_SOFT2;    /* For arm2/3 there is no need to do any scheduling if there is only     a floating point emulator, or we are doing software floating-point.  */  if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD) && (tune_flags & FL_MODE32) == 0)    flag_schedule_insns = flag_schedule_insns_after_reload = 0;    arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;    if (structure_size_string != NULL)    {      int size = strtol (structure_size_string, NULL, 0);            if (size == 8 || size == 32)	arm_structure_size_boundary = size;      else	warning ("Structure size boundary can only be set to 8 or 32");    }    /* If optimizing for space, don't synthesize constants.     For processors with load scheduling, it never costs more than 2 cycles     to load a constant, and the load scheduler may well reduce that to 1.  */  if (optimize_size || (tune_flags & FL_LDSCHED))    arm_constant_limit = 1;    /* If optimizing for size, bump the number of instructions that we     are prepared to conditionally execute (even on a StrongARM).      Otherwise for the StrongARM, which has early execution of branches,     a sequence that is worth skipping is shorter.  */  if (optimize_size)    max_insns_skipped = 6;  else if (arm_is_strong)    max_insns_skipped = 3;}/* Return 1 if it is possible to return using a single instruction */intuse_return_insn (iscond)     int iscond;{  int regno;  if (!reload_completed      || current_function_pretend_args_size      || current_function_anonymous_args      || ((get_frame_size () + current_function_outgoing_args_size != 0)	  && !(TARGET_APCS && frame_pointer_needed)))    return 0;  /* Can't be done if interworking with Thumb, and any registers have been     stacked.  Similarly, on StrongARM, conditional returns are expensive     if they aren't taken and registers have been stacked.  */  if (iscond && arm_is_strong && frame_pointer_needed)    return 0;  if ((iscond && arm_is_strong)      || TARGET_THUMB_INTERWORK)    for (regno = 0; regno < 16; regno++)      if (regs_ever_live[regno] && ! call_used_regs[regno])	return 0;        /* Can't be done if any of the FPU regs are pushed, since this also     requires an insn */  for (regno = 16; regno < 24; regno++)    if (regs_ever_live[regno] && ! call_used_regs[regno])      return 0;  /* If a function is naked, don't use the "return" insn.  */  if (arm_naked_function_p (current_function_decl))    return 0;  return 1;}/* Return TRUE if int I is a valid immediate ARM constant.  */intconst_ok_for_arm (i)     HOST_WIDE_INT i;{  unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;  /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must      be all zero, or all one.  */  if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0      && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) 	  != ((~(unsigned HOST_WIDE_INT) 0)	      & ~(unsigned HOST_WIDE_INT) 0xffffffff)))    return FALSE;    /* Fast return for 0 and powers of 2 */  if ((i & (i - 1)) == 0)    return TRUE;  do    {      if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)        return TRUE;      mask =	  (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)			 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff);    } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);  return FALSE;}/* Return true if I is a valid constant for the operation CODE. */static intconst_ok_for_op (i, code)     HOST_WIDE_INT i;     enum rtx_code code;{  if (const_ok_for_arm (i))    return 1;  switch (code)    {    case PLUS:      return const_ok_for_arm (ARM_SIGN_EXTEND (-i));    case MINUS:		/* Should only occur with (MINUS I reg) => rsb */    case XOR:    case IOR:      return 0;    case AND:      return const_ok_for_arm (ARM_SIGN_EXTEND (~i));    default:      abort ();    }}/* Emit a sequence of insns to handle a large constant.   CODE is the code of the operation required, it can be any of SET, PLUS,   IOR, AND, XOR, MINUS;   MODE is the mode in which the operation is being performed;   VAL is the integer to operate on;   SOURCE is the other operand (a register, or a null-pointer for SET);   SUBTARGETS means it is safe to create scratch registers if that will   either produce a simpler sequence, or we will want to cse the values.   Return value is the number of insns emitted.  */intarm_split_constant (code, mode, val, target, source, subtargets)     enum rtx_code code;     enum machine_mode mode;     HOST_WIDE_INT val;     rtx target;     rtx source;     int subtargets;{  if (subtargets || code == SET      || (GET_CODE (target) == REG && GET_CODE (source) == REG	  && REGNO (target) != REGNO (source)))    {      /* After arm_reorg has been called, we can't fix up expensive	 constants by pushing them into memory so we must synthesise	 them in-line, regardless of the cost.  This is only likely to	 be more costly on chips that have load delay slots and we are	 compiling without running the scheduler (so no splitting	 occurred before the final instruction emission).	 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c      */      if (! after_arm_reorg	  && (arm_gen_constant (code, mode, val, target, source, 1, 0)	      > arm_constant_limit + (code != SET)))	{	  if (code == SET)	    {	      /* Currently SET is the only monadic value for CODE, all		 the rest are diadic.  */	      emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));	      return 1;	    }	  else	    {	      rtx temp = subtargets ? gen_reg_rtx (mode) : target;	      emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));	      /* For MINUS, the value is subtracted from, since we never		 have subtraction of a constant.  */	      if (code == MINUS)		emit_insn (gen_rtx_SET (VOIDmode, target,					gen_rtx (code, mode, temp, source)));	      else		emit_insn (gen_rtx_SET (VOIDmode, target,					gen_rtx (code, mode, source, temp)));	      return 2;	    }	}    }  return arm_gen_constant (code, mode, val, target, source, subtargets, 1);}/* As above, but extra parameter GENERATE which, if clear, suppresses   RTL generation.  */intarm_gen_constant (code, mode, val, target, source, subtargets, generate)     enum rtx_code code;     enum machine_mode mode;     HOST_WIDE_INT val;     rtx target;     rtx source;     int subtargets;     int generate;{  int can_invert = 0;  int can_negate = 0;  int can_negate_initial = 0;  int can_shift = 0;  int i;  int num_bits_set = 0;  int set_sign_bit_copies = 0;  int clear_sign_bit_copies = 0;  int clear_zero_bit_copies = 0;  int set_zero_bit_copies = 0;  int insns = 0;  unsigned HOST_WIDE_INT temp1, temp2;  unsigned HOST_WIDE_INT remainder = val & 0xffffffff;  /* find out which operations are safe for a given CODE.  Also do a quick     check for degenerate cases; these can occur when DImode operations     are split.  */  switch (code)    {    case SET:      can_invert = 1;      can_shift = 1;      can_negate = 1;      break;    case PLUS:      can_negate = 1;      can_negate_initial = 1;      break;    case IOR:      if (remainder == 0xffffffff)	{	  if (generate)	    emit_insn (gen_rtx_SET (VOIDmode, target,				    GEN_INT (ARM_SIGN_EXTEND (val))));	  return 1;	}      if (remainder == 0)	{	  if (reload_completed && rtx_equal_p (target, source))	    return 0;	  if (generate)	    emit_insn (gen_rtx_SET (VOIDmode, target, source));	  return 1;	}      break;    case AND:      if (remainder == 0)	{	  if (generate)	    emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));	  return 1;	}      if (remainder == 0xffffffff)	{	  if (reload_completed && rtx_equal_p (target, source))	    return 0;	  if (generate)	    emit_insn (gen_rtx_SET (VOIDmode, target, source));	  return 1;	}      can_invert = 1;      break;    case XOR:      if (remainder == 0)	{	  if (reload_completed && rtx_equal_p (target, source))	    return 0;	  if (generate)	    emit_insn (gen_rtx_SET (VOIDmode, target, source));	  return 1;	}      if (remainder == 0xffffffff)	{	  if (generate)	    emit_insn (gen_rtx_SET (VOIDmode, target,				    gen_rtx_NOT (mode, source)));	  return 1;	}      /* We don't know how to handle this yet below.  */      abort ();    case MINUS:      /* We treat MINUS as (val - source), since (source - val) is always	 passed as (source + (-val)).  */      if (remainder == 0)	{	  if (generate)	    emit_insn (gen_rtx_SET (VOIDmode, target,				    gen_rtx_NEG (mode, source)));	  return 1;	}      if (const_ok_for_arm (val))	{	  if (generate)	    emit_insn (gen_rtx_SET (VOIDmode, target, 				    gen_rtx_MINUS (mode, GEN_INT (val),						   source)));	  return 1;	}      can_negate = 1;      break;    default:      abort ();    }  /* If we can do it in one insn get out quickly */  if (const_ok_for_arm (val)      || (can_negate_initial && const_ok_for_arm (-val))      || (can_invert && const_ok_for_arm (~val)))    {      if (generate)	emit_insn (gen_rtx_SET (VOIDmode, target,				(source ? gen_rtx (code, mode, source,						   GEN_INT (val))				 : GEN_INT (val))));      return 1;    }  /* Calculate a few attributes that may be useful for specific     optimizations. */  for (i = 31; i >= 0; i--)    {      if ((remainder & (1 << i)) == 0)	clear_sign_bit_copies++;      else	break;    }  for (i = 31; i >= 0; i--)    {      if ((remainder & (1 << i)) != 0)	set_sign_bit_copies++;      else	break;    }  for (i = 0; i <= 31; i++)    {      if ((remainder & (1 << i)) == 0)	clear_zero_bit_copies++;      else	break;    }  for (i = 0; i <= 31; i++)    {      if ((remainder & (1 << i)) != 0)	set_zero_bit_copies++;      else	break;    }  switch (code)    {    case SET:      /* See if we can do this by sign_extending a constant that is known	 to be negative.  This is a good, way of doing it, since the shift	 may well merge into a subsequent insn.  */      if (set_sign_bit_copies > 1)	{	  if (const_ok_for_arm	      (temp1 = ARM_SIGN_EXTEND (remainder 					<< (set_sign_bit_copies - 1))))	    {	      if (generate)		{		  rtx new_src = subtargets ? gen_reg_rtx (mode) : target;		  emit_insn (gen_rtx_SET (VOIDmode, new_src, 					  GEN_INT (temp1)));		  emit_insn (gen_ashrsi3 (target, new_src, 					  GEN_INT (set_sign_bit_copies - 1)));		}	      return 2;	    }	  /* For an inverted constant, we will need to set the low bits,	     these will be shifted out of harm's way.  */	  temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;	  if (const_ok_for_arm (~temp1))	    {	      if (generate)		{		  rtx new_src = subtargets ? gen_reg_rtx (mode) : target;		  emit_insn (gen_rtx_SET (VOIDmode, new_src,					  GEN_INT (temp1)));		  emit_insn (gen_ashrsi3 (target, new_src, 					  GEN_INT (set_sign_bit_copies - 1)));		}	      return 2;	    }	}      /* See if we can generate this by setting the bottom (or the top)	 16 bits, and then shifting these into the other half of the	 word.  We only look for the simplest cases, to do more would cost	 too much.  Be careful, however, not to generate this when the	 alternative would take fewer insns.  */      if (val & 0xffff0000)	{	  temp1 = remainder & 0xffff0000;	  temp2 = remainder & 0x0000ffff;	  /* Overlaps outside this range are best done using other methods. */	  for (i = 9; i < 24; i++)	    {	      if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)		  && ! const_ok_for_arm (temp2))		{		  rtx new_src = (subtargets				 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)				 : target);		  insns = arm_gen_constant (code, mode, temp2, new_src,					    source, subtargets, generate);		  source = new_src;		  if (generate)		    emit_insn (gen_rtx_SET			       (VOIDmode, target,				gen_rtx_IOR (mode,					     gen_rtx_ASHIFT (mode, source,							     GEN_INT (i)),					     source)));		  return insns + 1;		}	    }	  /* Don't duplicate cases already considered. */	  for (i = 17; i < 24; i++)	    {	      if (((temp1 | (temp1 >> i)) == remainder)		  && ! const_ok_for_arm (temp1))		{		  rtx new_src = (subtargets				 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)				 : target);		  insns = arm_gen_constant (code, mode, temp1, new_src,					    source, subtargets, generate);		  source = new_src;		  if (generate)		    emit_insn		      (gen_rtx_SET (VOIDmode, target,				    gen_rtx_IOR				    (mode,				     gen_rtx_LSHIFTRT (mode, source,						       GEN_INT (i)),				     source)));		  return insns + 1;		}	    }	}      break;    case IOR:    case XOR:      /* If we have IOR or XOR, and the constant can be loaded in a	 single instruction, and we can find a temporary to put it in,	 then this can be done in two instructions instead of 3-4.  */      if (subtargets	  /* TARGET can't be NULL if SUBTARGETS is 0 */	  || (reload_completed && ! reg_mentioned_p (target, source)))	{	  if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))	    {	      if (generate)		{		  rtx sub = subtargets ? gen_reg_rtx (mode) : target;		  emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));		  emit_insn (gen_rtx_SET (VOIDmode, target, 					  gen_rtx (code, mode, source, sub)));		}	      return 2;	    }	}      if (code == XOR)	break;      if (set_sign_bit_copies > 8	  && (val & (-1 << (32 - set_sign_bit_copies))) == val)	{	  if (generate)	    {	      rtx sub = subtargets ? gen_reg_rtx (mode) : target;	      rtx shift = GEN_INT (set_sign_bit_copies);	      emit_insn (gen_rtx_SET (VOIDmode, sub,				      gen_rtx_NOT (mode, 						   gen_rtx_ASHIFT (mode,								   source, 								   shift))));	      emit_insn (gen_rtx_SET (VOIDmode, target,				      gen_rtx_NOT (mode,						   gen_rtx_LSHIFTRT (mode, sub,								     shift))));	    }	  return 2;	}      if (set_zero_bit_copies > 8	  && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)	{	  if (generate)	    {	      rtx sub = subtargets ? gen_reg_rtx (mode) : target;	      rtx shift = GEN_INT (set_zero_bit_copies);	      emit_insn (gen_rtx_SET (VOIDmode, sub,				      gen_rtx_NOT (mode,						   gen_rtx_LSHIFTRT (mode,								     source,								     shift))));	      emit_insn (gen_rtx_SET (VOIDmode, target,				      gen_rtx_NOT (mode,						   gen_rtx_ASHIFT (mode, sub,								   shift))));	    }	  return 2;	}      if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))	{	  if (generate)	    {	      rtx sub = subtargets ? gen_reg_rtx (mode) : target;	      emit_insn (gen_rtx_SET (VOIDmode, sub,				      gen_rtx_NOT (mode, source)));	      source = sub;	      if (subtargets)		sub = gen_reg_rtx (mode);	      emit_insn (gen_rtx_SET (VOIDmode, sub,				      gen_rtx_AND (mode, source, 						   GEN_INT (temp1))));	      emit_insn (gen_rtx_SET (VOIDmode, target,				      gen_rtx_NOT (mode, sub)));	    }	  return 3;	}      break;    case AND:      /* See if two shifts will do 2 or more insn's worth of work.  */      if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)	{	  HOST_WIDE_INT shift_mask = ((0xffffffff 				       << (32 - clear_sign_bit_copies))				      & 0xffffffff);	  if ((remainder | shift_mask) != 0xffffffff)	    {	      if (generate)		{		  rtx new_src = subtargets ? gen_reg_rtx (mode) : target;		  insns = arm_gen_constant (AND, mode, remainder | shift_mask,					    new_src, source, subtargets, 1);		  source = new_src;		}	      else		{		  rtx targ = subtargets ? NULL_RTX : target;		  insns = arm_gen_constant (AND, mode, remainder | shift_mask,					    targ, source, subtargets, 0);		}	    }	  if (generate)	    {	      rtx new_src = subtargets ? gen_reg_rtx (mode) : target;	      rtx shift = GEN_INT (clear_sign_bit_copies);	      emit_insn (gen_ashlsi3 (new_src, source, shift));	      emit_insn (gen_lshrsi3 (target, new_src, shift));	    }	  return insns + 2;	}      if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)	{	  HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;	  	  if ((remainder | shift_mask) != 0xffffffff)	    {	      if (generate)		{		  rtx new_src = subtargets ? gen_reg_rtx (mode) : target;		  insns = arm_gen_constant (AND, mode, remainder | shift_mask,					    new_src, source, subtargets, 1);		  source = new_src;		}	      else		{		  rtx targ = subtargets ? NULL_RTX : target;		  insns = arm_gen_constant (AND, mode, remainder | shift_mask,					    targ, source, subtargets, 0);		}	    }	  if (generate)	    {	      rtx new_src = subtargets ? gen_reg_rtx (mode) : target;	      rtx shift = GEN_INT (clear_zero_bit_copies);	      emit_insn (gen_lshrsi3 (new_src, source, shift));	      emit_insn (gen_ashlsi3 (target, new_src, shift));	    }	  return insns + 2;	}      break;    default:      break;    }  for (i = 0; i < 32; i++)    if (remainder & (1 << i))      num_bits_set++;  if (code == AND || (can_invert && num_bits_set > 16))    remainder = (~remainder) & 0xffffffff;  else if (code == PLUS && num_bits_set > 16)    remainder = (-remainder) & 0xffffffff;  else    {      can_invert = 0;      can_negate = 0;    }  /* Now try and find a way of doing the job in either two or three     instructions.     We start by looking for the largest block of zeros that are aligned on     a 2-bit boundary, we then fill up the temps, wrapping around to the     top of the word when we drop off the bottom.     In the worst case this code should produce no more than four insns. */  {    int best_start = 0;    int best_consecutive_zeros = 0;    for (i = 0; i < 32; i += 2)      {	int consecutive_zeros = 0;	if (! (remainder & (3 << i)))	  {	    while ((i < 32) && ! (remainder & (3 << i)))	      {		consecutive_zeros += 2;		i += 2;	      }	    if (consecutive_zeros > best_consecutive_zeros)	      {		best_consecutive_zeros = consecutive_zeros;		best_start = i - consecutive_zeros;	      }	    i -= 2;	  }      }    /* Now start emitting the insns, starting with the one with the highest       bit set: we do this so that the smallest number will be emitted last;       this is more likely to be combinable with addressing insns. */    i = best_start;    do      {	int end;	if (i <= 0)	  i += 32;	if (remainder & (3 << (i - 2)))	  {	    end = i - 8;	    if (end < 0)	      end += 32;	    temp1 = remainder & ((0x0ff << end)				 | ((i < end) ? (0xff >> (32 - end)) : 0));	    remainder &= ~temp1;	    if (generate)	      {		rtx new_src;		if (code == SET)		  emit_insn (gen_rtx_SET (VOIDmode,					  new_src = (subtargets						     ? gen_reg_rtx (mode)						     : target),					  GEN_INT (can_invert						   ? ~temp1 : temp1)));		else if (code == MINUS)		  emit_insn (gen_rtx_SET (VOIDmode,					  new_src = (subtargets						     ? gen_reg_rtx (mode)						     : target),					  gen_rtx (code, mode, GEN_INT (temp1),						   source)));		else		  emit_insn (gen_rtx_SET (VOIDmode,					  new_src = (remainder						     ? (subtargets							? gen_reg_rtx (mode)							: target)						     : target),					  gen_rtx (code, mode, source,						   GEN_INT (can_invert ? ~temp1							    : (can_negate							       ? -temp1							       : temp1)))));		source = new_src;	      }	    if (code == SET)	      {		can_invert = 0;		code = PLUS;	      }	    else if (code == MINUS)	      code = PLUS;	    insns++;	    i -= 6;	  }	i -= 2;      } while (remainder);  }  return insns;}/* Canonicalize a comparison so that we are more likely to recognize it.   This can be done for a few constant compares, where we can make the   immediate value easier to load.  */enum rtx_codearm_canonicalize_comparison (code, op1)     enum rtx_code code;     rtx *op1;{  unsigned HOST_WIDE_INT i = INTVAL (*op1);  switch (code)    {    case EQ:    case NE:      return code;    case GT:    case LE:      if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))		- 1)	  && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))	{	  *op1 = GEN_INT (i+1);	  return code == GT ? GE : LT;	}      break;    case GE:    case LT:      if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))	  && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))	{	  *op1 = GEN_INT (i-1);	  return code == GE ? GT : LE;	}      break;    case GTU:    case LEU:      if (i != ~((unsigned HOST_WIDE_INT) 0)	  && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))	{	  *op1 = GEN_INT (i + 1);	  return code == GTU ? GEU : LTU;	}      break;    case GEU:    case LTU:      if (i != 0	  && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))	{	  *op1 = GEN_INT (i - 1);	  return code == GEU ? GTU : LEU;	}      break;    default:      abort ();    }  return code;}/* Decide whether a type should be returned in memory (true)   or in a register (false).  This is called by the macro   RETURN_IN_MEMORY.  */intarm_return_in_memory (type)     tree type;{  if (! AGGREGATE_TYPE_P (type))    {      /* All simple types are returned in registers. */      return 0;    }  else if (int_size_in_bytes (type) > 4)    {      /* All structures/unions bigger than one word are returned in memory. */      return 1;    }  else if (TREE_CODE (type) == RECORD_TYPE)    {      tree field;      /* For a struct the APCS says that we must return in a register if	 every addressable element has an offset of zero.  For practical	 purposes this means that the structure can have at most one non	 bit-field element and that this element must be the first one in	 the structure.  */      /* Find the first field, ignoring non FIELD_DECL things which will	 have been created by C++.  */      for (field = TYPE_FIELDS (type);	   field && TREE_CODE (field) != FIELD_DECL;	   field = TREE_CHAIN (field))	continue;            if (field == NULL)	return 0; /* An empty structure.  Allowed by an extension to ANSI C. */      /* Now check the remaining fields, if any. */      for (field = TREE_CHAIN (field);	   field;	   field = TREE_CHAIN (field))	{	  if (TREE_CODE (field) != FIELD_DECL)	    continue;	  	  if (! DECL_BIT_FIELD_TYPE (field))	    return 1;	}      return 0;    }  else if (TREE_CODE (type) == UNION_TYPE)    {      tree field;      /* Unions can be returned in registers if every element is	 integral, or can be returned in an integer register.  */      for (field = TYPE_FIELDS (type);	   field;	   field = TREE_CHAIN (field))	{	  if (TREE_CODE (field) != FIELD_DECL)	    continue;	  if (FLOAT_TYPE_P (TREE_TYPE (field)))	    return 1;	  	  if (RETURN_IN_MEMORY (TREE_TYPE (field)))	    return 1;	}            return 0;    }    /* XXX Not sure what should be done for other aggregates, so put them in     memory. */  return 1;}intlegitimate_pic_operand_p (x)     rtx x;{  if (CONSTANT_P (x) && flag_pic      && (GET_CODE (x) == SYMBOL_REF	  || (GET_CODE (x) == CONST	      && GET_CODE (XEXP (x, 0)) == PLUS	      && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))    return 0;  return 1;}rtxlegitimize_pic_address (orig, mode, reg)     rtx orig;     enum machine_mode mode;     rtx reg;{  if (GET_CODE (orig) == SYMBOL_REF)    {      rtx pic_ref, address;      rtx insn;      int subregs = 0;      if (reg == 0)	{	  if (reload_in_progress || reload_completed)	    abort ();	  else	    reg = gen_reg_rtx (Pmode);	  subregs = 1;	}#ifdef AOF_ASSEMBLER      /* The AOF assembler can generate relocations for these directly, and	 understands that the PIC register has to be added into the offset.	 */      insn = emit_insn (gen_pic_load_addr_based (reg, orig));#else      if (subregs)	address = gen_reg_rtx (Pmode);      else	address = reg;      emit_insn (gen_pic_load_addr (address, orig));      pic_ref = gen_rtx_MEM (Pmode,			     gen_rtx_PLUS (Pmode, pic_offset_table_rtx,					   address));      RTX_UNCHANGING_P (pic_ref) = 1;      insn = emit_move_insn (reg, pic_ref);#endif      current_function_uses_pic_offset_table = 1;      /* Put a REG_EQUAL note on this insn, so that it can be optimized	 by loop.  */      REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,					    REG_NOTES (insn));      return reg;    }  else if (GET_CODE (orig) == CONST)    {      rtx base, offset;      if (GET_CODE (XEXP (orig, 0)) == PLUS	  && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)	return orig;      if (reg == 0)	{	  if (reload_in_progress || reload_completed)	    abort ();	  else	    reg = gen_reg_rtx (Pmode);	}      if (GET_CODE (XEXP (orig, 0)) == PLUS)	{	  base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);	  offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,					   base == reg ? 0 : reg);	}      else	abort ();      if (GET_CODE (offset) == CONST_INT)	{	  /* The base register doesn't really matter, we only want to	     test the index for the appropriate mode.  */	  GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);	  if (! reload_in_progress && ! reload_completed)	    offset = force_reg (Pmode, offset);	  else	    abort ();	win:	  if (GET_CODE (offset) == CONST_INT)	    return plus_constant_for_output (base, INTVAL (offset));	}      if (GET_MODE_SIZE (mode) > 4	  && (GET_MODE_CLASS (mode) == MODE_INT	      || TARGET_SOFT_FLOAT))	{	  emit_insn (gen_addsi3 (reg, base, offset));	  return reg;	}      return gen_rtx_PLUS (Pmode, base, offset);    }  else if (GET_CODE (orig) == LABEL_REF)    current_function_uses_pic_offset_table = 1;  return orig;}static rtx pic_rtx;intis_pic(x)     rtx x;{  if (x == pic_rtx)    return 1;  return 0;}voidarm_finalize_pic (){#ifndef AOF_ASSEMBLER  rtx l1, pic_tmp, pic_tmp2, seq;  rtx global_offset_table;  if (current_function_uses_pic_offset_table == 0)    return;  if (! flag_pic)    abort ();  start_sequence ();  l1 = gen_label_rtx ();  global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");  /* On the ARM the PC register contains 'dot + 8' at the time of the     addition.  */  pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), 8);  pic_tmp2 = gen_rtx_CONST (VOIDmode,			    gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));  pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));    emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));  emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));  seq = gen_sequence ();  end_sequence ();  emit_insn_after (seq, get_insns ());  /* Need to emit this whether or not we obey regdecls,     since setjmp/longjmp can cause life info to screw up.  */  emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));#endif /* AOF_ASSEMBLER */}#define REG_OR_SUBREG_REG(X)						\  (GET_CODE (X) == REG							\   || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))#define REG_OR_SUBREG_RTX(X)			\   (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))#define ARM_FRAME_RTX(X)				\  ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx	\   || (X) == arg_pointer_rtx)intarm_rtx_costs (x, code)     rtx x;     enum rtx_code code;{  enum machine_mode mode = GET_MODE (x);  enum rtx_code subcode;  int extra_cost;  switch (code)    {    case MEM:      /* Memory costs quite a lot for the first word, but subsequent words	 load at the equivalent of a single insn each.  */      return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)	      + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));    case DIV:    case MOD:      return 100;    case ROTATE:      if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)	return 4;      /* Fall through */    case ROTATERT:      if (mode != SImode)	return 8;      /* Fall through */    case ASHIFT: case LSHIFTRT: case ASHIFTRT:      if (mode == DImode)	return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)		+ ((GET_CODE (XEXP (x, 0)) == REG 		    || (GET_CODE (XEXP (x, 0)) == SUBREG			&& GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))		   ? 0 : 8));      return (1 + ((GET_CODE (XEXP (x, 0)) == REG		    || (GET_CODE (XEXP (x, 0)) == SUBREG			&& GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))		   ? 0 : 4)	      + ((GET_CODE (XEXP (x, 1)) == REG		  || (GET_CODE (XEXP (x, 1)) == SUBREG		      && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)		  || (GET_CODE (XEXP (x, 1)) == CONST_INT))		 ? 0 : 4));    case MINUS:      if (mode == DImode)	return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)		+ ((REG_OR_SUBREG_REG (XEXP (x, 0))		    || (GET_CODE (XEXP (x, 0)) == CONST_INT		       && const_ok_for_arm (INTVAL (XEXP (x, 0)))))		   ? 0 : 8));      if (GET_MODE_CLASS (mode) == MODE_FLOAT)	return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))		      || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE			  && const_double_rtx_ok_for_fpu (XEXP (x, 1))))		     ? 0 : 8)		+ ((REG_OR_SUBREG_REG (XEXP (x, 0))		    || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE			&& const_double_rtx_ok_for_fpu (XEXP (x, 0))))		   ? 0 : 8));      if (((GET_CODE (XEXP (x, 0)) == CONST_INT	    && const_ok_for_arm (INTVAL (XEXP (x, 0)))	    && REG_OR_SUBREG_REG (XEXP (x, 1))))	  || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT	       || subcode == ASHIFTRT || subcode == LSHIFTRT	       || subcode == ROTATE || subcode == ROTATERT	       || (subcode == MULT		   && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT		   && ((INTVAL (XEXP (XEXP (x, 1), 1)) &			(INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))	      && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))	      && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))		  || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)	      && REG_OR_SUBREG_REG (XEXP (x, 0))))	return 1;      /* Fall through */    case PLUS:       if (GET_MODE_CLASS (mode) == MODE_FLOAT)	return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)		+ ((REG_OR_SUBREG_REG (XEXP (x, 1))		    || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE			&& const_double_rtx_ok_for_fpu (XEXP (x, 1))))		   ? 0 : 8));      /* Fall through */    case AND: case XOR: case IOR:       extra_cost = 0;      /* Normally the frame registers will be spilt into reg+const during	 reload, so it is a bad idea to combine them with other instructions,	 since then they might not be moved outside of loops.  As a compromise	 we allow integration with ops that have a constant as their second	 operand.  */      if ((REG_OR_SUBREG_REG (XEXP (x, 0))	   && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))	   && GET_CODE (XEXP (x, 1)) != CONST_INT)	  || (REG_OR_SUBREG_REG (XEXP (x, 0))	      && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))	extra_cost = 4;      if (mode == DImode)	return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)		+ ((REG_OR_SUBREG_REG (XEXP (x, 1))		    || (GET_CODE (XEXP (x, 1)) == CONST_INT			&& const_ok_for_op (INTVAL (XEXP (x, 1)), code)))		   ? 0 : 8));      if (REG_OR_SUBREG_REG (XEXP (x, 0)))	return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)		+ ((REG_OR_SUBREG_REG (XEXP (x, 1))		    || (GET_CODE (XEXP (x, 1)) == CONST_INT			&& const_ok_for_op (INTVAL (XEXP (x, 1)), code)))		   ? 0 : 4));      else if (REG_OR_SUBREG_REG (XEXP (x, 1)))	return (1 + extra_cost		+ ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT		     || subcode == LSHIFTRT || subcode == ASHIFTRT		     || subcode == ROTATE || subcode == ROTATERT		     || (subcode == MULT			 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT			 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &			      (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))		    && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))		    && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))			|| GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))		   ? 0 : 4));      return 8;    case MULT:      /* There is no point basing this on the tuning, since it is always the	 fast variant if it exists at all */      if (arm_fast_multiply && mode == DImode	  && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))	  && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND	      || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))	return 8;      if (GET_MODE_CLASS (mode) == MODE_FLOAT	  || mode == DImode)	return 30;      if (GET_CODE (XEXP (x, 1)) == CONST_INT)	{	  unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))				      & (unsigned HOST_WIDE_INT) 0xffffffff);	  int add_cost = const_ok_for_arm (i) ? 4 : 8;	  int j;	  /* Tune as appropriate */ 	  int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);	  	  for (j = 0; i && j < 32; j += booth_unit_size)	    {	      i >>= booth_unit_size;	      add_cost += 2;	    }	  return add_cost;	}      return (((tune_flags & FL_FAST_MULT) ? 8 : 30)	      + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)	      + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));    case TRUNCATE:      if (arm_fast_multiply && mode == SImode	  && GET_CODE (XEXP (x, 0)) == LSHIFTRT	  && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT	  && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))	      == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))	  && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND	      || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))	return 8;      return 99;    case NEG:      if (GET_MODE_CLASS (mode) == MODE_FLOAT)	return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);      /* Fall through */    case NOT:      if (mode == DImode)	return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);      return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);    case IF_THEN_ELSE:      if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)	return 14;      return 2;    case COMPARE:      return 1;    case ABS:      return 4 + (mode == DImode ? 4 : 0);    case SIGN_EXTEND:      if (GET_MODE (XEXP (x, 0)) == QImode)	return (4 + (mode == DImode ? 4 : 0)		+ (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));      /* Fall through */    case ZERO_EXTEND:      switch (GET_MODE (XEXP (x, 0)))	{	case QImode:	  return (1 + (mode == DImode ? 4 : 0)		  + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));	case HImode:	  return (4 + (mode == DImode ? 4 : 0)		  + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));	case SImode:	  return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));	default:	  break;	}      abort ();    default:      return 99;    }}intarm_adjust_cost (insn, link, dep, cost)     rtx insn;     rtx link;     rtx dep;     int cost;{  rtx i_pat, d_pat;  /* XXX This is not strictly true for the FPA. */  if (REG_NOTE_KIND(link) == REG_DEP_ANTI      || REG_NOTE_KIND(link) == REG_DEP_OUTPUT)    return 0;  if ((i_pat = single_set (insn)) != NULL      && GET_CODE (SET_SRC (i_pat)) == MEM      && (d_pat = single_set (dep)) != NULL      && GET_CODE (SET_DEST (d_pat)) == MEM)    {      /* This is a load after a store, there is no conflict if the load reads	 from a cached area.  Assume that loads from the stack, and from the	 constant pool are cached, and that others will miss.  This is a 	 hack. */      /*       debug_rtx (insn);      debug_rtx (dep);      debug_rtx (link);      fprintf (stderr, "costs %d\n", cost); */      if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))	  || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))	  || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))	  || reg_mentioned_p (hard_frame_pointer_rtx, 			      XEXP (SET_SRC (i_pat), 0)))	{/* 	  fprintf (stderr, "***** Now 1\n"); */	  return 1;	}    }  return cost;}/* This code has been fixed for cross compilation. */static int fpa_consts_inited = 0;char *strings_fpa[8] = {  "0",   "1",   "2",   "3",  "4",   "5",   "0.5", "10"};static REAL_VALUE_TYPE values_fpa[8];static voidinit_fpa_table (){  int i;  REAL_VALUE_TYPE r;  for (i = 0; i < 8; i++)    {      r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);      values_fpa[i] = r;    }  fpa_consts_inited = 1;}/* Return TRUE if rtx X is a valid immediate FPU constant. */intconst_double_rtx_ok_for_fpu (x)     rtx x;{  REAL_VALUE_TYPE r;  int i;    if (!fpa_consts_inited)    init_fpa_table ();    REAL_VALUE_FROM_CONST_DOUBLE (r, x);  if (REAL_VALUE_MINUS_ZERO (r))    return 0;  for (i = 0; i < 8; i++)    if (REAL_VALUES_EQUAL (r, values_fpa[i]))      return 1;  return 0;}/* Return TRUE if rtx X is a valid immediate FPU constant. */intneg_const_double_rtx_ok_for_fpu (x)     rtx x;{  REAL_VALUE_TYPE r;  int i;    if (!fpa_consts_inited)    init_fpa_table ();    REAL_VALUE_FROM_CONST_DOUBLE (r, x);  r = REAL_VALUE_NEGATE (r);  if (REAL_VALUE_MINUS_ZERO (r))    return 0;  for (i = 0; i < 8; i++)    if (REAL_VALUES_EQUAL (r, values_fpa[i]))      return 1;  return 0;}/* Predicates for `match_operand' and `match_operator'.  *//* s_register_operand is the same as register_operand, but it doesn't accept   (SUBREG (MEM)...).   This function exists because at the time it was put in it led to better   code.  SUBREG(MEM) always needs a reload in the places where   s_register_operand is used, and this seemed to lead to excessive   reloading.  */ints_register_operand (op, mode)     register rtx op;     enum machine_mode mode;{  if (GET_MODE (op) != mode && mode != VOIDmode)    return 0;  if (GET_CODE (op) == SUBREG)    op = SUBREG_REG (op);  /* We don't consider registers whose class is NO_REGS     to be a register operand.  */  return (GET_CODE (op) == REG	  && (REGNO (op) >= FIRST_PSEUDO_REGISTER	      || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));}/* Only accept reg, subreg(reg), const_int.  */intreg_or_int_operand (op, mode)     register rtx op;     enum machine_mode mode;{  if (GET_CODE (op) == CONST_INT)    return 1;  if (GET_MODE (op) != mode && mode != VOIDmode)    return 0;  if (GET_CODE (op) == SUBREG)    op = SUBREG_REG (op);  /* We don't consider registers whose class is NO_REGS     to be a register operand.  */  return (GET_CODE (op) == REG	  && (REGNO (op) >= FIRST_PSEUDO_REGISTER	      || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));}/* Return 1 if OP is an item in memory, given that we are in reload.  */intreload_memory_operand (op, mode)     rtx op;     enum machine_mode mode ATTRIBUTE_UNUSED;{  int regno = true_regnum (op);  return (! CONSTANT_P (op)	  && (regno == -1	      || (GET_CODE (op) == REG		  && REGNO (op) >= FIRST_PSEUDO_REGISTER)));}/* Return 1 if OP is a valid memory address, but not valid for a signed byte   memory access (architecture V4) */intbad_signed_byte_operand (op, mode)     rtx op;     enum machine_mode mode;{  if (! memory_operand (op, mode) || GET_CODE (op) != MEM)    return 0;  op = XEXP (op, 0);  /* A sum of anything more complex than reg + reg or reg + const is bad */  if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)      && (! s_register_operand (XEXP (op, 0), VOIDmode)	  || (! s_register_operand (XEXP (op, 1), VOIDmode)	      && GET_CODE (XEXP (op, 1)) != CONST_INT)))    return 1;  /* Big constants are also bad */  if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT      && (INTVAL (XEXP (op, 1)) > 0xff	  || -INTVAL (XEXP (op, 1)) > 0xff))    return 1;  /* Everything else is good, or can will automatically be made so. */  return 0;}/* Return TRUE for valid operands for the rhs of an ARM instruction.  */intarm_rhs_operand (op, mode)     rtx op;     enum machine_mode mode;{  return (s_register_operand (op, mode)	  || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));}/* Return TRUE for valid operands for the rhs of an ARM instruction, or a load. */intarm_rhsm_operand (op, mode)     rtx op;     enum machine_mode mode;{  return (s_register_operand (op, mode)	  || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))	  || memory_operand (op, mode));}/* Return TRUE for valid operands for the rhs of an ARM instruction, or if a   constant that is valid when negated.  */intarm_add_operand (op, mode)     rtx op;     enum machine_mode mode;{  return (s_register_operand (op, mode)	  || (GET_CODE (op) == CONST_INT	      && (const_ok_for_arm (INTVAL (op))		  || const_ok_for_arm (-INTVAL (op)))));}intarm_not_operand (op, mode)     rtx op;     enum machine_mode mode;{  return (s_register_operand (op, mode)	  || (GET_CODE (op) == CONST_INT	      && (const_ok_for_arm (INTVAL (op))		  || const_ok_for_arm (~INTVAL (op)))));}/* Return TRUE if the operand is a memory reference which contains an   offsettable address.  */intoffsettable_memory_operand (op, mode)     register rtx op;     enum machine_mode mode;{  if (mode == VOIDmode)    mode = GET_MODE (op);  return (mode == GET_MODE (op)	  && GET_CODE (op) == MEM	  && offsettable_address_p (reload_completed | reload_in_progress,				    mode, XEXP (op, 0)));}/* Return TRUE if the operand is a memory reference which is, or can be   made word aligned by adjusting the offset.  */intalignable_memory_operand (op, mode)     register rtx op;     enum machine_mode mode;{  rtx reg;  if (mode == VOIDmode)    mode = GET_MODE (op);  if (mode != GET_MODE (op) || GET_CODE (op) != MEM)    return 0;  op = XEXP (op, 0);  return ((GET_CODE (reg = op) == REG	   || (GET_CODE (op) == SUBREG	       && GET_CODE (reg = SUBREG_REG (op)) == REG)	   || (GET_CODE (op) == PLUS	       && GET_CODE (XEXP (op, 1)) == CONST_INT	       && (GET_CODE (reg = XEXP (op, 0)) == REG		   || (GET_CODE (XEXP (op, 0)) == SUBREG		       && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))	  && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4);}/* Similar to s_register_operand, but does not allow hard integer    registers.  */intf_register_operand (op, mode)     register rtx op;     enum machine_mode mode;{  if (GET_MODE (op) != mode && mode != VOIDmode)    return 0;  if (GET_CODE (op) == SUBREG)    op = SUBREG_REG (op);  /* We don't consider registers whose class is NO_REGS     to be a register operand.  */  return (GET_CODE (op) == REG	  && (REGNO (op) >= FIRST_PSEUDO_REGISTER	      || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));}/* Return TRUE for valid operands for the rhs of an FPU instruction.  */intfpu_rhs_operand (op, mode)     rtx op;     enum machine_mode mode;{  if (s_register_operand (op, mode))    return TRUE;  else if (GET_CODE (op) == CONST_DOUBLE)    return (const_double_rtx_ok_for_fpu (op));  return FALSE;}intfpu_add_operand (op, mode)     rtx op;     enum machine_mode mode;{  if (s_register_operand (op, mode))    return TRUE;  else if (GET_CODE (op) == CONST_DOUBLE)    return (const_double_rtx_ok_for_fpu (op) 	    || neg_const_double_rtx_ok_for_fpu (op));  return FALSE;}/* Return nonzero if OP is a constant power of two.  */intpower_of_two_operand (op, mode)     rtx op;     enum machine_mode mode ATTRIBUTE_UNUSED;{  if (GET_CODE (op) == CONST_INT)    {      HOST_WIDE_INT value = INTVAL(op);      return value != 0  &&  (value & (value - 1)) == 0;    }  return FALSE;}/* Return TRUE for a valid operand of a DImode operation.   Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).   Note that this disallows MEM(REG+REG), but allows   MEM(PRE/POST_INC/DEC(REG)).  */intdi_operand (op, mode)     rtx op;     enum machine_mode mode;{  if (s_register_operand (op, mode))    return TRUE;  if (GET_CODE (op) == SUBREG)    op = SUBREG_REG (op);  switch (GET_CODE (op))    {    case CONST_DOUBLE:    case CONST_INT:      return TRUE;    case MEM:      return memory_address_p (DImode, XEXP (op, 0));    default:      return FALSE;    }}/* Return TRUE for a valid operand of a DFmode operation when -msoft-float.   Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).   Note that this disallows MEM(REG+REG), but allows   MEM(PRE/POST_INC/DEC(REG)).  */intsoft_df_operand (op, mode)     rtx op;     enum machine_mode mode;{  if (s_register_operand (op, mode))    return TRUE;  if (GET_CODE (op) == SUBREG)    op = SUBREG_REG (op);  switch (GET_CODE (op))    {    case CONST_DOUBLE:      return TRUE;    case MEM:      return memory_address_p (DFmode, XEXP (op, 0));    default:      return FALSE;    }}/* Return TRUE for valid index operands. */intindex_operand (op, mode)     rtx op;     enum machine_mode mode;{  return (s_register_operand(op, mode)	  || (immediate_operand (op, mode)	      && INTVAL (op) < 4096 && INTVAL (op) > -4096));}/* Return TRUE for valid shifts by a constant. This also accepts any   power of two on the (somewhat overly relaxed) assumption that the   shift operator in this case was a mult. */intconst_shift_operand (op, mode)     rtx op;     enum machine_mode mode;{  return (power_of_two_operand (op, mode)	  || (immediate_operand (op, mode)	      && (INTVAL (op) < 32 && INTVAL (op) > 0)));}/* Return TRUE for arithmetic operators which can be combined with a multiply   (shift).  */intshiftable_operator (x, mode)     rtx x;     enum machine_mode mode;{  if (GET_MODE (x) != mode)    return FALSE;  else    {      enum rtx_code code = GET_CODE (x);      return (code == PLUS || code == MINUS	      || code == IOR || code == XOR || code == AND);    }}/* Return TRUE for shift operators. */intshift_operator (x, mode)     rtx x;     enum machine_mode mode;{  if (GET_MODE (x) != mode)    return FALSE;  else    {      enum rtx_code code = GET_CODE (x);      if (code == MULT)	return power_of_two_operand (XEXP (x, 1), mode);      return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT	      || code == ROTATERT);    }}int equality_operator (x, mode)     rtx x;     enum machine_mode mode ATTRIBUTE_UNUSED;{  return GET_CODE (x) == EQ || GET_CODE (x) == NE;}/* Return TRUE for SMIN SMAX UMIN UMAX operators. */intminmax_operator (x, mode)     rtx x;     enum machine_mode mode;{  enum rtx_code code = GET_CODE (x);  if (GET_MODE (x) != mode)    return FALSE;  return code == SMIN || code == SMAX || code == UMIN || code == UMAX;}/* return TRUE if x is EQ or NE *//* Return TRUE if this is the condition code register, if we aren't given   a mode, accept any class CCmode register */intcc_register (x, mode)     rtx x;     enum machine_mode mode;{  if (mode == VOIDmode)    {      mode = GET_MODE (x);      if (GET_MODE_CLASS (mode) != MODE_CC)	return FALSE;    }  if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)    return TRUE;  return FALSE;}/* Return TRUE if this is the condition code register, if we aren't given   a mode, accept any class CCmode register which indicates a dominance   expression.  */intdominant_cc_register (x, mode)     rtx x;     enum machine_mode mode;{  if (mode == VOIDmode)    {      mode = GET_MODE (x);      if (GET_MODE_CLASS (mode) != MODE_CC)	return FALSE;    }  if (mode != CC_DNEmode && mode != CC_DEQmode      && mode != CC_DLEmode && mode != CC_DLTmode      && mode != CC_DGEmode && mode != CC_DGTmode      && mode != CC_DLEUmode && mode != CC_DLTUmode      && mode != CC_DGEUmode && mode != CC_DGTUmode)    return FALSE;  if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)    return TRUE;  return FALSE;}/* Return TRUE if X references a SYMBOL_REF.  */intsymbol_mentioned_p (x)     rtx x;{  register char *fmt;  register int i;  if (GET_CODE (x) == SYMBOL_REF)    return 1;  fmt = GET_RTX_FORMAT (GET_CODE (x));  for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)    {      if (fmt[i] == 'E')	{	  register int j;	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)	    if (symbol_mentioned_p (XVECEXP (x, i, j)))	      return 1;	}      else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))	return 1;    }  return 0;}/* Return TRUE if X references a LABEL_REF.  */intlabel_mentioned_p (x)     rtx x;{  register char *fmt;  register int i;  if (GET_CODE (x) == LABEL_REF)    return 1;  fmt = GET_RTX_FORMAT (GET_CODE (x));  for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)    {      if (fmt[i] == 'E')	{	  register int j;	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)	    if (label_mentioned_p (XVECEXP (x, i, j)))	      return 1;	}      else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))	return 1;    }  return 0;}enum rtx_codeminmax_code (x)     rtx x;{  enum rtx_code code = GET_CODE (x);  if (code == SMAX)    return GE;  else if (code == SMIN)    return LE;  else if (code == UMIN)    return LEU;  else if (code == UMAX)    return GEU;  abort ();}/* Return 1 if memory locations are adjacent */intadjacent_mem_locations (a, b)     rtx a, b;{  int val0 = 0, val1 = 0;  int reg0, reg1;    if ((GET_CODE (XEXP (a, 0)) == REG       || (GET_CODE (XEXP (a, 0)) == PLUS	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))      && (GET_CODE (XEXP (b, 0)) == REG	  || (GET_CODE (XEXP (b, 0)) == PLUS	      && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))    {      if (GET_CODE (XEXP (a, 0)) == PLUS)        {	  reg0 = REGNO (XEXP (XEXP (a, 0), 0));	  val0 = INTVAL (XEXP (XEXP (a, 0), 1));        }      else	reg0 = REGNO (XEXP (a, 0));      if (GET_CODE (XEXP (b, 0)) == PLUS)        {	  reg1 = REGNO (XEXP (XEXP (b, 0), 0));	  val1 = INTVAL (XEXP (XEXP (b, 0), 1));        }      else	reg1 = REGNO (XEXP (b, 0));      return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);    }  return 0;}/* Return 1 if OP is a load multiple operation.  It is known to be   parallel and the first section will be tested. */intload_multiple_operation (op, mode)     rtx op;     enum machine_mode mode ATTRIBUTE_UNUSED;{  HOST_WIDE_INT count = XVECLEN (op, 0);  int dest_regno;  rtx src_addr;  HOST_WIDE_INT i = 1, base = 0;  rtx elt;  if (count <= 1      || GET_CODE (XVECEXP (op, 0, 0)) != SET)    return 0;  /* Check to see if this might be a write-back */  if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)    {      i++;      base = 1;      /* Now check it more carefully */      if (GET_CODE (SET_DEST (elt)) != REG          || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG          || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))          || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT          || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4          || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER          || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG          || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))              != REGNO (SET_DEST (elt)))        return 0;      count--;    }  /* Perform a quick check so we don't blow up below.  */  if (count <= i      || GET_CODE (XVECEXP (op, 0, i - 1)) != SET      || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG      || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)    return 0;  dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));  src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);  for (; i < count; i++)    {      elt = XVECEXP (op, 0, i);      if (GET_CODE (elt) != SET          || GET_CODE (SET_DEST (elt)) != REG          || GET_MODE (SET_DEST (elt)) != SImode          || REGNO (SET_DEST (elt)) != dest_regno + i - base          || GET_CODE (SET_SRC (elt)) != MEM          || GET_MODE (SET_SRC (elt)) != SImode          || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS          || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)          || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT          || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)        return 0;    }  return 1;}/* Return 1 if OP is a store multiple operation.  It is known to be   parallel and the first section will be tested. */intstore_multiple_operation (op, mode)     rtx op;     enum machine_mode mode ATTRIBUTE_UNUSED;{  HOST_WIDE_INT count = XVECLEN (op, 0);  int src_regno;  rtx dest_addr;  HOST_WIDE_INT i = 1, base = 0;  rtx elt;  if (count <= 1      || GET_CODE (XVECEXP (op, 0, 0)) != SET)    return 0;  /* Check to see if this might be a write-back */  if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)    {      i++;      base = 1;      /* Now check it more carefully */      if (GET_CODE (SET_DEST (elt)) != REG          || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG          || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))          || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT          || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4          || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER          || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG          || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))              != REGNO (SET_DEST (elt)))        return 0;      count--;    }  /* Perform a quick check so we don't blow up below.  */  if (count <= i      || GET_CODE (XVECEXP (op, 0, i - 1)) != SET      || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM      || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)    return 0;  src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));  dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);  for (; i < count; i++)    {      elt = XVECEXP (op, 0, i);      if (GET_CODE (elt) != SET          || GET_CODE (SET_SRC (elt)) != REG          || GET_MODE (SET_SRC (elt)) != SImode          || REGNO (SET_SRC (elt)) != src_regno + i - base          || GET_CODE (SET_DEST (elt)) != MEM          || GET_MODE (SET_DEST (elt)) != SImode          || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS          || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)          || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT          || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)        return 0;    }  return 1;}intload_multiple_sequence (operands, nops, regs, base, load_offset)     rtx *operands;     int nops;     int *regs;     int *base;     HOST_WIDE_INT *load_offset;{  int unsorted_regs[4];  HOST_WIDE_INT unsorted_offsets[4];  int order[4];  int base_reg = -1;  int i;  /* Can only handle 2, 3, or 4 insns at present, though could be easily     extended if required.  */  if (nops < 2 || nops > 4)    abort ();  /* Loop over the operands and check that the memory references are     suitable (ie immediate offsets from the same base register).  At     the same time, extract the target register, and the memory     offsets.  */  for (i = 0; i < nops; i++)    {      rtx reg;      rtx offset;      /* Convert a subreg of a mem into the mem itself.  */      if (GET_CODE (operands[nops + i]) == SUBREG)	operands[nops + i] = alter_subreg(operands[nops + i]);      if (GET_CODE (operands[nops + i]) != MEM)	abort ();      /* Don't reorder volatile memory references; it doesn't seem worth	 looking for the case where the order is ok anyway.  */      if (MEM_VOLATILE_P (operands[nops + i]))	return 0;      offset = const0_rtx;      if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG	   || (GET_CODE (reg) == SUBREG	       && GET_CODE (reg = SUBREG_REG (reg)) == REG))	  || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS	      && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))		   == REG)		  || (GET_CODE (reg) == SUBREG		      && GET_CODE (reg = SUBREG_REG (reg)) == REG))	      && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))		  == CONST_INT)))	{	  if (i == 0)	    {	      base_reg = REGNO(reg);	      unsorted_regs[0] = (GET_CODE (operands[i]) == REG				  ? REGNO (operands[i])				  : REGNO (SUBREG_REG (operands[i])));	      order[0] = 0;	    }	  else 	    {	      if (base_reg != REGNO (reg))		/* Not addressed from the same base register.  */		return 0;	      unsorted_regs[i] = (GET_CODE (operands[i]) == REG				  ? REGNO (operands[i])				  : REGNO (SUBREG_REG (operands[i])));	      if (unsorted_regs[i] < unsorted_regs[order[0]])		order[0] = i;	    }	  /* If it isn't an integer register, or if it overwrites the	     base register but isn't the last insn in the list, then	     we can't do this.  */	  if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14	      || (i != nops - 1 && unsorted_regs[i] == base_reg))	    return 0;	  unsorted_offsets[i] = INTVAL (offset);	}      else	/* Not a suitable memory address.  */	return 0;    }  /* All the useful information has now been extracted from the     operands into unsorted_regs and unsorted_offsets; additionally,     order[0] has been set to the lowest numbered register in the     list.  Sort the registers into order, and check that the memory     offsets are ascending and adjacent.  */  for (i = 1; i < nops; i++)    {      int j;      order[i] = order[i - 1];      for (j = 0; j < nops; j++)	if (unsorted_regs[j] > unsorted_regs[order[i - 1]]	    && (order[i] == order[i - 1]		|| unsorted_regs[j] < unsorted_regs[order[i]]))	  order[i] = j;      /* Have we found a suitable register? if not, one must be used more	 than once.  */      if (order[i] == order[i - 1])	return 0;      /* Is the memory address adjacent and ascending? */      if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)	return 0;    }  if (base)    {      *base = base_reg;      for (i = 0; i < nops; i++)	regs[i] = unsorted_regs[order[i]];      *load_offset = unsorted_offsets[order[0]];    }  if (unsorted_offsets[order[0]] == 0)    return 1; /* ldmia */  if (unsorted_offsets[order[0]] == 4)    return 2; /* ldmib */  if (unsorted_offsets[order[nops - 1]] == 0)    return 3; /* ldmda */  if (unsorted_offsets[order[nops - 1]] == -4)    return 4; /* ldmdb */  /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm if     the offset isn't small enough.  The reason 2 ldrs are faster is because     these ARMs are able to do more than one cache access in a single cycle.     The ARM9 and StrongARM have Harvard caches, whilst the ARM8 has a double      bandwidth cache.  This means that these cores can do both an instruction      fetch and a data fetch in a single cycle, so the trick of calculating the      address into a scratch register (one of the result regs) and then doing a      load multiple actually becomes slower (and no smaller in code size).  That      is the transformation  	ldr	rd1, [rbase + offset] 	ldr	rd2, [rbase + offset + 4]      to  	add	rd1, rbase, offset 	ldmia	rd1, {rd1, rd2}      produces worse code -- '3 cycles + any stalls on rd2' instead of '2 cycles      + any stalls on rd2'.  On ARMs with only one cache access per cycle, the      first sequence could never complete in less than 6 cycles, whereas the ldm      sequence would only take 5 and would make better use of sequential accesses     if not hitting the cache.     We cheat here and test 'arm_ld_sched' which we currently know to only be     true for the ARM8, ARM9 and StrongARM.  If this ever changes, then the test     below needs to be reworked.  */  if (nops == 2 && arm_ld_sched)    return 0;  /* Can't do it without setting up the offset, only do this if it takes     no more than one insn.  */  return (const_ok_for_arm (unsorted_offsets[order[0]]) 	  || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;}char *emit_ldm_seq (operands, nops)     rtx *operands;     int nops;{  int regs[4];  int base_reg;  HOST_WIDE_INT offset;  char buf[100];  int i;  switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))    {    case 1:      strcpy (buf, "ldm%?ia\t");      break;    case 2:      strcpy (buf, "ldm%?ib\t");      break;    case 3:      strcpy (buf, "ldm%?da\t");      break;    case 4:      strcpy (buf, "ldm%?db\t");      break;    case 5:      if (offset >= 0)	sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,		 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],		 (long) offset);      else	sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,		 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],		 (long) -offset);      output_asm_insn (buf, operands);      base_reg = regs[0];      strcpy (buf, "ldm%?ia\t");      break;    default:      abort ();    }  sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, 	   reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);  for (i = 1; i < nops; i++)    sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,	     reg_names[regs[i]]);  strcat (buf, "}\t%@ phole ldm");  output_asm_insn (buf, operands);  return "";}intstore_multiple_sequence (operands, nops, regs, base, load_offset)     rtx *operands;     int nops;     int *regs;     int *base;     HOST_WIDE_INT *load_offset;{  int unsorted_regs[4];  HOST_WIDE_INT unsorted_offsets[4];  int order[4];  int base_reg = -1;  int i;  /* Can only handle 2, 3, or 4 insns at present, though could be easily     extended if required.  */  if (nops < 2 || nops > 4)    abort ();  /* Loop over the operands and check that the memory references are     suitable (ie immediate offsets from the same base register).  At     the same time, extract the target register, and the memory     offsets.  */  for (i = 0; i < nops; i++)    {      rtx reg;      rtx offset;      /* Convert a subreg of a mem into the mem itself.  */      if (GET_CODE (operands[nops + i]) == SUBREG)	operands[nops + i] = alter_subreg(operands[nops + i]);      if (GET_CODE (operands[nops + i]) != MEM)	abort ();      /* Don't reorder volatile memory references; it doesn't seem worth	 looking for the case where the order is ok anyway.  */      if (MEM_VOLATILE_P (operands[nops + i]))	return 0;      offset = const0_rtx;      if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG	   || (GET_CODE (reg) == SUBREG	       && GET_CODE (reg = SUBREG_REG (reg)) == REG))	  || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS	      && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))		   == REG)		  || (GET_CODE (reg) == SUBREG		      && GET_CODE (reg = SUBREG_REG (reg)) == REG))	      && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))		  == CONST_INT)))	{	  if (i == 0)	    {	      base_reg = REGNO(reg);	      unsorted_regs[0] = (GET_CODE (operands[i]) == REG				  ? REGNO (operands[i])				  : REGNO (SUBREG_REG (operands[i])));	      order[0] = 0;	    }	  else 	    {	      if (base_reg != REGNO (reg))		/* Not addressed from the same base register.  */		return 0;	      unsorted_regs[i] = (GET_CODE (operands[i]) == REG				  ? REGNO (operands[i])				  : REGNO (SUBREG_REG (operands[i])));	      if (unsorted_regs[i] < unsorted_regs[order[0]])		order[0] = i;	    }	  /* If it isn't an integer register, then we can't do this.  */	  if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)	    return 0;	  unsorted_offsets[i] = INTVAL (offset);	}      else	/* Not a suitable memory address.  */	return 0;    }  /* All the useful information has now been extracted from the     operands into unsorted_regs and unsorted_offsets; additionally,     order[0] has been set to the lowest numbered register in the     list.  Sort the registers into order, and check that the memory     offsets are ascending and adjacent.  */  for (i = 1; i < nops; i++)    {      int j;      order[i] = order[i - 1];      for (j = 0; j < nops; j++)	if (unsorted_regs[j] > unsorted_regs[order[i - 1]]	    && (order[i] == order[i - 1]		|| unsorted_regs[j] < unsorted_regs[order[i]]))	  order[i] = j;      /* Have we found a suitable register? if not, one must be used more	 than once.  */      if (order[i] == order[i - 1])	return 0;      /* Is the memory address adjacent and ascending? */      if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)	return 0;    }  if (base)    {      *base = base_reg;      for (i = 0; i < nops; i++)	regs[i] = unsorted_regs[order[i]];      *load_offset = unsorted_offsets[order[0]];    }  if (unsorted_offsets[order[0]] == 0)    return 1; /* stmia */  if (unsorted_offsets[order[0]] == 4)    return 2; /* stmib */  if (unsorted_offsets[order[nops - 1]] == 0)    return 3; /* stmda */  if (unsorted_offsets[order[nops - 1]] == -4)    return 4; /* stmdb */  return 0;}char *emit_stm_seq (operands, nops)     rtx *operands;     int nops;{  int regs[4];  int base_reg;  HOST_WIDE_INT offset;  char buf[100];  int i;  switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))    {    case 1:      strcpy (buf, "stm%?ia\t");      break;    case 2:      strcpy (buf, "stm%?ib\t");      break;    case 3:      strcpy (buf, "stm%?da\t");      break;    case 4:      strcpy (buf, "stm%?db\t");      break;    default:      abort ();    }  sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, 	   reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);  for (i = 1; i < nops; i++)    sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,	     reg_names[regs[i]]);  strcat (buf, "}\t%@ phole stm");  output_asm_insn (buf, operands);  return "";}intmulti_register_push (op, mode)     rtx op;     enum machine_mode mode ATTRIBUTE_UNUSED;{  if (GET_CODE (op) != PARALLEL      || (GET_CODE (XVECEXP (op, 0, 0)) != SET)      || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)      || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))    return 0;  return 1;}/* Routines for use with attributes *//* Return nonzero if ATTR is a valid attribute for DECL.   ATTRIBUTES are any existing attributes and ARGS are the arguments   supplied with ATTR.   Supported attributes:   naked: don't output any prologue or epilogue code, the user is assumed   to do the right thing.  */intarm_valid_machine_decl_attribute (decl, attr, args)     tree decl;     tree attr;     tree args;{  if (args != NULL_TREE)    return 0;  if (is_attribute_p ("naked", attr))    return TREE_CODE (decl) == FUNCTION_DECL;  return 0;}/* Return non-zero if FUNC is a naked function.  */static intarm_naked_function_p (func)     tree func;{  tree a;  if (TREE_CODE (func) != FUNCTION_DECL)    abort ();    a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));  return a != NULL_TREE;}/* Routines for use in generating RTL */rtxarm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,		       in_struct_p, scalar_p)     int base_regno;     int count;     rtx from;     int up;     int write_back;     int unchanging_p;     int in_struct_p;     int scalar_p;{  int i = 0, j;  rtx result;  int sign = up ? 1 : -1;  rtx mem;  result = gen_rtx_PARALLEL (VOIDmode,			     rtvec_alloc (count + (write_back ? 2 : 0)));  if (write_back)    {      XVECEXP (result, 0, 0)	= gen_rtx_SET (GET_MODE (from), from,		       plus_constant (from, count * 4 * sign));      i = 1;      count++;    }  for (j = 0; i < count; i++, j++)    {      mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));      RTX_UNCHANGING_P (mem) = unchanging_p;      MEM_IN_STRUCT_P (mem) = in_struct_p;      MEM_SCALAR_P (mem) = scalar_p;      XVECEXP (result, 0, i)	= gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);    }  if (write_back)    XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, from);  return result;}rtxarm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,			in_struct_p, scalar_p)     int base_regno;     int count;     rtx to;     int up;     int write_back;     int unchanging_p;     int in_struct_p;     int scalar_p;{  int i = 0, j;  rtx result;  int sign = up ? 1 : -1;  rtx mem;  result = gen_rtx_PARALLEL (VOIDmode,			     rtvec_alloc (count + (write_back ? 2 : 0)));  if (write_back)    {      XVECEXP (result, 0, 0)	= gen_rtx_SET (GET_MODE (to), to,		       plus_constant (to, count * 4 * sign));      i = 1;      count++;    }  for (j = 0; i < count; i++, j++)    {      mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));      RTX_UNCHANGING_P (mem) = unchanging_p;      MEM_IN_STRUCT_P (mem) = in_struct_p;      MEM_SCALAR_P (mem) = scalar_p;      XVECEXP (result, 0, i)	= gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));    }  if (write_back)    XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, to);  return result;}intarm_gen_movstrqi (operands)     rtx *operands;{  HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;  int i;  rtx src, dst;  rtx st_src, st_dst, fin_src, fin_dst;  rtx part_bytes_reg = NULL;  rtx mem;  int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;  int dst_scalar_p, src_scalar_p;  if (GET_CODE (operands[2]) != CONST_INT      || GET_CODE (operands[3]) != CONST_INT      || INTVAL (operands[2]) > 64      || INTVAL (operands[3]) & 3)    return 0;  st_dst = XEXP (operands[0], 0);  st_src = XEXP (operands[1], 0);  dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);  dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);  dst_scalar_p = MEM_SCALAR_P (operands[0]);  src_unchanging_p = RTX_UNCHANGING_P (operands[1]);  src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);  src_scalar_p = MEM_SCALAR_P (operands[1]);  fin_dst = dst = copy_to_mode_reg (SImode, st_dst);  fin_src = src = copy_to_mode_reg (SImode, st_src);  in_words_to_go = (INTVAL (operands[2]) + 3) / 4;  out_words_to_go = INTVAL (operands[2]) / 4;  last_bytes = INTVAL (operands[2]) & 3;  if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)    part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);  for (i = 0; in_words_to_go >= 2; i+=4)    {      if (in_words_to_go > 4)	emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,					  src_unchanging_p,					  src_in_struct_p,					  src_scalar_p));      else	emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, 					  FALSE, src_unchanging_p,					  src_in_struct_p, src_scalar_p));      if (out_words_to_go)	{	  if (out_words_to_go > 4)	    emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,					       dst_unchanging_p,					       dst_in_struct_p,					       dst_scalar_p));	  else if (out_words_to_go != 1)	    emit_insn (arm_gen_store_multiple (0, out_words_to_go,					       dst, TRUE, 					       (last_bytes == 0						? FALSE : TRUE),					       dst_unchanging_p,					       dst_in_struct_p,					       dst_scalar_p));	  else	    {	      mem = gen_rtx_MEM (SImode, dst);	      RTX_UNCHANGING_P (mem) = dst_unchanging_p;	      MEM_IN_STRUCT_P (mem) = dst_in_struct_p;	      MEM_SCALAR_P (mem) = dst_scalar_p;	      emit_move_insn (mem, gen_rtx_REG (SImode, 0));	      if (last_bytes != 0)		emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));	    }	}      in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;      out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;    }  /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do.  */  if (out_words_to_go)  {    rtx sreg;    mem = gen_rtx_MEM (SImode, src);    RTX_UNCHANGING_P (mem) = src_unchanging_p;    MEM_IN_STRUCT_P (mem) = src_in_struct_p;    MEM_SCALAR_P (mem) = src_scalar_p;    emit_move_insn (sreg = gen_reg_rtx (SImode), mem);    emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));    mem = gen_rtx_MEM (SImode, dst);    RTX_UNCHANGING_P (mem) = dst_unchanging_p;    MEM_IN_STRUCT_P (mem) = dst_in_struct_p;    MEM_SCALAR_P (mem) = dst_scalar_p;    emit_move_insn (mem, sreg);    emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));    in_words_to_go--;    if (in_words_to_go)	/* Sanity check */      abort ();  }  if (in_words_to_go)    {      if (in_words_to_go < 0)	abort ();      mem = gen_rtx_MEM (SImode, src);      RTX_UNCHANGING_P (mem) = src_unchanging_p;      MEM_IN_STRUCT_P (mem) = src_in_struct_p;      MEM_SCALAR_P (mem) = src_scalar_p;      part_bytes_reg = copy_to_mode_reg (SImode, mem);    }  if (BYTES_BIG_ENDIAN && last_bytes)    {      rtx tmp = gen_reg_rtx (SImode);      if (part_bytes_reg == NULL)	abort ();      /* The bytes we want are in the top end of the word */      emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,			      GEN_INT (8 * (4 - last_bytes))));      part_bytes_reg = tmp;            while (last_bytes)	{	  mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));	  RTX_UNCHANGING_P (mem) = dst_unchanging_p;	  MEM_IN_STRUCT_P (mem) = dst_in_struct_p;	  MEM_SCALAR_P (mem) = dst_scalar_p;	  emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));	  if (--last_bytes)	    {	      tmp = gen_reg_rtx (SImode);	      emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));	      part_bytes_reg = tmp;	    }	}	      }  else    {      while (last_bytes)	{	  if (part_bytes_reg == NULL)	    abort ();	  mem = gen_rtx_MEM (QImode, dst);	  RTX_UNCHANGING_P (mem) = dst_unchanging_p;	  MEM_IN_STRUCT_P (mem) = dst_in_struct_p;	  MEM_SCALAR_P (mem) = dst_scalar_p;	  emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));	  if (--last_bytes)	    {	      rtx tmp = gen_reg_rtx (SImode);	      emit_insn (gen_addsi3 (dst, dst, const1_rtx));	      emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));	      part_bytes_reg = tmp;	    }	}    }  return 1;}/* Generate a memory reference for a half word, such that it will be loaded   into the top 16 bits of the word.  We can assume that the address is   known to be alignable and of the form reg, or plus (reg, const).  */rtxgen_rotated_half_load (memref)     rtx memref;{  HOST_WIDE_INT offset = 0;  rtx base = XEXP (memref, 0);  if (GET_CODE (base) == PLUS)    {      offset = INTVAL (XEXP (base, 1));      base = XEXP (base, 0);    }  /* If we aren't allowed to generate unaligned addresses, then fail.  */  if (TARGET_SHORT_BY_BYTES      && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))    return NULL;  base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));  if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))    return base;  return gen_rtx_ROTATE (SImode, base, GEN_INT (16));}static enum machine_modeselect_dominance_cc_mode (x, y, cond_or)     rtx x;     rtx y;     HOST_WIDE_INT cond_or;{  enum rtx_code cond1, cond2;  int swapped = 0;  /* Currently we will probably get the wrong result if the individual     comparisons are not simple.  This also ensures that it is safe to     reverse a comparison if necessary.  */  if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))       != CCmode)      || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))	  != CCmode))    return CCmode;  if (cond_or)    cond1 = reverse_condition (cond1);  /* If the comparisons are not equal, and one doesn't dominate the other,     then we can't do this.  */  if (cond1 != cond2       && ! comparison_dominates_p (cond1, cond2)      && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))    return CCmode;  if (swapped)    {      enum rtx_code temp = cond1;      cond1 = cond2;      cond2 = temp;    }  switch (cond1)    {    case EQ:      if (cond2 == EQ || ! cond_or)	return CC_DEQmode;      switch (cond2)	{	case LE: return CC_DLEmode;	case LEU: return CC_DLEUmode;	case GE: return CC_DGEmode;	case GEU: return CC_DGEUmode;	default: break;	}      break;    case LT:      if (cond2 == LT || ! cond_or)	return CC_DLTmode;      if (cond2 == LE)	return CC_DLEmode;      if (cond2 == NE)	return CC_DNEmode;      break;    case GT:      if (cond2 == GT || ! cond_or)	return CC_DGTmode;      if (cond2 == GE)	return CC_DGEmode;      if (cond2 == NE)	return CC_DNEmode;      break;          case LTU:      if (cond2 == LTU || ! cond_or)	return CC_DLTUmode;      if (cond2 == LEU)	return CC_DLEUmode;      if (cond2 == NE)	return CC_DNEmode;      break;    case GTU:      if (cond2 == GTU || ! cond_or)	return CC_DGTUmode;      if (cond2 == GEU)	return CC_DGEUmode;      if (cond2 == NE)	return CC_DNEmode;      break;    /* The remaining cases only occur when both comparisons are the       same.  */    case NE:      return CC_DNEmode;    case LE:      return CC_DLEmode;    case GE:      return CC_DGEmode;    case LEU:      return CC_DLEUmode;    case GEU:      return CC_DGEUmode;    default:      break;    }  abort ();}enum machine_modearm_select_cc_mode (op, x, y)     enum rtx_code op;     rtx x;     rtx y;{  /* All floating point compares return CCFP if it is an equality     comparison, and CCFPE otherwise.  */  if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)    return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;    /* A compare with a shifted operand.  Because of canonicalization, the     comparison will have to be swapped when we emit the assembler.  */  if (GET_MODE (y) == SImode && GET_CODE (y) == REG      && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT	  || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE	  || GET_CODE (x) == ROTATERT))    return CC_SWPmode;  /* This is a special case that is used by combine to allow a      comparison of a shifted byte load to be split into a zero-extend     followed by a comparison of the shifted integer (only valid for     equalities and unsigned inequalities).  */  if (GET_MODE (x) == SImode      && GET_CODE (x) == ASHIFT      && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24      && GET_CODE (XEXP (x, 0)) == SUBREG      && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM      && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode      && (op == EQ || op == NE	  || op == GEU || op == GTU || op == LTU || op == LEU)      && GET_CODE (y) == CONST_INT)    return CC_Zmode;  /* An operation that sets the condition codes as a side-effect, the     V flag is not set correctly, so we can only use comparisons where     this doesn't matter.  (For LT and GE we can use "mi" and "pl"     instead.  */  if (GET_MODE (x) == SImode      && y == const0_rtx      && (op == EQ || op == NE || op == LT || op == GE)      && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS	  || GET_CODE (x) == AND || GET_CODE (x) == IOR	  || GET_CODE (x) == XOR || GET_CODE (x) == MULT	  || GET_CODE (x) == NOT || GET_CODE (x) == NEG	  || GET_CODE (x) == LSHIFTRT	  || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT	  || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))    return CC_NOOVmode;  /* A construct for a conditional compare, if the false arm contains     0, then both conditions must be true, otherwise either condition     must be true.  Not all conditions are possible, so CCmode is     returned if it can't be done.  */  if (GET_CODE (x) == IF_THEN_ELSE      && (XEXP (x, 2) == const0_rtx	  || XEXP (x, 2) == const1_rtx)      && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'      && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')    return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 				     INTVAL (XEXP (x, 2)));  if (GET_MODE (x) == QImode && (op == EQ || op == NE))    return CC_Zmode;  if (GET_MODE (x) == SImode && (op == LTU || op == GEU)      && GET_CODE (x) == PLUS      && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))    return CC_Cmode;  return CCmode;}/* X and Y are two things to compare using CODE.  Emit the compare insn and   return the rtx for register 0 in the proper mode.  FP means this is a   floating point compare: I don't think that it is needed on the arm.  */rtxgen_compare_reg (code, x, y)     enum rtx_code code;     rtx x, y;{  enum machine_mode mode = SELECT_CC_MODE (code, x, y);  rtx cc_reg = gen_rtx_REG (mode, 24);  emit_insn (gen_rtx_SET (VOIDmode, cc_reg,			  gen_rtx_COMPARE (mode, x, y)));  return cc_reg;}voidarm_reload_in_hi (operands)     rtx *operands;{  rtx ref = operands[1];  rtx base, scratch;  HOST_WIDE_INT offset = 0;  if (GET_CODE (ref) == SUBREG)    {      offset = SUBREG_WORD (ref) * UNITS_PER_WORD;      if (BYTES_BIG_ENDIAN)	offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))		   - MIN (UNITS_PER_WORD,			  GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));      ref = SUBREG_REG (ref);    }  if (GET_CODE (ref) == REG)    {      /* We have a pseudo which has been spilt onto the stack; there	 are two cases here: the first where there is a simple	 stack-slot replacement and a second where the stack-slot is	 out of range, or is used as a subreg.  */      if (reg_equiv_mem[REGNO (ref)])	{	  ref = reg_equiv_mem[REGNO (ref)];	  base = find_replacement (&XEXP (ref, 0));	}      else	/* The slot is out of range, or was dressed up in a SUBREG */	base = reg_equiv_address[REGNO (ref)];    }  else    base = find_replacement (&XEXP (ref, 0));  /* Handle the case where the address is too complex to be offset by 1.  */  if (GET_CODE (base) == MINUS      || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))    {      rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);      emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));      base = base_plus;    }  else if (GET_CODE (base) == PLUS)    {      /* The addend must be CONST_INT, or we would have dealt with it above */      HOST_WIDE_INT hi, lo;      offset += INTVAL (XEXP (base, 1));      base = XEXP (base, 0);      /* Rework the address into a legal sequence of insns */      /* Valid range for lo is -4095 -> 4095 */      lo = (offset >= 0	    ? (offset & 0xfff)	    : -((-offset) & 0xfff));      /* Corner case, if lo is the max offset then we would be out of range	 once we have added the additional 1 below, so bump the msb into the	 pre-loading insn(s).  */      if (lo == 4095)	lo &= 0x7ff;      hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFF)	     ^ (HOST_WIDE_INT) 0x80000000)	    - (HOST_WIDE_INT) 0x80000000);      if (hi + lo != offset)	abort ();      if (hi != 0)	{	  rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);	  /* Get the base address; addsi3 knows how to handle constants	     that require more than one insn */	  emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));	  base = base_plus;	  offset = lo;	}    }  scratch = gen_rtx_REG (SImode, REGNO (operands[2]));  emit_insn (gen_zero_extendqisi2 (scratch,				   gen_rtx_MEM (QImode,						plus_constant (base,							       offset))));  emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),				   gen_rtx_MEM (QImode, 						plus_constant (base,							       offset + 1))));  if (BYTES_BIG_ENDIAN)    emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),			gen_rtx_IOR (SImode, 				     gen_rtx_ASHIFT				     (SImode,				      gen_rtx_SUBREG (SImode, operands[0], 0),				      GEN_INT (8)),				     scratch)));  else    emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),			    gen_rtx_IOR (SImode, 					 gen_rtx_ASHIFT (SImode, scratch,							 GEN_INT (8)),					 gen_rtx_SUBREG (SImode, operands[0],							 0))));}/* Handle storing a half-word to memory during reload by synthesising as two   byte stores.  Take care not to clobber the input values until after we   have moved them somewhere safe.  This code assumes that if the DImode   scratch in operands[2] overlaps either the input value or output address   in some way, then that value must die in this insn (we absolutely need   two scratch registers for some corner cases).  */voidarm_reload_out_hi (operands)     rtx *operands;{  rtx ref = operands[0];  rtx outval = operands[1];  rtx base, scratch;  HOST_WIDE_INT offset = 0;  if (GET_CODE (ref) == SUBREG)    {      offset = SUBREG_WORD (ref) * UNITS_PER_WORD;      if (BYTES_BIG_ENDIAN)	offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))		   - MIN (UNITS_PER_WORD,			  GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));      ref = SUBREG_REG (ref);    }  if (GET_CODE (ref) == REG)    {      /* We have a pseudo which has been spilt onto the stack; there	 are two cases here: the first where there is a simple	 stack-slot replacement and a second where the stack-slot is	 out of range, or is used as a subreg.  */      if (reg_equiv_mem[REGNO (ref)])	{	  ref = reg_equiv_mem[REGNO (ref)];	  base = find_replacement (&XEXP (ref, 0));	}      else	/* The slot is out of range, or was dressed up in a SUBREG */	base = reg_equiv_address[REGNO (ref)];    }  else    base = find_replacement (&XEXP (ref, 0));  scratch = gen_rtx_REG (SImode, REGNO (operands[2]));  /* Handle the case where the address is too complex to be offset by 1.  */  if (GET_CODE (base) == MINUS      || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))    {      rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);      /* Be careful not to destroy OUTVAL.  */      if (reg_overlap_mentioned_p (base_plus, outval))	{	  /* Updating base_plus might destroy outval, see if we can	     swap the scratch and base_plus.  */	  if (! reg_overlap_mentioned_p (scratch, outval))	    {	      rtx tmp = scratch;	      scratch = base_plus;	      base_plus = tmp;	    }	  else	    {	      rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));	      /* Be conservative and copy OUTVAL into the scratch now,		 this should only be necessary if outval is a subreg		 of something larger than a word.  */	      /* XXX Might this clobber base?  I can't see how it can,		 since scratch is known to overlap with OUTVAL, and		 must be wider than a word.  */	      emit_insn (gen_movhi (scratch_hi, outval));	      outval = scratch_hi;	    }	}      emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));      base = base_plus;    }  else if (GET_CODE (base) == PLUS)    {      /* The addend must be CONST_INT, or we would have dealt with it above */      HOST_WIDE_INT hi, lo;      offset += INTVAL (XEXP (base, 1));      base = XEXP (base, 0);      /* Rework the address into a legal sequence of insns */      /* Valid range for lo is -4095 -> 4095 */      lo = (offset >= 0	    ? (offset & 0xfff)	    : -((-offset) & 0xfff));      /* Corner case, if lo is the max offset then we would be out of range	 once we have added the additional 1 below, so bump the msb into the	 pre-loading insn(s).  */      if (lo == 4095)	lo &= 0x7ff;      hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFF)	     ^ (HOST_WIDE_INT) 0x80000000)	    - (HOST_WIDE_INT) 0x80000000);      if (hi + lo != offset)	abort ();      if (hi != 0)	{	  rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);	  /* Be careful not to destroy OUTVAL.  */	  if (reg_overlap_mentioned_p (base_plus, outval))	    {	      /* Updating base_plus might destroy outval, see if we		 can swap the scratch and base_plus.  */	      if (! reg_overlap_mentioned_p (scratch, outval))		{		  rtx tmp = scratch;		  scratch = base_plus;		  base_plus = tmp;		}	      else		{		  rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));		  /* Be conservative and copy outval into scratch now,		     this should only be necessary if outval is a		     subreg of something larger than a word.  */		  /* XXX Might this clobber base?  I can't see how it		     can, since scratch is known to overlap with		     outval.  */		  emit_insn (gen_movhi (scratch_hi, outval));		  outval = scratch_hi;		}	    }	  /* Get the base address; addsi3 knows how to handle constants	     that require more than one insn */	  emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));	  base = base_plus;	  offset = lo;	}    }  if (BYTES_BIG_ENDIAN)    {      emit_insn (gen_movqi (gen_rtx_MEM (QImode, 					 plus_constant (base, offset + 1)),			    gen_rtx_SUBREG (QImode, outval, 0)));      emit_insn (gen_lshrsi3 (scratch,			      gen_rtx_SUBREG (SImode, outval, 0),			      GEN_INT (8)));      emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),			    gen_rtx_SUBREG (QImode, scratch, 0)));    }  else    {      emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),			    gen_rtx_SUBREG (QImode, outval, 0)));      emit_insn (gen_lshrsi3 (scratch,			      gen_rtx_SUBREG (SImode, outval, 0),			      GEN_INT (8)));      emit_insn (gen_movqi (gen_rtx_MEM (QImode,					 plus_constant (base, offset + 1)),			    gen_rtx_SUBREG (QImode, scratch, 0)));    }}/* Routines for manipulation of the constant pool.  *//* This is unashamedly hacked from the version in sh.c, since the problem is   extremely similar.  *//* Arm instructions cannot load a large constant into a register,   constants have to come from a pc relative load.  The reference of a pc   relative load instruction must be less than 1k infront of the instruction.   This means that we often have to dump a constant inside a function, and   generate code to branch around it.   It is important to minimize this, since the branches will slow things   down and make things bigger.   Worst case code looks like:	ldr	rn, L1	b	L2	align	L1:	.long value	L2:	..	ldr	rn, L3	b	L4	align	L3:	.long value	L4:	..   We fix this by performing a scan before scheduling, which notices which   instructions need to have their operands fetched from the constant table   and builds the table.   The algorithm is:   scan, find an instruction which needs a pcrel move.  Look forward, find th   last barrier which is within MAX_COUNT bytes of the requirement.   If there isn't one, make one.  Process all the instructions between   the find and the barrier.   In the above example, we can tell that L3 is within 1k of L1, so   the first move can be shrunk from the 2 insn+constant sequence into   just 1 insn, and the constant moved to L3 to make:	ldr	rn, L1	..	ldr	rn, L3	b	L4	align	L1:	.long value	L3:	.long value	L4:   Then the second move becomes the target for the shortening process. */typedef struct{  rtx value;                    /* Value in table */  HOST_WIDE_INT next_offset;  enum machine_mode mode;       /* Mode of value */} pool_node;/* The maximum number of constants that can fit into one pool, since   the pc relative range is 0...1020 bytes and constants are at least 4   bytes long */#define MAX_POOL_SIZE (1020/4)static pool_node pool_vector[MAX_POOL_SIZE];static int pool_size;static rtx pool_vector_label;/* Add a constant to the pool and return its offset within the current   pool.   X is the rtx we want to replace. MODE is its mode.  On return,   ADDRESS_ONLY will be non-zero if we really want the address of such   a constant, not the constant itself.  */static HOST_WIDE_INTadd_constant (x, mode, address_only)     rtx x;     enum machine_mode mode;     int * address_only;{  int i;  HOST_WIDE_INT offset;  * address_only = 0;    if (mode == SImode && GET_CODE (x) == MEM && CONSTANT_P (XEXP (x, 0))      && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))    x = get_pool_constant (XEXP (x, 0));  else if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(x))    {      *address_only = 1;      mode = get_pool_mode (x);      x = get_pool_constant (x);    }#ifndef AOF_ASSEMBLER  else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == 3)    x = XVECEXP (x, 0, 0);#endif#ifdef AOF_ASSEMBLER  /* PIC Symbol references need to be converted into offsets into the      based area.  */  if (flag_pic && GET_CODE (x) == SYMBOL_REF)    x = aof_pic_entry (x);#endif /* AOF_ASSEMBLER */  /* First see if we've already got it */  for (i = 0; i < pool_size; i++)    {      if (GET_CODE (x) == pool_vector[i].value->code	  && mode == pool_vector[i].mode)	{	  if (GET_CODE (x) == CODE_LABEL)	    {	      if (XINT (x, 3) != XINT (pool_vector[i].value, 3))		continue;	    }	  if (rtx_equal_p (x, pool_vector[i].value))	    return pool_vector[i].next_offset - GET_MODE_SIZE (mode);	}    }  /* Need a new one */  pool_vector[pool_size].next_offset = GET_MODE_SIZE (mode);  offset = 0;  if (pool_size == 0)    pool_vector_label = gen_label_rtx ();  else    pool_vector[pool_size].next_offset      += (offset = pool_vector[pool_size - 1].next_offset);  pool_vector[pool_size].value = x;  pool_vector[pool_size].mode = mode;  pool_size++;  return offset;}/* Output the literal table */static voiddump_table (scan)     rtx scan;{  int i;  scan = emit_label_after (gen_label_rtx (), scan);  scan = emit_insn_after (gen_align_4 (), scan);  scan = emit_label_after (pool_vector_label, scan);  for (i = 0; i < pool_size; i++)    {      pool_node *p = pool_vector + i;      switch (GET_MODE_SIZE (p->mode))	{	case 4:	  scan = emit_insn_after (gen_consttable_4 (p->value), scan);	  break;	case 8:	  scan = emit_insn_after (gen_consttable_8 (p->value), scan);	  break;	default:	  abort ();	  break;	}    }  scan = emit_insn_after (gen_consttable_end (), scan);  scan = emit_barrier_after (scan);  pool_size = 0;}/* Non zero if the src operand needs to be fixed up */static intfixit (src, mode, destreg)     rtx src;     enum machine_mode mode;     int destreg;{  if (CONSTANT_P (src))    {      if (GET_CODE (src) == CONST_INT)	return (! const_ok_for_arm (INTVAL (src))		&& ! const_ok_for_arm (~INTVAL (src)));      if (GET_CODE (src) == CONST_DOUBLE)	return (GET_MODE (src) == VOIDmode		|| destreg < 16		|| (! const_double_rtx_ok_for_fpu (src)		    && ! neg_const_double_rtx_ok_for_fpu (src)));      return symbol_mentioned_p (src);    }#ifndef AOF_ASSEMBLER  else if (GET_CODE (src) == UNSPEC && XINT (src, 1) == 3)    return 1;#endif  else    return (mode == SImode && GET_CODE (src) == MEM	    && GET_CODE (XEXP (src, 0)) == SYMBOL_REF	    && CONSTANT_POOL_ADDRESS_P (XEXP (src, 0)));}/* Find the last barrier less than MAX_COUNT bytes from FROM, or create one. */static rtxfind_barrier (from, max_count)     rtx from;     int max_count;{  int count = 0;  rtx found_barrier = 0;  rtx last = from;  while (from && count < max_count)    {      rtx tmp;            if (GET_CODE (from) == BARRIER)	found_barrier = from;      /* Count the length of this insn */      if (GET_CODE (from) == INSN	  && GET_CODE (PATTERN (from)) == SET	  && CONSTANT_P (SET_SRC (PATTERN (from)))	  && CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from))))	count += 8;      /* Handle table jumps as a single entity.  */      else if (GET_CODE (from) == JUMP_INSN	       && JUMP_LABEL (from) != 0	       && ((tmp = next_real_insn (JUMP_LABEL (from)))		   == next_real_insn (from))	       && tmp != NULL	       && GET_CODE (tmp) == JUMP_INSN	       && (GET_CODE (PATTERN (tmp)) == ADDR_VEC		   || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))	{	  int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;	  count += (get_attr_length (from)		    + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));	  /* Continue after the dispatch table.  */	  last = from;	  from = NEXT_INSN (tmp);	  continue;	}      else	count += get_attr_length (from);      last = from;      from = NEXT_INSN (from);    }  if (! found_barrier)    {      /* We didn't find a barrier in time to	 dump our stuff, so we'll make one.  */      rtx label = gen_label_rtx ();            if (from)	from = PREV_INSN (last);      else	from = get_last_insn ();            /* Walk back to be just before any jump.  */      while (GET_CODE (from) == JUMP_INSN	     || GET_CODE (from) == NOTE	     || GET_CODE (from) == CODE_LABEL)	from = PREV_INSN (from);            from = emit_jump_insn_after (gen_jump (label), from);      JUMP_LABEL (from) = label;      found_barrier = emit_barrier_after (from);      emit_label_after (label, found_barrier);    }  return found_barrier;}/* Non zero if the insn is a move instruction which needs to be fixed. */static intbroken_move (insn)     rtx insn;{  if (!INSN_DELETED_P (insn)      && GET_CODE (insn) == INSN      && GET_CODE (PATTERN (insn)) == SET)    {      rtx pat = PATTERN (insn);      rtx src = SET_SRC (pat);      rtx dst = SET_DEST (pat);      int destreg;      enum machine_mode mode = GET_MODE (dst);      if (dst == pc_rtx)	return 0;      if (GET_CODE (dst) == REG)	destreg = REGNO (dst);      else if (GET_CODE (dst) == SUBREG && GET_CODE (SUBREG_REG (dst)) == REG)	destreg = REGNO (SUBREG_REG (dst));      else	return 0;      return fixit (src, mode, destreg);    }  return 0;}voidarm_reorg (first)     rtx first;{  rtx insn;  int count_size;#if 0  /* The ldr instruction can work with up to a 4k offset, and most constants     will be loaded with one of these instructions; however, the adr      instruction and the ldf instructions only work with a 1k offset.  This     code needs to be rewritten to use the 4k offset when possible, and to     adjust when a 1k offset is needed.  For now we just use a 1k offset     from the start.  */  count_size = 4000;  /* Floating point operands can't work further than 1024 bytes from the     PC, so to make things simple we restrict all loads for such functions.     */  if (TARGET_HARD_FLOAT)    {      int regno;      for (regno = 16; regno < 24; regno++)	if (regs_ever_live[regno])	  {	    count_size = 1000;	    break;	  }    }#else  count_size = 1000;#endif /* 0 */  for (insn = first; insn; insn = NEXT_INSN (insn))    {      if (broken_move (insn))	{	  /* This is a broken move instruction, scan ahead looking for	     a barrier to stick the constant table behind */	  rtx scan;	  rtx barrier = find_barrier (insn, count_size);	  /* Now find all the moves between the points and modify them */	  for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))	    {	      if (broken_move (scan))		{		  /* This is a broken move instruction, add it to the pool */		  rtx pat = PATTERN (scan);		  rtx src = SET_SRC (pat);		  rtx dst = SET_DEST (pat);		  enum machine_mode mode = GET_MODE (dst);		  HOST_WIDE_INT offset;		  rtx newinsn = scan;		  rtx newsrc;		  rtx addr;		  int scratch;		  int address_only;		  /* If this is an HImode constant load, convert it into		     an SImode constant load.  Since the register is always		     32 bits this is safe.  We have to do this, since the		     load pc-relative instruction only does a 32-bit load. */		  if (mode == HImode)		    {		      mode = SImode;		      if (GET_CODE (dst) != REG)			abort ();		      PUT_MODE (dst, SImode);		    }		  offset = add_constant (src, mode, &address_only);		  addr = plus_constant (gen_rtx_LABEL_REF (VOIDmode,							   pool_vector_label),					offset);		  /* If we only want the address of the pool entry, or		     for wide moves to integer regs we need to split		     the address calculation off into a separate insn.		     If necessary, the load can then be done with a		     load-multiple.  This is safe, since we have		     already noted the length of such insns to be 8,		     and we are immediately over-writing the scratch		     we have grabbed with the final result.  */		  if ((address_only || GET_MODE_SIZE (mode) > 4)		      && (scratch = REGNO (dst)) < 16)		    {		      rtx reg;		      if (mode == SImode)			reg = dst;		      else 			reg = gen_rtx_REG (SImode, scratch);		      newinsn = emit_insn_after (gen_movaddr (reg, addr),						 newinsn);		      addr = reg;		    }		  if (! address_only)		    {		      newsrc = gen_rtx_MEM (mode, addr);		      /* XXX Fixme -- I think the following is bogus.  */		      /* Build a jump insn wrapper around the move instead			 of an ordinary insn, because we want to have room for			 the target label rtx in fld[7], which an ordinary			 insn doesn't have. */		      newinsn			= emit_jump_insn_after (gen_rtx_SET (VOIDmode, dst,							     newsrc),						newinsn);		      JUMP_LABEL (newinsn) = pool_vector_label;		      /* But it's still an ordinary insn */		      PUT_CODE (newinsn, INSN);		    }		  /* Kill old insn */		  delete_insn (scan);		  scan = newinsn;		}	    }	  dump_table (barrier);	  insn = scan;	}    }  after_arm_reorg = 1;}/* Routines to output assembly language.  *//* If the rtx is the correct value then return the string of the number.   In this way we can ensure that valid double constants are generated even   when cross compiling. */char *fp_immediate_constant (x)     rtx x;{  REAL_VALUE_TYPE r;  int i;    if (!fpa_consts_inited)    init_fpa_table ();    REAL_VALUE_FROM_CONST_DOUBLE (r, x);  for (i = 0; i < 8; i++)    if (REAL_VALUES_EQUAL (r, values_fpa[i]))      return strings_fpa[i];  abort ();}/* As for fp_immediate_constant, but value is passed directly, not in rtx.  */static char *fp_const_from_val (r)     REAL_VALUE_TYPE *r;{  int i;  if (! fpa_consts_inited)    init_fpa_table ();  for (i = 0; i < 8; i++)    if (REAL_VALUES_EQUAL (*r, values_fpa[i]))      return strings_fpa[i];  abort ();}