if (s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) {
if (S3_ViRGE_GX2_SERIES(s3vPriv.chip) || S3_ViRGE_MX_SERIES(s3vPriv.chip)) {
S3VSave (save)vgaS3VPtr save;{int i;unsigned char cr3a, cr53, cr66;   /*    * This function will handle creating the data structure and filling    * in the generic VGA portion.    */   outb(vgaCRIndex, 0x66);   cr66 = inb(vgaCRReg);   outb(vgaCRReg, cr66 | 0x80);   outb(vgaCRIndex, 0x3a);   cr3a = inb(vgaCRReg);   outb(vgaCRReg, cr3a | 0x80);   outb(vgaCRIndex, 0x66);   cr66 = inb(vgaCRReg);   outb(vgaCRReg, cr66 | 0x80);   outb(vgaCRIndex, 0x3a);   cr3a = inb(vgaCRReg);   outb(vgaCRReg, cr3a | 0x80);   save = (vgaS3VPtr)vgaHWSave((vgaHWPtr)save, sizeof(vgaS3VRec));   outb(vgaCRIndex, 0x66);   outb(vgaCRReg, cr66);   outb(vgaCRIndex, 0x3a);                outb(vgaCRReg, cr3a);   outb(vgaCRIndex, 0x66);   outb(vgaCRReg, cr66);   outb(vgaCRIndex, 0x3a);                outb(vgaCRReg, cr3a);   /* First unlock extended sequencer regs */   outb(0x3c4, 0x08);   outb(0x3c5, 0x06);    /* Now we save all the s3 extended regs we need */   outb(vgaCRIndex, 0x31);                save->CR31 = inb(vgaCRReg);   outb(vgaCRIndex, 0x34);                save->CR34 = inb(vgaCRReg);   outb(vgaCRIndex, 0x36);                save->CR36 = inb(vgaCRReg);   outb(vgaCRIndex, 0x3a);                save->CR3A = inb(vgaCRReg);   outb(vgaCRIndex, 0x40);   save->CR40 = inb(vgaCRReg);   outb(vgaCRIndex, 0x42);   save->CR42 = inb(vgaCRReg);   outb(vgaCRIndex, 0x45);   save->CR45 = inb(vgaCRReg);   outb(vgaCRIndex, 0x51);                save->CR51 = inb(vgaCRReg);   outb(vgaCRIndex, 0x53);                save->CR53 = inb(vgaCRReg);   outb(vgaCRIndex, 0x54);                save->CR54 = inb(vgaCRReg);   outb(vgaCRIndex, 0x58);                save->CR58 = inb(vgaCRReg);   outb(vgaCRIndex, 0x63);   save->CR63 = inb(vgaCRReg);   outb(vgaCRIndex, 0x66);                save->CR66 = inb(vgaCRReg);   outb(vgaCRIndex, 0x67);                save->CR67 = inb(vgaCRReg);   outb(vgaCRIndex, 0x68);                save->CR68 = inb(vgaCRReg);   outb(vgaCRIndex, 0x69);   save->CR69 = inb(vgaCRReg);   outb(vgaCRIndex, 0x33);                save->CR33 = inb(vgaCRReg);   if (s3vPriv.chip == S3_ViRGE_DXGX) {      outb(vgaCRIndex, 0x86);      save->CR86 = inb(vgaCRReg);   }   if (s3vPriv.chip == S3_ViRGE_DXGX || s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) {      outb(vgaCRIndex, 0x90);      save->CR90 = inb(vgaCRReg);   }   /* Extended mode timings regs */   outb(vgaCRIndex, 0x3b);                save->CR3B = inb(vgaCRReg);   outb(vgaCRIndex, 0x3c);                save->CR3C = inb(vgaCRReg);   outb(vgaCRIndex, 0x43);                save->CR43 = inb(vgaCRReg);   outb(vgaCRIndex, 0x5d);                save->CR5D = inb(vgaCRReg);   outb(vgaCRIndex, 0x5e);   save->CR5E = inb(vgaCRReg);     outb(vgaCRIndex, 0x65);                save->CR65 = inb(vgaCRReg);   outb(vgaCRIndex, 0x6d);   save->CR6D = inb(vgaCRReg);   /* Save sequencer extended regs for DCLK PLL programming */   outb(0x3c4, 0x10);   save->SR10 = inb(0x3c5);   outb(0x3c4, 0x11);   save->SR11 = inb(0x3c5);   outb(0x3c4, 0x12);   save->SR12 = inb(0x3c5);   outb(0x3c4, 0x13);   save->SR13 = inb(0x3c5);   if (s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) {     outb(0x3c4, 0x29);     save->SR29 = inb(0x3c5);     outb(0x3c4, 0x54);     save->SR54 = inb(0x3c5);     outb(0x3c4, 0x55);     save->SR55 = inb(0x3c5);     outb(0x3c4, 0x56);     save->SR56 = inb(0x3c5);     outb(0x3c4, 0x57);     save->SR57 = inb(0x3c5);   }   outb(0x3c4, 0x15);   save->SR15 = inb(0x3c5);   outb(0x3c4, 0x18);   save->SR18 = inb(0x3c5);   /* And if streams is to be used, save that as well */      outb(vgaCRIndex, 0x53);   cr53 = inb(vgaCRReg);   outb(vgaCRReg, cr53 | 0x08);  /* Enable NEWMMIO to save MIU context */   outb(vgaCRIndex, 0x66);   cr66 = inb(vgaCRReg);   outb(vgaCRReg, cr66 | 0x80);   outb(vgaCRIndex, 0x3a);   cr3a = inb(vgaCRReg);   outb(vgaCRReg, cr3a | 0x80);   if(s3vPriv.NeedSTREAMS) {      S3VSaveSTREAMS(save->STREAMS);      }   /* Now save Memory Interface Unit registers, enable MMIO for this */   save->MMPR0 = ((mmtr)s3vMmioMem)->memport_regs.regs.fifo_control;   save->MMPR1 = ((mmtr)s3vMmioMem)->memport_regs.regs.miu_control;   save->MMPR2 = ((mmtr)s3vMmioMem)->memport_regs.regs.streams_timeout;   save->MMPR3 = ((mmtr)s3vMmioMem)->memport_regs.regs.misc_timeout;   if (xf86Verbose > 1) {      /* Debug */      ErrorF("MMPR regs: %08x %08x %08x %08x\n",         ((mmtr)s3vMmioMem)->memport_regs.regs.fifo_control,         ((mmtr)s3vMmioMem)->memport_regs.regs.miu_control,         ((mmtr)s3vMmioMem)->memport_regs.regs.streams_timeout,         ((mmtr)s3vMmioMem)->memport_regs.regs.misc_timeout );      ErrorF("\n\nViRGE driver: saved current video mode. Register dump:\n\n");   }   outb(vgaCRIndex, 0x53);   outb(vgaCRReg, cr53);   /* Restore CR53 to original for MMIO */   outb(vgaCRIndex, 0x3a);   outb(vgaCRReg, cr3a);   outb(vgaCRIndex, 0x66);   outb(vgaCRReg, cr66);   if (xf86Verbose > 1) S3VPrintRegs();   return ((void *) save);}