MGAG450SetPLLFreq(pScrn, f_out); return;
pReg->Clock = f_out; return;
MGAGSetPCLK( ScrnInfoPtr pScrn, long f_out ){	MGAPtr pMga = MGAPTR(pScrn);	MGARegPtr pReg = &pMga->ModeReg;	/* Pixel clock values */	int m, n, p, s;	/* The actual frequency output by the clock */	double f_pll;	if(MGAISGx50(pMga)) {		MGAG450SetPLLFreq(pScrn, f_out);		return;	}	/* Do the calculations for m, n, p and s */	f_pll = MGAGCalcClock( pScrn, f_out, &m, &n, &p, &s );	/* Values for the pixel clock PLL registers */	pReg->DacRegs[ MGA1064_PIX_PLLC_M ] = m & 0x1F;	pReg->DacRegs[ MGA1064_PIX_PLLC_N ] = n & 0x7F;	pReg->DacRegs[ MGA1064_PIX_PLLC_P ] = (p & 0x07) | ((s & 0x03) << 3);}