pdata->interruptPHY = MPC85xx_IRQ_EXT5; pdata->phyid = 4;  pdata->phy_reg_addr += binfo->bi_immr_base; memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
if (pdata) {  pdata->interruptPHY = MPC85xx_IRQ_EXT5; pdata->phyid = 4;  pdata->phy_reg_addr += binfo->bi_immr_base; memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); }
gp3_setup_arch(void){	bd_t *binfo = (bd_t *) __res;	unsigned int freq;	struct gianfar_platform_data *pdata;	cpm2_reset();	/* get the core frequency */	freq = binfo->bi_intfreq;	if (ppc_md.progress)		ppc_md.progress("gp3_setup_arch()", 0);	/* Set loops_per_jiffy to a half-way reasonable value,	   for use until calibrate_delay gets called. */	loops_per_jiffy = freq / HZ;#ifdef CONFIG_PCI	/* setup PCI host bridges */	mpc85xx_setup_hose();#endif	/* setup the board related information for the enet controllers */	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);/*	pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */	pdata->interruptPHY = MPC85xx_IRQ_EXT5;	pdata->phyid = 2;	pdata->phy_reg_addr += binfo->bi_immr_base;	memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);/*	pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */	pdata->interruptPHY = MPC85xx_IRQ_EXT5;	pdata->phyid = 4;	/* fixup phy address */	pdata->phy_reg_addr += binfo->bi_immr_base;	memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);#ifdef CONFIG_BLK_DEV_INITRD	if (initrd_start)		ROOT_DEV = Root_RAM0;	else#endif#ifdef	CONFIG_ROOT_NFS		ROOT_DEV = Root_NFS;#else		ROOT_DEV = Root_HDA1;#endif	printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base);}