* The Savage BIOS also writes to a debug card on port 80h.  It * shouldn't, but we can work around it here.
* The Savage BIOS writes to a debug card on port 80h and to the * timer chip at port 61.
S3SAVSetVESAMode( int n, int Refresh ){    struct LRMI_regs r;    /*      * The Savage BIOS also writes to a debug card on port 80h.  It      * shouldn't, but we can work around it here.     */    ioperm( 0x80, 1, 1 );    /* First, establish the refresh rate for this mode. */    memset(&r, 0, sizeof(r));    r.eax = 0x4f14;	/* S3 extensions */    r.ebx = 0x0001;	/* Set default refresh rate */    r.ecx = n;    r.edi = Refresh;    if( !LRMI_int(0x10, &r))    {	ErrorF("Can't set refresh rate.\n");    }    /* Now, make this mode current. */    /*     * The Savage BIOS reprograms the timer chip.  One could argue that     * these ports should be virtualized rather than laid wide open.     */    ioperm( 0x40, 4, 1 );    ioperm( 0x61, 1, 1 );    memset(&r, 0, sizeof(r));    r.eax = 0x4f02;    r.ebx = n;    if (!LRMI_int(0x10, &r))    {	ErrorF("Can't set video mode (vm86 failure)\n");    }    else if ((r.eax & 0xffff) != 0x4f)    {	ErrorF("Set video mode failed\n");    }    ioperm( 0x40, 4, 0 );    ioperm( 0x61, 1, 0 );    ioperm( 0x80, 1, 1 );}