void	*dec_550_intr_establish __P((void *, pci_intr_handle_t, int, int (*func)(void *), void *, char *)); void	dec_550_intr_disestablish(void *, void *);  void	*dec_550_pciide_compat_intr_establish __P((void *, struct device *, struct pci_attach_args *, int, int (*)(void *), void *)); void    dec_550_pciide_compat_intr_disestablish(void *, void *);  #define	DEC_550_PCI_IRQ_BEGIN	8 #define	DEC_550_MAX_IRQ		(64 - DEC_550_PCI_IRQ_BEGIN)   #define	PCI_STRAY_MAX		0   #define	DEC_550_LINE_IS_ISA(line)	((line) >= 0xe0 && (line) <= 0xef) #define	DEC_550_LINE_ISA_IRQ(line)	((line) & 0x0f)  struct alpha_shared_intr *dec_550_pci_intr;  void	dec_550_iointr(void *framep, unsigned long vec); void	dec_550_intr_enable(int irq); void	dec_550_intr_disable(int irq);  void pci_550_pickintr(ccp) struct cia_config *ccp; { bus_space_tag_t iot = &ccp->cc_iot; pci_chipset_tag_t pc = &ccp->cc_pc; #if 0 char *cp; #endif int i;  pc->pc_intr_v = ccp; pc->pc_intr_map = dec_550_intr_map; pc->pc_intr_string = dec_550_intr_string; pc->pc_intr_line = dec_550_intr_line; #if 0 pc->pc_intr_evcnt = dec_550_intr_evcnt; #endif pc->pc_intr_establish = dec_550_intr_establish; pc->pc_intr_disestablish = dec_550_intr_disestablish;  pc->pc_pciide_compat_intr_establish = dec_550_pciide_compat_intr_establish; pc->pc_pciide_compat_intr_disestablish = dec_550_pciide_compat_intr_disestablish;    for (i = 0; i < DEC_550_MAX_IRQ; i++) dec_550_intr_disable(i);  dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ); for (i = 0; i < DEC_550_MAX_IRQ; i++) { alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i, PCI_STRAY_MAX); alpha_shared_intr_set_private(dec_550_pci_intr, i, ccp); #if 0 cp = alpha_shared_intr_string(dec_550_pci_intr, i); sprintf(cp, "irq %d", i); evcnt_attach_dynamic(alpha_shared_intr_evcnt( dec_550_pci_intr, i), EVCNT_TYPE_INTR, NULL, "dec_550", cp); #endif }  #if NSIO sio_intr_setup(pc, iot); #endif  set_iointr(dec_550_iointr); }  int dec_550_intr_map(ccv, bustag, buspin, line, ihp) void *ccv; pcitag_t bustag; int buspin, line; pci_intr_handle_t *ihp; { struct cia_config *ccp = ccv; pci_chipset_tag_t pc = &ccp->cc_pc; int bus, device, function;  if (buspin == 0) {  return 1; } if (buspin > 4) { printf("dec_550_intr_map: bad interrupt pin %d\n", buspin); return 1; }  alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function);   if (bus == 0) { if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {  if (device == 7) panic("dec_550_intr_map: SIO device"); else if (device == 4) return (1); } else {  if (device == 7) { if (function == 0) panic("dec_550_intr_map: SIO device"); if (function == 1 || function == 2) return (1); } } }   if (line == 0xff) { printf("dec_550_intr_map: no mapping for %d/%d/%d\n", bus, device, function); return (1); }  #if NSIO == 0 if (DEC_550_LINE_IS_ISA(line)) { printf("dec_550_intr_map: ISA IRQ %d for %d/%d/%d\n", DEC_550_LINE_ISA_IRQ(line), bus, device, function); return (1); } #endif  if (DEC_550_LINE_IS_ISA(line) == 0 && line >= DEC_550_MAX_IRQ) panic("dec_550_intr_map: dec 550 irq too large (%d)\n", line);  *ihp = line; return (0); }  const char * dec_550_intr_string(ccv, ih) void *ccv; pci_intr_handle_t ih; { #if 0 struct cia_config *ccp = ccv; #endif static char irqstr[16];		  #if NSIO if (DEC_550_LINE_IS_ISA(ih)) return (sio_intr_string(NULL , DEC_550_LINE_ISA_IRQ(ih))); #endif  if (ih >= DEC_550_MAX_IRQ) panic("dec_550_intr_string: bogus 550 IRQ 0x%lx\n", ih); sprintf(irqstr, "dec 550 irq %ld", ih); return (irqstr); }  int dec_550_intr_line(ccv, ih) void *ccv; pci_intr_handle_t ih; { #if NSIO if (DEC_550_LINE_IS_ISA(ih)) return (sio_intr_line(NULL , DEC_550_LINE_ISA_IRQ(ih))); #endif  return (ih); }  #if 0 const struct evcnt * dec_550_intr_evcnt(ccv, ih) void *ccv; pci_intr_handle_t ih; { #if 0 struct cia_config *ccp = ccv; #endif  #if NSIO if (DEC_550_LINE_IS_ISA(ih)) return (sio_intr_evcnt(NULL , DEC_550_LINE_ISA_IRQ(ih))); #endif  if (ih >= DEC_550_MAX_IRQ) panic("dec_550_intr_evcnt: bogus 550 IRQ 0x%lx\n", ih);  return (alpha_shared_intr_evcnt(dec_550_pci_intr, ih)); } #endif  void *
void	*dec_550_intr_establish __P((void *, pci_intr_handle_t,	    int, int (*func)(void *), void *, char *));void	dec_550_intr_disestablish(void *, void *);void	*dec_550_pciide_compat_intr_establish __P((void *, struct device *,	    struct pci_attach_args *, int, int (*)(void *), void *));void    dec_550_pciide_compat_intr_disestablish(void *, void *);#define	DEC_550_PCI_IRQ_BEGIN	8#define	DEC_550_MAX_IRQ		(64 - DEC_550_PCI_IRQ_BEGIN)/* * The Miata has a Pyxis, which seems to have problems with stray * interrupts.  Work around this by just ignoring strays. */#define	PCI_STRAY_MAX		0/* * Some Miata models, notably models with a Cypress PCI-ISA bridge, have * a PCI device (the OHCI USB controller) with interrupts tied to ISA IRQ * lines.  This IRQ is encoded as: * *	line = 0xe0 | isa_irq; */#define	DEC_550_LINE_IS_ISA(line)	((line) >= 0xe0 && (line) <= 0xef)#define	DEC_550_LINE_ISA_IRQ(line)	((line) & 0x0f)struct alpha_shared_intr *dec_550_pci_intr;void	dec_550_iointr(void *framep, unsigned long vec);void	dec_550_intr_enable(int irq);void	dec_550_intr_disable(int irq);voidpci_550_pickintr(ccp)	struct cia_config *ccp;{	bus_space_tag_t iot = &ccp->cc_iot;	pci_chipset_tag_t pc = &ccp->cc_pc;#if 0	char *cp;#endif	int i;        pc->pc_intr_v = ccp;        pc->pc_intr_map = dec_550_intr_map;        pc->pc_intr_string = dec_550_intr_string;        pc->pc_intr_line = dec_550_intr_line;#if 0	pc->pc_intr_evcnt = dec_550_intr_evcnt;#endif        pc->pc_intr_establish = dec_550_intr_establish;        pc->pc_intr_disestablish = dec_550_intr_disestablish;	pc->pc_pciide_compat_intr_establish =	    dec_550_pciide_compat_intr_establish;	pc->pc_pciide_compat_intr_disestablish =	    dec_550_pciide_compat_intr_disestablish;	/*	 * DEC 550's interrupts are enabled via the Pyxis interrupt	 * mask register.  Nothing to map.	 */	for (i = 0; i < DEC_550_MAX_IRQ; i++)		dec_550_intr_disable(i);	dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ);	for (i = 0; i < DEC_550_MAX_IRQ; i++) {		alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i,		    PCI_STRAY_MAX);		alpha_shared_intr_set_private(dec_550_pci_intr, i, ccp);#if 0				cp = alpha_shared_intr_string(dec_550_pci_intr, i);		sprintf(cp, "irq %d", i);		evcnt_attach_dynamic(alpha_shared_intr_evcnt(		    dec_550_pci_intr, i), EVCNT_TYPE_INTR, NULL,		    "dec_550", cp);#endif	}#if NSIO	sio_intr_setup(pc, iot);#endif	set_iointr(dec_550_iointr);}int     dec_550_intr_map(ccv, bustag, buspin, line, ihp)        void *ccv;        pcitag_t bustag;         int buspin, line;        pci_intr_handle_t *ihp;{	struct cia_config *ccp = ccv;	pci_chipset_tag_t pc = &ccp->cc_pc;	int bus, device, function;	if (buspin == 0) {		/* No IRQ used. */		return 1;	}	if (buspin > 4) {		printf("dec_550_intr_map: bad interrupt pin %d\n", buspin);		return 1;	}	alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function);	/*	 * There are two main variants of Miata: Miata 1 (Intel SIO)	 * and Miata {1.5,2} (Cypress).	 *	 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at	 * device 4 of bus 0.  This variant apparently also has the	 * Pyxis DMA bug.	 *	 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives	 * on device 7 of bus 0.  This device has PCI IDE wired to	 * compatibility mode on functions 1 and 2.	 *	 * There will be no interrupt mapping for these devices, so just	 * bail out now.	 */	if (bus == 0) {		if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {			/* Miata 1 */			if (device == 7)				panic("dec_550_intr_map: SIO device");			else if (device == 4)				return (1);		} else {			/* Miata 1.5 or Miata 2 */			if (device == 7) {				if (function == 0)					panic("dec_550_intr_map: SIO device");				if (function == 1 || function == 2)					return (1);			}		}	}	/*	 * The console places the interrupt mapping in the "line" value.	 * A value of (char)-1 indicates there is no mapping.	 */	if (line == 0xff) {		printf("dec_550_intr_map: no mapping for %d/%d/%d\n",		    bus, device, function);		return (1);	}#if NSIO == 0	if (DEC_550_LINE_IS_ISA(line)) {		printf("dec_550_intr_map: ISA IRQ %d for %d/%d/%d\n",		    DEC_550_LINE_ISA_IRQ(line), bus, device, function);		return (1);	}#endif	if (DEC_550_LINE_IS_ISA(line) == 0 && line >= DEC_550_MAX_IRQ)		panic("dec_550_intr_map: dec 550 irq too large (%d)\n",		    line);	*ihp = line;	return (0);}const char *dec_550_intr_string(ccv, ih)	void *ccv;	pci_intr_handle_t ih;{#if 0	struct cia_config *ccp = ccv;#endif	static char irqstr[16];		/* 12 + 2 + NULL + sanity */#if NSIO	if (DEC_550_LINE_IS_ISA(ih))		return (sio_intr_string(NULL /*XXX*/,		    DEC_550_LINE_ISA_IRQ(ih)));#endif	if (ih >= DEC_550_MAX_IRQ)		panic("dec_550_intr_string: bogus 550 IRQ 0x%lx\n", ih);	sprintf(irqstr, "dec 550 irq %ld", ih);	return (irqstr);}intdec_550_intr_line(ccv, ih)	void *ccv;	pci_intr_handle_t ih;{#if NSIO	if (DEC_550_LINE_IS_ISA(ih))		return (sio_intr_line(NULL /*XXX*/, DEC_550_LINE_ISA_IRQ(ih)));#endif	return (ih);}#if 0const struct evcnt *dec_550_intr_evcnt(ccv, ih)	void *ccv;	pci_intr_handle_t ih;{#if 0	struct cia_config *ccp = ccv;#endif#if NSIO	if (DEC_550_LINE_IS_ISA(ih))		return (sio_intr_evcnt(NULL /*XXX*/,		    DEC_550_LINE_ISA_IRQ(ih)));#endif	if (ih >= DEC_550_MAX_IRQ)		panic("dec_550_intr_evcnt: bogus 550 IRQ 0x%lx\n", ih);	return (alpha_shared_intr_evcnt(dec_550_pci_intr, ih));}#endifvoid *dec_550_intr_establish(ccv, ih, level, func, arg, name)	void *ccv, *arg;	pci_intr_handle_t ih;	int level;	int (*func)(void *);	char *name;{#if 0	struct cia_config *ccp = ccv;#endif	void *cookie;#if NSIO	if (DEC_550_LINE_IS_ISA(ih))		return (sio_intr_establish(NULL /*XXX*/,		    DEC_550_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg,		    name));#endif	if (ih >= DEC_550_MAX_IRQ)		panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%lx\n", ih);	cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL,	    level, func, arg, name);	if (cookie != NULL && alpha_shared_intr_isactive(dec_550_pci_intr, ih))		dec_550_intr_enable(ih);	return (cookie);}