REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
bnx2_fw_sync(struct bnx2 *bp, u32 msg_data){	int i;	u32 val;	if (bp->fw_timed_out)		return -EBUSY;	bp->fw_wr_seq++;	msg_data |= bp->fw_wr_seq;	REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);	/* wait for an acknowledgement. */	for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {		udelay(5);		val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);		if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))			break;	}	/* If we timed out, inform the firmware that this is the case. */	if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&		((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {		msg_data &= ~BNX2_DRV_MSG_CODE;		msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;		REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);		bp->fw_timed_out = 1;		return -EBUSY;	}	return 0;}