PMC_Write(INTR_EN_0,PMC_Def(INTR_EN_0_INTA,HARDWARE));
static void ClearAndEnableInterrupts(void){  PGRAPH_Write(INTR_0,PGRAPH_Def(INTR_0_RESERVED,RESET)|                      PGRAPH_Def(INTR_0_CONTEXT_SWITCH,RESET)|                      PGRAPH_Def(INTR_0_VBLANK,RESET)|                      PGRAPH_Def(INTR_0_RANGE,RESET)|                      PGRAPH_Def(INTR_0_METHOD_COUNT,RESET)|                      PGRAPH_Def(INTR_0_FORMAT,RESET)|                      PGRAPH_Def(INTR_0_COMPLEX_CLIP,RESET)|                      PGRAPH_Def(INTR_0_NOTIFY,RESET));      PGRAPH_Write(INTR_EN_0,0xffffffff);  PGRAPH_Write(INTR_1,PGRAPH_Def(INTR_1_METHOD,RESET)|                      PGRAPH_Def(INTR_1_DATA,RESET)|                      PGRAPH_Def(INTR_1_DOUBLE_NOTIFY,RESET)|                      PGRAPH_Def(INTR_1_CTXSW_NOTIFY,RESET));  /* Don't care about any of this lot */  PGRAPH_Write(INTR_EN_1,0xffffffff);  PGRAPH_Write(DMA_INTR_0,0xffffffff);  PGRAPH_Write(DMA_INTR_EN_0,0xffffffff);    /* Reset the FIFO interrupt state */  PFIFO_Write(INTR_0, PFIFO_Def(INTR_0_CACHE_ERROR,RESET)|                      PFIFO_Def(INTR_0_RUNOUT,RESET)|                      PFIFO_Def(INTR_0_RUNOUT_OVERFLOW,RESET)|                      PFIFO_Def(INTR_0_DMA_PUSHER,RESET)|                      PFIFO_Def(INTR_0_DMA_PTE,RESET));  PFIFO_Write(INTR_EN_0, PFIFO_Def(INTR_EN_0_CACHE_ERROR,ENABLED)|                         PFIFO_Def(INTR_EN_0_RUNOUT,ENABLED)|                         PFIFO_Def(INTR_EN_0_RUNOUT_OVERFLOW,ENABLED));  /* Switch on all the user devices in the master control */  PMC_Write(ENABLE,0xffffffff);  PMC_Write(INTR_EN_0,PMC_Def(INTR_EN_0_INTA,HARDWARE));}