pdata->interruptPHY = MPC83xx_IRQ_EXT2; pdata->phyid = 1;  pdata->phy_reg_addr += binfo->bi_immr_base;
pdata->bus_id = GFAR_PHY_1;
mpc834x_sys_setup_arch(void){	bd_t *binfo = (bd_t *) __res;	unsigned int freq;	struct gianfar_platform_data *pdata;	/* get the core frequency */	freq = binfo->bi_intfreq;	/* Set loops_per_jiffy to a half-way reasonable value,	   for use until calibrate_delay gets called. */	loops_per_jiffy = freq / HZ;#ifdef CONFIG_PCI	/* setup PCI host bridges */	mpc83xx_setup_hose();#endif	mpc83xx_early_serial_map();	/* setup the board related information for the enet controllers */	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1);	if (pdata) {		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;		pdata->interruptPHY = MPC83xx_IRQ_EXT1;		pdata->phyid = 0;		/* fixup phy address */		pdata->phy_reg_addr += binfo->bi_immr_base;		memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);	}	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2);	if (pdata) {		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;		pdata->interruptPHY = MPC83xx_IRQ_EXT2;		pdata->phyid = 1;		/* fixup phy address */		pdata->phy_reg_addr += binfo->bi_immr_base;		memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);	}#ifdef CONFIG_BLK_DEV_INITRD	if (initrd_start)		ROOT_DEV = Root_RAM0;	else#endif#ifdef  CONFIG_ROOT_NFS		ROOT_DEV = Root_NFS;#else		ROOT_DEV = Root_HDA1;#endif}