case PCI_CHIP_ViRGE_MXP:
Bool Probe_S3(Chipset)int *Chipset;{	Bool result = FALSE;	Byte chip, cr38, cr39, cr42, tmp, rev;	int i = 0;	struct pci_config_reg *pcrp2;	if (!NoPCI)	{	    while ((pcrp = pci_devp[i]) != (struct pci_config_reg *)NULL) {		if (pcrp->_vendor == PCI_VENDOR_S3)		{ 		        Ports[0] = CRTC_IDX;			Ports[1] = CRTC_REG;			EnableIOPorts(NUMPORTS, Ports);			cr38 = rdinx(CRTC_IDX, 0x38);			cr39 = rdinx(CRTC_IDX, 0x39);			wrinx(CRTC_IDX, 0x38, 0x48);			wrinx(CRTC_IDX, 0x39, 0xa5);			switch (pcrp->_device)			{			case PCI_CHIP_TRIO:#if 1  /* can only be distinguished using port probing... */			        PCIProbed = FALSE;#else			        PCIProbed = TRUE;				*Chipset = CHIP_S3_Trio32; 				*Chipset = CHIP_S3_Trio64V; 				*Chipset = CHIP_S3_Trio64; #endif				break;			case PCI_CHIP_868:			        PCIProbed = TRUE;				*Chipset = CHIP_S3_868;				break;			case PCI_CHIP_928:			        PCIProbed = TRUE;				*Chipset = CHIP_S3_928P;				break;			case PCI_CHIP_864_0:			case PCI_CHIP_864_1:			        PCIProbed = TRUE;				*Chipset = CHIP_S3_864;				break;			case PCI_CHIP_964_0:			case PCI_CHIP_964_1:			        PCIProbed = TRUE;				*Chipset = CHIP_S3_964;				break;			case PCI_CHIP_968:			        PCIProbed = TRUE;				*Chipset = CHIP_S3_968;				/* probe for 3Dlabs chip in same PCI slot for ELSA Gloria */				cr42 = rdinx(CRTC_IDX, 0x42);				wrinx(CRTC_IDX, 0x42, cr42 | 0x08);				xf86scanpci();				if ((pcrp2 = pci_devp[i]) != (struct pci_config_reg *)NULL) {				   if (pcrp2->_vendor == PCI_VENDOR_3DLABS) {				      switch (pcrp2->_device) {				      case PCI_CHIP_3DLABS_300SX:					 *Chipset = CHIP_S3_968_3DLABS_300SX;					 break;				      default:					 *Chipset = CHIP_S3_968_3DLABS_UNK;					 break;				      }				   }				}				      				xf86scanpci();				break;			case PCI_CHIP_ViRGE:			        PCIProbed = TRUE;				*Chipset = CHIP_S3_ViRGE;				/*				 * the ViRGE is used as VGA part for				 * the GLINT				 */				S3_Descriptor.check_coproc = TRUE;				break;			case PCI_CHIP_ViRGE_DXGX:			        PCIProbed = TRUE;				if (rdinx(CRTC_IDX, 0x6f) & 1)				   *Chipset = CHIP_S3_ViRGE_GX;				else				   *Chipset = CHIP_S3_ViRGE_DX;				break;			case PCI_CHIP_ViRGE_GX2:			        PCIProbed = TRUE;				*Chipset = CHIP_S3_ViRGE_GX2;				break;			case PCI_CHIP_ViRGE_MX:			        PCIProbed = TRUE;				*Chipset = CHIP_S3_ViRGE_MX;				break;			case PCI_CHIP_ViRGE_VX:			        PCIProbed = TRUE;				*Chipset = CHIP_S3_ViRGE_VX;				break;			case PCI_CHIP_AURORA64VP:			        PCIProbed = TRUE;				*Chipset = CHIP_S3_Aurora64VP;				break;			case PCI_CHIP_TRIO64UVP:			        PCIProbed = TRUE;				*Chipset = CHIP_S3_Trio64UVP;				break;			case PCI_CHIP_TRIO64V2_DXGX:			        PCIProbed = TRUE;				if (rdinx(CRTC_IDX, 0x6f) & 1)				   *Chipset = CHIP_S3_Trio64V2_GX;				else				   *Chipset = CHIP_S3_Trio64V2_DX;				break;#if 0  /* use port probing then... */			default:			        PCIProbed = TRUE;				Chip_data = chip;				*Chipset = CHIP_S3_UNKNOWN;				break;#endif			}			wrinx(CRTC_IDX, 0x39, cr39);			wrinx(CRTC_IDX, 0x38, cr38);			DisableIOPorts(NUMPORTS, Ports);			if (PCIProbed)			   return(TRUE);		}		i++;	    }	}	/* Add CRTC to enabled ports */	Ports[0] = CRTC_IDX;	Ports[1] = CRTC_REG;	EnableIOPorts(NUMPORTS, Ports);	cr38 = rdinx(CRTC_IDX, 0x38);	cr39 = rdinx(CRTC_IDX, 0x39);	wrinx(CRTC_IDX, 0x38, 0x00);	if (!testinx2(CRTC_IDX, 0x35, 0x0F))	{		wrinx(CRTC_IDX, 0x38, 0x48);		if (testinx2(CRTC_IDX, 0x35, 0x0F))		{			result = TRUE;			wrinx(CRTC_IDX, 0x39, 0xa5);			rev = rdinx(CRTC_IDX, 0x30);			switch (rev & 0xF0)			{			case 0x80:				switch (rev & 0x0F)				{				case 0x01:					*Chipset = CHIP_S3_911;					break;				case 0x02:					*Chipset = CHIP_S3_924;					break;				default:					Chip_data = rev;					*Chipset = CHIP_S3_UNKNOWN;					break;				}				break;			case 0xA0:				tmp = rdinx(CRTC_IDX, 0x36);				switch (tmp & 0x03)				{				case 0x00:				case 0x01:					/* EISA or VLB - 805 */					switch (rev & 0x0F)					{					case 0x00:						*Chipset = CHIP_S3_805B;						break;					case 0x01:						Chip_data = rev;						*Chipset = CHIP_S3_UNKNOWN;						break;					case 0x02:					case 0x03:					case 0x04:						*Chipset = CHIP_S3_805C;						break;					case 0x05:						*Chipset = CHIP_S3_805D;						break;					case 0x08:						*Chipset = CHIP_S3_805I;						break;					default:						/* Call >0x05 D step for now */						*Chipset = CHIP_S3_805D;						break;					}					break;				case 0x03:					/* ISA - 801 */					switch (rev & 0x0F)					{					case 0x00:						*Chipset = CHIP_S3_801B;						break;					case 0x01:						Chip_data = rev;						*Chipset = CHIP_S3_UNKNOWN;						break;					case 0x02:					case 0x03:					case 0x04:						*Chipset = CHIP_S3_801C;						break;					case 0x05:						*Chipset = CHIP_S3_801D;						break;					case 0x08:						*Chipset = CHIP_S3_801I;						break;					default:						/* Call >0x05 D step for now */						*Chipset = CHIP_S3_801D;						break;					}					break;				default:					Chip_data = rev;					*Chipset = CHIP_S3_UNKNOWN;					break;				}				break;			case 0x90:				switch (rev & 0x0F)				{				case 0x00:				case 0x01:					/*					 * Contradictory documentation -					 * one says 0, the other says 1.					 */					*Chipset = CHIP_S3_928D;					break;				case 0x02:				case 0x03:					Chip_data = rev;					*Chipset = CHIP_S3_UNKNOWN;					break;				case 0x04:				case 0x05:					*Chipset = CHIP_S3_928E;					break;				default:					/* Call >0x05 E step for now */					*Chipset = CHIP_S3_928E;				}				break;			case 0xB0:				/*				 * Don't know anything more about this				 * just yet.				 */				*Chipset = CHIP_S3_928P;				break;			case 0xC0:				*Chipset = CHIP_S3_864;				break;			case 0xD0:				*Chipset = CHIP_S3_964;				break;			case 0xE0: {			   int chip_id, chip_rev;			   chip_id  = rdinx(CRTC_IDX, 0x2d) << 8;			   chip_id |= rdinx(CRTC_IDX, 0x2e);			   chip_rev = rdinx(CRTC_IDX, 0x2f);			   switch (chip_id) {			   case 0x8880:			      *Chipset = CHIP_S3_866;			      break;			   case 0x8890:			      *Chipset = CHIP_S3_868;			      break;			   case 0x8810: 			      *Chipset = CHIP_S3_Trio32;			      break;			   case PCI_CHIP_TRIO:			      if ((chip_rev&0x40)  ==  0x40)				 *Chipset = CHIP_S3_Trio64V;			      else				 *Chipset = CHIP_S3_Trio64;			      break;			   case PCI_CHIP_TRIO64V2_DXGX:			      if (rdinx(CRTC_IDX, 0x6f) & 1)				 *Chipset = CHIP_S3_Trio64V2_GX;			      else				 *Chipset = CHIP_S3_Trio64V2_DX;			      break;			   case PCI_CHIP_ViRGE_DXGX:			      if (rdinx(CRTC_IDX, 0x6f) & 1)				 *Chipset = CHIP_S3_ViRGE_GX;			      else				 *Chipset = CHIP_S3_ViRGE_DX;			      break;			   case PCI_CHIP_968:			   case PCI_CHIP_AURORA64VP:			   case PCI_CHIP_ViRGE:			   case PCI_CHIP_ViRGE_VX:			   case PCI_CHIP_PLATO_PX: 			   case PCI_CHIP_ViRGE_GX2:			   case PCI_CHIP_ViRGE_MX:			      *Chipset = chip_id;			      break;			   default:			     Chip_data = rev;			     Chip_data = (Chip_data << 16) | chip_id;			     Chip_data = (Chip_data <<  8) | chip_rev;			     *Chipset = CHIP_S3_UNKNOWN;			   }			   break;				 			}			default:				Chip_data = rev;				*Chipset = CHIP_S3_UNKNOWN;				break;			}		}	}	wrinx(CRTC_IDX, 0x39, cr39);	wrinx(CRTC_IDX, 0x38, cr38);	DisableIOPorts(NUMPORTS, Ports);	return(result);}