for (addr = CX2_SHARED_LOWER_BOUND; addr < CX2_REGISTER_DOMAIN1_END; addr += 4) {
for (addr = IPW_SHARED_LOWER_BOUND; addr < IPW_REGISTER_DOMAIN1_END; addr += 4) {
static int ipw_load_ucode(struct ipw_priv *priv, u8 * data, size_t len){	int rc = 0, i, addr;	u8 cr = 0;	u16 *image;	image = (u16 *) data;	IPW_DEBUG_TRACE(">> \n");	rc = ipw_stop_master(priv);	if (rc < 0)		return rc;//      spin_lock_irqsave(&priv->lock, flags);	for (addr = CX2_SHARED_LOWER_BOUND;	     addr < CX2_REGISTER_DOMAIN1_END; addr += 4) {		ipw_write32(priv, addr, 0);	}	/* no ucode (yet) */	memset(&priv->dino_alive, 0, sizeof(priv->dino_alive));	/* destroy DMA queues */	/* reset sequence */	ipw_write_reg32(priv, CX2_MEM_HALT_AND_RESET, CX2_BIT_HALT_RESET_ON);	ipw_arc_release(priv);	ipw_write_reg32(priv, CX2_MEM_HALT_AND_RESET, CX2_BIT_HALT_RESET_OFF);	mdelay(1);	/* reset PHY */	ipw_write_reg32(priv, CX2_INTERNAL_CMD_EVENT, CX2_BASEBAND_POWER_DOWN);	mdelay(1);	ipw_write_reg32(priv, CX2_INTERNAL_CMD_EVENT, 0);	mdelay(1);	/* enable ucode store */	ipw_write_reg8(priv, DINO_CONTROL_REG, 0x0);	ipw_write_reg8(priv, DINO_CONTROL_REG, DINO_ENABLE_CS);	mdelay(1);	/* write ucode */	/**	 * @bug	 * Do NOT set indirect address register once and then	 * store data to indirect data register in the loop.	 * It seems very reasonable, but in this case DINO do not	 * accept ucode. It is essential to set address each time.	 */	/* load new ipw uCode */	for (i = 0; i < len / 2; i++)		ipw_write_reg16(priv, CX2_BASEBAND_CONTROL_STORE,				cpu_to_le16(image[i]));	/* enable DINO */	ipw_write_reg8(priv, CX2_BASEBAND_CONTROL_STATUS, 0);	ipw_write_reg8(priv, CX2_BASEBAND_CONTROL_STATUS, DINO_ENABLE_SYSTEM);	/* this is where the igx / win driver deveates from the VAP driver. */	/* wait for alive response */	for (i = 0; i < 100; i++) {		/* poll for incoming data */		cr = ipw_read_reg8(priv, CX2_BASEBAND_CONTROL_STATUS);		if (cr & DINO_RXFIFO_DATA)			break;		mdelay(1);	}	if (cr & DINO_RXFIFO_DATA) {		/* alive_command_responce size is NOT multiple of 4 */		u32 response_buffer[(sizeof(priv->dino_alive) + 3) / 4];		for (i = 0; i < ARRAY_SIZE(response_buffer); i++)			response_buffer[i] =			    le32_to_cpu(ipw_read_reg32(priv,						       CX2_BASEBAND_RX_FIFO_READ));		memcpy(&priv->dino_alive, response_buffer,		       sizeof(priv->dino_alive));		if (priv->dino_alive.alive_command == 1		    && priv->dino_alive.ucode_valid == 1) {			rc = 0;			IPW_DEBUG_INFO			    ("Microcode OK, rev. %d (0x%x) dev. %d (0x%x) "			     "of %02d/%02d/%02d %02d:%02d\n",			     priv->dino_alive.software_revision,			     priv->dino_alive.software_revision,			     priv->dino_alive.device_identifier,			     priv->dino_alive.device_identifier,			     priv->dino_alive.time_stamp[0],			     priv->dino_alive.time_stamp[1],			     priv->dino_alive.time_stamp[2],			     priv->dino_alive.time_stamp[3],			     priv->dino_alive.time_stamp[4]);		} else {			IPW_DEBUG_INFO("Microcode is not alive\n");			rc = -EINVAL;		}	} else {		IPW_DEBUG_INFO("No alive response from DINO\n");		rc = -ETIME;	}	/* disable DINO, otherwise for some reason	   firmware have problem getting alive resp. */	ipw_write_reg8(priv, CX2_BASEBAND_CONTROL_STATUS, 0);//      spin_unlock_irqrestore(&priv->lock, flags);	return rc;}