if (is_hpet_enabled()){
if (is_hpet_enabled() && hpet_use_timer) {
static int __init init_tsc(char* override){	/* check clock override */	if (override[0] && strncmp(override,"tsc",3)) {#ifdef CONFIG_HPET_TIMER		if (is_hpet_enabled()) {			printk(KERN_ERR "Warning: clock= override failed. Defaulting to tsc\n");		} else#endif		{			return -ENODEV;		}	}	/*	 * If we have APM enabled or the CPU clock speed is variable	 * (CPU stops clock on HLT or slows clock to save power)	 * then the TSC timestamps may diverge by up to 1 jiffy from	 * 'real time' but nothing will break.	 * The most frequent case is that the CPU is "woken" from a halt	 * state by the timer interrupt itself, so we get 0 error. In the	 * rare cases where a driver would "wake" the CPU and request a	 * timestamp, the maximum error is < 1 jiffy. But timestamps are	 * still perfectly ordered.	 * Note that the TSC counter will be reset if APM suspends	 * to disk; this won't break the kernel, though, 'cuz we're	 * smart.  See arch/i386/kernel/apm.c.	 */ 	/* 	 *	Firstly we have to do a CPU check for chips with 	 * 	a potentially buggy TSC. At this point we haven't run 	 *	the ident/bugs checks so we must run this hook as it 	 *	may turn off the TSC flag. 	 * 	 *	NOTE: this doesn't yet handle SMP 486 machines where only 	 *	some CPU's have a TSC. Thats never worked and nobody has 	 *	moaned if you have the only one in the world - you fix it! 	 */	count2 = LATCH; /* initialize counter for mark_offset_tsc() */	if (cpu_has_tsc) {		unsigned long tsc_quotient;#ifdef CONFIG_HPET_TIMER		if (is_hpet_enabled()){			unsigned long result, remain;			printk("Using TSC for gettimeofday\n");			tsc_quotient = calibrate_tsc_hpet(NULL);			timer_tsc.mark_offset = &mark_offset_tsc_hpet;			/*			 * Math to calculate hpet to usec multiplier			 * Look for the comments at get_offset_tsc_hpet()			 */			ASM_DIV64_REG(result, remain, hpet_tick,					0, KERNEL_TICK_USEC);			if (remain > (hpet_tick >> 1))				result++; /* rounding the result */			hpet_usec_quotient = result;		} else#endif		{			tsc_quotient = calibrate_tsc();		}		if (tsc_quotient) {			fast_gettimeoffset_quotient = tsc_quotient;			use_tsc = 1;			/*			 *	We could be more selective here I suspect			 *	and just enable this for the next intel chips ?			 */			/* report CPU clock rate in Hz.			 * The formula is (10^6 * 2^32) / (2^32 * 1 / (clocks/us)) =			 * clock/second. Our precision is about 100 ppm.			 */			{	unsigned long eax=0, edx=1000;				__asm__("divl %2"		       		:"=a" (cpu_khz), "=d" (edx)        	       		:"r" (tsc_quotient),	                	"0" (eax), "1" (edx));				printk("Detected %lu.%03lu MHz processor.\n", cpu_khz / 1000, cpu_khz % 1000);			}			set_cyc2ns_scale(cpu_khz/1000);			return 0;		}	}	return -ENODEV;}