if (s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) {
if (S3_ViRGE_GX2_SERIES(s3vPriv.chip) || S3_ViRGE_MX_SERIES(s3vPriv.chip)) {
S3VRestore (restore)vgaS3VPtr restore;{unsigned char tmp, cr3a, cr53, cr66, cr67;   vgaProtect(TRUE);   /* Are we going to reenable STREAMS in this new mode? */   s3vPriv.STREAMSRunning = restore->CR67 & 0x0c;    /* First reset GE to make sure nothing is going on */   if(s3vPriv.chip == S3_ViRGE_VX) {      outb(vgaCRIndex, 0x63);      if(inb(vgaCRReg) & 0x01) S3VGEReset();      }   else {      outb(vgaCRIndex, 0x66);      if(inb(vgaCRReg) & 0x01) S3VGEReset();      }   /* As per databook, always disable STREAMS before changing modes */   outb(vgaCRIndex, 0x67);   cr67 = inb(vgaCRReg);   if ((cr67 & 0x0c) == 0x0c) {      S3VDisableSTREAMS();     /* If STREAMS was running, disable it */      }   /* Restore S3 extended regs */   outb(vgaCRIndex, 0x63);                outb(vgaCRReg, restore->CR63);   outb(vgaCRIndex, 0x66);                outb(vgaCRReg, restore->CR66);   outb(vgaCRIndex, 0x3a);                outb(vgaCRReg, restore->CR3A);   outb(vgaCRIndex, 0x31);       outb(vgaCRReg, restore->CR31);   outb(vgaCRIndex, 0x58);                outb(vgaCRReg, restore->CR58);   outb(0x3c4, 0x08);   outb(0x3c5, 0x06);    outb(0x3c4, 0x12);   outb(0x3c5, restore->SR12);   outb(0x3c4, 0x13);   outb(0x3c5, restore->SR13);   if (s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) {     outb(0x3c4, 0x29);     outb(0x3c5, restore->SR29);     outb(0x3c4, 0x54);     outb(0x3c5, restore->SR54);     outb(0x3c4, 0x55);     outb(0x3c5, restore->SR55);     outb(0x3c4, 0x56);     outb(0x3c5, restore->SR56);     outb(0x3c4, 0x57);     outb(0x3c5, restore->SR57);   }   outb(0x3c4, 0x15);   outb(0x3c5, restore->SR15);    /* Restore the standard VGA registers */   vgaHWRestore((vgaHWPtr)restore);   /* Extended mode timings registers */     outb(vgaCRIndex, 0x53);                outb(vgaCRReg, restore->CR53);    outb(vgaCRIndex, 0x5d);        outb(vgaCRReg, restore->CR5D);   outb(vgaCRIndex, 0x5e);                outb(vgaCRReg, restore->CR5E);   outb(vgaCRIndex, 0x3b);                outb(vgaCRReg, restore->CR3B);   outb(vgaCRIndex, 0x3c);                outb(vgaCRReg, restore->CR3C);   outb(vgaCRIndex, 0x43);                outb(vgaCRReg, restore->CR43);   outb(vgaCRIndex, 0x65);                outb(vgaCRReg, restore->CR65);   outb(vgaCRIndex, 0x6d);   outb(vgaCRReg, restore->CR6D);   /* Restore the desired video mode with CR67 */           outb(vgaCRIndex, 0x67);                cr67 = inb(vgaCRReg) & 0xf; /* Possible hardware bug on VX? */   outb(vgaCRReg, 0x50 | cr67);    usleep(10000);   outb(vgaCRIndex, 0x67);                outb(vgaCRReg, restore->CR67 & ~0x0c); /* Don't enable STREAMS yet */   /* Other mode timing and extended regs */   outb(vgaCRIndex, 0x34);                outb(vgaCRReg, restore->CR34);   outb(vgaCRIndex, 0x40);                outb(vgaCRReg, restore->CR40);   outb(vgaCRIndex, 0x42);                outb(vgaCRReg, restore->CR42);   outb(vgaCRIndex, 0x45);   outb(vgaCRReg, restore->CR45);   outb(vgaCRIndex, 0x51);                outb(vgaCRReg, restore->CR51);   outb(vgaCRIndex, 0x54);                outb(vgaCRReg, restore->CR54);      /* Memory timings */   outb(vgaCRIndex, 0x36);                outb(vgaCRReg, restore->CR36);   outb(vgaCRIndex, 0x68);                outb(vgaCRReg, restore->CR68);   outb(vgaCRIndex, 0x69);   outb(vgaCRReg, restore->CR69);   outb(vgaCRIndex, 0x33);   outb(vgaCRReg, restore->CR33);   if (s3vPriv.chip == S3_ViRGE_DXGX) {      outb(vgaCRIndex, 0x86);      outb(vgaCRReg, restore->CR86);   }   if (s3vPriv.chip == S3_ViRGE_DXGX || s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) {      outb(vgaCRIndex, 0x90);      outb(vgaCRReg, restore->CR90);   }   /* Unlock extended sequencer regs */   outb(0x3c4, 0x08);   outb(0x3c5, 0x06);    /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates that     * we should leave the default SR10 and SR11 values there.    */   if (restore->SR10 != 255) {          outb(0x3c4, 0x10);       outb(0x3c5, restore->SR10);       outb(0x3c4, 0x11);       outb(0x3c5, restore->SR11);       }   /* Restore extended sequencer regs for DCLK */   outb(0x3c4, 0x12);   outb(0x3c5, restore->SR12);   outb(0x3c4, 0x13);   outb(0x3c5, restore->SR13);   if (s3vPriv.chip == S3_ViRGE_GX2 || s3vPriv.chip == S3_ViRGE_MX) {     outb(0x3c4, 0x29);     outb(0x3c5, restore->SR29);     outb(0x3c4, 0x54);     outb(0x3c5, restore->SR54);     outb(0x3c4, 0x55);     outb(0x3c5, restore->SR55);     outb(0x3c4, 0x56);     outb(0x3c5, restore->SR56);     outb(0x3c4, 0x57);     outb(0x3c5, restore->SR57);   }   outb(0x3c4, 0x18);   outb(0x3c5, restore->SR18);    /* Load new m,n PLL values for DCLK & MCLK */   outb(0x3c4, 0x15);   tmp = inb(0x3c5) & ~0x21;   outb(0x3c5, tmp | 0x03);   outb(0x3c5, tmp | 0x23);   outb(0x3c5, tmp | 0x03);   outb(0x3c5, restore->SR15);   /* Now write out CR67 in full, possibly starting STREAMS */      VerticalRetraceWait();   outb(vgaCRIndex, 0x67);       outb(vgaCRReg, 0x50);   /* For possible bug on VX?! */             usleep(10000);   outb(vgaCRIndex, 0x67);   outb(vgaCRReg, restore->CR67);    /* And finally, we init the STREAMS processor if we have CR67 indicate 24bpp    * We also restore FIFO and TIMEOUT memory controller registers.    */      outb(vgaCRIndex, 0x53);   cr53 = inb(vgaCRReg);   outb(vgaCRReg, cr53 | 0x08);  /* Enable NEWMMIO temporarily */   outb(vgaCRIndex, 0x66);   cr66 = inb(vgaCRReg);   outb(vgaCRReg, cr66 | 0x80);   outb(vgaCRIndex, 0x3a);   cr3a = inb(vgaCRReg);   outb(vgaCRReg, cr3a | 0x80);   if (s3vPriv.NeedSTREAMS) {      if(s3vPriv.STREAMSRunning) S3VRestoreSTREAMS(restore->STREAMS);      }   /* Now, before we continue, check if this mode has the graphic engine ON     * If yes, then we reset it.     * This fixes some problems with corruption at 24bpp with STREAMS    * Also restore the MIU registers.     */   if(s3vPriv.chip == S3_ViRGE_VX) {      if(restore->CR63 & 0x01) S3VGEReset();      }   else {      if(restore->CR66 & 0x01) S3VGEReset();      }   VerticalRetraceWait();   ((mmtr)s3vMmioMem)->memport_regs.regs.fifo_control = restore->MMPR0;   WaitIdle();                  /* Don't ask... */   ((mmtr)s3vMmioMem)->memport_regs.regs.miu_control = restore->MMPR1;   WaitIdle();                     ((mmtr)s3vMmioMem)->memport_regs.regs.streams_timeout = restore->MMPR2;   WaitIdle();   ((mmtr)s3vMmioMem)->memport_regs.regs.misc_timeout = restore->MMPR3;   outb(vgaCRIndex, 0x53);   outb(vgaCRReg, cr53);   /* Restore CR53 to original for MMIO */   outb(vgaCRIndex, 0x66);                outb(vgaCRReg, cr66);   outb(vgaCRIndex, 0x3a);                outb(vgaCRReg, cr3a);   if (xf86Verbose > 1) {      ErrorF("\n\nViRGE driver: done restoring mode, dumping CR registers:\n\n");      S3VPrintRegs();   }   vgaProtect(FALSE);}