} else if( vgaBitsPerPixel == 16) {  if( vga256InfoRec.displayWidth == 1024 )
else if( vgaBitsPerPixel == 16)
S3SAVRestore (restore)vgaS3VPtr restore;{unsigned char tmp, cr3a, cr53, cr66, cr67;unsigned int width;   vgaProtect(TRUE);#ifdef USEBIOS    /*     * If S3VInit figured out a VESA mode number for this timing, the     * just use the S3 BIOS to do the switching, with a few additional     * tweaks.     */    if( restore->mode > 0x13 )    {	unsigned short cr6d;	unsigned short cr79;	/* Set up the mode.  Don't clear video RAM. */	S3SAVSetVESAMode( restore->mode | 0x8000, restore->refresh );	/* Restore the DAC.  Ordinarily, vgaHWRestore does this, */	/* but since we use the BIOS, we don't call vgaHWRestore. */	outb(0x03c6, 0xff);	if( vgaBitsPerPixel == 8 )	{	    unsigned short i;	    outb( 0x3c8, 0 );	    for( i = 0; i < 3*256; i++ )	    {	        outb(0x03c9, restore->std.DAC[i]);	    }	}	/* Enable linear addressing. */	outw(vgaCRIndex, 0x1358);	/* Disable old MMIO. */	outb(vgaCRIndex, 0x53);	outb(vgaCRReg, inb(vgaCRReg) & ~0x10);	/* We may need TV/panel fixups here.  See s3bios.c line 2904. */	/* Set FIFO fetch delay. */	outb(vgaCRIndex, 0x85);	outb(vgaCRReg, (inb(vgaCRReg) & 0xf8) | 0x03);	/* Unlock the extended registers. */	outw(vgaCRIndex, 0x4838);	outw(vgaCRIndex, 0xA039);	outw(0x3c4, 0x0608);	/* Patch CR79.  These values are magical. */	outb(vgaCRIndex, 0x6d);	cr6d = inb(vgaCRReg);	cr79 = 0x04;	if( vga256InfoRec.displayWidth >= 1024 )	{	    if( vgaBitsPerPixel == 32 )	    {		if( restore->refresh >= 130 )		    cr79 = 0x03;		else if( vga256InfoRec.displayWidth >= 1280 )		    cr79 = 0x02;		else if(		    (vga256InfoRec.displayWidth == 1024) &&		    (restore->refresh >= 75)		)		{		    if( cr6d && LCD_ACTIVE )			cr79 = 0x05;		    else			cr79 = 0x08;		}	    }	    else if( vgaBitsPerPixel == 16)	    {/* The windows driver uses 0x13 for 16-bit 130Hz, but I see terrible * screen artifacts with that value.  Let's keep it low for now. *		if( restore->refresh >= 130 ) *		    cr79 = 0x13; *		else */		if( vga256InfoRec.displayWidth == 1024 )		{		    if( cr6d && LCD_ACTIVE )			cr79 = 0x08;		    else			cr79 = 0x0e;		}	    }	}        if( s3vPriv.chip != S3_SAVAGE2000)	    outw(vgaCRIndex, (cr79 << 8) | 0x79);	/* Make sure 16-bit memory access is enabled. */	outb(vgaCRIndex, 0x31);	outb(vgaCRReg, 0x0c);	/* Enable the graphics engine. */	outw(vgaCRIndex, 0x0140);	if(!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options))	    S3SAVInitialize2DEngine();	/* Handle the pitch. */        outb(vgaCRIndex, 0x50);        outb(vgaCRReg, inb(vgaCRReg) | 0xC1);	width = (vga256InfoRec.displayWidth * (vgaBitsPerPixel / 8)) >> 3;	outw(vgaCRIndex, ((width & 0xff) << 8) | 0x13 );	outw(vgaCRIndex, ((width & 0x300) << 4) | 0x51 );	/* Some non-S3 BIOSes enable block write even on non-SGRAM devices. */        if( s3vPriv.chip == S3_SAVAGE2000 )	{	    outb(vgaCRIndex, 0x73);	    outb(vgaCRReg, inb(vgaCRReg) & 0xdf );	}	else	{	    outb(vgaCRIndex, 0x68);	    if( !(inb(vgaCRReg) & 0x80) )	    {		/* Not SGRAM; disable block write. */		outb(vgaCRIndex, 0x88);		outb(vgaCRReg, inb(vgaCRReg) | 0x10);	    }	}	outw(vgaCRIndex, 0x0140);	S3SAVSetGBD();    } else {#endif   /* Are we going to reenable STREAMS in this new mode? */   s3vPriv.STREAMSRunning = restore->CR67 & 0x0c;    /* First reset GE to make sure nothing is going on */   outb(vgaCRIndex, 0x66);   if(inb(vgaCRReg) & 0x01) S3SAVGEReset(0,__LINE__,__FILE__);   /* As per databook, always disable STREAMS before changing modes */   outb(vgaCRIndex, 0x67);   cr67 = inb(vgaCRReg);   if ((cr67 & 0x04) == 0x04) {      S3SAVDisableSTREAMS();     /* If STREAMS was running, disable it */      }   /* Restore S3 extended regs */   outb(vgaCRIndex, 0x66);                outb(vgaCRReg, restore->CR66);   outb(vgaCRIndex, 0x3a);                outb(vgaCRReg, restore->CR3A);   outb(vgaCRIndex, 0x31);       outb(vgaCRReg, restore->CR31);   outb(vgaCRIndex, 0x58);                outb(vgaCRReg, restore->CR58);   outb(0x3c4, 0x08);   outb(0x3c5, 0x06);    outb(0x3c4, 0x12);   outb(0x3c5, restore->SR12);   outb(0x3c4, 0x13);   outb(0x3c5, restore->SR13);   outb(0x3c4, 0x29);   outb(0x3c5, restore->SR29);   outb(0x3c4, 0x15);   outb(0x3c5, restore->SR15);    /* Restore the standard VGA registers */   vgaHWRestore((vgaHWPtr)restore);   /* Extended mode timings registers */     outb(vgaCRIndex, 0x53);                outb(vgaCRReg, restore->CR53);    outb(vgaCRIndex, 0x5d);        outb(vgaCRReg, restore->CR5D);   outb(vgaCRIndex, 0x5e);                outb(vgaCRReg, restore->CR5E);   outb(vgaCRIndex, 0x3b);                outb(vgaCRReg, restore->CR3B);   outb(vgaCRIndex, 0x3c);                outb(vgaCRReg, restore->CR3C);   outb(vgaCRIndex, 0x43);                outb(vgaCRReg, restore->CR43);   outb(vgaCRIndex, 0x65);                outb(vgaCRReg, restore->CR65);   /* Restore the desired video mode with CR67 */           outb(vgaCRIndex, 0x67);                cr67 = inb(vgaCRReg) & 0xf; /* Possible hardware bug on VX? */   outb(vgaCRReg, 0x50 | cr67);    usleep(10000);   outb(vgaCRIndex, 0x67);                outb(vgaCRReg, restore->CR67 & ~0x0c); /* Don't enable STREAMS yet */   /* Other mode timing and extended regs */   outb(vgaCRIndex, 0x34);                outb(vgaCRReg, restore->CR34);   outb(vgaCRIndex, 0x40);                outb(vgaCRReg, restore->CR40);   outb(vgaCRIndex, 0x42);                outb(vgaCRReg, restore->CR42);   outb(vgaCRIndex, 0x45);   outb(vgaCRReg, restore->CR45);   outb(vgaCRIndex, 0x50);   outb(vgaCRReg, restore->CR50);   outb(vgaCRIndex, 0x51);   outb(vgaCRReg, restore->CR51);      /* Memory timings */   outb(vgaCRIndex, 0x36);                outb(vgaCRReg, restore->CR36);   outb(vgaCRIndex, 0x68);                outb(vgaCRReg, restore->CR68);   outb(vgaCRIndex, 0x69);   outb(vgaCRReg, restore->CR69);   outb(vgaCRIndex, 0x6F);   outb(vgaCRReg, restore->CR6F);   outb(vgaCRIndex, 0x33);   outb(vgaCRReg, restore->CR33);   outb(vgaCRIndex, 0x86);   outb(vgaCRReg, restore->CR86);   outb(vgaCRIndex, 0x88);   outb(vgaCRReg, restore->CR88);   outb(vgaCRIndex, 0x90);   outb(vgaCRReg, restore->CR90);   outb(vgaCRIndex, 0x91);   outb(vgaCRReg, restore->CR91);   outb(vgaCRIndex, 0xB0); /* Savage4 config3 */   outb(vgaCRReg, restore->CRB0);   /* Unlock extended sequencer regs */   outb(0x3c4, 0x08);   outb(0x3c5, 0x06);    /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates that     * we should leave the default SR10 and SR11 values there.    */   if (restore->SR10 != 255) {          outb(0x3c4, 0x10);       outb(0x3c5, restore->SR10);       outb(0x3c4, 0x11);       outb(0x3c5, restore->SR11);       }   /* Restore extended sequencer regs for DCLK */   outb(0x3c4, 0x12);   outb(0x3c5, restore->SR12);   outb(0x3c4, 0x13);   outb(0x3c5, restore->SR13);   outb(0x3c4, 0x29);   outb(0x3c5, restore->SR29);   outb(0x3c4, 0x18);   outb(0x3c5, restore->SR18);    /* Load new m,n PLL values for DCLK & MCLK */   outb(0x3c4, 0x15);   tmp = inb(0x3c5) & ~0x21;   outb(0x3c5, tmp | 0x03);   outb(0x3c5, tmp | 0x23);   outb(0x3c5, tmp | 0x03);   outb(0x3c5, restore->SR15);   outb(0x3c4, 0x08);   outb(0x3c5, restore->SR8);    /* Now write out CR67 in full, possibly starting STREAMS */      VerticalRetraceWait();   outb(vgaCRIndex, 0x67);       outb(vgaCRReg, 0x50);   /* For possible bug on VX?! */             usleep(10000);   outb(vgaCRIndex, 0x67);   outb(vgaCRReg, restore->CR67);    /* And finally, we init the STREAMS processor if we have CR67 indicate 24bpp    * We also restore FIFO and TIMEOUT memory controller registers.    */   outb(vgaCRIndex, 0x53);   cr53 = inb(vgaCRReg);   outb(vgaCRReg, cr53 | 0x08);  /* Enable NEWMMIO temporarily */   outb(vgaCRIndex, 0x66);   cr66 = inb(vgaCRReg);   outb(vgaCRReg, cr66 | 0x80);   outb(vgaCRIndex, 0x3a);   cr3a = inb(vgaCRReg);   outb(vgaCRReg, cr3a | 0x80);   if (s3vPriv.NeedSTREAMS) {      if(s3vPriv.STREAMSRunning) S3SAVRestoreSTREAMS(restore->STREAMS);      }   /* Now, before we continue, check if this mode has the graphic engine ON     * If yes, then we reset it.     * This fixes some problems with corruption at 24bpp with STREAMS    * Also restore the MIU registers.     */   if(restore->CR66 & 0x01) S3SAVGEReset(0,__LINE__,__FILE__);   VerticalRetraceWait();   ((mmtr)s3savMmioMem)->memport_regs.regs.fifo_control = restore->MMPR0;   WaitIdle();                  /* Don't ask... */   ((mmtr)s3savMmioMem)->memport_regs.regs.miu_control = restore->MMPR1;   WaitIdle();                     ((mmtr)s3savMmioMem)->memport_regs.regs.streams_timeout = restore->MMPR2;   WaitIdle();   ((mmtr)s3savMmioMem)->memport_regs.regs.misc_timeout = restore->MMPR3;   /* If we're going into graphics mode and acceleration was enabled, */   /* go set up the BCI buffer and the global bitmap descriptor. */   if( (restore->CR31 & 0x0a) &&       (!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options))   )   {      outb(vgaCRIndex, 0x50);      outb(vgaCRReg, inb(vgaCRReg) | 0xC1);      S3SAVInitialize2DEngine();   }   outb(vgaCRIndex, 0x53);   outb(vgaCRReg, cr53);   /* Restore CR53 to original for MMIO */   outb(vgaCRIndex, 0x66);                outb(vgaCRReg, cr66);   outb(vgaCRIndex, 0x3a);                outb(vgaCRReg, cr3a);   if( restore->CR31 & 0x0a )      S3SAVSetGBD();#ifdef USEBIOS}#endif   if (xf86Verbose > 1) {      ErrorF("\n\nViRGE driver: done restoring mode, dumping CR registers:\n\n");      S3SAVPrintRegs();   }   vgaProtect(FALSE);}