if(cpuDmaHack || cpuDmaHack2) {
if(cpuDmaHack) {
inline u32 CPUReadMemory(u32 address){#ifdef DEV_VERSION  if(address & 3) {      if(systemVerbose & VERBOSE_UNALIGNED_MEMORY) {      log("Unaligned word read: %08x at %08x\n", address, armMode ?          armNextPC - 4 : armNextPC - 2);    }  }#endif    u32 value;  switch(address >> 24) {  case 0:    if(reg[15].I >> 24) {      if(address < 0x4000) {#ifdef DEV_VERSION        if(systemVerbose & VERBOSE_ILLEGAL_READ) {          log("Illegal word read: %08x at %08x\n", address, armMode ?              armNextPC - 4 : armNextPC - 2);        }#endif                value = READ32LE(((u32 *)&biosProtected));      }      else goto unreadable;    } else      value = READ32LE(((u32 *)&bios[address & 0x3FFC]));    break;  case 2:    value = READ32LE(((u32 *)&workRAM[address & 0x3FFFC]));    break;  case 3:    value = READ32LE(((u32 *)&internalRAM[address & 0x7ffC]));    break;  case 4:    if((address < 0x4000400) && ioReadable[address & 0x3fc]) {      if(ioReadable[(address & 0x3fc) + 2])        value = READ32LE(((u32 *)&ioMem[address & 0x3fC]));      else        value = READ16LE(((u16 *)&ioMem[address & 0x3fc]));    } else goto unreadable;    break;  case 5:    value = READ32LE(((u32 *)&paletteRAM[address & 0x3fC]));    break;  case 6:    value = READ32LE(((u32 *)&vram[address & 0x1fffc]));    break;  case 7:    value = READ32LE(((u32 *)&oam[address & 0x3FC]));    break;  case 8:  case 9:  case 10:  case 11:  case 12:    value = READ32LE(((u32 *)&rom[address&0x1FFFFFC]));    break;      case 13:    if(cpuEEPROMEnabled)      // no need to swap this      return eepromRead(address);    goto unreadable;  case 14:    if(cpuFlashEnabled | cpuSramEnabled)      // no need to swap this      return flashRead(address);    // default  default:  unreadable:#ifdef DEV_VERSION    if(systemVerbose & VERBOSE_ILLEGAL_READ) {      log("Illegal word read: %08x at %08x\n", address, armMode ?          armNextPC - 4 : armNextPC - 2);    }#endif    if(cpuDmaHack || cpuDmaHack2) {      value = cpuDmaLast;    } else {      if(armState) {        value = CPUReadMemoryQuick(reg[15].I);      } else {        value = CPUReadHalfWordQuick(reg[15].I) |          CPUReadHalfWordQuick(reg[15].I) << 16;      }    }  }  if(address & 3) {#ifdef C_CORE    int shift = (address & 3) << 3;    value = (value >> shift) | (value << (32 - shift));#else    #ifdef __GNUC__    asm("and $3, %%ecx;"        "shl $3 ,%%ecx;"        "ror %%cl, %0"        : "=r" (value)        : "r" (value), "c" (address));#else    __asm {      mov ecx, address;      and ecx, 3;      shl ecx, 3;      ror [dword ptr value], cl;    }#endif#endif  }  return value;}