Man , if I ' m not sweating and chugging gallons of water that I know is not effective then it isn ' t nearly spicy enough . <| sep |> the output of the generated fifo component . Normally you would not need to touch the BRAM during a write to an empty FWFT fifo , but whether the BRAM is used in such a case is undefined . Apparently fifogenerator uses the BRAM , since it reports that an extra clock cycle of latency is added . If it was implemented to bypass the BRAM , you would at least need an extra 21 multiplexer for the output registers source 1 bram , source 2 fifo input and minimum latency is not really a fifo feature you would invest extra resources into , because latency through a fifo is highly variable in typical use cases anyway . Were the fifo to bypass the BRAM alltogether on an empty condition it would have to cross the clock domains properly , which can be implemented , just like it is implemented for the control signals and headtail counters .