Jpn. J. Appl. Phys. Vol. 39 (2000) pp. L 694–L 697Part 2, No. 7A, 1 July 2000c⃝2000 The Japan Society of Applied Physics
Single Wafer Furnace and Its Thermal Processing Applications
Woo Sik YOO, Takashi FUKADA, Hiromitsu KURIBAYASHI, Hirofumi KITAYAMA1,Nobuaki TAKAHASHI2, Keiichi ENJOJI2 and Kiyoshi SUNOHARA2
WaferMasters, Inc., 246 East Gish Road, San Jose, CA 95112, U.S.A.1Tokyo Electron Yamanashi Limited, 2381-1 Kitagejo, Fujii-cho, Nirasaki, Yamanashi 407-8511, Japan2Tokyo Electron Limited, 3-6 Akasaka 5-chome, Minato-ku, Tokyo 107-8481, Japan
(Received March 8, 2000; accepted for publication May 19, 2000)
A resistively heated, vacuum and atmospheric pressure compatible, single wafer furnace (SWF) system is proposed to im-prove operational ﬂexibility of conventional furnaces and productivity of single wafer rapid thermal processing (RTP) systems.The design concept and hardware conﬁguration of the SWF system are described. The temperature measurement/control tech-niques and thermal characteristics of the SWF system are described. Typical process results in TiSi formation, implant annealand thin oxide formation using the SWF system are reported. Due to the vertically stacked, dual chamber conﬁguration andsteady state temperature control, very ﬂexible operation with a high throughput at a minimal power consumption (<3.5 kW perprocess chamber at 1150◦C) was realized. Many thermal processes used in furnaces and RTP systems can easily be convertedto SWF processes without decreasing cost performance and/or deteriorating process results by using the SWF system.
KEYWORDS: single wafer furnace (SWF), rapid thermal processing (RTP), furnace, silicide, oxidation, thermal budget, sheetresistance, uniformity, throughput, power consumption
1.Introduction
Thermal processing applications such as dopant diffusion,annealing, oxidation, nitridation and thermal chemical vapordeposition (CVD) have always been at the center of siliconsemiconductor device fabrication processes since its indus-try’s inception. Horizontal batch furnaces were used for along time, then vertical batch furnaces were introduced toimprove temperature uniformity and efﬁciency of cleanroomspace usage. Batch furnaces are able to meet the requirementsfor many thermal processing applications even for 0.18 µmtechnology.1)
As device dimensions and allowable thermal budgets (moreprecisely, integral of diffusivity during thermal process) de-crease, many thermal processing applications are performedin single wafer rapid thermal processing (RTP) systems. Theneed for improved ambient control due to the introduction ofnew materials requires single wafer processing system. Be-sides the technical reasons, the ﬂexibility in processing lotsize, reduced cycle time and the ability for wafer-to-waferquality control from the risk management point of view pro-vided by single wafer processing make the single wafer pro-cessing more attractive.1–3) Typical RTP systems employ ei-ther halogen lamps or resistively heated susceptor as heatsource.4) The lamp based RTP systems have very poor en-ergy efﬁciency and requires complicated temperature mea-surement/control algorithms. Although the susceptor basedRTP systems have higher energy efﬁciency, they cannot beused in an oxidation environment due to the oxidation of sus-ceptor material.5)
To overcome the drawbacks of batch furnaces and singlewafer RTP systems, a single wafer furnace (SWF) with avacuum loadlock is designed. In this paper, the design con-cept and thermal behavior of a vacuum and atmospheric pres-sure compatible dual chamber SWF system are described.Wafer temperature characterization results during ramp-up,ramp-down and preliminary process results using the SWFsystem are described.
2.System Conﬁguration and Process Chamber
The SWF controls process chamber temperature steady
state and move wafers in and out of preheated process cham-ber instead of controlling wafer temperature directly.TheSWF process chamber consists of a transparent quartz reac-tor, a silicon carbide cavity, a heater assembly and an alu-minum housing. Two vertically stacked process chambers areattached to one side of the wafer transport module. The stackof a vacuum loadlock and two cooling stations are attachedto the other side of the wafer transport module to reduce thefootprint of the system. (Fig. 1(a)). The system is vacuum andatmospheric pressure compatible. Since the process chamberis made of quartz, the system can be used in oxidation as wellas annealing applications. A cross-section of the SWF pro-
Fig. 1.(a) Single wafer furnace conﬁguration. (b) Schematic illustrationof process chamber.
cess chamber is shown in Fig. 1(b). The process chamberhas three standoffs made of quartz and no moving parts in-side. An R-type (Pt-13% Rh/Pt) thermocouple is embeddedin one of the quartz standoffs to monitor idle process envi-ronment temperature and wafer temperature during process.The wafer is placed on the quartz standoffs (8–9 mm tall) inthe middle of process chamber. The distance between waferand quartz walls is kept at ∼10 mm for both up and down-ward directions. The quartz process chamber is located in aSiC cavity which acts as heat distributor to create isothermalprocess environment. The SiC cavity is surrounded by a threezone heater assembly.The entire unit (quartz process chamber, SiC cavity andheater assembly) is enclosed inside an aluminum chamber.The wafers can be processed in either vacuum or atmosphericpressure (1–760 Torr). In the SWF process chamber, the tem-perature of the SiC cavity is monitored by three embeddedR-type thermocouples and controlled by the three zone heaterassembly using feedback signals from the thermocouples toprovide identical and nearly isothermal environment to wafersregardless of wafer conditions. The process chamber temper-ature is kept constant at predetermined temperature. A nearlyisothermal environment where the wafer is processed is cre-ated by the SiC cavity with very high thermal conductivity.
3.Wafer Temperature Proﬁle during Process
Wafer temperature proﬁle during process at different pro-cess chamber (SiC cavity) temperatures is monitored usinga thermocouple embedded instrumentation wafer (Fig. 2).The wafer temperature measurement was done under 760 Torrair environment. The idle process environment temperatureand wafer temperature during process can also be monitoredby the embedded R-type thermocouple in one of the quartzstandoffs. Wafer handling sequence is as follows: (1) waferis introduced into process chamber by wafer handling robot,(2) robot lowers the wafer to standoffs, (3) the robot leavesthe process chamber, (4) hold wafer in the process chamberfor process time and (5) robot removes wafer from processchamber at process temperature.As seen in Fig. 2, wafer is heated as soon as it is intro-duced in the preheated process chamber. Wafer temperature
Fig. 2.Wafer temperature proﬁle during process at different temperatures.
increases approximately exponentionally and approaches fur-nace temperature with time. Initial ramp rate is ranging from∼150◦C/s at a furnace temperature of 1100◦C. The higherfurnace temperature, the higher initial ramp rate. Wafer isquickly removed after processing at almost process temper-ature and placed into cooling station. An exponential rampdown is observed during natural radiation cool down. Wafercooling is generally done in cooling station. Wafer temper-ature reaches 60◦C in less than 60 s from wafer retrieval at1100◦C when cooling station is used.Typical lamp heated RTP systems require wafer rotationto minimize within-wafer temperature non-uniformity due topattern transfer from lamp array during process. They alsorequire purge, preheating and wafer cooling steps before andafter the process. To prevent slip generation during high tem-perature processes, dynamic zone temperature control andslip prevention hardware such as a Si or SiC ring are em-ployed. Fast ramp-up without temperature overshooting hasalways been a signiﬁcant technical challenge for lamp heatedRTP system design. Process time referred in lamp heated RTPsystem is the soak time near process temperature regardless ofoverhead times such as preheating, ramp-up and ramp-downtimes.In a SWF system, temperature overshooting is simply notpossible by nature and excellent temperature repeatability isgiven as long as the SiC cavity temperature remains constant.Process time referred in this paper is the wafer residence time(from wafer-in to wafer-out) in a heated process chamber. Theexponential ramp-up and ramp-down is considered to be idealfor a wafer-friendly, efﬁcient thermal processing without in-creasing unnecessary process steps which result in thermalbudget increase and productivity decrease.
4.Process Results and Discussion
The shape effect of heated cavities on within wafer temper-ature uniformity was investigated using two different types ofSiC cavities. One cavity was conﬁgured with two SiC parallelplates (284 mm×270 mm×5 mm) which was surrounded bya heater assembly. The other cavity was conﬁgured with a onepiece SiC tube with a rectangular cavity inside. The distancebetween the SiC planes in both cavities were kept constant at26 mm. The within wafer temperature uniformity was evalu-ated in terms of process uniformity as well as crystalline slipgeneration in the temperature range of 600–1150◦C.At temperatures below 800◦C, very uniform process re-sults were obtained regardless of SiC cavity conﬁguration.When two parallel plates are used as a heat diffuser, heatloss from the edge of the parallel plates and the wafer makethe within wafer temperature uniformity worse at tempera-ture above 800◦C. In the case of a one piece SiC tube cavity,we were able to maintain excellent within wafer temperatureuniformity in the temperature range of 600–1150◦C by con-trolling the power of both ends of the SiC cavity. Processuniformity was investigated using the one piece SiC cavity asa heat diffuser.Figure 3 shows sheet resistance contour maps for 200 mmdiameter wafers before and after TiSi formation. The sheetresistance was measured using a four point probe and 5 mmfrom wafer edge was excluded in measurement. The thick-ness of Ti ﬁlms was 80 nm. The annealing condition for TiSiformation was 600◦C/60 s and 800◦C/60 s. The uniformity
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with increased process ﬂexibility and short cycle time.Dual process chamber conﬁguration of the SWF systemprovides greater ﬂexibility in process temperature while keep-ing process chamber temperature constant. Many silicide re-quires two step (formation and annealing) processes at twodifferent temperatures.In the SWF system, each processchamber can be set at different temperature. In other words,one SWF system can handle the ﬁrst (formation) step and thesecond (annealing) step without waiting temperature changeand stabilization from one temperature to the other. Due todual process chamber conﬁguration and very efﬁcient tem-perature ramp up/down characteristics of the SWF system,a very high wafer throughput is achieved. Throughputs of
change in 1σ after process of wafers was less than 1.0%, sug-gesting excellent within-wafer temperature uniformity duringthe process. Excellent within-wafer temperature uniformitywas achieved over the entire silicidation temperature range.Sheet resistance uniformity of an arsenic implant wafer(75As+ 80 keV, 1 × 1016/cm2) after annealing is shown inFig. 4. Annealing was done at 915◦C for 85 s under 760 TorrN2. The sheet resistance and uniformity were 51.27 �/sq. and0.33% (1σ), respectively.Thin oxide ﬁlms were grown on 200 mm diameter Siwafers. Dry oxidation was done at 1050◦C under 100% O2760 Torr.Process time was varied from 60 to 3600 s andoxygen ﬂow of 3 slm was maintained throughout the process.Figure 5 shows thickness contour map of thin oxide formedfor 120 s in SWF process chamber. Oxide thickness was mea-sured by ellipsometry. An average ﬁlm thickness of 8.5 nmwith uniformity of ∼1.0% in 1σ was obtained.To investigate temperature uniformity and thermal shockduring high temperature process (>1000◦C), bare Si waferswere annealed 1 to 10 times in the temperature range of800–1150◦C. We were able to anneal Si wafers without gen-erating any slip lines in the temperature range of interest.X-ray topography does not indicate any slip generation inwafers processed 5 times repeatedly in the SWF system at1100◦C for 60 s under 760 Torr in air after process parameteroptimization. Process optimization details of slip preventionwill be published separately.Process and slip test results obtained using the SWF systemare equivalent or better than those obtained from the conven-tional lamp heated RTP systems. Feasibility of a new RTPsystem with a very simple design was demonstrated. Highthermal conductivity and diffusivity of SiC cavity and opti-mized geometry of heater zones made this possible. Lampbased RTP systems are limited to applications with relativelyshorter processing time due to the hardware limitations suchas reliability and lifetime of lamps, and temperature increaseof quartz windows and lamp housings. Since the SWF hasno hardware limitations affecting the length of process time,many batch furnace processes can also be done in the system
Fig. 4.Sheet resistance contour map of As+ implant wafer after anneal-ing (dose: 75As+ 1 × 1016/cm2, temperature: 915◦C, pressure: 760 Torr,process time: 85 s, N2 ﬂow: 1 slm).
Fig. 3.Sheet resistance contour maps of Ti (before process) and TiSi (afterprocess) layers on 200 mm wafer. (Ti ﬁlm thickness: 80 nm, pressure:760 Torr, process time: 60 s, N2 ﬂow: 1 slm)
Fig. 5.Thickness contour map of thin oxide ﬁlm (temperature: 1050◦C,pressure: 760 Torr, process time: 120 s, O2 ﬂow: 3 slm).
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60–70 wafers per hour can be achieved for 60 s processeswith a 60 s cool down step. Average steady state power con-sumption at 1150◦C is <3.5 kW per process chamber. Sincethe SiC cavity temperature is controlled at steady state, peakpower requirement does not normally exceed twice the aver-age steady state power consumption. In contrast, lamp basedRTP systems consume a peak power of 50–250 kW per pro-cess chamber at a temperature set point of 1000◦C dependingon the number of lamps and lamp array.
5.Summary
The concept and feasibility of a vacuum and atmosphericpressure compatible, dual chamber SWF system were demon-strated with TiSi, As+ implant anneal and dry oxidation pro-cesses. The temperature measurement/control techniques andthermal characteristics of the SWF system were described andcompared with those of conventional lamp heated RTP sys-tems. Uniformity change in sheet resistance before and af-ter process was kept below 1.0% (1σ) in both TiSi process.The As+ implantation anneal and dry oxidation results alsoshowed an excellent uniformity of 1.0% (1σ) or less. Dueto the dual process chamber conﬁguration and steady statetemperature control, a very high throughput (60–70 wafersper hour for 60 s process) at a minimal power consumption(<3.5 kW at 1150◦C) was achieved. Many furnace processes
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2) C. Ratliff, T. Koble, R. Sloan, S. Sedehi, A. Helms, Jr., J. Kowalskiand T. Qiu:Proc. 7th Int. Conf. Advanced Thermal Processing ofSemiconductors-RTP’99 (Colorado Springs, 1999) p. 16.3) A. L. Helms, Jr., R. B. Herring, C. Porter and A. Starner: Solid StateTechnol. 42, No. 11 (1999) 83.4) F.Roozeboom: Advances in Rapid Thermal & Integrated Processing, ed.F. Roozeboom (The Netherlands, 1996) NATO ASI Series E, Vol. 318,Chap. 1.5) W. S. Yoo, A. J. Atanos and J. F. Daviet: Jpn. J. Appl. Phys. 37 (1998)L1135.
can easily be converted to SWF processes without decreas-ing productivity. Thermal budget and process cycle time willbe reduced signiﬁcantly. Most of RTP processes can also bedone without decreasing cost performance and/or deteriorat-ing process results by using the SWF system.
Acknowledgements
The authors would like to thank Mr. Y. Hiraga, Mr. D.Carman, Mr. K. Kang, Ms. J. Lau and Mr. T. Yamazaki ofWaferMasters, Inc. for useful discussions and encouragementthroughout this work.
1) J. K. Truman, C. M. Gronet, N. L. Kuan, C. M. Czarnik, G. E. Miner,D. C. Jennings and I. Beinglass: Proc. 7th Int. Conf. Advanced ThermalProcessing of Semiconductors-RTP’99 (Colorado Springs, 1999) p. 6.