Micron MT41K512M16 x16 8Gbit
Micron MT41K512M16 x16 8Gbit
TDA2x Host Processor (ABC)
OS and Application Memory 2Gbyte Total
2x Micron MT41K512M16 16Gbit, 2x(64 Meg x 16 x 8 banks)
Micron MT41K512M8 4Gbit, 1x(64 Meg x 8 x 8 banks)
ECC Memory512Mbyte Total
CSI2.0 to VIN Bridge
Lattice LIF MD6000 &URVV/LQNŒ�FPGA #1
CSI2.0 to VIN Bridge
Lattice LIF MD6000 &URVV/LQNŒ�FPGA #2
VIN3ALattice LIF MD6000 &URVV/LQNŒ�FPGA #3
CSI2.0 to VIN Bridge
VIN4ALattice LIF MD6000 &URVV/LQNŒ�FPGA #4
CSI2.0 to VIN Bridge
DDR3-106632-Bit+ECCEMIF1
DDR3-106632-Bit EMIF2OS and Application Memory2Gbyte Total
2x Micron MT41K512M16 16Gbit (64 Meg x 16 x 8 banks)Hirose FX23-120S-0.5SV10
AWR1243 RF Board Connectors
CSI2.0 AWR#1
CSI2.0 AWR#2
CSI2.0 AWR#3
CSI2.0 AWR#3
UART31:4 MUX
UART AWR#1
UART AWR#2
UART AWR#3
UART AWR#4
SPI AWR#1/4
SPI AWR#2/3
GPIOSOP
UARTUSB Bridge
USB2.0MiniConnectorUART1
USB3.0DeviceConnector
USB3.0Super-Speed (5Gbps)
EMU Port/VOUT
60-Pin MIPI Debug Header
1G Ethernet PHY
DP83867IRPAPR
RGMIIRJ-45Magnetics
QSPI Flash, 133MHz, 1Gbit (128M x 8)
Micron MT25QL01GBBB8ESF
HDMIType-AConnectorHDMI1.4a
PCIe m.2 Host ConnectorPCIe 2.05Gbps
MicroSD CardConnectorMMC1
GPIOAWR_RESETS
2:1 MUX
VOUT 10GigE Header
1JAJU738–June 2019
TIDUEQ8 翻訳版 — 最新の英語版資料 http://www-s.ti.com/sc/techlit/TIDUEQ8
Copyright © 2019, Texas Instruments Incorporated
Jacinto™ ADAS プロセッサを使用するカスケード接続イメージング・レー
ダー・キャプチャのリファレンス・デザイン
参参考考資資料料
デデザザイインン・・ガガイイドド: TIDEP-01017
Jacinto™ ADAS ププロロセセッッササをを使使用用すするるカカススケケーードド接接続続イイメメーージジンン
ググ・・レレーーダダーー・・キキャャププチチャャののリリフファァレレンンスス・・デデザザイインン
このリファレンス・デザインは、カスケード接続イメージング・レーダー・システムの処理の基礎となるものです。カスケード接続のレーダー・デバイスは、フロントの長距離 (LRR)ビーム成形アプリケーションに加えて、コーナーおよび側面カスケード接続のレーダーおよびセンサ・フュージョン・システムにも対応できます。
このリファレンス・デザインには、認定開発者が ADAS アプリケーションの開発とテストを行うために使用できる、ソフトウェア評価プラットフォームを作成するための設計資料が用意されています。このデザインにより、複数の車載用レーダー・フロント・エンドおよびアンテナ・サブシステムに対応できる基本プラットフォームを短期間で開発できます。
リリソソーースス
TIDEP-01017デザイン・フォルダ
TDA2SXプロダクト・フォルダ
VisionSDKツール・フォルダ
TIDEP-01012デザイン・フォルダ
E2E™エキスパートに質問
•SVTronics AWRx CIR レーダー・アンテナのリファレンス・デザインと互換
•4 × 格子のクロスファイア FPGA ベースのインターフェイス(AWRx ごとに 1 つ)
•4 つのレーダー処理 SIMD アクセラレータを持つ高性能 TDA2x デバイス (AWRx ごとに 1 つの EVE)
•イーサネット接続により制御、PCIe 接続によりデータを転送
アアププリリケケーーシショョンン
•長距離レーダー
•イメージング・レーダー
•運転支援 ECU
•レーダー ECU
•中距離/短距離レーダー
•ADAS ドメイン・コントローラ
使用許可、知的財産、その他免責事項は、最終ページにあるIMPORTANT NOTICE (重要な注意事項)をご参照くださいますようお願いいたします。
System Descriptionwww.tij.co.jp
2JAJU738–June 2019
TIDUEQ8 翻訳版 — 最新の英語版資料 http://www-s.ti.com/sc/techlit/TIDUEQ8
Copyright © 2019, Texas Instruments Incorporated
Jacinto™ ADAS プロセッサを使用するカスケード接続イメージング・レーダー・キャプチャのリファレンス・デザイン
1System Description
Autonomous control of a vehicle provides quality-of-life and safety benefits in addition to making therelatively mundane act of driving safer and less difficult. The quality-of-life features include the ability of avehicle to park itself, or to determine whether a lane change is possible, and provide features likeautomatic cruise control—where a vehicle maintains a constant distance with respect to the car ahead ofit, essentially, tracking the velocity of the car in front of it. Autonomous braking and collision avoidance aresafety features that prevent accidents caused by driver inattention. These features work by observing thearea in front of a car and alerting the ADAS subsystems if obstacles are observed that are likely to hit thecar. Implementing these technologies requires a variety of sensors to detect obstacles in the environmentand track their velocities and positions over time.
1.1Key System Specifications
This reference design has two sets of specifications because the radar is used as a multi-mode radar.MIMO is the first specification. TX beamforming (TXBF) is the second specification,
表表 1. Key System Specifications
RECOMMENDED OPERATING CONDITIONSMINTYPMAX
Input voltage (VIN)6 V12 V24 V
1.2Why Cascade Radar?
Frequency-modulated continuous-wave (FMCW) radars allow the accurate measurement of range andrelative velocity of obstacles and other vehicles; therefore, radars are useful for autonomous vehicularapplications (such as parking assist and lane change assist) and car safety applications (autonomousbreaking and collision avoidance). An important advantage of radars over camera and light-detection-and-ranging (LIDAR)-based systems is that radars are relatively immune to environmental conditions (such asthe effects of rain, dust, and smoke). FMCW radars can work in complete darkness and also brightdaylight (radars are not affected by glare) because they transmit and receive electromagnetic waves.When compared with ultrasound, radars typically have a much longer range and much faster time oftransit for their signals.
Despite the many advantages of radar technology, in many cases, automotive manufacturers today stilluse camera sensors as the primary sensor technology used to make final safety decisions in the system.
The radar sensor is being used as the secondary sensor; meaning, the vehicle system receives the Radarwarning, but decides to take an action only upon the camera sensor verification. The main reason islimitation in radar angular resolution. The radar sensors deployed today in most vehicles lack the ability todistinguish between static objects with the same range and same relative velocity.
Today, a typical front radar sensor has about a 5-degree angular resolution that corresponds to the abilityof the sensor to distinguish between objects that are 8.5 m apart at 100 m. Objects that are closer than8.5 m appear as one object. For example, a vehicle stopped in the right lane, might look like a shoulderroad street lamp for example, and therefore would be ignored by the safety system.
This is about to change with the introduction of the Imaging Radar solution from Texas Instruments (TI).
The TI Imaging Radar is a four-chip cascade solution, that acts like a single-chip sensor but achieves20Log10(NTX) SNR gain in TX beamforming mode and 360/(N*pi) angular resolution (N is the number ofvirtual antennas in a MIMO configuration).
www.tij.co.jpSystem Description
3JAJU738–June 2019
TIDUEQ8 翻訳版 — 最新の英語版資料 http://www-s.ti.com/sc/techlit/TIDUEQ8
Copyright © 2019, Texas Instruments Incorporated
Jacinto™ ADAS プロセッサを使用するカスケード接続イメージング・レー
ダー・キャプチャのリファレンス・デザイン
The TI Imaging Radar solution, we can distinguish between static objects 0.6 degrees apart with allantennae placed in single dimension linearly, and reach a 350-m object detecting range(angular resolutionis dependent on the antenna configuration and the number of TX/RX antennae).
This performance enables TI Imaging Radar to become the primary sensor in the vehicle and enhancesafety across weather and visibility conditions by providing a high-resolution image for both static andmoving objects.
1.3TI Cascade Radar Design
The TIDEP-01017 provides an easy-to-use, detailed reference design of a base platform, based on theTDA2x, supporting multiple automotive radar front end and antenna sub-systems. This reference designcan be used as a starting point to design a standalone sensor for a variety of LRR and imaging radarapplications.
The base platform, or host board, works with the TI Cascade RF reference design, or RF board based onthe AWR1243P device.
The flexible chirp and frame timing engine available on the AWR1243P device (similar to other AWRfamily mmWave sensors) allows the system to function as a multi-mode radar, interleaving beamformingand MIMO configurations on a per-chirp basis. This enables the sensor designer to achieve best rangeand best angular resolution across the array of Cascaded AWR1243P devices as the scene dynamicsrequires.
A beamforming antenna across multiple, cascaded, AWR1243P devices provides sensor designers withhigher-output power and therefore, lower detectable target RCS or increased range detection, or both.Applications requiring detection of automobile, motorcycle, pedestrian, signage, bridges, and other road-way objects and barriers at or beyond a 350-m range can make use of this mode of operation.
In medium-range applications (150-m ranges), creating MIMO antenna arrays across multiple, cascaded,AWR1243P devices allows the sensor designer to maximize the number of active antennas enablingsubstantially improved angular resolution. This enables sub-1 degree resolution: true imaging radarcapability.
System Descriptionwww.tij.co.jp
4JAJU738–June 2019
TIDUEQ8 翻訳版 — 最新の英語版資料 http://www-s.ti.com/sc/techlit/TIDUEQ8
Copyright © 2019, Texas Instruments Incorporated
Jacinto™ ADAS プロセッサを使用するカスケード接続イメージング・レーダー・キャプチャのリファレンス・デザイン
図図 1. AWR1243P Four-Device Cascade Radar RF Radar Board
Micron MT41K512M16 x16 8Gbit
Micron MT41K512M16 x16 8Gbit
TDA2x Host Processor (ABC)
OS and Application Memory 2Gbyte Total
2x Micron MT41K512M16 16Gbit, 2x(64 Meg x 16 x 8 banks)
Micron MT41K512M8 4Gbit, 1x(64 Meg x 8 x 8 banks)
ECC Memory512Mbyte Total
CSI2.0 to VIN Bridge
Lattice LIF MD6000 &URVV/LQNŒ�FPGA #1
CSI2.0 to VIN Bridge
Lattice LIF MD6000 &URVV/LQNŒ�FPGA #2
VIN3ALattice LIF MD6000 &URVV/LQNŒ�FPGA #3
CSI2.0 to VIN Bridge
VIN4ALattice LIF MD6000 &URVV/LQNŒ�FPGA #4
CSI2.0 to VIN Bridge
DDR3-106632-Bit+ECCEMIF1
DDR3-106632-Bit EMIF2OS and Application Memory2Gbyte Total
2x Micron MT41K512M16 16Gbit (64 Meg x 16 x 8 banks)Hirose FX23-120S-0.5SV10
AWR1243 RF Board Connectors
CSI2.0 AWR#1
CSI2.0 AWR#2
CSI2.0 AWR#3
CSI2.0 AWR#3
UART31:4 MUX
UART AWR#1
UART AWR#2
UART AWR#3
UART AWR#4
SPI AWR#1/4
SPI AWR#2/3
GPIOSOP
UARTUSB Bridge
USB2.0MiniConnectorUART1
USB3.0DeviceConnector
USB3.0Super-Speed (5Gbps)
EMU Port/VOUT
60-Pin MIPI Debug Header
1G Ethernet PHY
DP83867IRPAPR
RGMIIRJ-45Magnetics
QSPI Flash, 133MHz, 1Gbit (128M x 8)
Micron MT25QL01GBBB8ESF
HDMIType-AConnectorHDMI1.4a
PCIe m.2 Host ConnectorPCIe 2.05Gbps
MicroSD CardConnectorMMC1
GPIOAWR_RESETS
2:1 MUX
VOUT 10GigE Header
www.tij.co.jpSystem Overview
5JAJU738–June 2019
TIDUEQ8 翻訳版 — 最新の英語版資料 http://www-s.ti.com/sc/techlit/TIDUEQ8
Copyright © 2019, Texas Instruments Incorporated
Jacinto™ ADAS プロセッサを使用するカスケード接続イメージング・レー
ダー・キャプチャのリファレンス・デザイン
2System Overview
2.1Block Diagram
図 2 shows the block diagram of the cascade radar host processor board.
図図 2. Cascade Radar Host Processor Block Diagram
System Overviewwww.tij.co.jp
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Jacinto™ ADAS プロセッサを使用するカスケード接続イメージング・レーダー・キャプチャのリファレンス・デザイン
2.2Design Considerations
2.2.1Cascade Radar Host Board based on TDA2x Application Processor
This cascade radar host board reference design supports the TDA2x application processor. TI designedthe TDA2x System-on-Chip (SoC) as a highly-optimized and scalable family of devices to meet therequirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2x family enables broadADAS applications in automobiles by integrating an optimal mix of performance, low power and ADASvision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.
The TDA2x SoC enables sophisticated embedded vision technology in automobiles by broadest range ofADAS applications including front camera, park assist, surround view and sensor fusion on a singlearchitecture
The TDA2x SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed andfloating-point TMS320C66x digital signal processor (DSP) cores, Vision AccelerationPac, Arm® Cortex®-A15 MPCore™ and dual Cortex-M4 processors. The integration of a video accelerator for decodingmultiple video streams over an Ethernet AVB network, along with graphics accelerators for renderingvirtual views, enable a 3D viewing experience. In addition, the TDA2x SoC also integrates a host ofperipherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround viewsystems, displays, CAN and GigB Ethernet AVB.
The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs)offloading the perception analytics functionality from the application processor while also reducing thepower footprint. The Vision AccelerationPac is optimized for perception processing with a 32-bit RISC corefor efficient program execution and a vector coprocessor for specialized perception processing.
Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor,including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and adebugging interface for visibility into source code execution.
The TDA2x ADAS processor is qualified according to the AEC-Q100 standard.
2.2.2Cascade Radar RF Board Based on AWR1243P Sensor
The Cascade Radar RF board is built around the AWR1243P device. The AWR1243P is an integratedsingle-chip, frequency modulated continuous wave (FMCW) sensor capable of operation in the 76 to 81GHz frequency band. Built with TI’s low-power, 45-nm RFCMOS processor and enabling unprecedentedlevels of analog and digital integration, the AWR1243P achieves an extremely small form factor. Thedevice has four receivers and three transmitters with a closed-loop phase-locked loop (PLL) for preciseand linear chirp synthesis.
Each transmitter includes a programmable 6-bit phase shifter (5.625 degree step) to enable beamformingapplications. Each device also includes two 20-GHz local oscillator (LO) output and two 20-GHz LO inputpaths for sharing the VCO output with neighboring devices. This enables a cost-effective, totally passive,cascaded radar architecture.
The sensor includes a built-in self test (BIST) for RF calibration and safety monitoring. Based on complexbaseband architecture, the sensor device supports an IF bandwidth of 15 MHz with reconfigurable outputsampling rates in both complex and real sampling modes. Two separate ARM Cortex R4F basedprocessors run the TI provided the radar front-end, calibration, and host processor interface firmwaretargeting ASIL-B compliance.
TPS43351QDAPRQ1 PMIC 
x�System 5 V, 1Ax�System 3.3 V 1A
TPS659039-Q1 (O9039A387IZWSRQ1) PMIC 
x�TDA2x Powerx�Multiple LDO, Buck Converters
x�1.35 V DDR3 SDRAM 
TPS57112-Q1 2A, 2-MHz, Synchronous Step-Down
TPS51200QDRCRQ1Push-Pull VTT Regulator
x�VTT/VREF DDR3 SDRAM 
TPS74801-Q1 LDOLP5907QMFX-2.5Q1  LDO
x�FPGA 2.5 Vx�Ethernet PHY 1.1V
x�12 V External Power
TPS62262TDRVRQ1 LDO
x�FPGA 1.2 V
www.tij.co.jpSystem Overview
7JAJU738–June 2019
TIDUEQ8 翻訳版 — 最新の英語版資料 http://www-s.ti.com/sc/techlit/TIDUEQ8
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Jacinto™ ADAS プロセッサを使用するカスケード接続イメージング・レー
ダー・キャプチャのリファレンス・デザイン
2.2.3TDA2x Reference Design Use Cases and Specifications
The RF board dictates this reference design’s use cases and specifications, and has two sets ofspecifications because the radar is used as a multi-mode radar: MIMO and T TX beamforming (TXBF).
表表 2. Cascade MIMO and Cascade Beamforming specifications
PARAMETERSPECIFICATIONS (MIMO)
SPECIFICATIONS
(TXBF)DETAILS
Maximum range150 m350 mThis represents the maximum distance that the radar can detect an objectrepresenting an RCS of approximately 10 m2.
Range resolution60 cm150 cmRange resolution is the ability of a radar system to distinguish betweentwo or more targets on the same bearing but at different ranges. Theresolution is configurable, so the provided number is just an example.
Azimuth angle resolution1.4 degrees1.4 degrees (with
multiple beam steering)
Angle resolution is the ability of a radar system to distinguish between twoor more targets with the same range and velocity but different angles. Theresolution is equivalent in both applications.
Elevation angle resolution18 degreesNAElevation angle resolution is only available for MIMO application given theantenna design on the TI cascade RF board.
Maximum velocity133 kmph133 kmphThis is the native maximum velocity obtained using a two-dimensionalFFT on the frame data. For TDM MIMO case, velocity compensationalgorithm is applied to recover the native maximum velocity. Thisspecification will be improved over time by showing how higher-levelalgorithms can extend the maximum measurable velocity beyond thislimit.
Velocity resolution0.53 kmph0.53 kmphThis parameter represents the capability of the radar sensor to distinguishbetween two or more objects at the same range but moving with differentvelocities.
2.2.4Power Considerations
図 3 shows the various power management devices necessary to provide the various voltage domainsnecessary for operation of the host board.
図図 3. Cascade Radar Host Processor Power Block Diagram
System Overviewwww.tij.co.jp
8JAJU738–June 2019
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Jacinto™ ADAS プロセッサを使用するカスケード接続イメージング・レーダー・キャプチャのリファレンス・デザイン
In addition, the Cascade RF board accepts 5-V DC, 8-A (max) power through the host board connectors.The primary 5-V system rail shall be converted into the various AWR12x device rails by a pair ofLP87524P, quad-channel, monolithic, buck-converters.
表表 3. High-Level System Features of Cascade Radar RF board
CASCADE RADAR RF BOARD
4 × AWR1243P76–81GHz radar SoC
Integrated VCO, LO distribution, PA, LNA, ADC, 3 TX and 4 RXARM MCU R4 Controller
AWR RF PERIPHERALS
12 × TX, 16 × RX antennas12 total transmitters across all 4 AWR1243 P devices16 total receivers across all 4 × AWR1243P devices
Azimuth array86 element virtual array – enabling 1.4 degree angular resolution
Elevation array4 element virtual array – enabling 28 degree angular resolution
Embedded antennaRogers RO3003 4-element, series-fed, patch antenna
20-GHz LOStar distribution
2 × passive Wilkinson Power dividers fed by the Master AWR12x device LO output to SlaveAWR12x devices and Master AWR12x device
AWR DIGITAL PERIPHERALS
Clock distributionLMK00804B low-jitter clock distribution
Digital sync distributionLMK00804B low-jitter clock distribution
CSI2.0 4-lane600Mbps/Lane, max 2.4Gbps ADC IF data per device
QSPI Flash16-Mbit QSPI flash for AWR firmware updates
Serial peripheralsSPI, I2C, UART, GPIO
System temperatureTMP112 I2C Temperature Sensors
Radar power management IC(PMIC) solution
2 × LP87524P-Q1 Quad-Channel, Integrated FET, Buck Converters and LC filtering solution
2.2.5Cascade Host System Features
表表 4. High-Level System Features of Cascade Radar Host board
CASCADE RADAR HOST BOARD
Host processorTDA2SX ADAS SoC
CPUDual-core ARM A15, 1176 MHz
DSP2 × C66x, 750 MHz
GPUDual-core SGX544 GPU, 532 MHz
EVE co-processor4 × EVE Matrix co-processor, 532 MHz
IVA co-processor2 × IVA Image co-processor, 532 MHz
Memory2 × 32-bit, 2GByte, DDR3L-1066 SDRAM (one bank ECC capable)
USBUSB3.0 host and USB2.0 host
CSI2.04 × 4-lane CSI2.0, 900Mbps
Video out24-bit digital video out, HDMI 1.4b
Connectivity1 Gigabit Ethernet, USB2.0 serial port (TI RTOS/ Linux console)
Data storagePCIe 2.0 m.2 connector(M-Keyed), 1 Gigabit NOR flash, MicroSD card
Mechanical160-mm × 140-mm - two automotive rated board to board connectors
SoftwareTI RTOS with radar SDK packages, TI processors SDK Linux distribution with radar SDK packages,algorithm support via VSDK 3.07
www.tij.co.jpSystem Overview
9JAJU738–June 2019
TIDUEQ8 翻訳版 — 最新の英語版資料 http://www-s.ti.com/sc/techlit/TIDUEQ8
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Jacinto™ ADAS プロセッサを使用するカスケード接続イメージング・レー
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2.2.6AWR1243P Cascade RF Board Architecture
The AWR1243P Cascade RF board consists of four AWR1243P 77-GHz radar devices and theirassociated power, clocking, synchronization, LO, and RF circuits.
Each AWR1243P RF, RX, and TX port is routed to its own set of etched, patch antenna. Each AWR1243Pon the RF board has a 4-port CSI2.0 transmitter that is used for sending radar data to a host processorCSI2.0 receiver set. The entire AWR1243P configuration, control, and reset lines are made available ontwo host-interface connectors implemented with Hirose FX32 series connectors.
The AWR1243P devices are separated into master and slave devices classes. AWR1243P #1, the masterdevice, uses the AWR1243P architecture built in LO distribution, clock distribution and framesynchronization distribution to provide 40-MHz clock, 20-GHz LO, and digital frame synchronization to theother three slave devices – AWR1243P #2, #3 and #4. This allows the system to generate and receivecoherent FMCW chirps across the 4 AWR1243P device array of transmitters and receivers; enablingbeamforming and MIMO operation across the array of devices.
The 20-GHz LO distribution follows the start-network configuration described in the AWR1243 CascadeRadar Application Note, SWRA574A. With the master AWR1243P #1 feeding a network of two Wilkinsonpower dividers, that provide synchronous LO for the Master and Slave RF PA and mixer subsystems. Allclock distribution, synchronization distribution, and LO distribution requirements are documented theProgramming Chirp Parameters in TI Radar Devices Application Report.
The Cascade RF board accepts 5-V DC, 8-A (max) power through the host board connectors. The primary5-V system rail can be converted into the various AWR12x device rails by a pair of LP87524P, quad-channel, monolithic, buck-converters.
2.2.720-GHz Local Oscillator (LO) Distribution
20-GHz LO distribution to all AWR1243P devices is accomplished through an entirely passive,transmission-line and etched power divider network. By using the dual LO outputs and LO inputs providedon each AWR1243P device, all devices including the master device, receive the same master devicegenerated LO output. This results in all package and die routing delays common across all devices. ThePCB designer is left with the task of delay matching only the BGA to BGA delays.
By using both of the 6-dBm (typical) LO output, and minimizing transmission line and power divider losses,no external amplifiers are required to be added to the LO network. Additionally, by outputting 20-GHz LOversus full 77-GHz RF for RF synchronization, the LO PCB link budgets can be more relaxed.
The passive LO distribution network and relaxed link budget results in more PCB design flexibility and alower overall system cost.
図 4 shows the block diagram of the delay matched LO distribution. 図 5 shows the implementedWilkinson power dividers in GCPW transmission-line. Fanout from the AWR1243P devices and powerdividers is through GCPW lines. The majority of the LO distribution length is carried through an internalStripline layer.
System Overviewwww.tij.co.jp
10JAJU738–June 2019
TIDUEQ8 翻訳版 — 最新の英語版資料 http://www-s.ti.com/sc/techlit/TIDUEQ8
Copyright © 2019, Texas Instruments Incorporated
Jacinto™ ADAS プロセッサを使用するカスケード接続イメージング・レーダー・キャプチャのリファレンス・デザイン
図図 4. 20-GHz LO Distribution Block Diagram
図図 5. 20-GHz LO Distribution Board Implementation
www.tij.co.jpSystem Overview
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2.3Highlighted Products
2.3.1TDA2SXBTQABCQ1
TI’s new TDA2x System-on-Chip (SoC) is a highly optimized and scalable family of devices designed tomeet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2x familyenables broad ADAS applications in automobiles by integrating an optimal mix of performance, low powerand ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free drivingexperience.
The TDA2x SoC enables sophisticated embedded vision technology in automobiles by broadest range ofADAS applications including front camera, park assist, surround view and sensor fusion on a singlearchitecture.
The TDA2x SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed andfloating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm®
Cortex®-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator fordecoding multiple video streams over an Ethernet AVB network, along with graphics accelerators forrendering virtual views, enable a 3D viewing experience. And the TDA2x SoC also integrates a host ofperipherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround viewsystems, displays, CAN and GigB Ethernet AVB.
The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs)offloading the vision analytics functionality from the application processor while also reducing the powerfootprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core forefficient program execution and a vector coprocessor for specialized vision processing.
Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor,including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and adebugging interface for visibility into source code execution.
2.3.2TPS43351-Q1
The and TPS43351-Q1 device includes two current-mode synchronous buck controllers designed for theharsh environment in automotive applications. The device is ideal for use in a multi-rail system with lowquiescent requirements, because it automatically operates in low-power mode (consuming typically 30 µA)at light loads. The device offers protection features such as thermal, soft-start, and overcurrent protection.During short-circuit conditions of the regulator output, activation of the current-foldback feature can limitthe current through the MOSFETs for control of power dissipation. The two independent soft-start inputsallow ramp-up of the output voltage independently during start-up.
The programmable range of the switching frequency is from 150 kHz to 600 kHz, as is the frequency of anexternal clock to which the devices can synchronize. Additionally, the TPS43351-Q1 device offersfrequency-hopping, spread-spectrum operation.
2.3.3TPS62262-Q1
The TPS6226x-Q1 devices are high-efficiency synchronous step-down dc-dc converters optimized forbattery-powered applications. The devices provide up. to. 600-mA output current from a single Li-Ion cell
and are ideal to power mobile phones and other portable applications.
With a wide input voltage range of 2 V to 6 V, the device supports applications powered by Li-Ion batterieswith extended voltage range, two- and three-cell alkaline batteries, 3.3-V and 5-V input voltage rails.
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The TPS6226x-Q1 devices operate at 2.25-MHz fixed switching frequency and enter power-save-modeoperation at light load currents to maintain high efficiency over the entire load-current range.
The power-save mode is optimized for low output-voltage ripple. For low-noise applications, the devicescan be forced into fixed-frequency PWM mode by pulling the MODE pin high. In the shutdown mode, thecurrent consumption is reduced to less than 1 μA. The TPS6226x-Q1 devices allow the use of smallinductors and capacitors to achieve a small solution size.
2.3.4TPS659039-Q1
The TPS659039-Q1 device is an integrated power-management integrated circuit (PMIC) for automotiveapplications. The device provides seven configurable step-down converters with up to 6 A of outputcurrent for memory, processor core, input-output (I/O), or preregulation of LDOs. One of theseconfigurable step-down converters can be combined with another 3-A regulator to allow up to 9 A ofoutput current. All of the step-down converters can synchronize to an external clock source between 1.7MHz and 2.7 MHz, or an internal fall back clock at 2.2 MHz. The TPS659039-Q1 device contains six LDOregulators for external use. This LDO regulator can be supplied from either a system supply or apreregulated supply. The power-up and power-down controller is configurable and supports any power-upand power-down sequences (OTP based). The TPS659039-Q1 device includes a 32-kHz RC oscillator tosequence all resources during power up and power down. In cases where a fast start up is needed, a 16-MHz crystal oscillator is also included to quickly generate a stable 32-kHz for the system. All LDOs andSMPS converters can be controlled by the SPI or I2C interface, or by power request signals. In addition,voltage scaling registers allow transitioning the SMPS to different voltages by SPI, I2C, or roof and floorcontrol. One dedicated pin in each package can be configured as part of the power-up sequence to controlexternal resources. General-purpose input-output (GPIO) functionality is available and two GPIOs can beconfigured as part of the power-up sequence to control external resources. Power request signals enablepower mode control for power optimization. The device includes a general-purpose (GP) sigma-deltaanalog-to-digital converter (ADC) with three external input channels. The TPS659039- Q1 device isavailable in a 13-ball × 13-ball nFBGA package with a 0,8-mm pitch.
2.3.5TPS57112-Q1
The TPS57112-Q1 device is a full-featured 6-V, 2-A, synchronous step-down current-mode converter withtwo integrated MOSFETs.
The TPS57112-Q1 device enables small designs by integrating the MOSFETs, implementing current-mode control to reduce external component count, reducing inductor size by enabling up to 2-MHzswitching frequency, and minimizing the IC footprint with a small 3-mm × 3-mm thermally enhanced QFNpackage.
The TPS57112-Q1 device provides accurate regulation for a variety of loads with a ±1% voltage reference(Vref) over temperature.
The integrated 12-mΩ MOSFETs and 515-μA typical supply current maximize efficiency. Using the enablepin to enter the shutdown mode reduces supply current to 5.5 µA, typical.
The internal undervoltage lockout setting is 2.45 V, but programming the threshold with a resistor networkon the enable pin can increase the setting. The slow-start pin controls the output-voltage start-up ramp. Anopen-drain power-good signal indicates when the output is within 93% to 107% of its nominal voltage.
Frequency foldback and thermal shutdown protect the device during an overcurrent condition.
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2.3.6TPS51200-Q1
The TPS51200-Q1 device is a sink and source double-data-rate (DDR) termination regulator specificallydesigned for low input voltage, low-cost, low-noise systems where space is a key consideration.
The TPS51200-Q1 device maintains a fast transient response and only requires a minimum outputcapacitance of 20 μF. The TPS51200-Q1 device supports a remote sensing function and all powerrequirements for DDR, DDR2, DDR3, DDR3L, low power DDR3 and DDR4 VTT bus termination.
In addition, the TPS51200-Q1 device provides an open-drain PGOOD signal to monitor the outputregulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDRapplications.
The TPS51200-Q1 device is available in the thermally-efficient VSON-10 package, and is rated both greenand Pb-free. The device is specified from –40°C to 125°C.
2.3.7TPS74801-Q1
The TPS74801-Q1 low-dropout (LDO) linear regulator provides an easy-to-use robust power managementsolution for a wide variety of applications. User-programmable soft-start minimizes stress on the inputpower source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well-suitedfor powering many different types of processors and ASICs. The enable input and power good outputallow easy sequencing with external regulators. This complete flexibility permits the user to configure asolution that meets the sequencing requirements of FPGAs, DSPs, and other applications with specialstart-up requirements.
A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process.The device is stable with any type of capacitor greater than or equal to 2.2 μF, and is fully specified from–40°C to 105°C for the DRC package, and from –40°C to 125°C for the RGW package. The TPS74801-Q1 device is offered in a small 3-mm × 3-mm VSON-10 package, yielding a highly compact, total solutionsize. It is also available in a 5 × 5 QFN-20 for compatibility with the TPS74401.
2.3.8LP5907-Q1
The LP5907-Q1 is a low-noise LDO that can supply 250 mA of output current. Designed to meet therequirements of RF and analog circuits, the LP5907-Q1 provides low noise, high PSRR, low quiescentcurrent, and low line or load transient response figures. Using new innovative design techniques, theLP5907-Q1 offers class-leading noise performance without a noise bypass capacitor and the ability forremote output capacitor placement.
The device is designed to work with a 1-µF input and a 1-µF output ceramic capacitor (no separate noisebypass capacitor is required).
This device is available with fixed output voltages from 1.2 V to 4.5 V in 25-mV steps. Contact TexasInstruments Sales for specific voltage option needs.
2.3.9DP83867
The DP83867 device is a robust, low power, fully featured Physical Layer transceiver with integrated PMDsublayers to support 10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols. Optimized for ESDprotection, the DP83867 exceeds 8-kV IEC 61000-4-2 (direct contact).
The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. Ithas low latency and provides IEEE 1588 Start of Frame Detection.
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3Hardware, Software, Testing Requirements, and Test Results
3.1Required Hardware and Software
3.1.1Hardware
図 6 shows the parts on the CPU.
図図 6. CPU Board – Front
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3.1.1.1Boot Mode
表 5 lists the supported boot modes. A ‘1’ for the switch configuration indicates ‘ON’, a ‘0’ for the switchconfiguration indicates ‘OFF’
表表 5. Supported Boot Modes
BOOT MODESW1 CONFIGURATION [5:0]
USB boot010000
UART boot010011
eMMC boot111000
eMMC boot partition111011
SD boot110000
3.1.1.2User Pushbuttons
There are three user pushbuttons on the design, as described in 表 6.
表表 6. Pushbutton Table
PUSHBUTTONDESCRIPTION
S1Board On/Off. By default button is disabled. Refer toSCH for resistor options.
S2Generates a PORz reset
S3Generates a RESETz on SoC
3.1.2Software
VSDK 3.07 contains algorithms that run on the TDA2x for the Cascade Radar application. The latestVSDK is available at from Processor SDK for TDAx ADAS SoCs - Linux and TI-RTOS Support.
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3.2Testing and Results
Multiple test scenarios were setup to explore the capabilities of the Cascade Radar RF design in bothMIMO and TX beamforming operation.
All data presented here was collected with the hardware mentioned in 3.1.1.
3.2.1Required Hardware
All data presented here was collected on the AWR1243P Cascade RF board through the TSW14J56-based data capture board. The Imaging Radar Using Cascaded AWR1243P mmWave Radar DesignGuide contains these same results.
3.2.2Test Setup
Multiple test scenarios were set up to explore the capabilities of the Cascade Radar RF design in bothMIMO and TX beamforming operation.
3.2.2.1MIMO Test Scenarios
•In-lab Angular Resolution
•Side-by-side Car Detection Resolution
•Side-by-side Car Detection Resolution – MUSIC Application
•Car, Pedestrian and Other Targets Close Range Separation
•Car Contour and Orientation
•Car Door Contour
•Bike Contour and Orientation
•Fence Contour Detection
•Curb Contour Detection
•Manhole Contour Detection
•Height Measurement
•Single-Device vs. Cascade Devices
3.2.2.2TX Beamforming Test Scenarios
•In-lab Beamforming Control Pattern
•Pedestrian Long-Range Detection
•Car Medium-Range detection
•Car Long-Range Detection
3.2.3MIMO Test Results
3.2.3.1In-lab Angular Resolution
A basic azimuth separation test was performed within an anechoic chamber radar test range. Two cornerreflectors were placed approximately 8 m from the AWR1243P radar sensor. 1.5 degrees of azimuthseparation was applied to the reflectors and the resulting azimuth resolution was measured.
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In the current configuration, with 96 virtual array elements in the azimuth axis, and lambda/2 spacing ofeach element, a best-case 1.4 degree angular resolution is possible. This system measured a 1.5 degreeseparation, which is in close alignment to the expected.
図図 7. Two Corner Reflectors Separated by 1.5 Degrees in Azimuth
図図 8. Range-Doppler FFT Plots Showing Detected, Separated Peaks From Both Reflectors
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3.2.3.2Car Angular Resolution Scenario
A test was performed with two cars located at 112 m range from the sensor at varying angularseparations, again showing the angular resolution capabilities of the AWR1243P MIMO radar operation.
図図 9. Two-Car Angular Separation Test Setup
図図 10. Two-Car Angular Separation Test Results
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3.2.3.3Car, Pedestrian, and Other Targets Close Range Separation
A test was performed showing the AWR1243P MIMO radar is able to separate a person and a bicycle atdifferent lateral distances away from the car. This represents a more challenging scenario due to thepedestrian (or another low RCS object) occupying the same range bin as the high reflecting point from thecar (high RCS object).
図図 11. Bicycle and Person 1.5 m Away From Vehicle
図図 12. Bicycle and Person 1.0 m (Left) and 0.5 m (Right) Away From Vehicle
3.2.3.4Car Contour and Orientation
A test was performed showing the AWR1243P MIMO radar detecting the contour and orientation of a car.The azimuth and range resolution allows for the detection of the contour of many vehicle surfaces.
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図図 13. Car at 0 Degrees (Top), 90 Degrees (Middle) and 135 Degrees (Bottom) Orientation and
Corresponding Azimuth Range Heatmap
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3.2.3.5Curb Contour Detection
A test was performed showing the AWR1243P MIMO radar detecting the contour and orientation ofmultiple curbs in a parking lot setting. The azimuth and range resolution allows for the detection of thecontour of these shorter driving obstacles.
図図 14. Parking Lot Curb Scene (Top), and Resulting Azimuth Range Heatmap (Bottom)
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3.2.4TX Beamforming Results
3.2.4.1In-lab Beamforming Control Pattern
A basic beam steering test was performed within an anechoic chamber radar test range. A single cornerreflector was placed approximately 8 m from the AWR1243P radar sensor. Beamsteering vectors werethen programmed into the AWR1243P devices to achieve a 15 degree beam rotation. The resulting targetreturn versus angle graph was then compared against the simulated 15-degree beam rotation pattern.
Close alignment between the simulated and measured system was observed.
図図 15. Simulated (Top) and Measured (Bottom) 15 Degree Beam Steering Test
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3.2.4.2Pedestrian Long-Range Detection
In this test a pedestrian jogging from 30 m to 140 m. The AWR1243P Cascade RF board is running in 9-TX beamforming mode.
The range profile shows the pedestrian at 120 m with 20-dB SNR. The Doppler-Range plot is shown tothe right. Slight Doppler displacement can be seen corresponding to the pedestrian velocity.
図図 16. Range Profile (Top Left), and Doppler-Range Plot of a Pedestrian Jogging Away From Radar at
120-m Range
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3.2.4.3Car Long-Range Detection
Similar to the pedestrian long range detection test, this test observes a car at 350-m range. TheAWR1243P Cascade RF board is running in 9-TX beamforming mode.
The range profile shows the vehicle at 350 m with 14-dB SNR.
図図 17. Range Profile (Left), and Doppler-Range Plot of a Vehicle 350-m Range
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4Design Files
4.1Schematics
To download the schematics, see the design files at TIDEP-01017.
4.2Bill of Materials
To download the bill of materials (BOM), see the design files at TIDEP-01017.
4.3Altium Project
To download the Altium Designer® project files, see the design files at TIDEP-01017.
4.4Gerber Files
To download the Gerber files, see the design files at TIDEP-01017.
4.5Assembly Drawings
To download the assembly drawings, see the design files at TIDEP-01017.
5Software Files
VSDK 3.07 contains algorithms that run on the TDA2x for the Cascade Radar application. The latestVSDK is available at from Processor SDK for TDAx ADAS SoCs - Linux and TI-RTOS Support.
6Related Documentation1. Texas Instruments, Programming Chirp Parameters in TI Radar Devices Application Report2. Texas Instruments, AWR1243 76-GHz to 81-GHz high-performance automotive MMIC3. Texas Instruments, AWR1243 Cascade Application Report4. Texas Instruments, MMWAVE-STUDIO
6.1商商標標
E2E is a trademark of Texas Instruments.Altium Designer is a registered trademark of Altium LLC or its affiliated companies.Arm, Cortex are registered trademarks of Arm Limited.すべての商標および登録商標はそれぞれの所有者に帰属します。
6.2Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOESNOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS ORSERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS ORSERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
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