4mm X 4mm QFN Package
EMI Filtering
EMI Filtering
0 5k 10k 15k 20k
Amplitude (dBc) 
Frequency (Hz) C005 
-133.6 dBc (Second Harmonic) 
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA1620
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INA1620 High-Fidelity Audio Operational Amplifier With Integrated Thin-Film Resistors
and EMI Filters
1Features
1•High-Quality Thin-Film ResistorsMatched to 0.004% (Typical)
•Integrated EMI Filters
•Ultra-low Noise: 2.8 nV/√Hz at 1 kHz
•Ultra-low Total Harmonic Distortion + Noise:–119 dB THD+N (142 mW/Ch Into 32 Ω/Ch)
•Wide Gain Bandwidth Product:32 MHz (G = +1000)
•High Slew Rate: 10 V/μs
•High Capacitive-Load Drive Capability: > 600 pF
•High Open-Loop Gain: 136 dB (600-Ω Load)
•Low Quiescent Current: 2.6 mA per Channel
•Low-Power Shutdown Mode With Reduced Pop-and-Click Noise: 5 μA per Channel
•Short-Circuit Protection
•Wide Supply Range: ±2 V to ±18 V
•Available in Small 24-pin WQFN Package
2Applications
•High-Fidelity (HiFi) Headphone Drivers
•Professional Audio Equipment
•Analog and Digital Mixing Consoles
•Audio Test and Measurement
3Description
The INA1620 integrates 4 precision-matched thin-filmresistor pairs and EMI filtering on-chip with a low-distortion, high output current, dual audio operationalamplifier. The amplifier achieves a very low,2.8-nV/√Hz noise density with an ultra-low THD+N of–119.2 dB at 1 kHz and drives a 32-Ω load at 150-mW output power. The integrated thin-film resistorsare matched to within 0.004% and can be used tocreate a large number of very high-performanceaudio circuits.
The INA1620 operates over a very wide supply rangeof ±2 V to ±18 V on only 2.6 mA of supply current perchannel. The INA1620 also has a shutdown mode,allowing the amplifiers to be switched from normaloperation to a standby current that is typically lessthan 5 µA. Shutdown mode is specifically designed toeliminate click-and-pop noise when transitioning intoor out of shutdown mode.
The INA1620 has a unique internal layout for lowestcrosstalk, and freedom from interactions betweenchannels, even when overdriven or overloaded. Thisdevice is specified from –40°C to +125°C.
Device Information(1)
PART NUMBERPACKAGEBODY SIZE (NOM)
INA1620WQFN (24)4.00 mm × 4.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
INA1620 Simplified Internal SchematicFFT: 1 kHz, 32-Ω Load, 50 mW
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Table of Contents
1Features.................................................................. 1
2Applications ........................................................... 1
3Description ............................................................. 1
4Revision History..................................................... 2
5Pin Configuration and Functions......................... 3
6Specifications......................................................... 46.1Absolute Maximum Ratings ...................................... 4
6.2ESD Ratings.............................................................. 4
6.3Recommended Operating Conditions....................... 4
6.4Thermal Information.................................................. 4
6.5Electrical Characteristics: ........................................ 5
6.6Typical Characteristics.............................................. 7
7Detailed Description ............................................ 157.1Overview ................................................................. 15
7.2Functional Block Diagram ....................................... 15
7.3Feature Description................................................. 15
7.4Device Functional Modes........................................ 18
8Application and Implementation ........................ 208.1Application Information............................................ 20
8.2Typical Application ................................................. 24
8.3Other Application Examples.................................... 27
9Power Supply Recommendations...................... 28
10Layout................................................................... 2810.1Layout Guidelines ................................................. 28
10.2Layout Example .................................................... 28
11Device and Documentation Support ................. 2911.1Device Support...................................................... 29
11.2Documentation Support ........................................ 29
11.3Receiving Notification of Documentation Updates 29
11.4Community Resources.......................................... 29
11.5Trademarks........................................................... 30
11.6Electrostatic Discharge Caution............................ 30
11.7Glossary................................................................ 30
12Mechanical, Packaging, and OrderableInformation ........................................................... 30
4Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2018) to Revision APage
•First release of production-data data sheet ........................................................................................................................... 1
789101112
192021222324
ThermalPad
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5Pin Configuration and Functions
RTW Package
24-Pin QFNTop View
Pin Functions
I/ODESCRIPTION
NAMENO.
GND3—Connect to ground
EN16IShutdown (logic low), enable (logic high)
IN+ A22INoninverting input, channel A
IN- A21IInverting input, channel A
IN+ B9INoninverting input, channel B
IN- B10IInverting input, channel B
NC4—No internal connection
NC15—No internal connection
OUT A17OOutput, channel A
OUT B14OOutput, channel B
R1A24—Resistor pair 1, end point A
R1B23—Resistor pair 1, center point
R1C1—Resistor pair 1, end point C
R2A19—Resistor pair 2, end point A
R2B20—Resistor pair 2, center point
R2C18—Resistor pair 2, end point C
R3A12—Resistor pair 3, end point A
R3B11—Resistor pair 3, center point
R3C13—Resistor pair 3, end point C
R4A7—Resistor pair 4, end point A
R4B8—Resistor pair 4, center point
R4C6—Resistor pair 4, end point C
V+2—Positive (highest) power supply
V–5—Negative (lowest) power supply
Thermal padExposed thermal die pad on underside; connect thermal die pad to V–.
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(1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.
6Specifications
6.1Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
Voltage
Supply voltage, VS = (V+) – (V–)40
VInput voltage (signal inputs, enable, ground)(V–) – 0.5(V+) + 0.5
Input differential voltage±0.5
Current
Input current (all pins except power-supply and resistor pins)±10
Through each resistor30
Output short-circuit(2)Continuous
Temperature
Operating, TA–55125
°CJunction, TJ150
Storage, Tstg–65150
(1)JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2ESD Ratings
VALUEUNIT
V(ESD)Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±1000
6.3Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
Supply voltage, (V+) – (V–)
Single-supply436
Dual-supply±2±18
Current per resistor15mA
Specified temperature–40125°C
(1)For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.
6.4Thermal Information
THERMAL METRIC(1)
INA1620
UNITRTW (QFN)
24 PINS
RθJAJunction-to-ambient thermal resistance33.7°C/W
RθJC(top)Junction-to-case (top) thermal resistance26.5°C/W
RθJBJunction-to-board thermal resistance13.1°C/W
ψJTJunction-to-top characterization parameter0.3°C/W
ψJBJunction-to-board characterization parameter13.1°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance3.8°C/W
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(1)Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
(2)Specified by design and characterization.
6.5Electrical Characteristics:
at TA = 25°C, VS = ±2 V to ±18 V, VCM = VOUT = midsupply, and RL = 1 kΩ (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
AUDIO PERFORMANCE
THD+NTotal harmonic distortion +noise
G = 1, f = 1 kHz, VOUT = 3.5 VRMS, RL = 2 kΩ,80-kHz measurement bandwidth
0.000025%
–132dB
G = 1, f = 1 kHz, VOUT = 3.5 VRMS, RL = 600 Ω,80-kHz measurement bandwidth
0.000025%
–132dB
G = 1, f = 1 kHz, POUT = 10 mW, RL = 128 Ω,80-kHz measurement bandwidth
0.000071%
–123dB
G = 1, f = 1 kHz, POUT = 10 mW, RL = 32 Ω,80-kHz measurement bandwidth
0.000158%
–116dB
G = 1, f = 1 kHz, POUT = 10 mW, RL = 16 Ω,80-kHz measurement bandwidth
0.000224%
–113dB
IMDIntermodulation distortion
SMPTE/DIN two-tone, 4:1 (60 Hz and 7 kHz),G = 1, VO = 3 VRMS, RL = 2 kΩ, 90-kHz measurementbandwidth
0.000018%
–135dB
CCIF twin-tone (19 kHz and 20 kHz), G = 1,VO = 3 VRMS, RL = 2 kΩ, 90-kHz measurement bandwidth
0.000032%
–130dB
FREQUENCY RESPONSE
GBWGain-bandwidth product
G = 100032
G = 18
SRSlew rateG = –110V/μs
Full-power bandwidth(1)VO = 1 VP1.6MHz
Overload recovery timeG = –10300ns
Channel separation (dual)f = 1 kHz140dB
EMI filter corner frequency500MHz
Input voltage noisef = 20 Hz to 20 kHz2.1μVPP
enInput voltage noise density(2)
f = 10 Hz6.5
nV/√Hzf = 100 Hz3.5
f = 1 kHz2.8
InInput current noise density
f = 10 Hz1.6
pA/√Hz
f = 1 kHz0.8
OFFSET VOLTAGE
VOSInput offset voltage
±0.1±1
TA = –40°C to 125°C±1.2
dVOS/dTInput offset voltage drift(2)TA = –40°C to 125°C-0.5±2.5μV/°C
PSRRPower-supply rejection ratio0.13μV/V
INPUT BIAS CURRENT
IBInput bias current
TA = –40°C to 125°C(2)2.2
IOSInput offset current
±10±100
TA = –40°C to 125°C(2)±140
INPUT VOLTAGE RANGE
VCMCommon-mode voltage range(V–) + 1.5(V+) – 1V
CMRRCommon-mode rejection ratio(V–) + 1.5 V ≤ VCM ≤ (V+) – 1 V, TA = –40°C to 125°C, VS= ±18 V108127dB
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Electrical Characteristics: (continued)
at TA = 25°C, VS = ±2 V to ±18 V, VCM = VOUT = midsupply, and RL = 1 kΩ (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
(3)Resistor ratio matching refers to the matching between the two 1-kΩ resistors in each resistor pair. There are four pairs on eachINA1620: RXA, RXB, RXC and RXD, where X is the terminal connection number. See Resistor Tolerancefor more details.
INPUT IMPEDANCE
Differential60k || 0.8Ω || pF
Common-mode500M || 0.9Ω || pF
OPEN-LOOP GAIN
AOLOpen-loop voltage gain
(V–) + 2 V ≤ VO ≤ (V+) – 2 V, RL = 32 Ω, VS = ± 5 V114120
(V–) + 1.5 V ≤ VO ≤ (V+) – 1.5 V, RL = 600 Ω, VS = ± 18 V120136
OUTPUT
VOVoltage output swing from rail
Positive rail
No load800
RL = 600 Ω1000
Negative rail
No load800
RL = 600 Ω1000
IOUTOutput currentFigure 38mA
ZOOpen-loop output impedanceFigure 40Ω
ISCShort-circuit currentVS = ±18 V+145 / –130mA
CLOADCapacitive load driveFigure 24pF
ENABLE PIN
VIHLogic high threshold
TA = –40°C to 125°C(2)0.95
VILLogic low threshold
TA = –40°C to 125°C(2)0.65
IIHInput currentVEN = 1.8 V1.5μA
RESISTOR PAIRS
Resistor ratio matching(3)Resistors in same pair0.004%0.02%
TA = –40°C to 125°C(2)0.023%
Resistor ratio matchingtemperature coefficientResistors in same pair±0.07±0.15ppm/°C
Individual resistor value0.8411.15kΩ
Individual resistor temperaturecoefficient220ppm/°C
POWER SUPPLY
Quiescent current(per channel)
VEN = 2 V, IOUT = 0 A
2.63.3
TA = –40°C to 125°C(2)4.2
VEN = 0 V, IOUT = 0 A510μA
110100 1k 10k 100k 1M 10M 100M
9ROWDJH�1RLVH�6SHFWUDO�'HQVLW\\ufffd�Q9�¥+]� 
Frequency (Hz) C307 
110100 1k 10k 100k 1M 10M 100M
&XUUHQW�1RLVH�6SHFWUDO�'HQVLW\\ufffd�S$�¥+]� 
Frequency (Hz) C306 
±75 ±50 ±25 0255075100125150
VOS (�V) 
Temperature (ƒC) C001 
±20 ±10 01020
VOS (µV) 
VCM (V) C001 
VCM = -16.5 V 
VCM = 17 V 
VOS (PV)
Amplifiers (%)
-1000-900-800-700-600-500-400-300-200-10001002003004005006007008009001000
VOS Drift (PV/qC)
Amplifiers (�)
-1.5-1.4-1.3-1.2-1.1-1-0.9-0.8-0.7-0.6-0.5-0.4-0.3-0.2-0.100.10.20.30.40.50.60.70.80.91.0
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6.6Typical Characteristics
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
9818 channels
Figure 1. Input Offset Voltage Histogram
50 channels
Figure 2. Input Offset Voltage Drift Histogram
4 typical units
Figure 3. Input Offset Voltage vs TemperatureFigure 4. Input Offset Voltage vs Common-Mode Voltage
Figure 5. Input Voltage Noise Spectral Density vs FrequencyFigure 6. Input Current Noise Spectral Density vs Frequency
±75 ±50 ±25 0255075100125150
AOL (µV/V) 
Temperature (ƒC) C001 
VS = ±18 V 
VS = ±2 V 
±75 ±50 ±25 0255075100125150
AOL (µV/V) 
Temperature (ƒC) C001 
VS = ±18 V 
VS = ±2 V 
 10k 100k1M10M
Output Amplitude (VP) 
Frequency (Hz) C303 
VS = ±5V 
VS = ±2V 
VS = ±15V 
110100 1k 10k 100k1M10M100M
Phase (º) 
Gain (dB) 
Frequency (Hz) C005 
50 nV/div 
Time (2 s/div) 
10100 1k 10k 100k1M
9ROWDJH�1RLVH�6SHFWUDO�'HQVLW\\ufffd�Q9�¥+]� 
Source Resistance (�) C302 
Current Noise Contribution 
Voltage Noise Contribution 
Total Noise 
Source Resistor Noise Contribution 
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
Figure 7. 0.1-Hz to 10-Hz NoiseFigure 8. Voltage Noise vs Source Resistance
Figure 9. Maximum Output Voltage vs FrequencyFigure 10. Open-Loop Gain and Phase vs Frequency
600-Ω load
Figure 11. Open-Loop Gain vs Temperature
2-kΩ load
Figure 12. Open-Loop Gain vs Temperature
0.00001
0.0001
0.010.1110
Total Harmonic Distortion + Noise (dB) 
Total Harmonic Distortion + Noise (%) 
Output Amplitude (VRMS) 
128-��Load 32-��Load 16-��Load 
Inverting 
Noninverting 
0.00001
0.0001
0.0010.010.1110
Intermodulation Distortion (dB) 
Intermodulation Distortion (%) 
Output Amplitude (VRMS)  
2k-��Load 32-��Load 
SMPTE 
0.00001
0.0001
20200 2k 20k
Total Harmonic Distortion + Noise (dB) 
Total Harmonic Distortion + Noise (%) 
Frequency (Hz) 
G = -1, 128-��Load G = -1, 32-��Load G = -1, 16-��Load G = +1, 128-��Load G = +1, 32-��Load G = +1, 16-��Load 
0.00001
0.0001
0.010.1110
Total Harmonic Distortion + Noise (dB) 
Total Harmonic Distortion + Noise (%) 
Output Amplitude (VRMS) 
2k-��Load 600-��Load 
Inverting 
Noninverting 
0.00001
0.0001
20200 2k 20k
Total Harmonic Distortion + Noise (dB) 
Total Harmonic Distortion + Noise (%) 
Frequency (Hz) 
G = -1, 600-��Load G = -1, 2k-��Load G = -1, 10k-��Load G = +1, 600-��Load G = +1, 2k-��Load G = +1, 10k-��Load 
100 1k 10k 100k 1M 10M
Gain (dB) 
Frequency (Hz) 
G = +10G = -1G = +1
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
Figure 13. Closed-Loop Gain vs Frequency
3.5 VRMS, 80-kHz measurement bandwidth
Figure 14. THD+N Ratio vs Frequency
10 mW, 80-kHz measurement bandwidth
Figure 15. THD+N Ratio vs Frequency
1 kHz, 80-kHz measurement bandwidth
Figure 16. THD+N Ratio vs Output Amplitude
1 kHz, 80-kHz measurement bandwidth
Figure 17. THD+N Ratio vs Output Amplitude
90-kHz measurement bandwidth
Figure 18. Intermodulation Distortion vs Output Amplitude
±75 ±50 ±25 0255075100125150
Common-Mode Rejection Ratio (µV/V) 
Temperature (ƒC) C001 
VS = ±18 V,  (V±) �����”�9CM ”��9���± 1V 
VS = ±2 V,  (V±) �����”�9CM ”��9���± 1 V 
02004006008001000
Phase Margin (º) 
Capacitive Load (pF) C308 
G = +1 
G = -1 
110100 1k 10k 100k 1M 10M
Common-mode Rejection Ratio (dB) 
Frequency (Hz) C004 
±75 ±50 ±25 0255075100125150
Power-Supply Rejection Ratio (µV/V) 
Temperature (ƒC) C001 
100 1k 10k 100k 1M 10M
Crosstalk (dB) 
Frequency (Hz) 
No Load32-��Load 600-��Load 
110100 1k 10k 100k 1M 10M
Power Supply Rejection Ratio (dB) 
Frequency (Hz) C115 
PSRR- 
PSRR+ 
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
Figure 19. Channel Separation vs FrequencyFigure 20. PSRR vs Frequency (Referred to Input)
Figure 21. PSRR vs TemperatureFigure 22. CMRR vs Frequency (Referred to Input)
Figure 23. CMRR vs TemperatureFigure 24. Phase Margin vs Capacitive Load
5 V/div 
Time (500 ms/div) 
VOUT VIN 
±50 ±25 0255075100125
Input Bias Current (�A) 
Temperature (ºC) 
5 V/div 
Time (200 ns/div) 
5 V/div 
Time (200 ns/div) 
2 mV/div 
Time (2.5 �s/div) 
2 V/div 
Time (2.5 �s/div) 
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
G = 1, 10 mV
Figure 25. Small-Signal Step Response
G = 1, 10 V
Figure 26. Large-Signal Step Response
G = –10
Figure 27. Negative Overload Recovery
G = –10
Figure 28. Positive Overload Recovery
Figure 29. No Phase ReversalFigure 30. IB vs Temperature
02468101214161820
IQ (mA) 
Supply Voltage (V) C001 
0.511.52
IQ (mA) 
Enable Voltage (V) C002 
125ºC 85ºC 
-40ºC 25ºC 
-1.5-1-0.500.511.5
Input Bias Current (�A) 
Common-Mode Voltage (V) C002 
±75 ±50 ±25 0255075100125150
IQ (mA) 
Temperature (ƒC) C001 
VS = ±18 V 
VS = ±2 V 
-20-1001020
Input Bias Current (�A) 
Common-Mode Voltage (V) C001 
±50 ±25 0255075100125
Input Offset Current (nA) 
Temperature (ºC) C305 
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
Figure 31. IOS vs Temperature
VS = ±18 V
Figure 32. IB vs Common-Mode Voltage
VS = ±2 V
Figure 33. IB vs Common-Mode VoltageFigure 34. Quiescent Current vs Temperature
Figure 35. Quiescent Current vs Supply VoltageFigure 36. Quiescent Current vs Enable Voltage
Resistor Ratio Matching Error (%)
Resistors (%)
-0.016
-0.012
-0.008
-0.004
Resistance (:)
Resistors (%)
925930935940945950955960965970975980985990995100010051010101510201025
110100 1k 10k 100k1M10M100M
ZO (�) 
Frequency (Hz) C001 
020406080100120140160180200
VO (V) 
IO (mA)    C001 
125°C 
±40°C 
±75 ±50 ±25 0255075100125150
ISC (mA) 
Temperature (ƒC) C001 
ISC, Sink 
ISC, Source 
020406080100120140160180200
VO (V) 
IO (mA)    C001 
±40°C 
25°C 125°C 
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
Figure 37. Short-Circuit Current vs TemperatureFigure 38. Positive Output Voltage vs Output Current
Figure 39. Negative Output Voltage vs Output CurrentFigure 40. Open-Loop Output Impedance vs Frequency
19635 resistors
Figure 41. Resistor Absolute Value Histogram
19639 resistor pairs
Figure 42. Resistor Pair Matching Histogram
Resistor Ratio Matching Drift (ppm/qC)
Resistor Pairs (�)
-0.15-0.14-0.13-0.12-0.11-0.1-0.09-0.08-0.07-0.06-0.05-0.04-0.03-0.02-0.0100.010.020.030.040.05
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 2 kΩ (unless otherwise noted)
64 resistor pairs
Figure 43. Resistor Pair Matching Drift Histogram
4mm X 4mm QFN Package
EMI Filtering
EMI Filtering
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7Detailed Description
7.1Overview
The INA1620 integrates a dual, bipolar-input, audio operational amplifier with four high-precision thin-film resistorpairs on the same die. The internal amplifiers and resistor pairs are pinned out to allow for many circuitconfigurations.
The internal amplifiers of the INA1620 use a unique topology to deliver high output current with extremely lowdistortion while consuming minimal supply current. A single gain-stage architecture, combining a high-gaintransconductance input stage and a unity-gain output stage, allows the INA1620 to achieve an open-loop gain of136 dB, even with 600-Ω loads.
A separate enable circuit maintains control of the input and output stage when the amplifier is placed into itsshutdown mode and limits transients at the amplifier output when transitioning to and from this state. The enablecircuit features logic levels referenced to the amplifier ground pin. This configuration simplifies the interfacebetween the amplifier and the ground-referenced GPIO pins of microcontrollers. The addition of a ground pin tothe amplifier provides several additional benefits. For example, the compensation capacitor between the inputand output stages of the INA1620 is referenced to the ground pin, greatly improving PSRR.
7.2Functional Block Diagram
7.3Feature Description
7.3.1Matched Thin-Film Resistor Pairs
The INA1620 integrates four thin-film resistor pairs. Each pair is made up of two thin-film resistors with a nominalresistance of 1 kΩ. While the absolute value of the resistor is not trimmed and can vary significantly, the tworesistors in an pair are designed to match each other extremely well. The resistors in an pair typically match towithin 0.004% of each other's value. This matching is also preserved well over temperature, with the matchingdrift having a 0.2 ppm/°C maximum specification. Each node in the resistor pair is bonded out to a pad on the
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Feature Description (continued)
INA1620 package allowing the resistor pairs to be used in multiple configurations. The nodes in the pair areprotected from damage due to electrostatic discharge (ESD) events by diodes tied to the power supplies of theIC. For this reason, voltages beyond the power supplies cannot be applied to the resistors without forward-biasing the ESD protection diodes. The resistor pairs should not be used if there is no power applied to theINA1620. The configuration of the ESD protection diodes is shown in Figure 44.
Figure 44. ESD Protection Diodes on Each Resistor Pair
Although the resistor pairs and amplifier core are fabricated on the same silicon substrate, they can be used inseparate circuits as long as the previously-mentioned voltage limits are observed. The functional state of theamplifier (enabled or shutdown) does not affect the resistor pair's performance.
7.3.2Power Dissipation
The INA1620 is capable of high output current with power-supply voltages up to ±18 V. Internal power dissipationincreases when operating at high supply voltages. The power dissipated in the op amp (POPA) is calculated usingEquation 1:
In order to calculate the worst-case power dissipation in the op amp, the ac and dc cases must be consideredseparately.
In the case of constant output current (dc) to a resistive load, the maximum power dissipation in the op ampoccurs when the output voltage is half the positive supply voltage. This calculation assumes that the op amp issourcing current from the positive supply to a grounded load. If the op amp sinks current from a grounded load,modify Equation 2 to include the negative supply voltage instead of the positive.
The maximum power dissipation in the op amp for a sinusoidal output current (ac) to a resistive load occurswhen the peak output voltage is 2/π times the supply voltage, given symmetrical supply voltages:
The dominant pathway for the INA1620 to dissipate heat is through the package thermal pad and pins to thePCB. Copper leadframe construction used in the INA1620 improves heat dissipation compared to conventionalmaterials. PCB layout greatly affects thermal performance. Connect the INA1620 package thermal pad to acopper pour at the most negative supply potential. This copper pour can be connected to a larger copper planewithin the PCB using vias to improve power dissipation. Figure 45 shows an analogous thermal circuit that canbe used for approximating the junction temperature of the INA1620. The power dissipated in the INA1620 isrepresented by current source PD; the ambient temperature is represented by voltage source 25ºC; and thejunction-to-board and board-to-ambient thermal resistances are represented by resistors RθJB and RθBA,respectively. The board-to-ambient thermal resistance is unique to every application. The sum of RθJB and RθBA isthe junction-to-ambient thermal resistance of the system. The value for junction-to-ambient thermal resistancereported in the Thermal Information table is determined using the JEDEC standard test PCB. The voltages in theanalogous thermal circuit at the points TJ and TPCB represent the INA1620 junction and PCB temperatures,respectively.
EN500 k��
To Amplifier
200 k��VEE
ENENV0.7 VI700 k�� 
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Feature Description (continued)
Figure 45. Approximate Thermal System Model of the INA1620 Soldered to a PCB
7.3.3Thermal Shutdown
If the junction temperature of the INA1620 exceeds 175°C, a thermal shutdown circuit disables the amplifier inorder to protect the device from damage. The amplifier is automatically re-enabled after the junction temperaturefalls below approximately 160°C. If the condition that caused excessive power dissipation has not been removed,the amplifier oscillates between a shutdown and enabled state until the output fault is corrected.
7.3.4EN Pin
The enable pin (EN) of the INA1620 is used to toggle the amplifier enabled and disabled states. The logic levelsdefining these two states are: VEN ≤ 0.78 V (shutdown mode), and VEN ≥ 0.82 V (enabled). These thresholdlevels are referenced to the device ground (GND) pin. The EN pin can be driven by a GPIO pin from the systemcontroller, discrete logic gates, or can be connected directly to the V+ supply. Do not leave the EN pin floatingbecause the amplifier is prevented from being enabled. Likewise, do not place GPIO pins used to control the ENpin in a high-impedance state because this placement also prevents the amplifier from being enabled. A smallcurrent flows into the enable pin when a voltage is applied. Using the simplified internal schematic shown inFigure 46, use Equation 4 to estimate the enable pin current:
As illustrated in Figure 46, the EN pin is protected by diodes to the amplifier power supplies. Do not connect theEN pin to voltages outside the limits defined in the Specifications section.
Figure 46. EN Pin Simplified Internal Schematic
DeviceOutput
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Feature Description (continued)
7.3.5GND Pin
The inclusion of a ground (GND) pin in the INA1620 architecture allows the internal enable circuitry to bereferenced to the system ground, eliminating the need for level shifting circuitry in many applications. The internalamplifier compensation capacitors are also referenced to this pin, greatly increasing the ac PSRR. For highestperformance, connect the GND pin to a low-impedance reference point with minimal noise present. As shown inFigure 46, the GND pin is protected by ESD diodes to the amplifier power supplies. Do not connect the GND pinto voltages outside the limits defined in the Specifications section.
7.3.6Input Protection
The amplifier input pins of the INA1620 are protected from excessive differential voltage with back-to-backdiodes, as Figure 47 shows. In most circuit applications, the input protection circuitry has no consequence.However, in low-gain or G = +1 circuits, fast-ramping input signals can forward bias these diodes because theoutput of the amplifier cannot respond quickly enough to the input ramp. If the input signal is fast enough tocreate this forward-bias condition, the input signal current must be limited to 10 mA or less. If the input signalcurrent is not inherently limited, use an input series resistor (RI) or a feedback resistor (RF) to limit the signalinput current. This input series resistor degrades the low-noise performance of the INA1620 and is examined inthe Noise Performance section. Figure 47 shows an example configuration when both current-limiting input andfeedback resistors are used.
Figure 47. Pulsed Operation
7.4Device Functional Modes
The INA1620 has two operating modes determined by the voltage between the EN and GND pins: a shutdownmode (VEN ≤ 0.78 V) and an enabled mode (VEN ≥ 0.82 V). The measured datasheet performance parametersspecified in the Typical Characteristics and Specifications sections are given with the amplifier in the enabledmode, unless otherwise noted.
7.4.1Shutdown Mode
When the EN pin voltage is below the logic low threshold, the INA1620 enters a shutdown mode with minimalpower consumption. In this state the output transistors of the amplifier are not powered on. However, do notconsider the amplifier output to be high-impedance. Applying signals to the output of the INA1620 while thedevice is in the shutdown mode can parasitically power the output stage, causing the INA1620 output to drawcurrent.
The INA1620 enable circuitry limits transients at the output when transitioning into or out of shutdown mode.However, small output transients do still accompany this transition, as illustrated in Figure 48 and Figure 49. Notethat in both figures the time scale is 1 µs per division, indicating that the output transients are extremely brief innature, and therefore not likely to be audible in headphone applications.
22.1 k��
10.7 k��
To enable pin on IC
Voltage 
Time (1 �s/div) 
Output (20 mV/div) 
Enable (2 V/div) 
Voltage 
Time (1 �s/div) 
Enable (2 V/div) 
Output (20 mV/div) 
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Device Functional Modes (continued)
Figure 48. INA1620 Output Voltage When EN Pin
Transitions High (32-Ω Load Connected)
Figure 49. INA1620 Output Voltage When EN Pin
Transitions Low (32-Ω Load Connected)
7.4.2Output Transients During Power Up and Power Down
To minimize the possibility of output transients that might produce an audible click or pop, ramp the supplyvoltages for the INA1620 symmetrically to their nominal values. Asymmetrical supply ramping can cause outputtransients during power up that can be audible in headphone applications. If possible, hold the EN pin low whilethe power supplies are ramping up or down. If the EN pin is not being independently controlled (for example, bya GPIO pin), use a voltage divider to hold the enable pin voltage below the logic-high threshold until the powersupplies reach the specified minimum voltage, as shown in Figure 50.
Figure 50. Voltage Divider Used to Hold Enable Low at Power-Up or Power-Down
10100 1k 10k 100k1M
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Source Resistance (�) C302 
Current Noise Contribution 
Voltage Noise Contribution 
Total Noise 
Source Resistor Noise Contribution 
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8Application and Implementation
Information in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.
8.1Application Information
The low noise and distortion of the INA1620 make the device useful for a variety of applications in professionaland consumer audio products. However, these same performance metrics also make the INA1620 useful forindustrial, test-and-measurement, and data-acquisition applications. The example shown here is only onepossible application where the INA1620 provides exceptional performance.
8.1.1Noise Performance
Figure 51 shows the total circuit noise for varying source impedances with the op amp in a unity-gainconfiguration (no feedback resistor network, and therefore no additional noise contributions).
The INA1620 is shown with total circuit noise calculated. The op amp contributes both a voltage noisecomponent and a current noise component. The voltage noise is commonly modeled as a time-varyingcomponent of the offset voltage. The current noise is modeled as the time-varying component of the input biascurrent, and reacts with the source resistance to create a voltage component of noise. Therefore, the lowestnoise op amp for a given application depends on the source impedance. For low source impedance, currentnoise is negligible, and voltage noise generally dominates. The low voltage and current noise of the INA1620internal op amps make the device an excellent choice for use in applications where the source impedance is lessthan 10 kΩ as shown in Figure 51.
Figure 51. Noise Performance of the INA1620 Internal Amplifiers
Resistor Matching, Maximum to Minimum (%)
Devices (�)
RRResistor Ratio Matching %100Average R,R� u
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Application Information (continued)
8.1.2Resistor Tolerance
The INA1620 integrated resistor pairs use an advanced thin film process to create resistor pairs that haveexcellent matching. Each specific resistor pair is specifically designed for accurate matching between the tworesistors. Figure 42 shows the distribution of resistor matching for a typical device population. The equation usedto calculate matching between resistors in a pair is shown in Equation 5.
In addition to excellent matching between resistors in each resistor pair, all resistors on a single INA1620 achievegood matching due to inherent process matching across each device. Figure 52 shows a typical distribution ofthe worst-case matching across all resistors on a single INA1620. The matching was calculated using the highestvalue resistance on a device matched with the lowest resistance value on the same device.
Figure 52. Matching Histogram, Maximum to Minimum
8.1.3EMI Rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operationalamplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RFsignal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has ahigher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but thissection provides the EMIRR IN+, which specifically describes the EMIRR performance when the RF signal isapplied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR forthe following three reasons:•Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than thesupply or output pins.
•The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit approximatelymatching EMIRR performance.
•EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input pin canbe isolated on a PCB. This isolation allows the RF signal to be applied directly to the noninverting inputterminal with no complex interactions from other components or connecting PCB traces.
High-frequency signals conducted or radiated to any pin of the operational amplifier result in adverse effects, asthe amplifier does not have sufficient loop gain to correct for signals with spectral content outside its bandwidth.Conducted or radiated EMI on inputs, power supply, or output may result in unexpected DC offsets, transientvoltages, or other unknown behavior. Take care to properly shield and isolate sensitive analog nodes from noisyradio signals and digital clocks and interfaces.
The EMIRR IN+ of the INA1620 amplifiers is plotted versus frequency as shown in Figure 53. See also EMIRejection Ratio of Operational Amplifiers, available for download from www.ti.com.
Frequency (Hz)
EMIRR IN+ (dB)
10152025303540455055606570
100M1G10G
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Application Information (continued)
Figure 53. INA1620 EMIRR IN+
Table 1 lists the EMIRR IN+ values for the INA1620 at particular frequencies commonly encountered in real-world applications. Applications listed in Table 1 may be centered on or operated near the particular frequencyshown. This information may be of special interest to designers working with these types of applications, orworking in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,and medical (ISM) radio band.
Table 1. INA1620 EMIRR IN+ for Frequencies of Interest
FREQUENCYAPPLICATION OR ALLOCATIONEMIRR IN+
900 MHzGlobal system for mobile communications (GSM) applications, radio communication, navigation,GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications18 dB
1.8 GHzGSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)33 dB
2.4 GHz802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific andmedical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)26 dB
3.6 GHzRadiolocation, aero communication and navigation, satellite, mobile, S-band40 dB
5 GHz802.11a, 802.11n, aero communication and navigation, mobile communication, space and satelliteoperation, C-band (4 GHz to 8 GHz)55 dB
Low-Pass Filter50 ��
Digital Multimeter
Ambient temperature: 25Û&
Sample / Averaging
Not shown: 0.1 µF and 10 µF supply decoupling
RF sourceDC Bias: 0 VModulation: None (CW)Frequency Sweep: 201 pt. Log
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8.1.4EMIRR +IN Test Configuration
Figure 54 shows the circuit configuration for testing the EMIRR IN+. An RF source connects to the op ampnoninverting input pin using a transmission line. The op amp is configured in a unity-gain buffer topology with theoutput connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance mismatch at theop amp input causes a voltage reflection; however, this effect is characterized and accounted for whendetermining the EMIRR IN+. A multimeter samples and measures the resulting DC offset voltage. The LPFisolates the multimeter from residual RF signals that may interfere with multimeter accuracy.
Figure 54. EMIRR +IN Test Configuration
2OUTDAC1OUT
RVVRR �
Audio DAC
INA1620
Headphone Output
1 k��1 k��
1 k��1 k��
100 pF
100 pF
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8.2Typical Application
The low distortion and high output-current capabilities of the INA1620 make this device an excellent choice forheadphone-amplifier applications in portable or studio applications. These applications typically employ an audiodigital-to-analog converter (DAC) and a separate headphone amplifier circuit connected to the DAC output. High-performance audio DACs can have an output signal that is either a varying current or voltage. Voltage outputconfigurations require less external circuitry, and therefore have advantages in cost, power consumption, andsolution size. However, these configurations can offer slightly lower performance than current outputconfigurations. Differential outputs are standard on both types of DACs. Differential outputs double the outputsignal levels that can be delivered on a single, low-voltage supply, and also allow for even-harmonics common toboth outputs to be cancelled by external circuitry. A simplified representation of a voltage-output audio DAC isshown in Figure 55. Two ac voltage sources (VAC) deliver the output signal to the complementary outputsthrough their associated output impedances (ROUT). Both output signals have a dc component as well,represented by dc voltage source VDC. The headphone amplifier circuit connected to the output of an audio DACmust convert the differential output into a single-ended signal and be capable of producing signals of sufficientamplitude at the headphones to achieve reasonable listening levels.
Figure 55. INA1620 Used as a Headphone Amplifier for a Voltage-Output Audio DAC
8.2.1Design Requirements
•±5-V power supplies
•150-mW output power (32-Ω load)
•< –110-dB THD+N at maximum output (32-Ω load)
•< 0.01-dB magnitude deviation (20 Hz to 20 kHz)
8.2.2Detailed Design Procedure
Figure 55 shows a schematic of a headphone amplifier circuit for voltage output DACs. An op amp is configuredas a difference amplifier that converts the differential output voltage to single-ended.
The gain of the difference amplifier in Figure 55 is determined by the resistor values, and includes the outputimpedance of the DAC. For R2 = R4 and R1 = R3, the output voltage of the headphone amplifier circuit is shownin Equation 6:
The output voltage required for headphones depends on the headphone impedance, as well as the headphoneefficiency (η), a measure of the sound pressure level (SPL, measured in dB) for a certain input power level(typically given at 1 mW). The headphone SPL at other power levels is calculated using Equation 7:
P22f20 kHzf416.6 kHz1111G0.999
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1f 2 (R ,R )(C ,C )S
ORMSVPR150 mW32 �������9 u u 
0.010.11101001000
Sound Pressure Level (SPL, dB) 
Input Power (mW) 
90-dB/mW
95-dB/mW
100-dB/mW
105-dB/mW
110-dB/mW
115-dB/mW
INPSPL(dB)10log 1 mW§· K �¨¸©¹
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Typical Application (continued)
•η = efficiency
•PIN = input power to the headphones(7)
Figure 56 shows the input power required to produce certain SPLs for different headphone efficiencies. Typically,over-the-ear style headphones have lower efficiencies than in-ear types with 95 dB/mW being a common value.
Figure 56. Sound Pressure Level vs Input Power for Headphones of Various Efficiencies
In-ear headphones can have efficiencies of 115 dB/mW or greater, and therefore have much lower powerrequirements. The output power goal for this design is 150 mW — sufficient power to produce extremely loudsound pressure levels in a wide range of headphones. A 32-Ω headphone impedance is used for thisrequirement because 32 Ω is a very common value in headphones for portable applications. Equation 8 showsthe voltage required for 32-Ω headphones:
Capacitors C1 and C2 limit the bandwidth of the circuit to prevent the unnecessary amplification of interferingsignals. The maximum value of these capacitors is determined by the limitations on frequency responsemagnitude deviation detailed in the Design Requirements section. C1 and C2 combine with resistors R2 and R4 toform a pole, as shown in Equation 9:
Calculate the minimum pole frequency allowable to meet the magnitude deviation requirements usingEquation 10:
•G represents the gain in decimal for a –0.01-dB deviation at 20 kHz.(10)
Frequency (Hz)
Amplitude (dBV)
05000100001500020000-150-140-130-120-110-100
-90-80-70-60-50-40-30-20-100
Output Level (Vrms)
Total Harmonic Distortion + Noise (dB)
0.010.115-120
Left ChannelRight Channel
Frequency (Hz)
Total Harmonic Distortion + Noise (dB)
-110-108-106-104-102-100
-98-96-94-92-90-88-86-84-82-80
101001k10k
Left ChannelRight Channel
11C ,C382 pF2 (R ,R )F2 (1 k���������N+]�dddSS
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Typical Application (continued)
Use Equation 11 to calculate the upper limit for the value of C1 and C2 in order to meet the goal for minimalmagnitude deviation at 20 kHz.
For this design, 100-pF capacitors were used because they meet the design requirements for amplitudedeviation in the audio bandwidth.
8.2.3Application Curves
Figure 57 shows the maximum output voltage achievable for a 32-Ω load before the onset of clipping (±5-Vsupplies), indicated by a sharp increase in distortion. As more current is delivered by the output transistors of anamplifier, additional distortion is produced. At low frequencies, this distortion is corrected by the feedback loop ofthe amplifier. However, as the loop gain of the amplifier begins to decline at high frequencies, the overalldistortion begins to climb. The unique output stage design of the INA1620 greatly reduces the additionaldistortion at high frequency when delivering large currents, as shown in Figure 58. High-ordered harmonics(above the 2nd and 3rd) are also kept to a minimal level at high output powers, as shown in Figure 59.
22.4-kHz measurement bandwidth
Figure 57. THD+N vs Output Voltage for a 32-Ω Load
90-kHz measurement bandwidth, 1-VRMS output
Figure 58. THD+N vs Frequency for a 32-Ω Load
1 kHz, 32-Ω load, 1 VRMS
Figure 59. Output Spectrum
0.1 �F
Output
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0.1 �F
OPA197
100 k�
100 k�
2.2 k�
2.2 k�
Microphone Input
XLR Connector
6.8 k�6.8 k�
48 V Phantom Power
1 k�1 k�1 k�
47 �FD1D2
10-k��Potentiometer (Logarithmic)
R3CR3AR2C
R3BR2B
INA1620
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8.3Other Application Examples
8.3.1Preamplifier for Professional Microphones
Figure 60 shows a preamplifier designed for high performance applications that require low-noise and highcommon-mode rejection. Both channels of the INA1620 are configured as a two-op amp instrumentation amplifierwith a variable gain from 6 to 40 dB. The excellent matching of the integrated 1kΩ resistors allows for highcommon-mode rejection in the circuit. An OPA197 is configured as a buffered power supply divider to provide abiasing voltage to the circuit, allowing the system to operate properly on a single 9-V battery. The additionalcomponents at the INA1620 inputs are for phantom power, EMI, and ESD protection.
Figure 60. Preamplifier for Professional Microphones
Place bypass capacitors as close to IC as possible
IC ground pin connected to low-impedance, low-noise system ground
Minimize feedback loop area
Copper pour for thermal pad must be connected to negative supply (VEE)
EMI Filtering
EMI Filtering
Minimize capacitance at amplifier inputs
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9Power Supply Recommendations
The INA1620 operates from ±2-V to ±18-V supplies, while maintaining excellent performance. However, someapplications do not require equal positive and negative output voltage swing. With the INA1620, power-supplyvoltages do not need to be equal. For example, the positive supply could be set to 25 V with the negative supplyat –5 V.
In all cases, the common-mode voltage must be maintained within the specified range. Key parameters arespecified over the temperature range of TA = –40°C to 125°C. Parameters that vary with operating voltage ortemperature are shown in the Typical Characteristics section.
10Layout
10.1Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:•Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as closeas possible to the device. A single bypass capacitor from V+ to ground is applicable for single-supplyapplications. The bypass capacitors are used to reduce the coupled noise by providing low-impedance powersources local to the analog circuitry, because noise can propagate into analog circuitry through the powerpins of the circuit as a whole and the op amp specifically.
•Connect the device ground pin to a low-impedance, low-noise, system reference point, such as an analogground.
•Place the external components as close to the device as possible. As shown in Figure 61, keep feedbackresistors close to the inverting input to minimize parasitic capacitance and the feedback loop area.
•Keep the length of input traces as short as possible. Always remember that the input traces are the mostsensitive part of the circuit.
•For proper amplifier function, connect the package thermal pad to the most negative supply voltage (VEE).
10.2Layout Example
Figure 61. Board Layout for a Difference Amplifier Configuration
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11Device and Documentation Support
11.1Device Support
11.1.1Development Support
11.1.1.1TINA-TI™ (Free Software Download)
TINA-TI software is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine.TINA-TI software is a free, fully-functional version of the TINA software, preloaded with a library of macro modelsin addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, andfrequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI software offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability toselect input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
These files require that either the TINA software (from DesignSoft™) or TINA-TI softwarebe installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2TI Precision Designs
TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI PrecisionDesigns are analog solutions created by TI’s precision analog applications experts and offer the theory ofoperation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measuredperformance of many useful circuits.
11.2Documentation Support
11.2.1Related Documentation
For related documentation see the following:•Feedback Plots Define Op Amp AC Performance
•Circuit Board Layout Techniques, SLOA089
•Headphone Amplifier for Voltage-Output Audio DACs Reference Design
•Stabilizing Difference Amplifiers for Headphone Applications
•Reducing Distortion from CMOS Analog Switches
•EMI Rejection Ratio of Operational Amplifiers
•HiFi Audio Circuit Design
11.3Receiving Notification of Documentation Updates
To receive notification of documentation updates, find the device product folder on ti.com. In the upper rightcorner, click on Alert me to receive a weekly digest of any product information that has changed. For changedetails, see the revision history included in any revised document.
11.4Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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11.5Trademarks
E2E is a trademark of Texas Instruments.TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.Bluetooth is a registered trademark of Bluetooth SIG, Inc.DesignSoft is a trademark of DesignSoft, Inc.All other trademarks are the property of their respective owners.
11.6Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
11.7Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable DeviceStatus
Package Type PackageDrawing
Pins PackageQty
Eco Plan
Lead finish/Ball material
MSL Peak Temp
Op Temp (°C)Device Marking
Samples
INA1620RTWRACTIVEWQFNRTW243000RoHS & GreenNIPDAULevel-2-260C-1 YEAR-40 to 125INA1620
INA1620RTWTACTIVEWQFNRTW24250RoHS & GreenNIPDAULevel-2-260C-1 YEAR-40 to 125INA1620
 (1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device. 
(2) RoHS:  TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement. 
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. 
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device. 
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com10-Dec-2020
Addendum-Page 2
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