DC/DC Converter
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TPS2373
AMPS_CTL
VC_OUT
Xfrmer Aux Bias Supply
MPS Control
Low Voltage DCDC Controller
Small Vc Cap
MPS pulses
MPS pulses automatically generated if I_in is too low
0.1 �F
RMPSCBULK
+CVC_OUT
MPS_DUTYRMPS_DUTY
CVC_IN
I_in(1 A/div)
VC_OUT(5 V/div)VC_IN(5 V/div)
V_in(50 V/div)
Inrush Wait time
20 ms/div
optional
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2373
SLUSCD1C –JUNE 2017–REVISED NOVEMBER 2018
TPS2373 High-Power PoE PD Interface with Advanced Startup
1Features
1•IEEE 802.3bt (Draft) PD Solution for Type 3 orType 4 PoE
•Supports Power Levels for Type-4 ( TPS2373-4)90-W and Type-3 ( TPS2373-3) 60-W Operation
•Robust 100 V Hotswap MOSFET–TPS2373-4 (typ.): 0.1-Ω, 2.2-A Current Limit
–TPS2373-3 (typ.): 0.3-Ω, 1.85-A Current Limit
•Allocated Power Indicator Outputs
•Advanced Startup for DC-DC–Simplifies Downstream DC-DC Design
–Compliant to PSE Inrush
•Automatic Maintain Power Signature (MPS)–Auto-adjust MPS for Type 1-2 or 3-4 PSE
–Supports Ultra-Low Power Standby Modes
•Primary Adapter Priority Input
•Supports PoE++ PSE
•-40°C to 125°C Junction Temperature Range
•20-lead VQFN Package
2Applications
•IEEE 802.3bt (Draft) Compliant Devices
•4PPOE
•Pass-through System
•Security Cameras
•Multiband access points
•Pico-base Stations
•Video and VoIP Telephones
•Systems using Redundant Power Feeds
3Description
The TPS2373 contains all of the features needed toimplement an IEEE802.3at or IEEE802.3bt (draft)(Type 1-4) powered device (PD). The low internalswitchresistanceallowstheTPS2373-4and
TPS2373-3 to support high power applications up to90 W and 60 W respectively. Assuming 100-meterCAT5 cable, this translates into 71.3 W and 51 W atPD input.
The TPS2373 operates with enhanced features.
The Advanced Startup function for DC-DC results in asimple, flexible, and minimal system cost solution,whileensuringthatIEEE802.3bt(draft)startup
requirements are met. It helps to reduce the size ofthe low voltage bias capacitor considerably. It alsoallows long DC-DC converter soft-start period andenables the use of a low-voltage PWM controller.
The Automatic MPS function enables applicationsrequiringverylowpowerstandbymodes.The
TPS2373automaticallygeneratesthenecessary
pulsedcurrenttomaintainthePSEpower.An
external resistor is used to enable this functionalityand to program the MPS pulsed current amplitude.
Device Information(1)
PART NUMBERPACKAGEBODY SIZE (NOM)
TPS2373VQFN (20)5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
spacer
spacer
Simplified Schematic
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Table of Contents
1Features.................................................................. 1
2Applications ........................................................... 1
3Description ............................................................. 1
4Revision History..................................................... 2
5Pin Configuration and Functions......................... 4
6Specifications......................................................... 56.1Absolute Maximum Ratings ...................................... 5
6.2ESD Ratings.............................................................. 5
6.3Recommended Operating Conditions....................... 6
6.4Thermal Information.................................................. 6
6.5Electrical Characteristics........................................... 7
6.6Typical Characteristics............................................ 11
7Detailed Description ............................................ 157.1Overview ................................................................. 15
7.2Functional Block Diagram ....................................... 16
7.3Feature Description................................................. 17
7.4Device Functional Modes........................................ 21
8Application and Implementation ........................ 32
8.1Application Information............................................ 32
8.2Typical Application .................................................. 32
9Power Supply Recommendations...................... 37
10Layout................................................................... 3710.1Layout Guidelines ................................................. 37
10.2Layout Example .................................................... 37
10.3EMI Containment .................................................. 38
10.4Thermal Considerations and OTSD...................... 38
10.5ESD....................................................................... 38
11Device and Documentation Support ................. 3911.1Documentation Support ........................................ 39
11.2Receiving Notification of Documentation Updates 39
11.3Community Resources.......................................... 39
11.4Trademarks........................................................... 39
11.5Electrostatic Discharge Caution............................ 39
11.6Glossary................................................................ 39
12Mechanical, Packaging, and OrderableInformation ........................................................... 39
4Revision History
Changes from Revision B (March 2018) to Revision CPage
•Added dashed box with optional in the Simplified Schematic................................................................................................ 1
•Added TableNote to Table 2................................................................................................................................................. 19
•Added dashed box with optional on it in Figure 30 ............................................................................................................. 32
•Added PSE and POE information to Opto-isolators for TPH, TPL and BT.......................................................................... 35
Changes from Revision A (October 2017) to Revision BPage
•Changed TPS2373-3 typical current limit to 1.85 A ............................................................................................................... 1
•Deleted the VAPD typical value ............................................................................................................................................... 7
•Changed minimum, typical, and maximum values of VAPD rising threshold........................................................................... 7
•Added minimum and maximum values of VAPDH in the Electrical Characteristics table......................................................... 7
•Changed current limit nominal value to 1.85 and maximum value to 2.2 .............................................................................. 7
•Changed minimum value of inrush termination to 65%.......................................................................................................... 7
•Changed typical shutdown temperature to 158°C................................................................................................................ 10
•Added TPS2373-4 to the title of Figure 11........................................................................................................................... 12
•Changed Functional Block Diagram image .......................................................................................................................... 16
•Changed "current limit is changed to 1.8 A" to "current limit is changed to 1.85 A" in Internal Pass MOSFET subsection 18
•Added "The VC switch ..." sentence to VC_IN, VC_OUT, UVLO_SEL, and Advanced PWM Setup subsection................ 20
•Changed "~" to "approximately" and "1.8 A" to "1.85 A" in the Advanced Startup and Converter Operation subsection ... 27
•Added reference for guidance on how to handle PoE shutdown conditions to the Advanced Startup and ConverterOperation subsection............................................................................................................................................................ 28
•Changed Typical Application Circuit..................................................................................................................................... 32
•Changed "KΩ" to "kΩ" and "1.65 V" to "1.75 V" in Equation 2............................................................................................. 34
•Changed "232 kΩ" to "221 kΩ" in Equation 3....................................................................................................................... 34
•Added sentence to end of the APD Pin Divider Network RAPD1, RAPD2 subsection ............................................................. 34
•Added information to end of the VC Input and Output, CVCIN and CVCOUT subsection .......................................................... 35
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•Changed equation 7 values in Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY................................................ 35
•Changed TPS2373-3 to ACTIVE.......................................................................................................................................... 39
Changes from Original (June 2017) to Revision APage
•Changed Automatic MPS falling current threshold MIN from 21.5 to 18, MAX from 34.5 to 38 ........................................... 9
VC_OUT
AMPS_CTL
UVLO_SEL
MPS_DUTY
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5Pin Configuration and Functions
RGW Package20-Pin VQFN
Top View
Pin Functions
I/ODESCRIPTION
NAMENO.
VDD1IConnect to positive PoE input power rail. Bypass with 0.1 µF to VSS.
DEN2I/OConnect a 24.9 kΩ resistor from DEN to VDD to provide the PoE detection signature. Pull DEN to VSS todisable the pass MOSFET during powered operation.
CLSA3OConnect a resistor from CLSA to VSS to program the first classification current.
VSS4, 5—Connect to negative power rail derived from PoE source.
CLSB6OConnect a resistor from CLSB to VSS to program the second classification current.
REF7OInternal 1.5 V voltage reference. Connect a 49.9kΩ_1% resistor from REF to VSS.
AMPS_CTL8OAutomatic MPS control. Connect a resistor with appropriate power rating (to support the MPS current) fromAMPS_CTL to VSS to program the MPS current amplitude. Leave AMPS_CTL open to disable the automaticMPS function.
MPS_DUTY9IMPS duty cycle select input, referenced to VSS, internally driven by a precision current source with voltagelimited to less than ~5.5V. A resistor connected to VSS determines if the MPS duty cycle selected is either5.4% (open), 8.1% (~60.4 kΩ) or 12.5% (short).
APD10IAuxiliary power detect input. Raise 1.65 V above RTN to disable pass MOSFET, to force TPH active (low) andto force TPL and /BT inactive (open). If not used, connect APD to RTN.
RTN11, 12—Drain of PoE pass MOSFET. Return line from the load to the controller.
PG13OPower Good output. Open-drain, active-high output referenced to RTN.
VC_OUT14OVC output. Connect to the low voltage supply pin of the PWM controller. Bypass with a 1 µF to RTN in mostapplications. If the applications requires operations from a 12 V adapter, a higher capacitance value is needed.
VC_IN15IVC input. Connect to auxiliary bias voltage source, usually derived from an auxiliary winding of the powertransformer of the converter. Bypass with a 0.1 µF to RTN.
UVLO_SEL16IUVLO select, referenced to RTN, internally pulled-up to 5.5 V internal rail. Leave open when the selected PWMhas a falling UVLO above 7.25V. Pull UVLO_SEL low if it is between 4.25V and 7.25V.
TPL17OPSE allocated power outputs, binary coded. Open-drain, active-low outputs referenced to RTN. TPL becomesopen and TPH pulls low if an auxiliary power adapter is detected via the APD input.TPH18O
BT19OIndicates that a PSE applying an IEEE802.3bt (Type 3 or 4) mutual identification scheme has been identified.Open-drain, active-low output referenced to RTN. /BT becomes open if an auxiliary power adapter is detected.
NC20—No connect pin. Leave open.
Pad——The exposed thermal pad must be connected to VSS. A large fill area is required to assist in heat dissipation.
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(1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)With I(RTN) = 0
(3)Do not apply voltages to these pins
(4)SOA limited to RTN = 80 V at 2.5 A.
6Specifications
6.1Absolute Maximum Ratings
over recommended TJ range; voltages with respect to VVSS (unless otherwise noted)(1)
MINMAXUNIT
Input voltage
VDD, DEN–0.3100
RTN(2)–0.6100
VC_IN to RTN–0.625
APD to RTN–0.36.5
UVLO_SEL to RTN–0.36.5
Output voltage
CLSA, CLSB, REF, MPS_DUTY(3)–0.36.5
VVC_OUT to RTN–0.3
VVDD-RTN+0.3
AMPS_CTL(3)–0.330
Voltage
PG to RTN–0.3100
TPH, TPL, BT to RTN–0.3100
Sinking current
RTN(4)Internally limited
mAPG, TPH, TPL, BT10
Sourcing current
VC_OUT startupInternally limited
VC_OUT operational mode60
CLSA, CLSB65
REFInternally limited
AMPS_CTL50
TJ(max)Maximum junction temperatureInternally limited°C
TstgStorage temperature–65150°C
(1)JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3)Discharges applied to circuit of Figure 30 between RJ-45, adapter, and output voltage rails, on TPS2373-4EVM-758.
6.2ESD Ratings
VALUEUNIT
V(ESD)Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, allpins(2)±500
IEC 61000-4-2 contact discharge(3)±8000
IEC 61000-4-2 air-gap discharge(3)±15000
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(1)Voltage should not be externally applied to this pin.
6.3Recommended Operating Conditions
over operating free-air temperature range and voltages with respect to VSS (unless otherwise noted)
MINNOMMAXUNIT
Input voltage range
RTN, VDD057V
APD to RTN05
VC_IN to RTN015
Voltage range
TPH, TPL, BT to RTN057
PG to RTN057
Sinking current
RTN ( TPS2373-3)1.2
RTN ( TPS2373-4)1.85
PG, TPH, TPL, BT3mA
Sourcing currentVC_OUT20mA
Resistance
CLSA, CLSB(1)60Ω
AMPS_CTL(1)1
kΩREF(1)48.949.950.9
APD to RTN200
Junction temperature–40125°C
(1)For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.
6.4Thermal Information
THERMAL METRIC(1)
TPS2373-3TPS2373-4
UNITRGW(VQFN)
RGW(VQFN)
20 PINS20 PINS
RθJAJunction-to-ambient thermal resistance40.238.0°C/W
RθJC(top)Junction-to-case (top) thermal resistance34.628.1°C/W
RθJBJunction-to-board thermal resistance17.916.1°C/W
ψJTJunction-to-top characterization parameter0.50.3°C/W
ψJBJunction-to-board characterization parameter17.816.0°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance3.41.8°C/W
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6.5Electrical Characteristics
Unless otherwise noted, 40 V ≤ VVDD ≤ 57 V; RDEN = 24.9 kΩ; PG, CLSA, CLSB, MPS_DUTY, AMPS_CTL, UVLO_SEL,VC_IN, TPH, TPL and BT open; APD connected to RTN; CVC_OUT = 1 µF; RREF = 49.9 kΩ; –40°C ≤ TJ ≤ 125°C. Positivecurrents are into pins. Typical values are at 25°C. All voltages are with respect to VVSS unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DETECTION (DEN)
Bias currentDEN open, VVDD = 10.1 V, MeasureISUPPLY(VDD, RTN, DEN), Not in mark34.814µA
DEN leakage currentVDEN = VVDD = 57 V0.55µA
Detection current
Measure ISUPPLY(VDD, RTN, DEN), VVDD =1.4 V53.856.558.3
Measure ISUPPLY(VDD, RTN, DEN), VVDD =10.1 V, Not in mark395410417
VPD_DIS
Disable thresholdDEN falling33.75V
Hysteresis75150250mV
AUXILIARY POWER DETECTION (APD)
VAPDENVoltage threshold
VAPD rising, measure to VRTN1.381.82
VAPDHHysteresis, measure to VRTN0.0550.090.145
Pulldown resistanceV(APD–RTN) = 5 V, measure RAPD2.8MΩ
CLASSIFICATION (CLS)
ICLSClassification A,B signaturecurrent
13 V ≤ VVDD ≤ 21 V, Measure IVDD + IDEN +IRTNRCLSA or RCLSB = 1210 Ω2.12.52.9
RCLSA or RCLSB = 249 Ω9.910.611.2
RCLSA or RCLSB = 140 Ω17.618.619.4
RCLSA or RCLSB = 90.9 Ω26.527.929.3
RCLSA or RCLSB = 63.4 Ω3839.942
VCL_ONClass lower threshold
VVDD rising, ICLS ↑11.912.513
VCL_HHysteresis1.41.61.7
VCU_ONClass upper threshold
VVDD rising, ICLS↓212223
VCU_HHysteresis0.50.780.9
VMSRMark reset thresholdVVDD falling33.95V
Mark state resistance2-point measurement at 5 V and 10.1 V61012kΩ
Leakage currentVVDD = 57 V, VCLS = 0 V, measure ICLS1µA
tLCF_PDLong first class event timingClass 1st event time duration for new MPS7681.586ms
PASS DEVICE (RTN)
rDS(on)On resistance
TPS2373-30.30.55
TPS2373-40.10.2
Input bias currentVVDD = VRTN = 30 V, measure IRTN50
RTN leakage currentVVDD = VRTN = 100 V, VDEN = VVSS , measureIRTN80
Current limit
VRTN = 1.5 VTPS2373-31.551.852.2
VRTN = 1.5 VTPS2373-41.92.22.5
Inrush current limit
VRTN = 2 V,VVDD: 20 V → 48 VTPS2373-3165200237
VRTN = 2 V,VVDD: 20 V → 48 VTPS2373-4275335395
Inrush termination
Percentage of inrush current65%90%99%
tINR_DELInrush delay7881.587ms
Foldback thresholdVRTN rising12.514.515.5V
Foldback deglitch timeVRTN rising to when current limit changes toinrush current limit1.351.651.95ms
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Electrical Characteristics (continued)
Unless otherwise noted, 40 V ≤ VVDD ≤ 57 V; RDEN = 24.9 kΩ; PG, CLSA, CLSB, MPS_DUTY, AMPS_CTL, UVLO_SEL,VC_IN, TPH, TPL and BT open; APD connected to RTN; CVC_OUT = 1 µF; RREF = 49.9 kΩ; –40°C ≤ TJ ≤ 125°C. Positivecurrents are into pins. Typical values are at 25°C. All voltages are with respect to VVSS unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER GOOD (PG)
Output low voltageMeasure VPG – VRTN, IPG = 2 mA, VRTN = 2V, VDD: 20 V → 48 V0.270.5V
Leakage current
VPG = 57 V, VRTN = 0 V10
VPG = 10 V, VRTN = 0 V1
PSE TYPE INDICATION (TPL, TPH, BT)
VTPLOutput low voltage
ITPL = 2 mA, after 2-, 3- or 5-eventclassification, startup has completed,VRTN = 0 V
0.270.5
VVTPHOutput low voltageITPH = 2 mA, after 4- or 5-event classification,startup has completed, VRTN = 0 V0.270.5
VBTOutput low voltageIBT = 2 mA, after IEEE802.3bt classification,startup has completed, VRTN = 0 V0.270.5
Leakage currentVTPL or VTPH or VBT = 7 V, VRTN = 0 V1µA
tTPLHBTTPL, TPH, BT delayFrom VC_IN high with PG open duringstartup to TPH and/or TPL and/or BT active202428ms
VUVLO_RUVLO rising thresholdVVDD rising36.338.140
VUVLO_FUVLO falling thresholdVVDD falling30.53233.6
VUVLO_HUVLO hysteresis6.1V
BIAS CURRENT
Operating current40 V ≤ VVDD ≤ 57 V, startup has completed550800µA
STARTUP
VVCO_UVVC_OUT undervoltagefalling threshold
VVC_OUT-RTN falling6.456.97.35
VVC_OUT-RTN falling, UVLO_SEL connected toRTN3.453.94.25
VVCO_UV_HVC_OUT undervoltagehysteresis
UVLO_SEL connected to RTN0.046
IVCOUTStartup current source
VAPD-RTN = 2.5 V
VVDD ≥ 28 V, VVC_OUT-RTN = 13.6 V21.52629
mAVVDD ≥ 10 V, VVC_OUT-RTN = 7 V812.519
VVDD ≥ 8 V, VVC_OUT-RTN = 6.5 V3.96.39.7
VVC_STVC_OUT startup voltage
Measure VVC_OUT during startup,IVC_OUT = 0 mA13.815V
Measure VVC_OUT during startup,IVC_OUT = 22 mA13.515V
VUVLO_SEVC_OUT UVLO selectthresholdto RTN1.82.12.3V
UVLO_SEL pullup current142025µA
VVCIN_ONVC_IN rising threshold toturn on the VC switchto RTN88.59V
rVCVC switch on resistance
VAPD-RTN = 2.5 V
VVDD ≥ 28 V, VVC_IN-RTN = 10 V13.3
VVDD ≥ 20 V, VVC_IN-RTN = 10 V15.5
tSTUP_OFF
Startup current source turnoff delay and TPH, TPL, BTturn on delay
From when the VC switch turns on202428ms
tSTUP_OUTStartup current source timeoutFrom startup source turn on to turn off47.55053ms
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Electrical Characteristics (continued)
Unless otherwise noted, 40 V ≤ VVDD ≤ 57 V; RDEN = 24.9 kΩ; PG, CLSA, CLSB, MPS_DUTY, AMPS_CTL, UVLO_SEL,VC_IN, TPH, TPL and BT open; APD connected to RTN; CVC_OUT = 1 µF; RREF = 49.9 kΩ; –40°C ≤ TJ ≤ 125°C. Positivecurrents are into pins. Typical values are at 25°C. All voltages are with respect to VVSS unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
MPS DC supply currentStartup has completed, IRTN = 0 mA0.8mA
AMPS_CTL pulsed voltageStartup has completed, IRTN < 20 mA,RMPS = 1 KΩ to 12 kΩ23.12424.9V
Automatic MPS fallingcurrent threshold
Startup has completed, IRTN threshold togenerate AMPS_CTL pulses182838
Hysteresis on RTN current1
MPS pulsed mode dutycycle for Type 1-2 PSE
MPS pulsed current duty cycle25.8%26.1%26.4%
MPS pulsed current ON time7681.587
MPS pulsed current OFF time230250
MPS pulsed mode dutycycle for Type 3-4 PSE
MPS pulsed current duty cycle,RMPS_DUTY > 230 kΩ5.2%5.43%5.6%
MPS pulsed current ON time,RMPS_DUTY > 230 kΩ14.515.015.7ms
MPS pulsed current duty cycle,RMPS_DUTY < 8 kΩ12.3%12.5%12.7%
MPS pulsed current ON time,RMPS_DUTY < 8 kΩ3637.539ms
MPS pulsed current duty cycle,43 kΩ < RMPS_DUTY < 77 kΩ7.9%8.1%8.3%
MPS pulsed current ON time,43 kΩ < RMPS_DUTY < 77 kΩ22.223.124ms
MPS pulsed current OFF time, RMPS_DUTYfrom 0 Ω to open circuit250263.5277ms
MPS_DUTY pullup current141720µA
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Electrical Characteristics (continued)
Unless otherwise noted, 40 V ≤ VVDD ≤ 57 V; RDEN = 24.9 kΩ; PG, CLSA, CLSB, MPS_DUTY, AMPS_CTL, UVLO_SEL,VC_IN, TPH, TPL and BT open; APD connected to RTN; CVC_OUT = 1 µF; RREF = 49.9 kΩ; –40°C ≤ TJ ≤ 125°C. Positivecurrents are into pins. Typical values are at 25°C. All voltages are with respect to VVSS unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
(1)Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty.
THERMAL SHUTDOWN
ShutdownTJ↑140158°C
Hysteresis (1)20°C
Junction Temperature (qC)
VDD-VSS Voltage (V)
-50-25025507510012521
VDD Rising (V)VDD Falling (V)
Junction Temperature (qC)
VDD-VSS Voltage (V)
-50-2502550751001253
Junction Temperature (qC)
APD-RTN Voltage (V)
-50-2502550751001251.4
APD Rising (V)APD Falling (V)
Junction Temperature (qC)
VDD-VSS Voltage (V)
-50-25025507510012510.5
VDD Rising (V)VDD Falling (V)
VDD-VSS Voltage (V)
VDD Bias Current (PA)
0123456789100
TJ = -40CTJ = 25CTJ = 125C
VDD-VSS Voltage (V)
VDD Bias Current (PA)
2530354045505560300
TJ = -40CTJ = 25CTJ = 125C
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6.6Typical Characteristics
Figure 1. Detection Bias Current vs PoE VoltageFigure 2. IVDD Bias Current vs Voltage
Figure 3. APD Threshold Voltage vs Temperature, TPS2373-
Figure 4. Classification Lower Threshold vs Temperature
Figure 5. Classification Upper Threshold vs TemperatureFigure 6. Mark Reset Threshold vs Temperature
Junction Temperature (qC)
Inrush Termination Threshold (%)
-50-25025507510012587
D011Junction Temperature (qC)
Inrush Time Delay (ms)
-50-25025507510012580
Junction Temperature (qC)
Current Limit (A)
-50-2502550751001252
D009Junction Temperature (qC)
Inrush Current Limit (mA)
-50-250255075100125320
Junction Temperature (qC)
Mark State Resistance (k:)
-50-2502550751001257.5
D006Junction Temperature (qC)
Pass FET Resistance (:)
-50-2502550751001250.075
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Typical Characteristics (continued)
Figure 7. Mark Resistance vs TemperatureFigure 8. Pass FET Resistance vs Temperature, TPS2373-4
Figure 9. PoE Current Limit vs Temperature, TPS2373-4Figure 10. PoE Inrush Current Limit vs Temperature,
TPS2373-4
Figure 11. Inrush Termination Threshold vs Temperature,
TPS2373-4
Figure 12. Inrush Time Delay vs Temperature
VDD-RTN Voltage (V)
VC_OUT Sourcing Current (mA)
101520253035404550550
VVC_OUT = 7 V
TJ = -40CTJ = 25CTJ = 125C
Junction Temperature (qC)
VC_OUT UVLO Falling (V)
-50-2502550751001253
UVLO_SEL FloatingUVLO_SEL to RTN
VC_OUT Sourcing Current (mA)
VC_OUT Voltage (V)
03691215182124273011
TJ = -40CTJ = 25CTJ = 125C
VDD-RTN Voltage (V)
VC_OUT Sourcing Current (mA)
1520253035404550556010
VVC_OUT = 13.6 V
TJ = -40CTJ = 25CTJ = 125C
Junction Temperature (qC)
VDD UVLO Rising (V)
-50-25025507510012538.4
D013Junction Temperature (qC)
VDD UVLO Falling (V)
-50-25025507510012532
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Typical Characteristics (continued)
Figure 13. UVLO Rising Threshold vs TemperatureFigure 14. UVLO Falling Threshold vs Temperature
Figure 15. Converter Startup Voltage vs CurrentFigure 16. Converter Startup Current vs Input Voltage
Figure 17. Converter Startup Current vs Input VoltageFigure 18. VC_OUT UVLO vs Temperature
Junction Temperature (qC)
VC_IN ON Rising (V)
-50-2502550751001258.4
D020Junction Temperature (qC)
VC Switch Resistance (:)
-50-2502550751001256
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Typical Characteristics (continued)
Figure 19. VC_IN Threshold vs TemperatureFigure 20. VC Switch Resistance vs Temperature
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7Detailed Description
7.1Overview
The TPS2373 device is a 20-pin integrated circuit that contains all of the features needed to implement a singleinterface IEEE802.3bt Type-3 ( TPS2373-3) and Type-4 ( TPS2373-4) powered device (PD). Basic functionalitysupported includes Detection, Hardware Classification, and inrush current limit (200-mA for TPS2373-3 and 335-mA for TPS2373-4) during startup. Enhanced features include the advanced startup function for DC-DCcontroller, as well as the automatic maintain power signature (MPS).
The TPS2373-3 integrates a low 0.3-Ω internal switch to support Type-3 applications up to 60 W of continuouspower sourced by the PSE, allowing beyond 1.2 A (1.55 A minimum current limit) through the PD during normaloperation.
Likewise, the TPS2373-4 integrates a low 0.1-Ω internal switch to support Type-4 applications up to 90 W ofcontinuous power sourced by the PSE, allowing up to 1.9 A through the PD during normal operation.
The TPS2373 has a built-in inrush time delay period, for a simple solution to meet the IEEE802.3bt startuprequirement.
The TPS2373 features an auxiliary power detect (APD) input, providing priority for an external power adapter.
The TPS2373 contains several protection features such as thermal shutdown, current limit foldback, and a robust100-V internal switch.
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7.2Functional Block Diagram
TPS2373
VC_OUT
Xfrmer Aux Bias Supply
PWMCSS
UCC2897A
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7.3Feature Description
7.3.1APD Auxiliary Power Detect
The APD pin is used in applications that may draw power either from the Ethernet cable or from an auxiliarypower source. When a voltage of more than about 1.65 V is applied on the APD pin relative to RTN, theTPS2373 does the following:•Internal pass MOSFET is turned off
•Classification current is disabled
•PG, TPL and BT outputs are forced to high impedance
•TPH output is turned on (low state)
•PWM startup is enabled without any inrush delay and over the full VDD voltage range, to allow operation froma low-voltage auxiliary power source
•The device will not properly detect due to PWM startup being enabled at low VDD voltage
•Maintain Power Signature (MPS) pulsed mode is enabled
This also gives adapter source priority over the PoE. A resistor divider (RAPD1–RAPD2 in Figure 30) providessystem-level ESD protection for the APD pin, discharges leakage from the blocking diode (DA in Figure 30) andprovides input voltage supervision to ensure that switch-over to the auxiliary voltage source does not occur atexcessively low voltages. If not used, connect APD to RTN.
Note that RAPD2 must be no more than 200 kΩ.
7.3.2PG Power Good (Converter Enable) Pin Interface
PG is an active high output that is pulled to RTN when the device is in inrush phase. It remains in a highimpedance state at all other times. This pin is an open-drain output, and it may require a pullup resistor or otherinterface to the downstream load. PG may be left open if it is not used.
The PG pin can be used to inhibit downstream converter startup by keeping the soft-start pin low. Figure 21shows an example where PG connects to the SS pin of a DC-DC controller. Because PG is an open drainoutput, it will not affect the soft-start capacitor charge time when it deasserts. Another common use of the PG pinis to enable a converter with an active-high enable input. In this case, PG may require a pullup resistor to eitherVDD, or to a bias supply, depending on the requirements of the controller enable pin.
Figure 21. PG Interface
7.3.3CLSA and CLSB Classification
Each of the two external resistors (RCLSA and RCLSB in Figure 30) connected between the CLSA (first and secondclass event) and CLSB (third and any subsequent class event) pins and VSS provide a distinct classificationsignature to the PSE, and are used to define the power class requested by the PD. The controller places avoltage of approximately 2.5 V across CLSA (first or second class event) or CLSB (all additional class events)external resistor whenever the voltage differential between VDD and VSS lies from about 10.9 V to 22 V. Thecurrent drawn by each resistor, combined with the internal current drain of the controller and any leakage throughthe internal pass MOSFET, creates the classification signature current. Table 1 lists the external resistor values
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Feature Description (continued)
required for each of the PD power ranges defined by IEEE802.3bt. The number of classification cycles thendetermines how much power is allocated by the PSE. The maximum average power drawn by the PD, plus thepower supplied to the downstream load, should not exceed the maximum power indicated in Table 1, as well asthe maximum power allocated by the PSE based on the number of classification cycles. Holding APD highdisables the classification signatures.
Type 2 and Type 3 PSEs may perform two classification cycles if Class 4 signature is presented on the firstcycle. Likewise, Type 3 and Type 4 PSEs may perform four classification cycles if Class 4 signature is presentedon the first two cycles and Class 0 or 1 signature is presented on the third cycle. Also, Type 4 PSEs may performfive classification cycles if Class 4 signature is presented on the first two cycles and Class 2 or 3 signature ispresented on the third cycle.
Table 1. Class Resistor Selection
PD ClassCLASS
SIGNATURE A
SIGNATURE B
MINIMUM
POWER AT PD
MAXIMUM
POWER AT PD
NUMBER OF
CYCLES @MAX POWER
RESISTORCLSA (Ω)
RESISTORCLSB (Ω)
0000.4412.95112101210
1110.443.841249249
2223.846.491140140
3336.4912.95190.990.9
44412.9525.52,363.463.4
54025.540463.41210
6414051463.4249
7425162563.4140
8436271563.490.9
7.3.4DEN Detection and Enable
DEN pin implements two separate functions. A resistor (RDEN in Figure 30) connected between VDD and DENgenerates a detection signature whenever the voltage differential between VDD and VSS lies from approximately1.4 to 10.9 V. Beyond this range, the controller disconnects this resistor to save power. The IEEE 802.3btstandard specifies a detection signature resistance, RDEN from 23.75 kΩ to 26.25 kΩ, or 25 kΩ ± 5%. TIrecommends a resistor of 24.9 kΩ ± 1% for RDEN.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET and class regulator to turnoff. If the resistance connected between VDD and DEN is divided into two roughly equal portions, then theapplication circuit can disable the PD by grounding the tap point between the two resistances, whilesimultaneously spoiling the detection signature which prevents the PD from properly re-detecting.
7.3.5Internal Pass MOSFET
RTN pin provides the negative power return path for the load. Once VVDD exceeds the UVLO threshold, theinternal pass MOSFET pulls RTN to VSS. Inrush limiting prevents the RTN current from exceeding a nominalvalue of about 200 mA and 335 mA for the TPS2373-3 and TPS2373-4 respectively until the bulk capacitance(CBULK in Figure 30) is fully charged. Two conditions must be met to reach the end of inrush phase. The first oneis when the RTN current drops below about 90% of nominal inrush current at which point the current limit ischanged to 1.85 A for TPS2373-3 and 2.2 A for TPS2373-4, while the second one is to ensure a minimum inrushdelay period of ~81.5 ms (tINR_DEL) from beginning of the inrush phase. The PG output becomes high impedanceto signal the downstream load that the bulk capacitance is fully charged and the inrush period has beencompleted.
If RTN ever exceeds about 14.5 V for longer than ~1.65 ms, then the TPS2373 returns to inrush phase; note thatin this particular case, the second condition described above about inrush phase duration (81.5 ms) is notapplicable.
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(1)The BT output is not required to indicate how much power is allocated to the PD by a IEEE802.3bt compliant PSE. Additionalinformation may be provided depending on the application described in the Application Detailed Design Requirements section Opto-isolators for TPH, TPL and BT
7.3.6TPH, TPL and BT PSE Type Indicators
The state of BT, TPH and TPL is used to provide information relative to the PSE Type (1-2 or 3-4) and itsallocated power. Table 2 lists the encoding corresponding to various combinations of PSE Type, PD Class andallocated power. Table 3 also corresponds to cases where the PSE allocated power is lower than what the PD isrequesting. The allocated power is determined by the number of classification cycles having been received.During startup, the TPH, TPL and BT outputs are enabled typically 24 ms after VVC_IN went high, to allow thepower supply to reach a stable state first. In applications where VC_IN is tied to a DC voltage already presentbefore end of inrush, the 24-ms delay applies from when PG output went from low to open state. These 3outputs will return to a high-impedance state if the part enters thermal shutdown, if VC_OUT voltage falls belowits UVLO threshold, or if VDD-to-VSS voltage falls below ~32 V. Note that in all these cases, as long as VDD-to-VSS voltage remains above the mark reset threshold, the internal logic state of these 3 signals is rememberedsuch that these outputs will be activated accordingly after the startup has completed. This circuit resets when theVDD-to-VSS voltage drops below the mark reset threshold. The TPH, TPL and BT pins can be left unconnectedif not used.
Table 2. TPH, TPL, BT and Allocated Power Truth Table
PSE TypePD ClassNUMBER OF
CLASS CYCLES
ALLOCATEDPOWER AT PD
TPHTPLBT(1)
1-20112.95HIGHHIGHHIGH
1-2113.84HIGHHIGHHIGH
1-2216.49HIGHHIGHHIGH
1-23112.95HIGHHIGHHIGH
24225.5HIGHLOWHIGH
3-40112.95HIGHHIGHLOW
3-4113.84HIGHHIGHLOW
3-4216.49HIGHHIGHLOW
3-43112.95HIGHHIGHLOW
3-442-325.5HIGHLOWLOW
3-45440LOWHIGHLOW
3-46451LOWHIGHLOW
47562LOWLOWLOW
48571LOWLOWLOW
Table 3. Power Demotion Cases
PSE TypePD ClassNUMBER OF
CLASS CYCLES
ALLOCATEDPOWER AT PD
TPHTPLBT
3-44-8112.95HIGHHIGHLOW
3-45-82,325.5HIGHLOWLOW
3-47-8451LOWHIGHLOW
7.3.7VC_IN, VC_OUT, UVLO_SEL, and Advanced PWM Startup
VC_OUT provides the auxiliary power supply for the external DC-DC controller. After the inrush phase hascompleted, VC_OUT initially sources the startup current from VDD input, then it is internally connected to VC_INonce VVC_IN has exceeded approximately 8.5 V, meaning that the DC-DC converter has ramped up its outputvoltage, or if VVC_IN has remained below 8.5 V for more than about 50 ms (time out period). VC_IN is usually fedby a bias winding of the DC-DC converter's power transformer to sustain operation after startup. The startup
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current source is turned on at the end of the inrush phase, and it is turned off about 24 ms after the VC switch,connecting VC_IN and VC_OUT together, has been turned on. Due to the high current capability of the startupsource, the recommended capacitance at VC_OUT is relatively small, typically 1 µF in most applications,including when there is auxiliary power input in the range of 20V and higher. VC_IN capacitance is also typically1/10 of VC_OUT capacitance to avoid a significant voltage drop at VC_OUT when the VC switch is turned on.
Once VVC_OUT falls below its UVLO threshold, the startup current source is turned back on, while the VC switch isturned off, initiating a new PWM startup cycle. The UVLO_SEL input is used to select the VC_OUT UVLOthreshold between ~6.9 V and ~3.9 V, which should be slightly below the minimum falling UVLO threshold of thePWM controller. The VC switch is also turned off when V(VDD-VSS) drops below the POE UVLO fallingthreshold.
If VC_OUT is not used, VC_IN must be connected to the low voltage bias supply of the PWM controller to ensureproper operation.
7.3.8AMPS_CTL, MPS_DUTY and Automatic MPS
To maintain PSE power, the AMPS_CTL output generates voltage pulses. This is translated into current pulsesby connecting a resistor between AMPS_CTL and VSS. These pulses are automatically generated as long as thecurrent through the RTN-to-VSS path is not high enough (< ~28 mA). Typical resistor value of 1.3 kΩ isrecommended, in applications where the load current may go below ~20 mA and the PSE power has to bemaintained.
If a Type 3 or 4 PSE is detected, the MPS_DUTY input can be used to select one out of three duty-cycles (5.4%,8.1%, 12.5%). The selection is based on various system parameters, which include the amount of bulkcapacitance, the input cable impedance and the type of input bridge. Also, inserting a blocking diode (orMOSFET) between the bulk capacitor and the TPS2373 allows the selection of a shorter MPS duty-cycle.Table 4should be used to select a proper MPS Duty Cycle.
Table 4. MPS Duty-Cycle Selection
PSE TypeMPS_DUTYMPS Duty-Cycle
1,2-26%
3,4Short to VSS12.5%
3,4Resistance (60.4K typ.) to VSS8.1%
3,4Open5.4%
(1)Applicable when PSE voltage step-down events are unlikely or are not expected to exceed -0.4 V.
Table 5. System Conditions and MPS Duty-Cycle
Expected PoE PD System ConditionsMPS_DUTY Selection
Blocking DiodeCBULKCable LengthMPS
Duty-cyclePin TerminationIMPS (mA)
YesAny
0 -100m
5.4% or longerOpen18.5
No≤ 60 µF8.1% or longer60 kΩ to VSS18.5
No> 60 µF, ≤ 120 µF12.5%Short to VSS18.5
No≤ 120 µF5.4% or longer(1)Open18.5
No> 120 µF, ≤ 300 µF8.1% or longer (1)60 kΩ to VSS18.5
7.3.9VDD Supply Voltage
VDD pin connects to the positive side of the input supply. It provides operating power to the PD controller andallows monitoring of the input line voltage. If VVDD falls below its UVLO threshold and goes back above it, or if athermal shutdown resumes while VVDD is already above its UVLO threshold, the TPS2373 returns to inrushphase.
7.3.10VSS
VSS pin is the input supply negative rail that serves as a local ground. The exposed thermal PAD must beconnected to this pin to ensure proper operation.
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7.3.11Exposed Thermal PAD
The exposed thermal PAD is internally connected to VSS pin. It should be tied to a large VSS copper area on thePCB to provide a low resistance thermal path to the circuit board. TI recommends maintaining a clearance of0.025” between VSS and high-voltage signals such as VDD.
7.4Device Functional Modes
7.4.1PoE Overview
The following text is intended as an aid in understanding the operation of the TPS2373 but not as a substitute forthe IEEE 802.3bt standard. The pending IEEE 802.3bt standard is an update to IEEE 802.3-2012 clause 33(PoE), adding 4-pair power, high-power options, additional features and enhanced classification. Generallyspeaking, a device compliant to IEEE 802.3-2012 is referred to as a Type 1 (Class 0-3) or 2 (Class 4) device,and devices with higher power and enhanced classification will be referred to as Type 3 (Class 5,6) or 4 (Class7,8) devices. Type 3 devices will also include Class 0-4 devices that are 4-pair capable. Standards change andshould always be referenced when making design decisions.
The IEEE 802.3bt standard defines a method of safely powering a PD (powered device) over a cable by powersourcing equipment (PSE), and then removing power if a PD is disconnected. The process proceeds through anidle state and three operational states of detection, classification, and operation. There is also a fourthoperational state used by Type 3 and 4 PSEs, called "connection check", to determine if the PD has same(single interface) or independent (dual interface or commonly referred to "dual-signature" in the IEEE802.3btstandard) classification signature on each pairset. The PSE leaves the cable unpowered (idle state) while itperiodically looks to see if something has been plugged in; this is referred to as detection, and also includesconnection check if Type 3 or 4 PSE. The low power levels used during detection and connection check areunlikely to damage devices not designed for PoE. If a valid PD signature is present, the PSE may inquire howmuch power the PD requires; this is referred to as classification. The PSE may then power the PD if it hasadequate capacity.
Type 3 or Type 4 PSEs are required to do an enhanced hardware classification of Type 3 or 4 respectively. Type2 PSEs are required to do Type 1 hardware classification plus a data-layer classification, or an enhanced Type 2hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL) classification. AType 3 or Type 4 PD must do respectively Type 3 or Type 4 hardware classification as well as DLL classification.A Type 2 PD must do Type 2 hardware classification as well as DLL classification. The PD may return thedefault, 13-W current-encoded class, or one of four other choices if Type 2, one of six other choices if Type 3,and one of eight other choices if Type 4. DLL classification occurs after power-on and the Ethernet data link hasbeen established.
Once started, the PD must present a maintain power signature (MPS) to assure the PSE that it is still present.The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returnsthe PSE to the idle state. Figure 22 shows the operational states as a function of PD input voltage.
5742373020.514.510.12.7
Detection Lower Limit
Detection Upper Limit
Classification Lower Limit
Classification Upper Limit
Must Turn Off by - Voltage Falling
Lower Limit -Operating Range
Must Turn On by- Voltage Rising
Maximum InputVoltage
DetectClassifyShut-down
PI Voltage (V)0
Lower Limit -13W Op.
Class-MarkTransition
250PsTransient
Normal Operation
       Normal   Operation                    
TPH/TPL Reset Range
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Device Functional Modes (continued)
Figure 22. Operational States
The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD inputrequirements differ from PSE output requirements to account for voltage drops and operating margin. Thestandard allots the maximum loss to the cable regardless of the actual installation to simplify implementation.IEEE 802.3-2008 was designed to run over infrastructure including ISO/IEC 11801 class C (CAT3 per TIA/EIA-568) that may have had AWG 26 conductors. IEEE 802.3at Type 2 and IEEE 802.3bt Type 3 cabling power lossallotments and voltage drops have been adjusted for 12.5-Ω power loops per ISO/IEC11801 class D (CAT5 orhigher per TIA/EIA-568, typically AWG 24 conductors). Table 6 shows key operational limits broken out for thetwo revisions of the standard.
Table 6. Comparison of Operational Limits
STANDARD
POWER LOOPRESISTANCE
PSE OUTPUTPOWER (MIN)
PSE STATIC OUTPUT
VOLTAGE (MIN)
PD INPUT
POWER (MAX)
STATIC PD INPUT VOLTAGE
POWER ≤ 13 WPOWER > 13 W
IEEE802.3-2012802.3at (Type 1)20 Ω
15.4 W
13 W37 V – 57 VN/A
802.3bt (Type 3)12.5 Ω50 V
802.3at (Type 2)802.3bt (Type 3)
12.5 Ω30 W50 V25.5 W37 V – 57 V42.5 V – 57 V
802.3bt (Type 3)6.25 Ω (4-pair)60 W50 V51 WN/A42.5 V - 57 V
802.3bt (Type 4)6.25 Ω (4-pair)90 W52 V71.3 WN/A41.2 V - 57 V
The PSE can apply voltage either between the RX and TX pairs (pins 1–2 and 3–6 for 10baseT or 100baseT), orbetweenthetwosparepairs(4–5and7–8).Powerapplicationtothesamepincombinationsin
1000/2.5G/5G/10GbaseT systems is recognized in IEEE 802.3bt. 1000/2.5G/5G/10GbaseT systems can handledata on all pairs, eliminating the spare pair terminology. Type 1 and 2 PSEs are allowed to apply voltage to onlyone set of pairs at a time, while Type 3 and 4 PSEs may apply power to one or both sets of pairs at a time. ThePD uses input diode or active bridges to accept power from any of the possible PSE configurations. The voltagedrops associated with the input bridges create a difference between the standard limits at the PI and theTPS2373 specifications.
A compliant Type 2, 3 or 4 PD has power management requirements not present with a Type 1 PD. Theserequirements include the following:1. Must interpret respectively Type 2, 3 or 4 hardware classification.2. Must present hardware Class 4 during the first two classfication events, applicable to Type 2 and 4 PDs, as
well as to Type 3 PD with Class level 4 or higher.
VUVLO_R
Detection
Classification
PD Powered
VCL_ON
VCU_ON
Note:  Variable names refer to Electrical Characteristic          Table parameters
VDD-VSS
VUVLO_H
Functional State
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3. If Type 3 or 4 single interface PD, it must present hardware Class in the range of 0 to 3 during the third and
any subsequent classification events.
4. Must implement DLL negotiation.5. Must behave like a Type 1 PD for 50 ms then must draw less than 400 mA until 80 m after the PSE applies
operation voltage (power up), if Type 2 or 3 single interface PD. This covers the PSE inrush period, which is75 ms maximum.
6. Should behave like a Type 1 PD for 50 ms then must draw less than 400 mA until 80 ms after the PSE
applies operation voltage (power up), if Type 4 single interface PD.
7. Must not draw more than 60 mA and 5 mA any time the input voltage falls below respectively 30 V and 10 V.8. Must not draw more than 13 W if it has not received at least a Type 2 hardware classification or received
permission through DLL.
9. Must not draw more than 25.5 W if it has not received at least 4 classification events or received permission
through DLL.
10. Must not draw more than 51 W if it has not received at least 5 classification events or received permission
through DLL.
11. Must meet various operating and transient templates.12. Optionally monitor for the presence or absence of an adapter (assume high power).
As a result of these requirements, the PD must be able to dynamically control its loading, and monitor TPL andTPH for changes. In cases where the design needs to know specifically if an adapter is plugged in andoperational, the adapter should be individually monitored, typically with an optocoupler.
7.4.2Threshold Voltages
The TPS2373 has a number of internal comparators with hysteresis for stable switching between the variousstates. Figure 23 relates the parameters in Electrical Characteristics to the PoE states. The mode labeled Idlebetween Classification and Operation implies that the DEN, CLSA, CLSB, and RTN pins are all high impedance.The state labeled Mark, which is drawn in dashed lines, is part of the Type 2-3-4 hardware class state machine.
Figure 23. Threshold Voltages
7.4.3PoE Startup Sequence
The waveforms of Figure 24 demonstrate detection, classification , and startup from a PSE with Type 3 Class 6hardware classification. The key waveforms shown are V(VDD-VSS), V(RTN-VSS) and IPI. IEEE 802.3bt requires a PSEallocating Class 6 level of power to generate a minimum of two detection levels, four class and mark cycles, andstartup from the fourth mark event. As shown below, the required minimum duration of the first class event hasbeen extended for Type 3 and 4 PSEs. VRTN to VSS falls as the TPS2373 charges CBULK following application offull voltage. In Figure 26, assertion of the PG signal is delayed and used to enable load current as seen in the IPIwaveform.
Time: 50ms/div
Voltage: 10V/divCurrent: 100mA/div
Inrush(TPS2373-3)
Load enabled after Startup delay
Detect
ClassMark
VVDD-VSS
VRTN-VSS
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Figure 24. Startup of Class 6 PD
7.4.4Detection
The TPS2373 pulls DEN to VSS whenever V(VDD-VSS) is below the lower classification threshold. When the inputvoltage rises above VCL_ON, the DEN pin goes to an open-drain condition to conserve power. While in detection,RTN is high impedance, and almost all the internal circuits are disabled. An RDEN of 24.9 kΩ (±1%), presents thecorrect signature. It may be a small, low-power resistor because it only sees a stress of about 5 mW. A valid PDdetection signature is an incremental resistance ( ΔV / ΔI ) from 23.7 kΩ to 26.3 kΩ at the PI.
The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with theparallel combination of RDEN and internal VDD loading. The input diode bridge’s incremental resistance may behundreds of Ω at the low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is partiallycompensated by the TPS2373 effective resistance during detection.
The hardware classification protocol of IEEE 802.3bt specifies that a Type 2, 3 or 4 PSE drops its output voltageinto the detection range during the classification sequence. The PD is required to have an incorrect detectionsignature in this condition, which is referred to as a mark event (see Figure 24). After the first mark event, theTPS2373 will present a signature less than 12 kΩ until it has experienced a V(VDD-VSS) voltage below the markreset threshold (VMSR). This is explained more fully under Hardware Classification.
7.4.5Hardware Classification
Hardware classification allows a PSE to determine a PD’s power requirements before powering, and helps withpower management once power is applied. Type 2, 3, and 4 hardware classification permits high power PDs todetermine whether the PSE can support its high-power operation. The number of class cycles generated by thePSE prior to turn on indicates to the PD if it allots the power requested or if the allocated power is less thanrequested, in which case there is power demotion as shown in
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Table 3. A Type 2 PD always presents Class 4 in hardware to indicate that it is a 25.5W device. A Class 5 or 6Type 3 PD presents Class 4 in hardware during the first two class events and it presents Class 0 or 1,respectively, for all subsequent class events. A Class 7 or 8 Type 4 PD presents Class 4 in hardware during thefirst two class events and it presents Class 2 or 3, respectively, for all subsequent class events. A Type 1 PSEwill treat a Class 4 to 8 device like a Class 0 device, allotting 13 W if it chooses to power the PD. A Type 2 PSEwill treat a Class 5 to 8 device like a Class 4 device, allotting 25.5W if it chooses to power the PD. A Class 4 PDthat receives a 2-event class, a Class 5 or 6 PD that receives a 4-event class, or a Class 7 or 8 PD that receivesa 5-event class, understands that the PSE has agreed to allocate the PD requested power. In the case wherethere is power demotion, the PD may choose to not start, or to start while not drawing more power than initiallyallocated, and request more power through the DLL after startup. The standard requires a Type 2, 3 or 4 PD toindicate that it is underpowered if this occurs. Startup of a high-power PD at lower power than requestedimplicitly requires some form of powering down sections of the application circuits.
The maximum power entries in Table 1 determine the class the PD must advertise. The PSE may disconnect aPD if it draws more than its stated class power, which may be the hardware class or a DLL-derived power level.The standard permits the PD to draw limited current peaks that increase the instantaneous power above theTable 1 limit; however, the average power requirement always applies.
The TPS2373 implements one- to five-event classification. RCLSA and RCLSB resistor values define the class ofthe PD. DLL communication is implemented by the Ethernet communication system in the PD and is notimplemented by the TPS2373.
The TPS2373 disables classification above VCU_ON to avoid excessive power dissipation. CLSA/B voltage isturned off during PD thermal limiting or when APD or DEN is active. The CLSA and CLSB outputs are inherentlycurrent-limited, but should not be shorted to VSS for long periods of time.
Figure 25 shows how classification works for the TPS2373. Transition from state-to-state occurs whencomparator thresholds are crossed (see Figure 22 and Figure 23). These comparators have hysteresis, whichadds inherent memory to the machine. Operation begins at idle (unpowered by PSE) and proceeds withincreasing voltage from left to right. A 2- to 5-event classification follows the (heavy lined) path towards thebottom, ending up with a latched TPL/TPH decode along the lower branch that is highlighted. Once the valid pathto the PSE detection is broken, the input voltage must transition below the mark reset threshold to start anew.
DetectClass
MarkClass
MarkClassBetween Ranges
Between Ranges
OperatingTPL/TPHopen-drain
OperatingTPL lowTPH open-drain
Between Ranges
UVLORising
UVLOFalling
UVLORising
UVLOFalling
TYPE 2 or 3 PSE Hardware Class
TYPE 1 or 3 PSE Hardware Class
Between Ranges
PoE Startup Sequence
Mark Reset
MarkClassBetween Ranges
OperatingTPL/TPH low
UVLORising
TYPE 4 PSE Hardware Class
PoE Startup Sequence
MarkClass
Between Ranges
ClassMark
MarkClassBetween Ranges
OperatingTPH lowTPL open-drain
UVLORising
UVLOFalling
TYPE 3 PSE Hardware Class
PoE Startup Sequence
Between Ranges
ClassMark
TYPE 3 PSE Hardware Class
UVLOFalling
Between Ranges
ClassMark
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Figure 25. Up to Five-Event Class Internal States
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7.4.6Inrush and Startup
IEEE 802.3bt has a startup current and time limitation, providing compatibility between a PSE of any Type and aPD of any Type. The PSE inrush limit varies according to the allotted power. If Class 0 to 4, Class 5 to 6 or Class7 to 8, the inrush limit is respectively from 400 mA to 450 mA, 400 mA to 900 mA or 800 mA to 900 mA. PSEinrush limit applies for up to 75 ms after power up (applying "48 V" to the PI), after which the Type 2, 3, or 4 PSEwill support a higher output current in accordance with the allocated class. The TPS2373-3 and TPS2373-4respectively implement a 200-mA and 335-mA inrush current, which is compatible with all PSE Types. A high-power PD must limit its converter startup peak current. The operational current for Type 2 and 3, and preferablyType 4, cannot exceed 400 mA for a period of 80 ms.
7.4.7Maintain Power Signature
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operatingvoltage is applied. For a Type 1 or Type 2 PD, a valid MPS consists of a minimum dc current of 10 mA, or a 10-mA pulsed current for at least 75 ms every 325 ms, and an AC impedance lower than 26.3 kΩ in parallel with0.05 μF. Only Type 1 and Type 2 PSEs monitor the AC MPS. A Type 1 or Type 2 PSE that monitors only the ACMPS may remove power from the PD.
To enable applications with stringent standby requirements, IEEE802.3bt introduced a significant changeregarding the minimum pulsed current duration to assure the PSE will maintain power. This applies to all Type 3and Type 4 PSEs, and the pulse duration is ~10% of what is required for Type 1 and 2 PSEs. The MPS currentamplitude requirement for Class 5-8 PDs have also increased to 16 mA at the PSE end of the ethernet cable.
If the current through the RTN-to-VSS path is below ~28 mA, the TPS2373 automatically generates the MPSpulsed current through the AMPS_CTL output pin, the current amplitude being adjustable with an externalresistor. The TPS2373 is also able to determine if the PSE is of Type 1-2 or Type 3-4, automatically adjusting theMPS pulse duration and duty-cycle. Note that the IEEE802.3bt requirement for the PD is applicable at the PSEend of the cable. That means that depending the cable length and other parameters including the bulkcapacitance, a longer MPS duration may be required to ensure a valid MPS. For that purpose, the TPS2373 has3 different selections of MPS pulse duration and duty-cycle, selectable through the MPS_DUTY input pin. Notethat the MPS pulsed mode also applies when APD is pulled high.
When DEN is used to force the hotswap switch off, the DC MPS will not be met. A PSE that monitors the DCMPS will remove power from the PD when this occurs.
7.4.8Advanced Startup and Converter Operation
The internal PoE UVLO (Undervoltage Lock Out) circuit holds the hotswap switch off before the PSE provides fullvoltage to the PD. This prevents the downstream converter circuits from loading the PoE input during detectionand classification. The converter circuits will discharge CBULK while the PD is unpowered. Thus V(VDD-RTN) will bea small voltage just after full voltage is applied to the PD, as seen in Figure 24. The PSE drives the PI voltage tothe operating range once it has decided to power up the PD. When VVDD rises above the UVLO turn-on threshold(VUVLO_R, approximately 38 V) with RTN high, the TPS2373-3 and TPS2373-4 enables the hotswap MOSFETwith inrush current limit (~200 mA for TPS2373-3 and ~335 mA for TPS2373-4) as seen in Figure 26. The PGpin is in low state while CBULK charges and VRTN falls from VVDD to nearly VVSS. VC_OUT output is also turned offduring that time, providing no low supply voltage to the PWM controller, to avoid additional loading between VVDDand VRTN that could prevent successful PD and subsequent converter start up. Once the inrush current fallsabout 10% below the inrush current limit, the PD current limit switches to the operational level (approximately1.85 A for TPS2373-3 and approximately 2.2 A for TPS2373-4).
Additionally, as seen in Figure 26 once the inrush period duration has also exceeded ~81.5 ms, PG outputbecomes high impedance and the PWM controller startup source is turned on charging CVC_OUT, the VC_OUTcapacitor, and allowing the downstream converter circuitry to start. As seen in Figure 27, the converter soft-startintroduces a slight additional delay before the start of switching. Note that the startup source current capability issuch that it can fully maintain VVC_OUT during the converter soft-start without requiring any significant CVC_OUTcapacitance. Once VVC_IN has risen above VVCIN_ON (~8.5 V), meaning that the DC-DC converter has ramped upits output voltage, VC_IN pin is internally connected to VC_OUT pin. The startup current source is then turned off~24 ms (tTPLHBT) later, completing the startup. TPH, TPL and BT outputs are enabled within tTPLHBT followingVVC_IN rising above VVCIN_ON. If there is a fault condition preventing VVC_IN from rising during converter startup (forexample a short-circuit at the output of the downstream converter), a tSTUP_OUT (~50 ms) timeout period is appliedat the end of which the startup source is turned off and the VC switch is turned on, until VVC_OUT falls belowVVCO_UV to initiate a new startup cycle.
PSE Inrush
HSW cap rechargeVC_OUT Startup Release PG
Ensures interoperability with PSE inrush limit
Startup source capable to sustain long soft start period
VC_IN present and stable:turn off Startup, connect VC_IN to VC_OUT
tinrush max
PD + Power Supply Fully Operational
Operational Mode
tinrush min
SSdelay
Time: 20ms/div
5V/div
200mA/div
Inrush (TPS2373-4)
Load enabled 
VVDD-RTN
VPG-RTN
VVC_OUT-RTN10V/div
50V/div
PI powered
VVC_IN-RTN
soft start
TPH/TPL enabled,Startup source turn off
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The falling VC_OUT UVLO threshold (VVCO_UV) needs to be below the minimum falling UVLO threshold of thePWM controller, to ensure that every time the TPS2373 initiates a new startup cycle, the PWM controller hasalready reached a reset state and will initiate a new soft-start sequence. VVCO_UV is selectable between nominally6.9 V and 3.9 V, via the UVLO_SEL input, to accommodate various PWM controllers.
Figure 26. Power Up and Start
Figure 27. Power Up and Start
If VVDD-VVSS drops below the lower PoE UVLO (VUVLO_F, ~32 V), the hotswap switch is turned off, but the PGoutput remains high impedance allowing the converter to continue operating until VVC_OUT falls below the PWMcontroller's UVLO threshold. See VC Input and Output, CVCIN and CVCOUT for general guidance on how to handlePoE shutdown conditions.
Time: 400us/div
5V/div
2A/div
Inrush
 VRTN-VSS > 15V
VRTN-VSS
VPG-VSS
20V/div
Current Limit  (TPS2373-4)
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7.4.9PD Hotswap Operation
IEEE802.3bt includes new PSE output limiting requirements for Type 3 and 4 operation to cover higher powerand 4-pair applications. Type 2, 3 and 4 PSEs must meet an output current vs time template with specifiedminimum and maximum sourcing boundaries. The peak output current per each 2-pair may be as high as 50 Afor 10 μs or 1.75 A for 75 ms, and the total peak current becomes twice these values when power is deliveredover 4 pairs. This makes robust protection of the PD device even more important than it was in IEEE 802.3-2012.
The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit anddeglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with V(RTN-
VSS) rising as a result. If V(RTN-VSS) rises above approximately 14.5 V for longer than approximately 1.65 ms, thecurrent limit reverts to the inrush value and PG output is forced low which turns off the converter, although thereis no minimum inrush delay period (81.5-ms) applicable in this case. The 1.65-ms deglitch feature preventsmomentary transients from causing a PD reset, provided that recovery lies within the bounds of the hotswap andPSE protection. Figure 28 shows an example of the RTN current profile during VDD to RTN short circuit, using 5-ohm load impedance. The hotswap MOSFET goes into current limit, causing the RTN voltage to increase. OnceVRTN exceeds 14.5 V, IRTN, which was clamped to the current limit drops to the level of inrush current limit after1.65 ms.
The inrush current limit is also reestablished when V(VDD-VSS) drops below UVLO then rises above it.
Figure 28. Response to PD Output Short Circuit
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The PD control has thermal sensors that protect the internal hotswap MOSFET, the startup current source andthe MPS pulsed current driver. Conditions like startup or operation into a VDD-to-RTN short cause high powerdissipation in the MOSFET. An over-temperature shutdown (OTSD) turns off the hotswap MOSFET, the classregulator, the startup current source, and the MPS driver, which are restarted after the device cools. Thehotswap MOSFET will be re-enabled and the TPS2373 will return to inrush phase when exiting from anovertemperature event. Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET toturn off. This feature allows a PD with option three ORing per Figure 29 to achieve adapter priority.
The hotswap switch will be forced off under the following conditions:1. VAPD above VAPDEN (approximately 1.65 V),2. V(DEN –VSS) < VPD-DIS when V(VDD-VSS) is in the operational range,3. PD is over-temperature, or4. V(VDD –VSS) < PoE UVLO falling threshold (approximately 32 V).
7.4.10Startup and Power Management, PG and TPH, TPL, BT
PG (power good or converter enable) is a pin that when at low level indicates when the internal hotswapMOSFET is in inrush phase. PG goes high impedance when inrush phase is over and can be used to enable adownstream converter to start up. Common interfaces to the converter controller include the soft-start or enablepins.
TPH, TPL and BT provide information relative to the PSE Type (1-2 or 3-4) and its allocated power. It can alsoindicate if the APD is driven high, in which case the code becomes "Low-High-High", respectively.
Using the APD encoding allows the PD to operate from an adapter at high-power if a PSE with enough powercapability is not present, assuming the adapter has sufficient capacity. Applications must monitor the state ofTPH, TPL and BT to detect power source transitions. Transitions could occur when a local power supply isadded or dropped, or when a PSE is enabled on the far end. The PD may be required to adjust the loadappropriately. The usage of TPH/TPL/BT is demonstrated in Figure 30.
The TPS2373 is also able to interoperate with non standard PoE++ PSE controllers. If powered from a PoE++PSE controller, the TPH/TPL/BT 3-bit code becomes "Low-Low-High". This also indicates that the PoE++PSEagreed to deliver the power requested by the TPS2373.
7.4.11Adapter ORing
Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local powersolution adds cost and complexity, but allows a product to be used if PoE is not available in a particularinstallation. While most applications only require that the PD operate when both sources are present, theTPS2373 supports forced operation from either of the power sources. Figure 29 illustrates three options for diodeORing external power into a PD. Only one option would be used in any particular design. Option 1 applies powerto the TPS2373 PoE input, option 2 applies power between the TPS2373 PoE section and the power circuit, andoption 3 applies power to the output side of the converter. Each of these options has advantages anddisadvantages. Many of the basic ORing configurations and much of the discussion contained in the applicationnote Advanced Adapter ORing Solutions using the TPS23753 (SLVA306), apply to the TPS2373 incorporating aDC/DC converter.
TPS2373
RDENRCLSA/B
From EthernetTransformers
CLSA/BDENLow Voltage Output
From Spare Pairs or Transformers
Power Circuit
AdapterOption 3AdapterOption 2
AdapterOption 1
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Figure 29. Oring Configurations
The IEEE standards require that the Ethernet cable be isolated from ground and all other system potentials. Theadapter must meet a minimum 1500 Vac dielectric withstand test between the output and all other connectionsfor ORing options 1 and 2. The adapter only needs this isolation for option 3 if it is not provided by the converter.
Adapter ORing diodes are shown for all the options to protect against a reverse voltage adapter, a short on theadapter input pins, or damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET inoption 3.
7.4.12Using DEN to Disable PoE
The DEN pin may be used to turn the PoE hotswap switch off by pulling it to VSS while in the operational state, orto prevent detection when in the idle state. A low voltage on DEN forces the hotswap MOSFET off during normaloperation. Additional information is available in the Advanced Adapter ORing Solutions using the TPS23753(SLVA306) application report.
7.4.13ORing Challenges
Preference of one power source presents a number of challenges. Combinations of adapter output voltage(nominal and tolerance), power insertion point, and which source is preferred determine solution complexity.Several factors adding to the complexity are the natural high-voltage selection of diode ORing (the simplestmethod of combining sources), the current limit implicit in the PSE, and PD inrush and protection circuits(necessary for operation and reliability). Creating simple and seamless solutions is difficult, if not impossible, formany of the combinations. However, the TPS2373 offers several built-in features that simplify somecombinations.
Several examples demonstrate the limitations inherent in ORing solutions. Diode ORing a 48-V adapter with PoE(option 1) presents the problem that either source may have the higher voltage. A blocking switch would berequired to assure that one source dominates. A second example combines a 12-V adapter with PoE usingoption 2. The converter draws approximately four times the current at 12 V from the adapter than it does fromPoE at 48 V. Transition from PoE power to adapter may demand more current than can be supplied by the PSE.The converter must be turned off while the CBULK capacitance charges, with a subsequent converter restart at thehigher voltage and lower input current.
DC/DC Converter
TPS2373
From EthernetPairs 1,2
From EthernetPairs 3,4
AMPS_CTL
VC_OUT
Xfrmer Aux Bias Supply
0.1 �F
49.9 K�
VCINCINC1D1
PoE PD Design
ACAdapter
UVLO_SEL MPS_DUTY
Optional
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8Application and Implementation
Information in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.
8.1Application Information
The TPS2373 has the flexibility to be implemented in IEEE802.3bt and PoE++ PDs. Therefore, it can be used ina wide range applications such as video and VoIP telephones, multiband access points, security cameras, powermodules, LED lighting converters, and pico-base stations.
8.2Typical Application
Figure 30. Typical Application Circuit
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Typical Application (continued)
8.2.1Design Requirements
For this design example, use the parameters in Table 7 for a PD Class 8 application.
Table 7. Design Parameters
PARAMETERTEST CONDITIONSMINMAXUNIT
POWER INTERFACE
Input voltagePower applied through PoE or adapter057V
Operating voltageAfter startup3057V
Adapter voltage4057V
Input UVLO
Rising input voltage at device terminals—40
Falling input voltage30.5—
Detection voltageAt device terminals1.410.1V
Classification voltageAt device terminals11.923V
PD class 8Class signature A3842mA
PD class 8Class signature B26.529.3mA
Inrush current limit275395mA
Operating curent-limit1.92.5A
PWM controllerUCC2897A
Automatic MPS12.5% Duty Cycle at no load
8.2.2Detailed Design Requirements
8.2.2.1Input Bridges and Schottky Diodes
Using Schottky diodes instead of PN junction diodes for the PoE input bridges will reduce the power dissipationin these devices by about 30%. There are, however, some things to consider when using them. The IEEEstandard specifies a maximum backfeed voltage of 2.8 V. A 100-kΩ resistor is placed between the unpoweredpairs and the voltage is measured across the resistor. Schottky diodes often have a higher reverse leakagecurrent than PN diodes, making this a harder requirement to meet. To compensate, use conservative design fordiode operating temperature, select lower-leakage devices where possible, and match leakage and temperaturesby using packaged bridges.
Schottky diode leakage currents and lower dynamic resistances can impact the detection signature. Settingreasonable expectations for the temperature range over which the detection signature is accurate is the simplestsolution. Increasing RDET slightly may also help meet the requirement.
Schottky diodes have proven less robust to the stresses of ESD transients than PN junction diodes. Afterexposure to ESD, Schottky diodes may become shorted or leak. Take care to provide adequate protection in linewith the exposure levels. This protection may be as simple as ferrite beads and capacitors.
As a general recommendation, use 3-A to 5-A, 100-V rated discrete or bridge diodes for the input rectifiers.
Many high power PoE PD designs require the need for an active FET bridge recitifier in high efficiencyapplications. An example of an active FET bridge rectifier design can be found in the TPS2373-4EVM-758 User'sGuide.
8.2.2.2Protection, D1
A TVS, D1, across the rectified PoE voltage per Figure 30 must be used. TI recommends a SMAJ58A, orequivalent, is recommended for general indoor applications. If an adapter is connected from VDD to RTN, as inORing option 2 above, then voltage transients caused by the input cable inductance ringing with the internal PDcapacitance can occur. Adequate capacitive filtering or a TVS must limit this voltage to within the absolutemaximum ratings. Outdoor transient levels or special applications require additional protection.
8.2.2.3Capacitor, C1
The IEEE 802.3at standard specifies an input bypass capacitor (from VDD to VSS) of 0.05 μF to 0.12 μF. Typicallya 0.1 μF, 100 V, 10% ceramic capacitor is used.
OUTTPx OUTTPx OUTTPx OUT
VV50.4I0.46 mAR10000
TPH/TPL/BT From TPS2373
RTPx-OUT
VTPx-OUT 
ITPx-OUT 
40 V10 k= 1.75 V10 kR��� �
AdapterAPD2APDENAPD1APD2
VRVRR �
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8.2.2.4Detection Resistor, RDEN
The IEEE 802.3at standard specifies a detection signature resistance, RDEN between 23.7 kΩ and 26.3 kΩ, or 25kΩ ± 5%. A resistor of 24.9 kΩ ± 1% is recommended for RDEN.
8.2.2.5Classification Resistors, RCLSA and RCLSB
Connect a resistor from CLSA and CLSB to VSS to program the classification current according to the IEEE802.3bt standard. The class power assigned should correspond to the maximum average power drawn by thePD during operation. Select RCLSA and RCLSB according to Table 1.
Choose Class 4 for RCLSA = 63.4 Ω.
Choose Class 3 for RCLSB = 90.9 Ω.
8.2.2.6APD Pin Divider Network RAPD1, RAPD2
For an adapter voltage threshold to switch from PoE to adapter at 40 V, choose 10 kΩ for RAPD2.
Solving for RAPD1:
RAPD1 = 221 kΩ(3)
Consider the UVLO of the PWM controller when using APD functionality.
8.2.2.7Opto-isolators for TPH, TPL and BT
The TPH, TPL and BT pin are active-low, open-drain outputs, which give an indication about the PSE allocatedpower along with its Type. Optocouplers can interface these pins to circuitry on the secondary side of theconverter. A high-gain optocoupler and a high-impedance (for example, CMOS) receiver are recommended.Design of the optocoupler interface can be accomplished as follows:
See Table 2 to decode PSE Type
Figure 31. TPH, TPL, and BT Interface
A. As shown in Figure 31, let VCOUT = 12 V, VOUT = 5 V, RTPx–OUT = 10 kΩ, VTPx = 260 mV, VTPx-OUT = 400 mV.
B. The optocoupler current transfer ratio, CTR, is needed to determine RTPx. A device with a minimum CTR of
100% at 1 mA LED bias current, ITPx, is selected. In practice, CTR will vary with temperature, LED biascurrent, and aging, These variations may require some iteration using the CTR-versus-IDIODE curve on theoptocoupler data sheet.a. The approximate forward voltage of the optocoupler diode, VFWLED, is 1.1 V from the data sheet.
22MPSRMPSMPS
VMPS Duty Cycle24V26.4%P115 mWR1.3 k
uu   :
DDMPSMPS
V57 VR=== 3.56 kΩI16 mA
TPx-OUTTPx-MINTPx
CTPxFWLEDTPxTPx
I0.46 mAI0.46 mA, Select I1 mACTR1.00VVV12 V0.26 V1.1 VR10.6 kΩI1 mA
�������
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b. Use Equation 5.
c. Choose a 10.7 kΩ resistor.
Most applications require that only the PSE’s allocated power information (TPH and TPL) is needed for the MCUor PD load. In this case, the circuitry needed to drive the BT signal is not necessary and the BT pin can be leftfloating.
Some applications such as PoE lighting can benefit from the BT signal to show that the power consumption instandby operation may not meet regulatory requirements. In non-standard PoE applications, BT is used with TPHand TPL to indicate a PoE++ PSE.
8.2.2.8VC Input and Output, CVCIN and CVCOUT
The advanced startup circuit requires that CVCOUT ≥ 10 x CVCIN. Using the minimum requirement of CVCIN,
CVCIN = 0.1 µFChoose CVCOUT = 1 µFThe primary switching FETs driven by the PWM controller should be chosen such that its total gate charge isless than 60nC. For gate charges greater than 60nC, COUT should be increased.
CVCOUT may need to be increased when using certain DC/DC converters like Active Clamp Forward. In someDC/DC converters, a low cost diode (DVC) can be added as shown in Figure 30 to allow the DC/DC to keep itsbias voltage during PoE shutdown conditions.
8.2.2.9UVLO Select, UVLO_SEL
The Design Parameters require the PWM controller UCC2897A which has a UVLO of 8.4 V.
Choose UVLO_SEL to be open circuited
8.2.2.10Automatic MPS and MPS Duty Cycle, RMPS and RMPS_DUTY
MPS_DUTY should be short circuited to VSS for 12.5% duty cycle
Choose 1.3 kΩ rated for 1/8 W26.4% duty cycle is chosen to take into account if the PD is connected to a IEEE802.3at PSE with a longerMPS timing specification.
8.2.2.11Internal Voltage Reference, RREF
Per Recommended Operating Conditions,
Choose RREF = 49.9 kΩ
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8.2.3Application Curves
Figure 32. StartupFigure 33. Power Up and Start
Figure 34. Advanced Startup and Converter Output StartupFigure 35. Converter Output Short and Recovery
Figure 36. Auto MPS
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9Power Supply Recommendations
The TPS2373 device will typically be followed by a power supply such as an isolated flyback or active clampforward converter or a non-isolated buck converter. The input voltage of the converter should be capable ofoperating within the IEEE802.3bt recommended input voltage as shown in Table 6.
10Layout
10.1Layout Guidelines
The layout of the PoE front end should follow power and EMI/ESD best practice guidelines. A basic set ofrecommendations include:•Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diodebridges, TVS and 0.1-μF capacitor, and TPS2373.
•All leads should be as short as possible with wide power traces and paired signal and return.
•There should not be any crossovers of signals from one part of the flow to another.
•Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltagerails and between the input and an isolated converter output.
•The TPS2373 should be located over split, local ground planes referenced to VSS for the PoE input and toRTN for the switched output.
•Large copper fills and traces should be used on SMT power-dissipating devices, and wide traces or overlaycopper fills should be used in the power path.
•Nine vias are recommended on the Exposed Thermal Pad of the TPS2373. These should connect to alllayers of a copper plane on the PCB. Ensure 80% printed solder coverage by area.
10.2Layout Example
Figure 37 and Figure 38 show the top and bottom layer and assemblies of the TPS2373-4EVM-758 as areference for optimum parts placement. A detailed PCB layout can be found in the user’s guide of the TPS2373-4EVM-758 Evaluation Module (SLUUBJ1)TPS2372-4EVM-006 Evaluation Module (SLVUB75).
Figure 37. TPS2373-4EVM-758 Top Side Layout and Component Placement
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Layout Example (continued)
Figure 38. TPS2373-4EVM-758 Bottom Side Layout and Component Placement
10.3EMI Containment
•Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives).
•Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching nodes(minimize exposed radiating surface).
•Use copper ground planes (possible stitching) and top layer copper floods (surround circuitry with groundfloods).
•Use 4 layer PCB if economically feasible (for better grounding).
•Minimize the amount of copper area associated with input traces (to minimize radiated pickup).
•Use Bob Smith terminations, Bob Smith EFT capacitor, and Bob Smith plane.
•Use Bob Smith plane as ground shield on input side of PCB (creating a phantom or literal earth ground).
•Use of ferrite beads on input (allow for possible use of beads or 0-Ω resistors).
•Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads asboundary line).
•Possible use of common-mode inductors.
•Possible use of integrated RJ-45 jacks (shielded with internal transformer and Bob Smith terminations).
•End-product enclosure considerations (shielding).
10.4Thermal Considerations and OTSD
Sources of nearby local PCB heating should be considered during the thermal design. Typical calculationsassume that the TPS2373 is the only heat source contributing to the PCB temperature rise. It is possible for anormally operating TPS2373 device to experience an OTSD event if it is excessively heated by a nearby device.
10.5ESD
ESD requirements for a unit that incorporates the TPS2373 have a much broader scope and operationalimplications than are used in TI’s testing. Unit-level requirements should not be confused with reference designtesting that only validates the ruggedness of the TPS2373.
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11Device and Documentation Support
11.1Documentation Support
11.1.1Related Documentation
For related documentation see the following:•Advanced Adapter ORing Solutions using the TPS23753, SLVA306
11.2Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.
11.3Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4Trademarks
E2E is a trademark of Texas Instruments.
11.5Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
11.6Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
20X 0.380.23
2.20.1
20X 0.650.45
(DIM A) TYPOPT 01 SHOWN
0.050.00
16X 0.65
2X 2.6
A5.14.9
5.14.9
VQFN - 1 mm max heightRGW0020B
PLASTIC QUAD FLATPACK - NO LEAD
4222816/A 06/2016
OPTION 01(0.1)
DIMENSION A
OPTION 02(0.2)
PIN 1 INDEX AREA
SEATING PLANE
2016(OPTIONAL)PIN 1 ID0.1C AB
EXPOSEDTHERMAL PAD
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancingper ASME Y14.5M.2. This drawing is subject to change without notice.3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE  3.000
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EXAMPLE BOARD LAYOUT
(0.85)
0.07 MINALL AROUND
0.07 MAXALL AROUND
20X (0.31)
20X (0.75)
(0.2) TYPVIA
16X (0.65)
(4.65)
(4.65)
(0.85)
(R0.05)TYP
VQFN - 1 mm max heightRGW0020B
PLASTIC QUAD FLATPACK - NO LEAD
4222816/A 06/2016
LAND PATTERN EXAMPLESCALE:15X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literaturenumber SLUA271 (www.ti.com/lit/slua271).5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shownon this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASKOPENING
METAL UNDERSOLDER MASK
SOLDER MASKDEFINED
SOLDER MASKOPENING
NON SOLDER MASK
SOLDER MASK DETAILS
DEFINED(PREFERRED)
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EXAMPLE STENCIL DESIGN
(0.59) TYP
20X (0.75)
20X (0.31)
16X (0.65)
(4.65)
(4.65)
4X (0.98)
(0.59) TYP(R0.05) TYP
VQFN - 1 mm max heightRGW0020B
PLASTIC QUAD FLATPACK - NO LEAD
4222816/A 06/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations.
METALTYP
BASED ON 0.125 mm THICK STENCILSOLDER PASTE EXAMPLE
EXPOSED PAD80% PRINTED SOLDER COVERAGE BY AREASCALE:20X
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable DeviceStatus
Package Type PackageDrawing
Pins PackageQty
Eco Plan
Lead finish/Ball material
MSL Peak Temp
Op Temp (°C)Device Marking
Samples
TPS2373-3RGWRACTIVEVQFNRGW203000RoHS & GreenNIPDAULevel-2-260C-1 YEAR-40 to 125TPS2373-3
TPS2373-3RGWTACTIVEVQFNRGW20250RoHS & GreenNIPDAULevel-2-260C-1 YEAR-40 to 125TPS2373-3
TPS2373-4RGWRACTIVEVQFNRGW203000RoHS & GreenNIPDAULevel-2-260C-1 YEAR-40 to 125TPS2373-4
TPS2373-4RGWTACTIVEVQFNRGW20250RoHS & GreenNIPDAULevel-2-260C-1 YEAR-40 to 125TPS2373-4
 (1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device. 
(2) RoHS:  TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement. 
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. 
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device. 
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 
TAPE AND REEL INFORMATION
*All dimensions are nominal
DevicePackageType
PackageDrawing
PinsSPQReelDiameter(mm)
ReelWidthW1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
Pin1Quadrant
TPS2373-3RGWRVQFNRGW203000330.012.45.35.31.18.012.0Q2
TPS2373-3RGWTVQFNRGW20250180.012.45.35.31.18.012.0Q2
TPS2373-4RGWRVQFNRGW203000330.012.45.35.31.18.012.0Q2
TPS2373-4RGWTVQFNRGW20250180.012.45.35.31.18.012.0Q2
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
*All dimensions are nominal
DevicePackage TypePackage DrawingPinsSPQLength (mm)Width (mm)Height (mm)
TPS2373-3RGWRVQFNRGW203000367.0367.035.0
TPS2373-3RGWTVQFNRGW20250210.0185.035.0
TPS2373-4RGWRVQFNRGW203000367.0367.035.0
TPS2373-4RGWTVQFNRGW20250210.0185.035.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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