CSD95492QVM Synchronous Buck NexFET Smart Power Stage (Rev. A)
Texas Instruments | CSD95492QVM Synchronous Buck NexFET Smart Power Stage (Rev. A) | Datasheet | Texas Instruments CSD95492QVM Synchronous Buck NexFET Smart Power Stage (Rev. A) Datasheet
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CSD95492QVM
SLPS672A – JUNE 2017 – REVISED JANUARY 2018
CSD95492QVM Synchronous Buck NexFET™ Smart Power Stage
20-A Continuous Operating Current Capability
Over 94% System Efficiency at 12 A
High-Frequency Operation (up to 1.25 MHz)
Diode Emulation Function
Temperature Compensated Bi-Directional Current
Analog Temperature Output
Fault Monitoring
3.3-V and 5-V PWM Signal Compatible
Tri-State PWM Input
Integrated Bootstrap Switch
Optimized Dead Time for Shoot-Through
High-Density VSON 4-mm × 5-mm Footprint
Ultra-Low-Inductance Package
System Optimized PCB Footprint
RoHS Compliant – Lead-Free Terminal Plating
Multiphase Synchronous Buck Converters
– High-Frequency Applications
– High-Current, Low-Duty Cycle Applications
POL DC-DC Converters
Memory and Graphic Cards
Desktop and Server VR12.x / VR13.x VRM
Synchronous Buck Converters
The CSD95492QVM NexFET™ power stage is a
highly optimized design for use in a high-power, highdensity synchronous buck converter. This product
integrates the driver IC and power MOSFETs to
complete the power stage switching function. This
combination produces high-current, high-efficiency,
and high-speed switching capability in a small 4-mm
× 5-mm outline package. It also integrates the
accurate current sensing and temperature sensing
functionality to simplify system design and improve
accuracy. In addition, the PCB footprint has been
optimized to help reduce design time and simplify the
completion of the overall system design.
Device Information(1)
Application Diagram
P12V
AVSP
AVSN
ASKIP#
EN/FCCM
CSD95492QVMT
7-Inch Reel
VSON
4.00-mm × 5.00-mm
13-Inch Reel
BOOT_R
CSD95490Q5M
PWM1
PGND
IOUT REFIN
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
ACSP1
Typical Power Stage Efficiency and Power Loss
V3P3
VIN_CSNIN
CSPIN
VCCIO
BEN_VCCIO
SCLK
SDIO
SALERT#
PIN_ALT#
VR_HOT#
SMB_CLK
SMB_ALERT#
SMB_DIO
AVR_RDY
BVR_RDY
AVR_EN
VR_FAULT#
RESET#
BVSN
BVSP
BPWM1
BSKIP#
VDD = 5 V
VIN = 12 V
VOUT = 1.2 V
LOUT = 220 nH
fSW = 500 kHz
TA = 25qC
BCSP1
Power Loss (W)
APWM6
Copyright © 2016, Texas Instruments Incorporated
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
www.ti.com
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
Application Schematic .......................................... 5
Device and Documentation Support.................... 6
Receiving Notification of Documentation Updates....
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
Mechanical, Packaging, and Orderable
Information ............................................................. 7
9.1 Mechanical Drawing.................................................. 7
9.2 Recommended PCB Land Pattern............................ 8
9.3 Recommended Stencil Opening ............................... 9
4 Revision History
Changes from Original (June 2017) to Revision A
Updated Mechanical Drawing section .................................................................................................................................... 7
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Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: CSD95492QVM
5 Pin Configuration and Functions
Pin Functions
External reference voltage input for current sensing amplifier.
IOUT
Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current.
A resistor from this pin to PGND pin sets the inductor value for the internal current sensing circuitry.
Supply voltage for gate drivers and internal circuitry.
Output voltage sensing pin for the internal current sensing circuitry.
Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor.
Input voltage pin. Connect input capacitors close to this pin.
BOOTR
Return path for HS gate driver. It is connected to VSW internally.
Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic cap from BOOT to BOOTR pins.
The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated.
Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high
sets control FET gate high and sync FET gate low. Both MOSFET gates are set low if PWM stays in Hi-Z for
greater than the tri-state shutdown holdoff time (t3HT).
This dual function pin either enables the diode emulation function or can be used as a simple enable for the
device. When this pin is driven into the tri-state window and held there for more than the tri-state holdoff time,
Diode Emulation Mode is enabled for sync FET. When the pin is high, device operates in Forced Continuous
Conduction Mode. When the pin is low, both FETs are held off. An internal resistor pulls this pin low if left
TAO/FAULT
Temperature Amplifier Output. Reports a voltage proportional to the IC temperature. An ORing diode is
integrated in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of
all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown,
LSOC, or HSS detection circuit is tripped.
Power ground.
6.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise stated) (1)
VIN to PGND
VIN to VSW
VIN to VSW (10 ns)
VSW to PGND
VSW to PGND (10 ns)
VDD to PGND
EN/FCCM, TAO/FLT, LSET to PGND (2)
VDD + 0.3
IOUT, VOS, PWM to PGND
BOOT to BOOTR (2)
BOOT to PGND
Operating junction temperature
Tstg
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Should not exceed 7 V.
6.2 ESD Ratings
V(ESD)
Electrostatic discharge
Human-body model (HBM)
±2000
Charged-device model (CDM)
±500
6.3 Recommended Operating Conditions
TA = 25°C (unless otherwise stated)
Driver supply voltage
Input supply voltage
VOUT
Output voltage
PWM to PGND
Continuous output current
Peak output current (3)
VIN = 12 V, VDD = 5 V, VOUT = 1.2 V,
ƒSW = 500 kHz (2)
IOUT-PK
ƒSW
Switching frequency
CBST = 0.1 µF (min), VOUT = 2.5 V (max)
On-time duty cycle
ƒSW = 1 MHz
Minimum PWM on-time
Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
Measurement made with six 10-µF (TDK C3216X7R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins.
System conditions as defined in Note 2. Peak output current is applied for tp = 50 µs.
7 Application Schematic
Figure 1. Application Schematic
Note: The schematic in Figure 1 is a conceptual drawing only. Actual designs may require additional components
not shown.
8 Device and Documentation Support
8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
8.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Mechanical Drawing
PIN 1 INDEX AREA
1.05 MAX
0.08 C
SEATING PLANE
(0.2) TYP
2X (0.31)
16X 0.5
PIN 1 ID
(0.25 x 45° )
0.25±0.1
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical
9.2 Recommended PCB Land Pattern
SYMM
10X (0.7)
10X (0.25)
8X (0.5)
(R0.05) TYP
METAL UNDER
( 0.2) VIA
0.05 MIN
NON SOLDER MASK
(PREFERRED)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON
PCB Attachment (SLUA271).
9.3 Recommended Stencil Opening
3. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
PACKAGE OPTION ADDENDUM
Orderable Device
Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
VSON-CLIP
Pb-Free (RoHS
Exempt)
CU SN
Level-2-260C-1 YEAR
95492QM
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
*All dimensions are nominal
Package Package Pins
Type Drawing
SPQ
Diameter Width (mm)
(mm) W1 (mm)
(mm) Quadrant
VSONCLIP
Pack Materials-Page 1
Package Drawing
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