A system mode control state machine is provided to define the source of the system clock and System Controller clock inputs.
Most applications only use NORMAL mode. The other modes are used for special power down conditions.
If the Most Significant Bit (MSB) is set then the system moves into NORMAL mode.
If the MSB is not set and the next MSB is set then the system moves into SLOW mode. This is described in SLOW mode.
If only the Least Significant Bit (LSB) is set then the system moves into DOZE mode. This is described in DOZE mode.
If none of the mode control bits are set the system moves into SLEEP mode. This is described in SLEEP mode.
x denotes that the bit can be set to 0 or 1.
When the required operating mode has been defined in the system mode control register the system mode control state machine moves to the required operating mode without further software interaction.
The current system mode is output on the SYSMODE[3:0] bus and can also be read back by the processor using the ModeStatus bit in the SCCTRL Register.
Following a power-on reset the system mode control state machine enters DOZE mode.
It is the responsibility of the system integrator to ensure that all the required clock sources are active and stable before the power-on reset is released and system operation begins.
If the nPOR input is activated, the state machine and the required operating mode in the system control register are set to DOZE. If the PRESETn input is activated, the system mode control state machine does not change mode but the required operating mode is set to DOZE in the system control register.
It is possible to override the mode control bits (in the system control register) when an interrupt is generated by the VIC, see Interrupt response mode. The state transitions are shown in Figure 2.3.
The signal states that are required to achieve the modes and transitions shown in Figure 2.3 are listed in Table 2.1.
In SLEEP mode, the system clocks, HCLK and CLK, are disabled and the System Controller clock, SCLK, is driven from a slow speed oscillator (nominally 32 768Hz).
When either a FIQ or an IRQ interrupt is activated (through the VIC) the system moves into the DOZE mode. Additionally, the required operating mode in the system control register automatically changes from SLEEP to DOZE.
Before entering SLEEP mode you must ensure that the processor is in the Wait-for-interrupt state. Processor status is determined by the STANDBYWFI output from the processor.
In DOZE mode, the system clocks and the System Controller clock are driven from a low frequency oscillator.
From DOZE mode it is possible to move into SLEEP mode when none of the mode control bits are set and the processor is in Wait-for-interrupt state.
If SLOW mode or NORMAL mode is required the system moves into the XTAL control transition state to initialize the crystal oscillator.
XTAL control transition state is used to initialize the crystal oscillator. While in this state, both the system clocks and the System Controller clock are driven from a low-frequency oscillator.
The system moves into the Switch to XTAL transition state when the crystal oscillator output is stable. This is indicated when either the Xtal timeout defined in the Xtal Control Register expires (when the XTALTIMEEN input is valid) or by the XTALON input being set to logic 1.
Switch to XTAL transition state is used to initiate the switching of the system clock source from the slow speed oscillator to the crystal oscillator.
The system moves into the SLOW mode when the XTALSW input is set to a logic 1, to indicate that the clock switching is complete.
Switch from XTAL transition state is entered when moving from the SLOW mode to DOZE mode. It initiates the switching of the system clock source from the crystal oscillator to the slow speed oscillator.
The system moves into the DOZE mode when the XTALSW input is reset to a logic 0, to indicate that the clock switching is complete.
In SLOW mode, both the system clocks and the System Controller clock are driven from the output of the crystal oscillator. If NORMAL mode is required the system moves into the PLL control transition state. If neither the SLOW or the NORMAL mode control bits are set the system moves into the Switch from XTAL transition state.
PLL control transition state is used to initialize the PLL. In this mode both the systems clock and the System Controller clock are driven from the output of the crystal oscillator.
the PLLON input is set to logic 1.
Switch to PLL transition state is used to initiate the switching of the system clock source from the crystal oscillator to the PLL output.
The system moves into the NORMAL mode when the PLLSW input is set to a logic 1, to indicate that clock switching is complete.
Switch from PLL transition state is entered when moving from the NORMAL mode to SLOW mode. It initiates the switching of the clock sources from the PLL to the crystal oscillator output.
The system moves into the SLOW mode when the PLLSW input is reset to a logic 0, to indicate that clock switching is complete.
In NORMAL mode both of the system clocks and the System Controller clock are driven from the output of the PLL.
If the NORMAL mode control bit is not set the system moves into the Switch from PLL transition state.
To enable the software to control the relative frequency of the core clock, CLK, and the bus clock, HCLK, the System Controller provides access to the HCLKDIVSEL[2:0] output through the system control register. These output signals are intended for use by the clock generation logic to control the generation of the CLK/HCLK clock source and the HCLKEN input.
To prevent spurious changes of the CLK/HCLK clock ratio, the HCLKDIVSEL output can only change when the system mode control state machine is in a stable state. That is, the actual system mode matches the required system mode.
HCLK and CLK are synchronous. In a very simple clock generation case, HCLK and CLK can be tied together and then HCLKEN is tied HIGH. This means that there is a 1:1 relationship between the CPU core clock and the bus clock HCLK.
Using this configuration limits the frequency that the core can run at to the maximum frequency supported by HCLK. To use the higher operating frequency capability of the core, CLK must operate at a multiple of the HCLK frequency. Configuration of this is supported by the system control register. HCLK can be set as equal to, divided by two, divided by three, or divided by four of CLK. This configuration is independent of operating mode. However, modes other than NORMAL only ever have to use 1:1.