I have a question about ultilization report between systhesis and export RTL.
In the export RTL, It uses additional SRL & SLICE and orther values is different synthesis report.
Could you please explain it for me?
The synthesis report is just a roughly estimation, you have to export the design and at least synthesize it to get a reliable utilization, which also depends on other factors releted to the full design like FPGA occupation and congestion.
As correctly indicated by @baltam, the utilization after exporting the RTL as IP with synthesis, place and route options will give the exact utilization values whereas synthesis option in HLS converts the c/c++ language into HDL giving just utilization estimates but not the exact utilization.