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A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.
This application is a continuation of U.S. application Ser. No. 11/457,320 filed Jul. 13, 2006 now U.S. Pat. No. 7,411,824, and is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2005-205950, filed Jul. 14, 2005, the entire contents of each of which are incorporated herein by reference.
The present invention relates to, e.g., an NAND flash memory using an EEPROM, and more particularly to a semiconductor memory device capable of storing multivalued data in a single memory cell.
In an NAND flash memory, a plurality of memory cells arranged in a column direction are connected in series to constitute NAND cells, and each NAND cell is connected with a corresponding bit line through a selection gate. Each bit line is connected with a latch circuit which latches write data and read data. All or a half of a plurality of cells arranged in a row direction are simultaneously selected, and a write or read operation is collectively carried out with respect to all or a half of the cells selected at the same time. The plurality of NAND cells arranged in the row direction constitute a block, and an erase operation is executed in this block unit. In the erase operation, a threshold voltage of the memory cells is set to a negative voltage. Injecting electrons into the memory cells in a write operation can set the threshold voltage to a positive voltage (see, e.g., Jpn. Pat. Appln. Publication No. 2004-192789).
Meanwhile, in the NAND cell, the memory cells are connected in series. Therefore, in a read operation, a non-selected cell must be in an on state, a voltage (Vread) higher than a threshold voltage is applied to a gate electrode of the non-selected cell. Therefore, in the write operation, the threshold voltage set with respect to cells must not exceed Vread, and a threshold distribution is controlled in such a manner that it does not exceed Vread by repeatedly executing a program operation and a program verify read operation in accordance with each bit in a write sequence.
Further, in recent years, with an increase in a capacity of a memory, a multivalued memory which stores two or more bits in one cell has been developed. For example, in order to store two bits in one cell, four threshold distributions must be set in such a manner that each distribution does not exceed Vread. Therefore, each threshold distribution must be controlled to be narrowed as compared with a case where one bit or two threshold distributions are stored in one cell. Furthermore, in order to store three bits or four bits in one cell, eight or 16 threshold distributions must be set. Therefore, a distribution width of each threshold voltage must be greatly narrowed. In order to narrow a distribution width of a threshold voltage in this manner, a program and a verify operation must be precisely repeated, and there occurs a problem of a decrease in a writing speed. Therefore, a semiconductor memory device capable of increasing a writing speed has been demanded.
According to a first aspect of the invention, there is provided a semiconductor memory device comprising: a memory cell array having a plurality of memory cells which are arranged in a matrix form and connected in series, the plurality of memory cells being connected with word lines and bit lines; a selection transistor which selects the word lines; and a control circuit which controls potentials of the word lines and the bit lines in accordance with input data, the control circuit controlling write, read and erase operations of data with respect to the memory cells, wherein the selection transistor is formed on a well, and a first negative voltage is supplied to the well, a first voltage (the first voltage≧ the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.
According to a second aspect of the invention, there is provided a semiconductor memory device comprising: a memory cell array having a plurality of memory cells which are arranged in a matrix form and connected in series, the plurality of memory cells being connected with word lines and bit lines; a selection transistor which selects the word lines; a control circuit which controls potentials of the word lines and the bit lines in accordance with input data, the control circuit controlling write, read and erase operations of data with respect to the memory cells, wherein the selection transistor is formed on a well, and a first negative voltage is supplied to the well and a first voltage (the first voltage≧ the first negative voltage) is supplied to a predetermined non-selected word line in the write operation.
According to a third aspect of the invention, there is provided a semiconductor memory device comprising: a memory cell array having a plurality of memory cells which are arranged in a matrix form, the plurality of memory cells being connected with word lines and bit lines; a selection transistor which selects the word lines; and a control circuit which controls potentials of the word lines and the bit lines in accordance with input data, the control circuit controlling write, read and erase operations of data with respect to the memory cells, wherein the selection transistor is formed on a well, and a first negative voltage is supplied to the well and a first voltage (the first voltage≧ the first negative voltage) is supplied to a selected word line in an erase verify read operation.
FIGS. 15A, 15B and 15C are views showing a modification of the present embodiment.
FIGS. 1A and 1B show a relationship between threshold voltages of a related art and the present embodiment. FIGS. 1A and 1B show a case where four-valued data consisting of two bits is stored.
As shown in FIG. 1B, in the present embodiment, a plurality of negative threshold voltages which are not greater than, e.g., 0 V are also set. When the plurality of negative threshold voltages are also set in this manner, each threshold distribution width can be increased without changing Vread. Therefore, the number of times of executing a program or a verify operation can be decreased, and a writing speed can be increased.
In order to set such threshold voltages, the following structure is required. That is, in order to set a negative voltage in a gate electrode of a selected cell, a negative potential must be set in a word line. Therefore, for example, an N-channel MOS transistor with a high withstand voltage constituting a row decoder is formed in a P-type well (which will be referred to as a P-well) region, and a negative voltage is supplied to this P-well region. At this time, Vread (e.g., 5 V) is supplied to a non-selected word line in a selected block to achieve electrical conduction of the non-selected cell.
Moreover, in writing “1” (non-writing), there has been designed a writing mode which is referred to as RLSB (Revised Local Self Boost) or REASB (Revised Erased Local Self Boost) in order to avoid erroneous writing. In this writing mode, a channel region of a cell which is in close proximity to a write cell in an NAND cell is set to OFF to facilitate booting a potential of the channel region. Therefore, a ground potential is supplied to a word line. However, in the present embodiment, when a cell is an erase cell, its threshold voltage has a larger negative value as compared with the related art as indicated by data “0” in FIG. 1B. Therefore, a negative potential must be supplied to the word line in order to turn off the channel region of the cell which is in close proximity to the write cell.
An embodiment according the present invention will now be described hereinafter with reference to the accompanying drawings.
FIG. 2 shows a configuration of a semiconductor memory device according to this embodiment which is specifically an NAND flash memory which stores, e.g., four-valued (two-bit) data.
A memory cell array 1 includes a plurality of bit lines, a plurality of word lines and a common source line, and memory cells which consist of, e.g., EEPROM cells and in which data can be electrically rewritten are arranged in a matrix form in the memory cell array 1. A bit control circuit 2 which controls bit lines and a word line control circuit 6 are connected with this memory cell array 1.
The bit line control circuit 2 reads data in the memory cells in the memory cell array 1 through bit lines, detects states of the memory cells in the memory cell array 1 through the bit lines, or applies a write control voltage to the memory cells in the memory cell array 1 through the bit lines to write data in the memory cells. A column decoder 3 and a data input/output buffer 4 are connected with the bit line control circuit 2. A data storage circuit in the bit line control circuit 2 is selected by the column decoder 3. Data in each memory cell read to the data storage circuit is output to the outside from a data input/output terminal 5 through the data input/output buffer 4.
Additionally, write data input to the data input/output terminal 5 from the outside is input to the data storage circuit selected by the column decoder 3 through the data input/output buffer 4.
The word line control circuit 6 includes a row decoder 6-1. The word line control circuit 6 selects a word line in the memory cell array 1 through the row decoder 6-1, and applies a voltage required for a read, write or erase operation to the selected word line.
The memory cell array 1, the bit line control circuit 2, the column decoder 3, the data input/output buffer 4 and the word line control circuit 6 are connected with and controlled by a control signal and control voltage generator circuit 7. The control signal and control voltage generator circuit 7 is connected with a control signal input terminal 8, and controlled by a control signal input from the outside through the control signal input terminal 8. The control signal and control voltage generator circuit 7 includes a later-described negative voltage generator circuit 7-1. This negative voltage generator circuit 7-1 generates a negative voltage in the data write or read operation.
The bit line control circuit 2, the column decoder 3, the word line control circuit 6, the control signal and control voltage generator circuit 7 constitute a write circuit and a read circuit.
FIG. 3 shows a configuration of the memory cell array 1 and the bit line control circuit 2 depicted in FIG. 2. A plurality of NAND cells are arranged in the memory cell array 1. One NAND cell is constituted of, e.g., 32 memory cells MC each consisting of an EEPROM which are connected in series, and selection gates S1 and S2. The selection gate S2 is connected with a bit line BL0e, and the selection gate S1 is connected with a source line SRC. Control gates of the memory cells MC arranged in each row are equally connected with word lines WL0 to WL29, WL30 and WL 31. Further, the selection gate S2 is equally connected with a select line SGD, and the selection gate S1 is equally connected with a select line SGS.
The bit line control circuit 2 has a plurality of data storage circuits 10. A pair of bit lines (BL0 e, BL0 o), (BL1 e, BL1 o) . . . (BLie, BLio) or (BL8 ke, BL8 ko) are connected with each data storage circuit 10.
As indicated by a broken line, the memory cell array 1 includes a plurality of blocks. Each block is constituted of the plurality of NAND cells, and data is erased in units of, e.g., this block. Furthermore, an erase operation is simultaneously carried out with respect to the two bit lines connected with the data storage circuit 10.
Moreover, a plurality of memory cells (memory cells in a range surrounded by the broken line) which are arranged every other bit line and connected with one word line constitute one sector. Data is written and read in accordance with each sector.
In a read operation, a program verify operation and a program operation, one bit line is selected from the two bit lines (BLie, BLio) connected with the data storage circuit 10 in accordance with an address signal (YA0, YA1 . . . YAi . . . YA8 k) supplied from the outside. Additionally, one word line is selected in accordance with an external address.
FIGS. 4A and 4B are cross-sectional views of the memory cell and the selection transistor. FIG. 4A shows the memory cell. n-type diffusion layers 42 as a source and a drain of the memory cell are formed in a substrate 51 (a later-described P-well region 55). A floating gate (FG) 44 is formed above the P-well region 55 through a gate insulating film 43, and a control gate (CG) 46 is formed above this floating gate 44 through an insulating film 45. FIG. 4B shows the selection gate. n-type diffusion layers 47 as a source and a drain are formed in the P-well region 55. A control gate 49 is formed above the P-well region 55 through a gate insulating film 48.
FIG. 5 is a cross-sectional view showing a semiconductor memory device. For example, N-type well (which will be referred to as N-well hereinafter) regions 52, 53, 54 and 56 and a P-well region 57 are formed, e.g., in a P-type semiconductor substrate 51. A P-well region 55 is formed in the N-well region 52, and a low-voltage N-channel MOS transistor LVNTr constituting the memory cell array 1 is formed in this P-well region 55. Further, a low-voltage P-channel MOS transistor LVPTr and a low-voltage N-channel MOS transistor LVNTr constituting the data storage circuit 10 are formed in the N-well region 53 and the P-well region 57.
A P-well region 58 is formed in the N-well region 56, and a high-voltage N-channel MOS transistor HVNTr constituting the row decoder 6-1 is formed in this P-well region 58. Furthermore, a high-voltage P-channel MOS transistor HVPTr constituting, e.g., a word line drive circuit is formed in the N-well region 54. The high-voltage transistor HVNTr or HVPTr has, e.g., a gate insulating film thicker than that of the low-voltage transistor LVNTr or LVPTr.
FIG. 6 shows a potential supplied to each well in the erase, program and read operations. A negative potential, e.g., −2V is supplied to the P-well 58 in which the N-channel MOS transistor constituting the row decoder 6-1 is formed in the program and data read operations.
FIG. 7 is a circuit diagram showing an example of the data storage circuit 10 depicted in FIG. 3.
This data storage circuit 10 has a primary data cache (PDC), a secondary cache (SDC), a dynamic data cache (DDC), and a temporary data cache (TDC). The SDC, the PDC and the DDC are used to hold input data in the write operation, hold read data in the read operation, temporarily hold data in the verify operation, and operate internal data when storing multivalued data. The TDC is used to amplify and temporarily hold bit line data when reading data, and operate internal data when storing multivalued data.
The SDC is constituted of clocked inverter circuits 61 a and 61 b configuring a latch circuit and transistors 61 c and 61 d. The transistor 61 c is connected between an input end of the clocked inverter circuit 61 a and an input end of the clocked inverter circuit 61 b. A signal EQ2 is supplied to a gate of this transistor 61 c. The transistor 61 d is connected between an output end of the clocked inverter circuit 61 b and the ground. A signal PRST is supplied to a gate of this transistor 61 d. A node N2 a of the SDC is connected with an input/output data line IO through a column selection transistor 61 e, and a node N2 b of the same is connected with an input/output data line IOn through a column selection transistor 61 f. A column selection signal CSLi is supplied to gates of these transistors 61 e and 61 f. The node N2 a of the SDC is connected with a node N1 a of the PDC through transistors 61 g and 61 h. A signal BLC2 is supplied to a gate of the transistor 61 g, and a signal BLC1 is supplied to a gate of the transistor 61 h.
The PDC is constituted of clocked inverter circuits 61 i and 61 j and a transistor 61 k. The transistor 61 k is connected between an input end of the clocked inverter circuit 61 i and an input end of the clocked inverter circuit 61 j. A signal EQ1 is supplied to a gate of this transistor 61 k. A node N1b of the PDC is connected with a gate of a transistor 611. One end of a current path of this transistor 611 is grounded through a transistor 61 m. A signal CHK1 is supplied to a gate of this transistor 61 m. Moreover, the other end of the current path of the transistor 611 is connected with one end of a current path of transistors 61 n and 61 o constituting a transfer gate. A signal CHK2 n is supplied to a gate of this transistor 61 n. Additionally, a gate of the transistor 610 is connected with a connection node N3 of the transistors 61 g and 61 h. A signal COMi is supplied to the other end of the current path of the transistors 61 n and 61 o. This signal COMi is a signal common to all the data storage circuits 10, and indicates whether verifying all the data storage circuits 10 has been completed. That is, as will be described later, when the verify operation is completed, the node N1b of PDC changes to a low level. Assuming that the signals CHK1 and CHK2 are on a high level in this state, the signal COMi changes to the high level if the verify operation is completed.
Further, the TDC is constituted of, e.g., an MOS capacitor 61 p. This capacitor 61 p is connected between the connection node N3 of the transistors 61 g and 61 h and the ground. Furthermore, the DDC is connected with the connection node N3 through a transistor 61 q. A signal REG is supplied to a gate of the transistor 61 q.
The DDC is constituted of transistors 61 r and 61 s. A signal VREG is supplied to one end of a current path of the transistor 61 r, and the other end of this current path is connected with a current path of the transistor 61 q. A gate of this transistor 61 r is connected with the node N1 a of the PDC through the transistor 61 s. A signal DTG is supplied to a gate of this transistor 61 s.
Moreover, one end of a current path of transistors 61 t and 61 u is connected with the connection node N3. A signal VPRE is supplied the other end of the current path of the transistor 61 u, and a signal BLPRE is supplied to a gate of the transistor 61 u. A signal BLCLAMP is supplied to a gate of the transistor 61 t. The other end of the current path of this transistor 61 t is connected with one end of a bit line BLo through a transistor 61 v, and further connected with one end of a bit line BLe through a transistor 61 w. Signals BLSo and BLSe are respectively supplied to gates of these transistors 61 v and 61 w. The other end of the bit line BLo is connected with one end of a current path of a transistor 61 x. A signal BIASo is supplied to a gate of this transistor 61 x. The other end of the bit line BLe is connected with one end of a current path of a transistor 61 y. A signal BIASe is supplied to a gate of this transistor 61 y. A signal BLCRL is fed to the other end of the current path of these transistors 61 x and 61 y. The transistors 61 x and 61 y are complementarily turned on in accordance with the signals BIASo and BIASe, and supply a potential of the signal BLCRL to a non-selected bit line.
Each signal and voltage mentioned above are generated by the control signal and control voltage generator circuit 7 depicted in FIG. 2, and the following operations are brought under control by this control signal and control voltage generator circuit 7.
FIG. 8 shows an example of the negative voltage generator circuit 7-1. The negative voltage generator circuit 7-1 is constituted of, e.g., a four-phase pump circuit PMP, a detection circuit DT, a control section 7 d and an oscillator circuit 7 e. The pump circuit PMP is formed of, e.g., a plurality of P-channel MOS transistors PMOS and a plurality of capacitors Cp. Each of clock signals CLK1 to CLK4 is supplied to one end of each capacitor Cp. These clock signals CLK1 to CLK4 sequentially turn on the PMOS, thereby generating a negative voltage.
The detection circuit DT is connected with an output end of the pump circuit PMP. This detection circuit DT is constituted of a constant current source 7 a, a resistance 7 b and a differential amplifier 7 c. The constant current source 7 a and the resistance 7 b are connected in series between a node to which a supply power VDD is supplied and the output end of the pump circuit PMP. One input end of the differential amplifier 7 c is connected with a connection node between the constant current source 7 a and the resistance 7 b, and a reference voltage Vref is supplied to the other end of the differential amplifier 7 c. This reference voltage Vref is a voltage of approximately 1 V generated by, e.g., a band gap reference circuit. This detection circuit DT detects an output voltage of the pump circuit PMP based on the reference voltage Vref. This detection output signal is fed to the control section 7 d. The control section 7 d controls the oscillator circuit 7 e in accordance with the detection output signal. The oscillator circuit 7 e is oscillated or stopped based on control by the control section 7 b. In this manner, a constant negative voltage is generated by the pump circuit PMP.
Moreover, the resistance 7 b constitutes a trimming circuit 7 f. This trimming circuit 7 f changes a resistance value of the resistance 7 b in accordance with a trimming signal TM to switch a level of a negative voltage output from the pump circuit PMP. The trimming signal TM is generated by, e.g., the control signal and control voltage generator circuit 7 in the data read operation or the program verify operation. Therefore, the negative voltage generator circuit 7-1 generates negative voltages on various levels in the data read operation or the program verify operation.
Since this memory is a multivalued memory, data consisting of two bits can be stored in one cell. Two-bit data can be changed over by using an address (a first page or a second page).
FIGS. 9A, 9B and 9C show a relationship between data in a memory cell and a threshold value of the memory cell. As shown in FIG. 9C, data in the memory cell becomes “0” when erasing is done. The data “0” corresponds to a negative voltage which is not greater than 0 V. As will be described later, in order to apply an RLSB or REASB writing mode, a verify operation is executed based on a verify voltage “z” after erasing. When a threshold voltage is not greater than the verify voltage “z”, a write operation is performed until the threshold voltage becomes the verify voltage “z”.
As shown in FIG. 9A, the data in the memory cell becomes data “0” and data “2” by writing a first page. Further, as shown in FIG. 9B, after writing a second page, the data in the memory cell becomes data “0”, “1”, “2” and “3”. In this embodiment, the data in the memory cell is defined in an ascending order of the threshold voltage.
FIG. 10 schematically shows a writing order in the present embodiment. As shown in FIG. 10, in a block, a write operation is executed every page from a memory cell close to a source line. In this case, in order to eliminate the influence of a threshold voltage of an adjacent memory cell having data previously written therein, the order of writing data in the memory cells is defined as shown in FIG. 9.
FIG. 11 shows a transfer gate constituting a part of the row decoder 6-1. This transfer gate is formed of the plurality of N-channel MOS transistors HVNTr. Voltages SGS_DRV, CG0 to CG31 and SGD_DRV are supplied to one end of each of the transistors HVNTr, and the other end of the same is connected with each of a select line SGS, word lines WL0 to WL31 and a select line SGD. A signal TG is supplied to a gate of each transistor HVNTr. When the transistor HVNTr of each selected block is turned on in accordance with the signal TG, a predetermined voltage is supplied to the word lines WL0 to WL31 of the cells.
It is to be noted that the P-well region 58 in which the row decoder 6-1 is arranged may be divided in accordance with each block (indicated by 58 a and 58 b in FIG. 5), or the row decoders of a plurality of or all blocks may be arranged in one P-well region 58 (indicated by 58 c in FIG. 5).
As shown in FIG. 9A, after writing the first page, the data in the memory cell becomes “0” or “2”. Therefore, supplying an intermediate level “a” of these data to the word line and performing the read operation enable reading these data. Furthermore, as shown in FIG. 9B, after writing the second page, the data in the memory cell becomes one of “0”, “1”, “2” and “3”. Therefore, supplying each intermediate level “b”, “c” or “d” of these data to the word line and performing the read operation enable reading these data. In this embodiment, the level “a” and “b” correspond to negative voltages, for example.
The well of the memory cell (the P-well region 55 in FIG. 5), the source line and a non-selected bit line are set to Vss (a ground potential=0 V). When the P-well region 58 is divided in accordance with each block, the P-well region 58 of a non-selected block is set to Vss or a negative potential (e.g., −2 V), and the transfer gate (shown in FIG. 11) of the non-selected block is turned off. Moreover, when the row decoders of a plurality of or all blocks are arranged in one P-well region 58, the P-well region 58 is set to a negative potential (e.g., −2 V), and the transfer gate of the non-selected block (shown in FIG. 11) is turned off. As a result, the word line of the non-selected block enters a floating state, and the selection gate becomes Vss.
When a negative potential (e.g., −2 V) is supplied to the P-well region 58 of the row decoder in a selected block and the transfer gate of the selected block is turned on, a potential in reading (e.g., −2 V to 3V) is supplied to a selected word line of the selected block, Vread (e.g., 5 V) is fed to a non-selected word line of the selected block, and Vsg (Vdd+Vth, e.g., 2.5 V+Vth) is supplied to the selection gate SG1 of the selected block. Here, when the potential in reading is not negative, the P-well region may be set to Vss.
Then, a signal VPRE of the data storage circuit 10 depicted in FIG. 7 is set to Vdd (e.g., 2.5 V), a signal BLPRE is set to Vsg (Vdd+Vth), a signal BLCLAMP is set to, e.g., (0.6 V+Vth), and a bit line is pre-charged to, e.g., 0.6 V. Subsequently, a select line SG2 of the cell on the source side is set to Vdd. When a threshold voltage of the memory cell is higher than the potential in reading, the cell is turned off, and hence the bit line remains in the high level. Additionally, when a threshold voltage of the memory cell is lower than the potential in reading, the cell is turned on, and hence a potential of the bit line becomes Vss.
Thereafter, the signal BLPRE of the data storage circuit 10 shown in FIG. 7 is temporarily set to Vsg (Vdd+Vth), the node N3 of the TDC is pre-charged to Vdd, and then the signal BLCLAMP is set to, e.g., (0.45+Vth). The node N3 of the TDC changes to the low level when a potential of the bit line is lower than 0.45 V, and it changes to the high level when a potential of the bit line is higher than 0.45 V. After setting the BLCLAMP to Vss, the signal BLC1 is set to Vsg (Vdd+Vth), and a potential of the TDC is read to the PDC. Therefore, the PDC enters the low level when a threshold voltage of the cell is lower than a potential of the word line, and the PDC enters the high level when the same is higher than a potential of the word line. The read operation is executed in this manner.
FIG. 12 shows a sequence of writing the first page, and FIG. 13 illustrates a sequence of writing the second page.
In a program operation, an address is first specified, and a half of memory cells (two pages) connected with one word line are selected as shown in FIG. 3. This memory can perform the program operation only in the order of the first page and the second page of these two pages. Therefore, the first page is first selected by using the address.
In the first page write operation shown in FIG. 12, write data is first input from the outside, and it is stored in the SDC of all the data storage circuits 10 (S11). Then, when a write command is input, data in the SDC in all the data storage circuits 10 is transferred to the PDC (S12). The node N1 a of the PDC changes to the high level when data “1” (writing is not executed) is input from the outside, and the node N1 a of the PDC changes to the low level when data “0” (writing is executed) is input. Thereafter, the data in the PDC has a potential of the node N1 a, and the data in the SDC has a potential of the node N2 a.
In the data storage circuit 10 shown in FIG. 7, when the signal BLC1 is set to Vdd+Vth, the transistor 61 h becomes electrically conductive. Therefore, the bit line is set to Vdd when the data “1” (writing is not executed) is stored in the PDC, and the bit line is set to Vss when the data “1” (writing is executed) is stored in the same. Further, writing must not be performed in a cell having a non-selected page (a bit line is not selected) which is connected with a selected word line. Therefore, the bit line connected with such a cell is set to Vdd like a bit line to which the data “1” is supplied.
In this state, when the P-well region 58 is divided in accordance with each block, the P-well region 58 of a non-selected block is set to Vss or a negative potential (e.g., −2 V), and the transfer gate (shown in FIG. 11) of the non-selected block is turned off. When the row decoders of a plurality of or all blocks are arranged in one P-well region 58, the P-well region 58 is set to a negative potential (e.g., −2 V), and the transfer gate (shown in FIG. 11) of the non-selected block is turned off. As a result, the word line of the non-selected block enters the floating state, and the selection gate has a potential of Vss.
Furthermore, the P-well region 58 of the row decoder in a selected block is set to a negative potential (e.g., −2 V), and electrical conduction is achieved in the transfer gate of the selected block, whereby Vdd (or a potential slightly lower than Vdd) is supplied to the selection gate SGD of the selected block. Moreover, when Vss is supplied to the selection gate SGS of the selected block, Vpgm (20 V) is supplied to the selected word line and Vpass (10 V) is supplied to the non-selected word line, a channel of the cell is set to Vss and the word line is set to Vpgm if the bit line has a potential of Vss, thereby effecting writing. On the other hand, if the bit line has a potential of Vdd, the channel of the cell is booted by coupling rather than Vss. Therefore, a potential difference between the gate and the channel is reduced, and writing is not carried out.
When writing is executed in the order depicted in FIG. 10, the number of cells in which data is written is increased as distanced from the source line. Therefore, there is a problem that the channel is hard to be booted and erroneous writing is executed. In order to solve this problem, the RLSB writing mode or the REASB writing mode has been developed. In the RLSB writing mode, an adjoining word line of a selected word line or a word line adjacent to the adjoining word line is set to Vss, and the selected word line is set to Vpgm, and other word lines are set to Vpass or an intermediate potential. Additionally, in the REASB writing mode, an adjoining word line of a selected word line on a source side or a word line adjacent to the adjoining word line is set to Vss, the selected word line is set to Vpgm, and other word lines are set to Vpass or an intermediate potential. The adjoining word line of the selected word line or the word line adjacent to the adjoining word line is set to Vss to turn off the memory cell, thereby facilitating booting a channel immediately below a selected cell.
In this embodiment, however, when a cell whose word line is set to Vss is an erase cell, a threshold value thereof is a negative voltage, and hence this cell is not turned off. Therefore, in case of the present embodiment, in the RLSB writing mode shown in FIGS. 14A and 14B or the REASB writing mode depicted in FIG. 14C, the adjoining word line of the selected word line or the word line adjacent to the adjoining word line is se to a negative potential, e.g., (−1.5 V) rather than Vss. In writing the first page, data in the memory cell becomes data “0” and data “2”.
A program verify read operation is the same as the read operation, but a verify level “a′” which is slightly higher than a read level is supplied to a word line to perform reading. When a threshold voltage of the memory cell reaches the verify level “a′” based on this verify reading, the PDC has the data “1”, and writing is not executed.
On the other hand, when the threshold voltage of the memory cell does not reach the verify level “a′”, the PDC has data “0”. In a case where data in all the PDCs in the respective data storage circuits 10 are not “1” (S15), the program is again executed (S13). The program operation and the verify operation are repeated until the data in the PDCs of the respective data storage circuits 10 are all changed to “1”.
In the second page write operation depicted in FIG. 13, write data is first input from the outside, and it is stored in the SDCs of all the data storage circuits 10 (S21). Then, in writing the first page, a read level “a” (e.g., a negative voltage) is set to the word line in order to confirm the written data, thereby reading data in the memory cell (S22). This reading operation is as described above. The PDC changes to the low level when a threshold voltage of the cell is lower than a potential “a” of the word line, and the PDC changes to the high level when the same is higher than the potential “a” of the word line.
Thereafter, a data cache is set (S23). That is, the second page is written as shown in FIG. 9B.
When data is “1” in writing the first page, and when data is “1” in writing the second page, the second page is not written.
When the data is “1” in writing the first page, and when the data is “0” in writing the second page, the data in the memory cell is set to “1” by writing the second page.
When the data is “0” in writing the first page, and when the data is “0” in writing the second page, the data in the memory cell is set to “2” by writing the second page.
When the data is “0” in writing the first page, and when the data is “1” in writing the second page, the data in the cell is set to “3” by writing the second page.
The data cache is set in order to execute this operation.
That is, in a case where the data in the memory cell is set to “0” (the data “1” in the first page, and the data “1” in the second page), the PDC is set to the high level, the DDC is set to the low level, and the SDC is set to the high level.
In a case where the data in the memory cell is set to “1” (the data “1” in the first page, and the data “0” in the second page) the PDC is set to the low level, the DDC is set to the high level, and the SDC is set to the low level.
In a case where the data in the memory cell is set to “2” (the data “0” in the first page, and the data “0” in the second page), the PDC is set to the low level, the DDC is set to the high level, and the SDC is set to the low level.
In a case where the data in the memory cell is set to “3” (the data “0” in the first page, and the data “1” in the second page), the PDC is set to the low level, the DDC is set to the low level, and the SDC is set to the low level.
Each data in the PDC, the DDC and the SDC is set by supplying the signals BLC1, BLC2, DTG, REG and VREG in a predetermined order and transferring data of the PDC, the DDC, the SDC and the TDC. It is to be noted that a specific operation will be eliminated.
A program operation is completely the same as the first page program operation. Writing is not executed when data “1” is stored in the PDC, and writing is carried out when data “0” is stored in the same.
Program verify reading is the same as the read operation. However, a verify level “b′”, “c′” or “d′” corresponds to a level obtained by adding a margin to a read level, and it is set to a level slightly higher than the read level. Verify reading is executed by using this verify level “b′”, “c′” or “d′”. For example, the verify level “b′” is a negative voltage, and the verify level “c′” or “d′” is a positive voltage.
The verify operation is executed in the order of, e.g., the verify levels “b′”, “c′” and “d′”.
That is, the verify level “b′” is first set to the word line, and whether a threshold voltage of the memory cell has reached the verify level “b′” is verified (S25). As a result, when the threshold voltage of the memory cell has reached the verify level, the PDC changes to the high level, and writing is not executed. On the other hand, when the threshold voltage has not reached the verify level, the PDC changes to the low level, and writing is executed in the next program.
Thereafter, the verify level “c′” is set to the word line, and whether the threshold voltage of the memory cell has reached the verify level “c′” is verified (26). As a result, when the threshold voltage of the memory cell has reached the verify level, the PDC is set to the high level, and writing is not executed. On the other hand, when the threshold voltage has not reached the verify level, the PDC is set to the low level, and writing is executed in the next program.
Then, the verify level “d′” is set to the word line, and whether the threshold voltage of the memory cell has reached the verify level “d′” is verified (S27). As a result, when the threshold voltage of the memory cell has reached the verify level, the PDC is set to the high level, and writing is not executed. On the other hand, when the threshold voltage has not reached the verify level, the PDC is set to the low level, and writing is executed in the next program.
The program operation and the verify operation are repeated in this manner until the PDCs in all the data storage circuits 10 are set to the high level.
A specific verify operation will now be described hereinafter.
In this program verify operation, a verify voltage “b′” is given to a selected word line.
First, a read potential Vread is supplied to a non-selected word line and a select line SG1 in a selected block. The signal BLCLAMP of the data storage circuit 10 is set to 1V+Vth, and the signal BLC2 of the same is set to Vdd+Vth, thereby pre-charging a bit line. At the time of writing data “2” or “3” in a memory cell, data stored in the SDC is “0”. Therefore, the bit line is not pre-charged, but the bit line is pre-charged only in writing data “0” or “1” in the memory cell.
Then, a select line SG2 of the cell on the source side is set to the high level. Since the cell is turned off when a threshold voltage thereof is higher than the potential “b′”, the bit line remains in the high level. Furthermore, since the cell is turned on when the threshold voltage is lower than the potential “b′”, the bit line is set to Vss. During discharge of this bit line, the node N3 of the TDC is temporarily set to Vss, the signal REG is set to the high level to turn on the transistor 61 q, and data in the DDC is transferred to the TDC.
Then, the signal DTG is set to the high level to temporarily turn on the transistor 61 s, and data in the PDC is transferred to the DDC. Thereafter, data in the TDC is transferred to the PDC. Subsequently, the signal BLPRE of the data storage circuit is set to a voltage Vdd+Vth to turn on the transistor 61 u, and the node N3 of the TDC is pre-charged to Vdd. Then, the signal BLCLAMP is set to 0.9 V+Vth to turn on the transistor 61 t. Then, the node N3 of the TDC changes to the low level when the bit line is on the low level, and it changes to the high level when the bit line is on the high level.
Here, the low level is stored in the DDC when writing is executed, and the high level is stored in the DDC when writing is not executed. Therefore, when the signal VREG is set to Vdd and the signal REG is set to the high level, the node N3 of the TDC is forcibly set to the high level only in a case where writing is not performed. After this operation, data in the PDC is transferred to the DDC, and a potential of the TDC is read to the PDC. The high level is latched in the PDC when writing is not executed and when data “1” has been written in the memory cell and a threshold voltage of the cell has reached the verify voltage “b′”. The low level is latched in the PDC when the threshold voltage of the cell does not reach the potential “b′” and when data “2” or “3” has been written in the memory cell.
In a cell in which data “2” is written, writing is executed by using a verify voltage “a′” which is lower than the original verify voltage “c′” in the first page. Then, a threshold voltage is increased by writing data in an adjacent cell in some cases, and some cells has reached the original verify voltage “c′” in other cases. Therefore, data “2” is first verified. In this program verify operation, the verify voltage “c′” is applied to a selected word line.
First, a potential Vread is supplied to a non-selected word line and the select line SG1 in a selected block, the signal BLCLAMP of the data storage circuit 10 shown in FIG. 7 is set to 1 V+Vth, and the signal REG is set to Vdd+Vth, thereby pre-charging a bit line. In case of writing data “0” or “3” in a memory cell, since the DDC is set to the low level, and hence the bit line is not pre-charged. Further, in case of writing data “1” or “2” in the memory cell, the DDC is set to the high level. Therefore, the bit line is pre-charged.
Then, the select line SG2 of the NAND cell on the source side is set to the high level. When a threshold voltage of the cell is higher than “c′”, the cell is turned off. Therefore, the bit line remains in the high level. Moreover, when the threshold voltage of the cell is lower than “c′”, the cell is turned on. Therefore, the bit line is set to Vss. During discharge of the bit line, the node N3 of the TDC is temporarily set to Vss. Then, the signal REG is set to the high level to turn on the transistor 61 q, and data in the DDC is transferred to the TDC.
Subsequently, the signal DTG is set to Vdd+Vth to temporarily turn on the transistor 61 s, and data in the PDC is transferred to the DDC. Then, data in the TDC is transferred to the PDC.
Subsequently, the signal VPRE is set to Vdd and the signal BLPRE is set to Vdd+Vth, whereby the node N3 of the TDC is pre-charged to Vdd. Thereafter, the signal BLCLAMP is set to 0.9 V+Vth to turn on the transistor 61 t. The node N3 of the TDC changes to the low level when the bit line is on the low level, and it changes to the high level when the bit line is on the high level.
Here, a low-level signal is stored in the DDC when writing is executed, and a high-level signal is stored in the DDC when writing is not executed. Therefore, when the signal VERG is set to Vdd and the signal REG is set to Vdd+Vth, the node N3 of the TDC is forcibly set to the high level only when writing is not executed.
Then, data in the PDC is transferred to the DDC, and a potential of the TDC is read to the PDC. The high-level signal is latched in the PDC only when writing is not executed and when data “2” is written in the memory cell and a threshold voltage of the cell has reached “c′” which is the verify voltage. The low level is latched in the PDC when the threshold voltage of the cell does not reach “c′” and when data “1” or “3” has been written in the memory cell.
In this program verify operation, a verify voltage “d′” is supplied to a selected word line. In this state, Vread is first supplied to a non-selected word line and the select line SG1 in a selected block, the signal BLCLAMP is set to 1 V+Vth, and the signal BLPRE is set to Vdd+Vth to turn on the transistors 61 t and 61 u, thereby pre-charging a bit line.
Then, the select line SG2 of the cell on the source side is set to the high level. Since a cell whose threshold voltage is higher than the potential “d′” is turned off, the bit line remains in the high level. Additionally, since a cell whose threshold voltage is lower than the potential “d′” is turned on, the bit line is set to Vss. During discharge of this bit line, the node N3 of the TDC is set to Vss, the signal REG is set to the high level, the transistor 61 q is turned on, and data in the DDC is transferred to the TDC.
Then, the signal DTG is set to the high level, the transistor 61 s is turned on, and data in the PDC is transferred to the DDC. Thereafter, data in the TDC is transferred to the PDC. Then, the signal BLPRE is set to Vdd+Vth to turn on the transistor 61 u, and the node N3 of the TDC is pre-charged to Vdd. Thereafter, the signal BLCLAMP is set to 0.9 V+Vth to turn on the transistor 61 t. The node N3 of the TDC changes to the low level when the bit line is on the low level, and it changes to the high level when the bit line is on the high level.
Here, the low level is stored in the DDC when writing is executed, and the high level is stored in the DDC when writing is not executed. Therefore, the signal VREG is set to Vdd, and the signal REG is set to the high level, thereby turning on the transistor 61 q. Then, the node N3 of the TDC is forcibly set to the high level only when writing is not executed. After this operation, data in the PDC is transferred to the DDC, and a potential of the TDC is read to the PDC. The high level is latched in the PDC only when writing is not executed and when data “3” has been written in the memory cell and a threshold voltage of the cell has reached the verify voltage “d′”. The low level is latched in the PDC when the threshold voltage of the cell does not reach the potential “d′” and when data “1” or “2” has been written in the memory cell.
When the PDC is on the low level, the write operation is again executed, and this program operation and the verify operation are repeated until data in the PDCs of all the data storage circuits are set to the high level (S28).
In the program verify operation, the three verify operations are executed after one program operation. However, in an initial program loop, a threshold voltage is not increased. Therefore, it is possible to eliminate verifying the memory cell data “3”, or verifying the memory cell data “3” and verifying the memory cell data “2”. Further, in a program loop close to end, writing the memory cell data “1”, or writing the memory cell data “2” and the memory cell data “1” has been terminated. Therefore, these verify operations may be eliminated. When verifying the memory cell data “1” is not necessary, data stored in the SDC does not have to be held. Therefore, data required for writing the next data can be read from the outside.
An erase operation is executed in units of the block indicated by a broken line in FIG. 3. Furthermore, this operation is executed with respect to two bit lines (BLie and BLio) connected with each data storage circuit 10 at the same time. After erasing, a threshold value of a cell becomes memory cell data “0” as shown in FIG. 9C. In case of the RLSB or REASB method, a threshold voltage of an erasing target cell must be shallowly set. Therefore, after the erase operation, all word lines in a block are selected to perform the program and program verify read operations, and the write operation is executed until the verify level “z” is reached as shown in FIG. 9C. At this time, in the program and program verify read operations, all word lines are selected, and a potential of a selected word line in verifying is set to z (e.g., −3 V). In other points, these operations are executed like the regular program and program verify read operations. In this manner, the threshold voltage after erasing is slightly shallowly set.
According to the embodiment, a plurality of threshold voltages including data “0” are set on a negative voltage side lower than 0 V. That is, data “0” and “1” are set on the negative voltage side. Therefore, it is good enough to set two sets of data, i.e., data “2” and “3” in a range of the read voltage Vread. Therefore, since the number of sets of data which are set in the range of the read voltage Vread which is the same as the related art can be reduced, a threshold voltage distribution of each data can expanded. Therefore, the number of times of program and verify operations can be decreased, and a writing speed can be increased.
Further, as described above, the write voltage Vpgm is supplied to a word line of a selected cell in writing, and the write voltage Vpgm is increased little by little in the program verify operation and writing is repeated until a threshold voltage of the selected cell reaches a predetermined threshold voltage. As shown in FIG. 1B, in case of this embodiment, the verify levels VC and VD can be set slightly lower that those in the related art depicted in FIG. 1A. Therefore, there is an advantage that the write voltage Vpgm can be reduced, a withstand voltage of a peripheral circuit can be decreased and the pump circuit which generates the write voltage Vpgm can be reduced in size.
It is to be noted that the above has described the two-bit or four-valued data in the foregoing embodiment. However, the present invention is not restricted thereto, and the foregoing embodiment can be applied to an example of eight-valued data consisting of three bits and 16-valued or higher-valued data consisting of four bits. In case of storing such multivalued data, it is good enough to set four-valued data on the negative side in case of eight-valued data and eight-valued data on the same side in case of 16-valued data, for example.
Moreover, in the foregoing embodiment, a central part of a plurality of threshold voltage distributions as multivalued data is set to 0 V. However, the present invention is not restricted thereto, and a central part of multivalued data may be set to a neutral threshold voltage (a threshold voltage when an electron does not exist in a floating gate) as shown in FIG. 15A, for example.
Additionally, FIGS. 15B and 15C show a relationship between a difference B, C or D between each threshold voltage and a neutral threshold voltage and a necessary data retention. As shown in FIGS. 15B and 15C, a necessary data retention margin, i.e., a difference VB-RB, VC-RC or VD-RD between a verify level VB, VC or VD and a read level RB, RC or RD shown in FIGS. 1A and 1B must be largely set as becoming apart from the neutral threshold voltage.
In case of the related art shown in FIG. 15B, VB-RB concerning the difference B from the neutral threshold voltage is 0.1 V, VC-RC concerning the difference C from the same is 0.2 V, and VD-RD concerning the difference D from the same is 0.3 V. A sum total of the differences is 0.6 V. Therefore, a margin of 0.6 V must be set in the related art.
On the contrary, in case of the present embodiment shown in FIG. 15C, VB-RB concerning the difference B is 0.2 V, VC-RC concerning the difference C is 0.1 V, and VD-RD concerning the difference D is 0.2 V. A sum total of the differences is 0.5 V. Therefore, setting a margin of 0.5 V can suffice.
A total margin can be reduced in this manner, more data can be stored in a range of Vread.
It is to be noted that the row decoder is formed in the P well 58 in the foregoing embodiment. However, the present invention is not restricted thereto, and it is good enough to form the row decoder in the substrate 51 as indicated by a broken line in FIG. 5, supply a negative voltage (−2 V) to the substrate 51 and feed a negative voltage (−3 V) to a selected word line in the erase verify read operation.
wherein the control circuit includes a negative voltage generator circuit which generates the first negative voltage.
one of the first negative voltage and a third voltage (the third voltage≧the first negative voltage) is supplied to the well corresponding to a non-selected block.
3. The device according to claim 2, wherein, when a potential read from the memory cell is not negative, a fourth voltage (the first voltage≧the fourth voltage) is supplied to the well corresponding to the selected block.
4. The device according to claim 2, wherein the selection transistors are formed on the well arranged in accordance with at least one of the blocks, and the first negative voltage is supplied to the well.
5. The device according to claim 1, wherein at least one of a plurality of negative threshold voltages and a plurality of positive threshold voltages is set with respect to the memory cell.
6. The device according to claim 2, wherein the selection transistors are included in a row decoder selecting the word line.
one of the first negative voltage and a second voltage (the second voltage ≧ the first negative voltage) is supplied to the well corresponding to a non-selected block.
9. The device according to claim 8, wherein the selection transistors are formed on the well arranged in accordance with at least one of the blocks, and the first negative voltage is supplied to the well.
10. The device according to claim 7, wherein one of a plurality of negative threshold voltages and a plurality of positive threshold voltages is set with respect to the memory cell.
11. The device according to claim 7, wherein the first negative voltage is supplied to a gate electrode of a memory cell which is positioned on at least a source line side apart from a writing target memory cell.
12. The device according to claim 9, wherein the selection transistors are included in a row decoder selecting the word line.
one of the first negative voltage and a second voltage (the second voltage≧the first negative voltage) is supplied to the well corresponding to a non-selected block.
15. The device according to claim 14, wherein the selection transistors are formed on the well arranged in accordance with at least one of the blocks, and the first negative voltage is supplied to the well.
16. The device according to claim 13, wherein at least one of a plurality of negative threshold voltages and a plurality of positive threshold voltages is set with respect to the memory cell.
17. The device according to claim 15, wherein the selection transistors are included in a row decoder selecting the word line.

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1999 L. Rev. Mich. St. U. Det. C.L. 171. More by Kopel on the Bureau of Alcohol, Tobacco, Firearms, and Explosives, and BATFE tracing.
In ancient Greece, priests would slaughter a sacrificial animal, and then carefully examine the animal's entrails. The priests and their followers both believed that by "reading entrails," one could forecast the future. This process, fortunately, has become less messy these days: rather than using entrails, our modern fact-inventors use something much cleaner, but no more reliable: trace data from the Bureau of Alcohol, Tobacco and Firearms ("BATF"). Today, powerful leaders also make unsupportable claims based on "information" which was never intended to be used in such a manner.
Almost every major firearms control proposal (including "assault weapons" bans,  the Brady Act , gun purchase rationing,  bans on small handguns , and eliminating home-based firearms dealers ) is touted on the basis of the "scientific" evidence provided by BATF traces. The staff of Representative Charles Schumer (D-N.Y.) earned itself a large amount of favorable publicity in 1997 by using BATF traces to create what Representative Schumer called "the first study that shows conclusively that gun control works."  Unfortunately, BATF tracing data was never intended to be used for policy guidance and is unsuitable for that purpose. To build the case for a particular gun law on the basis of BATF traces is to admit that there is no relevant data to support the law.
Only a small and unrepresentative fraction of guns which are seized by the police are ever traced by BATF and, for this reason, BATF has repeatedly stated that its trace data cannot be used to draw conclusions about patterns of criminal gun use or acquisition. The BATF's National Tracing Center advises police departments that the trace data "ONLY reflects trends relating to those firearms for which a trace request is submitted and is only as accurate as the information provided by the trace requesters."
Part One below explores various reasons why gun traces are not good substitutes for information about actual gun use and sales patterns. Part Two examines one case in which it is possible to compare BATF trace data with actual police crime data, namely, the use of "assault weapons" in crime.
Under federal law, all firearms manufactured or imported into the United States must have a serial number.  Firearms manufacturers, wholesalers, and retailers are required to keep precise records of the serial number of each gun they transfer.  Thus, if a particular gun is found at a crime scene, the BATF can, using the serial number, trace the chain of custody of the gun from its manufacture to its sale at retail. From there, law enforcement authorities can interview the retail buyer, to attempt to investigate how the gun eventually came into criminal hands (e.g., the gun was stolen from the lawful retail purchaser).
It is easy to see how the pre-1990s exclusion could skew results. In the 1990s, the majority of handgun sales were semiautomatics, while most handgun sales from earlier years were revolvers.  A trace sample limited to post-1990 guns would likely overstate the prevalence of semiautomatics relative to revolvers.
Similarly, the refusal to trace pre-1990 guns will also skew the types of long guns which are traced. So-called "assault weapons" were big sellers in the 1980s and early 1990s, but were a very small part of the firearms market in most prior decades.  Thus, limiting traces to only guns made after 1990 will artificially inflate the percentage of "assault weapons" which are traced.
Finally, studies have found that between forty and sixty percent of BATF gun traces fail.  This creates a situation similar to a pollster finding that half of the persons polled refuse to answer certain questions. Elementary statistics theory requires that a data gatherer not ignore the "non-response bias."  Thus, the subset of guns for which traces are successful is even less likely to resemble crime guns in general.
Violent crimes account for only one-seventh of BATF traces.  At least half of BATF traces are for possession offenses.  To the extent that any generalizations can be drawn from BATF trace data, these generalizations are about gun owners whose gun possession violated some kind of ordinance or statute, but who did not use their gun for illegal violence.
In New York City, obtaining a handgun license is very difficult. Although New York law requires the police to act on license applications within six months, delays of nearly a year are routine-even for crime witnesses who are being threatened by criminals out on bail.  In addition, it is nearly impossible for an applicant to get a license to carry a handgun, unless the applicant is named "Donald Trump," in which case the carry permit will be granted in a few days.
Because obtaining a New York City handgun permit is very difficult for unwealthy people who cannot afford lawyers, many citizens obtain handguns illegally; they adopt the adage that "it is better to be judged by twelve than to be carried by six." They would rather face the risk of prosecution for an unlicensed handgun than face the risk of living in New York City without a handgun.
Thus, to the extent that any conclusions could be drawn from BATF trace data, the conclusions show that guns from other states are used to evade a prohibition (Washington, D.C.) or near-prohibition (New York City) on handgun ownership by non-elites. The trace data, by themselves, do not show that other states are the main source of guns for violent criminals in New York City or Washington D.C., because five-sixths of traces do not involve violent crime.
Of course no one would even bother to attempt to trace a gun from which the serial number had been removed (sometimes the serial number can be removed through advanced forensics, but the process is difficult, and used very rarely). This is one more reason why the traced guns are generally not similar to non-traced guns.
The gun was carried into New York City by a Texan who moved to New York City. The ex-Texan committed no crime other than failing to spend hundreds of dollars to obtain a New York City handgun license.
The widely-publicized study by Representative Charles Schumer's staff presumes that the first possibility is the only possibility, since it attributes all interstate gun movement to gun-running, never mentioning other, more common possibilities.  The BATF data which Schumer used does not specify how the guns moved between states.
Of course, an intra-family transaction might not necessarily be legal; federal law makes it illegal for persons other than licensed dealers to sell handguns to persons from another state. And criminals, like ordinary citizens, do buy guns for self-defense. Nevertheless, the BATF data make it clear that interstate gun transfers are usually small-scale and involve guns sold through private transfers, not from retail outlets.  Thus, the picture painted by gun control advocates such as Representative Schumer-a picture of large volume interstate transfers of guns purchased directly from licensed retail dealers-is contrary to the known data.
The difference between the Schumer scenario and the BATF facts has major policy implications. If the Schumer scenario were true, it would support his proposals for even greater federal regulation of retail gun sales. Federal regulation not only would make sense because licensed dealers, wanting to keep their license, would obey federal gun laws, but also because licensed dealers are (supposedly) the main source of interstate guns.
"To hell with statistical theory," some people might say. "Whatever the objections raised by skeptics, we still think that gun traces provide good data about gun crime and gun sales in general, even if the figures might be a little rough here and there."
But dropping one-gun-a-month laws solely because of the Schumer study (or because of any other analysis of trace statistics) would be a mistake. We know that trace statistics can result in errors of more than 1000%, and therefore, trace statistics are so far removed from real-world experience to be of no value in determining crime policy. (Again, to point out this fact is not to denigrate the BATF tracing program; the program was designed to solve individual crimes, not to gather sociological data). One of the most notable real-world instances in which tracing data was used to "prove" facts which were wholly contrary to reality was in regard to so-called "assault weapons."
"Assault weapon" is a marketing term, whose meaning varies depending on whether the user of the term is a member of the gun industry or a gun control advocate. The term generally refers to firearms that have a military-style appearance. Appearance notwithstanding, "assault weapons" are functionally indistinguishable from normal-looking guns: they fire only one bullet with each press of the trigger and the bullets they fire are intermediate-sized and less powerful than the bullets from big game rifles.
The Cox report gave trace percentages for both the nation as a whole (ten percent) and for selected major cities.  The percentage of "assault weapons" reported by Cox newspapers, based on the BATF traces, was ten percent for Chicago, nineteen percent for Los Angeles, eleven percent for New York City, and thirteen percent for Washington, D.C.  In each of those cities, police departments conducted complete counts of all guns that had been seized (not just the guns for which the police department requested a BATF trace). According to the actual police department counts of crime guns in each city, the percentage of "assault weapons" were only three percent for Chicago, one percent for Los Angeles, one percent for New York City, and zero percent for Washington, D.C.  Thus, when the BATF trace sample was compared with the comprehensive police gun seizure data, BATF traces over- stated the percentage of assault weapons used in crime by over 1000% for Los Angeles, New York, and Washington.
"Assault weapons" were a high percentage of BATF gun traces, but a small percentage of total crime guns.
Sources: BATF; police departments in respective cities.
Polling data show that high-ranking police administrators, such as big- city police chiefs, may be far more supportive of gun control in general, and assault weapon prohibition in particular, than are mid-ranking or street-level law enforcement officers.  As a result, for the reasons explained by the Congressional Research Service, heightened policy administration concern about "assault weapons" could result in a disproportionate percentage of such guns being submitted to BATF for tracing.
In addition, almost all "assault weapons" were first sold at retail after 1968. Before 1968, gun retailers who sold only to in-state customers did not need a federal firearms license.  Also, before 1968, federal law did not require firearms dealers to maintain registration records of retail sales.  Thus, successful traces are more likely to be conducted on guns made after 1968-a category which includes a higher percentage of the total stock of assault weapons than of the total stock of, for example, bolt-action rifles. While the Cox study was in progress, BATF had a policy of not accepting trace requests for guns made before the early 1980s. This policy certainly would cause an increase in the percent of traces involving "assault weapons."
It should be noted that the discrepancy between the BATF traces and the actual crime gun seizures was not confined to the four major cities discussed above. Researchers have now obtained comprehensive crime gun data for many cities based on actual inventories of firearms seized by the police, in not one of the cities does the percentage of "assault weapons" seized even remotely approach the BATF trace figure of ten percent. The highest figure was four percent; one percent (or less) was much more common.  Accordingly, it can only be concluded that BATF firearm trace requests are not an accurate mirror of actual firearm use in crime.
To accompany the temporary federal prohibition on new "assault weapons,"  Congress in 1994, ordered the Attorney General to study whether the ban was changing patterns in "assault weapon" use by criminals. When asked if data existed to allow such a study, the FBI's Uniform Crime Reports (UCR) Section replied, "The UCR Section knows of no existing data to provide a basis to address the question."  Stated less delicately, the FBI's statistical experts do not believe that gun traces provide reliable information about the general use of guns in crime. Lobbyists and politicians who attempt to use trace data for this purpose should explain why they think that they are right and the FBI is wrong.
The (mis)use of BATF tracing reports by gun control lobbyists has often worked. The federal "assault weapons" ban, the Virginia gun rationing law, and the federal elimination of home-based businesses from the ranks of licensed firearms dealers all became law with the significant help of claims made about BATF traces. Proposals for further controls, such as federal licensing of gun owners, federal gun purchase rationing, and state and federal bans on small handguns are all predicated on the allegedly scientific information derived from BATF traces.
The English philosopher Jeremy Bentham once derided natural rights as "nonsense on stilts."  Whatever one thinks about natural rights, Bentham's phrase is an apt description of attempted use of BATF traces to support gun laws.
In the 19th century, practitioners of the "science" of phrenology conducted extensive measurements of people's skulls and used the data to produce all sorts of findings, all of which had the appearance of hard science, but none of which turned out to have any validity. For example, persons with certain shapes of skulls, dubbed "low-brow," were said to be intellectually inferior. The link between BATF gun traces and real-world use of violent crime guns is just as weak as the link between skull shapes and individual intelligence. BATF traces and the measurement of skulls both generate a large amount of data, but that data is not scientific evidence upon which criminal justice policy can be based.
Phrenology, unfortunately, fits the prejudices of its era, since it helped "prove" that Blacks and Eastern Europeans were intellectually inferior to people from northwest Europe. Likewise, BATF gun trace studies fit the prejudices of our own time, since they are designed almost exclusively to "prove" the need for more gun laws.
Unlike phrenological measurements, BATF gun traces do have a valid use: tracing the history of a particular gun used in a particular crime, up to the point of retail sale. The trace data should be released from their involuntary enlistment in the cause of pseudoscientific support for restrictive firearms legislation.
[a1]. Research Director, Independence Institute, Golden Colorado (i2i.org) J.D., 1985, University of Michigan; B.A. in History 1982, Brown University, Author of Gun Control and Gun Rights (N.Y.U. Press, forthcoming 2001).
 See Sen. Dianne Feinstein, Yes: The Weapons Are Harder to Get and Police Fatalities Are Down, Insight, Feb. 26, 1996, at 26. "In 1993 . . . assault weapons . . . accounted for 8.2% of all ATF gun traces. The ban became effective on Sept. 13, 1994; from that date through November 1995, assault weapons composed only 4.3% of all gun traces." Id. See Jeffrey A. Roth & Christopher S. Koper, Wash. Urban Inst., Impact Evaluation of the Public Safety and Recreational Firearms Use Protection Act of 1994 (1997) (In contrast to most other studies discussed in this article, the Roth study relies only partially on BATF traces and includes numerous caveats about their limitations).
 See Douglas S. Weil & Rebecca C. Knox, Effects of Limiting Handgun Purchases on Interstate Transfer of Firearms, 275 JAMA 1759 (1996).
 See Garen J. Wintemute, The Relationship between Firearm Design and Firearm Violence: Handguns in the 1990's, 275 JAMA 1749 (1996).
 See More Gun Dealers than Gas Stations, (1992).
. Fox Butterfield, Report Links Crimes to States With Weak Gun Controls, N.Y. Times, Apr. 9, 1997, at A14 (discussing Rep. Charles Schumer, War Between the States: How Gunrunners Smuggle Weapons Across America (visited Feb. 25, 1999) http://www.pcvp.org/pcvp/firearms/pubs/gunrun3.shtml>).
. It is tautological that the trace data would reflect trends in trace data. But as BATF notes, it is not appropriate to assume that trace data reflect trends for the much larger universe of untraced guns.
. See Keith Bea, "Assault Weapons": Military-Style Semiautomatic Firearms: Facts and Issues, Cong. Research Serv., Rep. No. 92-434, at 65 (1992).
. See 18 U.S.C. § 923(i) (1968).
. See 18 U.S.C. § 923(g) (1968).
. See Marianne W. Zawitz, U.S. Dep't. of Justice, Guns Used in Crime (1995) (estimating that guns were used in 1.3 million violent crimes in 1993).
. See G.L. Pierce, et al., BATF, The Identification of Patterns in Firearms Trafficking: Implications for Focused Enforcement Strategies (1996).
. See Gregore J. Sambor, Tracing Firearms, Police Chief, Mar. 1985, at 73-76.
. See id. at 73.
. See, e.g., Md. Code Ann. 27 § 36 H-3 442 (L)(1957), N.Y. Penal Code § 400 (1965); Cal. Penal Code §§ 12071, 12076-77 (1973); Mass. Ann. Laws ch. 140, § 129 C (1968).
. As explained by then Philadelphia Police Commissioner Gregore J. Sambor, "when a local agency has adequate information and their own means available, they can sometimes produce their own results quicker and with less chance of error." Sambor, supra note 13 at 73.
. See Bea, supra note 8, at 65.
. Bea, supra note 8, at 65.
. See D.M. Kennedy et al., Youth Gun Violence in Boston: Gun Markets, Serious Youth Offenders, and a Use Reduction Strategy, 59 Law & Contemp. Probs. 147 (1996).
. See Tom Diaz, Making a Killing 99 (1999).
. See id. at 125.
. See Kennedy, supra note 20, tbl. 5 (guns traced from youth offenders in Boston); Gerald A. Nunziato, BATF National Tracing Center, Briefing to the Homicide Research Working Group (June 10, 1997) (60 % failure rate); J. Wachtel, Sources of Crime Guns (Mar. 1996) ( paper presented at the annual meeting of the Academy of Criminal Justice Sciences in Las Vegas) (Los Angeles traces, using BATF data, supplemented by California Department of Justice data).
. Freedman, supra note 18, at 304.
. See Paul Blackman, The Uses and Limitations of BATF Tracing Data for Law Enforcement, Policymaking, and Criminological Research, 10 J. Firearms & Pub. Pol'y. 27, 62 n.19 (1998); Pierce, supra note 12, tbl. 3; Kennedy, supra note 20, at 196.
. See CBS Morning News: Lawmakers Try to Put a Plug in Illegal Gun Pipeline (CBS television broadcast, Feb. 09, 1993).
. See Memorandum from the BATF on Firearm Statistical Information For Calendar Year 1992 to Special Agent in Charge of the New York Field Division (Oct. 22, 1992). (hereinafter Firearms Statistical Information) (on file with the author). One reason that traces from Virginia were so high was that BATF was conducting a special investigation into firearms trafficking from Virginia to New York. Thus, when a Virginia gun store would call BATF to report a suspicious sale possibly headed for New York, BATF would advise the store to go ahead with the sale. Later, when the gun-runners were arrested in New York, the gun would be traced back to Virginia. See BATF Agent Irvin W. Moran, Affidavit before U.S. Magistrate David G. Lowe (Aug. 25, 1992); Letter from John W. Magaw, Director, BATF, to Sen. Olympia J. Snowe (Feb. 23, 1996). In ordinary circumstances, the guns never would have been sold; if they had been sold, they would not have been specially selected for tracing.
. See Firearm Statistical Information. (on file with the author).
. See S. Brill, Firearms Abuse: A Research and Policy Report (Police Found., 1977) (a handgun prohibitionist's analysis of a 1976 study of BATF traces).
. Author's personal interview with retired N.Y. City police officer Stephen D'Andrilli (Dec. 1992) (expert in firearms licensing).
. The only non-governmental persons who may own handguns are those whose handguns were registered before 1976. See D.C. Code Ann. §§ 6-2312 (1976).
. See James D. Wright & Peter Rossi, Armed and Considered Dangerous: A Survey of Felons and Their Firearms 10-11 (1986).
. A trace to a particular state could also result from the gun's having been stolen from a firearms store, or firearms wholesaler in that state, with the gun never having been sold at retail.
. See Butterfield, supra note 6, at A14.
. Firearms Statistical Information, supra note 29.
. Bureau of Alcohol, Tobacco and Firearms, Concentrated Urban Enforcement: An Analysis of the Initial Year of Operation Cue in the Cities of Washington D.C., Boston, Mass., Chicago, Ill. 61 (1977).
. See 18 U. S.C. § 924 (1968).
. Virginia's law was enacted in 1994, so it is possible that a significant number of guns traced were sold before the law was enacted. South Carolina's law was enacted in the 1970s; the state's status in 1996, at least in the Schumer study, as a leading crime gun exporter, casts some doubt on the law's effectiveness. Late in the 1996 legislative session, Maryland enacted a one-handgun-per-month law, which became effective in the fall. The law could not fairly be expected to have a major impact on 1996 traces.
. Handgun Control, Inc., The Assault Weapons Ban: Questions & Answers (rev. ed. 1996). For example, one HCI brochure used a line that also appeared in print advertisements, claiming "assault weapons have quickly become the 'weapons of choice' for drug traffickers, street gangs and paramilitary extremist groups." . President Clinton repeated this line verbatim in a speech. See President William J. Clinton, Speech at the Ohio Peace Officers Training Academy ( Feb. 15, 1994).
. See David B. Kopel, Rational Basis Analysis of "Assault Weapon" Prohibition, 20 J. Contemp. L. 381, 411 (1994)(citing Jim Stewart & Andrew Alexander, Assault Guns Muscling in on Front Lines of Crime, Atlanta J.-Atlanta Const., May 21, 1989, at A1).
. See Kopel, supra note 45, at 412.
. See, e.g., Hon. Luis V. Gutierrez, Introduction of Legislation to Ban Semiautomatic Assault Weapons, H.R. 893, Cong. Rec. at E358 (Feb. 17, 1993) (citing the Cox article).
. As noted above, not all guns seized by the police are seized from criminals or are connected with a crime. For the sake of argument, I presume that every "assault weapon" seized by the police was a crime gun.
. See Gary Kleck, Point Blank 75 (1991).
. See Kopel, supra note 45, at 413.
. Bea, supra note 8, at 66.
. See The Law Enforcement Technology Gun Control Survey, L. Enforcement Tech. (July/August 1991, at 14-15). Law Enforcement Technology magazine polled its readership and found that "75% do not favor gun control legislation . . . with street officers opposing it by as much as 85%." Id. In particular, 78.7% opposed a ban on "assault weapons." Id. About 37% of top management supported a ban as did about 11% of street officers. See id. Two thousand police officers participated in the magazine survey. The poll was not a random sample, but instead was based on voluntary mail responses. Accordingly, all the caveats from note 18, supra, are applicable.
. See Gun Control Act of 1968, Pub. L. No. 90-618, 82 Stat. 1313 (1968).
. See Kopel, supra note 45. The figures were: Akron, 1 to 2%; Baltimore, less than 0.3%; Bexar County (San Antonio), 0.1%; Connecticut, 2%; Denver 0.8%; Massachusetts, 0.7%; Miami, 3.13%; Minneapolis 0.4%; Oakland, 3.9%; Orange County (Orlando), Florida, 1.9%; San Diego, 0.3%; Virginia, 3.3%. All data are from police of the relevant jurisdiction. Full citations can be found in David B. Kopel, Guns: Who Should Have Them? 179-81 (1995).
. The law sunsets in 2004. 18 U.S.C. § 922(v) & (w) (1968).
. Letter from J. Harper Wilson, Chief, Uniform Crime Reporting Section, to Paul H. Blackman (Sept. 5, 1990).
. "(W)hen the frequency of traces is considered in proportion to each company's production, a tiny Atlanta company, S. W. Daniel, Inc., shows a tracing rate far higher." Erik Larson, The Story of a Gun, The Atlantic Monthly, Jan. 1993, at 48 (Cobray M-l1/9 pistol).
. See Weil, supra note 2.
. See Roth & Koper, supra note 1; See Handgun Control, Inc., Assault Weapons in America (visited Aug. 31, 1999) http://www.handguncontrol.org/asw.htm>; Physicians for Social Responsibility, Assault Weapons (visited Oct. 28, 1999) http://www.psr.org/assault.htm> "In the first eight months of 1995, after the ban took effect, there was an 18% drop in the number of crimes traced to assault weapons". Id.
. See Jeff Brazil & Steve Berry, Crackdown on Assault Weapons Has Missed Mark, L.A. Times, Aug. 24, 1997, at A1.
. See More Gun Dealers Than Gas Stations, supra note 5.
. See Weil, supra, note 3.
. Jeremy Bentham, Anarchial Fallacies, 2 Works of Jeremy Bentham 501 (1843).


Under section 224 of the Social Security Act (the Act), title II disability insurance benefits may be offset if the disabled worker receives workers' compensation (WC) benefits. The issue here is whether WC offset was properly computed on the basis of an amended stipulation to a prior WC settlement award.
The disabled worker became entitled to Social Security disability insurance benefits in September 1993. Periodic WC payments were paid to the disabled worker January 31, 1993 through July 11, 1994. The disabled worker subsequently received a lump-sum payment on August 19, 1994. The lump sum was prorated at the weekly rate at which the disabled worker had been receiving benefits before the lump-sum settlement. The lump-sum proration ended December 1997.
After offset was imposed, and nearly 2 years after the date of the original lump-sum settlement agreement, the disabled worker obtained an amended lump-sum award in which an attempt was made to subject the lump-sum award to proration over the disabled worker's life expectancy to remove the offset.
Based on section 224 of the Act, case law, and Social Security Administration (SSA) policy, SSA is not necessarily bound by the terms of a second, or amended, stipulation. Instead, SSA will evaluate both the original and amended stipulations and will disregard any language which has the effect of altering the terms in the original lump-sum settlement where, as here, the terms in the amended document are illusory or conflict with the terms of the first stipulation concerning the actual intent of the parties, and would have the effect of circumventing the WC offset provisions of section 224 of the Act.
A question was raised concerning whether SSA should give effect to a Minnesota amended stipulation on a prior lump-sum WC settlement award which originally resulted in offset of the disabled worker's claim. For the reasons stated below, effect need not be given to an amended stipulation to a WC award if it was amended solely to circumvent the WC offset provisions of section 224 of the Act.
The disabled worker became entitled to Social Security disability insurance benefits in September 1993. He received WC periodic payments of $458.99 weekly from January 31, 1993 through January 30, 1994, and $477.35 weekly from January 31, 1994 through July 11, 1994. The disabled worker subsequently received a lump-sum payment of $85,000 less $10,000 withheld for attorney fees based on a stipulation dated August 19, 1994. This lump sum was prorated at the weekly rate of $477.35, the rate at which the disabled worker had been receiving benefits just before the lump-sum award. The lump-sum proration ended December 8, 1997, with a remainder of $31.70 for December 1997.
After offset was imposed, and nearly 2 years after the date of the original lump-sum settlement agreement, the disabled worker obtained an amended lump-sum award in which an attempt was made to prorate the lump-sum award over the disabled worker's life expectancy, which would result in a weekly benefit of $64.97 and thereby trigger removal of the offset.
Section 224 of the Act, 42 U.S.C. 424a, places a ceiling on an individual's combined Social Security disability insurance benefits and State WC benefits. The statute provides that where an individual is receiving both Social Security disability insurance benefits and State WC benefits on account of a disability, his or her Social Security benefits "shall be reduced" by the amount necessary to ensure that the sum of the State and Federal benefits does not exceed 80 percent of the individual's average pre-disability earnings. 42 U.S.C. 424a(a); see also 20 CFR 404.408. As the Supreme Court has explained, "by limiting total state and federal benefits to 80% of the employee's average earnings prior to the disability, [section 224 of the Act] reduce[s] the duplication inherent in the programs and at the same time allow[s] a supplement to workmen's compensation where the state payments [are] inadequate." Richardson v. Belcher, 404 U.S. 78, 83 (1971).
The Act refers only to "periodic benefits" arising under a State worker's compensation program based upon the claimant's "total or partial disability (whether or not permanent)." 42 U.S.C. 424a(a)(2). By its own terms, the statute encompasses virtually every conceivable form of WC benefits. The Act also requires that lump-sum settlements, if they substitute for periodic benefits, be offset, at a rate that will "approximate as nearly as practicable" the rate at which the award would have been paid on a monthly basis and explicitly delegates to the Commissioner the authority to determine the appropriate method of prorating such a lump-sum benefit. 42 U.S.C. 424a(b). As a result, receipt of WC compensation benefits, whether or not in a lump sum, may subject Social Security benefits to reduction.
The issue of whether SSA correctly reduced or offset Social Security benefits due to the settlement of a WC claim is governed by Federal, not State, law. The Eighth Circuit, which is controlling for Minnesota cases, has expressly concluded that the resolution of these issues is entirely a "federal question" to be answered by "the federal statute and its underlying policy, notwithstanding conflicting state law." Munsinger v. Schweiker, 709 F.2d 1212, 1217 (8th Cir. 1983);  see also Campbell v. Shalala, 14 F.3d 424, 427 (8th Cir. 1994) (holding that Federal, not State, law governs whether WC payments could be offset against Social Security disability insurance benefits);  Krysztoforski v. Secretary of Health and Human Services, 55 F.3d 857, 859 (3rd Cir. 1994) (noting that section 224 of the Act does not refer to or defer to State law for the determination of whether a person's periodic benefits are subject to offset, the Third Circuit held that Federal law governs in determining whether a WC award should be offset against disability benefits).
In Munsinger, the Eighth Circuit held that the terms of the lump-sum settlement represented periodic payments which, without an offset, would result in duplicate benefits and that "to deny [the Commissioner] an offset of the settlement would frustrate congressional intent." This same reasoning applies to amendments or addenda to lump-sum settlements -- that is, the terms of both the original stipulations and the amendments to stipulations for settlements should be evaluated in light of the Federal statute and its underlying policy to avoid duplication in benefits. If the original language of the settlement establishes receipt of benefits, establishes the classification of benefits, triggers an offset, and/or establishes an appropriate offset rate, SSA is not bound by any language in a subsequent amendment or addendum which conflicts with, or alters, those terms. If the amended terms have no factual basis or were made solely to circumvent the offset provisions of section 224 of the Act, the use by SSA of such amended terms would frustrate congressional intent to avoid duplicate benefits and will be disregarded.
This is the approach followed in Fox v. Chater, No. 4-95-235 (D. Minn. Feb. 20, 1996), in which the District Court agreed that SSA was not bound by the terms of an amended stipulation. In Fox, after plaintiff received partial disability, temporary partial disability and permanent partial WC benefits, he entered into a stipulation for settlement which was approved by a WC judge, and he was awarded a lump-sum settlement as full and final settlement of any claims for WC benefits. The parties disputed, and left unresolved, whether plaintiff was permanently and totally disabled. In the meantime, the plaintiff applied for, and was awarded, Social Security disability insurance benefits. SSA subsequently determined that the lump-sum payment was subject to offset and reduced the plaintiff's disability benefits. After offset was imposed, the parties entered into a second stipulation which added a provision indicating that the parties agreed that the plaintiff had been permanently and totally disabled as a result of his personal injuries and that the WC benefits he received prior to the stipulation were subject to Minnesota's Social Security offset provisions and that the lump-sum payment agreed upon included a 5 percent reduction in the benefits payable for the Social Security offset. The plaintiff argued that the two stipulations established that the payments made before the stipulation were subject to SSA offset and that the subsequent lump-sum settlement was, therefore, subject to the reverse offset provisions of the Minnesota WC statute.
In Fox, the District Court rejected the plaintiff's arguments and affirmed the administrative law judge's (ALJ) determination not to apply reverse offset on the basis of the "illusory" terms of the amended stipulation. The Court concluded that Mr. Fox's belated claim that the Social Security offset had been considered in the first stipulation was illusory. Noting that the parties did not recognize an offset in the first stipulation and never provided for additional WC benefits if the Social Security disability insurance benefit claim were denied, the Court found that, despite his belated claim in his second stipulation, the plaintiff failed to make a sufficient showing that he had made a settlement which accounted for future Social Security benefits. The Court also rejected plaintiff's argument that both stipulations showed that the parties intended the lump-sum payment to be a permanent total disability benefit because, despite the language in the second stipulation that both parties agreed that Mr. Fox was permanently and totally disabled, the first stipulation was "very clear that the parties do not agree that Fox was permanently and totally disabled." Thus, the Court found that the ALJ was not bound to accept the illusory terms of the second stipulation.
Although unpublished, the holding of Fox is directly applicable to this case. Like Mr. Fox, the disabled worker's belated claim that the original award was to be prorated over his life expectancy appears illusory. The original award did not state that the lump-sum settlement was subject to proration over the disabled worker's life expectancy. A lump sum of $85,000, less attorney's fees, was awarded pursuant to the 1994 lump-sum stipulated settlement. Although the original stipulation did not specify the rate at which the lump sum would be prorated, it noted that a prior weekly rate had been paid. The original stipulation contained no other reference to the proration rate of the lump-sum award, much less any reference to the life expectancy of the disabled worker. The lump sum was prorated, then, at the prior weekly rate of $477.35.
Two years later, in 1996, after offset was imposed, the disabled worker obtained an amended stipulation which expressly confirmed the 1994 Stipulation for Settlement. Nevertheless, the amendment purports to "clarify" the terms of the settlement by attempting to characterize the lump-sum award as prorated over the disabled worker's life expectancy. The amended stipulation, however, did not change the dollar amounts of the award, did not involve any appeal of the award sought or change in the actual amount of WC benefits, and did not affect in any way the rights, liabilities or obligations of the parties with respect to the actual WC award. Its terms modify the original document which did not specify that the lump sum should be prorated over the disabled worker's life expectancy. It contained no supporting factual information that the original stipulation had, in fact, been based on life expectancy.
Based on section 224 of the Act, case law, and SSA policy, SSA is not necessarily bound by the terms of a second, or amended, stipulation in determining whether and by what rate a disabled worker's Social Security disability insurance benefits should be offset on account of a WC lump sum payment. SSA will evaluate both the original and amended stipulations and disregard any language which has the effect of altering the terms in the original lump-sum settlement where the terms in the amended document are illusory or conflict with the terms of the first stipulation concerning the actual intent of the parties, and where, as here, the terms in the amended document would have the effect of circumventing the WC offset provisions of section 224 of the Act. To give effect to such illusory terms would frustrate Congress' intent to avoid duplicate benefits.
 SSR 72-37c (C.E. 1971-1975, p. 466).
 SSR 85-6c (C.E. 1981-1985, p. 692).
 In addition, it is the disabled worker's burden to prove that a lump-sum payment paid by a WC carrier is not subject to offset against the claimant's Social Security disability insurance benefits. Campbell, 14 F.3d at 427-28.
 Under Minnesota law, after permanent total disability benefits of $25,000 have been paid, WC will reduce permanent total disability benefits in order to reflect the disability insurance benefits that an individual is receiving from SSA. Minn. Stat. Ann. § 176.101, Subd. 4; McClish v. Pan-O-Gold Baking Co., 336 N.W.2d 538 (Minn. 1983). Acknowledging this "reverse offset," SSA stops its own offset. POMS DI 52001.226.
 This Ruling does not address the related issue of the validity of stipulated lump-sum settlements where the original settlement contains a term purporting to prorate a lump sum over the life expectancy of the worker. This Ruling only addresses later-added amendments, addenda, etc. whose terms conflict with or change the original terms and where the purpose of these amendments is to circumvent the offset provisions of the Act.
 As noted above, Federal law requires that lump-sum awards be offset at a rate that will "approximate as nearly as practicable" the rate at which the award would have been paid on a monthly basis. 42 U.S.C. 424a(b); 20 CFR 404.408(g). The Commissioner has issued guidelines for calculating the rate at which lump-sum awards should be prorated based on an established weekly rate. See POMS DI 52001.555C.4. The guidelines provide a 3-step priority for establishing weekly rates: first, the rate specified in the award; second, if no rate is specified in the award, the periodic rate paid prior to the lump sum; and third, if no rate was established in the award and there was no preceding periodic benefit, the State's WC maximum weekly rate in effect at the time of the WC injury. POMS DI 52001.555C.4.a-DI 52001.555C.4.c.


104 Continuing Authorizations-Lakes Survey.-The survey- ing and charting of the "Northern and Northwestern lakes" is accomplished as a project under unique authorizations of a continuing nature. Since 1841, the Department of the Army has made surveys of the Great Lakes under legislation ap- propriating funds for that purpose, ascertaining and charting depths in all significant directions to a plane 30 feet below the adopted low-water datum of the open lakes and 25 feet below the corresponding datum in the channels of the connecting rivers.163 The scope of this continuing lake survey was ex- tended in 1911 to include lakes and other navigable waters of the New York State canals;164 in 1913, to include Lake Cham- plain; 165 and in 1914, to include the boundary waters between the Lake of the Woods and Lake Superior.166 Allocation to Navigation at Reclamation Projects.-Under the 1939 Reclamation Project Act, a portion of the total esti- mated construction cost of a reclamation project may be al- located by the Secretary of the Interior to navigation on a non- reimbursable basis.167 And the 1939 Act permits automatic authorization of a reclamation project upon fulfillment of pre- scribed conditions, including the express amendment in the 1944 Flood Control Act.168 Special Projects.-Particular note should be made of three important project authorizations which are exceptions to the general legislative practice of authorizing works in omnibus River and Harbor Acts. All provided for works of improve- ment for navigation and additional purposes. Earliest was the authorization in the 1916 National Defense Act for the construction and operation by the Army Engineers of the Wilson Dam on the Tennessee River, later transferred to TVA.169 In 1937, Congress authorized the Army Engineers to 188 Act of March 3, 1841, § 1, 5 Stat. 421, 431; and, e. g.t Act of October 13,1949, § 1, 63 Stat. 845, -. 164 Act of March 4,1911, § 1, 36 Stat. 1363,1407. 168 Act of June 23,1913, § 1, 38 Stat. 4,38. 169 Act of August 1,1914, § 1, 38 Stat. 609, 637. 187 Act of August 4,1939, § 9(a), 53 Stat. 1187,1193, 43 U. S. C. 485h(a). lftS Act of December 22,1944, § l(c), 58 Stat. 887, 889. 189 Act of June 3, 1916, § 124, 39 Stat. 166, 215, 50 U. S. C. 79. See supra, pp. 54-55.