The Court ended its Term in familiar fashion, with a blockbuster Obamacare ruling. In Burwell v. Hobby Lobby Stores, Inc. (13-354) and Conestoga Wood Specialties Corp. v. Burwell (13-356), the Court considered whether the Religious Freedom Restoration Act of 1993 (RFRA) excuses for-profit corporations that object on religious grounds from having to comply with Obamacare's mandate that employers provide insurance coverage for their employees' contraceptive medications and devices. In a sharply divided 5-4 decision, the Court sided with the plaintiff corporations.
The case involved the Affordable Care Act's employer mandate for group health insurance coverage to include cost-free preventive care for women, and related HHS regulations requiring coverage for all FDA-approved contraceptive methods. HHS exempted religious institutions and certain nonprofit corporations organized for religious purposes. If one of those nonprofit groups certified its religious objection, then the group's insurer would exclude contraceptive coverage from the insurance plan and the insurer would fund the covered women's contraceptive costs (with no net loss to the insurer due to the savings in health costs from women using the contraception).
Hobby Lobby (with 13,000 employees in 500 stores) and Conestoga (with 950 employees) are for-profit corporations, but closely held in that each is owned by a small number of family members. The owners of Hobby Lobby and Conestoga aim to run their businesses in accordance with their religious principles and therefore objected to specific contraceptives ("morning-after" pills and IUDs) that they believe are abortifacient. Both companies sought relief from the mandate, arguing that it amounted to a substantial incursion on their free exercise rights under RFRA.
The Court, in an opinion authored by Justice Alito and joined by the Chief and Justices Scalia, Kennedy, and Thomas, went through each of the statutory elements of RFRA and held that: (1) for-profit corporations are "persons" for purposes of RFRA's prohibition against the federal government substantially burdening a person's exercise of religion even with a law of general applicability; (2) the federal mandate substantially burdens the plaintiff corporations' exercise of religion; (3) the government may nevertheless be able to justify the mandate as furthering a compelling governmental interest (though the Court did not decide that disputed issue); (4) but even if the interest is compelling, the mandate violates the plaintiffs' rights under RFRA because it is not the least restrictive means of furthering that governmental interest.
Starting with the first statutory element, Justice Alito wrote passionately that corporations are owned and run by human beings, and that corporations have legal rights that protect the interests of those people. Given the strong protection for religious liberty in RFRA, Congress could not have intended either to exclude business owners from that protection if they chose to incorporate or to cause them to avoid that form of business organization in order to secure their liberty. The Dictionary Act (how often do we get to cite 1 U.S.C. § 1?) defines "person" to include corporations unless the context indicates otherwise. Moreover, nonprofit corporations have been recognized by the Court and by HHS as persons under the RFRA. According to Justice Alito, there is no basis for defining "personhood" under RFRA based upon the pursuit of profit. The pursuit of profit does not prevent a corporation under state law from also being organized around owners' religious principles, at least for closely held corporations. The Court was not troubled by the prospect of publicly traded corporations making RFRA claims, as none had done so and it was most improbable that unrelated shareholders could agree to run a business based on a set of sincere religious beliefs as Hobby Lobby and Conestoga have done.
Moving on to RFRA's second statutory element, the Court's majority thought the contraceptive mandate plainly burdened the plaintiffs' exercise of religion. Requiring the companies and their owners to arrange for coverage of birth control methods that may destroy a fertilized egg would violate their religious beliefs, and the statutory financial penalties for either ignoring the contraceptive mandate or dropping employee insurance coverage entirely would be burdensome. The Court thought little of the argument that simply offering health insurance coverage, with the employee making the choice of what medicines to take, does not substantially burden the exercise of religion. Yet, that is precisely the argument that the four dissenters (Justice Ginsburg, joined now by Justices Breyer and Kagan, in addition to Sotomayor) accepted, as the companies merely direct money into an undifferentiated fund for financing various benefits under a health plan and how the benefits are used is the employee's decision in consultation with her physician.
Under RFRA's third statutory element, the federal government may justify the burden if it furthers a compelling governmental interest. The majority chose not to tackle this issue head-on and, for purposes of its analysis, assumed that "the interest in guaranteeing cost-free access to the four challenged contraceptive methods is compelling within the meaning of RFRA." The four dissenting Justices went further and explained at length the compelling interest in protecting public health and women's well-being. In their view, no religious accommodation should ever be granted where the accommodation would be harmful to third parties.
The Court's decision therefore turned on RFRA's fourth statutory element, whether the contraceptive mandate was the least restrictive means of upholding the government's compelling interest. The majority deemed this test "exceptionally demanding," going beyond what the Constitution's guarantee of the free exercise of religion would require. The contraceptive mandate flunked. After all, the government could simply assume the cost of providing the contraceptives directly, as there is no evidence that this will be a significant cost to the government in relation to the overall cost of the Affordable Care Act and a small price to pay to achieve the compelling government interest. The majority rejected the notion that RFRA cannot be used to require creation of a new government program, although it acknowledged that cost could at some level factor into the least-restrictive-means analysis. In any case, HHS had already demonstrated another less restrictive means of achieving the Government's interest, in its accommodation of churches and religious nonprofits who are exempted from the mandate. The majority was careful, however, not to endorse that accommodation as necessarily complying with RFRA "for purposes of all religious claims."
Justice Alito closed by countering the concern of a slippery slope -- there was no evidence of a flood of requests for religious exemptions from any coverage mandate other than the contraceptive mandate, such as blood transfusions or vaccinations. The Court had already rejected religious objections to social security taxes, and "there simply is no less restrictive alternative to the categorical requirement to pay taxes." The majority posited its own slippery slope: That accepting HHS's position "would permit the Government to require all employers to provide coverage for any medical procedure allowed by law in the jurisdiction in question -- for instance, third-trimester abortions or assisted suicide." Because owners of many closely held corporations would object to that coverage, "HHS would effectively exclude these people from full participation in the economic life of the Nation. RFRA was enacted to prevent such an outcome."
Justice Kennedy, who fully joined the Court's opinion, wrote separately to emphasize "that the Court's opinion does not have the breadth and sweep ascribed to it by the respectful and powerful dissent." While the majority equivocated whether the government had a compelling interest, but assumed it to be the case, Justice Kennedy affirmed the compelling interest "in the health of female employees." But he also emphasized that the record shows there is an existing and workable alternative to the contraceptive mandate already in place for nonprofit religious organizations, and the government cannot meet its burden of showing that it cannot accommodate the for-profit corporations in the same manner. Somewhat in tension with the majority opinion, which did not fully embrace the nonprofit accommodation over a government-pay system, Justice Kennedy extolled this accommodation over the government itself creating a new program by funding the contraceptives. He believed that the existence of the accommodation distinguished this case from others where a corporation might argue for religious exemption from a different mandate.
The four dissenting Justices put no stock in the majority's view of an adequate, less restrictive means of furthering the government's compelling interest. The dissenters believed that trying to set up and administer any system other than the existing employer-based system of health insurance would impose logistical and administrative burdens on women seeking coverage. Plus, the dissenters wrote, the majority hedged whether the nonprofit accommodation would actually be acceptable to companies like Hobby Lobby and Conestoga. Also, unlike the majority, they did not see a logical stopping point to granting religious exemptions to for-profit corporations beyond the contraceptive mandate. In their view, distinguishing between a religious objection to contraceptives and an objection to other medicines or procedures would itself put the courts in the impermissible business of deciding which religious beliefs are more worthy of accommodation than others. As Justice Ginsburg wrote, "The Court, I fear, has ventured into a minefield."
Indeed, just a few days after Hobby Lobby was released, the Court issued an order in Wheaton College v. Burwell (13A1284), granting the Illinois religious college's emergency application for an injunction (previously refused by the Seventh Circuit) pending appeal of the District Court's denial of a preliminary injunction exempting it from the requirement that it use a specific HHS form certifying its religious objection to trigger the nonprofit accommodation for the contraceptive mandate. In the college's view, submitting that form to its insurance carrier, as HHS requires, makes the college complicit with the provision of the objectionable contraceptives. The college is willing, however, to notify HHS directly of its objection (without the form), and the Supreme Court's order found that sufficient for now without opining on the ultimate merits of the challenge to this part of the nonprofit accommodation. Justice Sotomayor, joined by Justices Ginsburg and Kagan, wrote a lengthy dissent from the order, finding no grounds for emergency interlocutory relief and questioning how using the form could burden religious belief, as well as noting how the Court had just relied on the nonprofit accommodation in the Hobby Lobby case to grant relief to for-profit corporations under RFRA.
Mach Mining, LLC v. EEOC (13-1019): "Whether and to what extent may a court enforce the EEOC's mandatory duty to conciliate discrimination claims before filing suit?"
Mellouli v. Holder (13-1034): "[M]ust the government prove the connection between a drug paraphernalia conviction and a substance listed in section 802 of the Controlled Substances Act" to trigger deportability under 8 U.S.C. § 1227(a)(2)(B)(i)?
United States v. Wong (13-1074): Is the six-month time bar for filing suit in federal court under the Federal Tort Claims Act, 28 U.S.C. 2401(b), subject to equitable tolling?
Relatedly, United States v. June (13-1075) asks: Is the two-year time limit for filing an administrative claim with the appropriate federal agency under the Federal Tort Claims Act, 28 U.S.C. 2401(b) subject to equitable tolling?
Gelboim v. Bank of America Corp. (13-1174): "Whether and in what circumstances is the dismissal of an action that has been consolidated with other suits immediately appealable?"
Young v. United Parcel Service, Inc. (12-1226): "Whether, and in what circumstances, an employer that provides work accommodations to nonpregnant employees with work limitations must provide work accommodations to pregnant employees who are ‘similar in their ability or inability to work.'"
Kellogg Brown & Root v. United States (12-1497): (1) "Whether the Wartime Suspension of Limitations Act—a criminal code provision that tolls the statute of limitations for ‘any offense' involving fraud against the government ‘[w]hen the United States is at war,' 18 U.S.C. § 3287 … applies to claims of civil fraud brought by private relators, and is triggered without a formal declaration of war, in a manner that leads to indefinite tolling;" and (2) "Whether … the False Claims Act's so-called ‘first-to file' bar, 31 U.S.C. § 3730(b)(5)—which creates a race to the courthouse to reward relators who promptly disclose fraud against the government, while prohibiting repetitive, parasitic claims—functions as a ‘one case- at-a-time' rule allowing an infinite series of duplicative claims so long as no prior claim is pending at the time of filing."
Oneok, Inc. v. Learjet, Inc. (13-271): "Does the Natural Gas Act preempt state-law claims challenging industry practices that directly affect the wholesale natural gas market when those claims are asserted by litigants who purchased gas in retail transactions?"
B&B Hardware, Inc. v. Hargis Industries, Inc. (13-352): Whether a finding by the Trademark Trial and Appeal Board that Hargis's "SEALTITE" mark created a likelihood of confusion with B&B's "SEALTIGHT" mark "precludes Hargis from relitigating that issue in infringement litigation, in which likelihood of confusion is an element;" and (2) "Whether, if issue preclusion does not apply, the district court was obliged to defer to the TTAB's finding of a likelihood of confusion absent strong evidence to rebut it."
Reed v. Gilbert, AZ (13-502): Whether the Town of Gilbert's "mere assertion of a lack of discriminatory motive render its facially content-based sign code content-neutral and justify the code's differential treatment of Petitioners' religious signs?"
Alabama Dept. of Revenue v. CSX Transportation (13-553): (1) "Whether a State ‘discriminates against a rail carrier' in violation of 49 U.S.C. §11501(b)(4) when the State generally requires commercial and industrial businesses, including rail carriers, to pay a sales-and-use tax but grants exemptions from the tax to the railroads' competitors;" and (2) "Whether, in resolving a claim of unlawful tax discrimination under 49 U.S.C. §11501(b)(4), a court should consider other aspects of the State's tax scheme rather than focusing solely on the challenged tax provision."
Wellness Int'l Network v. Sharif (13-935): (1) "Whether the presence of a subsidiary state property law issue in a 11 U.S.C. § 541 action brought against a debtor to determine whether property in the debtor's possession is property of the bankruptcy estate means that such action does not ‘stem from the bankruptcy itself' and therefore, that a bankruptcy court does not have the constitutional authority to enter a final order deciding that action"; and (2) "Whether Article III permits the exercise of the judicial power of the United States by the bankruptcy courts on the basis of litigant consent, and if so, whether implied consent based on a litigant's conduct is sufficient to satisfy Article III."
Direct Marketing Association v. Brohl (13-1032): Whether the Tax Injunction Act, 28 U.S.C. § 1341, "bars federal court jurisdiction over a suit brought by non taxpayers to enjoin the informational notice and reporting requirements of a state law that neither imposes a tax, nor requires the collection of a tax, but serves only as a secondary aspect of state tax administration?"
Finally, the Court asked for the SG's views on the petition for certiorari in Teva Pharmaceuticals USA v. Superior Court of California (13-956), which would ask whether the California Court of Appeal erred when it held that "federal law does not preempt state tort claims predicated on allegations that a generic drug manufacturer violated the [federal Food, Drug, and Cosmetic Act] by failing to immediately implement or otherwise disseminate notice of labeling changes that the United States Food and Drug Administration had approved for use on a generic drug product's brand name equivalent."
Thanks for following the 2013-2014 Term with us! We'll be back in the fall.


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[294 U.S. 458, 459] Messrs. J. P. Plunkett and R. J. Hagman, both of St. Paul, Minn., for petitioner.
Mr. Stanley B. Houck, of Minneapolis, Minn., for respondent.
Respondent sued the railway company in the District Court for Minnesota to recover $3,990.20 awarded by the Interstate Commerce Commission as reparation. Alberta Coal Sales Co. v. Canadian Nat. Rys., 142 I.C.C. 543. That court gave him judgment; the Circuit Court of Appeals affirmed. Great Northern Ry. Co. v. Sullivan, 72 F.(2d) 587. We are called on to decide whether the uncontroverted facts and those found by the commission are sufficient to warrant the conclusion that he sustained damage in consequence of violation of the Act (Interstate Commerce Act 1 et seq., 49 USCA 1 et seq.) by defendant.
Plaintiff, a wholesale dealer, bought carloads of lignite at mines on the Canadian Pacific in Alberta, and sold the same to retail dealers and others in North Dakota at Great Northern stations in competition with other fuels. The shipments moved on combination rates, being the sum of proportionals made respectively by the Canadian Pacific and the Great Northern,1 applicable from mines to destinations, and on through bills of lading issued by the former, routing over its railroad to junction with the latter [294 U.S. 458, 460] at the international boundary and thence over the railroad last mentioned to places of delivery. The combination rates necessarily reflect agreement, express or implied, between the connecting carriers to establish a through route for continuous carriage from origin on one to destination on the other. Each proportional necessarily was a part of the through rate and was capable of use only as such. St. Louis S.W. Ry. Co. v. United States, 245 U.S. 136 , 139 note 2, 38 S.Ct. 49, 50 note 4, 205 note 4. They show the basis of division of charges between connecting carriers and serve precisely as do agreed divisions of charges based on joint rates. A proportional differs from a local rate in that it covers only terminal service at place of receipt or at place of delivery but cannot, as does the local rate, cover both. Lewis, etc., Co. v. Southern Pac. Co., 283 U.S. 654, 663 , 51 S.Ct. 592.2There [294 U.S. 458, 461] was no applicable joint rate. The Great Northern collected the charges and paid the Canadian Pacific amounts equal to the proportionals established by the latter.
Plaintiff and another complained to the commission alleging the proportionals filed by the Great Northern and other American carriers to be unjust and unreasonable in violation of section 1 (49 USCA 1). They did not attack the combination or allege aught against the Canadian Pacific proportional. They prayed merely reasonable maximum American proportionals and reparation to the extent of the excess over such maxima. The commission found the American proportionals to be unjust and unreasonable so far as they exceed specified maxima which it made applicable in lieu of those assailed. It made no finding concerning the reasonableness of the Canadian proportionals or of the combination through rates. There being no claim or finding to the contrary, the charges collected on these shipments must be deemed to have been just and reasonable. Indeed, dissenting commissioners, without opposition on the part of the others, state that they are affirmatively shown to be reasonable.
The Great Northern was by the Act required to file tariffs establishing reasonable proportionals to constitute [294 U.S. 458, 462] and to be kept in force as factors in the combination through rates applicable to plaintiff's shipments. Its failure to specify just and reasonable charges was a violation of the Act. And, if injured thereby, plaintiff is entitled to recover the damages sustained in consequence of such failure. 49 U.S.C. 8 (49 USCA 8). Plaintiff invokes News Syndicate Co. v. N.Y.C.R.R., 275 U.S. 179 , 48 S.Ct. 39, and Lewis, etc., Co. v. Southern Pac. Co., supra. But neither is like this case. In each, shipments moved from an adjacent country into the United States on through rates made by joint action of the participating foreign and American carriers. The American carrier, having violated the Act by failure to file any tariff to cover its part of the transportation, collected freight charges found to be excessive and, as one of two or more joint tort-feasors, was held liable to the extent that the charges it exacted were in excess of what the commission ascertained to be just and reasonable. But here the charges collected were not excessive, and confessedly the same amounts lawfully might have been collected without injury or damage to plaintiff if only the connecting carriers had imposed the charges by means of 'joint' instead of the 'combination' through rates that they did establish.
If defendant's proportional added to that established by the Canadian Pacific had produced an unjust rate, then to the extent that the total charge was excessive, plaintiff would have been subjected to a disadvantage in competing with others selling fuel in the same territory. The commission has power to determine rates to be unreasonable in violation of section 1 (49 USCA 1) without determining whether their application has resulted or will result in pecuniary loss or damage to the shipper. It may determine whether a proportional constituting a part of a combination rate violates section 1 without passing upon the validity of the rate as a whole. Atchison, T. & S.F. Ry. v. United States, 279 U.S. 768, 776 , 49 S.Ct. 494. But the commission may not order [294 U.S. 458, 463] or permit payment of damages by way of reparation without finding that the amount of the charge was unjust and unreasonable. News Syndicate Co. v. N. Y.C.R.R., supra, page 187 of 275 U.S., 48 S.Ct. 39. And defendant, enforcing an unlawful charge to be divided between it and the Canadian Pacific, would be liable as a joint tort-feasor for the full amount of the excess. Louisville & N.R.R. Co. v. Sloss-Sheffield Co., 269 U.S. 217, 231 , 46 S.Ct. 73, et seq. News Syndicate Co. v. N.Y.C.R.R., supra. Lewis, etc., Co. v. Southern Pac. Co., supra.
But the claim before us has no such foundation. Plaintiff seeks to recover the difference between the proportional established by defendant and that found by the commission to be just and reasonable notwithstanding its fuel was hauled from mines to the competitive field for a just and reasonable charge. That position cannot be maintained for as to the shipments here involved the Great Northern proportional cannot be applied save as it is a part of the through rate. There was a single charge which, though based on the combination rate, was precisely the same in amount as if the rate had been jointly made. As shown by our decision in Louisville & N.R.R. Co. v. Sloss-Sheffield Co., supra, page 234, of 269 U.S., 46 S.Ct. 73, the division among connecting carriers of charges based on joint rates- those involved in that case were constructed out of existing proportionals- is no concern of the shipper. The proportionals here involved are but parts of a through rate and cannot be distinguished from divisions of a joint rate. Morrell & Co. v. N.Y.C.R.R. Co., 104 I.C.C. 104, 128. The shipper's only interest is that the charge shall be reasonable as a whole. It follows that retention by the defendant of an undue proportion of just and reasonable charges did not damage plaintiff. Louisville & N.R.R. Co. v. Sloss-Sheffield Co., supra, page 234 of 269 U.S., 46 S.Ct. 73. Parsons v. Chicago & Northwestern Ry., 167 U.S. 447, 460 , 17 S.Ct. 887.
[ Footnote 1 ] Canadian Pacific Tariff No. W-5379, I.C.C. No. W-723; Great Northern I.C.C. No. A-5681, G.F.O. No. 435-G.
Through bills of lading issued under the Interstate Commerce Act, 25(4, 5), 49 USCA 25(4, 5), do not constitute 'an arrangement for continuous carriage or shipment' within the meaning of the Act. Bills of Lading, 52 I.C.C. 671, 730. Export Bill of Lading, 64 I.C.C. 347.
The Commission deals with rates applicable to inland hauls above referred to and with reparation without consideration of charges or factors attributable to transportation by sea or in foreign countries. Ullman v. Adams Express Company, 14 I.C.C. 340, 345; Chamber of Commerce of N.Y. v. N.Y.C. & H.R.R. Co., 24 I.C.C. 55, 74; Henry Marble Co. v. B. & O.R.R. Co., 146 I.C.C. 414.

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FindACase | Fireman's Fund Insurance Co. v. Regions Insurance, Inc.
Fireman's Fund Insurance Co. v. Regions Insurance, Inc.
Before this Court is Defendant Performance Insurance Services' motions to dismiss, or, in the alternative compel arbitration [11, 22]. In this case, Plaintiff Fireman's Fund Insurance Company ("FFIC") alleges the Defendants failed to provide certain required documents to an insured, and, as a result FFIC was forced to pay out an insurance claim in excess of the stated limits of the insured policy. One of the Defendants, Performance Insurance Services ("Performance") argues that FFIC's claims against it should be dismissed, or alternatively arbitrated pursuant to arbitration provisions contained in the agreements between the two.
Defendant Regions Insurance, Inc. ("Regions") has filed an indemnity cross-claim against Performance. Performance argues that this cross-claim should also be dismissed, or alternatively, submitted to arbitration. The Court finds that these motions should be granted with respect to compelling arbitration but denied with respect to dismissing the claims.
In 2014, nonparty Dustin Roberts consulted with Casey Johnson, an employee of Regions, about obtaining insurance coverage for his business. Compl. ¶¶ 6-7. At that time, Regions was acting as a producer for Performance selling FFIC insurance policies, among other insurance products. Compl. ¶ 7. Johnson secured a policy for Roberts through FFIC that included coverage for several vehicles Roberts owned. Id. ¶¶ 7-8. By the terms of the policy, coverage included a single limit of $500, 000 in non-stacking, uninsured motorists coverage for each vehicle. Id. ¶ 8.
On February 2, 2015, while the policy was in effect, Roberts' wife, Tiffany, and his daughter, Kaylee, were driving a vehicle insured under the policy, when they were struck by an uninsured driver. Id. ¶¶ 10-12. Tiffany was killed, and Kaylee was severely injured. Id. ¶ 12.
Roberts filed an insurance claim with FFIC. Id. ¶ 13. Because the policy provided for non-stacking coverage, FFIC initially believed that maximum recovery amount was $500, 000. However, while investigating the claim, FFIC discovered that Roberts was unaware of the difference between stacking and non-stacking coverage. FFIC also discovered that Roberts had not executed an uninsured motorists coverage election form. Id. ¶ 14. Mississippi law requires that before issuing a policy that provides for non-stacking coverage, the insurer must inform the insured about the limits of non-stacking coverage and obtain an election form from the insured. Miss. Code Ann. §83-11-102.
Roberts eventually filed suit against FFIC, asserting FFIC's failure (through its agents and subagents) to comply with § 83-11-102 meant that he was entitled to stack the coverage of all of his vehicles. Id. ¶ 15. Despite the fact the policy provided only $500, 000 of coverage, FFIC believed they could not rely on the policy language, and therefore settled with Roberts for $3, 132, 946.00. Id. ¶ 16-17.
FFIC now brings claims for negligence, negligent training and supervision, breach of contract, and breach of fiduciary duties against Defendants, alleging that Johnson (and therefore Regions, and therefore Performance) failed to discuss the uninsured motorists coverage with Roberts and obtain the election form as required by Mississippi law. As a result, FFIC argues, it was forced to pay Roberts $2, 632, 946 more in insurance proceeds than it should have under the policy. Regions subsequently filed an indemnity cross-claim against Performance arguing that Performance must indemnify Regions for any damages it ultimately pays to FFIC.
Performance filed a motion to dismiss, or in the alternative, compel arbitration of FFIC's claims against it, arguing that the arbitration provisions in the agreements executed between FFIC and Performance requires the parties to arbitrate this dispute. Performance also filed a motion to dismiss, or in the alternative, compel arbitration of Regions' cross-claim, arguing that Regions cross-complaint failed to state a claim for relief, or alternatively, Regions should be forced to arbitrate its indemnity cross-claim. The Court now addresses those motions in turn.
The Court generally assesses whether the parties agreed to arbitrate the dispute in question using a two-step process: "(1) whether there is a valid agreement to arbitrate between the parties; and (2) whether the dispute in question falls within the scope of that arbitration agreement." See Gross v. GGNSC Southaven, L.L.C., 817 F.3d 169, 176 (5th Cir. 2016). If the Court finds that the parties have a valid agreement to arbitrate and that the dispute is within the scope of the arbitration agreement, the Court generally examines whether any legal constraints foreclose arbitration of those claims. See Brown v. Pac. Life Ins. Co., 462 F.3d 384, 396 (5th Cir. 2006) (citing Mitsubishi Motors Corp., 473 U.S. at 628, 105 S.Ct. 3346)). Courts must "apply the federal policy favoring arbitration when addressing ambiguities regarding whether a question falls within an arbitration agreement's scope, but... do not apply this policy when determining whether a valid agreement exists." Sherer v. Green Tree Servicing LLC, 548 F.3d 379, 381 (5th Cir. 2008). See Volt Info. Scis., Inc. v. Bd. o/Trs. of Leland Stanford Jr. Univ., 489 U.S. 468, 475-76, 109 S.Ct. 1248, 103 L.Ed.2d 488 (1989); Banc One Acceptance Corp. v. Hill, 367 F.3d 426, 429 (5th Cir. 2004) (citing Will-Drill Res., Inc. v. Samson Res. Co., 352 F.3d 211, 214 (5th Cir. 2003)); Westmoreland v. Sadoux, 299 F.3d 462, 465 (5th Cir. 2002). The determination of whether a party is bound by an arbitration agreement is included within the broader issue of whether the parties agreed to arbitrate. Bridas S.A.P.I.C. v. Gov't of Turkmenistan, 345 F.3d 347, 355 (5th Cir. 2003) (citing Smith/Enron Cogeneration Ltd. P'ship, Inc. v. Smith Cogeneration Int'l, Inc., 198 F.3d 88, 95 (2d Cir. 1999)). "The purpose of the FAA is to give arbitration agreements the same force and effect as other contracts-no more and no less." Washington Mut. Fin. Grp., LLC v. Bailey, 364 F.3d 260, 264 (5th Cir. 2004) (citing 9 U.S.C. § 2); see Pennzoil Expl. & Prod. Co. v. Ramco Energy Ltd., 139 F.3d 1061, 1064 (5th Cir. 1998) ("[arbitration is a matter of contract between the parties").
Performance and FFIC do not dispute that a valid arbitration agreement exists. See PL's Resp. at pp. 1-2. Rather, FFIC argues that the scope of the arbitration provision does not apply to the claims it makes against Performance.


text:
A string of memory cells with a charge trapping structure is read, by selecting part of a memory cell selected by a word line. Part of the memory cell is selected by turning on one of the pass transistors on either side of the string of memory cells. The charge storage state of the selected part is determined by measuring current in a bit line tied to both pass transistors.
The present application is a divisional of U.S. application Ser. No. 10/973,176 filed 26 Oct. 2004, which claims the benefit of U.S. Provisional Application 60/608,455 filed 9 Sep. 2004 and the benefit of U.S. Provisional Application No. 60/608,528 filed 9 Sep. 2004.
The present invention relates to electrically programmable and erasable non-volatile memory, and more particularly to charge trapping memory with a bias arrangement that reads the contents of different positions in the charge trapping structure of the memory cell with great sensitivity.
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry name PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
Conventional memory cell structures rely on the reverse read operation to determine the contents of the memory structure. However, the reverse read technique effectively couples together multiple locations of the charge trapping structure, even when only portion of the charge trapping structure contains data of interest. This dependence constrains the difficulty of using the charge trapping structure as nonvolatile memory, by narrowing the sensing window of currents measured from the reverse read technique. Less data are stored in the charge trapping structure than otherwise possible.
Thus, a need exists for a charge trapping memory cell that can be read without suffering substantial coupling between multiple locations of the charge trapping structure, even when only a portion of the charge trapping structure contains data of interest.
A method of operating a memory cell, an architecture for an integrated circuit including such a memory cell, and a method of manufacturing such memory, are provided.
A nonvolatile memory according to the described technology comprises memory cells arranged in a series having a first end and a second end, a first pass transistor coupled to the first end of the series, a second pass transistor coupled to the second end of the series, a bit line coupled to the first pass transistor and the second pass transistor, word lines coupled to the top dielectrics of the memory cells, and logic coupled to the memory cells. Each memory cell includes a substrate region including source and drain regions, a bottom dielectric coupled to the substrate region, a charge trapping structure coupled to the bottom dielectric having parts corresponding to the source and drain regions, and a top dielectric coupled to the charge trapping structure. Each of the parts of the charge trapping structure has a charge storage state, which stores one bit or multiple bits, depending on the application and design of the memory cell. The logic turns on one of the first pass transistor and the second pass transistor to permit electrical coupling of the bit line to the source region or the drain region of a memory cell. This selects part of the charge trapping structure corresponding to the source region or the drain region. For example, if a source region of a selected memory cell is closer to the first end of the series than the drain region of the selected memory cell, then turning on the first pass transistor coupled to the first end of the series selects the part of the charge trapping structure of the selected memory cell which corresponds to the source region. In another example, if a drain region of a selected memory cell is closer to the first end of the series than the source region of the selected memory cell, then turning on the first pass transistor coupled to the first end of the series selects the part of the charge trapping structure of the selected memory cell which corresponds to the drain region.
The voltage difference between the gate and one of the source region or the drain region creates an electric field which causes band bending in one of the source region or the drain region. The degree of band bending is affected by the charge storage state of the part of the charge trapping structure corresponding to one of the source region or the drain region, resulting in a band-to-band tunneling current in one of the source region or the drain region that varies with the charge storage state. In some embodiments, the bias arrangement applies a reverse bias voltage difference between the substrate region and one of the source region or the drain region, and floats the other of the source region or the drain region. Such a bias arrangement results in the avoidance of substantial coupling between the part of the charge trapping structure corresponding to the source region and the part of the charge trapping structure corresponding to the drain region. A current measurement that determines the charge storage state of the charge trapping structure corresponding to the source region is substantially independent of the charge storage state of the charge trapping structure corresponding to the drain region, and vice versa.
In some embodiments, the bias arrangement causes a first voltage difference between the gate and the one of the source region or the drain region, and a second voltage difference between the substrate region and the one of the source and drain regions. The first voltage difference and the second voltage difference cause sufficient band-to-band tunneling current for the measuring. However, the first voltage difference and the second voltage differences fail to change the charge storage state. Thus, the read operation is not destructive of the data stored in the charge trapping structure. In some embodiments the first voltage difference is at least about 5 V between the gate and the one of the source region or the drain region, and the second voltage difference less than about 2 V between the substrate region and the one of the source region or the drain region.
In some embodiments, the logic applies a second bias arrangement to adjust the charge storage state by increasing a net positive charge in the charge trapping structure, and applies a third bias arrangement to adjust the charge storage state by increasing a net negative charge in the charge trapping structure. Net positive charge is increased in the charge trapping structure via current mechanisms such as band-to-band hot hole tunneling. Net negative charge is increased in the charge trapping structure via current mechanisms such as electron tunneling, Fowler-Nordheim tunneling, channel hot electron injection current, and channel initiated secondary electron injection current. In some embodiments, the measured current is at least about 10 times greater for the charge storage state adjusted by one of the second bias arrangement and the third bias arrangement than said measured current for the charge storage state adjusted by the other of the second bias arrangement and the third bias arrangement, for example about 100 nA for one measurement and about 1 nA for the other measurement.
Other embodiments of the technology described above include a method for selecting a memory cell, and a method of manufacturing nonvolatile memory according to the described technology.
FIG. 2A is a simplified diagram of a charge trapping memory cell, showing a program operation being performed on the portion of the charge trapping structure corresponding to the drain side.
FIG. 2B is a simplified diagram of a charge trapping memory cell, showing an erase operation being performed on the charge trapping structure, with electrons moving in the general direction from the gate to the substrate region.
FIG. 2C is a simplified diagram of a charge trapping memory cell, showing another erase operation being performed on the charge trapping structure, with electrons moving in the general direction from the substrate region to the gate.
FIG. 3A is a graph showing the sensing window of an ideal memory cell.
FIG. 3B is a graph showing the sensing window of a typical memory cell.
FIG. 4A is a graph showing an erase operation being performed on a memory cell.
FIG. 4B is a graph showing a program operation being performed on part of the charge trapping structure of a memory cell.
FIG. 4C is a graph showing a program operation being performed on another part of the charge trapping structure of a memory cell.
FIG. 5A is a simplified diagram of a string of charge trapping memory cells, showing a program operation being performed on a portion of a selected memory cell.
FIG. 5B is a simplified diagram of a string of charge trapping memory cells, showing a program operation being performed on another portion of a selected memory cell.
FIG. 6A is a simplified diagram of a string of charge trapping memory cells, showing a read operation being performed on a portion of a selected memory cell.
FIG. 6B is a simplified diagram of a string of charge trapping memory cells, showing a read operation being performed on another portion of a selected memory cell.
FIG. 7A is a simplified diagram of a string of charge trapping memory cells, showing an erase operation being performed on the memory string.
FIG. 7B is a simplified diagram of a string of charge trapping memory cells, showing another erase operation being performed on the memory string.
FIG. 8 is a simplified diagram of a string of charge trapping memory cells, showing both ends of the memory string electrically coupled to a common bit line.
FIG. 9 is a simplified diagram of an array of charge trapping memory cells, showing an erase operation being performed on the memory array.
FIG. 10 is a simplified diagram of an array of charge trapping memory cells, showing another erase operation being performed on the memory array.
FIG. 11 is a simplified diagram of an array of charge trapping memory cells, showing a program operation being performed on one portion of selected cells of the memory array.
FIG. 12 is a simplified diagram of an array of charge trapping memory cells, showing a program operation being performed on another portion of selected cells of the memory array.
FIG. 13 is a simplified diagram of an array of charge trapping memory cells, showing a read operation being performed on one portion of selected cells of the memory array.
FIG. 14 is a simplified diagram of an array of charge trapping memory cells, showing a read operation being performed on another portion of selected cells of the memory array.
FIG. 15 is a simplified diagram of an integrated circuit with an array of charge trapping memory cells and control circuitry.
FIG. 1A is a simplified diagram of a charge trapping memory cell, showing a read operation being performed on the source side of the charge trapping structure. The p-doped substrate region 170 includes n+ doped source and drain regions 150 and 160. The remainder of the memory cell includes a bottom dielectric structure 140 on the substrate, a charge trapping structure 130 on the bottom dielectric structure 140 (bottom oxide), a top dielectric structure 120 (top oxide) on the charge trapping structure 130, and a gate 110 on the oxide structure 120. Representative top dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 5 to 10 nanometers, or other similar high dielectric constant materials including for example Al2O3. Representative bottom dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 3 to 10 nanometers, or other similar high dielectric constant materials. Representative charge trapping structures include silicon nitride having a thickness of about 3 to 9 nanometers, or other similar high dielectric constant materials, including metal oxides such as Al2O3, HfO2, and others. The charge trapping structure may be a discontinuous set of pockets or particles of charge trapping material, or a continuous layer as shown in the drawing.
The memory cell for PHINES-like cells has, for example, a bottom oxide with a thickness ranging from 2 nanometers to 10 nanometers, a charge trapping layer with a thickness ranging from 2 nanometers to 10 nanometers, and a top oxide with a thickness ranging from 2 nanometers to 15 nanometers.
In some embodiments, the gate comprises a material having a work function greater than the intrinsic work function of n-type silicon, or greater than about 4.1 eV, and preferably greater than about 4.25 eV, including for example greater than about 5 eV. Representative gate materials include p-type poly, TiN, Pt, and other high work function metals and materials. Other materials having a relatively high work function suitable for embodiments of the technology include metals including but not limited to Ru, Ir, Ni, and Co, metal alloys including but not limited to Ru—Ti and Ni-T, metal nitrides, and metal oxides including but not limited to RuO2. High work function gate materials result in higher injection barriers for electron tunneling than that of the typical n-type polysilicon gate. The injection barrier for n-type polysilicon gates with silicon dioxide as the top dielectric is around 3.15 eV. Thus, embodiments of the present technology use materials for the gate and for the top dielectric having an injection barrier higher than about 3.15 eV, such as higher than about 3.4 eV, and preferably higher than about 4 eV, For p-type polysilicon gates with silicon dioxide top dielectrics, the injection barrier is about 4.25 eV, and the resulting threshold of a converged cell is reduced about 2 volts relative to a cell having an n-type polysilicon gate with a silicon dioxide top dielectric.
In the diagram of FIG. 1A, the drain side of the memory cell has been programmed, for example via band-to-band hole injection into the drain side of the charge trapping structure 130. The source side of the memory cell has been erased, for example via a channel reset operation injecting electrons via Fowler-Nordheim tunneling from the gate 110 to the charge trapping structure 130, and from the charge trapping structure 130 to the substrate 170.
In the bias arrangement of FIG. 1A for reading the source side of the charge trapping structure 130, the voltage of the gate 110 is −10 V, the voltage of the source 150 is 2 V, the voltage of the drain 160 is floating, and the voltage of the substrate 170 is 0 V. The memory cell of FIG. 1B is similar to memory cell of FIG. 1A, except that a read operation is being performed on the drain side of the charge trapping structure rather than on the source side. In the bias arrangement of FIG. 1B for reading the drain side of the charge trapping structure 130, the voltage of the gate 110 is −10 V, the voltage of the source 150 is floating, the voltage of the drain 160 is 2 V, and the voltage of the substrate 170 is 0 V. The bias arrangement is determined among the various terminals, such that the energy bands bend sufficiently to cause band-to-band current in the n+ doped source 150 (FIG. 1A) or the n+ doped drain 160 (FIG. 1B), but to keep the potential difference between the substrate 170 and the source 150 (FIG. 1A) or the drain 160 (FIG. 1B) low enough such that programming does not occur, as discussed in connection with FIG. 2A.
In this bias arrangements of FIGS. 1A and 1B, the area of the junction between the p doped substrate 170, and either the n+ doped source 150 or the n+ doped drain 160, and displays the behavior of a reverse biased p-n junction. However, the gate voltage causes the energy bands to bend sufficiently such that band-to-band tunneling occurs in the n+ doped source 150 (FIG. 1A) or the n+ doped drain 160 (FIG. 1B). The high doping concentration in the source 150 or the drain 160, the resulting high charge density of the space charge region, and the accompanying short length of the space charge region over which the voltage changes, contribute to the sharp energy band bending. Electrons in the valence band tunnel through the forbidden gap to the conduction band and drift down the potential hill, deeper into either the n+ doped source 150 (FIG. 1A) or the n+ doped drain 160 (FIG. 1B). Similarly, holes drift up the potential hill, away from either the n+ doped source 150 (FIG. 1A) or the n+ doped drain 160 (FIG. 1B), and toward the p doped substrate 170.
As mentioned above, the drain side of the charge trapping structure 130 is programmed and occupied by holes, whereas the source side of the charge trapping structure 130 is erased and occupied by fewer holes than the drain side of the charge trapping structure 130. As a result, in accordance with Gauss's Law, when −10 V is applied to the gate 110, the bottom dielectric structure 140 (bottom oxide) is biased more negatively on the source side than on the drain side. Thus, more current flows between the source 150 and the substrate 170 in the bias arrangement shown in FIG. 1A for reading the source side of the charge trapping structure 130 than flows between the drain 160 and the substrate 170 in the bias arrangement shown in FIG. 1B for reading the drain side of the charge trapping structure 130.
The difference in the bias arrangements of FIGS. 1A and 1B for reading, and the bias arrangement of FIG. 2A for programming, show a careful balance. For reading, the potential difference between the source region or the drain region should not cause a substantial number of carriers to transit the tunnel oxide and affect the charge storage state. In contrast, for programming, the potential difference between the source region or the drain region is sufficient to cause a substantial number of carriers to transit the tunnel oxide and affect the charge storage state.
FIGS. 2A, 2B, and 2C are simplified diagrams of a memory cell that show program and erase operations being performed on the memory cell. As generally used herein, programming refers to making more positive the net charge stored in the charge trapping structure, such as by the addition of holes to or the removal of electrons from the charge trapping. Also as generally used herein, erasing refers to making more negative the net charge stored in the charge trapping structure, such as by the removal of holes from or the addition of electrons to the charge trapping structure. However, the invention encompasses both products and methods where programming refers to making the net charge stored in the charge trapping structure more negative or more positive, and products and methods where erasing refers to making the net charge stored in the charge trapping structure more negative or more positive.
In FIG. 2A, programming is accomplished using band-to-band tunneling induced hot hole injection, and in FIGS. 2B and 2C, erasing is accomplished using the negative gate voltage, E-field induced electron tunneling (also known as Fowler-Nordheim tunneling) which causes tunneling current from the gate to the charge trapping structure, or by using the negative substrate voltage, E-field induced electron tunneling (also known as Fowler-Nordheim tunneling) which causes tunneling current from the substrate to the charge trapping structure. Thus, as illustrated in FIG. 2A, a right bit is programmed by applying 5 V to the drain 260, 0 V to the source 250, and −6 V to the gate 210, while the substrate 270 is grounded. This induces hot holes having sufficient energy to jump over the tunnel dielectric 240 into drain side 23 3 of the charge trapping structure 230, as shown by hole 234 which is stored in the drain side 233 of the charge trapping structure 230. Similarly, a left bit is programmed by applying 5 V to the source 250, 0 V to the drain 260, and −6 V to the gate 210, while the substrate 270 is grounded (not shown). This induces hot holes having sufficient energy to jump over the bottom dielectric structure 240 into the source side of the charge trapping structure 230. FIG. 2B illustrates E-field assisted electron tunneling across top dielectric structure 220 and bottom dielectric structure 240 used for erase, induced by relatively high negative bias on the gate, and relatively high positive bias on the substrate. Both bits in the memory cell are simultaneously erased in the illustrated example by applying −20 V to the gate, and grounding the substrate, while both the source and the drain are floating. FIG. 2C illustrates E-field assisted electron tunneling used for erase, induced by relatively high negative bias on the substrate, drain, and source; and relatively high positive bias on the gate. Both bits in the memory cell are simultaneously erased in the illustrated example by applying −20 V to the substrate, sources and drain; and grounding the gate. Other program and erase techniques can be used in operation algorithms applied to the PHINES type memory cell, as described for example in U.S. Pat. No. 6,690,601. Other memory cells and other operation algorithms might also be used.
FIGS. 3A and 3B are graphs that contrast the sensing windows of an ideal memory cell with the sensing window of a memory cell that is read by a reverse read operation. Curve 310 represents the read current of the first bit. Curve 320 represents the read current of the second bit. During time interval 330, the first bit is undergoing programming. During time interval 340, the second bit is undergoing programming. Due to the program operation (via hot hole injection), the current (channel current) will increase in a reverse read operation and the current (BTB current) will drop in a BTB sensing operation. The read current interval is represented by the sensing window 350 of the memory cell.
In FIG. 3A, the ideal memory cell has a relatively wide sensing window 350. During the time interval 330, as the first bit is undergoing programming, the read current curve of the first bit 310 increases from a lowest level to a highest level. The programming of the first bit during the time interval 330 does not substantially affect the read current curve of the second bit 320. During the time interval 340, as the second bit is undergoing programming, the read current curve of the second bit 320 increases from a lowest level to a highest level. The programming of the second bit during the time interval 340 does not substantially affect the read current curve of the first bit 310.
In FIG. 3B, the memory cell read by a reverse read operation has a relatively narrow sensing window 350 due to the second bit effect, as explained below. During the time interval 330, as the first bit is undergoing programming, the read current curve of the first bit 310 increases from a lowest level 360 to a high level 364. Consequently, the programming of the first bit during the time interval 330 substantially affects the read current curve of the second bit 320, which increases from a lowest level 360 to a low level 362. During the time interval 340, as the second bit is undergoing programming, the read current curve of the second bit 320 increases from a low level 362 to a highest level 366. Consequently, the programming of the second bit during the time interval 340 substantially affects the read current curve of the first bit 310, which increases from a high level 364 to a highest level 366. Thus, when performing a reverse read operation on a memory cell on one bit, the resulting read current is substantially affected by the programmed or erased status of the other bit, because for a given gate voltage it becomes more difficult during the reverse read operation to force the substrate portion under the other bit into depletion and inversion, and to punch through the portion of the substrate under the other bit.
FIGS. 4A, 4B, and 4C are graphs that show program, erase, and band-to-band read operations being performed on the memory cell.
In the graph of FIG. 4A, a memory cell with both first and second charge trapping parts in a programmed state are erased via E-field assisted electron tunneling, induced by relatively high negative bias on the gate, and relatively high positive bias on the substrate. Both charge trapping parts in the memory cell are simultaneously erased in the graph by applying −19.5 V to the gate, and grounding the substrate, while both the source and the drain are floating. For each data point, the read operation is performed by applying −10 V to the gate, 2 V to one of the drain or source depending on the portion of the charge trapping structure being read, floating the other terminal of the drain or source, and grounding the substrate. If the source side of the charge trapping structure is being read, then 2 V is applied to the source and the drain is floated. If the drain side of the charge trapping structure is being read, then 2 V is applied to the drain and the source is floated.
In the graph of FIG. 4B, the first charge trapping part undergoes programming, and in the graph of FIG. 4C, the second charge trapping part undergoes programming. Curve 410 represents the read current of the first charge trapping part. Curve 420 represents the read current of the second charge trapping part. In FIG. 4B, the first charge trapping part is programmed by applying −8V to the gate and 5 V to the first terminal (the terminal closer to the storing the first charge trapping part of the charge trapping structure), floating the second terminal (the terminal farther from the first charge trapping part of the charge trapping structure), and grounding the substrate. In FIG. 4B, as the first charge trapping part is undergoing programming, the read current curve of the first charge trapping part 410 drops from a highest level of about 100 nA to a lowest level of about 1 nA. The programming of the first charge trapping part does not substantially affect the read current curve of the second charge trapping part 420. In FIG. 4C, the second charge trapping part is programmed by applying −8V to the gate and 5 V to the second terminal (the terminal closer to the second charge trapping part of the charge trapping structure), floating the first terminal (the terminal farther from the second charge trapping part of the charge trapping structure storing), and grounding the substrate. In FIG. 4C, as the second charge trapping part is undergoing programming, the read current curve of the second charge trapping part 420 drops from a highest level of about 100 nA to a lowest level of about 1 nA. The programming of the second charge trapping part does not substantially affect the read current curve of the first charge trapping part 410. For each data point in FIGS. 4B and 4C, the read operation is performed by applying −10 V to the gate, 2 V to one of the drain or source depending on the portion of the charge trapping structure being read, floating the other terminal of the drain or source, and grounding the substrate. If the source side of the charge trapping structure is being read, then 2 V is applied to the source and the drain is floated. If the drain side of the charge trapping structure is being read, then 2 V is applied to the drain and the source is floated.
The sensing window shown in FIGS. 4B and 4C is relatively wide, because the band-to-band read operation is local to either the first terminal or the second terminal. The read current resulting from a band-to-band read operation performed on the first charge trapping part is relatively insensitive to the logical state of the second charge trapping part, and the read current resulting from a band-to-band read operation performed on the second charge trapping part is relatively insensitive to the logical state of the first charge trapping part. The band-to-band read operation is relatively free of the second charge trapping part effect which characterizes the reverse read operation, where the read current resulting from a read operation performed on one side of the charge trapping structure is relatively dependent on the data stored on the other side of the charge trapping structure. Each charge trapping part can store one bit or multiple bits. For example, if each charge trapping part stores two bits, then there are four discrete levels of charge.
FIGS. 5A and 5B are simplified diagrams of memory cell strings that show program operations being performed on the memory cell.
In FIG. 5A, one of the memory cells of the string of memory cells including N memory cells coupled in series is programmed. The voltage of the substrate 502 is 0 V. The gate of the memory cell 540 selected to be programmed has a voltage of −5 V. More specifically, one portion of the charge trapping structure 542 is selected to be programmed. The portion of the charge trapping structure to be programmed 542 is selected by applying a voltage of 10 V to the gate of the pass transistor 510, turning on the pass transistor 510. Further, a voltage of 10 V is applied to the gates of memory cells 520 and 530. These gate voltages electrically couple a first bit line 505 with a voltage of 5 V to one of the source/drain region of the selected memory cell 540. The selected portion of the charge trapping structure 542 corresponding to one of the source/drain region is programmed, for example via band-to-band hot hole programming. The remaining transistors in the string of memory cells are turned off by applying a voltage of 0 V to the gates of memory cells 550, 560, 570, and 580; and to the gate of the pass transistor 590. These gate voltages electrically decouple a second bit line 595 from the other of the source/drain region of the selected memory cell 540. The unselected portion of the charge trapping structure corresponding to the other of the source/drain region is not programmed.
In FIG. 5B, one of the memory cells of the string of memory cells including N memory cells coupled in series is programmed. However, a gate voltage of 0 V is applied to the gate of the pass transistor 510 and to the gates of the memory cells 520 and 530. Also, a gate voltage of 10 V is applied to the gate of the pass transistor 590 and to the gates of the memory cells 550, 560, 570, and 580. In contrast with the bias arrangement of FIG. 5A, where the bit line 505 is electrically coupled to one of the source or drain of the memory cell 540 to program the portion of the charge trapping structure 542, in the bias arrangement of FIG. 5B the bit line 595 is electrically coupled to the other of the source or drain of the memory cell 540 to program the portion of the charge trapping structure 544.
FIGS. 6A and 6B are simplified diagrams of memory cell strings that show read operations being performed on the memory cell.
In FIG. 6A, one of the memory cells of the string of memory cells including N memory cells coupled in series is read. The voltage of the substrate 602 is 0 V. The gate of the memory cell 640 selected to be read has a voltage of −10 V. More specifically, one portion of the charge trapping structure 642 is selected to be read. The portion of the charge trapping structure to be read 642 is selected by applying a voltage of 10 V to the gate of the pass transistor 610, turning on the pass transistor 610. Further, a voltage of 10 V is applied to the gates of memory cells 620 and 630. These gate voltages electrically couple a first bit line 605 with a voltage of 2 V to one of the source/drain region of the selected memory cell 640. The selected portion of the charge trapping structure 642 corresponding to one of the source/drain region is read for example via band-to-band current sensing. The remaining transistors in the string of memory cells are turned off by applying a voltage of 0 V to the gates of memory cells 650, 660, 670, and 680; and to the gate of the pass transistor 690. These gate voltages electrically decouple a second bit line 695 from the other of the source/drain region of the selected memory cell 640. The unselected portion of the charge trapping structure corresponding to the other of the source/drain region is not read.
In FIG. 6B, one of the memory cells of the string of memory cells including N memory cells coupled in series is programmed. However, a gate voltage of 0 V is applied to the gate of the pass transistor 610 and to the gates of the memory cells 620 and 630. Also, a gate voltage of 10 V is applied to the gate of the pass transistor 690 and to the gates of the memory cells 660, 660, 670, and 680. In contrast with the bias arrangement of FIG. 6A, where the first bit line 605 is electrically coupled to one of the source or drain of the memory cell 640 to read the portion of the charge trapping structure 642, in the bias arrangement of FIG. 6B the second bit line 695 is electrically coupled to the other of the source or drain of the memory cell 640 to read the portion of the charge trapping structure 644.
FIGS. 7A and 7B are simplified diagrams of memory cell strings that show erase operations being performed on the memory cells.
In FIG. 7A, all of the memory cells of the string of memory cells including N memory cells coupled in series are erased. The voltage of the substrate 702 is 10 V. The gates of the memory cells to be erased 720, 730, 740, 750, 760, 770, and 780 have a voltage of −10 V. The gates of pass transistors 710 and 790 are floating. The bit lines 705 and 795 are floating. The memory cells 720, 730, 740, 750, 760, 770, and 780 are erased, for example via FN tunneling of electrons from the gate to the charge trapping structure and from the charge trapping structure to the substrate.
In FIG. 7B, all of the memory cells of the string of memory cells including N memory cells coupled in series are erased. The voltage of the substrate 702 is −10 V. The gates of the memory cells to be erased 720, 730, 740, 750, 760, 770, and 780 have a voltage of 10 V. The voltage of the gates of pass transistors 710 and 790 is 5V. The voltage of bit lines 705 and 795 is −10V. The memory cells 720, 730, 740, 750, 760, 770, and 780 are erased, for example via FN tunneling of electrons from the substrate to the charge trapping structure and from the charge trapping structure to the gate.
In FIG. 8, each column of memory cells is electrically coupled to at most one bit line 804. Stated another way, the architecture in FIG. 8 differs from the architecture of FIG. 6 in that the first bit line 605 and the second bit line 695 are permanently electrically coupled. Memory cells in the column of memory cells are selected by turning on word lines which set the gate voltages of the memory cells 820, 830, 840, 850, 860, 870, and 880. An example of a way to control which portion of a given memory cell is read or programmed is by turning on one of pass transistors 810 and 890 and turning off the other of pass transistors 810 and 890. Although the pass transistors 810 and 890 shown in FIG. 8 are not memory cells, in other embodiments one or both pass transistors 810 and 890 are also memory cells with charge trapping structures.
In FIG. 9, an array of memory cells is erased, with multiple strings each including N memory cells coupled in series. The voltage of the substrate 902 is 10 V. The word lines of the memory cells to be erased 920, 930, 940, 950, 960, 970, and 980 have a voltage of −10 V. The word lines of pass transistors 910 and 990 have a voltage of 0 V. The bit lines 903, 904, 905, 906, and 907 are floating. The memory cells of the array are erased, for example via FN tunneling of electrons from the gate to the charge trapping structure and from the charge trapping structure to the substrate.
In FIG. 10, an array of memory cells is erased, with multiple strings each including N memory cells coupled in series. The voltage of the substrate 1002 is −10 V. The word lines of the memory cells to be erased 1020, 1030, 1040, 1050, 1060, 1070, and 1080 have a voltage of 10 V. The word lines of pass transistors 1010 and 1090 have a voltage of 5 V. The bit lines 1003, 1004, 1005, 1006, and 1007 have a voltage of −10 V. The memory cells of the array are erased, for example via FN tunneling of electrons from the substrate (including drain and source) to the charge trapping structure and from the charge trapping structure to the gate.
In FIG. 11, several memory cells are programmed in an array of memory cells with multiple strings each including N memory cells coupled in series. The voltage of the substrate 1102 is 0 V. The word line 1140 of the memory cells to be programmed has a voltage of −5 V. With the memory cells selected by the word line 1140, the charge trapping structure parts 1143, 1144, 1145, 1146, and 1147 are selected by turning on the pass transistor word line 1110 with a voltage of 10 V. The voltages of the intervening memory cell word lines 1120 and 1130 is set to 10 V. The other pass transistor word line 1190 and the remaining memory cell word lines 1150, 1160, 1170, and 1180 are turned off with a voltage of 0 V. Out of the selected charge trapping structure parts 1143, 1144, 1145, 1146, and 1147, the charge trapping structure parts 1144, 1146, and 1147 are programmed by setting the voltages of the bit lines 1104, 1106, and 1107 to 5 V. Out of the selected charge trapping structure parts 1143, 1144, 1145, 1146, and 1147, the charge trapping structure parts 1143 and 1145 are not programmed, by setting the voltages of the bit lines 1103 and 1105 to 0 V.
In FIG. 12, several memory cells are programmed similar to FIG. 11. The voltage of the substrate 1202 is 0 V. However, with the memory cells selected by the word line 1240, the charge trapping structure parts 1243, 1244, 1245, 1246, and 1247 are selected by turning on the pass transistor word line 1290 with a voltage of 10 V. The voltages of the intervening memory cell word lines 1250, 1260, 1270, and 1280 is set to 10 V. The other pass transistor word line 1210 and the remaining memory cell word lines 1220 and 1230 are turned off with a voltage of 0 V. Out of the selected charge trapping structure parts 1243, 1244, 1245, 1246, and 1247, the charge trapping structure parts 1244, 1246, and 1247 are programmed by setting the voltages of the bit lines 1204, 1206, and 1207 to 5 V. Out of the selected charge trapping structure parts 1243, 1244, 1245, 1246, and 1247, the charge trapping structure parts 1243 and 1245 are not programmed, by setting the voltages of the bit lines 1203 and 1205 to 0 V.
In FIG. 13, several memory cells are read in an array of memory cells with multiple strings each including N memory cells coupled in series. The voltage of the substrate 1302 is 0 V, The word line 1340 of the memory cells to be read has a voltage of −10 V. With the memory cells selected by the word line 1340, the charge trapping structure parts 1343, 1344, 1345, 1346, and 1347 are selected by turning on the pass transistor word line 1310 with a voltage of 10 V. The voltages of the intervening memory cell word lines 1320 and 1330 are set to 10 V. The other pass transistor word line 1390 and the remaining memory cell word lines 1350, 1360, 1370, and 1380 are turned off with a voltage of 0 V. The selected charge trapping structure parts 1343, 1344, 1345, 1346, and 1347, are read by setting the voltages of the bit lines 1303, 1304, 1305, 1306, and 1307 to 2 V. In other embodiments, a subset of all the bit lines are read by setting the voltages to 2 V for only the bit lines of interest.
In FIG. 14, several memory cells are read similar to FIG. 13. The voltage of the substrate 1402 is 0 V. However, with the memory cells selected by the word line 1440, the charge trapping structure parts 1443, 1444, 1445, 1446, and 1447 are selected by turning on the pass transistor word line 1490 with a voltage of 10 V. The voltages of the intervening memory cell word lines 1450, 1460, 1470, and 1480 are set to 10 V. The other pass transistor word line 1410 and the remaining memory cell word lines 1420 and 1430 are turned off with a voltage of 0 V. The selected charge trapping structure parts 1443, 1444, 1445, 1446, and 1447, are read by setting the voltages of the bit lines 1403, 1404, 1405, 1406, and 1407 to 2 V. In other embodiments, a subset of all the bit lines are read by setting the voltages to 2 V for only the bit lines of interest.
FIG. 15 is a simplified block diagram of all integrated circuit according to an embodiment. The integrated circuit 1550 includes a memory array 1500 implemented using charge trapping memory cells, on a semiconductor substrate. A row decoder 1501 is coupled to a plurality of word lines 1502 arranged along rows in the memory array 1500. A column decoder 1503 is coupled to a plurality of bit lines 1504 arranged along columns in the memory array 1500. Addresses are supplied on bus 1505 to column decoder 1503 and row decoder 1501. Sense amplifiers and data-in structures in block 1506 are coupled to the column decoder 1503 via data bus 1507. Data is supplied via the data-in line 1511 from input/output ports on the integrated circuit 1550, or from other data sources internal or external to the integrated circuit 1550, to the data-in structures in block 1506. Data is supplied via the data-out line 1515 from the sense amplifiers in block 1506 to input/output ports on the integrated circuit 1550, or to other data destinations internal or external to the integrated circuit 1550. A bias arrangement state machine 1509 controls the application of bias arrangement supply voltages 1508, such as for the erase verify and program verify voltages, and the arrangements for programming, erasing, and reading the memory cells, such as with the band-to-band currents.
applying a first bias arrangement to determine a charge storage state of the selected part of the charge trapping structure.
2. The method of claim 1, wherein the first bias arrangement applies a voltage difference between the substrate region and one of the source region or the drain region, and floats the other of the source region or the drain region.
3. The method of claim l, wherein the first bias arrangement causes a first voltage difference between the gate and the one of the source region or the drain region, and a second voltage difference between the substrate region and the one of the source and drain regions, wherein the first voltage difference and the second voltage difference cause sufficient band-to-band tunneling current for said determining, and the first voltage difference and the second voltage differences fail to change the charge storage state.
4. The method of claim 1, wherein the first bias arrangement causes a first voltage difference of at least about 5 V between the gate and the one of the source region or the drain region, and a second voltage difference less than about 5 V between the substrate region and the one of the source region or the drain region.
5. The method of claim 1, wherein the first bias arrangement induces at least a band-to-band current component through the one of the source region or the drain region.
6. The method of claim 1, wherein said first bias arrangement measures current flowing through the substrate region, and the one of the source region or the drain region.
7. The method of claim 1, wherein the substrate region is a well in a semiconductor substrate.
applying a third bias arrangement to adjust the charge storage state by increasing a net negative charge in the charge trapping structure.
applying a third bias arrangement to adjust the charge storage state by increasing a net negative charge in the charge trapping structure via Fowler-Nordheim tunneling.
applying a third bias arrangement to adjust the charge storage state by increasing a net negative charge in the charge trapping structure via channel hot electron injection current.
applying a third bias arrangement to adjust the charge storage state by increasing a net negative charge in the charge trapping structure via channel initiated secondary electron injection current.
applying a third bias arrangement to adjust the charge storage state by increasing a net negative charge in the charge trapping structure via electron movement between the charge trapping structure and the substrate region.
applying a third bias arrangement to adjust the charge storage state by increasing a net negative charge in the charge trapping structure via electron movement between the charge trapping structure and the gate.
wherein said first bias arrangement measures current of about 100 nA for the charge storage state adjusted by one of the second bias arrangement and the third bias arrangement, and about 1 nA for the charge storage state adjusted by the other of the second bias arrangement and the third bias arrangement.
wherein said first bias arrangement measures current at least about 10 times greater for the charge storage state adjusted by one of the second bias arrangement and the third bias arrangement than for the charge storage state adjusted by the other of the second bias arrangement and the third bias arrangement.
16. The method of claim 1, wherein the charge storage state of each part of the charge trapping structure stores one bit.
17. The method of claim 1, wherein the charge storage state of each part of the charge trapping structure stores multiple bits.
18. The method of claim 1, wherein hot holes generated during the first bias arrangement are insufficient to disturb the charge storage state.

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Application No. 60
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