Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Sub-banking and Partitioned cache architecture <s> Caches consume a significant amount of energy in modern microprocessors. To design an energy-efficient microprocessor, it is important to optimize cache energy consumption. This paper examines performance and power trade-offs in cache designs and the effectiveness of energy reduction for several novel cache design techniques targeted for low power. <s> BIB001 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Sub-banking and Partitioned cache architecture <s> In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible for 20-25% of the power consumed in the Icache. Reducing the power consumed by the cache controller is important for low power I-cache design. We present three architectural modi cations, which in concert, allow us to reduce the cache controller activity to less than 2% for most applications. The rst modi cation involves comparing cache tags for only those instructions that result in fetches from a new cache block. The second modi cation involves the tagging of those branches that cause instructions to be fetched from a new cache block. The third modi cation involves augmenting the I-cache with a small on-chip memory called the S-cache. The most frequently executed basic blocks of code are statically allocated to the S-cache before program execution. We present empirical data to show the e ect that these modi cations have on the cache con- <s> BIB002 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Sub-banking and Partitioned cache architecture <s> This paper proposes a new approach using way prediction for achieving high performance and low energy consumption of set-associative caches. By accessing only a single cache way predicted, instead of accessing all the ways in a set, the energy consumption can be reduced. This paper shows that the way-predicting set-associative cache improves the ED (energy-delay) product by 60-70% compared to a conventional set-associative cache,. <s> BIB003 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Sub-banking and Partitioned cache architecture <s> The demand for high-performance architectures and powerful battery-operated mobile devices has accentuated the need for low-power systems. In many media and embedded applications, the memory system can consume more than 50p of the overall system energy, making it a ripe candidate for optimization. To address this increasingly important problem, this article studies energy-efficient cache architectures in the memory hierarchy that can have a significant impact on the overall system energy consumption.Existing cache optimization approaches have looked at partitioning the caches at the circuit level and enabling/disabling these cache partitions (subbanks) at the architectural level for both performance and energy. In contrast, this article focuses on partitioning the cache resources architecturally for energy and energy-delay optimizations. Specifically, we investigate ways of splitting the cache into several smaller units, each of which is a cache by itself (called a subcache). Subcache architectures not only reduce the per-access energy costs, but can potentially improve the locality behavior as well.The proposed subcache architecture employs a page-based placement strategy, a dynamic page remapping policy, and a subcache prediction policy in order to improve the memory system energy behavior, especially on-chip cache energy. Using applications from the SPECjvm98 and SPEC CPU2000 benchmarks, the proposed subcache architecture is shown to be very effective in improving both the energy and energy-delay metrics. It is more beneficial in larger caches as well. <s> BIB004 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Sub-banking and Partitioned cache architecture <s> Tag comparison elimination (TCE) is an effective approach to reduce I-cache energy. Current research focuses on finding good tradeoffs between hardware cost and percentage of comparisons that can be removed. For this purpose, two low cost innovations are proposed in this paper. We design a small dedicated TCE table whose size is flexible both horizontally (entry size) and vertically (number of entries). The design also minimizes interactions with the I-cache. For a 64-way 16K cache, the new design reduces the tag comparisons to 4.0% with a fraction only 20% of the hardware cost of the way memoization technique [5]. The result is 40% better compared to a recent proposed low cost design [2] of comparable hardware cost. <s> BIB005 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Sub-banking and Partitioned cache architecture <s> Caches contribute to much of a microprocessor system's power and energy consumption. We have developed a new cache architecture, called a way-halting cache, that reduces energy while imposing no performance overhead. Our way-halting cache is a four-way set-associative cache that stores the four lowest-order bits of all ways' tags into a fully associative memory, which we call the halt tag array. The lookup in the halt tag array is done in parallel with, and is no slower than, the set-index decoding. The halt tag array pre-determines which tags cannot match due to their low-order four bits mismatching. Further accesses to ways with known mismatching tags are then halted, thus saving power. Our halt tag array has an additional feature of using static logic only, rather than dynamic logic used in highly associative caches. We provide data from experiments on 17 benchmarks drawn from MediaBench and Spec 2000, based on our layouts in 0.18 micron CMOS technology. On average, 55% savings of memory-access related energy were obtained over a conventional four-way set-associative cache. We show that energy savings are greater than previous methods, and nearly twice that of highly-associative caches, while imposing no performance overhead and only 2% cache area overhead. <s> BIB006 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Sub-banking and Partitioned cache architecture <s> Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal partitioning reduces average power per data access by employing multiple smaller structures or using cache subbanks. For instance, region-based caching places small caches dedicated to stack and global accesses next to the L1 data cache. With respect to static power dissipation, leakage power may be addressed at both circuit and architectural levels. Drowsy caches reduce leakage power by keeping inactive lines in a low-power mode. Here we merge drowsy and region-based caching to reduce overall cache power consumption, showing that the combination yields more benefits than either alone. Applications from the MiBench suite exhibit power reductions in the cache system of up to 68-71%, depending on memory configuration, with a small increase in execution time <s> BIB007 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Sub-banking and Partitioned cache architecture <s> This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The non-uniform cache allows having different associativity values (i.e., the number of cache-ways) for different cache-sets. An algorithm determines the optimum number of cache-ways for each cache-set and generates object code suitable for the non-uniform cache memory. The paper also proposes a compiler technique for reducing redundant cache-way accesses and cache-tag accesses. Experiments demonstrate that the technique can reduce the power consumption of memory systems by up to 76% compared to the best result achieved by the conventional method. <s> BIB008 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Sub-banking and Partitioned cache architecture <s> In this paper we present a novel cache architecture for energy-efficient data caches in embedded processors with virtual memory. Application knowledge regarding the nature of memory references is used to eliminate tag address translations for most of the cache accesses. We introduce a novel cache tagging scheme, where both virtual and physical tags co-exist in the cache tag arrays. Physical tags and special handling for the super-set cache index bits are used for references to shared data regions in order to avoid cache consistency problems. By eliminating the need for address translation on cache access for the majority of references, a significant power reduction is achieved. We outline an efficient hardware architecture for the proposed approach, where the application information is captured in a reprogrammable way and the cache architecture is minimally modified. Our experimental results show energy reductions for the address translation hardware in the range of 90%, while the reduction for the entire cache architecture is within the range of 25%-30%. <s> BIB009 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Sub-banking and Partitioned cache architecture <s> In most processors, caches account for the largest fraction of onchip transistors, thus being a primary candidate for tackling the leakage problem. Existing architectural solutions usually rely on customized cache structures, which are needed to implement some kind of power management policy. Memory arrays, however, are carefully developed and finely tuned by foundries, and their internal structure is typically non accessible to system designers. In this work, we focus on the reduction of leakage energy in caches, without interfering with its internal design. We proposed a truly architectural solution that is based on cache sub-banking and on the detection and mapping of the application localities, detected from a profiling of the cache access patterns. By customizing the mapping between the application address space and the cache, we can expose as much address space idleness as possible, thus resulting in shutdown potential which allows significant leakage saving. Results show leakage energy reduction of up to 48% (about 30% on average), with marginal impact on miss rate or execution time. <s> BIB010 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Sub-banking and Partitioned cache architecture <s> As we embrace the world of personal, portable, and perplexingly complex digital systems, it has befallen upon the bewildered designer to take advantage of the available transistors to produce a system which is small, fast, cheap and correct, yet possesses increased functionality. Increasingly, these systems have to consume little energy. Designers are increasingly turning towards small processors, which are low power, and customize these processors both in software and hardware to achieve their objectives of a low power system, which is verified, and has short design turnaround times. Designing Embedded Processorsexamines the many ways in which processor based systems are designed to allow low power devices. It looks at processor design methods, memory optimization, dynamic voltage scaling methods, compiler methods, and multi processor methods. Each section has an introductory chapter to give a breadth view, and have a few specialist chapters in the area to give a deeper perspective. The book provides a good starting point to engineers in the area, and to research students embarking upon the exciting area of embedded systems and architectures. <s> BIB011
As feature sizes shrink, leakage power constitutes an increasing fraction of total processor power BIB007 . This affects cache structures disproportionately, since they have large area requirements. Subdividing the memory into smaller memories is one of the mechanisms used to reduce the effective length of the bit lines driven during memory operations, thereby reducing power dissipation BIB011 . In BIB004 the authors show a way to split the cache into several smaller units, each of which is a cache by itself. These so-called Subcache architectures not only reduce the per-access energy costs, but can potentially improve the locality behavior as well. Various paradigms for memory partitioning are discussed by Golubeva et al. BIB010 . One such paradigm is to define portions of a cache of suitable granularity (e.g., a cache line, a way, a bank); second, they put unused portions into a low-leakage state, based on their idleness. Another scheme proposed is to build a multi-bank cache architecture, rather than a single cache internally consisting of multiple banks. A basic structure for subbanking BIB001 is presented in Fig. 5 . Su et al. BIB001 explain various partitioning schemes for cache. Vertical partitioning is identical to buffering which is discussed in "Adding Buffers" section. Horizontal partitioning saves power by eliminating unnecessary access to caches (sub-banking techniques). Gray code addressing takes the advantage of the spatial locality of sequential memory address. Since address buses poses a challenge for power optimization gray code addressing tries to reduce the bit switching activities for the same number of cache hits. Reading and comparing the tags in the tag arrays consumes also significant power. For highly associative caches, the power consumption is a particular concern since large number of tag comparisons are carried out in parallel BIB005 . Tag comparison elimination (TCE) techniques have been proposed to remove unnecessary tag comparisons to achieve power reduction. A tag comparison is considered unnecessary if a match or a mismatch can be determined without a real comparison. The decision is made based on the runtime information that is maintained in low cost hardware. A fundamental cache design trade-off is between a direct-mapped cache and set-associative cache. A conventional direct mapped cache accesses only one tag array and one data array per cache access, whereas a conventional four-way set-associative cache accesses four tags arrays and four data arrays per cache access BIB006 . Inoue et al. BIB003 use way prediction for achieving high performance and low energy consumption of setassociative caches. It improves the energy delay product by 60-70% compared to a conventional set associative cache. The scheme speculatively predicts the cache way using the MRU (Most Recently Used) algorithm. If it is a cache hit there is a significant energy saving but if it is a prediction miss, the cache-access time of the waypredicting cache increases. Panwar et al. BIB002 propose three modifications to reduce the tag comparison frequency. The first modification involves comparing cache tags for only those instructions that result in fetches from a new cache block. The second modification involves the tagging of those branches that cause instructions to be fetched from a new cache block. The third modification involves augmenting the I-cache with a small on-chip memory called the S-cache. The most frequently executed basic blocks of code are statically allocated to the S-cache before program execution. A non uniform cache architecture BIB008 is wherein an algorithm determines the optimum number of cache-ways for each cache-set and generates object code suitable for the non-uniform cache memory. A novel cache tagging scheme was introduced by Zhou et al. BIB009 , where both virtual and physical tags co-exist in the cache tag arrays. Physical tags and special handling for the super-set cache index bits are used for references to shared data regions in order to avoid cache consistency problems. By eliminating the need for address translation on cache access for the majority of references, a significant power reduction is achieved.