Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> This paper describes the development of a high-density electronic interface to the central nervous system. Silicon micromachined electrode arrays now permit the long-term monitoring of neural activity in vivo as well as the insertion of electronic signals into neural networks at the cellular level. Efforts to understand and engineer the biology of the implant/tissue interface are also underway. These electrode arrays are facilitating significant advances in our understanding of the nervous system, and merged with on-chip circuitry, signal processing, microfluidics, and wireless interfaces, they are forming the basis for a family of neural prostheses for the possible treatment of disorders such as blindness, deafness, paralysis, severe epilepsy, and Parkinson's disease. <s> BIB001 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> In the design of brain-machine interface (BMI) algorithms, the activity of hundreds of chronically recorded neurons is used to reconstruct a variety of kinematic variables. A significant problem introduced with the use of neural ensemble inputs for model building is the explosion in the number of free parameters. Large models not only affect model generalization but also put a computational burden on computing an optimal solution especially when the goal is to implement the BMI in low-power, portable hardware. In this paper, three methods are presented to quantitatively rate the importance of neurons in neural to motor mapping, using single neuron correlation analysis, sensitivity analysis through a vector linear model, and a model-independent cellular directional tuning analysis for comparisons purpose. Although, the rankings are not identical, up to sixty percent of the top 10 ranking cells were in common. This set can then be used to determine a reduced-order model whose performance is similar to that of the ensemble. It is further shown that by pruning the initial ensemble neural input with the ranked importance of cells, a reduced sets of cells (between 40 and 80, depending upon the methods) can be found that exceed the BMI performance levels of the full ensemble. <s> BIB002 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> A 256-site, fully implantable, 3-D neural recording microsystem has been developed. The microsystem incorporates four active neural probes with integrated circuitry for site selection, amplification, and multiplexing. The probes drive an embedded data-compression ASIC that successfully detects neural spikes in the presence of neural and circuit noise. The spike detection ASIC achieves a factor of 12 bandwidth reduction while preserving the key features of the action potential waveshape necessary for spike discrimination. This work extends the total number of neural channels that can be recorded across a transcutaneous inductively coupled wireless link from 25 to 312. When a spike is detected, this ASIC serially shifts the 5-bit amplitude and 5-bit address of the spike off of the chip over a single 2.5 Mb/s wired or wireless line. The spike detection ASIC occupies 6 mm/sup 2/ in 0.5 /spl mu/m features and consumes 2.6 mW while the entire microsystem consumes 5.4 mW of power from a 3-V supply. <s> BIB003 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> An implantable neural recording front-end has been designed in two versions. The first is a multi-channel signal- conditioning ASIC for use with any neural recording probe technology. This ASIC was implemented in a commercial 0.5μm CMOS process, includes 16 parallel amplifier channels, and measures 2.3mm 2 . The amplifiers have a gain of 59.5dB, a high cutoff frequency at 9.1kHz and consume 75μW per channel. The low cutoff frequency is independently tunable on each channel to accept or reject field potentials. This chip is small enough to be chronically packaged for experiments in awake behaving animals or it can be integrated into a fully implantable neural recording microsystem. The second version of the front-end is a neural recording probe with integrated signal conditioning circuitry on the back-end implemented in a 3μm CMOS process. This version dissipates 142μW and includes 64 to 8 site selection, 8 per-channel amplifiers each having a gain of 50.2dB, a tunable low cutoff frequency, and a 7kHz upper cutoff frequency. Real-time site impedance and circuit testing has been integrated in this design. Keywords—Neural recording amplifiers, neural probes, neural prosthetics, microsystems <s> BIB004 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> Electrically active cells in the body produce a wide variety of voltage signals that are useful for medical diagnosis and scientific investigation. These biopotentials span a wide range of amplitudes and frequencies. We have developed a versatile front-end integrated circuit that can be used to amplify many types of bioelectrical signals. The 0.6-mum CMOS chip contains 16 fully-differential amplifiers with gains of 46 dB, 2mu Vrms input-referred noise, and bandwidths programmable from 10 Hz to 10 kHz. <s> BIB005 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson's disease, epilepsy, prosthetics for the blind, and experimental neuroscience systems. The circuits include a micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays; an analog linear decoding and learning architecture for data compression; low-power radio-frequency (RF) impedance-modulation circuits for data telemetry that minimize power consumption of implanted systems in the body; a wireless link for efficient power transfer; mixed-signal system integration for efficiency, robustness, and programmability; and circuits for wireless stimulation of neurons with power-conserving sleep modes and awake modes. Experimental results from chips that have stimulated and recorded from neurons in the zebra finch brain and results from RF power-link, RF data-link, electrode-recording and electrode-stimulating systems are presented. Simulations of analog learning circuits that have successfully decoded prerecorded neural signals from a monkey brain are also presented. <s> BIB006 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> Electrical stimulation of nerve tissue and recording of neural electrical activity are the basis of emerging prostheses and treatments for spinal cord injury, stroke, sensory deficits, and neurological disorders. An understanding of the electrochemical mechanisms underlying the behavior of neural stimulation and recording electrodes is important for the development of chronically implanted devices, particularly those employing large numbers of microelectrodes. For stimulation, materials that support charge injection by capacitive and faradaic mechanisms are available. These include titanium nitride, platinum, and iridium oxide, each with certain advantages and limitations. The use of charge-balanced waveforms and maximum electrochemical potential excursions as criteria for reversible charge injection with these electrode materials are described and critiqued. Techniques for characterizing electrochemical properties relevant to stimulation and recording are described with examples of differences in the in vitro and in vivo response of electrodes. <s> BIB007 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> This paper presents a low-voltage low-power 16-channel interface chip dedicated for implantable neural signal recording. It consists of 16 front-end channels with tunable band-pass filtering and gain settings, multiplexed to a 10-bit SAR ADC for simultaneous recording. To comply with the implantation safety issue while maintaining comparable performance, the overall system is optimized to achieve low power dissipation and efficient power distribution among each individual blocks. A power efficient OTA topology is adopted in the front-end amplifier and a novel dual-capacitive-array SAR ADC is chosen to achieve better power efficiency. A prototype fabricated in a 0.35-µm CMOS technology achieves a NEF of 2.16 and THD of 0.53% at full output swing while providing output data rate of 16 kS/s per channel. The interface consumes 60.3-µW total power from a 1-V supply. <s> BIB008 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> This paper reports a 128-channel neural recording integrated circuit (IC) with on-the-fly spike feature extraction and wireless telemetry. The chip consists of eight 16-channel front-end recording blocks, spike detection and feature extraction digital signal processor (DSP), ultra wideband (UWB) transmitter, and on-chip bias generators. Each recording channel has amplifiers with programmable gain and bandwidth to accommodate different types of biological signals. An analog-to-digital converter (ADC) shared by 16 amplifiers through time-multiplexing results in a balanced trade-off between the power consumption and chip area. A nonlinear energy operator (NEO) based spike detector is implemented for identifying spikes, which are further processed by a digital frequency-shaping filter. The computationally efficient spike detection and feature extraction algorithms attribute to an auspicious DSP implementation on-chip. UWB telemetry is designed to wirelessly transfer raw data from 128 recording channels at a data rate of 90 Mbit/s. The chip is realized in 0.35 mum complementary metal-oxide-semiconductor (CMOS) process with an area of 8.8 times 7.2 mm2 and consumes 6 mW by employing a sequential turn-on architecture that selectively powers off idle analog circuit blocks. The chip has been tested for electrical specifications and verified in an ex vivo biological environment. <s> BIB009 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> We present an inductively powered 32-channel wireless integrated neural recording (WINeR) system-on-a-chip (SoC) to be ultimately used for one or more small freely behaving animals. The inductive powering is intended to relieve the animals from carrying bulky batteries used in other wireless systems, and enables long recording sessions. The WINeR system uses time-division multiplexing along with a novel power scheduling method that reduces the current in unused low-noise amplifiers (LNAs) to cut the total SoC power consumption. In addition, an on-chip high-efficiency active rectifier with optimized coils help improve the overall system power efficiency, which is controlled in a closed loop to supply stable power to the WINeR regardless of the coil displacements. The WINeR SoC has been implemented in a 0.5-μ m standard complementary metal-oxide semiconductor process, measuring 4.9×3.3 mm2 and consuming 5.85 mW at ±1.5 V when 12 out of 32 LNAs are active at any time by power scheduling. Measured input-referred noise for the entire system, including the receiver located at 1.2 m, is 4.95 μVrms in the 1 Hz~10 kHz range when the system is inductively powered with 7-cm separation between aligned coils. <s> BIB010 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> We report an analog front-end prototype designed for integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. The front-end features an extremely low power consumption (4µW/channel), optimized energy efficiency using moderate inversion in low-noise amplifier (K LNA of 5.98×108 and NEF of 2.9) and programmable-gain amplifier, a minimized asynchronous interface (only 2 per 16 channels) for command and data capturing, a power-scalable sampling and digital operation (up to 50kS/s/channel), and a wide configuration range (9-bit) of gain and bandwidth. The implemented front-end module has achieved a reduction in noise-power-area by a factor of 5–25 times as compared to the-state-of-the-art front-ends reported up to date. <s> BIB011 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology, which utilizes a differential pair input stage. The proposed architecture, which is referred to as a partial operational transconductance amplifier sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of mismatch on crosstalk between channels and the tradeoff between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a -3-dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at 3.5 μVrms and the power consumption is 7.92 μW from a 1.8-V supply, which corresponds to NEF = 3.35. The worst-case crosstalk and common-mode rejection ratio within the desired bandwidth are - 43.5 dB and 70.1 dB, respectively, and the active silicon area of each amplifier is 256 μm × 256 μm in 0.18-μm complementary metal-oxide semiconductor technology. <s> BIB012 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> Chronic recording of neural signals is indispensable in designing efficient brain-machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode-neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal-oxide-semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 μA, modulating input referred noise from 9.92 μV to 3.9 μV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems. <s> BIB013 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> We report the design of an ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology. The chip consists of eight neural recording modules where each module contains four neural amplifiers, an analog multiplexer, an A/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to adjust each amplifier's input-referred noise to suit the background noise at the recording site. The amplifier's input-referred noise can be adjusted from 11.2 μVrms (total power of 5.4 μW) down to 5.4 μVrms (total power of 20 μW) in the spike-recording setting. The ADC in each recording module digitizes the a.c. signal input to each amplifier at 8-bit precision with a sampling rate of 31.25 kS/s per channel, with an average power consumption of 483 nW per channel, and, because of a.c. coupling, allows d.c. operation over a wide dynamic range. It achieves an ENOB of 7.65, resulting in a net efficiency of 77 fJ/State, making it one of the most energy-efficient designs for neural recording applications. The presented chip was successfully tested in an in vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 μ W. The neural amplifier and the ADC occupy areas of 0.03 mm2 and 0.02 mm2 respectively, making our design simultaneously area efficient and power efficient, thus enabling scaling to high channel-count systems. <s> BIB014 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> This paper describes a inductively powered multichannel bionic neural link (BNL) system-on-chip (SOC) for peripheral nerve function restoration. The BNL-SOC consists of 8 neural recording and 4 stimulation channels, and is implemented in a 0.35-μm CMOS technology. Full function of the BNL has been demonstrated with in-vivo animal experiments. The entire BNL SOC consumes 1.5mW and operates under a 3V supply with an external +/-9V multichannel stimulation output driver. <s> BIB015 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> An ultra wideband (UWB) 64-channel responsive neural stimulator system-on-chip (SoC) is presented. It demonstrates the first on-chip neural vector analyzer capable of wirelessly monitoring magnitude, phase and phase synchronization of neural signals. In a closed-loop, abnormal phase synchrony triggers the programmable-waveform biphasic current-mode neural stimulator. To implement these functionalities, the SoC integrates 64 neural recording amplifiers with tunable switched-capacitor (SC) bandpass filters, 64 multiplying 8-bit SAR ADCs, 64 programmable 16-tap FIR filters, a tri-core CORDIC processor, 64 biphasic current stimulation channels, and a 3.1-10.6 GHz UWB wireless transmitter onto a 4 mm × 3 mm 0.13 μm CMOS die. To minimize both the area and power dissipation of the SoC, the SAR ADC is re-used as a multiplier for FIR filtering and as a DAC and duty cycle controller for the biphasic neural stimulator. The SoC has been validated in the early detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line. <s> BIB016 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems. <s> BIB017 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Design strategies to minimize power consumption <s> Neural probes have become the most important tool for enabling neuroscientists to place microelectrode sensors close to individual neurons and to monitor their activity in vivo. With such devices, it is possible to perform acute or chronic extracellular recordings of electrical activity from a single neuron or from groups of neurons. After the many developments in neural implants, it has become clear that large arrays of electrodes are desirable to further investigate the activity performed by complex neural networks. Therefore, in this paper, we propose a CMOS neural probe containing 455 active electrodes in the probe shank (100 μm wide, 10 mm long, and 50 μm thick) and 52 simultaneous readout channels in the probe body (2.9 × 3.3 mm2). In situ amplification under each electrode enables low-impedance interconnection lines, regardless of the electrode impedance, with a residual crosstalk of -44.8 dB. This design has been implemented in a 0.18-μm standard CMOS technology, with additional CMOS-compatible post-processing performed at wafer level to define the electrodes and the probe outline. In this architecture, the analog front-end achieves an input-referred noise of 3.2 μVrms and an NEF of 3.08. The power consumption of the core circuit is 949.8 μW, while the total power consumption is 1.45 mW. The high-density active-electrode array in this neural probe allows for the massive recording of neural activity. In vivo measurements demonstrate successful simultaneous recordings from many individual cells. <s> BIB018
Decreasing the total power consumption for the system depicted in Fig. 3 can be accomplished at the systems level or at the component level. Here, we describe three systemlevel techniques commonly used to minimize the power consumed by a neural recording system. The first strategy is resource sharing. The second strategy is power scheduling. The final strategy is power supply voltage reduction. The first widely used technique consists of multiplexing a high-density electrode array to a much smaller amplifier array. This strategy leverages the fact that not all electrode sites may provide useful information after implantation BIB003 BIB004 BIB001 or that the necessary information can be obtained from a small subset of electrodes, although the useful electrode subset is not known a priori BIB002 . For example, Al-ashmouny et al. reported a 128-input channel neural recording IC BIB011 with only 16 inputs selectively routed to the front-end amplifiers, therefore achieving power and area reduction. Another recent work by Lopez et al. BIB018 adopted the same method and multiplexed 455 electrode inputs to 52 amplifiers. A closely related technique involves the sharing of power-and area-consuming components within the system. For example, it is common for multiple amplifier channels to share a single ADC or output driver in a time-multiplexed sequence BIB016 BIB005 BIB008 BIB015 . Chae et al. BIB009 described a method to minimize the power-area product of a neural recording system though the proper selection of the number of channels that share a single ADC. A recent work by Majidzadeh et al. BIB012 demonstrated how to share the reference branch of one front-end amplifier among multiple channels. However, this technique cannot be scaled beyond 4 channels due to inter-channel crosstalk. Power scheduling involves modulating the supply current of individual amplifier channels to reduce the overall power consumption. For example, in BIB010 BIB017 , when channels were not sampled by the ADC, they were put into a sleep mode where the channel's power consumption was maintained at a level to minimize the wake-up time. Further, the electrode's background noise power can vary from site to site due to both the material properties of the electrode and the activities of non-isolated neurons BIB007 . Therefore, another power-scheduling method is to adapt the current consumption of each amplifier channel according to the background noise present at the respective electrode BIB013 BIB006 BIB014 . For an electrode site that has higher input noise, the power consumption of the corresponding frontend amplifier can be reduced, and vice versa. Finally, reducing the supply voltage of the entire chip or individual subsystems can be a very effective method to reduce power. For example, the IC neural amplifier reported by Wattanapanitch and Sarpeshkar BIB014 was partitioned into two separate voltage domains. The frontend amplifiers operated at 1.8 V, while the supply voltage of the ADC and the backend digital blocks were reduced to 1 V to decrease the dynamic switching power. Similarly, Al-ashmouny et al. BIB011 reported an implementation where the supply voltage of the ADC was made scalable according to the sampling rate, throttling the power consumption. Finally, the chip reported by Han et al.  used 0.9 and 0.45 V supply domains for the amplification stage and ADC, respectively. A dynamic voltage folding circuit then remapped the large output swing of the amplifiers to fit the limited input swing of the ADC.