A Survey of Swarm Intelligence Techniques in VLSI Routing Problems <s> E. APPLICATION OF FA 1) APPLYING FA TO GLOBAL ROUTING <s> The performance of very large scale integration (VLSI) circuits is depends on the interconnected routing in the circuits. In VLSI routing, wire sizing, buffer sizing, and buffer insertion are techniques to improve power dissipation, area usage, noise, crosstalk, and time delay. Without considering buffer insertion, the shortest path in routing is assumed having the minimum delay and better performance. However, the interconnect delay can be further improved if buffers are inserted at proper locations along the routing path. Hence, this paper proposes a heuristic technique to simultaneously find the optimal routing path and buffer location for minimal interconnect delay in VLSI based on particle swarm optimization (PSO). PSO is a robust stochastic optimization technique based on the movement and information sharing of swarms. In this study, location of doglegs is employed to model the particles that represent the routing solutions in VLSI. The proposed approach has a good potential in VLSI routing and can be further extended in future <s> BIB001 </s> A Survey of Swarm Intelligence Techniques in VLSI Routing Problems <s> E. APPLICATION OF FA 1) APPLYING FA TO GLOBAL ROUTING <s> Many studies had been conducted in improving the performance of large scale integration circuits that heavily depends on the interconnected routing in the circuits. Strategic choice of wire placement and buffer placement for very large scale integration (VLSI) routing can improve time delay of VLSI circuit. This paper explores the use of Firefly Algorithm in VLSI routing. The location of doglegs is employed to model the firefly that represents the routing solution. The proposed approach is then compared with previous literature for benchmarking. The result indicates that it has a good potential in VLSI routing and can be further extended in future. <s> BIB002
Nasir et al. BIB002 applied FA on VLSI routing to find the minimum time delay by choosing the path and placing the buffers intelligently. The proposed algorithm employs the location of doglegs to model the firefly that represents the routing solution. Like the previous model of using PSO to solve routing problem BIB001 , in this work, a distributed RC network is still used as interconnected model and the Elmore Delay formulation is applied to compute the interconnect delay from source to sink. And the same grid-graph model, as shown in Figure 8 (a) and 8(b) , is used to represent the areas that are possible for routing path and information about obstacles and buffers. In the model of Figure 9 , each firefly represents a candidate solution of the problem. Similar to the particle swarm, the position of each firefly in FA is also a seven-vector from e 1 to e 7 . Thus the general representation of the firefly in VLSI routing problem as follows: