A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Online Testing and Reconfiguration <s> Programmable logic arrays (PLA), which can implement arbitrary logic functions in a two-level logic form, are promising as platforms for nanoelectronic logic due to their highly regular structure compatible with the nano crossbar architectures. Reliability is an important challenge as far as nanoelectronic devices are concerned. Consequently, it is necessary to focus on the fault tolerance aspects of nanoelectronic PLAs to ensure their viability as a foundation for nanoelectronic systems. In this paper, we investigate two types of fault tolerance techniques for nanoelectronic device based PLAs, focusing at the online faults occurring at the cross-points of nano devices. We develop a scheme to precisely locate the faults online, as this is a crucial step for efficient online reconfiguration based fault tolerance schemes. We also propose a tautology based fault masking scheme. We demonstrate that these two types of fault tolerance schemes developed for nano PLAs significantly improve at low hardware cost the reliability of the high fault occurrence nanoelectronic environment. <s> BIB001 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Online Testing and Reconfiguration <s> Fault-tolerance is one of the major challenges facing nanoelectronic systems. Previous defect-tolerance techniques have focused on offline testing and are ill-suited for handling device death. We propose a fault-tolerance scheme for nanoelectronic PLAs that is based on checkpointing. With low overhead, our scheme is able to test and diagnose crosspoint faults that may appear in the PLA during its operational lifetime.We also present a new test vector compaction algorithm that significantly reduces the number of test vectors. This new algorithm takes advantage of the density and reconfigurability of nanoelectronic circuits by raising the granularity of defect diagnosis to the row/column level. We are therefore able to reduce the number of test vectors to O(n+p) for a PLA with n input and p product lines without sacrificing diagnosability. Experimental results show that our checkpointing scheme, together with the compaction algorithm, tolerates a much higher fault rate than previously possible. <s> BIB002 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Online Testing and Reconfiguration <s> Crossbar nano-architectures based on self-assembled nano-structures are promising alternatives for current CMOS technology, which is facing serious challenges for further down-scaling. One of the major challenges in this nanotechnology is elevated failure rate due to atomic device sizes and inherent lack of control in self-assembly fabrication. Therefore, high permanent and transient failure rates lead to multiple faults during lifetime operation of crossbar nano architectures. In this paper, we present a concurrent multiple error detection scheme for multistage crossbar nano-architectures based on dual-rail implementations of logic functions. We prove the detectability of all single faults as well as most classes of multiple faults in this scheme. Based on statistical multiple fault injection, we compare the proposed technique with other online error detection and masking techniques such as Triple Module Redundancy (TMR), duplication, and parity checking, in terms of fault coverage as well as area and delay overhead. <s> BIB003
Constructed mainly on conventional fault detection and correction techniques, fault-tolerance schemes using testing and reconfiguration are proposed in BIB001 , BIB002 , and BIB003 . In BIB001 , a straightforward diagnostics technique is introduced with pattern RAMs that hold the correct output values of the mapped logic function. Therefore it is an easy task to determine erroneous results by checking input, product, and output vectors. One RAM for each AND and OR plane is integrated to a nano-crossbar. After locating the faults, reconfiguration process is assumed to be performed. In BIB002 , a checkpoint-based fault-tolerance offering reconfigurability is proposed. Online test is performed to a group of PLA blocks with choosing two of them as surrogates. Every block is checked in a round-table manner and if no fault is detected, a safe checkpoint is identified. To determine faults, row-and column-based diagnostic test vectors are designed. Starting with row based diagnostics, S type faults (previously explained in Table 13 ) can be found by setting all of the inputs or variables of the corresponding product to 1, and the rest of the inputs to 0 to make all of the products except the corresponding one being 0. In case of having a 1−→ 0 error, we can conclude that an S type fault occurs in the product. Since D type faults show the same 1−→ 0 error characteristics that is also applicable to detect A type faults by using duality, we can say that row-based diagnostics cover all types of faults except G types. Column-based diagnostics is proposed to locate G type faults. However, it is not possible to locate all G type faults with a single row test vector. For this reason a compaction algorithm is used to optimize the number of test vectors by finding products sharing most variables. In BIB003 , a dual rail implementation is proposed as an online test of detection. Both a logic function f and its negation ¬f are realized in an AND plane and outputs are received using an OR plane. Since f and ¬f always have opposite values, it is possible to detect faults by comparing the two values. The area overhead in comparison with 3-modular redundancy, 5-modular redundancy, parity, and duplication methods are favorably given regarding I, O, and P parameters defined in the previous subsection. Additionally, fault coverage ratios are given. Although the results are overwhelmingly better for the proposed dual rail technique, the used assumptions are quite weak covering very certain fault characteristics.