Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Pipelining <s> From the Publisher: ::: Synthesis and Optimization of Digital Circuits offers a modern, up-to-date look at computer-aided design (CAD) of very large-scale integration (VLSI) circuits. In particular, this book covers techniques for synthesis and optimization of digital circuits at the architectural and logic levels, i.e., the generation of performance-and/or area-optimal circuits representations from models in hardware description languages. The book provides a thorough explanation of synthesis and optimization algorithms accompanied by a sound mathematical formulation and a unified notation. The text covers the following topics: modern hardware description languages (e.g., VHDL, Verilog); architectural-level synthesis of data flow and control units, including algorithms for scheduling and resource binding; combinational logic optimization algorithms for two-level and multiple-level circuits; sequential logic optimization methods; and library binding techniques, including those applicable to FPGAs. <s> BIB001 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Pipelining <s> Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although speculative execution is essential for increasing the instructions per cycle (IPC), it does come at a cost. A large amount of unnecessary work results from wrong-path instructions entering the pipeline due to branch misprediction. Results generated with the SimpleScalar tool set using a 4-way issue pipeline and various branch predictors show an instruction overhead of 16% to 105% for event instruction committed. The instruction overhead will increase in the future as processors use more aggressive speculation and wider issue widths. In this paper we present an innovative method for power reduction ,which, unlike previous work that sacrificed flexibility or performance reduces power in high-performance microprocessors without impacting performance. In particular we introduce a hardware mechanism called pipeline gating to control rampant speculation in the pipeline. We present inexpensive mechanisms for determining when a branch is likely to mispredict, and for stopping wrong-path instructions from entering the pipeline. Results show up to a 38% reduction in wrong-path instructions with a negligible performance loss (/spl ap/1%). Best of all, even in programs with a high branch prediction accuracy, performance does not noticeable degrade. Our analysis indicates that there is little risk in implementing this method in existing processors since it does not impact performance and can benefit energy reduction. <s> BIB002 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Pipelining <s> Minimizing power dissipation is an important design requirement for both portable and non-portable systems. In this work, we propose an architectural solution to the power problem that retains performance while reducing power. The technique, known as Pipeline Balancing (PLB), dynamically tunes the resources of a general purpose processor to the needs of the program by monitoring performance within each program. We analyze metrics for triggering PLB, and detail instruction queue design and energy savings based on an extension of the Alpha 21264 processor. Using a detailed simulator, we present component and full chip power and energy savings for single and multi-threaded execution. Results show an issue queue and execution unit power reduction of up to 23% and 13%, respectively, with an average performance loss of 1% to 2%. <s> BIB003 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Pipelining <s> A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed. The execution time will be increased but, if the method is applied to applications with slack time, the user-perceived performance may not be degraded Two techniques are shown using an existing asynchronous processor as a starting point. The first method controls the pipeline occupancy using a token mechanism, the second enables adjacent pipeline stages to be merged, by making the latches between them 'permanently' transparent. An energy reduction of up to 16% is measured, using a collection of five benchmarks. <s> BIB004 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Pipelining <s> Recent mobile processors are required to exhibit both low-energy consumption and high performance. To satisfy these requirements, dynamic voltage scaling (DVS) is currently employed. However, its effectiveness will be limited in the future because of shrinking the variable supply voltage range. As an alternative, we previously proposed pipeline stage unification (PSU), which unifies multiple pipeline stages without reducing the supply voltage at a power-saving mode. This paper compares effectiveness of PSU to DVS in current and future process generations. Our evaluation results show PSU will reduce energy consumption by 27-34% more than DVS after about 10 years. <s> BIB005 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Pipelining <s> The impact of pipeline length on both the power and performance of a microprocessor is explored both by theory and by simulation. A theory is presented for a range of power/performance metrics, BIPSm/W. The theory shows that the more important power is to the metric, the shorter the optimum pipeline length that results. For typical parameters neither BIPS/W nor BIPS2/W yield an optimum, i.e., a non-pipelined design is optimal. For BIPS3/W the optimum, averaged over all 55 workloads studied, occurs at a 22.5 FO4 design point, a 7 stage pipeline, but this value is highly dependent on the assumed growth in latch count with pipeline depth. As dynamic power grows, the optimal design point shifts to shorter pipelines. Clock gating pushes the optimum to deeper pipelines. Surprisingly, as leakage power grows, the optimum is also found to shift to deeper pipelines. The optimum pipeline depth varies for different classes of workloads: SPEC95 and SPEC2000 integer applications, traditional (legacy) database and on-line transaction processing applications, modern (e. g. web) applications, and floating point applications. <s> BIB006 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Pipelining <s> In this article, we present a bipartition dual-encoding architecture for low-power pipelined circuits. We exploit the bipartition approach as well as encoding techniques to reduce power dissipation not only of combinational logic blocks but also of the pipeline registers. Based on Shannon expansion, we partition a given circuit into two subcircuits such that the number of different outputs of both subcircuits are reduced, and then encode the output of both subcircuits to minimize the Hamming distance for transitions with a high switching probability. We measure the benefits of four different combinational bipartitioning and encoding architectures for comparison. The transistor-level simulation results show that bipartition dual-encoding can effectively reduce power by 72.7p for the pipeline registers and 27.1p for the total power consumption on average. To the best of our knowledge, it is the first work that presents an in-depth study on bipartition and encoding techniques to optimize power for pipelined circuits. <s> BIB007 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Pipelining <s> This paper presents a method to investigate power-performance tradeoffs in digital pipelined designs. The method is applied at the architectural level of the design. It is shown that addressing the tradeoffs at this level results in significant savings in power consumption without impacting the performance. The reduction in power is obtained through reducing the number of registers used in implementing the pipeline stages. The method has been validated by synthesizing a floating-point unit with different pipeline stages and power consumption of the designs were obtained using industry standard tools. It is shown that it is possible to obtain up to 18% reduction in power without affecting the clock period and with less area. <s> BIB008
The primary method of reducing the effective switched capacitance, even in a single-issue processor, is to control speculation, i.e. any operation which is performed before it is known to be required. In this sense the most "profound" type of speculation is pipelining; letting instructions into the processor pipeline before knowing for certain that the instruction flow is not about to branch is clearly speculative. In most instances this is justified, however discarded instructions that are fetched and partially processed waste energy BIB004 . Here power performance issues are discussed that relate to pipelining with focus on branch prediction, pipeline gating and pipeline depth. Pipelining a design involves BIB008 the addition of registers to create stages with the aim of improving throughput when the pipeline is fully utilized. Crucially the location of the pipeline stage will dictate the number of registers required to implement the stage. Since registers are power hungry elements, reduction in the total number of registers will yield reduction in power consumption. Shimada et al. deploy another technique called as PSU BIB005 or pipeline stage unification. PSU dynamically scales the clock frequency to reduce energy consumption as with DVFS, but unlike DVFS, it unifies multiple pipeline stages by bypassing pipeline registers, instead of scaling down the supply voltage. PSU saves energy consumption in two ways: 1) by reducing the total load capacitance of the clock driver; this is accomplished by stopping the clock signal to bypassed pipeline registers and 2) PSU reduces the clock cycle count of program execution by reducing the number of pipeline stages. Ruan et al. BIB007 take advantage of bi-partitioning and encoding techniques toward optimizing power consumption of pipelined circuits. A pipeline architecture can be seen as combinational logic blocks separated by edge-triggered registers that are driven by a single clock signal. They propose a bipartition dual-encoding architecture to decrease power consumption of pipelined CMOS designs. The approach is based on the observation that the pipeline registers take a large fraction of total power dissipation for most of the circuits. In order to address this issue, a given circuit is bi-partitioned by using Shannon expansion to minimize the number of different outputs of both sub-circuits BIB001 . Subsequently, both partitions are encoded to reduce the switching activities of the pipeline registers and logic blocks. To take advantage of the parallelism at the instruction level it is necessary to have some kind of prediction or speculation techniques to identify which instructions can be executed in future. This speculation can cost substantial energy if instructions are executed as a result of wrong prediction. A hardware mechanism called pipeline gating BIB002 to reduce overgrowing speculations in the pipeline can help to avoid this energy wastage. In this technique a confidence estimator is used to assess the quality of each branch prediction. A "high confidence" estimate means the branch predictor is likely to be correct. A "low confidence" estimate means the branch predictor has incorrectly predicted the branch. These confidence estimates decide when the processor is likely to be executing instructions that will not commit; once that decision has been reached, the pipeline is "gated", stalling specific pipeline stages. Similarly Bahar et al. BIB003 introduce a pipeline balancing (PLB) technique to reduce component and full chip power without negatively impacting performance. PLB takes advantage of the inherent IPC (Instruction Per Cycle) variations within a program to adjust the pipeline issue rate to the dynamic needs of each program. Hartstein and Puzak BIB006 show that the optimum pipeline depth is found to be much shorter when power is taken into account. They define an appropriate power/performance metric, and optimize the design to that metric. Decreasing the pipeline depth slows down the processor but also saves energy because fewer "speculative" instructions are fetched and decoded. In addition, hardware that supports pipelining, such as branch prediction, can be turned off as it is less effective in shallow pipelines BIB004 . Efthymiou et al. questions the energy saving accomplished using the branch predictors and hence they exploit the slack times in the applications with soft real time deadlines. Two techniques are presented to control the pipeline depth, using an asynchronous design style BIB004 because of its capability to adapt to changing energy/performance requirements at run time. One technique uses token passing as a method to control the pipeline occupancy, and thus indirectly, the pipeline depth. The other enables the selective and dynamic merging of adjacent pipeline stages by making the pipeline latches between them "permanently" transparent.