A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulation Based Modeling <s> Simulation has historically been the primary technique used for evaluating the performance of new proposals in computer architecture. Speed and complexity considerations have traditionally limited its applicability to single-thread processors running application-level code. This is no longer sufficient to model modern multicore systems running the complex workloads of commercial interest today. COTSon is a simulator framework jointly developed by HP Labs and AMD. The goal of COTSon is to provide fast and accurate evaluation of current and future computing systems, covering the full software stack and complete hardware models. It targets cluster-level systems composed of hundreds of commodity multicore nodes and their associated devices connected through a standard communication network. COTSon adopts a functional-directed philosophy, where fast functional emulators and timing models cooperate to improve the simulation accuracy at a speed sufficient to simulate the full stack of applications, middleware and OSs. This paper describes the changes in simulation philosophy we embraced in COTSon to address these new challenges. We base functional emulation on established, fast and validated tools that support commodity OSs and complex multitier applications. Through a robust interface between the functional and timing domain, we can leverage other existing simulators for individual sub-components, such as disks or networks. We abandon the idea of "always-on" cycle-based simulation in favor of statistical sampling approaches that can trade accuracy for speed. COTSon opens up a new dimension in the speed/accuracy space, allowing simulation of a cluster of nodes several orders of magnitude faster with a minimal accuracy loss. <s> BIB001 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulation Based Modeling <s> The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS [9] simulators. M5 provides a highly configurable simulation framework, multiple ISAs, and diverse CPU models. GEMS complements these features with a detailed and exible memory system, including support for multiple cache coherence protocols and interconnect models. Currently, gem5 supports most commercial ISAs (ARM, ALPHA, MIPS, Power, SPARC, and x86), including booting Linux on three of them (ARM, ALPHA, and x86). The project is the result of the combined efforts of many academic and industrial institutions, including AMD, ARM, HP, MIPS, Princeton, MIT, and the Universities of Michigan, Texas, and Wisconsin. Over the past ten years, M5 and GEMS have been used in hundreds of publications and have been downloaded tens of thousands of times. The high level of collaboration on the gem5 project, combined with the previous success of the component parts and a liberal BSD-like license, make gem5 a valuable full-system simulation tool. <s> BIB002 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulation Based Modeling <s> The confluence of emerging technologies and new data-centric workloads offers a unique opportunity to rethink traditional system architectures and memory hierarchies in future designs. <s> BIB003 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulation Based Modeling <s> The adoption of non-volatile memories (NVMs) in system architecture and the growth in data-centric workloads offer exciting opportunities for new designs. In this paper, we examine the potential and limit of designs that move compute in close proximity to NVM-based data stores. To address the challenges in evaluating such system architectures for distributed systems, we develop and validate a new methodology for large-scale data-centric workloads. We then study "nanostores" as an example design that constructs distributed systems from building blocks with 3D-stacked compute and NVM layers on the same chip, replacing both traditional storage and memory with NVM. Our limits study demonstrates significant potential of this approach (3-162X improvement in energy delay product) over 2015 baselines, particularly for IO-intensive workloads. We also discuss and quantify the impact of network bandwidth, software scalability, and power density, and design tradeoffs for future NVM-based data-centric architectures. <s> BIB004 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulation Based Modeling <s> In computer architecture, near-data processing (NDP) refers to augmenting the memory or the storage with processing power so that it can process the data stored therein. By offloading the computational burden of CPU and saving the need for transferring raw data in its entirety, NDP exhibits a great potential for acceleration and power reduction. Despite this potential, specific research activities on NDP have witnessed only limited success until recently, often owing to performance mismatches between logic and memory process technologies that put a limit on the processing capability of memory. Recently, there have been two major changes in the game, igniting the resurgence of NDP with renewed interest. The first is the success of machine learning (ML), which often demands a great deal of computation for training, requiring frequent transfers of big data. The second is the advent of NAND flash-based solid-state drives (SSDs) containing multicore processors that can accommodate extra computation for data processing. Sparked by these application needs and technological support, we evaluate the potential of NDP for ML using a new SSD platform that allows us to simulate in-storage processing (ISP) of ML workloads. Our platform (named ISP-ML) is a full-fledged simulator of a realistic multi-channel SSD that can execute various ML algorithms using the data stored in the SSD. For thorough performance analysis and in-depth comparison with alternatives, we focus on a specific algorithm: stochastic gradient decent (SGD), which is the de facto standard for training differentiable learning machines including deep neural networks. We implement and compare three variants of SGD (synchronous, Downpour, and elastic averaging) using ISP-ML, exploiting the multiple NAND channels for parallelizing SGD. In addition, we compare the performance of ISP and that of conventional in-host processing, revealing the advantages of ISP. Based on the advantages and limitations identified through our experiments, we further discuss directions for future research on ISP for accelerating ML. <s> BIB005 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulation Based Modeling <s> Due to an explosive growth of Internet applications, the amount of data has increased enormously. In order to store and process this big data more efficiently, a solid-state device (SSD) has replaced a hard disk drive (HDD) as a primary storage media. In spite of high internal bandwidth, SSD has its performance bottleneck on the host interface whose bandwidth is relatively low. To overcome the problem of performance bottleneck in big data processing, the notion of intelligent SSD (iSSD) was proposed to give computing power to SSD. However, its real implementation has not been provided to the public yet. In this paper, we are going to verify the potential of iSSD in handling data-intensive algorithms. To the end, we first develop an iSSD simulator and then evaluate the performance of data mining algorithms inside iSSD on the top of it in comparison with that by the host CPU. The results reveal that data mining with iSSD outperforms that with host CPUs up to around 300%. <s> BIB006
To achieve more accurate performance numbers, architects often resort to modeling the entire micro-architecture precisely. However, this approach can be quite slow compared to analytic techniques. Hyeokjun et al. BIB005 evaluated the potential of NMC for machine learning (ML) using a full-fledged simulator of multi-channel SSD that can execute various ML algorithms on data stored on the SSD. Similarly, Jo et al. BIB006 developed the iSSD simulator based on the gem5 simulator BIB002 . Ranganathan et al. BIB004 , BIB003 for their nano-stores architecture used a hybrid methodology which is a bottom-up approach in which they built a high level model which breaks down applications into various phases, based on compute, network, and I/O sub system activities. This takes input from the low level performance and power models regarding the performance of each phase. They used COTSon BIB001 for detailed micro-architectural simulation. 