Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Dynamic Voltage-Frequency Scaling (DVFS) <s> A novel algorithm for servicing soft deadline aperiodic tasks in a real-time system in which hard deadline periodic tasks are scheduled using a fixed priority algorithm is presented. This algorithm is proved to be optimal in the sense that it provides the shortest aperiodic response time among all possible aperiodic service methods. Simulation studies show that it offers substantial performance improvements over current approaches, including the sporadic server algorithm. Moreover, standard queuing formulas can be used to predict aperiodic response times over a wide range of conditions. The algorithm can be extended to schedule hard deadline aperiodics and to efficiently reclaim unused periodic service time when periodic tasks have stochastic execution times. > <s> BIB001 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Dynamic Voltage-Frequency Scaling (DVFS) <s> The energy usage of computer systems is becoming more important, especially for battery operated systems. Displays, disks, and cpus, in that order, use the most energy. Reducing the energy used by displays and disks has been studied elsewhere; this paper considers a new method for reducing the energy used by the cpu. We introduce a new metric for cpu energy performance, millions-of-instructions-per-joule (MIPJ). We examine a class of methods to reduce MIPJ that are characterized by dynamic control of system clock speed by the operating system scheduler. Reducing clock speed alone does not reduce MIPJ, since to do the same work the system must run longer. However, a number of methods are available for reducing energy with reduced clock-speed, such as reducing the voltage [Chandrakasan et al 1992][Horowitz 1993] or using reversible [Younis and Knight 1993] or adiabatic logic [Athas et al 1994]. What are the right scheduling algorithms for taking advantage of reduced clock-speed, especially in the presence of applications demanding ever more instructions-per-second? We consider several methods for varying the clock speed dynamically under control of the operating system, and examine the performance of these methods against workstation traces. The primary result is that by adjusting the clock speed at a fine grain, substantial CPU energy can be saved with a limited impact on performance. <s> BIB002 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Dynamic Voltage-Frequency Scaling (DVFS) <s> A collision occurs in real network access if two or more packets are simultaneously transmitted. Hence, the contentioncollision must be resolved when applying a protocol in the wireless data network. In this paper,we adopt the concept of elimination and dynamic tree expansion in Randomly AddressedPolling (RAP) protocol to reduce the delay time and enhance the throughput. Analyses resultsindicate that the throughput performance of this algorithm is up to about 0.9 and thedelay time rapidly decays. <s> BIB003 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Dynamic Voltage-Frequency Scaling (DVFS) <s> In recent years, there has been a rapid and wide spread of non-traditional computing platforms, especially mobile and portable computing devices. As applications become increasingly sophisticated and processing power increases, the most serious limitation on these devices is the available battery life. Dynamic Voltage Scaling (DVS) has been a key technique in exploiting the hardware characteristics of processors to reduce energy dissipation by lowering the supply voltage and operating frequency. The DVS algorithms are shown to be able to make dramatic energy savings while providing the necessary peak computation power in general-purpose systems. However, for a large class of applications in embedded real-time systems like cellular phones and camcorders, the variable operating frequency interferes with their deadline guarantee mechanisms, and DVS in this context, despite its growing importance, is largely overlooked/under-developed. To provide real-time guarantees, DVS must consider deadlines and periodicity of real-time tasks, requiring integration with the real-time scheduler. In this paper, we present a class of novel algorithms called real-time DVS (RT-DVS) that modify the OS's real-time scheduler and task management service to provide significant energy savings while maintaining real-time deadline guarantees. We show through simulations and a working prototype implementation that these RT-DVS algorithms closely approach the theoretical lower bound on energy consumption, and can easily reduce energy consumption 20% to 40% in an embedded real-time system. <s> BIB004 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Dynamic Voltage-Frequency Scaling (DVFS) <s> Since the first results published in 1973 by Liu and Layland on the Rate Monotonic (RM) and Earliest Deadline First (EDF) algorithms, a lot of progress has been made in the schedulability analysis of periodic task sets. Unfortunately, many misconceptions still exist about the properties of these two scheduling methods, which usually tend to favor RM more than EDF. Typical wrong statements often heard in technical conferences and even in research papers claim that RM is easier to analyze than EDF, it introduces less runtime overhead, it is more predictable in overload conditions, and causes less jitter in task execution.Since the above statements are either wrong, or not precise, it is time to clarify these issues in a systematic fashion, because the use of EDF allows a better exploitation of the available resources and significantly improves system's performance.This paper compares RM against EDF under several aspects, using existing theoretical results, specific simulation experiments, or simple counterexamples to show that many common beliefs are either false or only restricted to specific situations. <s> BIB005 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Dynamic Voltage-Frequency Scaling (DVFS) <s> This work presents a dynamic voltage and frequency scaling (DVFS) technique that minimizes the total system energy consumption for performing a task while satisfying a given execution time constraint. We first show that in order to guarantee minimum energy for task execution by using DVFS it is essential to divide the system power into active and standby power components. Next, we present a new DVFS technique, which considers not only the active power, but also the standby component of the system power. This is in sharp contrast with previous DVFS techniques, which only consider the active power component. We have implemented the proposed DVFS technique on the BitsyX platform - an Intel PXA255-based platform manufactured by ADS Inc., and report detailed power measurements on this platform. These measurements show that, compared to conventional DVFS techniques, an additional system energy saving of up to 18% can be achieved while satisfying the user-specified timing constraints. <s> BIB006 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Dynamic Voltage-Frequency Scaling (DVFS) <s> A novel power attack resistant cryptosystem is presented in this paper. Security in digital computing and communication is becoming increasingly important. Design techniques that can protect cryptosystems from leaking information have been studied by several groups. Power attacks, which infer program behavior from observing power supply current into a processor core, are important forms of attacks. Various methods have been proposed to countermeasure the popular and efficient power attacks. However, these methods do not adequately protect against power attacks and may introduce new vulnerabilities. In this work, we addressed a novel approach against the power attacks, i.e., Dynamic Voltage and Frequency Switching (DVFS). Three designs, naive, improved and advanced implementations, have been studied to test the efficiency of DVFS against power attacks. A final advanced realization of our novel cryptosystem was given out, which achieved enough high power trace entropy and time trace entropy to block all kinds of power attacks, with 27% energy reduction and 16% time overhead for DES encryption and decryption algorithms. <s> BIB007 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Dynamic Voltage-Frequency Scaling (DVFS) <s> The importance and demand for various types of optimization techniques for program execution is growing rapidly. In particular, dynamic optimization techniques are regarded as important. Although conventional techniques usually generated an execution model for dynamic optimization by qualitatively analyzing the behaviors of computer systems in a knowledge-based manner, the proposed technique generates models by statistically analyzing the behaviors from quantitative data of hardware events. In the present paper, a novel dynamic voltage and frequency scaling (DVFS) method based on statistical analysis is proposed. The proposed technique is a hybrid technique in which static information, such as the breakpoint of program phases and, dynamic information, such as the number of cache misses given by the performance counter, are used together. Relationships between the performance and values of performance counters are learned statistically in advance. The compiler then inserts a run-time code for predicting the performance and setting the appropriate frequency/voltage depending on the predicted performance. The proposed technique can greatly reduce the energy consumption while satisfying soft timing constraints. <s> BIB008 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Dynamic Voltage-Frequency Scaling (DVFS) <s> This paper presents a supervised learning based dynamic power management (DPM) framework for a multicore processor, where a power manager (PM) learns to predict the system performance state from some readily available input features (such as the state of service queue occupancy and the task arrival rate) and then uses this predicted state to look up the optimal power management action from a pre-computed policy lookup table. The motivation for utilizing supervised learning in the form of a Bayesian classifier is to reduce overhead of the PM which has to recurrently determine and issue voltage-frequency setting commands to each processor core in the system. Experimental results reveal that the proposed Bayesian classification based DPM technique ensures system-wide energy savings under rapidly and widely varying workloads. <s> BIB009 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Dynamic Voltage-Frequency Scaling (DVFS) <s> As we embrace the world of personal, portable, and perplexingly complex digital systems, it has befallen upon the bewildered designer to take advantage of the available transistors to produce a system which is small, fast, cheap and correct, yet possesses increased functionality. Increasingly, these systems have to consume little energy. Designers are increasingly turning towards small processors, which are low power, and customize these processors both in software and hardware to achieve their objectives of a low power system, which is verified, and has short design turnaround times. Designing Embedded Processorsexamines the many ways in which processor based systems are designed to allow low power devices. It looks at processor design methods, memory optimization, dynamic voltage scaling methods, compiler methods, and multi processor methods. Each section has an introductory chapter to give a breadth view, and have a few specialist chapters in the area to give a deeper perspective. The book provides a good starting point to engineers in the area, and to research students embarking upon the exciting area of embedded systems and architectures. <s> BIB010
Dynamic Voltage and Frequency Scaling (DVFS) is an effective technique to attain low power consumption while meeting the performance requirements. Energy dissipation is reduced by dynamically scaling the supply voltage of the CPU, so that it operates at a minimum speed required by the specific task executed (i.e. maintaining real-timeliness) BIB010 . The DVFS technique principally involves scheduling in order to determine when each request of the task is to be executed by the processor and allows to slow down the processor, so that it consumes less power and takes greater time to execute. The tasks can be assigned priorities statically (when the priorities are fixed) or dynamically (when priorities are changed from one request to another). An example for well known dynamic priority assignment is Earliest Deadline First (EDF) and an example for static assignment is Rate-Monotonic Scheduling (RMS) BIB005 for periodic tasks. DVFS can be classified based on timing constraints, scaling granularity, and scheduling policy basis (Fig. 1) . The timing constraint based scheduling can be either nonreal time or real time. Pillai et al. BIB004 present a class of novel algorithms for real-time DVS that modify the operating systems' real-time scheduler and task management service to provide significant energy savings while meeting real-time deadlines. Their results show a reduction of energy consumption by 20% to 40%. Based on scaling granularity, DVFS can be classified as preemptive and non-pre-emptive. In pre-emptive scheduling, the time is typically divided into fixed intervals, as proposed in BIB002 BIB001 . DVFS is then applied by a task level scheduler based on processor utilization statistics over preceding interval. Smoothing (or spreading processing cycles) is used to utilize idle cycles. While in non-preemptive scheduling tasks run to completion and cannot be interrupted during execution BIB003 . This in turn compels DVFS decisions to be applied after the completion or before the start of individual tasks. A non pre-emptive scheduling technique that treats voltage as a variable is e.g. discussed in  . Jeffay et al.  analyzed scheduling of a set of periodic and sporadic tasks on a uniprocessor without pre-emption and without inserted idle time. Their results showed the universal viability of earliest deadline first algorithm for given sets of sporadic and periodic tasks. DVFS scheduling can also be classified into offline and online techniques BIB010 . Offline scheduling BIB002 has a lower runtime processing overhead, by assuming the worst case scenario or pessimistic scheduling approach, thus resulting in lower power savings. Online scheduling techniques as proposed in BIB006 could result in higher power savings than their static counterparts, however they are associated with a higher processing overhead. Jung et al. BIB009 present a supervised learning based dynamic power management (DPM) framework for multicore processors. The framework predicts on available input features such as the state of service queue occupancy and the task arrival rate. Then the predicted state is used to look up the optimal power management action from a pre-computed policy lookup table. This technique -in spite of being online -could result in smaller run time energy overhead. Sasaki et al. BIB008 propose a hybrid technique which takes advantage of lower processing overhead along with greater power efficiency. The technique uses both static and dynamic information and based on appropriate frequency/voltage set points inserted as a run-time code by the compiler. As per claim, the proposed technique can significantly reduce the energy consumption while satisfying soft timing constraints. Interestingly, DVFS can also be applied to secure the device from power attacks, which infer program behaviour from observing power supply current into a processor core: In BIB007 a power attack resistant cryptosystem is presented, which uses dynamic voltage and frequency switching to make the power traces show random properties and prevent the power attackers from carrying out time correlation between different power traces, while at the same time facilitating the energy saving task.