Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Asynchronous Processors <s> Field-programmable gate arrays are a dominant implementation medium for digital circuits, especially for glue logic. Unfortunately, they do not support asynchronous circuits. This is a significant problem because many aspects of glue logic and communication interfaces involve asynchronous elements, or require the interconnection of synchronous components operating under independent clocks. We describe Montage, the first FPGA to explicitly support asynchronous circuit implementation, and its mapping software. Montage can be used to realize asynchronous interface circuits or to prototype complete asynchronous systems, thus bringing the benefits of rapid prototyping to asynchronous design. Unfortunately, implementation media for asynchronous circuits and systems have not kept up with those for the synchronous world. Programmable logic devices do not include the special non-digital circuits required by asynchronous design methodologies (e.g., arbiters and synchronizers) nor do they facilitate hazard-free logic implementations. This leads to huge inefficiencies in the implementation of asynchronous designs as circuits require a variety of seperate devices. This has caused most asynchronous designers to focus on custom or semi-custom integrated circuits, thus incurring greater expense in time and money. The net effect has been that optimized and robust asynchronous circuits have not become a part of typical system designs. The asynchronous circuits that must be included are usually designed in an ad-hoc manner with many underlying assumptions. This is a highly error- prone process, and causes implementations to be unnecessarily delicate to delay variations. Field-programmable gate arrays, one of today's dominant media for prototyping and implementing digital circuits, are also inappropriate for constructing more than the simplest asynchronous interfaces. They lack the critical elements at the heart of today's asynchronous designs. Unfortunately, resolving this problem is not just a simple matter of adding these elements to the programmable array. The FPGA must also have predictable routing delay and must not introduce hazards in either the logic or routing. Futhermore, the mapping tools must also be modified to handle asynchronous concerns, especially the proper decomposition of logic to fit into the programmable logic blocks and the proper routing of signals to ensure that required timing relationships are met. Ideally, we need an FPGA that can support both synchronous and asynchronous circuits with comparable efficiency. As a step in this direction we present Montage, an integrated system of FPGA architecture and mapping software designed to support both asynchronous circuits and synchronous interfaces. The architecture provides circuits with hazard-free logic and routing, mutual exclusion elements to handle metastability, and methods for initializing unclocked elements. The mapping software generates placement and signal routing sensitive to the timing demands of asynchronous methods. With these features, the Montage system forms a prototyping and implementation medium for asynchronous designs, providing asynchronous circuits with a powerful tool from the synchronous designer's toolbox. <s> BIB001 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Asynchronous Processors <s> A silicon compiler, Balsa-c, has been developed for the automatic synthesis of asynchronous, delay-insensitive circuits from the language Balsa. Balsa is derived from CSP with similar language constructs and a single-bit granularity type system. <s> BIB002 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Asynchronous Processors <s> This paper describes a new technique for integrating asynchronous modules within a high-speed synchronous pipeline. Our design eliminates potential metastability problems by using a clock generated by a stoppable ring oscillator, which is capable of driving the large clock load found in present day microprocessors. Using the ATACS design tool, we designed highly optimized transistor-level circuits to control the ring oscillator and generate the clock and handshake signals with minimal overhead. Our interface architecture requires no redesign of the synchronous circuitry. Incorporating asynchronous modules in a high-speed pipeline improves performance by exploiting data-dependent delay variations. Since the speed of the synchronous circuitry tracks the speed of the ring oscillator under different processes, temperatures, and voltages, the entire chip operates at the speed dictated by the current operating conditions, rather than being governed by the worst-case conditions. These two factors together can lead to a significant improvement in average-case performance. The interface design is tested using the 0.6 /spl mu/m HP CMOS14B process in HSPICE. <s> BIB003 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Asynchronous Processors <s> Recent years have seen a burgeoning interest in embedded wireless sensor networks with applications ranging from habitat monitoring to medical applications. Wireless sensor networks have several important attributes that require special attention to device design. These include the need for inexpensive, long-lasting, highly reliable devices coupled with very low performance requirements. Ultimately, the "holy grail" of this design space is a truly untethered device that operates off of energy scavenged from the ambient environment. In this paper, we describe an application-driven approach to the architectural design and implementation of a wireless sensor device that recognizes the event-driven nature of many sensor-network workloads. We have developed a full-system simulator for our sensor node design to verify and explore our architecture. Our simulation results suggest one to two orders of magnitude reduction in power dissipation over existing commodity-based systems for an important class of sensor network applications. We are currently in the implementation stage of design, and plan to tape out the first version of our system within the next year. <s> BIB004 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Asynchronous Processors <s> We present a novel asynchronous processor architecture called BitSNAP that utilizes bit-serial datapaths with dynamic significance compression to yield extremely low-energy consumption. Based on the sensor network asynchronous processor (SNAP) ISA, BitSNAP can reduce datapath energy consumption by 50% over a comparable parallel-word processor, while still providing performance suited for powering low-energy sensor network nodes. In 180 nm CMOS, the processor is expected to run at between 6 and 54 MIPS while consuming 152 pJ/ins at 1.8 V and just 17 pJ/ins at 0.6 V. <s> BIB005 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Asynchronous Processors <s> This article consists of a collection of slides from the author's conference presentation on the ARM-Handshake Solutions partnership. Some of the specific topics discussed include: the specifics of the partnership which involved the joint development of the ARM core implementations; potential application domains; ARM embedded processors and measured power efficiency; a description of Handshake technology; and an overview of joint development technologies; and power processing capabilities. <s> BIB006 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Asynchronous Processors <s> The Integrated Systems Laboratory (IIS) of ETH Zurich (Swiss Federal Institute of Technology) has been active in globally-asynchronous locally-synchronous (GALS) research since 1998. During this time, a number of GALS circuits have been fabricated and tested successfully on silicon. From a hardware designers point of view, this article summarizes the evolution from proof of concept designs over multi-point interconnects to applications that specifically take advantage of GALS operation to improve cryptographic security. In spite of the fact that they fail to address numerous idiosyncrasies of GALS (such as good partitioning into synchronous islands, port controller design, pausable clock generators, design for test, etc.), hierarchical design flows have been found to form a workable basis. What prevents GALS from gaining a wider acceptance mainly is the initial effort required to come up with a design flow that is efficient and dependable. <s> BIB007 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Asynchronous Processors <s> In this paper, we propose the design of on-chip and off-chip interfaces adapted to a globally asynchronous locally synchronous (GALS) network-on-chip (NoC) architecture. The proposed on-chip interface not only handles the resynchronization between the synchronous and asynchronous NoC domains, but also implements NoC communication priorities. This design is based on existing multi-clock synchronization fifos based on Gray code, and is adapted to standard implementation tools. Concerning Off-chip communications, a new concept of mixed synchronous/asynchronous dual mode NoC port is proposed as an efficient off-chip NoC interface for NoC-based open-platform prototyping. These interfaces have been successfully implemented in a 0.13/spl mu/m CMOS technology. <s> BIB008 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Asynchronous Processors <s> This article provides a pragmatic survey on the state of the art in GALS architectural techniques, design flows, and applications. The authors also prescribe several industrial inventions and changes in methodology, tools, and design flow that would improve GALS-based integration of IP blocks. <s> BIB009 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Asynchronous Processors <s> Single-clocked digital systems are largely a thing of the past. Although most digital circuits remain synchronous, many designs feature multiple clock domains, often running at different frequencies. Using an asynchronous interconnect decouples the timing issues for the separate blocks. Systems employing such schemes are called globally asynchronous, locally synchronous (GALS). To minimize time to market, large SoC designs must integrate many functional blocks with minimal design effort. These blocks are usually designed using standard synchronous methods and often have different clocking requirements. A GALS approach can facilitate fast block reuse by providing wrapper circuits to handle interblock communication across clock domain boundaries. SoCs may also achieve power savings by clocking different blocks at their minimum speeds. For example, Scott et al. describe the advantages of GALS design for an embedded-processor peripheral bus. <s> BIB010 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Asynchronous Processors <s> The distribution of a synchronous clock in system-on-chip (SoC) has become a problem, because of wire length and process variation. Novel approaches such as the globally asynchronous, locally synchronous try to solve this issue by partitioning the SoC into isolated synchronous islands. This paper describes the bisynchronous FIFO used on the DSPIN network-on-chip capable to interface systems working with different clock signals (frequency and/or phase). Its interfaces are synchronous and its architecture is scalable and synthesizable in synchronous standard cells. The metastability situations and its latency are analyzed. Its throughput, maximum frequency, and area are evaluated in function of the FIFO depth. <s> BIB011 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Asynchronous Processors <s> Low-power design became crucial with widespread use of the embedded systems. The embedded processors need to be efficient in order to achieve real-time requirements with low power consumption for specific algorithms. As the superset of traditional very long instruction word (VLIW) architecture, the main advantages of transport triggered architecture (TTA) are its simplicity and flexibility. In TTA processors, the special function units can be utilized to increase performance or reduce power dissipation. Asynchronous circuits have characteristic of low power consumption and it is possible to exploit this characteristic to design embedded processors. In this article, we designed a low-power embedded processor using asynchronous function units. The processor core is globally synchronous and locally asynchronous implementation using not only synchronous function units but also asynchronous function units. We also presented an efficient design flow that use asynchronous circuits in TTA framework, which is only a synchronous design environment. The test result shows that this processor has lower power dissipation than its pure synchronous version that only uses synchronous function units. <s> BIB012
Asynchronous processor is a major development in low power architectures. The absence of a clock addresses the fact that the clock is a major power consumer in a synchronous processor. A clockless design does not only save clock power consumption but also protects from clock skew problem (which is more evident as the size of IC grows), reduces noise, and ease the component modularity and reuse. However the absence of clock also implicates careful design of handshake protocols; their failure could result in hazards  and race conditions  . Additionally, asynchronous circuits require more area for implementation as compared to their synchronous counterparts; thus resulting in higher production costs. An early example of an asynchronous processor is the AMULET, which is a pioneer Asynchronous ARM architecture debuted in 1993  . Internally the processor is constructed from several function units which operate independently and concurrently, exchanging information through a handshake protocol. This basic theme remains common with other asynchronous counterparts like SNAP BIB004 , Bit SNAP BIB005 , ARM996HS BIB006 , HT80C51, and SUN Sproull Pipeline Processor architecture  etc. Asynchronous circuits may have several advantages but the absence of suitable commercial grade synthesis tools have limited their wide spread usage to date. The TiDE -Timeless Design Environment BIB006 and BALSA BIB002 are addressing some of these issues. Also prototype development platforms for asynchronous design are still in the research phase e.g.  BIB001 . GALS (Globally Asynchronous and Locally Synchronous) is an approach aimed to combine the advantages of synchronous and asynchronous design methodologies while avoiding their disadvantages. GALS can be classified into three main implementation techniques, namely pausible clock generators, FIFO buffers, and boundary synchronization BIB009 .  Pausible-clock generators: The pausible-clock design style relies on locally generated, data driven clocks that can be stretched or paused either to prevent metastability or to let a transmitter or receiver stall because of a full or empty channel BIB007 BIB010 .  FIFO buffers: using asynchronous FIFO buffers between locally synchronous blocks to hide the synchronization problem. This technique can be seen in various NoC designs as BIB008 BIB011 .  Boundary synchronization: performing boundary synchronization on the signals crossing the borders of the locally synchronous island without stopping the complete locally synchronous block during data transfer BIB009 . GALS has been actively researched for more than 20 years. But despite several successful implementations, GALS has had little impact on commercial products BIB009 . In BIB009 the authors have analyzed the actual challenges and problems for wider adoption of the currently proposed GALS methods. Their analysis shows that significant improvement can be achieved in terms of system integration and EMI reduction; but with marginal improvements in power savings. Additionally, introduction of a GALS approach leads to relatively small area increases, and in some cases even causes certain performance losses. GSLA or Globally Synchronous Locally Asynchronous is a relatively new scheme with the same targets in mind; however this also suffers with large area overheads; examples of GSLA can be found in BIB003  BIB012 .