Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Advancing with Moore's law <s> A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3/spl sigma/ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations. <s> BIB001 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Advancing with Moore's law <s> High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption. <s> BIB002 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Advancing with Moore's law <s> FOREWORD.PREFACE.1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS.1.1 Design Methodology in the Nano-CMOS Era.1.2 Innovations Needed to Continue Performance Scaling.1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography.1.4 Process Control and Reliability.1.5 Lithographic Issues and Mask Data Explosion.1.6 New Breed of Circuit and Physical Design Engineers.1.7 Modeling Challenges.1.8 Need for Design Methodology Changes.1.9 Summary.References.PART I: PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS.2 CMOS DEVICE AND PROCESS TECHNOLOGY.2.1 Equipment Requirements for Front-End Processing.2.2 Front-End-Device Problems in CMOS Scaling.2.3 Back-End-of-Line Technology.References.3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY.3.1 Introduction and Simple Imaging Theory.3.2 Challenges for the 100-nm Node.3.3 Resolution Enhancement Techniques: Physics.3.4 Physical Design Style Impact on RET and OPC Complexity.3.5 The Road Ahead: Future Lithographic Technologies.References.PART II: PROCESS SCALING IMPACT ON DESIGN 4 MIXED-SIGNAL CIRCUIT DESIGN.4.1 Introduction.4.2 Design Considerations.4.3 Device Modeling.4.4 Passive Components.4.5 Design Methodology.4.6 Low-Voltage Techniques.4.7 Design Procedures.4.8 Electrostatic Discharge Protection.4.9 Noise Isolation.4.10 Decoupling.4.11 Power Busing.4.12 Integration Problems.4.13 Summary.References.5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN.5.1 Introduction.5.2 ESD Standards and Models.5.3 ESD Protection Design.5.4 Low-C ESD Protection Design for High-Speed I/O.5.5 ESD Protection Design for Mixed-Voltage I/O.5.6 SCR Devices for ESD Protection.5.7 Summary.References.6 INPUT/OUTPUT DESIGN.6.1 Introduction.6.2 I/O Standards.6.3 Signal Transfer.6.4 ESD Protection.6.5 I/O Switching Noise.6.6 Termination.6.7 Impedance Matching.6.8 Preemphasis.6.9 Equalization.6.10 Conclusion.References.7 DRAM.7.1 Introduction.7.2 DRAM Basics.7.3 Scaling the Capacitor.7.4 Scaling the Array Transistor.7.5 Scaling the Sense Amplifier.7.6 Summary.References.8 SIGNAL INTEGRITY PROBLEMS IN ON-CHIP INTERCONNECTS.8.1 Introduction.8.2 Interconnect Parasitics Extraction.8.3 Signal Integrity Analysis.8.4 Design Solutions for Signal Integrity.8.5 Summary.References.9 ULTRALOW POWER CIRCUIT DESIGN.9.1 Introduction.9.2 Design-Time Low-Power Techniques.9.3 Run-Time Low-Power Techniques.9.4 Technology Innovations for Low-Power Design.9.5 Perspectives for Future Ultralow-Power Design.References.PART III: IMPACT OF PHYSICAL DESIGN ON MANUFACTURING/YIELD AND PERFORMANCE.10 DESIGN FOR MANUFACTURABILITY.10.1 Introduction.10.2 Comparison of Optimal and Suboptimal Layouts.10.3 Global Route DFM.10.4 Analog DFM.10.5 Some Rules of Thumb.10.6 Summary.References.11 DESIGN FOR VARIABILITY.11.1 Impact of Variations on Future Design.11.2 Strategies to Mitigate Impact Due to Variations.11.3 Corner Modeling Methodology for Nano-CMOS Processes.11.4 New Features of the BSIM4 Model.11.5 Summary.References.INDEX. <s> BIB003 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Advancing with Moore's law <s> Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of ICs from their designers' original intent. These deviations reduce the parametric yield and revenues from integrated circuit fabrication. In this paper we provide a complete treatment to the subject of within-die variations. We propose a scan-chain based system, vMeter, to extract within-die variations in an automated fashion. We implement our system in a sample of 90 nm chips, and collect the within-die variations data. Then we propose a number of novel statistical analysis techniques that accurately model the within-die variation trends and capture the spatial correlations. We propose the use of maximum-likelihood techniques to find the required parameters to fit the model to the data. The accuracy of our models is statistically verified through residual analysis and variograms. Using our successful modeling technique, we propose a procedure to generate synthetic within-die variation patterns that mimic, or imitate, real silicon data. <s> BIB004 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Advancing with Moore's law <s> This book is the sequel to Nano-CMOS Circuit and Physical Design, taking design to technology nodes beyond 65nm geometries. It examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. It also tackles complex issues in the design process and introduces several emerging concepts, including stress proximity effects, contour-based extraction, and design process interactions. <s> BIB005 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Advancing with Moore's law <s> This brief presents a method to exploit gate leakage (GL) to create a feedback element for an input offset insensitive and output offset programmable inverting amplifier. Measurements are shown from a test circuit produced in a 90-nm multithreshold CMOS process where a GL element uses thin oxide and a amplifier input stage uses thick oxide. The feedback element has very high nonlinear impedance from about 100 M to several gigaohms depending on the applied voltage, and is suitable for adaptive applications where long time constants (1 ms to 1s) are required and small, slowly wandering offsets can be tolerated. <s> BIB006 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Advancing with Moore's law <s> As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The condition Vsb > 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, as Vsb > 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 109 devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters. <s> BIB007 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Advancing with Moore's law <s> Nanoscale analog CMOS IC design productivity is becoming a major concern for the semiconductor industry as chip device counts approach 1 billion at 32 nm and each technology offers a choice of several operating platform variants. A multitude of physical device pattern separation dimensions must now be entered into the prelayout simulation models in order to predict postlayout circuit performance accurately. The random nature of analog physical design, which focuses on signal flow and coupling, increases the randomness and difficulty of prelayout simulation parameter entry. A new paradigm for analog circuit and physical design is presented which relies on restrictive design rules for device physical design. <s> BIB008
For the past 30 years, the semiconductor industry has faithfully followed Moore's law, which predicted that the number of transistors in an IC doubles every 2 years. Moore's law also predicted that the size of transistors (and hence the die cost per transistor) would reduce by half every 2 years. This law has led to a consistent "scaling down" of transistor sizes by IC manufacturers and ushered sub-nanometer scale, fine-line CMOS process technologies. However, CMOS scaling has benefited ICs that contain primarily digital functions, such as the microprocessor and DSP. In fact, scaling has imposed increased design challenges to traditional analog circuits. Designing neural amplifiers, or any analog integrated circuit, in such fine-line, CMOS processes hold numerous challenges, including increased gate and channel leakage BIB002 , increased flicker noise   and increased intradie variability BIB001 BIB004 . There are more process-related design constraints that must be considered compared to the other mature industrial process technologies BIB008 BIB007 BIB003 BIB005 . Hence, it may seem that neural amplifiers would not benefit from this continuous CMOS process scaling. On the contrary, some notable neural amplifier ICs have significantly improved according to this trend and have been implemented in sub-100-nm CMOS processes. For example, Ng and Xu reported a neural amplifier system implemented in a 65-nm CMOS process that leverages the complementary characteristics of thin-gate and thick-gate transistors to perform on-chip analog signal processing  . A second reported method involves the migration of analog functions into their equivalent digital logic implementations. For example, Muller et al. digitized nearly the full analog-to-digital conversion chain  on a single IC. Finally, certain device "imperfections" can be leveraged as part of the circuit design. For example, Berge and Hafliger used the leaky gate of a transistor to form both the feedback capacitor and the DC bias pseudo-resistor of the neural amplifier, therefore completely eliminating the traditional pseudo-resistor element BIB006 . In order for the advanced CMOS process technologies to be a viable choice for implementing neural amplifiers, economies of scale must be accelerated, and new circuit design techniques must be devised to address or utilize "imperfections" associated with such advanced process technologies.