Computational workload in biometric identification systems: an overview <s> Acceleration <s> This report investigates the “decision landscapes” that characterize several forms of biometric decision making. The issues discussed include: (i) Estimating the degrees-of-freedom associated with different biometrics, as a way of measuring the randomness and complexity (and therefore the uniqueness) of their templates. (ii) The consequences of combining more than one biometric test to arrive at a decision. (iii) The requirements for performing identification by large-scale exhaustive database search, as opposed to mere verification by comparison against a single template. (iv) Scenarios for Biometric Key Cryptography (the use of biometrics for encryption of messages). These issues are considered here in abstract form, but where appropriate, the particular example of iris recognition is used as an illustration. A unifying theme of all four sets of issues is the role of combinatorial complexity, and its measurement, in determining the potential decisiveness of biometric decision making. <s> BIB001 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> In image processing, FPGAs have shown very high performance in spite of their low operational frequency. This high performance comes from (1) high parallelism in applications in image processing, (2) high ratio of 8 bit operations, and (3) a large number of internal memory banks on FPGAs which can be accessed in parallel. In the recent micro processors, it becomes possible to execute SIMD instructions on 128 bit data in one clock cycle. Furthermore, these processors support multi-cores and large cache memory which can hold all image data for each core. In this paper, we compare the performance of FPGAs with those processors using three applications in image processing; two-dimensional filters, stereo-vision and k-means clustering, and make it clear how fast is an FPGA in image processing, and how many hardware resources are required to achieve the performance. <s> BIB002 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> The advent of multicore CPUs and manycore GPUs means that mainstream processor chips are now parallel systems. Furthermore, their parallelism continues to scale with Moore's law. The challenge is to develop mainstream application software that transparently scales its parallelism to leverage the increasing number of processor cores, much as 3D graphics applications transparently scale their parallelism to manycore GPUs with widely varying numbers of cores. <s> BIB003 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> To the best of the authors' knowledge, this is the first brief that implements a complete automatic fingerprint-based authentication system (AFAS) application under a dynamically partial self-reconfigurable field-programmable gate array (FPGA). The main benefits of this implementation are the acceleration of the processing reached by the parallelism inherent to the hardware design, the high level of integration, the consequent security and reliability improvements provided by the usage of a system-on-programmable-chip device that is able to embed the main components of the application in a single chip, and the low cost achieved by the whole system due to the reconfigurability performance featured by the suggested FPGA. All these factors result in an outstanding system that is able to authenticate the identity of any user by means of those distinctive characteristics available in fingerprints. This brief reveals the advantages of run-time reconfigurable hardware in the implementation of those embedded systems demanding real-time performance at low cost. The minimization of the reconfiguration overhead by means of the proper sizing of the reconfigurable region in the FPGA and the design of a hardware configuration controller that is able to reach the maximum configuration rates allowed by the technology (3.2 Gb/s) are key factors to succeed in the development of the embedded AFAS application. The proposed system, which is implemented by means of hardware-software co-design techniques under a Virtex4 XC4VLX25 FPGA working at 100 MHz, is able to overcome in one order of magnitude the execution time performance achieved by a personal computer platform based on an Intel Core2Duo microprocessor running at 1.83 GHz. <s> BIB004 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> The OpenCL standard offers a common API for program execution on systems composed of different types of computational devices such as multicore CPUs, GPUs, or other accelerators. <s> BIB005 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> In this paper we develop a parallelized iris template matching implementation on inexpensive Graphics Processing Units (GPUs) with Nvidia's CUDA programming model to achieve matching rates of 44 million iris template comparisons per second without rotation invariance. With tolerance to head tilt, we achieve 4.2 million matches per second and compare our implementation to state of the art prior work performed on GPU and FPGA, emphasizing our improvements. Additionally a comparison to highly optimized CPU implementations of iris template matching is performed, showing a 14X speedup using our approach. In contrast to other published work, we develop an implementation for parallel iris template matching that incorporates iris code shifting for rotation invariance and provide timing data showing our proposed architecture is efficiently implemented, capitalizing on shared and texture memory to speedup the bit shifting process beyond current prior art. <s> BIB006 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> This paper describes the implementation of an iris recognition algorithm based ::: on hardware-software co-design. The system architecture consists of a general-purpose 32- ::: bit microprocessor and several slave coprocessors that accelerate the most intensive ::: calculations. The whole iris recognition algorithm has been implemented on a low-cost ::: Spartan 3 FPGA, achieving significant reduction in execution time when compared to a ::: conventional software-based application. Experimental results show that with a clock ::: speed of 40 MHz, an IrisCode is obtained in less than 523 ms from an image of 640x480 ::: pixels, which is just 20% of the total time needed by a software solution running on the ::: same microprocessor embedded in the architecture. <s> BIB007 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field. <s> BIB008 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> Both face detection and face recognition have started to be used widely these days in various applications such as biometric, surveillance, security, advertisement, entertainment, and so on. The ever increasing input image size in face detection and the large input DB in face recognition keep requiring more computational power to achieve real-time processing. Recently, embedded GPUs have started to support OpenCL and many applications can be accelerated successfully as the server GPUs have. In this paper, we propose several optimization techniques for the Local Binary Pattern (LBP) based integrated face detection and recognition algorithms, and successfully accelerated them achieving 22 fps using OpenCL on ARM Mali GPU, and 38 fps using CUDA on Tegra K1 GPU for HD inputs. This corresponds to 2.9 times and 3.7 times speedups respectively. To the best of our knowledge, it is the first paper that presents the acceleration of the face detection on embedded GPGPUs, and also that presents the performance of Tegra K1 GPU. <s> BIB009 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> Sclera vein recognition is shown to be a promising method for human identification. However, its matching speed is slow, which could impact its application for real-time applications. To improve the matching efficiency, we proposed a new parallel sclera vein recognition method using a two-stage parallel approach for registration and matching. First, we designed a rotation- and scale-invariant Y shape descriptor based feature extraction method to efficiently eliminate most unlikely matches. Second, we developed a weighted polar line sclera descriptor structure to incorporate mask information to reduce GPU memory cost. Third, we designed a coarse-to-fine two-stage matching method. Finally, we developed a mapping scheme to map the subtasks to GPU processing units. The experimental results show that our proposed method can achieve dramatic processing speed improvement without compromising the recognition accuracy. <s> BIB010 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> Reconfigurable architectures can bring unique capabilities to computational tasks. They offer the performance and energy efficiency of hardware with the flexibility of software. In some domains, they are the only way to achieve the required, real-time performance without fabricating custom integrated circuits. Their functionality can be upgraded and repaired during their operational lifecycle and specialized to the particular instance of a task. We survey the field of reconfigurable computing, providing a guide to the body-of-knowledge accumulated in architecture, compute models, tools, run-time reconfiguration, and applications. <s> BIB011 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> Nowadays, security is needed in every field for variety of applications. Securing personal information as well as personal verification is becoming a critical key problem because of continuous development in the field of electronics. Due to this fact, the biometric authentication has gaining popularity as it provides a high security and reliable approach for personal authentication. Biometrics is an automated recognition of an individual based on uniqueness of their biological or behavioral characteristics. Currently, there are variety of biometric systems like face, fingerprint and voice. However, these systems have some shortcomings like they can be easily duplicated. Finger vein biometric is advantageous over these biometric systems because it has low forgery rate, aliveness detection as well as stable over long period of time. Researchers in this field shows that Hardware based approach are well suited for developing highly secure system as they results in high performance and also low cost. The proposed work deals with the development of person authentication system based on finger vein patterns, which is implemented in Field Programmable Gate Array (FPGA). The paper presents the image processing algorithm and Feature extraction process are implemented in MATLAB. And for final authentication the template matching is carried out on Field Programmable Gate Array (FPGA) for fast recognition. The system is prototyped on Papilio one 500k FPGA board which has Xilinx Spartan 3E chip inside. The performance of the proposed system is evaluated by the time required to verify one input finger vein sample and Precision. <s> BIB012 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> As both CPUs and GPUs become employed in a wide range of applications, it has been acknowledged that both of these Processing Units (PUs) have their unique features and strengths and hence, CPU-GPU collaboration is inevitable to achieve high-performance computing. This has motivated a significant amount of research on heterogeneous computing techniques, along with the design of CPU-GPU fused chips and petascale heterogeneous supercomputers. In this article, we survey Heterogeneous Computing Techniques (HCTs) such as workload partitioning that enable utilizing both CPUs and GPUs to improve performance and/or energy efficiency. We review heterogeneous computing approaches at runtime, algorithm, programming, compiler, and application levels. Further, we review both discrete and fused CPU-GPU systems and discuss benchmark suites designed for evaluating Heterogeneous Computing Systems (HCSs). We believe that this article will provide insights into the workings and scope of applications of HCTs to researchers and motivate them to further harness the computational powers of CPUs and GPUs to achieve the goal of exascale performance. <s> BIB013 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> Despite significant recent advances in the field of face recognition [10, 14, 15, 17], implementing face verification and recognition efficiently at scale presents serious challenges to current approaches. In this paper we present a system, called FaceNet, that directly learns a mapping from face images to a compact Euclidean space where distances directly correspond to a measure of face similarity. Once this space has been produced, tasks such as face recognition, verification and clustering can be easily implemented using standard techniques with FaceNet embeddings as feature vectors. <s> BIB014 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> As one of the most important deep learning models, convolutional neural networks (CNNs) have achieved great successes in a number of applications such as image classification, speech recognition and nature language understanding. Training CNNs on large data sets is computationally expensive, leading to a flurry of research and development of open-source parallel implementations on GPUs. However, few studies have been performed to evaluate the performance characteristics of those implementations. In this paper, we conduct a comprehensive comparison of these implementations over a wide range of parameter configurations, investigate potential performance bottlenecks and point out a number of opportunities for further optimization. <s> BIB015 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> Convolutional Neural Networks (CNNs) have a broad range of applications, such as image processing and natural language processing. Inspired by the mammalian visual cortex, CNNs have been shown to achieve impressive results on a number of computer vision challenges, but often with large amounts of processing power and no timing restrictions. This paper presents a design methodology for accelerating CNNs using Hardware/Software Co-design techniques, in order to balance performance and flexibility, particularly for resource-constrained systems. The methodology is applied to a gender recognition case study, using an ARM processor and FPGA fabric to create an embedded system that can process facial images in real-time. <s> BIB016 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> Authentication technologies based on biometrics, such as speaker recognition, are attracting more and more interest thanks to the elevated level of security offered by these technologies. Despite offering many advantages, such as remote use and low vulnerability, speaker recognition applications are constrained by the heavy computational effort and the hard real-time constraints. When such applications are run on an embedded platform, the problem becomes more challenging, as additional constraints inherent to this specific domain are added. In the literature, different hardware architectures were used/designed for implementing a process with a focus on a given particular metric. In this article, we give a survey of the state-of-the-art works on implementations of embedded speaker recognition applications. Our aim is to provide an overview of the different approaches dealing with acceleration techniques oriented towards speaker and speech recognition applications and attempt to identify the past, current, and future research trends in the area. Indeed, on the one hand, many flexible solutions were implemented, using either General Purpose Processors or Digital Signal Processors. In general, these types of solutions suffer from low area and energy efficiency. On the other hand, high-performance solutions were implemented on Application Specific Integrated Circuits or Field Programmable Gate Arrays but at the expense of flexibility. Based on the available results, we compare the application requirements vis-a-vis the performance achieved by the systems. This leads to the projection of new research trends that can be undertaken in the future. <s> BIB017 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> To confirm an individual's identity accurately and reliably iris recognition systems analyse the texture that is visible in the iris of the eye. The rich random pattern of the iris constitutes a powerful biometric characteristic suitable for biometric identification in large-scale deployments. Identification attempts or deduplication checks require an exhaustive one-to-many comparison. Hence, for large-scale biometric databases with millions of enrollees, the time required for a biometric identification is expected to significantly increase. In this study, the authors analyse techniques to accelerate Hamming distance-based comparisons of binary biometric reference data, i.e. iris-codes, in large-scale iris recognition systems, which preserve the biometric performance. The focus is put on software-based optimisations, an efficient two-step iris-code alignment process referred to as TripleA, and a combination thereof. Benchmarking the throughput and identifying potential bottlenecks of a portable commodity hardware-based iris recognition system is of particular interest. Based on the conducted experiments the authors point out practical boundaries of large-scale comparisons in central processing unit-based iris recognition systems, bridging the gap between the fields of iris recognition and software design. <s> BIB018 </s> Computational workload in biometric identification systems: an overview <s> Acceleration <s> Large-scale biometric deployments are becoming ubiquitous. The computational workload of the conventional retrieval method, requiring 1:N comparisons in the identification mode, is impractical for such systems. In recent years, many approaches for efficient biometric identification were proposed, but their scalability is often questionable. Furthermore, the lack of a unified methodology for biometric workload reduction reporting often makes a direct benchmark or a thorough evaluation of the proposed schemes cumbersome. We present an iris indexing scheme based on Bloom filters and binary search trees. With a statistical model, the system is shown to be theoretically scalable for arbitrarily many enrollees. We evaluate this system on a combined database from several publicly available datasets, containing a total of 11,936 iris images from 1477 instances. In an open-set identification scenario, the system maintains the biometric performance of an iris-code 1:N baseline – a true positive identification rate of approximately 98% measured at 0.1% false positive identification rate, at only 10% of the baseline workload. In a proof-of-concept multi-iris indexing experiment, the true positive identification rate is further increased to over 99%, without additional workload costs. Lastly, we define several prerequisites necessary for a transparent and comprehensive methodology of biometric workload reduction results dissemination. <s> BIB019
Hardware acceleration can facilitate massive execution speed gains for certain types of computations. In the following subsections, the use of reconfigurable computing (subsection 3.6.1) and graphical processing units (subsection 3.6.2) in biometric systems is surveyed. The references in those two subsections are by no means exhaustive, due to the focus of this article being elsewhere. Instead, they outline the relevant concepts and highlight a few systems created for the different biometric characteristics. Lastly, they focus on the more recent publications due to the fast pace of developments within hardware components. For a quick general comparison of the capabilities, along with the advantages and disadvantages of those two types of hardware, the reader is referred to e.g. an industry white paper in  , or a general survey of various Big Data analysis platforms and methods  . Although hardware acceleration cannot be strictly considered a method of workload reduction (since the amount of computations is not reduced -it is merely parallelised, distributed, or executed more efficiently), it is also mentioned here as an important aspect of speeding-up transactions in large-scale biometric identification systems. There appears to be a substantial research interest in the area of hardware-based acceleration utilising FPGAs and GPUs. Some of the existing publications present convincing and well-substantiated results, whereby massive speed gains (up to two orders of magnitude) are achieved in the benchmarks. It should be noted, however, that in some cases the experimental protocols of the benchmarks are questionable; in particular, it is not always clear if the external latency factors (unrelated to the algorithms themselves) have been accounted for in the evaluation. Furthermore, the degree of the CPUbased baseline algorithm optimisation is often not clearly outlined. The results must therefore be closely scrutinised, as it could be that the speed gains result merely from a poor baseline implementation. This caveat notwithstanding, using reconfigurable computing and/or graphical processing units could be a promising avenue for speeding up the execution of various components (or even entire pipelines) in many different biometric modalities. On the other hand, factors such as difficulty of implementation, as well as purchase and maintenance cost have to be taken into consideration for real-world systems. Lastly, software acceleration and optimisation are also worth mentioning in this context; although there does not seem to be many scientific publications on the topic. In BIB018 , an extensive analysis of possible speed-ups in CPU-based Iris-Code comparisons is presented. The authors consider possible improvements through low-level implementations, manual loop unrolling, caching and pre-computing certain parts of data, analysis of memory access bottlenecks, multi-threading, as well as statistical optimisation of micro-operations. In BIB007 , a hardware-software co-design of iris recognition pipeline is proposed. The authors benchmark highly optimised software code, coupled with a hardware-based implementation of several of the pipeline components. Both publications show that substantial speed-ups (but not computational workload reduction) can be achieved through code optimisations, which do not in themselves change the underlying algorithms or biometric feature representations. 3.6.1 Reconfigurable Computing: Field Programmable Gate Arrays (FPGAs) are integrated circuits containing an array/matrix of programmable logic blocks (of different types, e.g. general logic, memory, arithmetic), which can be programmably interconnected with each other and with input/output blocks. The programming/configuring is generally done using a hardware description language (e.g. VHDL or Verilog) or (nowadays rarely) circuit diagrams, and takes place after the chip has been manufactured. In other words, the FPGAs can be configured and re-configured to execute arbitrary digital circuits, and thus are capable of solving any computable problem. FPGAs can utilise hardware parallelism and deep pipelining extensively, thereby completing many more computations per clock cycle as opposed to a normal sequential execution. Additionally, they rely on much fewer layers of abstraction than the general purpose CPUs, thus facilitating lower-level programming, as well as custom memory and I/O interfaces. Those properties can be exploited to yield potentially massive speed-ups for certain applications (see e.g. BIB002  ). For a more detailed view of the current FPGA state-of-the-art, advantages and disatvantages, as well as future outlook and challenges, the reader is referred to fundamentals, e.g.  . Due to the abovementioned advantages, reconfigurable computing has been extensively applied to solve a variety of problems in many fields (see e.g. BIB011 for a survey), including computer vision, signal processing and pattern matching (see e.g. BIB008 ), and neural networks (see e.g. BIB016 ). Algorithms from those domains are cornerstones of various biometric systems; hence, substantial research effort has also been devoted to development of FPGA-based processing of biometric data. FPGA based implementations of biometric systems' components or complete data processing pipelines were published e.g. for iris  , fingerprint BIB004 , face  , (finger)vein BIB012 , retina  , and voice BIB017 . There, speed-ups over traditional CPU-based algorithms of up to two orders of magnitude were reported. 3.6.2 Graphical Processing Units: As the name suggests, traditional Graphical Processing Units (GPUs) were designed for very efficient processing of two and three dimensional graphics and have a rigid set of functions and programmable features. Over time, the ease of use/programmability and the range of applications for GPUs have steadily increased, especially with the introduction of general purpose frameworks for GPU programming such as CUDA BIB003 and OpenCL BIB005 . Taking advantage of the single program multiple-data (SPMD) programming model, the data can be processed in highly parallel ways. Thus, adapting code to run on GPUs can yield massive execution speed gains for many applications, e.g. linear algebra, sorting and searching, differential equations, or more generally floating-point operations on vectorisable data. For a general introduction to GPU computing, the reader is referred to e.g. BIB013 . Some tasks at which GPUs excel are important in typical biometric processing pipelines. Hence, there has been interest in the scientific community to leverage the power of GPUs in this domain as well. A good general introduction to usage of GPUs in biometrics, along with a brief survey of applications for fingerprint-based systems can be found in  . GPU based implementations of biometric systems' components or complete data processing pipelines were reported. It should also be noted, that GPUs (and more recently, specialised tensor processing units (TPUs)  ), have also been utilised extensively in problems involving machine learning and deep neural networks, see e.g. BIB015 . In recent years, those technologies have also been applied to biometrics (e.g. facial recognition deep neural networks BIB014 ), highlighting possibilities of hardware-acceleration use beyond efficient biometric identification, more specifically in the algorithm training phase. E.g. for iris BIB006 , fingerprint  , face BIB009 , and sclera-vein BIB010 , similarly to FPGAs (see subsection 3.6.1), speedups over traditional CPU-based algorithms of up to two orders of magnitude were reported. Computational workload Not reduced per se, merely computed more efficiently (e.g. paralellised, distributed, or otherwise optimised). Biometric performance Typically unaffected, as functionally equivalent algorithms are somehow implemented or optimised to achieve faster computation speeds. Storage Possibly increased, as it may be necessary to port the biometric data to the specifics of the utilised system (e.g. CUDA) or distribute them across a network. Due to varying system requirements and policies, it is important to enable the biometric systems' operators to make well-informed decisions w.r.t. the used algorithms. Therefore, for any proposed computational workload reduction methods, it is crucial to include the above information, as well as benchmarks against a current state-of-the-art algorithm performing an exhaustive search (baseline). By doing so, the trade-offs (biometric performance, computational workload, storage) of the proposed methods can be evaluated, thereby facilitating informed decisions on the systems' design and policies. In some cases, it may even be possible to probabilistically model the impact of the proposed methods on the biometric performance, which could potentially be very useful in establishing the pertinent trade-offs even prior to the experimental evaluations on real data. However, such models rarely appear in the surveyed literature. Examples include, e.g. BIB001 , which discusses the binning approaches in general and BIB019 , where a statistical model for the proposed Bloom filter-based hierarchical retrieval method is included. Hence, the development of such models could be an interesting avenue of future research.