A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> A simple observation, made over 30 years ago, on the growth in the number of devices per silicon die has become the central driving force of one of the most dynamic of the world's industries. Because of the accuracy with which Moore's Law has predicted past growth in IC complexity, it is viewed as a reliable method of calculating future trends as well, setting the pace of innovation, and defining the rules and the very nature of competition. And since the semiconductor portion of electronic consumer products keeps growing by leaps and bounds, the Law has aroused in users and consumers an expectation of a continuous stream of faster, better, and cheaper high-technology products. Even the policy implications of Moore's Law are significant: it is used as the baseline assumption in the industry's strategic road map for the next decade and a half. <s> BIB001 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> The continuation of the remarkable exponential increases in processing power over the recent past faces imminent challenges due in part to the physics of deep-submicron CMOS devices and the costs of both chip masks and future fabrication plants. A promising solution to these problems is offered by an alternative to CMOS-based computing, chemically assembled electronic nanotechnology (CAEN). In this paper we outline how CAEN-based computing can become a reality. We briefly describe recent work in CAEN and how CAEN will affect computer architecture. We show how the inherently reconfigurable nature of CAEN devices can be exploited to provide high-density chips with defect tolerance at significantly reduced manufacturing costs. We develop a layered abstract architecture for CAEN-based computing devices and we present preliminary results which indicate that such devices will be competitive with CMOS circuits. <s> BIB002 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> Molecular electronics offer an alternative pathway to construct nanoscale circuits in which the critical dimension is naturally associated with molecular sizes. We describe the fabrication and testing of nanoscale molecular-electronic circuits that comprise a molecular monolayer of [2]rotaxanes sandwiched between metal nanowires to form an 8 × 8 crossbar within a 1 µm 2 area. The resistance at each cross point of the crossbar can be switched reversibly. By using each cross point as an active memory cell, crossbar circuits were operated as rewritable, nonvolatile memory with a density of 6. 4G bits cm −2 .B ys etting the resistances at specific cross points, two 4 × 4s ubarrays of the crossbar were configured to be a nanoscale demultiplexer and multiplexer that were used to read memory bits in a third subarray. <s> BIB003 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> Future electronic systems will need to adopt novel nanoelectronic solutions to keep pace with Moore's Law. Crossbar-based molecular electronics are among the most promising of nanotechnologies. However, circuits similar to the conventional mainstream electronics of today will have a presence in future complex systems for some time. This paper presents a circuit paradigm where silicon and molecular electronics are integrated. We discuss methods for realizing memory and logic using nanoscale crossbars as well as for interfacing the crossbars to CMOS circuitry. Using custom nanoscale device models, we perform circuit simulation and analysis of the crossbar circuits and the peripheral CMOS circuitry. Finally, we present a design methodology to accompany the CMOS/nano paradigm. <s> BIB004 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm. <s> BIB005 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> This paper describes a digital logic architecture for ‘CMOL’ hybrid circuits which combine a semiconductor–transistor (CMOS) stack and two levels of parallel nanowires, with molecular-scale nanodevices formed between the nanowires at every crosspoint. This cell-based, field-programmable gate array (FPGA)-like architecture is based on a uniform, reconfigurable CMOL fabric, with four-transistor CMOS cells and two-terminal nanodevices (‘latching switches’). The switches play two roles: they provide diode-like I –V curves for logic circuit operation, and allow circuit mapping on CMOL fabric and its reconfiguration around defective nanodevices. Monte Carlo simulations of two simple circuits (a 32-bit integer adder and a 64-bit full crossbar switch) have shown that the reconfiguration allows one to increase the circuit yield above 99% at the fraction of bad nanodevices above 20%. Estimates have shown that at the same time the circuits may have extremely high density (approximately 500 times higher than that of the usual CMOS FPGAs with the same design rules), while operating at higher speed at acceptable power consumption. (Some figures in this article are in colour only in the electronic version) <s> BIB006 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> We have developed a process to fabricate a cross-bar structure using UV-curable nanoimprint lithography with a UV-curable double-layer spin-on resist, metal lift off and Langmuir–Blodgett film deposition. This process allowed us to produce 1-kbit cross-bar memory circuits at 30-nm half-pitch on both top and bottom electrodes. Read, write, erase and cross talking were also investigated. <s> BIB007 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> The rapid progress of manufacturing nanoscale devices is pushing researchers to explore appropriate nanoscale computing architectures for high density beyond the physical limitations of conventional lithography. However, manufacturing and layout constraints, as well as high defect/fault rates expected in nanoscale fabrics, could make most device density lost when integrated into computing systems. Therefore, a nanoscale architecture that can deal with those constraints and tolerate defects/faults at expected rates, while still retaining the density advantage, is highly desirable. In this paper, we describe a novel nanoscale architecture based on semiconductor nanowires: NASICs (nanoscale application specific ICs). NASIC is a tile-based fabric built on 2-D nanowire grids and NW FETs. WISP-0 (wire streaming processor) is a processor design built on NASIC fabric where NASIC design principles and optimizations are applied. Built-in fault tolerance techniques are applied on NASICs designs to tolerate defects/faults on-the-fly. Evaluations show that compared with the equivalent CMOS design with 18 nm process (the most advanced technology expected in 2018), WISP-0 with combined built-in redundancy could be still 2~3X denser. Its yield would be 98% if the defect rate of transistors is 5%, and 77% for 10% defective transistors. <s> BIB008 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> While most of the electronics industry is dependent on the ever-decreasing size of lithographic tran- sistors, this scaling cannot continue indefinitely. Nanoelectro- nics (circuits built with components on the scale of 10 nm) seem to be the most promising successor to lithographic based ICs. Molecular-scale devices including diodes, bistable switches, carbon nanotubes, and nanowires have been fab- ricated and characterized in chemistry labs. Techniques for self-assembling these devices into different architectures have also been demonstrated and used to build small-scale proto- types. While these devices and assembly techniques will lead to nanoscale electronics, they also have the drawback of being prone to defects and transient faults. Fault-tolerance techni- ques will be crucial to the use of nanoelectronics. Lastly, changes to the software tools that support the fabrication and use of ICs will be needed to extend them to support nano- electronics. This paper introduces nanoelectronics and reviews the current progress made in research in the areas of tech- nologies, architectures, fault tolerance, and software tools. <s> BIB009 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> In a significant step forward in complexity and capability for bottom-up assembly of nanoelectronic circuits, this study demonstrates scalable and programmable logic tiles based on semiconductor nanowire transistor arrays. The same logic tile, consisting 496 configurable transistor nodes in an area of about 960 μm2, could be programmed and operated as, among other functions, a full-adder, full-subtractor and multiplexer. The promise is that these logic tiles can be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities. <s> BIB010 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> This outstanding textbook provides an introduction to electronic materials and device concepts for the major areas of current and future information technology. On about 1,000 pages, it collects the fundamental concepts and key technologies related to advanced electronic materials and devices. The obvious strength of the book is its encyclopedic character, providing adequate background material instead of just reviewing current trends. It focuses on the underlying principles which are illustrated by contemporary examples. The third edition now holds 47 chapters grouped into eight sections. The first two sections are devoted to principles, materials processing and characterization methods. Following sections hold contributions to relevant materials and various devices, computational concepts, storage systems, data transmission, imaging systems and displays. Each subject area is opened by a tutorial introduction, written by the editor and giving a rich list of references. The following chapters provide a concise yet in-depth description in a given topic. Primarily aimed at graduate students of physics, electrical engineering and information technology as well as material science, this book is equally of interest to professionals looking for a broader overview. Experts might appreciate the book for having quick access to principles as well as a source for getting insight into related fields. <s> BIB011 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> This Review looks at recent progress in the development and understanding of memristive devices, and examines the performance requirements for computing with such devices. <s> BIB012 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> As the CMOS technology is gradually scaling down to inherent physical device limits, significant challenges emerge related to scalability, leakage, reliability, etc. Alternative technologies are under research for next-generation VLSI circuits. Memristor is one of the promising candidates due to its scalability, practically zero leakage, non-volatility, etc. This paper proposes a novel design methodology for logic circuits targeting memristor crossbars. This methodology allows the optimization of the design of logic function, and their automatic mapping on the memristor crossbar. More important, this methodology supports the execution of Boolean logic functions within constant number of steps independent of its functionality. To illustrate the potential of the proposed methodology, multi-bit adders and multipliers are explored; their incurred delay, area and energy costs are analyzed. The comparison of our approach with state-of-the-art Boolean logic circuits for memristor crossbar architecture shows significant improvement in both delay (4 to 500 x) and energy consumption (1.22 to 3.71 x). The area overhead may decrease (down to 44%) or increase (up to 17%) depending on the circuit's functionality and logic optimization level. <s> BIB013 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> This work is part of a project that has received funding from the ::: European Union’s H2020 research and innovation programme under the ::: Marie Sklodowska-Curie grant agreement No 691178, and supported by the ::: TUBITAK-Career project #113E760 <s> BIB014 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> INTRODUCTION <s> Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements both arithmetic and memory elements, necessitated by achieving a computer, by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of arithmetic and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of "Emerging Computing Models" or "Computational Nanoelectronics", more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS. <s> BIB015
Since the first digital computer was developed in 1930s, several breakthroughs have been made both in technological and computational levels to improve the performance of computers. Researchers have aimed at finding the best way to realize the fundamental building element of computers that is a two-terminal switch. First, electromechanical systems and then, respectively, vacuum tubes, p-n junction-based diodes and transistors, and CMOS transistors are used as switches. Considering these different eras, without question the CMOS era is the longest prevailing and the 79:2 O. Tunali and M. Altun most fruitful one. For more than 50 years, CMOS computing performance has increased almost in a regular manner that is often called Moore's law BIB001 . However, this trend has started to slow down, and it is widely accepted that another transition to a new era is soon to occurr   . At this point, a significant amount of research has been dedicated to nanoscale technologies with new materials including nanotubes, nanowires, and individual molecules being used to implement a switch BIB011 . Although computing performances of these individual switches are quite satisfactory, generally much better than those of CMOS, there are still problems to be solved before the commercialization: (1) Integration of individual switching elements to generate a fully functional computing architecture is quite costly, and (2) the final forms of architectures are not immune to unusually high fault rates. In this regard, nano-crossbar arrays have been favored by researchers such as nanofabric using molecular switches (programmable diodes) BIB002 , nanoPLA using programmable diode BIB005 , CMOS-like structures using nFET or pFET transistors (Snider et al. 2005) , CMOL using programmable diodes BIB006 , NASIC using FET transistors or diodes BIB008 BIB014 BIB015 . Another prospective technology is based on memristors or memristive switches that are constructed as crossbarlike structures BIB012 ) and having the same logic mapping approach BIB013 . Moreover, as a physical realization, three fully operational implementations of nano-crossbar arrays as nanocomputers are shown to be feasible in BIB010 , Shulaker et al. (2013) , and . Even though these technologies differ in certain levels, basic computing blocks are always crossbars with each crosspoint behaving as a switch, so logic mapping schemes are similar. Arrays offer both structural efficiency with reconfiguration and prospective capability of integration. In addition, inherent redundancy present in nano-crossbars provides flexibility for fault tolerance that is much needed considering that fault tolerance is the main challenge to be resolved. Fault rate projections of nano-crossbars are as high as 20%, which is much higher than those of CMOS due mainly to the used bottom-up fabrication techniques with self-assembly that has stochastic nature as opposed to using conventional top-down fabrication techniques with directed assembly BIB007  BIB003 BIB009 . Therefore, it is fair to expect sophisticated fault-tolerance methods for nano-crossbars. The focus of this survey article is the assessment and evaluation of fault-tolerance methods and related algorithms applied in logic mapping and configuration processes of nano-crossbar arrays. Prior to examining fault-tolerance techniques in the literature, a very coarse description of a common crossbar structure and its computing fundamentals can be summarized as follows. Nanocrossbar arrays are formed by placing a group of lines/wires aligned parallel to each other on another group of array lines/wires orthogonally. Vertical and horizontal lines are used as input and outputs, respectively. This is illustrated in Figure 1 (a). Boolean literals are applied to input lines, and each output line corresponds to a product, that is, AND of literals. Therefore a given function in sum-of-products form can be directly implemented by using each product with an output line by deactivating and activating relevant crosspoints. Note that other forms based on factored Boolean expressions or binary decision diagrams cannot be used, since these forms require certain wirings/connections between lines and crosspoints that is not applicable for nano arrays BIB005 Snider et al. 2005; BIB015 . While a deactivated crosspoint behaves as an open circuit between the crossed lines, an activated crosspoint is a two-terminal switch that can behave as a diode BIB004 or a FET  . This is shown in Figure 1 (b) . If the components are ON (OFF), then their terminals are shorted (open) . Note that the distinction of the components is that their ON (OFF) states connect (disconnect) terminals in different lines. 