A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Fault Tolerance in Nano-Crossbar Arrays <s> In reluctance motors having rotors with segmentally disposed, axially extended, radially laminated stacks of steel strips carried on a conducting core, improved synchronous performance and increased asynchronous torque are achieved when the rotors are modified to associate only one segmental body with each pair of adjacent MMF poles of the stator field. The modification is actually a simplification, namely the span of each segmental body is peripherally extended to nearly the span of two adjacent stator poles, whereby the steel laminae carry a higher peak magnetic flux centered on the strips lying at the radial mid-depth position of a stack. A higher total flux is also realized and the flux distribution in the air gap is more nearly sinusoidal, lacking the gaps characterizing flux patterns of prior art rotors. Odd-numbered harmonic coefficients of the flux distribution are thus minimized. Considerable savings in construction are also realized. Motors are described ranging from one pair of rotor poles up to four pairs, although the invention extends to any practicable higher pole numbers. <s> BIB001 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Fault Tolerance in Nano-Crossbar Arrays <s> Lithography-based integrated circuit fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology-based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully crafted defect tolerance techniques. This paper presents an algorithm for reconfiguration-based defect tolerance in nanotechnology switches. The algorithm offers an average switch density improvement of 50% to 100% to most recently published techniques. The algorithm is also consistent in improving the yield through minimizing false rejects as the results show over a large sample. The improvement percentage varies depending on the manufactured switch size and the desired defect-free size with the improvement in efficiency directly proportional to the size of the switch. <s> BIB002 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Fault Tolerance in Nano-Crossbar Arrays <s> It is widely acknowledged that nanoelectronic devices will suffer from more manufacturing and operational faults than classical CMOS devices in large-scale integrated circuits. The confident use of these emerging technologies relies on our capacity to better understand their fault mechanisms, and our ability to deduce related fault models. These challenging goals are addressed in this paper for nanowire logic circuits, which constitute one of the most promising technologies in the nanoelectronics realm. Fault models are proposed attending to how fault mechanisms manifest at device and logic <s> BIB003 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Fault Tolerance in Nano-Crossbar Arrays <s> Programmable logic arrays (PLAs) using self-assembly nanowire crossbars have shown promising potential for future nano-scale circuit design. However, due to the density and size factors of nanowires and molecular switches, the fabrication fault densities are much higher than those of the conventional silicon technology, and hence pose greater design challenges. In this paper, we propose a novel defect-aware logic mapping framework via Boolean satisfiability (SAT). Compared with the prior works, our technique considers PLA defects on both input and output planes at the same time. This synergistic approach can help solve logic mapping problems with higher defect rates. The proposed method is universally suitable for various nano-scale PLAs, including AND/OR, NOR/NOR structures, etc. The experimental results have shown that it can efficiently solve large mapping problems at a total defect rate of 20% or even higher. We further investigate the impact of different defects on PLA mapping, which helps set up an initial contribution for yield estimation and utilization of partially-defective PLAs. <s> BIB004 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Fault Tolerance in Nano-Crossbar Arrays <s> Nanocrossbars (i.e., nanowire crossbars) offer extreme logic densities but come with very high defect rates; stuck-open/closed, broken nanowires. Achieving reasonable yield and utilization requires logic mapping that is defect-aware even at the crosspoint level. Such logic mapping works with a defect map per each manufactured chip. The problem can be expressed as matching of two bipartite graphs; one for the logic to be implemented and other for the nanocrossbar. This article shows that the problem becomes a Bipartite SubGraph Isomorphism (BSGI) problem within sub-nanocrossbars free of stuck-closed faults. Our heuristic KNS-2DS is an iterative rough canonizer with approximately O(N2) complexity followed by an O(N3) matching algorithm. Canonization brings a partial or full order to graph nodes. It is normally used for solving the regular Graph Isomorphism (GI) problem, while we apply it to BSGI. KNS stands for K-Neighbor Sort and is used for initializing our main contribution 2-Dimensional-Sort (2DS). 2DS operates on the adjacency matrix of a bipartite graph. Radix-2 2DS solves the problem in the absence of stuck-closed faults. With the addition of Radix-3 and our novel Radix-2.5 sort, we solve problems that also have stuck-closed faults. We offer very short runtimes (due to canonization) compared to previous work and have success on all benchmarks. KNS-2DS is also novel from the perspective of BSGI problem as it is based on canonization but not on a search tree with backtracking. <s> BIB005 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Fault Tolerance in Nano-Crossbar Arrays <s> Several emerging nano-technologies, including crossbar nano-architectures, have recently been studied as possible replacement or supplement to CMOS technology in the future. However, extreme process variation and high failure rates, mainly due to atomic device sizes, are major challenges for crossbar nano-architectures. This article presents variation- and defect-tolerant logic mapping on crossbar nano-architectures. Since variation/defect-aware mapping is an NP-hard problem, we introduce a set of Integer Linear Programming (ILP) formulations to effectively solve the problem in a reasonable time. The proposed ILP formulations can be used for both diode-based and FET-based crossbars. Experimental results on benchmark circuits show that our approach can reduce the critical-path delay 39p compared to the Simulated Annealing (SA) method. It can also successfully achieve 97p defect-free mapping with 40p defect density. It can tolerate process variations to meet timing constraints in 95p of the cases, compared to only 77p achieved by SA. <s> BIB006 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Fault Tolerance in Nano-Crossbar Arrays <s> Nanoelectronics are inherently defect prone, and defect-tolerant logic implementation has emerged as a new foundation to form reliable systems. Crossbar-based architectures have been shown to be promising in future nanoelectronic systems, with most of the existing defect tolerance approaches based on logic mapping. Essentially, mapping-based schemes exploit the freedom of choosing which variables/products (in a logic function) to map to which of the vertical/horizontal wires (in a crossbar). In this paper, we expand the realm of defecting tolerant logic implementation by introducing two approaches orthogonal to mapping-based schemes, namely, logic morphing and fine-grained fine-tuned logic hardening. Logic morphing exploits the various equivalent forms of a logic function to tolerate defects, while calculated logic hardening adds redundancies to make the hardened logic function inherently defect tolerable. A new integrated framework is proposed to utilize the two new schemes while not sacrificing existing mapping-based techniques. The algorithms in the framework can efficiently search for a successful logic implementation in the combined solution space. Simulation results show that the proposed integrated framework boost defect tolerance capability significantly with 2-10 yield improvement, while adding no runtime overhead on top of the basic mapping algorithm. <s> BIB007 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Fault Tolerance in Nano-Crossbar Arrays <s> This paper studies fault tolerance in switching reconfigurable nano-crossbar arrays. Both permanent and transient faults are taken into account by independently assigning stuck-open and stuck-closed fault probabilities into crosspoints. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. The algorithm’s effectiveness is demonstrated on standard benchmark circuits in terms of runtime, success rate, and accuracy. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions. In this way, we are able to specify fault tolerance performances of nano-crossbars without relying on randomly generated faults that is relatively costly regarding that the number of fault distributions in a crossbar grows exponentially with the crossbar size. <s> BIB008
Examining the fault-tolerance techniques in the literature, we see a common tendency of considering faults causing only phase shifts between activated and deactivated crosspoints  BIB002 BIB004 BIB005 BIB007 BIB008 . Only a few studies consider faults affecting the functionality of electrical components in crosspoints that causes phase shifts between ON and OFF states of the components BIB001 BIB003 BIB006 ). Indeed, component-based fault modeling is more appropriate for failures seen in field, and this is not quite applicable for emerging technologies, because they have very limited field data including nano-crossbar arrays. Another reason favoring activated/deactivated crosspoint-based fault modeling is its capability to deal with faults occurring in input and output lines such as broken and bridging faults. For example, all crosspoints of a broken line can be modeled as deactivated. Another examination is that distinct approaches are proposed to tolerate permanent and transient faults regarding their exclusive natures as summarized in Table 1 . While permanent faults called as defects are related to the configuration of nano-crossbars that is performed during post fabrication, transient faults occurring in field are tolerated using either redundancies or detectionreconfiguration cycles.