Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> The past decade has seen the development of productive fast electronic digital computers. Significant problems have been solved and significant numerical experiments have been executed. Moreover, as expected, a growing number of important problems have been recorded which are not practicably computable by existing systems. These latter problems have provided the incentive for the present development of several large scale digital computers with the goal of one or two orders of magnitude increase in overall computational speed. <s> BIB001 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> A dynamic instruction set computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to implement an arbitrary number of performance-enhancing application-specific instructions. DISC further enhances the functional density of FPGAs by physically relocating instruction modules to available FPGA space. <s> BIB002 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> MATRIX is a novel, coarse-grain, reconfigurable computing architecture which supports configurable instruction distribution. Device resources are allocated to controlling and describing the computation on a per task basis. Application-specific regularity allows us to compress the resources allocated to instruction control and distribution, in many situations yielding more resources for datapaths and computations. The adaptability is made possible by a multi-level configuration scheme, a unified configurable network supporting both datapaths and instruction distribution, and a coarse-grained building block which can serve as an instruction store, a memory element, or a computational element. In a 0.5 /spl mu/ CMOS process, the 8-bit functional unit at the heart of the MATRIX architecture has a footprint of roughly 1.5 mm/spl times/1.2 mm, making single dies with over a hundred function units practical today. At this process point, 100 MHz operation is easily achievable, allowing MATRIX components to deliver on the order of 10 Gop/s (8-bit ops). <s> BIB003 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> High-frequency design and instruction-level parallelism (ILP) are important for high-performance microprocessor implementations. The Binary-translation Optimized Architecture (BOA), an implementation of the IBM PowerPC family, combines binary translation with dynamic optimization. The authors use these techniques to simplify the hardware by bridging a semantic gap between the PowerPC's reduced instruction set and even simpler hardware primitives. Processors like the Pentium Pro and Power4 have tried to achieve high frequency and ILP by implementing a cracking scheme in hardware: an instruction decoder in the pipeline generates multiple micro-operations that can then be scheduled out of order. BOA relies on an alternative software approach to decompose complex operations and to generate schedules, and thus offers significant advantages over purely static compilation approaches. This article explains BOA's translation strategy, detailing system issues and architecture implementation. <s> BIB004 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> We describe the design and implementation of Dynamo, a software dynamic optimization system that is capable of transparently improving the performance of a native instruction stream as it executes on the processor. The input native instruction stream to Dynamo can be dynamically generated (by a JIT for example), or it can come from the execution of a statically compiled native binary. This paper evaluates the Dynamo system in the latter, more challenging situation, in order to emphasize the limits, rather than the potential, of the system. Our experiments demonstrate that even statically optimized native binaries can be accelerated Dynamo, and often by a significant degree. For example, the average performance of -O optimized SpecInt95 benchmark binaries created by the HP product C compiler is improved to a level comparable to their -O4 optimized version running without Dynamo. Dynamo achieves this by focusing its efforts on optimization opportunities that tend to manifest only at runtime, and hence opportunities that might be difficult for a static compiler to exploit. Dynamo's operation is transparent in the sense that it does not depend on any user annotations or binary instrumentation, and does not require multiple runs, or any special compiler, operating system or hardware support. The Dynamo prototype presented here is a realistic implementation running on an HP PA-8000 workstation under the HPUX 10.20 operating system. <s> BIB005 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> The paper surveys a decade of R&D on coarse grain reconfigurable hardware and related CAD, points out why this emerging discipline is heading toward a dichotomy of computing science, and advocates the introduction of a new soft machine paradigm to replace CAD by compilation. <s> BIB006 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> Gerald Estrin and his group at the University of California at Los Angeles did the earliest work on reconfigurable computer architectures. The early research, described here, provides pointers to work on models and tools for reconfigurable systems design and analysis. <s> BIB007 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> Current embedded multimedia applications have stringent time and power constraints. Coarse-grained reconfigurable processors have been shown to achieve the required performance. However, there is not much research regarding the power consumption of such processors. In this paper, we present a novel coarse-grained reconfigurable processor and study its power consumption using a power model derived from Wattch. Several processor configurations are evaluated using a set of multimedia applications. Results show that the presented coarse-grained processor can achieve on average 2.5x the performance of a RISC processor with an 18% increase in energy consumption. <s> BIB008 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy consumption in embedded systems. Meanwhile, dynamic software optimization methods have shown the usefulness and feasibility of runtime program optimization, but those optimizations do not achieve as much as partitioning. We introduce a first approach to dynamic hardware/software partitioning. We describe our system architecture and initial on-chip tools, including profiler, decompiler, synthesis, and placement and routing tools for a simplified configurable logic fabric, able to perform dynamic partitioning of real benchmarks. We show speedups averaging 2.6 for five benchmarks taken from Powerstone, NetBench, and our own benchmarks. <s> BIB009 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> Architectures for mobile multimedia devices need to find a balance between energy-efficiency, flexibility and performance. In this paper it is reasoned that this can be accomplished by way of a System-on-Chip (SoC) that comprises heterogeneous processing tiles. This heterogeneous SoC calls for domain specific coarse-grained reconfigurable processing tiles. A design of a domain specific coarse-grained reconfigurable architecture, the Montium , is discussed in detail. <s> BIB010 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> In previous work, we showed the benefits and feasibility of having a processor dynamically partition its executing software such that critical software kernels are transparently partitioned to execute as a hardware coprocessor on configurable logic - an approach we call warp processing. The configurable logic place and route step is the most computationally intensive part of such hardware/software partitioning, normally running for many minutes or hours on powerful desktop processors. In contrast, dynamic partitioning requires place and route to execute in just seconds and on a lean embedded processor. We have therefore designed a configurable logic architecture specifically for dynamic hardware/software partitioning. Through experiments with popular benchmarks, we show that by specifically focusing on the goal of software kernel speedup when designing the FPGA architecture, rather than on the more general goal of ASIC prototyping, we can perform place and route for our architecture 50 times faster, using 10,000 times less data memory, and 1,000 times less code memory, than popular commercial tools mapping to commercial configurable logic. Yet, we show that we obtain speedups (2x on average, and as much as 4x) and energy savings (33% on average, and up to 74%) when partitioning even just one loop, which are comparable to commercial tools and fabrics. Thus, our configurable logic architecture represents a good candidate for platforms that will support dynamic hardware/software partitioning, and enables ultra-fast desktop tools for hardware/software partitioning, and even for fast configurable logic design in general. <s> BIB011 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in general-purpose and special-purpose design methods. It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications. <s> BIB012 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> Field programmable gate arrays (FPGAs) provide designers with the ability to quickly create hardware circuits. Increases in FPGA configurable logic capacity and decreasing FPGA costs have enabled designers to more readily incorporate FPGAs in their designs. FPGA vendors have begun providing configurable soft processor cores that can be synthesized onto their FPGA products. While FPGAs with soft processor cores provide designers with increased flexibility, such processors typically have degraded performance and energy consumption compared to hard-core processors. Previously, we proposed warp processing, a technique capable of optimizing a software application by dynamically and transparently re-implementing critical software kernels as custom circuits in on-chip configurable logic. In this paper, we study the potential of a MicroBlaze soft-core based warp processing system to eliminate the performance and energy overhead of a soft-core processor compared to a hard-core processor. We demonstrate that the soft-core based warp processor achieves average speedups of 5.8 and energy reductions of 57% compared to the soft core alone. Our data shows that a soft-core based warp processor yields performance and energy consumption competitive with existing hard-core processors, thus expanding the usefulness of soft processor cores on FPGAs to a broader range of applications. <s> BIB013 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> This paper provides an introductory overview of the Cell multiprocessor. Cell represents a revolutionary extension of conventional microprocessor architecture and organization. The paper discusses the history of the project, the program objectives and challenges, the disign concept, the architecture and programming models, and the implementation. <s> BIB014 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> This paper provides a background and rationale for some of the architecture and design decisions in the cell processor, a processor optimized for compute-intensive and broadband rich media applications, jointly developed by Sony Group, Toshiba, and IBM. The paper discusses some of the challenges microprocessor designers face and provides motivation for performance per transistor as a reasonable first-order metric for design efficiency. Common microarchitectural enhancements relative to this metric are provided. Also alternate architectural choices and some of its limitations are discussed and non-homogeneous SMP as a means to overcome these limitations is proposed. <s> BIB015 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> B. Reconfigurable Instruction Set Processors (RISP) <s> We describe a new processing architecture, known as a warp processor, that utilizes a field-programmable gate array (FPGA) to improve the speed and energy consumption of a software binary executing on a microprocessor. Unlike previous approaches that also improve software using an FPGA but do so using a special compiler, a warp processor achieves these improvements completely transparently and operates from a standard binary. A warp processor dynamically detects the binary's critical regions, reimplements those regions as a custom hardware circuit in the FPGA, and replaces the software region by a call to the new hardware implementation of that region. While not all benchmarks can be improved using warp processing, many can, and the improvements are dramatically better than those achievable by more traditional architecture improvements. The hardest part of warp processing is that of dynamically reimplementing code regions on an FPGA, requiring partitioning, decompilation, synthesis, placement, and routing tools, all having to execute with minimal computation time and data memory so as to coexist on chip with the main processor. We describe the results of developing our warp processor. We developed a custom FPGA fabric specifically designed to enable lean place and route tools, and we developed extremely fast and efficient versions of partitioning, decompilation, synthesis, technology mapping, placement, and routing. Warp processors achieve overall application speedups of 6.3X with energy savings of 66p across a set of embedded benchmark applications. We further show that our tools utilize acceptably small amounts of computation and memory which are far less than traditional tools. Our work illustrates the feasibility and potential of warp processing, and we can foresee the possibility of warp processing becoming a feature in a variety of computing domains, including desktop, server, and embedded applications. <s> BIB016
The idea of reconfigurable computing dates back to 1960 when Gerald Estrin at UCLA; presented BIB001 a model of a fixed machine with some variable (or configurable) structure BIB007 (see Fig. 9(a) ). Work in this area has progressed substantially, but it is only in recent years that reconfigurable architectures are considered as potential runners for the low power race. RISPs are rather different to mainstream processors; they consist of fixed, simple functional units and a reconfigurable logic fabric (see Fig. 9(b) ), that enables the software to modify the datapath as per requirement. The underlying idea of an RISP is to avoid higher non-recurring engineering (NRE) costs as in the case of application specific IP and at the same time providing the flexibility of custom datapath design based on application at runtime  ; thus providing a highly power efficient and fast processor. Depending on the size of their configurable logic blocks (CLBs), RISPs can be classified as fine grained and coarse grained; while fine grained RISP give higher flexibility by handling data at bit (or several bits) level; however this complicates the handling algorithms and may result in higher power consumption, more area requirement and increased delay due to greater interconnects. Coarse grained RISP on the other hand are not very flexible as it consists of larger CLBs and can handle several bits simultaneously but may result in power losses on bit level computations BIB012 . The CLBs in coarse grained processors are sometimes alternatively referred to as rDPUs (reconfigurable DataPath Units) BIB006 to contrast from CLBs in a fine grained system. There are various issues in the design of such processors, i.e. the design of fixed part or the core, the design of reconfigurable logic, its granularity, the highly flexible or dynamic datapath, and last but not least, the interface between the fixed and reconfigurable part  . Examples of RISP can be found in BIB008 BIB002 , while in  a software development toolchain, based on opensource gcc complier, is proposed to target RISPs. A specialized form of RISP is the Warp processor; that uses dynamic software optimization for better speed/energy performance. When a program first runs on the fixed processor, the system monitors the program to detect its most frequently-executed parts. The processor then automatically tries to move those parts to the reconfigurable logic or FPGA, all in runtime, thus eliminating tool flow restrictions and extra designer effort associated with traditional compile-time optimizations BIB016 . This approach gives an edge on the established approaches like the Binary-translation Optimized Architecture (BOA) BIB004 and the Dynamic Optimization System (Dynamo) BIB005 ; by performing binary level hardware/software partitioning at runtime BIB009 . Warp processors are currently capable of achieving speedups averaging 6.0 and energy savings up to 60% BIB013 BIB011 . The only difference between a traditional RISP and a Warp is that the reconfigurable part is located off-thechip i.e. a separate Warp oriented FPGA or W-FPGA BIB016 . Other examples of RISP architectures are RICA  , Matrix BIB003 , and Montium BIB010 . Among these, RICA (Reconfigurable Instruction Cell Array)  is a novel cell BIB014 BIB015 based architecture; comprising of array of dynamically reconfigurable instruction cells (ICs), programmable with a high level language. All this is attained with an innovative design of the silicon fabric in a similar way to reconfigurable arrays but with a closer equivalence to software, thus achieving the high performance as coarse-grain FPGA architectures, while maintaining the flexibility, low cost, and programmability as of general purpose processors.