Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Relation between energy and power <s> In this paper we investigate possible ways to improve the energy efficiency of a general purpose microprocessor. We show that the energy of a processor depends on its performance, so we chose the energy-delay product to compare different processors. To improve the energy-delay product we explore methods of reducing energy consumption that do not lead to performance loss (i.e. wasted energy), and explore methods to reduce delay by exploiting instruction level parallelism. We found that careful design reduced the energy dissipation by almost 25%. Pipelining can give approximately a 2/spl times/ improvement in energy-delay product. Superscalar issue, however, does not improve the energy-delay product any further since the overhead required offsets the gains in performance. Further improvements will be hard to come by since a large fraction of the energy (50-80%) is dissipated in the clock network and the on-chip memories. Thus, the efficiency of processors will depend more on the technology being used and the algorithm chosen by the programmer than the micro-architecture. <s> BIB001 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Relation between energy and power <s> Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although speculative execution is essential for increasing the instructions per cycle (IPC), it does come at a cost. A large amount of unnecessary work results from wrong-path instructions entering the pipeline due to branch misprediction. Results generated with the SimpleScalar tool set using a 4-way issue pipeline and various branch predictors show an instruction overhead of 16% to 105% for event instruction committed. The instruction overhead will increase in the future as processors use more aggressive speculation and wider issue widths. In this paper we present an innovative method for power reduction ,which, unlike previous work that sacrificed flexibility or performance reduces power in high-performance microprocessors without impacting performance. In particular we introduce a hardware mechanism called pipeline gating to control rampant speculation in the pipeline. We present inexpensive mechanisms for determining when a branch is likely to mispredict, and for stopping wrong-path instructions from entering the pipeline. Results show up to a 38% reduction in wrong-path instructions with a negligible performance loss (/spl ap/1%). Best of all, even in programs with a high branch prediction accuracy, performance does not noticeable degrade. Our analysis indicates that there is little risk in implementing this method in existing processors since it does not impact performance and can benefit energy reduction. <s> BIB002 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Relation between energy and power <s> Power dissipation is becoming a major show stopper for integrated circuit design especially in the server and pervasive computing technologies. Careful consideration of power requirements is expected to bring major changes in the way we design and analyze integrated circuit performance. This paper proposes a practical methodology to evaluate the short-circuit power of static CMOS gates via effective use of timing information from timing analysis. We introduce three methods to estimate short-circuit power of a static CMOS circuit without requiring explicit circuit simulation. Our proposed methodology offers practical advantages over previous approaches, which heavily rely on simple special device models. Proposed approach is experimented with an extensive set of benchmark examples and several device models and found very accurate. <s> BIB003
Performance drives the market for the processors BIB002 and the system advancement relies on increasing performance while retaining energy at an acceptable level. Since , simply reducing the power consumption in a processor may not decrease the energy demand if the task now takes longer to execute. Richard et al. [3] noted a correlation between energy and performance. However, reducing performance does not always reduce the overall energy. With a potential objective of minimum power at a given performance level, or increased performance at a given power level, both quantities need to be considered concurrently. This can be achieved by taking the product of energy and delay BIB001 . The power consumption in a processor can be classified as 1) static and 2) dynamic. Firstly, the static power consumption of a device is defined as the amount of power that it consumes while there is no switching activity. If the operating voltage is assumed fixed then the static power consumption mainly comprises of leakage current, and is fabrication process dependent; its general optimization techniques are beyond the scope of this paper. Secondly, the dynamic power of a CMOS device comprises of short circuit power and switching power. The short circuit current is observed during input signal transitions, when both the NMOS and PMOS blocks in static CMOS circuits conduct simultaneously for a short period of time. This causes a direct current flow from power rails resulting in short-circuit power BIB003 . The switching power consumption is given as  where = Load Capacitance, = Drain to source voltage, = activity factor, = clock frequency. Based on  it is possible to infer that dynamic power consumption can be decreased, by decreasing any one of the factors. Once again and are fabrication technology dependent; however there are techniques such as assigning a lower to noncritical paths that could significantly reduce overall dynamic power consumption. However, lowering increases circuit delay and consequently reduces the overall throughput of device  . The circuit delay is given as  , BIB002 where is a constant that depends on capacitance, mobility, and transistor dimensions  and is the threshold voltage. Principle processor core level power optimization techniques are discussed in the following.