A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> 1) Restricted Memory Regions <s> Energy consumed for transferring data across the processor memory hierarchy constitutes a large fraction of total system energy consumption, and this fraction has steadily increased with technology scaling. In this paper, we propose near-DRAM acceleration (NDA) architectures, which process data using accelerators 3D-stacked on DRAM devices comprising off-chip main memory modules. NDA transfers most data through high-bandwidth and low-energy 3D interconnects between accelerators and DRAM devices instead of low-bandwidth and high-energy off-chip interconnects between a processor and DRAM devices, substantially reducing energy consumption and improving performance. Unlike previous near-memory processing architectures, NDA is built upon commodity DRAM devices; apart from inserting through-silicon vias (TSVs) to 3D-interconnect DRAM devices and accelerators, NDA requires minimal changes to the commodity DRAM device and standard memory module architectures. This allows NDA to be more easily adopted in both existing and emerging systems. Our experiments demonstrate that, on average, our NDA-based system consumes 46% (68%) lower (data transfer) energy at 1.67× higher performance than a system that integrates the same accelerator logic within the processor itself. <s> BIB001 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> 1) Restricted Memory Regions <s> The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations. In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems. <s> BIB002 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> 1) Restricted Memory Regions <s> Processing -in-memory (PIM) is rapidly rising as a viable solution for the memory wall crisis, rebounding from its unsuc­ cessful attempts in I990s due to practicality concerns, which are alleviated with recent advances in 3D stacking technolo­ gies. However, it is still challenging to integrate the PIM architectures with existing systems in a seamless manner due to two common characteristics: unconventional progr amming models for in-memor y computation units and lack of ability to utilize large on- chip caches. In this paper, we propose a new PIM architecture that (I) does not change the existing sequential progr amming mod­ el s and (2) aut omatically decides whet her to exe cut e PIM operations in memory or processor s de pending on the local­ ity of data. The key idea is to implement simple in-memory computation using compute- capable memory commands and use specialized instructions, which we call PIM- enabled in­ structions, to invo ke in-memory computation. This allows PIM operations to be interoperable with existing program­ ming models, cache coherence protocols, and virtual memo ry mechanisms with no modification. In addition, we introduce a simple har dware struct ure that monitors the locality of data acce ssed by a PIM-en abled instruction at runtime to adap ­ tively execut e the instruction at the host processor (instead of in memory) when the instruction can benefit from large <s> BIB003
Farahani et al. BIB001 divided the memory in two regions: one for the host processor and one for CGRAs, which is uncacheable. A similar approach has been used by Ahn et al. BIB002 for graph processing algorithms. Another strategy, proposed by Ahn et al. BIB003 , provides a simple hardware-based solution in which the PIM operations are restricted to only one last level cache block, due to which they can monitor the cache block and request for invalidation or write-back if required.