Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> This active probe can be used for the long-term recording of extracellular neural biopotentials and as a basis for closed-loop neural prostheses. The probe incorporates on-chip circuitry for amplifying, multiplexing, and buffering neural signals recorded from ten recording electrodes spaced 100-/spl mu/m apart. It requires only three leads and operates from a single 5-V supply. On-chip self-test circuitry for testing electrode impedance levels is provided. The on-chip circuitry is fabricated in a die area of 1.3 mm/SUP 2/ using 6-/spl mu/m LOCOS enhancement-depletion NMOS technology, and dissipates 5 mW of power. The probe is 4.7 mm long and 15 /spl mu/m thick, and has a shank which tapers from 160 /spl mu/m near the base to less than 15 /spl mu/m near the tip. <s> BIB001 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> A CMOS low-power low-noise monolithic instrumentation amplifier (IA) is described. The power drain is reduced by use of current feedback and by use of only single-stage operational transconductance amplifiers in the low-frequency loop. The bandwidth of the IA is designed for medical purposes (0.5-500 Hz) and it can produce variable gains of 14/20/26/40 dB, which are set by control software. <s> BIB002 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> This paper discusses certain important issues involved in the design of a nerve signal preamplifier for implantable neuroprostheses. Since the electroneurogram signal measured from cuff electrodes is typically on the order of 1 /spl mu/V, a very low-noise interface is essential. We present the argument for the use of BiCMOS technology in this application and then describe the design and evaluation of a complete preamplifier fabricated in a 0.8-/spl mu/m double-metal double-poly process. The preamplifier has a nominal voltage gain of 100, a bandwidth of 15 kHz, and a measured equivalent input-referred noise voltage spectral density of 3.3 nV//spl radic/Hz at 1 kHz. The total input-referred rms noise voltage in a bandwidth 1 Hz-10 kHz is 290 nV, the power consumption is 1.3 mW from /spl plusmn/2.5-V power supplies, and the active area is 0.3 mm/sup 2/. <s> BIB003 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> In this paper, we describe the design and testing of a system for recording electroneurographic signals (ENG) from a multielectrode nerve cuff (MEC). This device, which is an extension of the conventional nerve signal recording cuff, enables ENG to be classified by action potential velocity. In addition to electrical measurements, we provide preliminary in vitro data obtained from frogs that demonstrate the validity of the technique for the first time. Since typical ENG signals are extremely small, on the order of 1 1 muV, very low-noise, high-gain amplifiers are required. The ten-channel system we describe was realized in a 0.8 mum CMOS technology and detailed measured results are presented. The overall gain is 10 000 and the total input-referred root mean square (rms) noise in a bandwidth 1 Hz-5 kHZ is 291 nV. The active area is 12 mm2 and the power consumption is 24 mW from plusmn2.5 V power supplies <s> BIB004 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> This paper presents a portable, embedded, microcontroller-based system for bidirectional communication (recording and stimulation) between an electrode, implanted in the peripheral nervous system, and a host computer. The device is able to record and digitize spontaneous and/or evoked neural activities and store them in data files on a PC. In addition, the system has the capability of providing electrical stimulation of peripheral nerves, injecting biphasic current pulses with programmable duration, intensity, and frequency. The recording system provides a highly selective band-pass filter from 800 Hz to 3 kHz, with a gain of 56 dB. The amplification range can be further extended to 96 dB with a variable gain amplifier. The proposed acquisition/stimulation circuitry has been successfully tested through in vivo measurements, implanting a tf-LIFE electrode in the sciatic nerve of a rat. Once implanted, the device showed an input referred noise of 0.83 μVrms, was capable of recording signals below 10 μ V, and generated muscle responses to injected stimuli. The results demonstrate the capability of processing and transmitting neural signals with very low distortion and with a power consumption lower than 1 W. A graphic, user-friendly interface has been developed to facilitate the configuration of the entire system, providing the possibility to activate stimulation and monitor recordings in real time. <s> BIB005 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology, which utilizes a differential pair input stage. The proposed architecture, which is referred to as a partial operational transconductance amplifier sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of mismatch on crosstalk between channels and the tradeoff between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a -3-dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at 3.5 μVrms and the power consumption is 7.92 μW from a 1.8-V supply, which corresponds to NEF = 3.35. The worst-case crosstalk and common-mode rejection ratio within the desired bandwidth are - 43.5 dB and 70.1 dB, respectively, and the active silicon area of each amplifier is 256 μm × 256 μm in 0.18-μm complementary metal-oxide semiconductor technology. <s> BIB006 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> We report the design of an ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology. The chip consists of eight neural recording modules where each module contains four neural amplifiers, an analog multiplexer, an A/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to adjust each amplifier's input-referred noise to suit the background noise at the recording site. The amplifier's input-referred noise can be adjusted from 11.2 μVrms (total power of 5.4 μW) down to 5.4 μVrms (total power of 20 μW) in the spike-recording setting. The ADC in each recording module digitizes the a.c. signal input to each amplifier at 8-bit precision with a sampling rate of 31.25 kS/s per channel, with an average power consumption of 483 nW per channel, and, because of a.c. coupling, allows d.c. operation over a wide dynamic range. It achieves an ENOB of 7.65, resulting in a net efficiency of 77 fJ/State, making it one of the most energy-efficient designs for neural recording applications. The presented chip was successfully tested in an in vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 μ W. The neural amplifier and the ADC occupy areas of 0.03 mm2 and 0.02 mm2 respectively, making our design simultaneously area efficient and power efficient, thus enabling scaling to high channel-count systems. <s> BIB007 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> Conventional capacitively coupled neural recording amplifiers often present a large input load capacitance to the neural signal source and hence take up large circuit area. They suffer due to the unavoidable trade-off between the input capacitance and chip area versus the amplifier gain. In this work, this trade-off is relaxed by replacing the single feedback capacitor with a clamped T-capacitor network. With this simple modification, the proposed amplifier can achieve the same mid-band gain with less input capacitance, resulting in a higher input impedance and a smaller silicon area. Prototype neural recording amplifiers based on this proposal were fabricated in 0.35 μm CMOS, and their performance is reported. The amplifiers occupy smaller area and have lower input loading capacitance compared to conventional neural amplifiers. One of the proposed amplifiers occupies merely 0.056 mm2. It achieves 38.1-dB mid-band gain with 1.6 pF input capacitance, and hence has an effective feedback capacitance of 20 fF. Consuming 6 μW, it has an input referred noise of 13.3 μVrms over 8.5 kHz bandwidth and NEF of 7.87. In-vivo recordings from animal experiments are also demonstrated. <s> BIB008 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> We demonstrate a micropower low-noise CMOS amplifier array that reuses bias current to improve the fundamental noise-power tradeoffs of fully-differential amplifier designs. The presented circuit implements current-reuse by stacking the differential input pairs of four amplifiers. The output drain currents of each channel's differential pair are used as the tail currents for the differential pairs of the succeeding channel. Orthogonal current-reuse improves the noise and power tradeoff by sharing bias devices to conserve headroom. With four channels (n = 4), there are 16 unique output currents (2n) from the stack, each of which is a linear combination of the four inputs. Amplified versions of the original input signals are reconstructed by appropriately combining the small-signal output currents in output stages that operate at much lower bias currents. With an input-referred noise of 3.7 μVrms and a bandwidth of 19.9 kHz, a single channel achieves a noise efficiency factor (NEF) of 3.0. Amortizing the bias current across the amplifier's four channels yields an effective NEF of 1.64. The total power consumption is 15.6 μW, or 3.9 μW per path from a 1.5 V supply. Orthogonal biasing suppresses crosstalk between the channels, providing an isolation of 40 dB under 3-σ mismatch. The implemented circuit was fabricated in a standard 130 nm CMOS process and occupies an area of 0.125 mm2. The proposed technique is useful for a variety of applications ranging from low-power neural recording arrays to multiphase radio baseband amplifiers. <s> BIB009 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems. <s> BIB010 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> Conventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred noise requirement that determines the system sensitivity, while the supply voltage is determined by a DR requirement at the analog recording chain output that limits the maximum achievable resolution of the A-to-D conversion. In this paper, a power-efficient neural-recording architecture using a DR-folding technique is presented to enable low-voltage operation without compromising the DR performance. The proposed architecture can operate with only half of the typically required supply voltage, which results in about 50% power reduction. <s> BIB011 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> This paper presents a low-power low-noise amplifier for neural recording applications. A single-stage current-reuse telescopic topology is proposed to achieve high DC gain and improve the noise efficiency factor (NEF) while allowing the amplifier to be scaled for high bandwidth sensing applications and/or to achieve lower thermal noise floor. The design is fabricated in a standard 0.18μm CMOS process and occupies an active area of 0.16mm2. Experimental measurements show a 430nW power consumption from a 1.2V supply, a thermal noise floor of 63.8nV/√Hz and a corresponding NEF of 1.5. <s> BIB012 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end neural amplifier circuit design <s> Neural probes have become the most important tool for enabling neuroscientists to place microelectrode sensors close to individual neurons and to monitor their activity in vivo. With such devices, it is possible to perform acute or chronic extracellular recordings of electrical activity from a single neuron or from groups of neurons. After the many developments in neural implants, it has become clear that large arrays of electrodes are desirable to further investigate the activity performed by complex neural networks. Therefore, in this paper, we propose a CMOS neural probe containing 455 active electrodes in the probe shank (100 μm wide, 10 mm long, and 50 μm thick) and 52 simultaneous readout channels in the probe body (2.9 × 3.3 mm2). In situ amplification under each electrode enables low-impedance interconnection lines, regardless of the electrode impedance, with a residual crosstalk of -44.8 dB. This design has been implemented in a 0.18-μm standard CMOS technology, with additional CMOS-compatible post-processing performed at wafer level to define the electrodes and the probe outline. In this architecture, the analog front-end achieves an input-referred noise of 3.2 μVrms and an NEF of 3.08. The power consumption of the core circuit is 949.8 μW, while the total power consumption is 1.45 mW. The high-density active-electrode array in this neural probe allows for the massive recording of neural activity. In vivo measurements demonstrate successful simultaneous recordings from many individual cells. <s> BIB013
The circuit design of the front-end amplifier in Fig. 3 deserves special attention, as the electrical performance of this amplifier directly determines the performance of the overall recording system. Front-end amplifier gains range from 200 to 10,000. The choice of gain is influenced by the required application (CNS or PNS recording) and the system's power supply BIB004 . The noise introduced by the amplifier is typically designed to be lower than that introduced by the electrodes and, for a majority of neural applications, is maintained below 5 µV rms for amplifiers used to record CNS signals and less than 1 µV rms for PNS-recording amplifiers BIB005 BIB003 . The most common front-end amplifier for IC neural recordings was first proposed by Najafi and Wise BIB001 and then further refined by Harrison  to its present circuit shown in Fig. 4 . The input neural signals are AC-coupled through the pair of input capacitors, C in , and feed the shunt-shunt negative feedback network formed by feedback capacitors, C fb , applied around the operational transconductance amplifier (OTA), A 1 . The closed-loop gain is therefore accurately defined by the ratio C in /C fb . The pseudo-resistors formed by PMOS transistors help establish a proper DC negative feedback bias and together with C fb also define the lowside 3-dB cutoff frequency of the neural amplifier. To suppress noise contributions from downstream signal processing stages, a high amplifier gain is desired and achieved by incorporating a high C in /C fb ratio (usually by using a large C in ), but at the expense of increased silicon area and lowered input impedance. Recent studies have attempted to reduce the silicon area by using smaller unit capacitors or reducing the amplifier gain BIB013 BIB006 . However, Ng and Xu proposed relaxing this area-gain trade-off by introducing additional shunt elements onto the negative feedback network BIB008 . Recent works have also reported that by carefully designing the OTA A1, low current consumption and low input-referred noise are easily achievable BIB009 BIB007  BIB010 . Several metrics have been introduced to quantify frontend amplifier performance. For example, the noise efficiency factor (NEF) characterizes an amplifier's inputreferred noise with respect to its current consumption and bandwidth BIB002 . The NEF is defined as: where V irms is the input-referred root-mean-square (RMS) noise voltage, I tot is the total amplifier bias current, U t is the thermal voltage, κ is the Boltzmann's constant, T is the absolute temperature, and BW is the amplifier's effective noise bandwidth. The NEF is a useful performance metric by which neural amplifiers can be compared, and it represents a relative measure of how much noise an amplifier produces compared to that of a single bipolar transistor consuming the same bias current. However, the NEF alone is not a sufficient metric to compare neural amplifiers that are operated at different supply voltages. This inadequacy becomes more pronounced, as recent works have reported operating supply voltages below 1 V BIB011 BIB012 BIB010 . Recently, Muller et al.  introduced the power efficiency factor (PEF), which takes into account both the operating current and the supply voltage and therefore provides a better comparison of the amplifier's performance. The PEF is defined as: