SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> B. SHIFT REGISTER ARCHITECTURES <s> The rapid developments in the communications industry over the last decade have led to an escalation in the amount of sensitive data being transmitted over the Internet. This has resulted in an increased awareness of the need to provide security measures. Authentication is one such security measure. A novel highly efficient single-chip hardware design of the SHA-384 and SHA-512 authentication algorithms is described in this paper. The compact implementation achieves a throughput of 479 Mbits/sec utilising a shift register design approach and look-up tables (LUTs). This is believed to be the first SHA-384/SHA-512 hardware implementation to be reported in the literature. <s> BIB001 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> B. SHIFT REGISTER ARCHITECTURES <s> The hash functions MD5, RIPEMD-160, and SHA-1/224/256/384/512 were implemented by using a 0.13/spl mu/m CMOS standard cell library with two synthesis options, area and speed optimizations, and their performances were evaluated. The smallest circuit of 8.0 Kgates with a throughput of 929 Mbps, and the highest throughput of 2.9 Gbps with 27.3 Kgates were obtained for SHA-1 and SHA-384/512 respectively. In terms of overall performance with consideration of the security levels, we conclude that SHA-256 is the best algorithm, with compact circuits of 11.5 /spl sim/ 15.3 Kgates and high throughputs of 1.1 /spl sim/ 2.4 Gbps. Our implementations also showed the highest throughputs for all of the hash functions in comparison with the state of the art. <s> BIB002 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> B. SHIFT REGISTER ARCHITECTURES <s> Hash functions are common and important cryptographic primitives, which are very critical for data integrity assurance and data origin authentication security services. Field programmable gate arrays (FPGAs) being reconfigurable, flexible and physically secure are a natural choice for implementation of hash functions in a broad range of applications with different area-performance requirements. In this paper, we explore alternative architectures for the implementation of hash algorithms of the secure hash standards SHA-256 and SHA-512 on FPGAs and study their area-performance trade-offs. As several 64-bit adders are needed in SHA-512 hash value computation, new architectures proposed in this paper implement modulo-64 addition as modulo-32, modulo-16 and modulo-8 additions with a view to reduce the chip area. Hash function SHA-512 is implemented in different FPGA families of ALTERA to compare their performance metrics such as area, memory, latency, clocking frequency and throughput to guide a designer to select the most suitable FPGA for an application. In addition, a common architecture is designed for implementing SHA-256 and SHA-512 algorithms. <s> BIB003 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> B. SHIFT REGISTER ARCHITECTURES <s> Coupled with the increasing demand for strong secure data transmission in communications, SHA-2 hash family is becoming the newest powerful hash function standard. In this paper, a reconfigurable architecture is proposed. The architecture supports a multi-mode operation in the sense that it performs all the three hash functions algorithms (256,384 and 512) of the SHA-2 standard. Furthermore, the performance of proposed implementation in the term of throughput and resources is higher than other hardware implementations, due to using critical data path optimization and the method of reducing word length. Therefore this work can substitute efficiently the existing MD5 and SHA-1 hash function implementations in every security scheme, also offers a higher security level strength. <s> BIB004 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> B. SHIFT REGISTER ARCHITECTURES <s> The widespread adoption of Internet as a secure medium for communication and e-commerce has made cryptography a vital part of today's information systems. However, to achieve a more pervasive deployment, the supporting cryptographic (crypto) systems should exhibit processing power of high performance and efficiency. These demanding requirements can be achieved by integrating the cryptosystems into designs based on System-on-Chip (SoC). In this paper, the design and implementation of a crypto hash SHA-2 logic core in reconfigurable hardware is presented. We also discuss a public-key crypto SoC, which uses the SHA-2 hash core in conjunction with a 2048-bit RSA co-processor to perform a digital signature security scheme. We use Verilog to model the hardware, and C to code the embedded software. With the crypto SoC implemented in an Altera Nios II Stratix FPGA-based prototyping system running on a 50 MHz system clock, we obtained a throughput of 644 Mbits/sec for our SHA-512 hardware core. <s> BIB005 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> B. SHIFT REGISTER ARCHITECTURES <s> We present a compact SHA-256 hardware architecture suitable for the Trusted Mobile Platform (TMP), which requires low-area and low-power characteristics. The built-in hardware engine to compute a hash algorithm in TMP is one of the most important circuit blocks and contributes the performance of the whole platform because it is used as key primitives supporting platform integrity and command authentication. Unlike personal computers, mobile platform have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore, special architecture and design methods for a compact hash hardware module are required. Our SHA-256 hardware can compute 512-bit data block using 8,588 gates on a 0.25μm CMOS process. The highest operation frequency and throughput of the proposed architecture are 136MHz and 142Mbps, which satisfies processing requirement for the mobile application. <s> BIB006 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> B. SHIFT REGISTER ARCHITECTURES <s> This paper introduces the specialization of a NIOS2 processor targeting the computation of message authentication codes and integrity checks in constrained environments. Several hardware/software partitioning levels are considered, which vary from simple functions implemented as custom instructions to complete algorithms as peripherals. Our experimental results show that functions Sum, Sig, Ch, Maj implemented as custom instructions allows for SHA-256 and HMAC to be accelerated 1.38 and 1.36 times respectively, while keeping a small area footprint. If the entire SHA-256 algorithm is implemented as a peripheral, the hash computation is performed 11 times faster while decreasing the program size in 16%. Furthermore, the HMAC/SHA-256 peripheral accelerates the computation of a message authentication code 19 times with a 26% smaller program. These results allow for the specialization of the computational platform of constrained embedded systems to the processing requirements of cryptographic applications performing message authentication codes and integrity checks. <s> BIB007 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> B. SHIFT REGISTER ARCHITECTURES <s> To accelerate the speed of iterative computation for the existing SHA-256 algorithm, using 7-3-2 array compressor is proposed to reduce the critical path delay in this paper. The frequency of the proposed scheme is 1.7 times higher than other VLSI implementations under the same process. In addition, the paper designs a new universal architecture for implementing SHA-2 algorithms. The design is synthesized with the slow library of Synopsys Design Compiler in SMIC 0.18µm CMOS process. Its function has been verified sufficiently on FPGA. Furthermore, compared with the existing SHA-256 core, the results of the ASIC synthesis and FPGA verification are more preferable. This design is convenient to implant into SoC and embedded system with the versatile architecture and high clock frequency1. <s> BIB008 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> B. SHIFT REGISTER ARCHITECTURES <s> This paper presents a compact and unified hardware architecture implementing SHA-1 and SHA-256 algorithms that is suitable for the mobile trusted module (MTM), which should satisfy small area and low-power condition. The built-in hardware hash engine in a MTM is one of the most important circuit blocks and dominates the performance of the whole platform because it is used as a key primitive to support most MTM commands concerning to the platform integrity and the command authentication. Unlike the general trusted platform module (TPM) for PCs, the MTM, that is to be employed in mobile devices, has very stringent limitations with respect to available power, circuit area, and so on. Therefore, MTM needs the spatially optimized architecture and design method for the construction of a compact SHA hardware. The proposed hardware for unified SHA-1 and SHA-256 component can compute a sequence of 512-bit data blocks and has been implemented into 12,400 gates of 0.25 μm CMOS process. Furthermore, in the processing speed and power consumption, it shows the better performance in comparison with commercial TPM chips and software-only implementation. The highest operation frequency and throughput of the proposed architecture are 137 MHz and 197.6 Mbps, respectively, which satisfy the processing requirement for the mobile application. <s> BIB009 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> B. SHIFT REGISTER ARCHITECTURES <s> The modern era of Internet-of-Things (IoT) is naturally imposing a tight area/runtime constraint on the computing kernels. Security kernels, as part of the standardized protocols as well as custom defense techniques, are among the most common tasks executed on every digital device. Therefore, low area cost and high performance implementation of security kernels is an important goal of current system designers. In this paper, we revisit the state-of-the-art implementations of SHA-256, a standardized security primitive for authentication and propose novel optimizations. Our optimizations, based on architectural folding and 4-2 adder compressor, are geared toward both lightweight and high performance implementations. Detailed experiments of our optimized architecture on different FPGA fabrics clearly demonstrate their benefits. Our presented design point successfully attained the highest hardware efficiency (throughput/area) figures among the published literature so far. <s> BIB010
The architecture proposed in BIB001 exploits Equation (II.12) in the implementation of Equation (IV.1). In fact, Equation (II.12) implies that the accumulators can be chained in a shift register configuration, where for E t+1 the incoming value of D t is added with the output of the T 1 t function. The shift register chain is supplied with T 1 t + T 2 t as input, which is the value of A t+1 . The coprocessor architecture proposed in BIB007 also follows the shift register approach, both for the SHA-256 and the full HMAC-SHA-256 implementations. The multi-mode variant of the shift register approach is presented in BIB005 . The shift register architecture can be optimised to utilise a single adder to perform the final sum. This is illustrated in BIB002 , where an adder from the datapath is reused to this end. The shift register approach is also adopted in BIB006 , which is an architecture specifically tailored to low-power, area-constrained applications. The round function is implemented by reducing the number of operator blocks at the minimum, reusing the same operator block to perform multiple computations. The shift register architecture of the Compressor is therefore modified to work with a single adder, which subsequently adds different operands to compute the round function across several clock cycles, while the H t register is used as the accumulator for the addition. Interestingly, a similar architecture is adopted also for the Expander, which requires four clock cycles to compute a word, compared with the seven clock cycles of the Compressor. The whole circuit requires 490 clock cycles to fully compute a hash, hence effectively trading throughput for area and power consumption. The multi-mode extension of this architecture is presented in BIB009 . Another proposal aimed at reducing area occupation, following the shift register architecture, is BIB003 . In this case, the area reduction is obtained by reducing the word size of the SHA-512 hash function, which is normally 64 bit, to a lower value, taking advantage of the fact that most of the operations involved in the hash algorithm can be computed in a bit-wise fashion. Implementations with the word size reduced to 32 bit, 16 bit and 8 bit are considered. Interestingly, the 32-bit variant achieves 72% of the throughput of the full-word-size implementation, meaning that it is more area efficient than the full-word-size counterpart. The architecture described in  also reduces the word width of the circuit to 8 bit, exploiting also loop folding to achieve further area reduction. A different way to improve the shift register architecture involves the use of parallel adders for the adder chain. In BIB004 the adder chain is implemented with 5-to-3 parallel adders, while BIB008 employs a single 7-3-2 parallel adder to compute A t+1 . The architecture proposed in BIB010 combines the use of parallel adders with the loop folding technique, in order to reduce area occupation limiting the throughput penalty, therefore maximizing the area efficiency.