A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> Cache Coherence Protocols <s> This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high-performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and Web technologies, and high-performance computing. <s> BIB001 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> Cache Coherence Protocols <s> This paper analyzes the scalability of seven system applications (Exim, memcached, Apache, PostgreSQL, gmake, Psearchy, and MapReduce) running on Linux on a 48- core computer. Except for gmake, all applications trigger scalability bottlenecks inside a recent Linux kernel. Using mostly standard parallel programming techniques-- this paper introduces one new technique, sloppy counters-- these bottlenecks can be removed from the kernel or avoided by changing the applications slightly. Modifying the kernel required in total 3002 lines of code changes. A speculative conclusion from this analysis is that there is no scalability reason to give up on traditional operating system organizations just yet. <s> BIB002
Each core has its own data and uses its private data cache for speeding up the processing. However, when cores share data, each copy of the data is placed in the core's private cache and the cache coherence protocol is responsible for keeping the consistency between each copy (usually through bus snooping 3 ). Whenever a core writes into a data that other cores have cached, an invalidation occurs, increasing tasks' execution time. This invalidation operation is performed automatically by the hardware and take hundreds of cycles (about the same time as accessing the off-chip RAM), increasing the application's execution time BIB002 . Two kinds of scaling problem occur due to shared memory contention BIB002 : (1) access serialization to the same cache line done by the cache coherence protocol, which prevents parallel speedup, and (2) saturation into the intercore interconnection, also preventing parallel processing gains. MESI BIB001 , MOESI  , and MESIF  ] are the most used cache coherence protocols by current multicore processors. MESIF and MOESI protocols are usually used in ccNUMA architectures, such as Intel Sandy Bridge and AMD Opteron, respectively, while MESI is widely used in UMA architectures, such as Intel dual-core and ARM Cortex-A9.