A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> IV. PROCESSING NEAR STORAGE CLASS MEMORY <s> A new two-terminal circuit element-called the memristorcharacterized by a relationship between the charge q(t)\equiv \int_{-\infty}^{t} i(\tau) d \tau and the flux-linkage \varphi(t)\equiv \int_{- \infty}^{t} v(\tau) d \tau is introduced as the fourth basic circuit element. An electromagnetic field interpretation of this relationship in terms of a quasi-static expansion of Maxwell's equations is presented. Many circuit-theoretic properties of memistors are derived. It is shown that this element exhibits some peculiar behavior different from that exhibited by resistors, inductors, or capacitors. These properties lead to a number of unique applications which cannot be realized with RLC networks alone. Although a physical memristor device without internal power supply has not yet been discovered, operational laboratory models have been built with the help of active circuits. Experimental results are presented to demonstrate the properties and potential applications of memristors. <s> BIB001 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> IV. PROCESSING NEAR STORAGE CLASS MEMORY <s> The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. An alternative memory technology that uses resistance contrast in phase-change materials is being actively investigated in the circuits community. Phase Change Memory (PCM) devices offer more density relative to DRAM, and can help increase main memory capacity of future systems while remaining within the cost and power constraints. In this paper, we analyze a PCM-based hybrid main memory system using an architecture level model of PCM.We explore the trade-offs for a main memory system consisting of PCMstorage coupled with a small DRAM buffer. Such an architecture has the latency benefits of DRAM and the capacity benefits of PCM. Our evaluations for a baseline system of 16-cores with 8GB DRAM show that, on average, PCM can reduce page faults by 5X and provide a speedup of 3X. As PCM is projected to have limited write endurance, we also propose simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years. <s> BIB002 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> IV. PROCESSING NEAR STORAGE CLASS MEMORY <s> The confluence of emerging technologies and new data-centric workloads offers a unique opportunity to rethink traditional system architectures and memory hierarchies in future designs. <s> BIB003 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> IV. PROCESSING NEAR STORAGE CLASS MEMORY <s> Computer memories continue to serve the role that they first served in the electronic discrete variable automatic computer (EDVAC) machine documented by John von Neumann, namely that of supplying instructions and operands for calculations in a timely manner. As technology has made possible significantly larger and faster machines with multiple processors, the relative distance in processor cycles of this memory has increased considerably. Microarchitectural techniques have evolved to share this memory across ever-larger systems of processors with deep cache hierarchies and have managed to hide this latency for many applications, but are proving to be expensive and energy-inefficient for newer types of problems working on massive amounts of data. New paradigms include scale-out systems distributed across hundreds and even thousands of nodes, in-memory databases that keep data in memory much longer than the duration of a single task, and near-data computation, where some of the computation is off-loaded to the location of the data to avoid wasting energy in the movement of data. This paper provides a historical perspective on the evolution of memory architecture, and suggests that the requirements of new problems and new applications are likely to fundamentally change processor and system architecture away from the currently established von Neumann model. <s> BIB004 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> IV. PROCESSING NEAR STORAGE CLASS MEMORY <s> Nowadays solid state drives (SSDs) are gaining popularity and are replacing magnetic hard disk drives (HDDs) in enterprise storage systems. As a result, extracting the maximum performance from SSDs is becoming crucial to deal with the increasing storage volume and performance needs. Active disks were introduced as a way to offload data-processing tasks from the host into disks freeing system resources and achieving better performance. In this work, we present an active SSD architecture called Self-Sorting SSD that targets to offload sorting operations which are commonly used in data-intensive and database environments and that require heavy data transfer. Processing sorting operations directly on the SSD reduces data transfer from/to the storage devices, increasing system performance and the lifetime of SSDs. Experiments on a real SSD platform reveal that our proposed architecture outperforms traditional external merge sort by up to 60.75%, reduces energy consumption by up to 58.86%, and eliminates all the data transfer overhead to compute sorted results. <s> BIB005
Flashes and other emerging nonvolatile memories such as phase-change memory (PCM) BIB002 , spin-transfer torque RAM (STT-RAM)  , memristors BIB001 , etc., are termed as storageclass memories (SCMs) BIB004 . These memories are trying to fill the latency gap between DRAMs and disks. SCMs like NVRAM are even touted as a future replacement for DRAM BIB003 . Moving computation in SCM has some of the similar benefits to DRAM in terms of saving in bandwidth, power, latency, and energy but also because of the higher density it allows to work on much larger data-sets as compared to DRAM BIB005 .