Multi-core processors - An overview <s> Major challenges faced by multi-core processors. <s> Exploiting thread-level parallelism (TLP) is a promising way to improve the performance of applications with the advent of general-purpose cost effective uni-processor and shared-memory multiprocessor systems. In this paper, we describe the OpenMP implementation in the Intel/spl reg/ C++ and Fortran compilers for Intel platforms. We present our major design consideration and decisions in the Intel compiler for generating efficient multithreaded codes guided by OpenMP directives and pragmas. We describe several transformation phases in the compiler for the OpenMP parallelization. In addition to compiler support, the OpenMP runtime library is a critical part of the Intel compiler. We present runtime techniques developed in the Intel OpenMP runtime library for exploiting thread-level parallelism as well as integrating the OpenMP support with other forms of threading termed as sibling parallelism. The performance results of a set of benchmarks show good speedups over the well-optimized serial code performance on Intel/spl reg/ Pentium- and Itanium-processor based systems. <s> BIB001 </s> Multi-core processors - An overview <s> Major challenges faced by multi-core processors. <s> The increased deployment of system-on-chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, networks-on-chip (NoC) have been proposed. The NoC routing algorithm significantly influences the performance and energy consumption of the chip. We propose a router architecture which utilizes adaptive routing while maintaining low latency. The two-stage pipelined architecture uses look ahead routing, speculative allocation, and optimal output path selection concurrently. The routing algorithm benefits from congestion-aware flow control, making better routing decisions. We simulate and evaluate the proposed architecture in terms of network latency and energy consumption. Our results indicate that the architecture is effective in balancing the performance and energy of NoC designs. <s> BIB002 </s> Multi-core processors - An overview <s> Major challenges faced by multi-core processors. <s> With no other way to improve the performance of processors further, chip makers have staked their future on putting more and more processor cores on the same chip. Engineers at Sandia National Laboratories, in New Mexico, have simulated future high-performance computers containing the 8-core, 16?core, and 32-core microprocessors that chip makers say are the future of the industry. The results are distressing. Because of limited memory bandwidth and memory-management schemes that are poorly suited to supercomputers, the performance of these machines would level off or even decline with more cores. The performance is especially bad for informatics applications? data-intensive programs that are increasingly crucial to the labs? national security function. <s> BIB003 </s> Multi-core processors - An overview <s> Major challenges faced by multi-core processors. <s> The primary consequence of the transition to multicore processors is that applications will increasingly need to be parallelized to fully exploit the throughput gains now becoming available. Unfortunately, parallel programming is no doubt much more tedious and errorprone than serial programming. Software vendors have begun efforts to educate developers and provide them with better tools for multicore programming. But many of the tools available are still works in progress. This paper presents a preliminary study of the usability of the state-of-the-art threading tools for multicore programming. We report on our evaluation of the usability of two Intel threading tools: Intel Thread Profiler a visual profiling tool for monitoring the parallelism gain of parallel applications and Intel Thread Checker a sophisticated tool for finding potential deadlocks and data race conditions in a parallel code. <s> BIB004 </s> Multi-core processors - An overview <s> Major challenges faced by multi-core processors. <s> Multicore and multithreaded CPUs have become the new approach to obtaining increases in CPU performance. Numeric applications mostly benefit from a large number of computationally powerful cores. Servers typically benefit more if chip circuitry is used for maximizing throughput via multiple threads per core. <s> BIB005
In spite of the many advantages that multi-core processors come with, there are a few major challenges the technology is facing. One main issue seen is with regard to software programs which run slower on multicore processors when compared to single core processors. It has been correctly pointed out that "Applications on multi-core systems don't get faster automatically as cores are increased"  . Programmers must write applications that exploit the increasing number of processors in a multi-core environment without stretching the time needed to develop software  . Majority of applications used today were written to run on only a single processor, failing to use the capability of multi-core processors  . Although software firms can develop software programs capable of utilizing the multi-core processor to the fullest, the grave challenge the industry faces is how to port legacy software programs developed years ago to multi-core aware software programs  . Redesigning programs although sounds possible, it's really not a technological decision in today's environment. It's more of a business decision where in companies have to decide whether to go ahead redesigning software programs keeping in mind key parameters such as time to market, customer satisfaction and cost reduction  . The industry is addressing this problem by designing compilers which can port legacy single core software programs to 'multi-core aware' programs which will be capable of utilizing the power of multi-core processors. The compilers could perform "code reordering", where in compilers will generate code, reordering instructions such that instructions that can be executed in parallel are close to each other  . This would enable us to execute instructions in parallel improving performance. Also compilers are being developed to generate parallel threads or processes automatically for a given application so that these processes can be executed in parallel  . Intel released major updates for C++ and Fortran tools which aimed at programmers exploiting parallelism in multi-core processors. Also along side OpenMP (Open Multiprocessing), an application programming interface which supports multiprocessing programming in C, C++ and Fortran provides directives for efficient multithreaded codes BIB001 . It has however been correctly pointed out that "The throughput, energy efficiency and multitasking performance of multi-core processors will all be fully realized when application code is multi-core ready"  . Secondly, on-chip interconnects are becoming a critical bottle-neck in meeting performance of multi-core chips BIB002 . With increasing number of cores comes along the huge interconnect delays (wire delays) when data has to be moved across the multi-core chip from memories in particular  . The performance of the processor truly depends on how fast a CPU can fetch data rather than how fast it can operate on it to avoid data starvation scenario BIB003 . Buffering and smarter integration of memory and processors are a few classic techniques which have attempted to address this issue. Network on a chip (NoCs) are IPs (Intellectual Property) being developed and researched upon which are capable of routing data on a SoC in a much more efficient manner ensuring less interconnect delay  . Increased design complexity due to possible race conditions as the number of cores increase in a multi-core environment. "Multiple threads accessing shared data simultaneously may lead to a timing dependent error known as data race condition" BIB004 . In a multi-core environment data structure is open to access to all other cores when one core is updating it. In the event of a secondary core accessing data even before the first core finishes updating the memory, the secondary core faults in some manner. Race conditions are especially difficult to debug and cannot be detected by inspecting the code, because they occur randomly. Special hardware requirement implementing mutually exclusion techniques have to be implemented for avoiding race conditions BIB004 . Another important feature which impacts multi-core performance is the interaction between on chip components viz. cores, memory controllers and shared components viz. cache and memories BIB005 where bus contention and latency are the key areas of concern. Special crossbars or mesh techniques have been implemented on hardware to address this issue BIB005 .