Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff. <s> BIB001 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> Two thin-film microelectrode arrays with integrated circuitry have been developed for extracellular neural recording in behaving animals. An eight-site probe for simultaneous neural recording and stimulation has been designed that includes on-chip amplifiers that can be individually bypassed, allowing direct access to the iridium sites for electrical stimulation. The on-probe amplifiers have a gain of 38.9 dB, an upper-cutoff frequency of 9.9 kHz, and an input-referred noise of 9.2 /spl mu/V /sub rms/ integrated from 100 Hz to 10 kHz. The low-frequency cutoff of the amplifier is tunable to allow the recording of field potentials and minimize stimulus artifact. The amplifier consumes 68 /spl mu/W from /spl plusmn/1.5 V supplies and occupies 0.177 mm/sup 2/ in 3 /spl mu/m features. In vivo recordings have shown that the preamplifiers can record single-unit activity 1 ms after the onset of stimulation on sites as close as 20 /spl mu/m to the stimulating electrode. A second neural recording array has been developed which multiplexes 32 neural signals onto four output data leads. Providing gain on this array eliminates the need for bulky head-mounted circuitry and reduces motion artifacts. The time-division multiplexing circuitry has crosstalk between consecutive channels of less than 6% at a sample rate of 20 kHz per channel. Amplified, time-division-multiplexed multichannel neural recording allows the large-scale recording of neuronal activity in freely behaving small animals with minimum number of interconnect leads. <s> BIB002 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> Chronically implanted electrode arrays have enabled a broad range of advances in basic electrophysiology and neural prosthetics. Those successes motivate new experiments, particularly, the development of prototype implantable prosthetic processors for continuous use in freely behaving subjects, both monkeys and humans. However, traditional experimental techniques require the subject to be restrained, limiting both the types and duration of experiments. In this paper, we present a dual-channel, battery-powered neural recording system with an integrated three-axis accelerometer for use with chronically implanted electrode arrays in freely behaving primates. The recording system called HermesB, is self-contained, autonomous, programmable, and capable of recording broadband neural (sampled at 30 kS/s) and acceleration data to a removable compact flash card for up to 48 h. We have collected long-duration data sets with HermesB from an adult macaque monkey which provide insight into time scales and free behaviors inaccessible under traditional experiments. Variations in action potential shape and root-mean square (RMS) noise are observed across a range of time scales. The peak-to-peak voltage of action potentials varied by up to 30% over a 24-h period including step changes in waveform amplitude (up to 25%) coincident with high acceleration movements of the head. These initial results suggest that spike-sorting algorithms can no longer assume stable neural signals and will need to transition to adaptive signal processing methodologies to maximize performance. During physically active periods (defined by head-mounted accelerometer), significantly reduced 5-25-Hz local field potential (LFP) power and increased firing rate variability were observed. Using a threshold fit to LFP power, 93% of 403 5-min recording blocks were correctly classified as active or inactive, potentially providing an efficient tool for identifying different behavioral contexts in prosthetic applications. These results demonstrate the utility of the HermesB system and motivate using this type of system to advance neural prosthetics and electrophysiological experiments. <s> BIB003 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> This paper reports an implantable microsystem capable of recording neural activity simultaneously on 64 channels, wirelessly transmitting spike occurrences to an external interface. The microsystem also allows the user to examine the spike waveforms on any channel with 8 bit resolution. Signals are amplified by 60 dB with a programmable bandwidth from < 100 Hz to 10 kHz. The input-referred noise is 8 ?Vrms. The channel scan rate for spike detection is 62.5 kS/sec using a 2 MHz clock. The system dissipates 14.4 mW at 1.8 V, weighs 275 mg, and measures 1.4 cm 1.55 cm. <s> BIB004 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> This paper describes a micropower low-noise neural front-end circuit capable of recording epileptic fast ripples (FR). The front-end circuit consisting of a preamplifier followed by a 6th-order bandpass filter is designed for signal sensing in a future epileptic deep brain stimulator. A current-splitting technique is combined with an output-branch current scaling technique in a folded-cascode amplifier structure to improve the noise and power tradeoff in the preamplifier. In measurements, the preamplifier exhibits 39.4 dB DC gain, 0.36 Hz to 1.3 kHz of -3 dB bandwidth, and 3.07 μVrms total input-referred noise while consuming 2.4 μW from a 2.8 V power supply provided by an on-chip regulator circuit. A noise efficiency factor (NEF) of 3.09 is achieved with minimal power consumption and is one of the lowest published to date. The 6th-order follow-the-leader feedback elliptic bandpass filter passes FR signals and provides -110 dB/decade attenuation to out-of-band frequency components. In measurements, the entire front-end circuit achieves a mid-band gain of 38.5 dB, a bandwidth from 250 to 486 Hz, and a total input-referred noise of 2.48 μVrms while consuming 4.5 μW from the 2.8 V power supply. The front-end NEF achieved is 7.6. To the authors' knowledge, the proposed epileptic seizure- detection system is the first to achieve the FR-recording functionality. The chip is fabricated in a standard 0.6 μm CMOS process. Die size is 0.45 mm2. <s> BIB005 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> We report the design of an ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology. The chip consists of eight neural recording modules where each module contains four neural amplifiers, an analog multiplexer, an A/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to adjust each amplifier's input-referred noise to suit the background noise at the recording site. The amplifier's input-referred noise can be adjusted from 11.2 μVrms (total power of 5.4 μW) down to 5.4 μVrms (total power of 20 μW) in the spike-recording setting. The ADC in each recording module digitizes the a.c. signal input to each amplifier at 8-bit precision with a sampling rate of 31.25 kS/s per channel, with an average power consumption of 483 nW per channel, and, because of a.c. coupling, allows d.c. operation over a wide dynamic range. It achieves an ENOB of 7.65, resulting in a net efficiency of 77 fJ/State, making it one of the most energy-efficient designs for neural recording applications. The presented chip was successfully tested in an in vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 μ W. The neural amplifier and the ADC occupy areas of 0.03 mm2 and 0.02 mm2 respectively, making our design simultaneously area efficient and power efficient, thus enabling scaling to high channel-count systems. <s> BIB006 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> This paper describes a inductively powered multichannel bionic neural link (BNL) system-on-chip (SOC) for peripheral nerve function restoration. The BNL-SOC consists of 8 neural recording and 4 stimulation channels, and is implemented in a 0.35-μm CMOS technology. Full function of the BNL has been demonstrated with in-vivo animal experiments. The entire BNL SOC consumes 1.5mW and operates under a 3V supply with an external +/-9V multichannel stimulation output driver. <s> BIB007 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> Peripheral nerve injuries with large gaps and long nerve regrowth paths are difficult to repair using existing surgical techniques, due to nerve degeneration and muscle atrophy. This paper proposes a Bionic Neural Link (BNL) as an alternative way for peripheral nerve repair. The concept of the BNL is described, along with the hypothetical benefits. A prototype monolithic single channel BNL has been developed, which consists of 16 neural recording channels and one stimulation channel, and is implemented in a 0.35-µm CMOS technology. The BNL has been tested in in-vivo animal experiments. Full function of the BNL chip has been demonstrated. <s> BIB008 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> Advances in neuroscience research and clinical applications have increasingly called for the low-power low-noise simultaneous recording of neural signals from a large number of electrodes. The neural interface IC is one of the essential blocks to capture the weak neural signals. Presented is an energy-efficient low-noise neural recording amplifier with enhanced noise efficiency factor (NEF) for neural recording systems. Based on the conventional capacitive feedback and pseudo-resistor structure, the fully differential neural amplifier employs the current-reuse technique to achieve low noise and high current efficiency, consuming 800 nA at 1 V power supply. The measured thermal noise floor is 43nV/√Hz and the input-referred noise is 5.71 µVrms when integrated from 1 Hz to 50 kHz, leading to an NEF of 2.59. The entire neural amplifier has been fabricated using a 0.18 µm CMOS technology, occupying an area of 0.05 mm2. <s> BIB009 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> Conventional capacitively coupled neural recording amplifiers often present a large input load capacitance to the neural signal source and hence take up large circuit area. They suffer due to the unavoidable trade-off between the input capacitance and chip area versus the amplifier gain. In this work, this trade-off is relaxed by replacing the single feedback capacitor with a clamped T-capacitor network. With this simple modification, the proposed amplifier can achieve the same mid-band gain with less input capacitance, resulting in a higher input impedance and a smaller silicon area. Prototype neural recording amplifiers based on this proposal were fabricated in 0.35 μm CMOS, and their performance is reported. The amplifiers occupy smaller area and have lower input loading capacitance compared to conventional neural amplifiers. One of the proposed amplifiers occupies merely 0.056 mm2. It achieves 38.1-dB mid-band gain with 1.6 pF input capacitance, and hence has an effective feedback capacitance of 20 fF. Consuming 6 μW, it has an input referred noise of 13.3 μVrms over 8.5 kHz bandwidth and NEF of 7.87. In-vivo recordings from animal experiments are also demonstrated. <s> BIB010 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> Conventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred noise requirement that determines the system sensitivity, while the supply voltage is determined by a DR requirement at the analog recording chain output that limits the maximum achievable resolution of the A-to-D conversion. In this paper, a power-efficient neural-recording architecture using a DR-folding technique is presented to enable low-voltage operation without compromising the DR performance. The proposed architecture can operate with only half of the typically required supply voltage, which results in about 50% power reduction. <s> BIB011 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> This paper presents a low-power low-noise amplifier for neural recording applications. A single-stage current-reuse telescopic topology is proposed to achieve high DC gain and improve the noise efficiency factor (NEF) while allowing the amplifier to be scaled for high bandwidth sensing applications and/or to achieve lower thermal noise floor. The design is fabricated in a standard 0.18μm CMOS process and occupies an active area of 0.16mm2. Experimental measurements show a 430nW power consumption from a 1.2V supply, a thermal noise floor of 63.8nV/√Hz and a corresponding NEF of 1.5. <s> BIB012 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> Front-end operational transconductance amplifier topologies <s> This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems. <s> BIB013
As illustrated in Fig. 4 , the active amplifying element is generally referred to as an operational transconductance amplifier (OTA). As opposed to an operational amplifier Front-end neural recording amplifier as proposed in  and explained in the text (OpAmp), the OTA does not have a power-consuming output driver circuit, as it does not need to bias any resistive elements other than the high-resistance pseudo-resistor in the feedback network in Fig. 4 . Four different CMOS OTA topologies that are often used in neural amplifiers are depicted in Fig. 5 . In all cases, the input-referred noise of the OTA arises from the thermal noise and flicker noise of the transistors' conduction channels  . The thermal noise of the OTA is inversely related to the amount of bias current supplied to the input differential pair of the OTA (M 1 and M 2 ), whereas the flicker noise component is inversely proportional to the active gate area of the input different pair. The transistors can be operated in either weak, midor strong inversion, of which the former achieves the highest transconductance (g m ) per unit ampere of bias current. Therefore, to reduce the input-referred noise, the NEF and the PEF, the input transistors are usually operated in the weak inversion region and supplied with a large biasing current. Although the gate areas of the input transistors are usually large to reduce the flicker noise component, the flicker noise reduction is contradicted by the increased capacitance multiplying effect contributed by the parasitic gate area BIB010 . Hence, the gate areas of the input differential pair must be appropriately sized according to the method described by Ng and Xu BIB010 . A comprehensive noise-versus-power consumption analysis of the OTAs, as shown in Fig. 5 , was performed by Sansen BIB003 , which led to the conclusion that the 2-stage Miller OTA (Fig. 5a ) and the symmetrical cascode OTA (Fig. 5b ) have higher (worse) obtainable NEFs compared to the alternative topologies. For both types of OTAs, a significant part of the total supply current is only used for maintaining proper biasing and feedback stability at their second stages, leaving less current to bias their input differential stages and therefore leading to a higher NEF. The telescopic cascode OTA (Fig. 5c ) achieves the lowest NEF among the listed OTAs, as all of the supply current is devoted to biasing the differential pair, allowing it to obtain a higher input g m (and hence lower noise and NEF) compared to the prior 2 OTAs. Indeed, previous studies BIB001 BIB002 BIB004 , which used either a symmetrical cascode OTA or a 2-stage Miller OTA, reported NEFs ranging from 4 to 17. Recent works BIB007 BIB008 , which used the telescopic cascode OTA, achieved consistently low NEF values below 2.6. For recording systems that must operate at supply voltages below 2.5 V and that must be implemented with CMOS processes lacking transistors with low threshold voltages, the telescopic cascode OTA cannot be used, as it requires at least 2.5 V to operate. Instead, the folded cascode OTA (Fig. 5d) is the natural choice for front-end Wattanapanitch et al.  further proposed an NEF optimization scheme for low-voltage neural amplifiers implemented using the folded cascode OTA, which were adopted in later studies BIB005 BIB006 . Resource sharing, which is generally employed at the system level, can be used to increase the power efficiency of the front-end amplifier. The term current reuse is used to describe amplifier topologies that share the biasing current among additional active elements or across channels. Figure 6 (reproduced from BIB009 ) shows an example currentreuse amplifier topology. Here, two complementary input pairs (P1, N1) and (P2, N2) are used within the same amplifier, which allows the NEF to be reduced by a factor of √2. If the g m of the NMOS and PMOS is assumed the same, the g m of the amplifier increases by a factor of two for the same amount of biasing current. This leads to a reduction in the thermal noise component of the input-referred noise (and hence the NEF) by a factor of √2. Amplifiers using this topology achieve state-of-the-art noise performance BIB011 BIB012 BIB013 . Although this current-reuse technique is a promising method for reducing the thermal noise component, it doubles the gate capacitance of the input differential pair. Thus, the gate area optimization technique proposed by Ng and Xu BIB010 must be used to reduce the input-referred noise due to flicker noise and capacitor transformer effect for the complimentary input pairs. 