SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. BASIC ARCHITECTURES <s> Couple to the communications wired and unwired networks growth, is the increasing demand for strong secure data transmission. New cryptographic standards are developed, and new encryption algorithms are designed, in order to satisfy the special needs for security. SHA-2 is the newest powerful standard in the hash functions families. In this paper, a VLSI architecture for the SHA-2 family is proposed. For every hash function SHA-2 (256, 384, and 512) of this standard, a hardware implementation is presented. All the implementations are examined and compared in the supported security level and in the performance by using hardware terms. This work can substitute efficiently the previous SHA-1 standard implementations, in every integrity security scheme, with higher offered security level, and better performance. In addition, the proposed implementations could be applied alternatively in the integrations of digital signature algorithms, keyed-hash message authentication codes and in random numbers generators architectures. <s> BIB001 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. BASIC ARCHITECTURES <s> A secure communications protocol contains a symmetric key cryptosystem, a hash algorithm and a method for providing digital signatures and key exchange using public key cryptography. This work presents an implementation of these core ciphers on a single FPGA. A novel architecture combining a symmetric-key and message authentication algorithm is proposed, with FIFO memory-blocks used as buffers to allow them run in parallel from the same data source. The generation of digital signatures and key exchange using a modular exponentiator core block is also considered. The complete design is implemented on a PCI prototyping card containing a Xilinx Virtex-2000E FPGA and SRAM memory banks. To optimise the data transfer rate between the SRAMs and the FPGA. The memory interface and encryption cores are partitioned into separate clock domains. Comparisons are then made between theoretical results from timing analysis reports and implemented results on the prototyping card. <s> BIB002 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. BASIC ARCHITECTURES <s> The continued growth of both wired and wireless communications has triggered the revolution for the generation of new cryptographic algorithms. SHA-2 hash family is a new standard in the widely used hash functions category. An architecture and the VLSI implementation of this standard are proposed in this work. The proposed architecture supports a multi-mode operation in the sense that it performs all the three hash functions (256, 384 and 512) of the SHA-2 standard. The proposed system is compared with the implementation of each hash function in a separate FPGA device. Comparing with previous designs, the introduced system can work in higher operation frequency and needs less silicon area resources. The achieved performance in the term of throughput of the proposed system/architecture is much higher (in a range from 277 to 417%) than the other hardware implementations. The introduced architecture also performs much better than the implementations of the existing standard SHA-1, and also offers a higher security level strength. The proposed system could be used for the implementation of integrity units, and in many other sensitive cryptographic applications, such as, digital signatures, message authentication codes and random number generators. <s> BIB003 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. BASIC ARCHITECTURES <s> A design approach to create small-sized high-speed implementation of the new version of secure hash algorithm is proposed. The resulted design can be easily embedded to operate in HMAC IP cores, providing a high degree of security. The proposed implementation does not introduce significant area penalty, compared to other competitive designs. However the achieved throughput presents an increase compared to commercially available IP cores that range from 43%-1830%. <s> BIB004 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. BASIC ARCHITECTURES <s> Designers of RFID security protocols can choose between a wide variety of cryptographic algorithms However, when implementing these algorithms on RFID tags fierce constraints have to be considered Looking at the common assumption in the literature that hash functions are implementable in a manner suitable for RFID tags and thus heavily used by RFID security protocol designers we claim the following Current standards and state-of-the-art low-power implementation techniques favor the use of block ciphers like the Advanced Encryption Standard (AES) instead of hash functions from the SHA family as building blocks for RFID security protocols In turn, we present a low-power architecture for the widely recommended hash function SHA-256 which is the basis for the smallest and most energy-efficient ASIC implementation published so far To back up our claim we compare the achieved results with the smallest available AES implementation The AES module requires only a third of the chip area and half of the mean power Our conclusions are even stronger since we can show that smaller hash functions like SHA-1, MD5 and MD4 are also less suitable for RFID tags than the AES Our analysis of the reasons of this result gives some input for future hash function designs. <s> BIB005 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. BASIC ARCHITECTURES <s> The main applications of the hash functions are met in the fields of communication's integrity and signature authentication. Many hash algorithms have been investigated and developed in the last years. This work is related to hash functions FPGA implementation. Field programmable gate arrays (FPGAs) being reconfigurable, flexible and physically secure are a natural choice for implementation of hash functions in a broad range of applications with different area-performance requirements. We propose a configurable secure hash algorithm (SHA) processor for extended signature authentication. This paper investigates different optimizations algorithms of recent techniques that have been proposed in the literature. In our implementation based on Xilinx Virtex FPGAs, the throughput of SHA processor is equal to 1296 Mbit/s. Speed/area results from these processors are analyzed and shown to compare favorably with other FPGA-based implementations. A fastest data throughput is achieved by our optimized algorithm <s> BIB006 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. BASIC ARCHITECTURES <s> The continued growth of both wired and wireless communications has triggered the revolution for the generation of new cryptographic algorithms. Hash functions are common and important cryptographic primitives, which are very critical for data integrity assurance and data origin authentication security services. Many hash algorithms have been investigated and developed in the last years. This work is related to hash functions FPGA implementation. SHA-2 hash family is a new standard in the widely used hash functions category. An architecture and the FPGA implementation of this standard are proposed in this work. We propose a reconfigurable SHA-2 processor in the sense that it performs the two hash functions (256, and 512) of the SHA-2 standard for extended signature authentication. This paper investigates optimizations techniques that have recently been proposed in the literature. These techniques consist mostly in operation rescheduling and hardware reutilization, allowing a significant reduction of the critical path while the required area also decreases. As several 64-bit adders are needed in SHA-512 hash value computation, investigations on the adders implementations on FPGAs are analyzed and developed, with a view to reduce the chip area. The proposed processor is compared with the implementation of each hash function in a separate FPGA device to demonstrate that our architecture achieves a performance comparable to separate implementations while requiring much less hardware. Two types of FPGAs are evaluated in order to produce realistic results. Speed/area results from this processor are analyzed and are shown to demonstrate that our designs achieves a favorably performances with other FPGA-based implementations. A fastest data throughput is achieved by our optimized design. <s> BIB007 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. BASIC ARCHITECTURES <s> Cryptographic algorithms are used to enable security services that are the core of modern communication systems. In particular, Hash functions algorithms are widely used to provide services of data integrity and authentication. These algorithms are based on performing a number of complex operations on the input data, thus it is important to count with novel designs that can be efficiently mapped to hardware architectures. Hash functions perform internal operations in an iterative fashion, which open the possibility of exploring several implementation strategies. In the paper, two different schemes to improve the performance of the hardware implementation of the SHA-2 family of algorithms are proposed. The main focus of the proposed schemes is to reduce the critical path by reordering the operations required at each iteration of the algorithm. Implementation results on an FPGA device show an improvement on the performance on the SHA-256 algorithm when compared against similar previously proposed approaches. <s> BIB008 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. BASIC ARCHITECTURES <s> In order to design efficient hardware implementations of cryptographic algorithms for a particular application, itis often required to explore several architectures in order to select the one that offers the appropriate trade-off between throughput and hardware resources. A natural choice for performing a design space exploration are the Field Programmable Gate Arrays (FPGAs) for being reconfigurable, flexible and physically secure devices. In this paper we explore several architectures for implementing the SHA-512 algorithm based on the loop unrolling technique and analyze their area-performance trade-offs. The analysis consists on unrolling at different levels the main loop which is the most costly part in the SHA-512 algorithm. The resulting hardware architectures are implemented and analyzed in order to identify the critical path and make decisions on the architectural design. The obtained results provide a practical guide to understand the effect of introducing different levels (1, 2, 4, 5, 8) of unrolling in terms of throughput and hardware resources. The hardware architecture 4x that partially unrolls four iterations of the main loop of the SHA-512 algorithm reports the best performance compared against related works, while the1x architecture exhibits the best efficiency. <s> BIB009 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. BASIC ARCHITECTURES <s> Hash function algorithms are widely used to provide security services of integrity and authentication, being SHA-2 the latest set of hash algorithms standardized by the US Federal Government. The main computation block in SHA-2 algorithms is governed by a loop with high data dependence for which several implementation strategies are explored in this work as well as designs efficiently mapped to hardware architectures. Four new different hardware architectures are proposed to improve the performance of SHA-256 algorithms, reducing the critical path by reordering some operations required at each iteration of the algorithm and computing some values in advance, as possible as data dependence allows. The proposed designs were implemented and validated in the FPGA Virtex-2 XC2VP-7. The achieved results show a significant improvement on the performance of the SHA-256 algorithm compared to similar previously proposed approaches, obtaining a throughput of 909Mbps and an improved efficiency of 0.713Mbps/slice. <s> BIB010 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. BASIC ARCHITECTURES <s> In this paper, we implement the SHA-256 FPGA hardware module for the security protocol of the IEEE 1609.2 vehicle communication (VC). VC requires high-throughput and low-latency hardware architectures. For fast and efficient design, we exploit parallel structures for preprocessing and hash computation in SHA-256. The proposed design is im- plemented in Vertex-5 and verified for correct hash operation. As a result, we can achieve up to 179.08 MHz with 2796 slices. <s> BIB011 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. BASIC ARCHITECTURES <s> Hash functions play an important role in modern cryptography. They are widely used to provide services of data integrity and authentication. The hash algorithms are based on performing a number of complex operations on the input data that require a significant amount of computing resources especially when the input data are huge. Thus, hardware implementation is far more suitable, for security and performances execution issues, compared to the corresponding software implementations. Hash functions perform internal operations in an iterative fashion, which open the possibility of exploring several implementation strategies. In this paper, we are concerned by optimizing the hardware implementation of the SHA-256 algorithm on virtex-5 Xilinx FPGA. Our main contribution is to design a compact SHA-256 core and to speed-up its critical paths. These are respectively seven and six words addition. The CS (Carry Save) representation is advantageously used to overcome the carry propagation, until the last addition. Special efforts were made to design, at the LUT level, the two components (compressors 7:2 and 6:2) which are the key features of our design; their delay is data path independent and equivalent to the delay of two LUT6. The resulting architecture is compact and operates at 170 MHz with throughput of 1.36 Gbps. <s> BIB012
The work in BIB001 proposes a hardware implementation of Equations (II.6) to (II.11) with dedicated logic within a transformation round unit. Since the equations employ only bitwise logic operations, shift operations and modulo additions, corresponding logic gates, bit reordering and modular adders are used to build up the transformation round unit. This is surrounded by a ROM, which provides it with the K t constant values, and a number of support units. The Constants Unit supplies the transformation round core with the initialisation values DM . The initial values DM (0) are hard-coded in the FPGA LUTs, while for the subsequent PDBs the initialisation values DM provided by the Constants Unit are updated by the Last Transformation Unit. This unit includes an array of adders which perform Equation (II.13) to update the intermediate message digest. The W t values are provided by a W t -unit, which in turn is fed by the Padding Unit. A very similar architecture is implemented in BIB011 on a Xilinx Virtex-5 FPGA board, while BIB012 proposes the use of parallel adders to implement the additions leading to the computation of A t+1 and E t+1 . The work in BIB003 implements a multi-mode variant of BIB001 , where a Control Unit is in charge of reconfiguring the circuit to perform one of the different SHA-2 variants, according to the user's specifications. The most important aspect of BIB003 is the management of the different word widths of SHA-256 and SHA-512. This is tackled by clearing the least significant 32 bits of the datapath when SHA-256 is selected. The multi-mode architecture of  takes advantage of the similarities between MD5, SHA-1, and SHA-256 to support all of them. On the other hand, it does not support SHA-512, which is the case in BIB003 . This exclusion is due to the fact that SHA-512 works on 64-bit words, whereas  is a 32 −bit architecture. A straightforward implementation of loop unrolling is presented in BIB002 , where multiple instances of the transformation logic round are placed between registers. This allows for evaluating different values of the unrolling factor. Loop unrolling by a factor 2 is also exploited in  with the aim of decreasing power consumption while increasing parallelism in the round function computation. This architecture is further optimized in BIB004 where multi-operand additions are compressed by using CSAs. The same optimisation techniques are exploited in BIB006 , where a multi-mode architecture is proposed. This architecture is further optimised in BIB007 by observing that, due to data dependencies, the whole round function can be computed using only two CSAs without incurring any performance penalty, by properly scheduling the various additions. In BIB008 , a reordering within the transformation round is proposed. The following variable is defined and substituted into Equation (IV.1), leading to This architecture is further improved in BIB010 with the addition of CSAs, while in BIB009 the application of loop unrolling is explored, with the unrolling factor 4 yielding the best results. In order to achieve low power consumption, BIB005 reduces the number of adders and the simultaneously clocked register by employing the loop folding technique. Only one adder is used to perform all the operations of the Compressor and the Expander, which therefore do not operate in parallel and can be disconnected from the clock network accordingly.