Low power processor architectures and contemporary techniques for power optimization—a review <s> III. ADDITIONAL APPROACHES <s> Memory is one of the most restricted resources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressed code CPU, a cache miss triggers the decompression of a main memory block, before it gets transferred to the cache. Because the code must be decompressible starting from any point (or at least at cache block boundaries), most file-oriented compression techniques cannot be used. We propose two algorithms to compress code in a space-efficient and simple to decompress way, one which is independent of the instruction set and another which depends on the instruction set. We perform experiments on true instruction sets, a typical RISC (MIPS) and a typical CISC (x86) and compare our results to existing file-oriented compression algorithms. <s> BIB001 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> III. ADDITIONAL APPROACHES <s> It is widely acknowledged that even as VLSI technology advances, there is a looming crisis that is an important obstacle to the widespread deployment of mobile embedded devices, namely that of power. This problem can be tackled at many levels like devices, logic, operating systems, micro-architecture and compiler. While there have been various proposals for specific compiler optimizations for power, there has not been any attempt to systematically map out the space for possible improvements. In this paper, we quantitatively characterize the limits of what a compiler can do in optimizing for power using precise modeling of a state-of-the-art embedded processor in conjunction with a robust compiler. We provide insights to how compiler optimizations interact with the internal workings of a processor from the perspective of power consumption. The goal is to point out the promising and not so promising directions of work in this area, to guide the future compiler designer. <s> BIB002
Although the focus of the paper is processor and chip level technologies for achieving low power but it is necessary to briefly introduce well known methodologies which can be applied into other stages of design. With new design ideas optimization part into compiler is being equally weighed as having power efficient hardware. Chakrapani et al. BIB002 identify two classes A and B of the compiler optimizations for energy reduction. Class A BIB002 consists of energy saving due to performance improvement such as reductions in the number of loads and stores, procedure cloning, loop unrolling, procedure inlining, and loop transformations. Class B BIB002 uses techniques like instruction scheduling; register pipelining, innovations in code selection to replace high power dissipating instructions with other instructions. One further method centers on the application of compression algorithms to instruction code, cache blocks. Different code compression schemes for embedded systems are discussed in BIB001 . Arithmetic circuits are generously used in Arithmetic Logic Unit (ALU), Floating Point Unit (FPU) designs as well as DSP. Piguet  discusses various power efficient CMOS circuit design issues for basic arithmetic operators such as adder and their use in multiplier, square etc. In the following some novel low power architectures are introduced.