A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> This paper describes the symbolic execution of programs. Instead of supplying the normal inputs to a program (e.g. numbers) one supplies symbols representing arbitrary values. The execution proceeds as in a normal execution except that values may be symbolic formulas over the input symbols. The difficult, yet interesting issues arise during the symbolic execution of conditional branch type statements. A particular system called EFFIGY which provides symbolic execution for program testing and debugging is also described. It interpretively executes programs written in a simple PL/I style programming language. It includes many standard debugging features, the ability to manage and to prove things about symbolic expressions, a simple program testing manager, and a program verifier. A brief discussion of the relationship between symbolic execution and program proving is also included. <s> BIB001 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> The predictability of the computation time of program modules is very important for estimating an accurate worst-case execution time (WCET) of a task in real-time systems. Dynamic storage allocation (DSA) is a common programming technique. Although many DSA algorithms have been developed, they focus on the average execution time rather than the WCET, making it is very difficult to calculate their WCET accurately. In this paper, we propose a new algorithm called Half-Fit whose WCET can be calculated accurately. The algorithm finds a free block without searching on a free list or tree, allowing extra unusable memory called incomplete memory use. In a simulation following a queueing model of M/G//spl infin/, Half-Fit has the advantage over the binary buddy system of more efficient storage utilization. The binary buddy system is a conventional algorithm whose WCET can be calculated. <s> BIB002 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> To narrow the widening gap between processor and memory performance, the authors propose improving the cache locality of pointer-manipulating programs and bolstering performance by careful placement of structure elements. It is concluded that considering past trends and future technology, it seems clear that the processor-memory performance gap will continue to increase and software will continue to grow larger and more complex. Although cache-conscious algorithms and data structures are the first and perhaps best place to attack this performance problem, the complexity of software design and an increasing tendency to build large software systems by assembling smaller components does not favor a focused, integrated approach. We propose another, more incremental approach of cache-conscious data layout, which uses techniques such as clustering, coloring, and compression to enhance data locality by placing structure elements more carefully in the cache. <s> BIB003 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> In order to contribute to the solution of the software reliability problem, tools have been designed to analyze statically the run-time behavior of programs. Because the correctness problem is undecidable, some form of approximation is needed. The purpose of abstract interpretation is to formalize this idea of approximation. We illustrate informally the application of abstraction to the semantics of programming languages as well as to static program analysis. The main point is that in order to reason or compute about a complex system, some information must be lost, that is the observation of executions must be either partial or at a high level of abstraction. ::: ::: A few challenges for static program analysis by abstract interpretation are finally briefly discussed. ::: ::: The electronic version of this paper includes a comparison with other formal methods: typing, model-checking and deductive methods. <s> BIB004 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> Dynamic storage allocation (DSA) algorithms play an important role in the modern software engineering paradigms and techniques (such as object oriented programming). Using DSA increases the flexibility and functionalities of applications. There exists a large number of references to this particular issue in the literature. However, the use of DSA has been considered a source of indeterminism in the real-time domain, due to the unconstrained response time of DSA algorithms and the fragmentation problem. Nowadays, real-time applications require more flexibility: the ability to adjust system configuration in response to workload changes and application reconfiguration. This aspect adds value to the definition and implementation of dynamic storage allocation algorithms. Considering these reasons, DSA algorithms with a bounded and acceptable timing behaviour must be developed to be used by real-time operating systems (RTOSs). In this paper a DSA algorithm called two-level segregated fit memory allocator (TLSF), developed specifically to be used by RTOS, is introduced. The TLSF algorithm provides explicit allocation and deallocation of memory blocks with a temporal cost /spl Theta/(1). <s> BIB005 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> Tools for acquiring dynamic memory address information for large scale applications are important for performance modeling, optimization, and for trace-driven simulation. However, straightforward use of binary instrumentation tools for such a fine-grained task as address tracing can cause astonishing slowdown in application run time. For example, in a large scale FY05 collaboration with the Department of Defense High Performance Computing Modernization Office (HPCMO), over 1 million processor hours were expended in order to gather address information on 7 parallel applications. In this paper, we discuss in detail the issues surrounding the performance of memory address acquisition using low-level binary instrumentation tracing. We present three techniques and optimizations to improve performance: 1) SimPoint-guided sampling, 2) instrumentation tool routine optimization, and 3) reduction of instrumentation points through static application analysis. The use of these three techniques together reduces instrumented application slowdown by an order of magnitude. The techniques are generally applicable and have been deployed in the MetaSim tracer thereby enabling memory address acquisition for real-sized applications. We expect the optimizations reported here reduce the HPCMO effort by approximately 80% in FY06. <s> BIB006 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> We propose a real real-time memory management system called Compact-fit that offers both time and space predictability. Compact-fit is a compacting memory management system for allocating, deallocating, and accessing memory in real time. The system provides predictable memory fragmentation and response times that are constant or linear in the size of the request, independently of the global memory state. We present two Compact-fit implementations and compare them to established memory management systems, which all fail to provide predictable memory fragmentation. The experiments confirm our theoretical complexity bounds and demonstrate competitive performance. In addition, we can control the performance versus fragmentation trade-off via our concept of partial compaction. The system can be parameterized with the needed level of compaction, improving the performance while keeping memory fragmentation predictable. <s> BIB007 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> Current worst-case execution time (WCET) analyses do not support programs using dynamic memory allocation. This is mainly due to the unpredictable cache performance when standard memory allocators ::: are used. We present algorithms to compute a static allocation for programs using dynamic memory allocation. Our algorithms strive to produce static allocations that lead to minimal WCET times in a subsequent WCET analyses. Preliminary experiments suggest that static allocations for hard real-time applications can be computed at reasonable computational costs. <s> BIB008 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> Poor placement of data blocks in memory may negatively impact application performance because of an increase in the cache conflict miss rate [18]. For dynamically allocated structures this placement is typically determined by the memory allocator. Cache index-oblivious allocators may inadvertently place blocks on a restricted fraction of the available cache indexes, artificially and needlessly increasing the conflict miss rate. While some allocators are less vulnerable to this phenomena, no general-purpose malloc allocator is index-aware and methodologically addresses this concern. We demonstrate that many existing state-of-the-art allocators are index-oblivious, admitting performance pathologies for certain block sizes. We show that a simple adjustment within the allocator to control the spacing of blocks can provide better index coverage, which in turn reduces the superfluous conflict miss rate in various applications, improving performance with no observed negative consequences. The result is an index-aware allocator. Our technique is general and can easily be applied to most memory allocators and to various processor architectures. Furthermore, we can reduce inter-thread and inter-process conflict misses for processors where threads concurrently share the level-1 cache such as the Sun UltraSPARC-T2™ and Intel "Nehalem" by coloring the placement of blocks so that allocations for different threads and processes start on different cache indexes. <s> BIB009 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> General-purpose dynamic memory allocation algorithms strive for small memory fragmentation and good av\-er\-age-case response times. Hard real-time settings, in contrast, place different demands on dynamic memory allocators: worst-case response times are more important than av\-er\-age-case response times. Furthermore, predictable cache behavior is a prerequisite for timing analysis to derive tight bounds on a program's execution time. This paper proposes a novel algorithm that meets these demands. It guarantees constant response times, does not cause unpredictable cache pollution, and allocations are cache-set directed, i.e., allocated memory is guaranteed to be mapped to a given cache set. The latter two are necessary to enable a subsequent precise static cache analysis. <s> BIB010 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> As programs become increasingly complex, tools for monitoring and performing dynamic analysis of running software are very much desirable. A flexible program source-level instrumentation framework is proposed in the paper. Unlike most of the existing tools, the proposed instrumentation framework has the ability to instrument for various events, the flexibility to instrument (or not to instrument) specific events and mechanisms to control instrumentation overhead, and it also provides convenience for applications to process the collected runtime instrumentation information for performing dynamic analysis. A prototype of this instrumentation framework is implemented and evaluated on the KLEE Symbolic Virtual Machine. <s> BIB011 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> In emerging and future high-end processor systems, tolerating increasing cache miss latency and properly managing memory bandwidth will be critical to achieving high performance. Prefetching, in both hardware and software, is among our most important available techniques for doing so; yet, we claim that prefetching is perhaps also the least well-understood. Thus, the goal of this study is to develop a novel, foundational understanding of both the benefits and limitations of hardware and software prefetching. Our study includes: source code-level analysis, to help in understanding the practical strengths and weaknesses of compiler- and software-based prefetching; a study of the synergistic and antagonistic effects between software and hardware prefetching; and an evaluation of hardware prefetching training policies in the presence of software prefetching requests. We use both simulation and measurement on real systems. We find, for instance, that although there are many opportunities for compilers to prefetch much more aggressively than they currently do, there is also a tangible risk of interference with training existing hardware prefetching mechanisms. Taken together, our observations suggest new research directions for cooperative hardware/software prefetching. <s> BIB012 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> Shared cache partitioning is a well-known technique used in multicore real-time systems to isolate task workloads and improve system predictability. Presently, the state-of-the-art studies that evaluate shared cache partitioning on multicore processors lack two key issues. First, the cache partitioning mechanism is typically implemented either in a simulation environment or in a general-purpose OS, and so the impact of kernel activities, such as interrupt handlers and context switching, on the task partitions tend to be overlooked. Second, the evaluation is typically restricted to either a global or partitioned scheduler, thereby by falling to compare the performance of cache partitioning when tasks are scheduled by different schedulers. In this work, we design and implement a shared cache partitioning mechanism in a multicore component-based RTOS capable of assigning partitions to internal OS data structures, including task and system stacks and interrupt handlers data. We evaluate our shared cache partitioning mechanism running task sets under global (G-EDF) and partitioned (P-EDF) multicore real-time scheduling algorithms. Our results indicate that a lightweight RTOS does not impact real-time tasks, and shared cache partitioning has different behavior depending on the scheduler and the task's working set size. <s> BIB013 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> Multi-core architectures are shaking the fundamental assumption that in real-time systems the WCET, used to analyze the schedulability of the complete system, is calculated on individual tasks. This is not even true in an approximate sense in a modern multi-core chip, due to interference caused by hardware resource sharing. In this work we propose (1) a complete framework to analyze and profile task memory access patterns and (2) a novel kernel-level cache management technique to enforce an efficient and deterministic cache allocation of the most frequently accessed memory areas. In this way, we provide a powerful tool to address one of the main sources of interference in a system where the last level of cache is shared among two or more CPUs. The technique has been implemented on commercial hardware and our evaluations show that it can be used to significantly improve the predictability of a given set of critical tasks. <s> BIB014 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> Static timing analysis is the state-of-the-art practice of ascertaining the timing behavior of current-generation real-time embedded systems. The adoption of more complex hardware to respond to the increasing demand for computing power in next-generation systems exacerbates some of the limitations of static timing analysis. In particular, the effort of acquiring (1) detailed information on the hardware to develop an accurate model of its execution latency as well as (2) knowledge of the timing behavior of the program in the presence of varying hardware conditions, such as those dependent on the history of previously executed instructions. We call these problems the timing analysis walls. In this vision-statement article, we present probabilistic timing analysis, a novel approach to the analysis of the timing behavior of next-generation real-time embedded systems. We show how probabilistic timing analysis attacks the timing analysis walls; we then illustrate the mathematical foundations on which this method is based and the challenges we face in the effort of efficiently implementing it. We also present experimental evidence that shows how probabilistic timing analysis reduces the extent of knowledge about the execution platform required to produce probabilistically accurate WCET estimations. <s> BIB015 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> Caches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses to provide tight WCET estimates. Probabilistic Timing Analysis (PTA) has emerged as a solution to reduce the amount of information needed to provide tight WCET estimates, although it imposes new requirements on hardware design. At cache level, so far only fully-associative random-replacement caches have been proven to fulfill the needs of PTA, but they are expensive in size and energy. In this paper we propose a cache design that allows set-associative and direct-mapped caches to be analysed with PTA techniques. In particular we propose a novel parametric random placement suitable for PTA that is proven to have low hardware complexity and energy consumption while providing comparable performance to that of conventional modulo placement. <s> BIB016 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> Caches are key resources in high-end processor architectures to increase performance. In fact, most high-performance processors come equipped with a multi-level cache hierarchy. In terms of guaranteed performance, however, cache hierarchies severely challenge the computation of tight worst-case execution time (WCET) estimates. On the one hand, the analysis of the timing behaviour of a single level of cache is already challenging, particularly for data accesses. On the other hand, unifying data and instructions in each level, makes the problem of cache analysis significantly more complex requiring tracking simultaneously data and instruction accesses to cache. In this paper we prove that multi-level cache hierarchies can be used in the context of Probabilistic Timing Analysis and tight WCET estimates can be obtained. Our detailed analysis (1) covers unified data and instruction caches, (2) covers different cache-write policies (write-through and write back), write allocation policies (write-allocate and non-write-allocate) and several inclusion mechanisms (inclusive, non-inclusive and exclusive caches), and (3) scales to an arbitrary number of cache levels. Our results show that the probabilistic WCET (pWCET) estimates provided by our analysis technique effectively benefit from having multi-level caches. For a two-level cache configuration and for EEMBC benchmarks, pWCET reductions are 55% on average (and up to 90%) with respect to a processor with a single level of cache. <s> BIB017 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> This paper integrates analysis of probabilistic cache related pre-emption delays (pCRPD) and static probabilistic timing analysis (SPTA) for multipath programs running on a hardware platform that uses an evict-on-miss random cache replacement policy. The SPTA computes an upper bound on the probabilistic worst-case execution time (pWCET) of the program, which is an exceedance function giving the probability that the execution time of the program will exceed any given value on any particular run. The pCRPD analysis determines the maximum effect of a pre-emption on the pWCET. The integration between SPTA and pCRPD updates the pWCET to account for the effects of one or more pre-emptions at any arbitrary points in the program. This integration is a necessary step enabling effective schedulability analysis for probabilistic hard real-time systems that use pre-emptive or co-operative scheduling. The analysis is illustrated via a number of benchmark programs. <s> BIB018 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> To compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis. The timing-relevant result of the cache analysis is the categorization of the accesses to cached memory. Categorizations that are obtainable by the well-known must and may cache analysis [Ferdinand 1997] are always-hit, always-miss and not-classified. The cache persistence analysis tries to provide additional information for the not-classified case to limit the number of misses. There exists a cache persistence analysis by Ferdinand and Wilhelm based on abstract interpretation computing these classifications. In this article, we present a correctness issue with this analysis. To fix this issue, we propose two new abstract interpretation based persistence analyses and show their safety. One is based on the known may analysis and a second one on the concept of conflict counting. For fully timing compositional architectures [Wilhelm et al. 2009] the persistence information is straightforward to use. We will apply the concepts of persistence analysis for the first time to state-of-the-art architectures that exhibit both timing anomalies and domino effects. Such architectures do not allow the analyzer to quantify the costs of a single cache hit or miss in isolation. To make the usage of the persistence information feasible, we integrate the presented novel persistence analyses together with a novel path analysis approach into the industrially used WCET analyzer aiT. <s> BIB019 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> Shared caches in multicores challenge Worst-Case Execution Time (WCET) estimation due to inter-task interferences. Hardware and software cache partitioning address this issue although they complicate data sharing among tasks and the Operating System (OS) task scheduling and migration. In the context of Probabilistic Timing Analysis (PTA) time-randomised caches are used. We propose a new hardware mechanism to control inter-task interferences in shared time-randomised caches without the need of any hardware or software partitioning. Our proposed mechanism effectively bounds inter-task interferences by limiting the cache eviction frequency of each task, while providing tighter WCET estimates than cache partitioning algorithms. In a 4-core multicore processor setup our proposal improves cache partitioning by 56% in terms of guaranteed performance and 16% in terms of average performance. <s> BIB020 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> The translation look aside buffer (TLB) improves the performance of systems by caching the virtual page to physical frame mapping. But TLBs present a source of unpredictability for real-time systems. Standard heap allocated regions do not provide guarantees on the TLB set that will hold a particular page translation. This unpredictability can lead to TLB misses with a penalty of up to thousands of cycles and consequently intra- and inter-task interference resulting in loose bounds on the worst case execution time (WCET) and TLB-related preemption delay. In this work, we design and implement a new heap allocator that guarantees the TLB set, which will hold a particular page translation on a uniprocessor of a contemporary architecture. The allocator is based on the concept of page coloring, a software TLB partitioning method. Virtual pages are colored such that two pages of different color cannot map to the same TLB set. Our experimental evaluations confirm the unpredictability associated with the standard heap allocation. Using a set of synthetic and standard benchmarks, we show that our allocator provides task isolation for real-time tasks. To the best of our knowledge, such TLB isolation without special hardware support is unprecedented, increases TLB predictability and can facilitate WCET analysis. <s> BIB021 </s> A Survey on Cache Management Mechanisms for Real-Time Embedded Systems <s> FUTURE DIRECTIONS <s> Tools for memory access detection are widely used, playing an important role especially in real-time systems. For example, on multi-core platforms, the problem of co-scheduling CPU and memory resources with hard real-time constraints requires a deep understanding of the memory access patterns of the deployed task set. While code execution flow can be analyzed by considering the control-flow graph and reasoning in terms of basic blocks, a similar approach cannot apply to data accesses. In this paper, we propose MadT, a tool that uses a novel mechanism to perform memory access detection of general purpose applications. MadT does not perform binary instrumentation and always executes application code natively on the platform. Hence it can operate entirely in user-space without sand-boxing the task under analysis. Furthermore, MadT provides detailed symbolic information about the accessed memory structures, so it is able to translate the virtual addresses to their original symbolic variable names. Finally, it requires no modifications to application source code. The proposed methodology relies on existing OS-level capabilities. In this paper, we describe how MadT has been implemented on commercial hardware and compare its performance with state-of-the-art software techniques for memory access detection. <s> BIB022
None of the reviewed works support the three cache management mechanisms (cache locking or partitioning, and memory allocator). Some of them, such as Suhendra and BIB003 no yes clustering and page coloring CIF BIB009 no yes index-based Dynamic translation BIB008 yes no -C++ new overload BIB013 no yes page coloring PALLOC ] no yes page coloring Half-fit BIB002 yes no -TLSF BIB005 yes no -TLSF-I  yes no -CF BIB007 yes no -CAMA BIB010 yes yes index-based and BIB014 , provide support for cache partitioning and locking but are not integrated in a cache-aware real-time memory allocator. Other works, such as BIB013 and BIB010 , have a cache-aware memory allocator but do not support cache locking. Finally, the work in integrates cache management using coloring and locking with a DRAM-aware memory allocator. The allocator, however, is not fully time-predictable. In general, the integration of the presented techniques is feasible and would result in a good approach to improve the predictability at the shared cache level. Nevertheless, there are several processor architectural aspects that impact the predictability of real-time applications and are still open problems. Below, we provide a discussion of future research directions considering some aspects of current multicore processors, such as hardware prefetchers, I/O devices, cache coherence protocols, processor architecture, and random caches. -Hardware prefetchers: By fetching instructions and/or data from memory to cache before the processor needs it, hardware prefetching reduces the latency of accesses to main memory. However, hardware prefetchers can be quite unpredictable. For instance, stride prefetchers use the distance (i.e., stride of the load) between the current memory and last memory addresses referenced by a load instruction to fetch an address formed by the last address plus the stride distance. For a complete review on hardware prefetchers, please refer to BIB012 . Usually, real-time application designers disable hardware prefetchers to improve predictability. If page coloring could also be supported by hardware prefetchers, a real-time tasks would not interfere with another one. Moreover, rearranging data structures to be contiguously allocated in memory and re-using memory locations that have been released help to improve the hardware prefetcher performance. -Input and Output: I/O devices can also interfere with real-time tasks at the shared cache level, either directly by DMA or through the cache coherence protocol (snooping). This behavior is the same as a regular core. Thus, cache locking and partitioning could also include I/O devices to avoid this interference. We believe that I/O is a hot future topic for real-time research. -Cache Coherence: To the best of our knowledge no existing static WCET analysis technique is able to account for the effects of the coherence protocol. When tasks share data or colors (in page coloring), they access the same cache lines, incurring in extra overhead. If frequent shared memory accesses occur, the WCET can be largely affected BIB013 . Depending on the application, shared data is intrinsic and cannot be avoided. In these cases, an alternative to decrease the contention caused by the cache coherence protocol is to combine page coloring, cache locking, scheduling, and hardware performance counters (HPCs). For instance, HPCs would feed the RTOS scheduler with runtime information about cache coherence activities, indicating when tasks are interfering with each other. Then, the scheduler can take an action, as to prevent the execution of interfering tasks. Another alternative is to disable caching for shared pages. Thus, invalidations caused by the coherence protocols are avoided. -Processor architecture: Several features could be added to current multicore architectures to improve their predictability at the cache levels. For instance, to deal with the limited number of colors in page coloring, it would be possible to implement a mechanism of page recoloring. Without any additional hardware support, page recoloring requires the copy of complete pages, which may take a long time and lead to deadline misses. Frequent recoloring of a large number of tasks negates the benefit of page coloring ]. An approach is to provide a mechanism of retagging in the page address layout to enable page recoloring without page copies. Moreover, to provide HRT guarantees, cache locking is essential and must be supported by all embedded multicore processors. We suggest that hardware designers should add cache-locking capabilities in future multicore processors. As cache locking is implemented in hardware, the runtime overhead is almost negligible. Table VI provides a nonexhaustive list of COTS processors and platforms that feature hardware support for cache managements schemes (locking and partitioning). ARM9 single-core processors are among the first to introduce support for cache lockdown features in hardware. Dedicated registers are provided for controlling which cache ways are made unavailable for allocation to the standard replacement policy. However, ARM9 implementations often feature one level of virtually indexed, virtually tagged cache where locked data is flushed upon page-table switching. ARM Cortex-A9 CPUs introduce a second level of cache which is shared in multicore implementations and managed by the L2C-310 (PL-213) cache controller. L2 sizes can range from 512 KB to 2 MB in these chips and cache blocks are physically indexed and tagged. Although cache-locking features can be configured at synthesis time by manufacturers, it is often the case that L2 controllers in Cortex-A9 chips are configured to support cache management features. A nonatomic lockdown by-line scheme is provided, together with the more flexible lockdown by-master. In the latter scheme, each core is associated a register to configure the state of each cache way with respect to operations performed by the considered core. For instance, the same cache way can be configured to accept allocations for lines fetched by core A, while not allowing any allocation for requests originated from core B. As such, lockdown by-master can be used to enforce traditional by-way locking or by-way partitioning. Freescale PowerPC platforms have historically provided more attention to safetycritical applications, often adding advanced support for performance monitoring and tuning. As a part of the extended hardware support offered in these platforms, cache management schemes are often provided at the ISA level or at the cache controller level. Freescale e500 and e600 processors feature two levels of private cache. In both single-core and multicore configurations (e500mc and e600mc), they provide atomic instructions to perform by-line prefetch and lock of cache content. These instructions can be used to manage the content of both the private levels of cache. Multicore configurations introduce a third level of cache, called platform cache, which can be managed using the same instructions and feature additional by-way/by-master cache-partitioning capabilities. The newer Freescale e5500 and e6500 CPUs not only maintain the support for atomic cache management instructions but also introduce by-thread cache-partitioning capabilities at the second level of private cache (L2). Finally, Intel has recently introduced support for cache management and monitoring on server-grade CPUs: the Xeon E5 v3 family. Although these processors are not meant for the embedded market, soft real-time applications can be optimized at an OS level to use the large caches (20MB to 45MB) of these processors through the newly introduced features. The Intel Cache Allocation Technology (CAT) allows the definition of classes of service (COS). Each thread can be associated to a COS and for each COS the hardware provides a cache allocation bitmap. If bit n is set in the bitmap associated to COS A, all the threads defined in this class of service will be allowed to allocate cache lines in the n − th cache partition. Bitmaps for different COS's can be configured independently, allowing de-facto overlapped and private assignment of cache blocks to threads. -Random Caches: Recently, PTA (Probabilistic Timing Analysis) has been proposed as an alternative to conventional timing analysis that can be highly pessimistic for the worst case BIB015 . PTA provides pWCET estimates (Probabilistic WCET) that can be exceeded with a given probability. That is, a pWCET with an associated low probability, say 10 −15 , means that the probability for the execution time to exceed this pWCET is 10 −15 . However, PTA techniques require the execution times of programs to have a probability of occurrence that is independent and identically distributed. These two features are essential to allow using random variables and apply statistical methods for analyzing the system. At the cache level, caches with LRU replacement policy cannot be used because the result of each memory access is dependent on the previous accesses. A fully associative cache with random replacement is one example that can be used for PTA. Along this line of research, PTA has been applied to a single-level cache BIB016 ], multilevel caches BIB017 ] and for CRPD BIB018 . Recently, PTA was used for shared caches to estimate the intercore cache conflicts BIB020 ]. -Translation Lookaside Buffer (TLB): The paging mechanism relies on a table to perform address translation at runtime. Since the table is too large to fit in processor registers, instead a subset of the table is stored in a hardware structure known as TLB. The TLB functions as a specialized data cache for page table entries and, therefore, suffers from predictability problems common to other caches, including intratask, intracore, and intercore interference BIB021 . Due to its similarity to data caches, both locking and partitioning solutions appear to be feasible, but there is very little published work focusing on TLB management for real-time systems:  discuss TLB locking based on the support provided by some ARM platforms, while BIB021 supports index-based partitioning in the TLB using page coloring. -Profiling Techniques: The majority of challenges in designing cache management techniques lay in the establishment of a good trade-off between the determinism imposed on the hardware circuitry and the resulting performance. However, without full knowledge of the application behavior in terms of memory access pattern, this trade-off is decided empirically for all the applications. Consequently, only specific classes of applications can benefit from a specific cache management technique. The ability to profile and analyze the key aspects of applications' memory access patterns is a turning point in the optimization of cache management techniques. A body of works exists that use abstract interpretation BIB004 BIB019 , symbolic execution BIB001 ], hardware and software memory tracing BIB011 BIB006 BIB022 to gather information about memory access patterns. These techniques have been mostly used to perform static analysis. Nonetheless, similar approaches could be used to evolve cache management mechanism into memory pattern-aware techniques.