A Brief Overview of Novel Approaches in Designing High Performance VCOs <s> A. A novel design using capacitive devision <s> Based on a physical understanding of phase-noise mechanisms, a passive LC filter is found to lower the phase-noise factor in a differential oscillator to its fundamental minimum. Three fully integrated LC voltage-controlled oscillators (VCOs) serve as a proof of concept. Two 1.1-GHz VCOs achieve -153 dBc/Hz at 3 MHz offset, biased at 3.7 mA from 2.5 V. A 2.1-GHz VCO achieves -148 dBc/Hz at 15 MHz offset, taking 4 mA from a 2.7-V supply. All oscillators use fully integrated resonators, and the first two exceed discrete transistor modules in figure of merit. Practical aspects and repercussions of the technique are discussed. <s> BIB001 </s> A Brief Overview of Novel Approaches in Designing High Performance VCOs <s> A. A novel design using capacitive devision <s> This letter presents a swing and phase-noise enhanced dynamic-threshold voltage controlled oscillator (VCO) using a capacitive division technique. This technique prevents forward biasing of the pn-junction between the body and source when the output swing increases, which results in low phase noise. The proposed VCO shows phase noise of $-$ 122.0 dBc/Hz at a 1 MHz offset frequency at 2.31 GHz and a figure of merit of $-$ 192.7 dBc/Hz while consuming 0.46 mW from a 0.38-V supply voltage. It is implemented using a 0.11 $\mu\text{m}$ CMOS process with a chip area of 0.96 $\text{mm}^{2}$ . <s> BIB002
In BIB002 , a VCO with boosted output swing and enhanced phase noise has been proposed using the Dynamic Threshold Metal Oxide Semiconductor (DTMOS) including capacitive division as shown in Fig.6 . Fig.6 . A novel VCO design using capacitive division technique. Source: Adapted from BIB002 , copyright 2016, IEEE. In existing DTMOS VCOs, the output swing should have a small value to keep the substrate-source P-N junction in the reverse biased mode. Conversely, the efficiency of the phase noise is proportional to the output swing, which means the larger the output swing, the better is the phase noise. Therefore, this capacitive division solution would drive the substrate which results in decreasing the threshold voltage in case of higher output swing BIB002 . In Eq. (10) Vth0 is the initial threshold voltage,  is the body effect co-efficient, F  is related to substrate work function, S V is the source voltage and G V is the voltage of DTMOS gate. Fig.7 . The optimized value for C1 and C2 ratio to have the optimum phase noise and output swing. Source: Adapted from BIB002 , copyright 2016, IEEE. In Fig.6 . the tail inductor and the associated parasitic capacitance of the transistor's source, function as a noise filter which will omit the second harmonics and boost the swing amplitude BIB002 , BIB001 .