Overview of Nanoelectronic Devices <s> B. Obstacles to Further Miniaturization of FET's <s> Minimal energy dissipations for the logic process based on thermodynamics and general phase space considerations are known. The actual availability of these minimal dissipations has not, however, been demonstrated. These minimal dissipation sources in a computing system also act as noise sources and thereby lead to questions about the ultimate available reliability of the computing process. A new and hypothetical device is presented in this paper and used to construct a physically analyzable computing system. It is demonstrated that this system has dissipations larger than, but of the same order of magnitude as, the original minimal quantities. It is also shown that any required reliability can be obtained with this device, without increased energy expenditure, but at the expense of an increasing time per computational step. <s> BIB001 </s> Overview of Nanoelectronic Devices <s> B. Obstacles to Further Miniaturization of FET's <s> The physical phenomena which will ultimately limit MOS circuit miniaturization are considered. It is found that the minimum MOS transistor size is determined by gate oxide breakdown and drain-source punch-through. Other factors which limit device size are drain-substrate breakdown, drain ‘corner’ breakdown and substrate doping fluctuations. However these limitations are less severe than the oxide breakdown limitation mentioned above. Power dissipation and metal migration limit the frequency and/or packing density of fully dynamic and of complementary MOS circuits. In static non-complementary circuits, power dissipation is the principal limitation of the number of circuit functions per chip. The channel length of a minimum size MOS transistor is a factor of 10 smaller than that of the smallest present day devices. The tolerances required to manufacture such a transistor are compatible with electron beam masking techniques. It is thus possible to envision fully dynamic silicon chips with up to 10^7–10^8 MOS transistors per cm^2. <s> BIB002 </s> Overview of Nanoelectronic Devices <s> B. Obstacles to Further Miniaturization of FET's <s> The performance limits of conventional integrated circuits will be reached within twenty years. Avoiding these limits requires revolutionary approaches to both devices and architectures that exploit the unique properties of nanometer- sized electronic structures. The casualties of this revolution will include high connectivity architectures, transistors, and classical circuit concepts. One approach, Nanoelectronics, combines quantum coupled devices and cellular automata architectures to provide computing functions that are downscalable to fundamental physical limits. This paper reviews the motivations for nanoelectronics are reviewed, and presents a framework for developing this technology. Some of the issues relevant to nanoelectronic computation are also addressed. <s> BIB003 </s> Overview of Nanoelectronic Devices <s> B. Obstacles to Further Miniaturization of FET's <s> There are limits on the size and number of circuit elements that can be packed on a computer chip. One is the wave behavior of electrons, which can interfere with performance in the smallest of devices. Physicists are not turning that behavior to their advantage in a new kind of component that depends on electron waves for its operation. With the so called quantum semiconductor device, it will be possible to put the circuitry of a supercomputer on a single chip. The structures for quantum devices have already been made using the same materials as today's chips. Because they can be about 100 times smaller than the devices in present-day integrated circuits, designing and fabricating a viable device presents a formidable challenge. Manufacturing processes will have to become considerably more sophisticated, and new strategies for interconnection and architecture will have to be devised to cope with the special problems of size reduction. 5 figs. <s> BIB004 </s> Overview of Nanoelectronic Devices <s> B. Obstacles to Further Miniaturization of FET's <s> Ultra-submicrometer-gate AlGaAs/GaAs high-electron-mobility transistors (HEMTs) that have gate lengths ranging from 25 to 85 nm and were fabricated using electron-beam lithographic techniques on epitaxial wafers grown by molecular beam epitaxy are discussed. These devices show that velocity overshoot and short-gate geometry effects play an important role for the gate lengths less than 100 nm. The maximum intrinsic transconductance is 215 mS/mm, and the effective saturated electron velocity reaches 3*10/sup 7/ cm/s for a 30-nm HEMT. > <s> BIB005 </s> Overview of Nanoelectronic Devices <s> B. Obstacles to Further Miniaturization of FET's <s> Limitations, innovations, and challenges of circuits and devices in silicon integrated circuits when they are scaled down to a half micrometer and smaller are reviewed. The major directions of innovation are given. Then, device innovations in advanced MOSFET devices featuring sizes of a half micrometer, quarter micrometer, and even smaller than one tenth of a micrometer are reviewed. Major issues are signal-to-noise ratio and speed of operation at low supply voltages. It is pointed out that miniaturized MOSFETs with channel lengths even shorter than one tenth of a micrometer could probably be realized with superior performance, but the circuit technique of using them at low-voltage power supplies still remains a challenge. Finally, it is pointed out that the real challenges in the future will be design and test limits of huge systems, and the real goals of engineers in the future will be functional integration rather than scale integration. > <s> BIB006 </s> Overview of Nanoelectronic Devices <s> B. Obstacles to Further Miniaturization of FET's <s> Forty-nanometer gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. To achieve such shallow junctions, a technique of solid-phase diffusion (SPD) from phosphorous-doped silicated glass (PSG) gate sidewalls is used. The resulting 40 nm gate length n-MOSFETs operate quite normally at room temperature. Even in the sub-50 nm region, short-channel effects-V/sub th/ shift and S-factor degradation-are suppressed very well. The impact ionization rate falls significantly as Vd falls below 1.5 V. It is found that, in the case of Vd less than 1.5 V, hot-carrier degradation is not a serious problem even in the sub-50 nm region. > <s> BIB007 </s> Overview of Nanoelectronic Devices <s> B. Obstacles to Further Miniaturization of FET's <s> Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology is reduction in feature size. Reduction in feature size, and the attendant changes in device behavior, will shape the nature of effective uses of the technology at the system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude with some remarks on the system-level implications of feature size as the minimum size approaches physical limits. <s> BIB008 </s> Overview of Nanoelectronic Devices <s> B. Obstacles to Further Miniaturization of FET's <s> An overview of nanocomputers is given, including a discussion of reversible computing techniques and an explanation of why they are necessary. The design of a nanocomputer will specify every atom and covalent bond present in the device. We can reasonably expect the switches, gates, or other embodiment of the logical elements to be on the order of a nanometer in size. (They may have to be further apart than that if electrical, due to electron tunneling.) In any case, it is quite reasonable to expect the entire computer to be smaller than a cubic micron, which contains a billion cubic nanometers. There are two new design rules that the nanocomputer designer must adopt: erase as few bits as possible, and eliminate entropy loss in operations that do not erase bits. The macroscopic strictures of the Second Law are consequences of the microscopic reversibility of the laws of physics. There are some hints that the oddities of quantum mechanics may have a similar source. One speculates that under the proper formulation, information, like energy, is a conserved quantity in the universe. <s> BIB009 </s> Overview of Nanoelectronic Devices <s> B. Obstacles to Further Miniaturization of FET's <s> Forty nm gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. In order to fabricate such small geometry MOSFETs, two special techniques have been adopted. One is a resist thinning technique using isotropic oxygen plasma ashing for the fabrication of 40 nm gate electrodes. The other is a solid phase diffusion technique from phosphorus doped silicated glass (PSG) for the fabrication of 10 nm source and drain junctions. The resulting 40 mm gate length n-MOSFETs operate quite normally at room temperature. Using these n-MOSFETs, we investigated short channel effects and current drivability in the 40 nm region at room temperature. We have also investigated hot-carrier related phenomena in the 40-nm region. Results indicate that the impact ionization rate increases slightly as the gate length is reduced to around 40 nm, and that both impact ionization rate and substrate current fall significantly as V/sub d/ falls below 1.5 V. This demonstrates that reliability as regards degradation due to hot carriers is not a serious problem even in the 40 mm region if V/sub d/ is less than or equal to 1.5 V. > <s> BIB010 </s> Overview of Nanoelectronic Devices <s> B. Obstacles to Further Miniaturization of FET's <s> We have fabricated field effect transistors with undoped GaAs channels, undoped AlxGa1−xAs barriers, and either n+GaAs or epitaxial Al gates. Low resistance ohmic contacts are made separately to the gate and channel in samples with 250 A barriers and in which the depth of the channel below the top surface is 900 A. Because electrons in the channel are neutralized by conducting charge on the gate, they do not experience the dopant‐induced disorder inevitable in modulation doped structures. Electron mobility is above 106 cm2/V s, even when their Fermi wavelength exceeds 1000 A, making these devices ideally suited for nanofabrication. <s> BIB011 </s> Overview of Nanoelectronic Devices <s> B. Obstacles to Further Miniaturization of FET's <s> The long-continued advance of the performance of information processing technologies has been based on miniaturization of components. The history of miniaturization is presented through examples. They suggest that limits proposed by Landauer in the 1960s will be reached in two or three decades. <s> BIB012
Despite formidable challenges, however, many of those in the research community and industry do envision close variants of conventional microelectronic transistors becoming miniaturized into the nanometer-scale regime BIB002 - [41] , [171] . For example, the The National Technology Roadmap for Semiconductors, published by the Semiconductor Industry Association, projects that chips will be made from transistors with major features (gate lengths) of 70 nm in the year 2010  . (Revisions of that document now in progress may be even more optimistic [44] .) Individual working transistors with 40 nm gate lengths have already been demonstrated in silicon BIB007 , BIB010 . Transistors with gate lengths as small as 25 nm have been made using gallium arsenide BIB005 . It is unclear, though, whether such transistors can be made sufficiently uniform and reliable to build a densely integrated computer containing a billion or more of them. Additionally, a dense network of such transistors could be slowed down by the flow of current through extremely narrow wires from one device to the next. Detailed treatments of the fundamental limitations upon small electronic circuitry BIB012 -  ,  and of the scaling problem for FET's may be found elsewhere in the literature BIB008 , BIB006 , including this issue of the Proceedings  , [171] . However, to provide points of reference for contrasting nanoelectronic devices with scaled-down FET's, a few of the obstacles to FET scaling are simply enumerated below, in increasing order of their intractability. • High electric fields, due to a bias voltage being applied over very short distances, can cause "avalanche breakdown" by knocking large numbers of electrons out of the semiconductor at high energies, thus causing current surges and progressive damage to devices  ,  . This may remain a problem in nanoelectronic devices made from bulk semiconductors. • Heat dissipation of transistors (and other switching devices), due to their necessarily limited thermodynamic efficiency, limits their density in circuits, since overheating can cause them to malfunction. This is likely to be a problem for any type of densely packed nanodevices BIB009 ,  , BIB001 . • Vanishing bulk properties and nonuniformity of doped semiconductors on small scales. This can only be overcome either by not doping at all (accumulating electrons purely using gates, as has been demonstrated in a GaAs heterostructure) BIB011 or by making the dopant atoms form a regular array. Molecular nanoelectronics is one path to the latter option. • Shrinkage of depletion regions until they are too thin to prevent quantum mechanical tunneling of electrons from source to drain when the device supposedly is turned off BIB003 . The function of nanoelectronic devices is not similarly impaired, because it depends on such tunneling of electrons through barriers. • Shrinkage and unevenness of the thin oxide layer beneath the gate that prevents electrons from leaking out of the gate to the drain. This leakage through thin spots in the oxide also involves electron tunneling. The thermodynamic obstacle to FET scaling, heat dissipation, suggests that it would be desirable to find replacements for FET's that might permit the construction of circuits that require fewer switching devices in order to perform the same functions. Below, it is discussed how alternative nanoelectronic devices can accomplish this. Further, all but one of the other obstacles to scaling result from the simultaneous decrease in the effectiveness of doping and the increase in the significance of quantum mechanical effects. Once electronic devices approach the nanometer and the molecular scale, the bulk properties of solids are replaced by the quantum mechanical properties of a relatively few atoms. Properties associated with uniformly doped semiconductors will become less evident and influential in the operation of an electronic device. Quantum mechanical effects, such as energy quantization and tunneling, become much more significant. In order for a transistor-like device to operate on the nanometerscale and, ultimately, on the molecular scale, it would be advantageous if it did not depend upon doped materials and if it operated based on quantum mechanical effects, rather than in spite of them BIB004 . This is the nature and the strength of the nanoelectronic alternatives to FET's that are discussed below.