Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> State-of-the-art CNS neural amplifier IC designs <s> A micropower signal-processor IC is the key component of an implantable telemetry system for neurophysiology. The bipolar/JFET/I/SUP 2/L chip uses digital and low-noise analog circuitry to amplify, filter, and multiplex eight channels of neutral, electrogram, and temperature data from unanesthetized and freely moving animals. Fully integrated continuous-time bandpass amplifiers incorporate a frequency-sensitive feedback network to prevent the amplification of input offset voltage. The system can telemeter data for over 500 h, permitting long-term neurophysiological investigations. <s> BIB001 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> State-of-the-art CNS neural amplifier IC designs <s> This active probe can be used for the long-term recording of extracellular neural biopotentials and as a basis for closed-loop neural prostheses. The probe incorporates on-chip circuitry for amplifying, multiplexing, and buffering neural signals recorded from ten recording electrodes spaced 100-/spl mu/m apart. It requires only three leads and operates from a single 5-V supply. On-chip self-test circuitry for testing electrode impedance levels is provided. The on-chip circuitry is fabricated in a die area of 1.3 mm/SUP 2/ using 6-/spl mu/m LOCOS enhancement-depletion NMOS technology, and dissipates 5 mW of power. The probe is 4.7 mm long and 15 /spl mu/m thick, and has a shank which tapers from 160 /spl mu/m near the base to less than 15 /spl mu/m near the tip. <s> BIB002 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> State-of-the-art CNS neural amplifier IC designs <s> A 3D microsystem for multi-site penetrating extracellular neural recording from the brain is presented. A 16 times 16-channel neural recording interface integrated prototype fabricated in 0.35 mum CMOS occupies 3.5 mm times 4.5 mm area. Each recording channel dissipates 15 muW of power with input-referred noise of 7 muVrms over 5 kHz bandwidth. A switched-capacitor delta read-out data compression circuit trades recording accuracy for the output data rate. An array of 1.5 mm platinum-coated microelectrodes is bonded directly onto the die. Results of in vitro experimental recordings from intact mouse hippocampus validate the circuit design and the on-chip electrode bonding technology. <s> BIB003 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> State-of-the-art CNS neural amplifier IC designs <s> This paper reports a 128-channel neural recording integrated circuit (IC) with on-the-fly spike feature extraction and wireless telemetry. The chip consists of eight 16-channel front-end recording blocks, spike detection and feature extraction digital signal processor (DSP), ultra wideband (UWB) transmitter, and on-chip bias generators. Each recording channel has amplifiers with programmable gain and bandwidth to accommodate different types of biological signals. An analog-to-digital converter (ADC) shared by 16 amplifiers through time-multiplexing results in a balanced trade-off between the power consumption and chip area. A nonlinear energy operator (NEO) based spike detector is implemented for identifying spikes, which are further processed by a digital frequency-shaping filter. The computationally efficient spike detection and feature extraction algorithms attribute to an auspicious DSP implementation on-chip. UWB telemetry is designed to wirelessly transfer raw data from 128 recording channels at a data rate of 90 Mbit/s. The chip is realized in 0.35 mum complementary metal-oxide-semiconductor (CMOS) process with an area of 8.8 times 7.2 mm2 and consumes 6 mW by employing a sequential turn-on architecture that selectively powers off idle analog circuit blocks. The chip has been tested for electrical specifications and verified in an ex vivo biological environment. <s> BIB004 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> State-of-the-art CNS neural amplifier IC designs <s> We present an inductively powered 32-channel wireless integrated neural recording (WINeR) system-on-a-chip (SoC) to be ultimately used for one or more small freely behaving animals. The inductive powering is intended to relieve the animals from carrying bulky batteries used in other wireless systems, and enables long recording sessions. The WINeR system uses time-division multiplexing along with a novel power scheduling method that reduces the current in unused low-noise amplifiers (LNAs) to cut the total SoC power consumption. In addition, an on-chip high-efficiency active rectifier with optimized coils help improve the overall system power efficiency, which is controlled in a closed loop to supply stable power to the WINeR regardless of the coil displacements. The WINeR SoC has been implemented in a 0.5-μ m standard complementary metal-oxide semiconductor process, measuring 4.9×3.3 mm2 and consuming 5.85 mW at ±1.5 V when 12 out of 32 LNAs are active at any time by power scheduling. Measured input-referred noise for the entire system, including the receiver located at 1.2 m, is 4.95 μVrms in the 1 Hz~10 kHz range when the system is inductively powered with 7-cm separation between aligned coils. <s> BIB005 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> State-of-the-art CNS neural amplifier IC designs <s> This paper reports a programmable 400 μm pitch neural spike recording channel, fabricated in a 130 nm standard CMOS technology, which implements amplification, filtering, digitization, analog spike detection plus feature extraction, and self-calibration functionalities. It can operate in two different output modes: 1) signal tracking, in which the neural signal is sampled and transmitted as raw data; and 2) feature extraction, in which the spikes of the neural signal are detected and encoded by piece-wise linear curves. Additionally, the channel offers a foreground calibration procedure in which the amplification gain and the passband of the embedded filter can be self-adjusted. The amplification stage obtains a noise efficiency factor of 2.16 and an input referred noise of 2.84 μVrms over a nominal bandwidth of 167 Hz-6.9 kHz. The channel includes a reconfigurable 8-bit analog-to-digital converter combined with a 3-bit controlled programmable gain amplifier for adjusting the input signal to the full scale range of the converter. This combined block achieves an overall energy consumption per conversion of 102 fJ at 90 kS/s. The energy consumed by the circuit elements which are strictly related to the digitization process is 14.12 fJ at the same conversion rate. The complete channel consumes 2.8 μW at 1.2 V voltage supply when operated in the signal tracking mode, and 3.1 μW when the feature extraction mode is enabled. <s> BIB006 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> State-of-the-art CNS neural amplifier IC designs <s> Conventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred noise requirement that determines the system sensitivity, while the supply voltage is determined by a DR requirement at the analog recording chain output that limits the maximum achievable resolution of the A-to-D conversion. In this paper, a power-efficient neural-recording architecture using a DR-folding technique is presented to enable low-voltage operation without compromising the DR performance. The proposed architecture can operate with only half of the typically required supply voltage, which results in about 50% power reduction. <s> BIB007 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> State-of-the-art CNS neural amplifier IC designs <s> This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems. <s> BIB008 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> State-of-the-art CNS neural amplifier IC designs <s> Neural probes have become the most important tool for enabling neuroscientists to place microelectrode sensors close to individual neurons and to monitor their activity in vivo. With such devices, it is possible to perform acute or chronic extracellular recordings of electrical activity from a single neuron or from groups of neurons. After the many developments in neural implants, it has become clear that large arrays of electrodes are desirable to further investigate the activity performed by complex neural networks. Therefore, in this paper, we propose a CMOS neural probe containing 455 active electrodes in the probe shank (100 μm wide, 10 mm long, and 50 μm thick) and 52 simultaneous readout channels in the probe body (2.9 × 3.3 mm2). In situ amplification under each electrode enables low-impedance interconnection lines, regardless of the electrode impedance, with a residual crosstalk of -44.8 dB. This design has been implemented in a 0.18-μm standard CMOS technology, with additional CMOS-compatible post-processing performed at wafer level to define the electrodes and the probe outline. In this architecture, the analog front-end achieves an input-referred noise of 3.2 μVrms and an NEF of 3.08. The power consumption of the core circuit is 949.8 μW, while the total power consumption is 1.45 mW. The high-density active-electrode array in this neural probe allows for the massive recording of neural activity. In vivo measurements demonstrate successful simultaneous recordings from many individual cells. <s> BIB009 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> State-of-the-art CNS neural amplifier IC designs <s> Widely utilized in the field of Neuroscience, implantable neural recording devices could capture neuron activities with an acquisition rate on the order of megabytes per second. In order to efficiently transmit neural signals through wireless channels, these devices require compression methods that reduce power consumption. Although recent Compressed Sensing (CS) approaches have successfully demonstrated their power, their full potential is yet to be explored. Built upon our previous on-chip CS implementation, we propose an energy efficient multi-mode CS framework that focuses on improving the off-chip components, including (i) a two-stage sensing strategy, (ii) a sparsifying dictionary directly using data, (iii) enhanced compression performance from Full Signal CS mode and Spike Restoration mode to Spike CS + Restoration mode and; (iv) extension of our framework to the Tetrode CS recovery using joint sparsity. This new framework achieves energy efficiency, implementation simplicity and system flexibility simultaneously. Extensive experiments are performed on simulation and real datasets. For our Spike CS + Restoration mode, we achieve a compression ratio of 6% with a reconstruction SNDR > 10 dB and a classification accuracy > 95% for synthetic datasets. For real datasets, we get a 10% compression ratio with ~ 10 dB for Spike CS + Restoration mode. <s> BIB010 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> State-of-the-art CNS neural amplifier IC designs <s> Objective. This paper describes a low power closed-loop compressive sensing (CS) based neural recording system. This system provides an efficient method to reduce data transmission bandwidth for implantable neural recording devices. By doing so, this technique reduces a majority of system power consumption which is dissipated at data readout interface. The design of the system is scalable and is a viable option for large scale integration of electrodes or recording sites onto a single device. Approach. The entire system consists of an application-specific integrated circuit (ASIC) with 4 recording readout channels with CS circuits, a real time off-chip CS recovery block and a recovery quality evaluation block that provides a closed feedback to adaptively adjust compression rate. Since CS performance is strongly signal dependent, the ASIC has been tested in vivo and with standard public neural databases. Main results. Implemented using efficient digital circuit, this system is able to achieve >10 times data compression on the entire neural spike band (500–6KHz) while consuming only 0.83uW (0.53 V voltage supply) additional digital power per electrode. When only the spikes are desired, the system is able to further compress the detected spikes by around 16 times. Unlike other similar systems, the characteristic spikes and inter-spike data can both be recovered which guarantes a >95% spike classification success rate. The compression circuit occupied 0.11mm2/electrode in a 180nm CMOS process. The complete signal processing circuit consumes <16uW/electrode. Significance. Power and area efficiency demonstrated by the system make it an ideal candidate for integration into large recording arrays containing thousands of electrode. Closed-loop recording and reconstruction performance evaluation further improves the robustness of the compression method, thus making the system more practical for long term recording. <s> BIB011
Neural amplifier ICs were first designed to meet the need for compact electrical recording of brain activities. In 1985, Dorman et al. BIB001 reported a single chip that contained three front-end amplifiers and a radio transmitter that relayed the recorded signals to an off-chip display. Similarly, Wise and Najafi reported a 10-channel amplifier system (Fig. 7a ) that was integrated with a neural probe BIB002 . The steady reduction in fine-line CMOS technologies V out+ V out- Fig. 6 An example of the current-reuse OTA proposed by Liu et al. [74] Fig. 7 a Early manifestation of a complete neural recording amplifier system proposed by Wise and Najafi BIB002 . b A recent state-of-the-art implementation of a neural amplifier system reported by Lee et al. BIB005 . Measuring 4.9 mm by 3 mm, neural amplifiers, analog-todigital converters, inductive power harvesting and a digital data transmitter are included on a single chip. Reproduced with permission from IEEE has contributed to increased channel counts BIB003 BIB009 and expanded capabilities, such as on-chip analog-to-digital conversion BIB007 BIB008 and digital radio transmission BIB004 BIB005 . Another emerging trend includes on-chip signal processing, such as spike detection BIB004  or other forms of data compression BIB006 BIB010 BIB011 to reduce the amount of transmitted data. These design choices are driven by the trend of packing increasingly higher numbers of recording channels on a single IC and the desire of researchers to have more integrated features. These needs require more power-efficient methods to send recorded data off-chip. Table 1 summarizes several IC neural amplifiers for CNS studies and their specifications and performances. Of note is the reduction in the process dimensions (smallest features), which has been reduced to 180 nm. Another area of continued improvement is the reduction in total power consumption of the ICs. Various solutions in Table 1 achieve hundreds of channels while meeting the criteria of a small die size, low power consumption and low noise.