Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Cache <s> This paper describes a 160 MHz 500 mW 32 b StrongARM(R) microprocessor designed for low-power, low-cost applications. The chip implements the ARM(R) V4 instruction set and is bus compatible with earlier implementations. The pin interface runs at 3.3 V but the internal power supplies can vary from 1.5 to 2.2 V, providing various options to balance performance and power dissipation. At 160 MHz internal clock speed with a nominal Vdd of 1.65 V, it delivers 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. The range of operating points runs from 100 MHz at 1.65 V dissipating less than 300 mW to 200 MHz at 2.0 V for less than 900 mW. An on-chip PLL provides the internal clock based on a 3.68 MHz clock input. The chip contains 2.5 million transistors, 90% of which are in the two 16 kB caches. It is fabricated in a 0.35-/spl mu/m three-metal CMOS process with 0.35 V thresholds and 0.25 /spl mu/m effective channel lengths. The chip measures 7.8 mm/spl times/6.4 mm and is packaged in a 144-pin plastic thin quad flat pack (TQFP) package. <s> BIB001 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Cache <s> Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occupy a large portion of the chip area. Not surprisingly, these caches often consume a significant amount of power. In many applications, such as portable devices, low power is more important than performance. We propose to trade performance for power consumption by filtering cache references through an unusually small L1 cache. An L2 cache, which is similar in size and structure to a typical L1 cache, is positioned behind the filter cache and serves to reduce the performance loss. Experimental results across a wide range of embedded applications show that the filter cache results in improved memory system energy efficiency. For example, a direct mapped 256-byte filter cache achieves a 58% power reduction while reducing performance by 21%, corresponding to a 51% reduction in the energy-delay product over conventional design. <s> BIB002 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Cache <s> Modern microprocessors employ one or two levels of on-chip caches to bridge the burgeoning speed disparities between the processor and the RAM. These SRAM caches are a major source of power dissipation. We investigate architectural techniques, that do not compromise the processor cycle time, for reducing the power dissipation within the on-chip cache hierarchy in superscalar microprocessors. We use a detailed register-level simulator of a superscalar microprocessor that simulates the execution of the SPEC benchmarks and SPICE measurements for the actual layout of a 0.5 micron, 4-metal layer cache, optimized for a 300 MHz, clock. We show that a combination of subbanking, multiple line buffers and bit-line segmentation can reduce the on-chip cache power dissipation by as much as 75% in a technology-independent manner. <s> BIB003 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Cache <s> In this paper, we propose a technique that uses an additional mini cache, the LO-Cache, located between the instruction cache (I-Cache) and the CPU core. This mechanism can provide the instruction stream to the data path and, when managed properly, it can effectively eliminate the need for high utilization of the more expensive I-Cache. In this work, we propose, implement, and evaluate a series of run-time techniques for dynamic analysis of the program instruction access behavior, which are then used to preactively guide the access of the LO-Cache. The basic idea is that only the most frequently executed portions of the code should be stored in the LO-Cache since this is where the program spends most of its time. We present experimental results to evaluate the effectiveness of our scheme in terms of performance and energy dissipation for a series of SPEC95 benchmarks. We also discuss the performance and energy tradeoffs that are involved in these dynamic schemes. <s> BIB004 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Cache <s> In embedded processors, instruction fetch and decode can consume more than 40% of processor power. An instruction filter cache can be placed between the CPU core and the instruction cache to service the instruction stream. Power savings in instruction fetch result from accesses to a small cache. In this paper, we introduce a decode filter cache to provide a decoded instruction stream. On a hit in the decode filter cache, fetching from the instruction cache and the subsequent decoding is eliminated, which results in power savings in both instruction fetch and instruction decode. We propose to classify instructions into cacheable or uncacheable depending on the decoded width. Then sectored cache design is used in the decode filter cache so that cacheable and uncacheable instructions can coexist in a decode filter cache sector. Finally, a prediction mechanism is presented to reduce the decode filter cache miss penalty. Experimental results show average 34% processor power reduction and less than 1% performance degradation. <s> BIB005 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> A. Cache <s> As we embrace the world of personal, portable, and perplexingly complex digital systems, it has befallen upon the bewildered designer to take advantage of the available transistors to produce a system which is small, fast, cheap and correct, yet possesses increased functionality. Increasingly, these systems have to consume little energy. Designers are increasingly turning towards small processors, which are low power, and customize these processors both in software and hardware to achieve their objectives of a low power system, which is verified, and has short design turnaround times. Designing Embedded Processorsexamines the many ways in which processor based systems are designed to allow low power devices. It looks at processor design methods, memory optimization, dynamic voltage scaling methods, compiler methods, and multi processor methods. Each section has an introductory chapter to give a breadth view, and have a few specialist chapters in the area to give a deeper perspective. The book provides a good starting point to engineers in the area, and to research students embarking upon the exciting area of embedded systems and architectures. <s> BIB006
Cache power dissipation is contributed to by the tag and data arrays BIB003 since these are employed as static RAMS so that the cache access rate matches the pipeline clock rate. A further contribution is the frequency of access. Lastly the cache area is more densely packed than other areas on the die, which means more transistors and hence more power dissipation. A significant amount of power is dissipated by on-chip caches, as exemplified in the following  :  The on-chip caches in the DEC 21164 microprocessor account for 25% of the total power dissipation  In the bipolar, multi-chip implementation of a 300-MHz. CPU, 50% of the total dissipated power is due to the primary caches.  A low-power microprocessor the DEC SA-110, dissipates 27% and 16% of the total power, respectively, in the on-chip instruction cache and data cache respectively BIB001 . Caches clearly present one of the most attractive targets for power reduction, this power reduction in caches can be achieved through several means: semiconductor process improvements, memory cell redesign, voltage reduction, and optimized cache structures BIB004 . Important additional techniques are:  Adding buffers/filter cache/block buffering/Horizontal partitioning  Turn off cache lines  Sub-banking/Vertical partitioning  Efficient tagging scheme (i.e. reducing tag comparisons) (1) Adding buffers A large number of low power cache ideas have been centered on the principle that adding an extra cache or buffer, usually small in size, and designing the system to fetch data directly from this buffer, allows thereby preventing an access to the original cache altogether. Since the buffer is relatively small, it is possible to achieve significant power savings if one can ensure a high hit rate to the buffer BIB006 . Another term that is used in the same context is filter cache. It has been observed that the instruction fetch and decode can consume more than 40% of processor power BIB005 . Experimental results across a wide range of embedded applications show that the filter cache results in improved memory system energy efficiency. For example, a direct mapped 256-byte filter cache achieves a 58% power reduction while reducing performance by 21%, corresponding to a 51% reduction in the energy-delay product over a conventional design BIB002 . An instruction filter cache or so called level zero cache BIB004 can be placed between the CPU core and the instruction cache to service the instruction stream. Power savings in instruction fetch result from accesses to a small cache BIB005 . Fig. 4 shows the effect of additional filter cache on the memory organization BIB004 , where parts of the memory hierarchy can be on-chip or off-chip. The filter cache can be more efficiently optimized according to Kin et al. [32] , who propose a scheme to predict the subsequent fetch addresses at run-time to identify whether the next fetch address is in the filter cache. In case a miss is predicted, it reduces the miss penalty by accessing the instruction cache directly.