SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. PROGRAMMABLE PROCESSOR ARCHITECTURES <s> This article presents the design of an integrated circuit which is able to perform various different hash algorithms of the MD4 family. Hash algorithms are used for digital signature schemes, data integrity, message authentication, and other cryptographic purposes (password protection, electronic bidding, confirmation of knowledge). The MD4 family is a group of hash algorithms which have similar properties. These properties can be exploited to build a universal hardware module for an efficient calculation of these hash algorithms. Special attention was turned to a well-structured hardware design. <s> BIB001 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. PROGRAMMABLE PROCESSOR ARCHITECTURES <s> This paper summarizes the design of a reprogrammable Application Specific Integrated Circuit capable of performing all members of the Secure Hash Algorithm (SHA) group of Hash Functions. The need for high-speed cryptography is introduced, as well as the SHA-1 and SHA-2 Hash Functions and their operation. Work performed at other institutions to improve throughput and power consumption is presented with advantages and disadvantages discussed. The ASIC design is then discussed, with comparisons made to previously published ASIC and FPGA implementations. The possibility of using this ASIC architecture for the SHA-3 candidates, as well as the Message Digest (MD) families of Hash Functions is suggested as an area of future work as it is shown the ASIC Architecture designed would be capable of this with only program modifications required. <s> BIB002 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> A. PROGRAMMABLE PROCESSOR ARCHITECTURES <s> This work reports an efficient and compact FPGA processor for the SHA-256 algorithm. The novel processor architecture is based on a custom datapath that exploits the reusing of modules, having as main component a 4-input Arithmetic-Logic Unit not previously reported. This ALU is designed as a result of studying the type of operations in the SHA algorithm, their execution sequence and the associated dataflow. The processor hardware architecture was modeled in VHDL and implemented in FPGAs. The results obtained from the implementation in a Virtex5 device demonstrate that the proposed design uses fewer resources achieving higher performance and efficiency, outperforming previous approaches in the literature focused on compact designs, saving around 60% FPGA slices with an increased throughput (Mbps) and efficiency (Mbps/Slice). The proposed SHA processor is well suited for applications like Wi-Fi, TMP (Trusted Mobile Platform), and MTM (Mobile Trusted Module), where the data transfer speed is around 50Mbps. <s> BIB003
The datapath of a SHA-2 processor implementation is shown in Figure 1 . It includes the components commonly used in a processor design, such as an I/O module, a Control Unit, a Program Counter, a RAM memory used to hold the working variables and the message M to be hashed, and a ROM memory for the K t constants and the initialisation values DM k (0). These components are arranged around a central bus, along with components designed specifically for the SHA-2 computation, such as a computation unit dedicated to the expansion of M to produce the W t words, and one or more computation units for implementing the compressor function. A detailed description of the datapath of a processor architecture can be found in BIB002 , where other elements commonly used in general-purpose processors, such as Memory Address Registers and Memory Data Registers, are also used. To be executed by this kind of implementations, the SHA-2 algorithm must be described in terms of microoperations, which are the operations directly executable by the architecture in a clock cycle. Since one iteration of the SHA-2 algorithm usually requires more than one microoperation, processor architectures require multiple clock cycles to hash a single message, compared to accelerator architectures which take one cycle per SHA-2 iteration. Improved processor architectures may rely on the optimisation of some of its components, particularly the arithmetic units. For example, in BIB003 a four-input ALU is used to compute Equations (II.6) and (II.7). A different strategy relies on multiple instances of the same unit, so as to parallelise the execution of different micro-operations. In BIB001 the number of cycles needed by a SHA-2 iteration is reduced by executing two micro-operations of the same iteration simultaneously, taking advantage of multiple arithmetic units.