SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> I. INTRODUCTION <s> Many cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec, and VPNs utilize hash functions, which form a special family of cryptographic algorithms. Applications that use these security schemes are becoming very popular as time goes by and this means that some of these applications call for higher throughput either due to their rapid acceptance by the market or due to their nature. In this work, a new methodology is presented for achieving high operating frequency and throughput for the implementations of all widely used-and those expected to be used in the near future-hash functions such as MD-5, SHA-1, RIPEMD (all versions), SHA-256, SHA-384, SHA-512, and so forth. In the proposed methodology, five different techniques have been developed and combined with the finest way so as to achieve the maximum performance. Compared to conventional pipelined implementations of hash functions (in FPGAs), the proposed methodology can lead even to a 160 percent throughput increase. <s> BIB001 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> I. INTRODUCTION <s> Hash functions are a crucial tool in a large variety of applications, ranging from security protocols to cryptocurrencies down to the Internet-of-Things devices used, for example, as biomedical appliances. In particular, SHA-2 is today a ubiquitous hashing primitive. Its acceleration has driven a wealth of contributions in the technical literature and even a whole industry segment involving dedicated hash processing accelerators. Because of the variety of requirements in terms of performance, resources, and energy consumption as well as the impact of the particular hardware technology of choice, evaluating and comparing different architectural schemes is a nontrivial task, along with the exploration of new solutions matching given user requirements. Based on a careful review of the state of the art, this paper introduces an SHA-2 workbench to be used as a framework for evaluating different implementation styles and architectural choices. The workbench comes in the form of a generic HDL description, where the various implementation options are exposed in the form of user-configurable parameters and can be variously combined obtaining either known solutions or possibly new configurations to be explored. We systematically use the workbench to analyze the available SHA-2 architectural techniques. This extensive evaluation provides a deep understanding of the performance and energy implications of each implementation style and even allows the identification of nonobvious matches between architectural choices and target technologies in order to optimize hash rate and area efficiency figures. <s> BIB002
Cryptographic hash functions have been employed for decades as a fundamental building block of information security. Their properties ensure that message integrity as well as the sender's identity in a communication can be securely verified, provided that a secret has been shared between the communicating parties. Because of serious vulnerabilities identified in popular hash algorithms used in the past, namely MD5 and SHA-1, SHA-2 has now become crucial in a range of applications, being today the most commonly used hash function in practice. The traditional application domain of hash functions has been network security, usually over the Internet. In this context, client devices are usually sufficiently powerful to perform the relatively limited number of hash computations required by the security protocols, while servers can possibly benefit from hardware acceleration of the hash operation BIB001 . The hardware accelerator is designed to deliver the maximum possible throughput, usually traded off for increased area and power consumption. However, the particular properties of cryptographic hash functions have paved the way for new application domains, beyond mere network security, with different sets of requirements. The most significant example is provided by blockchain applications, brought to the fore by the explosion The associate editor coordinating the review of this manuscript and approving it for publication was Junaid Shuja . of the Bitcoin cryptocurrency. The Bitcoin mining process, which heavily relies on the SHA-2 hash function, is extremely demanding in terms of energy efficiency, even making its profitability uncertain from the miner's standpoint. The development of new domains such as the Internetof-Things (IoT), with its low-cost battery-powered devices needing secure communication, has also contributed to an increased demand for area-and energy-efficient accelerators to be paired with the resource-constrained main processor. Pushed by the new classes of requirements posed by emerging applications, a number of different techniques have been introduced for the design of SHA-2 accelerators, geared towards the optimisation of area as well as energy or power consumption. While many of these area-and power-efficient techniques reach reasonable throughput levels, a few of them even sacrifice throughput in order to achieve substantial area or power savings. A designer confronted with the task of designing a SHA-2 hardware accelerator has therefore several alternatives to choose from, each with its own strengths and weaknesses. This paper comprehensively surveys the available techniques, discussing their impact on the different evaluation metrics of relevance for the designer: throughput, area occupation, and energy or power consumption. The discussion takes also advantage of the authors' previous work BIB002 , which presented a SHA-2 evaluation framework used to analyze the implementation requirements of existing solutions. This analysis is combined here with an extensive review of the VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see http://creativecommons.org/licenses/by/4.0/ state of the art to systematically show how relevant evaluation metrics are affected by architectural choices. The applications of SHA-2 are also surveyed in order to identify their key requirements and hence the most effective techniques adopted to meet them. The rest of the paper is organised as follows. Section II reviews the SHA-2 algorithm family, while Section III surveys the fields of application for the hash functions. Section IV presents the spectrum of techniques available for the acceleration of SHA-2. Section V focuses on the dedicated SHA-2 hardware solutions proposed in the literature. In Section VI the impact of different implementation techniques on circuit-level metrics and the needs of end applications are discussed. Section VII concludes the paper with a few final remarks.