Low power processor architectures and contemporary techniques for power optimization—a review <s> C. Low power Buses <s> Power consumption from logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between interconnections, clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom design. Also comparisons between static and dynamic logic are given. Results show that the power consumption of all interconnections and off chip driving can be up to 20% and 65% of the total power consumption respectively. Compared to cell library design, gate array designed chips consume about 10% more power, and power reduction in full custom designed chips could be 15%. > <s> BIB001 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> C. Low power Buses <s> This paper reviews a number of low-swing on-chip interconnect schemes, and presents a thorough analysis of their effectiveness and limitations. In addition, several new interface circuits, presenting even more energy savings, are proposed. Some of these circuits not only reduce the interconnect swing, but also use very-low supply voltages, so as to obtain quadratic energy savings. The performance of each of the presented circuits is thoroughly examined using simulation on a benchmark interconnect circuit. Energy savings with a factor of seven have been observed for some of the schemes. <s> BIB002 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> C. Low power Buses <s> A bi-directional CMOS voltage interface cir- cuit is proposed for applications that require an interface between two circuits operating at different voltage levels. The circuit can also be used as a level converter at the driver and receiver ends of long interconnect lines for low swing applications. The proposed interface circuit operates at high speed while consuming very little power. Operation of the interface circuit is verified by both simulation and experimental test circuits. <s> BIB003 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> C. Low power Buses <s> The concept of bus segmentation has been proposed to minimize power consumption by reducing the switched capacitance on each bus [Chen et al. 1999]. This paper details the design theory and implementation issues of segmented bus systems. Based on a graph model and the Gomory-Hu cut-equivalent tree algorithm, a bus can be partitioned into several bus segments separated by pass transistors. Highly communicating devices are placed to adjacent bus segments, so most data communication can be achieved by switching a small portion of the bus segments. Thus, a significant amount of power consumption can be saved. It can be proved that the proposed bus partitioning method achieves an optimal solution. The concept of tree clustering is also proposed to merge bus segments for further power reduction. The design flow, which includes bus tree construction in the register-transfer level and bus segmentation cell placement and routing in the physical level, is discussed for design implementation. The technology has been applied to a μ-controller design, and simulation results by PowerMill show significant improvement in power consumption. <s> BIB004 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> C. Low power Buses <s> Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems being designed with battery considerations in mind, minimizing the energy consumed in on-chip interconnects becomes crucial. Further, the use of nanometer technologies is making it increasingly important to consider reliability issues during the design of SoC communication architectures. Continued supply voltage scaling has led to decreased noise margins, making interconnects more susceptible to noise sources such as crosstalk, power supply noise, radiation induced defects, etc. The resulting transient faults cause the interconnect to behave as an unreliable transport medium for data signals. Therefore, fault tolerant communication mechanism, such as Automatic Repeat Request (ARQ), Forward Error Correction (FEC), etc., which have been widely used in the networking community, are likely to percolate to the SoC domain. This paper presents a survey of techniques for energy efficient on-chip communication. Techniques operating at different levels of the communication design hierarchy are described, including circuit-level techniques, such as low voltage signaling, architecture-level techniques, such as communication architecture selection and bus isolation, system-level techniques, such as communication based power management and dynamic voltage scaling for interconnects, and network-level techniques, such as error resilient encoding for packetized on-chip communication. Emerging technologies, such as Code Division Multiple Access (CDMA) based buses, and wireless interconnects are also surveyed. <s> BIB005 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> C. Low power Buses <s> In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies. We develop a methodology to calculate the repeater size and separation that minimize the total power dissipation for joint repeater insertion and coding for a specific delay target. This methodology is employed to obtain power vs. delay trade-offs for 130-nm, 90-nm, 65-nm, and 45-nm technology nodes. Using ITRS technology scaling data, we show that proposed technique provides 54%, 67%, and 69% power savings over optimally repeater-inserted 10-mm 32-bit bus at 90-nm, 65-nm, and 45-nm technology nodes, respectively, while achieving the same delay. <s> BIB006 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> C. Low power Buses <s> Global interconnect temperature keeps rising in the current and future technologies due to self-heating and the adiabatic property of top metal layers. The thermal effects impact adversely both reliability and performance of the interconnect wire, shortening the interconnect lifetime and increasing the interconnect delay. Such effects must be considered during the process of interconnect design. In this paper, one important argument is that the traditional linear dependence between wire resistance and wire width is no longer adequate for high layer interconnects due to the adiabatic property of these wires. By using curve fitting technique, we propose a quadratic model to represent the resistance of interconnect, which is aware of the thermal effects. Based on this model and the Elmore delay model, we derived a linear optimal wire sizing formula in form of f (x) = ax + b. Compared to non-thermal-aware exponential wire sizing formula in form of f (x) = ae-bx, we observed a 49.7% average delay gain with different choices of physical parameters. <s> BIB007
As the technology paradigm shifts towards globally asynchronous locally synchronous (GALS) and networkon-chip (NoC), interconnect mechanism increasingly contribute to power efficiency. Such interconnect mechanism (e.g. buses) can become a major bottleneck if not designed to be energy efficient. Generally, a significant portion of power in a chip is consumed by its bus system. For example, the bus wires dissipate about 15% to 30% BIB004 of the total power in DEC Alpha 21064 and Intel 80386 BIB001 . The delay and power dissipation of global buses BIB006 is increasing with technology scaling. This is bound to increase as the resistance of the wire increases with reduced size of the wire. With increasing bandwidth and communication efficiency, network fabrics BIB007 are becoming more attractive as the principle interconnect. Such fabrics are incorporated with high speed router and data links with bandwidth of several Gb/s BIB007 . Interconnect power optimization can be achieved at all the levels of design as shown BIB005 in Fig.  6 . The architecture level and circuit level techniques will be illustrated. These two categories can be sub divided into BIB004  Designing bus drivers/receivers to reduce the bus swing [ Figure 6 . Interconnect optimizations at different levels (Adapted from BIB005 ) (1) Reducing bus swing The power consumption related to interconnect is given by  : Where is the signal activity (the probability that the signal will change per clock cycle), is the clock frequency, is the interconnect wire capacitance and the signal voltage swing. It is apparent from the equation that the interconnect power can be reduced by decreasing the voltage swing on the wires. In BIB003 Kursun et al. propose a low power bi-directional CMOS voltage interface circuit which acts as the level converter between the driver and receiver, reducing the voltage level at the transmitter and amplifying it back at the receiver. A simple schematic representing this scheme BIB002 is shown in Fig. 7 . The driver converts a full-swing input into a reducedswing interconnect signal, which is converted back to a full-swing output by the receiver. A detailed analysis of the low swing architectures has been undertaken by Zhang et al. BIB002 , where methodologies have been introduced which involve reduced driver supply voltage, dynamically enabled drivers, level converters with low threshold voltage etc.