Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Confidentiality and Integrity of <s> The fabrication of digital Integrated Circuits (ICs) is increasingly outsourced. Given this trend, security is recognized as an important issue. The threat agent is an attacker at the IC foundry that has information about the circuit and inserts covert, malicious circuitry. The use of 3D IC technology has been suggested as a possible technique to counter this threat. However, to our knowledge, there is no prior work on how such technology can be used effectively. We propose a way to use 3D IC technology for security in this context. Specifically, we obfuscate the circuit by lifting wires to a trusted tier, which is fabricated separately. This is referred to as split manufacturing. For this setting, we provide a precise notion of security, that we call k-security, and a characterization of the underlying computational problems and their complexity. We further propose a concrete approach for identifying sets of wires to be lifted, and the corresponding security they provide. We conclude with a comprehensive empirical assessment with benchmark circuits that highlights the security versus cost trade-offs introduced by 3D IC based circuit obfuscation. <s> BIB001 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Confidentiality and Integrity of <s> Due to escalating manufacturing costs the latest and most advanced semiconductor technologies are often available at off-shore foundries. Utilizing these facilities significantly limits the trustworthiness of the corresponding integrated circuits for mission critical applications. We address this challenge of cost-effective and trustworthy CMOS manufacturing for advanced technologies using split fabrication. Split fabrication, the process of splitting an IC into an untrusted and trusted component, enables the designer to exploit the most advanced semiconductor manufacturing capabilities available offshore without disclosing critical IP or system design intent. We show that split fabrication after the Metal1 layer is secure and has negligible performance and area overhead compared to complete IC manufacturing in the off-shore foundry. Measurements from split fabricated 130nm testchips demonstrate the feasibility and efficacy of the proposed approach. <s> BIB002 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Confidentiality and Integrity of <s> New hardware security threats are identified in emerging three-dimensional (3D) integrated circuits (ICs) and potential counter-measures are introduced. Trigger and payload mechanisms for future 3D hardware Trojans are predicted. Furthermore, a novel, network-on-chip based 3D obfuscation method is proposed to block the direct communication between two commercial dies in a 3D structure, thus thwarting reverse engineering attacks on the vertical dimension. Simulation results demonstrate that the proposed method effectively obfuscates the cross-plane communication by increasing the reverse engineering time by approximately 5× as compared to using direct through silicon via (TSV) connections. The proposed method consumes approximately one fifth the area and power of a typical network-on-chip designed in a 65 nm technology, exhibiting limited overhead. <s> BIB003 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Confidentiality and Integrity of <s> Existing works on Three-dimensional (3D) hardware security focus on leveraging the unique 3D characteristics to address the supply chain attacks that exist in 2D design. However, 3D ICs introduce specific and unexplored challenges as well as new opportunities for managing hardware security. In this paper, we analyze new security threats unique to 3D ICs. The corresponding attack models are summarized for future research. Furthermore, existing representative countermeasures, including split manufacturing, camouflaging, transistor locking, techniques against thermal signal based side-channel attacks, and network-on-chip based shielding plane (NoCSIP) for different hardware threats are reviewed and categorized. Moreover, preliminary countermeasures are proposed to thwart TSV-based hardware Trojan insertion attacks. <s> BIB004 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Confidentiality and Integrity of <s> To combat security threats to integrated circuit (IC) fabrication outsourcing, 2.5D integration can obfuscate the outsourced design by lifting a portion of the wires into an interposer layer. A security-aware physical design flow for 2.5D IC technology can then help defend against attacks by increasing the layout and functionality obfuscation. <s> BIB005 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Confidentiality and Integrity of <s> Although 3D integrated circuit technology has typically been used to solve specific design goals, it has great potential for protecting intellectual property from theft or unwanted modification while at a third-party fabrication facility. We present analysis of a technique for splitting a design across multiple die layers for this purpose. From the perspective of a third-party, this technique effectively encrypts the circuit, preventing unauthorized use of, or alteration to, the design. The device is “unencrypted” at a secure final assembly location where it is oriented and bonded according to its secret key. As is true for any cryptographic technique, analysis of the algorithm or implementation may result in attacks with lower combinatorial complexity. We look at some of these potential attacks and discuss a number of possible solutions. Finally, we introduce the inter-die routing layer, which effectively complements the 3D splitting technique, making it much more difficult to develop attacks to bypass a brute force approach. <s> BIB006 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Confidentiality and Integrity of <s> Reverse engineering (RE) attacks pose a serious threat to the semiconductor supply chain. In this paper, we address this problem by proposing a design flow that leverages the unique capabilities of 3D integration to synergistically combine split fabrication and circuit camouflaging. First, 3D heterogeneous multi-chip integration is utilized to support efficient dielevel split fabrication to protect against RE during manufacturing. Second, to prevent RE after manufacturing, a subset of the trusted foundry’s die is obscured to significantly increase decamouflaging difficulty. A security-based cutsize-optimized partition algorithm is proposed to maximize the number of securely camouflaged gates on the trusted die while reducing the cutsize. Third, cost modeling is applied to demonstrate the cost effectiveness of the proposed 3D split fabrication flow compared with existing solutions. Across six widely used benchmarks, evaluations on 3D split fabrication designs between 15nm to 90nm processes show that the proposed design can effectively hinder practical RE attacks during manufacturing (Hamming Distance=30%) and after manufacturing (Complexity-to-Decamouflage=145), with minimum overheads to cutsize, foot-print, and cost. <s> BIB007 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Confidentiality and Integrity of <s> With the globalization of manufacturing and supply chains, ensuring the security and trustworthiness of ICs has become an urgent challenge. Split manufacturing (SM) and layout camouflaging (LC) are promising techniques to protect the intellectual property (IP) of ICs from malicious entities during and after manufacturing (i.e., from untrusted foundries and reverse-engineering by end-users). In this paper, we strive for "the best of both worlds," that is of SM and LC. To do so, we extend both techniques towards 3D integration, an up-and-coming design and manufacturing paradigm based on stacking and interconnecting of multiple chips/dies/tiers. Initially, we review prior art and their limitations. We also put forward a novel, practical threat model of IP piracy which is in line with the business models of present-day design houses. Next, we discuss how 3D integration is a naturally strong match to combine SM and LC. We propose a security-driven CAD and manufacturing flow for face-to-face (F2F) 3D ICs, along with obfuscation of interconnects. Based on this CAD flow, we conduct comprehensive experiments on DRC-clean layouts. Strengthened by an extensive security analysis (also based on a novel attack to recover obfuscated F2F interconnects), we argue that entering the next, third dimension is eminent for effective and efficient IP protection. <s> BIB008 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Confidentiality and Integrity of <s> Split manufacturing (SM) and layout camouflaging (LC) are two promising techniques to obscure integrated circuits (ICs) from malicious entities during and after manufacturing. While both techniques enable protecting the intellectual property (IP) of ICs, SM can further mitigate the insertion of hardware Trojans (HTs). In this paper, we strive for the "best of both worlds," that is we seek to combine the individual strengths of SM and LC. By jointly extending SM and LC techniques toward 3D integration, an up-and-coming paradigm based on stacking and interconnecting of multiple chips, we establish a modern approach to hardware security. Toward that end, we develop a security-driven CAD and manufacturing flow for 3D ICs in two variations, one for IP protection and one for HT prevention. Essential concepts of that flow are (i) "3D splitting" of the netlist to protect, (ii) obfuscation of the vertical interconnects (i.e., the wiring between stacked chips), and (iii) for HT prevention, a security-driven synthesis stage. We conduct comprehensive experiments on DRC-clean layouts of multi-million-gate DARPA and OpenCores designs (and others). Strengthened by extensive security analysis for both IP protection and HT prevention, we argue that entering the third dimension is eminent for effective and efficient hardware security. <s> BIB009
Hardware: Split Manufacturing. To advance split manufacturing via 3D and 2.5D integration seems both straightforward and promising. That is because 3D and 2.5D integration allows to split a design into multiple chips, which can maintain their FEOL and BEOL layers independently as is, whereas the overall 2.5D/3D stack can comprise further parts of the system-level interconnects. Moreover, concerns regarding the practicability of classical split manufacturing-which are still prevalent, despite proof-of-concept studies like  BIB002 -can be elevated due to this very fact that individual chip would not have to be split manufactured, but only the overall system. The idea of such "3D split manufacturing" was outlined in 2008, by Tezzaron Semiconductor  . Various studies are hinting at 3D split manufacturing as well, but most have some limitations. For example, the study BIB004 remains only on the conceptional level, while the studies BIB001 BIB005 utilize 2.5D integration with "only" wires being hidden from untrusted facilities. The latter is in principal equivalent to traditional split manufacturing but seems more practical; still, the studies BIB001 BIB005 report on considerable layout cost. Later on, BIB007 BIB009 BIB006 BIB008 promoted "native 3D split manufacturing, " i.e., with logic being split across trusted and untrusted facilities. One important finding of those later studies BIB007 BIB009 BIB006 BIB008 is that the 3D partitioning as well as the vertical interconnect fabric both play an important role and define a cost-security trade-off as follows: the more the design is split up across multiple chips, the higher the layout cost, due to the need for more vertical interconnect links and related circuitry, but the more flexible and easier it becomes to "dissolve" the IP across the 3D stack. Note that BIB007 BIB009 BIB008 proposed 3D split manufacturing in conjunction with camouflaging. While the study BIB007 applies regular, FEOL-centric camouflaging, the studies BIB009 BIB008 argue that another camouflaging approach is more appropriate for 3D split manufacturing, namely the obfuscation of the vertical interconnects. Other works also suggest camouflaging at the system level. For example, BIB003 proposed to obfuscate the vertical interconnect fabric of 3D ICs by rerouting within dedicated network-on-chip (NoC) chips "sandwiched" between the regular chips. This idea is conceptionally similar to the notion of randomized routing in BIB009 BIB008 , but more flexible, yet also more costly-it seems only warranted in case 3D NoCs are to be employed in any case.