Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> The ability to manipulate electron spin in organic molecular materials offers a new and extremely tantalizing route towards spin electronics, both from fundamental and technological points of view. This is mainly due to the unquestionable advantage of weak spin–orbit and hyperfine interactions in organic molecules, which leads to the possibility of preserving spin-coherence over times and distances much longer than in conventional metals or semiconductors. Here we demonstrate theoretically that organic spin valves, obtained by sandwiching an organic molecule between magnetic contacts, can show a large bias-dependent magnetoresistance and that this can be engineered by an appropriate choice of molecules and anchoring groups. Our results, obtained through a combination of state-of-the-art non-equilibrium transport methods and density functional theory, show that although the magnitude of the effect varies with the details of the molecule, large magnetoresistance can be found both in the tunnelling and the metallic limit. <s> BIB001 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> Presents a prolog to the article, "Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking". <s> BIB002 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> The isolation of graphene has triggered an avalanche of studies into the spin-dependent physical properties of this material, as well as graphene-based spintronic devices. Here we review the experimental and theoretical state-of-art concerning spin injection and transport, defect-induced magnetic moments, spin-orbit coupling and spin relaxation in graphene. Future research in graphene spintronics will need to address the development of applications such as spin transistors and spin logic devices, as well as exotic physical properties including topological states and proximity-induced phenomena in graphene and other 2D materials. <s> BIB003 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> Traditional studies that combine spintronics and superconductivity have mainly focused on the injection of spin-polarized quasiparticles into superconducting materials. However, a complete synergy between superconducting and magnetic orders turns out to be possible through the creation of spin-triplet Cooper pairs, which are generated at carefully engineered superconductor interfaces with ferromagnetic materials. Currently, there is intense activity focused on identifying materials combinations that merge superconductivity and spintronics to enhance device functionality and performance. The results look promising: it has been shown, for example, that superconducting order can greatly enhance central effects in spintronics such as spin injection and magnetoresistance. Here, we review the experimental and theoretical advances in this field and provide an outlook for upcoming challenges in superconducting spintronics. <s> BIB004 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> Information security has emerged as an important system and application metric. Classical security solutions use algorithmic mechanisms that address a small subset of emerg- ing security requirements, often at high-energy and perfor- mance overhead. Further, emerging side-channel and physical attacks can compromise classical security solutions. Hardware security solutions overcome many of these limitations with less energy and performance overhead. Nanoelectronics-based hardware security preserves these advantages while enabling conceptually new security primitives and applications. This tu- torial paper shows how one can develop hardware security primitives by exploiting the unique characteristics such as complex device and system models, bidirectional operation, and nonvolatility of emerging nanoelectronic devices. This pa- per then explains the security capabilities of several emerging nanoelectronic devices: memristors, resistive random-access memory, contact-resistive random-access memory, phase change memories, spin torque-transfer random-access memory, orthogonal spin transfer random access memory, graphene, carbon nanotubes, silicon nanowire field-effect tran- sistors, and nanoelectronic mechanical switches. Further, the paper describes hardware security primitives for authentica- <s> BIB005 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> As CMOS technology begins to face significant scaling challenges, considerable research efforts are being directed to investigate alternative device technologies that can serve as a replacement for CMOS. Spintronic devices, which utilize the spin of electrons as the state variable for computation, have recently emerged as one of the leading candidates for post-CMOS technology. Recent experiments have shown that a nano-magnet can be switched by a spin-polarized current and this has led to a number of novel device proposals over the past few years. In this paper, we provide a review of different mechanisms that manipulate the state of a nano-magnet using current-induced spin-transfer torque and demonstrate how such mechanisms have been engineered to develop device structures for energy-efficient on-chip memory and logic. <s> BIB006 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> The experimental demonstration of current-driven spin-transfer torque (STT) for switching magnets and push domain walls (DWs) in magnetic nanowires have opened up new avenues for spintronic computations. These devices have shown great promise for logic and memory applications due to superior energy efficiency and nonvolatility. It has been noted that the nonlinear dynamics of DWs in the physical magnetic system is an untapped source of entropy that can be leveraged for hardware security. The inherent noise, spatial, and temporal randomness in the magnetic system can be employed in conjunction with microscopic and macroscopic properties to realize novel hardware security primitives. Due to simplicity of integration, the spintronic circuits can be an add-on to the silicon substrate to complement the existing CMOS-based security and trust infrastructures. This paper investigates the prospects of spintronics in hardware security by exploring the security-specific properties and novel security primitives realized using spintronic building blocks. As spintronic elements enter the mainstream computing platforms, they are exposed to emerging attacks that were infeasible before. This paper covers the security vulnerabilities, security and privacy attack models, and possible countermeasures to enable safe computing environment using spintronics. <s> BIB007 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> This article reviews spintronics based memories, in particular, magnetic random access memory (MRAM) in a systematic manner. Debuted as a humble 4 Mb product by FreeScale in 2006, the MRAM has grown to a 256 Mb product of Everspin in 2016. During this period, MRAM has overcome several hurdles and have reached a stage, where the potential for MRAM is very promising. One of the main hurdles that the MRAM overcome between 2006 and 2016 is the way the information is written. The 4 Mb MRAM used a magnetic field based switching technology that would be almost impossible to scale below 100 nm. The 256 Mb MRAM, on the other hand uses a different writing mechanism based on Spin Transfer Torque (STT), which is scalable to very low dimensions. In addition to the difference in the writing mechanism, there has also been a major shift in the storage material. Whereas the 4 Mb MRAM used materials with in-plane magnetic anisotropy, the 256 Mb MRAM uses materials with a perpendicular magnetic anisotropy (PMA). MRAM based on PMA is also scalable to much higher densities. The paper starts with a brief history of memory technologies, followed by a brief description of the working principles of MRAM for novice. Reading information from MRAM, the technologies, materials and the physics behind reading of bits in MRAM are described in detail. As a next step, the physics and technologies involved in writing information are described. The magnetic field based writing and its limitations are described first, followed by an explanation of STT mechanism. The materials and physics behind storage of information is described next. MRAMs with in-plane magnetization, their layered material structure and the disadvantages are described first, followed by the advantages of MRAMs with perpendicular magnetization, their advantages etc. The technologies to improve writability and potential challenges and reliability issues are discussed next. Some of the future technologies that might help the industry to move beyond the conventional MRAM technology are discussed at the end of the paper, followed by a summary and an outlook. <s> BIB008 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> This paper focuses on the design, performance modeling, and evaluation of probabilistic logic using superparamagnetic nanomagnets for which there exists a strong interplay between deterministic dynamics and intrinsic thermal noise. The switching element in the spin domain is chosen as the giant spin-Hall effect (GSHE) device that operates based on the dipolar coupling phenomenon in a two-magnet system to achieve low-energy ( $\approx ~1.3$ fJ/b) and low-power ( $\approx ~0.5~\mu $ W) switching characteristics. The use of spin currents on the order of a few tens of mA/ $\mu $ m2 in the subcritical regime to operate the GSHE device yields nondeterministic switching behavior with probability of correctness less than 100%. Therefore, the proposed technique allows us to trade off circuit accuracy for tremendous reduction in energy and power dissipation. In this paper, we identify the required dimensions and material parameters of the read–write units to ensure robust magnetic dipolar coupling for reliable operation of the GSHE switch. Then, through Monte Carlo simulations, we evaluate the probabilistic switching behavior of the GSHE switch as a function of the input spin current amplitude and pulsewidth for various orientations of the magnetization vectors. The delay of the GSHE switch is quantified using a probability distribution function owing to the randomness imparted to the dynamics by intrinsic thermal noise of the nanomagnets. The relationship between the probability of correctness and the energy dissipation of the GSHE switch is quantified. The results are extended to evaluate the performance and circuit error rate of complex logic gates, such as NAND and NOR, constructed using the GSHE switch. It is shown that unlike the probabilistic CMOS (PCMOS) logic, the circuit error rate in the GSHE logic becomes a function of the input vector combination and the prior state of the switch. These nuances are captured in the compact model of the circuit error rate of multiple-input GSHE logic developed in this paper. The performance of the probabilistic GSHE logic is compared with that of PCMOS logic at the 14 nm technology node. Since the noise generation process in PCMOS logic has a limited bandwidth of tens of megahertz and consumes tens of microwatt power, the peripheral circuitry becomes prohibitive. By utilizing the inherent thermal stochasticity, nanomagnets provide a clear advantage to implement probabilistic computing platform targeted toward error-tolerant applications such as those from the image processing and machine learning domains. <s> BIB009 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> Hardware-oriented security and trust has traditionally relied on the dominant CMOS technology to develop security primitives and provide protection against different attacks and vulnerabilities. With CMOS nearly reaching its fundamental scaling limit and the shortcomings of current solutions, researchers are now looking to exploit emerging nanoelectronic devices for various security applications. In this paper, we discuss the unique features of three emerging nanoelectronic technologies, namely, phase-change memory, grapheme, and carbon nanotubes, and analyze how these features can aid in hardware security and trust. In addition, we present challenges and future research directions about how to effectively integrate emerging nanoscale devices into hardware security. We emphasize that an interdisciplinary initiative is needed for emerging technologies to reach their full potential in security and trust applications. <s> BIB010 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> Spintronic devices offer low power consumption, built-in memory, high scalability and reconfigurability, and could therefore provide an alternative to traditional semiconductor-based electronic devices. However, for spintronic devices to be useful in computing, complementary logic operation using spintronic logic gates is likely to be required. Here we report a complementary spin logic device using electric-field controlled spin–orbit torque switching in a heavy metal/ferromagnet/oxide structure. We show that the critical current for spin–orbit-torque-induced switching of perpendicular magnetization can be efficiently modulated by an electric field via the voltage-controlled magnetic anisotropy effect. Moreover, the polarity of the voltage-controlled magnetic anisotropy can be tuned through modification of the oxidation state at the ferromagnet/oxide interface. This allows us to create both n-type and p-type spin logic devices and demonstrate complementary logic operation. <s> BIB011 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> Since the early 1980s, most electronics have relied on the use of complementary metal–oxide–semiconductor (CMOS) transistors. However, the principles of CMOS operation, involving a switchable semiconductor conductance controlled by an insulating gate, have remained largely unchanged, even as transistors are miniaturized to sizes of 10 nanometres. We investigated what dimensionally scalable logic technology beyond CMOS could provide improvements in efficiency and performance for von Neumann architectures and enable growth in emerging computing such as artifical intelligence. Such a computing technology needs to allow progressive miniaturization, reduce switching energy, improve device interconnection and provide a complete logic and memory family. Here we propose a scalable spintronic logic device that operates via spin–orbit transduction (the coupling of an electron’s angular momentum with its linear momentum) combined with magnetoelectric switching. The device uses advanced quantum materials, especially correlated oxides and topological states of matter, for collective switching and detection. We describe progress in magnetoelectric switching and spin–orbit detection of state, and show that in comparison with CMOS technology our device has superior switching energy (by a factor of 10 to 30), lower switching voltage (by a factor of 5) and enhanced logic density (by a factor of 5). In addition, its non-volatility enables ultralow standby power, which is critical to modern computing. The properties of our device indicate that the proposed technology could enable the development of multi-generational computing. A scalable spintronic device operating via spin–orbit transduction and magnetoelectric switching and using advanced quantum materials shows non-volatility and improved performance and energy efficiency compared with CMOS devices. <s> BIB012 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> Digital keys are commonly used in today’s hardware security systems. However, the provable destruction of these keys after use remains a challenging problem. Most security primitives built using traditional complementary metal–oxide–semiconductor transistors are not well suited to address this issue because of their volatility and unreliability at small scales. Here we show that the unique physical fingerprint of a 128 × 64 hafnium oxide memristor crossbar array integrated with transistors is capable of provable key destruction. The fingerprint is extracted by comparing the conductance of neighbouring memristors, and it can be revealed only if a digital key stored on the same array is erased. On the basis of this provable key destruction technique, we propose a protocol for logic locking/unlocking that can support secure outsourcing of integrated circuit manufacturing. By leveraging the unique properties of memristors, including reconfigurability and variability, our chip demonstrates the integration of security, memory and computing functionalities into the same circuits, and could be used to develop more secure, compact and efficient memristive hardware systems. <s> BIB013 </s> Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges <s> Emerging Devices <s> Editor's note: This article proposes a reconfigurable logic family comprised of spin-based devices that may be dynamically configured/reconfigured owing the versatility of the giant spin-Hall effect (GSHE) device. A GSHE device can be used to realize numerous Boolean logic functions, and the proposed spin-based polymorphic logic has the potential to be extremely area efficient. -Michael Niemier, University of Notre Dame. <s> BIB014
3.1.1 Spintronics. Also known as spin electronics, spintronics differ from CMOS technology in various aspects BIB011 BIB012 BIB002  BIB006 BIB014 . First and foremost, in addition to an electronic charge, the spin of electrons is leveraged for both computation and storage/memory. Second, the switching process is non-volatile, magnetoelectric, and subject to other related phenomena like spin-transfer torque (STT). Third, spintronics are implemented typically as stack of heavy metals, ferromagnets, and/or oxide structures BIB011 BIB012 BIB002  BIB006 BIB014 , but the use of other materials has been proposed as well, e.g., graphene BIB003 , superconducting materials BIB004 , or even organic materials BIB001 . Still, manufacturing of spintronics can be made compatible with CMOS processing BIB012  . Fourth, in comparison to CMOS, spintronic devices can offer lower power consumption, built-in memory functionality, built-in reconfigurability, and better scalability BIB012 BIB002  BIB006 . Spintronics have been studied in detail for memory  BIB006 BIB008 and/or logic BIB011 BIB012 BIB002  BIB006 BIB014 BIB009 applications. For example, efforts led jointly by Intel, UC Berkeley, and Berkeley Lab promote a type of magnetoelectric spin-orbit logic that has superior switching energy (by a factor of 10 to 30), lower switching voltage (by a factor of 5), and enhanced logic density (by a factor of 5) when compared to CMOS. Among other applications, reconfigurable logic, probabilistic computing, and in-memory computing are good matches for spintronics  BIB009  . The reviewed emerging devices have some interesting properties in common, which are more difficult to achieve in traditional CMOS technology. More specifically, spintronics, memristors, CNT-FETs, and NWFETs can all be tailored to comprise significant variability/randomness, reconfigurability or polymorphic behavior, resilience against reverse engineering, and possibly also for separation of trusted and untrusted parts (the latter by means of split manufacturing). Therefore, these devices can serve well for PUFs, TRNGs, IP protection schemes, and to mask side-channel leakage. Moreover, memristors may also offer resilience against tampering, by means of destructive data management BIB013 . It should be understood that the prospects for actual implementation of such security schemes based on emerging devices depends on various aspects, ranging from circuit design and security analysis in general, down to manufacturing capabilities and device maturity, among others. Still, there is a wide range of prior art developing and promoting such schemes, of which some are reviewed next. Note that other papers have reviewed emerging devices in the context of hardware security as well, e.g., see BIB005 BIB007 BIB010 .