A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Transient Fault <s> This article discusses a novel probabilistic design paradigm targeting reconfigurable architected nanofabrics and points to a promising foundation for comprehensively addressing, at the system level, the density, scalability, and reliability challenges of emerging nanotechnologies. The approach exposes a new class of yield, delay, and cost trade-offs that must be jointly considered when designing computing systems in defect-prone nanotechnologies. <s> BIB001 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Transient Fault <s> Programmable logic arrays (PLA), which can implement arbitrary logic functions in a two-level logic form, are promising as platforms for nanoelectronic logic due to their highly regular structure compatible with the nano crossbar architectures. Reliability is an important challenge as far as nanoelectronic devices are concerned. Consequently, it is necessary to focus on the fault tolerance aspects of nanoelectronic PLAs to ensure their viability as a foundation for nanoelectronic systems. In this paper, we investigate two types of fault tolerance techniques for nanoelectronic device based PLAs, focusing at the online faults occurring at the cross-points of nano devices. We develop a scheme to precisely locate the faults online, as this is a crucial step for efficient online reconfiguration based fault tolerance schemes. We also propose a tautology based fault masking scheme. We demonstrate that these two types of fault tolerance schemes developed for nano PLAs significantly improve at low hardware cost the reliability of the high fault occurrence nanoelectronic environment. <s> BIB002 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Transient Fault <s> Entering the nanometer era, a major challenge to current design methodologies and tools is how to effectively address the high defect densities projected for nanoelectronic technologies. To this end, a reconfiguration-based defect-avoidance methodology for defect-prone nanofabrics was proposed. It judiciously architects the nanofabric, using probabilistic considerations, such that a very large number of alternative implementations can be mapped into it, enabling defects to be circumvented at configuration time, in a scalable way. Building on this foundation, in this paper, a synthesis framework aimed at implementing this new design paradigm is proposed. A key novelty of the approach with respect to traditional high-level synthesis (HLS) is that, rather than carefully optimizing a single ("deterministic") solution, the goal is to simultaneously synthesize a large family of alternative solutions, so as to meet the required probability of successful configuration, or yield, while maximizing the average performance of the family of synthesized solutions. Experimental results generated for a set of representative benchmark kernels, assuming different defect regimes and target yields, empirically show that the proposed algorithms can effectively explore the complex probabilistic design space associated with this new class of HLS problems <s> BIB003 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Transient Fault <s> Fault-tolerance is one of the major challenges facing nanoelectronic systems. Previous defect-tolerance techniques have focused on offline testing and are ill-suited for handling device death. We propose a fault-tolerance scheme for nanoelectronic PLAs that is based on checkpointing. With low overhead, our scheme is able to test and diagnose crosspoint faults that may appear in the PLA during its operational lifetime.We also present a new test vector compaction algorithm that significantly reduces the number of test vectors. This new algorithm takes advantage of the density and reconfigurability of nanoelectronic circuits by raising the granularity of defect diagnosis to the row/column level. We are therefore able to reduce the number of test vectors to O(n+p) for a PLA with n input and p product lines without sacrificing diagnosability. Experimental results show that our checkpointing scheme, together with the compaction algorithm, tolerates a much higher fault rate than previously possible. <s> BIB004 </s> A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays <s> Transient Fault <s> Crossbar nano-architectures based on self-assembled nano-structures are promising alternatives for current CMOS technology, which is facing serious challenges for further down-scaling. One of the major challenges in this nanotechnology is elevated failure rate due to atomic device sizes and inherent lack of control in self-assembly fabrication. Therefore, high permanent and transient failure rates lead to multiple faults during lifetime operation of crossbar nano architectures. In this paper, we present a concurrent multiple error detection scheme for multistage crossbar nano-architectures based on dual-rail implementations of logic functions. We prove the detectability of all single faults as well as most classes of multiple faults in this scheme. Based on statistical multiple fault injection, we compare the proposed technique with other online error detection and masking techniques such as Triple Module Redundancy (TMR), duplication, and parity checking, in terms of fault coverage as well as area and delay overhead. <s> BIB005
Tolerance. Another aspect of fault tolerance in nano-crossbars is the transient faults occurring in field. Similarly to conventional technologies targeting transient faults, hardware redundant solutions are proposed. In BIB002 , two approaches using an online test with reconfiguration and a fault masking scheme are investigated. Comparing the approaches, fault masking offers smaller hardware overhead at the cost of having very limited capability of tolerating multiple faults. In , another fault masking method with a focus on missing devices (denoted with stuck-at deactivated faults in this article) is proposed with utilizing logic tautologies. In BIB004 , an alternative reconfiguration-based fault-tolerance scheme is proposed with novel online testing using a text vector compaction. It is possible to accomplish input/output level diagnoses with reduced runtime by means of the proposed test vectors. Even though a fault-tolerance mechanism is excluded, a novel error detection method proposed in BIB005 . Logic implementation is realized with a dual rail structure having both the function and its negation as outputs. By comparing the outputs, it is possible to detect faults conforming to certain assumptions of fault characteristics. So far mentioned articles are related to the logic synthesis level of fault tolerance. In BIB001 and BIB003 , a high-level synthesis paradigm with reconfiguration is proposed with choosing certain mapping units with an optimization among many solutions. It should be noted that transient fault tolerance of nano-crossbar arrays is in exploratory phase, and only small fraction of the aforementioned articles fully target nano-crossbar arrays. Mostly, conventional PLA-based architectures are used. Additionally, as for all emerging technologies, nano-crossbar arrays have very limited field data that is needed for accurate modeling of transient faults.