Low power processor architectures and contemporary techniques for power optimization—a review <s> D. No Instruction Set Computer (NISC) <s> With complexities of Systems-on-Chip rising almost daily, the design community has been searching for new methodology that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear how many of these building blocks we need and what these basic blocks should be. Obviously, the necessary building blocks are processors and memories. One interesting question is: “Are they sufficient?”. The other interesting question is: “How many types of processors and memories we really need?”. In this report we try to answer both of these questions and argue that the No-instruction-set computer (NISC) is a single, necessary and sufficient processor component for design of any digital system. <s> BIB001 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> D. No Instruction Set Computer (NISC) <s> Traditional high level synthesis (HLS) techniques generate a datapath and controller for a given behavioral description. The growing wiring cost and delay of today technologies require aggressive optimizations, such as interconnect pipelining, that cannot be done after generating the datapath and without invalidating the schedule. On the other hand, the increasing manufacturing complexities demand approaches that favor design for manufacturability (DFM).To address these problems we propose an approach in which the datapath of the architecture is fully allocated before scheduling and binding. We compile a C program directly to the datapath and generate the controller. We can support the entire ANSI C syntax because the datapath can be as complex as the datapath of a processor. Since there is no instruction abstraction in this architecture we call it No-Instruction-Set-Computer (NISC). As the first step towards realization of a NISC-based design flow, we present an algorithm that maps an application on a given datapath by performing scheduling and binding simultaneously. With this algorithm, we achieved up to 70% speedup on a NISC with a datapath similar to that of MIPS, compared to a MIPS gcc compiler. It also efficiently handles different datapath features such as pipelining, forwarding and multi-cycle units. <s> BIB002 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> D. No Instruction Set Computer (NISC) <s> The stringent performance constraints and short time to market of modern digital systems require automatic methods for design of high performance applicationspecific architectures. This paper presents a novel algorithm for automatic generation of custom pipelined data path for a given application from its C code. The data path optimization targets both resource utilization and performance. The input to this architecture generator includes application C code, operation execution frequencies obtained by the profile run and a component library consisting of functional units, busses, multiplexers etc. The output is data path specified as a net-list of resource instances and their connections. The algorithm starts with an architecture that supports maximum parallelism for implementation of the input C code and iteratively refines it until an efficient resource utilization is obtained while maintaining the performance constraint. This paper also presents an algorithm to choose the priority of application basic blocks for optimization. Our experimental results show that automatically generated data paths satisfy given performance criteria and can be obtained in a matter of minutes leading to significant productivity gains. <s> BIB003
A very different type of architecture that has no instructions at all, is presented in BIB001 BIB002 where authors suggest to build a custom datapath based on application code without any fixed instruction set. In this approach the datapath of the architecture is fully allocated before scheduling and binding. It compiles a C program directly to the datapath, the compilation results in Control Words (CWs) instead of instructions, and that"s basically a data path specified as a net-list of resource instances and their connections. Fig. 11 elaborates the difference between typical RISC and NISC architectures. In BIB002 an algorithm is presented that maps an application on a given datapath by performing scheduling and binding simultaneously. In BIB003 two algorithms are presented, the first algorithm starts with an architecture that supports maximum parallelism for implementation of the input C code and iteratively refines it until an efficient resource utilization The other algorithm is used to choose the priority of application basic blocks for optimization.