A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulator Year <s> In order to observe and understand the architectural behavior of applications and evaluate new techniques, computer architects often use simulation tools. Several cycle-accurate simulators have been proposed to simulate the operation of the processor on the micro-architectural level. However, an important step before adopting a simulator is its validation, in order to determine how accurate the simulator is compared to a real machine. This validation step is often neglected with the argument that only the industry possesses the implementation details of the architectural components. The lack of publicly available micro-benchmarks that are capable of providing insights about the processor implementation is another barrier. In this paper, we present the validation of a new cycle-accurate, trace-driven simulator, SiNUCA. To perform the validation, we introduce a new set of micro-benchmarks to evaluate the performance of architectural components. SiNUCA provides a controlled environment to simulate the micro-architecture inside the cores, the cache memory sub-system with multi-banked caches, a NoC interconnection and a detailed memory controller. Using our micro-benchmarks, we present a simulation validation comparing the performance of real Core 2 Duo and Sandy-Bridge processors, achieving an average performance error of less than 9%. <s> BIB001 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulator Year <s> Data movement between memory and CPU is a well-known energy bottleneck for analytics. Near-Memory Processing (NMP) is a promising approach for eliminating this bottleneck by shifting the bulk of the computation toward memory arrays in emerging stacked DRAM chips. Recent work in this space has been limited to regular computations that can be localized to a single DRAM partition. This paper examines a Join workload, which is fundamental to analytics and is characterized by irregular memory access patterns. We consider several join algorithms and show that while near-data execution can improve both energy-efficiency and performance, effective NMP algorithms must consider locality, access granularity, and microarchitecture of the stacked memory devices. <s> BIB002 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulator Year <s> Deep learning methods are proven to be state-of-theart in addressing many challenges in machine learning domains. However, it comes at the cost of high computational requirements and energy consumption. The emergence of Processing In Memory (PIM) with diestacking technology presents an opportunity to speed up deep learning computation and reduce energy consumption by providing low-cost high-bandwidth memory accesses. PIM uses 3D die stacking to move computations closer to memory and therefore reduce data movement overheads. In this paper, we study the parallelization of deep learning methods on a system with multiple PIM devices. We select three typical layers: the convolutional, pooling, and fully connected layers from common deep learning models and parallelize them using different schemes. Preliminary results show we are able to reach competitive or even better performance using multiple PIM devices when comparing with traditional GPU parallelization. <s> BIB003 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulator Year <s> The recent advent of stacked memory devices has led to a resurgence of researchassociated with the fundamental memory hierarchy and associated memory pipeline. The bandwidth advantages provided by stacked logic and DRAM devices haveinspired research associated with eliminating the bandwidth bottlenecksassociated with many applications in high performance computing. Further, recent efforts have focused on utilizing stacked memory devices as last-levelcaches. In addition to the two aforementioned focus areas, a third area of research isemerging to explore augmenting the stacked memory logic layer with additionaloperations. This first generation of Hybrid Memory Cube (HMC) devices providedrudimentary atomic memory operations. The Gen2 Hybrid Memory Cube devicesprovide more expressive atomic memory operations that include primitiveinteger arithmetic operations. Despite the inclusion of more expressivearithmetic operations, many users have expressed interest in more complex andpotentially orthogonal custom memory cube, or CMC, operations in futurerevisions of the Hybrid Memory Cube specification. This work presents recent development associated with the HMC-Sim Hybrid MemoryCube simulation framework that provides users a powerful infrastructure toexperiment and research augmented custom memory cube, or CMC, operations withinthe current Gen2 Hybrid Memory Cube device infrastructure. We provide anoverview of extending the original HMC-Sim simulation infrastructure to includesupport for CMC operations with requiring users to modify the core simulationcode base. We also present three examples of building and utilizing custom, user-defined CMC operations in sample simulations to exhibit potentialapplication speedup with future HMC device specifications. In doing so, we presenta model to replace traditional thread mutexes with custom HMC mutex commands. <s> BIB004 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulator Year <s> 3D integration of solid-state memories and logic, as demonstrated by the Hybrid Memory Cube HMC, offers major opportunities for revisiting near-memory computation and gives new hope to mitigate the power and performance losses caused by the "memory wall". Several publications in the past few years demonstrate this renewed interest. In this paper we present the first exploration steps towards design of the Smart Memory Cube SMC, a new Processor-in-Memory PIM architecture that enhances the capabilities of the logic-base LoB die in HMC. An accurate simulation environment called SMCSim has been developed, along with a full featured software stack. The key contribution of this work is full system analysis of near memory computation including high-level software to low-level firmware and hardware layers, considering offloading and dynamic overheads caused by the operating system OS, cache coherence, and memory management. A zero-copy pointer passing mechanism has been devised to allow low overhead data sharing between the host and the PIM. Benchmarking results demonstrate upi?źto 2X performance improvement in comparison with the host System-on-Chip SoC, and around 1.5X against a similar host-side accelerator. Moreover, by scaling down the voltage and frequency of PIM's processor it is possible to reduce energy by around 70i?ź% and 55i?ź% in comparison with the host and the accelerator, respectively. <s> BIB005 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulator Year <s> 3D-stacked DRAM has been actively studied to overcome the limits of conventional DRAM. The Hybrid Memory Cube (HMC) is a type of 3D-stacked DRAM that has drawn great attention because of its usability for server systems and processing-in-memory (PIM) architecture. Since HMC is not directly stacked on the processor die where the central processing units (CPUs) and graphic processing units (GPUs) are integrated, HMC has to be linked to other processor components through high speed serial links. Therefore, the communication bandwidth and latency should be carefully estimated to evaluate the performance of HMC. However, most existing HMC simulators employ only simple HMC modeling. In this paper, we propose a cycle-accurate simulator for hybrid memory cube called CasHMC. It provides a cycle-by-cycle simulation of every module in an HMC and generates analysis results including a bandwidth graph and statistical data. Furthermore, CasHMC is implemented in C++ as a single wrapped object that includes an HMC controller, communication links, and HMC memory. Instantiating this single wrapped object facilitates simultaneous simulation in parallel with other simulators that generate memory access patterns such as a processor simulator or a memory trace generator. <s> BIB006 </s> A Review of Near-Memory Computing Architectures: Opportunities and Challenges <s> Simulator Year <s> Simulators help computer architects optimize system designs. The limited performance of simulators even of moderate size and detail makes the approach infeasible for design-space exploration of future exascale systems. Analytic models, in contrast, offer very fast turn-around times. In this paper we propose an analytic multi-core processor-performance model that takes as inputs a) a parametric microarchitecture-independent characterization of the target workload, and b) a hardware configuration of the core and the memory hierarchy. The processor-performance model considers instruction-level parallelism (ILP) per type, models single instruction, multiple data (SIMD) features, and considers cache and memory-bandwidth contention between cores. We validate our model by comparing its performance estimates with measurements from hardware performance counters on Intel Xeon and ARM Cortex-A15 systems. We estimate multi-core contention with a maximum error of 11.4 percent. The average single-thread error increases from 25 percent for a state-of-the-art simulator to 59 percent for our model, but the correlation is still 0.8, a high relative accuracy, while we achieve a speedup of several orders of magnitude. With a much higher capacity than simulators and more reliable insights than back-of-the-envelope calculations it makes automated design-space exploration of exascale systems possible, which we show using a real-world case study from radio astronomy. <s> BIB007
Category NMC capabilities Sinuca BIB001 2015 Cycle-Accurate Yes HMC-SIM BIB004 2016 Cycle-Accurate Limited CasHMC BIB006 2016 Cycle-Accurate No SMC BIB005 2016 Cycle-Accurate Yes CLAPPS  2017 Cycle-Accurate Yes Table 4 : Open source simulators the early design stage, system architects are faced with large design choices which range from semiconductor physics, to circuit level, micro-architectural properties (eg., issue width, branch prediction), cooling concerns, and other system design constrains BIB007 . During the first stage of design-space exploration analytic models can provide quick estimate number. Mirzadeh et al. BIB002 studied a join workload, on multiple HMC like 3D-stacked DRAM devices connected together via SerDes links using a first-order analytic model. Zhang et al BIB003 designed an analytic model using machine learning techniques to estimate the final device performance.