SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> D. ARCHITECTURES WITH SPATIAL REORDERING <s> Many cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec, and VPNs utilize hash functions, which form a special family of cryptographic algorithms. Applications that use these security schemes are becoming very popular as time goes by and this means that some of these applications call for higher throughput either due to their rapid acceptance by the market or due to their nature. In this work, a new methodology is presented for achieving high operating frequency and throughput for the implementations of all widely used-and those expected to be used in the near future-hash functions such as MD-5, SHA-1, RIPEMD (all versions), SHA-256, SHA-384, SHA-512, and so forth. In the proposed methodology, five different techniques have been developed and combined with the finest way so as to achieve the maximum performance. Compared to conventional pipelined implementations of hash functions (in FPGAs), the proposed methodology can lead even to a 160 percent throughput increase. <s> BIB001 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> D. ARCHITECTURES WITH SPATIAL REORDERING <s> Cryptographic algorithms are used to enable security services that are the core of modern communication systems. In particular, Hash functions algorithms are widely used to provide services of data integrity and authentication. These algorithms are based on performing a number of complex operations on the input data, thus it is important to count with novel designs that can be efficiently mapped to hardware architectures. Hash functions perform internal operations in an iterative fashion, which open the possibility of exploring several implementation strategies. In the paper, two different schemes to improve the performance of the hardware implementation of the SHA-2 family of algorithms are proposed. The main focus of the proposed schemes is to reduce the critical path by reordering the operations required at each iteration of the algorithm. Implementation results on an FPGA device show an improvement on the performance on the SHA-256 algorithm when compared against similar previously proposed approaches. <s> BIB002 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> D. ARCHITECTURES WITH SPATIAL REORDERING <s> High-throughput and area-efficient designs of hash functions and corresponding mechanisms for Message Authentication Codes (MACs) are in high demand due to new security protocols that have arisen and call for security services in every transmitted data packet. For instance, IPv6 incorporates the IPSec protocol for secure data transmission. However, the IPSec's performance bottleneck is the HMAC mechanism which is responsible for authenticating the transmitted data. HMAC's performance bottleneck in its turn is the underlying hash function. In this article a high-throughput and small-size SHA-256 hash function FPGA design and the corresponding HMAC FPGA design is presented. Advanced optimization techniques have been deployed leading to a SHA-256 hashing core which performs more than 30p better, compared to the next better design. This improvement is achieved both in terms of throughput as well as in terms of throughput/area cost factor. It is the first reported SHA-256 hashing core that exceeds 11Gbps (after place and route in Xilinx Virtex 6 board). <s> BIB003 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> D. ARCHITECTURES WITH SPATIAL REORDERING <s> In this study, novel pipelined architectures, optimised in terms of throughput and throughput/area factors, for the SHA-512 cryptographic hash function, are proposed. To achieve this, algorithmic- and circuit-level optimisation techniques such as loop unrolling, re-timing, temporal pre-computation, resource re-ordering and pipeline are applied. All the techniques, except pipeline are applied in the function's transformation round. The pipeline was applied through the development of all the alternative pipelined architectures and implementation in several Xilinx FPGA families and they are evaluated in terms of frequency, area, throughput and throughput/area factors. Compared to the initial un-optimised implementation of SHA-512 function, the introduced five-stage pipelined architecture improves the both the throughput and throughput/area factors by 123 and 61.5%, respectively. Furthermore, the proposed five-stage pipelined architecture outperforms the existing ones both in throughput (3.4× up to 16.9×) and throughput/area (19.5% up to 6.9×) factors. <s> BIB004 </s> SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey <s> D. ARCHITECTURES WITH SPATIAL REORDERING <s> Abstract In this paper, area-efficient and high-throughput multi-mode architectures for the SHA-1 and SHA-2 hash families are proposed and implemented in several FPGA technologies. Additionally a systematic flow for designing multi-mode architectures (implementing more than one function) of these families is introduced. Compared to the corresponding architectures that are produced by a commercial synthesis tool, the proposed ones are better in terms of both area (at least 40%) and throughput/area (from 32% up to 175%). Finally, the proposed architectures outperform similar existing ones in terms of throughput and throughput/area, from 4.2× up to 279.4× and from 1.2× up to 5.5×, respectively. <s> BIB005
[90] introduces the use of spatial reordering within the design of the transformation round core for SHA-2. The computation of To stress the fact that Equation (V.5) is computed at round t − 1 while Equation (V.1) is computed at round t, BIB002 calls the latter δ t instead of τ t is performed before the pipeline registers, while the computation of is performed after the register, along with Equation (II.12). Because of this reordering, the critical path includes the two adders used for computing of A t+1 and the following adder for P1 * t , along with the Maj function. The same authors propose in BIB001 a methodology for the optimisation of the block responsible for the computation of the round function, building on the spatial reordering technique. This methodology takes also advantage of loop unrolling, component improvements and variable precomputation, and leads to the following computation ahead of the pipeline registers: In the above equation, (K + W ) denotes that the sum is precomputed outside the operational block, due to data prefetching. Note also that p2 t+1 is not computed from p3 t+1 , due to the fact that the sum D t−1 +H t−1 +(K + W ) t−1 is performed by a Carry-Save Adder. The results of Equation (V.10) are stored in the pipeline registers along with A t−1 , B t−1 , E t−1 , and F t−1 , allowing for the following computation after the pipeline registers: While the methodology in BIB001 proposes a sequence of techniques to be applied for obtaining an optimised hash core, their application is not always straightforward and requires a careful analysis of the circuit by the designer. The approach is further improved in BIB003 , most notably by adding recursion, obtaining an even improved hash core. The latter version is evaluated against different FPGA platforms in BIB004 , where the corresponding architecture of the Expander is also described. Finally, BIB005 presents a multi-mode hash accelerator based on the same techniques. 