Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> General neural amplifier system architecture and design considerations <s> This paper describes a new multielectrode microprobe which utilizes integrated-circuit fabrication techniques to overcome many of the problems associated with conventional microelectrodes. The probe structure consists of an array of gold electrodes which are supported on a silicon carrier and which project beyond the carrier for a distance of about 50 ? to allow a close approach to active neurons. These electrodes are covered with a thin (0.4-?) layer of silicon dioxide which is selectively removed at the electrode tips using high-resolution photoengraving techniques to define the recording areas precisely. The processing sequence described permits any two-dimensional electrode array to be realized. Interelectrode spacings can be accurately controlled in the range from 10 to 20 ? or larger, and electrode-tip diameters can be as small as 2 ?. <s> BIB001 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> General neural amplifier system architecture and design considerations <s> A micropower signal-processor IC is the key component of an implantable telemetry system for neurophysiology. The bipolar/JFET/I/SUP 2/L chip uses digital and low-noise analog circuitry to amplify, filter, and multiplex eight channels of neutral, electrogram, and temperature data from unanesthetized and freely moving animals. Fully integrated continuous-time bandpass amplifiers incorporate a frequency-sensitive feedback network to prevent the amplification of input offset voltage. The system can telemeter data for over 500 h, permitting long-term neurophysiological investigations. <s> BIB002 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> General neural amplifier system architecture and design considerations <s> Several aspects of ESD are described from the point of view of the test, design, product, and reliability engineering. A review of the ESD phenomena along with the test methods, the appropriate on-chip protection techniques, and the impact of process technology advances from CMOS to BiCMOS on the ESD sensitivity of IC protection circuits are presented. The status of understanding in the field of ESD failure physics and the current approaches for modeling are discussed. > <s> BIB003 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> General neural amplifier system architecture and design considerations <s> Electrostatic discharge (ESD) refers to the sudden transfer (discharge) of static charge between objects at different electrostatic potentials. ESD belongs to a family of electrical problems known as electrical overstress (EOS). ESD poses a serious threat to electronic devices, such as microcircuits, transistors, and diodes, and affects the operation of the systems that contain those devices. Most electronic companies regard all semiconductor devices as ESD sensitive because of the damage ESD can cause. For this reason, ESD is a major concern in the microelectronic and electronic industry in manufacture and testing. ESD concerns also exist in nonelectronic components such as disk drives, magnetic recording heads, and sensors. The article describes the causes of ESD, its damaging effects and how the effects can be prevented or minimized. <s> BIB004 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> General neural amplifier system architecture and design considerations <s> This paper reports a 128-channel neural recording integrated circuit (IC) with on-the-fly spike feature extraction and wireless telemetry. The chip consists of eight 16-channel front-end recording blocks, spike detection and feature extraction digital signal processor (DSP), ultra wideband (UWB) transmitter, and on-chip bias generators. Each recording channel has amplifiers with programmable gain and bandwidth to accommodate different types of biological signals. An analog-to-digital converter (ADC) shared by 16 amplifiers through time-multiplexing results in a balanced trade-off between the power consumption and chip area. A nonlinear energy operator (NEO) based spike detector is implemented for identifying spikes, which are further processed by a digital frequency-shaping filter. The computationally efficient spike detection and feature extraction algorithms attribute to an auspicious DSP implementation on-chip. UWB telemetry is designed to wirelessly transfer raw data from 128 recording channels at a data rate of 90 Mbit/s. The chip is realized in 0.35 mum complementary metal-oxide-semiconductor (CMOS) process with an area of 8.8 times 7.2 mm2 and consumes 6 mW by employing a sequential turn-on architecture that selectively powers off idle analog circuit blocks. The chip has been tested for electrical specifications and verified in an ex vivo biological environment. <s> BIB005 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> General neural amplifier system architecture and design considerations <s> Battery systems have been developed that provide years of service for implantable medical devices. The primary systems utilize lithium metal anodes with cathode systems including iodine, manganese oxide, carbon monofluoride, silver vanadium oxide and hybrid cathodes. Secondary lithium ion batteries have also been developed for medical applications where the batteries are charged while remaining implanted. While the specific performance requirements of the devices vary, some general requirements are common. These include high safety, reliability and volumetric energy density, long service life, and state of discharge indication. Successful development and implementation of these battery types has helped enable implanted biomedical devices and their treatment of human disease. <s> BIB006 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> General neural amplifier system architecture and design considerations <s> Conventional capacitively coupled neural recording amplifiers often present a large input load capacitance to the neural signal source and hence take up large circuit area. They suffer due to the unavoidable trade-off between the input capacitance and chip area versus the amplifier gain. In this work, this trade-off is relaxed by replacing the single feedback capacitor with a clamped T-capacitor network. With this simple modification, the proposed amplifier can achieve the same mid-band gain with less input capacitance, resulting in a higher input impedance and a smaller silicon area. Prototype neural recording amplifiers based on this proposal were fabricated in 0.35 μm CMOS, and their performance is reported. The amplifiers occupy smaller area and have lower input loading capacitance compared to conventional neural amplifiers. One of the proposed amplifiers occupies merely 0.056 mm2. It achieves 38.1-dB mid-band gain with 1.6 pF input capacitance, and hence has an effective feedback capacitance of 20 fF. Consuming 6 μW, it has an input referred noise of 13.3 μVrms over 8.5 kHz bandwidth and NEF of 7.87. In-vivo recordings from animal experiments are also demonstrated. <s> BIB007 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> General neural amplifier system architecture and design considerations <s> Neural probes have become the most important tool for enabling neuroscientists to place microelectrode sensors close to individual neurons and to monitor their activity in vivo. With such devices, it is possible to perform acute or chronic extracellular recordings of electrical activity from a single neuron or from groups of neurons. After the many developments in neural implants, it has become clear that large arrays of electrodes are desirable to further investigate the activity performed by complex neural networks. Therefore, in this paper, we propose a CMOS neural probe containing 455 active electrodes in the probe shank (100 μm wide, 10 mm long, and 50 μm thick) and 52 simultaneous readout channels in the probe body (2.9 × 3.3 mm2). In situ amplification under each electrode enables low-impedance interconnection lines, regardless of the electrode impedance, with a residual crosstalk of -44.8 dB. This design has been implemented in a 0.18-μm standard CMOS technology, with additional CMOS-compatible post-processing performed at wafer level to define the electrodes and the probe outline. In this architecture, the analog front-end achieves an input-referred noise of 3.2 μVrms and an NEF of 3.08. The power consumption of the core circuit is 949.8 μW, while the total power consumption is 1.45 mW. The high-density active-electrode array in this neural probe allows for the massive recording of neural activity. In vivo measurements demonstrate successful simultaneous recordings from many individual cells. <s> BIB008 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> General neural amplifier system architecture and design considerations <s> A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/f ::: n ::: characteristics of neural signals is described in this paper. The amplified output is `folded' into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm can be applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range. It also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, lower harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a behavioral model to provide a quick estimate of the post reconstruction dynamic range. Measurement results from two different core amplifier designs in 65 nm and 180 nm CMOS processes are presented to prove the generality of the proposed scheme in the neural recording applications. Operating from a 1 V power supply, the amplifier in 180 nm CMOS has a gain of 54.2 dB, bandwidth of 5.7 kHz, input referred noise of 3.8 μV ::: rms ::: and power dissipation of 2.52 μW leading to a NEF of 3.1 in spike band. It exhibits a dynamic range of 66 dB and maximum SNDR of 43 dB in LFP band. It also reduces system level power (by reducing the number of bits in the ADC by 2) as well as data rate to 80% of a conventional design. In vivo measurements validate the ability of this amplifier to simultaneously record spike and LFP signals. <s> BIB009 </s> Implantable neurotechnologies: a review of integrated circuit neural amplifiers <s> General neural amplifier system architecture and design considerations <s> Electrodes serve as the first critical interface to the biological organ system. In neuroprosthetic applications, for example, electrodes interface to the tissue for either signal recording or tissue stimulation. In this review, we consider electrodes for recording neural activity. Recording electrodes serve as wiretaps into the neural tissues, providing readouts of electrical activity. These signals give us valuable insights into the organization and functioning of the nervous system. The recording interfaces have also shown promise in aiding treatment of motor and sensory disabilities caused by neurological disorders. Recent advances in fabrication technology have generated wide interest in creating tiny, high-density electrode interfaces for neural tissues. An ideal electrode should be small enough and be able to achieve reliable and conformal integration with the structures of the nervous system. As a result, the existing electrode designs are being shrunk and packed to form small form factor interfaces to tissue. Here, an overview of the historic and state-of-the-art electrode technologies for recording neural activity is presented first with a focus on their development road map. The fact that the dimensions of recording electrode sites are being scaled down from micron to submicron scale to enable dense interfaces is appreciated. The current trends in recording electrode technologies are then reviewed. Current and future considerations in electrode design, including the use of inorganic nanostructures and biologically inspired or biocomapatible materials are discussed, along with an overview of the applications of flexible materials and transistor transduction schemes. Finally, we detail the major technical challenges facing chronic use of reliable recording electrode technology. <s> BIB010
The basic structure of neural amplifier systems is shown in Fig. 3 . The neural signals are transduced by neural probes   BIB001 , such as surface or subdural electrodes for recording ECoG signals or microelectrodes for recording neural spikes or action potentials BIB010 . However, neural signals are first preamplified by a front-end amplifier. This amplifier should have the lowest input-referred noise and higher gain than the subsequent stages, as the RTI noise of all subsequent stages are referred back to the electrodes through the gain of this amplifier  . The subsequent amplifier stages composed of one or more cascaded amplifier configurations provide additional gain, limit the signal bandwidth (to filter noise) and drive external loads, such as the input of an oscilloscope or a digitizer. After the neural signals are amplified, they can be processed and observed via analog signal processing methods. This can be as simple as visualizing the waveforms on an oscilloscope or telemetering using an analog radio transmitter BIB002 . The amplified signals can also be digitized and post-processed using algorithms that are run either on-chip BIB005 or off-chip on digital post-processors. Minimizing the total power consumption for such neural recording systems is an important task, especially for such systems that are designed for portable applications or implantation. When a neural amplifier IC is used for portable recording applications, it is usually powered via a compact and reliable power source (e.g., a battery) BIB006 . Portable recording applications using neural amplifier ICs need to consume minimal power to allow for the use of small batteries while extending operation time. When a recording device containing a neural amplifier IC is implanted for chronic recording, the device should generate less than 40 mW/cm 2 of heat flux to prevent heating the surrounding nerve tissues by more than 2 °C, beyond which tissue/nerve necrosis occurs  . Neural amplifier ICs that consume low power certainly helps in achieving this requirement. If the implantable system is powered via electromagnetic induction, the body adsorption loss leads to a poor power transfer efficiency and therefore requires an electromagnetic power source to emit a high level of electromagnetic power through bodily tissues. Ensuring electromagnetic power emissions are maintained below regulatory levels  is particularly challenging. Therefore, low-power neural amplifier designs are essential to mitigating this challenge. In addition to noise and power considerations, the size of IC neural amplifiers is an additional consideration when they are used for portable or implantable applications. Both applications require a highly miniaturized integrated system with a small IC area and overall system footprint. In general, both the chip area and power consumption of any neural amplifier are dependent on the application and design process (the number of active channels, the size of transistors and the wiring). On the one hand, it is desirable to have a small IC die size. On the other hand, it is desirable to maximize on-chip functionality (a large number of channels, post-processing capability, wireless power and communication circuits). A trade-off between the IC die size and functionality is generally required. However, modern circuit designs BIB008 BIB007 and IC fabrication technologies BIB009  have resulted in innovative designs, enabling designers to relax such compromises. Vulnerability to an electrostatic discharge (ESD) from a charged human operator or during machine-based assembly processes is another critical consideration BIB003 BIB004 . This is a particularly serious problem when the amplifier IC is used in dry environments, such as in the operating theater or in dry climates. Although most ICs are designed to meet standard ESD specifications   , the static electric charges that are typically encountered may result in voltages higher than 25 kV BIB004 , and hence proper ESD design of the ICs and correct device handling procedures are still required. Furthermore, latent and cumulative soft damage occurs when the pins of neural ICs are repeatedly subjected to ESD, as would occur when an unknowingly charged human operator repeatedly handles the IC amplifier terminals. Hence, standard ESD protection handling procedures, such as grounding the subject and surgeon performing the implant must be adhered to when assembling and implanting such sensitive IC amplifiers. Special design considerations also have to be made to mitigate an ESD failure, especially for implanted applications. A typical ESD event would disconnect the input terminals of an IC neural amplifier from the electrodes, disabling the still functional amplifiers' ability to acquire the neural signals. However, a worst-case ESD damage scenario would cause an electrical current to flow from the voltage supply terminal of the powered IC though the input pins to an electrode site. This would lead to uncontrolled electrical current stimulation of the surrounding biological tissue whenever the device is powered up  , causing long-term tissue damage.