Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Bus structures <s> A split-bus architecture is proposed to improve the power dissipation for global data exchange among a set of modules. The resulting bus splitting problem is formulated and solved combinatorially. Experimental results show that the power saving of the split-bus architecture compared to the monolithic-bus architecture varies from 16% to 50%, depending on the characteristics of the data transfer among the modules and the configuration of the split bus. The proposed split-bus architecture can be extended to multi-way split-bus when a large number of modules are to be connected. <s> BIB001 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Bus structures <s> In modern embedded systems including communication and multimedia applications, a large fraction of power is consumed during memory access and data transfer. Thus, buses should be designed and optimized to consume reasonable power while delivering sufficient performance. In this paper, we address a bus ordering problem for low-power application-specific systems. A heuristic algorithm is proposed to determine the order in a way that effective lateral component of capacitance is reduced, thereby reducing the power consumed by buses. Experimental results for various examples indicate that an average power saving from 30% to 46.7%, depending on capacitance components, can be obtained without any circuit overhead. <s> BIB002 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Bus structures <s> The concept of bus segmentation has been proposed to minimize power consumption by reducing the switched capacitance on each bus [Chen et al. 1999]. This paper details the design theory and implementation issues of segmented bus systems. Based on a graph model and the Gomory-Hu cut-equivalent tree algorithm, a bus can be partitioned into several bus segments separated by pass transistors. Highly communicating devices are placed to adjacent bus segments, so most data communication can be achieved by switching a small portion of the bus segments. Thus, a significant amount of power consumption can be saved. It can be proved that the proposed bus partitioning method achieves an optimal solution. The concept of tree clustering is also proposed to merge bus segments for further power reduction. The design flow, which includes bus tree construction in the register-transfer level and bus segmentation cell placement and routing in the physical level, is discussed for design implementation. The technology has been applied to a μ-controller design, and simulation results by PowerMill show significant improvement in power consumption. <s> BIB003 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Bus structures <s> In this paper we present an algorithm which automatically maps the IPs onto a generic regular Network on Chip (NoC) architecture and constructs a deadlock-free deterministic routing function such that the total communication energy is minimized. At the same time, the performance of the resulting communication system is guaranteed to satisfy the specified constraints through bandwidth reservation. As the main contribution, we first formulate the problem of energy/performance aware mapping, in a topological sense, and show how the routing flexibility can be exploited to expand the solution space and improve the solution quality An efficient branch-and-bound algorithm is then described to solve this problem. Experimental results show that the proposed algorithm is very fast, and significant energy savings can be achieved. For instance, for a complex video/audio application, 51.7% energy savings have been observed, on average, compared to an ad-hoc implementation. <s> BIB004 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (3) Bus structures <s> As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been identified to be a major design challenge. Network topologies have high impact on network power consumption. Technology scaling is another important factor that affects network power since each new technology changes semiconductor physical properties. As shown in this paper, these two aspects need to be considered synergistically. In this paper, we characterize the impact of process technologies on network energy for a range of topologies, starting from 2-dimensional meshes/tori, to variants of meshes/tori that incorporate higher dimensions, multiple hierarchies and express channels. We present a method which uses an analytical model to predict the most energy-efficient topology based on network size and architecture parameters for future technologies. Our model is validated against cycle-accurate network power simulation and shown to arrive at the same predictions. We also show how our method can be applied to actual parallel benchmarks with a case study. We see this work as a starting point for defining a roadmap of future on-chip networks. <s> BIB005
As previously discussed, the primary bottleneck is the capacitance during the switching activity. There has been research being done on redesigning the complete bus structure to reduce this capacitance. Shin et al. BIB002 developed a design methodology where it is assumed that capacitance components of buses are available from the layout of the processor core and the address streams from typical runs of the application code. Based on this information the optimal bus order is derived and this order is used to modify the processor layout. In BIB001 the split shared bus architecture is described. As shown in Fig. 8 the long bus is divided into two smaller buses and the dual port bus driver passes the data between the two buses. The power consumption is reduced in a sense that the effective capacitance for complete bus is divided into smaller portions and only active portions contribute to the power. As the effective length is shortened the parasitic components are also reduced. Similar idea is elaborated in BIB003 under the name of bus segmentation. Network on Chip is considered to be one of the potential forerunners in coming years due to the performance demands with multiple processing blocks operating within same chip. This opens up flurry of opportunities for designing efficient network and routing architectures. Apart from the above mentioned methods there are different Network topologies and routing architectures/algorithms BIB004 which are exploited for energy/performance. Network topologies determine the number of hops and wire length BIB005 required for data 