A Survey of Swarm Intelligence Techniques in VLSI Routing Problems <s> 3) DETAILED ROUTING <s> Improving detailed routing routability is an important objective of a global router. In this paper, we propose GDRouter, an interleaved global routing and detailed routing algorithm for the ultimate routability i.e., detailed routing routability. The newly proposed router makes the global routing aware of detailed routing routability by correctly setting global capacity to reduce the inconsistency between the two stages. The final result contains both the detailed routing guided global routing and deailed routing solutions. Fast and efficient academic global routing and detailed routing tools FastRoute [1] and RegularRoute [2] are interleaved in GDRouter. In the Initial Capacity and Routing Weight Esitmation (ICRWE) phase, the weight for each global and detailed routing grid is calculated to make GDRouter aware of pin distribution based on a Gridded Voronoi Diagram method. Then the algorithm generates initial global capacity based on both local usage and global segment usage. In particular, Spine routing is utilized to estimate local usage. And a virtual routing i.e. fast implementations of FastRoute and RegularRoute, is performed to estimate global segment usage. The initial global capacity is applied in Full Routing phase to obtain detailed routing routability i.e., number of unassigned global segment. To further improve routability, in the following Iterative Test Routing (ITR) phase, GDRouter incrementally applies the interleaved global routing and detailed routing to adjust the global capcity based on detailed routing solution. To save runtime, GDRouter quits the loop if detailed routing routability stops improving or it reaches maximum iteration. Experimental results reveal that the newly proposed algorithm is capable of enhancing detailed routing routability. In particular, GDRouter reduces number of unassigned global segments by 90% for ISPD98 [3] derived testcases and around 60% for ISPD05/06 [4, 5] derived test-cases with 2.9x runtime overhead. <s> BIB001 </s> A Survey of Swarm Intelligence Techniques in VLSI Routing Problems <s> 3) DETAILED ROUTING <s> We present algorithms for routing in advanced technology nodes, used by BonnRoute (BR) to obtain efficient and almost design rule clean wire packings and pin access solutions. Designs with dense standard cell libraries in presence of complex industrial design rules, with a special focus on multiple patterning lithography are considered. The key components of this approach are a multilabel interval-based shortest path algorithm for long on-track connections, and a dynamic program for computing packings of pin access paths and short connections between closely spaced pins. The multilabel path search implementation is very general and is driven with different labeling rules, allowing to trade-off runtime against accuracy in terms of obeyed design rules. We combine BR with an industrial router for cleaning up the remaining design rule violations, and demonstrate superior results over that industrial router in our experiments in terms of wire length, number of vias, design rule violations, and runtime. <s> BIB002 </s> A Survey of Swarm Intelligence Techniques in VLSI Routing Problems <s> 3) DETAILED ROUTING <s> Detailed routing is an important stage in very large scale integrated physical design. Due to the extreme scaling of transistor feature size and the complicated design rules, ensuring routing completion without design rule checking (DRC) violations becomes more and more difficult. Studies have shown that the low routing quality partly results from nonoptimal net-ordering nature of traditional sequential methods. The concurrent routing strategy is always based on an NP-hard model, thus is at a disadvantage in runtime. In this paper, we present a novel concurrent detailed routing algorithm that routes all nets simultaneously. Based on the multicommodity flow model, detailed routing problem with complex design rule constraints is formulated as an integer linear programming. Some model simplification heuristics and efficient model solving algorithms are proposed to improve the runtime. Experimental results show that, the proposed algorithms can reduce the DRC violations by 80%, meanwhile can reduce wirelength and via count by 5% and 8% compared with an industry tool. In addition, the proposed algorithm is general that it can be adopted as an incremental detailed router to refine a routing solution, so the number of DRC violations that industry tool cannot fix are further reduced by 27%. <s> BIB003
Detailed routing methods can be divided into serial algorithms and parallel algorithms. In order to make up for the effect of the order of nets on global results, the serial routing usually refines the routing results by means of rip-up and reroute, and can quickly obtain a good quality solution. But these serial routing methods BIB001 , BIB002 may generate some invalid solutions, while the parallel detailed routing algorithms based on the multi-commodity flow model BIB003 can simultaneously route multiple nets. However, these algorithms do not take into account the delay optimization problem and the complexity is too high, which cannot solve the performance-driven routing problem well. While the introduction of via-pillar process can effectively optimize the delay. Therefore, finding an efficient algorithm for detailed routing under the via-pillar process is also a problem worth exploring.