Low power processor architectures and contemporary techniques for power optimization—a review <s> (2) Encoding techniques <s> CMOS circuits consume power during the charging and discharging of capacitances. Reducing switching activity then, saves power in embedded processors. The authors' two-pronged attack uses Gray code addressing and cold scheduling to eliminate bit switches. > <s> BIB001 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (2) Encoding techniques <s> Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the bus-invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power. > <s> BIB002 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (2) Encoding techniques <s> We present low power techniques for mapping arrays in behavioral specifications to physical memory, specifically for memory intensive behaviors that exhibit regularity in their memory access patterns. Our approach exploits this regularity in memory accesses by reducing the number of transitions on the memory address bus. We study the impact of different strategies for mapping arrays in behaviors to physical memory, on power dissipation during memory accesses. We describe a heuristic for selecting a memory mapping strategy to achieve low power, and present an evaluation of the architecture that implements the mapping techniques to study the transition count overhead. Experiments on several image processing benchmarks indicate power savings of upto 63 % through reduced transition activity on the memory address bus. <s> BIB003 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (2) Encoding techniques <s> Gray code addressing is one of the techniques previously proposed to reduce switching activity on high capacitance address bus lines. However in order to convert a system to gray address encoding there are several issues a designer needs to consider. This paper analyzes two issues which include gray code encodings for counter increments other than one and tradeoffs in power consumption incurred due to code conversions (binary to gray, gray to binary) when considering address increments and adders. Results are shown for different encodings and different configurations. <s> BIB004 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (2) Encoding techniques <s> In microprocessor-based systems, large power savings can be achieved through reduction of the transition activity of the on- and off-chip buses. This is because the total capacitance being switched when a voltage change occurs on a bus line is usually sensibly larger than the capacitive load that must be charged/discharged when internal nodes toggle. In this paper, we propose an encoding scheme which is suitable for reducing the switching activity on the lines of an address bus. The technique relies on the observation that, in a remarkable number of cases, patterns traveling onto address buses are consecutive. Under this condition it may therefore be possible, for the devices located at the receiving end of the bus, to automatically calculate the address to be received at the next clock cycle; consequently, the transmission of the new pattern can be avoided, resulting in an overall switching activity decrease. We present analytical and experimental analyses showing the improved performance of our encoding scheme when compared to both binary and Gray addressing schemes, the latter being widely accepted as the most efficient method for address bus encoding. We also propose power and timing efficient implementations of the encoding and the decoding logic, and we discuss the applicability of the technique to real microprocessor-based designs. <s> BIB005 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (2) Encoding techniques <s> The energy consumption at the I/O pins is a significant part of the overall chip consumption. This paper presents a method for encoding an external address bus which lowers its activity and, thus, decreases the energy. This method relies on the locality of memory references. Since applications favor a few working zones of their address space at each instant, for an address to one of these zones only the offset of this reference with respect to the previous reference to that zone needs to be sent over the bus, along with an identifier of the current working zone. This is combined with a modified one-shot encoding for the offset. An estimate of the area and energy overhead of the encoder/decoder are given; their effect is small. The approach has been applied to two memory-intensive examples, obtaining a bus-activity reduction of about 2/3 in both of them. Comparisons are given with previous methods for bus encoding, showing significant improvement. <s> BIB006 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (2) Encoding techniques <s> This paper describes a new approach to low-power bus encoding, called "The Beach Solution", which is thought for power optimization of digital systems containing an embedded processor or a microcontroller executing a special-purpose software routine. The main difference between the proposed method and existing bus encoding techniques is that it is strongly application-dependent, in the sense that it is Based on the analysis of the execution stream of a given program. This allows an accurate computation of the correlations that may exist between blocks of bits in consecutive patterns, and that can be successfully exploited to determine an encoding which minimizes the bus transition activity. Experimental results, obtained on a set of special-purpose applications, are very promising; reductions of the bus activity up to 64.8% (41.9% on average) have been achieved over the original address streams. <s> BIB007 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (2) Encoding techniques <s> The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I/O interfaces can provide significant savings on the overall power budget. This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses. In particular, the schemes illustrated here target the reduction of the average number of bus line transitions per clock cycle. Experimental results, conducted on address streams generated by a real microprocessor, have demonstrated the effectiveness of the proposed methods. <s> BIB008 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (2) Encoding techniques <s> This paper presents Pyramid code, an optimal code for transmitting sequential addresses over a DRAM bus. Constructed by finding an Eulerian cycle on a complete graph, this code is optimal for conventional DRAM in the sense that it minimizes the switching activity on the time-multiplexed address bus from CPU to DRAM. Experimental results on a large number of testbenches with different characteristics (i.e. sequential vs. random memory access behaviors) are reported and demonstrate a reduction of bus activity by as much as 50%. <s> BIB009 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (2) Encoding techniques <s> Power-efficient design requires reducing power dissipation in all parts of the design and during all stages of the design process subject to constraints on the system performance and quality of service (QoS). Power-aware high-level language compilers, dynamic power management policies, memory management schemes, bus encoding techniques, and hardware design tools are needed to meet these often-conflicting design requirements. This paper reviews techniques and tools for power-efficient embedded system design, considering the hardware platform, the application software, and the system software. Design examples from an Intel StrongARM based system are provided to illustrate the concepts and the techniques. This paper is not intended as a comprehensive review, rather as a starting point for understanding power-aware design methodologies and techniques targeted toward embedded systems. <s> BIB010 </s> Low power processor architectures and contemporary techniques for power optimization—a review <s> (2) Encoding techniques <s> In this paper we present a genetic approach for the efficient generation of an encoder to minimize switching activity on the high-capacity lines of a communication bus. The approach is a static one in the sense that the encoder is realized ad hoc according to the traffic on the bus. This is not, however, a limiting hypothesis if the application scenario considered is that of embedded systems. An embedded system, in fact, executes the same application throughout its lifetime and so it is possible to have detailed knowledge of the trace of the patterns transmitted on a bus following execution of a specific application. The approach is compared with the most efficient encoding schemes proposed in the literature on both multiplexed and separate buses. The results obtained demonstrate the validity of the approach, which on average saves up to 50% of the transitions normally required. <s> BIB011
Signal transitions in terms of logic level bit values, is another source of power consumption in CMOS circuits BIB003 . Short length interconnect wires present a parasitic capacitance similar to gate or drain capacitance which is negligible. However, for wires that are connecting more distant blocks the interconnect capacitance is of substantial measure  . A remedy for this is to reduce the switching activity on the wires effectively reducing the capacitance. Bus encoding schemes have been investigated as a means to downsize the total number of transitions on interconnects. Several encoding approaches have been proposed BIB011 according to the type of bus to which the encoding schemes are applied (address/data/control bus), the class of architectures considered (general-purpose, special-purpose), the complexity of the encoder, which determines whether it is applicable on-chip and/or offchip, etc. Stan et al. BIB002 propose a bus invert method to reduce the power consumption by half. This method uses the hamming distance between the present data value on the bus and the next data value. In case of off-chip communication such as external memory access Gray code encoding achieves the minimum switching activity as it takes the advantage of the spatial locality of the addresses generated by the microprocessor BIB008 . However Benini et al. have devised a better address encoding scheme T0 code BIB005 which outperforms the Gray code in the case of streams of consecutive addresses of limited and unlimited lengths. In BIB010 a review of some of the encoding techniques has been undertaken. The encoding function can be optimized for specific access patterns such as sequential access (Gray BIB001 BIB004 , T0 BIB008 , Pyramid BIB009 ) or random data (Bus Invert BIB002 ), for special data types such as floating point numbers in DSP applications  . The encoding may be fully customized to the target data (Working Zone BIB006 , Beach BIB007 ). The key idea behind all of these techniques is to reduce the Hamming distance between consecutive address and data transfers.